1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; f -- Floating point registers.
31 ;; t -- Access registers 36 and 37.
32 ;; G -- Const double zero operand
33 ;; I -- An 8-bit constant (0..255).
34 ;; J -- A 12-bit constant (0..4095).
35 ;; K -- A 16-bit constant (-32768..32767).
36 ;; L -- Value appropriate as displacement.
37 ;; (0..4095) for short displacement
38 ;; (-524288..524287) for long displacement
39 ;; M -- Constant integer with a value of 0x7fffffff.
40 ;; N -- Multiple letter constraint followed by 4 parameter letters.
41 ;; 0..9,x: number of the part counting from most to least significant
42 ;; H,Q: mode of the part
43 ;; D,S,H: mode of the containing operand
44 ;; 0,F: value of the other parts (F - all bits set)
46 ;; The constraint matches if the specified part of a constant
47 ;; has a value different from its other parts. If the letter x
48 ;; is specified instead of a part number, the constraint matches
49 ;; if there is any single part with non-default value.
50 ;; O -- Multiple letter constraint followed by 1 parameter.
51 ;; s: Signed extended immediate value (-2G .. 2G-1).
52 ;; p: Positive extended immediate value (0 .. 4G-1).
53 ;; n: Negative extended immediate value (-4G .. -1).
54 ;; These constraints do not accept any operand if the machine does
55 ;; not provide the extended-immediate facility.
56 ;; P -- Any integer constant that can be loaded without literal pool.
57 ;; Q -- Memory reference without index register and with short displacement.
58 ;; R -- Memory reference with index register and short displacement.
59 ;; S -- Memory reference without index register but with long displacement.
60 ;; T -- Memory reference with index register and long displacement.
61 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
62 ;; Offsettable memory reference of type specified by second letter.
63 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
64 ;; Memory reference of the type specified by second letter that
65 ;; does *not* refer to a literal pool entry.
66 ;; U -- Pointer with short displacement.
67 ;; W -- Pointer with long displacement.
68 ;; Y -- Shift count operand.
70 ;; Special formats used for outputting 390 instructions.
72 ;; %C: print opcode suffix for branch condition.
73 ;; %D: print opcode suffix for inverse branch condition.
74 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
75 ;; %O: print only the displacement of a memory reference.
76 ;; %R: print only the base register of a memory reference.
77 ;; %S: print S-type memory reference (base+displacement).
78 ;; %N: print the second word of a DImode operand.
79 ;; %M: print the second word of a TImode operand.
81 ;; %b: print integer X as if it's an unsigned byte.
82 ;; %x: print integer X as if it's an unsigned word.
83 ;; %h: print integer X as if it's a signed word.
84 ;; %i: print the first nonzero HImode part of X
85 ;; %j: print the first HImode part unequal to 0xffff of X
88 ;; We have a special constraint for pattern matching.
90 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
103 ; GOT/PLT and lt-relative accesses
104 (UNSPEC_LTREL_OFFSET 100)
105 (UNSPEC_LTREL_BASE 101)
113 (UNSPEC_RELOAD_BASE 210)
114 (UNSPEC_MAIN_BASE 211)
119 ; TLS relocation specifiers
124 (UNSPEC_GOTNTPOFF 504)
125 (UNSPEC_INDNTPOFF 505)
128 (UNSPEC_TLSLDM_NTPOFF 511)
129 (UNSPEC_TLS_LOAD 512)
135 ; Stack Smashing Protector
141 ;; UNSPEC_VOLATILE usage
149 (UNSPECV_TPF_PROLOGUE 20)
150 (UNSPECV_TPF_EPILOGUE 21)
154 (UNSPECV_POOL_SECTION 201)
155 (UNSPECV_POOL_ALIGN 202)
156 (UNSPECV_POOL_ENTRY 203)
157 (UNSPECV_MAIN_POOL 300)
173 ; Sibling call register.
175 ; Literal pool base register.
177 ; Return address register.
179 ; Condition code register.
181 ; Thread local storage pointer register.
186 ;; Instruction operand type as used in the Principles of Operation.
187 ;; Used to determine defaults for length and other attribute values.
189 (define_attr "op_type"
190 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
193 ;; Instruction type attribute used for scheduling.
195 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
196 cs,vs,store,sem,idiv,
197 imulhi,imulsi,imuldi,
198 branch,jsr,fsimpdf,fsimpsf,
199 floaddf,floadsf,fstoredf,fstoresf,
200 fmuldf,fmulsf,fdivdf,fdivsf,
201 ftoi,itof,fsqrtdf,fsqrtsf,
203 (cond [(eq_attr "op_type" "NN") (const_string "other")
204 (eq_attr "op_type" "SS") (const_string "cs")]
205 (const_string "integer")))
207 ;; Another attribute used for scheduling purposes:
208 ;; agen: Instruction uses the address generation unit
209 ;; reg: Instruction does not use the agen unit
211 (define_attr "atype" "agen,reg"
212 (cond [(eq_attr "op_type" "E") (const_string "reg")
213 (eq_attr "op_type" "RR") (const_string "reg")
214 (eq_attr "op_type" "RX") (const_string "agen")
215 (eq_attr "op_type" "RI") (const_string "reg")
216 (eq_attr "op_type" "RRE") (const_string "reg")
217 (eq_attr "op_type" "RS") (const_string "agen")
218 (eq_attr "op_type" "RSI") (const_string "agen")
219 (eq_attr "op_type" "S") (const_string "agen")
220 (eq_attr "op_type" "SI") (const_string "agen")
221 (eq_attr "op_type" "SS") (const_string "agen")
222 (eq_attr "op_type" "SSE") (const_string "agen")
223 (eq_attr "op_type" "RXE") (const_string "agen")
224 (eq_attr "op_type" "RSE") (const_string "agen")
225 (eq_attr "op_type" "RIL") (const_string "agen")
226 (eq_attr "op_type" "RXY") (const_string "agen")
227 (eq_attr "op_type" "RSY") (const_string "agen")
228 (eq_attr "op_type" "SIY") (const_string "agen")]
229 (const_string "agen")))
233 (define_attr "length" ""
234 (cond [(eq_attr "op_type" "E") (const_int 2)
235 (eq_attr "op_type" "RR") (const_int 2)
236 (eq_attr "op_type" "RX") (const_int 4)
237 (eq_attr "op_type" "RI") (const_int 4)
238 (eq_attr "op_type" "RRE") (const_int 4)
239 (eq_attr "op_type" "RS") (const_int 4)
240 (eq_attr "op_type" "RSI") (const_int 4)
241 (eq_attr "op_type" "S") (const_int 4)
242 (eq_attr "op_type" "SI") (const_int 4)
243 (eq_attr "op_type" "SS") (const_int 6)
244 (eq_attr "op_type" "SSE") (const_int 6)
245 (eq_attr "op_type" "RXE") (const_int 6)
246 (eq_attr "op_type" "RSE") (const_int 6)
247 (eq_attr "op_type" "RIL") (const_int 6)
248 (eq_attr "op_type" "RXY") (const_int 6)
249 (eq_attr "op_type" "RSY") (const_int 6)
250 (eq_attr "op_type" "SIY") (const_int 6)]
254 ;; Processor type. This attribute must exactly match the processor_type
255 ;; enumeration in s390.h. The current machine description does not
256 ;; distinguish between g5 and g6, but there are differences between the two
257 ;; CPUs could in theory be modeled.
259 (define_attr "cpu" "g5,g6,z900,z990,z9_109"
260 (const (symbol_ref "s390_tune")))
262 ;; Pipeline description for z900. For lack of anything better,
263 ;; this description is also used for the g5 and g6.
266 ;; Pipeline description for z990.
270 (include "predicates.md")
277 ;; This mode macro allows DF and SF patterns to be generated from the
279 (define_mode_macro FPR [DF SF])
281 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
282 ;; from the same template.
283 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
284 (define_mode_macro DSI [DI SI])
286 ;; This mode macro allows :P to be used for patterns that operate on
287 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
288 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
290 ;; This mode macro allows the QI and HI patterns to be defined from
291 ;; the same template.
292 (define_mode_macro HQI [HI QI])
294 ;; This mode macro allows the integer patterns to be defined from the
296 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
298 ;; This macro allows to unify all 'bCOND' expander patterns.
299 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
300 ordered uneq unlt ungt unle unge ltgt])
302 ;; This macro allows to unify all 'sCOND' patterns.
303 (define_code_macro SCOND [ltu gtu leu geu])
305 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
306 ;; the same template.
307 (define_code_macro SHIFT [ashift lshiftrt])
310 ;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
311 ;; and "ltebr" in SFmode.
312 (define_mode_attr de [(DF "d") (SF "e")])
314 ;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
315 ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern.
316 (define_mode_attr dee [(DF "d") (SF "ee")])
318 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
319 ;; 'ashift' and "srdl" in 'lshiftrt'.
320 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
322 ;; In SHIFT templates, this attribute holds the correct standard name for the
323 ;; pattern itself and the corresponding function calls.
324 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
326 ;; This attribute handles differences in the instruction 'type' and will result
327 ;; in "RRE" for DImode and "RR" for SImode.
328 (define_mode_attr E [(DI "E") (SI "")])
330 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
331 ;; and "lcr" in SImode.
332 (define_mode_attr g [(DI "g") (SI "")])
334 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
335 ;; and "cfdbr" in SImode.
336 (define_mode_attr gf [(DI "g") (SI "f")])
338 ;; ICM mask required to load MODE value into the highest subreg
339 ;; of a SImode register.
340 (define_mode_attr icm_hi [(HI "12") (QI "8")])
342 ;; ICM mask required to load MODE value into the lowest subreg
343 ;; of a SImode register.
344 (define_mode_attr icm_lo [(HI "3") (QI "1")])
346 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
347 ;; HImode and "llgc" in QImode.
348 (define_mode_attr hc [(HI "h") (QI "c")])
350 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
352 (define_mode_attr DBL [(DI "TI") (SI "DI")])
354 ;; Maximum unsigned integer that fits in MODE.
355 (define_mode_attr max_uint [(HI "65535") (QI "255")])
359 ;;- Compare instructions.
362 (define_expand "cmp<mode>"
363 [(set (reg:CC CC_REGNUM)
364 (compare:CC (match_operand:GPR 0 "register_operand" "")
365 (match_operand:GPR 1 "general_operand" "")))]
368 s390_compare_op0 = operands[0];
369 s390_compare_op1 = operands[1];
373 (define_expand "cmp<mode>"
374 [(set (reg:CC CC_REGNUM)
375 (compare:CC (match_operand:FPR 0 "register_operand" "")
376 (match_operand:FPR 1 "general_operand" "")))]
379 s390_compare_op0 = operands[0];
380 s390_compare_op1 = operands[1];
385 ; Test-under-Mask instructions
387 (define_insn "*tmqi_mem"
388 [(set (reg CC_REGNUM)
389 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
390 (match_operand:QI 1 "immediate_operand" "n,n"))
391 (match_operand:QI 2 "immediate_operand" "n,n")))]
392 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
396 [(set_attr "op_type" "SI,SIY")])
398 (define_insn "*tmdi_reg"
399 [(set (reg CC_REGNUM)
400 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
401 (match_operand:DI 1 "immediate_operand"
402 "N0HD0,N1HD0,N2HD0,N3HD0"))
403 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
405 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
406 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
412 [(set_attr "op_type" "RI")])
414 (define_insn "*tmsi_reg"
415 [(set (reg CC_REGNUM)
416 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
417 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
418 (match_operand:SI 2 "immediate_operand" "n,n")))]
419 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
420 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
424 [(set_attr "op_type" "RI")])
426 (define_insn "*tm<mode>_full"
427 [(set (reg CC_REGNUM)
428 (compare (match_operand:HQI 0 "register_operand" "d")
429 (match_operand:HQI 1 "immediate_operand" "n")))]
430 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
432 [(set_attr "op_type" "RI")])
435 ; Load-and-Test instructions
437 (define_insn "*tstdi_sign"
438 [(set (reg CC_REGNUM)
439 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
440 (const_int 32)) (const_int 32))
441 (match_operand:DI 1 "const0_operand" "")))
442 (set (match_operand:DI 2 "register_operand" "=d")
443 (sign_extend:DI (match_dup 0)))]
444 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
446 [(set_attr "op_type" "RRE")])
448 (define_insn "*tstdi_extimm"
449 [(set (reg CC_REGNUM)
450 (compare (match_operand:DI 0 "nonimmediate_operand" "d,m")
451 (match_operand:DI 1 "const0_operand" "")))
452 (set (match_operand:DI 2 "register_operand" "=d,d")
454 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM"
458 [(set_attr "op_type" "RRE,RXY")])
460 (define_insn "*tstdi_cconly_extimm"
461 [(set (reg CC_REGNUM)
462 (compare (match_operand:DI 0 "nonimmediate_operand" "d,m")
463 (match_operand:DI 1 "const0_operand" "")))
464 (clobber (match_scratch:DI 2 "=X,d"))]
465 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM"
469 [(set_attr "op_type" "RRE,RXY")])
471 (define_insn "*tstdi"
472 [(set (reg CC_REGNUM)
473 (compare (match_operand:DI 0 "register_operand" "d")
474 (match_operand:DI 1 "const0_operand" "")))
475 (set (match_operand:DI 2 "register_operand" "=d")
477 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
479 [(set_attr "op_type" "RRE")])
481 (define_insn "*tstdi_cconly"
482 [(set (reg CC_REGNUM)
483 (compare (match_operand:DI 0 "register_operand" "d")
484 (match_operand:DI 1 "const0_operand" "")))]
485 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
487 [(set_attr "op_type" "RRE")])
489 (define_insn "*tstdi_cconly_31"
490 [(set (reg CC_REGNUM)
491 (compare (match_operand:DI 0 "register_operand" "d")
492 (match_operand:DI 1 "const0_operand" "")))]
493 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
495 [(set_attr "op_type" "RS")
496 (set_attr "atype" "reg")])
498 (define_insn "*tstsi_extimm"
499 [(set (reg CC_REGNUM)
500 (compare (match_operand:SI 0 "nonimmediate_operand" "d,m")
501 (match_operand:SI 1 "const0_operand" "")))
502 (set (match_operand:SI 2 "register_operand" "=d,d")
504 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
508 [(set_attr "op_type" "RR,RXY")])
510 (define_insn "*tstsi_cconly_extimm"
511 [(set (reg CC_REGNUM)
512 (compare (match_operand:SI 0 "nonimmediate_operand" "d,m")
513 (match_operand:SI 1 "const0_operand" "")))
514 (clobber (match_scratch:SI 2 "=X,d"))]
515 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
519 [(set_attr "op_type" "RR,RXY")])
521 (define_insn "*tstsi"
522 [(set (reg CC_REGNUM)
523 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
524 (match_operand:SI 1 "const0_operand" "")))
525 (set (match_operand:SI 2 "register_operand" "=d,d,d")
527 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
532 [(set_attr "op_type" "RR,RS,RSY")])
534 (define_insn "*tstsi_cconly"
535 [(set (reg CC_REGNUM)
536 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
537 (match_operand:SI 1 "const0_operand" "")))
538 (clobber (match_scratch:SI 2 "=X,d,d"))]
539 "s390_match_ccmode(insn, CCSmode)"
544 [(set_attr "op_type" "RR,RS,RSY")])
546 (define_insn "*tstsi_cconly2"
547 [(set (reg CC_REGNUM)
548 (compare (match_operand:SI 0 "register_operand" "d")
549 (match_operand:SI 1 "const0_operand" "")))]
550 "s390_match_ccmode(insn, CCSmode)"
552 [(set_attr "op_type" "RR")])
554 (define_insn "*tst<mode>CCT"
555 [(set (reg CC_REGNUM)
556 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
557 (match_operand:HQI 1 "const0_operand" "")))
558 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
560 "s390_match_ccmode(insn, CCTmode)"
563 icmy\t%2,<icm_lo>,%S0
565 [(set_attr "op_type" "RS,RSY,RI")])
567 (define_insn "*tsthiCCT_cconly"
568 [(set (reg CC_REGNUM)
569 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
570 (match_operand:HI 1 "const0_operand" "")))
571 (clobber (match_scratch:HI 2 "=d,d,X"))]
572 "s390_match_ccmode(insn, CCTmode)"
577 [(set_attr "op_type" "RS,RSY,RI")])
579 (define_insn "*tstqiCCT_cconly"
580 [(set (reg CC_REGNUM)
581 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
582 (match_operand:QI 1 "const0_operand" "")))]
583 "s390_match_ccmode(insn, CCTmode)"
588 [(set_attr "op_type" "SI,SIY,RI")])
590 (define_insn "*tst<mode>"
591 [(set (reg CC_REGNUM)
592 (compare (match_operand:HQI 0 "s_operand" "Q,S")
593 (match_operand:HQI 1 "const0_operand" "")))
594 (set (match_operand:HQI 2 "register_operand" "=d,d")
596 "s390_match_ccmode(insn, CCSmode)"
599 icmy\t%2,<icm_lo>,%S0"
600 [(set_attr "op_type" "RS,RSY")])
602 (define_insn "*tst<mode>_cconly"
603 [(set (reg CC_REGNUM)
604 (compare (match_operand:HQI 0 "s_operand" "Q,S")
605 (match_operand:HQI 1 "const0_operand" "")))
606 (clobber (match_scratch:HQI 2 "=d,d"))]
607 "s390_match_ccmode(insn, CCSmode)"
610 icmy\t%2,<icm_lo>,%S0"
611 [(set_attr "op_type" "RS,RSY")])
614 ; Compare (equality) instructions
616 (define_insn "*cmpdi_cct"
617 [(set (reg CC_REGNUM)
618 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
619 (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))]
620 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
627 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")])
629 (define_insn "*cmpsi_cct"
630 [(set (reg CC_REGNUM)
631 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
632 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
633 "s390_match_ccmode (insn, CCTmode)"
641 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")])
644 ; Compare (signed) instructions
646 (define_insn "*cmpdi_ccs_sign"
647 [(set (reg CC_REGNUM)
648 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
649 (match_operand:DI 0 "register_operand" "d,d")))]
650 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
654 [(set_attr "op_type" "RRE,RXY")])
656 (define_insn "*cmpdi_ccs"
657 [(set (reg CC_REGNUM)
658 (compare (match_operand:DI 0 "register_operand" "d,d,d,d")
659 (match_operand:DI 1 "general_operand" "d,K,Os,m")))]
660 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
666 [(set_attr "op_type" "RRE,RI,RIL,RXY")])
668 (define_insn "*cmpsi_ccs_sign"
669 [(set (reg CC_REGNUM)
670 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
671 (match_operand:SI 0 "register_operand" "d,d")))]
672 "s390_match_ccmode(insn, CCSRmode)"
676 [(set_attr "op_type" "RX,RXY")])
678 (define_insn "*cmpsi_ccs"
679 [(set (reg CC_REGNUM)
680 (compare (match_operand:SI 0 "register_operand" "d,d,d,d,d")
681 (match_operand:SI 1 "general_operand" "d,K,Os,R,T")))]
682 "s390_match_ccmode(insn, CCSmode)"
689 [(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
692 ; Compare (unsigned) instructions
694 (define_insn "*cmpdi_ccu_zero"
695 [(set (reg CC_REGNUM)
696 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
697 (match_operand:DI 0 "register_operand" "d,d")))]
698 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
702 [(set_attr "op_type" "RRE,RXY")])
704 (define_insn "*cmpdi_ccu"
705 [(set (reg CC_REGNUM)
706 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
707 (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))]
708 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
715 [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")])
717 (define_insn "*cmpsi_ccu"
718 [(set (reg CC_REGNUM)
719 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ")
720 (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))]
721 "s390_match_ccmode (insn, CCUmode)"
729 [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")])
731 (define_insn "*cmphi_ccu"
732 [(set (reg CC_REGNUM)
733 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
734 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
735 "s390_match_ccmode (insn, CCUmode)
736 && !register_operand (operands[1], HImode)"
742 [(set_attr "op_type" "RS,RSY,SS,SS")])
744 (define_insn "*cmpqi_ccu"
745 [(set (reg CC_REGNUM)
746 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
747 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
748 "s390_match_ccmode (insn, CCUmode)
749 && !register_operand (operands[1], QImode)"
757 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
760 ; Block compare (CLC) instruction patterns.
763 [(set (reg CC_REGNUM)
764 (compare (match_operand:BLK 0 "memory_operand" "Q")
765 (match_operand:BLK 1 "memory_operand" "Q")))
766 (use (match_operand 2 "const_int_operand" "n"))]
767 "s390_match_ccmode (insn, CCUmode)
768 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
769 "clc\t%O0(%2,%R0),%S1"
770 [(set_attr "op_type" "SS")])
773 [(set (reg CC_REGNUM)
774 (compare (match_operand 0 "memory_operand" "")
775 (match_operand 1 "memory_operand" "")))]
777 && s390_match_ccmode (insn, CCUmode)
778 && GET_MODE (operands[0]) == GET_MODE (operands[1])
779 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
781 [(set (match_dup 0) (match_dup 1))
782 (use (match_dup 2))])]
784 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
785 operands[0] = adjust_address (operands[0], BLKmode, 0);
786 operands[1] = adjust_address (operands[1], BLKmode, 0);
788 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
789 operands[0], operands[1]);
790 operands[0] = SET_DEST (PATTERN (curr_insn));
794 ; (DF|SF) instructions
796 (define_insn "*cmp<mode>_ccs_0"
797 [(set (reg CC_REGNUM)
798 (compare (match_operand:FPR 0 "register_operand" "f")
799 (match_operand:FPR 1 "const0_operand" "")))]
800 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
802 [(set_attr "op_type" "RRE")
803 (set_attr "type" "fsimp<mode>")])
805 (define_insn "*cmp<mode>_ccs_0_ibm"
806 [(set (reg CC_REGNUM)
807 (compare (match_operand:FPR 0 "register_operand" "f")
808 (match_operand:FPR 1 "const0_operand" "")))]
809 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
811 [(set_attr "op_type" "RR")
812 (set_attr "type" "fsimp<mode>")])
814 (define_insn "*cmp<mode>_ccs"
815 [(set (reg CC_REGNUM)
816 (compare (match_operand:FPR 0 "register_operand" "f,f")
817 (match_operand:FPR 1 "general_operand" "f,R")))]
818 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
822 [(set_attr "op_type" "RRE,RXE")
823 (set_attr "type" "fsimp<mode>")])
825 (define_insn "*cmp<mode>_ccs_ibm"
826 [(set (reg CC_REGNUM)
827 (compare (match_operand:FPR 0 "register_operand" "f,f")
828 (match_operand:FPR 1 "general_operand" "f,R")))]
829 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
833 [(set_attr "op_type" "RR,RX")
834 (set_attr "type" "fsimp<mode>")])
838 ;;- Move instructions.
842 ; movti instruction pattern(s).
846 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
847 (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))]
855 [(set_attr "op_type" "RSY,RSY,*,*,SS")
856 (set_attr "type" "lm,stm,*,*,*")])
859 [(set (match_operand:TI 0 "nonimmediate_operand" "")
860 (match_operand:TI 1 "general_operand" ""))]
861 "TARGET_64BIT && reload_completed
862 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
863 [(set (match_dup 2) (match_dup 4))
864 (set (match_dup 3) (match_dup 5))]
866 operands[2] = operand_subword (operands[0], 0, 0, TImode);
867 operands[3] = operand_subword (operands[0], 1, 0, TImode);
868 operands[4] = operand_subword (operands[1], 0, 0, TImode);
869 operands[5] = operand_subword (operands[1], 1, 0, TImode);
873 [(set (match_operand:TI 0 "nonimmediate_operand" "")
874 (match_operand:TI 1 "general_operand" ""))]
875 "TARGET_64BIT && reload_completed
876 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
877 [(set (match_dup 2) (match_dup 4))
878 (set (match_dup 3) (match_dup 5))]
880 operands[2] = operand_subword (operands[0], 1, 0, TImode);
881 operands[3] = operand_subword (operands[0], 0, 0, TImode);
882 operands[4] = operand_subword (operands[1], 1, 0, TImode);
883 operands[5] = operand_subword (operands[1], 0, 0, TImode);
887 [(set (match_operand:TI 0 "register_operand" "")
888 (match_operand:TI 1 "memory_operand" ""))]
889 "TARGET_64BIT && reload_completed
890 && !s_operand (operands[1], VOIDmode)"
891 [(set (match_dup 0) (match_dup 1))]
893 rtx addr = operand_subword (operands[0], 1, 0, TImode);
894 s390_load_address (addr, XEXP (operands[1], 0));
895 operands[1] = replace_equiv_address (operands[1], addr);
898 (define_expand "reload_outti"
899 [(parallel [(match_operand:TI 0 "" "")
900 (match_operand:TI 1 "register_operand" "d")
901 (match_operand:DI 2 "register_operand" "=&a")])]
904 gcc_assert (MEM_P (operands[0]));
905 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
906 operands[0] = replace_equiv_address (operands[0], operands[2]);
907 emit_move_insn (operands[0], operands[1]);
912 ; movdi instruction pattern(s).
915 (define_expand "movdi"
916 [(set (match_operand:DI 0 "general_operand" "")
917 (match_operand:DI 1 "general_operand" ""))]
920 /* Handle symbolic constants. */
921 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
922 emit_symbolic_move (operands);
925 (define_insn "*movdi_larl"
926 [(set (match_operand:DI 0 "register_operand" "=d")
927 (match_operand:DI 1 "larl_operand" "X"))]
929 && !FP_REG_P (operands[0])"
931 [(set_attr "op_type" "RIL")
932 (set_attr "type" "larl")])
934 (define_insn "*movdi_64extimm"
935 [(set (match_operand:DI 0 "nonimmediate_operand"
936 "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
937 (match_operand:DI 1 "general_operand"
938 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
939 "TARGET_64BIT && TARGET_EXTIMM"
963 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY,
964 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
965 (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store,
966 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
968 (define_insn "*movdi_64"
969 [(set (match_operand:DI 0 "nonimmediate_operand"
970 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
971 (match_operand:DI 1 "general_operand"
972 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
973 "TARGET_64BIT && !TARGET_EXTIMM"
994 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
995 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
996 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
997 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
1000 [(set (match_operand:DI 0 "register_operand" "")
1001 (match_operand:DI 1 "register_operand" ""))]
1002 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
1003 [(set (match_dup 2) (match_dup 3))
1004 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1005 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1006 "operands[2] = gen_lowpart (SImode, operands[0]);
1007 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1010 [(set (match_operand:DI 0 "register_operand" "")
1011 (match_operand:DI 1 "register_operand" ""))]
1012 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1013 && dead_or_set_p (insn, operands[1])"
1014 [(set (match_dup 3) (match_dup 2))
1015 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1016 (set (match_dup 4) (match_dup 2))]
1017 "operands[2] = gen_lowpart (SImode, operands[1]);
1018 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1021 [(set (match_operand:DI 0 "register_operand" "")
1022 (match_operand:DI 1 "register_operand" ""))]
1023 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1024 && !dead_or_set_p (insn, operands[1])"
1025 [(set (match_dup 3) (match_dup 2))
1026 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1027 (set (match_dup 4) (match_dup 2))
1028 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1029 "operands[2] = gen_lowpart (SImode, operands[1]);
1030 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1032 (define_insn "*movdi_31"
1033 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
1034 (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))]
1049 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
1050 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
1053 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1054 (match_operand:DI 1 "general_operand" ""))]
1055 "!TARGET_64BIT && reload_completed
1056 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1057 [(set (match_dup 2) (match_dup 4))
1058 (set (match_dup 3) (match_dup 5))]
1060 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1061 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1062 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1063 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1067 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1068 (match_operand:DI 1 "general_operand" ""))]
1069 "!TARGET_64BIT && reload_completed
1070 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1071 [(set (match_dup 2) (match_dup 4))
1072 (set (match_dup 3) (match_dup 5))]
1074 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1075 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1076 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1077 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1081 [(set (match_operand:DI 0 "register_operand" "")
1082 (match_operand:DI 1 "memory_operand" ""))]
1083 "!TARGET_64BIT && reload_completed
1084 && !FP_REG_P (operands[0])
1085 && !s_operand (operands[1], VOIDmode)"
1086 [(set (match_dup 0) (match_dup 1))]
1088 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1089 s390_load_address (addr, XEXP (operands[1], 0));
1090 operands[1] = replace_equiv_address (operands[1], addr);
1093 (define_expand "reload_outdi"
1094 [(parallel [(match_operand:DI 0 "" "")
1095 (match_operand:DI 1 "register_operand" "d")
1096 (match_operand:SI 2 "register_operand" "=&a")])]
1099 gcc_assert (MEM_P (operands[0]));
1100 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1101 operands[0] = replace_equiv_address (operands[0], operands[2]);
1102 emit_move_insn (operands[0], operands[1]);
1107 [(set (match_operand:DI 0 "register_operand" "")
1108 (mem:DI (match_operand 1 "address_operand" "")))]
1110 && !FP_REG_P (operands[0])
1111 && GET_CODE (operands[1]) == SYMBOL_REF
1112 && CONSTANT_POOL_ADDRESS_P (operands[1])
1113 && get_pool_mode (operands[1]) == DImode
1114 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1115 [(set (match_dup 0) (match_dup 2))]
1116 "operands[2] = get_pool_constant (operands[1]);")
1118 (define_insn "*la_64"
1119 [(set (match_operand:DI 0 "register_operand" "=d,d")
1120 (match_operand:QI 1 "address_operand" "U,W"))]
1125 [(set_attr "op_type" "RX,RXY")
1126 (set_attr "type" "la")])
1130 [(set (match_operand:DI 0 "register_operand" "")
1131 (match_operand:QI 1 "address_operand" ""))
1132 (clobber (reg:CC CC_REGNUM))])]
1134 && preferred_la_operand_p (operands[1], const0_rtx)"
1135 [(set (match_dup 0) (match_dup 1))]
1139 [(set (match_operand:DI 0 "register_operand" "")
1140 (match_operand:DI 1 "register_operand" ""))
1143 (plus:DI (match_dup 0)
1144 (match_operand:DI 2 "nonmemory_operand" "")))
1145 (clobber (reg:CC CC_REGNUM))])]
1147 && !reg_overlap_mentioned_p (operands[0], operands[2])
1148 && preferred_la_operand_p (operands[1], operands[2])"
1149 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1152 (define_expand "reload_indi"
1153 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1154 (match_operand:DI 1 "s390_plus_operand" "")
1155 (match_operand:DI 2 "register_operand" "=&a")])]
1158 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1163 ; movsi instruction pattern(s).
1166 (define_expand "movsi"
1167 [(set (match_operand:SI 0 "general_operand" "")
1168 (match_operand:SI 1 "general_operand" ""))]
1171 /* Handle symbolic constants. */
1172 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1173 emit_symbolic_move (operands);
1176 (define_insn "*movsi_larl"
1177 [(set (match_operand:SI 0 "register_operand" "=d")
1178 (match_operand:SI 1 "larl_operand" "X"))]
1179 "!TARGET_64BIT && TARGET_CPU_ZARCH
1180 && !FP_REG_P (operands[0])"
1182 [(set_attr "op_type" "RIL")
1183 (set_attr "type" "larl")])
1185 (define_insn "*movsi_zarch"
1186 [(set (match_operand:SI 0 "nonimmediate_operand"
1187 "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1188 (match_operand:SI 1 "general_operand"
1189 "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1212 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY,
1213 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1214 (set_attr "type" "*,*,*,*,la,lr,load,load,store,store,
1215 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1217 (define_insn "*movsi_esa"
1218 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1219 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1234 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1235 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1238 [(set (match_operand:SI 0 "register_operand" "")
1239 (mem:SI (match_operand 1 "address_operand" "")))]
1240 "!FP_REG_P (operands[0])
1241 && GET_CODE (operands[1]) == SYMBOL_REF
1242 && CONSTANT_POOL_ADDRESS_P (operands[1])
1243 && get_pool_mode (operands[1]) == SImode
1244 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1245 [(set (match_dup 0) (match_dup 2))]
1246 "operands[2] = get_pool_constant (operands[1]);")
1248 (define_insn "*la_31"
1249 [(set (match_operand:SI 0 "register_operand" "=d,d")
1250 (match_operand:QI 1 "address_operand" "U,W"))]
1251 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1255 [(set_attr "op_type" "RX,RXY")
1256 (set_attr "type" "la")])
1260 [(set (match_operand:SI 0 "register_operand" "")
1261 (match_operand:QI 1 "address_operand" ""))
1262 (clobber (reg:CC CC_REGNUM))])]
1264 && preferred_la_operand_p (operands[1], const0_rtx)"
1265 [(set (match_dup 0) (match_dup 1))]
1269 [(set (match_operand:SI 0 "register_operand" "")
1270 (match_operand:SI 1 "register_operand" ""))
1273 (plus:SI (match_dup 0)
1274 (match_operand:SI 2 "nonmemory_operand" "")))
1275 (clobber (reg:CC CC_REGNUM))])]
1277 && !reg_overlap_mentioned_p (operands[0], operands[2])
1278 && preferred_la_operand_p (operands[1], operands[2])"
1279 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1282 (define_insn "*la_31_and"
1283 [(set (match_operand:SI 0 "register_operand" "=d,d")
1284 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1285 (const_int 2147483647)))]
1290 [(set_attr "op_type" "RX,RXY")
1291 (set_attr "type" "la")])
1293 (define_insn_and_split "*la_31_and_cc"
1294 [(set (match_operand:SI 0 "register_operand" "=d")
1295 (and:SI (match_operand:QI 1 "address_operand" "p")
1296 (const_int 2147483647)))
1297 (clobber (reg:CC CC_REGNUM))]
1300 "&& reload_completed"
1302 (and:SI (match_dup 1) (const_int 2147483647)))]
1304 [(set_attr "op_type" "RX")
1305 (set_attr "type" "la")])
1307 (define_insn "force_la_31"
1308 [(set (match_operand:SI 0 "register_operand" "=d,d")
1309 (match_operand:QI 1 "address_operand" "U,W"))
1310 (use (const_int 0))]
1315 [(set_attr "op_type" "RX")
1316 (set_attr "type" "la")])
1318 (define_expand "reload_insi"
1319 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1320 (match_operand:SI 1 "s390_plus_operand" "")
1321 (match_operand:SI 2 "register_operand" "=&a")])]
1324 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1329 ; movhi instruction pattern(s).
1332 (define_expand "movhi"
1333 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1334 (match_operand:HI 1 "general_operand" ""))]
1337 /* Make it explicit that loading a register from memory
1338 always sign-extends (at least) to SImode. */
1339 if (optimize && !no_new_pseudos
1340 && register_operand (operands[0], VOIDmode)
1341 && GET_CODE (operands[1]) == MEM)
1343 rtx tmp = gen_reg_rtx (SImode);
1344 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1345 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1346 operands[1] = gen_lowpart (HImode, tmp);
1350 (define_insn "*movhi"
1351 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1352 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1362 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1363 (set_attr "type" "lr,*,*,*,store,store,*")])
1366 [(set (match_operand:HI 0 "register_operand" "")
1367 (mem:HI (match_operand 1 "address_operand" "")))]
1368 "GET_CODE (operands[1]) == SYMBOL_REF
1369 && CONSTANT_POOL_ADDRESS_P (operands[1])
1370 && get_pool_mode (operands[1]) == HImode
1371 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1372 [(set (match_dup 0) (match_dup 2))]
1373 "operands[2] = get_pool_constant (operands[1]);")
1376 ; movqi instruction pattern(s).
1379 (define_expand "movqi"
1380 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1381 (match_operand:QI 1 "general_operand" ""))]
1384 /* On z/Architecture, zero-extending from memory to register
1385 is just as fast as a QImode load. */
1386 if (TARGET_ZARCH && optimize && !no_new_pseudos
1387 && register_operand (operands[0], VOIDmode)
1388 && GET_CODE (operands[1]) == MEM)
1390 rtx tmp = gen_reg_rtx (word_mode);
1391 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1392 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1393 operands[1] = gen_lowpart (QImode, tmp);
1397 (define_insn "*movqi"
1398 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1399 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1411 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1412 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1415 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1416 (mem:QI (match_operand 1 "address_operand" "")))]
1417 "GET_CODE (operands[1]) == SYMBOL_REF
1418 && CONSTANT_POOL_ADDRESS_P (operands[1])
1419 && get_pool_mode (operands[1]) == QImode
1420 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1421 [(set (match_dup 0) (match_dup 2))]
1422 "operands[2] = get_pool_constant (operands[1]);")
1425 ; movstrictqi instruction pattern(s).
1428 (define_insn "*movstrictqi"
1429 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1430 (match_operand:QI 1 "memory_operand" "R,T"))]
1435 [(set_attr "op_type" "RX,RXY")])
1438 ; movstricthi instruction pattern(s).
1441 (define_insn "*movstricthi"
1442 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1443 (match_operand:HI 1 "memory_operand" "Q,S"))
1444 (clobber (reg:CC CC_REGNUM))]
1449 [(set_attr "op_type" "RS,RSY")])
1452 ; movstrictsi instruction pattern(s).
1455 (define_insn "movstrictsi"
1456 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1457 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1464 [(set_attr "op_type" "RR,RX,RXY,RRE")
1465 (set_attr "type" "lr,load,load,*")])
1468 ; movdf instruction pattern(s).
1471 (define_expand "movdf"
1472 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1473 (match_operand:DF 1 "general_operand" ""))]
1477 (define_insn "*movdf_64"
1478 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
1479 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
1492 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1493 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1495 (define_insn "*movdf_31"
1496 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q")
1497 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))]
1513 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
1514 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\
1515 lm,lm,stm,stm,*,*,*")])
1518 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1519 (match_operand:DF 1 "general_operand" ""))]
1520 "!TARGET_64BIT && reload_completed
1521 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1522 [(set (match_dup 2) (match_dup 4))
1523 (set (match_dup 3) (match_dup 5))]
1525 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1526 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1527 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1528 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1532 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1533 (match_operand:DF 1 "general_operand" ""))]
1534 "!TARGET_64BIT && reload_completed
1535 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1536 [(set (match_dup 2) (match_dup 4))
1537 (set (match_dup 3) (match_dup 5))]
1539 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1540 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1541 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1542 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1546 [(set (match_operand:DF 0 "register_operand" "")
1547 (match_operand:DF 1 "memory_operand" ""))]
1548 "!TARGET_64BIT && reload_completed
1549 && !FP_REG_P (operands[0])
1550 && !s_operand (operands[1], VOIDmode)"
1551 [(set (match_dup 0) (match_dup 1))]
1553 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1554 s390_load_address (addr, XEXP (operands[1], 0));
1555 operands[1] = replace_equiv_address (operands[1], addr);
1558 (define_expand "reload_outdf"
1559 [(parallel [(match_operand:DF 0 "" "")
1560 (match_operand:DF 1 "register_operand" "d")
1561 (match_operand:SI 2 "register_operand" "=&a")])]
1564 gcc_assert (MEM_P (operands[0]));
1565 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1566 operands[0] = replace_equiv_address (operands[0], operands[2]);
1567 emit_move_insn (operands[0], operands[1]);
1572 ; movsf instruction pattern(s).
1575 (define_insn "movsf"
1576 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
1577 (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
1592 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1593 (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
1594 lr,load,load,store,store,*")])
1597 ; movcc instruction pattern
1600 (define_insn "movcc"
1601 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1602 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1612 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1613 (set_attr "type" "lr,*,*,store,store,load,load")])
1616 ; Block move (MVC) patterns.
1620 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1621 (match_operand:BLK 1 "memory_operand" "Q"))
1622 (use (match_operand 2 "const_int_operand" "n"))]
1623 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1624 "mvc\t%O0(%2,%R0),%S1"
1625 [(set_attr "op_type" "SS")])
1628 [(set (match_operand 0 "memory_operand" "")
1629 (match_operand 1 "memory_operand" ""))]
1631 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1632 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1634 [(set (match_dup 0) (match_dup 1))
1635 (use (match_dup 2))])]
1637 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1638 operands[0] = adjust_address (operands[0], BLKmode, 0);
1639 operands[1] = adjust_address (operands[1], BLKmode, 0);
1644 [(set (match_operand:BLK 0 "memory_operand" "")
1645 (match_operand:BLK 1 "memory_operand" ""))
1646 (use (match_operand 2 "const_int_operand" ""))])
1648 [(set (match_operand:BLK 3 "memory_operand" "")
1649 (match_operand:BLK 4 "memory_operand" ""))
1650 (use (match_operand 5 "const_int_operand" ""))])]
1651 "s390_offset_p (operands[0], operands[3], operands[2])
1652 && s390_offset_p (operands[1], operands[4], operands[2])
1653 && !s390_overlap_p (operands[0], operands[1],
1654 INTVAL (operands[2]) + INTVAL (operands[5]))
1655 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1657 [(set (match_dup 6) (match_dup 7))
1658 (use (match_dup 8))])]
1659 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1660 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1661 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1665 ; load_multiple pattern(s).
1667 ; ??? Due to reload problems with replacing registers inside match_parallel
1668 ; we currently support load_multiple/store_multiple only after reload.
1671 (define_expand "load_multiple"
1672 [(match_par_dup 3 [(set (match_operand 0 "" "")
1673 (match_operand 1 "" ""))
1674 (use (match_operand 2 "" ""))])]
1677 enum machine_mode mode;
1683 /* Support only loading a constant number of fixed-point registers from
1684 memory and only bother with this if more than two */
1685 if (GET_CODE (operands[2]) != CONST_INT
1686 || INTVAL (operands[2]) < 2
1687 || INTVAL (operands[2]) > 16
1688 || GET_CODE (operands[1]) != MEM
1689 || GET_CODE (operands[0]) != REG
1690 || REGNO (operands[0]) >= 16)
1693 count = INTVAL (operands[2]);
1694 regno = REGNO (operands[0]);
1695 mode = GET_MODE (operands[0]);
1696 if (mode != SImode && mode != word_mode)
1699 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1702 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1704 from = XEXP (operands[1], 0);
1707 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1708 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1709 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1711 from = XEXP (XEXP (operands[1], 0), 0);
1712 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1719 from = force_reg (Pmode, XEXP (operands[1], 0));
1723 for (i = 0; i < count; i++)
1724 XVECEXP (operands[3], 0, i)
1725 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1726 change_address (operands[1], mode,
1727 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1730 (define_insn "*load_multiple_di"
1731 [(match_parallel 0 "load_multiple_operation"
1732 [(set (match_operand:DI 1 "register_operand" "=r")
1733 (match_operand:DI 2 "s_operand" "QS"))])]
1734 "reload_completed && word_mode == DImode"
1736 int words = XVECLEN (operands[0], 0);
1737 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1738 return "lmg\t%1,%0,%S2";
1740 [(set_attr "op_type" "RSY")
1741 (set_attr "type" "lm")])
1743 (define_insn "*load_multiple_si"
1744 [(match_parallel 0 "load_multiple_operation"
1745 [(set (match_operand:SI 1 "register_operand" "=r,r")
1746 (match_operand:SI 2 "s_operand" "Q,S"))])]
1749 int words = XVECLEN (operands[0], 0);
1750 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1751 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1753 [(set_attr "op_type" "RS,RSY")
1754 (set_attr "type" "lm")])
1757 ; store multiple pattern(s).
1760 (define_expand "store_multiple"
1761 [(match_par_dup 3 [(set (match_operand 0 "" "")
1762 (match_operand 1 "" ""))
1763 (use (match_operand 2 "" ""))])]
1766 enum machine_mode mode;
1772 /* Support only storing a constant number of fixed-point registers to
1773 memory and only bother with this if more than two. */
1774 if (GET_CODE (operands[2]) != CONST_INT
1775 || INTVAL (operands[2]) < 2
1776 || INTVAL (operands[2]) > 16
1777 || GET_CODE (operands[0]) != MEM
1778 || GET_CODE (operands[1]) != REG
1779 || REGNO (operands[1]) >= 16)
1782 count = INTVAL (operands[2]);
1783 regno = REGNO (operands[1]);
1784 mode = GET_MODE (operands[1]);
1785 if (mode != SImode && mode != word_mode)
1788 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1792 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1794 to = XEXP (operands[0], 0);
1797 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1798 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1799 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1801 to = XEXP (XEXP (operands[0], 0), 0);
1802 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1809 to = force_reg (Pmode, XEXP (operands[0], 0));
1813 for (i = 0; i < count; i++)
1814 XVECEXP (operands[3], 0, i)
1815 = gen_rtx_SET (VOIDmode,
1816 change_address (operands[0], mode,
1817 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1818 gen_rtx_REG (mode, regno + i));
1821 (define_insn "*store_multiple_di"
1822 [(match_parallel 0 "store_multiple_operation"
1823 [(set (match_operand:DI 1 "s_operand" "=QS")
1824 (match_operand:DI 2 "register_operand" "r"))])]
1825 "reload_completed && word_mode == DImode"
1827 int words = XVECLEN (operands[0], 0);
1828 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1829 return "stmg\t%2,%0,%S1";
1831 [(set_attr "op_type" "RSY")
1832 (set_attr "type" "stm")])
1835 (define_insn "*store_multiple_si"
1836 [(match_parallel 0 "store_multiple_operation"
1837 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1838 (match_operand:SI 2 "register_operand" "r,r"))])]
1841 int words = XVECLEN (operands[0], 0);
1842 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1843 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1845 [(set_attr "op_type" "RS,RSY")
1846 (set_attr "type" "stm")])
1849 ;; String instructions.
1852 (define_insn "*execute"
1853 [(match_parallel 0 ""
1854 [(unspec [(match_operand 1 "register_operand" "a")
1855 (match_operand:BLK 2 "memory_operand" "R")
1856 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1857 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1858 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1860 [(set_attr "op_type" "RX")
1861 (set_attr "type" "cs")])
1865 ; strlenM instruction pattern(s).
1868 (define_expand "strlen<mode>"
1869 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
1872 (unspec:P [(const_int 0)
1873 (match_operand:BLK 1 "memory_operand" "")
1875 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1876 (clobber (scratch:P))
1877 (clobber (reg:CC CC_REGNUM))])
1879 [(set (match_operand:P 0 "register_operand" "")
1880 (minus:P (match_dup 4) (match_dup 5)))
1881 (clobber (reg:CC CC_REGNUM))])]
1884 operands[4] = gen_reg_rtx (Pmode);
1885 operands[5] = gen_reg_rtx (Pmode);
1886 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1887 operands[1] = replace_equiv_address (operands[1], operands[5]);
1890 (define_insn "*strlen<mode>"
1891 [(set (match_operand:P 0 "register_operand" "=a")
1892 (unspec:P [(match_operand:P 2 "general_operand" "0")
1893 (mem:BLK (match_operand:P 3 "register_operand" "1"))
1895 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1896 (clobber (match_scratch:P 1 "=a"))
1897 (clobber (reg:CC CC_REGNUM))]
1899 "srst\t%0,%1\;jo\t.-4"
1900 [(set_attr "length" "8")
1901 (set_attr "type" "vs")])
1904 ; cmpstrM instruction pattern(s).
1907 (define_expand "cmpstrsi"
1908 [(set (reg:SI 0) (const_int 0))
1910 [(clobber (match_operand 3 "" ""))
1911 (clobber (match_dup 4))
1912 (set (reg:CCU CC_REGNUM)
1913 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
1914 (match_operand:BLK 2 "memory_operand" "")))
1917 [(set (match_operand:SI 0 "register_operand" "=d")
1918 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT))
1919 (clobber (reg:CC CC_REGNUM))])]
1922 /* As the result of CMPINT is inverted compared to what we need,
1923 we have to swap the operands. */
1924 rtx op1 = operands[2];
1925 rtx op2 = operands[1];
1926 rtx addr1 = gen_reg_rtx (Pmode);
1927 rtx addr2 = gen_reg_rtx (Pmode);
1929 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
1930 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
1931 operands[1] = replace_equiv_address_nv (op1, addr1);
1932 operands[2] = replace_equiv_address_nv (op2, addr2);
1933 operands[3] = addr1;
1934 operands[4] = addr2;
1937 (define_insn "*cmpstr<mode>"
1938 [(clobber (match_operand:P 0 "register_operand" "=d"))
1939 (clobber (match_operand:P 1 "register_operand" "=d"))
1940 (set (reg:CCU CC_REGNUM)
1941 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
1942 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
1945 "clst\t%0,%1\;jo\t.-4"
1946 [(set_attr "length" "8")
1947 (set_attr "type" "vs")])
1950 ; movstr instruction pattern.
1953 (define_expand "movstr"
1954 [(set (reg:SI 0) (const_int 0))
1956 [(clobber (match_dup 3))
1957 (set (match_operand:BLK 1 "memory_operand" "")
1958 (match_operand:BLK 2 "memory_operand" ""))
1959 (set (match_operand 0 "register_operand" "")
1960 (unspec [(match_dup 1)
1962 (reg:SI 0)] UNSPEC_MVST))
1963 (clobber (reg:CC CC_REGNUM))])]
1966 rtx addr1 = gen_reg_rtx (Pmode);
1967 rtx addr2 = gen_reg_rtx (Pmode);
1969 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1970 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
1971 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1972 operands[2] = replace_equiv_address_nv (operands[2], addr2);
1973 operands[3] = addr2;
1976 (define_insn "*movstr"
1977 [(clobber (match_operand:P 2 "register_operand" "=d"))
1978 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
1979 (mem:BLK (match_operand:P 3 "register_operand" "2")))
1980 (set (match_operand:P 0 "register_operand" "=d")
1981 (unspec [(mem:BLK (match_dup 1))
1982 (mem:BLK (match_dup 3))
1983 (reg:SI 0)] UNSPEC_MVST))
1984 (clobber (reg:CC CC_REGNUM))]
1986 "mvst\t%1,%2\;jo\t.-4"
1987 [(set_attr "length" "8")
1988 (set_attr "type" "vs")])
1992 ; movmemM instruction pattern(s).
1995 (define_expand "movmem<mode>"
1996 [(set (match_operand:BLK 0 "memory_operand" "")
1997 (match_operand:BLK 1 "memory_operand" ""))
1998 (use (match_operand:GPR 2 "general_operand" ""))
1999 (match_operand 3 "" "")]
2001 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2003 ; Move a block that is up to 256 bytes in length.
2004 ; The block length is taken as (operands[2] % 256) + 1.
2006 (define_expand "movmem_short"
2008 [(set (match_operand:BLK 0 "memory_operand" "")
2009 (match_operand:BLK 1 "memory_operand" ""))
2010 (use (match_operand 2 "nonmemory_operand" ""))
2011 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2012 (clobber (match_dup 3))])]
2014 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2016 (define_insn "*movmem_short"
2017 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2018 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
2019 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2020 (use (match_operand 3 "immediate_operand" "X,R,X"))
2021 (clobber (match_scratch 4 "=X,X,&a"))]
2022 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2023 && GET_MODE (operands[4]) == Pmode"
2025 [(set_attr "type" "cs")])
2028 [(set (match_operand:BLK 0 "memory_operand" "")
2029 (match_operand:BLK 1 "memory_operand" ""))
2030 (use (match_operand 2 "const_int_operand" ""))
2031 (use (match_operand 3 "immediate_operand" ""))
2032 (clobber (scratch))]
2035 [(set (match_dup 0) (match_dup 1))
2036 (use (match_dup 2))])]
2037 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2040 [(set (match_operand:BLK 0 "memory_operand" "")
2041 (match_operand:BLK 1 "memory_operand" ""))
2042 (use (match_operand 2 "register_operand" ""))
2043 (use (match_operand 3 "memory_operand" ""))
2044 (clobber (scratch))]
2047 [(unspec [(match_dup 2) (match_dup 3)
2048 (const_int 0)] UNSPEC_EXECUTE)
2049 (set (match_dup 0) (match_dup 1))
2050 (use (const_int 1))])]
2054 [(set (match_operand:BLK 0 "memory_operand" "")
2055 (match_operand:BLK 1 "memory_operand" ""))
2056 (use (match_operand 2 "register_operand" ""))
2057 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2058 (clobber (match_operand 3 "register_operand" ""))]
2059 "reload_completed && TARGET_CPU_ZARCH"
2060 [(set (match_dup 3) (label_ref (match_dup 4)))
2062 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2063 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2064 (set (match_dup 0) (match_dup 1))
2065 (use (const_int 1))])]
2066 "operands[4] = gen_label_rtx ();")
2068 ; Move a block of arbitrary length.
2070 (define_expand "movmem_long"
2072 [(clobber (match_dup 2))
2073 (clobber (match_dup 3))
2074 (set (match_operand:BLK 0 "memory_operand" "")
2075 (match_operand:BLK 1 "memory_operand" ""))
2076 (use (match_operand 2 "general_operand" ""))
2078 (clobber (reg:CC CC_REGNUM))])]
2081 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2082 rtx reg0 = gen_reg_rtx (dword_mode);
2083 rtx reg1 = gen_reg_rtx (dword_mode);
2084 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2085 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2086 rtx len0 = gen_lowpart (Pmode, reg0);
2087 rtx len1 = gen_lowpart (Pmode, reg1);
2089 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2090 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2091 emit_move_insn (len0, operands[2]);
2093 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2094 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2095 emit_move_insn (len1, operands[2]);
2097 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2098 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2103 (define_insn "*movmem_long"
2104 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2105 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2106 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2107 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2110 (clobber (reg:CC CC_REGNUM))]
2112 "mvcle\t%0,%1,0\;jo\t.-4"
2113 [(set_attr "length" "8")
2114 (set_attr "type" "vs")])
2117 ; setmemM instruction pattern(s).
2120 (define_expand "setmem<mode>"
2121 [(set (match_operand:BLK 0 "memory_operand" "")
2122 (match_operand:QI 2 "general_operand" ""))
2123 (use (match_operand:GPR 1 "general_operand" ""))
2124 (match_operand 3 "" "")]
2126 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2128 ; Clear a block that is up to 256 bytes in length.
2129 ; The block length is taken as (operands[1] % 256) + 1.
2131 (define_expand "clrmem_short"
2133 [(set (match_operand:BLK 0 "memory_operand" "")
2135 (use (match_operand 1 "nonmemory_operand" ""))
2136 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2137 (clobber (match_dup 2))
2138 (clobber (reg:CC CC_REGNUM))])]
2140 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2142 (define_insn "*clrmem_short"
2143 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2145 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
2146 (use (match_operand 2 "immediate_operand" "X,R,X"))
2147 (clobber (match_scratch 3 "=X,X,&a"))
2148 (clobber (reg:CC CC_REGNUM))]
2149 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2150 && GET_MODE (operands[3]) == Pmode"
2152 [(set_attr "type" "cs")])
2155 [(set (match_operand:BLK 0 "memory_operand" "")
2157 (use (match_operand 1 "const_int_operand" ""))
2158 (use (match_operand 2 "immediate_operand" ""))
2160 (clobber (reg:CC CC_REGNUM))]
2163 [(set (match_dup 0) (const_int 0))
2165 (clobber (reg:CC CC_REGNUM))])]
2166 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2169 [(set (match_operand:BLK 0 "memory_operand" "")
2171 (use (match_operand 1 "register_operand" ""))
2172 (use (match_operand 2 "memory_operand" ""))
2174 (clobber (reg:CC CC_REGNUM))]
2177 [(unspec [(match_dup 1) (match_dup 2)
2178 (const_int 0)] UNSPEC_EXECUTE)
2179 (set (match_dup 0) (const_int 0))
2181 (clobber (reg:CC CC_REGNUM))])]
2185 [(set (match_operand:BLK 0 "memory_operand" "")
2187 (use (match_operand 1 "register_operand" ""))
2188 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2189 (clobber (match_operand 2 "register_operand" ""))
2190 (clobber (reg:CC CC_REGNUM))]
2191 "reload_completed && TARGET_CPU_ZARCH"
2192 [(set (match_dup 2) (label_ref (match_dup 3)))
2194 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2195 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2196 (set (match_dup 0) (const_int 0))
2198 (clobber (reg:CC CC_REGNUM))])]
2199 "operands[3] = gen_label_rtx ();")
2201 ; Initialize a block of arbitrary length with (operands[2] % 256).
2203 (define_expand "setmem_long"
2205 [(clobber (match_dup 1))
2206 (set (match_operand:BLK 0 "memory_operand" "")
2207 (match_operand 2 "setmem_operand" ""))
2208 (use (match_operand 1 "general_operand" ""))
2210 (clobber (reg:CC CC_REGNUM))])]
2213 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2214 rtx reg0 = gen_reg_rtx (dword_mode);
2215 rtx reg1 = gen_reg_rtx (dword_mode);
2216 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2217 rtx len0 = gen_lowpart (Pmode, reg0);
2219 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2220 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2221 emit_move_insn (len0, operands[1]);
2223 emit_move_insn (reg1, const0_rtx);
2225 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2230 (define_insn "*setmem_long"
2231 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2232 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2233 (match_operand 2 "setmem_operand" "Y"))
2235 (use (match_operand:<DBL> 1 "register_operand" "d"))
2236 (clobber (reg:CC CC_REGNUM))]
2238 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2239 [(set_attr "length" "8")
2240 (set_attr "type" "vs")])
2243 ; cmpmemM instruction pattern(s).
2246 (define_expand "cmpmemsi"
2247 [(set (match_operand:SI 0 "register_operand" "")
2248 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2249 (match_operand:BLK 2 "memory_operand" "") ) )
2250 (use (match_operand:SI 3 "general_operand" ""))
2251 (use (match_operand:SI 4 "" ""))]
2253 "s390_expand_cmpmem (operands[0], operands[1],
2254 operands[2], operands[3]); DONE;")
2256 ; Compare a block that is up to 256 bytes in length.
2257 ; The block length is taken as (operands[2] % 256) + 1.
2259 (define_expand "cmpmem_short"
2261 [(set (reg:CCU CC_REGNUM)
2262 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2263 (match_operand:BLK 1 "memory_operand" "")))
2264 (use (match_operand 2 "nonmemory_operand" ""))
2265 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2266 (clobber (match_dup 3))])]
2268 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2270 (define_insn "*cmpmem_short"
2271 [(set (reg:CCU CC_REGNUM)
2272 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2273 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2274 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2275 (use (match_operand 3 "immediate_operand" "X,R,X"))
2276 (clobber (match_scratch 4 "=X,X,&a"))]
2277 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2278 && GET_MODE (operands[4]) == Pmode"
2280 [(set_attr "type" "cs")])
2283 [(set (reg:CCU CC_REGNUM)
2284 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2285 (match_operand:BLK 1 "memory_operand" "")))
2286 (use (match_operand 2 "const_int_operand" ""))
2287 (use (match_operand 3 "immediate_operand" ""))
2288 (clobber (scratch))]
2291 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2292 (use (match_dup 2))])]
2293 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2296 [(set (reg:CCU CC_REGNUM)
2297 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2298 (match_operand:BLK 1 "memory_operand" "")))
2299 (use (match_operand 2 "register_operand" ""))
2300 (use (match_operand 3 "memory_operand" ""))
2301 (clobber (scratch))]
2304 [(unspec [(match_dup 2) (match_dup 3)
2305 (const_int 0)] UNSPEC_EXECUTE)
2306 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2307 (use (const_int 1))])]
2311 [(set (reg:CCU CC_REGNUM)
2312 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2313 (match_operand:BLK 1 "memory_operand" "")))
2314 (use (match_operand 2 "register_operand" ""))
2315 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2316 (clobber (match_operand 3 "register_operand" ""))]
2317 "reload_completed && TARGET_CPU_ZARCH"
2318 [(set (match_dup 3) (label_ref (match_dup 4)))
2320 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2321 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2322 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2323 (use (const_int 1))])]
2324 "operands[4] = gen_label_rtx ();")
2326 ; Compare a block of arbitrary length.
2328 (define_expand "cmpmem_long"
2330 [(clobber (match_dup 2))
2331 (clobber (match_dup 3))
2332 (set (reg:CCU CC_REGNUM)
2333 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2334 (match_operand:BLK 1 "memory_operand" "")))
2335 (use (match_operand 2 "general_operand" ""))
2336 (use (match_dup 3))])]
2339 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2340 rtx reg0 = gen_reg_rtx (dword_mode);
2341 rtx reg1 = gen_reg_rtx (dword_mode);
2342 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2343 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2344 rtx len0 = gen_lowpart (Pmode, reg0);
2345 rtx len1 = gen_lowpart (Pmode, reg1);
2347 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2348 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2349 emit_move_insn (len0, operands[2]);
2351 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2352 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2353 emit_move_insn (len1, operands[2]);
2355 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2356 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2361 (define_insn "*cmpmem_long"
2362 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2363 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2364 (set (reg:CCU CC_REGNUM)
2365 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2366 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
2368 (use (match_dup 3))]
2370 "clcle\t%0,%1,0\;jo\t.-4"
2371 [(set_attr "length" "8")
2372 (set_attr "type" "vs")])
2374 ; Convert CCUmode condition code to integer.
2375 ; Result is zero if EQ, positive if LTU, negative if GTU.
2377 (define_insn_and_split "cmpint"
2378 [(set (match_operand:SI 0 "register_operand" "=d")
2379 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2381 (clobber (reg:CC CC_REGNUM))]
2385 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2387 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2388 (clobber (reg:CC CC_REGNUM))])])
2390 (define_insn_and_split "*cmpint_cc"
2391 [(set (reg CC_REGNUM)
2392 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2395 (set (match_operand:SI 0 "register_operand" "=d")
2396 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2397 "s390_match_ccmode (insn, CCSmode)"
2399 "&& reload_completed"
2400 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2402 [(set (match_dup 2) (match_dup 3))
2403 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2405 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2406 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2407 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2410 (define_insn_and_split "*cmpint_sign"
2411 [(set (match_operand:DI 0 "register_operand" "=d")
2412 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2414 (clobber (reg:CC CC_REGNUM))]
2417 "&& reload_completed"
2418 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2420 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2421 (clobber (reg:CC CC_REGNUM))])])
2423 (define_insn_and_split "*cmpint_sign_cc"
2424 [(set (reg CC_REGNUM)
2425 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2426 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2428 (const_int 32)) (const_int 32))
2430 (set (match_operand:DI 0 "register_operand" "=d")
2431 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2432 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2434 "&& reload_completed"
2435 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2437 [(set (match_dup 2) (match_dup 3))
2438 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2440 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2441 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2442 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2447 ;;- Conversion instructions.
2451 (define_insn "*sethigh<mode>si"
2452 [(set (match_operand:SI 0 "register_operand" "=d,d")
2453 (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2454 (clobber (reg:CC CC_REGNUM))]
2457 icm\t%0,<icm_hi>,%S1
2458 icmy\t%0,<icm_hi>,%S1"
2459 [(set_attr "op_type" "RS,RSY")])
2461 (define_insn "*sethighqidi_64"
2462 [(set (match_operand:DI 0 "register_operand" "=d")
2463 (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
2464 (clobber (reg:CC CC_REGNUM))]
2467 [(set_attr "op_type" "RSY")])
2469 (define_insn "*sethighqidi_31"
2470 [(set (match_operand:DI 0 "register_operand" "=d,d")
2471 (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2472 (clobber (reg:CC CC_REGNUM))]
2477 [(set_attr "op_type" "RS,RSY")])
2479 (define_insn_and_split "*extractqi"
2480 [(set (match_operand:SI 0 "register_operand" "=d")
2481 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2482 (match_operand 2 "const_int_operand" "n")
2484 (clobber (reg:CC CC_REGNUM))]
2486 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2488 "&& reload_completed"
2490 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2491 (clobber (reg:CC CC_REGNUM))])
2492 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2494 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2495 operands[1] = change_address (operands[1], QImode, 0);
2498 (define_insn_and_split "*extracthi"
2499 [(set (match_operand:SI 0 "register_operand" "=d")
2500 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2501 (match_operand 2 "const_int_operand" "n")
2503 (clobber (reg:CC CC_REGNUM))]
2505 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2507 "&& reload_completed"
2509 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2510 (clobber (reg:CC CC_REGNUM))])
2511 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2513 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2514 operands[1] = change_address (operands[1], HImode, 0);
2518 ; extendsidi2 instruction pattern(s).
2521 (define_expand "extendsidi2"
2522 [(set (match_operand:DI 0 "register_operand" "")
2523 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2528 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2529 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2530 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2531 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2536 (define_insn "*extendsidi2"
2537 [(set (match_operand:DI 0 "register_operand" "=d,d")
2538 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2543 [(set_attr "op_type" "RRE,RXY")])
2546 ; extend(hi|qi)di2 instruction pattern(s).
2549 (define_expand "extend<mode>di2"
2550 [(set (match_operand:DI 0 "register_operand" "")
2551 (sign_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2556 rtx tmp = gen_reg_rtx (SImode);
2557 emit_insn (gen_extend<mode>si2 (tmp, operands[1]));
2558 emit_insn (gen_extendsidi2 (operands[0], tmp));
2561 else if (!TARGET_EXTIMM)
2563 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) -
2564 GET_MODE_BITSIZE (<MODE>mode));
2565 operands[1] = gen_lowpart (DImode, operands[1]);
2566 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2567 emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount));
2572 (define_insn "*extendhidi2_extimm"
2573 [(set (match_operand:DI 0 "register_operand" "=d,d")
2574 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
2575 "TARGET_64BIT && TARGET_EXTIMM"
2579 [(set_attr "op_type" "RRE,RXY")])
2581 (define_insn "*extendhidi2"
2582 [(set (match_operand:DI 0 "register_operand" "=d")
2583 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2586 [(set_attr "op_type" "RXY")])
2588 (define_insn "*extendqidi2_extimm"
2589 [(set (match_operand:DI 0 "register_operand" "=d,d")
2590 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2591 "TARGET_64BIT && TARGET_EXTIMM"
2595 [(set_attr "op_type" "RRE,RXY")])
2597 (define_insn "*extendqidi2"
2598 [(set (match_operand:DI 0 "register_operand" "=d")
2599 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2600 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2602 [(set_attr "op_type" "RXY")])
2604 (define_insn_and_split "*extendqidi2_short_displ"
2605 [(set (match_operand:DI 0 "register_operand" "=d")
2606 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2607 (clobber (reg:CC CC_REGNUM))]
2608 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2610 "&& reload_completed"
2612 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
2613 (clobber (reg:CC CC_REGNUM))])
2615 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2616 (clobber (reg:CC CC_REGNUM))])]
2620 ; extend(hi|qi)si2 instruction pattern(s).
2623 (define_expand "extend<mode>si2"
2624 [(set (match_operand:SI 0 "register_operand" "")
2625 (sign_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2630 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) -
2631 GET_MODE_BITSIZE(<MODE>mode));
2632 operands[1] = gen_lowpart (SImode, operands[1]);
2633 emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount));
2634 emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount));
2639 (define_insn "*extendhisi2_extimm"
2640 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2641 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
2647 [(set_attr "op_type" "RRE,RX,RXY")])
2649 (define_insn "*extendhisi2"
2650 [(set (match_operand:SI 0 "register_operand" "=d,d")
2651 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2656 [(set_attr "op_type" "RX,RXY")])
2658 (define_insn "*extendqisi2_extimm"
2659 [(set (match_operand:SI 0 "register_operand" "=d,d")
2660 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2665 [(set_attr "op_type" "RRE,RXY")])
2667 (define_insn "*extendqisi2"
2668 [(set (match_operand:SI 0 "register_operand" "=d")
2669 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2670 "TARGET_LONG_DISPLACEMENT && !TARGET_EXTIMM"
2672 [(set_attr "op_type" "RXY")])
2674 (define_insn_and_split "*extendqisi2_short_displ"
2675 [(set (match_operand:SI 0 "register_operand" "=d")
2676 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2677 (clobber (reg:CC CC_REGNUM))]
2678 "!TARGET_LONG_DISPLACEMENT"
2680 "&& reload_completed"
2682 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2683 (clobber (reg:CC CC_REGNUM))])
2685 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2686 (clobber (reg:CC CC_REGNUM))])]
2690 ; extendqihi2 instruction pattern(s).
2695 ; zero_extendsidi2 instruction pattern(s).
2698 (define_expand "zero_extendsidi2"
2699 [(set (match_operand:DI 0 "register_operand" "")
2700 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2705 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2706 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2707 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2712 (define_insn "*zero_extendsidi2"
2713 [(set (match_operand:DI 0 "register_operand" "=d,d")
2714 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2719 [(set_attr "op_type" "RRE,RXY")])
2722 ; zero_extend(hi|qi)di2 instruction pattern(s).
2725 (define_expand "zero_extend<mode>di2"
2726 [(set (match_operand:DI 0 "register_operand" "")
2727 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2732 rtx tmp = gen_reg_rtx (SImode);
2733 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
2734 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2737 else if (!TARGET_EXTIMM)
2739 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
2740 GET_MODE_BITSIZE(<MODE>mode));
2741 operands[1] = gen_lowpart (DImode, operands[1]);
2742 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2743 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
2748 (define_insn "*zero_extend<mode>di2_extimm"
2749 [(set (match_operand:DI 0 "register_operand" "=d,d")
2750 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
2751 "TARGET_64BIT && TARGET_EXTIMM"
2755 [(set_attr "op_type" "RRE,RXY")])
2757 (define_insn "*zero_extend<mode>di2"
2758 [(set (match_operand:DI 0 "register_operand" "=d")
2759 (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))]
2760 "TARGET_64BIT && !TARGET_EXTIMM"
2762 [(set_attr "op_type" "RXY")])
2765 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2768 (define_insn "*llgt_sidi"
2769 [(set (match_operand:DI 0 "register_operand" "=d")
2770 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2771 (const_int 2147483647)))]
2774 [(set_attr "op_type" "RXE")])
2776 (define_insn_and_split "*llgt_sidi_split"
2777 [(set (match_operand:DI 0 "register_operand" "=d")
2778 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2779 (const_int 2147483647)))
2780 (clobber (reg:CC CC_REGNUM))]
2783 "&& reload_completed"
2785 (and:DI (subreg:DI (match_dup 1) 0)
2786 (const_int 2147483647)))]
2789 (define_insn "*llgt_sisi"
2790 [(set (match_operand:SI 0 "register_operand" "=d,d")
2791 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2792 (const_int 2147483647)))]
2797 [(set_attr "op_type" "RRE,RXE")])
2799 (define_insn "*llgt_didi"
2800 [(set (match_operand:DI 0 "register_operand" "=d,d")
2801 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2802 (const_int 2147483647)))]
2807 [(set_attr "op_type" "RRE,RXE")])
2810 [(set (match_operand:GPR 0 "register_operand" "")
2811 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
2812 (const_int 2147483647)))
2813 (clobber (reg:CC CC_REGNUM))]
2814 "TARGET_ZARCH && reload_completed"
2816 (and:GPR (match_dup 1)
2817 (const_int 2147483647)))]
2821 ; zero_extend(hi|qi)si2 instruction pattern(s).
2824 (define_expand "zero_extend<mode>si2"
2825 [(set (match_operand:SI 0 "register_operand" "")
2826 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2831 operands[1] = gen_lowpart (SImode, operands[1]);
2832 emit_insn (gen_andsi3 (operands[0], operands[1],
2833 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
2838 (define_insn "*zero_extend<mode>si2_extimm"
2839 [(set (match_operand:SI 0 "register_operand" "=d,d")
2840 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
2845 [(set_attr "op_type" "RRE,RXY")])
2847 (define_insn "*zero_extend<mode>si2_64"
2848 [(set (match_operand:SI 0 "register_operand" "=d")
2849 (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))]
2850 "TARGET_ZARCH && !TARGET_EXTIMM"
2852 [(set_attr "op_type" "RXY")])
2854 (define_insn_and_split "*zero_extendhisi2_31"
2855 [(set (match_operand:SI 0 "register_operand" "=&d")
2856 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2857 (clobber (reg:CC CC_REGNUM))]
2860 "&& reload_completed"
2861 [(set (match_dup 0) (const_int 0))
2863 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2864 (clobber (reg:CC CC_REGNUM))])]
2865 "operands[2] = gen_lowpart (HImode, operands[0]);")
2867 (define_insn_and_split "*zero_extendqisi2_31"
2868 [(set (match_operand:SI 0 "register_operand" "=&d")
2869 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2872 "&& reload_completed"
2873 [(set (match_dup 0) (const_int 0))
2874 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2875 "operands[2] = gen_lowpart (QImode, operands[0]);")
2878 ; zero_extendqihi2 instruction pattern(s).
2881 (define_expand "zero_extendqihi2"
2882 [(set (match_operand:HI 0 "register_operand" "")
2883 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2884 "TARGET_ZARCH && !TARGET_EXTIMM"
2886 operands[1] = gen_lowpart (HImode, operands[1]);
2887 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2891 (define_insn "*zero_extendqihi2_64"
2892 [(set (match_operand:HI 0 "register_operand" "=d")
2893 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2894 "TARGET_ZARCH && !TARGET_EXTIMM"
2896 [(set_attr "op_type" "RXY")])
2898 (define_insn_and_split "*zero_extendqihi2_31"
2899 [(set (match_operand:HI 0 "register_operand" "=&d")
2900 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2903 "&& reload_completed"
2904 [(set (match_dup 0) (const_int 0))
2905 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2906 "operands[2] = gen_lowpart (QImode, operands[0]);")
2910 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
2913 (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
2914 [(set (match_operand:GPR 0 "register_operand" "")
2915 (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
2916 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2918 rtx label1 = gen_label_rtx ();
2919 rtx label2 = gen_label_rtx ();
2920 rtx temp = gen_reg_rtx (<FPR:MODE>mode);
2921 REAL_VALUE_TYPE cmp, sub;
2923 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2924 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
2925 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
2927 emit_insn (gen_cmp<FPR:mode> (operands[1],
2928 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
2929 emit_jump_insn (gen_blt (label1));
2930 emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
2931 CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
2932 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
2936 emit_label (label1);
2937 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
2938 operands[1], GEN_INT(5)));
2939 emit_label (label2);
2943 (define_expand "fix_trunc<FPR:mode>di2"
2944 [(set (match_operand:DI 0 "register_operand" "")
2945 (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))]
2946 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2948 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
2949 emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1],
2954 (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
2955 [(set (match_operand:GPR 0 "register_operand" "=d")
2956 (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
2957 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
2958 (clobber (reg:CC CC_REGNUM))]
2959 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2960 "c<GPR:gf><FPR:de>br\t%0,%h2,%1"
2961 [(set_attr "op_type" "RRE")
2962 (set_attr "type" "ftoi")])
2965 ; fix_truncdfsi2 instruction pattern(s).
2968 (define_expand "fix_truncdfsi2"
2969 [(set (match_operand:SI 0 "register_operand" "")
2970 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2973 if (TARGET_IBM_FLOAT)
2975 /* This is the algorithm from POP chapter A.5.7.2. */
2977 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2978 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2979 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2981 operands[1] = force_reg (DFmode, operands[1]);
2982 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2983 two31r, two32, temp));
2987 operands[1] = force_reg (DFmode, operands[1]);
2988 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2994 (define_insn "fix_truncdfsi2_ibm"
2995 [(set (match_operand:SI 0 "register_operand" "=d")
2996 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2997 (use (match_operand:DI 2 "immediate_operand" "m"))
2998 (use (match_operand:DI 3 "immediate_operand" "m"))
2999 (use (match_operand:BLK 4 "memory_operand" "m"))
3000 (clobber (reg:CC CC_REGNUM))]
3001 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3003 output_asm_insn ("sd\t%1,%2", operands);
3004 output_asm_insn ("aw\t%1,%3", operands);
3005 output_asm_insn ("std\t%1,%4", operands);
3006 output_asm_insn ("xi\t%N4,128", operands);
3009 [(set_attr "length" "20")])
3012 ; fix_truncsfsi2 instruction pattern(s).
3015 (define_expand "fix_truncsfsi2"
3016 [(set (match_operand:SI 0 "register_operand" "")
3017 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
3020 if (TARGET_IBM_FLOAT)
3022 /* Convert to DFmode and then use the POP algorithm. */
3023 rtx temp = gen_reg_rtx (DFmode);
3024 emit_insn (gen_extendsfdf2 (temp, operands[1]));
3025 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
3029 operands[1] = force_reg (SFmode, operands[1]);
3030 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3037 ; floatdi(df|sf)2 instruction pattern(s).
3040 (define_insn "floatdi<mode>2"
3041 [(set (match_operand:FPR 0 "register_operand" "=f")
3042 (float:FPR (match_operand:DI 1 "register_operand" "d")))]
3043 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3045 [(set_attr "op_type" "RRE")
3046 (set_attr "type" "itof" )])
3049 ; floatsidf2 instruction pattern(s).
3052 (define_expand "floatsidf2"
3053 [(set (match_operand:DF 0 "register_operand" "")
3054 (float:DF (match_operand:SI 1 "register_operand" "")))]
3057 if (TARGET_IBM_FLOAT)
3059 /* This is the algorithm from POP chapter A.5.7.1. */
3061 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3062 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
3064 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
3069 (define_insn "floatsidf2_ieee"
3070 [(set (match_operand:DF 0 "register_operand" "=f")
3071 (float:DF (match_operand:SI 1 "register_operand" "d")))]
3072 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3074 [(set_attr "op_type" "RRE")
3075 (set_attr "type" "itof" )])
3077 (define_insn "floatsidf2_ibm"
3078 [(set (match_operand:DF 0 "register_operand" "=f")
3079 (float:DF (match_operand:SI 1 "register_operand" "d")))
3080 (use (match_operand:DI 2 "immediate_operand" "m"))
3081 (use (match_operand:BLK 3 "memory_operand" "m"))
3082 (clobber (reg:CC CC_REGNUM))]
3083 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3085 output_asm_insn ("st\t%1,%N3", operands);
3086 output_asm_insn ("xi\t%N3,128", operands);
3087 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
3088 output_asm_insn ("ld\t%0,%3", operands);
3091 [(set_attr "length" "20")])
3094 ; floatsisf2 instruction pattern(s).
3097 (define_expand "floatsisf2"
3098 [(set (match_operand:SF 0 "register_operand" "")
3099 (float:SF (match_operand:SI 1 "register_operand" "")))]
3102 if (TARGET_IBM_FLOAT)
3104 /* Use the POP algorithm to convert to DFmode and then truncate. */
3105 rtx temp = gen_reg_rtx (DFmode);
3106 emit_insn (gen_floatsidf2 (temp, operands[1]));
3107 emit_insn (gen_truncdfsf2 (operands[0], temp));
3112 (define_insn "floatsisf2_ieee"
3113 [(set (match_operand:SF 0 "register_operand" "=f")
3114 (float:SF (match_operand:SI 1 "register_operand" "d")))]
3115 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3117 [(set_attr "op_type" "RRE")
3118 (set_attr "type" "itof" )])
3121 ; truncdfsf2 instruction pattern(s).
3124 (define_expand "truncdfsf2"
3125 [(set (match_operand:SF 0 "register_operand" "")
3126 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
3130 (define_insn "truncdfsf2_ieee"
3131 [(set (match_operand:SF 0 "register_operand" "=f")
3132 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3133 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3135 [(set_attr "op_type" "RRE")])
3137 (define_insn "truncdfsf2_ibm"
3138 [(set (match_operand:SF 0 "register_operand" "=f,f")
3139 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3140 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3144 [(set_attr "op_type" "RR,RX")
3145 (set_attr "type" "floadsf")])
3148 ; extendsfdf2 instruction pattern(s).
3151 (define_expand "extendsfdf2"
3152 [(set (match_operand:DF 0 "register_operand" "")
3153 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3156 if (TARGET_IBM_FLOAT)
3158 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3163 (define_insn "extendsfdf2_ieee"
3164 [(set (match_operand:DF 0 "register_operand" "=f,f")
3165 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3166 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3170 [(set_attr "op_type" "RRE,RXE")
3171 (set_attr "type" "floadsf")])
3173 (define_insn "extendsfdf2_ibm"
3174 [(set (match_operand:DF 0 "register_operand" "=f,f")
3175 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
3176 (clobber (reg:CC CC_REGNUM))]
3177 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3179 sdr\t%0,%0\;ler\t%0,%1
3180 sdr\t%0,%0\;le\t%0,%1"
3181 [(set_attr "length" "4,6")
3182 (set_attr "type" "floadsf")])
3186 ;; ARITHMETIC OPERATIONS
3188 ; arithmetic operations set the ConditionCode,
3189 ; because of unpredictable Bits in Register for Halfword and Byte
3190 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3193 ;;- Add instructions.
3197 ; addti3 instruction pattern(s).
3200 (define_insn_and_split "addti3"
3201 [(set (match_operand:TI 0 "register_operand" "=&d")
3202 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3203 (match_operand:TI 2 "general_operand" "do") ) )
3204 (clobber (reg:CC CC_REGNUM))]
3207 "&& reload_completed"
3209 [(set (reg:CCL1 CC_REGNUM)
3210 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3212 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3214 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3215 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
3216 (clobber (reg:CC CC_REGNUM))])]
3217 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3218 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3219 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3220 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3221 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3222 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3225 ; adddi3 instruction pattern(s).
3228 (define_insn "*adddi3_sign"
3229 [(set (match_operand:DI 0 "register_operand" "=d,d")
3230 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3231 (match_operand:DI 1 "register_operand" "0,0")))
3232 (clobber (reg:CC CC_REGNUM))]
3237 [(set_attr "op_type" "RRE,RXY")])
3239 (define_insn "*adddi3_zero_cc"
3240 [(set (reg CC_REGNUM)
3241 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3242 (match_operand:DI 1 "register_operand" "0,0"))
3244 (set (match_operand:DI 0 "register_operand" "=d,d")
3245 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3246 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3250 [(set_attr "op_type" "RRE,RXY")])
3252 (define_insn "*adddi3_zero_cconly"
3253 [(set (reg CC_REGNUM)
3254 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3255 (match_operand:DI 1 "register_operand" "0,0"))
3257 (clobber (match_scratch:DI 0 "=d,d"))]
3258 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3262 [(set_attr "op_type" "RRE,RXY")])
3264 (define_insn "*adddi3_zero"
3265 [(set (match_operand:DI 0 "register_operand" "=d,d")
3266 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3267 (match_operand:DI 1 "register_operand" "0,0")))
3268 (clobber (reg:CC CC_REGNUM))]
3273 [(set_attr "op_type" "RRE,RXY")])
3275 (define_insn "*adddi3_imm_cc"
3276 [(set (reg CC_REGNUM)
3277 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
3278 (match_operand:DI 2 "const_int_operand" "K,Os"))
3280 (set (match_operand:DI 0 "register_operand" "=d,d")
3281 (plus:DI (match_dup 1) (match_dup 2)))]
3283 && s390_match_ccmode (insn, CCAmode)
3284 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3285 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))"
3289 [(set_attr "op_type" "RI,RIL")])
3291 (define_insn "*adddi3_carry1_cc"
3292 [(set (reg CC_REGNUM)
3293 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3294 (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3296 (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3297 (plus:DI (match_dup 1) (match_dup 2)))]
3298 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3304 [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
3306 (define_insn "*adddi3_carry1_cconly"
3307 [(set (reg CC_REGNUM)
3308 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3309 (match_operand:DI 2 "general_operand" "d,m"))
3311 (clobber (match_scratch:DI 0 "=d,d"))]
3312 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3316 [(set_attr "op_type" "RRE,RXY")])
3318 (define_insn "*adddi3_carry2_cc"
3319 [(set (reg CC_REGNUM)
3320 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3321 (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3323 (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3324 (plus:DI (match_dup 1) (match_dup 2)))]
3325 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3331 [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
3333 (define_insn "*adddi3_carry2_cconly"
3334 [(set (reg CC_REGNUM)
3335 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3336 (match_operand:DI 2 "general_operand" "d,m"))
3338 (clobber (match_scratch:DI 0 "=d,d"))]
3339 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3343 [(set_attr "op_type" "RRE,RXY")])
3345 (define_insn "*adddi3_cc"
3346 [(set (reg CC_REGNUM)
3347 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
3348 (match_operand:DI 2 "general_operand" "d,Op,On,m"))
3350 (set (match_operand:DI 0 "register_operand" "=d,d,d,d")
3351 (plus:DI (match_dup 1) (match_dup 2)))]
3352 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3358 [(set_attr "op_type" "RRE,RIL,RIL,RXY")])
3360 (define_insn "*adddi3_cconly"
3361 [(set (reg CC_REGNUM)
3362 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3363 (match_operand:DI 2 "general_operand" "d,m"))
3365 (clobber (match_scratch:DI 0 "=d,d"))]
3366 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3370 [(set_attr "op_type" "RRE,RXY")])
3372 (define_insn "*adddi3_cconly2"
3373 [(set (reg CC_REGNUM)
3374 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3375 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3376 (clobber (match_scratch:DI 0 "=d,d"))]
3377 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3381 [(set_attr "op_type" "RRE,RXY")])
3383 (define_insn "*adddi3_64"
3384 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d")
3385 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0")
3386 (match_operand:DI 2 "general_operand" "d,K,Op,On,m") ) )
3387 (clobber (reg:CC CC_REGNUM))]
3395 [(set_attr "op_type" "RRE,RI,RIL,RIL,RXY")])
3397 (define_insn_and_split "*adddi3_31z"
3398 [(set (match_operand:DI 0 "register_operand" "=&d")
3399 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3400 (match_operand:DI 2 "general_operand" "do") ) )
3401 (clobber (reg:CC CC_REGNUM))]
3402 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3404 "&& reload_completed"
3406 [(set (reg:CCL1 CC_REGNUM)
3407 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3409 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3411 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3412 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3413 (clobber (reg:CC CC_REGNUM))])]
3414 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3415 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3416 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3417 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3418 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3419 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3421 (define_insn_and_split "*adddi3_31"
3422 [(set (match_operand:DI 0 "register_operand" "=&d")
3423 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3424 (match_operand:DI 2 "general_operand" "do") ) )
3425 (clobber (reg:CC CC_REGNUM))]
3428 "&& reload_completed"
3430 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3431 (clobber (reg:CC CC_REGNUM))])
3433 [(set (reg:CCL1 CC_REGNUM)
3434 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3436 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3438 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3440 (label_ref (match_dup 9))))
3442 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3443 (clobber (reg:CC CC_REGNUM))])
3445 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3446 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3447 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3448 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3449 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3450 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3451 operands[9] = gen_label_rtx ();")
3453 (define_expand "adddi3"
3455 [(set (match_operand:DI 0 "register_operand" "")
3456 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3457 (match_operand:DI 2 "general_operand" "")))
3458 (clobber (reg:CC CC_REGNUM))])]
3463 ; addsi3 instruction pattern(s).
3466 (define_insn "*addsi3_imm_cc"
3467 [(set (reg CC_REGNUM)
3468 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
3469 (match_operand:SI 2 "const_int_operand" "K,Os"))
3471 (set (match_operand:SI 0 "register_operand" "=d,d")
3472 (plus:SI (match_dup 1) (match_dup 2)))]
3473 "s390_match_ccmode (insn, CCAmode)
3474 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3475 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
3476 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << 31)"
3480 [(set_attr "op_type" "RI,RIL")])
3482 (define_insn "*addsi3_carry1_cc"
3483 [(set (reg CC_REGNUM)
3484 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3485 (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3487 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3488 (plus:SI (match_dup 1) (match_dup 2)))]
3489 "s390_match_ccmode (insn, CCL1mode)"
3495 [(set_attr "op_type" "RR,RIL,RX,RXY")])
3497 (define_insn "*addsi3_carry1_cconly"
3498 [(set (reg CC_REGNUM)
3499 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3500 (match_operand:SI 2 "general_operand" "d,R,T"))
3502 (clobber (match_scratch:SI 0 "=d,d,d"))]
3503 "s390_match_ccmode (insn, CCL1mode)"
3508 [(set_attr "op_type" "RR,RX,RXY")])
3510 (define_insn "*addsi3_carry2_cc"
3511 [(set (reg CC_REGNUM)
3512 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3513 (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3515 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3516 (plus:SI (match_dup 1) (match_dup 2)))]
3517 "s390_match_ccmode (insn, CCL1mode)"
3523 [(set_attr "op_type" "RR,RIL,RX,RXY")])
3525 (define_insn "*addsi3_carry2_cconly"
3526 [(set (reg CC_REGNUM)
3527 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3528 (match_operand:SI 2 "general_operand" "d,R,T"))
3530 (clobber (match_scratch:SI 0 "=d,d,d"))]
3531 "s390_match_ccmode (insn, CCL1mode)"
3536 [(set_attr "op_type" "RR,RX,RXY")])
3538 (define_insn "*addsi3_cc"
3539 [(set (reg CC_REGNUM)
3540 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3541 (match_operand:SI 2 "general_operand" "d,Os,R,T"))
3543 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3544 (plus:SI (match_dup 1) (match_dup 2)))]
3545 "s390_match_ccmode (insn, CCLmode)"
3551 [(set_attr "op_type" "RR,RIL,RX,RXY")])
3553 (define_insn "*addsi3_cconly"
3554 [(set (reg CC_REGNUM)
3555 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3556 (match_operand:SI 2 "general_operand" "d,R,T"))
3558 (clobber (match_scratch:SI 0 "=d,d,d"))]
3559 "s390_match_ccmode (insn, CCLmode)"
3564 [(set_attr "op_type" "RR,RX,RXY")])
3566 (define_insn "*addsi3_cconly2"
3567 [(set (reg CC_REGNUM)
3568 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3569 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3570 (clobber (match_scratch:SI 0 "=d,d,d"))]
3571 "s390_match_ccmode (insn, CCLmode)"
3576 [(set_attr "op_type" "RR,RX,RXY")])
3578 (define_insn "*addsi3_sign"
3579 [(set (match_operand:SI 0 "register_operand" "=d,d")
3580 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3581 (match_operand:SI 1 "register_operand" "0,0")))
3582 (clobber (reg:CC CC_REGNUM))]
3587 [(set_attr "op_type" "RX,RXY")])
3589 (define_insn "addsi3"
3590 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
3591 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
3592 (match_operand:SI 2 "general_operand" "d,K,Os,R,T")))
3593 (clobber (reg:CC CC_REGNUM))]
3601 [(set_attr "op_type" "RR,RI,RIL,RX,RXY")])
3604 ; add(df|sf)3 instruction pattern(s).
3607 (define_expand "add<mode>3"
3609 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3610 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3611 (match_operand:FPR 2 "general_operand" "f,R")))
3612 (clobber (reg:CC CC_REGNUM))])]
3616 (define_insn "*add<mode>3"
3617 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3618 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3619 (match_operand:FPR 2 "general_operand" "f,R")))
3620 (clobber (reg:CC CC_REGNUM))]
3621 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3625 [(set_attr "op_type" "RRE,RXE")
3626 (set_attr "type" "fsimp<mode>")])
3628 (define_insn "*add<mode>3_cc"
3629 [(set (reg CC_REGNUM)
3630 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3631 (match_operand:FPR 2 "general_operand" "f,R"))
3632 (match_operand:FPR 3 "const0_operand" "")))
3633 (set (match_operand:FPR 0 "register_operand" "=f,f")
3634 (plus:FPR (match_dup 1) (match_dup 2)))]
3635 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3639 [(set_attr "op_type" "RRE,RXE")
3640 (set_attr "type" "fsimp<mode>")])
3642 (define_insn "*add<mode>3_cconly"
3643 [(set (reg CC_REGNUM)
3644 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3645 (match_operand:FPR 2 "general_operand" "f,R"))
3646 (match_operand:FPR 3 "const0_operand" "")))
3647 (clobber (match_scratch:FPR 0 "=f,f"))]
3648 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3652 [(set_attr "op_type" "RRE,RXE")
3653 (set_attr "type" "fsimp<mode>")])
3655 (define_insn "*add<mode>3_ibm"
3656 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3657 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3658 (match_operand:FPR 2 "general_operand" "f,R")))
3659 (clobber (reg:CC CC_REGNUM))]
3660 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3664 [(set_attr "op_type" "RR,RX")
3665 (set_attr "type" "fsimp<mode>")])
3669 ;;- Subtract instructions.
3673 ; subti3 instruction pattern(s).
3676 (define_insn_and_split "subti3"
3677 [(set (match_operand:TI 0 "register_operand" "=&d")
3678 (minus:TI (match_operand:TI 1 "register_operand" "0")
3679 (match_operand:TI 2 "general_operand" "do") ) )
3680 (clobber (reg:CC CC_REGNUM))]
3683 "&& reload_completed"
3685 [(set (reg:CCL2 CC_REGNUM)
3686 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3688 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3690 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3691 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
3692 (clobber (reg:CC CC_REGNUM))])]
3693 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3694 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3695 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3696 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3697 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3698 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3701 ; subdi3 instruction pattern(s).
3704 (define_insn "*subdi3_sign"
3705 [(set (match_operand:DI 0 "register_operand" "=d,d")
3706 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3707 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3708 (clobber (reg:CC CC_REGNUM))]
3713 [(set_attr "op_type" "RRE,RXY")])
3715 (define_insn "*subdi3_zero_cc"
3716 [(set (reg CC_REGNUM)
3717 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3718 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3720 (set (match_operand:DI 0 "register_operand" "=d,d")
3721 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3722 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3726 [(set_attr "op_type" "RRE,RXY")])
3728 (define_insn "*subdi3_zero_cconly"
3729 [(set (reg CC_REGNUM)
3730 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3731 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3733 (clobber (match_scratch:DI 0 "=d,d"))]
3734 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3738 [(set_attr "op_type" "RRE,RXY")])
3740 (define_insn "*subdi3_zero"
3741 [(set (match_operand:DI 0 "register_operand" "=d,d")
3742 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3743 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3744 (clobber (reg:CC CC_REGNUM))]
3749 [(set_attr "op_type" "RRE,RXY")])
3751 (define_insn "*subdi3_borrow_cc"
3752 [(set (reg CC_REGNUM)
3753 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3754 (match_operand:DI 2 "general_operand" "d,m"))
3756 (set (match_operand:DI 0 "register_operand" "=d,d")
3757 (minus:DI (match_dup 1) (match_dup 2)))]
3758 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3762 [(set_attr "op_type" "RRE,RXY")])
3764 (define_insn "*subdi3_borrow_cconly"
3765 [(set (reg CC_REGNUM)
3766 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3767 (match_operand:DI 2 "general_operand" "d,m"))
3769 (clobber (match_scratch:DI 0 "=d,d"))]
3770 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3774 [(set_attr "op_type" "RRE,RXY")])
3776 (define_insn "*subdi3_cc"
3777 [(set (reg CC_REGNUM)
3778 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3779 (match_operand:DI 2 "general_operand" "d,m"))
3781 (set (match_operand:DI 0 "register_operand" "=d,d")
3782 (minus:DI (match_dup 1) (match_dup 2)))]
3783 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3787 [(set_attr "op_type" "RRE,RXY")])
3789 (define_insn "*subdi3_cc2"
3790 [(set (reg CC_REGNUM)
3791 (compare (match_operand:DI 1 "register_operand" "0,0")
3792 (match_operand:DI 2 "general_operand" "d,m")))
3793 (set (match_operand:DI 0 "register_operand" "=d,d")
3794 (minus:DI (match_dup 1) (match_dup 2)))]
3795 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3799 [(set_attr "op_type" "RRE,RXY")])
3801 (define_insn "*subdi3_cconly"
3802 [(set (reg CC_REGNUM)
3803 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3804 (match_operand:DI 2 "general_operand" "d,m"))
3806 (clobber (match_scratch:DI 0 "=d,d"))]
3807 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3811 [(set_attr "op_type" "RRE,RXY")])
3813 (define_insn "*subdi3_cconly2"
3814 [(set (reg CC_REGNUM)
3815 (compare (match_operand:DI 1 "register_operand" "0,0")
3816 (match_operand:DI 2 "general_operand" "d,m")))
3817 (clobber (match_scratch:DI 0 "=d,d"))]
3818 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3822 [(set_attr "op_type" "RRE,RXY")])
3824 (define_insn "*subdi3_64"
3825 [(set (match_operand:DI 0 "register_operand" "=d,d")
3826 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3827 (match_operand:DI 2 "general_operand" "d,m") ) )
3828 (clobber (reg:CC CC_REGNUM))]
3833 [(set_attr "op_type" "RRE,RRE")])
3835 (define_insn_and_split "*subdi3_31z"
3836 [(set (match_operand:DI 0 "register_operand" "=&d")
3837 (minus:DI (match_operand:DI 1 "register_operand" "0")
3838 (match_operand:DI 2 "general_operand" "do") ) )
3839 (clobber (reg:CC CC_REGNUM))]
3840 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3842 "&& reload_completed"
3844 [(set (reg:CCL2 CC_REGNUM)
3845 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3847 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3849 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3850 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
3851 (clobber (reg:CC CC_REGNUM))])]
3852 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3853 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3854 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3855 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3856 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3857 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3859 (define_insn_and_split "*subdi3_31"
3860 [(set (match_operand:DI 0 "register_operand" "=&d")
3861 (minus:DI (match_operand:DI 1 "register_operand" "0")
3862 (match_operand:DI 2 "general_operand" "do") ) )
3863 (clobber (reg:CC CC_REGNUM))]
3866 "&& reload_completed"
3868 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3869 (clobber (reg:CC CC_REGNUM))])
3871 [(set (reg:CCL2 CC_REGNUM)
3872 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3874 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3876 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
3878 (label_ref (match_dup 9))))
3880 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3881 (clobber (reg:CC CC_REGNUM))])
3883 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3884 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3885 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3886 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3887 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3888 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3889 operands[9] = gen_label_rtx ();")
3891 (define_expand "subdi3"
3893 [(set (match_operand:DI 0 "register_operand" "")
3894 (minus:DI (match_operand:DI 1 "register_operand" "")
3895 (match_operand:DI 2 "general_operand" "")))
3896 (clobber (reg:CC CC_REGNUM))])]
3901 ; subsi3 instruction pattern(s).
3904 (define_insn "*subsi3_borrow_cc"
3905 [(set (reg CC_REGNUM)
3906 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3907 (match_operand:SI 2 "general_operand" "d,R,T"))
3909 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3910 (minus:SI (match_dup 1) (match_dup 2)))]
3911 "s390_match_ccmode (insn, CCL2mode)"
3916 [(set_attr "op_type" "RR,RX,RXY")])
3918 (define_insn "*subsi3_borrow_cconly"
3919 [(set (reg CC_REGNUM)
3920 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3921 (match_operand:SI 2 "general_operand" "d,R,T"))
3923 (clobber (match_scratch:SI 0 "=d,d,d"))]
3924 "s390_match_ccmode (insn, CCL2mode)"
3929 [(set_attr "op_type" "RR,RX,RXY")])
3931 (define_insn "*subsi3_cc"
3932 [(set (reg CC_REGNUM)
3933 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3934 (match_operand:SI 2 "general_operand" "d,R,T"))
3936 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3937 (minus:SI (match_dup 1) (match_dup 2)))]
3938 "s390_match_ccmode (insn, CCLmode)"
3943 [(set_attr "op_type" "RR,RX,RXY")])
3945 (define_insn "*subsi3_cc2"
3946 [(set (reg CC_REGNUM)
3947 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3948 (match_operand:SI 2 "general_operand" "d,R,T")))
3949 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3950 (minus:SI (match_dup 1) (match_dup 2)))]
3951 "s390_match_ccmode (insn, CCL3mode)"
3956 [(set_attr "op_type" "RR,RX,RXY")])
3958 (define_insn "*subsi3_cconly"
3959 [(set (reg CC_REGNUM)
3960 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3961 (match_operand:SI 2 "general_operand" "d,R,T"))
3963 (clobber (match_scratch:SI 0 "=d,d,d"))]
3964 "s390_match_ccmode (insn, CCLmode)"
3969 [(set_attr "op_type" "RR,RX,RXY")])
3971 (define_insn "*subsi3_cconly2"
3972 [(set (reg CC_REGNUM)
3973 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3974 (match_operand:SI 2 "general_operand" "d,R,T")))
3975 (clobber (match_scratch:SI 0 "=d,d,d"))]
3976 "s390_match_ccmode (insn, CCL3mode)"
3981 [(set_attr "op_type" "RR,RX,RXY")])
3983 (define_insn "*subsi3_sign"
3984 [(set (match_operand:SI 0 "register_operand" "=d,d")
3985 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3986 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
3987 (clobber (reg:CC CC_REGNUM))]
3992 [(set_attr "op_type" "RX,RXY")])
3994 (define_insn "subsi3"
3995 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3996 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3997 (match_operand:SI 2 "general_operand" "d,R,T")))
3998 (clobber (reg:CC CC_REGNUM))]
4004 [(set_attr "op_type" "RR,RX,RXY")])
4008 ; sub(df|sf)3 instruction pattern(s).
4011 (define_expand "sub<mode>3"
4013 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4014 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4015 (match_operand:FPR 2 "general_operand" "f,R")))
4016 (clobber (reg:CC CC_REGNUM))])]
4020 (define_insn "*sub<mode>3"
4021 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4022 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4023 (match_operand:FPR 2 "general_operand" "f,R")))
4024 (clobber (reg:CC CC_REGNUM))]
4025 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4029 [(set_attr "op_type" "RRE,RXE")
4030 (set_attr "type" "fsimp<mode>")])
4032 (define_insn "*sub<mode>3_cc"
4033 [(set (reg CC_REGNUM)
4034 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
4035 (match_operand:FPR 2 "general_operand" "f,R"))
4036 (match_operand:FPR 3 "const0_operand" "")))
4037 (set (match_operand:FPR 0 "register_operand" "=f,f")
4038 (minus:FPR (match_dup 1) (match_dup 2)))]
4039 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4043 [(set_attr "op_type" "RRE,RXE")
4044 (set_attr "type" "fsimp<mode>")])
4046 (define_insn "*sub<mode>3_cconly"
4047 [(set (reg CC_REGNUM)
4048 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
4049 (match_operand:FPR 2 "general_operand" "f,R"))
4050 (match_operand:FPR 3 "const0_operand" "")))
4051 (clobber (match_scratch:FPR 0 "=f,f"))]
4052 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4056 [(set_attr "op_type" "RRE,RXE")
4057 (set_attr "type" "fsimp<mode>")])
4059 (define_insn "*sub<mode>3_ibm"
4060 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4061 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4062 (match_operand:FPR 2 "general_operand" "f,R")))
4063 (clobber (reg:CC CC_REGNUM))]
4064 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4068 [(set_attr "op_type" "RR,RX")
4069 (set_attr "type" "fsimp<mode>")])
4073 ;;- Conditional add/subtract instructions.
4077 ; add(di|si)cc instruction pattern(s).
4080 (define_insn "*add<mode>3_alc_cc"
4081 [(set (reg CC_REGNUM)
4083 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4084 (match_operand:GPR 2 "general_operand" "d,m"))
4085 (match_operand:GPR 3 "s390_alc_comparison" ""))
4087 (set (match_operand:GPR 0 "register_operand" "=d,d")
4088 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4089 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4093 [(set_attr "op_type" "RRE,RXY")])
4095 (define_insn "*add<mode>3_alc"
4096 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4097 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4098 (match_operand:GPR 2 "general_operand" "d,m"))
4099 (match_operand:GPR 3 "s390_alc_comparison" "")))
4100 (clobber (reg:CC CC_REGNUM))]
4105 [(set_attr "op_type" "RRE,RXY")])
4107 (define_insn "*sub<mode>3_slb_cc"
4108 [(set (reg CC_REGNUM)
4110 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4111 (match_operand:GPR 2 "general_operand" "d,m"))
4112 (match_operand:GPR 3 "s390_slb_comparison" ""))
4114 (set (match_operand:GPR 0 "register_operand" "=d,d")
4115 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4116 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4120 [(set_attr "op_type" "RRE,RXY")])
4122 (define_insn "*sub<mode>3_slb"
4123 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4124 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4125 (match_operand:GPR 2 "general_operand" "d,m"))
4126 (match_operand:GPR 3 "s390_slb_comparison" "")))
4127 (clobber (reg:CC CC_REGNUM))]
4132 [(set_attr "op_type" "RRE,RXY")])
4134 (define_expand "add<mode>cc"
4135 [(match_operand:GPR 0 "register_operand" "")
4136 (match_operand 1 "comparison_operator" "")
4137 (match_operand:GPR 2 "register_operand" "")
4138 (match_operand:GPR 3 "const_int_operand" "")]
4140 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4141 s390_compare_op0, s390_compare_op1,
4142 operands[0], operands[2],
4143 operands[3])) FAIL; DONE;")
4146 ; scond instruction pattern(s).
4149 (define_insn_and_split "*scond<mode>"
4150 [(set (match_operand:GPR 0 "register_operand" "=&d")
4151 (match_operand:GPR 1 "s390_alc_comparison" ""))
4152 (clobber (reg:CC CC_REGNUM))]
4155 "&& reload_completed"
4156 [(set (match_dup 0) (const_int 0))
4158 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
4160 (clobber (reg:CC CC_REGNUM))])]
4163 (define_insn_and_split "*scond<mode>_neg"
4164 [(set (match_operand:GPR 0 "register_operand" "=&d")
4165 (match_operand:GPR 1 "s390_slb_comparison" ""))
4166 (clobber (reg:CC CC_REGNUM))]
4169 "&& reload_completed"
4170 [(set (match_dup 0) (const_int 0))
4172 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
4174 (clobber (reg:CC CC_REGNUM))])
4176 [(set (match_dup 0) (neg:GPR (match_dup 0)))
4177 (clobber (reg:CC CC_REGNUM))])]
4181 (define_expand "s<code>"
4182 [(set (match_operand:SI 0 "register_operand" "")
4183 (SCOND (match_dup 0)
4186 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
4187 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4189 (define_expand "seq"
4191 [(set (match_operand:SI 0 "register_operand" "=d")
4193 (clobber (reg:CC CC_REGNUM))])
4195 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
4196 (clobber (reg:CC CC_REGNUM))])]
4199 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
4201 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
4202 PUT_MODE (operands[1], SImode);
4205 (define_insn_and_split "*sne"
4206 [(set (match_operand:SI 0 "register_operand" "=d")
4207 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
4209 (clobber (reg:CC CC_REGNUM))]
4214 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
4215 (clobber (reg:CC CC_REGNUM))])])
4219 ;;- Multiply instructions.
4223 ; muldi3 instruction pattern(s).
4226 (define_insn "*muldi3_sign"
4227 [(set (match_operand:DI 0 "register_operand" "=d,d")
4228 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4229 (match_operand:DI 1 "register_operand" "0,0")))]
4234 [(set_attr "op_type" "RRE,RXY")
4235 (set_attr "type" "imuldi")])
4237 (define_insn "muldi3"
4238 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4239 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4240 (match_operand:DI 2 "general_operand" "d,K,m")))]
4246 [(set_attr "op_type" "RRE,RI,RXY")
4247 (set_attr "type" "imuldi")])
4250 ; mulsi3 instruction pattern(s).
4253 (define_insn "*mulsi3_sign"
4254 [(set (match_operand:SI 0 "register_operand" "=d")
4255 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4256 (match_operand:SI 1 "register_operand" "0")))]
4259 [(set_attr "op_type" "RX")
4260 (set_attr "type" "imulhi")])
4262 (define_insn "mulsi3"
4263 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4264 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4265 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4272 [(set_attr "op_type" "RRE,RI,RX,RXY")
4273 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4276 ; mulsidi3 instruction pattern(s).
4279 (define_insn "mulsidi3"
4280 [(set (match_operand:DI 0 "register_operand" "=d,d")
4281 (mult:DI (sign_extend:DI
4282 (match_operand:SI 1 "register_operand" "%0,0"))
4284 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4289 [(set_attr "op_type" "RR,RX")
4290 (set_attr "type" "imulsi")])
4293 ; umulsidi3 instruction pattern(s).
4296 (define_insn "umulsidi3"
4297 [(set (match_operand:DI 0 "register_operand" "=d,d")
4298 (mult:DI (zero_extend:DI
4299 (match_operand:SI 1 "register_operand" "%0,0"))
4301 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4302 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4306 [(set_attr "op_type" "RRE,RXY")
4307 (set_attr "type" "imulsi")])
4310 ; mul(df|sf)3 instruction pattern(s).
4313 (define_expand "mul<mode>3"
4314 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4315 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4316 (match_operand:FPR 2 "general_operand" "f,R")))]
4320 (define_insn "*mul<mode>3"
4321 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4322 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4323 (match_operand:FPR 2 "general_operand" "f,R")))]
4324 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4328 [(set_attr "op_type" "RRE,RXE")
4329 (set_attr "type" "fmul<mode>")])
4331 (define_insn "*mul<mode>3_ibm"
4332 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4333 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4334 (match_operand:FPR 2 "general_operand" "f,R")))]
4335 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4339 [(set_attr "op_type" "RR,RX")
4340 (set_attr "type" "fmul<mode>")])
4342 (define_insn "*fmadd<mode>"
4343 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4344 (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
4345 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4346 (match_operand:FPR 3 "register_operand" "0,0")))]
4347 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4351 [(set_attr "op_type" "RRE,RXE")
4352 (set_attr "type" "fmul<mode>")])
4354 (define_insn "*fmsub<mode>"
4355 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4356 (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
4357 (match_operand:FPR 2 "nonimmediate_operand" "f,R"))
4358 (match_operand:FPR 3 "register_operand" "0,0")))]
4359 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4363 [(set_attr "op_type" "RRE,RXE")
4364 (set_attr "type" "fmul<mode>")])
4367 ;;- Divide and modulo instructions.
4371 ; divmoddi4 instruction pattern(s).
4374 (define_expand "divmoddi4"
4375 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4376 (div:DI (match_operand:DI 1 "register_operand" "")
4377 (match_operand:DI 2 "general_operand" "")))
4378 (set (match_operand:DI 3 "general_operand" "")
4379 (mod:DI (match_dup 1) (match_dup 2)))])
4380 (clobber (match_dup 4))]
4383 rtx insn, div_equal, mod_equal;
4385 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4386 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4388 operands[4] = gen_reg_rtx(TImode);
4389 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4391 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4393 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4395 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4397 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4402 (define_insn "divmodtidi3"
4403 [(set (match_operand:TI 0 "register_operand" "=d,d")
4407 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4408 (match_operand:DI 2 "general_operand" "d,m")))
4410 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4415 [(set_attr "op_type" "RRE,RXY")
4416 (set_attr "type" "idiv")])
4418 (define_insn "divmodtisi3"
4419 [(set (match_operand:TI 0 "register_operand" "=d,d")
4423 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4425 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4428 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4433 [(set_attr "op_type" "RRE,RXY")
4434 (set_attr "type" "idiv")])
4437 ; udivmoddi4 instruction pattern(s).
4440 (define_expand "udivmoddi4"
4441 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4442 (udiv:DI (match_operand:DI 1 "general_operand" "")
4443 (match_operand:DI 2 "nonimmediate_operand" "")))
4444 (set (match_operand:DI 3 "general_operand" "")
4445 (umod:DI (match_dup 1) (match_dup 2)))])
4446 (clobber (match_dup 4))]
4449 rtx insn, div_equal, mod_equal, equal;
4451 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4452 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4453 equal = gen_rtx_IOR (TImode,
4454 gen_rtx_ASHIFT (TImode,
4455 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4457 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4459 operands[4] = gen_reg_rtx(TImode);
4460 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4461 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4462 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4463 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4465 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4467 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4469 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4471 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4473 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4478 (define_insn "udivmodtidi3"
4479 [(set (match_operand:TI 0 "register_operand" "=d,d")
4484 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4486 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4490 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4495 [(set_attr "op_type" "RRE,RXY")
4496 (set_attr "type" "idiv")])
4499 ; divmodsi4 instruction pattern(s).
4502 (define_expand "divmodsi4"
4503 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4504 (div:SI (match_operand:SI 1 "general_operand" "")
4505 (match_operand:SI 2 "nonimmediate_operand" "")))
4506 (set (match_operand:SI 3 "general_operand" "")
4507 (mod:SI (match_dup 1) (match_dup 2)))])
4508 (clobber (match_dup 4))]
4511 rtx insn, div_equal, mod_equal, equal;
4513 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4514 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4515 equal = gen_rtx_IOR (DImode,
4516 gen_rtx_ASHIFT (DImode,
4517 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4519 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4521 operands[4] = gen_reg_rtx(DImode);
4522 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4523 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4525 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4527 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4529 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4531 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4533 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4538 (define_insn "divmoddisi3"
4539 [(set (match_operand:DI 0 "register_operand" "=d,d")
4544 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4546 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4550 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4555 [(set_attr "op_type" "RR,RX")
4556 (set_attr "type" "idiv")])
4559 ; udivsi3 and umodsi3 instruction pattern(s).
4562 (define_expand "udivmodsi4"
4563 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4564 (udiv:SI (match_operand:SI 1 "general_operand" "")
4565 (match_operand:SI 2 "nonimmediate_operand" "")))
4566 (set (match_operand:SI 3 "general_operand" "")
4567 (umod:SI (match_dup 1) (match_dup 2)))])
4568 (clobber (match_dup 4))]
4569 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4571 rtx insn, div_equal, mod_equal, equal;
4573 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4574 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4575 equal = gen_rtx_IOR (DImode,
4576 gen_rtx_ASHIFT (DImode,
4577 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4579 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4581 operands[4] = gen_reg_rtx(DImode);
4582 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4583 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4584 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4585 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4587 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4589 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4591 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4593 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4595 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4600 (define_insn "udivmoddisi3"
4601 [(set (match_operand:DI 0 "register_operand" "=d,d")
4606 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4608 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4612 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4613 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4617 [(set_attr "op_type" "RRE,RXY")
4618 (set_attr "type" "idiv")])
4620 (define_expand "udivsi3"
4621 [(set (match_operand:SI 0 "register_operand" "=d")
4622 (udiv:SI (match_operand:SI 1 "general_operand" "")
4623 (match_operand:SI 2 "general_operand" "")))
4624 (clobber (match_dup 3))]
4625 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4627 rtx insn, udiv_equal, umod_equal, equal;
4629 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4630 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4631 equal = gen_rtx_IOR (DImode,
4632 gen_rtx_ASHIFT (DImode,
4633 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4635 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4637 operands[3] = gen_reg_rtx (DImode);
4639 if (CONSTANT_P (operands[2]))
4641 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4643 rtx label1 = gen_label_rtx ();
4645 operands[1] = make_safe_from (operands[1], operands[0]);
4646 emit_move_insn (operands[0], const0_rtx);
4647 emit_insn (gen_cmpsi (operands[1], operands[2]));
4648 emit_jump_insn (gen_bltu (label1));
4649 emit_move_insn (operands[0], const1_rtx);
4650 emit_label (label1);
4654 operands[2] = force_reg (SImode, operands[2]);
4655 operands[2] = make_safe_from (operands[2], operands[0]);
4657 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4658 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4661 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4663 insn = emit_move_insn (operands[0],
4664 gen_lowpart (SImode, operands[3]));
4666 gen_rtx_EXPR_LIST (REG_EQUAL,
4667 udiv_equal, REG_NOTES (insn));
4672 rtx label1 = gen_label_rtx ();
4673 rtx label2 = gen_label_rtx ();
4674 rtx label3 = gen_label_rtx ();
4676 operands[1] = force_reg (SImode, operands[1]);
4677 operands[1] = make_safe_from (operands[1], operands[0]);
4678 operands[2] = force_reg (SImode, operands[2]);
4679 operands[2] = make_safe_from (operands[2], operands[0]);
4681 emit_move_insn (operands[0], const0_rtx);
4682 emit_insn (gen_cmpsi (operands[2], operands[1]));
4683 emit_jump_insn (gen_bgtu (label3));
4684 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4685 emit_jump_insn (gen_blt (label2));
4686 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4687 emit_jump_insn (gen_beq (label1));
4688 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4689 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4692 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4694 insn = emit_move_insn (operands[0],
4695 gen_lowpart (SImode, operands[3]));
4697 gen_rtx_EXPR_LIST (REG_EQUAL,
4698 udiv_equal, REG_NOTES (insn));
4700 emit_label (label1);
4701 emit_move_insn (operands[0], operands[1]);
4703 emit_label (label2);
4704 emit_move_insn (operands[0], const1_rtx);
4705 emit_label (label3);
4707 emit_move_insn (operands[0], operands[0]);
4711 (define_expand "umodsi3"
4712 [(set (match_operand:SI 0 "register_operand" "=d")
4713 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4714 (match_operand:SI 2 "nonimmediate_operand" "")))
4715 (clobber (match_dup 3))]
4716 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4718 rtx insn, udiv_equal, umod_equal, equal;
4720 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4721 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4722 equal = gen_rtx_IOR (DImode,
4723 gen_rtx_ASHIFT (DImode,
4724 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4726 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4728 operands[3] = gen_reg_rtx (DImode);
4730 if (CONSTANT_P (operands[2]))
4732 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4734 rtx label1 = gen_label_rtx ();
4736 operands[1] = make_safe_from (operands[1], operands[0]);
4737 emit_move_insn (operands[0], operands[1]);
4738 emit_insn (gen_cmpsi (operands[0], operands[2]));
4739 emit_jump_insn (gen_bltu (label1));
4740 emit_insn (gen_abssi2 (operands[0], operands[2]));
4741 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4742 emit_label (label1);
4746 operands[2] = force_reg (SImode, operands[2]);
4747 operands[2] = make_safe_from (operands[2], operands[0]);
4749 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4750 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4753 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4755 insn = emit_move_insn (operands[0],
4756 gen_highpart (SImode, operands[3]));
4758 gen_rtx_EXPR_LIST (REG_EQUAL,
4759 umod_equal, REG_NOTES (insn));
4764 rtx label1 = gen_label_rtx ();
4765 rtx label2 = gen_label_rtx ();
4766 rtx label3 = gen_label_rtx ();
4768 operands[1] = force_reg (SImode, operands[1]);
4769 operands[1] = make_safe_from (operands[1], operands[0]);
4770 operands[2] = force_reg (SImode, operands[2]);
4771 operands[2] = make_safe_from (operands[2], operands[0]);
4773 emit_move_insn(operands[0], operands[1]);
4774 emit_insn (gen_cmpsi (operands[2], operands[1]));
4775 emit_jump_insn (gen_bgtu (label3));
4776 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4777 emit_jump_insn (gen_blt (label2));
4778 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4779 emit_jump_insn (gen_beq (label1));
4780 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4781 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4784 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4786 insn = emit_move_insn (operands[0],
4787 gen_highpart (SImode, operands[3]));
4789 gen_rtx_EXPR_LIST (REG_EQUAL,
4790 umod_equal, REG_NOTES (insn));
4792 emit_label (label1);
4793 emit_move_insn (operands[0], const0_rtx);
4795 emit_label (label2);
4796 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4797 emit_label (label3);
4803 ; div(df|sf)3 instruction pattern(s).
4806 (define_expand "div<mode>3"
4807 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4808 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4809 (match_operand:FPR 2 "general_operand" "f,R")))]
4813 (define_insn "*div<mode>3"
4814 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4815 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4816 (match_operand:FPR 2 "general_operand" "f,R")))]
4817 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4821 [(set_attr "op_type" "RRE,RXE")
4822 (set_attr "type" "fdiv<mode>")])
4824 (define_insn "*div<mode>3_ibm"
4825 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4826 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4827 (match_operand:FPR 2 "general_operand" "f,R")))]
4828 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4832 [(set_attr "op_type" "RR,RX")
4833 (set_attr "type" "fdiv<mode>")])
4837 ;;- And instructions.
4840 (define_expand "and<mode>3"
4841 [(set (match_operand:INT 0 "nonimmediate_operand" "")
4842 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
4843 (match_operand:INT 2 "general_operand" "")))
4844 (clobber (reg:CC CC_REGNUM))]
4846 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
4849 ; anddi3 instruction pattern(s).
4852 (define_insn "*anddi3_cc"
4853 [(set (reg CC_REGNUM)
4854 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4855 (match_operand:DI 2 "general_operand" "d,m"))
4857 (set (match_operand:DI 0 "register_operand" "=d,d")
4858 (and:DI (match_dup 1) (match_dup 2)))]
4859 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4863 [(set_attr "op_type" "RRE,RXY")])
4865 (define_insn "*anddi3_cconly"
4866 [(set (reg CC_REGNUM)
4867 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4868 (match_operand:DI 2 "general_operand" "d,m"))
4870 (clobber (match_scratch:DI 0 "=d,d"))]
4871 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
4872 /* Do not steal TM patterns. */
4873 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
4877 [(set_attr "op_type" "RRE,RXY")])
4879 (define_insn "*anddi3_extimm"
4880 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
4881 (and:DI (match_operand:DI 1 "nonimmediate_operand"
4882 "%d,o,0,0,0,0,0,0,0,0,0,0")
4883 (match_operand:DI 2 "general_operand"
4884 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q")))
4885 (clobber (reg:CC CC_REGNUM))]
4886 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
4900 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
4902 (define_insn "*anddi3"
4903 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
4904 (and:DI (match_operand:DI 1 "nonimmediate_operand"
4905 "%d,o,0,0,0,0,0,0,0,0")
4906 (match_operand:DI 2 "general_operand"
4907 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
4908 (clobber (reg:CC CC_REGNUM))]
4909 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
4921 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
4924 [(set (match_operand:DI 0 "s_operand" "")
4925 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
4926 (clobber (reg:CC CC_REGNUM))]
4929 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
4930 (clobber (reg:CC CC_REGNUM))])]
4931 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
4935 ; andsi3 instruction pattern(s).
4938 (define_insn "*andsi3_cc"
4939 [(set (reg CC_REGNUM)
4940 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4941 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
4943 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4944 (and:SI (match_dup 1) (match_dup 2)))]
4945 "s390_match_ccmode(insn, CCTmode)"
4951 [(set_attr "op_type" "RIL,RR,RX,RXY")])
4953 (define_insn "*andsi3_cconly"
4954 [(set (reg CC_REGNUM)
4955 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4956 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
4958 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
4959 "s390_match_ccmode(insn, CCTmode)
4960 /* Do not steal TM patterns. */
4961 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
4967 [(set_attr "op_type" "RIL,RR,RX,RXY")])
4969 (define_insn "*andsi3_zarch"
4970 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
4971 (and:SI (match_operand:SI 1 "nonimmediate_operand"
4972 "%d,o,0,0,0,0,0,0,0,0")
4973 (match_operand:SI 2 "general_operand"
4974 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
4975 (clobber (reg:CC CC_REGNUM))]
4976 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
4988 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")])
4990 (define_insn "*andsi3_esa"
4991 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
4992 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4993 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
4994 (clobber (reg:CC CC_REGNUM))]
4995 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5001 [(set_attr "op_type" "RR,RX,SI,SS")])
5004 [(set (match_operand:SI 0 "s_operand" "")
5005 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5006 (clobber (reg:CC CC_REGNUM))]
5009 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5010 (clobber (reg:CC CC_REGNUM))])]
5011 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5014 ; andhi3 instruction pattern(s).
5017 (define_insn "*andhi3_zarch"
5018 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5019 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5020 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5021 (clobber (reg:CC CC_REGNUM))]
5022 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5028 [(set_attr "op_type" "RR,RI,SI,SS")])
5030 (define_insn "*andhi3_esa"
5031 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5032 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5033 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5034 (clobber (reg:CC CC_REGNUM))]
5035 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5040 [(set_attr "op_type" "RR,SI,SS")])
5043 [(set (match_operand:HI 0 "s_operand" "")
5044 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5045 (clobber (reg:CC CC_REGNUM))]
5048 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5049 (clobber (reg:CC CC_REGNUM))])]
5050 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5053 ; andqi3 instruction pattern(s).
5056 (define_insn "*andqi3_zarch"
5057 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5058 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5059 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5060 (clobber (reg:CC CC_REGNUM))]
5061 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5068 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5070 (define_insn "*andqi3_esa"
5071 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5072 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5073 (match_operand:QI 2 "general_operand" "d,n,Q")))
5074 (clobber (reg:CC CC_REGNUM))]
5075 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5080 [(set_attr "op_type" "RR,SI,SS")])
5083 ; Block and (NC) patterns.
5087 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5088 (and:BLK (match_dup 0)
5089 (match_operand:BLK 1 "memory_operand" "Q")))
5090 (use (match_operand 2 "const_int_operand" "n"))
5091 (clobber (reg:CC CC_REGNUM))]
5092 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5093 "nc\t%O0(%2,%R0),%S1"
5094 [(set_attr "op_type" "SS")])
5097 [(set (match_operand 0 "memory_operand" "")
5099 (match_operand 1 "memory_operand" "")))
5100 (clobber (reg:CC CC_REGNUM))]
5102 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5103 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5105 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
5107 (clobber (reg:CC CC_REGNUM))])]
5109 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5110 operands[0] = adjust_address (operands[0], BLKmode, 0);
5111 operands[1] = adjust_address (operands[1], BLKmode, 0);
5116 [(set (match_operand:BLK 0 "memory_operand" "")
5117 (and:BLK (match_dup 0)
5118 (match_operand:BLK 1 "memory_operand" "")))
5119 (use (match_operand 2 "const_int_operand" ""))
5120 (clobber (reg:CC CC_REGNUM))])
5122 [(set (match_operand:BLK 3 "memory_operand" "")
5123 (and:BLK (match_dup 3)
5124 (match_operand:BLK 4 "memory_operand" "")))
5125 (use (match_operand 5 "const_int_operand" ""))
5126 (clobber (reg:CC CC_REGNUM))])]
5127 "s390_offset_p (operands[0], operands[3], operands[2])
5128 && s390_offset_p (operands[1], operands[4], operands[2])
5129 && !s390_overlap_p (operands[0], operands[1],
5130 INTVAL (operands[2]) + INTVAL (operands[5]))
5131 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5133 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
5135 (clobber (reg:CC CC_REGNUM))])]
5136 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5137 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5138 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5142 ;;- Bit set (inclusive or) instructions.
5145 (define_expand "ior<mode>3"
5146 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5147 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
5148 (match_operand:INT 2 "general_operand" "")))
5149 (clobber (reg:CC CC_REGNUM))]
5151 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
5154 ; iordi3 instruction pattern(s).
5157 (define_insn "*iordi3_cc"
5158 [(set (reg CC_REGNUM)
5159 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5160 (match_operand:DI 2 "general_operand" "d,m"))
5162 (set (match_operand:DI 0 "register_operand" "=d,d")
5163 (ior:DI (match_dup 1) (match_dup 2)))]
5164 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5168 [(set_attr "op_type" "RRE,RXY")])
5170 (define_insn "*iordi3_cconly"
5171 [(set (reg CC_REGNUM)
5172 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5173 (match_operand:DI 2 "general_operand" "d,m"))
5175 (clobber (match_scratch:DI 0 "=d,d"))]
5176 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5180 [(set_attr "op_type" "RRE,RXY")])
5182 (define_insn "*iordi3_extimm"
5183 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5184 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
5185 (match_operand:DI 2 "general_operand"
5186 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q")))
5187 (clobber (reg:CC CC_REGNUM))]
5188 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5200 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5202 (define_insn "*iordi3"
5203 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5204 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5205 (match_operand:DI 2 "general_operand"
5206 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5207 (clobber (reg:CC CC_REGNUM))]
5208 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5218 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5221 [(set (match_operand:DI 0 "s_operand" "")
5222 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5223 (clobber (reg:CC CC_REGNUM))]
5226 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5227 (clobber (reg:CC CC_REGNUM))])]
5228 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5231 ; iorsi3 instruction pattern(s).
5234 (define_insn "*iorsi3_cc"
5235 [(set (reg CC_REGNUM)
5236 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5237 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5239 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5240 (ior:SI (match_dup 1) (match_dup 2)))]
5241 "s390_match_ccmode(insn, CCTmode)"
5247 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5249 (define_insn "*iorsi3_cconly"
5250 [(set (reg CC_REGNUM)
5251 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5252 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5254 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5255 "s390_match_ccmode(insn, CCTmode)"
5261 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5263 (define_insn "*iorsi3_zarch"
5264 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5265 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5266 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
5267 (clobber (reg:CC CC_REGNUM))]
5268 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5278 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")])
5280 (define_insn "*iorsi3_esa"
5281 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5282 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5283 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5284 (clobber (reg:CC CC_REGNUM))]
5285 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5291 [(set_attr "op_type" "RR,RX,SI,SS")])
5294 [(set (match_operand:SI 0 "s_operand" "")
5295 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5296 (clobber (reg:CC CC_REGNUM))]
5299 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5300 (clobber (reg:CC CC_REGNUM))])]
5301 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5304 ; iorhi3 instruction pattern(s).
5307 (define_insn "*iorhi3_zarch"
5308 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5309 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5310 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5311 (clobber (reg:CC CC_REGNUM))]
5312 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5318 [(set_attr "op_type" "RR,RI,SI,SS")])
5320 (define_insn "*iorhi3_esa"
5321 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5322 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5323 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5324 (clobber (reg:CC CC_REGNUM))]
5325 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5330 [(set_attr "op_type" "RR,SI,SS")])
5333 [(set (match_operand:HI 0 "s_operand" "")
5334 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5335 (clobber (reg:CC CC_REGNUM))]
5338 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5339 (clobber (reg:CC CC_REGNUM))])]
5340 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5343 ; iorqi3 instruction pattern(s).
5346 (define_insn "*iorqi3_zarch"
5347 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5348 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5349 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5350 (clobber (reg:CC CC_REGNUM))]
5351 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5358 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5360 (define_insn "*iorqi3_esa"
5361 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5362 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5363 (match_operand:QI 2 "general_operand" "d,n,Q")))
5364 (clobber (reg:CC CC_REGNUM))]
5365 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5370 [(set_attr "op_type" "RR,SI,SS")])
5373 ; Block inclusive or (OC) patterns.
5377 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5378 (ior:BLK (match_dup 0)
5379 (match_operand:BLK 1 "memory_operand" "Q")))
5380 (use (match_operand 2 "const_int_operand" "n"))
5381 (clobber (reg:CC CC_REGNUM))]
5382 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5383 "oc\t%O0(%2,%R0),%S1"
5384 [(set_attr "op_type" "SS")])
5387 [(set (match_operand 0 "memory_operand" "")
5389 (match_operand 1 "memory_operand" "")))
5390 (clobber (reg:CC CC_REGNUM))]
5392 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5393 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5395 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5397 (clobber (reg:CC CC_REGNUM))])]
5399 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5400 operands[0] = adjust_address (operands[0], BLKmode, 0);
5401 operands[1] = adjust_address (operands[1], BLKmode, 0);
5406 [(set (match_operand:BLK 0 "memory_operand" "")
5407 (ior:BLK (match_dup 0)
5408 (match_operand:BLK 1 "memory_operand" "")))
5409 (use (match_operand 2 "const_int_operand" ""))
5410 (clobber (reg:CC CC_REGNUM))])
5412 [(set (match_operand:BLK 3 "memory_operand" "")
5413 (ior:BLK (match_dup 3)
5414 (match_operand:BLK 4 "memory_operand" "")))
5415 (use (match_operand 5 "const_int_operand" ""))
5416 (clobber (reg:CC CC_REGNUM))])]
5417 "s390_offset_p (operands[0], operands[3], operands[2])
5418 && s390_offset_p (operands[1], operands[4], operands[2])
5419 && !s390_overlap_p (operands[0], operands[1],
5420 INTVAL (operands[2]) + INTVAL (operands[5]))
5421 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5423 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5425 (clobber (reg:CC CC_REGNUM))])]
5426 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5427 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5428 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5432 ;;- Xor instructions.
5435 (define_expand "xor<mode>3"
5436 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5437 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5438 (match_operand:INT 2 "general_operand" "")))
5439 (clobber (reg:CC CC_REGNUM))]
5441 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5444 ; xordi3 instruction pattern(s).
5447 (define_insn "*xordi3_cc"
5448 [(set (reg CC_REGNUM)
5449 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5450 (match_operand:DI 2 "general_operand" "d,m"))
5452 (set (match_operand:DI 0 "register_operand" "=d,d")
5453 (xor:DI (match_dup 1) (match_dup 2)))]
5454 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5458 [(set_attr "op_type" "RRE,RXY")])
5460 (define_insn "*xordi3_cconly"
5461 [(set (reg CC_REGNUM)
5462 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5463 (match_operand:DI 2 "general_operand" "d,m"))
5465 (clobber (match_scratch:DI 0 "=d,d"))]
5466 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5470 [(set_attr "op_type" "RRE,RXY")])
5472 (define_insn "*xordi3_extimm"
5473 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5474 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5475 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q")))
5476 (clobber (reg:CC CC_REGNUM))]
5477 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5485 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")])
5487 (define_insn "*xordi3"
5488 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5489 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5490 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5491 (clobber (reg:CC CC_REGNUM))]
5492 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5498 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5501 [(set (match_operand:DI 0 "s_operand" "")
5502 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5503 (clobber (reg:CC CC_REGNUM))]
5506 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5507 (clobber (reg:CC CC_REGNUM))])]
5508 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5511 ; xorsi3 instruction pattern(s).
5514 (define_insn "*xorsi3_cc"
5515 [(set (reg CC_REGNUM)
5516 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5517 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5519 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5520 (xor:SI (match_dup 1) (match_dup 2)))]
5521 "s390_match_ccmode(insn, CCTmode)"
5527 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5529 (define_insn "*xorsi3_cconly"
5530 [(set (reg CC_REGNUM)
5531 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5532 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5534 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5535 "s390_match_ccmode(insn, CCTmode)"
5541 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5543 (define_insn "*xorsi3"
5544 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5545 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5546 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
5547 (clobber (reg:CC CC_REGNUM))]
5548 "s390_logical_operator_ok_p (operands)"
5556 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")])
5559 [(set (match_operand:SI 0 "s_operand" "")
5560 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5561 (clobber (reg:CC CC_REGNUM))]
5564 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5565 (clobber (reg:CC CC_REGNUM))])]
5566 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5569 ; xorhi3 instruction pattern(s).
5572 (define_insn "*xorhi3"
5573 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5574 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5575 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
5576 (clobber (reg:CC CC_REGNUM))]
5577 "s390_logical_operator_ok_p (operands)"
5583 [(set_attr "op_type" "RIL,RR,SI,SS")])
5586 [(set (match_operand:HI 0 "s_operand" "")
5587 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5588 (clobber (reg:CC CC_REGNUM))]
5591 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5592 (clobber (reg:CC CC_REGNUM))])]
5593 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5596 ; xorqi3 instruction pattern(s).
5599 (define_insn "*xorqi3"
5600 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5601 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5602 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
5603 (clobber (reg:CC CC_REGNUM))]
5604 "s390_logical_operator_ok_p (operands)"
5611 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")])
5614 ; Block exclusive or (XC) patterns.
5618 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5619 (xor:BLK (match_dup 0)
5620 (match_operand:BLK 1 "memory_operand" "Q")))
5621 (use (match_operand 2 "const_int_operand" "n"))
5622 (clobber (reg:CC CC_REGNUM))]
5623 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5624 "xc\t%O0(%2,%R0),%S1"
5625 [(set_attr "op_type" "SS")])
5628 [(set (match_operand 0 "memory_operand" "")
5630 (match_operand 1 "memory_operand" "")))
5631 (clobber (reg:CC CC_REGNUM))]
5633 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5634 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5636 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5638 (clobber (reg:CC CC_REGNUM))])]
5640 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5641 operands[0] = adjust_address (operands[0], BLKmode, 0);
5642 operands[1] = adjust_address (operands[1], BLKmode, 0);
5647 [(set (match_operand:BLK 0 "memory_operand" "")
5648 (xor:BLK (match_dup 0)
5649 (match_operand:BLK 1 "memory_operand" "")))
5650 (use (match_operand 2 "const_int_operand" ""))
5651 (clobber (reg:CC CC_REGNUM))])
5653 [(set (match_operand:BLK 3 "memory_operand" "")
5654 (xor:BLK (match_dup 3)
5655 (match_operand:BLK 4 "memory_operand" "")))
5656 (use (match_operand 5 "const_int_operand" ""))
5657 (clobber (reg:CC CC_REGNUM))])]
5658 "s390_offset_p (operands[0], operands[3], operands[2])
5659 && s390_offset_p (operands[1], operands[4], operands[2])
5660 && !s390_overlap_p (operands[0], operands[1],
5661 INTVAL (operands[2]) + INTVAL (operands[5]))
5662 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5664 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5666 (clobber (reg:CC CC_REGNUM))])]
5667 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5668 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5669 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5672 ; Block xor (XC) patterns with src == dest.
5675 (define_insn "*xc_zero"
5676 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5678 (use (match_operand 1 "const_int_operand" "n"))
5679 (clobber (reg:CC CC_REGNUM))]
5680 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5681 "xc\t%O0(%1,%R0),%S0"
5682 [(set_attr "op_type" "SS")])
5686 [(set (match_operand:BLK 0 "memory_operand" "")
5688 (use (match_operand 1 "const_int_operand" ""))
5689 (clobber (reg:CC CC_REGNUM))])
5691 [(set (match_operand:BLK 2 "memory_operand" "")
5693 (use (match_operand 3 "const_int_operand" ""))
5694 (clobber (reg:CC CC_REGNUM))])]
5695 "s390_offset_p (operands[0], operands[2], operands[1])
5696 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5698 [(set (match_dup 4) (const_int 0))
5700 (clobber (reg:CC CC_REGNUM))])]
5701 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5702 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5706 ;;- Negate instructions.
5710 ; neg(di|si)2 instruction pattern(s).
5713 (define_expand "neg<mode>2"
5715 [(set (match_operand:DSI 0 "register_operand" "=d")
5716 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5717 (clobber (reg:CC CC_REGNUM))])]
5721 (define_insn "*negdi2_sign_cc"
5722 [(set (reg CC_REGNUM)
5723 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5724 (match_operand:SI 1 "register_operand" "d") 0)
5725 (const_int 32)) (const_int 32)))
5727 (set (match_operand:DI 0 "register_operand" "=d")
5728 (neg:DI (sign_extend:DI (match_dup 1))))]
5729 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5731 [(set_attr "op_type" "RRE")])
5733 (define_insn "*negdi2_sign"
5734 [(set (match_operand:DI 0 "register_operand" "=d")
5735 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5736 (clobber (reg:CC CC_REGNUM))]
5739 [(set_attr "op_type" "RRE")])
5741 (define_insn "*neg<mode>2_cc"
5742 [(set (reg CC_REGNUM)
5743 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5745 (set (match_operand:GPR 0 "register_operand" "=d")
5746 (neg:GPR (match_dup 1)))]
5747 "s390_match_ccmode (insn, CCAmode)"
5749 [(set_attr "op_type" "RR<E>")])
5751 (define_insn "*neg<mode>2_cconly"
5752 [(set (reg CC_REGNUM)
5753 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5755 (clobber (match_scratch:GPR 0 "=d"))]
5756 "s390_match_ccmode (insn, CCAmode)"
5758 [(set_attr "op_type" "RR<E>")])
5760 (define_insn "*neg<mode>2"
5761 [(set (match_operand:GPR 0 "register_operand" "=d")
5762 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5763 (clobber (reg:CC CC_REGNUM))]
5766 [(set_attr "op_type" "RR<E>")])
5768 (define_insn_and_split "*negdi2_31"
5769 [(set (match_operand:DI 0 "register_operand" "=d")
5770 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5771 (clobber (reg:CC CC_REGNUM))]
5774 "&& reload_completed"
5776 [(set (match_dup 2) (neg:SI (match_dup 3)))
5777 (clobber (reg:CC CC_REGNUM))])
5779 [(set (reg:CCAP CC_REGNUM)
5780 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5781 (set (match_dup 4) (neg:SI (match_dup 5)))])
5783 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
5785 (label_ref (match_dup 6))))
5787 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5788 (clobber (reg:CC CC_REGNUM))])
5790 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5791 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5792 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5793 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5794 operands[6] = gen_label_rtx ();")
5797 ; neg(df|sf)2 instruction pattern(s).
5800 (define_expand "neg<mode>2"
5802 [(set (match_operand:FPR 0 "register_operand" "=f")
5803 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5804 (clobber (reg:CC CC_REGNUM))])]
5808 (define_insn "*neg<mode>2_cc"
5809 [(set (reg CC_REGNUM)
5810 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5811 (match_operand:FPR 2 "const0_operand" "")))
5812 (set (match_operand:FPR 0 "register_operand" "=f")
5813 (neg:FPR (match_dup 1)))]
5814 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5816 [(set_attr "op_type" "RRE")
5817 (set_attr "type" "fsimp<mode>")])
5819 (define_insn "*neg<mode>2_cconly"
5820 [(set (reg CC_REGNUM)
5821 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5822 (match_operand:FPR 2 "const0_operand" "")))
5823 (clobber (match_scratch:FPR 0 "=f"))]
5824 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5826 [(set_attr "op_type" "RRE")
5827 (set_attr "type" "fsimp<mode>")])
5829 (define_insn "*neg<mode>2"
5830 [(set (match_operand:FPR 0 "register_operand" "=f")
5831 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5832 (clobber (reg:CC CC_REGNUM))]
5833 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5835 [(set_attr "op_type" "RRE")
5836 (set_attr "type" "fsimp<mode>")])
5838 (define_insn "*neg<mode>2_ibm"
5839 [(set (match_operand:FPR 0 "register_operand" "=f")
5840 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5841 (clobber (reg:CC CC_REGNUM))]
5842 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5844 [(set_attr "op_type" "RR")
5845 (set_attr "type" "fsimp<mode>")])
5849 ;;- Absolute value instructions.
5853 ; abs(di|si)2 instruction pattern(s).
5856 (define_insn "*absdi2_sign_cc"
5857 [(set (reg CC_REGNUM)
5858 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5859 (match_operand:SI 1 "register_operand" "d") 0)
5860 (const_int 32)) (const_int 32)))
5862 (set (match_operand:DI 0 "register_operand" "=d")
5863 (abs:DI (sign_extend:DI (match_dup 1))))]
5864 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5866 [(set_attr "op_type" "RRE")])
5868 (define_insn "*absdi2_sign"
5869 [(set (match_operand:DI 0 "register_operand" "=d")
5870 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5871 (clobber (reg:CC CC_REGNUM))]
5874 [(set_attr "op_type" "RRE")])
5876 (define_insn "*abs<mode>2_cc"
5877 [(set (reg CC_REGNUM)
5878 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
5880 (set (match_operand:GPR 0 "register_operand" "=d")
5881 (abs:GPR (match_dup 1)))]
5882 "s390_match_ccmode (insn, CCAmode)"
5884 [(set_attr "op_type" "RR<E>")])
5886 (define_insn "*abs<mode>2_cconly"
5887 [(set (reg CC_REGNUM)
5888 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
5890 (clobber (match_scratch:GPR 0 "=d"))]
5891 "s390_match_ccmode (insn, CCAmode)"
5893 [(set_attr "op_type" "RR<E>")])
5895 (define_insn "abs<mode>2"
5896 [(set (match_operand:GPR 0 "register_operand" "=d")
5897 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5898 (clobber (reg:CC CC_REGNUM))]
5901 [(set_attr "op_type" "RR<E>")])
5904 ; abs(df|sf)2 instruction pattern(s).
5907 (define_expand "abs<mode>2"
5909 [(set (match_operand:FPR 0 "register_operand" "=f")
5910 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5911 (clobber (reg:CC CC_REGNUM))])]
5915 (define_insn "*abs<mode>2_cc"
5916 [(set (reg CC_REGNUM)
5917 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5918 (match_operand:FPR 2 "const0_operand" "")))
5919 (set (match_operand:FPR 0 "register_operand" "=f")
5920 (abs:FPR (match_dup 1)))]
5921 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5923 [(set_attr "op_type" "RRE")
5924 (set_attr "type" "fsimp<mode>")])
5926 (define_insn "*abs<mode>2_cconly"
5927 [(set (reg CC_REGNUM)
5928 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
5929 (match_operand:FPR 2 "const0_operand" "")))
5930 (clobber (match_scratch:FPR 0 "=f"))]
5931 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5933 [(set_attr "op_type" "RRE")
5934 (set_attr "type" "fsimp<mode>")])
5936 (define_insn "*abs<mode>2"
5937 [(set (match_operand:FPR 0 "register_operand" "=f")
5938 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5939 (clobber (reg:CC CC_REGNUM))]
5940 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5942 [(set_attr "op_type" "RRE")
5943 (set_attr "type" "fsimp<mode>")])
5945 (define_insn "*abs<mode>2_ibm"
5946 [(set (match_operand:FPR 0 "register_operand" "=f")
5947 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
5948 (clobber (reg:CC CC_REGNUM))]
5949 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5951 [(set_attr "op_type" "RR")
5952 (set_attr "type" "fsimp<mode>")])
5955 ;;- Negated absolute value instructions
5962 (define_insn "*negabsdi2_sign_cc"
5963 [(set (reg CC_REGNUM)
5964 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
5965 (match_operand:SI 1 "register_operand" "d") 0)
5966 (const_int 32)) (const_int 32))))
5968 (set (match_operand:DI 0 "register_operand" "=d")
5969 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
5970 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5972 [(set_attr "op_type" "RRE")])
5974 (define_insn "*negabsdi2_sign"
5975 [(set (match_operand:DI 0 "register_operand" "=d")
5976 (neg:DI (abs:DI (sign_extend:DI
5977 (match_operand:SI 1 "register_operand" "d")))))
5978 (clobber (reg:CC CC_REGNUM))]
5981 [(set_attr "op_type" "RRE")])
5983 (define_insn "*negabs<mode>2_cc"
5984 [(set (reg CC_REGNUM)
5985 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5987 (set (match_operand:GPR 0 "register_operand" "=d")
5988 (neg:GPR (abs:GPR (match_dup 1))))]
5989 "s390_match_ccmode (insn, CCAmode)"
5991 [(set_attr "op_type" "RR<E>")])
5993 (define_insn "*negabs<mode>2_cconly"
5994 [(set (reg CC_REGNUM)
5995 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
5997 (clobber (match_scratch:GPR 0 "=d"))]
5998 "s390_match_ccmode (insn, CCAmode)"
6000 [(set_attr "op_type" "RR<E>")])
6002 (define_insn "*negabs<mode>2"
6003 [(set (match_operand:GPR 0 "register_operand" "=d")
6004 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
6005 (clobber (reg:CC CC_REGNUM))]
6008 [(set_attr "op_type" "RR<E>")])
6014 (define_insn "*negabs<mode>2_cc"
6015 [(set (reg CC_REGNUM)
6016 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6017 (match_operand:FPR 2 "const0_operand" "")))
6018 (set (match_operand:FPR 0 "register_operand" "=f")
6019 (neg:FPR (abs:FPR (match_dup 1))))]
6020 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6022 [(set_attr "op_type" "RRE")
6023 (set_attr "type" "fsimp<mode>")])
6025 (define_insn "*negabs<mode>2_cconly"
6026 [(set (reg CC_REGNUM)
6027 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6028 (match_operand:FPR 2 "const0_operand" "")))
6029 (clobber (match_scratch:FPR 0 "=f"))]
6030 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6032 [(set_attr "op_type" "RRE")
6033 (set_attr "type" "fsimp<mode>")])
6035 (define_insn "*negabs<mode>2"
6036 [(set (match_operand:FPR 0 "register_operand" "=f")
6037 (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
6038 (clobber (reg:CC CC_REGNUM))]
6039 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6041 [(set_attr "op_type" "RRE")
6042 (set_attr "type" "fsimp<mode>")])
6045 ;;- Square root instructions.
6049 ; sqrt(df|sf)2 instruction pattern(s).
6052 (define_insn "sqrt<mode>2"
6053 [(set (match_operand:FPR 0 "register_operand" "=f,f")
6054 (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
6055 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6059 [(set_attr "op_type" "RRE,RXE")
6060 (set_attr "type" "fsqrt<mode>")])
6064 ;;- One complement instructions.
6068 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
6071 (define_expand "one_cmpl<mode>2"
6073 [(set (match_operand:INT 0 "register_operand" "")
6074 (xor:INT (match_operand:INT 1 "register_operand" "")
6076 (clobber (reg:CC CC_REGNUM))])]
6082 ;; Find leftmost bit instructions.
6085 (define_expand "clzdi2"
6086 [(set (match_operand:DI 0 "register_operand" "=d")
6087 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
6088 "TARGET_EXTIMM && TARGET_64BIT"
6090 rtx insn, clz_equal;
6091 rtx wide_reg = gen_reg_rtx (TImode);
6092 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
6094 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
6096 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
6098 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
6100 gen_rtx_EXPR_LIST (REG_EQUAL, clz_equal, REG_NOTES (insn));
6105 (define_insn "clztidi2"
6106 [(set (match_operand:TI 0 "register_operand" "=d")
6110 (xor:DI (match_operand:DI 1 "register_operand" "d")
6111 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
6112 (subreg:SI (clz:DI (match_dup 1)) 4))))
6115 (zero_extend:TI (clz:DI (match_dup 1)))))
6116 (clobber (reg:CC CC_REGNUM))]
6117 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
6118 == (unsigned HOST_WIDE_INT) 1 << 63
6119 && TARGET_EXTIMM && TARGET_64BIT"
6121 [(set_attr "op_type" "RRE")])
6125 ;;- Rotate instructions.
6129 ; rotl(di|si)3 instruction pattern(s).
6132 (define_insn "rotl<mode>3"
6133 [(set (match_operand:GPR 0 "register_operand" "=d")
6134 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6135 (match_operand:SI 2 "shift_count_operand" "Y")))]
6138 [(set_attr "op_type" "RSE")
6139 (set_attr "atype" "reg")])
6143 ;;- Shift instructions.
6147 ; (ashl|lshr)di3 instruction pattern(s).
6150 (define_expand "<shift>di3"
6151 [(set (match_operand:DI 0 "register_operand" "")
6152 (SHIFT:DI (match_operand:DI 1 "register_operand" "")
6153 (match_operand:SI 2 "shift_count_operand" "")))]
6157 (define_insn "*<shift>di3_31"
6158 [(set (match_operand:DI 0 "register_operand" "=d")
6159 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6160 (match_operand:SI 2 "shift_count_operand" "Y")))]
6163 [(set_attr "op_type" "RS")
6164 (set_attr "atype" "reg")])
6166 (define_insn "*<shift>di3_64"
6167 [(set (match_operand:DI 0 "register_operand" "=d")
6168 (SHIFT:DI (match_operand:DI 1 "register_operand" "d")
6169 (match_operand:SI 2 "shift_count_operand" "Y")))]
6171 "s<lr>lg\t%0,%1,%Y2"
6172 [(set_attr "op_type" "RSE")
6173 (set_attr "atype" "reg")])
6176 ; ashrdi3 instruction pattern(s).
6179 (define_expand "ashrdi3"
6181 [(set (match_operand:DI 0 "register_operand" "")
6182 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6183 (match_operand:SI 2 "shift_count_operand" "")))
6184 (clobber (reg:CC CC_REGNUM))])]
6188 (define_insn "*ashrdi3_cc_31"
6189 [(set (reg CC_REGNUM)
6190 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6191 (match_operand:SI 2 "shift_count_operand" "Y"))
6193 (set (match_operand:DI 0 "register_operand" "=d")
6194 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6195 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6197 [(set_attr "op_type" "RS")
6198 (set_attr "atype" "reg")])
6200 (define_insn "*ashrdi3_cconly_31"
6201 [(set (reg CC_REGNUM)
6202 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6203 (match_operand:SI 2 "shift_count_operand" "Y"))
6205 (clobber (match_scratch:DI 0 "=d"))]
6206 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6208 [(set_attr "op_type" "RS")
6209 (set_attr "atype" "reg")])
6211 (define_insn "*ashrdi3_31"
6212 [(set (match_operand:DI 0 "register_operand" "=d")
6213 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6214 (match_operand:SI 2 "shift_count_operand" "Y")))
6215 (clobber (reg:CC CC_REGNUM))]
6218 [(set_attr "op_type" "RS")
6219 (set_attr "atype" "reg")])
6221 (define_insn "*ashrdi3_cc_64"
6222 [(set (reg CC_REGNUM)
6223 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6224 (match_operand:SI 2 "shift_count_operand" "Y"))
6226 (set (match_operand:DI 0 "register_operand" "=d")
6227 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6228 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6230 [(set_attr "op_type" "RSE")
6231 (set_attr "atype" "reg")])
6233 (define_insn "*ashrdi3_cconly_64"
6234 [(set (reg CC_REGNUM)
6235 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6236 (match_operand:SI 2 "shift_count_operand" "Y"))
6238 (clobber (match_scratch:DI 0 "=d"))]
6239 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6241 [(set_attr "op_type" "RSE")
6242 (set_attr "atype" "reg")])
6244 (define_insn "*ashrdi3_64"
6245 [(set (match_operand:DI 0 "register_operand" "=d")
6246 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6247 (match_operand:SI 2 "shift_count_operand" "Y")))
6248 (clobber (reg:CC CC_REGNUM))]
6251 [(set_attr "op_type" "RSE")
6252 (set_attr "atype" "reg")])
6256 ; (ashl|lshr)si3 instruction pattern(s).
6259 (define_insn "<shift>si3"
6260 [(set (match_operand:SI 0 "register_operand" "=d")
6261 (SHIFT:SI (match_operand:SI 1 "register_operand" "0")
6262 (match_operand:SI 2 "shift_count_operand" "Y")))]
6265 [(set_attr "op_type" "RS")
6266 (set_attr "atype" "reg")])
6269 ; ashrsi3 instruction pattern(s).
6272 (define_insn "*ashrsi3_cc"
6273 [(set (reg CC_REGNUM)
6274 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6275 (match_operand:SI 2 "shift_count_operand" "Y"))
6277 (set (match_operand:SI 0 "register_operand" "=d")
6278 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
6279 "s390_match_ccmode(insn, CCSmode)"
6281 [(set_attr "op_type" "RS")
6282 (set_attr "atype" "reg")])
6285 (define_insn "*ashrsi3_cconly"
6286 [(set (reg CC_REGNUM)
6287 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6288 (match_operand:SI 2 "shift_count_operand" "Y"))
6290 (clobber (match_scratch:SI 0 "=d"))]
6291 "s390_match_ccmode(insn, CCSmode)"
6293 [(set_attr "op_type" "RS")
6294 (set_attr "atype" "reg")])
6296 (define_insn "ashrsi3"
6297 [(set (match_operand:SI 0 "register_operand" "=d")
6298 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6299 (match_operand:SI 2 "shift_count_operand" "Y")))
6300 (clobber (reg:CC CC_REGNUM))]
6303 [(set_attr "op_type" "RS")
6304 (set_attr "atype" "reg")])
6308 ;; Branch instruction patterns.
6311 (define_expand "b<code>"
6313 (if_then_else (COMPARE (match_operand 0 "" "")
6318 "s390_emit_jump (operands[0],
6319 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
6323 ;;- Conditional jump instructions.
6326 (define_insn "*cjump_64"
6329 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6330 (label_ref (match_operand 0 "" ""))
6334 if (get_attr_length (insn) == 4)
6337 return "jg%C1\t%l0";
6339 [(set_attr "op_type" "RI")
6340 (set_attr "type" "branch")
6341 (set (attr "length")
6342 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6343 (const_int 4) (const_int 6)))])
6345 (define_insn "*cjump_31"
6348 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6349 (label_ref (match_operand 0 "" ""))
6353 gcc_assert (get_attr_length (insn) == 4);
6356 [(set_attr "op_type" "RI")
6357 (set_attr "type" "branch")
6358 (set (attr "length")
6359 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6360 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6361 (const_int 4) (const_int 6))
6362 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6363 (const_int 4) (const_int 8))))])
6365 (define_insn "*cjump_long"
6368 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6369 (match_operand 0 "address_operand" "U")
6373 if (get_attr_op_type (insn) == OP_TYPE_RR)
6378 [(set (attr "op_type")
6379 (if_then_else (match_operand 0 "register_operand" "")
6380 (const_string "RR") (const_string "RX")))
6381 (set_attr "type" "branch")
6382 (set_attr "atype" "agen")])
6386 ;;- Negated conditional jump instructions.
6389 (define_insn "*icjump_64"
6392 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6394 (label_ref (match_operand 0 "" ""))))]
6397 if (get_attr_length (insn) == 4)
6400 return "jg%D1\t%l0";
6402 [(set_attr "op_type" "RI")
6403 (set_attr "type" "branch")
6404 (set (attr "length")
6405 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6406 (const_int 4) (const_int 6)))])
6408 (define_insn "*icjump_31"
6411 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6413 (label_ref (match_operand 0 "" ""))))]
6416 gcc_assert (get_attr_length (insn) == 4);
6419 [(set_attr "op_type" "RI")
6420 (set_attr "type" "branch")
6421 (set (attr "length")
6422 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6423 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6424 (const_int 4) (const_int 6))
6425 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6426 (const_int 4) (const_int 8))))])
6428 (define_insn "*icjump_long"
6431 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6433 (match_operand 0 "address_operand" "U")))]
6436 if (get_attr_op_type (insn) == OP_TYPE_RR)
6441 [(set (attr "op_type")
6442 (if_then_else (match_operand 0 "register_operand" "")
6443 (const_string "RR") (const_string "RX")))
6444 (set_attr "type" "branch")
6445 (set_attr "atype" "agen")])
6448 ;;- Trap instructions.
6452 [(trap_if (const_int 1) (const_int 0))]
6455 [(set_attr "op_type" "RI")
6456 (set_attr "type" "branch")])
6458 (define_expand "conditional_trap"
6459 [(trap_if (match_operand 0 "comparison_operator" "")
6460 (match_operand 1 "general_operand" ""))]
6463 if (operands[1] != const0_rtx) FAIL;
6464 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6465 s390_compare_op0, s390_compare_op1);
6468 (define_insn "*trap"
6469 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6473 [(set_attr "op_type" "RI")
6474 (set_attr "type" "branch")])
6477 ;;- Loop instructions.
6479 ;; This is all complicated by the fact that since this is a jump insn
6480 ;; we must handle our own output reloads.
6482 (define_expand "doloop_end"
6483 [(use (match_operand 0 "" "")) ; loop pseudo
6484 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6485 (use (match_operand 2 "" "")) ; max iterations
6486 (use (match_operand 3 "" "")) ; loop level
6487 (use (match_operand 4 "" ""))] ; label
6490 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6491 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6492 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6493 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6494 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6495 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6502 (define_insn_and_split "doloop_si64"
6505 (ne (match_operand:SI 1 "register_operand" "d,d")
6507 (label_ref (match_operand 0 "" ""))
6509 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6510 (plus:SI (match_dup 1) (const_int -1)))
6511 (clobber (match_scratch:SI 3 "=X,&1"))
6512 (clobber (reg:CC CC_REGNUM))]
6515 if (which_alternative != 0)
6517 else if (get_attr_length (insn) == 4)
6518 return "brct\t%1,%l0";
6520 return "ahi\t%1,-1\;jgne\t%l0";
6522 "&& reload_completed
6523 && (! REG_P (operands[2])
6524 || ! rtx_equal_p (operands[1], operands[2]))"
6525 [(parallel [(set (reg:CCAN CC_REGNUM)
6526 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6528 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6529 (set (match_dup 2) (match_dup 3))
6530 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6531 (label_ref (match_dup 0))
6534 [(set_attr "op_type" "RI")
6535 (set_attr "type" "branch")
6536 (set (attr "length")
6537 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6538 (const_int 4) (const_int 10)))])
6540 (define_insn_and_split "doloop_si31"
6543 (ne (match_operand:SI 1 "register_operand" "d,d")
6545 (label_ref (match_operand 0 "" ""))
6547 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
6548 (plus:SI (match_dup 1) (const_int -1)))
6549 (clobber (match_scratch:SI 3 "=X,&1"))
6550 (clobber (reg:CC CC_REGNUM))]
6553 if (which_alternative != 0)
6555 else if (get_attr_length (insn) == 4)
6556 return "brct\t%1,%l0";
6560 "&& reload_completed
6561 && (! REG_P (operands[2])
6562 || ! rtx_equal_p (operands[1], operands[2]))"
6563 [(parallel [(set (reg:CCAN CC_REGNUM)
6564 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6566 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6567 (set (match_dup 2) (match_dup 3))
6568 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6569 (label_ref (match_dup 0))
6572 [(set_attr "op_type" "RI")
6573 (set_attr "type" "branch")
6574 (set (attr "length")
6575 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6576 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6577 (const_int 4) (const_int 6))
6578 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6579 (const_int 4) (const_int 8))))])
6581 (define_insn "*doloop_si_long"
6584 (ne (match_operand:SI 1 "register_operand" "d,d")
6586 (match_operand 0 "address_operand" "U,U")
6588 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
6589 (plus:SI (match_dup 1) (const_int -1)))
6590 (clobber (match_scratch:SI 3 "=X,&1"))
6591 (clobber (reg:CC CC_REGNUM))]
6594 if (get_attr_op_type (insn) == OP_TYPE_RR)
6595 return "bctr\t%1,%0";
6597 return "bct\t%1,%a0";
6599 [(set (attr "op_type")
6600 (if_then_else (match_operand 0 "register_operand" "")
6601 (const_string "RR") (const_string "RX")))
6602 (set_attr "type" "branch")
6603 (set_attr "atype" "agen")])
6605 (define_insn_and_split "doloop_di"
6608 (ne (match_operand:DI 1 "register_operand" "d,d")
6610 (label_ref (match_operand 0 "" ""))
6612 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
6613 (plus:DI (match_dup 1) (const_int -1)))
6614 (clobber (match_scratch:DI 3 "=X,&1"))
6615 (clobber (reg:CC CC_REGNUM))]
6618 if (which_alternative != 0)
6620 else if (get_attr_length (insn) == 4)
6621 return "brctg\t%1,%l0";
6623 return "aghi\t%1,-1\;jgne\t%l0";
6625 "&& reload_completed
6626 && (! REG_P (operands[2])
6627 || ! rtx_equal_p (operands[1], operands[2]))"
6628 [(parallel [(set (reg:CCAN CC_REGNUM)
6629 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6631 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6632 (set (match_dup 2) (match_dup 3))
6633 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6634 (label_ref (match_dup 0))
6637 [(set_attr "op_type" "RI")
6638 (set_attr "type" "branch")
6639 (set (attr "length")
6640 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6641 (const_int 4) (const_int 10)))])
6644 ;;- Unconditional jump instructions.
6648 ; jump instruction pattern(s).
6651 (define_expand "jump"
6652 [(match_operand 0 "" "")]
6654 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6656 (define_insn "*jump64"
6657 [(set (pc) (label_ref (match_operand 0 "" "")))]
6660 if (get_attr_length (insn) == 4)
6665 [(set_attr "op_type" "RI")
6666 (set_attr "type" "branch")
6667 (set (attr "length")
6668 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6669 (const_int 4) (const_int 6)))])
6671 (define_insn "*jump31"
6672 [(set (pc) (label_ref (match_operand 0 "" "")))]
6675 gcc_assert (get_attr_length (insn) == 4);
6678 [(set_attr "op_type" "RI")
6679 (set_attr "type" "branch")
6680 (set (attr "length")
6681 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6682 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6683 (const_int 4) (const_int 6))
6684 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6685 (const_int 4) (const_int 8))))])
6688 ; indirect-jump instruction pattern(s).
6691 (define_insn "indirect_jump"
6692 [(set (pc) (match_operand 0 "address_operand" "U"))]
6695 if (get_attr_op_type (insn) == OP_TYPE_RR)
6700 [(set (attr "op_type")
6701 (if_then_else (match_operand 0 "register_operand" "")
6702 (const_string "RR") (const_string "RX")))
6703 (set_attr "type" "branch")
6704 (set_attr "atype" "agen")])
6707 ; casesi instruction pattern(s).
6710 (define_insn "casesi_jump"
6711 [(set (pc) (match_operand 0 "address_operand" "U"))
6712 (use (label_ref (match_operand 1 "" "")))]
6715 if (get_attr_op_type (insn) == OP_TYPE_RR)
6720 [(set (attr "op_type")
6721 (if_then_else (match_operand 0 "register_operand" "")
6722 (const_string "RR") (const_string "RX")))
6723 (set_attr "type" "branch")
6724 (set_attr "atype" "agen")])
6726 (define_expand "casesi"
6727 [(match_operand:SI 0 "general_operand" "")
6728 (match_operand:SI 1 "general_operand" "")
6729 (match_operand:SI 2 "general_operand" "")
6730 (label_ref (match_operand 3 "" ""))
6731 (label_ref (match_operand 4 "" ""))]
6734 rtx index = gen_reg_rtx (SImode);
6735 rtx base = gen_reg_rtx (Pmode);
6736 rtx target = gen_reg_rtx (Pmode);
6738 emit_move_insn (index, operands[0]);
6739 emit_insn (gen_subsi3 (index, index, operands[1]));
6740 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6743 if (Pmode != SImode)
6744 index = convert_to_mode (Pmode, index, 1);
6745 if (GET_CODE (index) != REG)
6746 index = copy_to_mode_reg (Pmode, index);
6749 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6751 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
6753 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6755 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
6756 emit_move_insn (target, index);
6759 target = gen_rtx_PLUS (Pmode, base, target);
6760 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6767 ;;- Jump to subroutine.
6772 ; untyped call instruction pattern(s).
6775 ;; Call subroutine returning any type.
6776 (define_expand "untyped_call"
6777 [(parallel [(call (match_operand 0 "" "")
6779 (match_operand 1 "" "")
6780 (match_operand 2 "" "")])]
6785 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6787 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6789 rtx set = XVECEXP (operands[2], 0, i);
6790 emit_move_insn (SET_DEST (set), SET_SRC (set));
6793 /* The optimizer does not know that the call sets the function value
6794 registers we stored in the result block. We avoid problems by
6795 claiming that all hard registers are used and clobbered at this
6797 emit_insn (gen_blockage ());
6802 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6803 ;; all of memory. This blocks insns from being moved across this point.
6805 (define_insn "blockage"
6806 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6809 [(set_attr "type" "none")
6810 (set_attr "length" "0")])
6816 (define_expand "sibcall"
6817 [(call (match_operand 0 "" "")
6818 (match_operand 1 "" ""))]
6821 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
6825 (define_insn "*sibcall_br"
6826 [(call (mem:QI (reg SIBCALL_REGNUM))
6827 (match_operand 0 "const_int_operand" "n"))]
6828 "SIBLING_CALL_P (insn)
6829 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
6831 [(set_attr "op_type" "RR")
6832 (set_attr "type" "branch")
6833 (set_attr "atype" "agen")])
6835 (define_insn "*sibcall_brc"
6836 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6837 (match_operand 1 "const_int_operand" "n"))]
6838 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6840 [(set_attr "op_type" "RI")
6841 (set_attr "type" "branch")])
6843 (define_insn "*sibcall_brcl"
6844 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6845 (match_operand 1 "const_int_operand" "n"))]
6846 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6848 [(set_attr "op_type" "RIL")
6849 (set_attr "type" "branch")])
6852 ; sibcall_value patterns
6855 (define_expand "sibcall_value"
6856 [(set (match_operand 0 "" "")
6857 (call (match_operand 1 "" "")
6858 (match_operand 2 "" "")))]
6861 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
6865 (define_insn "*sibcall_value_br"
6866 [(set (match_operand 0 "" "")
6867 (call (mem:QI (reg SIBCALL_REGNUM))
6868 (match_operand 1 "const_int_operand" "n")))]
6869 "SIBLING_CALL_P (insn)
6870 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
6872 [(set_attr "op_type" "RR")
6873 (set_attr "type" "branch")
6874 (set_attr "atype" "agen")])
6876 (define_insn "*sibcall_value_brc"
6877 [(set (match_operand 0 "" "")
6878 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6879 (match_operand 2 "const_int_operand" "n")))]
6880 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
6882 [(set_attr "op_type" "RI")
6883 (set_attr "type" "branch")])
6885 (define_insn "*sibcall_value_brcl"
6886 [(set (match_operand 0 "" "")
6887 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6888 (match_operand 2 "const_int_operand" "n")))]
6889 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
6891 [(set_attr "op_type" "RIL")
6892 (set_attr "type" "branch")])
6896 ; call instruction pattern(s).
6899 (define_expand "call"
6900 [(call (match_operand 0 "" "")
6901 (match_operand 1 "" ""))
6902 (use (match_operand 2 "" ""))]
6905 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
6906 gen_rtx_REG (Pmode, RETURN_REGNUM));
6910 (define_insn "*bras"
6911 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6912 (match_operand 1 "const_int_operand" "n"))
6913 (clobber (match_operand 2 "register_operand" "=r"))]
6914 "!SIBLING_CALL_P (insn)
6915 && TARGET_SMALL_EXEC
6916 && GET_MODE (operands[2]) == Pmode"
6918 [(set_attr "op_type" "RI")
6919 (set_attr "type" "jsr")])
6921 (define_insn "*brasl"
6922 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
6923 (match_operand 1 "const_int_operand" "n"))
6924 (clobber (match_operand 2 "register_operand" "=r"))]
6925 "!SIBLING_CALL_P (insn)
6927 && GET_MODE (operands[2]) == Pmode"
6929 [(set_attr "op_type" "RIL")
6930 (set_attr "type" "jsr")])
6932 (define_insn "*basr"
6933 [(call (mem:QI (match_operand 0 "address_operand" "U"))
6934 (match_operand 1 "const_int_operand" "n"))
6935 (clobber (match_operand 2 "register_operand" "=r"))]
6936 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
6938 if (get_attr_op_type (insn) == OP_TYPE_RR)
6939 return "basr\t%2,%0";
6941 return "bas\t%2,%a0";
6943 [(set (attr "op_type")
6944 (if_then_else (match_operand 0 "register_operand" "")
6945 (const_string "RR") (const_string "RX")))
6946 (set_attr "type" "jsr")
6947 (set_attr "atype" "agen")])
6950 ; call_value instruction pattern(s).
6953 (define_expand "call_value"
6954 [(set (match_operand 0 "" "")
6955 (call (match_operand 1 "" "")
6956 (match_operand 2 "" "")))
6957 (use (match_operand 3 "" ""))]
6960 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
6961 gen_rtx_REG (Pmode, RETURN_REGNUM));
6965 (define_insn "*bras_r"
6966 [(set (match_operand 0 "" "")
6967 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6968 (match_operand:SI 2 "const_int_operand" "n")))
6969 (clobber (match_operand 3 "register_operand" "=r"))]
6970 "!SIBLING_CALL_P (insn)
6971 && TARGET_SMALL_EXEC
6972 && GET_MODE (operands[3]) == Pmode"
6974 [(set_attr "op_type" "RI")
6975 (set_attr "type" "jsr")])
6977 (define_insn "*brasl_r"
6978 [(set (match_operand 0 "" "")
6979 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
6980 (match_operand 2 "const_int_operand" "n")))
6981 (clobber (match_operand 3 "register_operand" "=r"))]
6982 "!SIBLING_CALL_P (insn)
6984 && GET_MODE (operands[3]) == Pmode"
6986 [(set_attr "op_type" "RIL")
6987 (set_attr "type" "jsr")])
6989 (define_insn "*basr_r"
6990 [(set (match_operand 0 "" "")
6991 (call (mem:QI (match_operand 1 "address_operand" "U"))
6992 (match_operand 2 "const_int_operand" "n")))
6993 (clobber (match_operand 3 "register_operand" "=r"))]
6994 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
6996 if (get_attr_op_type (insn) == OP_TYPE_RR)
6997 return "basr\t%3,%1";
6999 return "bas\t%3,%a1";
7001 [(set (attr "op_type")
7002 (if_then_else (match_operand 1 "register_operand" "")
7003 (const_string "RR") (const_string "RX")))
7004 (set_attr "type" "jsr")
7005 (set_attr "atype" "agen")])
7008 ;;- Thread-local storage support.
7011 (define_expand "get_tp_64"
7012 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
7016 (define_expand "get_tp_31"
7017 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
7021 (define_expand "set_tp_64"
7022 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
7023 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
7027 (define_expand "set_tp_31"
7028 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
7029 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
7033 (define_insn "*set_tp"
7034 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
7037 [(set_attr "type" "none")
7038 (set_attr "length" "0")])
7040 (define_insn "*tls_load_64"
7041 [(set (match_operand:DI 0 "register_operand" "=d")
7042 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
7043 (match_operand:DI 2 "" "")]
7047 [(set_attr "op_type" "RXE")])
7049 (define_insn "*tls_load_31"
7050 [(set (match_operand:SI 0 "register_operand" "=d,d")
7051 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
7052 (match_operand:SI 2 "" "")]
7058 [(set_attr "op_type" "RX,RXY")])
7060 (define_insn "*bras_tls"
7061 [(set (match_operand 0 "" "")
7062 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7063 (match_operand 2 "const_int_operand" "n")))
7064 (clobber (match_operand 3 "register_operand" "=r"))
7065 (use (match_operand 4 "" ""))]
7066 "!SIBLING_CALL_P (insn)
7067 && TARGET_SMALL_EXEC
7068 && GET_MODE (operands[3]) == Pmode"
7070 [(set_attr "op_type" "RI")
7071 (set_attr "type" "jsr")])
7073 (define_insn "*brasl_tls"
7074 [(set (match_operand 0 "" "")
7075 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7076 (match_operand 2 "const_int_operand" "n")))
7077 (clobber (match_operand 3 "register_operand" "=r"))
7078 (use (match_operand 4 "" ""))]
7079 "!SIBLING_CALL_P (insn)
7081 && GET_MODE (operands[3]) == Pmode"
7083 [(set_attr "op_type" "RIL")
7084 (set_attr "type" "jsr")])
7086 (define_insn "*basr_tls"
7087 [(set (match_operand 0 "" "")
7088 (call (mem:QI (match_operand 1 "address_operand" "U"))
7089 (match_operand 2 "const_int_operand" "n")))
7090 (clobber (match_operand 3 "register_operand" "=r"))
7091 (use (match_operand 4 "" ""))]
7092 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7094 if (get_attr_op_type (insn) == OP_TYPE_RR)
7095 return "basr\t%3,%1%J4";
7097 return "bas\t%3,%a1%J4";
7099 [(set (attr "op_type")
7100 (if_then_else (match_operand 1 "register_operand" "")
7101 (const_string "RR") (const_string "RX")))
7102 (set_attr "type" "jsr")
7103 (set_attr "atype" "agen")])
7106 ;;- Atomic operations
7110 ; memory barrier pattern.
7113 (define_expand "memory_barrier"
7114 [(set (mem:BLK (match_dup 0))
7115 (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
7118 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
7119 MEM_VOLATILE_P (operands[0]) = 1;
7122 (define_insn "*memory_barrier"
7123 [(set (match_operand:BLK 0 "" "")
7124 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
7127 [(set_attr "op_type" "RR")])
7130 ; compare and swap patterns.
7133 (define_insn "sync_compare_and_swap<mode>"
7134 [(set (match_operand:GPR 0 "register_operand" "=r")
7135 (match_operand:GPR 1 "memory_operand" "+Q"))
7137 (unspec_volatile:GPR
7139 (match_operand:GPR 2 "register_operand" "0")
7140 (match_operand:GPR 3 "register_operand" "r")]
7142 (clobber (reg:CC CC_REGNUM))]
7145 [(set_attr "op_type" "RS<E>")
7146 (set_attr "type" "sem")])
7148 (define_expand "sync_compare_and_swap_cc<mode>"
7150 [(set (match_operand:GPR 0 "register_operand" "")
7151 (match_operand:GPR 1 "memory_operand" ""))
7153 (unspec_volatile:GPR
7155 (match_operand:GPR 2 "register_operand" "")
7156 (match_operand:GPR 3 "register_operand" "")]
7159 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7162 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
7163 s390_compare_op0 = operands[1];
7164 s390_compare_op1 = operands[2];
7165 s390_compare_emitted = operands[4];
7168 (define_insn "*sync_compare_and_swap_cc<mode>"
7169 [(set (match_operand:GPR 0 "register_operand" "=r")
7170 (match_operand:GPR 1 "memory_operand" "+Q"))
7172 (unspec_volatile:GPR
7174 (match_operand:GPR 2 "register_operand" "0")
7175 (match_operand:GPR 3 "register_operand" "r")]
7177 (set (reg:CCZ1 CC_REGNUM)
7178 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7181 [(set_attr "op_type" "RS<E>")
7182 (set_attr "type" "sem")])
7186 ;;- Miscellaneous instructions.
7190 ; allocate stack instruction pattern(s).
7193 (define_expand "allocate_stack"
7194 [(match_operand 0 "general_operand" "")
7195 (match_operand 1 "general_operand" "")]
7198 rtx temp = gen_reg_rtx (Pmode);
7200 emit_move_insn (temp, s390_back_chain_rtx ());
7201 anti_adjust_stack (operands[1]);
7202 emit_move_insn (s390_back_chain_rtx (), temp);
7204 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7210 ; setjmp instruction pattern.
7213 (define_expand "builtin_setjmp_receiver"
7214 [(match_operand 0 "" "")]
7217 emit_insn (s390_load_got ());
7218 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
7222 ;; These patterns say how to save and restore the stack pointer. We need not
7223 ;; save the stack pointer at function level since we are careful to
7224 ;; preserve the backchain. At block level, we have to restore the backchain
7225 ;; when we restore the stack pointer.
7227 ;; For nonlocal gotos, we must save both the stack pointer and its
7228 ;; backchain and restore both. Note that in the nonlocal case, the
7229 ;; save area is a memory location.
7231 (define_expand "save_stack_function"
7232 [(match_operand 0 "general_operand" "")
7233 (match_operand 1 "general_operand" "")]
7237 (define_expand "restore_stack_function"
7238 [(match_operand 0 "general_operand" "")
7239 (match_operand 1 "general_operand" "")]
7243 (define_expand "restore_stack_block"
7244 [(match_operand 0 "register_operand" "")
7245 (match_operand 1 "register_operand" "")]
7248 rtx temp = gen_reg_rtx (Pmode);
7250 emit_move_insn (temp, s390_back_chain_rtx ());
7251 emit_move_insn (operands[0], operands[1]);
7252 emit_move_insn (s390_back_chain_rtx (), temp);
7257 (define_expand "save_stack_nonlocal"
7258 [(match_operand 0 "memory_operand" "")
7259 (match_operand 1 "register_operand" "")]
7262 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7263 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7265 /* Copy the backchain to the first word, sp to the second and the
7266 literal pool base to the third. */
7268 if (TARGET_BACKCHAIN)
7270 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
7271 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
7274 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
7275 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
7280 (define_expand "restore_stack_nonlocal"
7281 [(match_operand 0 "register_operand" "")
7282 (match_operand 1 "memory_operand" "")]
7285 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7286 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7287 rtx temp = NULL_RTX;
7289 /* Restore the backchain from the first word, sp from the second and the
7290 literal pool base from the third. */
7292 if (TARGET_BACKCHAIN)
7293 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7295 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7296 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7299 emit_move_insn (s390_back_chain_rtx (), temp);
7301 emit_insn (gen_rtx_USE (VOIDmode, base));
7305 (define_expand "exception_receiver"
7309 s390_set_has_landing_pad_p (true);
7314 ; nop instruction pattern(s).
7321 [(set_attr "op_type" "RR")])
7325 ; Special literal pool access instruction pattern(s).
7328 (define_insn "*pool_entry"
7329 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7330 UNSPECV_POOL_ENTRY)]
7333 enum machine_mode mode = GET_MODE (PATTERN (insn));
7334 unsigned int align = GET_MODE_BITSIZE (mode);
7335 s390_output_pool_entry (operands[0], mode, align);
7338 [(set (attr "length")
7339 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7341 (define_insn "pool_align"
7342 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7343 UNSPECV_POOL_ALIGN)]
7346 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7348 (define_insn "pool_section_start"
7349 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7352 [(set_attr "length" "0")])
7354 (define_insn "pool_section_end"
7355 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
7358 [(set_attr "length" "0")])
7360 (define_insn "main_base_31_small"
7361 [(set (match_operand 0 "register_operand" "=a")
7362 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7363 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7365 [(set_attr "op_type" "RR")
7366 (set_attr "type" "la")])
7368 (define_insn "main_base_31_large"
7369 [(set (match_operand 0 "register_operand" "=a")
7370 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
7371 (set (pc) (label_ref (match_operand 2 "" "")))]
7372 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7374 [(set_attr "op_type" "RI")])
7376 (define_insn "main_base_64"
7377 [(set (match_operand 0 "register_operand" "=a")
7378 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7379 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7381 [(set_attr "op_type" "RIL")
7382 (set_attr "type" "larl")])
7384 (define_insn "main_pool"
7385 [(set (match_operand 0 "register_operand" "=a")
7386 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
7387 "GET_MODE (operands[0]) == Pmode"
7392 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
7393 (const_string "larl") (const_string "la")))])
7395 (define_insn "reload_base_31"
7396 [(set (match_operand 0 "register_operand" "=a")
7397 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7398 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7399 "basr\t%0,0\;la\t%0,%1-.(%0)"
7400 [(set_attr "length" "6")
7401 (set_attr "type" "la")])
7403 (define_insn "reload_base_64"
7404 [(set (match_operand 0 "register_operand" "=a")
7405 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7406 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7408 [(set_attr "op_type" "RIL")
7409 (set_attr "type" "larl")])
7412 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7417 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7420 ;; Insns related to generating the function prologue and epilogue.
7424 (define_expand "prologue"
7425 [(use (const_int 0))]
7427 "s390_emit_prologue (); DONE;")
7429 (define_expand "epilogue"
7430 [(use (const_int 1))]
7432 "s390_emit_epilogue (false); DONE;")
7434 (define_expand "sibcall_epilogue"
7435 [(use (const_int 0))]
7437 "s390_emit_epilogue (true); DONE;")
7439 (define_insn "*return"
7441 (use (match_operand 0 "register_operand" "a"))]
7442 "GET_MODE (operands[0]) == Pmode"
7444 [(set_attr "op_type" "RR")
7445 (set_attr "type" "jsr")
7446 (set_attr "atype" "agen")])
7449 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7450 ;; pointer. This is used for compatibility.
7452 (define_expand "ptr_extend"
7453 [(set (match_operand:DI 0 "register_operand" "=r")
7454 (match_operand:SI 1 "register_operand" "r"))]
7457 emit_insn (gen_anddi3 (operands[0],
7458 gen_lowpart (DImode, operands[1]),
7459 GEN_INT (0x7fffffff)));
7463 ;; Instruction definition to expand eh_return macro to support
7464 ;; swapping in special linkage return addresses.
7466 (define_expand "eh_return"
7467 [(use (match_operand 0 "register_operand" ""))]
7470 s390_emit_tpf_eh_return (operands[0]);
7475 ; Stack Protector Patterns
7478 (define_expand "stack_protect_set"
7479 [(set (match_operand 0 "memory_operand" "")
7480 (match_operand 1 "memory_operand" ""))]
7483 #ifdef TARGET_THREAD_SSP_OFFSET
7485 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7486 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7489 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
7491 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
7496 (define_insn "stack_protect_set<mode>"
7497 [(set (match_operand:DSI 0 "memory_operand" "=Q")
7498 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
7500 "mvc\t%O0(%G0,%R0),%S1"
7501 [(set_attr "op_type" "SS")])
7503 (define_expand "stack_protect_test"
7504 [(set (reg:CC CC_REGNUM)
7505 (compare (match_operand 0 "memory_operand" "")
7506 (match_operand 1 "memory_operand" "")))
7507 (match_operand 2 "" "")]
7510 #ifdef TARGET_THREAD_SSP_OFFSET
7512 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7513 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7515 s390_compare_op0 = operands[0];
7516 s390_compare_op1 = operands[1];
7517 s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM);
7520 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
7522 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
7524 emit_jump_insn (gen_beq (operands[2]));
7529 (define_insn "stack_protect_test<mode>"
7530 [(set (reg:CCZ CC_REGNUM)
7531 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
7532 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
7534 "clc\t%O0(%G0,%R0),%S1"
7535 [(set_attr "op_type" "SS")])