1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; I -- An 8-bit constant (0..255).
31 ;; J -- A 12-bit constant (0..4095).
32 ;; K -- A 16-bit constant (-32768..32767).
33 ;; L -- Value appropriate as displacement.
34 ;; (0..4095) for short displacement
35 ;; (-524288..524287) for long displacement
36 ;; M -- Constant integer with a value of 0x7fffffff.
37 ;; N -- Multiple letter constraint followed by 4 parameter letters.
38 ;; 0..9,x: number of the part counting from most to least significant
39 ;; H,Q: mode of the part
40 ;; D,S,H: mode of the containing operand
41 ;; 0,F: value of the other parts (F - all bits set)
43 ;; The constraint matches if the specified part of a constant
44 ;; has a value different from its other parts. If the letter x
45 ;; is specified instead of a part number, the constraint matches
46 ;; if there is any single part with non-default value.
47 ;; Q -- Memory reference without index register and with short displacement.
48 ;; R -- Memory reference with index register and short displacement.
49 ;; S -- Memory reference without index register but with long displacement.
50 ;; T -- Memory reference with index register and long displacement.
51 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
52 ;; Offsettable memory reference of type specified by second letter.
53 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
54 ;; Memory reference of the type specified by second letter that
55 ;; does *not* refer to a literal pool entry.
56 ;; U -- Pointer with short displacement.
57 ;; W -- Pointer with long displacement.
58 ;; Y -- Shift count operand.
60 ;; Special formats used for outputting 390 instructions.
62 ;; %C: print opcode suffix for branch condition.
63 ;; %D: print opcode suffix for inverse branch condition.
64 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
65 ;; %O: print only the displacement of a memory reference.
66 ;; %R: print only the base register of a memory reference.
67 ;; %S: print S-type memory reference (base+displacement).
68 ;; %N: print the second word of a DImode operand.
69 ;; %M: print the second word of a TImode operand.
71 ;; %b: print integer X as if it's an unsigned byte.
72 ;; %x: print integer X as if it's an unsigned word.
73 ;; %h: print integer X as if it's a signed word.
74 ;; %i: print the first nonzero HImode part of X
75 ;; %j: print the first HImode part unequal to 0xffff of X
78 ;; We have a special constraint for pattern matching.
80 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
93 ; GOT/PLT and lt-relative accesses
94 (UNSPEC_LTREL_OFFSET 100)
95 (UNSPEC_LTREL_BASE 101)
103 (UNSPEC_RELOAD_BASE 210)
104 (UNSPEC_MAIN_BASE 211)
109 ; TLS relocation specifiers
114 (UNSPEC_GOTNTPOFF 504)
115 (UNSPEC_INDNTPOFF 505)
118 (UNSPEC_TLSLDM_NTPOFF 511)
119 (UNSPEC_TLS_LOAD 512)
126 ;; UNSPEC_VOLATILE usage
134 (UNSPECV_TPF_PROLOGUE 20)
135 (UNSPECV_TPF_EPILOGUE 21)
139 (UNSPECV_POOL_SECTION 201)
140 (UNSPECV_POOL_ALIGN 202)
141 (UNSPECV_POOL_ENTRY 203)
142 (UNSPECV_MAIN_POOL 300)
149 ;; Instruction operand type as used in the Principles of Operation.
150 ;; Used to determine defaults for length and other attribute values.
152 (define_attr "op_type"
153 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
156 ;; Instruction type attribute used for scheduling.
158 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
160 imulhi,imulsi,imuldi,
161 branch,jsr,fsimpd,fsimps,
162 floadd,floads,fstored, fstores,
163 fmuld,fmuls,fdivd,fdivs,
164 ftoi,itof,fsqrtd,fsqrts,
166 (cond [(eq_attr "op_type" "NN") (const_string "other")
167 (eq_attr "op_type" "SS") (const_string "cs")]
168 (const_string "integer")))
170 ;; Another attribute used for scheduling purposes:
171 ;; agen: Instruction uses the address generation unit
172 ;; reg: Instruction does not use the agen unit
174 (define_attr "atype" "agen,reg"
175 (cond [(eq_attr "op_type" "E") (const_string "reg")
176 (eq_attr "op_type" "RR") (const_string "reg")
177 (eq_attr "op_type" "RX") (const_string "agen")
178 (eq_attr "op_type" "RI") (const_string "reg")
179 (eq_attr "op_type" "RRE") (const_string "reg")
180 (eq_attr "op_type" "RS") (const_string "agen")
181 (eq_attr "op_type" "RSI") (const_string "agen")
182 (eq_attr "op_type" "S") (const_string "agen")
183 (eq_attr "op_type" "SI") (const_string "agen")
184 (eq_attr "op_type" "SS") (const_string "agen")
185 (eq_attr "op_type" "SSE") (const_string "agen")
186 (eq_attr "op_type" "RXE") (const_string "agen")
187 (eq_attr "op_type" "RSE") (const_string "agen")
188 (eq_attr "op_type" "RIL") (const_string "agen")
189 (eq_attr "op_type" "RXY") (const_string "agen")
190 (eq_attr "op_type" "RSY") (const_string "agen")
191 (eq_attr "op_type" "SIY") (const_string "agen")]
192 (const_string "agen")))
196 (define_attr "length" ""
197 (cond [(eq_attr "op_type" "E") (const_int 2)
198 (eq_attr "op_type" "RR") (const_int 2)
199 (eq_attr "op_type" "RX") (const_int 4)
200 (eq_attr "op_type" "RI") (const_int 4)
201 (eq_attr "op_type" "RRE") (const_int 4)
202 (eq_attr "op_type" "RS") (const_int 4)
203 (eq_attr "op_type" "RSI") (const_int 4)
204 (eq_attr "op_type" "S") (const_int 4)
205 (eq_attr "op_type" "SI") (const_int 4)
206 (eq_attr "op_type" "SS") (const_int 6)
207 (eq_attr "op_type" "SSE") (const_int 6)
208 (eq_attr "op_type" "RXE") (const_int 6)
209 (eq_attr "op_type" "RSE") (const_int 6)
210 (eq_attr "op_type" "RIL") (const_int 6)
211 (eq_attr "op_type" "RXY") (const_int 6)
212 (eq_attr "op_type" "RSY") (const_int 6)
213 (eq_attr "op_type" "SIY") (const_int 6)]
217 ;; Processor type. This attribute must exactly match the processor_type
218 ;; enumeration in s390.h. The current machine description does not
219 ;; distinguish between g5 and g6, but there are differences between the two
220 ;; CPUs could in theory be modeled.
222 (define_attr "cpu" "g5,g6,z900,z990"
223 (const (symbol_ref "s390_tune")))
225 ;; Pipeline description for z900. For lack of anything better,
226 ;; this description is also used for the g5 and g6.
229 ;; Pipeline description for z990.
233 (include "predicates.md")
238 ;; This mode macro allows 31-bit and 64-bit GPR patterns to be generated
239 ;; from the same template.
240 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
242 ;; This mode macro allows :P to be used for patterns that operate on
243 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
244 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
246 ;; This mode macro allows the QI and HI patterns to be defined from
247 ;; the same template.
248 (define_mode_macro HQI [HI QI])
251 ;; ICM mask required to load MODE value into the highest subreg
252 ;; of a SImode register.
253 (define_mode_attr icm_hi [(HI "12") (QI "8")])
255 ;; ICM mask required to load MODE value into the lowest subreg
256 ;; of a SImode register.
257 (define_mode_attr icm_lo [(HI "3") (QI "1")])
259 ;; Maximum unsigned integer that fits in MODE.
260 (define_mode_attr max_uint [(HI "65535") (QI "255")])
264 ;;- Compare instructions.
267 (define_expand "cmp<mode>"
269 (compare:CC (match_operand:GPR 0 "register_operand" "")
270 (match_operand:GPR 1 "general_operand" "")))]
273 s390_compare_op0 = operands[0];
274 s390_compare_op1 = operands[1];
278 (define_expand "cmpdf"
280 (compare:CC (match_operand:DF 0 "register_operand" "")
281 (match_operand:DF 1 "general_operand" "")))]
284 s390_compare_op0 = operands[0];
285 s390_compare_op1 = operands[1];
289 (define_expand "cmpsf"
291 (compare:CC (match_operand:SF 0 "register_operand" "")
292 (match_operand:SF 1 "general_operand" "")))]
295 s390_compare_op0 = operands[0];
296 s390_compare_op1 = operands[1];
301 ; Test-under-Mask instructions
303 (define_insn "*tmqi_mem"
305 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
306 (match_operand:QI 1 "immediate_operand" "n,n"))
307 (match_operand:QI 2 "immediate_operand" "n,n")))]
308 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
312 [(set_attr "op_type" "SI,SIY")])
314 (define_insn "*tmdi_reg"
316 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
317 (match_operand:DI 1 "immediate_operand"
318 "N0HD0,N1HD0,N2HD0,N3HD0"))
319 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
321 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
322 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
328 [(set_attr "op_type" "RI")])
330 (define_insn "*tmsi_reg"
332 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
333 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
334 (match_operand:SI 2 "immediate_operand" "n,n")))]
335 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
336 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
340 [(set_attr "op_type" "RI")])
342 (define_insn "*tm<mode>_full"
344 (compare (match_operand:HQI 0 "register_operand" "d")
345 (match_operand:HQI 1 "immediate_operand" "n")))]
346 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))"
348 [(set_attr "op_type" "RI")])
351 ; Load-and-Test instructions
353 (define_insn "*tstdi_sign"
355 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
356 (const_int 32)) (const_int 32))
357 (match_operand:DI 1 "const0_operand" "")))
358 (set (match_operand:DI 2 "register_operand" "=d")
359 (sign_extend:DI (match_dup 0)))]
360 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
362 [(set_attr "op_type" "RRE")])
364 (define_insn "*tstdi"
366 (compare (match_operand:DI 0 "register_operand" "d")
367 (match_operand:DI 1 "const0_operand" "")))
368 (set (match_operand:DI 2 "register_operand" "=d")
370 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
372 [(set_attr "op_type" "RRE")])
374 (define_insn "*tstdi_cconly"
376 (compare (match_operand:DI 0 "register_operand" "d")
377 (match_operand:DI 1 "const0_operand" "")))]
378 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
380 [(set_attr "op_type" "RRE")])
382 (define_insn "*tstdi_cconly_31"
384 (compare (match_operand:DI 0 "register_operand" "d")
385 (match_operand:DI 1 "const0_operand" "")))]
386 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
388 [(set_attr "op_type" "RS")
389 (set_attr "atype" "reg")])
392 (define_insn "*tstsi"
394 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
395 (match_operand:SI 1 "const0_operand" "")))
396 (set (match_operand:SI 2 "register_operand" "=d,d,d")
398 "s390_match_ccmode(insn, CCSmode)"
403 [(set_attr "op_type" "RR,RS,RSY")])
405 (define_insn "*tstsi_cconly"
407 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
408 (match_operand:SI 1 "const0_operand" "")))
409 (clobber (match_scratch:SI 2 "=X,d,d"))]
410 "s390_match_ccmode(insn, CCSmode)"
415 [(set_attr "op_type" "RR,RS,RSY")])
417 (define_insn "*tstsi_cconly2"
419 (compare (match_operand:SI 0 "register_operand" "d")
420 (match_operand:SI 1 "const0_operand" "")))]
421 "s390_match_ccmode(insn, CCSmode)"
423 [(set_attr "op_type" "RR")])
425 (define_insn "*tst<mode>CCT"
427 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
428 (match_operand:HQI 1 "const0_operand" "")))
429 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
431 "s390_match_ccmode(insn, CCTmode)"
434 icmy\t%2,<icm_lo>,%S0
436 [(set_attr "op_type" "RS,RSY,RI")])
438 (define_insn "*tsthiCCT_cconly"
440 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
441 (match_operand:HI 1 "const0_operand" "")))
442 (clobber (match_scratch:HI 2 "=d,d,X"))]
443 "s390_match_ccmode(insn, CCTmode)"
448 [(set_attr "op_type" "RS,RSY,RI")])
450 (define_insn "*tstqiCCT_cconly"
452 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
453 (match_operand:QI 1 "const0_operand" "")))]
454 "s390_match_ccmode(insn, CCTmode)"
459 [(set_attr "op_type" "SI,SIY,RI")])
461 (define_insn "*tst<mode>"
463 (compare (match_operand:HQI 0 "s_operand" "Q,S")
464 (match_operand:HQI 1 "const0_operand" "")))
465 (set (match_operand:HQI 2 "register_operand" "=d,d")
467 "s390_match_ccmode(insn, CCSmode)"
470 icmy\t%2,<icm_lo>,%S0"
471 [(set_attr "op_type" "RS,RSY")])
473 (define_insn "*tst<mode>_cconly"
475 (compare (match_operand:HQI 0 "s_operand" "Q,S")
476 (match_operand:HQI 1 "const0_operand" "")))
477 (clobber (match_scratch:HQI 2 "=d,d"))]
478 "s390_match_ccmode(insn, CCSmode)"
481 icmy\t%2,<icm_lo>,%S0"
482 [(set_attr "op_type" "RS,RSY")])
485 ; Compare (equality) instructions
487 (define_insn "*cmpdi_cct"
489 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q")
490 (match_operand:DI 1 "general_operand" "d,K,m,BQ")))]
491 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
497 [(set_attr "op_type" "RRE,RI,RXY,SS")])
499 (define_insn "*cmpsi_cct"
501 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q")
502 (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))]
503 "s390_match_ccmode (insn, CCTmode)"
510 [(set_attr "op_type" "RR,RI,RX,RXY,SS")])
513 ; Compare (signed) instructions
515 (define_insn "*cmpdi_ccs_sign"
517 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
518 (match_operand:DI 0 "register_operand" "d,d")))]
519 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
523 [(set_attr "op_type" "RRE,RXY")])
525 (define_insn "*cmpdi_ccs"
527 (compare (match_operand:DI 0 "register_operand" "d,d,d")
528 (match_operand:DI 1 "general_operand" "d,K,m")))]
529 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
534 [(set_attr "op_type" "RRE,RI,RXY")])
536 (define_insn "*cmpsi_ccs_sign"
538 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
539 (match_operand:SI 0 "register_operand" "d,d")))]
540 "s390_match_ccmode(insn, CCSRmode)"
544 [(set_attr "op_type" "RX,RXY")])
546 (define_insn "*cmpsi_ccs"
548 (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
549 (match_operand:SI 1 "general_operand" "d,K,R,T")))]
550 "s390_match_ccmode(insn, CCSmode)"
556 [(set_attr "op_type" "RR,RI,RX,RXY")])
559 ; Compare (unsigned) instructions
561 (define_insn "*cmpdi_ccu_zero"
563 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
564 (match_operand:DI 0 "register_operand" "d,d")))]
565 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
569 [(set_attr "op_type" "RRE,RXY")])
571 (define_insn "*cmpdi_ccu"
573 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ")
574 (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))]
575 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
581 [(set_attr "op_type" "RRE,RXY,SS,SS")])
583 (define_insn "*cmpsi_ccu"
585 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
586 (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))]
587 "s390_match_ccmode (insn, CCUmode)"
594 [(set_attr "op_type" "RR,RX,RXY,SS,SS")])
596 (define_insn "*cmphi_ccu"
598 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
599 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
600 "s390_match_ccmode (insn, CCUmode)
601 && !register_operand (operands[1], HImode)"
607 [(set_attr "op_type" "RS,RSY,SS,SS")])
609 (define_insn "*cmpqi_ccu"
611 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
612 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
613 "s390_match_ccmode (insn, CCUmode)
614 && !register_operand (operands[1], QImode)"
622 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
625 ; Block compare (CLC) instruction patterns.
629 (compare (match_operand:BLK 0 "memory_operand" "Q")
630 (match_operand:BLK 1 "memory_operand" "Q")))
631 (use (match_operand 2 "const_int_operand" "n"))]
632 "s390_match_ccmode (insn, CCUmode)
633 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
634 "clc\t%O0(%2,%R0),%S1"
635 [(set_attr "op_type" "SS")])
639 (compare (match_operand 0 "memory_operand" "")
640 (match_operand 1 "memory_operand" "")))]
642 && s390_match_ccmode (insn, CCUmode)
643 && GET_MODE (operands[0]) == GET_MODE (operands[1])
644 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
646 [(set (match_dup 0) (match_dup 1))
647 (use (match_dup 2))])]
649 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
650 operands[0] = adjust_address (operands[0], BLKmode, 0);
651 operands[1] = adjust_address (operands[1], BLKmode, 0);
653 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
654 operands[0], operands[1]);
655 operands[0] = SET_DEST (PATTERN (curr_insn));
661 (define_insn "*cmpdf_ccs_0"
663 (compare (match_operand:DF 0 "register_operand" "f")
664 (match_operand:DF 1 "const0_operand" "")))]
665 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
667 [(set_attr "op_type" "RRE")
668 (set_attr "type" "fsimpd")])
670 (define_insn "*cmpdf_ccs_0_ibm"
672 (compare (match_operand:DF 0 "register_operand" "f")
673 (match_operand:DF 1 "const0_operand" "")))]
674 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
676 [(set_attr "op_type" "RR")
677 (set_attr "type" "fsimpd")])
679 (define_insn "*cmpdf_ccs"
681 (compare (match_operand:DF 0 "register_operand" "f,f")
682 (match_operand:DF 1 "general_operand" "f,R")))]
683 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
687 [(set_attr "op_type" "RRE,RXE")
688 (set_attr "type" "fsimpd")])
690 (define_insn "*cmpdf_ccs_ibm"
692 (compare (match_operand:DF 0 "register_operand" "f,f")
693 (match_operand:DF 1 "general_operand" "f,R")))]
694 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
698 [(set_attr "op_type" "RR,RX")
699 (set_attr "type" "fsimpd")])
704 (define_insn "*cmpsf_ccs_0"
706 (compare (match_operand:SF 0 "register_operand" "f")
707 (match_operand:SF 1 "const0_operand" "")))]
708 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
710 [(set_attr "op_type" "RRE")
711 (set_attr "type" "fsimps")])
713 (define_insn "*cmpsf_ccs_0_ibm"
715 (compare (match_operand:SF 0 "register_operand" "f")
716 (match_operand:SF 1 "const0_operand" "")))]
717 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
719 [(set_attr "op_type" "RR")
720 (set_attr "type" "fsimps")])
722 (define_insn "*cmpsf_ccs"
724 (compare (match_operand:SF 0 "register_operand" "f,f")
725 (match_operand:SF 1 "general_operand" "f,R")))]
726 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
730 [(set_attr "op_type" "RRE,RXE")
731 (set_attr "type" "fsimps")])
733 (define_insn "*cmpsf_ccs"
735 (compare (match_operand:SF 0 "register_operand" "f,f")
736 (match_operand:SF 1 "general_operand" "f,R")))]
737 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
741 [(set_attr "op_type" "RR,RX")
742 (set_attr "type" "fsimps")])
746 ;;- Move instructions.
750 ; movti instruction pattern(s).
754 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
755 (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
763 [(set_attr "op_type" "RSY,RSY,*,*,SS")
764 (set_attr "type" "lm,stm,*,*,*")])
767 [(set (match_operand:TI 0 "nonimmediate_operand" "")
768 (match_operand:TI 1 "general_operand" ""))]
769 "TARGET_64BIT && reload_completed
770 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
771 [(set (match_dup 2) (match_dup 4))
772 (set (match_dup 3) (match_dup 5))]
774 operands[2] = operand_subword (operands[0], 0, 0, TImode);
775 operands[3] = operand_subword (operands[0], 1, 0, TImode);
776 operands[4] = operand_subword (operands[1], 0, 0, TImode);
777 operands[5] = operand_subword (operands[1], 1, 0, TImode);
781 [(set (match_operand:TI 0 "nonimmediate_operand" "")
782 (match_operand:TI 1 "general_operand" ""))]
783 "TARGET_64BIT && reload_completed
784 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
785 [(set (match_dup 2) (match_dup 4))
786 (set (match_dup 3) (match_dup 5))]
788 operands[2] = operand_subword (operands[0], 1, 0, TImode);
789 operands[3] = operand_subword (operands[0], 0, 0, TImode);
790 operands[4] = operand_subword (operands[1], 1, 0, TImode);
791 operands[5] = operand_subword (operands[1], 0, 0, TImode);
795 [(set (match_operand:TI 0 "register_operand" "")
796 (match_operand:TI 1 "memory_operand" ""))]
797 "TARGET_64BIT && reload_completed
798 && !s_operand (operands[1], VOIDmode)"
799 [(set (match_dup 0) (match_dup 1))]
801 rtx addr = operand_subword (operands[0], 1, 0, TImode);
802 s390_load_address (addr, XEXP (operands[1], 0));
803 operands[1] = replace_equiv_address (operands[1], addr);
806 (define_expand "reload_outti"
807 [(parallel [(match_operand:TI 0 "" "")
808 (match_operand:TI 1 "register_operand" "d")
809 (match_operand:DI 2 "register_operand" "=&a")])]
812 gcc_assert (MEM_P (operands[0]));
813 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
814 operands[0] = replace_equiv_address (operands[0], operands[2]);
815 emit_move_insn (operands[0], operands[1]);
820 ; movdi instruction pattern(s).
823 (define_expand "movdi"
824 [(set (match_operand:DI 0 "general_operand" "")
825 (match_operand:DI 1 "general_operand" ""))]
828 /* Handle symbolic constants. */
829 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
830 emit_symbolic_move (operands);
833 (define_insn "*movdi_larl"
834 [(set (match_operand:DI 0 "register_operand" "=d")
835 (match_operand:DI 1 "larl_operand" "X"))]
837 && !FP_REG_P (operands[0])"
839 [(set_attr "op_type" "RIL")
840 (set_attr "type" "larl")])
842 (define_insn "*movdi_64"
843 [(set (match_operand:DI 0 "nonimmediate_operand"
844 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
845 (match_operand:DI 1 "general_operand"
846 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
868 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
869 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
870 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
871 floadd,floadd,floadd,fstored,fstored,*,*,*,*,*")])
874 [(set (match_operand:DI 0 "register_operand" "")
875 (match_operand:DI 1 "register_operand" ""))]
876 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
877 [(set (match_dup 2) (match_dup 3))
878 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
879 (set (strict_low_part (match_dup 2)) (match_dup 4))]
880 "operands[2] = gen_lowpart (SImode, operands[0]);
881 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
884 [(set (match_operand:DI 0 "register_operand" "")
885 (match_operand:DI 1 "register_operand" ""))]
886 "TARGET_64BIT && ACCESS_REG_P (operands[0])
887 && dead_or_set_p (insn, operands[1])"
888 [(set (match_dup 3) (match_dup 2))
889 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
890 (set (match_dup 4) (match_dup 2))]
891 "operands[2] = gen_lowpart (SImode, operands[1]);
892 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
895 [(set (match_operand:DI 0 "register_operand" "")
896 (match_operand:DI 1 "register_operand" ""))]
897 "TARGET_64BIT && ACCESS_REG_P (operands[0])
898 && !dead_or_set_p (insn, operands[1])"
899 [(set (match_dup 3) (match_dup 2))
900 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
901 (set (match_dup 4) (match_dup 2))
902 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
903 "operands[2] = gen_lowpart (SImode, operands[1]);
904 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
906 (define_insn "*movdi_31"
907 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
908 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
921 [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS")
922 (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,*")])
925 [(set (match_operand:DI 0 "nonimmediate_operand" "")
926 (match_operand:DI 1 "general_operand" ""))]
927 "!TARGET_64BIT && reload_completed
928 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
929 [(set (match_dup 2) (match_dup 4))
930 (set (match_dup 3) (match_dup 5))]
932 operands[2] = operand_subword (operands[0], 0, 0, DImode);
933 operands[3] = operand_subword (operands[0], 1, 0, DImode);
934 operands[4] = operand_subword (operands[1], 0, 0, DImode);
935 operands[5] = operand_subword (operands[1], 1, 0, DImode);
939 [(set (match_operand:DI 0 "nonimmediate_operand" "")
940 (match_operand:DI 1 "general_operand" ""))]
941 "!TARGET_64BIT && reload_completed
942 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
943 [(set (match_dup 2) (match_dup 4))
944 (set (match_dup 3) (match_dup 5))]
946 operands[2] = operand_subword (operands[0], 1, 0, DImode);
947 operands[3] = operand_subword (operands[0], 0, 0, DImode);
948 operands[4] = operand_subword (operands[1], 1, 0, DImode);
949 operands[5] = operand_subword (operands[1], 0, 0, DImode);
953 [(set (match_operand:DI 0 "register_operand" "")
954 (match_operand:DI 1 "memory_operand" ""))]
955 "!TARGET_64BIT && reload_completed
956 && !FP_REG_P (operands[0])
957 && !s_operand (operands[1], VOIDmode)"
958 [(set (match_dup 0) (match_dup 1))]
960 rtx addr = operand_subword (operands[0], 1, 0, DImode);
961 s390_load_address (addr, XEXP (operands[1], 0));
962 operands[1] = replace_equiv_address (operands[1], addr);
965 (define_expand "reload_outdi"
966 [(parallel [(match_operand:DI 0 "" "")
967 (match_operand:DI 1 "register_operand" "d")
968 (match_operand:SI 2 "register_operand" "=&a")])]
971 gcc_assert (MEM_P (operands[0]));
972 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
973 operands[0] = replace_equiv_address (operands[0], operands[2]);
974 emit_move_insn (operands[0], operands[1]);
979 [(set (match_operand:DI 0 "register_operand" "")
980 (mem:DI (match_operand 1 "address_operand" "")))]
982 && !FP_REG_P (operands[0])
983 && GET_CODE (operands[1]) == SYMBOL_REF
984 && CONSTANT_POOL_ADDRESS_P (operands[1])
985 && get_pool_mode (operands[1]) == DImode
986 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
987 [(set (match_dup 0) (match_dup 2))]
988 "operands[2] = get_pool_constant (operands[1]);")
990 (define_insn "*la_64"
991 [(set (match_operand:DI 0 "register_operand" "=d,d")
992 (match_operand:QI 1 "address_operand" "U,W"))]
997 [(set_attr "op_type" "RX,RXY")
998 (set_attr "type" "la")])
1002 [(set (match_operand:DI 0 "register_operand" "")
1003 (match_operand:QI 1 "address_operand" ""))
1004 (clobber (reg:CC 33))])]
1006 && preferred_la_operand_p (operands[1], const0_rtx)"
1007 [(set (match_dup 0) (match_dup 1))]
1011 [(set (match_operand:DI 0 "register_operand" "")
1012 (match_operand:DI 1 "register_operand" ""))
1015 (plus:DI (match_dup 0)
1016 (match_operand:DI 2 "nonmemory_operand" "")))
1017 (clobber (reg:CC 33))])]
1019 && !reg_overlap_mentioned_p (operands[0], operands[2])
1020 && preferred_la_operand_p (operands[1], operands[2])"
1021 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1024 (define_expand "reload_indi"
1025 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1026 (match_operand:DI 1 "s390_plus_operand" "")
1027 (match_operand:DI 2 "register_operand" "=&a")])]
1030 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1035 ; movsi instruction pattern(s).
1038 (define_expand "movsi"
1039 [(set (match_operand:SI 0 "general_operand" "")
1040 (match_operand:SI 1 "general_operand" ""))]
1043 /* Handle symbolic constants. */
1044 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1045 emit_symbolic_move (operands);
1048 (define_insn "*movsi_larl"
1049 [(set (match_operand:SI 0 "register_operand" "=d")
1050 (match_operand:SI 1 "larl_operand" "X"))]
1051 "!TARGET_64BIT && TARGET_CPU_ZARCH
1052 && !FP_REG_P (operands[0])"
1054 [(set_attr "op_type" "RIL")
1055 (set_attr "type" "larl")])
1057 (define_insn "*movsi_zarch"
1058 [(set (match_operand:SI 0 "nonimmediate_operand"
1059 "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1060 (match_operand:SI 1 "general_operand"
1061 "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1083 [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,
1084 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1085 (set_attr "type" "*,*,*,la,lr,load,load,store,store,
1086 floads,floads,floads,fstores,fstores,*,*,*,*,*")])
1088 (define_insn "*movsi_esa"
1089 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1090 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1105 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1106 (set_attr "type" "*,lr,load,store,floads,floads,fstores,*,*,*,*,*")])
1109 [(set (match_operand:SI 0 "register_operand" "")
1110 (mem:SI (match_operand 1 "address_operand" "")))]
1111 "!FP_REG_P (operands[0])
1112 && GET_CODE (operands[1]) == SYMBOL_REF
1113 && CONSTANT_POOL_ADDRESS_P (operands[1])
1114 && get_pool_mode (operands[1]) == SImode
1115 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1116 [(set (match_dup 0) (match_dup 2))]
1117 "operands[2] = get_pool_constant (operands[1]);")
1119 (define_insn "*la_31"
1120 [(set (match_operand:SI 0 "register_operand" "=d,d")
1121 (match_operand:QI 1 "address_operand" "U,W"))]
1122 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1126 [(set_attr "op_type" "RX,RXY")
1127 (set_attr "type" "la")])
1131 [(set (match_operand:SI 0 "register_operand" "")
1132 (match_operand:QI 1 "address_operand" ""))
1133 (clobber (reg:CC 33))])]
1135 && preferred_la_operand_p (operands[1], const0_rtx)"
1136 [(set (match_dup 0) (match_dup 1))]
1140 [(set (match_operand:SI 0 "register_operand" "")
1141 (match_operand:SI 1 "register_operand" ""))
1144 (plus:SI (match_dup 0)
1145 (match_operand:SI 2 "nonmemory_operand" "")))
1146 (clobber (reg:CC 33))])]
1148 && !reg_overlap_mentioned_p (operands[0], operands[2])
1149 && preferred_la_operand_p (operands[1], operands[2])"
1150 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1153 (define_insn "*la_31_and"
1154 [(set (match_operand:SI 0 "register_operand" "=d,d")
1155 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1156 (const_int 2147483647)))]
1161 [(set_attr "op_type" "RX,RXY")
1162 (set_attr "type" "la")])
1164 (define_insn_and_split "*la_31_and_cc"
1165 [(set (match_operand:SI 0 "register_operand" "=d")
1166 (and:SI (match_operand:QI 1 "address_operand" "p")
1167 (const_int 2147483647)))
1168 (clobber (reg:CC 33))]
1171 "&& reload_completed"
1173 (and:SI (match_dup 1) (const_int 2147483647)))]
1175 [(set_attr "op_type" "RX")
1176 (set_attr "type" "la")])
1178 (define_insn "force_la_31"
1179 [(set (match_operand:SI 0 "register_operand" "=d,d")
1180 (match_operand:QI 1 "address_operand" "U,W"))
1181 (use (const_int 0))]
1186 [(set_attr "op_type" "RX")
1187 (set_attr "type" "la")])
1189 (define_expand "reload_insi"
1190 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1191 (match_operand:SI 1 "s390_plus_operand" "")
1192 (match_operand:SI 2 "register_operand" "=&a")])]
1195 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1200 ; movhi instruction pattern(s).
1203 (define_expand "movhi"
1204 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1205 (match_operand:HI 1 "general_operand" ""))]
1208 /* Make it explicit that loading a register from memory
1209 always sign-extends (at least) to SImode. */
1210 if (optimize && !no_new_pseudos
1211 && register_operand (operands[0], VOIDmode)
1212 && GET_CODE (operands[1]) == MEM)
1214 rtx tmp = gen_reg_rtx (SImode);
1215 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1216 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1217 operands[1] = gen_lowpart (HImode, tmp);
1221 (define_insn "*movhi"
1222 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1223 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1233 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1234 (set_attr "type" "lr,*,*,*,store,store,*")])
1237 [(set (match_operand:HI 0 "register_operand" "")
1238 (mem:HI (match_operand 1 "address_operand" "")))]
1239 "GET_CODE (operands[1]) == SYMBOL_REF
1240 && CONSTANT_POOL_ADDRESS_P (operands[1])
1241 && get_pool_mode (operands[1]) == HImode
1242 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1243 [(set (match_dup 0) (match_dup 2))]
1244 "operands[2] = get_pool_constant (operands[1]);")
1247 ; movqi instruction pattern(s).
1250 (define_expand "movqi"
1251 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1252 (match_operand:QI 1 "general_operand" ""))]
1255 /* On z/Architecture, zero-extending from memory to register
1256 is just as fast as a QImode load. */
1257 if (TARGET_ZARCH && optimize && !no_new_pseudos
1258 && register_operand (operands[0], VOIDmode)
1259 && GET_CODE (operands[1]) == MEM)
1261 rtx tmp = gen_reg_rtx (word_mode);
1262 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1263 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1264 operands[1] = gen_lowpart (QImode, tmp);
1268 (define_insn "*movqi"
1269 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1270 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1282 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1283 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1286 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1287 (mem:QI (match_operand 1 "address_operand" "")))]
1288 "GET_CODE (operands[1]) == SYMBOL_REF
1289 && CONSTANT_POOL_ADDRESS_P (operands[1])
1290 && get_pool_mode (operands[1]) == QImode
1291 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1292 [(set (match_dup 0) (match_dup 2))]
1293 "operands[2] = get_pool_constant (operands[1]);")
1296 ; movstrictqi instruction pattern(s).
1299 (define_insn "*movstrictqi"
1300 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1301 (match_operand:QI 1 "memory_operand" "R,T"))]
1306 [(set_attr "op_type" "RX,RXY")])
1309 ; movstricthi instruction pattern(s).
1312 (define_insn "*movstricthi"
1313 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1314 (match_operand:HI 1 "memory_operand" "Q,S"))
1315 (clobber (reg:CC 33))]
1320 [(set_attr "op_type" "RS,RSY")])
1323 ; movstrictsi instruction pattern(s).
1326 (define_insn "movstrictsi"
1327 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1328 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1335 [(set_attr "op_type" "RR,RX,RXY,RRE")
1336 (set_attr "type" "lr,load,load,*")])
1339 ; movdf instruction pattern(s).
1342 (define_expand "movdf"
1343 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1344 (match_operand:DF 1 "general_operand" ""))]
1348 (define_insn "*movdf_64"
1349 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q")
1350 (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))]
1362 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1363 (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,*")])
1365 (define_insn "*movdf_31"
1366 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
1367 (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))]
1380 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
1381 (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,*")])
1384 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1385 (match_operand:DF 1 "general_operand" ""))]
1386 "!TARGET_64BIT && reload_completed
1387 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1388 [(set (match_dup 2) (match_dup 4))
1389 (set (match_dup 3) (match_dup 5))]
1391 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1392 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1393 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1394 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1398 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1399 (match_operand:DF 1 "general_operand" ""))]
1400 "!TARGET_64BIT && reload_completed
1401 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1402 [(set (match_dup 2) (match_dup 4))
1403 (set (match_dup 3) (match_dup 5))]
1405 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1406 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1407 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1408 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1412 [(set (match_operand:DF 0 "register_operand" "")
1413 (match_operand:DF 1 "memory_operand" ""))]
1414 "!TARGET_64BIT && reload_completed
1415 && !FP_REG_P (operands[0])
1416 && !s_operand (operands[1], VOIDmode)"
1417 [(set (match_dup 0) (match_dup 1))]
1419 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1420 s390_load_address (addr, XEXP (operands[1], 0));
1421 operands[1] = replace_equiv_address (operands[1], addr);
1424 (define_expand "reload_outdf"
1425 [(parallel [(match_operand:DF 0 "" "")
1426 (match_operand:DF 1 "register_operand" "d")
1427 (match_operand:SI 2 "register_operand" "=&a")])]
1430 gcc_assert (MEM_P (operands[0]));
1431 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1432 operands[0] = replace_equiv_address (operands[0], operands[2]);
1433 emit_move_insn (operands[0], operands[1]);
1438 ; movsf instruction pattern(s).
1441 (define_insn "movsf"
1442 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q")
1443 (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))]
1457 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1458 (set_attr "type" "floads,floads,floads,fstores,fstores,
1459 lr,load,load,store,store,*")])
1462 ; movcc instruction pattern
1465 (define_insn "movcc"
1466 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1467 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1477 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1478 (set_attr "type" "lr,*,*,store,store,load,load")])
1481 ; Block move (MVC) patterns.
1485 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1486 (match_operand:BLK 1 "memory_operand" "Q"))
1487 (use (match_operand 2 "const_int_operand" "n"))]
1488 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1489 "mvc\t%O0(%2,%R0),%S1"
1490 [(set_attr "op_type" "SS")])
1493 [(set (match_operand 0 "memory_operand" "")
1494 (match_operand 1 "memory_operand" ""))]
1496 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1497 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1499 [(set (match_dup 0) (match_dup 1))
1500 (use (match_dup 2))])]
1502 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1503 operands[0] = adjust_address (operands[0], BLKmode, 0);
1504 operands[1] = adjust_address (operands[1], BLKmode, 0);
1509 [(set (match_operand:BLK 0 "memory_operand" "")
1510 (match_operand:BLK 1 "memory_operand" ""))
1511 (use (match_operand 2 "const_int_operand" ""))])
1513 [(set (match_operand:BLK 3 "memory_operand" "")
1514 (match_operand:BLK 4 "memory_operand" ""))
1515 (use (match_operand 5 "const_int_operand" ""))])]
1516 "s390_offset_p (operands[0], operands[3], operands[2])
1517 && s390_offset_p (operands[1], operands[4], operands[2])
1518 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1520 [(set (match_dup 6) (match_dup 7))
1521 (use (match_dup 8))])]
1522 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1523 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1524 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1528 ; load_multiple pattern(s).
1530 ; ??? Due to reload problems with replacing registers inside match_parallel
1531 ; we currently support load_multiple/store_multiple only after reload.
1534 (define_expand "load_multiple"
1535 [(match_par_dup 3 [(set (match_operand 0 "" "")
1536 (match_operand 1 "" ""))
1537 (use (match_operand 2 "" ""))])]
1540 enum machine_mode mode;
1546 /* Support only loading a constant number of fixed-point registers from
1547 memory and only bother with this if more than two */
1548 if (GET_CODE (operands[2]) != CONST_INT
1549 || INTVAL (operands[2]) < 2
1550 || INTVAL (operands[2]) > 16
1551 || GET_CODE (operands[1]) != MEM
1552 || GET_CODE (operands[0]) != REG
1553 || REGNO (operands[0]) >= 16)
1556 count = INTVAL (operands[2]);
1557 regno = REGNO (operands[0]);
1558 mode = GET_MODE (operands[0]);
1559 if (mode != SImode && mode != word_mode)
1562 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1565 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1567 from = XEXP (operands[1], 0);
1570 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1571 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1572 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1574 from = XEXP (XEXP (operands[1], 0), 0);
1575 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1582 from = force_reg (Pmode, XEXP (operands[1], 0));
1586 for (i = 0; i < count; i++)
1587 XVECEXP (operands[3], 0, i)
1588 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1589 change_address (operands[1], mode,
1590 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1593 (define_insn "*load_multiple_di"
1594 [(match_parallel 0 "load_multiple_operation"
1595 [(set (match_operand:DI 1 "register_operand" "=r")
1596 (match_operand:DI 2 "s_operand" "QS"))])]
1597 "reload_completed && word_mode == DImode"
1599 int words = XVECLEN (operands[0], 0);
1600 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1601 return "lmg\t%1,%0,%S2";
1603 [(set_attr "op_type" "RSY")
1604 (set_attr "type" "lm")])
1606 (define_insn "*load_multiple_si"
1607 [(match_parallel 0 "load_multiple_operation"
1608 [(set (match_operand:SI 1 "register_operand" "=r,r")
1609 (match_operand:SI 2 "s_operand" "Q,S"))])]
1612 int words = XVECLEN (operands[0], 0);
1613 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1614 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1616 [(set_attr "op_type" "RS,RSY")
1617 (set_attr "type" "lm")])
1620 ; store multiple pattern(s).
1623 (define_expand "store_multiple"
1624 [(match_par_dup 3 [(set (match_operand 0 "" "")
1625 (match_operand 1 "" ""))
1626 (use (match_operand 2 "" ""))])]
1629 enum machine_mode mode;
1635 /* Support only storing a constant number of fixed-point registers to
1636 memory and only bother with this if more than two. */
1637 if (GET_CODE (operands[2]) != CONST_INT
1638 || INTVAL (operands[2]) < 2
1639 || INTVAL (operands[2]) > 16
1640 || GET_CODE (operands[0]) != MEM
1641 || GET_CODE (operands[1]) != REG
1642 || REGNO (operands[1]) >= 16)
1645 count = INTVAL (operands[2]);
1646 regno = REGNO (operands[1]);
1647 mode = GET_MODE (operands[1]);
1648 if (mode != SImode && mode != word_mode)
1651 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1655 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1657 to = XEXP (operands[0], 0);
1660 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1661 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1662 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1664 to = XEXP (XEXP (operands[0], 0), 0);
1665 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1672 to = force_reg (Pmode, XEXP (operands[0], 0));
1676 for (i = 0; i < count; i++)
1677 XVECEXP (operands[3], 0, i)
1678 = gen_rtx_SET (VOIDmode,
1679 change_address (operands[0], mode,
1680 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1681 gen_rtx_REG (mode, regno + i));
1684 (define_insn "*store_multiple_di"
1685 [(match_parallel 0 "store_multiple_operation"
1686 [(set (match_operand:DI 1 "s_operand" "=QS")
1687 (match_operand:DI 2 "register_operand" "r"))])]
1688 "reload_completed && word_mode == DImode"
1690 int words = XVECLEN (operands[0], 0);
1691 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1692 return "stmg\t%2,%0,%S1";
1694 [(set_attr "op_type" "RSY")
1695 (set_attr "type" "stm")])
1698 (define_insn "*store_multiple_si"
1699 [(match_parallel 0 "store_multiple_operation"
1700 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1701 (match_operand:SI 2 "register_operand" "r,r"))])]
1704 int words = XVECLEN (operands[0], 0);
1705 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1706 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1708 [(set_attr "op_type" "RS,RSY")
1709 (set_attr "type" "stm")])
1712 ;; String instructions.
1715 (define_insn "*execute"
1716 [(match_parallel 0 ""
1717 [(unspec [(match_operand 1 "register_operand" "a")
1718 (match_operand:BLK 2 "memory_operand" "R")
1719 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1720 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1721 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1723 [(set_attr "op_type" "RX")
1724 (set_attr "type" "cs")])
1728 ; strlenM instruction pattern(s).
1731 (define_expand "strlen<mode>"
1732 [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
1735 (unspec:P [(const_int 0)
1736 (match_operand:BLK 1 "memory_operand" "")
1738 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1739 (clobber (scratch:P))
1740 (clobber (reg:CC 33))])
1742 [(set (match_operand:P 0 "register_operand" "")
1743 (minus:P (match_dup 4) (match_dup 5)))
1744 (clobber (reg:CC 33))])]
1747 operands[4] = gen_reg_rtx (Pmode);
1748 operands[5] = gen_reg_rtx (Pmode);
1749 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1750 operands[1] = replace_equiv_address (operands[1], operands[5]);
1753 (define_insn "*strlen<mode>"
1754 [(set (match_operand:P 0 "register_operand" "=a")
1755 (unspec:P [(match_operand:P 2 "general_operand" "0")
1756 (mem:BLK (match_operand:P 3 "register_operand" "1"))
1758 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1759 (clobber (match_scratch:P 1 "=a"))
1760 (clobber (reg:CC 33))]
1762 "srst\t%0,%1\;jo\t.-4"
1763 [(set_attr "length" "8")
1764 (set_attr "type" "vs")])
1767 ; movmemM instruction pattern(s).
1770 (define_expand "movmem<mode>"
1771 [(set (match_operand:BLK 0 "memory_operand" "")
1772 (match_operand:BLK 1 "memory_operand" ""))
1773 (use (match_operand:GPR 2 "general_operand" ""))
1774 (match_operand 3 "" "")]
1776 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1778 ; Move a block that is up to 256 bytes in length.
1779 ; The block length is taken as (operands[2] % 256) + 1.
1781 (define_expand "movmem_short"
1783 [(set (match_operand:BLK 0 "memory_operand" "")
1784 (match_operand:BLK 1 "memory_operand" ""))
1785 (use (match_operand 2 "nonmemory_operand" ""))
1786 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1787 (clobber (match_dup 3))])]
1789 "operands[3] = gen_rtx_SCRATCH (Pmode);")
1791 (define_insn "*movmem_short"
1792 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1793 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
1794 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
1795 (use (match_operand 3 "immediate_operand" "X,R,X"))
1796 (clobber (match_scratch 4 "=X,X,&a"))]
1797 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
1798 && GET_MODE (operands[4]) == Pmode"
1800 [(set_attr "type" "cs")])
1803 [(set (match_operand:BLK 0 "memory_operand" "")
1804 (match_operand:BLK 1 "memory_operand" ""))
1805 (use (match_operand 2 "const_int_operand" ""))
1806 (use (match_operand 3 "immediate_operand" ""))
1807 (clobber (scratch))]
1810 [(set (match_dup 0) (match_dup 1))
1811 (use (match_dup 2))])]
1812 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
1815 [(set (match_operand:BLK 0 "memory_operand" "")
1816 (match_operand:BLK 1 "memory_operand" ""))
1817 (use (match_operand 2 "register_operand" ""))
1818 (use (match_operand 3 "memory_operand" ""))
1819 (clobber (scratch))]
1822 [(unspec [(match_dup 2) (match_dup 3)
1823 (const_int 0)] UNSPEC_EXECUTE)
1824 (set (match_dup 0) (match_dup 1))
1825 (use (const_int 1))])]
1829 [(set (match_operand:BLK 0 "memory_operand" "")
1830 (match_operand:BLK 1 "memory_operand" ""))
1831 (use (match_operand 2 "register_operand" ""))
1832 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1833 (clobber (match_operand 3 "register_operand" ""))]
1834 "reload_completed && TARGET_CPU_ZARCH"
1835 [(set (match_dup 3) (label_ref (match_dup 4)))
1837 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
1838 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
1839 (set (match_dup 0) (match_dup 1))
1840 (use (const_int 1))])]
1841 "operands[4] = gen_label_rtx ();")
1843 ; Move a block of arbitrary length.
1845 (define_expand "movmem_long"
1847 [(clobber (match_dup 2))
1848 (clobber (match_dup 3))
1849 (set (match_operand:BLK 0 "memory_operand" "")
1850 (match_operand:BLK 1 "memory_operand" ""))
1851 (use (match_operand 2 "general_operand" ""))
1853 (clobber (reg:CC 33))])]
1856 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
1857 rtx reg0 = gen_reg_rtx (dword_mode);
1858 rtx reg1 = gen_reg_rtx (dword_mode);
1859 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
1860 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
1861 rtx len0 = gen_lowpart (Pmode, reg0);
1862 rtx len1 = gen_lowpart (Pmode, reg1);
1864 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
1865 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
1866 emit_move_insn (len0, operands[2]);
1868 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
1869 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1870 emit_move_insn (len1, operands[2]);
1872 operands[0] = replace_equiv_address_nv (operands[0], addr0);
1873 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1878 (define_insn "*movmem_long_64"
1879 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1880 (clobber (match_operand:TI 1 "register_operand" "=d"))
1881 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1882 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))
1885 (clobber (reg:CC 33))]
1887 "mvcle\t%0,%1,0\;jo\t.-4"
1888 [(set_attr "length" "8")
1889 (set_attr "type" "vs")])
1891 (define_insn "*movmem_long_31"
1892 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1893 (clobber (match_operand:DI 1 "register_operand" "=d"))
1894 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1895 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))
1898 (clobber (reg:CC 33))]
1900 "mvcle\t%0,%1,0\;jo\t.-4"
1901 [(set_attr "length" "8")
1902 (set_attr "type" "vs")])
1905 ; clrmemM instruction pattern(s).
1908 (define_expand "clrmem<mode>"
1909 [(set (match_operand:BLK 0 "memory_operand" "")
1911 (use (match_operand:GPR 1 "general_operand" ""))
1912 (match_operand 2 "" "")]
1914 "s390_expand_clrmem (operands[0], operands[1]); DONE;")
1916 ; Clear a block that is up to 256 bytes in length.
1917 ; The block length is taken as (operands[1] % 256) + 1.
1919 (define_expand "clrmem_short"
1921 [(set (match_operand:BLK 0 "memory_operand" "")
1923 (use (match_operand 1 "nonmemory_operand" ""))
1924 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1925 (clobber (match_dup 2))
1926 (clobber (reg:CC 33))])]
1928 "operands[2] = gen_rtx_SCRATCH (Pmode);")
1930 (define_insn "*clrmem_short"
1931 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1933 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
1934 (use (match_operand 2 "immediate_operand" "X,R,X"))
1935 (clobber (match_scratch 3 "=X,X,&a"))
1936 (clobber (reg:CC 33))]
1937 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
1938 && GET_MODE (operands[3]) == Pmode"
1940 [(set_attr "type" "cs")])
1943 [(set (match_operand:BLK 0 "memory_operand" "")
1945 (use (match_operand 1 "const_int_operand" ""))
1946 (use (match_operand 2 "immediate_operand" ""))
1948 (clobber (reg:CC 33))]
1951 [(set (match_dup 0) (const_int 0))
1953 (clobber (reg:CC 33))])]
1954 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
1957 [(set (match_operand:BLK 0 "memory_operand" "")
1959 (use (match_operand 1 "register_operand" ""))
1960 (use (match_operand 2 "memory_operand" ""))
1962 (clobber (reg:CC 33))]
1965 [(unspec [(match_dup 1) (match_dup 2)
1966 (const_int 0)] UNSPEC_EXECUTE)
1967 (set (match_dup 0) (const_int 0))
1969 (clobber (reg:CC 33))])]
1973 [(set (match_operand:BLK 0 "memory_operand" "")
1975 (use (match_operand 1 "register_operand" ""))
1976 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1977 (clobber (match_operand 2 "register_operand" ""))
1978 (clobber (reg:CC 33))]
1979 "reload_completed && TARGET_CPU_ZARCH"
1980 [(set (match_dup 2) (label_ref (match_dup 3)))
1982 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
1983 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
1984 (set (match_dup 0) (const_int 0))
1986 (clobber (reg:CC 33))])]
1987 "operands[3] = gen_label_rtx ();")
1989 ; Clear a block of arbitrary length.
1991 (define_expand "clrmem_long"
1993 [(clobber (match_dup 1))
1994 (set (match_operand:BLK 0 "memory_operand" "")
1996 (use (match_operand 1 "general_operand" ""))
1998 (clobber (reg:CC 33))])]
2001 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2002 rtx reg0 = gen_reg_rtx (dword_mode);
2003 rtx reg1 = gen_reg_rtx (dword_mode);
2004 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2005 rtx len0 = gen_lowpart (Pmode, reg0);
2007 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2008 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2009 emit_move_insn (len0, operands[1]);
2011 emit_move_insn (reg1, const0_rtx);
2013 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2018 (define_insn "*clrmem_long_64"
2019 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2020 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2023 (use (match_operand:TI 1 "register_operand" "d"))
2024 (clobber (reg:CC 33))]
2026 "mvcle\t%0,%1,0\;jo\t.-4"
2027 [(set_attr "length" "8")
2028 (set_attr "type" "vs")])
2030 (define_insn "*clrmem_long_31"
2031 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2032 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2035 (use (match_operand:DI 1 "register_operand" "d"))
2036 (clobber (reg:CC 33))]
2038 "mvcle\t%0,%1,0\;jo\t.-4"
2039 [(set_attr "length" "8")
2040 (set_attr "type" "vs")])
2043 ; cmpmemM instruction pattern(s).
2046 (define_expand "cmpmemsi"
2047 [(set (match_operand:SI 0 "register_operand" "")
2048 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2049 (match_operand:BLK 2 "memory_operand" "") ) )
2050 (use (match_operand:SI 3 "general_operand" ""))
2051 (use (match_operand:SI 4 "" ""))]
2053 "s390_expand_cmpmem (operands[0], operands[1],
2054 operands[2], operands[3]); DONE;")
2056 ; Compare a block that is up to 256 bytes in length.
2057 ; The block length is taken as (operands[2] % 256) + 1.
2059 (define_expand "cmpmem_short"
2062 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2063 (match_operand:BLK 1 "memory_operand" "")))
2064 (use (match_operand 2 "nonmemory_operand" ""))
2065 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2066 (clobber (match_dup 3))])]
2068 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2070 (define_insn "*cmpmem_short"
2072 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2073 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2074 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2075 (use (match_operand 3 "immediate_operand" "X,R,X"))
2076 (clobber (match_scratch 4 "=X,X,&a"))]
2077 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2078 && GET_MODE (operands[4]) == Pmode"
2080 [(set_attr "type" "cs")])
2084 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2085 (match_operand:BLK 1 "memory_operand" "")))
2086 (use (match_operand 2 "const_int_operand" ""))
2087 (use (match_operand 3 "immediate_operand" ""))
2088 (clobber (scratch))]
2091 [(set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
2092 (use (match_dup 2))])]
2093 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2097 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2098 (match_operand:BLK 1 "memory_operand" "")))
2099 (use (match_operand 2 "register_operand" ""))
2100 (use (match_operand 3 "memory_operand" ""))
2101 (clobber (scratch))]
2104 [(unspec [(match_dup 2) (match_dup 3)
2105 (const_int 0)] UNSPEC_EXECUTE)
2106 (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
2107 (use (const_int 1))])]
2112 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2113 (match_operand:BLK 1 "memory_operand" "")))
2114 (use (match_operand 2 "register_operand" ""))
2115 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2116 (clobber (match_operand 3 "register_operand" ""))]
2117 "reload_completed && TARGET_CPU_ZARCH"
2118 [(set (match_dup 3) (label_ref (match_dup 4)))
2120 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2121 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2122 (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
2123 (use (const_int 1))])]
2124 "operands[4] = gen_label_rtx ();")
2126 ; Compare a block of arbitrary length.
2128 (define_expand "cmpmem_long"
2130 [(clobber (match_dup 2))
2131 (clobber (match_dup 3))
2133 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2134 (match_operand:BLK 1 "memory_operand" "")))
2135 (use (match_operand 2 "general_operand" ""))
2136 (use (match_dup 3))])]
2139 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2140 rtx reg0 = gen_reg_rtx (dword_mode);
2141 rtx reg1 = gen_reg_rtx (dword_mode);
2142 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2143 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2144 rtx len0 = gen_lowpart (Pmode, reg0);
2145 rtx len1 = gen_lowpart (Pmode, reg1);
2147 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2148 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2149 emit_move_insn (len0, operands[2]);
2151 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2152 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2153 emit_move_insn (len1, operands[2]);
2155 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2156 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2161 (define_insn "*cmpmem_long_64"
2162 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2163 (clobber (match_operand:TI 1 "register_operand" "=d"))
2165 (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2166 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
2168 (use (match_dup 3))]
2170 "clcle\t%0,%1,0\;jo\t.-4"
2171 [(set_attr "length" "8")
2172 (set_attr "type" "vs")])
2174 (define_insn "*cmpmem_long_31"
2175 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2176 (clobber (match_operand:DI 1 "register_operand" "=d"))
2178 (compare:CCU (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2179 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
2181 (use (match_dup 3))]
2183 "clcle\t%0,%1,0\;jo\t.-4"
2184 [(set_attr "length" "8")
2185 (set_attr "type" "vs")])
2187 ; Convert CCUmode condition code to integer.
2188 ; Result is zero if EQ, positive if LTU, negative if GTU.
2190 (define_insn_and_split "cmpint"
2191 [(set (match_operand:SI 0 "register_operand" "=d")
2192 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2194 (clobber (reg:CC 33))]
2198 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2200 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2201 (clobber (reg:CC 33))])])
2203 (define_insn_and_split "*cmpint_cc"
2205 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2208 (set (match_operand:SI 0 "register_operand" "=d")
2209 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2210 "s390_match_ccmode (insn, CCSmode)"
2212 "&& reload_completed"
2213 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2215 [(set (match_dup 2) (match_dup 3))
2216 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2218 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2219 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2220 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2223 (define_insn_and_split "*cmpint_sign"
2224 [(set (match_operand:DI 0 "register_operand" "=d")
2225 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2227 (clobber (reg:CC 33))]
2230 "&& reload_completed"
2231 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2233 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2234 (clobber (reg:CC 33))])])
2236 (define_insn_and_split "*cmpint_sign_cc"
2238 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2239 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2241 (const_int 32)) (const_int 32))
2243 (set (match_operand:DI 0 "register_operand" "=d")
2244 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2245 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2247 "&& reload_completed"
2248 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2250 [(set (match_dup 2) (match_dup 3))
2251 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2253 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2254 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2255 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2260 ;;- Conversion instructions.
2264 (define_insn "*sethigh<mode>si"
2265 [(set (match_operand:SI 0 "register_operand" "=d,d")
2266 (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2267 (clobber (reg:CC 33))]
2270 icm\t%0,<icm_hi>,%S1
2271 icmy\t%0,<icm_hi>,%S1"
2272 [(set_attr "op_type" "RS,RSY")])
2274 (define_insn "*sethighqidi_64"
2275 [(set (match_operand:DI 0 "register_operand" "=d")
2276 (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
2277 (clobber (reg:CC 33))]
2280 [(set_attr "op_type" "RSY")])
2282 (define_insn "*sethighqidi_31"
2283 [(set (match_operand:DI 0 "register_operand" "=d,d")
2284 (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2285 (clobber (reg:CC 33))]
2290 [(set_attr "op_type" "RS,RSY")])
2292 (define_insn_and_split "*extractqi"
2293 [(set (match_operand:SI 0 "register_operand" "=d")
2294 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2295 (match_operand 2 "const_int_operand" "n")
2297 (clobber (reg:CC 33))]
2299 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2301 "&& reload_completed"
2303 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2304 (clobber (reg:CC 33))])
2305 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2307 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2308 operands[1] = change_address (operands[1], QImode, 0);
2311 (define_insn_and_split "*extracthi"
2312 [(set (match_operand:SI 0 "register_operand" "=d")
2313 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2314 (match_operand 2 "const_int_operand" "n")
2316 (clobber (reg:CC 33))]
2318 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2320 "&& reload_completed"
2322 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2323 (clobber (reg:CC 33))])
2324 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2326 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2327 operands[1] = change_address (operands[1], HImode, 0);
2331 ; extendsidi2 instruction pattern(s).
2334 (define_expand "extendsidi2"
2335 [(set (match_operand:DI 0 "register_operand" "")
2336 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2342 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2343 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2344 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2345 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2351 (define_insn "*extendsidi2"
2352 [(set (match_operand:DI 0 "register_operand" "=d,d")
2353 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2358 [(set_attr "op_type" "RRE,RXY")])
2361 ; extendhidi2 instruction pattern(s).
2364 (define_expand "extendhidi2"
2365 [(set (match_operand:DI 0 "register_operand" "")
2366 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2372 rtx tmp = gen_reg_rtx (SImode);
2373 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2374 emit_insn (gen_extendsidi2 (operands[0], tmp));
2379 operands[1] = gen_lowpart (DImode, operands[1]);
2380 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2381 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2387 (define_insn "*extendhidi2"
2388 [(set (match_operand:DI 0 "register_operand" "=d")
2389 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2392 [(set_attr "op_type" "RXY")])
2395 ; extendqidi2 instruction pattern(s).
2398 (define_expand "extendqidi2"
2399 [(set (match_operand:DI 0 "register_operand" "")
2400 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2406 rtx tmp = gen_reg_rtx (SImode);
2407 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2408 emit_insn (gen_extendsidi2 (operands[0], tmp));
2413 operands[1] = gen_lowpart (DImode, operands[1]);
2414 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2415 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2421 (define_insn "*extendqidi2"
2422 [(set (match_operand:DI 0 "register_operand" "=d")
2423 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2424 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2426 [(set_attr "op_type" "RXY")])
2428 (define_insn_and_split "*extendqidi2_short_displ"
2429 [(set (match_operand:DI 0 "register_operand" "=d")
2430 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2431 (clobber (reg:CC 33))]
2432 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2434 "&& reload_completed"
2436 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
2437 (clobber (reg:CC 33))])
2439 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2440 (clobber (reg:CC 33))])]
2444 ; extendhisi2 instruction pattern(s).
2447 (define_expand "extendhisi2"
2448 [(set (match_operand:SI 0 "register_operand" "")
2449 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2453 operands[1] = gen_lowpart (SImode, operands[1]);
2454 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2455 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2460 (define_insn "*extendhisi2"
2461 [(set (match_operand:SI 0 "register_operand" "=d,d")
2462 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2467 [(set_attr "op_type" "RX,RXY")])
2470 ; extendqisi2 instruction pattern(s).
2473 (define_expand "extendqisi2"
2474 [(set (match_operand:SI 0 "register_operand" "")
2475 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2479 operands[1] = gen_lowpart (SImode, operands[1]);
2480 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2481 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2486 (define_insn "*extendqisi2"
2487 [(set (match_operand:SI 0 "register_operand" "=d")
2488 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2489 "TARGET_LONG_DISPLACEMENT"
2491 [(set_attr "op_type" "RXY")])
2493 (define_insn_and_split "*extendqisi2_short_displ"
2494 [(set (match_operand:SI 0 "register_operand" "=d")
2495 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2496 (clobber (reg:CC 33))]
2497 "!TARGET_LONG_DISPLACEMENT"
2499 "&& reload_completed"
2501 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2502 (clobber (reg:CC 33))])
2504 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2505 (clobber (reg:CC 33))])]
2509 ; extendqihi2 instruction pattern(s).
2514 ; zero_extendsidi2 instruction pattern(s).
2517 (define_expand "zero_extendsidi2"
2518 [(set (match_operand:DI 0 "register_operand" "")
2519 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2525 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2526 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2527 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2533 (define_insn "*zero_extendsidi2"
2534 [(set (match_operand:DI 0 "register_operand" "=d,d")
2535 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2540 [(set_attr "op_type" "RRE,RXY")])
2543 ; zero_extendhidi2 instruction pattern(s).
2546 (define_expand "zero_extendhidi2"
2547 [(set (match_operand:DI 0 "register_operand" "")
2548 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2554 rtx tmp = gen_reg_rtx (SImode);
2555 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2556 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2561 operands[1] = gen_lowpart (DImode, operands[1]);
2562 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2563 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2569 (define_insn "*zero_extendhidi2"
2570 [(set (match_operand:DI 0 "register_operand" "=d")
2571 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2574 [(set_attr "op_type" "RXY")])
2577 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2580 (define_insn "*llgt_sidi"
2581 [(set (match_operand:DI 0 "register_operand" "=d")
2582 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2583 (const_int 2147483647)))]
2586 [(set_attr "op_type" "RXE")])
2588 (define_insn_and_split "*llgt_sidi_split"
2589 [(set (match_operand:DI 0 "register_operand" "=d")
2590 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2591 (const_int 2147483647)))
2592 (clobber (reg:CC 33))]
2595 "&& reload_completed"
2597 (and:DI (subreg:DI (match_dup 1) 0)
2598 (const_int 2147483647)))]
2601 (define_insn "*llgt_sisi"
2602 [(set (match_operand:SI 0 "register_operand" "=d,d")
2603 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2604 (const_int 2147483647)))]
2609 [(set_attr "op_type" "RRE,RXE")])
2612 [(set (match_operand:SI 0 "register_operand" "")
2613 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
2614 (const_int 2147483647)))
2615 (clobber (reg:CC 33))]
2616 "TARGET_64BIT && reload_completed"
2618 (and:SI (match_dup 1)
2619 (const_int 2147483647)))]
2622 (define_insn "*llgt_didi"
2623 [(set (match_operand:DI 0 "register_operand" "=d,d")
2624 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2625 (const_int 2147483647)))]
2630 [(set_attr "op_type" "RRE,RXE")])
2633 [(set (match_operand:DI 0 "register_operand" "")
2634 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
2635 (const_int 2147483647)))
2636 (clobber (reg:CC 33))]
2637 "TARGET_64BIT && reload_completed"
2639 (and:DI (match_dup 1)
2640 (const_int 2147483647)))]
2644 ; zero_extendqidi2 instruction pattern(s)
2647 (define_expand "zero_extendqidi2"
2648 [(set (match_operand:DI 0 "register_operand" "")
2649 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2655 rtx tmp = gen_reg_rtx (SImode);
2656 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2657 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2662 operands[1] = gen_lowpart (DImode, operands[1]);
2663 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2664 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2670 (define_insn "*zero_extendqidi2"
2671 [(set (match_operand:DI 0 "register_operand" "=d")
2672 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2675 [(set_attr "op_type" "RXY")])
2678 ; zero_extendhisi2 instruction pattern(s).
2681 (define_expand "zero_extendhisi2"
2682 [(set (match_operand:SI 0 "register_operand" "")
2683 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2687 operands[1] = gen_lowpart (SImode, operands[1]);
2688 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2693 (define_insn "*zero_extendhisi2_64"
2694 [(set (match_operand:SI 0 "register_operand" "=d")
2695 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2698 [(set_attr "op_type" "RXY")])
2700 (define_insn_and_split "*zero_extendhisi2_31"
2701 [(set (match_operand:SI 0 "register_operand" "=&d")
2702 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2703 (clobber (reg:CC 33))]
2706 "&& reload_completed"
2707 [(set (match_dup 0) (const_int 0))
2709 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2710 (clobber (reg:CC 33))])]
2711 "operands[2] = gen_lowpart (HImode, operands[0]);")
2714 ; zero_extendqisi2 instruction pattern(s).
2717 (define_expand "zero_extendqisi2"
2718 [(set (match_operand:SI 0 "register_operand" "")
2719 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2723 operands[1] = gen_lowpart (SImode, operands[1]);
2724 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2729 (define_insn "*zero_extendqisi2_64"
2730 [(set (match_operand:SI 0 "register_operand" "=d")
2731 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2734 [(set_attr "op_type" "RXY")])
2736 (define_insn_and_split "*zero_extendqisi2_31"
2737 [(set (match_operand:SI 0 "register_operand" "=&d")
2738 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2741 "&& reload_completed"
2742 [(set (match_dup 0) (const_int 0))
2743 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2744 "operands[2] = gen_lowpart (QImode, operands[0]);")
2747 ; zero_extendqihi2 instruction pattern(s).
2750 (define_expand "zero_extendqihi2"
2751 [(set (match_operand:HI 0 "register_operand" "")
2752 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2756 operands[1] = gen_lowpart (HImode, operands[1]);
2757 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2762 (define_insn "*zero_extendqihi2_64"
2763 [(set (match_operand:HI 0 "register_operand" "=d")
2764 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2767 [(set_attr "op_type" "RXY")])
2769 (define_insn_and_split "*zero_extendqihi2_31"
2770 [(set (match_operand:HI 0 "register_operand" "=&d")
2771 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2774 "&& reload_completed"
2775 [(set (match_dup 0) (const_int 0))
2776 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2777 "operands[2] = gen_lowpart (QImode, operands[0]);")
2781 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2784 (define_expand "fixuns_truncdfdi2"
2785 [(set (match_operand:DI 0 "register_operand" "")
2786 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2787 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2789 rtx label1 = gen_label_rtx ();
2790 rtx label2 = gen_label_rtx ();
2791 rtx temp = gen_reg_rtx (DFmode);
2792 operands[1] = force_reg (DFmode, operands[1]);
2794 emit_insn (gen_cmpdf (operands[1],
2795 CONST_DOUBLE_FROM_REAL_VALUE (
2796 REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode)));
2797 emit_jump_insn (gen_blt (label1));
2798 emit_insn (gen_subdf3 (temp, operands[1],
2799 CONST_DOUBLE_FROM_REAL_VALUE (
2800 REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode)));
2801 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2804 emit_label (label1);
2805 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2806 emit_label (label2);
2810 (define_expand "fix_truncdfdi2"
2811 [(set (match_operand:DI 0 "register_operand" "")
2812 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2813 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2815 operands[1] = force_reg (DFmode, operands[1]);
2816 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2820 (define_insn "fix_truncdfdi2_ieee"
2821 [(set (match_operand:DI 0 "register_operand" "=d")
2822 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2823 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2824 (clobber (reg:CC 33))]
2825 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2827 [(set_attr "op_type" "RRE")
2828 (set_attr "type" "ftoi")])
2831 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2834 (define_expand "fixuns_truncdfsi2"
2835 [(set (match_operand:SI 0 "register_operand" "")
2836 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2837 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2839 rtx label1 = gen_label_rtx ();
2840 rtx label2 = gen_label_rtx ();
2841 rtx temp = gen_reg_rtx (DFmode);
2843 operands[1] = force_reg (DFmode,operands[1]);
2844 emit_insn (gen_cmpdf (operands[1],
2845 CONST_DOUBLE_FROM_REAL_VALUE (
2846 REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode)));
2847 emit_jump_insn (gen_blt (label1));
2848 emit_insn (gen_subdf3 (temp, operands[1],
2849 CONST_DOUBLE_FROM_REAL_VALUE (
2850 REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode)));
2851 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2854 emit_label (label1);
2855 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2856 emit_label (label2);
2860 (define_expand "fix_truncdfsi2"
2861 [(set (match_operand:SI 0 "register_operand" "")
2862 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2865 if (TARGET_IBM_FLOAT)
2867 /* This is the algorithm from POP chapter A.5.7.2. */
2869 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2870 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2871 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2873 operands[1] = force_reg (DFmode, operands[1]);
2874 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2875 two31r, two32, temp));
2879 operands[1] = force_reg (DFmode, operands[1]);
2880 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2886 (define_insn "fix_truncdfsi2_ieee"
2887 [(set (match_operand:SI 0 "register_operand" "=d")
2888 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2889 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2890 (clobber (reg:CC 33))]
2891 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2893 [(set_attr "op_type" "RRE")
2894 (set_attr "type" "ftoi")])
2896 (define_insn "fix_truncdfsi2_ibm"
2897 [(set (match_operand:SI 0 "register_operand" "=d")
2898 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2899 (use (match_operand:DI 2 "immediate_operand" "m"))
2900 (use (match_operand:DI 3 "immediate_operand" "m"))
2901 (use (match_operand:BLK 4 "memory_operand" "m"))
2902 (clobber (reg:CC 33))]
2903 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2905 output_asm_insn ("sd\t%1,%2", operands);
2906 output_asm_insn ("aw\t%1,%3", operands);
2907 output_asm_insn ("std\t%1,%4", operands);
2908 output_asm_insn ("xi\t%N4,128", operands);
2911 [(set_attr "length" "20")])
2914 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2917 (define_expand "fixuns_truncsfdi2"
2918 [(set (match_operand:DI 0 "register_operand" "")
2919 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2920 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2922 rtx label1 = gen_label_rtx ();
2923 rtx label2 = gen_label_rtx ();
2924 rtx temp = gen_reg_rtx (SFmode);
2926 operands[1] = force_reg (SFmode, operands[1]);
2927 emit_insn (gen_cmpsf (operands[1],
2928 CONST_DOUBLE_FROM_REAL_VALUE (
2929 REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode)));
2930 emit_jump_insn (gen_blt (label1));
2932 emit_insn (gen_subsf3 (temp, operands[1],
2933 CONST_DOUBLE_FROM_REAL_VALUE (
2934 REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode)));
2935 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2938 emit_label (label1);
2939 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2940 emit_label (label2);
2944 (define_expand "fix_truncsfdi2"
2945 [(set (match_operand:DI 0 "register_operand" "")
2946 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2947 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2949 operands[1] = force_reg (SFmode, operands[1]);
2950 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2954 (define_insn "fix_truncsfdi2_ieee"
2955 [(set (match_operand:DI 0 "register_operand" "=d")
2956 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2957 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2958 (clobber (reg:CC 33))]
2959 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2961 [(set_attr "op_type" "RRE")
2962 (set_attr "type" "ftoi")])
2965 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2968 (define_expand "fixuns_truncsfsi2"
2969 [(set (match_operand:SI 0 "register_operand" "")
2970 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2971 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2973 rtx label1 = gen_label_rtx ();
2974 rtx label2 = gen_label_rtx ();
2975 rtx temp = gen_reg_rtx (SFmode);
2977 operands[1] = force_reg (SFmode, operands[1]);
2978 emit_insn (gen_cmpsf (operands[1],
2979 CONST_DOUBLE_FROM_REAL_VALUE (
2980 REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode)));
2981 emit_jump_insn (gen_blt (label1));
2982 emit_insn (gen_subsf3 (temp, operands[1],
2983 CONST_DOUBLE_FROM_REAL_VALUE (
2984 REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode)));
2985 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2988 emit_label (label1);
2989 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2990 emit_label (label2);
2994 (define_expand "fix_truncsfsi2"
2995 [(set (match_operand:SI 0 "register_operand" "")
2996 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2999 if (TARGET_IBM_FLOAT)
3001 /* Convert to DFmode and then use the POP algorithm. */
3002 rtx temp = gen_reg_rtx (DFmode);
3003 emit_insn (gen_extendsfdf2 (temp, operands[1]));
3004 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
3008 operands[1] = force_reg (SFmode, operands[1]);
3009 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3015 (define_insn "fix_truncsfsi2_ieee"
3016 [(set (match_operand:SI 0 "register_operand" "=d")
3017 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3018 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3019 (clobber (reg:CC 33))]
3020 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3022 [(set_attr "op_type" "RRE")
3023 (set_attr "type" "ftoi")])
3026 ; floatdidf2 instruction pattern(s).
3029 (define_insn "floatdidf2"
3030 [(set (match_operand:DF 0 "register_operand" "=f")
3031 (float:DF (match_operand:DI 1 "register_operand" "d")))]
3032 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3034 [(set_attr "op_type" "RRE")
3035 (set_attr "type" "itof" )])
3038 ; floatdisf2 instruction pattern(s).
3041 (define_insn "floatdisf2"
3042 [(set (match_operand:SF 0 "register_operand" "=f")
3043 (float:SF (match_operand:DI 1 "register_operand" "d")))]
3044 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3046 [(set_attr "op_type" "RRE")
3047 (set_attr "type" "itof" )])
3050 ; floatsidf2 instruction pattern(s).
3053 (define_expand "floatsidf2"
3054 [(set (match_operand:DF 0 "register_operand" "")
3055 (float:DF (match_operand:SI 1 "register_operand" "")))]
3058 if (TARGET_IBM_FLOAT)
3060 /* This is the algorithm from POP chapter A.5.7.1. */
3062 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3063 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
3065 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
3070 (define_insn "floatsidf2_ieee"
3071 [(set (match_operand:DF 0 "register_operand" "=f")
3072 (float:DF (match_operand:SI 1 "register_operand" "d")))]
3073 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3075 [(set_attr "op_type" "RRE")
3076 (set_attr "type" "itof" )])
3078 (define_insn "floatsidf2_ibm"
3079 [(set (match_operand:DF 0 "register_operand" "=f")
3080 (float:DF (match_operand:SI 1 "register_operand" "d")))
3081 (use (match_operand:DI 2 "immediate_operand" "m"))
3082 (use (match_operand:BLK 3 "memory_operand" "m"))
3083 (clobber (reg:CC 33))]
3084 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3086 output_asm_insn ("st\t%1,%N3", operands);
3087 output_asm_insn ("xi\t%N3,128", operands);
3088 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
3089 output_asm_insn ("ld\t%0,%3", operands);
3092 [(set_attr "length" "20")])
3095 ; floatsisf2 instruction pattern(s).
3098 (define_expand "floatsisf2"
3099 [(set (match_operand:SF 0 "register_operand" "")
3100 (float:SF (match_operand:SI 1 "register_operand" "")))]
3103 if (TARGET_IBM_FLOAT)
3105 /* Use the POP algorithm to convert to DFmode and then truncate. */
3106 rtx temp = gen_reg_rtx (DFmode);
3107 emit_insn (gen_floatsidf2 (temp, operands[1]));
3108 emit_insn (gen_truncdfsf2 (operands[0], temp));
3113 (define_insn "floatsisf2_ieee"
3114 [(set (match_operand:SF 0 "register_operand" "=f")
3115 (float:SF (match_operand:SI 1 "register_operand" "d")))]
3116 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3118 [(set_attr "op_type" "RRE")
3119 (set_attr "type" "itof" )])
3122 ; truncdfsf2 instruction pattern(s).
3125 (define_expand "truncdfsf2"
3126 [(set (match_operand:SF 0 "register_operand" "")
3127 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
3131 (define_insn "truncdfsf2_ieee"
3132 [(set (match_operand:SF 0 "register_operand" "=f")
3133 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3134 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3136 [(set_attr "op_type" "RRE")])
3138 (define_insn "truncdfsf2_ibm"
3139 [(set (match_operand:SF 0 "register_operand" "=f,f")
3140 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3141 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3145 [(set_attr "op_type" "RR,RX")
3146 (set_attr "type" "floads,floads")])
3149 ; extendsfdf2 instruction pattern(s).
3152 (define_expand "extendsfdf2"
3153 [(set (match_operand:DF 0 "register_operand" "")
3154 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3157 if (TARGET_IBM_FLOAT)
3159 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3164 (define_insn "extendsfdf2_ieee"
3165 [(set (match_operand:DF 0 "register_operand" "=f,f")
3166 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3167 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3171 [(set_attr "op_type" "RRE,RXE")
3172 (set_attr "type" "floads,floads")])
3174 (define_insn "extendsfdf2_ibm"
3175 [(set (match_operand:DF 0 "register_operand" "=f,f")
3176 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
3177 (clobber (reg:CC 33))]
3178 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3180 sdr\t%0,%0\;ler\t%0,%1
3181 sdr\t%0,%0\;le\t%0,%1"
3182 [(set_attr "length" "4,6")
3183 (set_attr "type" "floads,floads")])
3187 ;; ARITHMETIC OPERATIONS
3189 ; arithmetic operations set the ConditionCode,
3190 ; because of unpredictable Bits in Register for Halfword and Byte
3191 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3194 ;;- Add instructions.
3198 ; addti3 instruction pattern(s).
3201 (define_insn_and_split "addti3"
3202 [(set (match_operand:TI 0 "register_operand" "=&d")
3203 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3204 (match_operand:TI 2 "general_operand" "do") ) )
3205 (clobber (reg:CC 33))]
3208 "&& reload_completed"
3211 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3213 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3215 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3216 (ltu:DI (reg:CCL1 33) (const_int 0))))
3217 (clobber (reg:CC 33))])]
3218 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3219 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3220 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3221 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3222 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3223 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3226 ; adddi3 instruction pattern(s).
3229 (define_insn "*adddi3_sign"
3230 [(set (match_operand:DI 0 "register_operand" "=d,d")
3231 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3232 (match_operand:DI 1 "register_operand" "0,0")))
3233 (clobber (reg:CC 33))]
3238 [(set_attr "op_type" "RRE,RXY")])
3240 (define_insn "*adddi3_zero_cc"
3242 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3243 (match_operand:DI 1 "register_operand" "0,0"))
3245 (set (match_operand:DI 0 "register_operand" "=d,d")
3246 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3247 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3251 [(set_attr "op_type" "RRE,RXY")])
3253 (define_insn "*adddi3_zero_cconly"
3255 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3256 (match_operand:DI 1 "register_operand" "0,0"))
3258 (clobber (match_scratch:DI 0 "=d,d"))]
3259 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3263 [(set_attr "op_type" "RRE,RXY")])
3265 (define_insn "*adddi3_zero"
3266 [(set (match_operand:DI 0 "register_operand" "=d,d")
3267 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3268 (match_operand:DI 1 "register_operand" "0,0")))
3269 (clobber (reg:CC 33))]
3274 [(set_attr "op_type" "RRE,RXY")])
3276 (define_insn "*adddi3_imm_cc"
3278 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
3279 (match_operand:DI 2 "const_int_operand" "K"))
3281 (set (match_operand:DI 0 "register_operand" "=d")
3282 (plus:DI (match_dup 1) (match_dup 2)))]
3284 && s390_match_ccmode (insn, CCAmode)
3285 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3287 [(set_attr "op_type" "RI")])
3289 (define_insn "*adddi3_carry1_cc"
3291 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3292 (match_operand:DI 2 "general_operand" "d,m"))
3294 (set (match_operand:DI 0 "register_operand" "=d,d")
3295 (plus:DI (match_dup 1) (match_dup 2)))]
3296 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3300 [(set_attr "op_type" "RRE,RXY")])
3302 (define_insn "*adddi3_carry1_cconly"
3304 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3305 (match_operand:DI 2 "general_operand" "d,m"))
3307 (clobber (match_scratch:DI 0 "=d,d"))]
3308 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3312 [(set_attr "op_type" "RRE,RXY")])
3314 (define_insn "*adddi3_carry2_cc"
3316 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3317 (match_operand:DI 2 "general_operand" "d,m"))
3319 (set (match_operand:DI 0 "register_operand" "=d,d")
3320 (plus:DI (match_dup 1) (match_dup 2)))]
3321 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3325 [(set_attr "op_type" "RRE,RXY")])
3327 (define_insn "*adddi3_carry2_cconly"
3329 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3330 (match_operand:DI 2 "general_operand" "d,m"))
3332 (clobber (match_scratch:DI 0 "=d,d"))]
3333 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3337 [(set_attr "op_type" "RRE,RXY")])
3339 (define_insn "*adddi3_cc"
3341 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3342 (match_operand:DI 2 "general_operand" "d,m"))
3344 (set (match_operand:DI 0 "register_operand" "=d,d")
3345 (plus:DI (match_dup 1) (match_dup 2)))]
3346 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3350 [(set_attr "op_type" "RRE,RXY")])
3352 (define_insn "*adddi3_cconly"
3354 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3355 (match_operand:DI 2 "general_operand" "d,m"))
3357 (clobber (match_scratch:DI 0 "=d,d"))]
3358 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3362 [(set_attr "op_type" "RRE,RXY")])
3364 (define_insn "*adddi3_cconly2"
3366 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3367 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3368 (clobber (match_scratch:DI 0 "=d,d"))]
3369 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3373 [(set_attr "op_type" "RRE,RXY")])
3375 (define_insn "*adddi3_64"
3376 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3377 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3378 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3379 (clobber (reg:CC 33))]
3385 [(set_attr "op_type" "RRE,RI,RXY")])
3387 (define_insn_and_split "*adddi3_31z"
3388 [(set (match_operand:DI 0 "register_operand" "=&d")
3389 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3390 (match_operand:DI 2 "general_operand" "do") ) )
3391 (clobber (reg:CC 33))]
3392 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3394 "&& reload_completed"
3397 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3399 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3401 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3402 (ltu:SI (reg:CCL1 33) (const_int 0))))
3403 (clobber (reg:CC 33))])]
3404 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3405 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3406 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3407 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3408 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3409 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3411 (define_insn_and_split "*adddi3_31"
3412 [(set (match_operand:DI 0 "register_operand" "=&d")
3413 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3414 (match_operand:DI 2 "general_operand" "do") ) )
3415 (clobber (reg:CC 33))]
3418 "&& reload_completed"
3420 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3421 (clobber (reg:CC 33))])
3424 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3426 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3428 (if_then_else (ltu (reg:CCL1 33) (const_int 0))
3430 (label_ref (match_dup 9))))
3432 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3433 (clobber (reg:CC 33))])
3435 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3436 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3437 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3438 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3439 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3440 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3441 operands[9] = gen_label_rtx ();")
3443 (define_expand "adddi3"
3445 [(set (match_operand:DI 0 "register_operand" "")
3446 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3447 (match_operand:DI 2 "general_operand" "")))
3448 (clobber (reg:CC 33))])]
3453 ; addsi3 instruction pattern(s).
3456 (define_insn "*addsi3_imm_cc"
3458 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3459 (match_operand:SI 2 "const_int_operand" "K"))
3461 (set (match_operand:SI 0 "register_operand" "=d")
3462 (plus:SI (match_dup 1) (match_dup 2)))]
3463 "s390_match_ccmode (insn, CCAmode)
3464 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3466 [(set_attr "op_type" "RI")])
3468 (define_insn "*addsi3_carry1_cc"
3470 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3471 (match_operand:SI 2 "general_operand" "d,R,T"))
3473 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3474 (plus:SI (match_dup 1) (match_dup 2)))]
3475 "s390_match_ccmode (insn, CCL1mode)"
3480 [(set_attr "op_type" "RR,RX,RXY")])
3482 (define_insn "*addsi3_carry1_cconly"
3484 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3485 (match_operand:SI 2 "general_operand" "d,R,T"))
3487 (clobber (match_scratch:SI 0 "=d,d,d"))]
3488 "s390_match_ccmode (insn, CCL1mode)"
3493 [(set_attr "op_type" "RR,RX,RXY")])
3495 (define_insn "*addsi3_carry2_cc"
3497 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3498 (match_operand:SI 2 "general_operand" "d,R,T"))
3500 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3501 (plus:SI (match_dup 1) (match_dup 2)))]
3502 "s390_match_ccmode (insn, CCL1mode)"
3507 [(set_attr "op_type" "RR,RX,RXY")])
3509 (define_insn "*addsi3_carry2_cconly"
3511 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3512 (match_operand:SI 2 "general_operand" "d,R,T"))
3514 (clobber (match_scratch:SI 0 "=d,d,d"))]
3515 "s390_match_ccmode (insn, CCL1mode)"
3520 [(set_attr "op_type" "RR,RX,RXY")])
3522 (define_insn "*addsi3_cc"
3524 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3525 (match_operand:SI 2 "general_operand" "d,R,T"))
3527 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3528 (plus:SI (match_dup 1) (match_dup 2)))]
3529 "s390_match_ccmode (insn, CCLmode)"
3534 [(set_attr "op_type" "RR,RX,RXY")])
3536 (define_insn "*addsi3_cconly"
3538 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3539 (match_operand:SI 2 "general_operand" "d,R,T"))
3541 (clobber (match_scratch:SI 0 "=d,d,d"))]
3542 "s390_match_ccmode (insn, CCLmode)"
3547 [(set_attr "op_type" "RR,RX,RXY")])
3549 (define_insn "*addsi3_cconly2"
3551 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3552 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3553 (clobber (match_scratch:SI 0 "=d,d,d"))]
3554 "s390_match_ccmode (insn, CCLmode)"
3559 [(set_attr "op_type" "RR,RX,RXY")])
3561 (define_insn "*addsi3_sign"
3562 [(set (match_operand:SI 0 "register_operand" "=d,d")
3563 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3564 (match_operand:SI 1 "register_operand" "0,0")))
3565 (clobber (reg:CC 33))]
3570 [(set_attr "op_type" "RX,RXY")])
3572 (define_insn "addsi3"
3573 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3574 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3575 (match_operand:SI 2 "general_operand" "d,K,R,T")))
3576 (clobber (reg:CC 33))]
3583 [(set_attr "op_type" "RR,RI,RX,RXY")])
3586 ; adddf3 instruction pattern(s).
3589 (define_expand "adddf3"
3591 [(set (match_operand:DF 0 "register_operand" "=f,f")
3592 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3593 (match_operand:DF 2 "general_operand" "f,R")))
3594 (clobber (reg:CC 33))])]
3598 (define_insn "*adddf3"
3599 [(set (match_operand:DF 0 "register_operand" "=f,f")
3600 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3601 (match_operand:DF 2 "general_operand" "f,R")))
3602 (clobber (reg:CC 33))]
3603 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3607 [(set_attr "op_type" "RRE,RXE")
3608 (set_attr "type" "fsimpd,fsimpd")])
3610 (define_insn "*adddf3_cc"
3612 (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3613 (match_operand:DF 2 "general_operand" "f,R"))
3614 (match_operand:DF 3 "const0_operand" "")))
3615 (set (match_operand:DF 0 "register_operand" "=f,f")
3616 (plus:DF (match_dup 1) (match_dup 2)))]
3617 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3621 [(set_attr "op_type" "RRE,RXE")
3622 (set_attr "type" "fsimpd,fsimpd")])
3624 (define_insn "*adddf3_cconly"
3626 (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3627 (match_operand:DF 2 "general_operand" "f,R"))
3628 (match_operand:DF 3 "const0_operand" "")))
3629 (clobber (match_scratch:DF 0 "=f,f"))]
3630 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3634 [(set_attr "op_type" "RRE,RXE")
3635 (set_attr "type" "fsimpd,fsimpd")])
3637 (define_insn "*adddf3_ibm"
3638 [(set (match_operand:DF 0 "register_operand" "=f,f")
3639 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3640 (match_operand:DF 2 "general_operand" "f,R")))
3641 (clobber (reg:CC 33))]
3642 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3646 [(set_attr "op_type" "RR,RX")
3647 (set_attr "type" "fsimpd,fsimpd")])
3650 ; addsf3 instruction pattern(s).
3653 (define_expand "addsf3"
3655 [(set (match_operand:SF 0 "register_operand" "=f,f")
3656 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3657 (match_operand:SF 2 "general_operand" "f,R")))
3658 (clobber (reg:CC 33))])]
3662 (define_insn "*addsf3"
3663 [(set (match_operand:SF 0 "register_operand" "=f,f")
3664 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3665 (match_operand:SF 2 "general_operand" "f,R")))
3666 (clobber (reg:CC 33))]
3667 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3671 [(set_attr "op_type" "RRE,RXE")
3672 (set_attr "type" "fsimps,fsimps")])
3674 (define_insn "*addsf3_cc"
3676 (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3677 (match_operand:SF 2 "general_operand" "f,R"))
3678 (match_operand:SF 3 "const0_operand" "")))
3679 (set (match_operand:SF 0 "register_operand" "=f,f")
3680 (plus:SF (match_dup 1) (match_dup 2)))]
3681 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3685 [(set_attr "op_type" "RRE,RXE")
3686 (set_attr "type" "fsimps,fsimps")])
3688 (define_insn "*addsf3_cconly"
3690 (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3691 (match_operand:SF 2 "general_operand" "f,R"))
3692 (match_operand:SF 3 "const0_operand" "")))
3693 (clobber (match_scratch:SF 0 "=f,f"))]
3694 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3698 [(set_attr "op_type" "RRE,RXE")
3699 (set_attr "type" "fsimps,fsimps")])
3701 (define_insn "*addsf3"
3702 [(set (match_operand:SF 0 "register_operand" "=f,f")
3703 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3704 (match_operand:SF 2 "general_operand" "f,R")))
3705 (clobber (reg:CC 33))]
3706 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3710 [(set_attr "op_type" "RR,RX")
3711 (set_attr "type" "fsimps,fsimps")])
3715 ;;- Subtract instructions.
3719 ; subti3 instruction pattern(s).
3722 (define_insn_and_split "subti3"
3723 [(set (match_operand:TI 0 "register_operand" "=&d")
3724 (minus:TI (match_operand:TI 1 "register_operand" "0")
3725 (match_operand:TI 2 "general_operand" "do") ) )
3726 (clobber (reg:CC 33))]
3729 "&& reload_completed"
3732 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3734 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3736 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3737 (gtu:DI (reg:CCL2 33) (const_int 0))))
3738 (clobber (reg:CC 33))])]
3739 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3740 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3741 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3742 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3743 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3744 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3747 ; subdi3 instruction pattern(s).
3750 (define_insn "*subdi3_sign"
3751 [(set (match_operand:DI 0 "register_operand" "=d,d")
3752 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3753 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3754 (clobber (reg:CC 33))]
3759 [(set_attr "op_type" "RRE,RXY")])
3761 (define_insn "*subdi3_zero_cc"
3763 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3764 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3766 (set (match_operand:DI 0 "register_operand" "=d,d")
3767 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3768 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3772 [(set_attr "op_type" "RRE,RXY")])
3774 (define_insn "*subdi3_zero_cconly"
3776 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3777 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3779 (clobber (match_scratch:DI 0 "=d,d"))]
3780 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3784 [(set_attr "op_type" "RRE,RXY")])
3786 (define_insn "*subdi3_zero"
3787 [(set (match_operand:DI 0 "register_operand" "=d,d")
3788 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3789 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3790 (clobber (reg:CC 33))]
3795 [(set_attr "op_type" "RRE,RXY")])
3797 (define_insn "*subdi3_borrow_cc"
3799 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3800 (match_operand:DI 2 "general_operand" "d,m"))
3802 (set (match_operand:DI 0 "register_operand" "=d,d")
3803 (minus:DI (match_dup 1) (match_dup 2)))]
3804 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3808 [(set_attr "op_type" "RRE,RXY")])
3810 (define_insn "*subdi3_borrow_cconly"
3812 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3813 (match_operand:DI 2 "general_operand" "d,m"))
3815 (clobber (match_scratch:DI 0 "=d,d"))]
3816 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3820 [(set_attr "op_type" "RRE,RXY")])
3822 (define_insn "*subdi3_cc"
3824 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3825 (match_operand:DI 2 "general_operand" "d,m"))
3827 (set (match_operand:DI 0 "register_operand" "=d,d")
3828 (minus:DI (match_dup 1) (match_dup 2)))]
3829 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3833 [(set_attr "op_type" "RRE,RXY")])
3835 (define_insn "*subdi3_cc2"
3837 (compare (match_operand:DI 1 "register_operand" "0,0")
3838 (match_operand:DI 2 "general_operand" "d,m")))
3839 (set (match_operand:DI 0 "register_operand" "=d,d")
3840 (minus:DI (match_dup 1) (match_dup 2)))]
3841 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3845 [(set_attr "op_type" "RRE,RXY")])
3847 (define_insn "*subdi3_cconly"
3849 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3850 (match_operand:DI 2 "general_operand" "d,m"))
3852 (clobber (match_scratch:DI 0 "=d,d"))]
3853 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3857 [(set_attr "op_type" "RRE,RXY")])
3859 (define_insn "*subdi3_cconly2"
3861 (compare (match_operand:DI 1 "register_operand" "0,0")
3862 (match_operand:DI 2 "general_operand" "d,m")))
3863 (clobber (match_scratch:DI 0 "=d,d"))]
3864 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3868 [(set_attr "op_type" "RRE,RXY")])
3870 (define_insn "*subdi3_64"
3871 [(set (match_operand:DI 0 "register_operand" "=d,d")
3872 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3873 (match_operand:DI 2 "general_operand" "d,m") ) )
3874 (clobber (reg:CC 33))]
3879 [(set_attr "op_type" "RRE,RRE")])
3881 (define_insn_and_split "*subdi3_31z"
3882 [(set (match_operand:DI 0 "register_operand" "=&d")
3883 (minus:DI (match_operand:DI 1 "register_operand" "0")
3884 (match_operand:DI 2 "general_operand" "do") ) )
3885 (clobber (reg:CC 33))]
3886 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3888 "&& reload_completed"
3891 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3893 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3895 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3896 (gtu:SI (reg:CCL2 33) (const_int 0))))
3897 (clobber (reg:CC 33))])]
3898 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3899 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3900 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3901 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3902 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3903 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3905 (define_insn_and_split "*subdi3_31"
3906 [(set (match_operand:DI 0 "register_operand" "=&d")
3907 (minus:DI (match_operand:DI 1 "register_operand" "0")
3908 (match_operand:DI 2 "general_operand" "do") ) )
3909 (clobber (reg:CC 33))]
3912 "&& reload_completed"
3914 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3915 (clobber (reg:CC 33))])
3918 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3920 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3922 (if_then_else (gtu (reg:CCL2 33) (const_int 0))
3924 (label_ref (match_dup 9))))
3926 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3927 (clobber (reg:CC 33))])
3929 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3930 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3931 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3932 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3933 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3934 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3935 operands[9] = gen_label_rtx ();")
3937 (define_expand "subdi3"
3939 [(set (match_operand:DI 0 "register_operand" "")
3940 (minus:DI (match_operand:DI 1 "register_operand" "")
3941 (match_operand:DI 2 "general_operand" "")))
3942 (clobber (reg:CC 33))])]
3947 ; subsi3 instruction pattern(s).
3950 (define_insn "*subsi3_borrow_cc"
3952 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3953 (match_operand:SI 2 "general_operand" "d,R,T"))
3955 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3956 (minus:SI (match_dup 1) (match_dup 2)))]
3957 "s390_match_ccmode (insn, CCL2mode)"
3962 [(set_attr "op_type" "RR,RX,RXY")])
3964 (define_insn "*subsi3_borrow_cconly"
3966 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3967 (match_operand:SI 2 "general_operand" "d,R,T"))
3969 (clobber (match_scratch:SI 0 "=d,d,d"))]
3970 "s390_match_ccmode (insn, CCL2mode)"
3975 [(set_attr "op_type" "RR,RX,RXY")])
3977 (define_insn "*subsi3_cc"
3979 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
3980 (match_operand:SI 2 "general_operand" "d,R,T"))
3982 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3983 (minus:SI (match_dup 1) (match_dup 2)))]
3984 "s390_match_ccmode (insn, CCLmode)"
3989 [(set_attr "op_type" "RR,RX,RXY")])
3991 (define_insn "*subsi3_cc2"
3993 (compare (match_operand:SI 1 "register_operand" "0,0,0")
3994 (match_operand:SI 2 "general_operand" "d,R,T")))
3995 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3996 (minus:SI (match_dup 1) (match_dup 2)))]
3997 "s390_match_ccmode (insn, CCL3mode)"
4002 [(set_attr "op_type" "RR,RX,RXY")])
4004 (define_insn "*subsi3_cconly"
4006 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4007 (match_operand:SI 2 "general_operand" "d,R,T"))
4009 (clobber (match_scratch:SI 0 "=d,d,d"))]
4010 "s390_match_ccmode (insn, CCLmode)"
4015 [(set_attr "op_type" "RR,RX,RXY")])
4017 (define_insn "*subsi3_cconly2"
4019 (compare (match_operand:SI 1 "register_operand" "0,0,0")
4020 (match_operand:SI 2 "general_operand" "d,R,T")))
4021 (clobber (match_scratch:SI 0 "=d,d,d"))]
4022 "s390_match_ccmode (insn, CCL3mode)"
4027 [(set_attr "op_type" "RR,RX,RXY")])
4029 (define_insn "*subsi3_sign"
4030 [(set (match_operand:SI 0 "register_operand" "=d,d")
4031 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4032 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4033 (clobber (reg:CC 33))]
4038 [(set_attr "op_type" "RX,RXY")])
4040 (define_insn "subsi3"
4041 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
4042 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4043 (match_operand:SI 2 "general_operand" "d,R,T")))
4044 (clobber (reg:CC 33))]
4050 [(set_attr "op_type" "RR,RX,RXY")])
4054 ; subdf3 instruction pattern(s).
4057 (define_expand "subdf3"
4059 [(set (match_operand:DF 0 "register_operand" "=f,f")
4060 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
4061 (match_operand:DF 2 "general_operand" "f,R")))
4062 (clobber (reg:CC 33))])]
4066 (define_insn "*subdf3"
4067 [(set (match_operand:DF 0 "register_operand" "=f,f")
4068 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
4069 (match_operand:DF 2 "general_operand" "f,R")))
4070 (clobber (reg:CC 33))]
4071 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4075 [(set_attr "op_type" "RRE,RXE")
4076 (set_attr "type" "fsimpd,fsimpd")])
4078 (define_insn "*subdf3_cc"
4080 (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
4081 (match_operand:DF 2 "general_operand" "f,R"))
4082 (match_operand:DF 3 "const0_operand" "")))
4083 (set (match_operand:DF 0 "register_operand" "=f,f")
4084 (minus:DF (match_dup 1) (match_dup 2)))]
4085 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4089 [(set_attr "op_type" "RRE,RXE")
4090 (set_attr "type" "fsimpd,fsimpd")])
4092 (define_insn "*subdf3_cconly"
4094 (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
4095 (match_operand:DF 2 "general_operand" "f,R"))
4096 (match_operand:DF 3 "const0_operand" "")))
4097 (clobber (match_scratch:DF 0 "=f,f"))]
4098 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4102 [(set_attr "op_type" "RRE,RXE")
4103 (set_attr "type" "fsimpd,fsimpd")])
4105 (define_insn "*subdf3_ibm"
4106 [(set (match_operand:DF 0 "register_operand" "=f,f")
4107 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
4108 (match_operand:DF 2 "general_operand" "f,R")))
4109 (clobber (reg:CC 33))]
4110 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4114 [(set_attr "op_type" "RR,RX")
4115 (set_attr "type" "fsimpd,fsimpd")])
4118 ; subsf3 instruction pattern(s).
4121 (define_expand "subsf3"
4123 [(set (match_operand:SF 0 "register_operand" "=f,f")
4124 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
4125 (match_operand:SF 2 "general_operand" "f,R")))
4126 (clobber (reg:CC 33))])]
4130 (define_insn "*subsf3"
4131 [(set (match_operand:SF 0 "register_operand" "=f,f")
4132 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
4133 (match_operand:SF 2 "general_operand" "f,R")))
4134 (clobber (reg:CC 33))]
4135 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4139 [(set_attr "op_type" "RRE,RXE")
4140 (set_attr "type" "fsimps,fsimps")])
4142 (define_insn "*subsf3_cc"
4144 (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
4145 (match_operand:SF 2 "general_operand" "f,R"))
4146 (match_operand:SF 3 "const0_operand" "")))
4147 (set (match_operand:SF 0 "register_operand" "=f,f")
4148 (minus:SF (match_dup 1) (match_dup 2)))]
4149 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4153 [(set_attr "op_type" "RRE,RXE")
4154 (set_attr "type" "fsimps,fsimps")])
4156 (define_insn "*subsf3_cconly"
4158 (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
4159 (match_operand:SF 2 "general_operand" "f,R"))
4160 (match_operand:SF 3 "const0_operand" "")))
4161 (clobber (match_scratch:SF 0 "=f,f"))]
4162 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4166 [(set_attr "op_type" "RRE,RXE")
4167 (set_attr "type" "fsimps,fsimps")])
4169 (define_insn "*subsf3_ibm"
4170 [(set (match_operand:SF 0 "register_operand" "=f,f")
4171 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
4172 (match_operand:SF 2 "general_operand" "f,R")))
4173 (clobber (reg:CC 33))]
4174 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4178 [(set_attr "op_type" "RR,RX")
4179 (set_attr "type" "fsimps,fsimps")])
4183 ;;- Conditional add/subtract instructions.
4187 ; adddicc instruction pattern(s).
4190 (define_insn "*adddi3_alc_cc"
4193 (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4194 (match_operand:DI 2 "general_operand" "d,m"))
4195 (match_operand:DI 3 "s390_alc_comparison" ""))
4197 (set (match_operand:DI 0 "register_operand" "=d,d")
4198 (plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4199 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4203 [(set_attr "op_type" "RRE,RXY")])
4205 (define_insn "*adddi3_alc"
4206 [(set (match_operand:DI 0 "register_operand" "=d,d")
4207 (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4208 (match_operand:DI 2 "general_operand" "d,m"))
4209 (match_operand:DI 3 "s390_alc_comparison" "")))
4210 (clobber (reg:CC 33))]
4215 [(set_attr "op_type" "RRE,RXY")])
4217 (define_insn "*subdi3_slb_cc"
4220 (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
4221 (match_operand:DI 2 "general_operand" "d,m"))
4222 (match_operand:DI 3 "s390_slb_comparison" ""))
4224 (set (match_operand:DI 0 "register_operand" "=d,d")
4225 (minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4226 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4230 [(set_attr "op_type" "RRE,RXY")])
4232 (define_insn "*subdi3_slb"
4233 [(set (match_operand:DI 0 "register_operand" "=d,d")
4234 (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
4235 (match_operand:DI 2 "general_operand" "d,m"))
4236 (match_operand:DI 3 "s390_slb_comparison" "")))
4237 (clobber (reg:CC 33))]
4242 [(set_attr "op_type" "RRE,RXY")])
4244 (define_expand "adddicc"
4245 [(match_operand:DI 0 "register_operand" "")
4246 (match_operand 1 "comparison_operator" "")
4247 (match_operand:DI 2 "register_operand" "")
4248 (match_operand:DI 3 "const_int_operand" "")]
4250 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4251 s390_compare_op0, s390_compare_op1,
4252 operands[0], operands[2],
4253 operands[3])) FAIL; DONE;")
4256 ; addsicc instruction pattern(s).
4259 (define_insn "*addsi3_alc_cc"
4262 (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4263 (match_operand:SI 2 "general_operand" "d,m"))
4264 (match_operand:SI 3 "s390_alc_comparison" ""))
4266 (set (match_operand:SI 0 "register_operand" "=d,d")
4267 (plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4268 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4272 [(set_attr "op_type" "RRE,RXY")])
4274 (define_insn "*addsi3_alc"
4275 [(set (match_operand:SI 0 "register_operand" "=d,d")
4276 (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4277 (match_operand:SI 2 "general_operand" "d,m"))
4278 (match_operand:SI 3 "s390_alc_comparison" "")))
4279 (clobber (reg:CC 33))]
4284 [(set_attr "op_type" "RRE,RXY")])
4286 (define_insn "*subsi3_slb_cc"
4289 (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
4290 (match_operand:SI 2 "general_operand" "d,m"))
4291 (match_operand:SI 3 "s390_slb_comparison" ""))
4293 (set (match_operand:SI 0 "register_operand" "=d,d")
4294 (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4295 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4299 [(set_attr "op_type" "RRE,RXY")])
4301 (define_insn "*subsi3_slb"
4302 [(set (match_operand:SI 0 "register_operand" "=d,d")
4303 (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
4304 (match_operand:SI 2 "general_operand" "d,m"))
4305 (match_operand:SI 3 "s390_slb_comparison" "")))
4306 (clobber (reg:CC 33))]
4311 [(set_attr "op_type" "RRE,RXY")])
4313 (define_expand "addsicc"
4314 [(match_operand:SI 0 "register_operand" "")
4315 (match_operand 1 "comparison_operator" "")
4316 (match_operand:SI 2 "register_operand" "")
4317 (match_operand:SI 3 "const_int_operand" "")]
4319 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4320 s390_compare_op0, s390_compare_op1,
4321 operands[0], operands[2],
4322 operands[3])) FAIL; DONE;")
4325 ; scond instruction pattern(s).
4328 (define_insn_and_split "*sconddi"
4329 [(set (match_operand:DI 0 "register_operand" "=&d")
4330 (match_operand:DI 1 "s390_alc_comparison" ""))
4331 (clobber (reg:CC 33))]
4334 "&& reload_completed"
4335 [(set (match_dup 0) (const_int 0))
4337 [(set (match_dup 0) (plus:DI (plus:DI (match_dup 0) (match_dup 0))
4339 (clobber (reg:CC 33))])]
4342 (define_insn_and_split "*scondsi"
4343 [(set (match_operand:SI 0 "register_operand" "=&d")
4344 (match_operand:SI 1 "s390_alc_comparison" ""))
4345 (clobber (reg:CC 33))]
4348 "&& reload_completed"
4349 [(set (match_dup 0) (const_int 0))
4351 [(set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 0))
4353 (clobber (reg:CC 33))])]
4356 (define_insn_and_split "*sconddi_neg"
4357 [(set (match_operand:DI 0 "register_operand" "=&d")
4358 (match_operand:DI 1 "s390_slb_comparison" ""))
4359 (clobber (reg:CC 33))]
4362 "&& reload_completed"
4363 [(set (match_dup 0) (const_int 0))
4365 [(set (match_dup 0) (minus:DI (minus:DI (match_dup 0) (match_dup 0))
4367 (clobber (reg:CC 33))])
4369 [(set (match_dup 0) (neg:DI (match_dup 0)))
4370 (clobber (reg:CC 33))])]
4373 (define_insn_and_split "*scondsi_neg"
4374 [(set (match_operand:SI 0 "register_operand" "=&d")
4375 (match_operand:SI 1 "s390_slb_comparison" ""))
4376 (clobber (reg:CC 33))]
4379 "&& reload_completed"
4380 [(set (match_dup 0) (const_int 0))
4382 [(set (match_dup 0) (minus:SI (minus:SI (match_dup 0) (match_dup 0))
4384 (clobber (reg:CC 33))])
4386 [(set (match_dup 0) (neg:SI (match_dup 0)))
4387 (clobber (reg:CC 33))])]
4390 (define_expand "sltu"
4391 [(match_operand:SI 0 "register_operand" "")]
4393 "if (!s390_expand_addcc (LTU, s390_compare_op0, s390_compare_op1,
4394 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4396 (define_expand "sgtu"
4397 [(match_operand:SI 0 "register_operand" "")]
4399 "if (!s390_expand_addcc (GTU, s390_compare_op0, s390_compare_op1,
4400 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4402 (define_expand "sleu"
4403 [(match_operand:SI 0 "register_operand" "")]
4405 "if (!s390_expand_addcc (LEU, s390_compare_op0, s390_compare_op1,
4406 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4408 (define_expand "sgeu"
4409 [(match_operand:SI 0 "register_operand" "")]
4411 "if (!s390_expand_addcc (GEU, s390_compare_op0, s390_compare_op1,
4412 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4416 ;;- Multiply instructions.
4420 ; muldi3 instruction pattern(s).
4423 (define_insn "*muldi3_sign"
4424 [(set (match_operand:DI 0 "register_operand" "=d,d")
4425 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4426 (match_operand:DI 1 "register_operand" "0,0")))]
4431 [(set_attr "op_type" "RRE,RXY")
4432 (set_attr "type" "imuldi")])
4434 (define_insn "muldi3"
4435 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4436 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4437 (match_operand:DI 2 "general_operand" "d,K,m")))]
4443 [(set_attr "op_type" "RRE,RI,RXY")
4444 (set_attr "type" "imuldi")])
4447 ; mulsi3 instruction pattern(s).
4450 (define_insn "*mulsi3_sign"
4451 [(set (match_operand:SI 0 "register_operand" "=d")
4452 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4453 (match_operand:SI 1 "register_operand" "0")))]
4456 [(set_attr "op_type" "RX")
4457 (set_attr "type" "imulhi")])
4459 (define_insn "mulsi3"
4460 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4461 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4462 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4469 [(set_attr "op_type" "RRE,RI,RX,RXY")
4470 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4473 ; mulsidi3 instruction pattern(s).
4476 (define_insn "mulsidi3"
4477 [(set (match_operand:DI 0 "register_operand" "=d,d")
4478 (mult:DI (sign_extend:DI
4479 (match_operand:SI 1 "register_operand" "%0,0"))
4481 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4486 [(set_attr "op_type" "RR,RX")
4487 (set_attr "type" "imulsi")])
4490 ; umulsidi3 instruction pattern(s).
4493 (define_insn "umulsidi3"
4494 [(set (match_operand:DI 0 "register_operand" "=d,d")
4495 (mult:DI (zero_extend:DI
4496 (match_operand:SI 1 "register_operand" "%0,0"))
4498 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4499 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4503 [(set_attr "op_type" "RRE,RXY")
4504 (set_attr "type" "imulsi")])
4507 ; muldf3 instruction pattern(s).
4510 (define_expand "muldf3"
4511 [(set (match_operand:DF 0 "register_operand" "=f,f")
4512 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
4513 (match_operand:DF 2 "general_operand" "f,R")))]
4517 (define_insn "*muldf3"
4518 [(set (match_operand:DF 0 "register_operand" "=f,f")
4519 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
4520 (match_operand:DF 2 "general_operand" "f,R")))]
4521 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4525 [(set_attr "op_type" "RRE,RXE")
4526 (set_attr "type" "fmuld")])
4528 (define_insn "*muldf3_ibm"
4529 [(set (match_operand:DF 0 "register_operand" "=f,f")
4530 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
4531 (match_operand:DF 2 "general_operand" "f,R")))]
4532 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4536 [(set_attr "op_type" "RR,RX")
4537 (set_attr "type" "fmuld")])
4539 (define_insn "*fmadddf"
4540 [(set (match_operand:DF 0 "register_operand" "=f,f")
4541 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f")
4542 (match_operand:DF 2 "nonimmediate_operand" "f,R"))
4543 (match_operand:DF 3 "register_operand" "0,0")))]
4544 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4548 [(set_attr "op_type" "RRE,RXE")
4549 (set_attr "type" "fmuld")])
4551 (define_insn "*fmsubdf"
4552 [(set (match_operand:DF 0 "register_operand" "=f,f")
4553 (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f")
4554 (match_operand:DF 2 "nonimmediate_operand" "f,R"))
4555 (match_operand:DF 3 "register_operand" "0,0")))]
4556 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4560 [(set_attr "op_type" "RRE,RXE")
4561 (set_attr "type" "fmuld")])
4564 ; mulsf3 instruction pattern(s).
4567 (define_expand "mulsf3"
4568 [(set (match_operand:SF 0 "register_operand" "=f,f")
4569 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
4570 (match_operand:SF 2 "general_operand" "f,R")))]
4574 (define_insn "*mulsf3"
4575 [(set (match_operand:SF 0 "register_operand" "=f,f")
4576 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
4577 (match_operand:SF 2 "general_operand" "f,R")))]
4578 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4582 [(set_attr "op_type" "RRE,RXE")
4583 (set_attr "type" "fmuls")])
4585 (define_insn "*mulsf3_ibm"
4586 [(set (match_operand:SF 0 "register_operand" "=f,f")
4587 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
4588 (match_operand:SF 2 "general_operand" "f,R")))]
4589 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4593 [(set_attr "op_type" "RR,RX")
4594 (set_attr "type" "fmuls")])
4596 (define_insn "*fmaddsf"
4597 [(set (match_operand:SF 0 "register_operand" "=f,f")
4598 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f")
4599 (match_operand:SF 2 "nonimmediate_operand" "f,R"))
4600 (match_operand:SF 3 "register_operand" "0,0")))]
4601 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4605 [(set_attr "op_type" "RRE,RXE")
4606 (set_attr "type" "fmuls")])
4608 (define_insn "*fmsubsf"
4609 [(set (match_operand:SF 0 "register_operand" "=f,f")
4610 (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f")
4611 (match_operand:SF 2 "nonimmediate_operand" "f,R"))
4612 (match_operand:SF 3 "register_operand" "0,0")))]
4613 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4617 [(set_attr "op_type" "RRE,RXE")
4618 (set_attr "type" "fmuls")])
4621 ;;- Divide and modulo instructions.
4625 ; divmoddi4 instruction pattern(s).
4628 (define_expand "divmoddi4"
4629 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4630 (div:DI (match_operand:DI 1 "register_operand" "")
4631 (match_operand:DI 2 "general_operand" "")))
4632 (set (match_operand:DI 3 "general_operand" "")
4633 (mod:DI (match_dup 1) (match_dup 2)))])
4634 (clobber (match_dup 4))]
4637 rtx insn, div_equal, mod_equal;
4639 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4640 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4642 operands[4] = gen_reg_rtx(TImode);
4643 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4645 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4647 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4649 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4651 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4656 (define_insn "divmodtidi3"
4657 [(set (match_operand:TI 0 "register_operand" "=d,d")
4661 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4662 (match_operand:DI 2 "general_operand" "d,m")))
4664 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4669 [(set_attr "op_type" "RRE,RXY")
4670 (set_attr "type" "idiv")])
4672 (define_insn "divmodtisi3"
4673 [(set (match_operand:TI 0 "register_operand" "=d,d")
4677 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4679 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4682 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4687 [(set_attr "op_type" "RRE,RXY")
4688 (set_attr "type" "idiv")])
4691 ; udivmoddi4 instruction pattern(s).
4694 (define_expand "udivmoddi4"
4695 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4696 (udiv:DI (match_operand:DI 1 "general_operand" "")
4697 (match_operand:DI 2 "nonimmediate_operand" "")))
4698 (set (match_operand:DI 3 "general_operand" "")
4699 (umod:DI (match_dup 1) (match_dup 2)))])
4700 (clobber (match_dup 4))]
4703 rtx insn, div_equal, mod_equal, equal;
4705 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4706 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4707 equal = gen_rtx_IOR (TImode,
4708 gen_rtx_ASHIFT (TImode,
4709 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4711 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4713 operands[4] = gen_reg_rtx(TImode);
4714 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4715 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4716 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4717 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4719 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4721 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4723 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4725 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4727 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4732 (define_insn "udivmodtidi3"
4733 [(set (match_operand:TI 0 "register_operand" "=d,d")
4738 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4740 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4744 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4749 [(set_attr "op_type" "RRE,RXY")
4750 (set_attr "type" "idiv")])
4753 ; divmodsi4 instruction pattern(s).
4756 (define_expand "divmodsi4"
4757 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4758 (div:SI (match_operand:SI 1 "general_operand" "")
4759 (match_operand:SI 2 "nonimmediate_operand" "")))
4760 (set (match_operand:SI 3 "general_operand" "")
4761 (mod:SI (match_dup 1) (match_dup 2)))])
4762 (clobber (match_dup 4))]
4765 rtx insn, div_equal, mod_equal, equal;
4767 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4768 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4769 equal = gen_rtx_IOR (DImode,
4770 gen_rtx_ASHIFT (DImode,
4771 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4773 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4775 operands[4] = gen_reg_rtx(DImode);
4776 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4777 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4779 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4781 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4783 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4785 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4787 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4792 (define_insn "divmoddisi3"
4793 [(set (match_operand:DI 0 "register_operand" "=d,d")
4798 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4800 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4804 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4809 [(set_attr "op_type" "RR,RX")
4810 (set_attr "type" "idiv")])
4813 ; udivsi3 and umodsi3 instruction pattern(s).
4816 (define_expand "udivmodsi4"
4817 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4818 (udiv:SI (match_operand:SI 1 "general_operand" "")
4819 (match_operand:SI 2 "nonimmediate_operand" "")))
4820 (set (match_operand:SI 3 "general_operand" "")
4821 (umod:SI (match_dup 1) (match_dup 2)))])
4822 (clobber (match_dup 4))]
4823 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4825 rtx insn, div_equal, mod_equal, equal;
4827 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4828 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4829 equal = gen_rtx_IOR (DImode,
4830 gen_rtx_ASHIFT (DImode,
4831 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4833 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4835 operands[4] = gen_reg_rtx(DImode);
4836 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4837 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4838 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4839 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4841 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4843 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4845 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4847 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4849 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4854 (define_insn "udivmoddisi3"
4855 [(set (match_operand:DI 0 "register_operand" "=d,d")
4860 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4862 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4866 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4867 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4871 [(set_attr "op_type" "RRE,RXY")
4872 (set_attr "type" "idiv")])
4874 (define_expand "udivsi3"
4875 [(set (match_operand:SI 0 "register_operand" "=d")
4876 (udiv:SI (match_operand:SI 1 "general_operand" "")
4877 (match_operand:SI 2 "general_operand" "")))
4878 (clobber (match_dup 3))]
4879 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4881 rtx insn, udiv_equal, umod_equal, equal;
4883 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4884 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4885 equal = gen_rtx_IOR (DImode,
4886 gen_rtx_ASHIFT (DImode,
4887 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4889 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4891 operands[3] = gen_reg_rtx (DImode);
4893 if (CONSTANT_P (operands[2]))
4895 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4897 rtx label1 = gen_label_rtx ();
4899 operands[1] = make_safe_from (operands[1], operands[0]);
4900 emit_move_insn (operands[0], const0_rtx);
4901 emit_insn (gen_cmpsi (operands[1], operands[2]));
4902 emit_jump_insn (gen_bltu (label1));
4903 emit_move_insn (operands[0], const1_rtx);
4904 emit_label (label1);
4908 operands[2] = force_reg (SImode, operands[2]);
4909 operands[2] = make_safe_from (operands[2], operands[0]);
4911 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4912 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4915 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4917 insn = emit_move_insn (operands[0],
4918 gen_lowpart (SImode, operands[3]));
4920 gen_rtx_EXPR_LIST (REG_EQUAL,
4921 udiv_equal, REG_NOTES (insn));
4926 rtx label1 = gen_label_rtx ();
4927 rtx label2 = gen_label_rtx ();
4928 rtx label3 = gen_label_rtx ();
4930 operands[1] = force_reg (SImode, operands[1]);
4931 operands[1] = make_safe_from (operands[1], operands[0]);
4932 operands[2] = force_reg (SImode, operands[2]);
4933 operands[2] = make_safe_from (operands[2], operands[0]);
4935 emit_move_insn (operands[0], const0_rtx);
4936 emit_insn (gen_cmpsi (operands[2], operands[1]));
4937 emit_jump_insn (gen_bgtu (label3));
4938 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4939 emit_jump_insn (gen_blt (label2));
4940 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4941 emit_jump_insn (gen_beq (label1));
4942 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4943 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4946 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4948 insn = emit_move_insn (operands[0],
4949 gen_lowpart (SImode, operands[3]));
4951 gen_rtx_EXPR_LIST (REG_EQUAL,
4952 udiv_equal, REG_NOTES (insn));
4954 emit_label (label1);
4955 emit_move_insn (operands[0], operands[1]);
4957 emit_label (label2);
4958 emit_move_insn (operands[0], const1_rtx);
4959 emit_label (label3);
4961 emit_move_insn (operands[0], operands[0]);
4965 (define_expand "umodsi3"
4966 [(set (match_operand:SI 0 "register_operand" "=d")
4967 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4968 (match_operand:SI 2 "nonimmediate_operand" "")))
4969 (clobber (match_dup 3))]
4970 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4972 rtx insn, udiv_equal, umod_equal, equal;
4974 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4975 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4976 equal = gen_rtx_IOR (DImode,
4977 gen_rtx_ASHIFT (DImode,
4978 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4980 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4982 operands[3] = gen_reg_rtx (DImode);
4984 if (CONSTANT_P (operands[2]))
4986 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4988 rtx label1 = gen_label_rtx ();
4990 operands[1] = make_safe_from (operands[1], operands[0]);
4991 emit_move_insn (operands[0], operands[1]);
4992 emit_insn (gen_cmpsi (operands[0], operands[2]));
4993 emit_jump_insn (gen_bltu (label1));
4994 emit_insn (gen_abssi2 (operands[0], operands[2]));
4995 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4996 emit_label (label1);
5000 operands[2] = force_reg (SImode, operands[2]);
5001 operands[2] = make_safe_from (operands[2], operands[0]);
5003 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5004 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5007 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5009 insn = emit_move_insn (operands[0],
5010 gen_highpart (SImode, operands[3]));
5012 gen_rtx_EXPR_LIST (REG_EQUAL,
5013 umod_equal, REG_NOTES (insn));
5018 rtx label1 = gen_label_rtx ();
5019 rtx label2 = gen_label_rtx ();
5020 rtx label3 = gen_label_rtx ();
5022 operands[1] = force_reg (SImode, operands[1]);
5023 operands[1] = make_safe_from (operands[1], operands[0]);
5024 operands[2] = force_reg (SImode, operands[2]);
5025 operands[2] = make_safe_from (operands[2], operands[0]);
5027 emit_move_insn(operands[0], operands[1]);
5028 emit_insn (gen_cmpsi (operands[2], operands[1]));
5029 emit_jump_insn (gen_bgtu (label3));
5030 emit_insn (gen_cmpsi (operands[2], const0_rtx));
5031 emit_jump_insn (gen_blt (label2));
5032 emit_insn (gen_cmpsi (operands[2], const1_rtx));
5033 emit_jump_insn (gen_beq (label1));
5034 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5035 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5038 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5040 insn = emit_move_insn (operands[0],
5041 gen_highpart (SImode, operands[3]));
5043 gen_rtx_EXPR_LIST (REG_EQUAL,
5044 umod_equal, REG_NOTES (insn));
5046 emit_label (label1);
5047 emit_move_insn (operands[0], const0_rtx);
5049 emit_label (label2);
5050 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5051 emit_label (label3);
5057 ; divdf3 instruction pattern(s).
5060 (define_expand "divdf3"
5061 [(set (match_operand:DF 0 "register_operand" "=f,f")
5062 (div:DF (match_operand:DF 1 "register_operand" "0,0")
5063 (match_operand:DF 2 "general_operand" "f,R")))]
5067 (define_insn "*divdf3"
5068 [(set (match_operand:DF 0 "register_operand" "=f,f")
5069 (div:DF (match_operand:DF 1 "register_operand" "0,0")
5070 (match_operand:DF 2 "general_operand" "f,R")))]
5071 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5075 [(set_attr "op_type" "RRE,RXE")
5076 (set_attr "type" "fdivd")])
5078 (define_insn "*divdf3_ibm"
5079 [(set (match_operand:DF 0 "register_operand" "=f,f")
5080 (div:DF (match_operand:DF 1 "register_operand" "0,0")
5081 (match_operand:DF 2 "general_operand" "f,R")))]
5082 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5086 [(set_attr "op_type" "RR,RX")
5087 (set_attr "type" "fdivd")])
5090 ; divsf3 instruction pattern(s).
5093 (define_expand "divsf3"
5094 [(set (match_operand:SF 0 "register_operand" "=f,f")
5095 (div:SF (match_operand:SF 1 "register_operand" "0,0")
5096 (match_operand:SF 2 "general_operand" "f,R")))]
5100 (define_insn "*divsf3"
5101 [(set (match_operand:SF 0 "register_operand" "=f,f")
5102 (div:SF (match_operand:SF 1 "register_operand" "0,0")
5103 (match_operand:SF 2 "general_operand" "f,R")))]
5104 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5108 [(set_attr "op_type" "RRE,RXE")
5109 (set_attr "type" "fdivs")])
5111 (define_insn "*divsf3"
5112 [(set (match_operand:SF 0 "register_operand" "=f,f")
5113 (div:SF (match_operand:SF 1 "register_operand" "0,0")
5114 (match_operand:SF 2 "general_operand" "f,R")))]
5115 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5119 [(set_attr "op_type" "RR,RX")
5120 (set_attr "type" "fdivs")])
5124 ;;- And instructions.
5128 ; anddi3 instruction pattern(s).
5131 (define_insn "*anddi3_cc"
5133 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5134 (match_operand:DI 2 "general_operand" "d,m"))
5136 (set (match_operand:DI 0 "register_operand" "=d,d")
5137 (and:DI (match_dup 1) (match_dup 2)))]
5138 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5142 [(set_attr "op_type" "RRE,RXY")])
5144 (define_insn "*anddi3_cconly"
5146 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5147 (match_operand:DI 2 "general_operand" "d,m"))
5149 (clobber (match_scratch:DI 0 "=d,d"))]
5150 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
5151 /* Do not steal TM patterns. */
5152 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5156 [(set_attr "op_type" "RRE,RXY")])
5158 (define_insn "*anddi3"
5159 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5160 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5161 "%d,o,0,0,0,0,0,0,0,0")
5162 (match_operand:DI 2 "general_operand"
5163 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
5164 (clobber (reg:CC 33))]
5165 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5177 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
5180 [(set (match_operand:DI 0 "s_operand" "")
5181 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5182 (clobber (reg:CC 33))]
5185 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5186 (clobber (reg:CC 33))])]
5187 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5189 (define_expand "anddi3"
5190 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5191 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
5192 (match_operand:DI 2 "general_operand" "")))
5193 (clobber (reg:CC 33))]
5195 "s390_expand_logical_operator (AND, DImode, operands); DONE;")
5198 ; andsi3 instruction pattern(s).
5201 (define_insn "*andsi3_cc"
5203 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5204 (match_operand:SI 2 "general_operand" "d,R,T"))
5206 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5207 (and:SI (match_dup 1) (match_dup 2)))]
5208 "s390_match_ccmode(insn, CCTmode)"
5213 [(set_attr "op_type" "RR,RX,RXY")])
5215 (define_insn "*andsi3_cconly"
5217 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5218 (match_operand:SI 2 "general_operand" "d,R,T"))
5220 (clobber (match_scratch:SI 0 "=d,d,d"))]
5221 "s390_match_ccmode(insn, CCTmode)
5222 /* Do not steal TM patterns. */
5223 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5228 [(set_attr "op_type" "RR,RX,RXY")])
5230 (define_insn "*andsi3_zarch"
5231 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q")
5232 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5233 "%d,o,0,0,0,0,0,0,0")
5234 (match_operand:SI 2 "general_operand"
5235 "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q")))
5236 (clobber (reg:CC 33))]
5237 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5248 [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")])
5250 (define_insn "*andsi3_esa"
5251 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5252 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5253 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5254 (clobber (reg:CC 33))]
5255 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5261 [(set_attr "op_type" "RR,RX,SI,SS")])
5264 [(set (match_operand:SI 0 "s_operand" "")
5265 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5266 (clobber (reg:CC 33))]
5269 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5270 (clobber (reg:CC 33))])]
5271 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5273 (define_expand "andsi3"
5274 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5275 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
5276 (match_operand:SI 2 "general_operand" "")))
5277 (clobber (reg:CC 33))]
5279 "s390_expand_logical_operator (AND, SImode, operands); DONE;")
5282 ; andhi3 instruction pattern(s).
5285 (define_insn "*andhi3_zarch"
5286 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5287 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5288 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5289 (clobber (reg:CC 33))]
5290 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5296 [(set_attr "op_type" "RR,RI,SI,SS")])
5298 (define_insn "*andhi3_esa"
5299 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5300 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5301 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5302 (clobber (reg:CC 33))]
5303 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5308 [(set_attr "op_type" "RR,SI,SS")])
5311 [(set (match_operand:HI 0 "s_operand" "")
5312 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5313 (clobber (reg:CC 33))]
5316 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5317 (clobber (reg:CC 33))])]
5318 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5320 (define_expand "andhi3"
5321 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5322 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
5323 (match_operand:HI 2 "general_operand" "")))
5324 (clobber (reg:CC 33))]
5326 "s390_expand_logical_operator (AND, HImode, operands); DONE;")
5329 ; andqi3 instruction pattern(s).
5332 (define_insn "*andqi3_zarch"
5333 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5334 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5335 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5336 (clobber (reg:CC 33))]
5337 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5344 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5346 (define_insn "*andqi3_esa"
5347 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5348 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5349 (match_operand:QI 2 "general_operand" "d,n,Q")))
5350 (clobber (reg:CC 33))]
5351 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5356 [(set_attr "op_type" "RR,SI,SS")])
5358 (define_expand "andqi3"
5359 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5360 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
5361 (match_operand:QI 2 "general_operand" "")))
5362 (clobber (reg:CC 33))]
5364 "s390_expand_logical_operator (AND, QImode, operands); DONE;")
5367 ; Block and (NC) patterns.
5371 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5372 (and:BLK (match_dup 0)
5373 (match_operand:BLK 1 "memory_operand" "Q")))
5374 (use (match_operand 2 "const_int_operand" "n"))
5375 (clobber (reg:CC 33))]
5376 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5377 "nc\t%O0(%2,%R0),%S1"
5378 [(set_attr "op_type" "SS")])
5381 [(set (match_operand 0 "memory_operand" "")
5383 (match_operand 1 "memory_operand" "")))
5384 (clobber (reg:CC 33))]
5386 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5387 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5389 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
5391 (clobber (reg:CC 33))])]
5393 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5394 operands[0] = adjust_address (operands[0], BLKmode, 0);
5395 operands[1] = adjust_address (operands[1], BLKmode, 0);
5400 [(set (match_operand:BLK 0 "memory_operand" "")
5401 (and:BLK (match_dup 0)
5402 (match_operand:BLK 1 "memory_operand" "")))
5403 (use (match_operand 2 "const_int_operand" ""))
5404 (clobber (reg:CC 33))])
5406 [(set (match_operand:BLK 3 "memory_operand" "")
5407 (and:BLK (match_dup 3)
5408 (match_operand:BLK 4 "memory_operand" "")))
5409 (use (match_operand 5 "const_int_operand" ""))
5410 (clobber (reg:CC 33))])]
5411 "s390_offset_p (operands[0], operands[3], operands[2])
5412 && s390_offset_p (operands[1], operands[4], operands[2])
5413 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5415 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
5417 (clobber (reg:CC 33))])]
5418 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5419 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5420 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5424 ;;- Bit set (inclusive or) instructions.
5428 ; iordi3 instruction pattern(s).
5431 (define_insn "*iordi3_cc"
5433 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5434 (match_operand:DI 2 "general_operand" "d,m"))
5436 (set (match_operand:DI 0 "register_operand" "=d,d")
5437 (ior:DI (match_dup 1) (match_dup 2)))]
5438 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5442 [(set_attr "op_type" "RRE,RXY")])
5444 (define_insn "*iordi3_cconly"
5446 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5447 (match_operand:DI 2 "general_operand" "d,m"))
5449 (clobber (match_scratch:DI 0 "=d,d"))]
5450 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5454 [(set_attr "op_type" "RRE,RXY")])
5456 (define_insn "*iordi3"
5457 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5458 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5459 (match_operand:DI 2 "general_operand"
5460 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5461 (clobber (reg:CC 33))]
5462 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5472 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5475 [(set (match_operand:DI 0 "s_operand" "")
5476 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5477 (clobber (reg:CC 33))]
5480 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5481 (clobber (reg:CC 33))])]
5482 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5484 (define_expand "iordi3"
5485 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5486 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
5487 (match_operand:DI 2 "general_operand" "")))
5488 (clobber (reg:CC 33))]
5490 "s390_expand_logical_operator (IOR, DImode, operands); DONE;")
5493 ; iorsi3 instruction pattern(s).
5496 (define_insn "*iorsi3_cc"
5498 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5499 (match_operand:SI 2 "general_operand" "d,R,T"))
5501 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5502 (ior:SI (match_dup 1) (match_dup 2)))]
5503 "s390_match_ccmode(insn, CCTmode)"
5508 [(set_attr "op_type" "RR,RX,RXY")])
5510 (define_insn "*iorsi3_cconly"
5512 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5513 (match_operand:SI 2 "general_operand" "d,R,T"))
5515 (clobber (match_scratch:SI 0 "=d,d,d"))]
5516 "s390_match_ccmode(insn, CCTmode)"
5521 [(set_attr "op_type" "RR,RX,RXY")])
5523 (define_insn "*iorsi3_zarch"
5524 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q")
5525 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
5526 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q")))
5527 (clobber (reg:CC 33))]
5528 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5537 [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")])
5539 (define_insn "*iorsi3_esa"
5540 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5541 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5542 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5543 (clobber (reg:CC 33))]
5544 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5550 [(set_attr "op_type" "RR,RX,SI,SS")])
5553 [(set (match_operand:SI 0 "s_operand" "")
5554 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5555 (clobber (reg:CC 33))]
5558 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5559 (clobber (reg:CC 33))])]
5560 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5562 (define_expand "iorsi3"
5563 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5564 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
5565 (match_operand:SI 2 "general_operand" "")))
5566 (clobber (reg:CC 33))]
5568 "s390_expand_logical_operator (IOR, SImode, operands); DONE;")
5571 ; iorhi3 instruction pattern(s).
5574 (define_insn "*iorhi3_zarch"
5575 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5576 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5577 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5578 (clobber (reg:CC 33))]
5579 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5585 [(set_attr "op_type" "RR,RI,SI,SS")])
5587 (define_insn "*iorhi3_esa"
5588 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5589 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5590 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5591 (clobber (reg:CC 33))]
5592 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5597 [(set_attr "op_type" "RR,SI,SS")])
5600 [(set (match_operand:HI 0 "s_operand" "")
5601 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5602 (clobber (reg:CC 33))]
5605 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5606 (clobber (reg:CC 33))])]
5607 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5609 (define_expand "iorhi3"
5610 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5611 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
5612 (match_operand:HI 2 "general_operand" "")))
5613 (clobber (reg:CC 33))]
5615 "s390_expand_logical_operator (IOR, HImode, operands); DONE;")
5618 ; iorqi3 instruction pattern(s).
5621 (define_insn "*iorqi3_zarch"
5622 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5623 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5624 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5625 (clobber (reg:CC 33))]
5626 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5633 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5635 (define_insn "*iorqi3_esa"
5636 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5637 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5638 (match_operand:QI 2 "general_operand" "d,n,Q")))
5639 (clobber (reg:CC 33))]
5640 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5645 [(set_attr "op_type" "RR,SI,SS")])
5647 (define_expand "iorqi3"
5648 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5649 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
5650 (match_operand:QI 2 "general_operand" "")))
5651 (clobber (reg:CC 33))]
5653 "s390_expand_logical_operator (IOR, QImode, operands); DONE;")
5656 ; Block inclusive or (OC) patterns.
5660 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5661 (ior:BLK (match_dup 0)
5662 (match_operand:BLK 1 "memory_operand" "Q")))
5663 (use (match_operand 2 "const_int_operand" "n"))
5664 (clobber (reg:CC 33))]
5665 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5666 "oc\t%O0(%2,%R0),%S1"
5667 [(set_attr "op_type" "SS")])
5670 [(set (match_operand 0 "memory_operand" "")
5672 (match_operand 1 "memory_operand" "")))
5673 (clobber (reg:CC 33))]
5675 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5676 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5678 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5680 (clobber (reg:CC 33))])]
5682 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5683 operands[0] = adjust_address (operands[0], BLKmode, 0);
5684 operands[1] = adjust_address (operands[1], BLKmode, 0);
5689 [(set (match_operand:BLK 0 "memory_operand" "")
5690 (ior:BLK (match_dup 0)
5691 (match_operand:BLK 1 "memory_operand" "")))
5692 (use (match_operand 2 "const_int_operand" ""))
5693 (clobber (reg:CC 33))])
5695 [(set (match_operand:BLK 3 "memory_operand" "")
5696 (ior:BLK (match_dup 3)
5697 (match_operand:BLK 4 "memory_operand" "")))
5698 (use (match_operand 5 "const_int_operand" ""))
5699 (clobber (reg:CC 33))])]
5700 "s390_offset_p (operands[0], operands[3], operands[2])
5701 && s390_offset_p (operands[1], operands[4], operands[2])
5702 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5704 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5706 (clobber (reg:CC 33))])]
5707 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5708 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5709 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5713 ;;- Xor instructions.
5717 ; xordi3 instruction pattern(s).
5720 (define_insn "*xordi3_cc"
5722 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5723 (match_operand:DI 2 "general_operand" "d,m"))
5725 (set (match_operand:DI 0 "register_operand" "=d,d")
5726 (xor:DI (match_dup 1) (match_dup 2)))]
5727 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5731 [(set_attr "op_type" "RRE,RXY")])
5733 (define_insn "*xordi3_cconly"
5735 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5736 (match_operand:DI 2 "general_operand" "d,m"))
5738 (clobber (match_scratch:DI 0 "=d,d"))]
5739 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5743 [(set_attr "op_type" "RRE,RXY")])
5745 (define_insn "*xordi3"
5746 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5747 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5748 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5749 (clobber (reg:CC 33))]
5750 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5756 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5759 [(set (match_operand:DI 0 "s_operand" "")
5760 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5761 (clobber (reg:CC 33))]
5764 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5765 (clobber (reg:CC 33))])]
5766 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5768 (define_expand "xordi3"
5769 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5770 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
5771 (match_operand:DI 2 "general_operand" "")))
5772 (clobber (reg:CC 33))]
5774 "s390_expand_logical_operator (XOR, DImode, operands); DONE;")
5777 ; xorsi3 instruction pattern(s).
5780 (define_insn "*xorsi3_cc"
5782 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5783 (match_operand:SI 2 "general_operand" "d,R,T"))
5785 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5786 (xor:SI (match_dup 1) (match_dup 2)))]
5787 "s390_match_ccmode(insn, CCTmode)"
5792 [(set_attr "op_type" "RR,RX,RXY")])
5794 (define_insn "*xorsi3_cconly"
5796 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5797 (match_operand:SI 2 "general_operand" "d,R,T"))
5799 (clobber (match_scratch:SI 0 "=d,d,d"))]
5800 "s390_match_ccmode(insn, CCTmode)"
5805 [(set_attr "op_type" "RR,RX,RXY")])
5807 (define_insn "*xorsi3"
5808 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q")
5809 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5810 (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q")))
5811 (clobber (reg:CC 33))]
5812 "s390_logical_operator_ok_p (operands)"
5819 [(set_attr "op_type" "RR,RX,RXY,SI,SS")])
5822 [(set (match_operand:SI 0 "s_operand" "")
5823 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5824 (clobber (reg:CC 33))]
5827 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5828 (clobber (reg:CC 33))])]
5829 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5831 (define_expand "xorsi3"
5832 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5833 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
5834 (match_operand:SI 2 "general_operand" "")))
5835 (clobber (reg:CC 33))]
5837 "s390_expand_logical_operator (XOR, SImode, operands); DONE;")
5840 ; xorhi3 instruction pattern(s).
5843 (define_insn "*xorhi3"
5844 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5845 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5846 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5847 (clobber (reg:CC 33))]
5848 "s390_logical_operator_ok_p (operands)"
5853 [(set_attr "op_type" "RR,SI,SS")])
5856 [(set (match_operand:HI 0 "s_operand" "")
5857 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5858 (clobber (reg:CC 33))]
5861 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5862 (clobber (reg:CC 33))])]
5863 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5865 (define_expand "xorhi3"
5866 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5867 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
5868 (match_operand:HI 2 "general_operand" "")))
5869 (clobber (reg:CC 33))]
5871 "s390_expand_logical_operator (XOR, HImode, operands); DONE;")
5874 ; xorqi3 instruction pattern(s).
5877 (define_insn "*xorqi3"
5878 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q")
5879 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0")
5880 (match_operand:QI 2 "general_operand" "d,n,n,Q")))
5881 (clobber (reg:CC 33))]
5882 "s390_logical_operator_ok_p (operands)"
5888 [(set_attr "op_type" "RR,SI,SIY,SS")])
5890 (define_expand "xorqi3"
5891 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5892 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
5893 (match_operand:QI 2 "general_operand" "")))
5894 (clobber (reg:CC 33))]
5896 "s390_expand_logical_operator (XOR, QImode, operands); DONE;")
5899 ; Block exclusive or (XC) patterns.
5903 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5904 (xor:BLK (match_dup 0)
5905 (match_operand:BLK 1 "memory_operand" "Q")))
5906 (use (match_operand 2 "const_int_operand" "n"))
5907 (clobber (reg:CC 33))]
5908 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5909 "xc\t%O0(%2,%R0),%S1"
5910 [(set_attr "op_type" "SS")])
5913 [(set (match_operand 0 "memory_operand" "")
5915 (match_operand 1 "memory_operand" "")))
5916 (clobber (reg:CC 33))]
5918 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5919 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5921 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5923 (clobber (reg:CC 33))])]
5925 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5926 operands[0] = adjust_address (operands[0], BLKmode, 0);
5927 operands[1] = adjust_address (operands[1], BLKmode, 0);
5932 [(set (match_operand:BLK 0 "memory_operand" "")
5933 (xor:BLK (match_dup 0)
5934 (match_operand:BLK 1 "memory_operand" "")))
5935 (use (match_operand 2 "const_int_operand" ""))
5936 (clobber (reg:CC 33))])
5938 [(set (match_operand:BLK 3 "memory_operand" "")
5939 (xor:BLK (match_dup 3)
5940 (match_operand:BLK 4 "memory_operand" "")))
5941 (use (match_operand 5 "const_int_operand" ""))
5942 (clobber (reg:CC 33))])]
5943 "s390_offset_p (operands[0], operands[3], operands[2])
5944 && s390_offset_p (operands[1], operands[4], operands[2])
5945 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5947 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5949 (clobber (reg:CC 33))])]
5950 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5951 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5952 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5955 ; Block xor (XC) patterns with src == dest.
5958 (define_insn "*xc_zero"
5959 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5961 (use (match_operand 1 "const_int_operand" "n"))
5962 (clobber (reg:CC 33))]
5963 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5964 "xc\t%O0(%1,%R0),%S0"
5965 [(set_attr "op_type" "SS")])
5969 [(set (match_operand:BLK 0 "memory_operand" "")
5971 (use (match_operand 1 "const_int_operand" ""))
5972 (clobber (reg:CC 33))])
5974 [(set (match_operand:BLK 2 "memory_operand" "")
5976 (use (match_operand 3 "const_int_operand" ""))
5977 (clobber (reg:CC 33))])]
5978 "s390_offset_p (operands[0], operands[2], operands[1])
5979 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5981 [(set (match_dup 4) (const_int 0))
5983 (clobber (reg:CC 33))])]
5984 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5985 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5989 ;;- Negate instructions.
5993 ; negdi2 instruction pattern(s).
5996 (define_expand "negdi2"
5998 [(set (match_operand:DI 0 "register_operand" "=d")
5999 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6000 (clobber (reg:CC 33))])]
6004 (define_insn "*negdi2_sign_cc"
6006 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
6007 (match_operand:SI 1 "register_operand" "d") 0)
6008 (const_int 32)) (const_int 32)))
6010 (set (match_operand:DI 0 "register_operand" "=d")
6011 (neg:DI (sign_extend:DI (match_dup 1))))]
6012 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6014 [(set_attr "op_type" "RRE")])
6016 (define_insn "*negdi2_sign"
6017 [(set (match_operand:DI 0 "register_operand" "=d")
6018 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6019 (clobber (reg:CC 33))]
6022 [(set_attr "op_type" "RRE")])
6024 (define_insn "*negdi2_cc"
6026 (compare (neg:DI (match_operand:DI 1 "register_operand" "d"))
6028 (set (match_operand:DI 0 "register_operand" "=d")
6029 (neg:DI (match_dup 1)))]
6030 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6032 [(set_attr "op_type" "RRE")])
6034 (define_insn "*negdi2_cconly"
6036 (compare (neg:DI (match_operand:DI 1 "register_operand" "d"))
6038 (clobber (match_scratch:DI 0 "=d"))]
6039 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6041 [(set_attr "op_type" "RRE")])
6043 (define_insn "*negdi2_64"
6044 [(set (match_operand:DI 0 "register_operand" "=d")
6045 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6046 (clobber (reg:CC 33))]
6049 [(set_attr "op_type" "RRE")])
6051 (define_insn_and_split "*negdi2_31"
6052 [(set (match_operand:DI 0 "register_operand" "=d")
6053 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6054 (clobber (reg:CC 33))]
6057 "&& reload_completed"
6059 [(set (match_dup 2) (neg:SI (match_dup 3)))
6060 (clobber (reg:CC 33))])
6063 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
6064 (set (match_dup 4) (neg:SI (match_dup 5)))])
6066 (if_then_else (ne (reg:CCAP 33) (const_int 0))
6068 (label_ref (match_dup 6))))
6070 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
6071 (clobber (reg:CC 33))])
6073 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
6074 operands[3] = operand_subword (operands[1], 0, 0, DImode);
6075 operands[4] = operand_subword (operands[0], 1, 0, DImode);
6076 operands[5] = operand_subword (operands[1], 1, 0, DImode);
6077 operands[6] = gen_label_rtx ();")
6080 ; negsi2 instruction pattern(s).
6083 (define_insn "*negsi2_cc"
6085 (compare (neg:SI (match_operand:SI 1 "register_operand" "d"))
6087 (set (match_operand:SI 0 "register_operand" "=d")
6088 (neg:SI (match_dup 1)))]
6089 "s390_match_ccmode (insn, CCAmode)"
6091 [(set_attr "op_type" "RR")])
6093 (define_insn "*negsi2_cconly"
6095 (compare (neg:SI (match_operand:SI 1 "register_operand" "d"))
6097 (clobber (match_scratch:SI 0 "=d"))]
6098 "s390_match_ccmode (insn, CCAmode)"
6100 [(set_attr "op_type" "RR")])
6102 (define_insn "negsi2"
6103 [(set (match_operand:SI 0 "register_operand" "=d")
6104 (neg:SI (match_operand:SI 1 "register_operand" "d")))
6105 (clobber (reg:CC 33))]
6108 [(set_attr "op_type" "RR")])
6111 ; negdf2 instruction pattern(s).
6114 (define_expand "negdf2"
6116 [(set (match_operand:DF 0 "register_operand" "=f")
6117 (neg:DF (match_operand:DF 1 "register_operand" "f")))
6118 (clobber (reg:CC 33))])]
6122 (define_insn "*negdf2_cc"
6124 (compare (neg:DF (match_operand:DF 1 "register_operand" "f"))
6125 (match_operand:DF 2 "const0_operand" "")))
6126 (set (match_operand:DF 0 "register_operand" "=f")
6127 (neg:DF (match_dup 1)))]
6128 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6130 [(set_attr "op_type" "RRE")
6131 (set_attr "type" "fsimpd")])
6133 (define_insn "*negdf2_cconly"
6135 (compare (neg:DF (match_operand:DF 1 "register_operand" "f"))
6136 (match_operand:DF 2 "const0_operand" "")))
6137 (clobber (match_scratch:DF 0 "=f"))]
6138 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6140 [(set_attr "op_type" "RRE")
6141 (set_attr "type" "fsimpd")])
6143 (define_insn "*negdf2"
6144 [(set (match_operand:DF 0 "register_operand" "=f")
6145 (neg:DF (match_operand:DF 1 "register_operand" "f")))
6146 (clobber (reg:CC 33))]
6147 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6149 [(set_attr "op_type" "RRE")
6150 (set_attr "type" "fsimpd")])
6152 (define_insn "*negdf2_ibm"
6153 [(set (match_operand:DF 0 "register_operand" "=f")
6154 (neg:DF (match_operand:DF 1 "register_operand" "f")))
6155 (clobber (reg:CC 33))]
6156 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6158 [(set_attr "op_type" "RR")
6159 (set_attr "type" "fsimpd")])
6162 ; negsf2 instruction pattern(s).
6165 (define_expand "negsf2"
6167 [(set (match_operand:SF 0 "register_operand" "=f")
6168 (neg:SF (match_operand:SF 1 "register_operand" "f")))
6169 (clobber (reg:CC 33))])]
6173 (define_insn "*negsf2_cc"
6175 (compare (neg:SF (match_operand:SF 1 "register_operand" "f"))
6176 (match_operand:SF 2 "const0_operand" "")))
6177 (set (match_operand:SF 0 "register_operand" "=f")
6178 (neg:SF (match_dup 1)))]
6179 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6181 [(set_attr "op_type" "RRE")
6182 (set_attr "type" "fsimps")])
6184 (define_insn "*negsf2_cconly"
6186 (compare (neg:SF (match_operand:SF 1 "register_operand" "f"))
6187 (match_operand:SF 2 "const0_operand" "")))
6188 (clobber (match_scratch:SF 0 "=f"))]
6189 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6191 [(set_attr "op_type" "RRE")
6192 (set_attr "type" "fsimps")])
6194 (define_insn "*negsf2"
6195 [(set (match_operand:SF 0 "register_operand" "=f")
6196 (neg:SF (match_operand:SF 1 "register_operand" "f")))
6197 (clobber (reg:CC 33))]
6198 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6200 [(set_attr "op_type" "RRE")
6201 (set_attr "type" "fsimps")])
6203 (define_insn "*negsf2"
6204 [(set (match_operand:SF 0 "register_operand" "=f")
6205 (neg:SF (match_operand:SF 1 "register_operand" "f")))
6206 (clobber (reg:CC 33))]
6207 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6209 [(set_attr "op_type" "RR")
6210 (set_attr "type" "fsimps")])
6214 ;;- Absolute value instructions.
6218 ; absdi2 instruction pattern(s).
6221 (define_insn "*absdi2_sign_cc"
6223 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6224 (match_operand:SI 1 "register_operand" "d") 0)
6225 (const_int 32)) (const_int 32)))
6227 (set (match_operand:DI 0 "register_operand" "=d")
6228 (abs:DI (sign_extend:DI (match_dup 1))))]
6229 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6231 [(set_attr "op_type" "RRE")])
6233 (define_insn "*absdi2_sign"
6234 [(set (match_operand:DI 0 "register_operand" "=d")
6235 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6236 (clobber (reg:CC 33))]
6239 [(set_attr "op_type" "RRE")])
6241 (define_insn "*absdi2_cc"
6243 (compare (abs:DI (match_operand:DI 1 "register_operand" "d"))
6245 (set (match_operand:DI 0 "register_operand" "=d")
6246 (abs:DI (match_dup 1)))]
6247 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6249 [(set_attr "op_type" "RRE")])
6251 (define_insn "*absdi2_cconly"
6253 (compare (abs:DI (match_operand:DI 1 "register_operand" "d"))
6255 (clobber (match_scratch:DI 0 "=d"))]
6256 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6258 [(set_attr "op_type" "RRE")])
6260 (define_insn "absdi2"
6261 [(set (match_operand:DI 0 "register_operand" "=d")
6262 (abs:DI (match_operand:DI 1 "register_operand" "d")))
6263 (clobber (reg:CC 33))]
6266 [(set_attr "op_type" "RRE")])
6269 ; abssi2 instruction pattern(s).
6272 (define_insn "*abssi2_cc"
6274 (compare (abs:SI (match_operand:SI 1 "register_operand" "d"))
6276 (set (match_operand:SI 0 "register_operand" "=d")
6277 (abs:SI (match_dup 1)))]
6278 "s390_match_ccmode (insn, CCAmode)"
6280 [(set_attr "op_type" "RR")])
6282 (define_insn "*abssi2_cconly"
6284 (compare (abs:SI (match_operand:SI 1 "register_operand" "d"))
6286 (clobber (match_scratch:SI 0 "=d"))]
6287 "s390_match_ccmode (insn, CCAmode)"
6289 [(set_attr "op_type" "RR")])
6291 (define_insn "abssi2"
6292 [(set (match_operand:SI 0 "register_operand" "=d")
6293 (abs:SI (match_operand:SI 1 "register_operand" "d")))
6294 (clobber (reg:CC 33))]
6297 [(set_attr "op_type" "RR")])
6300 ; absdf2 instruction pattern(s).
6303 (define_expand "absdf2"
6305 [(set (match_operand:DF 0 "register_operand" "=f")
6306 (abs:DF (match_operand:DF 1 "register_operand" "f")))
6307 (clobber (reg:CC 33))])]
6311 (define_insn "*absdf2_cc"
6313 (compare (abs:DF (match_operand:DF 1 "register_operand" "f"))
6314 (match_operand:DF 2 "const0_operand" "")))
6315 (set (match_operand:DF 0 "register_operand" "=f")
6316 (abs:DF (match_dup 1)))]
6317 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6319 [(set_attr "op_type" "RRE")
6320 (set_attr "type" "fsimpd")])
6322 (define_insn "*absdf2_cconly"
6324 (compare (abs:DF (match_operand:DF 1 "register_operand" "f"))
6325 (match_operand:DF 2 "const0_operand" "")))
6326 (clobber (match_scratch:DF 0 "=f"))]
6327 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6329 [(set_attr "op_type" "RRE")
6330 (set_attr "type" "fsimpd")])
6332 (define_insn "*absdf2"
6333 [(set (match_operand:DF 0 "register_operand" "=f")
6334 (abs:DF (match_operand:DF 1 "register_operand" "f")))
6335 (clobber (reg:CC 33))]
6336 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6338 [(set_attr "op_type" "RRE")
6339 (set_attr "type" "fsimpd")])
6341 (define_insn "*absdf2_ibm"
6342 [(set (match_operand:DF 0 "register_operand" "=f")
6343 (abs:DF (match_operand:DF 1 "register_operand" "f")))
6344 (clobber (reg:CC 33))]
6345 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6347 [(set_attr "op_type" "RR")
6348 (set_attr "type" "fsimpd")])
6351 ; abssf2 instruction pattern(s).
6354 (define_expand "abssf2"
6356 [(set (match_operand:SF 0 "register_operand" "=f")
6357 (abs:SF (match_operand:SF 1 "register_operand" "f")))
6358 (clobber (reg:CC 33))])]
6362 (define_insn "*abssf2_cc"
6364 (compare (abs:SF (match_operand:SF 1 "register_operand" "f"))
6365 (match_operand:SF 2 "const0_operand" "")))
6366 (set (match_operand:SF 0 "register_operand" "=f")
6367 (abs:SF (match_dup 1)))]
6368 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6370 [(set_attr "op_type" "RRE")
6371 (set_attr "type" "fsimps")])
6373 (define_insn "*abssf2_cconly"
6375 (compare (abs:SF (match_operand:SF 1 "register_operand" "f"))
6376 (match_operand:SF 2 "const0_operand" "")))
6377 (clobber (match_scratch:SF 0 "=f"))]
6378 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6380 [(set_attr "op_type" "RRE")
6381 (set_attr "type" "fsimps")])
6383 (define_insn "*abssf2"
6384 [(set (match_operand:SF 0 "register_operand" "=f")
6385 (abs:SF (match_operand:SF 1 "register_operand" "f")))
6386 (clobber (reg:CC 33))]
6387 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6389 [(set_attr "op_type" "RRE")
6390 (set_attr "type" "fsimps")])
6392 (define_insn "*abssf2_ibm"
6393 [(set (match_operand:SF 0 "register_operand" "=f")
6394 (abs:SF (match_operand:SF 1 "register_operand" "f")))
6395 (clobber (reg:CC 33))]
6396 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6398 [(set_attr "op_type" "RR")
6399 (set_attr "type" "fsimps")])
6402 ;;- Negated absolute value instructions
6409 (define_insn "*negabsdi2_sign_cc"
6411 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6412 (match_operand:SI 1 "register_operand" "d") 0)
6413 (const_int 32)) (const_int 32))))
6415 (set (match_operand:DI 0 "register_operand" "=d")
6416 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6417 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6419 [(set_attr "op_type" "RRE")])
6421 (define_insn "*negabsdi2_sign"
6422 [(set (match_operand:DI 0 "register_operand" "=d")
6423 (neg:DI (abs:DI (sign_extend:DI
6424 (match_operand:SI 1 "register_operand" "d")))))
6425 (clobber (reg:CC 33))]
6428 [(set_attr "op_type" "RRE")])
6430 (define_insn "*negabsdi2_cc"
6432 (compare (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))
6434 (set (match_operand:DI 0 "register_operand" "=d")
6435 (neg:DI (abs:DI (match_dup 1))))]
6436 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6438 [(set_attr "op_type" "RRE")])
6440 (define_insn "*negabsdi2_cconly"
6442 (compare (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))
6444 (clobber (match_scratch:DI 0 "=d"))]
6445 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6447 [(set_attr "op_type" "RRE")])
6449 (define_insn "*negabsdi2"
6450 [(set (match_operand:DI 0 "register_operand" "=d")
6451 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d"))))
6452 (clobber (reg:CC 33))]
6455 [(set_attr "op_type" "RRE")])
6457 (define_insn "*negabssi2_cc"
6459 (compare (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))
6461 (set (match_operand:SI 0 "register_operand" "=d")
6462 (neg:SI (abs:SI (match_dup 1))))]
6463 "s390_match_ccmode (insn, CCAmode)"
6465 [(set_attr "op_type" "RR")])
6467 (define_insn "*negabssi2_cconly"
6469 (compare (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))
6471 (clobber (match_scratch:SI 0 "=d"))]
6472 "s390_match_ccmode (insn, CCAmode)"
6474 [(set_attr "op_type" "RR")])
6476 (define_insn "*negabssi2"
6477 [(set (match_operand:SI 0 "register_operand" "=d")
6478 (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d"))))
6479 (clobber (reg:CC 33))]
6482 [(set_attr "op_type" "RR")])
6488 (define_insn "*negabsdf2_cc"
6490 (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))
6491 (match_operand:DF 2 "const0_operand" "")))
6492 (set (match_operand:DF 0 "register_operand" "=f")
6493 (neg:DF (abs:DF (match_dup 1))))]
6494 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6496 [(set_attr "op_type" "RRE")
6497 (set_attr "type" "fsimpd")])
6499 (define_insn "*negabsdf2_cconly"
6501 (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))
6502 (match_operand:DF 2 "const0_operand" "")))
6503 (clobber (match_scratch:DF 0 "=f"))]
6504 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6506 [(set_attr "op_type" "RRE")
6507 (set_attr "type" "fsimpd")])
6509 (define_insn "*negabsdf2"
6510 [(set (match_operand:DF 0 "register_operand" "=f")
6511 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6512 (clobber (reg:CC 33))]
6513 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6515 [(set_attr "op_type" "RRE")
6516 (set_attr "type" "fsimpd")])
6518 (define_insn "*negabssf2_cc"
6520 (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))
6521 (match_operand:SF 2 "const0_operand" "")))
6522 (set (match_operand:SF 0 "register_operand" "=f")
6523 (neg:SF (abs:SF (match_dup 1))))]
6524 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6526 [(set_attr "op_type" "RRE")
6527 (set_attr "type" "fsimps")])
6529 (define_insn "*negabssf2_cconly"
6531 (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))
6532 (match_operand:SF 2 "const0_operand" "")))
6533 (clobber (match_scratch:SF 0 "=f"))]
6534 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6536 [(set_attr "op_type" "RRE")
6537 (set_attr "type" "fsimps")])
6539 (define_insn "*negabssf2"
6540 [(set (match_operand:SF 0 "register_operand" "=f")
6541 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6542 (clobber (reg:CC 33))]
6543 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6545 [(set_attr "op_type" "RRE")
6546 (set_attr "type" "fsimps")])
6549 ;;- Square root instructions.
6553 ; sqrtdf2 instruction pattern(s).
6556 (define_insn "sqrtdf2"
6557 [(set (match_operand:DF 0 "register_operand" "=f,f")
6558 (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))]
6559 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6563 [(set_attr "op_type" "RRE,RXE")
6564 (set_attr "type" "fsqrtd")])
6567 ; sqrtsf2 instruction pattern(s).
6570 (define_insn "sqrtsf2"
6571 [(set (match_operand:SF 0 "register_operand" "=f,f")
6572 (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))]
6573 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6577 [(set_attr "op_type" "RRE,RXE")
6578 (set_attr "type" "fsqrts")])
6581 ;;- One complement instructions.
6585 ; one_cmpldi2 instruction pattern(s).
6588 (define_expand "one_cmpldi2"
6590 [(set (match_operand:DI 0 "register_operand" "")
6591 (xor:DI (match_operand:DI 1 "register_operand" "")
6593 (clobber (reg:CC 33))])]
6598 ; one_cmplsi2 instruction pattern(s).
6601 (define_expand "one_cmplsi2"
6603 [(set (match_operand:SI 0 "register_operand" "")
6604 (xor:SI (match_operand:SI 1 "register_operand" "")
6606 (clobber (reg:CC 33))])]
6611 ; one_cmplhi2 instruction pattern(s).
6614 (define_expand "one_cmplhi2"
6616 [(set (match_operand:HI 0 "register_operand" "")
6617 (xor:HI (match_operand:HI 1 "register_operand" "")
6619 (clobber (reg:CC 33))])]
6624 ; one_cmplqi2 instruction pattern(s).
6627 (define_expand "one_cmplqi2"
6629 [(set (match_operand:QI 0 "register_operand" "")
6630 (xor:QI (match_operand:QI 1 "register_operand" "")
6632 (clobber (reg:CC 33))])]
6638 ;;- Rotate instructions.
6642 ; rotldi3 instruction pattern(s).
6645 (define_insn "rotldi3"
6646 [(set (match_operand:DI 0 "register_operand" "=d")
6647 (rotate:DI (match_operand:DI 1 "register_operand" "d")
6648 (match_operand:SI 2 "shift_count_operand" "Y")))]
6651 [(set_attr "op_type" "RSE")
6652 (set_attr "atype" "reg")])
6655 ; rotlsi3 instruction pattern(s).
6658 (define_insn "rotlsi3"
6659 [(set (match_operand:SI 0 "register_operand" "=d")
6660 (rotate:SI (match_operand:SI 1 "register_operand" "d")
6661 (match_operand:SI 2 "shift_count_operand" "Y")))]
6664 [(set_attr "op_type" "RSE")
6665 (set_attr "atype" "reg")])
6669 ;;- Arithmetic shift instructions.
6673 ; ashldi3 instruction pattern(s).
6676 (define_expand "ashldi3"
6677 [(set (match_operand:DI 0 "register_operand" "")
6678 (ashift:DI (match_operand:DI 1 "register_operand" "")
6679 (match_operand:SI 2 "shift_count_operand" "")))]
6683 (define_insn "*ashldi3_31"
6684 [(set (match_operand:DI 0 "register_operand" "=d")
6685 (ashift:DI (match_operand:DI 1 "register_operand" "0")
6686 (match_operand:SI 2 "shift_count_operand" "Y")))]
6689 [(set_attr "op_type" "RS")
6690 (set_attr "atype" "reg")])
6692 (define_insn "*ashldi3_64"
6693 [(set (match_operand:DI 0 "register_operand" "=d")
6694 (ashift:DI (match_operand:DI 1 "register_operand" "d")
6695 (match_operand:SI 2 "shift_count_operand" "Y")))]
6698 [(set_attr "op_type" "RSE")
6699 (set_attr "atype" "reg")])
6702 ; ashrdi3 instruction pattern(s).
6705 (define_expand "ashrdi3"
6707 [(set (match_operand:DI 0 "register_operand" "")
6708 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6709 (match_operand:SI 2 "shift_count_operand" "")))
6710 (clobber (reg:CC 33))])]
6714 (define_insn "*ashrdi3_cc_31"
6716 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6717 (match_operand:SI 2 "shift_count_operand" "Y"))
6719 (set (match_operand:DI 0 "register_operand" "=d")
6720 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6721 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6723 [(set_attr "op_type" "RS")
6724 (set_attr "atype" "reg")])
6726 (define_insn "*ashrdi3_cconly_31"
6728 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6729 (match_operand:SI 2 "shift_count_operand" "Y"))
6731 (clobber (match_scratch:DI 0 "=d"))]
6732 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6734 [(set_attr "op_type" "RS")
6735 (set_attr "atype" "reg")])
6737 (define_insn "*ashrdi3_31"
6738 [(set (match_operand:DI 0 "register_operand" "=d")
6739 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6740 (match_operand:SI 2 "shift_count_operand" "Y")))
6741 (clobber (reg:CC 33))]
6744 [(set_attr "op_type" "RS")
6745 (set_attr "atype" "reg")])
6747 (define_insn "*ashrdi3_cc_64"
6749 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6750 (match_operand:SI 2 "shift_count_operand" "Y"))
6752 (set (match_operand:DI 0 "register_operand" "=d")
6753 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6754 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6756 [(set_attr "op_type" "RSE")
6757 (set_attr "atype" "reg")])
6759 (define_insn "*ashrdi3_cconly_64"
6761 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6762 (match_operand:SI 2 "shift_count_operand" "Y"))
6764 (clobber (match_scratch:DI 0 "=d"))]
6765 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6767 [(set_attr "op_type" "RSE")
6768 (set_attr "atype" "reg")])
6770 (define_insn "*ashrdi3_64"
6771 [(set (match_operand:DI 0 "register_operand" "=d")
6772 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6773 (match_operand:SI 2 "shift_count_operand" "Y")))
6774 (clobber (reg:CC 33))]
6777 [(set_attr "op_type" "RSE")
6778 (set_attr "atype" "reg")])
6782 ; ashlsi3 instruction pattern(s).
6785 (define_insn "ashlsi3"
6786 [(set (match_operand:SI 0 "register_operand" "=d")
6787 (ashift:SI (match_operand:SI 1 "register_operand" "0")
6788 (match_operand:SI 2 "shift_count_operand" "Y")))]
6791 [(set_attr "op_type" "RS")
6792 (set_attr "atype" "reg")])
6795 ; ashrsi3 instruction pattern(s).
6798 (define_insn "*ashrsi3_cc"
6800 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6801 (match_operand:SI 2 "shift_count_operand" "Y"))
6803 (set (match_operand:SI 0 "register_operand" "=d")
6804 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
6805 "s390_match_ccmode(insn, CCSmode)"
6807 [(set_attr "op_type" "RS")
6808 (set_attr "atype" "reg")])
6811 (define_insn "*ashrsi3_cconly"
6813 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6814 (match_operand:SI 2 "shift_count_operand" "Y"))
6816 (clobber (match_scratch:SI 0 "=d"))]
6817 "s390_match_ccmode(insn, CCSmode)"
6819 [(set_attr "op_type" "RS")
6820 (set_attr "atype" "reg")])
6822 (define_insn "ashrsi3"
6823 [(set (match_operand:SI 0 "register_operand" "=d")
6824 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6825 (match_operand:SI 2 "shift_count_operand" "Y")))
6826 (clobber (reg:CC 33))]
6829 [(set_attr "op_type" "RS")
6830 (set_attr "atype" "reg")])
6834 ;;- logical shift instructions.
6838 ; lshrdi3 instruction pattern(s).
6841 (define_expand "lshrdi3"
6842 [(set (match_operand:DI 0 "register_operand" "")
6843 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
6844 (match_operand:SI 2 "shift_count_operand" "")))]
6848 (define_insn "*lshrdi3_31"
6849 [(set (match_operand:DI 0 "register_operand" "=d")
6850 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
6851 (match_operand:SI 2 "shift_count_operand" "Y")))]
6854 [(set_attr "op_type" "RS")
6855 (set_attr "atype" "reg")])
6857 (define_insn "*lshrdi3_64"
6858 [(set (match_operand:DI 0 "register_operand" "=d")
6859 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
6860 (match_operand:SI 2 "shift_count_operand" "Y")))]
6863 [(set_attr "op_type" "RSE")
6864 (set_attr "atype" "reg")])
6867 ; lshrsi3 instruction pattern(s).
6870 (define_insn "lshrsi3"
6871 [(set (match_operand:SI 0 "register_operand" "=d")
6872 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
6873 (match_operand:SI 2 "shift_count_operand" "Y")))]
6876 [(set_attr "op_type" "RS")
6877 (set_attr "atype" "reg")])
6881 ;; Branch instruction patterns.
6884 (define_expand "beq"
6885 [(match_operand 0 "" "")]
6887 "s390_emit_jump (operands[0],
6888 s390_emit_compare (EQ, s390_compare_op0, s390_compare_op1)); DONE;")
6890 (define_expand "bne"
6891 [(match_operand 0 "" "")]
6893 "s390_emit_jump (operands[0],
6894 s390_emit_compare (NE, s390_compare_op0, s390_compare_op1)); DONE;")
6896 (define_expand "bgt"
6897 [(match_operand 0 "" "")]
6899 "s390_emit_jump (operands[0],
6900 s390_emit_compare (GT, s390_compare_op0, s390_compare_op1)); DONE;")
6902 (define_expand "bgtu"
6903 [(match_operand 0 "" "")]
6905 "s390_emit_jump (operands[0],
6906 s390_emit_compare (GTU, s390_compare_op0, s390_compare_op1)); DONE;")
6908 (define_expand "blt"
6909 [(match_operand 0 "" "")]
6911 "s390_emit_jump (operands[0],
6912 s390_emit_compare (LT, s390_compare_op0, s390_compare_op1)); DONE;")
6914 (define_expand "bltu"
6915 [(match_operand 0 "" "")]
6917 "s390_emit_jump (operands[0],
6918 s390_emit_compare (LTU, s390_compare_op0, s390_compare_op1)); DONE;")
6920 (define_expand "bge"
6921 [(match_operand 0 "" "")]
6923 "s390_emit_jump (operands[0],
6924 s390_emit_compare (GE, s390_compare_op0, s390_compare_op1)); DONE;")
6926 (define_expand "bgeu"
6927 [(match_operand 0 "" "")]
6929 "s390_emit_jump (operands[0],
6930 s390_emit_compare (GEU, s390_compare_op0, s390_compare_op1)); DONE;")
6932 (define_expand "ble"
6933 [(match_operand 0 "" "")]
6935 "s390_emit_jump (operands[0],
6936 s390_emit_compare (LE, s390_compare_op0, s390_compare_op1)); DONE;")
6938 (define_expand "bleu"
6939 [(match_operand 0 "" "")]
6941 "s390_emit_jump (operands[0],
6942 s390_emit_compare (LEU, s390_compare_op0, s390_compare_op1)); DONE;")
6944 (define_expand "bunordered"
6945 [(match_operand 0 "" "")]
6947 "s390_emit_jump (operands[0],
6948 s390_emit_compare (UNORDERED, s390_compare_op0, s390_compare_op1)); DONE;")
6950 (define_expand "bordered"
6951 [(match_operand 0 "" "")]
6953 "s390_emit_jump (operands[0],
6954 s390_emit_compare (ORDERED, s390_compare_op0, s390_compare_op1)); DONE;")
6956 (define_expand "buneq"
6957 [(match_operand 0 "" "")]
6959 "s390_emit_jump (operands[0],
6960 s390_emit_compare (UNEQ, s390_compare_op0, s390_compare_op1)); DONE;")
6962 (define_expand "bunlt"
6963 [(match_operand 0 "" "")]
6965 "s390_emit_jump (operands[0],
6966 s390_emit_compare (UNLT, s390_compare_op0, s390_compare_op1)); DONE;")
6968 (define_expand "bungt"
6969 [(match_operand 0 "" "")]
6971 "s390_emit_jump (operands[0],
6972 s390_emit_compare (UNGT, s390_compare_op0, s390_compare_op1)); DONE;")
6974 (define_expand "bunle"
6975 [(match_operand 0 "" "")]
6977 "s390_emit_jump (operands[0],
6978 s390_emit_compare (UNLE, s390_compare_op0, s390_compare_op1)); DONE;")
6980 (define_expand "bunge"
6981 [(match_operand 0 "" "")]
6983 "s390_emit_jump (operands[0],
6984 s390_emit_compare (UNGE, s390_compare_op0, s390_compare_op1)); DONE;")
6986 (define_expand "bltgt"
6987 [(match_operand 0 "" "")]
6989 "s390_emit_jump (operands[0],
6990 s390_emit_compare (LTGT, s390_compare_op0, s390_compare_op1)); DONE;")
6994 ;;- Conditional jump instructions.
6997 (define_insn "*cjump_64"
7000 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7001 (label_ref (match_operand 0 "" ""))
7005 if (get_attr_length (insn) == 4)
7008 return "jg%C1\t%l0";
7010 [(set_attr "op_type" "RI")
7011 (set_attr "type" "branch")
7012 (set (attr "length")
7013 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7014 (const_int 4) (const_int 6)))])
7016 (define_insn "*cjump_31"
7019 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7020 (label_ref (match_operand 0 "" ""))
7024 if (get_attr_length (insn) == 4)
7029 [(set_attr "op_type" "RI")
7030 (set_attr "type" "branch")
7031 (set (attr "length")
7032 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7033 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7034 (const_int 4) (const_int 6))
7035 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7036 (const_int 4) (const_int 8))))])
7038 (define_insn "*cjump_long"
7041 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7042 (match_operand 0 "address_operand" "U")
7046 if (get_attr_op_type (insn) == OP_TYPE_RR)
7051 [(set (attr "op_type")
7052 (if_then_else (match_operand 0 "register_operand" "")
7053 (const_string "RR") (const_string "RX")))
7054 (set_attr "type" "branch")
7055 (set_attr "atype" "agen")])
7059 ;;- Negated conditional jump instructions.
7062 (define_insn "*icjump_64"
7065 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7067 (label_ref (match_operand 0 "" ""))))]
7070 if (get_attr_length (insn) == 4)
7073 return "jg%D1\t%l0";
7075 [(set_attr "op_type" "RI")
7076 (set_attr "type" "branch")
7077 (set (attr "length")
7078 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7079 (const_int 4) (const_int 6)))])
7081 (define_insn "*icjump_31"
7084 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7086 (label_ref (match_operand 0 "" ""))))]
7089 if (get_attr_length (insn) == 4)
7094 [(set_attr "op_type" "RI")
7095 (set_attr "type" "branch")
7096 (set (attr "length")
7097 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7098 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7099 (const_int 4) (const_int 6))
7100 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7101 (const_int 4) (const_int 8))))])
7103 (define_insn "*icjump_long"
7106 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7108 (match_operand 0 "address_operand" "U")))]
7111 if (get_attr_op_type (insn) == OP_TYPE_RR)
7116 [(set (attr "op_type")
7117 (if_then_else (match_operand 0 "register_operand" "")
7118 (const_string "RR") (const_string "RX")))
7119 (set_attr "type" "branch")
7120 (set_attr "atype" "agen")])
7123 ;;- Trap instructions.
7127 [(trap_if (const_int 1) (const_int 0))]
7130 [(set_attr "op_type" "RI")
7131 (set_attr "type" "branch")])
7133 (define_expand "conditional_trap"
7134 [(trap_if (match_operand 0 "comparison_operator" "")
7135 (match_operand 1 "general_operand" ""))]
7138 if (operands[1] != const0_rtx) FAIL;
7139 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
7140 s390_compare_op0, s390_compare_op1);
7143 (define_insn "*trap"
7144 [(trap_if (match_operator 0 "s390_comparison" [(reg 33) (const_int 0)])
7148 [(set_attr "op_type" "RI")
7149 (set_attr "type" "branch")])
7152 ;;- Loop instructions.
7154 ;; This is all complicated by the fact that since this is a jump insn
7155 ;; we must handle our own output reloads.
7157 (define_expand "doloop_end"
7158 [(use (match_operand 0 "" "")) ; loop pseudo
7159 (use (match_operand 1 "" "")) ; iterations; zero if unknown
7160 (use (match_operand 2 "" "")) ; max iterations
7161 (use (match_operand 3 "" "")) ; loop level
7162 (use (match_operand 4 "" ""))] ; label
7165 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
7166 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
7167 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
7168 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
7169 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
7170 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
7177 (define_insn_and_split "doloop_si64"
7180 (ne (match_operand:SI 1 "register_operand" "d,d")
7182 (label_ref (match_operand 0 "" ""))
7184 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
7185 (plus:SI (match_dup 1) (const_int -1)))
7186 (clobber (match_scratch:SI 3 "=X,&1"))
7187 (clobber (reg:CC 33))]
7190 if (which_alternative != 0)
7192 else if (get_attr_length (insn) == 4)
7193 return "brct\t%1,%l0";
7195 return "ahi\t%1,-1\;jgne\t%l0";
7197 "&& reload_completed
7198 && (! REG_P (operands[2])
7199 || ! rtx_equal_p (operands[1], operands[2]))"
7200 [(parallel [(set (reg:CCAN 33)
7201 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7203 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7204 (set (match_dup 2) (match_dup 3))
7205 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
7206 (label_ref (match_dup 0))
7209 [(set_attr "op_type" "RI")
7210 (set_attr "type" "branch")
7211 (set (attr "length")
7212 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7213 (const_int 4) (const_int 10)))])
7215 (define_insn_and_split "doloop_si31"
7218 (ne (match_operand:SI 1 "register_operand" "d,d")
7220 (label_ref (match_operand 0 "" ""))
7222 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
7223 (plus:SI (match_dup 1) (const_int -1)))
7224 (clobber (match_scratch:SI 3 "=X,&1"))
7225 (clobber (reg:CC 33))]
7228 if (which_alternative != 0)
7230 else if (get_attr_length (insn) == 4)
7231 return "brct\t%1,%l0";
7235 "&& reload_completed
7236 && (! REG_P (operands[2])
7237 || ! rtx_equal_p (operands[1], operands[2]))"
7238 [(parallel [(set (reg:CCAN 33)
7239 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7241 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7242 (set (match_dup 2) (match_dup 3))
7243 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
7244 (label_ref (match_dup 0))
7247 [(set_attr "op_type" "RI")
7248 (set_attr "type" "branch")
7249 (set (attr "length")
7250 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7251 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7252 (const_int 4) (const_int 6))
7253 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7254 (const_int 4) (const_int 8))))])
7256 (define_insn "*doloop_si_long"
7259 (ne (match_operand:SI 1 "register_operand" "d,d")
7261 (match_operand 0 "address_operand" "U,U")
7263 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
7264 (plus:SI (match_dup 1) (const_int -1)))
7265 (clobber (match_scratch:SI 3 "=X,&1"))
7266 (clobber (reg:CC 33))]
7269 if (get_attr_op_type (insn) == OP_TYPE_RR)
7270 return "bctr\t%1,%0";
7272 return "bct\t%1,%a0";
7274 [(set (attr "op_type")
7275 (if_then_else (match_operand 0 "register_operand" "")
7276 (const_string "RR") (const_string "RX")))
7277 (set_attr "type" "branch")
7278 (set_attr "atype" "agen")])
7280 (define_insn_and_split "doloop_di"
7283 (ne (match_operand:DI 1 "register_operand" "d,d")
7285 (label_ref (match_operand 0 "" ""))
7287 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
7288 (plus:DI (match_dup 1) (const_int -1)))
7289 (clobber (match_scratch:DI 3 "=X,&1"))
7290 (clobber (reg:CC 33))]
7293 if (which_alternative != 0)
7295 else if (get_attr_length (insn) == 4)
7296 return "brctg\t%1,%l0";
7298 return "aghi\t%1,-1\;jgne\t%l0";
7300 "&& reload_completed
7301 && (! REG_P (operands[2])
7302 || ! rtx_equal_p (operands[1], operands[2]))"
7303 [(parallel [(set (reg:CCAN 33)
7304 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
7306 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
7307 (set (match_dup 2) (match_dup 3))
7308 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
7309 (label_ref (match_dup 0))
7312 [(set_attr "op_type" "RI")
7313 (set_attr "type" "branch")
7314 (set (attr "length")
7315 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7316 (const_int 4) (const_int 10)))])
7319 ;;- Unconditional jump instructions.
7323 ; jump instruction pattern(s).
7326 (define_expand "jump"
7327 [(match_operand 0 "" "")]
7329 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
7331 (define_insn "*jump64"
7332 [(set (pc) (label_ref (match_operand 0 "" "")))]
7335 if (get_attr_length (insn) == 4)
7340 [(set_attr "op_type" "RI")
7341 (set_attr "type" "branch")
7342 (set (attr "length")
7343 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7344 (const_int 4) (const_int 6)))])
7346 (define_insn "*jump31"
7347 [(set (pc) (label_ref (match_operand 0 "" "")))]
7350 if (get_attr_length (insn) == 4)
7355 [(set_attr "op_type" "RI")
7356 (set_attr "type" "branch")
7357 (set (attr "length")
7358 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7359 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7360 (const_int 4) (const_int 6))
7361 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7362 (const_int 4) (const_int 8))))])
7365 ; indirect-jump instruction pattern(s).
7368 (define_insn "indirect_jump"
7369 [(set (pc) (match_operand 0 "address_operand" "U"))]
7372 if (get_attr_op_type (insn) == OP_TYPE_RR)
7377 [(set (attr "op_type")
7378 (if_then_else (match_operand 0 "register_operand" "")
7379 (const_string "RR") (const_string "RX")))
7380 (set_attr "type" "branch")
7381 (set_attr "atype" "agen")])
7384 ; casesi instruction pattern(s).
7387 (define_insn "casesi_jump"
7388 [(set (pc) (match_operand 0 "address_operand" "U"))
7389 (use (label_ref (match_operand 1 "" "")))]
7392 if (get_attr_op_type (insn) == OP_TYPE_RR)
7397 [(set (attr "op_type")
7398 (if_then_else (match_operand 0 "register_operand" "")
7399 (const_string "RR") (const_string "RX")))
7400 (set_attr "type" "branch")
7401 (set_attr "atype" "agen")])
7403 (define_expand "casesi"
7404 [(match_operand:SI 0 "general_operand" "")
7405 (match_operand:SI 1 "general_operand" "")
7406 (match_operand:SI 2 "general_operand" "")
7407 (label_ref (match_operand 3 "" ""))
7408 (label_ref (match_operand 4 "" ""))]
7411 rtx index = gen_reg_rtx (SImode);
7412 rtx base = gen_reg_rtx (Pmode);
7413 rtx target = gen_reg_rtx (Pmode);
7415 emit_move_insn (index, operands[0]);
7416 emit_insn (gen_subsi3 (index, index, operands[1]));
7417 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
7420 if (Pmode != SImode)
7421 index = convert_to_mode (Pmode, index, 1);
7422 if (GET_CODE (index) != REG)
7423 index = copy_to_mode_reg (Pmode, index);
7426 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
7428 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
7430 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
7432 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
7433 emit_move_insn (target, index);
7436 target = gen_rtx_PLUS (Pmode, base, target);
7437 emit_jump_insn (gen_casesi_jump (target, operands[3]));
7444 ;;- Jump to subroutine.
7449 ; untyped call instruction pattern(s).
7452 ;; Call subroutine returning any type.
7453 (define_expand "untyped_call"
7454 [(parallel [(call (match_operand 0 "" "")
7456 (match_operand 1 "" "")
7457 (match_operand 2 "" "")])]
7462 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7464 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7466 rtx set = XVECEXP (operands[2], 0, i);
7467 emit_move_insn (SET_DEST (set), SET_SRC (set));
7470 /* The optimizer does not know that the call sets the function value
7471 registers we stored in the result block. We avoid problems by
7472 claiming that all hard registers are used and clobbered at this
7474 emit_insn (gen_blockage ());
7479 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7480 ;; all of memory. This blocks insns from being moved across this point.
7482 (define_insn "blockage"
7483 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7486 [(set_attr "type" "none")
7487 (set_attr "length" "0")])
7493 (define_expand "sibcall"
7494 [(call (match_operand 0 "" "")
7495 (match_operand 1 "" ""))]
7498 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
7502 (define_insn "*sibcall_br"
7503 [(call (mem:QI (reg 1))
7504 (match_operand 0 "const_int_operand" "n"))]
7505 "SIBLING_CALL_P (insn)
7506 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
7508 [(set_attr "op_type" "RR")
7509 (set_attr "type" "branch")
7510 (set_attr "atype" "agen")])
7512 (define_insn "*sibcall_brc"
7513 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7514 (match_operand 1 "const_int_operand" "n"))]
7515 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7517 [(set_attr "op_type" "RI")
7518 (set_attr "type" "branch")])
7520 (define_insn "*sibcall_brcl"
7521 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7522 (match_operand 1 "const_int_operand" "n"))]
7523 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7525 [(set_attr "op_type" "RIL")
7526 (set_attr "type" "branch")])
7529 ; sibcall_value patterns
7532 (define_expand "sibcall_value"
7533 [(set (match_operand 0 "" "")
7534 (call (match_operand 1 "" "")
7535 (match_operand 2 "" "")))]
7538 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
7542 (define_insn "*sibcall_value_br"
7543 [(set (match_operand 0 "" "")
7544 (call (mem:QI (reg 1))
7545 (match_operand 1 "const_int_operand" "n")))]
7546 "SIBLING_CALL_P (insn)
7547 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
7549 [(set_attr "op_type" "RR")
7550 (set_attr "type" "branch")
7551 (set_attr "atype" "agen")])
7553 (define_insn "*sibcall_value_brc"
7554 [(set (match_operand 0 "" "")
7555 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7556 (match_operand 2 "const_int_operand" "n")))]
7557 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7559 [(set_attr "op_type" "RI")
7560 (set_attr "type" "branch")])
7562 (define_insn "*sibcall_value_brcl"
7563 [(set (match_operand 0 "" "")
7564 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7565 (match_operand 2 "const_int_operand" "n")))]
7566 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7568 [(set_attr "op_type" "RIL")
7569 (set_attr "type" "branch")])
7573 ; call instruction pattern(s).
7576 (define_expand "call"
7577 [(call (match_operand 0 "" "")
7578 (match_operand 1 "" ""))
7579 (use (match_operand 2 "" ""))]
7582 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
7583 gen_rtx_REG (Pmode, RETURN_REGNUM));
7587 (define_insn "*bras"
7588 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7589 (match_operand 1 "const_int_operand" "n"))
7590 (clobber (match_operand 2 "register_operand" "=r"))]
7591 "!SIBLING_CALL_P (insn)
7592 && TARGET_SMALL_EXEC
7593 && GET_MODE (operands[2]) == Pmode"
7595 [(set_attr "op_type" "RI")
7596 (set_attr "type" "jsr")])
7598 (define_insn "*brasl"
7599 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7600 (match_operand 1 "const_int_operand" "n"))
7601 (clobber (match_operand 2 "register_operand" "=r"))]
7602 "!SIBLING_CALL_P (insn)
7604 && GET_MODE (operands[2]) == Pmode"
7606 [(set_attr "op_type" "RIL")
7607 (set_attr "type" "jsr")])
7609 (define_insn "*basr"
7610 [(call (mem:QI (match_operand 0 "address_operand" "U"))
7611 (match_operand 1 "const_int_operand" "n"))
7612 (clobber (match_operand 2 "register_operand" "=r"))]
7613 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
7615 if (get_attr_op_type (insn) == OP_TYPE_RR)
7616 return "basr\t%2,%0";
7618 return "bas\t%2,%a0";
7620 [(set (attr "op_type")
7621 (if_then_else (match_operand 0 "register_operand" "")
7622 (const_string "RR") (const_string "RX")))
7623 (set_attr "type" "jsr")
7624 (set_attr "atype" "agen")])
7627 ; call_value instruction pattern(s).
7630 (define_expand "call_value"
7631 [(set (match_operand 0 "" "")
7632 (call (match_operand 1 "" "")
7633 (match_operand 2 "" "")))
7634 (use (match_operand 3 "" ""))]
7637 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
7638 gen_rtx_REG (Pmode, RETURN_REGNUM));
7642 (define_insn "*bras_r"
7643 [(set (match_operand 0 "" "")
7644 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7645 (match_operand:SI 2 "const_int_operand" "n")))
7646 (clobber (match_operand 3 "register_operand" "=r"))]
7647 "!SIBLING_CALL_P (insn)
7648 && TARGET_SMALL_EXEC
7649 && GET_MODE (operands[3]) == Pmode"
7651 [(set_attr "op_type" "RI")
7652 (set_attr "type" "jsr")])
7654 (define_insn "*brasl_r"
7655 [(set (match_operand 0 "" "")
7656 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7657 (match_operand 2 "const_int_operand" "n")))
7658 (clobber (match_operand 3 "register_operand" "=r"))]
7659 "!SIBLING_CALL_P (insn)
7661 && GET_MODE (operands[3]) == Pmode"
7663 [(set_attr "op_type" "RIL")
7664 (set_attr "type" "jsr")])
7666 (define_insn "*basr_r"
7667 [(set (match_operand 0 "" "")
7668 (call (mem:QI (match_operand 1 "address_operand" "U"))
7669 (match_operand 2 "const_int_operand" "n")))
7670 (clobber (match_operand 3 "register_operand" "=r"))]
7671 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7673 if (get_attr_op_type (insn) == OP_TYPE_RR)
7674 return "basr\t%3,%1";
7676 return "bas\t%3,%a1";
7678 [(set (attr "op_type")
7679 (if_then_else (match_operand 1 "register_operand" "")
7680 (const_string "RR") (const_string "RX")))
7681 (set_attr "type" "jsr")
7682 (set_attr "atype" "agen")])
7685 ;;- Thread-local storage support.
7688 (define_expand "get_tp_64"
7689 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI 36))]
7693 (define_expand "get_tp_31"
7694 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI 36))]
7698 (define_expand "set_tp_64"
7699 [(set (reg:DI 36) (match_operand:DI 0 "nonimmediate_operand" ""))
7700 (set (reg:DI 36) (unspec_volatile:DI [(reg:DI 36)] UNSPECV_SET_TP))]
7704 (define_expand "set_tp_31"
7705 [(set (reg:SI 36) (match_operand:SI 0 "nonimmediate_operand" ""))
7706 (set (reg:SI 36) (unspec_volatile:SI [(reg:SI 36)] UNSPECV_SET_TP))]
7710 (define_insn "*set_tp"
7711 [(set (reg 36) (unspec_volatile [(reg 36)] UNSPECV_SET_TP))]
7714 [(set_attr "type" "none")
7715 (set_attr "length" "0")])
7717 (define_insn "*tls_load_64"
7718 [(set (match_operand:DI 0 "register_operand" "=d")
7719 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
7720 (match_operand:DI 2 "" "")]
7724 [(set_attr "op_type" "RXE")])
7726 (define_insn "*tls_load_31"
7727 [(set (match_operand:SI 0 "register_operand" "=d,d")
7728 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
7729 (match_operand:SI 2 "" "")]
7735 [(set_attr "op_type" "RX,RXY")])
7737 (define_insn "*bras_tls"
7738 [(set (match_operand 0 "" "")
7739 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7740 (match_operand 2 "const_int_operand" "n")))
7741 (clobber (match_operand 3 "register_operand" "=r"))
7742 (use (match_operand 4 "" ""))]
7743 "!SIBLING_CALL_P (insn)
7744 && TARGET_SMALL_EXEC
7745 && GET_MODE (operands[3]) == Pmode"
7747 [(set_attr "op_type" "RI")
7748 (set_attr "type" "jsr")])
7750 (define_insn "*brasl_tls"
7751 [(set (match_operand 0 "" "")
7752 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7753 (match_operand 2 "const_int_operand" "n")))
7754 (clobber (match_operand 3 "register_operand" "=r"))
7755 (use (match_operand 4 "" ""))]
7756 "!SIBLING_CALL_P (insn)
7758 && GET_MODE (operands[3]) == Pmode"
7760 [(set_attr "op_type" "RIL")
7761 (set_attr "type" "jsr")])
7763 (define_insn "*basr_tls"
7764 [(set (match_operand 0 "" "")
7765 (call (mem:QI (match_operand 1 "address_operand" "U"))
7766 (match_operand 2 "const_int_operand" "n")))
7767 (clobber (match_operand 3 "register_operand" "=r"))
7768 (use (match_operand 4 "" ""))]
7769 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7771 if (get_attr_op_type (insn) == OP_TYPE_RR)
7772 return "basr\t%3,%1%J4";
7774 return "bas\t%3,%a1%J4";
7776 [(set (attr "op_type")
7777 (if_then_else (match_operand 1 "register_operand" "")
7778 (const_string "RR") (const_string "RX")))
7779 (set_attr "type" "jsr")
7780 (set_attr "atype" "agen")])
7783 ;;- Miscellaneous instructions.
7787 ; allocate stack instruction pattern(s).
7790 (define_expand "allocate_stack"
7791 [(match_operand 0 "general_operand" "")
7792 (match_operand 1 "general_operand" "")]
7795 rtx temp = gen_reg_rtx (Pmode);
7797 emit_move_insn (temp, s390_back_chain_rtx ());
7798 anti_adjust_stack (operands[1]);
7799 emit_move_insn (s390_back_chain_rtx (), temp);
7801 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7807 ; setjmp instruction pattern.
7810 (define_expand "builtin_setjmp_receiver"
7811 [(match_operand 0 "" "")]
7814 emit_insn (s390_load_got ());
7815 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
7819 ;; These patterns say how to save and restore the stack pointer. We need not
7820 ;; save the stack pointer at function level since we are careful to
7821 ;; preserve the backchain. At block level, we have to restore the backchain
7822 ;; when we restore the stack pointer.
7824 ;; For nonlocal gotos, we must save both the stack pointer and its
7825 ;; backchain and restore both. Note that in the nonlocal case, the
7826 ;; save area is a memory location.
7828 (define_expand "save_stack_function"
7829 [(match_operand 0 "general_operand" "")
7830 (match_operand 1 "general_operand" "")]
7834 (define_expand "restore_stack_function"
7835 [(match_operand 0 "general_operand" "")
7836 (match_operand 1 "general_operand" "")]
7840 (define_expand "restore_stack_block"
7841 [(match_operand 0 "register_operand" "")
7842 (match_operand 1 "register_operand" "")]
7845 rtx temp = gen_reg_rtx (Pmode);
7847 emit_move_insn (temp, s390_back_chain_rtx ());
7848 emit_move_insn (operands[0], operands[1]);
7849 emit_move_insn (s390_back_chain_rtx (), temp);
7854 (define_expand "save_stack_nonlocal"
7855 [(match_operand 0 "memory_operand" "")
7856 (match_operand 1 "register_operand" "")]
7859 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7860 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7862 /* Copy the backchain to the first word, sp to the second and the
7863 literal pool base to the third. */
7865 if (TARGET_BACKCHAIN)
7867 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
7868 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
7871 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
7872 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
7877 (define_expand "restore_stack_nonlocal"
7878 [(match_operand 0 "register_operand" "")
7879 (match_operand 1 "memory_operand" "")]
7882 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7883 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7884 rtx temp = NULL_RTX;
7886 /* Restore the backchain from the first word, sp from the second and the
7887 literal pool base from the third. */
7889 if (TARGET_BACKCHAIN)
7890 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7892 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7893 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7896 emit_move_insn (s390_back_chain_rtx (), temp);
7898 emit_insn (gen_rtx_USE (VOIDmode, base));
7904 ; nop instruction pattern(s).
7911 [(set_attr "op_type" "RR")])
7915 ; Special literal pool access instruction pattern(s).
7918 (define_insn "*pool_entry"
7919 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7920 UNSPECV_POOL_ENTRY)]
7923 enum machine_mode mode = GET_MODE (PATTERN (insn));
7924 unsigned int align = GET_MODE_BITSIZE (mode);
7925 s390_output_pool_entry (operands[0], mode, align);
7928 [(set (attr "length")
7929 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7931 (define_insn "pool_align"
7932 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7933 UNSPECV_POOL_ALIGN)]
7936 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7938 (define_insn "pool_section_start"
7939 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7942 [(set_attr "length" "0")])
7944 (define_insn "pool_section_end"
7945 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
7948 [(set_attr "length" "0")])
7950 (define_insn "main_base_31_small"
7951 [(set (match_operand 0 "register_operand" "=a")
7952 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7953 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7955 [(set_attr "op_type" "RR")
7956 (set_attr "type" "la")])
7958 (define_insn "main_base_31_large"
7959 [(set (match_operand 0 "register_operand" "=a")
7960 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
7961 (set (pc) (label_ref (match_operand 2 "" "")))]
7962 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7964 [(set_attr "op_type" "RI")])
7966 (define_insn "main_base_64"
7967 [(set (match_operand 0 "register_operand" "=a")
7968 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7969 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7971 [(set_attr "op_type" "RIL")
7972 (set_attr "type" "larl")])
7974 (define_insn "main_pool"
7975 [(set (match_operand 0 "register_operand" "=a")
7976 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
7977 "GET_MODE (operands[0]) == Pmode"
7980 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
7981 (const_string "larl") (const_string "la")))])
7983 (define_insn "reload_base_31"
7984 [(set (match_operand 0 "register_operand" "=a")
7985 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7986 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7987 "basr\t%0,0\;la\t%0,%1-.(%0)"
7988 [(set_attr "length" "6")
7989 (set_attr "type" "la")])
7991 (define_insn "reload_base_64"
7992 [(set (match_operand 0 "register_operand" "=a")
7993 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7994 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7996 [(set_attr "op_type" "RIL")
7997 (set_attr "type" "larl")])
8000 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
8003 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8006 ;; Insns related to generating the function prologue and epilogue.
8010 (define_expand "prologue"
8011 [(use (const_int 0))]
8013 "s390_emit_prologue (); DONE;")
8015 (define_insn "prologue_tpf"
8016 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE)
8017 (clobber (reg:DI 1))]
8018 "TARGET_TPF_PROFILING"
8019 "larl\t%%r1,.+14\;tm\t4065,255\;bnz\t4064"
8020 [(set_attr "length" "14")])
8022 (define_expand "epilogue"
8023 [(use (const_int 1))]
8025 "s390_emit_epilogue (false); DONE;")
8027 (define_insn "epilogue_tpf"
8028 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE)
8029 (clobber (reg:DI 1))]
8030 "TARGET_TPF_PROFILING"
8031 "larl\t%%r1,.+14\;tm\t4071,255\;bnz\t4070"
8032 [(set_attr "length" "14")])
8034 (define_expand "sibcall_epilogue"
8035 [(use (const_int 0))]
8037 "s390_emit_epilogue (true); DONE;")
8039 (define_insn "*return"
8041 (use (match_operand 0 "register_operand" "a"))]
8042 "GET_MODE (operands[0]) == Pmode"
8044 [(set_attr "op_type" "RR")
8045 (set_attr "type" "jsr")
8046 (set_attr "atype" "agen")])
8049 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
8050 ;; pointer. This is used for compatibility.
8052 (define_expand "ptr_extend"
8053 [(set (match_operand:DI 0 "register_operand" "=r")
8054 (match_operand:SI 1 "register_operand" "r"))]
8057 emit_insn (gen_anddi3 (operands[0],
8058 gen_lowpart (DImode, operands[1]),
8059 GEN_INT (0x7fffffff)));
8063 ;; Instruction definition to expand eh_return macro to support
8064 ;; swapping in special linkage return addresses.
8066 (define_expand "eh_return"
8067 [(use (match_operand 0 "register_operand" ""))]
8070 s390_emit_tpf_eh_return (operands[0]);