1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
23 ;; Special constraints for s/390 machine description:
25 ;; a -- Any address register from 1 to 15.
26 ;; d -- Any register from 0 to 15.
27 ;; I -- An 8-bit constant (0..255).
28 ;; J -- A 12-bit constant (0..4095).
29 ;; K -- A 16-bit constant (-32768..32767).
30 ;; Q -- A memory reference without index-register.
31 ;; S -- Valid operand for the LARL instruction.
33 ;; Special formats used for outputting 390 instructions.
35 ;; %b -- Print a constant byte integer. xy
36 ;; %h -- Print a signed 16-bit. wxyz
37 ;; %N -- Print next register (second word of a DImode reg) or next word.
38 ;; %M -- Print next register (second word of a TImode reg) or next word.
39 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
40 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
42 ;; We have a special constraint for pattern matching.
44 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
48 ;; Define an insn type attribute. This is used in function unit delay
51 (define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
52 (const_string "integer"))
54 ;; Insn are devide in two classes:
55 ;; mem: Insn accessing memory
56 ;; reg: Insn operands all in registers
58 (define_attr "atype" "reg,mem"
61 ;; Generic pipeline function unit.
63 (define_function_unit "integer" 1 0
64 (eq_attr "type" "none") 0 0)
66 (define_function_unit "integer" 1 0
67 (eq_attr "type" "integer") 1 1)
69 (define_function_unit "integer" 1 0
70 (eq_attr "type" "load") 1 1)
72 (define_function_unit "integer" 1 0
73 (eq_attr "type" "la") 1 1)
75 (define_function_unit "integer" 1 0
76 (eq_attr "type" "lr") 1 1)
78 (define_function_unit "integer" 1 0
79 (eq_attr "type" "store") 1 1)
81 (define_function_unit "integer" 1 0
82 (eq_attr "type" "lm") 2 2)
84 (define_function_unit "integer" 1 0
85 (eq_attr "type" "stm") 2 2)
87 (define_function_unit "integer" 1 0
88 (eq_attr "type" "cs") 5 5)
90 (define_function_unit "integer" 1 0
91 (eq_attr "type" "vs") 30 30)
93 (define_function_unit "integer" 1 0
94 (eq_attr "type" "jsr") 5 5)
96 (define_function_unit "integer" 1 0
97 (eq_attr "type" "imul") 7 7)
99 (define_function_unit "integer" 1 0
100 (eq_attr "type" "fmul") 6 6)
102 (define_function_unit "integer" 1 0
103 (eq_attr "type" "idiv") 33 33)
105 (define_function_unit "integer" 1 0
106 (eq_attr "type" "fdiv") 33 33)
108 (define_function_unit "integer" 1 0
109 (eq_attr "type" "o2") 2 2)
111 (define_function_unit "integer" 1 0
112 (eq_attr "type" "o3") 3 3)
114 (define_function_unit "integer" 1 0
115 (eq_attr "type" "other") 5 5)
117 ;; Operand type. Used to default length attribute values
119 (define_attr "op_type"
120 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
125 (define_attr "length" ""
126 (cond [ (eq_attr "op_type" "E") (const_int 2)
127 (eq_attr "op_type" "RR") (const_int 2)
128 (eq_attr "op_type" "RX") (const_int 4)
129 (eq_attr "op_type" "RI") (const_int 4)
130 (eq_attr "op_type" "RRE") (const_int 4)
131 (eq_attr "op_type" "RS") (const_int 4)
132 (eq_attr "op_type" "RSI") (const_int 4)
133 (eq_attr "op_type" "RX") (const_int 4)
134 (eq_attr "op_type" "S") (const_int 4)
135 (eq_attr "op_type" "SI") (const_int 4)
136 (eq_attr "op_type" "SS") (const_int 6)
137 (eq_attr "op_type" "SSE") (const_int 6)
138 (eq_attr "op_type" "RXE") (const_int 6)
139 (eq_attr "op_type" "RSE") (const_int 6)
140 (eq_attr "op_type" "RIL") (const_int 6)]
143 ;; Define attributes for `asm' insns.
145 (define_asm_attributes [(set_attr "type" "other")
146 (set_attr "op_type" "NN")])
152 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
153 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
154 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
155 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
156 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
159 ; CCZ1 -> CCA/CCU/CCS/CCT
162 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
163 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
167 ;;- Compare instructions.
170 (define_expand "cmpdi"
172 (compare:CC (match_operand:DI 0 "register_operand" "")
173 (match_operand:DI 1 "general_operand" "")))]
177 s390_compare_op0 = operands[0];
178 s390_compare_op1 = operands[1];
182 (define_expand "cmpsi"
184 (compare:CC (match_operand:SI 0 "register_operand" "")
185 (match_operand:SI 1 "general_operand" "")))]
189 s390_compare_op0 = operands[0];
190 s390_compare_op1 = operands[1];
194 (define_expand "cmpdf"
196 (compare:CC (match_operand:DF 0 "register_operand" "")
197 (match_operand:DF 1 "general_operand" "")))]
201 s390_compare_op0 = operands[0];
202 s390_compare_op1 = operands[1];
206 (define_expand "cmpsf"
208 (compare:CC (match_operand:SF 0 "register_operand" "")
209 (match_operand:SF 1 "general_operand" "")))]
213 s390_compare_op0 = operands[0];
214 s390_compare_op1 = operands[1];
219 ; Test-under-Mask (zero_extract) instructions
221 (define_insn "*tmdi_ext"
223 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
224 (match_operand:DI 1 "const_int_operand" "n")
225 (match_operand:DI 2 "const_int_operand" "n"))
227 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
228 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
229 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
230 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
231 == INTVAL (operands[2]) >> 4"
234 int part = INTVAL (operands[2]) >> 4;
235 int block = (1 << INTVAL (operands[1])) - 1;
236 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
238 operands[2] = GEN_INT (block << shift);
242 case 0: return \"tmhh\\t%0,%x2\";
243 case 1: return \"tmhl\\t%0,%x2\";
244 case 2: return \"tmlh\\t%0,%x2\";
245 case 3: return \"tmll\\t%0,%x2\";
249 [(set_attr "op_type" "RI")])
251 (define_insn "*tmsi_ext"
253 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
254 (match_operand:SI 1 "const_int_operand" "n")
255 (match_operand:SI 2 "const_int_operand" "n"))
257 "s390_match_ccmode(insn, CCTmode)
258 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
259 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
260 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
261 == INTVAL (operands[2]) >> 4"
264 int part = INTVAL (operands[2]) >> 4;
265 int block = (1 << INTVAL (operands[1])) - 1;
266 int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15);
268 operands[2] = GEN_INT (block << shift);
272 case 0: return \"tmh\\t%0,%x2\";
273 case 1: return \"tml\\t%0,%x2\";
277 [(set_attr "op_type" "RI")])
279 (define_insn "*tmqi_ext"
281 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q")
282 (match_operand:SI 1 "const_int_operand" "n")
283 (match_operand:SI 2 "const_int_operand" "n"))
285 "s390_match_ccmode(insn, CCTmode)
286 && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
287 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
290 int block = (1 << INTVAL (operands[1])) - 1;
291 int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
293 operands[2] = GEN_INT (block << shift);
294 return \"tm\\t%0,%b2\";
296 [(set_attr "op_type" "SI")
297 (set_attr "atype" "mem")])
299 ; Test-under-Mask instructions
301 (define_insn "*tmdi_mem"
303 (compare (and:DI (match_operand:DI 0 "memory_operand" "Q")
304 (match_operand:DI 1 "immediate_operand" "n"))
305 (match_operand:DI 2 "immediate_operand" "n")))]
307 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
308 && s390_single_qi (operands[1], DImode, 0) >= 0"
311 int part = s390_single_qi (operands[1], DImode, 0);
312 operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
314 operands[0] = gen_rtx_MEM (QImode,
315 plus_constant (XEXP (operands[0], 0), part));
316 return \"tm\\t%0,%b1\";
318 [(set_attr "op_type" "SI")
319 (set_attr "atype" "mem")])
321 (define_insn "*tmsi_mem"
323 (compare (and:SI (match_operand:SI 0 "memory_operand" "Q")
324 (match_operand:SI 1 "immediate_operand" "n"))
325 (match_operand:SI 2 "immediate_operand" "n")))]
326 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
327 && s390_single_qi (operands[1], SImode, 0) >= 0"
330 int part = s390_single_qi (operands[1], SImode, 0);
331 operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
333 operands[0] = gen_rtx_MEM (QImode,
334 plus_constant (XEXP (operands[0], 0), part));
335 return \"tm\\t%0,%b1\";
337 [(set_attr "op_type" "SI")
338 (set_attr "atype" "mem")])
340 (define_insn "*tmhi_mem"
342 (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0)
343 (match_operand:SI 1 "immediate_operand" "n"))
344 (match_operand:SI 2 "immediate_operand" "n")))]
345 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
346 && s390_single_qi (operands[1], HImode, 0) >= 0"
349 int part = s390_single_qi (operands[1], HImode, 0);
350 operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
352 operands[0] = gen_rtx_MEM (QImode,
353 plus_constant (XEXP (operands[0], 0), part));
354 return \"tm\\t%0,%b1\";
356 [(set_attr "op_type" "SI")
357 (set_attr "atype" "mem")])
359 (define_insn "*tmqi_mem"
361 (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0)
362 (match_operand:SI 1 "immediate_operand" "n"))
363 (match_operand:SI 2 "immediate_operand" "n")))]
364 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
366 [(set_attr "op_type" "SI")
367 (set_attr "atype" "mem")])
369 (define_insn "*tmdi_reg"
371 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d")
372 (match_operand:DI 1 "immediate_operand" "n"))
373 (match_operand:DI 2 "immediate_operand" "n")))]
375 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
376 && s390_single_hi (operands[1], DImode, 0) >= 0"
379 int part = s390_single_hi (operands[1], DImode, 0);
380 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
384 case 0: return \"tmhh\\t%0,%x1\";
385 case 1: return \"tmhl\\t%0,%x1\";
386 case 2: return \"tmlh\\t%0,%x1\";
387 case 3: return \"tmll\\t%0,%x1\";
391 [(set_attr "op_type" "RI")])
393 (define_insn "*tmsi_reg"
395 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d")
396 (match_operand:SI 1 "immediate_operand" "n"))
397 (match_operand:SI 2 "immediate_operand" "n")))]
398 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
399 && s390_single_hi (operands[1], SImode, 0) >= 0"
402 int part = s390_single_hi (operands[1], SImode, 0);
403 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
407 case 0: return \"tmh\\t%0,%x1\";
408 case 1: return \"tml\\t%0,%x1\";
412 [(set_attr "op_type" "RI")])
414 (define_insn "*tmhi_full"
416 (compare (match_operand:HI 0 "register_operand" "d")
417 (match_operand:HI 1 "immediate_operand" "n")))]
418 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
420 [(set_attr "op_type" "RX")])
422 (define_insn "*tmqi_full"
424 (compare (match_operand:QI 0 "register_operand" "d")
425 (match_operand:QI 1 "immediate_operand" "n")))]
426 "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
428 [(set_attr "op_type" "RI")])
431 ; Load-and-Test instructions
433 (define_insn "*tstdi_sign"
435 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
436 (const_int 32)) (const_int 32))
437 (match_operand:DI 1 "const0_operand" "")))
438 (set (match_operand:DI 2 "register_operand" "=d")
439 (sign_extend:DI (match_dup 0)))]
440 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
442 [(set_attr "op_type" "RRE")])
444 (define_insn "*tstdi"
446 (compare (match_operand:DI 0 "register_operand" "d")
447 (match_operand:DI 1 "const0_operand" "")))
448 (set (match_operand:DI 2 "register_operand" "=d")
450 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
452 [(set_attr "op_type" "RRE")])
454 (define_insn "*tstdi_cconly"
456 (compare (match_operand:DI 0 "register_operand" "d")
457 (match_operand:DI 1 "const0_operand" "")))]
458 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
460 [(set_attr "op_type" "RRE")])
462 (define_insn "*tstdi_cconly_31"
464 (compare (match_operand:DI 0 "register_operand" "d")
465 (match_operand:DI 1 "const0_operand" "")))]
466 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
468 [(set_attr "op_type" "RS")])
470 (define_insn "*tstsi"
472 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
473 (match_operand:SI 1 "const0_operand" "")))
474 (set (match_operand:SI 2 "register_operand" "=d,d")
476 "s390_match_ccmode(insn, CCSmode)"
480 [(set_attr "op_type" "RR,RS")
481 (set_attr "atype" "reg,mem")])
483 (define_insn "*tstsi_cconly"
485 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q")
486 (match_operand:SI 1 "const0_operand" "")))
487 (clobber (match_scratch:SI 2 "=X,d"))]
488 "s390_match_ccmode(insn, CCSmode)"
492 [(set_attr "op_type" "RR,RS")
493 (set_attr "atype" "reg,mem")])
495 (define_insn "*tstsi_cconly2"
497 (compare (match_operand:SI 0 "register_operand" "d")
498 (match_operand:SI 1 "const0_operand" "")))]
499 "s390_match_ccmode(insn, CCSmode)"
501 [(set_attr "op_type" "RR")])
503 (define_insn "*tsthi"
505 (compare (match_operand:HI 0 "s_operand" "Q")
506 (match_operand:HI 1 "const0_operand" "")))
507 (set (match_operand:HI 2 "register_operand" "=d")
509 "s390_match_ccmode(insn, CCSmode)"
511 [(set_attr "op_type" "RS")
512 (set_attr "atype" "mem")])
514 (define_insn "*tsthi_cconly"
516 (compare (match_operand:HI 0 "s_operand" "Q")
517 (match_operand:HI 1 "const0_operand" "")))
518 (clobber (match_scratch:HI 2 "=d"))]
519 "s390_match_ccmode(insn, CCSmode)"
521 [(set_attr "op_type" "RS")
522 (set_attr "atype" "mem")])
524 (define_insn "*tstqi"
526 (compare (match_operand:QI 0 "s_operand" "Q")
527 (match_operand:QI 1 "const0_operand" "")))
528 (set (match_operand:QI 2 "register_operand" "=d")
530 "s390_match_ccmode(insn, CCSmode)"
532 [(set_attr "op_type" "RS")
533 (set_attr "atype" "mem")])
535 (define_insn "*tstqi_cconly"
537 (compare (match_operand:QI 0 "s_operand" "Q")
538 (match_operand:QI 1 "const0_operand" "")))
539 (clobber (match_scratch:QI 2 "=d"))]
540 "s390_match_ccmode(insn, CCSmode)"
542 [(set_attr "op_type" "RS")
543 (set_attr "atype" "mem")])
546 ; Compare (signed) instructions
548 (define_insn "*cmpdi_ccs_sign"
550 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
551 (match_operand:DI 0 "register_operand" "d,d")))]
552 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
556 [(set_attr "op_type" "RRE,RXE")
557 (set_attr "atype" "reg,mem")])
559 (define_insn "*cmpdi_ccs"
561 (compare (match_operand:DI 0 "register_operand" "d,d,d")
562 (match_operand:DI 1 "general_operand" "d,K,m")))]
563 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
568 [(set_attr "op_type" "RRE,RI,RXE")
569 (set_attr "atype" "reg,reg,mem")])
571 (define_insn "*cmpsi_ccs_sign"
573 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))
574 (match_operand:SI 0 "register_operand" "d")))]
575 "s390_match_ccmode(insn, CCSRmode)"
577 [(set_attr "op_type" "RX")
578 (set_attr "atype" "mem")])
580 (define_insn "*cmpsi_ccs"
582 (compare (match_operand:SI 0 "register_operand" "d,d,d")
583 (match_operand:SI 1 "general_operand" "d,K,m")))]
584 "s390_match_ccmode(insn, CCSmode)"
589 [(set_attr "op_type" "RR,RI,RX")
590 (set_attr "atype" "reg,reg,mem")])
593 ; Compare (unsigned) instructions
595 (define_insn "*cmpdi_ccu_zero"
597 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
598 (match_operand:DI 0 "register_operand" "d,d")))]
599 "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT"
603 [(set_attr "op_type" "RRE,RXE")
604 (set_attr "atype" "reg,mem")])
606 (define_insn "*cmpdi_ccu"
608 (compare (match_operand:DI 0 "register_operand" "d,d")
609 (match_operand:DI 1 "general_operand" "d,m")))]
610 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
614 [(set_attr "op_type" "RRE,RXE")
615 (set_attr "atype" "reg,mem")])
617 (define_insn "*cmpsi_ccu"
619 (compare (match_operand:SI 0 "register_operand" "d,d")
620 (match_operand:SI 1 "general_operand" "d,m")))]
621 "s390_match_ccmode(insn, CCUmode)"
625 [(set_attr "op_type" "RR,RX")
626 (set_attr "atype" "reg,mem")])
628 (define_insn "*cmphi_ccu"
630 (compare (match_operand:HI 0 "register_operand" "d")
631 (match_operand:HI 1 "s_imm_operand" "Q")))]
632 "s390_match_ccmode(insn, CCUmode)"
634 [(set_attr "op_type" "RS")
635 (set_attr "atype" "mem")])
637 (define_insn "*cmpqi_ccu"
639 (compare (match_operand:QI 0 "register_operand" "d")
640 (match_operand:QI 1 "s_imm_operand" "Q")))]
641 "s390_match_ccmode(insn, CCUmode)"
643 [(set_attr "op_type" "RS")
644 (set_attr "atype" "mem")])
648 (compare (match_operand:QI 0 "memory_operand" "Q")
649 (match_operand:QI 1 "immediate_operand" "n")))]
650 "s390_match_ccmode (insn, CCUmode)"
652 [(set_attr "op_type" "SI")
653 (set_attr "atype" "mem")])
655 (define_insn "*cmpdi_ccu_mem"
657 (compare (match_operand:DI 0 "s_operand" "Q")
658 (match_operand:DI 1 "s_imm_operand" "Q")))]
659 "s390_match_ccmode(insn, CCUmode)"
660 "clc\\t%O0(8,%R0),%1"
661 [(set_attr "op_type" "SS")
662 (set_attr "atype" "mem")])
664 (define_insn "*cmpsi_ccu_mem"
666 (compare (match_operand:SI 0 "s_operand" "Q")
667 (match_operand:SI 1 "s_imm_operand" "Q")))]
668 "s390_match_ccmode(insn, CCUmode)"
669 "clc\\t%O0(4,%R0),%1"
670 [(set_attr "op_type" "SS")
671 (set_attr "atype" "mem")])
673 (define_insn "*cmphi_ccu_mem"
675 (compare (match_operand:HI 0 "s_operand" "Q")
676 (match_operand:HI 1 "s_imm_operand" "Q")))]
677 "s390_match_ccmode(insn, CCUmode)"
678 "clc\\t%O0(2,%R0),%1"
679 [(set_attr "op_type" "SS")
680 (set_attr "atype" "mem")])
682 (define_insn "*cmpqi_ccu_mem"
684 (compare (match_operand:QI 0 "s_operand" "Q")
685 (match_operand:QI 1 "s_imm_operand" "Q")))]
686 "s390_match_ccmode(insn, CCUmode)"
687 "clc\\t%O0(1,%R0),%1"
688 [(set_attr "op_type" "SS")
689 (set_attr "atype" "mem")])
694 (define_insn "*cmpdf_ccs_0"
696 (compare (match_operand:DF 0 "register_operand" "f")
697 (match_operand:DF 1 "const0_operand" "")))]
698 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
700 [(set_attr "op_type" "RRE")])
702 (define_insn "*cmpdf_ccs_0_ibm"
704 (compare (match_operand:DF 0 "register_operand" "f")
705 (match_operand:DF 1 "const0_operand" "")))]
706 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
708 [(set_attr "op_type" "RR")])
710 (define_insn "*cmpdf_ccs"
712 (compare (match_operand:DF 0 "register_operand" "f,f")
713 (match_operand:DF 1 "general_operand" "f,m")))]
714 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
718 [(set_attr "op_type" "RRE,RXE")
719 (set_attr "atype" "reg,mem")])
721 (define_insn "*cmpdf_ccs_ibm"
723 (compare (match_operand:DF 0 "register_operand" "f,f")
724 (match_operand:DF 1 "general_operand" "f,m")))]
725 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
729 [(set_attr "op_type" "RR,RX")
730 (set_attr "atype" "reg,mem")])
735 (define_insn "*cmpsf_ccs_0"
737 (compare (match_operand:SF 0 "register_operand" "f")
738 (match_operand:SF 1 "const0_operand" "")))]
739 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
741 [(set_attr "op_type" "RRE")])
743 (define_insn "*cmpsf_ccs_0_ibm"
745 (compare (match_operand:SF 0 "register_operand" "f")
746 (match_operand:SF 1 "const0_operand" "")))]
747 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
749 [(set_attr "op_type" "RR")])
751 (define_insn "*cmpsf_ccs"
753 (compare (match_operand:SF 0 "register_operand" "f,f")
754 (match_operand:SF 1 "general_operand" "f,m")))]
755 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
759 [(set_attr "op_type" "RRE,RXE")
760 (set_attr "atype" "reg,mem")])
762 (define_insn "*cmpsf_ccs"
764 (compare (match_operand:SF 0 "register_operand" "f,f")
765 (match_operand:SF 1 "general_operand" "f,m")))]
766 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
770 [(set_attr "op_type" "RR,RX")
771 (set_attr "atype" "reg,mem")])
775 ;;- Move instructions.
779 ; movti instruction pattern(s).
783 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m,Q")
784 (match_operand:TI 1 "general_operand" "Q,d,dKm,d,Q"))]
791 mvc\\t%O0(16,%R0),%1"
792 [(set_attr "op_type" "RSE,RSE,NN,NN,SS")
793 (set_attr "atype" "mem")])
796 [(set (match_operand:TI 0 "nonimmediate_operand" "")
797 (match_operand:TI 1 "general_operand" ""))]
798 "TARGET_64BIT && reload_completed
799 && !s_operand (operands[0], VOIDmode)
800 && !s_operand (operands[1], VOIDmode)
801 && (register_operand (operands[0], VOIDmode)
802 || register_operand (operands[1], VOIDmode))
803 && (!register_operand (operands[0], VOIDmode)
804 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
806 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
808 [(set (match_dup 2) (match_dup 4))
809 (set (match_dup 3) (match_dup 5))]
812 if (!register_operand (operands[0], VOIDmode)
813 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
816 operands[2] = operand_subword (operands[0], 0, 0, TImode);
817 operands[3] = operand_subword (operands[0], 1, 0, TImode);
818 operands[4] = operand_subword (operands[1], 0, 0, TImode);
819 operands[5] = operand_subword (operands[1], 1, 0, TImode);
823 operands[2] = operand_subword (operands[0], 1, 0, TImode);
824 operands[3] = operand_subword (operands[0], 0, 0, TImode);
825 operands[4] = operand_subword (operands[1], 1, 0, TImode);
826 operands[5] = operand_subword (operands[1], 0, 0, TImode);
831 [(set (match_operand:TI 0 "register_operand" "")
832 (match_operand:TI 1 "memory_operand" ""))]
833 "TARGET_64BIT && reload_completed
834 && !s_operand (operands[1], VOIDmode)"
835 [(set (match_dup 0) (match_dup 1))]
838 rtx addr = operand_subword (operands[0], 1, 0, TImode);
839 s390_load_address (addr, XEXP (operands[1], 0));
840 operands[1] = replace_equiv_address (operands[1], addr);
844 ; movdi instruction pattern(s).
847 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
848 ;; move to get the address of the symbolic object from the GOT.
850 (define_expand "movdi"
851 [(set (match_operand:DI 0 "general_operand" "")
852 (match_operand:DI 1 "general_operand" ""))]
856 /* Handle PIC symbolic constants. */
857 if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
858 emit_pic_move (operands, DImode);
860 /* During and after reload, we need to force constants
861 to the literal pool ourselves, if necessary. */
862 if ((reload_in_progress || reload_completed)
863 && CONSTANT_P (operands[1])
864 && (!legitimate_reload_constant_p (operands[1])
865 || FP_REG_P (operands[0])))
866 operands[1] = force_const_mem (DImode, operands[1]);
869 (define_insn "*movdi_lhi"
870 [(set (match_operand:DI 0 "register_operand" "=d")
871 (match_operand:DI 1 "immediate_operand" "K"))]
873 && GET_CODE (operands[1]) == CONST_INT
874 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
875 && !FP_REG_P (operands[0])"
877 [(set_attr "op_type" "RI")
878 (set_attr "atype" "reg")])
880 (define_insn "*movdi_lli"
881 [(set (match_operand:DI 0 "register_operand" "=d")
882 (match_operand:DI 1 "immediate_operand" "n"))]
883 "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
884 && !FP_REG_P (operands[0])"
887 int part = s390_single_hi (operands[1], DImode, 0);
888 operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
892 case 0: return \"llihh\\t%0,%x1\";
893 case 1: return \"llihl\\t%0,%x1\";
894 case 2: return \"llilh\\t%0,%x1\";
895 case 3: return \"llill\\t%0,%x1\";
899 [(set_attr "op_type" "RI")
900 (set_attr "atype" "reg")])
902 (define_insn "*movdi_larl"
903 [(set (match_operand:DI 0 "register_operand" "=d")
904 (match_operand:DI 1 "larl_operand" "X"))]
906 && !FP_REG_P (operands[0])"
908 [(set_attr "op_type" "RIL")
909 (set_attr "atype" "reg")
910 (set_attr "type" "la")])
912 (define_insn "*movdi_64"
913 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
914 (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
924 [(set_attr "op_type" "RRE,RXE,RXE,RR,RX,RX,SS")
925 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
927 (define_insn "*movdi_31"
928 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,!*f,!*f,!m,Q")
929 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f,Q"))]
940 [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
941 (set_attr "atype" "mem,mem,*,*,reg,mem,mem,mem")])
944 [(set (match_operand:DI 0 "nonimmediate_operand" "")
945 (match_operand:DI 1 "general_operand" ""))]
946 "!TARGET_64BIT && reload_completed
947 && !FP_REG_P (operands[0])
948 && !FP_REG_P (operands[1])
949 && !s_operand (operands[0], VOIDmode)
950 && !s_operand (operands[1], VOIDmode)
951 && (register_operand (operands[0], VOIDmode)
952 || register_operand (operands[1], VOIDmode))
953 && (!register_operand (operands[0], VOIDmode)
954 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
956 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode),
958 [(set (match_dup 2) (match_dup 4))
959 (set (match_dup 3) (match_dup 5))]
962 if (!register_operand (operands[0], VOIDmode)
963 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode),
966 operands[2] = operand_subword (operands[0], 0, 0, DImode);
967 operands[3] = operand_subword (operands[0], 1, 0, DImode);
968 operands[4] = operand_subword (operands[1], 0, 0, DImode);
969 operands[5] = operand_subword (operands[1], 1, 0, DImode);
973 operands[2] = operand_subword (operands[0], 1, 0, DImode);
974 operands[3] = operand_subword (operands[0], 0, 0, DImode);
975 operands[4] = operand_subword (operands[1], 1, 0, DImode);
976 operands[5] = operand_subword (operands[1], 0, 0, DImode);
981 [(set (match_operand:DI 0 "register_operand" "")
982 (match_operand:DI 1 "memory_operand" ""))]
983 "!TARGET_64BIT && reload_completed
984 && !FP_REG_P (operands[0])
985 && !FP_REG_P (operands[1])
986 && !s_operand (operands[1], VOIDmode)"
987 [(set (match_dup 0) (match_dup 1))]
990 rtx addr = operand_subword (operands[0], 1, 0, DImode);
991 s390_load_address (addr, XEXP (operands[1], 0));
992 operands[1] = replace_equiv_address (operands[1], addr);
996 [(set (match_operand:DI 0 "register_operand" "")
997 (mem:DI (match_operand 1 "address_operand" "")))]
999 && !FP_REG_P (operands[0])
1000 && GET_CODE (operands[1]) == SYMBOL_REF
1001 && CONSTANT_POOL_ADDRESS_P (operands[1])
1002 && get_pool_mode (operands[1]) == DImode
1003 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1004 [(set (match_dup 0) (match_dup 2))]
1005 "operands[2] = get_pool_constant (operands[1]);")
1008 ; movsi instruction pattern(s).
1011 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
1012 ;; move to get the address of the symbolic object from the GOT.
1014 (define_expand "movsi"
1015 [(set (match_operand:SI 0 "general_operand" "")
1016 (match_operand:SI 1 "general_operand" ""))]
1020 /* Handle PIC symbolic constants. */
1021 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
1022 emit_pic_move (operands, SImode);
1024 /* expr.c tries to load an effective address using
1025 force_reg. This fails because we don't have a
1026 generic load_address pattern. Convert the move
1027 to a proper arithmetic operation instead, unless
1028 it is guaranteed to be OK. */
1029 if (GET_CODE (operands[1]) == PLUS
1030 && !legitimate_la_operand_p (operands[1]))
1032 operands[1] = force_operand (operands[1], operands[0]);
1033 if (operands[1] == operands[0])
1037 /* During and after reload, we need to force constants
1038 to the literal pool ourselves, if necessary. */
1039 if ((reload_in_progress || reload_completed)
1040 && CONSTANT_P (operands[1])
1041 && (!legitimate_reload_constant_p (operands[1])
1042 || FP_REG_P (operands[0])))
1043 operands[1] = force_const_mem (SImode, operands[1]);
1046 (define_insn "*movsi_lhi"
1047 [(set (match_operand:SI 0 "register_operand" "=d")
1048 (match_operand:SI 1 "immediate_operand" "K"))]
1049 "GET_CODE (operands[1]) == CONST_INT
1050 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
1051 && !FP_REG_P (operands[0])"
1053 [(set_attr "op_type" "RI")])
1055 (define_insn "*movsi_lli"
1056 [(set (match_operand:SI 0 "register_operand" "=d")
1057 (match_operand:SI 1 "immediate_operand" "n"))]
1058 "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
1059 && !FP_REG_P (operands[0])"
1062 int part = s390_single_hi (operands[1], SImode, 0);
1063 operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
1067 case 0: return \"llilh\\t%0,%x1\";
1068 case 1: return \"llill\\t%0,%x1\";
1072 [(set_attr "op_type" "RI")])
1074 (define_insn "*movsi"
1075 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
1076 (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,Q"))]
1085 mvc\\t%O0(4,%R0),%1"
1086 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1087 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1090 [(set (match_operand:SI 0 "register_operand" "")
1091 (mem:SI (match_operand 1 "address_operand" "")))]
1092 "!FP_REG_P (operands[0])
1093 && GET_CODE (operands[1]) == SYMBOL_REF
1094 && CONSTANT_POOL_ADDRESS_P (operands[1])
1095 && get_pool_mode (operands[1]) == SImode
1096 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1097 [(set (match_dup 0) (match_dup 2))]
1098 "operands[2] = get_pool_constant (operands[1]);")
1101 ; movhi instruction pattern(s).
1104 (define_insn "movhi"
1105 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,Q")
1106 (match_operand:HI 1 "general_operand" "d,n,m,d,Q"))]
1113 mvc\\t%O0(2,%R0),%1"
1114 [(set_attr "op_type" "RR,RI,RX,RX,SS")
1115 (set_attr "atype" "reg,reg,mem,mem,mem")])
1118 [(set (match_operand:HI 0 "register_operand" "")
1119 (mem:HI (match_operand 1 "address_operand" "")))]
1120 "GET_CODE (operands[1]) == SYMBOL_REF
1121 && CONSTANT_POOL_ADDRESS_P (operands[1])
1122 && get_pool_mode (operands[1]) == HImode
1123 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1124 [(set (match_dup 0) (match_dup 2))]
1125 "operands[2] = get_pool_constant (operands[1]);")
1128 ; movqi instruction pattern(s).
1131 (define_insn "movqi_64"
1132 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1133 (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1141 mvc\\t%O0(1,%R0),%1"
1142 [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
1143 (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
1146 (define_insn "movqi"
1147 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
1148 (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))]
1156 mvc\\t%O0(1,%R0),%1"
1157 [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")
1158 (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
1161 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1162 (mem:QI (match_operand 1 "address_operand" "")))]
1163 "GET_CODE (operands[1]) == SYMBOL_REF
1164 && CONSTANT_POOL_ADDRESS_P (operands[1])
1165 && get_pool_mode (operands[1]) == QImode
1166 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1167 [(set (match_dup 0) (match_dup 2))]
1168 "operands[2] = get_pool_constant (operands[1]);")
1171 ; movstrictqi instruction pattern(s).
1174 (define_insn "*movstrictqi"
1175 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
1176 (match_operand:QI 1 "memory_operand" "m"))]
1179 [(set_attr "op_type" "RX")
1180 (set_attr "atype" "mem")])
1183 ; movstricthi instruction pattern(s).
1186 (define_insn "*movstricthi"
1187 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
1188 (match_operand:HI 1 "s_imm_operand" "Q"))
1189 (clobber (reg:CC 33))]
1192 [(set_attr "op_type" "RS")
1193 (set_attr "atype" "mem")])
1197 ; movstrictsi instruction pattern(s).
1200 (define_insn "movstrictsi"
1201 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d"))
1202 (match_operand:SI 1 "general_operand" "d,m"))]
1207 [(set_attr "op_type" "RR,RS")
1208 (set_attr "atype" "reg,mem")])
1212 ; movdf instruction pattern(s).
1215 (define_expand "movdf"
1216 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1217 (match_operand:DF 1 "general_operand" ""))]
1221 /* During and after reload, we need to force constants
1222 to the literal pool ourselves, if necessary. */
1223 if ((reload_in_progress || reload_completed)
1224 && CONSTANT_P (operands[1]))
1225 operands[1] = force_const_mem (DFmode, operands[1]);
1228 (define_insn "*movdf_64"
1229 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1230 (match_operand:DF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1239 mvc\\t%O0(8,%R0),%1"
1240 [(set_attr "op_type" "RR,RX,RX,RRE,RXE,RXE,SS")
1241 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1243 (define_insn "*movdf_31"
1244 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m,Q")
1245 (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d,Q"))]
1255 mvc\\t%O0(8,%R0),%1"
1256 [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
1257 (set_attr "atype" "reg,mem,mem,mem,mem,*,*,mem")])
1260 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1261 (match_operand:DF 1 "general_operand" ""))]
1262 "!TARGET_64BIT && reload_completed
1263 && !FP_REG_P (operands[0])
1264 && !FP_REG_P (operands[1])
1265 && !s_operand (operands[0], VOIDmode)
1266 && !s_operand (operands[1], VOIDmode)
1267 && (register_operand (operands[0], VOIDmode)
1268 || register_operand (operands[1], VOIDmode))
1269 && (!register_operand (operands[0], VOIDmode)
1270 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1272 || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode),
1274 [(set (match_dup 2) (match_dup 4))
1275 (set (match_dup 3) (match_dup 5))]
1278 if (!register_operand (operands[0], VOIDmode)
1279 || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode),
1282 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1283 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1284 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1285 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1289 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1290 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1291 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1292 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1297 [(set (match_operand:DF 0 "register_operand" "")
1298 (match_operand:DF 1 "memory_operand" ""))]
1299 "!TARGET_64BIT && reload_completed
1300 && !FP_REG_P (operands[0])
1301 && !FP_REG_P (operands[1])
1302 && !s_operand (operands[1], VOIDmode)"
1303 [(set (match_dup 0) (match_dup 1))]
1306 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1307 s390_load_address (addr, XEXP (operands[1], 0));
1308 operands[1] = replace_equiv_address (operands[1], addr);
1312 ; movsf instruction pattern(s).
1315 (define_expand "movsf"
1316 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1317 (match_operand:SF 1 "general_operand" ""))]
1321 /* During and after reload, we need to force constants
1322 to the literal pool ourselves, if necessary. */
1323 if ((reload_in_progress || reload_completed)
1324 && CONSTANT_P (operands[1]))
1325 operands[1] = force_const_mem (SFmode, operands[1]);
1328 (define_insn "*movsf"
1329 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q")
1330 (match_operand:SF 1 "general_operand" "f,m,f,d,m,d,Q"))]
1339 mvc\\t%O0(4,%R0),%1"
1340 [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
1341 (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
1344 ; load_multiple pattern(s).
1347 (define_expand "load_multiple"
1348 [(match_par_dup 3 [(set (match_operand 0 "" "")
1349 (match_operand 1 "" ""))
1350 (use (match_operand 2 "" ""))])]
1359 /* Support only loading a constant number of fixed-point registers from
1360 memory and only bother with this if more than two */
1361 if (GET_CODE (operands[2]) != CONST_INT
1362 || INTVAL (operands[2]) < 2
1363 || INTVAL (operands[2]) > 16
1364 || GET_CODE (operands[1]) != MEM
1365 || GET_CODE (operands[0]) != REG
1366 || REGNO (operands[0]) >= 16)
1369 count = INTVAL (operands[2]);
1370 regno = REGNO (operands[0]);
1372 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1375 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1377 from = XEXP (operands[1], 0);
1380 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1381 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1382 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1384 from = XEXP (XEXP (operands[1], 0), 0);
1385 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1390 if (from == frame_pointer_rtx || from == arg_pointer_rtx)
1395 from = force_reg (Pmode, XEXP (operands[1], 0));
1399 for (i = 0; i < count; i++)
1400 XVECEXP (operands[3], 0, i)
1401 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1402 change_address (operands[1], Pmode,
1403 plus_constant (from,
1404 off + i * UNITS_PER_WORD)));
1407 (define_insn "*load_multiple_di"
1408 [(match_parallel 0 "load_multiple_operation"
1409 [(set (match_operand:DI 1 "register_operand" "=r")
1410 (match_operand:DI 2 "s_operand" "Q"))])]
1414 int words = XVECLEN (operands[0], 0);
1416 if (XVECLEN (operands[0], 0) == 1)
1417 return \"lg\\t%1,0(%2)\";
1419 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1420 return \"lmg\\t%1,%0,%2\";
1422 [(set_attr "op_type" "RXE")
1423 (set_attr "atype" "mem")
1424 (set_attr "type" "lm")])
1426 (define_insn "*load_multiple_si"
1427 [(match_parallel 0 "load_multiple_operation"
1428 [(set (match_operand:SI 1 "register_operand" "=r")
1429 (match_operand:SI 2 "s_operand" "Q"))])]
1433 int words = XVECLEN (operands[0], 0);
1435 if (XVECLEN (operands[0], 0) == 1)
1436 return \"l\\t%1,0(%2)\";
1438 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1439 return \"lm\\t%1,%0,%2\";
1441 [(set_attr "op_type" "RXE")
1442 (set_attr "atype" "mem")
1443 (set_attr "type" "lm")])
1446 ; store multiple pattern(s).
1449 (define_expand "store_multiple"
1450 [(match_par_dup 3 [(set (match_operand 0 "" "")
1451 (match_operand 1 "" ""))
1452 (use (match_operand 2 "" ""))])]
1461 /* Support only storing a constant number of fixed-point registers to
1462 memory and only bother with this if more than two. */
1463 if (GET_CODE (operands[2]) != CONST_INT
1464 || INTVAL (operands[2]) < 2
1465 || INTVAL (operands[2]) > 16
1466 || GET_CODE (operands[0]) != MEM
1467 || GET_CODE (operands[1]) != REG
1468 || REGNO (operands[1]) >= 16)
1471 count = INTVAL (operands[2]);
1472 regno = REGNO (operands[1]);
1474 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1478 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1480 to = XEXP (operands[0], 0);
1483 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1484 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1485 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1487 to = XEXP (XEXP (operands[0], 0), 0);
1488 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1493 if (to == frame_pointer_rtx || to == arg_pointer_rtx)
1498 to = force_reg (Pmode, XEXP (operands[0], 0));
1502 for (i = 0; i < count; i++)
1503 XVECEXP (operands[3], 0, i)
1504 = gen_rtx_SET (VOIDmode,
1505 change_address (operands[0], Pmode,
1507 off + i * UNITS_PER_WORD)),
1508 gen_rtx_REG (Pmode, regno + i));
1511 (define_insn "*store_multiple_di"
1512 [(match_parallel 0 "store_multiple_operation"
1513 [(set (match_operand:DI 1 "s_operand" "=Q")
1514 (match_operand:DI 2 "register_operand" "r"))])]
1518 int words = XVECLEN (operands[0], 0);
1520 if (XVECLEN (operands[0], 0) == 1)
1521 return \"stg\\t%1,0(%2)\";
1523 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1524 return \"stmg\\t%2,%0,%1\";
1526 [(set_attr "op_type" "RXE")
1527 (set_attr "atype" "mem")
1528 (set_attr "type" "stm")])
1531 (define_insn "*store_multiple_si"
1532 [(match_parallel 0 "store_multiple_operation"
1533 [(set (match_operand:SI 1 "s_operand" "=Q")
1534 (match_operand:SI 2 "register_operand" "r"))])]
1538 int words = XVECLEN (operands[0], 0);
1540 if (XVECLEN (operands[0], 0) == 1)
1541 return \"st\\t%1,0(%2)\";
1543 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1544 return \"stm\\t%2,%0,%1\";
1546 [(set_attr "op_type" "RXE")
1547 (set_attr "atype" "mem")
1548 (set_attr "type" "stm")])
1551 ;; String instructions.
1555 ; movstrM instruction pattern(s).
1558 (define_expand "movstrdi"
1559 [(set (match_operand:BLK 0 "memory_operand" "")
1560 (match_operand:BLK 1 "memory_operand" ""))
1561 (use (match_operand:DI 2 "general_operand" ""))
1562 (match_operand 3 "" "")]
1564 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1566 (define_expand "movstrsi"
1567 [(set (match_operand:BLK 0 "memory_operand" "")
1568 (match_operand:BLK 1 "memory_operand" ""))
1569 (use (match_operand:SI 2 "general_operand" ""))
1570 (match_operand 3 "" "")]
1572 "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;")
1574 ; Move a block that is up to 256 bytes in length.
1575 ; The block length is taken as (operands[2] % 256) + 1.
1577 (define_insn "movstr_short_64"
1578 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1579 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1580 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1581 (clobber (match_scratch:DI 3 "=X,&a"))]
1585 switch (which_alternative)
1588 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1591 output_asm_insn (\"bras\\t%3,.+10\", operands);
1592 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1593 return \"ex\\t%2,0(%3)\";
1599 [(set_attr "op_type" "SS,NN")
1600 (set_attr "type" "cs,cs")
1601 (set_attr "atype" "mem,mem")
1602 (set_attr "length" "*,14")])
1604 (define_insn "movstr_short_31"
1605 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1606 (match_operand:BLK 1 "memory_operand" "Q,Q"))
1607 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1608 (clobber (match_scratch:SI 3 "=X,&a"))]
1612 switch (which_alternative)
1615 return \"mvc\\t%O0(%b2+1,%R0),%1\";
1618 output_asm_insn (\"bras\\t%3,.+10\", operands);
1619 output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
1620 return \"ex\\t%2,0(%3)\";
1626 [(set_attr "op_type" "SS,NN")
1627 (set_attr "type" "cs,cs")
1628 (set_attr "atype" "mem,mem")
1629 (set_attr "length" "*,14")])
1631 ; Move a block of arbitrary length.
1633 (define_insn "movstr_long_64"
1634 [(set (match_operand:TI 0 "register_operand" "=d")
1635 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1636 (lshiftrt:TI (match_dup 2) (const_int 64)))
1638 (set (match_operand:TI 1 "register_operand" "=d")
1639 (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1")
1640 (lshiftrt:TI (match_dup 3) (const_int 64)))
1642 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1643 (mem:BLK (subreg:DI (match_dup 3) 0)))
1644 (clobber (reg:CC 33))]
1646 "mvcle\\t%0,%1,0\;jo\\t.-4"
1647 [(set_attr "op_type" "NN")
1648 (set_attr "type" "vs")
1649 (set_attr "atype" "mem")
1650 (set_attr "length" "8")])
1652 (define_insn "movstr_long_31"
1653 [(set (match_operand:DI 0 "register_operand" "=d")
1654 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1655 (lshiftrt:DI (match_dup 2) (const_int 32)))
1657 (set (match_operand:DI 1 "register_operand" "=d")
1658 (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1")
1659 (lshiftrt:DI (match_dup 3) (const_int 32)))
1661 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1662 (mem:BLK (subreg:SI (match_dup 3) 0)))
1663 (clobber (reg:CC 33))]
1665 "mvcle\\t%0,%1,0\;jo\\t.-4"
1666 [(set_attr "op_type" "NN")
1667 (set_attr "type" "vs")
1668 (set_attr "atype" "mem")
1669 (set_attr "length" "8")])
1672 ; clrstrM instruction pattern(s).
1675 (define_expand "clrstrdi"
1676 [(set (match_operand:BLK 0 "memory_operand" "")
1678 (use (match_operand:DI 1 "general_operand" ""))
1679 (match_operand 2 "" "")]
1681 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1683 (define_expand "clrstrsi"
1684 [(set (match_operand:BLK 0 "memory_operand" "")
1686 (use (match_operand:SI 1 "general_operand" ""))
1687 (match_operand 2 "" "")]
1689 "s390_expand_clrstr (operands[0], operands[1]); DONE;")
1691 ; Clear a block that is up to 256 bytes in length.
1692 ; The block length is taken as (operands[2] % 256) + 1.
1694 (define_insn "clrstr_short_64"
1695 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1697 (use (match_operand:DI 1 "nonmemory_operand" "n,a"))
1698 (clobber (match_scratch:DI 2 "=X,&a"))
1699 (clobber (reg:CC 33))]
1703 switch (which_alternative)
1706 return \"xc\\t%O0(%b1+1,%R0),%0\";
1709 output_asm_insn (\"bras\\t%2,.+10\", operands);
1710 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1711 return \"ex\\t%1,0(%2)\";
1717 [(set_attr "op_type" "SS,NN")
1718 (set_attr "type" "cs,cs")
1719 (set_attr "atype" "mem,mem")
1720 (set_attr "length" "*,14")])
1722 (define_insn "clrstr_short_31"
1723 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q")
1725 (use (match_operand:SI 1 "nonmemory_operand" "n,a"))
1726 (clobber (match_scratch:SI 2 "=X,&a"))
1727 (clobber (reg:CC 33))]
1731 switch (which_alternative)
1734 return \"xc\\t%O0(%b1+1,%R0),%0\";
1737 output_asm_insn (\"bras\\t%2,.+10\", operands);
1738 output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
1739 return \"ex\\t%1,0(%2)\";
1745 [(set_attr "op_type" "SS,NN")
1746 (set_attr "type" "cs,cs")
1747 (set_attr "atype" "mem,mem")
1748 (set_attr "length" "*,14")])
1750 ; Clear a block of arbitrary length.
1752 (define_insn "clrstr_long_64"
1753 [(set (match_operand:TI 0 "register_operand" "=d")
1754 (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0")
1755 (lshiftrt:TI (match_dup 2) (const_int 64)))
1757 (set (mem:BLK (subreg:DI (match_dup 2) 0))
1759 (use (match_operand:TI 1 "register_operand" "d"))
1760 (clobber (reg:CC 33))]
1762 "mvcle\\t%0,%1,0\;jo\\t.-4"
1763 [(set_attr "op_type" "NN")
1764 (set_attr "atype" "mem")
1765 (set_attr "type" "vs")
1766 (set_attr "length" "8")])
1768 (define_insn "clrstr_long_31"
1769 [(set (match_operand:DI 0 "register_operand" "=d")
1770 (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0")
1771 (lshiftrt:DI (match_dup 2) (const_int 32)))
1773 (set (mem:BLK (subreg:SI (match_dup 2) 0))
1775 (use (match_operand:DI 1 "register_operand" "d"))
1776 (clobber (reg:CC 33))]
1778 "mvcle\\t%0,%1,0\;jo\\t.-4"
1779 [(set_attr "op_type" "NN")
1780 (set_attr "atype" "mem")
1781 (set_attr "type" "vs")
1782 (set_attr "length" "8")])
1785 ; cmpstrM instruction pattern(s).
1788 (define_expand "cmpstrdi"
1789 [(set (match_operand:DI 0 "register_operand" "")
1790 (compare:DI (match_operand:BLK 1 "memory_operand" "")
1791 (match_operand:BLK 2 "memory_operand" "") ) )
1792 (use (match_operand:DI 3 "general_operand" ""))
1793 (use (match_operand:DI 4 "" ""))]
1795 "s390_expand_cmpstr (operands[0], operands[1],
1796 operands[2], operands[3]); DONE;")
1798 (define_expand "cmpstrsi"
1799 [(set (match_operand:SI 0 "register_operand" "")
1800 (compare:SI (match_operand:BLK 1 "memory_operand" "")
1801 (match_operand:BLK 2 "memory_operand" "") ) )
1802 (use (match_operand:SI 3 "general_operand" ""))
1803 (use (match_operand:SI 4 "" ""))]
1805 "s390_expand_cmpstr (operands[0], operands[1],
1806 operands[2], operands[3]); DONE;")
1808 ; Compare a block that is up to 256 bytes in length.
1809 ; The block length is taken as (operands[2] % 256) + 1.
1811 (define_insn "cmpstr_short_64"
1813 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1814 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1815 (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
1816 (clobber (match_scratch:DI 3 "=X,&a"))]
1820 switch (which_alternative)
1823 return \"clc\\t%O0(%b2+1,%R0),%1\";
1826 output_asm_insn (\"bras\\t%3,.+10\", operands);
1827 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1828 return \"ex\\t%2,0(%3)\";
1834 [(set_attr "op_type" "SS,NN")
1835 (set_attr "type" "cs,cs")
1836 (set_attr "atype" "mem,mem")
1837 (set_attr "length" "*,14")])
1839 (define_insn "cmpstr_short_31"
1841 (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
1842 (match_operand:BLK 1 "memory_operand" "Q,Q")))
1843 (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
1844 (clobber (match_scratch:SI 3 "=X,&a"))]
1848 switch (which_alternative)
1851 return \"clc\\t%O0(%b2+1,%R0),%1\";
1854 output_asm_insn (\"bras\\t%3,.+10\", operands);
1855 output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
1856 return \"ex\\t%2,0(%3)\";
1862 [(set_attr "op_type" "SS,NN")
1863 (set_attr "type" "cs,cs")
1864 (set_attr "atype" "mem,mem")
1865 (set_attr "length" "*,14")])
1867 ; Compare a block of arbitrary length.
1869 (define_insn "cmpstr_long_64"
1870 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1871 (clobber (match_operand:TI 1 "register_operand" "=d"))
1873 (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1874 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
1876 (use (match_dup 3))]
1879 [(set_attr "op_type" "RR")
1880 (set_attr "atype" "mem")
1881 (set_attr "type" "vs")])
1883 (define_insn "cmpstr_long_31"
1884 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1885 (clobber (match_operand:DI 1 "register_operand" "=d"))
1887 (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1888 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
1890 (use (match_dup 3))]
1893 [(set_attr "op_type" "RR")
1894 (set_attr "atype" "mem")
1895 (set_attr "type" "vs")])
1897 ; Convert condition code to integer in range (-1, 0, 1)
1899 (define_insn "cmpint_si"
1900 [(set (match_operand:SI 0 "register_operand" "=d")
1901 (compare:SI (reg:CCS 33) (const_int 0)))]
1905 output_asm_insn (\"lhi\\t%0,1\", operands);
1906 output_asm_insn (\"jh\\t.+12\", operands);
1907 output_asm_insn (\"jl\\t.+6\", operands);
1908 output_asm_insn (\"sr\\t%0,%0\", operands);
1909 return \"lcr\\t%0,%0\";
1911 [(set_attr "op_type" "NN")
1912 (set_attr "length" "16")
1913 (set_attr "atype" "reg")
1914 (set_attr "type" "other")])
1916 (define_insn "cmpint_di"
1917 [(set (match_operand:DI 0 "register_operand" "=d")
1918 (compare:DI (reg:CCS 33) (const_int 0)))]
1922 output_asm_insn (\"lghi\\t%0,1\", operands);
1923 output_asm_insn (\"jh\\t.+12\", operands);
1924 output_asm_insn (\"jl\\t.+6\", operands);
1925 output_asm_insn (\"sgr\\t%0,%0\", operands);
1926 return \"lcgr\\t%0,%0\";
1928 [(set_attr "op_type" "NN")
1929 (set_attr "length" "22")
1930 (set_attr "atype" "reg")
1931 (set_attr "type" "other")])
1935 ;;- Conversion instructions.
1938 (define_insn "*sethighqisi"
1939 [(set (match_operand:SI 0 "register_operand" "=d")
1940 (unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10))
1941 (clobber (reg:CC 33))]
1944 [(set_attr "op_type" "RS")
1945 (set_attr "atype" "mem")])
1947 (define_insn "*sethighhisi"
1948 [(set (match_operand:SI 0 "register_operand" "=d")
1949 (unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10))
1950 (clobber (reg:CC 33))]
1953 [(set_attr "op_type" "RS")
1954 (set_attr "atype" "mem")])
1956 (define_insn "*sethighqidi_64"
1957 [(set (match_operand:DI 0 "register_operand" "=d")
1958 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
1959 (clobber (reg:CC 33))]
1962 [(set_attr "op_type" "RSE")
1963 (set_attr "atype" "mem")])
1965 (define_insn "*sethighqidi_31"
1966 [(set (match_operand:DI 0 "register_operand" "=d")
1967 (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10))
1968 (clobber (reg:CC 33))]
1971 [(set_attr "op_type" "RS")
1972 (set_attr "atype" "mem")])
1974 (define_insn_and_split "*extractqi"
1975 [(set (match_operand:SI 0 "register_operand" "=d")
1976 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
1977 (match_operand 2 "const_int_operand" "n")
1979 (clobber (reg:CC 33))]
1981 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
1983 "&& reload_completed"
1985 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
1986 (clobber (reg:CC 33))])
1987 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
1990 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1991 operands[1] = change_address (operands[1], QImode, 0);
1993 [(set_attr "type" "o2")
1994 (set_attr "atype" "mem")])
1996 (define_insn_and_split "*extracthi"
1997 [(set (match_operand:SI 0 "register_operand" "=d")
1998 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
1999 (match_operand 2 "const_int_operand" "n")
2001 (clobber (reg:CC 33))]
2003 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2005 "&& reload_completed"
2007 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2008 (clobber (reg:CC 33))])
2009 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2012 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2013 operands[1] = change_address (operands[1], HImode, 0);
2015 [(set_attr "type" "o2")
2016 (set_attr "atype" "mem")])
2019 ; extendsidi2 instruction pattern(s).
2022 (define_expand "extendsidi2"
2023 [(set (match_operand:DI 0 "register_operand" "")
2024 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2030 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2031 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2032 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2033 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2039 (define_insn "*extendsidi2"
2040 [(set (match_operand:DI 0 "register_operand" "=d,d")
2041 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2046 [(set_attr "op_type" "RRE,RXE")
2047 (set_attr "atype" "reg,mem")])
2050 ; extendhidi2 instruction pattern(s).
2053 (define_expand "extendhidi2"
2054 [(set (match_operand:DI 0 "register_operand" "")
2055 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2061 rtx tmp = gen_reg_rtx (SImode);
2062 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2063 emit_insn (gen_extendsidi2 (operands[0], tmp));
2068 operands[1] = gen_lowpart (DImode, operands[1]);
2069 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2070 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2076 (define_insn "*extendhidi2"
2077 [(set (match_operand:DI 0 "register_operand" "=d")
2078 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2081 [(set_attr "op_type" "RXE")
2082 (set_attr "atype" "mem")])
2085 ; extendqidi2 instruction pattern(s).
2088 (define_expand "extendqidi2"
2089 [(set (match_operand:DI 0 "register_operand" "")
2090 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2096 rtx tmp = gen_reg_rtx (SImode);
2097 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2098 emit_insn (gen_extendsidi2 (operands[0], tmp));
2103 operands[1] = gen_lowpart (DImode, operands[1]);
2104 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2105 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2112 [(set (match_operand:DI 0 "register_operand" "")
2113 (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
2114 "TARGET_64BIT && !reload_completed"
2116 [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
2117 (clobber (reg:CC 33))])
2119 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2120 (clobber (reg:CC 33))])]
2124 ; extendhisi2 instruction pattern(s).
2127 (define_expand "extendhisi2"
2128 [(set (match_operand:SI 0 "register_operand" "")
2129 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2133 operands[1] = gen_lowpart (SImode, operands[1]);
2134 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2135 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2140 (define_insn "*extendhisi2"
2141 [(set (match_operand:SI 0 "register_operand" "=d")
2142 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2145 [(set_attr "op_type" "RX")
2146 (set_attr "atype" "mem")])
2149 ; extendqisi2 instruction pattern(s).
2152 (define_expand "extendqisi2"
2153 [(set (match_operand:SI 0 "register_operand" "")
2154 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2158 operands[1] = gen_lowpart (SImode, operands[1]);
2159 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2160 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2166 [(set (match_operand:SI 0 "register_operand" "")
2167 (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
2170 [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
2171 (clobber (reg:CC 33))])
2173 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2174 (clobber (reg:CC 33))])]
2178 ; extendqihi2 instruction pattern(s).
2183 ; zero_extendsidi2 instruction pattern(s).
2186 (define_expand "zero_extendsidi2"
2187 [(set (match_operand:DI 0 "register_operand" "")
2188 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2194 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2195 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2196 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2202 (define_insn "*zero_extendsidi2"
2203 [(set (match_operand:DI 0 "register_operand" "=d,d")
2204 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2209 [(set_attr "op_type" "RRE,RXE")
2210 (set_attr "atype" "reg,mem")])
2213 ; zero_extendhidi2 instruction pattern(s).
2216 (define_expand "zero_extendhidi2"
2217 [(set (match_operand:DI 0 "register_operand" "")
2218 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2224 rtx tmp = gen_reg_rtx (SImode);
2225 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2226 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2231 operands[1] = gen_lowpart (DImode, operands[1]);
2232 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2233 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2239 (define_insn "*zero_extendhidi2"
2240 [(set (match_operand:DI 0 "register_operand" "=d")
2241 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2244 [(set_attr "op_type" "RXE")
2245 (set_attr "atype" "mem")])
2248 ; zero_extendqidi2 instruction pattern(s)
2251 (define_expand "zero_extendqidi2"
2252 [(set (match_operand:DI 0 "register_operand" "")
2253 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2259 rtx tmp = gen_reg_rtx (SImode);
2260 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2261 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2266 operands[1] = gen_lowpart (DImode, operands[1]);
2267 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2268 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2274 (define_insn "*zero_extendqidi2"
2275 [(set (match_operand:DI 0 "register_operand" "=d")
2276 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2279 [(set_attr "op_type" "RXE")
2280 (set_attr "atype" "mem")])
2283 ; zero_extendhisi2 instruction pattern(s).
2286 (define_expand "zero_extendhisi2"
2287 [(set (match_operand:SI 0 "register_operand" "")
2288 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2292 operands[1] = gen_lowpart (SImode, operands[1]);
2293 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2298 (define_insn "*zero_extendhisi2_64"
2299 [(set (match_operand:SI 0 "register_operand" "=d")
2300 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2303 [(set_attr "op_type" "RXE")
2304 (set_attr "atype" "mem")])
2306 (define_insn_and_split "*zero_extendhisi2_31"
2307 [(set (match_operand:SI 0 "register_operand" "=&d")
2308 (zero_extend:SI (match_operand:HI 1 "memory_operand" "Q")))
2309 (clobber (reg:CC 33))]
2312 "&& reload_completed"
2313 [(set (match_dup 0) (const_int 0))
2315 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2316 (clobber (reg:CC 33))])]
2317 "operands[2] = gen_lowpart (HImode, operands[0]);"
2318 [(set_attr "type" "o2")
2319 (set_attr "atype" "mem")])
2322 ; zero_extendqisi2 instruction pattern(s).
2325 (define_expand "zero_extendqisi2"
2326 [(set (match_operand:SI 0 "register_operand" "")
2327 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2331 operands[1] = gen_lowpart (SImode, operands[1]);
2332 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2337 (define_insn "*zero_extendqisi2_64"
2338 [(set (match_operand:SI 0 "register_operand" "=d")
2339 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2342 [(set_attr "op_type" "RXE")
2343 (set_attr "atype" "mem")])
2345 (define_insn_and_split "*zero_extendqisi2_31"
2346 [(set (match_operand:SI 0 "register_operand" "=&d")
2347 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2350 "&& reload_completed"
2351 [(set (match_dup 0) (const_int 0))
2352 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2353 "operands[2] = gen_lowpart (QImode, operands[0]);"
2354 [(set_attr "type" "o2")
2355 (set_attr "atype" "mem")])
2358 ; zero_extendqihi2 instruction pattern(s).
2361 (define_expand "zero_extendqihi2"
2362 [(set (match_operand:HI 0 "register_operand" "")
2363 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2367 operands[1] = gen_lowpart (HImode, operands[1]);
2368 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2373 (define_insn "*zero_extendqihi2_64"
2374 [(set (match_operand:HI 0 "register_operand" "=d")
2375 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2378 [(set_attr "op_type" "RXE")
2379 (set_attr "atype" "mem")])
2381 (define_insn_and_split "*zero_extendqihi2_31"
2382 [(set (match_operand:HI 0 "register_operand" "=&d")
2383 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2386 "&& reload_completed"
2387 [(set (match_dup 0) (const_int 0))
2388 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2389 "operands[2] = gen_lowpart (QImode, operands[0]);"
2390 [(set_attr "type" "o2")
2391 (set_attr "atype" "mem")])
2395 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2398 (define_expand "fixuns_truncdfdi2"
2399 [(set (match_operand:DI 0 "register_operand" "")
2400 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2401 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2404 rtx label1 = gen_label_rtx ();
2405 rtx label2 = gen_label_rtx ();
2406 rtx temp = gen_reg_rtx (DFmode);
2407 operands[1] = force_reg (DFmode, operands[1]);
2409 emit_insn (gen_cmpdf (operands[1],
2410 CONST_DOUBLE_FROM_REAL_VALUE (
2411 REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
2412 emit_jump_insn (gen_blt (label1));
2413 emit_insn (gen_subdf3 (temp, operands[1],
2414 CONST_DOUBLE_FROM_REAL_VALUE (
2415 REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
2416 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2419 emit_label (label1);
2420 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2421 emit_label (label2);
2425 (define_expand "fix_truncdfdi2"
2426 [(set (match_operand:DI 0 "register_operand" "")
2427 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2428 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2431 operands[1] = force_reg (DFmode, operands[1]);
2432 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2436 (define_insn "fix_truncdfdi2_ieee"
2437 [(set (match_operand:DI 0 "register_operand" "=d")
2438 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2439 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2440 (clobber (reg:CC 33))]
2441 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2443 [(set_attr "op_type" "RRE")
2444 (set_attr "type" "other")])
2447 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2450 (define_expand "fixuns_truncdfsi2"
2451 [(set (match_operand:SI 0 "register_operand" "")
2452 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2453 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2456 rtx label1 = gen_label_rtx ();
2457 rtx label2 = gen_label_rtx ();
2458 rtx temp = gen_reg_rtx (DFmode);
2460 operands[1] = force_reg (DFmode,operands[1]);
2461 emit_insn (gen_cmpdf (operands[1],
2462 CONST_DOUBLE_FROM_REAL_VALUE (
2463 REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
2464 emit_jump_insn (gen_blt (label1));
2465 emit_insn (gen_subdf3 (temp, operands[1],
2466 CONST_DOUBLE_FROM_REAL_VALUE (
2467 REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
2468 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2471 emit_label (label1);
2472 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2473 emit_label (label2);
2477 (define_expand "fix_truncdfsi2"
2478 [(set (match_operand:SI 0 "register_operand" "")
2479 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2483 if (TARGET_IBM_FLOAT)
2485 /* This is the algorithm from POP chapter A.5.7.2. */
2487 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2488 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2489 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2491 operands[1] = force_reg (DFmode, operands[1]);
2492 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2493 two31r, two32, temp));
2497 operands[1] = force_reg (DFmode, operands[1]);
2498 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2504 (define_insn "fix_truncdfsi2_ieee"
2505 [(set (match_operand:SI 0 "register_operand" "=d")
2506 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2507 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2508 (clobber (reg:CC 33))]
2509 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2511 [(set_attr "op_type" "RRE")
2512 (set_attr "type" "other" )])
2514 (define_insn "fix_truncdfsi2_ibm"
2515 [(set (match_operand:SI 0 "register_operand" "=d")
2516 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2517 (use (match_operand:DI 2 "immediate_operand" "m"))
2518 (use (match_operand:DI 3 "immediate_operand" "m"))
2519 (use (match_operand:BLK 4 "memory_operand" "m"))
2520 (clobber (reg:CC 33))]
2521 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2524 output_asm_insn (\"sd\\t%1,%2\", operands);
2525 output_asm_insn (\"aw\\t%1,%3\", operands);
2526 output_asm_insn (\"std\\t%1,%4\", operands);
2527 output_asm_insn (\"xi\\t%N4,128\", operands);
2528 return \"l\\t%0,%N4\";
2530 [(set_attr "op_type" "NN")
2531 (set_attr "type" "other")
2532 (set_attr "length" "20")])
2535 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2538 (define_expand "fixuns_truncsfdi2"
2539 [(set (match_operand:DI 0 "register_operand" "")
2540 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2541 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2544 rtx label1 = gen_label_rtx ();
2545 rtx label2 = gen_label_rtx ();
2546 rtx temp = gen_reg_rtx (SFmode);
2548 operands[1] = force_reg (SFmode, operands[1]);
2549 emit_insn (gen_cmpsf (operands[1],
2550 CONST_DOUBLE_FROM_REAL_VALUE (
2551 REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
2552 emit_jump_insn (gen_blt (label1));
2554 emit_insn (gen_subsf3 (temp, operands[1],
2555 CONST_DOUBLE_FROM_REAL_VALUE (
2556 REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
2557 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2560 emit_label (label1);
2561 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2562 emit_label (label2);
2566 (define_expand "fix_truncsfdi2"
2567 [(set (match_operand:DI 0 "register_operand" "")
2568 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2569 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2572 operands[1] = force_reg (SFmode, operands[1]);
2573 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2577 (define_insn "fix_truncsfdi2_ieee"
2578 [(set (match_operand:DI 0 "register_operand" "=d")
2579 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2580 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2581 (clobber (reg:CC 33))]
2582 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2584 [(set_attr "op_type" "RRE")
2585 (set_attr "type" "other")])
2588 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2591 (define_expand "fixuns_truncsfsi2"
2592 [(set (match_operand:SI 0 "register_operand" "")
2593 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2594 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2597 rtx label1 = gen_label_rtx ();
2598 rtx label2 = gen_label_rtx ();
2599 rtx temp = gen_reg_rtx (SFmode);
2601 operands[1] = force_reg (SFmode, operands[1]);
2602 emit_insn (gen_cmpsf (operands[1],
2603 CONST_DOUBLE_FROM_REAL_VALUE (
2604 REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
2605 emit_jump_insn (gen_blt (label1));
2606 emit_insn (gen_subsf3 (temp, operands[1],
2607 CONST_DOUBLE_FROM_REAL_VALUE (
2608 REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
2609 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2612 emit_label (label1);
2613 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2614 emit_label (label2);
2618 (define_expand "fix_truncsfsi2"
2619 [(set (match_operand:SI 0 "register_operand" "")
2620 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2624 if (TARGET_IBM_FLOAT)
2626 /* Convert to DFmode and then use the POP algorithm. */
2627 rtx temp = gen_reg_rtx (DFmode);
2628 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2629 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2633 operands[1] = force_reg (SFmode, operands[1]);
2634 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2640 (define_insn "fix_truncsfsi2_ieee"
2641 [(set (match_operand:SI 0 "register_operand" "=d")
2642 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2643 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2644 (clobber (reg:CC 33))]
2645 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2647 [(set_attr "op_type" "RRE")
2648 (set_attr "type" "other")])
2651 ; floatdidf2 instruction pattern(s).
2654 (define_insn "floatdidf2"
2655 [(set (match_operand:DF 0 "register_operand" "=f")
2656 (float:DF (match_operand:DI 1 "register_operand" "d")))
2657 (clobber (reg:CC 33))]
2658 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2660 [(set_attr "op_type" "RRE")
2661 (set_attr "type" "other" )])
2664 ; floatdisf2 instruction pattern(s).
2667 (define_insn "floatdisf2"
2668 [(set (match_operand:SF 0 "register_operand" "=f")
2669 (float:SF (match_operand:DI 1 "register_operand" "d")))
2670 (clobber (reg:CC 33))]
2671 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2673 [(set_attr "op_type" "RRE")
2674 (set_attr "type" "other" )])
2677 ; floatsidf2 instruction pattern(s).
2680 (define_expand "floatsidf2"
2682 [(set (match_operand:DF 0 "register_operand" "")
2683 (float:DF (match_operand:SI 1 "register_operand" "")))
2684 (clobber (reg:CC 33))])]
2688 if (TARGET_IBM_FLOAT)
2690 /* This is the algorithm from POP chapter A.5.7.1. */
2692 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2693 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
2695 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2700 (define_insn "floatsidf2_ieee"
2701 [(set (match_operand:DF 0 "register_operand" "=f")
2702 (float:DF (match_operand:SI 1 "register_operand" "d")))
2703 (clobber (reg:CC 33))]
2704 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2706 [(set_attr "op_type" "RRE")
2707 (set_attr "type" "other" )])
2709 (define_insn "floatsidf2_ibm"
2710 [(set (match_operand:DF 0 "register_operand" "=f")
2711 (float:DF (match_operand:SI 1 "register_operand" "d")))
2712 (use (match_operand:DI 2 "immediate_operand" "m"))
2713 (use (match_operand:BLK 3 "memory_operand" "m"))
2714 (clobber (reg:CC 33))]
2715 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2718 output_asm_insn (\"st\\t%1,%N3\", operands);
2719 output_asm_insn (\"xi\\t%N3,128\", operands);
2720 output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2721 output_asm_insn (\"ld\\t%0,%3\", operands);
2722 return \"sd\\t%0,%2\";
2724 [(set_attr "op_type" "NN")
2725 (set_attr "type" "other" )
2726 (set_attr "length" "20")])
2729 ; floatsisf2 instruction pattern(s).
2732 (define_expand "floatsisf2"
2734 [(set (match_operand:SF 0 "register_operand" "")
2735 (float:SF (match_operand:SI 1 "register_operand" "")))
2736 (clobber (reg:CC 33))])]
2740 if (TARGET_IBM_FLOAT)
2742 /* Use the POP algorithm to convert to DFmode and then truncate. */
2743 rtx temp = gen_reg_rtx (DFmode);
2744 emit_insn (gen_floatsidf2 (temp, operands[1]));
2745 emit_insn (gen_truncdfsf2 (operands[0], temp));
2750 (define_insn "floatsisf2_ieee"
2751 [(set (match_operand:SF 0 "register_operand" "=f")
2752 (float:SF (match_operand:SI 1 "register_operand" "d")))
2753 (clobber (reg:CC 33))]
2754 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2756 [(set_attr "op_type" "RRE")
2757 (set_attr "type" "other" )])
2760 ; truncdfsf2 instruction pattern(s).
2763 (define_expand "truncdfsf2"
2764 [(set (match_operand:SF 0 "register_operand" "")
2765 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2769 (define_insn "truncdfsf2_ieee"
2770 [(set (match_operand:SF 0 "register_operand" "=f")
2771 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
2772 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2774 [(set_attr "op_type" "RRE")])
2776 (define_insn "truncdfsf2_ibm"
2777 [(set (match_operand:SF 0 "register_operand" "=f,f")
2778 (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))]
2779 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2783 [(set_attr "op_type" "RR,RX")
2784 (set_attr "atype" "reg,mem")])
2787 ; extendsfdf2 instruction pattern(s).
2790 (define_expand "extendsfdf2"
2791 [(set (match_operand:DF 0 "register_operand" "")
2792 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2796 if (TARGET_IBM_FLOAT)
2798 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2803 (define_insn "extendsfdf2_ieee"
2804 [(set (match_operand:DF 0 "register_operand" "=f,f")
2805 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
2806 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2810 [(set_attr "op_type" "RRE,RXE")])
2812 (define_insn "extendsfdf2_ibm"
2813 [(set (match_operand:DF 0 "register_operand" "=f,f")
2814 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
2815 (clobber (reg:CC 33))]
2816 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2818 sdr\\t%0,%0\;ler\\t%0,%1
2819 sdr\\t%0,%0\;le\\t%0,%1"
2820 [(set_attr "op_type" "RRE,RXE")
2821 (set_attr "atype" "reg,mem")
2822 (set_attr "type" "o2,o2")])
2826 ;; ARITHMETRIC OPERATIONS
2828 ; arithmetric operations set the ConditionCode,
2829 ; because of unpredictable Bits in Register for Halfword and Byte
2830 ; the ConditionCode can be set wrong in operations for Halfword and Byte
2833 ;;- Add instructions.
2837 ; adddi3 instruction pattern(s).
2840 (define_insn "*la_64_cc"
2841 [(set (match_operand:DI 0 "register_operand" "=d")
2842 (match_operand:QI 1 "address_operand" "p"))
2843 (clobber (reg:CC 33))]
2845 && preferred_la_operand_p (operands[1], 1)"
2847 [(set_attr "op_type" "RX")
2848 (set_attr "atype" "mem")
2849 (set_attr "type" "la")])
2852 [(set (match_operand:DI 0 "register_operand" "")
2853 (match_operand:QI 1 "address_operand" ""))
2854 (clobber (reg:CC 33))]
2855 "TARGET_64BIT && reload_completed
2856 && preferred_la_operand_p (operands[1], 0)"
2857 [(set (match_dup 0) (match_dup 1))])
2859 (define_insn "*adddi3_sign"
2860 [(set (match_operand:DI 0 "register_operand" "=d,d")
2861 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2862 (match_operand:DI 1 "register_operand" "0,0")))
2863 (clobber (reg:CC 33))]
2868 [(set_attr "op_type" "RRE,RXE")
2869 (set_attr "atype" "reg,mem")])
2871 (define_insn "*adddi3_zero_cc"
2873 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2874 (match_operand:DI 1 "register_operand" "0,0"))
2876 (set (match_operand:DI 0 "register_operand" "=d,d")
2877 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
2878 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2882 [(set_attr "op_type" "RRE,RXE")
2883 (set_attr "atype" "reg,mem")])
2885 (define_insn "*adddi3_zero_cconly"
2887 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2888 (match_operand:DI 1 "register_operand" "0,0"))
2890 (clobber (match_scratch:DI 0 "=d,d"))]
2891 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2895 [(set_attr "op_type" "RRE,RXE")
2896 (set_attr "atype" "reg,mem")])
2898 (define_insn "*adddi3_zero"
2899 [(set (match_operand:DI 0 "register_operand" "=d,d")
2900 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
2901 (match_operand:DI 1 "register_operand" "0,0")))
2902 (clobber (reg:CC 33))]
2907 [(set_attr "op_type" "RRE,RXE")
2908 (set_attr "atype" "reg,mem")])
2910 (define_insn "*adddi3_imm_cc"
2912 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
2913 (match_operand:DI 2 "const_int_operand" "K"))
2915 (set (match_operand:DI 0 "register_operand" "=d")
2916 (plus:DI (match_dup 1) (match_dup 2)))]
2918 && s390_match_ccmode (insn, CCAmode)
2919 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
2921 [(set_attr "op_type" "RI")
2922 (set_attr "atype" "reg")])
2924 (define_insn "*adddi3_cc"
2926 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2927 (match_operand:DI 2 "general_operand" "d,m"))
2929 (set (match_operand:DI 0 "register_operand" "=d,d")
2930 (plus:DI (match_dup 1) (match_dup 2)))]
2931 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2935 [(set_attr "op_type" "RRE,RXE")
2936 (set_attr "atype" "reg,mem")])
2938 (define_insn "*adddi3_cconly"
2940 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2941 (match_operand:DI 2 "general_operand" "d,m"))
2943 (clobber (match_scratch:DI 0 "=d,d"))]
2944 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
2948 [(set_attr "op_type" "RRE,RXE")
2949 (set_attr "atype" "reg,mem")])
2951 (define_insn "*adddi3_cconly2"
2953 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
2954 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
2955 (clobber (match_scratch:DI 0 "=d,d"))]
2956 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
2960 [(set_attr "op_type" "RRE,RXE")
2961 (set_attr "atype" "reg,mem")])
2963 (define_insn "*adddi3_64"
2964 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
2965 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
2966 (match_operand:DI 2 "general_operand" "d,K,m") ) )
2967 (clobber (reg:CC 33))]
2973 [(set_attr "op_type" "RRE,RI,RXE")
2974 (set_attr "atype" "reg,reg,mem")])
2976 (define_insn_and_split "*adddi3_31"
2977 [(set (match_operand:DI 0 "register_operand" "=&d")
2978 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
2979 (match_operand:DI 2 "general_operand" "dm") ) )
2980 (clobber (reg:CC 33))]
2983 "&& reload_completed"
2985 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
2986 (clobber (reg:CC 33))])
2989 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
2991 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
2993 (if_then_else (ltu (reg:CCL1 33) (const_int 0))
2995 (label_ref (match_dup 9))))
2997 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
2998 (clobber (reg:CC 33))])
3000 "operands[3] = operand_subword (operands[0], 0, 1, DImode);
3001 operands[4] = operand_subword (operands[1], 0, 1, DImode);
3002 operands[5] = operand_subword (operands[2], 0, 1, DImode);
3003 operands[6] = operand_subword (operands[0], 1, 1, DImode);
3004 operands[7] = operand_subword (operands[1], 1, 1, DImode);
3005 operands[8] = operand_subword (operands[2], 1, 1, DImode);
3006 operands[9] = gen_label_rtx ();"
3007 [(set_attr "op_type" "NN")
3008 (set_attr "type" "o3")])
3010 (define_expand "adddi3"
3012 [(set (match_operand:DI 0 "register_operand" "")
3013 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3014 (match_operand:DI 2 "general_operand" "")))
3015 (clobber (reg:CC 33))])]
3019 (define_insn "*la_64"
3020 [(set (match_operand:DI 0 "register_operand" "=d")
3021 (match_operand:QI 1 "address_operand" "p"))]
3024 [(set_attr "op_type" "RX")
3025 (set_attr "atype" "mem")
3026 (set_attr "type" "la")])
3028 (define_expand "reload_indi"
3029 [(parallel [(match_operand:DI 0 "register_operand" "=a")
3030 (match_operand:DI 1 "s390_plus_operand" "")
3031 (match_operand:DI 2 "register_operand" "=&a")])]
3035 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3041 ; addsi3 instruction pattern(s).
3044 (define_insn "*la_31_cc"
3045 [(set (match_operand:SI 0 "register_operand" "=d")
3046 (match_operand:QI 1 "address_operand" "p"))
3047 (clobber (reg:CC 33))]
3049 && preferred_la_operand_p (operands[1], 1)"
3051 [(set_attr "op_type" "RX")
3052 (set_attr "atype" "mem")
3053 (set_attr "type" "la")])
3056 [(set (match_operand:SI 0 "register_operand" "")
3057 (match_operand:QI 1 "address_operand" ""))
3058 (clobber (reg:CC 33))]
3059 "!TARGET_64BIT && reload_completed
3060 && preferred_la_operand_p (operands[1], 0)"
3061 [(set (match_dup 0) (match_dup 1))])
3063 (define_insn "*addsi3_imm_cc"
3065 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3066 (match_operand:SI 2 "const_int_operand" "K"))
3068 (set (match_operand:SI 0 "register_operand" "=d")
3069 (plus:SI (match_dup 1) (match_dup 2)))]
3070 "s390_match_ccmode (insn, CCAmode)
3071 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
3073 [(set_attr "op_type" "RI")
3074 (set_attr "atype" "reg")])
3076 (define_insn "*addsi3_carry1_cc"
3078 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3079 (match_operand:SI 2 "general_operand" "d,m"))
3081 (set (match_operand:SI 0 "register_operand" "=d,d")
3082 (plus:SI (match_dup 1) (match_dup 2)))]
3083 "s390_match_ccmode (insn, CCL1mode)"
3087 [(set_attr "op_type" "RR,RX")
3088 (set_attr "atype" "reg,mem")])
3090 (define_insn "*addsi3_carry1_cconly"
3092 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3093 (match_operand:SI 2 "general_operand" "d,m"))
3095 (clobber (match_scratch:SI 0 "=d,d"))]
3096 "s390_match_ccmode (insn, CCL1mode)"
3100 [(set_attr "op_type" "RR,RX")
3101 (set_attr "atype" "reg,mem")])
3103 (define_insn "*addsi3_carry2_cc"
3105 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3106 (match_operand:SI 2 "general_operand" "d,m"))
3108 (set (match_operand:SI 0 "register_operand" "=d,d")
3109 (plus:SI (match_dup 1) (match_dup 2)))]
3110 "s390_match_ccmode (insn, CCL1mode)"
3114 [(set_attr "op_type" "RR,RX")
3115 (set_attr "atype" "reg,mem")])
3117 (define_insn "*addsi3_carry2_cconly"
3119 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3120 (match_operand:SI 2 "general_operand" "d,m"))
3122 (clobber (match_scratch:SI 0 "=d,d"))]
3123 "s390_match_ccmode (insn, CCL1mode)"
3127 [(set_attr "op_type" "RR,RX")
3128 (set_attr "atype" "reg,mem")])
3130 (define_insn "*addsi3_cc"
3132 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3133 (match_operand:SI 2 "general_operand" "d,m"))
3135 (set (match_operand:SI 0 "register_operand" "=d,d")
3136 (plus:SI (match_dup 1) (match_dup 2)))]
3137 "s390_match_ccmode (insn, CCLmode)"
3141 [(set_attr "op_type" "RR,RX")
3142 (set_attr "atype" "reg,mem")])
3144 (define_insn "*addsi3_cconly"
3146 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3147 (match_operand:SI 2 "general_operand" "d,m"))
3149 (clobber (match_scratch:SI 0 "=d,d"))]
3150 "s390_match_ccmode (insn, CCLmode)"
3154 [(set_attr "op_type" "RR,RX")
3155 (set_attr "atype" "reg,mem")])
3157 (define_insn "*addsi3_cconly2"
3159 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0")
3160 (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
3161 (clobber (match_scratch:SI 0 "=d,d"))]
3162 "s390_match_ccmode(insn, CCLmode)"
3166 [(set_attr "op_type" "RR,RX")
3167 (set_attr "atype" "reg,mem")])
3169 (define_insn "*addsi3_sign"
3170 [(set (match_operand:SI 0 "register_operand" "=d")
3171 (plus:SI (match_operand:SI 1 "register_operand" "0")
3172 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3173 (clobber (reg:CC 33))]
3176 [(set_attr "op_type" "RX")
3177 (set_attr "atype" "mem")])
3179 (define_insn "*addsi3_sub"
3180 [(set (match_operand:SI 0 "register_operand" "=d")
3181 (plus:SI (match_operand:SI 1 "register_operand" "0")
3182 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3183 (clobber (reg:CC 33))]
3186 [(set_attr "op_type" "RX")
3187 (set_attr "atype" "mem")])
3189 (define_insn "addsi3"
3190 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3191 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3192 (match_operand:SI 2 "general_operand" "d,K,m")))
3193 (clobber (reg:CC 33))]
3199 [(set_attr "op_type" "RR,RI,RX")
3200 (set_attr "atype" "reg,reg,mem")])
3202 (define_insn "*la_31"
3203 [(set (match_operand:SI 0 "register_operand" "=d")
3204 (match_operand:QI 1 "address_operand" "p"))]
3205 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
3207 [(set_attr "op_type" "RX")
3208 (set_attr "atype" "mem")
3209 (set_attr "type" "la")])
3211 (define_insn "*la_31_and"
3212 [(set (match_operand:SI 0 "register_operand" "=d")
3213 (and:SI (match_operand:QI 1 "address_operand" "p")
3214 (const_int 2147483647)))]
3217 [(set_attr "op_type" "RX")
3218 (set_attr "atype" "mem")
3219 (set_attr "type" "la")])
3221 (define_insn_and_split "*la_31_and_cc"
3222 [(set (match_operand:SI 0 "register_operand" "=d")
3223 (and:SI (match_operand:QI 1 "address_operand" "p")
3224 (const_int 2147483647)))
3225 (clobber (reg:CC 33))]
3228 "&& reload_completed"
3230 (and:SI (match_dup 1) (const_int 2147483647)))]
3232 [(set_attr "op_type" "RX")
3233 (set_attr "atype" "mem")
3234 (set_attr "type" "la")])
3236 (define_insn "force_la_31"
3237 [(set (match_operand:SI 0 "register_operand" "=d")
3238 (match_operand:QI 1 "address_operand" "p"))
3239 (use (const_int 0))]
3242 [(set_attr "op_type" "RX")
3243 (set_attr "atype" "mem")
3244 (set_attr "type" "la")])
3246 (define_expand "reload_insi"
3247 [(parallel [(match_operand:SI 0 "register_operand" "=a")
3248 (match_operand:SI 1 "s390_plus_operand" "")
3249 (match_operand:SI 2 "register_operand" "=&a")])]
3253 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
3259 ; adddf3 instruction pattern(s).
3262 (define_expand "adddf3"
3264 [(set (match_operand:DF 0 "register_operand" "=f,f")
3265 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3266 (match_operand:DF 2 "general_operand" "f,m")))
3267 (clobber (reg:CC 33))])]
3271 (define_insn "*adddf3"
3272 [(set (match_operand:DF 0 "register_operand" "=f,f")
3273 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3274 (match_operand:DF 2 "general_operand" "f,m")))
3275 (clobber (reg:CC 33))]
3276 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3280 [(set_attr "op_type" "RRE,RXE")
3281 (set_attr "atype" "reg,mem")])
3283 (define_insn "*adddf3_ibm"
3284 [(set (match_operand:DF 0 "register_operand" "=f,f")
3285 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3286 (match_operand:DF 2 "general_operand" "f,m")))
3287 (clobber (reg:CC 33))]
3288 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3292 [(set_attr "op_type" "RR,RX")
3293 (set_attr "atype" "reg,mem")])
3296 ; addsf3 instruction pattern(s).
3299 (define_expand "addsf3"
3301 [(set (match_operand:SF 0 "register_operand" "=f,f")
3302 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3303 (match_operand:SF 2 "general_operand" "f,m")))
3304 (clobber (reg:CC 33))])]
3308 (define_insn "*addsf3"
3309 [(set (match_operand:SF 0 "register_operand" "=f,f")
3310 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3311 (match_operand:SF 2 "general_operand" "f,m")))
3312 (clobber (reg:CC 33))]
3313 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3317 [(set_attr "op_type" "RRE,RXE")
3318 (set_attr "atype" "reg,mem")])
3320 (define_insn "*addsf3"
3321 [(set (match_operand:SF 0 "register_operand" "=f,f")
3322 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3323 (match_operand:SF 2 "general_operand" "f,m")))
3324 (clobber (reg:CC 33))]
3325 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3329 [(set_attr "op_type" "RR,RX")
3330 (set_attr "atype" "reg,mem")])
3334 ;;- Subtract instructions.
3338 ; subdi3 instruction pattern(s).
3341 (define_insn "*subdi3_sign"
3342 [(set (match_operand:DI 0 "register_operand" "=d,d")
3343 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3344 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3345 (clobber (reg:CC 33))]
3350 [(set_attr "op_type" "RRE,RXE")
3351 (set_attr "atype" "reg,mem")])
3353 (define_insn "*subdi3_zero_cc"
3355 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3356 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3358 (set (match_operand:DI 0 "register_operand" "=d,d")
3359 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3360 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3364 [(set_attr "op_type" "RRE,RXE")
3365 (set_attr "atype" "reg,mem")])
3367 (define_insn "*subdi3_zero_cconly"
3369 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3370 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3372 (clobber (match_scratch:DI 0 "=d,d"))]
3373 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3377 [(set_attr "op_type" "RRE,RXE")
3378 (set_attr "atype" "reg,mem")])
3380 (define_insn "*subdi3_zero"
3381 [(set (match_operand:DI 0 "register_operand" "=d,d")
3382 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3383 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3384 (clobber (reg:CC 33))]
3389 [(set_attr "op_type" "RRE,RXE")
3390 (set_attr "atype" "reg,mem")])
3392 (define_insn "*subdi3_cc"
3394 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3395 (match_operand:DI 2 "general_operand" "d,m"))
3397 (set (match_operand:DI 0 "register_operand" "=d,d")
3398 (minus:DI (match_dup 1) (match_dup 2)))]
3399 "s390_match_ccmode (insn, CCLmode)"
3403 [(set_attr "op_type" "RRE,RXE")
3404 (set_attr "atype" "reg,mem")])
3406 (define_insn "*subdi3_cconly"
3408 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3409 (match_operand:DI 2 "general_operand" "d,m"))
3411 (clobber (match_scratch:DI 0 "=d,d"))]
3412 "s390_match_ccmode (insn, CCLmode)"
3416 [(set_attr "op_type" "RRE,RXE")
3417 (set_attr "atype" "reg,mem")])
3419 (define_insn "*subdi3_64"
3420 [(set (match_operand:DI 0 "register_operand" "=d,d")
3421 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3422 (match_operand:DI 2 "general_operand" "d,m") ) )
3423 (clobber (reg:CC 33))]
3428 [(set_attr "op_type" "RRE,RRE")
3429 (set_attr "atype" "reg,mem")])
3431 (define_insn_and_split "*subdi3_31"
3432 [(set (match_operand:DI 0 "register_operand" "=&d")
3433 (minus:DI (match_operand:DI 1 "register_operand" "0")
3434 (match_operand:DI 2 "general_operand" "dm") ) )
3435 (clobber (reg:CC 33))]
3438 "&& reload_completed"
3440 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3441 (clobber (reg:CC 33))])
3444 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3446 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3448 (if_then_else (gtu (reg:CCL2 33) (const_int 0))
3450 (label_ref (match_dup 9))))
3452 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
3453 (clobber (reg:CC 33))])
3455 "operands[3] = operand_subword (operands[0], 0, 1, DImode);
3456 operands[4] = operand_subword (operands[1], 0, 1, DImode);
3457 operands[5] = operand_subword (operands[2], 0, 1, DImode);
3458 operands[6] = operand_subword (operands[0], 1, 1, DImode);
3459 operands[7] = operand_subword (operands[1], 1, 1, DImode);
3460 operands[8] = operand_subword (operands[2], 1, 1, DImode);
3461 operands[9] = gen_label_rtx ();"
3462 [(set_attr "op_type" "NN")
3463 (set_attr "type" "o3")])
3465 (define_expand "subdi3"
3467 [(set (match_operand:DI 0 "register_operand" "")
3468 (minus:DI (match_operand:DI 1 "register_operand" "")
3469 (match_operand:DI 2 "general_operand" "")))
3470 (clobber (reg:CC 33))])]
3475 ; subsi3 instruction pattern(s).
3478 (define_insn "*subsi3_borrow_cc"
3480 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3481 (match_operand:SI 2 "general_operand" "d,m"))
3483 (set (match_operand:SI 0 "register_operand" "=d,d")
3484 (minus:SI (match_dup 1) (match_dup 2)))]
3485 "s390_match_ccmode(insn, CCL2mode)"
3489 [(set_attr "op_type" "RR,RX")
3490 (set_attr "atype" "reg,mem")])
3492 (define_insn "*subsi3_borrow_cconly"
3494 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3495 (match_operand:SI 2 "general_operand" "d,m"))
3497 (clobber (match_scratch:SI 0 "=d,d"))]
3498 "s390_match_ccmode(insn, CCL2mode)"
3502 [(set_attr "op_type" "RR,RX")
3503 (set_attr "atype" "reg,mem")])
3505 (define_insn "*subsi3_cc"
3507 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3508 (match_operand:SI 2 "general_operand" "d,m"))
3510 (set (match_operand:SI 0 "register_operand" "=d,d")
3511 (minus:SI (match_dup 1) (match_dup 2)))]
3512 "s390_match_ccmode(insn, CCLmode)"
3516 [(set_attr "op_type" "RR,RX")
3517 (set_attr "atype" "reg,mem")])
3519 (define_insn "*subsi3_cconly"
3521 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3522 (match_operand:SI 2 "general_operand" "d,m"))
3524 (clobber (match_scratch:SI 0 "=d,d"))]
3525 "s390_match_ccmode(insn, CCLmode)"
3529 [(set_attr "op_type" "RR,RX")
3530 (set_attr "atype" "reg,mem")])
3532 (define_insn "*subsi3_sign"
3533 [(set (match_operand:SI 0 "register_operand" "=d")
3534 (minus:SI (match_operand:SI 1 "register_operand" "0")
3535 (sign_extend:SI (match_operand:HI 2 "memory_operand" "m"))))
3536 (clobber (reg:CC 33))]
3539 [(set_attr "op_type" "RX")
3540 (set_attr "atype" "mem")])
3542 (define_insn "*subsi3_sub"
3543 [(set (match_operand:SI 0 "register_operand" "=d")
3544 (minus:SI (match_operand:SI 1 "register_operand" "0")
3545 (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0)))
3546 (clobber (reg:CC 33))]
3549 [(set_attr "op_type" "RX")
3550 (set_attr "atype" "mem")])
3552 (define_insn "subsi3"
3553 [(set (match_operand:SI 0 "register_operand" "=d,d")
3554 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3555 (match_operand:SI 2 "general_operand" "d,m")))
3556 (clobber (reg:CC 33))]
3561 [(set_attr "op_type" "RR,RX")
3562 (set_attr "atype" "reg,mem")])
3566 ; subdf3 instruction pattern(s).
3569 (define_expand "subdf3"
3571 [(set (match_operand:DF 0 "register_operand" "=f,f")
3572 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3573 (match_operand:DF 2 "general_operand" "f,m")))
3574 (clobber (reg:CC 33))])]
3578 (define_insn "*subdf3"
3579 [(set (match_operand:DF 0 "register_operand" "=f,f")
3580 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3581 (match_operand:DF 2 "general_operand" "f,m")))
3582 (clobber (reg:CC 33))]
3583 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3587 [(set_attr "op_type" "RRE,RXE")
3588 (set_attr "atype" "reg,mem")])
3590 (define_insn "*subdf3_ibm"
3591 [(set (match_operand:DF 0 "register_operand" "=f,f")
3592 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3593 (match_operand:DF 2 "general_operand" "f,m")))
3594 (clobber (reg:CC 33))]
3595 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3599 [(set_attr "op_type" "RR,RX")
3600 (set_attr "atype" "reg,mem")])
3603 ; subsf3 instruction pattern(s).
3606 (define_expand "subsf3"
3608 [(set (match_operand:SF 0 "register_operand" "=f,f")
3609 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3610 (match_operand:SF 2 "general_operand" "f,m")))
3611 (clobber (reg:CC 33))])]
3615 (define_insn "*subsf3"
3616 [(set (match_operand:SF 0 "register_operand" "=f,f")
3617 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3618 (match_operand:SF 2 "general_operand" "f,m")))
3619 (clobber (reg:CC 33))]
3620 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3624 [(set_attr "op_type" "RRE,RXE")
3625 (set_attr "atype" "reg,mem")])
3627 (define_insn "*subsf3_ibm"
3628 [(set (match_operand:SF 0 "register_operand" "=f,f")
3629 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3630 (match_operand:SF 2 "general_operand" "f,m")))
3631 (clobber (reg:CC 33))]
3632 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3636 [(set_attr "op_type" "RR,RX")
3637 (set_attr "atype" "reg,mem")])
3641 ;;- Multiply instructions.
3645 ; muldi3 instruction pattern(s).
3648 (define_insn "*muldi3_sign"
3649 [(set (match_operand:DI 0 "register_operand" "=d,d")
3650 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
3651 (match_operand:DI 1 "register_operand" "0,0")))]
3656 [(set_attr "op_type" "RRE,RXE")
3657 (set_attr "atype" "reg,mem")
3658 (set_attr "type" "imul")])
3661 (define_insn "muldi3"
3662 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3663 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3664 (match_operand:DI 2 "general_operand" "d,K,m")))]
3670 [(set_attr "op_type" "RRE,RI,RXE")
3671 (set_attr "atype" "reg,reg,mem")
3672 (set_attr "type" "imul")])
3675 ; mulsi3 instruction pattern(s).
3678 (define_insn "mulsi3"
3679 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3680 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3681 (match_operand:SI 2 "general_operand" "d,K,m")))]
3687 [(set_attr "op_type" "RRE,RI,RX")
3688 (set_attr "atype" "reg,reg,mem")
3689 (set_attr "type" "imul")])
3692 ; mulsidi3 instruction pattern(s).
3695 (define_expand "mulsidi3"
3696 [(set (match_operand:DI 0 "register_operand" "")
3697 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))
3698 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
3704 emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
3705 insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
3708 gen_rtx_EXPR_LIST (REG_EQUAL,
3709 gen_rtx_MULT (DImode,
3710 gen_rtx_SIGN_EXTEND (DImode, operands[1]),
3711 gen_rtx_SIGN_EXTEND (DImode, operands[2])),
3716 (define_insn "mulsi_6432"
3717 [(set (match_operand:DI 0 "register_operand" "=d,d")
3718 (mult:DI (sign_extend:DI
3719 (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
3721 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
3726 [(set_attr "op_type" "RR,RX")
3727 (set_attr "atype" "reg,mem")
3728 (set_attr "type" "imul")])
3731 ; muldf3 instruction pattern(s).
3734 (define_expand "muldf3"
3736 [(set (match_operand:DF 0 "register_operand" "=f,f")
3737 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3738 (match_operand:DF 2 "general_operand" "f,m")))
3739 (clobber (reg:CC 33))])]
3743 (define_insn "*muldf3"
3744 [(set (match_operand:DF 0 "register_operand" "=f,f")
3745 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3746 (match_operand:DF 2 "general_operand" "f,m")))
3747 (clobber (reg:CC 33))]
3748 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3752 [(set_attr "op_type" "RRE,RXE")
3753 (set_attr "type" "fmul")
3754 (set_attr "atype" "reg,mem")])
3756 (define_insn "*muldf3_ibm"
3757 [(set (match_operand:DF 0 "register_operand" "=f,f")
3758 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3759 (match_operand:DF 2 "general_operand" "f,m")))
3760 (clobber (reg:CC 33))]
3761 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3765 [(set_attr "op_type" "RR,RX")
3766 (set_attr "type" "fmul")
3767 (set_attr "atype" "reg,mem")])
3770 ; mulsf3 instruction pattern(s).
3773 (define_expand "mulsf3"
3775 [(set (match_operand:SF 0 "register_operand" "=f,f")
3776 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3777 (match_operand:SF 2 "general_operand" "f,m")))
3778 (clobber (reg:CC 33))])]
3782 (define_insn "*mulsf3"
3783 [(set (match_operand:SF 0 "register_operand" "=f,f")
3784 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3785 (match_operand:SF 2 "general_operand" "f,m")))
3786 (clobber (reg:CC 33))]
3787 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3791 [(set_attr "op_type" "RRE,RXE")
3792 (set_attr "type" "fmul")
3793 (set_attr "atype" "reg,mem")])
3795 (define_insn "*mulsf3_ibm"
3796 [(set (match_operand:SF 0 "register_operand" "=f,f")
3797 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3798 (match_operand:SF 2 "general_operand" "f,m")))
3799 (clobber (reg:CC 33))]
3800 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3804 [(set_attr "op_type" "RR,RX")
3805 (set_attr "type" "fmul")
3806 (set_attr "atype" "reg,mem")])
3810 ;;- Divide and modulo instructions.
3814 ; divmoddi4 instruction pattern(s).
3817 (define_expand "divmoddi4"
3818 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3819 (div:DI (match_operand:DI 1 "general_operand" "")
3820 (match_operand:DI 2 "general_operand" "")))
3821 (set (match_operand:DI 3 "general_operand" "")
3822 (mod:DI (match_dup 1) (match_dup 2)))])
3823 (clobber (match_dup 4))]
3827 rtx insn, div_equal, mod_equal, equal;
3829 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
3830 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
3831 equal = gen_rtx_IOR (TImode,
3832 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3833 gen_rtx_ASHIFT (TImode,
3834 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3837 operands[4] = gen_reg_rtx(TImode);
3838 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3839 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3840 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3841 insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
3843 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3845 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3847 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3849 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3851 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3856 (define_insn "divmodtidi3"
3857 [(set (match_operand:TI 0 "register_operand" "=d,d")
3860 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3861 (match_operand:DI 2 "general_operand" "d,m")))
3864 (mod:DI (truncate:DI (match_dup 1))
3871 [(set_attr "op_type" "RRE,RXE")
3872 (set_attr "type" "idiv")
3873 (set_attr "atype" "reg,mem")])
3875 (define_insn "divmodtisi3"
3876 [(set (match_operand:TI 0 "register_operand" "=d,d")
3879 (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
3880 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
3883 (mod:DI (truncate:DI (match_dup 1))
3884 (sign_extend:DI (match_dup 2))))
3890 [(set_attr "op_type" "RRE,RXE")
3891 (set_attr "type" "idiv")
3892 (set_attr "atype" "reg,mem")])
3895 ; udivmoddi4 instruction pattern(s).
3898 (define_expand "udivmoddi4"
3899 [(parallel [(set (match_operand:DI 0 "general_operand" "")
3900 (udiv:DI (match_operand:DI 1 "general_operand" "")
3901 (match_operand:DI 2 "nonimmediate_operand" "")))
3902 (set (match_operand:DI 3 "general_operand" "")
3903 (umod:DI (match_dup 1) (match_dup 2)))])
3904 (clobber (match_dup 4))]
3908 rtx insn, div_equal, mod_equal, equal;
3910 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
3911 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
3912 equal = gen_rtx_IOR (TImode,
3913 gen_rtx_ZERO_EXTEND (TImode, div_equal),
3914 gen_rtx_ASHIFT (TImode,
3915 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
3918 operands[4] = gen_reg_rtx(TImode);
3919 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
3920 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
3921 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
3922 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
3924 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3926 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
3928 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3930 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
3932 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3937 (define_insn "udivmodtidi3"
3938 [(set (match_operand:TI 0 "register_operand" "=d,d")
3939 (ior:TI (zero_extend:TI
3941 (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
3943 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
3947 (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
3953 [(set_attr "op_type" "RRE,RXE")
3954 (set_attr "type" "idiv")
3955 (set_attr "atype" "reg,mem")])
3958 ; divmodsi4 instruction pattern(s).
3961 (define_expand "divmodsi4"
3962 [(parallel [(set (match_operand:SI 0 "general_operand" "")
3963 (div:SI (match_operand:SI 1 "general_operand" "")
3964 (match_operand:SI 2 "nonimmediate_operand" "")))
3965 (set (match_operand:SI 3 "general_operand" "")
3966 (mod:SI (match_dup 1) (match_dup 2)))])
3967 (clobber (match_dup 4))]
3971 rtx insn, div_equal, mod_equal, equal;
3973 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
3974 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
3975 equal = gen_rtx_IOR (DImode,
3976 gen_rtx_ZERO_EXTEND (DImode, div_equal),
3977 gen_rtx_ASHIFT (DImode,
3978 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
3981 operands[4] = gen_reg_rtx(DImode);
3982 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
3983 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
3985 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
3987 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
3989 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
3991 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
3993 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
3998 (define_insn "divmoddisi3"
3999 [(set (match_operand:DI 0 "register_operand" "=d,d")
4000 (ior:DI (zero_extend:DI
4002 (div:DI (match_operand:DI 1 "register_operand" "0,0")
4004 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4008 (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2)))))
4014 [(set_attr "op_type" "RR,RX")
4015 (set_attr "type" "idiv")
4016 (set_attr "atype" "reg,mem")])
4019 ; udivsi3 and umodsi3 instruction pattern(s).
4023 (define_expand "udivsi3"
4024 [(set (match_operand:SI 0 "register_operand" "=d")
4025 (udiv:SI (match_operand:SI 1 "general_operand" "")
4026 (match_operand:SI 2 "general_operand" "")))
4027 (clobber (match_dup 3))]
4031 rtx insn, udiv_equal, umod_equal, equal;
4033 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4034 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4035 equal = gen_rtx_IOR (DImode,
4036 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4037 gen_rtx_ASHIFT (DImode,
4038 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4041 operands[3] = gen_reg_rtx (DImode);
4043 if (CONSTANT_P (operands[2]))
4045 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4047 rtx label1 = gen_label_rtx ();
4049 operands[1] = make_safe_from (operands[1], operands[0]);
4050 emit_move_insn (operands[0], const0_rtx);
4051 emit_insn (gen_cmpsi (operands[1], operands[2]));
4052 emit_jump_insn (gen_bltu (label1));
4053 emit_move_insn (operands[0], const1_rtx);
4054 emit_label (label1);
4058 operands[2] = force_reg (SImode, operands[2]);
4059 operands[2] = make_safe_from (operands[2], operands[0]);
4061 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4062 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4065 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4067 insn = emit_move_insn (operands[0],
4068 gen_lowpart (SImode, operands[3]));
4070 gen_rtx_EXPR_LIST (REG_EQUAL,
4071 udiv_equal, REG_NOTES (insn));
4076 rtx label1 = gen_label_rtx ();
4077 rtx label2 = gen_label_rtx ();
4078 rtx label3 = gen_label_rtx ();
4080 operands[1] = force_reg (SImode, operands[1]);
4081 operands[1] = make_safe_from (operands[1], operands[0]);
4082 operands[2] = force_reg (SImode, operands[2]);
4083 operands[2] = make_safe_from (operands[2], operands[0]);
4085 emit_move_insn (operands[0], const0_rtx);
4086 emit_insn (gen_cmpsi (operands[2], operands[1]));
4087 emit_jump_insn (gen_bgtu (label3));
4088 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4089 emit_jump_insn (gen_blt (label2));
4090 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4091 emit_jump_insn (gen_beq (label1));
4092 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4093 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4096 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4098 insn = emit_move_insn (operands[0],
4099 gen_lowpart (SImode, operands[3]));
4101 gen_rtx_EXPR_LIST (REG_EQUAL,
4102 udiv_equal, REG_NOTES (insn));
4104 emit_label (label1);
4105 emit_move_insn (operands[0], operands[1]);
4107 emit_label (label2);
4108 emit_move_insn (operands[0], const1_rtx);
4109 emit_label (label3);
4111 emit_move_insn (operands[0], operands[0]);
4115 (define_expand "umodsi3"
4116 [(set (match_operand:SI 0 "register_operand" "=d")
4117 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4118 (match_operand:SI 2 "nonimmediate_operand" "")))
4119 (clobber (match_dup 3))]
4123 rtx insn, udiv_equal, umod_equal, equal;
4125 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4126 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4127 equal = gen_rtx_IOR (DImode,
4128 gen_rtx_ZERO_EXTEND (DImode, udiv_equal),
4129 gen_rtx_ASHIFT (DImode,
4130 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4133 operands[3] = gen_reg_rtx (DImode);
4135 if (CONSTANT_P (operands[2]))
4137 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4139 rtx label1 = gen_label_rtx ();
4141 operands[1] = make_safe_from (operands[1], operands[0]);
4142 emit_move_insn (operands[0], operands[1]);
4143 emit_insn (gen_cmpsi (operands[0], operands[2]));
4144 emit_jump_insn (gen_bltu (label1));
4145 emit_insn (gen_abssi2 (operands[0], operands[2]));
4146 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4147 emit_label (label1);
4151 operands[2] = force_reg (SImode, operands[2]);
4152 operands[2] = make_safe_from (operands[2], operands[0]);
4154 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4155 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4158 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4160 insn = emit_move_insn (operands[0],
4161 gen_highpart (SImode, operands[3]));
4163 gen_rtx_EXPR_LIST (REG_EQUAL,
4164 umod_equal, REG_NOTES (insn));
4169 rtx label1 = gen_label_rtx ();
4170 rtx label2 = gen_label_rtx ();
4171 rtx label3 = gen_label_rtx ();
4173 operands[1] = force_reg (SImode, operands[1]);
4174 operands[1] = make_safe_from (operands[1], operands[0]);
4175 operands[2] = force_reg (SImode, operands[2]);
4176 operands[2] = make_safe_from (operands[2], operands[0]);
4178 emit_move_insn(operands[0], operands[1]);
4179 emit_insn (gen_cmpsi (operands[2], operands[1]));
4180 emit_jump_insn (gen_bgtu (label3));
4181 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4182 emit_jump_insn (gen_blt (label2));
4183 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4184 emit_jump_insn (gen_beq (label1));
4185 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4186 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4189 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4191 insn = emit_move_insn (operands[0],
4192 gen_highpart (SImode, operands[3]));
4194 gen_rtx_EXPR_LIST (REG_EQUAL,
4195 umod_equal, REG_NOTES (insn));
4197 emit_label (label1);
4198 emit_move_insn (operands[0], const0_rtx);
4200 emit_label (label2);
4201 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4202 emit_label (label3);
4208 ; divdf3 instruction pattern(s).
4211 (define_expand "divdf3"
4213 [(set (match_operand:DF 0 "register_operand" "=f,f")
4214 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4215 (match_operand:DF 2 "general_operand" "f,m")))
4216 (clobber (reg:CC 33))])]
4220 (define_insn "*divdf3"
4221 [(set (match_operand:DF 0 "register_operand" "=f,f")
4222 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4223 (match_operand:DF 2 "general_operand" "f,m")))
4224 (clobber (reg:CC 33))]
4225 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4229 [(set_attr "op_type" "RRE,RXE")
4230 (set_attr "type" "fdiv")
4231 (set_attr "atype" "reg,mem")])
4233 (define_insn "*divdf3_ibm"
4234 [(set (match_operand:DF 0 "register_operand" "=f,f")
4235 (div:DF (match_operand:DF 1 "register_operand" "0,0")
4236 (match_operand:DF 2 "general_operand" "f,m")))
4237 (clobber (reg:CC 33))]
4238 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4242 [(set_attr "op_type" "RR,RX")
4243 (set_attr "type" "fdiv")
4244 (set_attr "atype" "reg,mem")])
4247 ; divsf3 instruction pattern(s).
4250 (define_expand "divsf3"
4252 [(set (match_operand:SF 0 "register_operand" "=f,f")
4253 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4254 (match_operand:SF 2 "general_operand" "f,m")))
4255 (clobber (reg:CC 33))])]
4259 (define_insn "*divsf3"
4260 [(set (match_operand:SF 0 "register_operand" "=f,f")
4261 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4262 (match_operand:SF 2 "general_operand" "f,m")))
4263 (clobber (reg:CC 33))]
4264 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4268 [(set_attr "op_type" "RRE,RXE")
4269 (set_attr "type" "fdiv")
4270 (set_attr "atype" "reg,mem")])
4272 (define_insn "*divsf3"
4273 [(set (match_operand:SF 0 "register_operand" "=f,f")
4274 (div:SF (match_operand:SF 1 "register_operand" "0,0")
4275 (match_operand:SF 2 "general_operand" "f,m")))
4276 (clobber (reg:CC 33))]
4277 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4281 [(set_attr "op_type" "RR,RX")
4282 (set_attr "type" "fdiv")
4283 (set_attr "atype" "reg,mem")])
4287 ;;- And instructions.
4291 ; anddi3 instruction pattern(s).
4294 (define_insn "*anddi3_cc"
4296 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4297 (match_operand:DI 2 "general_operand" "d,m"))
4299 (set (match_operand:DI 0 "register_operand" "=d,d")
4300 (and:DI (match_dup 1) (match_dup 2)))]
4301 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4305 [(set_attr "op_type" "RRE,RXE")
4306 (set_attr "atype" "reg,mem")])
4308 (define_insn "*anddi3_cconly"
4310 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4311 (match_operand:DI 2 "general_operand" "d,m"))
4313 (clobber (match_scratch:DI 0 "=d,d"))]
4314 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4318 [(set_attr "op_type" "RRE,RXE")
4319 (set_attr "atype" "reg,mem")])
4321 (define_insn "*anddi3_ni"
4322 [(set (match_operand:DI 0 "register_operand" "=d")
4323 (and:DI (match_operand:DI 1 "nonimmediate_operand" "0")
4324 (match_operand:DI 2 "immediate_operand" "n")))
4325 (clobber (reg:CC 33))]
4326 "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
4329 int part = s390_single_hi (operands[2], DImode, -1);
4330 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4334 case 0: return \"nihh\\t%0,%x2\";
4335 case 1: return \"nihl\\t%0,%x2\";
4336 case 2: return \"nilh\\t%0,%x2\";
4337 case 3: return \"nill\\t%0,%x2\";
4341 [(set_attr "op_type" "RI")
4342 (set_attr "atype" "reg")])
4344 (define_insn "anddi3"
4345 [(set (match_operand:DI 0 "register_operand" "=d,d")
4346 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4347 (match_operand:DI 2 "general_operand" "d,m")))
4348 (clobber (reg:CC 33))]
4353 [(set_attr "op_type" "RRE,RXE")
4354 (set_attr "atype" "reg,mem")])
4356 (define_insn "*anddi3_ss"
4357 [(set (match_operand:DI 0 "s_operand" "=Q")
4358 (and:DI (match_dup 0)
4359 (match_operand:DI 1 "s_imm_operand" "Q")))
4360 (clobber (reg:CC 33))]
4362 "nc\\t%O0(8,%R0),%1"
4363 [(set_attr "op_type" "SS")
4364 (set_attr "atype" "mem")])
4366 (define_insn "*anddi3_ss_inv"
4367 [(set (match_operand:DI 0 "s_operand" "=Q")
4368 (and:DI (match_operand:DI 1 "s_imm_operand" "Q")
4370 (clobber (reg:CC 33))]
4372 "nc\\t%O0(8,%R0),%1"
4373 [(set_attr "op_type" "SS")
4374 (set_attr "atype" "mem")])
4377 ; andsi3 instruction pattern(s).
4380 (define_insn "*andsi3_cc"
4382 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4383 (match_operand:SI 2 "general_operand" "d,m"))
4385 (set (match_operand:SI 0 "register_operand" "=d,d")
4386 (and:SI (match_dup 1) (match_dup 2)))]
4387 "s390_match_ccmode(insn, CCTmode)"
4391 [(set_attr "op_type" "RR,RX")
4392 (set_attr "atype" "reg,mem")])
4394 (define_insn "*andsi3_cconly"
4396 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4397 (match_operand:SI 2 "general_operand" "d,m"))
4399 (clobber (match_scratch:SI 0 "=d,d"))]
4400 "s390_match_ccmode(insn, CCTmode)"
4404 [(set_attr "op_type" "RR,RX")
4405 (set_attr "atype" "reg,mem")])
4407 (define_insn "*andsi3_ni"
4408 [(set (match_operand:SI 0 "register_operand" "=d")
4409 (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
4410 (match_operand:SI 2 "immediate_operand" "n")))
4411 (clobber (reg:CC 33))]
4412 "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
4415 int part = s390_single_hi (operands[2], SImode, -1);
4416 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4420 case 0: return \"nilh\\t%0,%x2\";
4421 case 1: return \"nill\\t%0,%x2\";
4425 [(set_attr "op_type" "RI")
4426 (set_attr "atype" "reg")])
4428 (define_insn "andsi3"
4429 [(set (match_operand:SI 0 "register_operand" "=d,d")
4430 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4431 (match_operand:SI 2 "general_operand" "d,m")))
4432 (clobber (reg:CC 33))]
4437 [(set_attr "op_type" "RR,RX")
4438 (set_attr "atype" "reg,mem")])
4440 (define_insn "*andsi3_ss"
4441 [(set (match_operand:SI 0 "s_operand" "=Q")
4442 (and:SI (match_dup 0)
4443 (match_operand:SI 1 "s_imm_operand" "Q")))
4444 (clobber (reg:CC 33))]
4446 "nc\\t%O0(4,%R0),%1"
4447 [(set_attr "op_type" "SS")
4448 (set_attr "atype" "mem")])
4450 (define_insn "*andsi3_ss_inv"
4451 [(set (match_operand:SI 0 "s_operand" "=Q")
4452 (and:SI (match_operand:SI 1 "s_imm_operand" "Q")
4454 (clobber (reg:CC 33))]
4456 "nc\\t%O0(4,%R0),%1"
4457 [(set_attr "op_type" "SS")
4458 (set_attr "atype" "mem")])
4461 ; andhi3 instruction pattern(s).
4464 (define_insn "*andhi3_ni"
4465 [(set (match_operand:HI 0 "register_operand" "=d,d")
4466 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
4467 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4468 (clobber (reg:CC 33))]
4473 [(set_attr "op_type" "RR,RI")
4474 (set_attr "atype" "reg")])
4476 (define_insn "andhi3"
4477 [(set (match_operand:HI 0 "register_operand" "=d")
4478 (and:HI (match_operand:HI 1 "register_operand" "%0")
4479 (match_operand:HI 2 "nonmemory_operand" "d")))
4480 (clobber (reg:CC 33))]
4483 [(set_attr "op_type" "RR")
4484 (set_attr "atype" "reg")])
4486 (define_insn "*andhi3_ss"
4487 [(set (match_operand:HI 0 "s_operand" "=Q")
4488 (and:HI (match_dup 0)
4489 (match_operand:HI 1 "s_imm_operand" "Q")))
4490 (clobber (reg:CC 33))]
4492 "nc\\t%O0(2,%R0),%1"
4493 [(set_attr "op_type" "SS")
4494 (set_attr "atype" "mem")])
4496 (define_insn "*andhi3_ss_inv"
4497 [(set (match_operand:HI 0 "s_operand" "=Q")
4498 (and:HI (match_operand:HI 1 "s_imm_operand" "Q")
4500 (clobber (reg:CC 33))]
4502 "nc\\t%O0(2,%R0),%1"
4503 [(set_attr "op_type" "SS")
4504 (set_attr "atype" "mem")])
4507 ; andqi3 instruction pattern(s).
4510 (define_insn "*andqi3_ni"
4511 [(set (match_operand:QI 0 "register_operand" "=d,d")
4512 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
4513 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4514 (clobber (reg:CC 33))]
4519 [(set_attr "op_type" "RR,RI")
4520 (set_attr "atype" "reg")])
4522 (define_insn "andqi3"
4523 [(set (match_operand:QI 0 "register_operand" "=d")
4524 (and:QI (match_operand:QI 1 "register_operand" "%0")
4525 (match_operand:QI 2 "nonmemory_operand" "d")))
4526 (clobber (reg:CC 33))]
4529 [(set_attr "op_type" "RR")
4530 (set_attr "atype" "reg")])
4532 (define_insn "*andqi3_ss"
4533 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4534 (and:QI (match_dup 0)
4535 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4536 (clobber (reg:CC 33))]
4541 [(set_attr "op_type" "SI,SS")
4542 (set_attr "atype" "mem")])
4544 (define_insn "*andqi3_ss_inv"
4545 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4546 (and:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4548 (clobber (reg:CC 33))]
4553 [(set_attr "op_type" "SI,SS")
4554 (set_attr "atype" "mem")])
4558 ;;- Bit set (inclusive or) instructions.
4562 ; iordi3 instruction pattern(s).
4565 (define_insn "*iordi3_cc"
4567 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4568 (match_operand:DI 2 "general_operand" "d,m"))
4570 (set (match_operand:DI 0 "register_operand" "=d,d")
4571 (ior:DI (match_dup 1) (match_dup 2)))]
4572 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4576 [(set_attr "op_type" "RRE,RXE")
4577 (set_attr "atype" "reg,mem")])
4579 (define_insn "*iordi3_cconly"
4581 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4582 (match_operand:DI 2 "general_operand" "d,m"))
4584 (clobber (match_scratch:DI 0 "=d,d"))]
4585 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4589 [(set_attr "op_type" "RRE,RXE")
4590 (set_attr "atype" "reg,mem")])
4592 (define_insn "*iordi3_oi"
4593 [(set (match_operand:DI 0 "register_operand" "=d")
4594 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4595 (match_operand:DI 2 "immediate_operand" "n")))
4596 (clobber (reg:CC 33))]
4597 "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
4600 int part = s390_single_hi (operands[2], DImode, 0);
4601 operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
4605 case 0: return \"oihh\\t%0,%x2\";
4606 case 1: return \"oihl\\t%0,%x2\";
4607 case 2: return \"oilh\\t%0,%x2\";
4608 case 3: return \"oill\\t%0,%x2\";
4612 [(set_attr "op_type" "RI")
4613 (set_attr "atype" "reg")])
4615 (define_insn "iordi3"
4616 [(set (match_operand:DI 0 "register_operand" "=d,d")
4617 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4618 (match_operand:DI 2 "general_operand" "d,m")))
4619 (clobber (reg:CC 33))]
4624 [(set_attr "op_type" "RRE,RXE")
4625 (set_attr "atype" "reg,mem")])
4627 (define_insn "*iordi3_ss"
4628 [(set (match_operand:DI 0 "s_operand" "=Q")
4629 (ior:DI (match_dup 0)
4630 (match_operand:DI 1 "s_imm_operand" "Q")))
4631 (clobber (reg:CC 33))]
4633 "oc\\t%O0(8,%R0),%1"
4634 [(set_attr "op_type" "SS")
4635 (set_attr "atype" "mem")])
4637 (define_insn "*iordi3_ss_inv"
4638 [(set (match_operand:DI 0 "s_operand" "=Q")
4639 (ior:DI (match_operand:DI 1 "s_imm_operand" "Q")
4641 (clobber (reg:CC 33))]
4643 "oc\\t%O0(8,%R0),%1"
4644 [(set_attr "op_type" "SS")
4645 (set_attr "atype" "mem")])
4648 ; iorsi3 instruction pattern(s).
4651 (define_insn "*iorsi3_cc"
4653 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4654 (match_operand:SI 2 "general_operand" "d,m"))
4656 (set (match_operand:SI 0 "register_operand" "=d,d")
4657 (ior:SI (match_dup 1) (match_dup 2)))]
4658 "s390_match_ccmode(insn, CCTmode)"
4662 [(set_attr "op_type" "RR,RX")
4663 (set_attr "atype" "reg,mem")])
4665 (define_insn "*iorsi3_cconly"
4667 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4668 (match_operand:SI 2 "general_operand" "d,m"))
4670 (clobber (match_scratch:SI 0 "=d,d"))]
4671 "s390_match_ccmode(insn, CCTmode)"
4675 [(set_attr "op_type" "RR,RX")
4676 (set_attr "atype" "reg,mem")])
4678 (define_insn "*iorsi3_oi"
4679 [(set (match_operand:SI 0 "register_operand" "=d")
4680 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
4681 (match_operand:SI 2 "immediate_operand" "n")))
4682 (clobber (reg:CC 33))]
4683 "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
4686 int part = s390_single_hi (operands[2], SImode, 0);
4687 operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
4691 case 0: return \"oilh\\t%0,%x2\";
4692 case 1: return \"oill\\t%0,%x2\";
4696 [(set_attr "op_type" "RI")
4697 (set_attr "atype" "reg")])
4699 (define_insn "iorsi3"
4700 [(set (match_operand:SI 0 "register_operand" "=d,d")
4701 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4702 (match_operand:SI 2 "general_operand" "d,m")))
4703 (clobber (reg:CC 33))]
4708 [(set_attr "op_type" "RR,RX")
4709 (set_attr "atype" "reg,mem")])
4711 (define_insn "*iorsi3_ss"
4712 [(set (match_operand:SI 0 "s_operand" "=Q")
4713 (ior:SI (match_dup 0)
4714 (match_operand:SI 1 "s_imm_operand" "Q")))
4715 (clobber (reg:CC 33))]
4717 "oc\\t%O0(4,%R0),%1"
4718 [(set_attr "op_type" "SS")
4719 (set_attr "atype" "mem")])
4721 (define_insn "*iorsi3_ss_inv"
4722 [(set (match_operand:SI 0 "s_operand" "=Q")
4723 (ior:SI (match_operand:SI 1 "s_imm_operand" "Q")
4725 (clobber (reg:CC 33))]
4727 "oc\\t%O0(4,%R0),%1"
4728 [(set_attr "op_type" "SS")
4729 (set_attr "atype" "mem")])
4732 ; iorhi3 instruction pattern(s).
4735 (define_insn "*iorhi3_oi"
4736 [(set (match_operand:HI 0 "register_operand" "=d,d")
4737 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
4738 (match_operand:HI 2 "nonmemory_operand" "d,n")))
4739 (clobber (reg:CC 33))]
4744 [(set_attr "op_type" "RR,RI")
4745 (set_attr "atype" "reg")])
4747 (define_insn "iorhi3"
4748 [(set (match_operand:HI 0 "register_operand" "=d")
4749 (ior:HI (match_operand:HI 1 "register_operand" "%0")
4750 (match_operand:HI 2 "nonmemory_operand" "d")))
4751 (clobber (reg:CC 33))]
4754 [(set_attr "op_type" "RR")
4755 (set_attr "atype" "reg")])
4757 (define_insn "*iorhi3_ss"
4758 [(set (match_operand:HI 0 "s_operand" "=Q")
4759 (ior:HI (match_dup 0)
4760 (match_operand:HI 1 "s_imm_operand" "Q")))
4761 (clobber (reg:CC 33))]
4763 "oc\\t%O0(2,%R0),%1"
4764 [(set_attr "op_type" "SS")
4765 (set_attr "atype" "mem")])
4767 (define_insn "*iorhi3_ss_inv"
4768 [(set (match_operand:HI 0 "s_operand" "=Q")
4769 (ior:HI (match_operand:HI 1 "s_imm_operand" "Q")
4771 (clobber (reg:CC 33))]
4773 "oc\\t%O0(2,%R0),%1"
4774 [(set_attr "op_type" "SS")
4775 (set_attr "atype" "mem")])
4778 ; iorqi3 instruction pattern(s).
4781 (define_insn "*iorqi3_oi"
4782 [(set (match_operand:QI 0 "register_operand" "=d,d")
4783 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
4784 (match_operand:QI 2 "nonmemory_operand" "d,n")))
4785 (clobber (reg:CC 33))]
4790 [(set_attr "op_type" "RR,RI")
4791 (set_attr "atype" "reg")])
4793 (define_insn "iorqi3"
4794 [(set (match_operand:QI 0 "register_operand" "=d")
4795 (ior:QI (match_operand:QI 1 "register_operand" "%0")
4796 (match_operand:QI 2 "nonmemory_operand" "d")))
4797 (clobber (reg:CC 33))]
4800 [(set_attr "op_type" "RR")
4801 (set_attr "atype" "reg")])
4803 (define_insn "*iorqi3_ss"
4804 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4805 (ior:QI (match_dup 0)
4806 (match_operand:QI 1 "s_imm_operand" "n,Q")))
4807 (clobber (reg:CC 33))]
4812 [(set_attr "op_type" "SI,SS")
4813 (set_attr "atype" "reg,mem")])
4815 (define_insn "*iorqi3_ss_inv"
4816 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
4817 (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
4819 (clobber (reg:CC 33))]
4824 [(set_attr "op_type" "SI,SS")
4825 (set_attr "atype" "reg,mem")])
4829 ;;- Xor instructions.
4833 ; xordi3 instruction pattern(s).
4836 (define_insn "*xordi3_cc"
4838 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4839 (match_operand:DI 2 "general_operand" "d,m"))
4841 (set (match_operand:DI 0 "register_operand" "=d,d")
4842 (xor:DI (match_dup 1) (match_dup 2)))]
4843 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4847 [(set_attr "op_type" "RRE,RXE")
4848 (set_attr "atype" "reg,mem")])
4850 (define_insn "*xordi3_cconly"
4852 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4853 (match_operand:DI 2 "general_operand" "d,m"))
4855 (clobber (match_scratch:DI 0 "=d,d"))]
4856 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4860 [(set_attr "op_type" "RRE,RXE")
4861 (set_attr "atype" "reg,mem")])
4863 (define_insn "xordi3"
4864 [(set (match_operand:DI 0 "register_operand" "=d,d")
4865 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4866 (match_operand:DI 2 "general_operand" "d,m")))
4867 (clobber (reg:CC 33))]
4872 [(set_attr "op_type" "RRE,RXE")
4873 (set_attr "atype" "reg,mem")])
4875 (define_insn "*xordi3_ss"
4876 [(set (match_operand:DI 0 "s_operand" "=Q")
4877 (xor:DI (match_dup 0)
4878 (match_operand:DI 1 "s_imm_operand" "Q")))
4879 (clobber (reg:CC 33))]
4881 "xc\\t%O0(8,%R0),%1"
4882 [(set_attr "op_type" "SS")
4883 (set_attr "atype" "mem")])
4885 (define_insn "*xordi3_ss_inv"
4886 [(set (match_operand:DI 0 "s_operand" "=Q")
4887 (xor:DI (match_operand:DI 1 "s_imm_operand" "Q")
4889 (clobber (reg:CC 33))]
4891 "xc\\t%O0(8,%R0),%1"
4892 [(set_attr "op_type" "SS")
4893 (set_attr "atype" "mem")])
4896 ; xorsi3 instruction pattern(s).
4899 (define_insn "*xorsi3_cc"
4901 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4902 (match_operand:SI 2 "general_operand" "d,m"))
4904 (set (match_operand:SI 0 "register_operand" "=d,d")
4905 (xor:SI (match_dup 1) (match_dup 2)))]
4906 "s390_match_ccmode(insn, CCTmode)"
4910 [(set_attr "op_type" "RR,RX")
4911 (set_attr "atype" "reg,mem")])
4913 (define_insn "*xorsi3_cconly"
4915 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4916 (match_operand:SI 2 "general_operand" "d,m"))
4918 (clobber (match_scratch:SI 0 "=d,d"))]
4919 "s390_match_ccmode(insn, CCTmode)"
4923 [(set_attr "op_type" "RR,RX")
4924 (set_attr "atype" "reg,mem")])
4926 (define_insn "xorsi3"
4927 [(set (match_operand:SI 0 "register_operand" "=d,d")
4928 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4929 (match_operand:SI 2 "general_operand" "d,m")))
4930 (clobber (reg:CC 33))]
4935 [(set_attr "op_type" "RR,RX")
4936 (set_attr "atype" "reg,mem")])
4938 (define_insn "*xorsi3_ss"
4939 [(set (match_operand:SI 0 "s_operand" "=Q")
4940 (xor:SI (match_dup 0)
4941 (match_operand:SI 1 "s_imm_operand" "Q")))
4942 (clobber (reg:CC 33))]
4944 "xc\\t%O0(4,%R0),%1"
4945 [(set_attr "op_type" "SS")
4946 (set_attr "atype" "mem")])
4948 (define_insn "*xorsi3_ss_inv"
4949 [(set (match_operand:SI 0 "s_operand" "=Q")
4950 (xor:SI (match_operand:SI 1 "s_imm_operand" "Q")
4952 (clobber (reg:CC 33))]
4954 "xc\\t%O0(4,%R0),%1"
4955 [(set_attr "op_type" "SS")
4956 (set_attr "atype" "mem")])
4959 ; xorhi3 instruction pattern(s).
4962 (define_insn "xorhi3"
4963 [(set (match_operand:HI 0 "register_operand" "=d")
4964 (xor:HI (match_operand:HI 1 "register_operand" "%0")
4965 (match_operand:HI 2 "nonmemory_operand" "d")))
4966 (clobber (reg:CC 33))]
4969 [(set_attr "op_type" "RR")
4970 (set_attr "atype" "reg")])
4972 (define_insn "*xorhi3_ss"
4973 [(set (match_operand:HI 0 "s_operand" "=Q")
4974 (xor:HI (match_dup 0)
4975 (match_operand:HI 1 "s_imm_operand" "Q")))
4976 (clobber (reg:CC 33))]
4978 "xc\\t%O0(2,%R0),%1"
4979 [(set_attr "op_type" "SS")
4980 (set_attr "atype" "mem")])
4982 (define_insn "*xorhi3_ss_inv"
4983 [(set (match_operand:HI 0 "s_operand" "=Q")
4984 (xor:HI (match_operand:HI 1 "s_imm_operand" "Q")
4986 (clobber (reg:CC 33))]
4988 "xc\\t%O0(2,%R0),%1"
4989 [(set_attr "op_type" "SS")
4990 (set_attr "atype" "mem")])
4993 ; xorqi3 instruction pattern(s).
4996 (define_insn "xorqi3"
4997 [(set (match_operand:QI 0 "register_operand" "=d")
4998 (xor:QI (match_operand:QI 1 "register_operand" "%0")
4999 (match_operand:QI 2 "nonmemory_operand" "d")))
5000 (clobber (reg:CC 33))]
5003 [(set_attr "op_type" "RR")
5004 (set_attr "atype" "reg")])
5006 (define_insn "*xorqi3_ss"
5007 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
5008 (xor:QI (match_dup 0)
5009 (match_operand:QI 1 "s_imm_operand" "n,Q")))
5010 (clobber (reg:CC 33))]
5015 [(set_attr "op_type" "SI,SS")
5016 (set_attr "atype" "mem")])
5018 (define_insn "*xorqi3_ss_inv"
5019 [(set (match_operand:QI 0 "s_operand" "=Q,Q")
5020 (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q")
5022 (clobber (reg:CC 33))]
5027 [(set_attr "op_type" "SI,SS")
5028 (set_attr "atype" "mem")])
5032 ;;- Negate instructions.
5036 ; negdi2 instruction pattern(s).
5039 (define_expand "negdi2"
5041 [(set (match_operand:DI 0 "register_operand" "=d")
5042 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5043 (clobber (reg:CC 33))])]
5047 (define_insn "*negdi2_64"
5048 [(set (match_operand:DI 0 "register_operand" "=d")
5049 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5050 (clobber (reg:CC 33))]
5053 [(set_attr "op_type" "RR")])
5055 (define_insn "*negdi2_31"
5056 [(set (match_operand:DI 0 "register_operand" "=d")
5057 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5058 (clobber (reg:CC 33))]
5063 xop[0] = gen_label_rtx ();
5064 output_asm_insn (\"lcr\\t%0,%1\", operands);
5065 output_asm_insn (\"lcr\\t%N0,%N1\", operands);
5066 output_asm_insn (\"je\\t%l0\", xop);
5067 output_asm_insn (\"bctr\\t%0,0\", operands);
5068 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
5069 CODE_LABEL_NUMBER (xop[0]));
5072 [(set_attr "op_type" "NN")
5073 (set_attr "type" "other")
5074 (set_attr "length" "10")])
5077 ; negsi2 instruction pattern(s).
5080 (define_insn "negsi2"
5081 [(set (match_operand:SI 0 "register_operand" "=d")
5082 (neg:SI (match_operand:SI 1 "register_operand" "d")))
5083 (clobber (reg:CC 33))]
5086 [(set_attr "op_type" "RR")])
5089 ; negdf2 instruction pattern(s).
5092 (define_expand "negdf2"
5094 [(set (match_operand:DF 0 "register_operand" "=f")
5095 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5096 (clobber (reg:CC 33))])]
5100 (define_insn "*negdf2"
5101 [(set (match_operand:DF 0 "register_operand" "=f")
5102 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5103 (clobber (reg:CC 33))]
5104 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5106 [(set_attr "op_type" "RRE")])
5108 (define_insn "*negdf2_ibm"
5109 [(set (match_operand:DF 0 "register_operand" "=f")
5110 (neg:DF (match_operand:DF 1 "register_operand" "f")))
5111 (clobber (reg:CC 33))]
5112 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5114 [(set_attr "op_type" "RR")])
5117 ; negsf2 instruction pattern(s).
5120 (define_expand "negsf2"
5122 [(set (match_operand:SF 0 "register_operand" "=f")
5123 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5124 (clobber (reg:CC 33))])]
5128 (define_insn "*negsf2"
5129 [(set (match_operand:SF 0 "register_operand" "=f")
5130 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5131 (clobber (reg:CC 33))]
5132 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5134 [(set_attr "op_type" "RRE")])
5136 (define_insn "*negsf2"
5137 [(set (match_operand:SF 0 "register_operand" "=f")
5138 (neg:SF (match_operand:SF 1 "register_operand" "f")))
5139 (clobber (reg:CC 33))]
5140 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5142 [(set_attr "op_type" "RR")])
5146 ;;- Absolute value instructions.
5150 ; absdi2 instruction pattern(s).
5153 (define_insn "absdi2"
5154 [(set (match_operand:DI 0 "register_operand" "=d")
5155 (abs:DI (match_operand:DI 1 "register_operand" "d")))
5156 (clobber (reg:CC 33))]
5159 [(set_attr "op_type" "RRE")])
5162 ; abssi2 instruction pattern(s).
5165 (define_insn "abssi2"
5166 [(set (match_operand:SI 0 "register_operand" "=d")
5167 (abs:SI (match_operand:SI 1 "register_operand" "d")))
5168 (clobber (reg:CC 33))]
5171 [(set_attr "op_type" "RR")])
5174 ; absdf2 instruction pattern(s).
5177 (define_expand "absdf2"
5179 [(set (match_operand:DF 0 "register_operand" "=f")
5180 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5181 (clobber (reg:CC 33))])]
5185 (define_insn "*absdf2"
5186 [(set (match_operand:DF 0 "register_operand" "=f")
5187 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5188 (clobber (reg:CC 33))]
5189 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5191 [(set_attr "op_type" "RRE")])
5193 (define_insn "*absdf2_ibm"
5194 [(set (match_operand:DF 0 "register_operand" "=f")
5195 (abs:DF (match_operand:DF 1 "register_operand" "f")))
5196 (clobber (reg:CC 33))]
5197 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5199 [(set_attr "op_type" "RR")])
5202 ; abssf2 instruction pattern(s).
5205 (define_expand "abssf2"
5207 [(set (match_operand:SF 0 "register_operand" "=f")
5208 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5209 (clobber (reg:CC 33))])]
5213 (define_insn "*abssf2"
5214 [(set (match_operand:SF 0 "register_operand" "=f")
5215 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5216 (clobber (reg:CC 33))]
5217 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5219 [(set_attr "op_type" "RRE")])
5221 (define_insn "*abssf2_ibm"
5222 [(set (match_operand:SF 0 "register_operand" "=f")
5223 (abs:SF (match_operand:SF 1 "register_operand" "f")))
5224 (clobber (reg:CC 33))]
5225 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5227 [(set_attr "op_type" "RR")])
5230 ;;- Square root instructions.
5234 ; sqrtdf2 instruction pattern(s).
5237 (define_insn "sqrtdf2"
5238 [(set (match_operand:DF 0 "register_operand" "=f,f")
5239 (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))]
5240 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5244 [(set_attr "op_type" "RRE,RSE")])
5247 ; sqrtsf2 instruction pattern(s).
5250 (define_insn "sqrtsf2"
5251 [(set (match_operand:SF 0 "register_operand" "=f,f")
5252 (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))]
5253 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5257 [(set_attr "op_type" "RRE,RSE")])
5260 ;;- One complement instructions.
5264 ; one_cmpldi2 instruction pattern(s).
5267 (define_expand "one_cmpldi2"
5269 [(set (match_operand:DI 0 "register_operand" "")
5270 (xor:DI (match_operand:DI 1 "register_operand" "")
5272 (clobber (reg:CC 33))])]
5277 ; one_cmplsi2 instruction pattern(s).
5280 (define_expand "one_cmplsi2"
5282 [(set (match_operand:SI 0 "register_operand" "")
5283 (xor:SI (match_operand:SI 1 "register_operand" "")
5285 (clobber (reg:CC 33))])]
5290 ; one_cmplhi2 instruction pattern(s).
5293 (define_expand "one_cmplhi2"
5295 [(set (match_operand:HI 0 "register_operand" "")
5296 (xor:HI (match_operand:HI 1 "register_operand" "")
5298 (clobber (reg:CC 33))])]
5303 ; one_cmplqi2 instruction pattern(s).
5306 (define_expand "one_cmplqi2"
5308 [(set (match_operand:QI 0 "register_operand" "")
5309 (xor:QI (match_operand:QI 1 "register_operand" "")
5311 (clobber (reg:CC 33))])]
5317 ;;- Rotate instructions.
5321 ; rotldi3 instruction pattern(s).
5324 (define_insn "rotldi3"
5325 [(set (match_operand:DI 0 "register_operand" "=d,d")
5326 (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
5327 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5332 [(set_attr "op_type" "RSE")])
5335 ; rotlsi3 instruction pattern(s).
5338 (define_insn "rotlsi3"
5339 [(set (match_operand:SI 0 "register_operand" "=d,d")
5340 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
5341 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5346 [(set_attr "op_type" "RSE")])
5350 ;;- Arithmetic shift instructions.
5354 ; ashldi3 instruction pattern(s).
5357 (define_expand "ashldi3"
5358 [(set (match_operand:DI 0 "register_operand" "")
5359 (ashift:DI (match_operand:DI 1 "register_operand" "")
5360 (match_operand:SI 2 "nonmemory_operand" "")))]
5364 (define_insn "*ashldi3_31"
5365 [(set (match_operand:DI 0 "register_operand" "=d,d")
5366 (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
5367 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5372 [(set_attr "op_type" "RS")])
5374 (define_insn "*ashldi3_64"
5375 [(set (match_operand:DI 0 "register_operand" "=d,d")
5376 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
5377 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5382 [(set_attr "op_type" "RSE")])
5385 ; ashrdi3 instruction pattern(s).
5388 (define_expand "ashrdi3"
5390 [(set (match_operand:DI 0 "register_operand" "")
5391 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5392 (match_operand:SI 2 "nonmemory_operand" "")))
5393 (clobber (reg:CC 33))])]
5397 (define_insn "*ashrdi3_cc_31"
5399 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5400 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5402 (set (match_operand:DI 0 "register_operand" "=d,d")
5403 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5404 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5408 [(set_attr "op_type" "RS")])
5410 (define_insn "*ashrdi3_cconly_31"
5412 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5413 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5415 (clobber (match_scratch:DI 0 "=d,d"))]
5416 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
5420 [(set_attr "op_type" "RS")])
5422 (define_insn "*ashrdi3_31"
5423 [(set (match_operand:DI 0 "register_operand" "=d,d")
5424 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5425 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5426 (clobber (reg:CC 33))]
5431 [(set_attr "op_type" "RS")])
5433 (define_insn "*ashrdi3_cc_64"
5435 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5436 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5438 (set (match_operand:DI 0 "register_operand" "=d,d")
5439 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
5440 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5444 [(set_attr "op_type" "RSE")])
5446 (define_insn "*ashrdi3_cconly_64"
5448 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5449 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5451 (clobber (match_scratch:DI 0 "=d,d"))]
5452 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
5456 [(set_attr "op_type" "RSE")])
5458 (define_insn "*ashrdi3_64"
5459 [(set (match_operand:DI 0 "register_operand" "=d,d")
5460 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5461 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5462 (clobber (reg:CC 33))]
5467 [(set_attr "op_type" "RSE")])
5470 ; ashlsi3 instruction pattern(s).
5473 (define_insn "ashlsi3"
5474 [(set (match_operand:SI 0 "register_operand" "=d,d")
5475 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
5476 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5481 [(set_attr "op_type" "RS")])
5484 ; ashrsi3 instruction pattern(s).
5487 (define_insn "*ashrsi3_cc"
5489 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5490 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5492 (set (match_operand:SI 0 "register_operand" "=d,d")
5493 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5494 "s390_match_ccmode(insn, CCSmode)"
5498 [(set_attr "op_type" "RS")])
5500 (define_insn "*ashrsi3_cconly"
5502 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5503 (match_operand:SI 2 "nonmemory_operand" "J,a"))
5505 (clobber (match_scratch:SI 0 "=d,d"))]
5506 "s390_match_ccmode(insn, CCSmode)"
5510 [(set_attr "op_type" "RS")])
5512 (define_insn "ashrsi3"
5513 [(set (match_operand:SI 0 "register_operand" "=d,d")
5514 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5515 (match_operand:SI 2 "nonmemory_operand" "J,a")))
5516 (clobber (reg:CC 33))]
5521 [(set_attr "op_type" "RS")])
5525 ;;- logical shift instructions.
5529 ; lshrdi3 instruction pattern(s).
5532 (define_expand "lshrdi3"
5533 [(set (match_operand:DI 0 "register_operand" "")
5534 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5535 (match_operand:SI 2 "nonmemory_operand" "")))]
5539 (define_insn "*lshrdi3_31"
5540 [(set (match_operand:DI 0 "register_operand" "=d,d")
5541 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5542 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5547 [(set_attr "op_type" "RS,RS")])
5549 (define_insn "*lshrdi3_64"
5550 [(set (match_operand:DI 0 "register_operand" "=d,d")
5551 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
5552 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5557 [(set_attr "op_type" "RSE,RSE")])
5560 ; lshrsi3 instruction pattern(s).
5563 (define_insn "lshrsi3"
5564 [(set (match_operand:SI 0 "register_operand" "=d,d")
5565 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
5566 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
5571 [(set_attr "op_type" "RS")])
5575 ;; Branch instruction patterns.
5578 (define_expand "beq"
5579 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5581 (if_then_else (eq (reg:CCZ 33) (const_int 0))
5582 (label_ref (match_operand 0 "" ""))
5585 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5587 (define_expand "bne"
5588 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
5590 (if_then_else (ne (reg:CCZ 33) (const_int 0))
5591 (label_ref (match_operand 0 "" ""))
5594 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5596 (define_expand "bgt"
5597 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5599 (if_then_else (gt (reg:CCS 33) (const_int 0))
5600 (label_ref (match_operand 0 "" ""))
5603 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5605 (define_expand "bgtu"
5606 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5608 (if_then_else (gtu (reg:CCU 33) (const_int 0))
5609 (label_ref (match_operand 0 "" ""))
5612 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5614 (define_expand "blt"
5615 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5617 (if_then_else (lt (reg:CCS 33) (const_int 0))
5618 (label_ref (match_operand 0 "" ""))
5621 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5623 (define_expand "bltu"
5624 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5626 (if_then_else (ltu (reg:CCU 33) (const_int 0))
5627 (label_ref (match_operand 0 "" ""))
5630 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5632 (define_expand "bge"
5633 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5635 (if_then_else (ge (reg:CCS 33) (const_int 0))
5636 (label_ref (match_operand 0 "" ""))
5639 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5641 (define_expand "bgeu"
5642 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5644 (if_then_else (geu (reg:CCU 33) (const_int 0))
5645 (label_ref (match_operand 0 "" ""))
5648 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5650 (define_expand "ble"
5651 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5653 (if_then_else (le (reg:CCS 33) (const_int 0))
5654 (label_ref (match_operand 0 "" ""))
5657 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5659 (define_expand "bleu"
5660 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5662 (if_then_else (leu (reg:CCU 33) (const_int 0))
5663 (label_ref (match_operand 0 "" ""))
5666 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5668 (define_expand "bunordered"
5669 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5671 (if_then_else (unordered (reg:CCS 33) (const_int 0))
5672 (label_ref (match_operand 0 "" ""))
5675 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5677 (define_expand "bordered"
5678 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5680 (if_then_else (ordered (reg:CCS 33) (const_int 0))
5681 (label_ref (match_operand 0 "" ""))
5684 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5686 (define_expand "buneq"
5687 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5689 (if_then_else (uneq (reg:CCS 33) (const_int 0))
5690 (label_ref (match_operand 0 "" ""))
5693 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5695 (define_expand "bungt"
5696 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5698 (if_then_else (ungt (reg:CCS 33) (const_int 0))
5699 (label_ref (match_operand 0 "" ""))
5702 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5704 (define_expand "bunlt"
5705 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5707 (if_then_else (unlt (reg:CCS 33) (const_int 0))
5708 (label_ref (match_operand 0 "" ""))
5711 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5713 (define_expand "bunge"
5714 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5716 (if_then_else (unge (reg:CCS 33) (const_int 0))
5717 (label_ref (match_operand 0 "" ""))
5720 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5722 (define_expand "bunle"
5723 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5725 (if_then_else (unle (reg:CCS 33) (const_int 0))
5726 (label_ref (match_operand 0 "" ""))
5729 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5731 (define_expand "bltgt"
5732 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5734 (if_then_else (ltgt (reg:CCS 33) (const_int 0))
5735 (label_ref (match_operand 0 "" ""))
5738 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5742 ;;- Conditional jump instructions.
5745 (define_insn "cjump"
5748 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5749 (label_ref (match_operand 0 "" ""))
5754 if (get_attr_length (insn) == 4)
5755 return \"j%C1\\t%l0\";
5756 else if (TARGET_64BIT)
5757 return \"jg%C1\\t%l0\";
5761 [(set_attr "op_type" "RI")
5762 (set (attr "length")
5763 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5765 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5767 (eq (symbol_ref "flag_pic") (const_int 0))
5768 (const_int 6)] (const_int 8)))])
5770 (define_insn "*cjump_long"
5773 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5774 (match_operand 0 "address_operand" "p")
5779 if (get_attr_op_type (insn) == OP_TYPE_RR)
5780 return \"b%C1r\\t%0\";
5782 return \"b%C1\\t%a0\";
5784 [(set (attr "op_type")
5785 (if_then_else (match_operand 0 "register_operand" "")
5786 (const_string "RR") (const_string "RX")))
5787 (set_attr "atype" "mem")])
5791 ;;- Negated conditional jump instructions.
5794 (define_insn "icjump"
5797 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5799 (label_ref (match_operand 0 "" ""))))]
5803 if (get_attr_length (insn) == 4)
5804 return \"j%D1\\t%l0\";
5805 else if (TARGET_64BIT)
5806 return \"jg%D1\\t%l0\";
5810 [(set_attr "op_type" "RI")
5811 (set (attr "length")
5812 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5814 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5816 (eq (symbol_ref "flag_pic") (const_int 0))
5817 (const_int 6)] (const_int 8)))])
5819 (define_insn "*icjump_long"
5822 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5824 (match_operand 0 "address_operand" "p")))]
5828 if (get_attr_op_type (insn) == OP_TYPE_RR)
5829 return \"b%D1r\\t%0\";
5831 return \"b%D1\\t%a0\";
5833 [(set (attr "op_type")
5834 (if_then_else (match_operand 0 "register_operand" "")
5835 (const_string "RR") (const_string "RX")))
5836 (set_attr "atype" "mem")])
5839 ;;- Trap instructions.
5843 [(trap_if (const_int 1) (const_int 0))]
5846 [(set_attr "op_type" "RX")])
5848 (define_expand "conditional_trap"
5849 [(set (match_dup 2) (match_dup 3))
5850 (trap_if (match_operator 0 "comparison_operator"
5851 [(match_dup 2) (const_int 0)])
5852 (match_operand:SI 1 "general_operand" ""))]
5856 enum machine_mode ccmode;
5858 if (operands[1] != const0_rtx) FAIL;
5860 ccmode = s390_select_ccmode (GET_CODE (operands[0]),
5861 s390_compare_op0, s390_compare_op1);
5862 operands[2] = gen_rtx_REG (ccmode, 33);
5863 operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1);
5866 (define_insn "*trap"
5867 [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)])
5871 [(set_attr "op_type" "RX")])
5874 ;;- Loop instructions.
5876 ;; This is all complicated by the fact that since this is a jump insn
5877 ;; we must handle our own output reloads.
5879 (define_expand "doloop_end"
5880 [(use (match_operand 0 "" "")) ; loop pseudo
5881 (use (match_operand 1 "" "")) ; iterations; zero if unknown
5882 (use (match_operand 2 "" "")) ; max iterations
5883 (use (match_operand 3 "" "")) ; loop level
5884 (use (match_operand 4 "" ""))] ; label
5888 if (GET_MODE (operands[0]) == SImode)
5889 emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0]));
5890 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
5891 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
5898 (define_insn "doloop_si"
5901 (ne (match_operand:SI 1 "register_operand" "d,d")
5903 (label_ref (match_operand 0 "" ""))
5905 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5906 (plus:SI (match_dup 1) (const_int -1)))
5907 (clobber (match_scratch:SI 3 "=X,&d"))
5908 (clobber (reg:CC 33))]
5912 if (which_alternative != 0)
5914 else if (get_attr_length (insn) == 4)
5915 return \"brct\\t%1,%l0\";
5919 [(set_attr "op_type" "RI")
5920 (set (attr "length")
5921 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5923 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
5925 (eq (symbol_ref "flag_pic") (const_int 0))
5926 (const_int 6)] (const_int 8)))])
5928 (define_insn "*doloop_si_long"
5931 (ne (match_operand:SI 1 "register_operand" "d,d")
5933 (match_operand 0 "address_operand" "p,p")
5935 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
5936 (plus:SI (match_dup 1) (const_int -1)))
5937 (clobber (match_scratch:SI 3 "=X,&d"))
5938 (clobber (reg:CC 33))]
5942 if (get_attr_op_type (insn) == OP_TYPE_RR)
5943 return \"bctr\\t%1,%0\";
5945 return \"bct\\t%1,%a0\";
5947 [(set (attr "op_type")
5948 (if_then_else (match_operand 0 "register_operand" "")
5949 (const_string "RR") (const_string "RX")))
5950 (set_attr "atype" "mem")])
5954 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
5956 (match_operand 0 "" "")
5958 (set (match_operand:SI 2 "nonimmediate_operand" "")
5959 (plus:SI (match_dup 1) (const_int -1)))
5960 (clobber (match_scratch:SI 3 ""))
5961 (clobber (reg:CC 33))]
5963 && (! REG_P (operands[2])
5964 || ! rtx_equal_p (operands[1], operands[2]))"
5965 [(set (match_dup 3) (match_dup 1))
5966 (parallel [(set (reg:CCAN 33)
5967 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
5969 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
5970 (set (match_dup 2) (match_dup 3))
5971 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
5976 (define_insn "doloop_di"
5979 (ne (match_operand:DI 1 "register_operand" "d,d")
5981 (label_ref (match_operand 0 "" ""))
5983 (set (match_operand:DI 2 "register_operand" "=1,?*m*r")
5984 (plus:DI (match_dup 1) (const_int -1)))
5985 (clobber (match_scratch:DI 3 "=X,&d"))
5986 (clobber (reg:CC 33))]
5990 if (which_alternative != 0)
5992 else if (get_attr_length (insn) == 4)
5993 return \"brctg\\t%1,%l0\";
5997 [(set_attr "op_type" "RI")
5998 (set (attr "length")
5999 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6000 (const_int 4) (const_int 12)))])
6002 (define_insn "*doloop_di_long"
6005 (ne (match_operand:DI 1 "register_operand" "d,d")
6007 (match_operand 0 "address_operand" "p,p")
6009 (set (match_operand:DI 2 "register_operand" "=1,?*m*d")
6010 (plus:DI (match_dup 1) (const_int -1)))
6011 (clobber (match_scratch:DI 3 "=X,&d"))
6012 (clobber (reg:CC 33))]
6016 if (get_attr_op_type (insn) == OP_TYPE_RRE)
6017 return \"bctgr\\t%1,%0\";
6019 return \"bctg\\t%1,%a0\";
6021 [(set (attr "op_type")
6022 (if_then_else (match_operand 0 "register_operand" "")
6023 (const_string "RRE") (const_string "RXE")))
6024 (set_attr "atype" "mem")])
6028 (if_then_else (ne (match_operand:DI 1 "register_operand" "")
6030 (match_operand 0 "" "")
6032 (set (match_operand:DI 2 "nonimmediate_operand" "")
6033 (plus:DI (match_dup 1) (const_int -1)))
6034 (clobber (match_scratch:DI 3 ""))
6035 (clobber (reg:CC 33))]
6037 && (! REG_P (operands[2])
6038 || ! rtx_equal_p (operands[1], operands[2]))"
6039 [(set (match_dup 3) (match_dup 1))
6040 (parallel [(set (reg:CCAN 33)
6041 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6043 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6044 (set (match_dup 2) (match_dup 3))
6045 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
6051 ;;- Unconditional jump instructions.
6055 ; jump instruction pattern(s).
6059 [(set (pc) (label_ref (match_operand 0 "" "")))]
6063 if (get_attr_length (insn) == 4)
6065 else if (TARGET_64BIT)
6066 return \"jg\\t%l0\";
6070 [(set_attr "op_type" "RI")
6071 (set (attr "length")
6072 (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6074 (ne (symbol_ref "TARGET_64BIT") (const_int 0))
6076 (eq (symbol_ref "flag_pic") (const_int 0))
6077 (const_int 6)] (const_int 8)))])
6080 ; indirect-jump instruction pattern(s).
6083 (define_insn "indirect_jump"
6084 [(set (pc) (match_operand 0 "address_operand" "p"))]
6088 if (get_attr_op_type (insn) == OP_TYPE_RR)
6093 [(set (attr "op_type")
6094 (if_then_else (match_operand 0 "register_operand" "")
6095 (const_string "RR") (const_string "RX")))
6096 (set_attr "atype" "mem")])
6099 ; casesi instruction pattern(s).
6102 (define_insn "casesi_jump"
6103 [(set (pc) (match_operand 0 "address_operand" "p"))
6104 (use (label_ref (match_operand 1 "" "")))]
6108 if (get_attr_op_type (insn) == OP_TYPE_RR)
6113 [(set (attr "op_type")
6114 (if_then_else (match_operand 0 "register_operand" "")
6115 (const_string "RR") (const_string "RX")))
6116 (set_attr "atype" "mem")])
6118 (define_expand "casesi"
6119 [(match_operand:SI 0 "general_operand" "")
6120 (match_operand:SI 1 "general_operand" "")
6121 (match_operand:SI 2 "general_operand" "")
6122 (label_ref (match_operand 3 "" ""))
6123 (label_ref (match_operand 4 "" ""))]
6127 rtx index = gen_reg_rtx (SImode);
6128 rtx base = gen_reg_rtx (Pmode);
6129 rtx target = gen_reg_rtx (Pmode);
6131 emit_move_insn (index, operands[0]);
6132 emit_insn (gen_subsi3 (index, index, operands[1]));
6133 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6136 if (Pmode != SImode)
6137 index = convert_to_mode (Pmode, index, 1);
6138 if (GET_CODE (index) != REG)
6139 index = copy_to_mode_reg (Pmode, index);
6142 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
6144 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
6146 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
6148 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
6149 emit_move_insn (target, index);
6152 target = gen_rtx_PLUS (Pmode, base, target);
6153 emit_jump_insn (gen_casesi_jump (target, operands[3]));
6160 ;;- Jump to subroutine.
6165 ; untyped call instruction pattern(s).
6168 ;; Call subroutine returning any type.
6169 (define_expand "untyped_call"
6170 [(parallel [(call (match_operand 0 "" "")
6172 (match_operand 1 "" "")
6173 (match_operand 2 "" "")])]
6179 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
6181 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6183 rtx set = XVECEXP (operands[2], 0, i);
6184 emit_move_insn (SET_DEST (set), SET_SRC (set));
6187 /* The optimizer does not know that the call sets the function value
6188 registers we stored in the result block. We avoid problems by
6189 claiming that all hard registers are used and clobbered at this
6191 emit_insn (gen_blockage ());
6196 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6197 ;; all of memory. This blocks insns from being moved across this point.
6199 (define_insn "blockage"
6200 [(unspec_volatile [(const_int 0)] 0)]
6203 [(set_attr "type" "none")
6204 (set_attr "length" "0")])
6209 ; call instruction pattern(s).
6212 (define_expand "call"
6213 [(call (match_operand 0 "" "")
6214 (match_operand 1 "" ""))
6215 (use (match_operand 2 "" ""))]
6222 /* Direct function calls need special treatment. */
6223 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6225 rtx sym = XEXP (operands[0], 0);
6227 /* When calling a global routine in PIC mode, we must
6228 replace the symbol itself with the PLT stub. */
6229 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6231 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6232 sym = gen_rtx_CONST (Pmode, sym);
6237 /* Unless we can use the bras(l) insn, force the
6238 routine address into a register. */
6239 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6241 rtx target = gen_reg_rtx (Pmode);
6242 emit_move_insn (target, sym);
6246 operands[0] = gen_rtx_MEM (QImode, sym);
6250 insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
6251 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6253 /* In 31-bit, we must load the GOT register even if the
6254 compiler doesn't know about it, because the PLT glue
6255 code uses it. In 64-bit, this is not necessary. */
6256 if (plt_call && !TARGET_64BIT)
6257 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6262 (define_expand "call_exp"
6263 [(parallel [(call (match_operand 0 "" "")
6264 (match_operand 1 "" ""))
6265 (clobber (match_operand 2 "" ""))])]
6269 (define_insn "brasl"
6270 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
6271 (match_operand:SI 1 "const_int_operand" "n"))
6272 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6275 [(set_attr "op_type" "RIL")
6276 (set_attr "type" "jsr")])
6279 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
6280 (match_operand:SI 1 "const_int_operand" "n"))
6281 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6284 [(set_attr "op_type" "RI")
6285 (set_attr "type" "jsr")])
6287 (define_insn "basr_64"
6288 [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
6289 (match_operand:SI 1 "const_int_operand" "n"))
6290 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6293 [(set_attr "op_type" "RR")
6294 (set_attr "type" "jsr")
6295 (set_attr "atype" "mem")])
6297 (define_insn "basr_31"
6298 [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
6299 (match_operand:SI 1 "const_int_operand" "n"))
6300 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6303 [(set_attr "op_type" "RR")
6304 (set_attr "type" "jsr")
6305 (set_attr "atype" "mem")])
6307 (define_insn "bas_64"
6308 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6309 (match_operand:SI 1 "const_int_operand" "n"))
6310 (clobber (match_operand:DI 2 "register_operand" "=r"))]
6313 [(set_attr "op_type" "RX")
6314 (set_attr "type" "jsr")
6315 (set_attr "atype" "mem")])
6317 (define_insn "bas_31"
6318 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
6319 (match_operand:SI 1 "const_int_operand" "n"))
6320 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6323 [(set_attr "op_type" "RX")
6324 (set_attr "type" "jsr")
6325 (set_attr "atype" "mem")])
6329 ; call_value instruction pattern(s).
6332 (define_expand "call_value"
6333 [(set (match_operand 0 "" "")
6334 (call (match_operand 1 "" "")
6335 (match_operand 2 "" "")))
6336 (use (match_operand 3 "" ""))]
6343 /* Direct function calls need special treatment. */
6344 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6346 rtx sym = XEXP (operands[1], 0);
6348 /* When calling a global routine in PIC mode, we must
6349 replace the symbol itself with the PLT stub. */
6350 if (flag_pic && !SYMBOL_REF_FLAG (sym))
6352 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
6353 sym = gen_rtx_CONST (Pmode, sym);
6358 /* Unless we can use the bras(l) insn, force the
6359 routine address into a register. */
6360 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
6362 rtx target = gen_reg_rtx (Pmode);
6363 emit_move_insn (target, sym);
6367 operands[1] = gen_rtx_MEM (QImode, sym);
6371 insn = emit_call_insn (
6372 gen_call_value_exp (operands[0], operands[1], operands[2],
6373 gen_rtx_REG (Pmode, RETURN_REGNUM)));
6375 /* In 31-bit, we must load the GOT register even if the
6376 compiler doesn't know about it, because the PLT glue
6377 code uses it. In 64-bit, this is not necessary. */
6378 if (plt_call && !TARGET_64BIT)
6379 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
6384 (define_expand "call_value_exp"
6385 [(parallel [(set (match_operand 0 "" "")
6386 (call (match_operand 1 "" "")
6387 (match_operand 2 "" "")))
6388 (clobber (match_operand 3 "" ""))])]
6392 (define_insn "brasl_r"
6393 [(set (match_operand 0 "register_operand" "=df")
6394 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
6395 (match_operand:SI 2 "const_int_operand" "n")))
6396 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6399 [(set_attr "op_type" "RIL")
6400 (set_attr "type" "jsr")])
6402 (define_insn "bras_r"
6403 [(set (match_operand 0 "register_operand" "=df")
6404 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
6405 (match_operand:SI 2 "const_int_operand" "n")))
6406 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6409 [(set_attr "op_type" "RI")
6410 (set_attr "type" "jsr")])
6412 (define_insn "basr_r_64"
6413 [(set (match_operand 0 "register_operand" "=df")
6414 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
6415 (match_operand:SI 2 "const_int_operand" "n")))
6416 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6419 [(set_attr "op_type" "RR")
6420 (set_attr "type" "jsr")])
6422 (define_insn "basr_r_31"
6423 [(set (match_operand 0 "register_operand" "=df")
6424 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
6425 (match_operand:SI 2 "const_int_operand" "n")))
6426 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6429 [(set_attr "op_type" "RR")
6430 (set_attr "type" "jsr")
6431 (set_attr "atype" "mem")])
6433 (define_insn "bas_r_64"
6434 [(set (match_operand 0 "register_operand" "=df")
6435 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6436 (match_operand:SI 2 "const_int_operand" "n")))
6437 (clobber (match_operand:DI 3 "register_operand" "=r"))]
6440 [(set_attr "op_type" "RX")
6441 (set_attr "type" "jsr")
6442 (set_attr "atype" "mem")])
6444 (define_insn "bas_r_31"
6445 [(set (match_operand 0 "register_operand" "=df")
6446 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
6447 (match_operand:SI 2 "const_int_operand" "n")))
6448 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6451 [(set_attr "op_type" "RX")
6452 (set_attr "type" "jsr")
6453 (set_attr "atype" "mem")])
6457 ;;- Miscellaneous instructions.
6461 ; allocate stack instruction pattern(s).
6464 (define_expand "allocate_stack"
6466 (plus (reg 15) (match_operand 1 "general_operand" "")))
6467 (set (match_operand 0 "general_operand" "")
6472 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
6473 rtx chain = gen_rtx (MEM, Pmode, stack);
6474 rtx temp = gen_reg_rtx (Pmode);
6476 emit_move_insn (temp, chain);
6479 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6481 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
6483 emit_move_insn (chain, temp);
6485 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6491 ; setjmp/longjmp instruction pattern(s).
6494 (define_expand "builtin_setjmp_setup"
6495 [(unspec [(match_operand 0 "register_operand" "a")] 1)]
6499 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6500 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6502 emit_move_insn (base, basereg);
6506 (define_expand "builtin_setjmp_receiver"
6507 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
6511 rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6512 rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
6513 SYMBOL_REF_FLAG (got) = 1;
6515 emit_move_insn (gotreg, got);
6516 emit_insn (gen_rtx_USE (VOIDmode, gotreg));
6520 (define_expand "builtin_longjmp"
6521 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6525 /* The elements of the buffer are, in order: */
6526 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6527 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
6528 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
6529 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
6530 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
6531 rtx jmp = gen_rtx_REG (Pmode, 14);
6533 emit_move_insn (jmp, lab);
6534 emit_move_insn (basereg, base);
6535 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6536 emit_move_insn (hard_frame_pointer_rtx, fp);
6538 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6539 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6540 emit_insn (gen_rtx_USE (VOIDmode, basereg));
6541 emit_indirect_jump (jmp);
6546 ;; These patterns say how to save and restore the stack pointer. We need not
6547 ;; save the stack pointer at function level since we are careful to
6548 ;; preserve the backchain. At block level, we have to restore the backchain
6549 ;; when we restore the stack pointer.
6551 ;; For nonlocal gotos, we must save both the stack pointer and its
6552 ;; backchain and restore both. Note that in the nonlocal case, the
6553 ;; save area is a memory location.
6555 (define_expand "save_stack_function"
6556 [(match_operand 0 "general_operand" "")
6557 (match_operand 1 "general_operand" "")]
6561 (define_expand "restore_stack_function"
6562 [(match_operand 0 "general_operand" "")
6563 (match_operand 1 "general_operand" "")]
6567 (define_expand "restore_stack_block"
6568 [(use (match_operand 0 "register_operand" ""))
6569 (set (match_dup 2) (match_dup 3))
6570 (set (match_dup 0) (match_operand 1 "register_operand" ""))
6571 (set (match_dup 3) (match_dup 2))]
6575 operands[2] = gen_reg_rtx (Pmode);
6576 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
6579 (define_expand "save_stack_nonlocal"
6580 [(match_operand 0 "memory_operand" "")
6581 (match_operand 1 "register_operand" "")]
6585 rtx temp = gen_reg_rtx (Pmode);
6587 /* Copy the backchain to the first word, sp to the second. */
6588 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
6589 emit_move_insn (operand_subword (operands[0], 0, 0,
6590 TARGET_64BIT ? TImode : DImode),
6592 emit_move_insn (operand_subword (operands[0], 1, 0,
6593 TARGET_64BIT ? TImode : DImode),
6598 (define_expand "restore_stack_nonlocal"
6599 [(match_operand 0 "register_operand" "")
6600 (match_operand 1 "memory_operand" "")]
6604 rtx temp = gen_reg_rtx (Pmode);
6606 /* Restore the backchain from the first word, sp from the second. */
6607 emit_move_insn (temp,
6608 operand_subword (operands[1], 0, 0,
6609 TARGET_64BIT ? TImode : DImode));
6610 emit_move_insn (operands[0],
6611 operand_subword (operands[1], 1, 0,
6612 TARGET_64BIT ? TImode : DImode));
6613 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
6619 ; nop instruction pattern(s).
6626 [(set_attr "op_type" "RR")])
6630 ; Special literal pool access instruction pattern(s).
6633 (define_insn "consttable_qi"
6634 [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] 200)]
6638 assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
6641 [(set_attr "op_type" "NN")
6642 (set_attr "length" "1")])
6644 (define_insn "consttable_hi"
6645 [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] 201)]
6649 assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1);
6652 [(set_attr "op_type" "NN")
6653 (set_attr "length" "2")])
6655 (define_insn "consttable_si"
6656 [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] 202)]
6660 if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[0]))
6661 return \".long\\t%0\";
6663 assemble_integer (operands[0], 4, 4*BITS_PER_UNIT, 1);
6666 [(set_attr "op_type" "NN")
6667 (set_attr "length" "4")])
6669 (define_insn "consttable_di"
6670 [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] 203)]
6674 assemble_integer (operands[0], 8, 8*BITS_PER_UNIT, 1);
6677 [(set_attr "op_type" "NN")
6678 (set_attr "length" "8")])
6680 (define_insn "consttable_sf"
6681 [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] 204)]
6687 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6690 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6691 assemble_real (r, SFmode, 4*BITS_PER_UNIT);
6694 [(set_attr "op_type" "NN")
6695 (set_attr "length" "4")])
6697 (define_insn "consttable_df"
6698 [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")] 205)]
6704 if (GET_CODE (operands[0]) != CONST_DOUBLE)
6707 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
6708 assemble_real (r, DFmode, 8*BITS_PER_UNIT);
6711 [(set_attr "op_type" "NN")
6712 (set_attr "length" "8")])
6714 (define_insn "pool_start_31"
6715 [(unspec_volatile [(const_int 0)] 206)]
6718 [(set_attr "op_type" "NN")
6719 (set_attr "length" "2")])
6721 (define_insn "pool_end_31"
6722 [(unspec_volatile [(const_int 0)] 207)]
6725 [(set_attr "op_type" "NN")
6726 (set_attr "length" "2")])
6728 (define_insn "pool_start_64"
6729 [(unspec_volatile [(const_int 0)] 206)]
6731 ".section\\t.rodata\;.align\\t8"
6732 [(set_attr "op_type" "NN")
6733 (set_attr "length" "0")])
6735 (define_insn "pool_end_64"
6736 [(unspec_volatile [(const_int 0)] 207)]
6739 [(set_attr "op_type" "NN")
6740 (set_attr "length" "0")])
6742 (define_insn "reload_base_31"
6743 [(set (match_operand:SI 0 "register_operand" "=a")
6744 (unspec:SI [(label_ref (match_operand 1 "" ""))] 210))]
6746 "basr\\t%0,0\;la\\t%0,%1-.(%0)"
6747 [(set_attr "op_type" "NN")
6748 (set_attr "type" "la")
6749 (set_attr "length" "6")])
6751 (define_insn "reload_base_64"
6752 [(set (match_operand:DI 0 "register_operand" "=a")
6753 (unspec:DI [(label_ref (match_operand 1 "" ""))] 210))]
6756 [(set_attr "op_type" "RIL")
6757 (set_attr "type" "la")])
6759 (define_insn "reload_anchor"
6760 [(set (match_operand:SI 0 "register_operand" "=a")
6761 (unspec:SI [(match_operand:SI 1 "register_operand" "a")] 211))]
6763 "l\\t%0,0(%1)\;la\\t%0,0(%0,%1)"
6764 [(set_attr "op_type" "NN")
6765 (set_attr "type" "la")
6766 (set_attr "length" "8")])
6769 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] 220)]
6772 [(set_attr "op_type" "NN")
6773 (set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
6776 ;; Insns related to generating the function prologue and epilogue.
6780 (define_expand "prologue"
6781 [(use (const_int 0))]
6785 s390_emit_prologue ();
6789 (define_expand "epilogue"
6790 [(use (const_int 1))]
6794 s390_emit_epilogue ();
6799 (define_insn "*return_si"
6801 (use (match_operand:SI 0 "register_operand" "a"))]
6804 [(set_attr "op_type" "RR")
6805 (set_attr "type" "jsr")
6806 (set_attr "atype" "mem")])
6808 (define_insn "*return_di"
6810 (use (match_operand:DI 0 "register_operand" "a"))]
6813 [(set_attr "op_type" "RR")
6814 (set_attr "type" "jsr")
6815 (set_attr "atype" "mem")])
6817 (define_insn "literal_pool_31"
6818 [(unspec_volatile [(const_int 0)] 300)
6819 (set (match_operand:SI 0 "register_operand" "=a")
6820 (label_ref (match_operand 1 "" "")))
6821 (use (label_ref (match_operand 2 "" "")))]
6825 if (s390_nr_constants) {
6826 output_asm_insn (\"bras\\t%0,%2\", operands);
6827 s390_output_constant_pool (operands[1], operands[2]);
6831 [(set_attr "op_type" "NN")
6832 (set_attr "type" "la")])
6834 (define_insn "literal_pool_64"
6835 [(unspec_volatile [(const_int 0)] 300)
6836 (set (match_operand:DI 0 "register_operand" "=a")
6837 (label_ref (match_operand 1 "" "")))
6838 (use (label_ref (match_operand 2 "" "")))]
6842 if (s390_nr_constants) {
6843 output_asm_insn (\"larl\\t%0,%1\", operands);
6844 s390_output_constant_pool (operands[1], operands[2]);
6848 [(set_attr "op_type" "NN")
6849 (set_attr "type" "la")])