1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com) and
6 ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify it under
11 ;; the terms of the GNU General Public License as published by the Free
12 ;; Software Foundation; either version 3, or (at your option) any later
15 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %c: print integer X as if it's an signed byte.
43 ;; %x: print integer X as if it's an unsigned halfword.
44 ;; %h: print integer X as if it's a signed halfword.
45 ;; %i: print the first nonzero HImode part of X.
46 ;; %j: print the first HImode part unequal to -1 of X.
47 ;; %k: print the first nonzero SImode part of X.
48 ;; %m: print the first SImode part unequal to -1 of X.
49 ;; %o: print integer X as if it's an unsigned 32bit word.
51 ;; We have a special constraint for pattern matching.
53 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
68 ; GOT/PLT and lt-relative accesses
69 (UNSPEC_LTREL_OFFSET 100)
70 (UNSPEC_LTREL_BASE 101)
71 (UNSPEC_POOL_OFFSET 102)
79 (UNSPEC_RELOAD_BASE 210)
80 (UNSPEC_MAIN_BASE 211)
85 ; TLS relocation specifiers
90 (UNSPEC_GOTNTPOFF 504)
91 (UNSPEC_INDNTPOFF 505)
94 (UNSPEC_TLSLDM_NTPOFF 511)
101 ; Stack Smashing Protector
105 ; Copy sign instructions
106 (UNSPEC_COPYSIGN 800)
108 ; Test Data Class (TDC)
109 (UNSPEC_TDC_INSN 900)
113 ;; UNSPEC_VOLATILE usage
121 (UNSPECV_TPF_PROLOGUE 20)
122 (UNSPECV_TPF_EPILOGUE 21)
126 (UNSPECV_POOL_SECTION 201)
127 (UNSPECV_POOL_ALIGN 202)
128 (UNSPECV_POOL_ENTRY 203)
129 (UNSPECV_MAIN_POOL 300)
143 ; Registers with special meaning
147 ; Sibling call register.
149 ; Literal pool base register.
151 ; Return address register.
153 ; Condition code register.
155 ; Thread local storage pointer register.
159 ; Hardware register names
163 ; General purpose registers
165 ; Floating point registers.
171 ;; PFPO GPR0 argument format
176 ; PFPO operation type
177 (PFPO_CONVERT 0x1000000)
179 (PFPO_OP_TYPE_SF 0x5)
180 (PFPO_OP_TYPE_DF 0x6)
181 (PFPO_OP_TYPE_TF 0x7)
182 (PFPO_OP_TYPE_SD 0x8)
183 (PFPO_OP_TYPE_DD 0x9)
184 (PFPO_OP_TYPE_TD 0xa)
185 ; Bitposition of operand types
186 (PFPO_OP0_TYPE_SHIFT 16)
187 (PFPO_OP1_TYPE_SHIFT 8)
191 ;; Instruction operand type as used in the Principles of Operation.
192 ;; Used to determine defaults for length and other attribute values.
194 (define_attr "op_type"
195 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
198 ;; Instruction type attribute used for scheduling.
200 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
201 cs,vs,store,sem,idiv,
202 imulhi,imulsi,imuldi,
203 branch,jsr,fsimptf,fsimpdf,fsimpsf,
204 floadtf,floaddf,floadsf,fstoredf,fstoresf,
205 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
206 ftoi,fsqrttf,fsqrtdf,fsqrtsf,
207 ftrunctf,ftruncdf, ftruncsd, ftruncdd,
208 itoftf, itofdf, itofsf, itofdd, itoftd,
209 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
210 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd,
212 (cond [(eq_attr "op_type" "NN") (const_string "other")
213 (eq_attr "op_type" "SS") (const_string "cs")]
214 (const_string "integer")))
216 ;; Another attribute used for scheduling purposes:
217 ;; agen: Instruction uses the address generation unit
218 ;; reg: Instruction does not use the agen unit
220 (define_attr "atype" "agen,reg"
221 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE")
223 (const_string "agen")))
225 ;; Properties concerning Z10 execution grouping and value forwarding.
226 ;; z10_super: instruction is superscalar.
227 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c.
228 ;; z10_fwd: The instruction reads the value of an operand and stores it into a
229 ;; target register. It can forward this value to a second instruction that reads
230 ;; the same register if that second instruction is issued in the same group.
231 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the
232 ;; instruction in the S pipe writes to the register, then the T instruction
233 ;; can immediately read the new value.
234 ;; z10_fr: union of Z10_fwd and z10_rec.
235 ;; z10_c: second operand of instruction is a register and read with complemented bits.
236 ;; z10_cobra: its a compare and branch instruction
238 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass.
241 (define_attr "z10prop" "none,
242 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1,
243 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1,
245 z10_fr, z10_fr_A3, z10_fr_E1,
247 (const_string "none"))
252 (define_attr "length" ""
253 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
254 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
258 ;; Processor type. This attribute must exactly match the processor_type
259 ;; enumeration in s390.h. The current machine description does not
260 ;; distinguish between g5 and g6, but there are differences between the two
261 ;; CPUs could in theory be modeled.
263 (define_attr "cpu" "g5,g6,z900,z990,z9_109,z10"
264 (const (symbol_ref "s390_tune")))
266 (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10"
267 (const_string "standard"))
269 (define_attr "enabled" ""
270 (cond [(eq_attr "cpu_facility" "standard")
273 (and (eq_attr "cpu_facility" "ieee")
274 (ne (symbol_ref "TARGET_CPU_IEEE_FLOAT") (const_int 0)))
277 (and (eq_attr "cpu_facility" "zarch")
278 (ne (symbol_ref "TARGET_ZARCH") (const_int 0)))
281 (and (eq_attr "cpu_facility" "longdisp")
282 (ne (symbol_ref "TARGET_LONG_DISPLACEMENT") (const_int 0)))
285 (and (eq_attr "cpu_facility" "extimm")
286 (ne (symbol_ref "TARGET_EXTIMM") (const_int 0)))
289 (and (eq_attr "cpu_facility" "dfp")
290 (ne (symbol_ref "TARGET_DFP") (const_int 0)))
293 (and (eq_attr "cpu_facility" "z10")
294 (ne (symbol_ref "TARGET_Z10") (const_int 0)))
298 ;; Pipeline description for z900. For lack of anything better,
299 ;; this description is also used for the g5 and g6.
302 ;; Pipeline description for z990, z9-109 and z9-ec.
305 ;; Pipeline description for z10
309 (include "predicates.md")
311 ;; Constraint definitions
312 (include "constraints.md")
319 ;; These mode iterators allow floating point patterns to be generated from the
321 (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
322 (SD "TARGET_HARD_DFP")])
323 (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
324 (define_mode_iterator FPALL [TF DF SF TD DD SD])
325 (define_mode_iterator BFP [TF DF SF])
326 (define_mode_iterator DFP [TD DD])
327 (define_mode_iterator DFP_ALL [TD DD SD])
328 (define_mode_iterator DSF [DF SF])
329 (define_mode_iterator SD_SF [SF SD])
330 (define_mode_iterator DD_DF [DF DD])
331 (define_mode_iterator TD_TF [TF TD])
333 ;; This mode iterator allows 31-bit and 64-bit TDSI patterns to be generated
334 ;; from the same template.
335 (define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI])
337 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
338 ;; from the same template.
339 (define_mode_iterator GPR [(DI "TARGET_64BIT") SI])
340 (define_mode_iterator DSI [DI SI])
342 ;; These mode iterators allow :P to be used for patterns that operate on
343 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
344 (define_mode_iterator DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
345 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
347 ;; This mode iterator allows the QI and HI patterns to be defined from
348 ;; the same template.
349 (define_mode_iterator HQI [HI QI])
351 ;; This mode iterator allows the integer patterns to be defined from the
353 (define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI])
354 (define_mode_iterator INTALL [TI DI SI HI QI])
356 ;; This iterator allows to unify all 'bCOND' expander patterns.
357 (define_code_iterator COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
358 ordered uneq unlt ungt unle unge ltgt])
360 ;; This iterator allows to unify all 'sCOND' patterns.
361 (define_code_iterator SCOND [ltu gtu leu geu])
363 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
364 ;; the same template.
365 (define_code_iterator SHIFT [ashift lshiftrt])
367 ;; This iterator and attribute allow to combine most atomic operations.
368 (define_code_iterator ATOMIC [and ior xor plus minus mult])
369 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
370 (plus "add") (minus "sub") (mult "nand")])
372 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
373 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
374 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
376 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
377 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
379 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
381 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
382 ;; Likewise for "<RXe>".
383 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
384 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
386 ;; The decimal floating point variants of add, sub, div and mul support 3
387 ;; fp register operands. The following attributes allow to merge the bfp and
388 ;; dfp variants in a single insn definition.
390 ;; This attribute is used to set op_type accordingly.
391 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
392 (DD "RRR") (SD "RRR")])
394 ;; This attribute is used in the operand constraint list in order to have the
395 ;; first and the second operand match for bfp modes.
396 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
398 ;; This attribute is used in the operand list of the instruction to have an
399 ;; additional operand for the dfp instructions.
400 (define_mode_attr op1 [(TF "") (DF "") (SF "")
401 (TD "%1,") (DD "%1,") (SD "%1,")])
404 ;; This attribute is used in the operand constraint list
405 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
406 ;; TFmode values are represented by a fp register pair. Since the
407 ;; sign bit instructions only handle single source and target fp registers
408 ;; these instructions can only be used for TFmode values if the source and
409 ;; target operand uses the same fp register.
410 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
412 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
413 ;; This is used to disable the memory alternative in TFmode patterns.
414 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
416 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used
417 ;; within instruction mnemonics.
418 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
420 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp
421 ;; modes and to an empty string for bfp modes.
422 (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")])
424 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
425 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
426 ;; version only operates on one register.
427 (define_mode_attr d0 [(DI "d") (SI "0")])
429 ;; In combination with d0 this allows to combine instructions of which the 31bit
430 ;; version only operates on one register. The DImode version needs an additional
431 ;; register for the assembler output.
432 (define_mode_attr 1 [(DI "%1,") (SI "")])
434 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
435 ;; 'ashift' and "srdl" in 'lshiftrt'.
436 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
438 ;; In SHIFT templates, this attribute holds the correct standard name for the
439 ;; pattern itself and the corresponding function calls.
440 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
442 ;; This attribute handles differences in the instruction 'type' and will result
443 ;; in "RRE" for DImode and "RR" for SImode.
444 (define_mode_attr E [(DI "E") (SI "")])
446 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
447 ;; to result in "RXY" for DImode and "RX" for SImode.
448 (define_mode_attr Y [(DI "Y") (SI "")])
450 ;; This attribute handles differences in the instruction 'type' and will result
451 ;; in "RSE" for TImode and "RS" for DImode.
452 (define_mode_attr TE [(TI "E") (DI "")])
454 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
455 ;; and "lcr" in SImode.
456 (define_mode_attr g [(DI "g") (SI "")])
458 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
459 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
460 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
461 ;; variant for long displacements.
462 (define_mode_attr y [(DI "g") (SI "y")])
464 ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
465 ;; and "cds" in DImode.
466 (define_mode_attr tg [(TI "g") (DI "")])
468 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
469 ;; and "cfdbr" in SImode.
470 (define_mode_attr gf [(DI "g") (SI "f")])
472 ;; ICM mask required to load MODE value into the lowest subreg
473 ;; of a SImode register.
474 (define_mode_attr icm_lo [(HI "3") (QI "1")])
476 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
477 ;; HImode and "llgc" in QImode.
478 (define_mode_attr hc [(HI "h") (QI "c")])
480 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
482 (define_mode_attr DBL [(DI "TI") (SI "DI")])
484 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
485 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
486 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
488 ;; Maximum unsigned integer that fits in MODE.
489 (define_mode_attr max_uint [(HI "65535") (QI "255")])
492 ;;- Compare instructions.
495 (define_expand "cmp<mode>"
496 [(set (reg:CC CC_REGNUM)
497 (compare:CC (match_operand:GPR 0 "register_operand" "")
498 (match_operand:GPR 1 "general_operand" "")))]
501 s390_compare_op0 = operands[0];
502 s390_compare_op1 = operands[1];
506 (define_expand "cmp<mode>"
507 [(set (reg:CC CC_REGNUM)
508 (compare:CC (match_operand:FP 0 "register_operand" "")
509 (match_operand:FP 1 "general_operand" "")))]
512 s390_compare_op0 = operands[0];
513 s390_compare_op1 = operands[1];
518 ; Test-under-Mask instructions
520 (define_insn "*tmqi_mem"
521 [(set (reg CC_REGNUM)
522 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
523 (match_operand:QI 1 "immediate_operand" "n,n"))
524 (match_operand:QI 2 "immediate_operand" "n,n")))]
525 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
529 [(set_attr "op_type" "SI,SIY")
530 (set_attr "z10prop" "z10_super,z10_super")])
532 (define_insn "*tmdi_reg"
533 [(set (reg CC_REGNUM)
534 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
535 (match_operand:DI 1 "immediate_operand"
536 "N0HD0,N1HD0,N2HD0,N3HD0"))
537 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
539 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
540 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
546 [(set_attr "op_type" "RI")
547 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")])
549 (define_insn "*tmsi_reg"
550 [(set (reg CC_REGNUM)
551 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
552 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
553 (match_operand:SI 2 "immediate_operand" "n,n")))]
554 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
555 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
559 [(set_attr "op_type" "RI")])
561 (define_insn "*tm<mode>_full"
562 [(set (reg CC_REGNUM)
563 (compare (match_operand:HQI 0 "register_operand" "d")
564 (match_operand:HQI 1 "immediate_operand" "n")))]
565 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
567 [(set_attr "op_type" "RI")])
571 ; Load-and-Test instructions
574 ; tst(di|si) instruction pattern(s).
576 (define_insn "*tstdi_sign"
577 [(set (reg CC_REGNUM)
581 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
582 (const_int 32)) (const_int 32))
583 (match_operand:DI 1 "const0_operand" "")))
584 (set (match_operand:DI 2 "register_operand" "=d,d")
585 (sign_extend:DI (match_dup 0)))]
586 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
589 [(set_attr "op_type" "RRE,RXY")
590 (set_attr "cpu_facility" "*,z10")
591 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ])
594 (define_insn "*tst<mode>_extimm"
595 [(set (reg CC_REGNUM)
596 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
597 (match_operand:GPR 1 "const0_operand" "")))
598 (set (match_operand:GPR 2 "register_operand" "=d,d")
600 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
604 [(set_attr "op_type" "RR<E>,RXY")
605 (set_attr "z10prop" "z10_fr_E1,z10_fr_A3") ])
608 (define_insn "*tst<mode>_cconly_extimm"
609 [(set (reg CC_REGNUM)
610 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
611 (match_operand:GPR 1 "const0_operand" "")))
612 (clobber (match_scratch:GPR 2 "=X,d"))]
613 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
617 [(set_attr "op_type" "RR<E>,RXY")
618 (set_attr "z10prop" "z10_fr_E1,z10_fr_A3")])
620 (define_insn "*tstdi"
621 [(set (reg CC_REGNUM)
622 (compare (match_operand:DI 0 "register_operand" "d")
623 (match_operand:DI 1 "const0_operand" "")))
624 (set (match_operand:DI 2 "register_operand" "=d")
626 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
628 [(set_attr "op_type" "RRE")
629 (set_attr "z10prop" "z10_fr_E1")])
631 (define_insn "*tstsi"
632 [(set (reg CC_REGNUM)
633 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
634 (match_operand:SI 1 "const0_operand" "")))
635 (set (match_operand:SI 2 "register_operand" "=d,d,d")
637 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
642 [(set_attr "op_type" "RR,RS,RSY")
643 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
645 (define_insn "*tstsi_cconly"
646 [(set (reg CC_REGNUM)
647 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
648 (match_operand:SI 1 "const0_operand" "")))
649 (clobber (match_scratch:SI 2 "=X,d,d"))]
650 "s390_match_ccmode(insn, CCSmode)"
655 [(set_attr "op_type" "RR,RS,RSY")
656 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
658 (define_insn "*tstdi_cconly_31"
659 [(set (reg CC_REGNUM)
660 (compare (match_operand:DI 0 "register_operand" "d")
661 (match_operand:DI 1 "const0_operand" "")))]
662 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
664 [(set_attr "op_type" "RS")
665 (set_attr "atype" "reg")])
668 (define_insn "*tst<mode>_cconly2"
669 [(set (reg CC_REGNUM)
670 (compare (match_operand:GPR 0 "register_operand" "d")
671 (match_operand:GPR 1 "const0_operand" "")))]
672 "s390_match_ccmode(insn, CCSmode)"
674 [(set_attr "op_type" "RR<E>")
675 (set_attr "z10prop" "z10_fr_E1")])
677 ; tst(hi|qi) instruction pattern(s).
679 (define_insn "*tst<mode>CCT"
680 [(set (reg CC_REGNUM)
681 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
682 (match_operand:HQI 1 "const0_operand" "")))
683 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
685 "s390_match_ccmode(insn, CCTmode)"
688 icmy\t%2,<icm_lo>,%S0
690 [(set_attr "op_type" "RS,RSY,RI")
691 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
693 (define_insn "*tsthiCCT_cconly"
694 [(set (reg CC_REGNUM)
695 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
696 (match_operand:HI 1 "const0_operand" "")))
697 (clobber (match_scratch:HI 2 "=d,d,X"))]
698 "s390_match_ccmode(insn, CCTmode)"
703 [(set_attr "op_type" "RS,RSY,RI")
704 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
706 (define_insn "*tstqiCCT_cconly"
707 [(set (reg CC_REGNUM)
708 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
709 (match_operand:QI 1 "const0_operand" "")))]
710 "s390_match_ccmode(insn, CCTmode)"
715 [(set_attr "op_type" "SI,SIY,RI")
716 (set_attr "z10prop" "z10_super,z10_super,*")])
718 (define_insn "*tst<mode>"
719 [(set (reg CC_REGNUM)
720 (compare (match_operand:HQI 0 "s_operand" "Q,S")
721 (match_operand:HQI 1 "const0_operand" "")))
722 (set (match_operand:HQI 2 "register_operand" "=d,d")
724 "s390_match_ccmode(insn, CCSmode)"
727 icmy\t%2,<icm_lo>,%S0"
728 [(set_attr "op_type" "RS,RSY")
729 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
731 (define_insn "*tst<mode>_cconly"
732 [(set (reg CC_REGNUM)
733 (compare (match_operand:HQI 0 "s_operand" "Q,S")
734 (match_operand:HQI 1 "const0_operand" "")))
735 (clobber (match_scratch:HQI 2 "=d,d"))]
736 "s390_match_ccmode(insn, CCSmode)"
739 icmy\t%2,<icm_lo>,%S0"
740 [(set_attr "op_type" "RS,RSY")
741 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
744 ; Compare (equality) instructions
746 (define_insn "*cmpdi_cct"
747 [(set (reg CC_REGNUM)
748 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
749 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
750 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
757 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")
758 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")])
760 (define_insn "*cmpsi_cct"
761 [(set (reg CC_REGNUM)
762 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
763 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
764 "s390_match_ccmode (insn, CCTmode)"
772 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
773 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super,z10_super,*")])
775 ; Compare (signed) instructions
777 (define_insn "*cmpdi_ccs_sign"
778 [(set (reg CC_REGNUM)
779 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
781 (match_operand:DI 0 "register_operand" "d, d,d")))]
782 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
787 [(set_attr "op_type" "RRE,RXY,RIL")
788 (set_attr "z10prop" "z10_c,*,*")
789 (set_attr "type" "*,*,larl")])
793 (define_insn "*cmpsi_ccs_sign"
794 [(set (reg CC_REGNUM)
795 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b"))
796 (match_operand:SI 0 "register_operand" "d,d,d")))]
797 "s390_match_ccmode(insn, CCSRmode)"
802 [(set_attr "op_type" "RX,RXY,RIL")
803 (set_attr "cpu_facility" "*,*,z10")
804 (set_attr "type" "*,*,larl")])
806 (define_insn "*cmphi_ccs_z10"
807 [(set (reg CC_REGNUM)
808 (compare (match_operand:HI 0 "s_operand" "Q")
809 (match_operand:HI 1 "immediate_operand" "K")))]
810 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
812 [(set_attr "op_type" "SIL")])
814 (define_insn "*cmpdi_ccs_signhi_rl"
815 [(set (reg CC_REGNUM)
816 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
817 (match_operand:GPR 0 "register_operand" "d,d")))]
818 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
822 [(set_attr "op_type" "RXY,RIL")
823 (set_attr "type" "*,larl")])
825 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
826 (define_insn "*cmp<mode>_ccs"
827 [(set (reg CC_REGNUM)
828 (compare (match_operand:GPR 0 "nonimmediate_operand"
830 (match_operand:GPR 1 "general_operand"
832 "s390_match_ccmode(insn, CCSmode)"
841 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
842 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
843 (set_attr "type" "*,*,*,*,*,*,larl")
844 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
847 ; Compare (unsigned) instructions
849 (define_insn "*cmpsi_ccu_zerohi_rlsi"
850 [(set (reg CC_REGNUM)
851 (compare (zero_extend:SI (mem:HI (match_operand:SI 1
852 "larl_operand" "X")))
853 (match_operand:SI 0 "register_operand" "d")))]
854 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
856 [(set_attr "op_type" "RIL")
857 (set_attr "type" "larl")])
860 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
861 [(set (reg CC_REGNUM)
862 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1
863 "larl_operand" "X")))
864 (match_operand:GPR 0 "register_operand" "d")))]
865 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
867 [(set_attr "op_type" "RIL")
868 (set_attr "type" "larl")
869 (set_attr "z10prop" "z10_super")])
871 (define_insn "*cmpdi_ccu_zero"
872 [(set (reg CC_REGNUM)
873 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
875 (match_operand:DI 0 "register_operand" "d, d,d")))]
876 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
881 [(set_attr "op_type" "RRE,RXY,RIL")
882 (set_attr "cpu_facility" "*,*,z10")
883 (set_attr "type" "*,*,larl")
884 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
886 (define_insn "*cmpdi_ccu"
887 [(set (reg CC_REGNUM)
888 (compare (match_operand:DI 0 "nonimmediate_operand"
890 (match_operand:DI 1 "general_operand"
891 "d,Op,b,D,RT,BQ,Q")))]
892 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
901 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
902 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
903 (set_attr "type" "*,*,larl,*,*,*,*")
904 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
906 (define_insn "*cmpsi_ccu"
907 [(set (reg CC_REGNUM)
908 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ")
909 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))]
910 "s390_match_ccmode (insn, CCUmode)"
920 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
921 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
922 (set_attr "type" "*,*,larl,*,*,*,*,*")
923 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
925 (define_insn "*cmphi_ccu"
926 [(set (reg CC_REGNUM)
927 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ")
928 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))]
929 "s390_match_ccmode (insn, CCUmode)
930 && !register_operand (operands[1], HImode)"
937 [(set_attr "op_type" "RS,RSY,SIL,SS,SS")
938 (set_attr "cpu_facility" "*,*,z10,*,*")
939 (set_attr "z10prop" "*,*,z10_super,*,*")])
941 (define_insn "*cmpqi_ccu"
942 [(set (reg CC_REGNUM)
943 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
944 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
945 "s390_match_ccmode (insn, CCUmode)
946 && !register_operand (operands[1], QImode)"
954 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
955 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
958 ; Block compare (CLC) instruction patterns.
961 [(set (reg CC_REGNUM)
962 (compare (match_operand:BLK 0 "memory_operand" "Q")
963 (match_operand:BLK 1 "memory_operand" "Q")))
964 (use (match_operand 2 "const_int_operand" "n"))]
965 "s390_match_ccmode (insn, CCUmode)
966 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
967 "clc\t%O0(%2,%R0),%S1"
968 [(set_attr "op_type" "SS")])
971 [(set (reg CC_REGNUM)
972 (compare (match_operand 0 "memory_operand" "")
973 (match_operand 1 "memory_operand" "")))]
975 && s390_match_ccmode (insn, CCUmode)
976 && GET_MODE (operands[0]) == GET_MODE (operands[1])
977 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
979 [(set (match_dup 0) (match_dup 1))
980 (use (match_dup 2))])]
982 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
983 operands[0] = adjust_address (operands[0], BLKmode, 0);
984 operands[1] = adjust_address (operands[1], BLKmode, 0);
986 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
987 operands[0], operands[1]);
988 operands[0] = SET_DEST (PATTERN (curr_insn));
992 ; (TF|DF|SF|TD|DD|SD) instructions
994 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
995 (define_insn "*cmp<mode>_ccs_0"
996 [(set (reg CC_REGNUM)
997 (compare (match_operand:FP 0 "register_operand" "f")
998 (match_operand:FP 1 "const0_operand" "")))]
999 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1000 "lt<xde><bt>r\t%0,%0"
1001 [(set_attr "op_type" "RRE")
1002 (set_attr "type" "fsimp<mode>")])
1004 ; cxtr, cxbr, cdbr, cebr, cxb, cdb, ceb, cxbtr, cdbtr
1005 (define_insn "*cmp<mode>_ccs"
1006 [(set (reg CC_REGNUM)
1007 (compare (match_operand:FP 0 "register_operand" "f,f")
1008 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
1009 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
1013 [(set_attr "op_type" "RRE,RXE")
1014 (set_attr "type" "fsimp<mode>")])
1017 ; Compare and Branch instructions
1019 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
1020 ; The following instructions do a complementary access of their second
1021 ; operand (z01 only): crj_c, cgrjc, cr, cgr
1022 (define_insn "*cmp_and_br_signed_<mode>"
1024 (if_then_else (match_operator 0 "s390_signed_integer_comparison"
1025 [(match_operand:GPR 1 "register_operand" "d,d")
1026 (match_operand:GPR 2 "nonmemory_operand" "d,C")])
1027 (label_ref (match_operand 3 "" ""))
1029 (clobber (reg:CC CC_REGNUM))]
1032 if (get_attr_length (insn) == 6)
1033 return which_alternative ?
1034 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3";
1036 return which_alternative ?
1037 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3";
1039 [(set_attr "op_type" "RIE")
1040 (set_attr "type" "branch")
1041 (set_attr "z10prop" "z10_cobra,z10_super")
1042 (set (attr "length")
1043 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1044 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
1045 ; 10 byte for cgr/jg
1047 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
1048 ; The following instructions do a complementary access of their second
1049 ; operand (z10 only): clrj, clgrj, clr, clgr
1050 (define_insn "*cmp_and_br_unsigned_<mode>"
1052 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
1053 [(match_operand:GPR 1 "register_operand" "d,d")
1054 (match_operand:GPR 2 "nonmemory_operand" "d,I")])
1055 (label_ref (match_operand 3 "" ""))
1057 (clobber (reg:CC CC_REGNUM))]
1060 if (get_attr_length (insn) == 6)
1061 return which_alternative ?
1062 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3";
1064 return which_alternative ?
1065 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3";
1067 [(set_attr "op_type" "RIE")
1068 (set_attr "type" "branch")
1069 (set_attr "z10prop" "z10_cobra,z10_super")
1070 (set (attr "length")
1071 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
1072 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
1073 ; 10 byte for clgr/jg
1076 ;;- Move instructions.
1080 ; movti instruction pattern(s).
1083 (define_insn "movti"
1084 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
1085 (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
1092 [(set_attr "op_type" "RSY,RSY,*,*")
1093 (set_attr "type" "lm,stm,*,*")])
1096 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1097 (match_operand:TI 1 "general_operand" ""))]
1098 "TARGET_64BIT && reload_completed
1099 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
1100 [(set (match_dup 2) (match_dup 4))
1101 (set (match_dup 3) (match_dup 5))]
1103 operands[2] = operand_subword (operands[0], 0, 0, TImode);
1104 operands[3] = operand_subword (operands[0], 1, 0, TImode);
1105 operands[4] = operand_subword (operands[1], 0, 0, TImode);
1106 operands[5] = operand_subword (operands[1], 1, 0, TImode);
1110 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1111 (match_operand:TI 1 "general_operand" ""))]
1112 "TARGET_64BIT && reload_completed
1113 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
1114 [(set (match_dup 2) (match_dup 4))
1115 (set (match_dup 3) (match_dup 5))]
1117 operands[2] = operand_subword (operands[0], 1, 0, TImode);
1118 operands[3] = operand_subword (operands[0], 0, 0, TImode);
1119 operands[4] = operand_subword (operands[1], 1, 0, TImode);
1120 operands[5] = operand_subword (operands[1], 0, 0, TImode);
1124 [(set (match_operand:TI 0 "register_operand" "")
1125 (match_operand:TI 1 "memory_operand" ""))]
1126 "TARGET_64BIT && reload_completed
1127 && !s_operand (operands[1], VOIDmode)"
1128 [(set (match_dup 0) (match_dup 1))]
1130 rtx addr = operand_subword (operands[0], 1, 0, TImode);
1131 s390_load_address (addr, XEXP (operands[1], 0));
1132 operands[1] = replace_equiv_address (operands[1], addr);
1137 ; Patterns used for secondary reloads
1140 ; z10 provides move instructions accepting larl memory operands.
1141 ; Unfortunately there is no such variant for QI, TI and FP mode moves.
1142 ; These patterns are also used for unaligned SI and DI accesses.
1144 (define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
1145 [(parallel [(match_operand:INTALL 0 "memory_operand" "")
1146 (match_operand:INTALL 1 "register_operand" "=d")
1147 (match_operand:P 2 "register_operand" "=&a")])]
1150 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1154 (define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
1155 [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
1156 (match_operand:INTALL 1 "memory_operand" "")
1157 (match_operand:P 2 "register_operand" "=a")])]
1160 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1164 (define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
1165 [(parallel [(match_operand:FPALL 0 "memory_operand" "")
1166 (match_operand:FPALL 1 "register_operand" "=d")
1167 (match_operand:P 2 "register_operand" "=&a")])]
1170 s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
1174 (define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
1175 [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
1176 (match_operand:FPALL 1 "memory_operand" "")
1177 (match_operand:P 2 "register_operand" "=a")])]
1180 s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
1184 (define_expand "reload<P:mode>_larl_odd_addend_z10"
1185 [(parallel [(match_operand:P 0 "register_operand" "=d")
1186 (match_operand:P 1 "larl_operand" "")
1187 (match_operand:P 2 "register_operand" "=a")])]
1190 s390_reload_larl_operand (operands[0], operands[1], operands[2]);
1194 ; Handles loading a PLUS (load address) expression
1196 (define_expand "reload<mode>_plus"
1197 [(parallel [(match_operand:P 0 "register_operand" "=a")
1198 (match_operand:P 1 "s390_plus_operand" "")
1199 (match_operand:P 2 "register_operand" "=&a")])]
1202 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1206 ; Handles assessing a non-offsetable memory address
1208 (define_expand "reload<mode>_nonoffmem_in"
1209 [(parallel [(match_operand 0 "register_operand" "")
1210 (match_operand 1 "" "")
1211 (match_operand:P 2 "register_operand" "=&a")])]
1214 gcc_assert (MEM_P (operands[1]));
1215 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
1216 operands[1] = replace_equiv_address (operands[1], operands[2]);
1217 emit_move_insn (operands[0], operands[1]);
1221 (define_expand "reload<mode>_nonoffmem_out"
1222 [(parallel [(match_operand 0 "" "")
1223 (match_operand 1 "register_operand" "")
1224 (match_operand:P 2 "register_operand" "=&a")])]
1227 gcc_assert (MEM_P (operands[0]));
1228 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1229 operands[0] = replace_equiv_address (operands[0], operands[2]);
1230 emit_move_insn (operands[0], operands[1]);
1234 (define_expand "reload<mode>_PIC_addr"
1235 [(parallel [(match_operand 0 "register_operand" "=d")
1236 (match_operand 1 "larl_operand" "")
1237 (match_operand:P 2 "register_operand" "=a")])]
1240 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]);
1241 emit_move_insn (operands[0], new_rtx);
1245 ; movdi instruction pattern(s).
1248 (define_expand "movdi"
1249 [(set (match_operand:DI 0 "general_operand" "")
1250 (match_operand:DI 1 "general_operand" ""))]
1253 /* Handle symbolic constants. */
1255 && (SYMBOLIC_CONST (operands[1])
1256 || (GET_CODE (operands[1]) == PLUS
1257 && XEXP (operands[1], 0) == pic_offset_table_rtx
1258 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
1259 emit_symbolic_move (operands);
1262 (define_insn "*movdi_larl"
1263 [(set (match_operand:DI 0 "register_operand" "=d")
1264 (match_operand:DI 1 "larl_operand" "X"))]
1266 && !FP_REG_P (operands[0])"
1268 [(set_attr "op_type" "RIL")
1269 (set_attr "type" "larl")
1270 (set_attr "z10prop" "z10_super_A1")])
1272 (define_insn "*movdi_64"
1273 [(set (match_operand:DI 0 "nonimmediate_operand"
1274 "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
1275 RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
1276 (match_operand:DI 1 "general_operand"
1277 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
1278 d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
1307 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
1308 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
1309 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
1310 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
1312 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
1313 z10,*,*,*,*,*,longdisp,*,longdisp,
1315 (set_attr "z10prop" "z10_fwd_A1,
1344 [(set (match_operand:DI 0 "register_operand" "")
1345 (match_operand:DI 1 "register_operand" ""))]
1346 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
1347 [(set (match_dup 2) (match_dup 3))
1348 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1349 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1350 "operands[2] = gen_lowpart (SImode, operands[0]);
1351 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1354 [(set (match_operand:DI 0 "register_operand" "")
1355 (match_operand:DI 1 "register_operand" ""))]
1356 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1357 && dead_or_set_p (insn, operands[1])"
1358 [(set (match_dup 3) (match_dup 2))
1359 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1360 (set (match_dup 4) (match_dup 2))]
1361 "operands[2] = gen_lowpart (SImode, operands[1]);
1362 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1365 [(set (match_operand:DI 0 "register_operand" "")
1366 (match_operand:DI 1 "register_operand" ""))]
1367 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1368 && !dead_or_set_p (insn, operands[1])"
1369 [(set (match_dup 3) (match_dup 2))
1370 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1371 (set (match_dup 4) (match_dup 2))
1372 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1373 "operands[2] = gen_lowpart (SImode, operands[1]);
1374 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1376 (define_insn "*movdi_31"
1377 [(set (match_operand:DI 0 "nonimmediate_operand"
1378 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
1379 (match_operand:DI 1 "general_operand"
1380 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
1395 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
1396 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
1397 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
1399 ; For a load from a symbol ref we can use one of the target registers
1400 ; together with larl to load the address.
1402 [(set (match_operand:DI 0 "register_operand" "")
1403 (match_operand:DI 1 "memory_operand" ""))]
1404 "!TARGET_64BIT && reload_completed && TARGET_Z10
1405 && larl_operand (XEXP (operands[1], 0), SImode)"
1406 [(set (match_dup 2) (match_dup 3))
1407 (set (match_dup 0) (match_dup 1))]
1409 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1410 operands[3] = XEXP (operands[1], 0);
1411 operands[1] = replace_equiv_address (operands[1], operands[2]);
1415 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1416 (match_operand:DI 1 "general_operand" ""))]
1417 "!TARGET_64BIT && reload_completed
1418 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1419 [(set (match_dup 2) (match_dup 4))
1420 (set (match_dup 3) (match_dup 5))]
1422 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1423 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1424 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1425 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1429 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1430 (match_operand:DI 1 "general_operand" ""))]
1431 "!TARGET_64BIT && reload_completed
1432 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1433 [(set (match_dup 2) (match_dup 4))
1434 (set (match_dup 3) (match_dup 5))]
1436 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1437 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1438 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1439 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1443 [(set (match_operand:DI 0 "register_operand" "")
1444 (match_operand:DI 1 "memory_operand" ""))]
1445 "!TARGET_64BIT && reload_completed
1446 && !FP_REG_P (operands[0])
1447 && !s_operand (operands[1], VOIDmode)"
1448 [(set (match_dup 0) (match_dup 1))]
1450 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1451 s390_load_address (addr, XEXP (operands[1], 0));
1452 operands[1] = replace_equiv_address (operands[1], addr);
1456 [(set (match_operand:DI 0 "register_operand" "")
1457 (mem:DI (match_operand 1 "address_operand" "")))]
1459 && !FP_REG_P (operands[0])
1460 && GET_CODE (operands[1]) == SYMBOL_REF
1461 && CONSTANT_POOL_ADDRESS_P (operands[1])
1462 && get_pool_mode (operands[1]) == DImode
1463 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1464 [(set (match_dup 0) (match_dup 2))]
1465 "operands[2] = get_pool_constant (operands[1]);")
1467 (define_insn "*la_64"
1468 [(set (match_operand:DI 0 "register_operand" "=d,d")
1469 (match_operand:QI 1 "address_operand" "U,W"))]
1474 [(set_attr "op_type" "RX,RXY")
1475 (set_attr "type" "la")
1476 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1480 [(set (match_operand:DI 0 "register_operand" "")
1481 (match_operand:QI 1 "address_operand" ""))
1482 (clobber (reg:CC CC_REGNUM))])]
1484 && preferred_la_operand_p (operands[1], const0_rtx)"
1485 [(set (match_dup 0) (match_dup 1))]
1489 [(set (match_operand:DI 0 "register_operand" "")
1490 (match_operand:DI 1 "register_operand" ""))
1493 (plus:DI (match_dup 0)
1494 (match_operand:DI 2 "nonmemory_operand" "")))
1495 (clobber (reg:CC CC_REGNUM))])]
1497 && !reg_overlap_mentioned_p (operands[0], operands[2])
1498 && preferred_la_operand_p (operands[1], operands[2])"
1499 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1503 ; movsi instruction pattern(s).
1506 (define_expand "movsi"
1507 [(set (match_operand:SI 0 "general_operand" "")
1508 (match_operand:SI 1 "general_operand" ""))]
1511 /* Handle symbolic constants. */
1513 && (SYMBOLIC_CONST (operands[1])
1514 || (GET_CODE (operands[1]) == PLUS
1515 && XEXP (operands[1], 0) == pic_offset_table_rtx
1516 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1517 emit_symbolic_move (operands);
1520 (define_insn "*movsi_larl"
1521 [(set (match_operand:SI 0 "register_operand" "=d")
1522 (match_operand:SI 1 "larl_operand" "X"))]
1523 "!TARGET_64BIT && TARGET_CPU_ZARCH
1524 && !FP_REG_P (operands[0])"
1526 [(set_attr "op_type" "RIL")
1527 (set_attr "type" "larl")
1528 (set_attr "z10prop" "z10_super_A1")])
1530 (define_insn "*movsi_zarch"
1531 [(set (match_operand:SI 0 "nonimmediate_operand"
1532 "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
1533 (match_operand:SI 1 "general_operand"
1534 "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
1559 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
1560 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
1561 (set_attr "type" "*,
1583 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
1584 *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
1585 (set_attr "z10prop" "z10_fwd_A1,
1608 (define_insn "*movsi_esa"
1609 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
1610 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
1624 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
1625 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
1626 (set_attr "z10prop" "z10_fwd_A1,
1640 [(set (match_operand:SI 0 "register_operand" "")
1641 (mem:SI (match_operand 1 "address_operand" "")))]
1642 "!FP_REG_P (operands[0])
1643 && GET_CODE (operands[1]) == SYMBOL_REF
1644 && CONSTANT_POOL_ADDRESS_P (operands[1])
1645 && get_pool_mode (operands[1]) == SImode
1646 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1647 [(set (match_dup 0) (match_dup 2))]
1648 "operands[2] = get_pool_constant (operands[1]);")
1650 (define_insn "*la_31"
1651 [(set (match_operand:SI 0 "register_operand" "=d,d")
1652 (match_operand:QI 1 "address_operand" "U,W"))]
1653 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1657 [(set_attr "op_type" "RX,RXY")
1658 (set_attr "type" "la")
1659 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1663 [(set (match_operand:SI 0 "register_operand" "")
1664 (match_operand:QI 1 "address_operand" ""))
1665 (clobber (reg:CC CC_REGNUM))])]
1667 && preferred_la_operand_p (operands[1], const0_rtx)"
1668 [(set (match_dup 0) (match_dup 1))]
1672 [(set (match_operand:SI 0 "register_operand" "")
1673 (match_operand:SI 1 "register_operand" ""))
1676 (plus:SI (match_dup 0)
1677 (match_operand:SI 2 "nonmemory_operand" "")))
1678 (clobber (reg:CC CC_REGNUM))])]
1680 && !reg_overlap_mentioned_p (operands[0], operands[2])
1681 && preferred_la_operand_p (operands[1], operands[2])"
1682 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1685 (define_insn "*la_31_and"
1686 [(set (match_operand:SI 0 "register_operand" "=d,d")
1687 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1688 (const_int 2147483647)))]
1693 [(set_attr "op_type" "RX,RXY")
1694 (set_attr "type" "la")
1695 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1697 (define_insn_and_split "*la_31_and_cc"
1698 [(set (match_operand:SI 0 "register_operand" "=d")
1699 (and:SI (match_operand:QI 1 "address_operand" "p")
1700 (const_int 2147483647)))
1701 (clobber (reg:CC CC_REGNUM))]
1704 "&& reload_completed"
1706 (and:SI (match_dup 1) (const_int 2147483647)))]
1708 [(set_attr "op_type" "RX")
1709 (set_attr "type" "la")])
1711 (define_insn "force_la_31"
1712 [(set (match_operand:SI 0 "register_operand" "=d,d")
1713 (match_operand:QI 1 "address_operand" "U,W"))
1714 (use (const_int 0))]
1719 [(set_attr "op_type" "RX")
1720 (set_attr "type" "la")
1721 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
1724 ; movhi instruction pattern(s).
1727 (define_expand "movhi"
1728 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1729 (match_operand:HI 1 "general_operand" ""))]
1732 /* Make it explicit that loading a register from memory
1733 always sign-extends (at least) to SImode. */
1734 if (optimize && can_create_pseudo_p ()
1735 && register_operand (operands[0], VOIDmode)
1736 && GET_CODE (operands[1]) == MEM)
1738 rtx tmp = gen_reg_rtx (SImode);
1739 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1740 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1741 operands[1] = gen_lowpart (HImode, tmp);
1745 (define_insn "*movhi"
1746 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
1747 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
1759 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
1760 (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
1761 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
1762 (set_attr "z10prop" "z10_fr_E1,
1773 [(set (match_operand:HI 0 "register_operand" "")
1774 (mem:HI (match_operand 1 "address_operand" "")))]
1775 "GET_CODE (operands[1]) == SYMBOL_REF
1776 && CONSTANT_POOL_ADDRESS_P (operands[1])
1777 && get_pool_mode (operands[1]) == HImode
1778 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1779 [(set (match_dup 0) (match_dup 2))]
1780 "operands[2] = get_pool_constant (operands[1]);")
1783 ; movqi instruction pattern(s).
1786 (define_expand "movqi"
1787 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1788 (match_operand:QI 1 "general_operand" ""))]
1791 /* On z/Architecture, zero-extending from memory to register
1792 is just as fast as a QImode load. */
1793 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1794 && register_operand (operands[0], VOIDmode)
1795 && GET_CODE (operands[1]) == MEM)
1797 rtx tmp = gen_reg_rtx (word_mode);
1798 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1799 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1800 operands[1] = gen_lowpart (QImode, tmp);
1804 (define_insn "*movqi"
1805 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S")
1806 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n"))]
1817 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY")
1818 (set_attr "type" "lr,*,*,*,store,store,store,store")
1819 (set_attr "z10prop" "z10_fr_E1,
1829 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1830 (mem:QI (match_operand 1 "address_operand" "")))]
1831 "GET_CODE (operands[1]) == SYMBOL_REF
1832 && CONSTANT_POOL_ADDRESS_P (operands[1])
1833 && get_pool_mode (operands[1]) == QImode
1834 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1835 [(set (match_dup 0) (match_dup 2))]
1836 "operands[2] = get_pool_constant (operands[1]);")
1839 ; movstrictqi instruction pattern(s).
1842 (define_insn "*movstrictqi"
1843 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1844 (match_operand:QI 1 "memory_operand" "R,T"))]
1849 [(set_attr "op_type" "RX,RXY")
1850 (set_attr "z10prop" "z10_super_E1,z10_super")])
1853 ; movstricthi instruction pattern(s).
1856 (define_insn "*movstricthi"
1857 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1858 (match_operand:HI 1 "memory_operand" "Q,S"))
1859 (clobber (reg:CC CC_REGNUM))]
1864 [(set_attr "op_type" "RS,RSY")
1865 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
1868 ; movstrictsi instruction pattern(s).
1871 (define_insn "movstrictsi"
1872 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1873 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1880 [(set_attr "op_type" "RR,RX,RXY,RRE")
1881 (set_attr "type" "lr,load,load,*")
1882 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
1885 ; mov(tf|td) instruction pattern(s).
1888 (define_expand "mov<mode>"
1889 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1890 (match_operand:TD_TF 1 "general_operand" ""))]
1894 (define_insn "*mov<mode>_64"
1895 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
1896 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
1907 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
1908 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")])
1910 (define_insn "*mov<mode>_31"
1911 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
1912 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
1919 [(set_attr "op_type" "RRE,RRE,*,*")
1920 (set_attr "type" "fsimptf,fsimptf,*,*")])
1922 ; TFmode in GPRs splitters
1925 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1926 (match_operand:TD_TF 1 "general_operand" ""))]
1927 "TARGET_64BIT && reload_completed
1928 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
1929 [(set (match_dup 2) (match_dup 4))
1930 (set (match_dup 3) (match_dup 5))]
1932 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
1933 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
1934 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
1935 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
1939 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1940 (match_operand:TD_TF 1 "general_operand" ""))]
1941 "TARGET_64BIT && reload_completed
1942 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
1943 [(set (match_dup 2) (match_dup 4))
1944 (set (match_dup 3) (match_dup 5))]
1946 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
1947 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
1948 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
1949 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
1953 [(set (match_operand:TD_TF 0 "register_operand" "")
1954 (match_operand:TD_TF 1 "memory_operand" ""))]
1955 "TARGET_64BIT && reload_completed
1956 && !FP_REG_P (operands[0])
1957 && !s_operand (operands[1], VOIDmode)"
1958 [(set (match_dup 0) (match_dup 1))]
1960 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
1961 s390_load_address (addr, XEXP (operands[1], 0));
1962 operands[1] = replace_equiv_address (operands[1], addr);
1965 ; TFmode in BFPs splitters
1968 [(set (match_operand:TD_TF 0 "register_operand" "")
1969 (match_operand:TD_TF 1 "memory_operand" ""))]
1970 "reload_completed && offsettable_memref_p (operands[1])
1971 && FP_REG_P (operands[0])"
1972 [(set (match_dup 2) (match_dup 4))
1973 (set (match_dup 3) (match_dup 5))]
1975 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
1977 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
1979 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
1980 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
1984 [(set (match_operand:TD_TF 0 "memory_operand" "")
1985 (match_operand:TD_TF 1 "register_operand" ""))]
1986 "reload_completed && offsettable_memref_p (operands[0])
1987 && FP_REG_P (operands[1])"
1988 [(set (match_dup 2) (match_dup 4))
1989 (set (match_dup 3) (match_dup 5))]
1991 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
1992 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
1993 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
1995 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
2000 ; mov(df|dd) instruction pattern(s).
2003 (define_expand "mov<mode>"
2004 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2005 (match_operand:DD_DF 1 "general_operand" ""))]
2009 (define_insn "*mov<mode>_64dfp"
2010 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2011 "=f,f,f,d,f,f,R,T,d, d,RT")
2012 (match_operand:DD_DF 1 "general_operand"
2013 " G,f,d,f,R,T,f,f,d,RT, d"))]
2014 "TARGET_64BIT && TARGET_DFP"
2027 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
2028 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
2029 fstoredf,fstoredf,lr,load,store")
2030 (set_attr "z10prop" "*,
2043 (define_insn "*mov<mode>_64"
2044 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
2045 (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))]
2057 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
2058 (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
2059 fstore<mode>,fstore<mode>,lr,load,store")
2060 (set_attr "z10prop" "*,
2070 (define_insn "*mov<mode>_31"
2071 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
2072 "=f,f,f,f,R,T,d,d,Q,S, d,o")
2073 (match_operand:DD_DF 1 "general_operand"
2074 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
2089 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
2090 (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
2091 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")])
2094 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2095 (match_operand:DD_DF 1 "general_operand" ""))]
2096 "!TARGET_64BIT && reload_completed
2097 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
2098 [(set (match_dup 2) (match_dup 4))
2099 (set (match_dup 3) (match_dup 5))]
2101 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
2102 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
2103 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
2104 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
2108 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
2109 (match_operand:DD_DF 1 "general_operand" ""))]
2110 "!TARGET_64BIT && reload_completed
2111 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
2112 [(set (match_dup 2) (match_dup 4))
2113 (set (match_dup 3) (match_dup 5))]
2115 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
2116 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
2117 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
2118 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
2122 [(set (match_operand:DD_DF 0 "register_operand" "")
2123 (match_operand:DD_DF 1 "memory_operand" ""))]
2124 "!TARGET_64BIT && reload_completed
2125 && !FP_REG_P (operands[0])
2126 && !s_operand (operands[1], VOIDmode)"
2127 [(set (match_dup 0) (match_dup 1))]
2129 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
2130 s390_load_address (addr, XEXP (operands[1], 0));
2131 operands[1] = replace_equiv_address (operands[1], addr);
2135 ; mov(sf|sd) instruction pattern(s).
2138 (define_insn "mov<mode>"
2139 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
2140 "=f,f,f,f,R,T,d,d,d,R,T")
2141 (match_operand:SD_SF 1 "general_operand"
2142 " G,f,R,T,f,f,d,R,T,d,d"))]
2156 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
2157 (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
2158 fstore<mode>,fstore<mode>,lr,load,load,store,store")
2159 (set_attr "z10prop" "*,
2172 ; movcc instruction pattern
2175 (define_insn "movcc"
2176 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
2177 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
2187 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
2188 (set_attr "type" "lr,*,*,store,store,load,load")
2189 (set_attr "z10prop" "z10_fr_E1,*,*,z10_super,z10_rec,z10_fwd_A3,z10_fwd_A3")])
2192 ; Block move (MVC) patterns.
2196 [(set (match_operand:BLK 0 "memory_operand" "=Q")
2197 (match_operand:BLK 1 "memory_operand" "Q"))
2198 (use (match_operand 2 "const_int_operand" "n"))]
2199 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
2200 "mvc\t%O0(%2,%R0),%S1"
2201 [(set_attr "op_type" "SS")])
2205 [(set (match_operand:BLK 0 "memory_operand" "")
2206 (match_operand:BLK 1 "memory_operand" ""))
2207 (use (match_operand 2 "const_int_operand" ""))])
2209 [(set (match_operand:BLK 3 "memory_operand" "")
2210 (match_operand:BLK 4 "memory_operand" ""))
2211 (use (match_operand 5 "const_int_operand" ""))])]
2212 "s390_offset_p (operands[0], operands[3], operands[2])
2213 && s390_offset_p (operands[1], operands[4], operands[2])
2214 && !s390_overlap_p (operands[0], operands[1],
2215 INTVAL (operands[2]) + INTVAL (operands[5]))
2216 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
2218 [(set (match_dup 6) (match_dup 7))
2219 (use (match_dup 8))])]
2220 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
2221 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
2222 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
2226 ; load_multiple pattern(s).
2228 ; ??? Due to reload problems with replacing registers inside match_parallel
2229 ; we currently support load_multiple/store_multiple only after reload.
2232 (define_expand "load_multiple"
2233 [(match_par_dup 3 [(set (match_operand 0 "" "")
2234 (match_operand 1 "" ""))
2235 (use (match_operand 2 "" ""))])]
2238 enum machine_mode mode;
2244 /* Support only loading a constant number of fixed-point registers from
2245 memory and only bother with this if more than two */
2246 if (GET_CODE (operands[2]) != CONST_INT
2247 || INTVAL (operands[2]) < 2
2248 || INTVAL (operands[2]) > 16
2249 || GET_CODE (operands[1]) != MEM
2250 || GET_CODE (operands[0]) != REG
2251 || REGNO (operands[0]) >= 16)
2254 count = INTVAL (operands[2]);
2255 regno = REGNO (operands[0]);
2256 mode = GET_MODE (operands[0]);
2257 if (mode != SImode && mode != word_mode)
2260 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2261 if (!can_create_pseudo_p ())
2263 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2265 from = XEXP (operands[1], 0);
2268 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
2269 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
2270 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
2272 from = XEXP (XEXP (operands[1], 0), 0);
2273 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2280 from = force_reg (Pmode, XEXP (operands[1], 0));
2284 for (i = 0; i < count; i++)
2285 XVECEXP (operands[3], 0, i)
2286 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
2287 change_address (operands[1], mode,
2288 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
2291 (define_insn "*load_multiple_di"
2292 [(match_parallel 0 "load_multiple_operation"
2293 [(set (match_operand:DI 1 "register_operand" "=r")
2294 (match_operand:DI 2 "s_operand" "QS"))])]
2295 "reload_completed && word_mode == DImode"
2297 int words = XVECLEN (operands[0], 0);
2298 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
2299 return "lmg\t%1,%0,%S2";
2301 [(set_attr "op_type" "RSY")
2302 (set_attr "type" "lm")])
2304 (define_insn "*load_multiple_si"
2305 [(match_parallel 0 "load_multiple_operation"
2306 [(set (match_operand:SI 1 "register_operand" "=r,r")
2307 (match_operand:SI 2 "s_operand" "Q,S"))])]
2310 int words = XVECLEN (operands[0], 0);
2311 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
2312 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
2314 [(set_attr "op_type" "RS,RSY")
2315 (set_attr "type" "lm")])
2318 ; store multiple pattern(s).
2321 (define_expand "store_multiple"
2322 [(match_par_dup 3 [(set (match_operand 0 "" "")
2323 (match_operand 1 "" ""))
2324 (use (match_operand 2 "" ""))])]
2327 enum machine_mode mode;
2333 /* Support only storing a constant number of fixed-point registers to
2334 memory and only bother with this if more than two. */
2335 if (GET_CODE (operands[2]) != CONST_INT
2336 || INTVAL (operands[2]) < 2
2337 || INTVAL (operands[2]) > 16
2338 || GET_CODE (operands[0]) != MEM
2339 || GET_CODE (operands[1]) != REG
2340 || REGNO (operands[1]) >= 16)
2343 count = INTVAL (operands[2]);
2344 regno = REGNO (operands[1]);
2345 mode = GET_MODE (operands[1]);
2346 if (mode != SImode && mode != word_mode)
2349 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2351 if (!can_create_pseudo_p ())
2353 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2355 to = XEXP (operands[0], 0);
2358 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
2359 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
2360 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
2362 to = XEXP (XEXP (operands[0], 0), 0);
2363 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2370 to = force_reg (Pmode, XEXP (operands[0], 0));
2374 for (i = 0; i < count; i++)
2375 XVECEXP (operands[3], 0, i)
2376 = gen_rtx_SET (VOIDmode,
2377 change_address (operands[0], mode,
2378 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
2379 gen_rtx_REG (mode, regno + i));
2382 (define_insn "*store_multiple_di"
2383 [(match_parallel 0 "store_multiple_operation"
2384 [(set (match_operand:DI 1 "s_operand" "=QS")
2385 (match_operand:DI 2 "register_operand" "r"))])]
2386 "reload_completed && word_mode == DImode"
2388 int words = XVECLEN (operands[0], 0);
2389 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2390 return "stmg\t%2,%0,%S1";
2392 [(set_attr "op_type" "RSY")
2393 (set_attr "type" "stm")])
2396 (define_insn "*store_multiple_si"
2397 [(match_parallel 0 "store_multiple_operation"
2398 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2399 (match_operand:SI 2 "register_operand" "r,r"))])]
2402 int words = XVECLEN (operands[0], 0);
2403 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2404 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2406 [(set_attr "op_type" "RS,RSY")
2407 (set_attr "type" "stm")])
2410 ;; String instructions.
2413 (define_insn "*execute_rl"
2414 [(match_parallel 0 ""
2415 [(unspec [(match_operand 1 "register_operand" "a")
2416 (match_operand 2 "" "")
2417 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])]
2418 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2419 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2421 [(set_attr "op_type" "RIL")
2422 (set_attr "type" "cs")])
2424 (define_insn "*execute"
2425 [(match_parallel 0 ""
2426 [(unspec [(match_operand 1 "register_operand" "a")
2427 (match_operand:BLK 2 "memory_operand" "R")
2428 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2429 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2430 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2432 [(set_attr "op_type" "RX")
2433 (set_attr "type" "cs")])
2437 ; strlenM instruction pattern(s).
2440 (define_expand "strlen<mode>"
2441 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2444 (unspec:P [(const_int 0)
2445 (match_operand:BLK 1 "memory_operand" "")
2447 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2448 (clobber (scratch:P))
2449 (clobber (reg:CC CC_REGNUM))])
2451 [(set (match_operand:P 0 "register_operand" "")
2452 (minus:P (match_dup 4) (match_dup 5)))
2453 (clobber (reg:CC CC_REGNUM))])]
2456 operands[4] = gen_reg_rtx (Pmode);
2457 operands[5] = gen_reg_rtx (Pmode);
2458 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2459 operands[1] = replace_equiv_address (operands[1], operands[5]);
2462 (define_insn "*strlen<mode>"
2463 [(set (match_operand:P 0 "register_operand" "=a")
2464 (unspec:P [(match_operand:P 2 "general_operand" "0")
2465 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2467 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2468 (clobber (match_scratch:P 1 "=a"))
2469 (clobber (reg:CC CC_REGNUM))]
2471 "srst\t%0,%1\;jo\t.-4"
2472 [(set_attr "length" "8")
2473 (set_attr "type" "vs")])
2476 ; cmpstrM instruction pattern(s).
2479 (define_expand "cmpstrsi"
2480 [(set (reg:SI 0) (const_int 0))
2482 [(clobber (match_operand 3 "" ""))
2483 (clobber (match_dup 4))
2484 (set (reg:CCU CC_REGNUM)
2485 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2486 (match_operand:BLK 2 "memory_operand" "")))
2489 [(set (match_operand:SI 0 "register_operand" "=d")
2490 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2491 (clobber (reg:CC CC_REGNUM))])]
2494 /* As the result of CMPINT is inverted compared to what we need,
2495 we have to swap the operands. */
2496 rtx op1 = operands[2];
2497 rtx op2 = operands[1];
2498 rtx addr1 = gen_reg_rtx (Pmode);
2499 rtx addr2 = gen_reg_rtx (Pmode);
2501 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2502 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2503 operands[1] = replace_equiv_address_nv (op1, addr1);
2504 operands[2] = replace_equiv_address_nv (op2, addr2);
2505 operands[3] = addr1;
2506 operands[4] = addr2;
2509 (define_insn "*cmpstr<mode>"
2510 [(clobber (match_operand:P 0 "register_operand" "=d"))
2511 (clobber (match_operand:P 1 "register_operand" "=d"))
2512 (set (reg:CCU CC_REGNUM)
2513 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2514 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2517 "clst\t%0,%1\;jo\t.-4"
2518 [(set_attr "length" "8")
2519 (set_attr "type" "vs")])
2522 ; movstr instruction pattern.
2525 (define_expand "movstr"
2526 [(set (reg:SI 0) (const_int 0))
2528 [(clobber (match_dup 3))
2529 (set (match_operand:BLK 1 "memory_operand" "")
2530 (match_operand:BLK 2 "memory_operand" ""))
2531 (set (match_operand 0 "register_operand" "")
2532 (unspec [(match_dup 1)
2534 (reg:SI 0)] UNSPEC_MVST))
2535 (clobber (reg:CC CC_REGNUM))])]
2538 rtx addr1 = gen_reg_rtx (Pmode);
2539 rtx addr2 = gen_reg_rtx (Pmode);
2541 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2542 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2543 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2544 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2545 operands[3] = addr2;
2548 (define_insn "*movstr"
2549 [(clobber (match_operand:P 2 "register_operand" "=d"))
2550 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2551 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2552 (set (match_operand:P 0 "register_operand" "=d")
2553 (unspec [(mem:BLK (match_dup 1))
2554 (mem:BLK (match_dup 3))
2555 (reg:SI 0)] UNSPEC_MVST))
2556 (clobber (reg:CC CC_REGNUM))]
2558 "mvst\t%1,%2\;jo\t.-4"
2559 [(set_attr "length" "8")
2560 (set_attr "type" "vs")])
2564 ; movmemM instruction pattern(s).
2567 (define_expand "movmem<mode>"
2568 [(set (match_operand:BLK 0 "memory_operand" "") ; destination
2569 (match_operand:BLK 1 "memory_operand" "")) ; source
2570 (use (match_operand:GPR 2 "general_operand" "")) ; count
2571 (match_operand 3 "" "")]
2573 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2575 ; Move a block that is up to 256 bytes in length.
2576 ; The block length is taken as (operands[2] % 256) + 1.
2578 (define_expand "movmem_short"
2580 [(set (match_operand:BLK 0 "memory_operand" "")
2581 (match_operand:BLK 1 "memory_operand" ""))
2582 (use (match_operand 2 "nonmemory_operand" ""))
2583 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2584 (clobber (match_dup 3))])]
2586 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2588 (define_insn "*movmem_short"
2589 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2590 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))
2591 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2592 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2593 (clobber (match_scratch 4 "=X,X,X,&a"))]
2594 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2595 && GET_MODE (operands[4]) == Pmode"
2597 [(set_attr "type" "cs")
2598 (set_attr "cpu_facility" "*,*,z10,*")])
2601 [(set (match_operand:BLK 0 "memory_operand" "")
2602 (match_operand:BLK 1 "memory_operand" ""))
2603 (use (match_operand 2 "const_int_operand" ""))
2604 (use (match_operand 3 "immediate_operand" ""))
2605 (clobber (scratch))]
2608 [(set (match_dup 0) (match_dup 1))
2609 (use (match_dup 2))])]
2610 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2613 [(set (match_operand:BLK 0 "memory_operand" "")
2614 (match_operand:BLK 1 "memory_operand" ""))
2615 (use (match_operand 2 "register_operand" ""))
2616 (use (match_operand 3 "memory_operand" ""))
2617 (clobber (scratch))]
2620 [(unspec [(match_dup 2) (match_dup 3)
2621 (const_int 0)] UNSPEC_EXECUTE)
2622 (set (match_dup 0) (match_dup 1))
2623 (use (const_int 1))])]
2627 [(set (match_operand:BLK 0 "memory_operand" "")
2628 (match_operand:BLK 1 "memory_operand" ""))
2629 (use (match_operand 2 "register_operand" ""))
2630 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2631 (clobber (scratch))]
2632 "TARGET_Z10 && reload_completed"
2634 [(unspec [(match_dup 2) (const_int 0)
2635 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2636 (set (match_dup 0) (match_dup 1))
2637 (use (const_int 1))])]
2638 "operands[3] = gen_label_rtx ();")
2641 [(set (match_operand:BLK 0 "memory_operand" "")
2642 (match_operand:BLK 1 "memory_operand" ""))
2643 (use (match_operand 2 "register_operand" ""))
2644 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2645 (clobber (match_operand 3 "register_operand" ""))]
2646 "reload_completed && TARGET_CPU_ZARCH"
2647 [(set (match_dup 3) (label_ref (match_dup 4)))
2649 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2650 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2651 (set (match_dup 0) (match_dup 1))
2652 (use (const_int 1))])]
2653 "operands[4] = gen_label_rtx ();")
2655 ; Move a block of arbitrary length.
2657 (define_expand "movmem_long"
2659 [(clobber (match_dup 2))
2660 (clobber (match_dup 3))
2661 (set (match_operand:BLK 0 "memory_operand" "")
2662 (match_operand:BLK 1 "memory_operand" ""))
2663 (use (match_operand 2 "general_operand" ""))
2665 (clobber (reg:CC CC_REGNUM))])]
2668 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2669 rtx reg0 = gen_reg_rtx (dword_mode);
2670 rtx reg1 = gen_reg_rtx (dword_mode);
2671 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2672 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2673 rtx len0 = gen_lowpart (Pmode, reg0);
2674 rtx len1 = gen_lowpart (Pmode, reg1);
2676 emit_clobber (reg0);
2677 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2678 emit_move_insn (len0, operands[2]);
2680 emit_clobber (reg1);
2681 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2682 emit_move_insn (len1, operands[2]);
2684 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2685 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2690 (define_insn "*movmem_long"
2691 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2692 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2693 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2694 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2697 (clobber (reg:CC CC_REGNUM))]
2699 "mvcle\t%0,%1,0\;jo\t.-4"
2700 [(set_attr "length" "8")
2701 (set_attr "type" "vs")])
2708 (define_expand "signbit<mode>2"
2709 [(set (reg:CCZ CC_REGNUM)
2710 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2713 (set (match_operand:SI 0 "register_operand" "=d")
2714 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2717 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2720 (define_expand "isinf<mode>2"
2721 [(set (reg:CCZ CC_REGNUM)
2722 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f")
2725 (set (match_operand:SI 0 "register_operand" "=d")
2726 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2729 operands[2] = GEN_INT (S390_TDC_INFINITY);
2732 ; This insn is used to generate all variants of the Test Data Class
2733 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2734 ; is the register to be tested and the second one is the bit mask
2735 ; specifying the required test(s).
2737 (define_insn "*TDC_insn_<mode>"
2738 [(set (reg:CCZ CC_REGNUM)
2739 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f")
2740 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2742 "t<_d>c<xde><bt>\t%0,%1"
2743 [(set_attr "op_type" "RXE")
2744 (set_attr "type" "fsimp<mode>")])
2746 (define_insn_and_split "*ccz_to_int"
2747 [(set (match_operand:SI 0 "register_operand" "=d")
2748 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2749 UNSPEC_CCZ_TO_INT))]
2753 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2757 ; setmemM instruction pattern(s).
2760 (define_expand "setmem<mode>"
2761 [(set (match_operand:BLK 0 "memory_operand" "")
2762 (match_operand:QI 2 "general_operand" ""))
2763 (use (match_operand:GPR 1 "general_operand" ""))
2764 (match_operand 3 "" "")]
2766 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2768 ; Clear a block that is up to 256 bytes in length.
2769 ; The block length is taken as (operands[1] % 256) + 1.
2771 (define_expand "clrmem_short"
2773 [(set (match_operand:BLK 0 "memory_operand" "")
2775 (use (match_operand 1 "nonmemory_operand" ""))
2776 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2777 (clobber (match_dup 2))
2778 (clobber (reg:CC CC_REGNUM))])]
2780 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2782 (define_insn "*clrmem_short"
2783 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q")
2785 (use (match_operand 1 "nonmemory_operand" "n,a,a,a"))
2786 (use (match_operand 2 "immediate_operand" "X,R,X,X"))
2787 (clobber (match_scratch 3 "=X,X,X,&a"))
2788 (clobber (reg:CC CC_REGNUM))]
2789 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2790 && GET_MODE (operands[3]) == Pmode"
2792 [(set_attr "type" "cs")
2793 (set_attr "cpu_facility" "*,*,z10,*")])
2796 [(set (match_operand:BLK 0 "memory_operand" "")
2798 (use (match_operand 1 "const_int_operand" ""))
2799 (use (match_operand 2 "immediate_operand" ""))
2801 (clobber (reg:CC CC_REGNUM))]
2804 [(set (match_dup 0) (const_int 0))
2806 (clobber (reg:CC CC_REGNUM))])]
2807 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2810 [(set (match_operand:BLK 0 "memory_operand" "")
2812 (use (match_operand 1 "register_operand" ""))
2813 (use (match_operand 2 "memory_operand" ""))
2815 (clobber (reg:CC CC_REGNUM))]
2818 [(unspec [(match_dup 1) (match_dup 2)
2819 (const_int 0)] UNSPEC_EXECUTE)
2820 (set (match_dup 0) (const_int 0))
2822 (clobber (reg:CC CC_REGNUM))])]
2826 [(set (match_operand:BLK 0 "memory_operand" "")
2828 (use (match_operand 1 "register_operand" ""))
2829 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2831 (clobber (reg:CC CC_REGNUM))]
2832 "TARGET_Z10 && reload_completed"
2834 [(unspec [(match_dup 1) (const_int 0)
2835 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2836 (set (match_dup 0) (const_int 0))
2838 (clobber (reg:CC CC_REGNUM))])]
2839 "operands[3] = gen_label_rtx ();")
2842 [(set (match_operand:BLK 0 "memory_operand" "")
2844 (use (match_operand 1 "register_operand" ""))
2845 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2846 (clobber (match_operand 2 "register_operand" ""))
2847 (clobber (reg:CC CC_REGNUM))]
2848 "reload_completed && TARGET_CPU_ZARCH"
2849 [(set (match_dup 2) (label_ref (match_dup 3)))
2851 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2852 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2853 (set (match_dup 0) (const_int 0))
2855 (clobber (reg:CC CC_REGNUM))])]
2856 "operands[3] = gen_label_rtx ();")
2858 ; Initialize a block of arbitrary length with (operands[2] % 256).
2860 (define_expand "setmem_long"
2862 [(clobber (match_dup 1))
2863 (set (match_operand:BLK 0 "memory_operand" "")
2864 (match_operand 2 "shift_count_or_setmem_operand" ""))
2865 (use (match_operand 1 "general_operand" ""))
2867 (clobber (reg:CC CC_REGNUM))])]
2870 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2871 rtx reg0 = gen_reg_rtx (dword_mode);
2872 rtx reg1 = gen_reg_rtx (dword_mode);
2873 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2874 rtx len0 = gen_lowpart (Pmode, reg0);
2876 emit_clobber (reg0);
2877 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2878 emit_move_insn (len0, operands[1]);
2880 emit_move_insn (reg1, const0_rtx);
2882 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2887 (define_insn "*setmem_long"
2888 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2889 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2890 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2892 (use (match_operand:<DBL> 1 "register_operand" "d"))
2893 (clobber (reg:CC CC_REGNUM))]
2895 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2896 [(set_attr "length" "8")
2897 (set_attr "type" "vs")])
2899 (define_insn "*setmem_long_and"
2900 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2901 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2902 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2903 (match_operand 4 "const_int_operand" "n")))
2905 (use (match_operand:<DBL> 1 "register_operand" "d"))
2906 (clobber (reg:CC CC_REGNUM))]
2907 "(INTVAL (operands[4]) & 255) == 255"
2908 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2909 [(set_attr "length" "8")
2910 (set_attr "type" "vs")])
2912 ; cmpmemM instruction pattern(s).
2915 (define_expand "cmpmemsi"
2916 [(set (match_operand:SI 0 "register_operand" "")
2917 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2918 (match_operand:BLK 2 "memory_operand" "") ) )
2919 (use (match_operand:SI 3 "general_operand" ""))
2920 (use (match_operand:SI 4 "" ""))]
2922 "s390_expand_cmpmem (operands[0], operands[1],
2923 operands[2], operands[3]); DONE;")
2925 ; Compare a block that is up to 256 bytes in length.
2926 ; The block length is taken as (operands[2] % 256) + 1.
2928 (define_expand "cmpmem_short"
2930 [(set (reg:CCU CC_REGNUM)
2931 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2932 (match_operand:BLK 1 "memory_operand" "")))
2933 (use (match_operand 2 "nonmemory_operand" ""))
2934 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2935 (clobber (match_dup 3))])]
2937 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2939 (define_insn "*cmpmem_short"
2940 [(set (reg:CCU CC_REGNUM)
2941 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q")
2942 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")))
2943 (use (match_operand 2 "nonmemory_operand" "n,a,a,a"))
2944 (use (match_operand 3 "immediate_operand" "X,R,X,X"))
2945 (clobber (match_scratch 4 "=X,X,X,&a"))]
2946 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2947 && GET_MODE (operands[4]) == Pmode"
2949 [(set_attr "type" "cs")
2950 (set_attr "cpu_facility" "*,*,z10,*")])
2953 [(set (reg:CCU CC_REGNUM)
2954 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2955 (match_operand:BLK 1 "memory_operand" "")))
2956 (use (match_operand 2 "const_int_operand" ""))
2957 (use (match_operand 3 "immediate_operand" ""))
2958 (clobber (scratch))]
2961 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2962 (use (match_dup 2))])]
2963 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2966 [(set (reg:CCU CC_REGNUM)
2967 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2968 (match_operand:BLK 1 "memory_operand" "")))
2969 (use (match_operand 2 "register_operand" ""))
2970 (use (match_operand 3 "memory_operand" ""))
2971 (clobber (scratch))]
2974 [(unspec [(match_dup 2) (match_dup 3)
2975 (const_int 0)] UNSPEC_EXECUTE)
2976 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2977 (use (const_int 1))])]
2981 [(set (reg:CCU CC_REGNUM)
2982 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2983 (match_operand:BLK 1 "memory_operand" "")))
2984 (use (match_operand 2 "register_operand" ""))
2985 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2986 (clobber (scratch))]
2987 "TARGET_Z10 && reload_completed"
2989 [(unspec [(match_dup 2) (const_int 0)
2990 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2991 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2992 (use (const_int 1))])]
2993 "operands[4] = gen_label_rtx ();")
2996 [(set (reg:CCU CC_REGNUM)
2997 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2998 (match_operand:BLK 1 "memory_operand" "")))
2999 (use (match_operand 2 "register_operand" ""))
3000 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
3001 (clobber (match_operand 3 "register_operand" ""))]
3002 "reload_completed && TARGET_CPU_ZARCH"
3003 [(set (match_dup 3) (label_ref (match_dup 4)))
3005 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
3006 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
3007 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
3008 (use (const_int 1))])]
3009 "operands[4] = gen_label_rtx ();")
3011 ; Compare a block of arbitrary length.
3013 (define_expand "cmpmem_long"
3015 [(clobber (match_dup 2))
3016 (clobber (match_dup 3))
3017 (set (reg:CCU CC_REGNUM)
3018 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
3019 (match_operand:BLK 1 "memory_operand" "")))
3020 (use (match_operand 2 "general_operand" ""))
3021 (use (match_dup 3))])]
3024 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
3025 rtx reg0 = gen_reg_rtx (dword_mode);
3026 rtx reg1 = gen_reg_rtx (dword_mode);
3027 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
3028 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
3029 rtx len0 = gen_lowpart (Pmode, reg0);
3030 rtx len1 = gen_lowpart (Pmode, reg1);
3032 emit_clobber (reg0);
3033 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
3034 emit_move_insn (len0, operands[2]);
3036 emit_clobber (reg1);
3037 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
3038 emit_move_insn (len1, operands[2]);
3040 operands[0] = replace_equiv_address_nv (operands[0], addr0);
3041 operands[1] = replace_equiv_address_nv (operands[1], addr1);
3046 (define_insn "*cmpmem_long"
3047 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
3048 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
3049 (set (reg:CCU CC_REGNUM)
3050 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
3051 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
3053 (use (match_dup 3))]
3055 "clcle\t%0,%1,0\;jo\t.-4"
3056 [(set_attr "length" "8")
3057 (set_attr "type" "vs")])
3059 ; Convert CCUmode condition code to integer.
3060 ; Result is zero if EQ, positive if LTU, negative if GTU.
3062 (define_insn_and_split "cmpint"
3063 [(set (match_operand:SI 0 "register_operand" "=d")
3064 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3066 (clobber (reg:CC CC_REGNUM))]
3070 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3072 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
3073 (clobber (reg:CC CC_REGNUM))])])
3075 (define_insn_and_split "*cmpint_cc"
3076 [(set (reg CC_REGNUM)
3077 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3080 (set (match_operand:SI 0 "register_operand" "=d")
3081 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
3082 "s390_match_ccmode (insn, CCSmode)"
3084 "&& reload_completed"
3085 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
3087 [(set (match_dup 2) (match_dup 3))
3088 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
3090 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
3091 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3092 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3095 (define_insn_and_split "*cmpint_sign"
3096 [(set (match_operand:DI 0 "register_operand" "=d")
3097 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3098 UNSPEC_CCU_TO_INT)))
3099 (clobber (reg:CC CC_REGNUM))]
3102 "&& reload_completed"
3103 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3105 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
3106 (clobber (reg:CC CC_REGNUM))])])
3108 (define_insn_and_split "*cmpint_sign_cc"
3109 [(set (reg CC_REGNUM)
3110 (compare (ashiftrt:DI (ashift:DI (subreg:DI
3111 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
3112 UNSPEC_CCU_TO_INT) 0)
3113 (const_int 32)) (const_int 32))
3115 (set (match_operand:DI 0 "register_operand" "=d")
3116 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
3117 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
3119 "&& reload_completed"
3120 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
3122 [(set (match_dup 2) (match_dup 3))
3123 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
3125 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
3126 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
3127 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
3132 ;;- Conversion instructions.
3135 (define_insn "*sethighpartsi"
3136 [(set (match_operand:SI 0 "register_operand" "=d,d")
3137 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
3138 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3139 (clobber (reg:CC CC_REGNUM))]
3144 [(set_attr "op_type" "RS,RSY")
3145 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3147 (define_insn "*sethighpartdi_64"
3148 [(set (match_operand:DI 0 "register_operand" "=d")
3149 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
3150 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
3151 (clobber (reg:CC CC_REGNUM))]
3154 [(set_attr "op_type" "RSY")])
3156 (define_insn "*sethighpartdi_31"
3157 [(set (match_operand:DI 0 "register_operand" "=d,d")
3158 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
3159 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
3160 (clobber (reg:CC CC_REGNUM))]
3165 [(set_attr "op_type" "RS,RSY")
3166 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3169 (define_insn_and_split "*extzv<mode>"
3170 [(set (match_operand:GPR 0 "register_operand" "=d")
3171 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3172 (match_operand 2 "const_int_operand" "n")
3174 (clobber (reg:CC CC_REGNUM))]
3175 "INTVAL (operands[2]) > 0
3176 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3178 "&& reload_completed"
3180 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3181 (clobber (reg:CC CC_REGNUM))])
3182 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
3184 int bitsize = INTVAL (operands[2]);
3185 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3186 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3188 operands[1] = adjust_address (operands[1], BLKmode, 0);
3189 set_mem_size (operands[1], GEN_INT (size));
3190 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3191 operands[3] = GEN_INT (mask);
3194 (define_insn_and_split "*extv<mode>"
3195 [(set (match_operand:GPR 0 "register_operand" "=d")
3196 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
3197 (match_operand 2 "const_int_operand" "n")
3199 (clobber (reg:CC CC_REGNUM))]
3200 "INTVAL (operands[2]) > 0
3201 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
3203 "&& reload_completed"
3205 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
3206 (clobber (reg:CC CC_REGNUM))])
3208 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3209 (clobber (reg:CC CC_REGNUM))])]
3211 int bitsize = INTVAL (operands[2]);
3212 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
3213 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
3215 operands[1] = adjust_address (operands[1], BLKmode, 0);
3216 set_mem_size (operands[1], GEN_INT (size));
3217 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
3218 operands[3] = GEN_INT (mask);
3222 ; insv instruction patterns
3225 (define_expand "insv"
3226 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
3227 (match_operand 1 "const_int_operand" "")
3228 (match_operand 2 "const_int_operand" ""))
3229 (match_operand 3 "general_operand" ""))]
3232 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
3237 (define_insn "*insv<mode>_z10"
3238 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
3239 (match_operand 1 "const_int_operand" "I")
3240 (match_operand 2 "const_int_operand" "I"))
3241 (match_operand:GPR 3 "nonimmediate_operand" "d"))
3242 (clobber (reg:CC CC_REGNUM))]
3244 && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
3245 GET_MODE_BITSIZE (<MODE>mode)"
3247 int start = INTVAL (operands[2]);
3248 int size = INTVAL (operands[1]);
3249 int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
3251 operands[2] = GEN_INT (offset + start); /* start bit position */
3252 operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */
3253 operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
3254 start - size); /* left shift count */
3256 return "risbg\t%0,%3,%b2,%b1,%b4";
3258 [(set_attr "op_type" "RIE")
3259 (set_attr "z10prop" "z10_super_E1")])
3261 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3262 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
3263 (define_insn "*insv<mode>_z10_noshift"
3264 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3265 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3266 (match_operand 2 "const_int_operand" "n"))
3267 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
3268 (match_operand 4 "const_int_operand" "n"))))
3269 (clobber (reg:CC CC_REGNUM))]
3271 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3272 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)
3273 && INTVAL (operands[2]) == ~(INTVAL (operands[4]))"
3279 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3280 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3282 operands[5] = GEN_INT (64 - start - size); /* start bit position */
3283 operands[6] = GEN_INT (64 - 1 - start); /* end bit position */
3284 operands[7] = const0_rtx; /* left shift count */
3286 return "risbg\t%0,%1,%b5,%b6,%b7";
3288 [(set_attr "op_type" "RIE")
3289 (set_attr "z10prop" "z10_super_E1")])
3291 ; and op1 with a mask being 1 for the selected bits and 0 for the rest
3292 (define_insn "*insv<mode>_or_z10_noshift"
3293 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
3294 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
3295 (match_operand 2 "const_int_operand" "n"))
3296 (match_operand:GPR 3 "nonimmediate_operand" "0")))
3297 (clobber (reg:CC CC_REGNUM))]
3299 && s390_contiguous_bitmask_p (INTVAL (operands[2]),
3300 GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)"
3305 s390_contiguous_bitmask_p (INTVAL (operands[2]),
3306 GET_MODE_BITSIZE (<MODE>mode), &start, &size);
3308 operands[4] = GEN_INT (64 - start - size); /* start bit position */
3309 operands[5] = GEN_INT (64 - 1 - start); /* end bit position */
3310 operands[6] = const0_rtx; /* left shift count */
3312 return "rosbg\t%0,%1,%b4,%b5,%b6";
3314 [(set_attr "op_type" "RIE")])
3316 (define_insn "*insv<mode>_mem_reg"
3317 [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
3318 (match_operand 1 "const_int_operand" "n,n")
3320 (match_operand:P 2 "register_operand" "d,d"))]
3321 "INTVAL (operands[1]) > 0
3322 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3323 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3325 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3327 operands[1] = GEN_INT ((1ul << size) - 1);
3328 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
3329 : "stcmy\t%2,%1,%S0";
3331 [(set_attr "op_type" "RS,RSY")
3332 (set_attr "z10prop" "z10_super,z10_super")])
3334 (define_insn "*insvdi_mem_reghigh"
3335 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
3336 (match_operand 1 "const_int_operand" "n")
3338 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
3341 && INTVAL (operands[1]) > 0
3342 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
3343 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
3345 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
3347 operands[1] = GEN_INT ((1ul << size) - 1);
3348 return "stcmh\t%2,%1,%S0";
3350 [(set_attr "op_type" "RSY")
3351 (set_attr "z10prop" "z10_super")])
3353 (define_insn "*insv<mode>_reg_imm"
3354 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
3356 (match_operand 1 "const_int_operand" "n"))
3357 (match_operand:P 2 "const_int_operand" "n"))]
3359 && INTVAL (operands[1]) >= 0
3360 && INTVAL (operands[1]) < BITS_PER_WORD
3361 && INTVAL (operands[1]) % 16 == 0"
3363 switch (BITS_PER_WORD - INTVAL (operands[1]))
3365 case 64: return "iihh\t%0,%x2"; break;
3366 case 48: return "iihl\t%0,%x2"; break;
3367 case 32: return "iilh\t%0,%x2"; break;
3368 case 16: return "iill\t%0,%x2"; break;
3369 default: gcc_unreachable();
3372 [(set_attr "op_type" "RI")
3373 (set_attr "z10prop" "z10_super_E1")])
3376 (define_insn "*insv<mode>_reg_extimm"
3377 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
3379 (match_operand 1 "const_int_operand" "n"))
3380 (match_operand:P 2 "const_int_operand" "n"))]
3382 && INTVAL (operands[1]) >= 0
3383 && INTVAL (operands[1]) < BITS_PER_WORD
3384 && INTVAL (operands[1]) % 32 == 0"
3386 switch (BITS_PER_WORD - INTVAL (operands[1]))
3388 case 64: return "iihf\t%0,%o2"; break;
3389 case 32: return "iilf\t%0,%o2"; break;
3390 default: gcc_unreachable();
3393 [(set_attr "op_type" "RIL")
3394 (set_attr "z10prop" "z10_fwd_E1")])
3398 ; extendsidi2 instruction pattern(s).
3401 (define_expand "extendsidi2"
3402 [(set (match_operand:DI 0 "register_operand" "")
3403 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3408 emit_clobber (operands[0]);
3409 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
3410 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
3411 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
3416 (define_insn "*extendsidi2"
3417 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3418 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3424 [(set_attr "op_type" "RRE,RXY,RIL")
3425 (set_attr "type" "*,*,larl")
3426 (set_attr "cpu_facility" "*,*,z10")
3427 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3430 ; extend(hi|qi)(si|di)2 instruction pattern(s).
3433 (define_expand "extend<HQI:mode><DSI:mode>2"
3434 [(set (match_operand:DSI 0 "register_operand" "")
3435 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3438 if (<DSI:MODE>mode == DImode && !TARGET_64BIT)
3440 rtx tmp = gen_reg_rtx (SImode);
3441 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
3442 emit_insn (gen_extendsidi2 (operands[0], tmp));
3445 else if (!TARGET_EXTIMM)
3447 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
3448 GET_MODE_BITSIZE (<HQI:MODE>mode));
3450 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
3451 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
3452 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
3458 ; extendhidi2 instruction pattern(s).
3461 (define_insn "*extendhidi2_extimm"
3462 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3463 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
3464 "TARGET_64BIT && TARGET_EXTIMM"
3469 [(set_attr "op_type" "RRE,RXY,RIL")
3470 (set_attr "type" "*,*,larl")
3471 (set_attr "cpu_facility" "extimm,extimm,z10")
3472 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
3474 (define_insn "*extendhidi2"
3475 [(set (match_operand:DI 0 "register_operand" "=d")
3476 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
3479 [(set_attr "op_type" "RXY")
3480 (set_attr "z10prop" "z10_super_E1")])
3483 ; extendhisi2 instruction pattern(s).
3486 (define_insn "*extendhisi2_extimm"
3487 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3488 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))]
3495 [(set_attr "op_type" "RRE,RX,RXY,RIL")
3496 (set_attr "type" "*,*,*,larl")
3497 (set_attr "cpu_facility" "extimm,extimm,extimm,z10")
3498 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
3500 (define_insn "*extendhisi2"
3501 [(set (match_operand:SI 0 "register_operand" "=d,d")
3502 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
3507 [(set_attr "op_type" "RX,RXY")
3508 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3511 ; extendqi(si|di)2 instruction pattern(s).
3514 ; lbr, lgbr, lb, lgb
3515 (define_insn "*extendqi<mode>2_extimm"
3516 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3517 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
3522 [(set_attr "op_type" "RRE,RXY")
3523 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3526 (define_insn "*extendqi<mode>2"
3527 [(set (match_operand:GPR 0 "register_operand" "=d")
3528 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
3529 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
3531 [(set_attr "op_type" "RXY")
3532 (set_attr "z10prop" "z10_super_E1")])
3534 (define_insn_and_split "*extendqi<mode>2_short_displ"
3535 [(set (match_operand:GPR 0 "register_operand" "=d")
3536 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3537 (clobber (reg:CC CC_REGNUM))]
3538 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3540 "&& reload_completed"
3542 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3543 (clobber (reg:CC CC_REGNUM))])
3545 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3546 (clobber (reg:CC CC_REGNUM))])]
3548 operands[1] = adjust_address (operands[1], BLKmode, 0);
3549 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
3550 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
3551 - GET_MODE_BITSIZE (QImode));
3555 ; zero_extendsidi2 instruction pattern(s).
3558 (define_expand "zero_extendsidi2"
3559 [(set (match_operand:DI 0 "register_operand" "")
3560 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3565 emit_clobber (operands[0]);
3566 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3567 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3572 (define_insn "*zero_extendsidi2"
3573 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3574 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
3580 [(set_attr "op_type" "RRE,RXY,RIL")
3581 (set_attr "type" "*,*,larl")
3582 (set_attr "cpu_facility" "*,*,z10")
3583 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
3586 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3589 (define_insn "*llgt_sidi"
3590 [(set (match_operand:DI 0 "register_operand" "=d")
3591 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3592 (const_int 2147483647)))]
3595 [(set_attr "op_type" "RXE")
3596 (set_attr "z10prop" "z10_super_E1")])
3598 (define_insn_and_split "*llgt_sidi_split"
3599 [(set (match_operand:DI 0 "register_operand" "=d")
3600 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
3601 (const_int 2147483647)))
3602 (clobber (reg:CC CC_REGNUM))]
3605 "&& reload_completed"
3607 (and:DI (subreg:DI (match_dup 1) 0)
3608 (const_int 2147483647)))]
3611 (define_insn "*llgt_sisi"
3612 [(set (match_operand:SI 0 "register_operand" "=d,d")
3613 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
3614 (const_int 2147483647)))]
3619 [(set_attr "op_type" "RRE,RXE")
3620 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3622 (define_insn "*llgt_didi"
3623 [(set (match_operand:DI 0 "register_operand" "=d,d")
3624 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3625 (const_int 2147483647)))]
3630 [(set_attr "op_type" "RRE,RXE")
3631 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
3634 [(set (match_operand:GPR 0 "register_operand" "")
3635 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3636 (const_int 2147483647)))
3637 (clobber (reg:CC CC_REGNUM))]
3638 "TARGET_ZARCH && reload_completed"
3640 (and:GPR (match_dup 1)
3641 (const_int 2147483647)))]
3645 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3648 (define_expand "zero_extend<mode>di2"
3649 [(set (match_operand:DI 0 "register_operand" "")
3650 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3655 rtx tmp = gen_reg_rtx (SImode);
3656 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3657 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3660 else if (!TARGET_EXTIMM)
3662 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
3663 GET_MODE_BITSIZE(<MODE>mode));
3664 operands[1] = gen_lowpart (DImode, operands[1]);
3665 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3666 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3671 (define_expand "zero_extend<mode>si2"
3672 [(set (match_operand:SI 0 "register_operand" "")
3673 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3678 operands[1] = gen_lowpart (SImode, operands[1]);
3679 emit_insn (gen_andsi3 (operands[0], operands[1],
3680 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
3686 (define_insn "*zero_extendhi<mode>2_z10"
3687 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
3688 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
3694 [(set_attr "op_type" "RXY,RRE,RIL")
3695 (set_attr "type" "*,*,larl")
3696 (set_attr "cpu_facility" "*,*,z10")
3697 (set_attr "z10prop" "z10_fwd_A3")])
3699 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3700 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3701 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3702 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
3707 [(set_attr "op_type" "RRE,RXY")
3708 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")])
3711 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3712 [(set (match_operand:GPR 0 "register_operand" "=d")
3713 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
3714 "TARGET_ZARCH && !TARGET_EXTIMM"
3716 [(set_attr "op_type" "RXY")
3717 (set_attr "z10prop" "z10_fwd_A3")])
3719 (define_insn_and_split "*zero_extendhisi2_31"
3720 [(set (match_operand:SI 0 "register_operand" "=&d")
3721 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3722 (clobber (reg:CC CC_REGNUM))]
3725 "&& reload_completed"
3726 [(set (match_dup 0) (const_int 0))
3728 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3729 (clobber (reg:CC CC_REGNUM))])]
3730 "operands[2] = gen_lowpart (HImode, operands[0]);")
3732 (define_insn_and_split "*zero_extendqisi2_31"
3733 [(set (match_operand:SI 0 "register_operand" "=&d")
3734 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
3737 "&& reload_completed"
3738 [(set (match_dup 0) (const_int 0))
3739 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3740 "operands[2] = gen_lowpart (QImode, operands[0]);")
3743 ; zero_extendqihi2 instruction pattern(s).
3746 (define_expand "zero_extendqihi2"
3747 [(set (match_operand:HI 0 "register_operand" "")
3748 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3749 "TARGET_ZARCH && !TARGET_EXTIMM"
3751 operands[1] = gen_lowpart (HImode, operands[1]);
3752 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3756 (define_insn "*zero_extendqihi2_64"
3757 [(set (match_operand:HI 0 "register_operand" "=d")
3758 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3759 "TARGET_ZARCH && !TARGET_EXTIMM"
3761 [(set_attr "op_type" "RXY")
3762 (set_attr "z10prop" "z10_fwd_A3")])
3764 (define_insn_and_split "*zero_extendqihi2_31"
3765 [(set (match_operand:HI 0 "register_operand" "=&d")
3766 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
3769 "&& reload_completed"
3770 [(set (match_dup 0) (const_int 0))
3771 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3772 "operands[2] = gen_lowpart (QImode, operands[0]);")
3775 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
3778 (define_expand "fixuns_truncdddi2"
3780 [(set (match_operand:DI 0 "register_operand" "")
3781 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
3782 (clobber (match_scratch:TD 2 "=f"))])]
3786 rtx label1 = gen_label_rtx ();
3787 rtx label2 = gen_label_rtx ();
3788 rtx temp = gen_reg_rtx (TDmode);
3789 REAL_VALUE_TYPE cmp, sub;
3791 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3792 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3794 /* 2^63 can't be represented as 64bit DFP number with full precision. The
3795 solution is doing the check and the subtraction in TD mode and using a
3796 TD -> DI convert afterwards. */
3797 emit_insn (gen_extendddtd2 (temp, operands[1]));
3798 temp = force_reg (TDmode, temp);
3799 emit_insn (gen_cmptd (temp,
3800 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode)));
3801 emit_jump_insn (gen_blt (label1));
3802 emit_insn (gen_subtd3 (temp, temp,
3803 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3804 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3807 emit_label (label1);
3808 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3809 emit_label (label2);
3813 (define_expand "fixuns_trunctddi2"
3814 [(set (match_operand:DI 0 "register_operand" "")
3815 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))]
3818 rtx label1 = gen_label_rtx ();
3819 rtx label2 = gen_label_rtx ();
3820 rtx temp = gen_reg_rtx (TDmode);
3821 REAL_VALUE_TYPE cmp, sub;
3823 operands[1] = force_reg (TDmode, operands[1]);
3824 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3825 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3827 emit_insn (gen_cmptd (operands[1],
3828 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode)));
3829 emit_jump_insn (gen_blt (label1));
3830 emit_insn (gen_subtd3 (temp, operands[1],
3831 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3832 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3835 emit_label (label1);
3836 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3837 emit_label (label2);
3842 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2
3843 ; instruction pattern(s).
3846 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
3847 [(set (match_operand:GPR 0 "register_operand" "")
3848 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))]
3851 rtx label1 = gen_label_rtx ();
3852 rtx label2 = gen_label_rtx ();
3853 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
3854 REAL_VALUE_TYPE cmp, sub;
3856 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
3857 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
3858 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
3860 emit_insn (gen_cmp<BFP:mode> (operands[1],
3861 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode)));
3862 emit_jump_insn (gen_blt (label1));
3863 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
3864 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
3865 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
3869 emit_label (label1);
3870 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
3871 operands[1], GEN_INT (5)));
3872 emit_label (label2);
3876 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
3877 [(set (match_operand:GPR 0 "register_operand" "")
3878 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
3881 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
3886 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
3887 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
3888 [(set (match_operand:GPR 0 "register_operand" "=d")
3889 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
3890 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
3891 (clobber (reg:CC CC_REGNUM))]
3893 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
3894 [(set_attr "op_type" "RRE")
3895 (set_attr "type" "ftoi")])
3899 ; fix_trunc(td|dd)di2 instruction pattern(s).
3902 (define_expand "fix_trunc<mode>di2"
3903 [(set (match_operand:DI 0 "register_operand" "")
3904 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
3905 "TARGET_64BIT && TARGET_HARD_DFP"
3907 operands[1] = force_reg (<MODE>mode, operands[1]);
3908 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
3914 (define_insn "fix_trunc<DFP:mode>di2_dfp"
3915 [(set (match_operand:DI 0 "register_operand" "=d")
3916 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
3917 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3918 (clobber (reg:CC CC_REGNUM))]
3919 "TARGET_64BIT && TARGET_HARD_DFP"
3920 "cg<DFP:xde>tr\t%0,%h2,%1"
3921 [(set_attr "op_type" "RRF")
3922 (set_attr "type" "ftoidfp")])
3926 ; fix_trunctf(si|di)2 instruction pattern(s).
3929 (define_expand "fix_trunctf<mode>2"
3930 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
3931 (fix:GPR (match_operand:TF 1 "register_operand" "")))
3932 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
3933 (clobber (reg:CC CC_REGNUM))])]
3939 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
3942 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
3943 (define_insn "floatdi<mode>2"
3944 [(set (match_operand:FP 0 "register_operand" "=f")
3945 (float:FP (match_operand:DI 1 "register_operand" "d")))]
3946 "TARGET_64BIT && TARGET_HARD_FLOAT"
3947 "c<xde>g<bt>r\t%0,%1"
3948 [(set_attr "op_type" "RRE")
3949 (set_attr "type" "itof<mode>" )])
3951 ; cxfbr, cdfbr, cefbr
3952 (define_insn "floatsi<mode>2"
3953 [(set (match_operand:BFP 0 "register_operand" "=f")
3954 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
3957 [(set_attr "op_type" "RRE")
3958 (set_attr "type" "itof<mode>" )])
3962 ; truncdfsf2 instruction pattern(s).
3965 (define_insn "truncdfsf2"
3966 [(set (match_operand:SF 0 "register_operand" "=f")
3967 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3970 [(set_attr "op_type" "RRE")
3971 (set_attr "type" "ftruncdf")])
3974 ; trunctf(df|sf)2 instruction pattern(s).
3978 (define_insn "trunctf<mode>2"
3979 [(set (match_operand:DSF 0 "register_operand" "=f")
3980 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
3981 (clobber (match_scratch:TF 2 "=f"))]
3983 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
3984 [(set_attr "length" "6")
3985 (set_attr "type" "ftrunctf")])
3988 ; trunctddd2 and truncddsd2 instruction pattern(s).
3991 (define_insn "trunctddd2"
3992 [(set (match_operand:DD 0 "register_operand" "=f")
3993 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
3994 (clobber (match_scratch:TD 2 "=f"))]
3996 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
3997 [(set_attr "length" "6")
3998 (set_attr "type" "ftruncdd")])
4000 (define_insn "truncddsd2"
4001 [(set (match_operand:SD 0 "register_operand" "=f")
4002 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
4005 [(set_attr "op_type" "RRF")
4006 (set_attr "type" "ftruncsd")])
4009 ; extend(sf|df)(df|tf)2 instruction pattern(s).
4012 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
4013 (define_insn "extend<DSF:mode><BFP:mode>2"
4014 [(set (match_operand:BFP 0 "register_operand" "=f,f")
4015 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
4017 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
4019 l<BFP:xde><DSF:xde>br\t%0,%1
4020 l<BFP:xde><DSF:xde>b\t%0,%1"
4021 [(set_attr "op_type" "RRE,RXE")
4022 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
4025 ; extendddtd2 and extendsddd2 instruction pattern(s).
4028 (define_insn "extendddtd2"
4029 [(set (match_operand:TD 0 "register_operand" "=f")
4030 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
4033 [(set_attr "op_type" "RRF")
4034 (set_attr "type" "fsimptf")])
4036 (define_insn "extendsddd2"
4037 [(set (match_operand:DD 0 "register_operand" "=f")
4038 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
4041 [(set_attr "op_type" "RRF")
4042 (set_attr "type" "fsimptf")])
4044 ; Binary <-> Decimal floating point trunc patterns
4047 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
4048 [(set (reg:DFP_ALL FPR0_REGNUM)
4049 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4050 (use (reg:SI GPR0_REGNUM))
4051 (clobber (reg:CC CC_REGNUM))]
4055 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
4056 [(set (reg:BFP FPR0_REGNUM)
4057 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4058 (use (reg:SI GPR0_REGNUM))
4059 (clobber (reg:CC CC_REGNUM))]
4063 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
4064 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4065 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4067 [(set (reg:DFP_ALL FPR0_REGNUM)
4068 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
4069 (use (reg:SI GPR0_REGNUM))
4070 (clobber (reg:CC CC_REGNUM))])
4071 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4072 (reg:DFP_ALL FPR0_REGNUM))]
4074 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4076 HOST_WIDE_INT flags;
4078 flags = (PFPO_CONVERT |
4079 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4080 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4082 operands[2] = GEN_INT (flags);
4085 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
4086 [(set (reg:DFP_ALL FPR2_REGNUM)
4087 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4088 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4090 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
4091 (use (reg:SI GPR0_REGNUM))
4092 (clobber (reg:CC CC_REGNUM))])
4093 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4095 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
4097 HOST_WIDE_INT flags;
4099 flags = (PFPO_CONVERT |
4100 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4101 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4103 operands[2] = GEN_INT (flags);
4107 ; Binary <-> Decimal floating point extend patterns
4110 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
4111 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4112 (use (reg:SI GPR0_REGNUM))
4113 (clobber (reg:CC CC_REGNUM))]
4117 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
4118 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4119 (use (reg:SI GPR0_REGNUM))
4120 (clobber (reg:CC CC_REGNUM))]
4124 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
4125 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
4126 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4128 [(set (reg:DFP_ALL FPR0_REGNUM)
4129 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
4130 (use (reg:SI GPR0_REGNUM))
4131 (clobber (reg:CC CC_REGNUM))])
4132 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
4133 (reg:DFP_ALL FPR0_REGNUM))]
4135 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
4137 HOST_WIDE_INT flags;
4139 flags = (PFPO_CONVERT |
4140 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
4141 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
4143 operands[2] = GEN_INT (flags);
4146 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
4147 [(set (reg:DFP_ALL FPR2_REGNUM)
4148 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
4149 (set (reg:SI GPR0_REGNUM) (match_dup 2))
4151 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
4152 (use (reg:SI GPR0_REGNUM))
4153 (clobber (reg:CC CC_REGNUM))])
4154 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
4156 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
4158 HOST_WIDE_INT flags;
4160 flags = (PFPO_CONVERT |
4161 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
4162 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
4164 operands[2] = GEN_INT (flags);
4169 ;; ARITHMETIC OPERATIONS
4171 ; arithmetic operations set the ConditionCode,
4172 ; because of unpredictable Bits in Register for Halfword and Byte
4173 ; the ConditionCode can be set wrong in operations for Halfword and Byte
4176 ;;- Add instructions.
4180 ; addti3 instruction pattern(s).
4183 (define_insn_and_split "addti3"
4184 [(set (match_operand:TI 0 "register_operand" "=&d")
4185 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
4186 (match_operand:TI 2 "general_operand" "do") ) )
4187 (clobber (reg:CC CC_REGNUM))]
4190 "&& reload_completed"
4192 [(set (reg:CCL1 CC_REGNUM)
4193 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
4195 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
4197 [(set (match_dup 3) (plus:DI
4198 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))
4199 (match_dup 4)) (match_dup 5)))
4200 (clobber (reg:CC CC_REGNUM))])]
4201 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4202 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4203 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4204 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4205 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4206 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4209 ; adddi3 instruction pattern(s).
4212 (define_expand "adddi3"
4214 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4215 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4216 (match_operand:DI 2 "general_operand" "")))
4217 (clobber (reg:CC CC_REGNUM))])]
4221 (define_insn "*adddi3_sign"
4222 [(set (match_operand:DI 0 "register_operand" "=d,d")
4223 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4224 (match_operand:DI 1 "register_operand" "0,0")))
4225 (clobber (reg:CC CC_REGNUM))]
4230 [(set_attr "op_type" "RRE,RXY")])
4232 (define_insn "*adddi3_zero_cc"
4233 [(set (reg CC_REGNUM)
4234 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4235 (match_operand:DI 1 "register_operand" "0,0"))
4237 (set (match_operand:DI 0 "register_operand" "=d,d")
4238 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
4239 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4243 [(set_attr "op_type" "RRE,RXY")
4244 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4246 (define_insn "*adddi3_zero_cconly"
4247 [(set (reg CC_REGNUM)
4248 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4249 (match_operand:DI 1 "register_operand" "0,0"))
4251 (clobber (match_scratch:DI 0 "=d,d"))]
4252 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4256 [(set_attr "op_type" "RRE,RXY")
4257 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4259 (define_insn "*adddi3_zero"
4260 [(set (match_operand:DI 0 "register_operand" "=d,d")
4261 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
4262 (match_operand:DI 1 "register_operand" "0,0")))
4263 (clobber (reg:CC CC_REGNUM))]
4268 [(set_attr "op_type" "RRE,RXY")
4269 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
4271 (define_insn_and_split "*adddi3_31z"
4272 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4273 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4274 (match_operand:DI 2 "general_operand" "do") ) )
4275 (clobber (reg:CC CC_REGNUM))]
4276 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4278 "&& reload_completed"
4280 [(set (reg:CCL1 CC_REGNUM)
4281 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4283 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4285 [(set (match_dup 3) (plus:SI
4286 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))
4287 (match_dup 4)) (match_dup 5)))
4288 (clobber (reg:CC CC_REGNUM))])]
4289 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4290 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4291 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4292 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4293 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4294 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4296 (define_insn_and_split "*adddi3_31"
4297 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
4298 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
4299 (match_operand:DI 2 "general_operand" "do") ) )
4300 (clobber (reg:CC CC_REGNUM))]
4303 "&& reload_completed"
4305 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
4306 (clobber (reg:CC CC_REGNUM))])
4308 [(set (reg:CCL1 CC_REGNUM)
4309 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
4311 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
4313 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
4315 (label_ref (match_dup 9))))
4317 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
4318 (clobber (reg:CC CC_REGNUM))])
4320 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4321 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4322 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4323 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4324 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4325 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4326 operands[9] = gen_label_rtx ();")
4329 ; addsi3 instruction pattern(s).
4332 (define_expand "addsi3"
4334 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4335 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4336 (match_operand:SI 2 "general_operand" "")))
4337 (clobber (reg:CC CC_REGNUM))])]
4341 (define_insn "*addsi3_sign"
4342 [(set (match_operand:SI 0 "register_operand" "=d,d")
4343 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
4344 (match_operand:SI 1 "register_operand" "0,0")))
4345 (clobber (reg:CC CC_REGNUM))]
4350 [(set_attr "op_type" "RX,RXY")])
4353 ; add(di|si)3 instruction pattern(s).
4356 ; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
4357 (define_insn "*add<mode>3"
4358 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,QS")
4359 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
4360 (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T,C") ) )
4361 (clobber (reg:CC CC_REGNUM))]
4371 [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY")
4372 (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10")
4373 (set_attr "z10prop" "z10_super_E1,
4381 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4382 (define_insn "*add<mode>3_carry1_cc"
4383 [(set (reg CC_REGNUM)
4384 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4385 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4387 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d")
4388 (plus:GPR (match_dup 1) (match_dup 2)))]
4389 "s390_match_ccmode (insn, CCL1mode)"
4397 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4398 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4399 (set_attr "z10prop" "z10_super_E1,
4406 ; alr, al, aly, algr, alg
4407 (define_insn "*add<mode>3_carry1_cconly"
4408 [(set (reg CC_REGNUM)
4409 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4410 (match_operand:GPR 2 "general_operand" "d,R,T"))
4412 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4413 "s390_match_ccmode (insn, CCL1mode)"
4418 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4419 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4421 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4422 (define_insn "*add<mode>3_carry2_cc"
4423 [(set (reg CC_REGNUM)
4424 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4425 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4427 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
4428 (plus:GPR (match_dup 1) (match_dup 2)))]
4429 "s390_match_ccmode (insn, CCL1mode)"
4437 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4438 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4439 (set_attr "z10prop" "z10_super_E1,
4446 ; alr, al, aly, algr, alg
4447 (define_insn "*add<mode>3_carry2_cconly"
4448 [(set (reg CC_REGNUM)
4449 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4450 (match_operand:GPR 2 "general_operand" "d,R,T"))
4452 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4453 "s390_match_ccmode (insn, CCL1mode)"
4458 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4459 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4461 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
4462 (define_insn "*add<mode>3_cc"
4463 [(set (reg CC_REGNUM)
4464 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
4465 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
4467 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
4468 (plus:GPR (match_dup 1) (match_dup 2)))]
4469 "s390_match_ccmode (insn, CCLmode)"
4477 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
4478 (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
4479 (set_attr "z10prop" "z10_super_E1,
4486 ; alr, al, aly, algr, alg
4487 (define_insn "*add<mode>3_cconly"
4488 [(set (reg CC_REGNUM)
4489 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4490 (match_operand:GPR 2 "general_operand" "d,R,T"))
4492 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4493 "s390_match_ccmode (insn, CCLmode)"
4498 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4499 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4501 ; alr, al, aly, algr, alg
4502 (define_insn "*add<mode>3_cconly2"
4503 [(set (reg CC_REGNUM)
4504 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
4505 (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T"))))
4506 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4507 "s390_match_ccmode(insn, CCLmode)"
4512 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4513 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4515 ; ahi, afi, aghi, agfi, asi, agsi
4516 (define_insn "*add<mode>3_imm_cc"
4517 [(set (reg CC_REGNUM)
4518 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0,0")
4519 (match_operand:GPR 2 "const_int_operand" "K,Os,C"))
4521 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,QS")
4522 (plus:GPR (match_dup 1) (match_dup 2)))]
4523 "s390_match_ccmode (insn, CCAmode)
4524 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
4525 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")
4526 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\"))
4527 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
4532 [(set_attr "op_type" "RI,RIL,SIY")
4533 (set_attr "cpu_facility" "*,extimm,z10")
4534 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
4537 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
4540 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4541 (define_insn "add<mode>3"
4542 [(set (match_operand:FP 0 "register_operand" "=f, f")
4543 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4544 (match_operand:FP 2 "general_operand" " f,<Rf>")))
4545 (clobber (reg:CC CC_REGNUM))]
4548 a<xde><bt>r\t%0,<op1>%2
4550 [(set_attr "op_type" "<RRer>,RXE")
4551 (set_attr "type" "fsimp<mode>")])
4553 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4554 (define_insn "*add<mode>3_cc"
4555 [(set (reg CC_REGNUM)
4556 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4557 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4558 (match_operand:FP 3 "const0_operand" "")))
4559 (set (match_operand:FP 0 "register_operand" "=f,f")
4560 (plus:FP (match_dup 1) (match_dup 2)))]
4561 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4563 a<xde><bt>r\t%0,<op1>%2
4565 [(set_attr "op_type" "<RRer>,RXE")
4566 (set_attr "type" "fsimp<mode>")])
4568 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
4569 (define_insn "*add<mode>3_cconly"
4570 [(set (reg CC_REGNUM)
4571 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4572 (match_operand:FP 2 "general_operand" " f,<Rf>"))
4573 (match_operand:FP 3 "const0_operand" "")))
4574 (clobber (match_scratch:FP 0 "=f,f"))]
4575 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4577 a<xde><bt>r\t%0,<op1>%2
4579 [(set_attr "op_type" "<RRer>,RXE")
4580 (set_attr "type" "fsimp<mode>")])
4584 ;;- Subtract instructions.
4588 ; subti3 instruction pattern(s).
4591 (define_insn_and_split "subti3"
4592 [(set (match_operand:TI 0 "register_operand" "=&d")
4593 (minus:TI (match_operand:TI 1 "register_operand" "0")
4594 (match_operand:TI 2 "general_operand" "do") ) )
4595 (clobber (reg:CC CC_REGNUM))]
4598 "&& reload_completed"
4600 [(set (reg:CCL2 CC_REGNUM)
4601 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
4603 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4605 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4606 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4607 (clobber (reg:CC CC_REGNUM))])]
4608 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4609 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4610 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4611 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4612 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4613 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4616 ; subdi3 instruction pattern(s).
4619 (define_expand "subdi3"
4621 [(set (match_operand:DI 0 "register_operand" "")
4622 (minus:DI (match_operand:DI 1 "register_operand" "")
4623 (match_operand:DI 2 "general_operand" "")))
4624 (clobber (reg:CC CC_REGNUM))])]
4628 (define_insn "*subdi3_sign"
4629 [(set (match_operand:DI 0 "register_operand" "=d,d")
4630 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4631 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4632 (clobber (reg:CC CC_REGNUM))]
4637 [(set_attr "op_type" "RRE,RXY")
4638 (set_attr "z10prop" "z10_c,*")])
4640 (define_insn "*subdi3_zero_cc"
4641 [(set (reg CC_REGNUM)
4642 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4643 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4645 (set (match_operand:DI 0 "register_operand" "=d,d")
4646 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4647 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4651 [(set_attr "op_type" "RRE,RXY")
4652 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4654 (define_insn "*subdi3_zero_cconly"
4655 [(set (reg CC_REGNUM)
4656 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4657 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
4659 (clobber (match_scratch:DI 0 "=d,d"))]
4660 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4664 [(set_attr "op_type" "RRE,RXY")
4665 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4667 (define_insn "*subdi3_zero"
4668 [(set (match_operand:DI 0 "register_operand" "=d,d")
4669 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4670 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
4671 (clobber (reg:CC CC_REGNUM))]
4676 [(set_attr "op_type" "RRE,RXY")
4677 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")])
4679 (define_insn_and_split "*subdi3_31z"
4680 [(set (match_operand:DI 0 "register_operand" "=&d")
4681 (minus:DI (match_operand:DI 1 "register_operand" "0")
4682 (match_operand:DI 2 "general_operand" "do") ) )
4683 (clobber (reg:CC CC_REGNUM))]
4684 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4686 "&& reload_completed"
4688 [(set (reg:CCL2 CC_REGNUM)
4689 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4691 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4693 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
4694 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
4695 (clobber (reg:CC CC_REGNUM))])]
4696 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4697 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4698 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4699 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4700 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4701 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4703 (define_insn_and_split "*subdi3_31"
4704 [(set (match_operand:DI 0 "register_operand" "=&d")
4705 (minus:DI (match_operand:DI 1 "register_operand" "0")
4706 (match_operand:DI 2 "general_operand" "do") ) )
4707 (clobber (reg:CC CC_REGNUM))]
4710 "&& reload_completed"
4712 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4713 (clobber (reg:CC CC_REGNUM))])
4715 [(set (reg:CCL2 CC_REGNUM)
4716 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4718 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4720 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4722 (label_ref (match_dup 9))))
4724 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4725 (clobber (reg:CC CC_REGNUM))])
4727 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4728 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4729 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4730 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4731 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4732 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4733 operands[9] = gen_label_rtx ();")
4736 ; subsi3 instruction pattern(s).
4739 (define_expand "subsi3"
4741 [(set (match_operand:SI 0 "register_operand" "")
4742 (minus:SI (match_operand:SI 1 "register_operand" "")
4743 (match_operand:SI 2 "general_operand" "")))
4744 (clobber (reg:CC CC_REGNUM))])]
4748 (define_insn "*subsi3_sign"
4749 [(set (match_operand:SI 0 "register_operand" "=d,d")
4750 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4751 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4752 (clobber (reg:CC CC_REGNUM))]
4757 [(set_attr "op_type" "RX,RXY")])
4760 ; sub(di|si)3 instruction pattern(s).
4763 ; sr, s, sy, sgr, sg
4764 (define_insn "*sub<mode>3"
4765 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4766 (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4767 (match_operand:GPR 2 "general_operand" "d,R,T") ) )
4768 (clobber (reg:CC CC_REGNUM))]
4774 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4775 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4777 ; slr, sl, sly, slgr, slg
4778 (define_insn "*sub<mode>3_borrow_cc"
4779 [(set (reg CC_REGNUM)
4780 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4781 (match_operand:GPR 2 "general_operand" "d,R,T"))
4783 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4784 (minus:GPR (match_dup 1) (match_dup 2)))]
4785 "s390_match_ccmode (insn, CCL2mode)"
4790 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4791 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4793 ; slr, sl, sly, slgr, slg
4794 (define_insn "*sub<mode>3_borrow_cconly"
4795 [(set (reg CC_REGNUM)
4796 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4797 (match_operand:GPR 2 "general_operand" "d,R,T"))
4799 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4800 "s390_match_ccmode (insn, CCL2mode)"
4805 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4806 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4808 ; slr, sl, sly, slgr, slg
4809 (define_insn "*sub<mode>3_cc"
4810 [(set (reg CC_REGNUM)
4811 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4812 (match_operand:GPR 2 "general_operand" "d,R,T"))
4814 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4815 (minus:GPR (match_dup 1) (match_dup 2)))]
4816 "s390_match_ccmode (insn, CCLmode)"
4821 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4822 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4824 ; slr, sl, sly, slgr, slg
4825 (define_insn "*sub<mode>3_cc2"
4826 [(set (reg CC_REGNUM)
4827 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4828 (match_operand:GPR 2 "general_operand" "d,R,T")))
4829 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4830 (minus:GPR (match_dup 1) (match_dup 2)))]
4831 "s390_match_ccmode (insn, CCL3mode)"
4836 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4837 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4839 ; slr, sl, sly, slgr, slg
4840 (define_insn "*sub<mode>3_cconly"
4841 [(set (reg CC_REGNUM)
4842 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4843 (match_operand:GPR 2 "general_operand" "d,R,T"))
4845 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4846 "s390_match_ccmode (insn, CCLmode)"
4851 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4852 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4855 ; slr, sl, sly, slgr, slg
4856 (define_insn "*sub<mode>3_cconly2"
4857 [(set (reg CC_REGNUM)
4858 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4859 (match_operand:GPR 2 "general_operand" "d,R,T")))
4860 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4861 "s390_match_ccmode (insn, CCL3mode)"
4866 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
4867 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
4871 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
4874 ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
4875 (define_insn "sub<mode>3"
4876 [(set (match_operand:FP 0 "register_operand" "=f, f")
4877 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
4878 (match_operand:FP 2 "general_operand" "f,<Rf>")))
4879 (clobber (reg:CC CC_REGNUM))]
4882 s<xde><bt>r\t%0,<op1>%2
4884 [(set_attr "op_type" "<RRer>,RXE")
4885 (set_attr "type" "fsimp<mode>")])
4887 ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
4888 (define_insn "*sub<mode>3_cc"
4889 [(set (reg CC_REGNUM)
4890 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4891 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4892 (match_operand:FP 3 "const0_operand" "")))
4893 (set (match_operand:FP 0 "register_operand" "=f,f")
4894 (minus:FP (match_dup 1) (match_dup 2)))]
4895 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4897 s<xde><bt>r\t%0,<op1>%2
4899 [(set_attr "op_type" "<RRer>,RXE")
4900 (set_attr "type" "fsimp<mode>")])
4902 ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
4903 (define_insn "*sub<mode>3_cconly"
4904 [(set (reg CC_REGNUM)
4905 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4906 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4907 (match_operand:FP 3 "const0_operand" "")))
4908 (clobber (match_scratch:FP 0 "=f,f"))]
4909 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4911 s<xde><bt>r\t%0,<op1>%2
4913 [(set_attr "op_type" "<RRer>,RXE")
4914 (set_attr "type" "fsimp<mode>")])
4918 ;;- Conditional add/subtract instructions.
4922 ; add(di|si)cc instruction pattern(s).
4925 ; the following 4 patterns are used when the result of an add with
4926 ; carry is checked for an overflow condition
4928 ; op1 + op2 + c < op1
4930 ; alcr, alc, alcgr, alcg
4931 (define_insn "*add<mode>3_alc_carry1_cc"
4932 [(set (reg CC_REGNUM)
4934 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4935 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4936 (match_operand:GPR 2 "general_operand" "d,RT"))
4938 (set (match_operand:GPR 0 "register_operand" "=d,d")
4939 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
4940 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
4944 [(set_attr "op_type" "RRE,RXY")])
4946 ; alcr, alc, alcgr, alcg
4947 (define_insn "*add<mode>3_alc_carry1_cconly"
4948 [(set (reg CC_REGNUM)
4950 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4951 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4952 (match_operand:GPR 2 "general_operand" "d,RT"))
4954 (clobber (match_scratch:GPR 0 "=d,d"))]
4955 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
4959 [(set_attr "op_type" "RRE,RXY")])
4961 ; op1 + op2 + c < op2
4963 ; alcr, alc, alcgr, alcg
4964 (define_insn "*add<mode>3_alc_carry2_cc"
4965 [(set (reg CC_REGNUM)
4967 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4968 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4969 (match_operand:GPR 2 "general_operand" "d,RT"))
4971 (set (match_operand:GPR 0 "register_operand" "=d,d")
4972 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
4973 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
4977 [(set_attr "op_type" "RRE,RXY")])
4979 ; alcr, alc, alcgr, alcg
4980 (define_insn "*add<mode>3_alc_carry2_cconly"
4981 [(set (reg CC_REGNUM)
4983 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4984 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
4985 (match_operand:GPR 2 "general_operand" "d,RT"))
4987 (clobber (match_scratch:GPR 0 "=d,d"))]
4988 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
4992 [(set_attr "op_type" "RRE,RXY")])
4994 ; alcr, alc, alcgr, alcg
4995 (define_insn "*add<mode>3_alc_cc"
4996 [(set (reg CC_REGNUM)
4998 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
4999 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5000 (match_operand:GPR 2 "general_operand" "d,RT"))
5002 (set (match_operand:GPR 0 "register_operand" "=d,d")
5003 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
5004 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5008 [(set_attr "op_type" "RRE,RXY")])
5010 ; alcr, alc, alcgr, alcg
5011 (define_insn "*add<mode>3_alc"
5012 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5013 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
5014 (match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
5015 (match_operand:GPR 2 "general_operand" "d,RT")))
5016 (clobber (reg:CC CC_REGNUM))]
5021 [(set_attr "op_type" "RRE,RXY")])
5023 ; slbr, slb, slbgr, slbg
5024 (define_insn "*sub<mode>3_slb_cc"
5025 [(set (reg CC_REGNUM)
5027 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5028 (match_operand:GPR 2 "general_operand" "d,RT"))
5029 (match_operand:GPR 3 "s390_slb_comparison" ""))
5031 (set (match_operand:GPR 0 "register_operand" "=d,d")
5032 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
5033 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
5037 [(set_attr "op_type" "RRE,RXY")
5038 (set_attr "z10prop" "z10_c,*")])
5040 ; slbr, slb, slbgr, slbg
5041 (define_insn "*sub<mode>3_slb"
5042 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5043 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
5044 (match_operand:GPR 2 "general_operand" "d,RT"))
5045 (match_operand:GPR 3 "s390_slb_comparison" "")))
5046 (clobber (reg:CC CC_REGNUM))]
5051 [(set_attr "op_type" "RRE,RXY")
5052 (set_attr "z10prop" "z10_c,*")])
5054 (define_expand "add<mode>cc"
5055 [(match_operand:GPR 0 "register_operand" "")
5056 (match_operand 1 "comparison_operator" "")
5057 (match_operand:GPR 2 "register_operand" "")
5058 (match_operand:GPR 3 "const_int_operand" "")]
5060 "if (!s390_expand_addcc (GET_CODE (operands[1]),
5061 s390_compare_op0, s390_compare_op1,
5062 operands[0], operands[2],
5063 operands[3])) FAIL; DONE;")
5066 ; scond instruction pattern(s).
5069 (define_insn_and_split "*scond<mode>"
5070 [(set (match_operand:GPR 0 "register_operand" "=&d")
5071 (match_operand:GPR 1 "s390_alc_comparison" ""))
5072 (clobber (reg:CC CC_REGNUM))]
5075 "&& reload_completed"
5076 [(set (match_dup 0) (const_int 0))
5078 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0))
5080 (clobber (reg:CC CC_REGNUM))])]
5083 (define_insn_and_split "*scond<mode>_neg"
5084 [(set (match_operand:GPR 0 "register_operand" "=&d")
5085 (match_operand:GPR 1 "s390_slb_comparison" ""))
5086 (clobber (reg:CC CC_REGNUM))]
5089 "&& reload_completed"
5090 [(set (match_dup 0) (const_int 0))
5092 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
5094 (clobber (reg:CC CC_REGNUM))])
5096 [(set (match_dup 0) (neg:GPR (match_dup 0)))
5097 (clobber (reg:CC CC_REGNUM))])]
5101 (define_expand "s<code>"
5102 [(set (match_operand:SI 0 "register_operand" "")
5103 (SCOND (match_dup 0)
5106 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
5107 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
5109 (define_expand "seq"
5111 [(set (match_operand:SI 0 "register_operand" "=d")
5113 (clobber (reg:CC CC_REGNUM))])
5115 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
5116 (clobber (reg:CC CC_REGNUM))])]
5119 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
5121 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
5122 PUT_MODE (operands[1], SImode);
5125 (define_insn_and_split "*sne"
5126 [(set (match_operand:SI 0 "register_operand" "=d")
5127 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
5129 (clobber (reg:CC CC_REGNUM))]
5134 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
5135 (clobber (reg:CC CC_REGNUM))])])
5139 ;;- Multiply instructions.
5143 ; muldi3 instruction pattern(s).
5146 (define_insn "*muldi3_sign"
5147 [(set (match_operand:DI 0 "register_operand" "=d,d")
5148 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
5149 (match_operand:DI 1 "register_operand" "0,0")))]
5154 [(set_attr "op_type" "RRE,RXY")
5155 (set_attr "type" "imuldi")])
5157 (define_insn "muldi3"
5158 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
5159 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5160 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
5167 [(set_attr "op_type" "RRE,RI,RXY,RIL")
5168 (set_attr "type" "imuldi")
5169 (set_attr "cpu_facility" "*,*,*,z10")])
5172 ; mulsi3 instruction pattern(s).
5175 (define_insn "*mulsi3_sign"
5176 [(set (match_operand:SI 0 "register_operand" "=d,d")
5177 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
5178 (match_operand:SI 1 "register_operand" "0,0")))]
5183 [(set_attr "op_type" "RX,RXY")
5184 (set_attr "type" "imulhi")
5185 (set_attr "cpu_facility" "*,z10")])
5187 (define_insn "mulsi3"
5188 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
5189 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5190 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
5198 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
5199 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
5200 (set_attr "cpu_facility" "*,*,*,*,z10")])
5203 ; mulsidi3 instruction pattern(s).
5206 (define_insn "mulsidi3"
5207 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5208 (mult:DI (sign_extend:DI
5209 (match_operand:SI 1 "register_operand" "%0,0,0"))
5211 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
5217 [(set_attr "op_type" "RR,RX,RXY")
5218 (set_attr "type" "imulsi")
5219 (set_attr "cpu_facility" "*,*,z10")])
5222 ; umulsidi3 instruction pattern(s).
5225 (define_insn "umulsidi3"
5226 [(set (match_operand:DI 0 "register_operand" "=d,d")
5227 (mult:DI (zero_extend:DI
5228 (match_operand:SI 1 "register_operand" "%0,0"))
5230 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))]
5231 "!TARGET_64BIT && TARGET_CPU_ZARCH"
5235 [(set_attr "op_type" "RRE,RXY")
5236 (set_attr "type" "imulsi")])
5239 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
5242 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
5243 (define_insn "mul<mode>3"
5244 [(set (match_operand:FP 0 "register_operand" "=f,f")
5245 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
5246 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5249 m<xdee><bt>r\t%0,<op1>%2
5251 [(set_attr "op_type" "<RRer>,RXE")
5252 (set_attr "type" "fmul<mode>")])
5254 ; madbr, maebr, maxb, madb, maeb
5255 (define_insn "*fmadd<mode>"
5256 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5257 (plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f")
5258 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
5259 (match_operand:DSF 3 "register_operand" "0,0")))]
5260 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5264 [(set_attr "op_type" "RRE,RXE")
5265 (set_attr "type" "fmul<mode>")])
5267 ; msxbr, msdbr, msebr, msxb, msdb, mseb
5268 (define_insn "*fmsub<mode>"
5269 [(set (match_operand:DSF 0 "register_operand" "=f,f")
5270 (minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f")
5271 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
5272 (match_operand:DSF 3 "register_operand" "0,0")))]
5273 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5277 [(set_attr "op_type" "RRE,RXE")
5278 (set_attr "type" "fmul<mode>")])
5281 ;;- Divide and modulo instructions.
5285 ; divmoddi4 instruction pattern(s).
5288 (define_expand "divmoddi4"
5289 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5290 (div:DI (match_operand:DI 1 "register_operand" "")
5291 (match_operand:DI 2 "general_operand" "")))
5292 (set (match_operand:DI 3 "general_operand" "")
5293 (mod:DI (match_dup 1) (match_dup 2)))])
5294 (clobber (match_dup 4))]
5297 rtx insn, div_equal, mod_equal;
5299 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
5300 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
5302 operands[4] = gen_reg_rtx(TImode);
5303 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
5305 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5306 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5308 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5309 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5314 (define_insn "divmodtidi3"
5315 [(set (match_operand:TI 0 "register_operand" "=d,d")
5319 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5320 (match_operand:DI 2 "general_operand" "d,RT")))
5322 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
5327 [(set_attr "op_type" "RRE,RXY")
5328 (set_attr "type" "idiv")])
5330 (define_insn "divmodtisi3"
5331 [(set (match_operand:TI 0 "register_operand" "=d,d")
5335 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5337 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
5340 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
5345 [(set_attr "op_type" "RRE,RXY")
5346 (set_attr "type" "idiv")])
5349 ; udivmoddi4 instruction pattern(s).
5352 (define_expand "udivmoddi4"
5353 [(parallel [(set (match_operand:DI 0 "general_operand" "")
5354 (udiv:DI (match_operand:DI 1 "general_operand" "")
5355 (match_operand:DI 2 "nonimmediate_operand" "")))
5356 (set (match_operand:DI 3 "general_operand" "")
5357 (umod:DI (match_dup 1) (match_dup 2)))])
5358 (clobber (match_dup 4))]
5361 rtx insn, div_equal, mod_equal, equal;
5363 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
5364 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
5365 equal = gen_rtx_IOR (TImode,
5366 gen_rtx_ASHIFT (TImode,
5367 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
5369 gen_rtx_ZERO_EXTEND (TImode, div_equal));
5371 operands[4] = gen_reg_rtx(TImode);
5372 emit_clobber (operands[4]);
5373 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
5374 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
5376 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
5377 set_unique_reg_note (insn, REG_EQUAL, equal);
5379 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
5380 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5382 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
5383 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5388 (define_insn "udivmodtidi3"
5389 [(set (match_operand:TI 0 "register_operand" "=d,d")
5394 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
5396 (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
5400 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
5405 [(set_attr "op_type" "RRE,RXY")
5406 (set_attr "type" "idiv")])
5409 ; divmodsi4 instruction pattern(s).
5412 (define_expand "divmodsi4"
5413 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5414 (div:SI (match_operand:SI 1 "general_operand" "")
5415 (match_operand:SI 2 "nonimmediate_operand" "")))
5416 (set (match_operand:SI 3 "general_operand" "")
5417 (mod:SI (match_dup 1) (match_dup 2)))])
5418 (clobber (match_dup 4))]
5421 rtx insn, div_equal, mod_equal, equal;
5423 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
5424 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
5425 equal = gen_rtx_IOR (DImode,
5426 gen_rtx_ASHIFT (DImode,
5427 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5429 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5431 operands[4] = gen_reg_rtx(DImode);
5432 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
5434 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
5435 set_unique_reg_note (insn, REG_EQUAL, equal);
5437 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5438 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5440 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5441 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5446 (define_insn "divmoddisi3"
5447 [(set (match_operand:DI 0 "register_operand" "=d,d")
5452 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
5454 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
5458 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
5463 [(set_attr "op_type" "RR,RX")
5464 (set_attr "type" "idiv")])
5467 ; udivsi3 and umodsi3 instruction pattern(s).
5470 (define_expand "udivmodsi4"
5471 [(parallel [(set (match_operand:SI 0 "general_operand" "")
5472 (udiv:SI (match_operand:SI 1 "general_operand" "")
5473 (match_operand:SI 2 "nonimmediate_operand" "")))
5474 (set (match_operand:SI 3 "general_operand" "")
5475 (umod:SI (match_dup 1) (match_dup 2)))])
5476 (clobber (match_dup 4))]
5477 "!TARGET_64BIT && TARGET_CPU_ZARCH"
5479 rtx insn, div_equal, mod_equal, equal;
5481 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5482 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5483 equal = gen_rtx_IOR (DImode,
5484 gen_rtx_ASHIFT (DImode,
5485 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
5487 gen_rtx_ZERO_EXTEND (DImode, div_equal));
5489 operands[4] = gen_reg_rtx(DImode);
5490 emit_clobber (operands[4]);
5491 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
5492 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
5494 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
5495 set_unique_reg_note (insn, REG_EQUAL, equal);
5497 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
5498 set_unique_reg_note (insn, REG_EQUAL, div_equal);
5500 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
5501 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
5506 (define_insn "udivmoddisi3"
5507 [(set (match_operand:DI 0 "register_operand" "=d,d")
5512 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
5514 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
5518 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
5519 "!TARGET_64BIT && TARGET_CPU_ZARCH"
5523 [(set_attr "op_type" "RRE,RXY")
5524 (set_attr "type" "idiv")])
5526 (define_expand "udivsi3"
5527 [(set (match_operand:SI 0 "register_operand" "=d")
5528 (udiv:SI (match_operand:SI 1 "general_operand" "")
5529 (match_operand:SI 2 "general_operand" "")))
5530 (clobber (match_dup 3))]
5531 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
5533 rtx insn, udiv_equal, umod_equal, equal;
5535 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5536 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5537 equal = gen_rtx_IOR (DImode,
5538 gen_rtx_ASHIFT (DImode,
5539 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5541 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5543 operands[3] = gen_reg_rtx (DImode);
5545 if (CONSTANT_P (operands[2]))
5547 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5549 rtx label1 = gen_label_rtx ();
5551 operands[1] = make_safe_from (operands[1], operands[0]);
5552 emit_move_insn (operands[0], const0_rtx);
5553 emit_insn (gen_cmpsi (operands[1], operands[2]));
5554 emit_jump_insn (gen_bltu (label1));
5555 emit_move_insn (operands[0], const1_rtx);
5556 emit_label (label1);
5560 operands[2] = force_reg (SImode, operands[2]);
5561 operands[2] = make_safe_from (operands[2], operands[0]);
5563 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5564 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5566 set_unique_reg_note (insn, REG_EQUAL, equal);
5568 insn = emit_move_insn (operands[0],
5569 gen_lowpart (SImode, operands[3]));
5570 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5575 rtx label1 = gen_label_rtx ();
5576 rtx label2 = gen_label_rtx ();
5577 rtx label3 = gen_label_rtx ();
5579 operands[1] = force_reg (SImode, operands[1]);
5580 operands[1] = make_safe_from (operands[1], operands[0]);
5581 operands[2] = force_reg (SImode, operands[2]);
5582 operands[2] = make_safe_from (operands[2], operands[0]);
5584 emit_move_insn (operands[0], const0_rtx);
5585 emit_insn (gen_cmpsi (operands[2], operands[1]));
5586 emit_jump_insn (gen_bgtu (label3));
5587 emit_insn (gen_cmpsi (operands[2], const0_rtx));
5588 emit_jump_insn (gen_blt (label2));
5589 emit_insn (gen_cmpsi (operands[2], const1_rtx));
5590 emit_jump_insn (gen_beq (label1));
5591 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5592 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5594 set_unique_reg_note (insn, REG_EQUAL, equal);
5596 insn = emit_move_insn (operands[0],
5597 gen_lowpart (SImode, operands[3]));
5598 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
5601 emit_label (label1);
5602 emit_move_insn (operands[0], operands[1]);
5604 emit_label (label2);
5605 emit_move_insn (operands[0], const1_rtx);
5606 emit_label (label3);
5608 emit_move_insn (operands[0], operands[0]);
5612 (define_expand "umodsi3"
5613 [(set (match_operand:SI 0 "register_operand" "=d")
5614 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5615 (match_operand:SI 2 "nonimmediate_operand" "")))
5616 (clobber (match_dup 3))]
5617 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
5619 rtx insn, udiv_equal, umod_equal, equal;
5621 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5622 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5623 equal = gen_rtx_IOR (DImode,
5624 gen_rtx_ASHIFT (DImode,
5625 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5627 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5629 operands[3] = gen_reg_rtx (DImode);
5631 if (CONSTANT_P (operands[2]))
5633 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5635 rtx label1 = gen_label_rtx ();
5637 operands[1] = make_safe_from (operands[1], operands[0]);
5638 emit_move_insn (operands[0], operands[1]);
5639 emit_insn (gen_cmpsi (operands[0], operands[2]));
5640 emit_jump_insn (gen_bltu (label1));
5641 emit_insn (gen_abssi2 (operands[0], operands[2]));
5642 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5643 emit_label (label1);
5647 operands[2] = force_reg (SImode, operands[2]);
5648 operands[2] = make_safe_from (operands[2], operands[0]);
5650 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5651 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5653 set_unique_reg_note (insn, REG_EQUAL, equal);
5655 insn = emit_move_insn (operands[0],
5656 gen_highpart (SImode, operands[3]));
5657 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5662 rtx label1 = gen_label_rtx ();
5663 rtx label2 = gen_label_rtx ();
5664 rtx label3 = gen_label_rtx ();
5666 operands[1] = force_reg (SImode, operands[1]);
5667 operands[1] = make_safe_from (operands[1], operands[0]);
5668 operands[2] = force_reg (SImode, operands[2]);
5669 operands[2] = make_safe_from (operands[2], operands[0]);
5671 emit_move_insn(operands[0], operands[1]);
5672 emit_insn (gen_cmpsi (operands[2], operands[1]));
5673 emit_jump_insn (gen_bgtu (label3));
5674 emit_insn (gen_cmpsi (operands[2], const0_rtx));
5675 emit_jump_insn (gen_blt (label2));
5676 emit_insn (gen_cmpsi (operands[2], const1_rtx));
5677 emit_jump_insn (gen_beq (label1));
5678 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5679 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5681 set_unique_reg_note (insn, REG_EQUAL, equal);
5683 insn = emit_move_insn (operands[0],
5684 gen_highpart (SImode, operands[3]));
5685 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
5688 emit_label (label1);
5689 emit_move_insn (operands[0], const0_rtx);
5691 emit_label (label2);
5692 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5693 emit_label (label3);
5699 ; div(df|sf)3 instruction pattern(s).
5702 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
5703 (define_insn "div<mode>3"
5704 [(set (match_operand:FP 0 "register_operand" "=f,f")
5705 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5706 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5709 d<xde><bt>r\t%0,<op1>%2
5711 [(set_attr "op_type" "<RRer>,RXE")
5712 (set_attr "type" "fdiv<mode>")])
5716 ;;- And instructions.
5719 (define_expand "and<mode>3"
5720 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5721 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
5722 (match_operand:INT 2 "general_operand" "")))
5723 (clobber (reg:CC CC_REGNUM))]
5725 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
5728 ; anddi3 instruction pattern(s).
5731 (define_insn "*anddi3_cc"
5732 [(set (reg CC_REGNUM)
5733 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5734 (match_operand:DI 2 "general_operand" "d,RT"))
5736 (set (match_operand:DI 0 "register_operand" "=d,d")
5737 (and:DI (match_dup 1) (match_dup 2)))]
5738 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5742 [(set_attr "op_type" "RRE,RXY")
5743 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
5745 (define_insn "*anddi3_cconly"
5746 [(set (reg CC_REGNUM)
5747 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5748 (match_operand:DI 2 "general_operand" "d,RT"))
5750 (clobber (match_scratch:DI 0 "=d,d"))]
5751 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
5752 /* Do not steal TM patterns. */
5753 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5757 [(set_attr "op_type" "RRE,RXY")
5758 (set_attr "z10prop" "z10_super_E1, z10_super_E1")])
5760 (define_insn "*anddi3"
5761 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
5762 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5763 "%d,o,0,0,0,0,0,0,0,0,0,0")
5764 (match_operand:DI 2 "general_operand"
5765 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q")))
5766 (clobber (reg:CC CC_REGNUM))]
5767 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5781 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
5782 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*")
5783 (set_attr "z10prop" "*,
5797 [(set (match_operand:DI 0 "s_operand" "")
5798 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5799 (clobber (reg:CC CC_REGNUM))]
5802 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5803 (clobber (reg:CC CC_REGNUM))])]
5804 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5808 ; andsi3 instruction pattern(s).
5811 (define_insn "*andsi3_cc"
5812 [(set (reg CC_REGNUM)
5813 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5814 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5816 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5817 (and:SI (match_dup 1) (match_dup 2)))]
5818 "s390_match_ccmode(insn, CCTmode)"
5824 [(set_attr "op_type" "RIL,RR,RX,RXY")
5825 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
5827 (define_insn "*andsi3_cconly"
5828 [(set (reg CC_REGNUM)
5829 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5830 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5832 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5833 "s390_match_ccmode(insn, CCTmode)
5834 /* Do not steal TM patterns. */
5835 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5841 [(set_attr "op_type" "RIL,RR,RX,RXY")
5842 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
5844 (define_insn "*andsi3_zarch"
5845 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5846 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5847 "%d,o,0,0,0,0,0,0,0,0")
5848 (match_operand:SI 2 "general_operand"
5849 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
5850 (clobber (reg:CC CC_REGNUM))]
5851 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5863 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")
5864 (set_attr "z10prop" "*,
5875 (define_insn "*andsi3_esa"
5876 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5877 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5878 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5879 (clobber (reg:CC CC_REGNUM))]
5880 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5886 [(set_attr "op_type" "RR,RX,SI,SS")
5887 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
5891 [(set (match_operand:SI 0 "s_operand" "")
5892 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5893 (clobber (reg:CC CC_REGNUM))]
5896 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5897 (clobber (reg:CC CC_REGNUM))])]
5898 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5901 ; andhi3 instruction pattern(s).
5904 (define_insn "*andhi3_zarch"
5905 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5906 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5907 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5908 (clobber (reg:CC CC_REGNUM))]
5909 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5915 [(set_attr "op_type" "RR,RI,SI,SS")
5916 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")
5919 (define_insn "*andhi3_esa"
5920 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5921 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5922 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5923 (clobber (reg:CC CC_REGNUM))]
5924 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5929 [(set_attr "op_type" "RR,SI,SS")
5930 (set_attr "z10prop" "z10_super_E1,*,*")
5934 [(set (match_operand:HI 0 "s_operand" "")
5935 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5936 (clobber (reg:CC CC_REGNUM))]
5939 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5940 (clobber (reg:CC CC_REGNUM))])]
5941 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5944 ; andqi3 instruction pattern(s).
5947 (define_insn "*andqi3_zarch"
5948 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5949 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5950 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5951 (clobber (reg:CC CC_REGNUM))]
5952 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5959 [(set_attr "op_type" "RR,RI,SI,SIY,SS")
5960 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
5962 (define_insn "*andqi3_esa"
5963 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5964 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5965 (match_operand:QI 2 "general_operand" "d,n,Q")))
5966 (clobber (reg:CC CC_REGNUM))]
5967 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5972 [(set_attr "op_type" "RR,SI,SS")
5973 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
5976 ; Block and (NC) patterns.
5980 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5981 (and:BLK (match_dup 0)
5982 (match_operand:BLK 1 "memory_operand" "Q")))
5983 (use (match_operand 2 "const_int_operand" "n"))
5984 (clobber (reg:CC CC_REGNUM))]
5985 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5986 "nc\t%O0(%2,%R0),%S1"
5987 [(set_attr "op_type" "SS")])
5990 [(set (match_operand 0 "memory_operand" "")
5992 (match_operand 1 "memory_operand" "")))
5993 (clobber (reg:CC CC_REGNUM))]
5995 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5996 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5998 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
6000 (clobber (reg:CC CC_REGNUM))])]
6002 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6003 operands[0] = adjust_address (operands[0], BLKmode, 0);
6004 operands[1] = adjust_address (operands[1], BLKmode, 0);
6009 [(set (match_operand:BLK 0 "memory_operand" "")
6010 (and:BLK (match_dup 0)
6011 (match_operand:BLK 1 "memory_operand" "")))
6012 (use (match_operand 2 "const_int_operand" ""))
6013 (clobber (reg:CC CC_REGNUM))])
6015 [(set (match_operand:BLK 3 "memory_operand" "")
6016 (and:BLK (match_dup 3)
6017 (match_operand:BLK 4 "memory_operand" "")))
6018 (use (match_operand 5 "const_int_operand" ""))
6019 (clobber (reg:CC CC_REGNUM))])]
6020 "s390_offset_p (operands[0], operands[3], operands[2])
6021 && s390_offset_p (operands[1], operands[4], operands[2])
6022 && !s390_overlap_p (operands[0], operands[1],
6023 INTVAL (operands[2]) + INTVAL (operands[5]))
6024 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6026 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
6028 (clobber (reg:CC CC_REGNUM))])]
6029 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6030 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6031 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6035 ;;- Bit set (inclusive or) instructions.
6038 (define_expand "ior<mode>3"
6039 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6040 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
6041 (match_operand:INT 2 "general_operand" "")))
6042 (clobber (reg:CC CC_REGNUM))]
6044 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
6047 ; iordi3 instruction pattern(s).
6050 (define_insn "*iordi3_cc"
6051 [(set (reg CC_REGNUM)
6052 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6053 (match_operand:DI 2 "general_operand" "d,RT"))
6055 (set (match_operand:DI 0 "register_operand" "=d,d")
6056 (ior:DI (match_dup 1) (match_dup 2)))]
6057 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6061 [(set_attr "op_type" "RRE,RXY")
6062 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6064 (define_insn "*iordi3_cconly"
6065 [(set (reg CC_REGNUM)
6066 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6067 (match_operand:DI 2 "general_operand" "d,RT"))
6069 (clobber (match_scratch:DI 0 "=d,d"))]
6070 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6074 [(set_attr "op_type" "RRE,RXY")
6075 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6077 (define_insn "*iordi3"
6078 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
6079 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
6080 (match_operand:DI 2 "general_operand"
6081 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q")))
6082 (clobber (reg:CC CC_REGNUM))]
6083 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
6095 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
6096 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*")
6097 (set_attr "z10prop" "z10_super_E1,
6109 [(set (match_operand:DI 0 "s_operand" "")
6110 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6111 (clobber (reg:CC CC_REGNUM))]
6114 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6115 (clobber (reg:CC CC_REGNUM))])]
6116 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6119 ; iorsi3 instruction pattern(s).
6122 (define_insn "*iorsi3_cc"
6123 [(set (reg CC_REGNUM)
6124 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6125 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6127 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
6128 (ior:SI (match_dup 1) (match_dup 2)))]
6129 "s390_match_ccmode(insn, CCTmode)"
6135 [(set_attr "op_type" "RIL,RR,RX,RXY")
6136 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6138 (define_insn "*iorsi3_cconly"
6139 [(set (reg CC_REGNUM)
6140 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6141 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6143 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
6144 "s390_match_ccmode(insn, CCTmode)"
6150 [(set_attr "op_type" "RIL,RR,RX,RXY")
6151 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6153 (define_insn "*iorsi3_zarch"
6154 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
6155 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
6156 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
6157 (clobber (reg:CC CC_REGNUM))]
6158 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6168 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")
6169 (set_attr "z10prop" "z10_super_E1,
6178 (define_insn "*iorsi3_esa"
6179 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6180 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6181 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
6182 (clobber (reg:CC CC_REGNUM))]
6183 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6189 [(set_attr "op_type" "RR,RX,SI,SS")
6190 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6193 [(set (match_operand:SI 0 "s_operand" "")
6194 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6195 (clobber (reg:CC CC_REGNUM))]
6198 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6199 (clobber (reg:CC CC_REGNUM))])]
6200 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6203 ; iorhi3 instruction pattern(s).
6206 (define_insn "*iorhi3_zarch"
6207 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6208 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
6209 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
6210 (clobber (reg:CC CC_REGNUM))]
6211 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6217 [(set_attr "op_type" "RR,RI,SI,SS")
6218 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6220 (define_insn "*iorhi3_esa"
6221 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
6222 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
6223 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
6224 (clobber (reg:CC CC_REGNUM))]
6225 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6230 [(set_attr "op_type" "RR,SI,SS")
6231 (set_attr "z10prop" "z10_super_E1,*,*")])
6234 [(set (match_operand:HI 0 "s_operand" "")
6235 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6236 (clobber (reg:CC CC_REGNUM))]
6239 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
6240 (clobber (reg:CC CC_REGNUM))])]
6241 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
6244 ; iorqi3 instruction pattern(s).
6247 (define_insn "*iorqi3_zarch"
6248 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6249 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6250 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
6251 (clobber (reg:CC CC_REGNUM))]
6252 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6259 [(set_attr "op_type" "RR,RI,SI,SIY,SS")
6260 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6262 (define_insn "*iorqi3_esa"
6263 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
6264 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6265 (match_operand:QI 2 "general_operand" "d,n,Q")))
6266 (clobber (reg:CC CC_REGNUM))]
6267 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
6272 [(set_attr "op_type" "RR,SI,SS")
6273 (set_attr "z10prop" "z10_super_E1,z10_super,*")])
6276 ; Block inclusive or (OC) patterns.
6280 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6281 (ior:BLK (match_dup 0)
6282 (match_operand:BLK 1 "memory_operand" "Q")))
6283 (use (match_operand 2 "const_int_operand" "n"))
6284 (clobber (reg:CC CC_REGNUM))]
6285 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6286 "oc\t%O0(%2,%R0),%S1"
6287 [(set_attr "op_type" "SS")])
6290 [(set (match_operand 0 "memory_operand" "")
6292 (match_operand 1 "memory_operand" "")))
6293 (clobber (reg:CC CC_REGNUM))]
6295 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6296 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6298 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
6300 (clobber (reg:CC CC_REGNUM))])]
6302 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6303 operands[0] = adjust_address (operands[0], BLKmode, 0);
6304 operands[1] = adjust_address (operands[1], BLKmode, 0);
6309 [(set (match_operand:BLK 0 "memory_operand" "")
6310 (ior:BLK (match_dup 0)
6311 (match_operand:BLK 1 "memory_operand" "")))
6312 (use (match_operand 2 "const_int_operand" ""))
6313 (clobber (reg:CC CC_REGNUM))])
6315 [(set (match_operand:BLK 3 "memory_operand" "")
6316 (ior:BLK (match_dup 3)
6317 (match_operand:BLK 4 "memory_operand" "")))
6318 (use (match_operand 5 "const_int_operand" ""))
6319 (clobber (reg:CC CC_REGNUM))])]
6320 "s390_offset_p (operands[0], operands[3], operands[2])
6321 && s390_offset_p (operands[1], operands[4], operands[2])
6322 && !s390_overlap_p (operands[0], operands[1],
6323 INTVAL (operands[2]) + INTVAL (operands[5]))
6324 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6326 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
6328 (clobber (reg:CC CC_REGNUM))])]
6329 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6330 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6331 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6335 ;;- Xor instructions.
6338 (define_expand "xor<mode>3"
6339 [(set (match_operand:INT 0 "nonimmediate_operand" "")
6340 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
6341 (match_operand:INT 2 "general_operand" "")))
6342 (clobber (reg:CC CC_REGNUM))]
6344 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
6347 ; xordi3 instruction pattern(s).
6350 (define_insn "*xordi3_cc"
6351 [(set (reg CC_REGNUM)
6352 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6353 (match_operand:DI 2 "general_operand" "d,RT"))
6355 (set (match_operand:DI 0 "register_operand" "=d,d")
6356 (xor:DI (match_dup 1) (match_dup 2)))]
6357 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6361 [(set_attr "op_type" "RRE,RXY")
6362 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6364 (define_insn "*xordi3_cconly"
6365 [(set (reg CC_REGNUM)
6366 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
6367 (match_operand:DI 2 "general_operand" "d,RT"))
6369 (clobber (match_scratch:DI 0 "=d,d"))]
6370 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
6374 [(set_attr "op_type" "RRE,RXY")
6375 (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
6377 (define_insn "*xordi3"
6378 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
6379 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
6380 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q")))
6381 (clobber (reg:CC CC_REGNUM))]
6382 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
6390 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")
6391 (set_attr "cpu_facility" "extimm,extimm,*,*,*,*")
6392 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
6395 [(set (match_operand:DI 0 "s_operand" "")
6396 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
6397 (clobber (reg:CC CC_REGNUM))]
6400 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6401 (clobber (reg:CC CC_REGNUM))])]
6402 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6405 ; xorsi3 instruction pattern(s).
6408 (define_insn "*xorsi3_cc"
6409 [(set (reg CC_REGNUM)
6410 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6411 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6413 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
6414 (xor:SI (match_dup 1) (match_dup 2)))]
6415 "s390_match_ccmode(insn, CCTmode)"
6421 [(set_attr "op_type" "RIL,RR,RX,RXY")
6422 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6424 (define_insn "*xorsi3_cconly"
6425 [(set (reg CC_REGNUM)
6426 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
6427 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
6429 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
6430 "s390_match_ccmode(insn, CCTmode)"
6436 [(set_attr "op_type" "RIL,RR,RX,RXY")
6437 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
6439 (define_insn "*xorsi3"
6440 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
6441 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
6442 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
6443 (clobber (reg:CC CC_REGNUM))]
6444 "s390_logical_operator_ok_p (operands)"
6452 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")
6453 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
6456 [(set (match_operand:SI 0 "s_operand" "")
6457 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
6458 (clobber (reg:CC CC_REGNUM))]
6461 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6462 (clobber (reg:CC CC_REGNUM))])]
6463 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6466 ; xorhi3 instruction pattern(s).
6469 (define_insn "*xorhi3"
6470 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
6471 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
6472 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
6473 (clobber (reg:CC CC_REGNUM))]
6474 "s390_logical_operator_ok_p (operands)"
6480 [(set_attr "op_type" "RIL,RR,SI,SS")
6481 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
6484 [(set (match_operand:HI 0 "s_operand" "")
6485 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
6486 (clobber (reg:CC CC_REGNUM))]
6489 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
6490 (clobber (reg:CC CC_REGNUM))])]
6491 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
6494 ; xorqi3 instruction pattern(s).
6497 (define_insn "*xorqi3"
6498 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
6499 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
6500 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
6501 (clobber (reg:CC CC_REGNUM))]
6502 "s390_logical_operator_ok_p (operands)"
6509 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")
6510 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
6514 ; Block exclusive or (XC) patterns.
6518 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6519 (xor:BLK (match_dup 0)
6520 (match_operand:BLK 1 "memory_operand" "Q")))
6521 (use (match_operand 2 "const_int_operand" "n"))
6522 (clobber (reg:CC CC_REGNUM))]
6523 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
6524 "xc\t%O0(%2,%R0),%S1"
6525 [(set_attr "op_type" "SS")])
6528 [(set (match_operand 0 "memory_operand" "")
6530 (match_operand 1 "memory_operand" "")))
6531 (clobber (reg:CC CC_REGNUM))]
6533 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6534 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6536 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
6538 (clobber (reg:CC CC_REGNUM))])]
6540 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6541 operands[0] = adjust_address (operands[0], BLKmode, 0);
6542 operands[1] = adjust_address (operands[1], BLKmode, 0);
6547 [(set (match_operand:BLK 0 "memory_operand" "")
6548 (xor:BLK (match_dup 0)
6549 (match_operand:BLK 1 "memory_operand" "")))
6550 (use (match_operand 2 "const_int_operand" ""))
6551 (clobber (reg:CC CC_REGNUM))])
6553 [(set (match_operand:BLK 3 "memory_operand" "")
6554 (xor:BLK (match_dup 3)
6555 (match_operand:BLK 4 "memory_operand" "")))
6556 (use (match_operand 5 "const_int_operand" ""))
6557 (clobber (reg:CC CC_REGNUM))])]
6558 "s390_offset_p (operands[0], operands[3], operands[2])
6559 && s390_offset_p (operands[1], operands[4], operands[2])
6560 && !s390_overlap_p (operands[0], operands[1],
6561 INTVAL (operands[2]) + INTVAL (operands[5]))
6562 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6564 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
6566 (clobber (reg:CC CC_REGNUM))])]
6567 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6568 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6569 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6572 ; Block xor (XC) patterns with src == dest.
6575 (define_insn "*xc_zero"
6576 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6578 (use (match_operand 1 "const_int_operand" "n"))
6579 (clobber (reg:CC CC_REGNUM))]
6580 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
6581 "xc\t%O0(%1,%R0),%S0"
6582 [(set_attr "op_type" "SS")])
6586 [(set (match_operand:BLK 0 "memory_operand" "")
6588 (use (match_operand 1 "const_int_operand" ""))
6589 (clobber (reg:CC CC_REGNUM))])
6591 [(set (match_operand:BLK 2 "memory_operand" "")
6593 (use (match_operand 3 "const_int_operand" ""))
6594 (clobber (reg:CC CC_REGNUM))])]
6595 "s390_offset_p (operands[0], operands[2], operands[1])
6596 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
6598 [(set (match_dup 4) (const_int 0))
6600 (clobber (reg:CC CC_REGNUM))])]
6601 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6602 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
6606 ;;- Negate instructions.
6610 ; neg(di|si)2 instruction pattern(s).
6613 (define_expand "neg<mode>2"
6615 [(set (match_operand:DSI 0 "register_operand" "=d")
6616 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
6617 (clobber (reg:CC CC_REGNUM))])]
6621 (define_insn "*negdi2_sign_cc"
6622 [(set (reg CC_REGNUM)
6623 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
6624 (match_operand:SI 1 "register_operand" "d") 0)
6625 (const_int 32)) (const_int 32)))
6627 (set (match_operand:DI 0 "register_operand" "=d")
6628 (neg:DI (sign_extend:DI (match_dup 1))))]
6629 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6631 [(set_attr "op_type" "RRE")])
6633 (define_insn "*negdi2_sign"
6634 [(set (match_operand:DI 0 "register_operand" "=d")
6635 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6636 (clobber (reg:CC CC_REGNUM))]
6639 [(set_attr "op_type" "RRE")])
6642 (define_insn "*neg<mode>2_cc"
6643 [(set (reg CC_REGNUM)
6644 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6646 (set (match_operand:GPR 0 "register_operand" "=d")
6647 (neg:GPR (match_dup 1)))]
6648 "s390_match_ccmode (insn, CCAmode)"
6650 [(set_attr "op_type" "RR<E>")
6651 (set_attr "z10prop" "z10_super_c_E1")])
6654 (define_insn "*neg<mode>2_cconly"
6655 [(set (reg CC_REGNUM)
6656 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
6658 (clobber (match_scratch:GPR 0 "=d"))]
6659 "s390_match_ccmode (insn, CCAmode)"
6661 [(set_attr "op_type" "RR<E>")
6662 (set_attr "z10prop" "z10_super_c_E1")])
6665 (define_insn "*neg<mode>2"
6666 [(set (match_operand:GPR 0 "register_operand" "=d")
6667 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
6668 (clobber (reg:CC CC_REGNUM))]
6671 [(set_attr "op_type" "RR<E>")
6672 (set_attr "z10prop" "z10_super_c_E1")])
6674 (define_insn_and_split "*negdi2_31"
6675 [(set (match_operand:DI 0 "register_operand" "=d")
6676 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6677 (clobber (reg:CC CC_REGNUM))]
6680 "&& reload_completed"
6682 [(set (match_dup 2) (neg:SI (match_dup 3)))
6683 (clobber (reg:CC CC_REGNUM))])
6685 [(set (reg:CCAP CC_REGNUM)
6686 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
6687 (set (match_dup 4) (neg:SI (match_dup 5)))])
6689 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
6691 (label_ref (match_dup 6))))
6693 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
6694 (clobber (reg:CC CC_REGNUM))])
6696 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
6697 operands[3] = operand_subword (operands[1], 0, 0, DImode);
6698 operands[4] = operand_subword (operands[0], 1, 0, DImode);
6699 operands[5] = operand_subword (operands[1], 1, 0, DImode);
6700 operands[6] = gen_label_rtx ();")
6703 ; neg(df|sf)2 instruction pattern(s).
6706 (define_expand "neg<mode>2"
6708 [(set (match_operand:BFP 0 "register_operand" "=f")
6709 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6710 (clobber (reg:CC CC_REGNUM))])]
6714 ; lcxbr, lcdbr, lcebr
6715 (define_insn "*neg<mode>2_cc"
6716 [(set (reg CC_REGNUM)
6717 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6718 (match_operand:BFP 2 "const0_operand" "")))
6719 (set (match_operand:BFP 0 "register_operand" "=f")
6720 (neg:BFP (match_dup 1)))]
6721 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6723 [(set_attr "op_type" "RRE")
6724 (set_attr "type" "fsimp<mode>")])
6726 ; lcxbr, lcdbr, lcebr
6727 (define_insn "*neg<mode>2_cconly"
6728 [(set (reg CC_REGNUM)
6729 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6730 (match_operand:BFP 2 "const0_operand" "")))
6731 (clobber (match_scratch:BFP 0 "=f"))]
6732 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6734 [(set_attr "op_type" "RRE")
6735 (set_attr "type" "fsimp<mode>")])
6738 (define_insn "*neg<mode>2_nocc"
6739 [(set (match_operand:FP 0 "register_operand" "=f")
6740 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6743 [(set_attr "op_type" "RRE")
6744 (set_attr "type" "fsimp<mode>")])
6746 ; lcxbr, lcdbr, lcebr
6747 (define_insn "*neg<mode>2"
6748 [(set (match_operand:BFP 0 "register_operand" "=f")
6749 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6750 (clobber (reg:CC CC_REGNUM))]
6753 [(set_attr "op_type" "RRE")
6754 (set_attr "type" "fsimp<mode>")])
6758 ;;- Absolute value instructions.
6762 ; abs(di|si)2 instruction pattern(s).
6765 (define_insn "*absdi2_sign_cc"
6766 [(set (reg CC_REGNUM)
6767 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6768 (match_operand:SI 1 "register_operand" "d") 0)
6769 (const_int 32)) (const_int 32)))
6771 (set (match_operand:DI 0 "register_operand" "=d")
6772 (abs:DI (sign_extend:DI (match_dup 1))))]
6773 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6775 [(set_attr "op_type" "RRE")])
6777 (define_insn "*absdi2_sign"
6778 [(set (match_operand:DI 0 "register_operand" "=d")
6779 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6780 (clobber (reg:CC CC_REGNUM))]
6783 [(set_attr "op_type" "RRE")])
6786 (define_insn "*abs<mode>2_cc"
6787 [(set (reg CC_REGNUM)
6788 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
6790 (set (match_operand:GPR 0 "register_operand" "=d")
6791 (abs:GPR (match_dup 1)))]
6792 "s390_match_ccmode (insn, CCAmode)"
6794 [(set_attr "op_type" "RR<E>")
6795 (set_attr "z10prop" "z10_c")])
6798 (define_insn "*abs<mode>2_cconly"
6799 [(set (reg CC_REGNUM)
6800 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
6802 (clobber (match_scratch:GPR 0 "=d"))]
6803 "s390_match_ccmode (insn, CCAmode)"
6805 [(set_attr "op_type" "RR<E>")
6806 (set_attr "z10prop" "z10_c")])
6809 (define_insn "abs<mode>2"
6810 [(set (match_operand:GPR 0 "register_operand" "=d")
6811 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6812 (clobber (reg:CC CC_REGNUM))]
6815 [(set_attr "op_type" "RR<E>")
6816 (set_attr "z10prop" "z10_c")])
6819 ; abs(df|sf)2 instruction pattern(s).
6822 (define_expand "abs<mode>2"
6824 [(set (match_operand:BFP 0 "register_operand" "=f")
6825 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6826 (clobber (reg:CC CC_REGNUM))])]
6830 ; lpxbr, lpdbr, lpebr
6831 (define_insn "*abs<mode>2_cc"
6832 [(set (reg CC_REGNUM)
6833 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6834 (match_operand:BFP 2 "const0_operand" "")))
6835 (set (match_operand:BFP 0 "register_operand" "=f")
6836 (abs:BFP (match_dup 1)))]
6837 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6839 [(set_attr "op_type" "RRE")
6840 (set_attr "type" "fsimp<mode>")])
6842 ; lpxbr, lpdbr, lpebr
6843 (define_insn "*abs<mode>2_cconly"
6844 [(set (reg CC_REGNUM)
6845 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6846 (match_operand:BFP 2 "const0_operand" "")))
6847 (clobber (match_scratch:BFP 0 "=f"))]
6848 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6850 [(set_attr "op_type" "RRE")
6851 (set_attr "type" "fsimp<mode>")])
6854 (define_insn "*abs<mode>2_nocc"
6855 [(set (match_operand:FP 0 "register_operand" "=f")
6856 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6859 [(set_attr "op_type" "RRE")
6860 (set_attr "type" "fsimp<mode>")])
6862 ; lpxbr, lpdbr, lpebr
6863 (define_insn "*abs<mode>2"
6864 [(set (match_operand:BFP 0 "register_operand" "=f")
6865 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6866 (clobber (reg:CC CC_REGNUM))]
6869 [(set_attr "op_type" "RRE")
6870 (set_attr "type" "fsimp<mode>")])
6874 ;;- Negated absolute value instructions
6881 (define_insn "*negabsdi2_sign_cc"
6882 [(set (reg CC_REGNUM)
6883 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6884 (match_operand:SI 1 "register_operand" "d") 0)
6885 (const_int 32)) (const_int 32))))
6887 (set (match_operand:DI 0 "register_operand" "=d")
6888 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6889 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6891 [(set_attr "op_type" "RRE")])
6893 (define_insn "*negabsdi2_sign"
6894 [(set (match_operand:DI 0 "register_operand" "=d")
6895 (neg:DI (abs:DI (sign_extend:DI
6896 (match_operand:SI 1 "register_operand" "d")))))
6897 (clobber (reg:CC CC_REGNUM))]
6900 [(set_attr "op_type" "RRE")])
6903 (define_insn "*negabs<mode>2_cc"
6904 [(set (reg CC_REGNUM)
6905 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6907 (set (match_operand:GPR 0 "register_operand" "=d")
6908 (neg:GPR (abs:GPR (match_dup 1))))]
6909 "s390_match_ccmode (insn, CCAmode)"
6911 [(set_attr "op_type" "RR<E>")
6912 (set_attr "z10prop" "z10_c")])
6915 (define_insn "*negabs<mode>2_cconly"
6916 [(set (reg CC_REGNUM)
6917 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6919 (clobber (match_scratch:GPR 0 "=d"))]
6920 "s390_match_ccmode (insn, CCAmode)"
6922 [(set_attr "op_type" "RR<E>")
6923 (set_attr "z10prop" "z10_c")])
6926 (define_insn "*negabs<mode>2"
6927 [(set (match_operand:GPR 0 "register_operand" "=d")
6928 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
6929 (clobber (reg:CC CC_REGNUM))]
6932 [(set_attr "op_type" "RR<E>")
6933 (set_attr "z10prop" "z10_c")])
6939 ; lnxbr, lndbr, lnebr
6940 (define_insn "*negabs<mode>2_cc"
6941 [(set (reg CC_REGNUM)
6942 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6943 (match_operand:BFP 2 "const0_operand" "")))
6944 (set (match_operand:BFP 0 "register_operand" "=f")
6945 (neg:BFP (abs:BFP (match_dup 1))))]
6946 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6948 [(set_attr "op_type" "RRE")
6949 (set_attr "type" "fsimp<mode>")])
6951 ; lnxbr, lndbr, lnebr
6952 (define_insn "*negabs<mode>2_cconly"
6953 [(set (reg CC_REGNUM)
6954 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6955 (match_operand:BFP 2 "const0_operand" "")))
6956 (clobber (match_scratch:BFP 0 "=f"))]
6957 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6959 [(set_attr "op_type" "RRE")
6960 (set_attr "type" "fsimp<mode>")])
6963 (define_insn "*negabs<mode>2_nocc"
6964 [(set (match_operand:FP 0 "register_operand" "=f")
6965 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
6968 [(set_attr "op_type" "RRE")
6969 (set_attr "type" "fsimp<mode>")])
6971 ; lnxbr, lndbr, lnebr
6972 (define_insn "*negabs<mode>2"
6973 [(set (match_operand:BFP 0 "register_operand" "=f")
6974 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
6975 (clobber (reg:CC CC_REGNUM))]
6978 [(set_attr "op_type" "RRE")
6979 (set_attr "type" "fsimp<mode>")])
6982 ;;- Copy sign instructions
6986 (define_insn "copysign<mode>3"
6987 [(set (match_operand:FP 0 "register_operand" "=f")
6988 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
6989 (match_operand:FP 2 "register_operand" "f")]
6993 [(set_attr "op_type" "RRF")
6994 (set_attr "type" "fsimp<mode>")])
6997 ;;- Square root instructions.
7001 ; sqrt(df|sf)2 instruction pattern(s).
7004 ; sqxbr, sqdbr, sqebr, sqdb, sqeb
7005 (define_insn "sqrt<mode>2"
7006 [(set (match_operand:BFP 0 "register_operand" "=f,f")
7007 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
7012 [(set_attr "op_type" "RRE,RXE")
7013 (set_attr "type" "fsqrt<mode>")])
7017 ;;- One complement instructions.
7021 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
7024 (define_expand "one_cmpl<mode>2"
7026 [(set (match_operand:INT 0 "register_operand" "")
7027 (xor:INT (match_operand:INT 1 "register_operand" "")
7029 (clobber (reg:CC CC_REGNUM))])]
7035 ;; Find leftmost bit instructions.
7038 (define_expand "clzdi2"
7039 [(set (match_operand:DI 0 "register_operand" "=d")
7040 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
7041 "TARGET_EXTIMM && TARGET_64BIT"
7043 rtx insn, clz_equal;
7044 rtx wide_reg = gen_reg_rtx (TImode);
7045 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
7047 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
7049 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
7051 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
7052 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
7057 (define_insn "clztidi2"
7058 [(set (match_operand:TI 0 "register_operand" "=d")
7062 (xor:DI (match_operand:DI 1 "register_operand" "d")
7063 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
7064 (subreg:SI (clz:DI (match_dup 1)) 4))))
7067 (zero_extend:TI (clz:DI (match_dup 1)))))
7068 (clobber (reg:CC CC_REGNUM))]
7069 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
7070 == (unsigned HOST_WIDE_INT) 1 << 63
7071 && TARGET_EXTIMM && TARGET_64BIT"
7073 [(set_attr "op_type" "RRE")])
7077 ;;- Rotate instructions.
7081 ; rotl(di|si)3 instruction pattern(s).
7085 (define_insn "rotl<mode>3"
7086 [(set (match_operand:GPR 0 "register_operand" "=d")
7087 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7088 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7091 [(set_attr "op_type" "RSE")
7092 (set_attr "atype" "reg")
7093 (set_attr "z10prop" "z10_super_E1")])
7096 (define_insn "*rotl<mode>3_and"
7097 [(set (match_operand:GPR 0 "register_operand" "=d")
7098 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
7099 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7100 (match_operand:SI 3 "const_int_operand" "n"))))]
7101 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
7103 [(set_attr "op_type" "RSE")
7104 (set_attr "atype" "reg")
7105 (set_attr "z10prop" "z10_super_E1")])
7109 ;;- Shift instructions.
7113 ; (ashl|lshr)(di|si)3 instruction pattern(s).
7116 (define_expand "<shift><mode>3"
7117 [(set (match_operand:DSI 0 "register_operand" "")
7118 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
7119 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
7124 (define_insn "*<shift>di3_31"
7125 [(set (match_operand:DI 0 "register_operand" "=d")
7126 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7127 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7130 [(set_attr "op_type" "RS")
7131 (set_attr "atype" "reg")])
7133 ; sll, srl, sllg, srlg
7134 (define_insn "*<shift><mode>3"
7135 [(set (match_operand:GPR 0 "register_operand" "=d")
7136 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7137 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
7139 "s<lr>l<g>\t%0,<1>%Y2"
7140 [(set_attr "op_type" "RS<E>")
7141 (set_attr "atype" "reg")
7142 (set_attr "z10prop" "z10_super_E1")])
7145 (define_insn "*<shift>di3_31_and"
7146 [(set (match_operand:DI 0 "register_operand" "=d")
7147 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
7148 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7149 (match_operand:SI 3 "const_int_operand" "n"))))]
7150 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
7152 [(set_attr "op_type" "RS")
7153 (set_attr "atype" "reg")])
7155 ; sll, srl, sllg, srlg
7156 (define_insn "*<shift><mode>3_and"
7157 [(set (match_operand:GPR 0 "register_operand" "=d")
7158 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7159 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7160 (match_operand:SI 3 "const_int_operand" "n"))))]
7161 "(INTVAL (operands[3]) & 63) == 63"
7162 "s<lr>l<g>\t%0,<1>%Y2"
7163 [(set_attr "op_type" "RS<E>")
7164 (set_attr "atype" "reg")
7165 (set_attr "z10prop" "z10_super_E1")])
7168 ; ashr(di|si)3 instruction pattern(s).
7171 (define_expand "ashr<mode>3"
7173 [(set (match_operand:DSI 0 "register_operand" "")
7174 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
7175 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
7176 (clobber (reg:CC CC_REGNUM))])]
7180 (define_insn "*ashrdi3_cc_31"
7181 [(set (reg CC_REGNUM)
7182 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7183 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7185 (set (match_operand:DI 0 "register_operand" "=d")
7186 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7187 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
7189 [(set_attr "op_type" "RS")
7190 (set_attr "atype" "reg")])
7192 (define_insn "*ashrdi3_cconly_31"
7193 [(set (reg CC_REGNUM)
7194 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7195 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7197 (clobber (match_scratch:DI 0 "=d"))]
7198 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
7200 [(set_attr "op_type" "RS")
7201 (set_attr "atype" "reg")])
7203 (define_insn "*ashrdi3_31"
7204 [(set (match_operand:DI 0 "register_operand" "=d")
7205 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7206 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7207 (clobber (reg:CC CC_REGNUM))]
7210 [(set_attr "op_type" "RS")
7211 (set_attr "atype" "reg")])
7214 (define_insn "*ashr<mode>3_cc"
7215 [(set (reg CC_REGNUM)
7216 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7217 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7219 (set (match_operand:GPR 0 "register_operand" "=d")
7220 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
7221 "s390_match_ccmode(insn, CCSmode)"
7223 [(set_attr "op_type" "RS<E>")
7224 (set_attr "atype" "reg")
7225 (set_attr "z10prop" "z10_super_E1")])
7228 (define_insn "*ashr<mode>3_cconly"
7229 [(set (reg CC_REGNUM)
7230 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7231 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
7233 (clobber (match_scratch:GPR 0 "=d"))]
7234 "s390_match_ccmode(insn, CCSmode)"
7236 [(set_attr "op_type" "RS<E>")
7237 (set_attr "atype" "reg")
7238 (set_attr "z10prop" "z10_super_E1")])
7241 (define_insn "*ashr<mode>3"
7242 [(set (match_operand:GPR 0 "register_operand" "=d")
7243 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7244 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
7245 (clobber (reg:CC CC_REGNUM))]
7248 [(set_attr "op_type" "RS<E>")
7249 (set_attr "atype" "reg")
7250 (set_attr "z10prop" "z10_super_E1")])
7253 ; shift pattern with implicit ANDs
7255 (define_insn "*ashrdi3_cc_31_and"
7256 [(set (reg CC_REGNUM)
7257 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7258 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7259 (match_operand:SI 3 "const_int_operand" "n")))
7261 (set (match_operand:DI 0 "register_operand" "=d")
7262 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7263 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
7264 && (INTVAL (operands[3]) & 63) == 63"
7266 [(set_attr "op_type" "RS")
7267 (set_attr "atype" "reg")])
7269 (define_insn "*ashrdi3_cconly_31_and"
7270 [(set (reg CC_REGNUM)
7271 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7272 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7273 (match_operand:SI 3 "const_int_operand" "n")))
7275 (clobber (match_scratch:DI 0 "=d"))]
7276 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
7277 && (INTVAL (operands[3]) & 63) == 63"
7279 [(set_attr "op_type" "RS")
7280 (set_attr "atype" "reg")])
7282 (define_insn "*ashrdi3_31_and"
7283 [(set (match_operand:DI 0 "register_operand" "=d")
7284 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
7285 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7286 (match_operand:SI 3 "const_int_operand" "n"))))
7287 (clobber (reg:CC CC_REGNUM))]
7288 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
7290 [(set_attr "op_type" "RS")
7291 (set_attr "atype" "reg")])
7294 (define_insn "*ashr<mode>3_cc_and"
7295 [(set (reg CC_REGNUM)
7296 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7297 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7298 (match_operand:SI 3 "const_int_operand" "n")))
7300 (set (match_operand:GPR 0 "register_operand" "=d")
7301 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
7302 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7304 [(set_attr "op_type" "RS<E>")
7305 (set_attr "atype" "reg")
7306 (set_attr "z10prop" "z10_super_E1")])
7309 (define_insn "*ashr<mode>3_cconly_and"
7310 [(set (reg CC_REGNUM)
7311 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7312 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7313 (match_operand:SI 3 "const_int_operand" "n")))
7315 (clobber (match_scratch:GPR 0 "=d"))]
7316 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
7318 [(set_attr "op_type" "RS<E>")
7319 (set_attr "atype" "reg")
7320 (set_attr "z10prop" "z10_super_E1")])
7323 (define_insn "*ashr<mode>3_and"
7324 [(set (match_operand:GPR 0 "register_operand" "=d")
7325 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
7326 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
7327 (match_operand:SI 3 "const_int_operand" "n"))))
7328 (clobber (reg:CC CC_REGNUM))]
7329 "(INTVAL (operands[3]) & 63) == 63"
7331 [(set_attr "op_type" "RS<E>")
7332 (set_attr "atype" "reg")
7333 (set_attr "z10prop" "z10_super_E1")])
7337 ;; Branch instruction patterns.
7340 (define_expand "b<code>"
7342 (if_then_else (COMPARE (match_operand 0 "" "")
7347 "s390_emit_jump (operands[0],
7348 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
7352 ;;- Conditional jump instructions.
7355 (define_insn "*cjump_64"
7358 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7359 (label_ref (match_operand 0 "" ""))
7363 if (get_attr_length (insn) == 4)
7366 return "jg%C1\t%l0";
7368 [(set_attr "op_type" "RI")
7369 (set_attr "type" "branch")
7370 (set (attr "length")
7371 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7372 (const_int 4) (const_int 6)))])
7374 (define_insn "*cjump_31"
7377 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7378 (label_ref (match_operand 0 "" ""))
7382 gcc_assert (get_attr_length (insn) == 4);
7385 [(set_attr "op_type" "RI")
7386 (set_attr "type" "branch")
7387 (set (attr "length")
7388 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7389 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7390 (const_int 4) (const_int 6))
7391 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7392 (const_int 4) (const_int 8))))])
7394 (define_insn "*cjump_long"
7397 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7398 (match_operand 0 "address_operand" "U")
7402 if (get_attr_op_type (insn) == OP_TYPE_RR)
7407 [(set (attr "op_type")
7408 (if_then_else (match_operand 0 "register_operand" "")
7409 (const_string "RR") (const_string "RX")))
7410 (set_attr "type" "branch")
7411 (set_attr "atype" "agen")])
7415 ;;- Negated conditional jump instructions.
7418 (define_insn "*icjump_64"
7421 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7423 (label_ref (match_operand 0 "" ""))))]
7426 if (get_attr_length (insn) == 4)
7429 return "jg%D1\t%l0";
7431 [(set_attr "op_type" "RI")
7432 (set_attr "type" "branch")
7433 (set (attr "length")
7434 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7435 (const_int 4) (const_int 6)))])
7437 (define_insn "*icjump_31"
7440 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7442 (label_ref (match_operand 0 "" ""))))]
7445 gcc_assert (get_attr_length (insn) == 4);
7448 [(set_attr "op_type" "RI")
7449 (set_attr "type" "branch")
7450 (set (attr "length")
7451 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7452 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7453 (const_int 4) (const_int 6))
7454 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7455 (const_int 4) (const_int 8))))])
7457 (define_insn "*icjump_long"
7460 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7462 (match_operand 0 "address_operand" "U")))]
7465 if (get_attr_op_type (insn) == OP_TYPE_RR)
7470 [(set (attr "op_type")
7471 (if_then_else (match_operand 0 "register_operand" "")
7472 (const_string "RR") (const_string "RX")))
7473 (set_attr "type" "branch")
7474 (set_attr "atype" "agen")])
7477 ;;- Trap instructions.
7481 [(trap_if (const_int 1) (const_int 0))]
7484 [(set_attr "op_type" "RI")
7485 (set_attr "type" "branch")])
7487 (define_expand "conditional_trap"
7488 [(trap_if (match_operand 0 "comparison_operator" "")
7489 (match_operand 1 "general_operand" ""))]
7492 if (operands[1] != const0_rtx) FAIL;
7493 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
7494 s390_compare_op0, s390_compare_op1);
7497 (define_insn "*trap"
7498 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
7502 [(set_attr "op_type" "RI")
7503 (set_attr "type" "branch")])
7505 ; crt, cgrt, cit, cgit
7506 (define_insn "*cmp_and_trap_signed_int<mode>"
7507 [(trap_if (match_operator 0 "s390_signed_integer_comparison"
7508 [(match_operand:GPR 1 "register_operand" "d,d")
7509 (match_operand:GPR 2 "nonmemory_operand" "d,K")])
7515 [(set_attr "op_type" "RRF,RIE")
7516 (set_attr "type" "branch")
7517 (set_attr "z10prop" "z10_c,*")])
7519 ; clrt, clgrt, clfit, clgit
7520 (define_insn "*cmp_and_trap_unsigned_int<mode>"
7521 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
7522 [(match_operand:GPR 1 "register_operand" "d,d")
7523 (match_operand:GPR 2 "nonmemory_operand" "d,D")])
7528 cl<gf>it%C0\t%1,%x2"
7529 [(set_attr "op_type" "RRF,RIE")
7530 (set_attr "type" "branch")
7531 (set_attr "z10prop" "z10_c,*")])
7534 ;;- Loop instructions.
7536 ;; This is all complicated by the fact that since this is a jump insn
7537 ;; we must handle our own output reloads.
7539 (define_expand "doloop_end"
7540 [(use (match_operand 0 "" "")) ; loop pseudo
7541 (use (match_operand 1 "" "")) ; iterations; zero if unknown
7542 (use (match_operand 2 "" "")) ; max iterations
7543 (use (match_operand 3 "" "")) ; loop level
7544 (use (match_operand 4 "" ""))] ; label
7547 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
7548 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
7549 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
7550 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
7551 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
7552 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
7559 (define_insn_and_split "doloop_si64"
7562 (ne (match_operand:SI 1 "register_operand" "d,d,d")
7564 (label_ref (match_operand 0 "" ""))
7566 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
7567 (plus:SI (match_dup 1) (const_int -1)))
7568 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
7569 (clobber (reg:CC CC_REGNUM))]
7572 if (which_alternative != 0)
7574 else if (get_attr_length (insn) == 4)
7575 return "brct\t%1,%l0";
7577 return "ahi\t%1,-1\;jgne\t%l0";
7579 "&& reload_completed
7580 && (! REG_P (operands[2])
7581 || ! rtx_equal_p (operands[1], operands[2]))"
7582 [(set (match_dup 3) (match_dup 1))
7583 (parallel [(set (reg:CCAN CC_REGNUM)
7584 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7586 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7587 (set (match_dup 2) (match_dup 3))
7588 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7589 (label_ref (match_dup 0))
7592 [(set_attr "op_type" "RI")
7593 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7594 ; hurt us in the (rare) case of ahi.
7595 (set_attr "z10prop" "z10_super")
7596 (set_attr "type" "branch")
7597 (set (attr "length")
7598 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7599 (const_int 4) (const_int 10)))])
7601 (define_insn_and_split "doloop_si31"
7604 (ne (match_operand:SI 1 "register_operand" "d,d,d")
7606 (label_ref (match_operand 0 "" ""))
7608 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
7609 (plus:SI (match_dup 1) (const_int -1)))
7610 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
7611 (clobber (reg:CC CC_REGNUM))]
7614 if (which_alternative != 0)
7616 else if (get_attr_length (insn) == 4)
7617 return "brct\t%1,%l0";
7621 "&& reload_completed
7622 && (! REG_P (operands[2])
7623 || ! rtx_equal_p (operands[1], operands[2]))"
7624 [(set (match_dup 3) (match_dup 1))
7625 (parallel [(set (reg:CCAN CC_REGNUM)
7626 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7628 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7629 (set (match_dup 2) (match_dup 3))
7630 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7631 (label_ref (match_dup 0))
7634 [(set_attr "op_type" "RI")
7635 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7636 ; hurt us in the (rare) case of ahi.
7637 (set_attr "z10prop" "z10_super")
7638 (set_attr "type" "branch")
7639 (set (attr "length")
7640 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7641 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7642 (const_int 4) (const_int 6))
7643 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7644 (const_int 4) (const_int 8))))])
7646 (define_insn "*doloop_si_long"
7649 (ne (match_operand:SI 1 "register_operand" "d")
7651 (match_operand 0 "address_operand" "U")
7653 (set (match_operand:SI 2 "register_operand" "=1")
7654 (plus:SI (match_dup 1) (const_int -1)))
7655 (clobber (match_scratch:SI 3 "=X"))
7656 (clobber (reg:CC CC_REGNUM))]
7659 if (get_attr_op_type (insn) == OP_TYPE_RR)
7660 return "bctr\t%1,%0";
7662 return "bct\t%1,%a0";
7664 [(set (attr "op_type")
7665 (if_then_else (match_operand 0 "register_operand" "")
7666 (const_string "RR") (const_string "RX")))
7667 (set_attr "type" "branch")
7668 (set_attr "atype" "agen")])
7670 (define_insn_and_split "doloop_di"
7673 (ne (match_operand:DI 1 "register_operand" "d,d,d")
7675 (label_ref (match_operand 0 "" ""))
7677 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
7678 (plus:DI (match_dup 1) (const_int -1)))
7679 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
7680 (clobber (reg:CC CC_REGNUM))]
7683 if (which_alternative != 0)
7685 else if (get_attr_length (insn) == 4)
7686 return "brctg\t%1,%l0";
7688 return "aghi\t%1,-1\;jgne\t%l0";
7690 "&& reload_completed
7691 && (! REG_P (operands[2])
7692 || ! rtx_equal_p (operands[1], operands[2]))"
7693 [(set (match_dup 3) (match_dup 1))
7694 (parallel [(set (reg:CCAN CC_REGNUM)
7695 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
7697 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
7698 (set (match_dup 2) (match_dup 3))
7699 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
7700 (label_ref (match_dup 0))
7703 [(set_attr "op_type" "RI")
7704 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
7705 ; hurt us in the (rare) case of ahi.
7706 (set_attr "z10prop" "z10_super")
7707 (set_attr "type" "branch")
7708 (set (attr "length")
7709 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7710 (const_int 4) (const_int 10)))])
7713 ;;- Unconditional jump instructions.
7717 ; jump instruction pattern(s).
7720 (define_expand "jump"
7721 [(match_operand 0 "" "")]
7723 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
7725 (define_insn "*jump64"
7726 [(set (pc) (label_ref (match_operand 0 "" "")))]
7729 if (get_attr_length (insn) == 4)
7734 [(set_attr "op_type" "RI")
7735 (set_attr "type" "branch")
7736 (set (attr "length")
7737 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7738 (const_int 4) (const_int 6)))])
7740 (define_insn "*jump31"
7741 [(set (pc) (label_ref (match_operand 0 "" "")))]
7744 gcc_assert (get_attr_length (insn) == 4);
7747 [(set_attr "op_type" "RI")
7748 (set_attr "type" "branch")
7749 (set (attr "length")
7750 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7751 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7752 (const_int 4) (const_int 6))
7753 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7754 (const_int 4) (const_int 8))))])
7757 ; indirect-jump instruction pattern(s).
7760 (define_insn "indirect_jump"
7761 [(set (pc) (match_operand 0 "address_operand" "U"))]
7764 if (get_attr_op_type (insn) == OP_TYPE_RR)
7769 [(set (attr "op_type")
7770 (if_then_else (match_operand 0 "register_operand" "")
7771 (const_string "RR") (const_string "RX")))
7772 (set_attr "type" "branch")
7773 (set_attr "atype" "agen")
7774 (set_attr "z10prop" "z10_super")])
7777 ; casesi instruction pattern(s).
7780 (define_insn "casesi_jump"
7781 [(set (pc) (match_operand 0 "address_operand" "U"))
7782 (use (label_ref (match_operand 1 "" "")))]
7785 if (get_attr_op_type (insn) == OP_TYPE_RR)
7790 [(set (attr "op_type")
7791 (if_then_else (match_operand 0 "register_operand" "")
7792 (const_string "RR") (const_string "RX")))
7793 (set_attr "type" "branch")
7794 (set_attr "atype" "agen")])
7796 (define_expand "casesi"
7797 [(match_operand:SI 0 "general_operand" "")
7798 (match_operand:SI 1 "general_operand" "")
7799 (match_operand:SI 2 "general_operand" "")
7800 (label_ref (match_operand 3 "" ""))
7801 (label_ref (match_operand 4 "" ""))]
7804 rtx index = gen_reg_rtx (SImode);
7805 rtx base = gen_reg_rtx (Pmode);
7806 rtx target = gen_reg_rtx (Pmode);
7808 emit_move_insn (index, operands[0]);
7809 emit_insn (gen_subsi3 (index, index, operands[1]));
7810 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
7813 if (Pmode != SImode)
7814 index = convert_to_mode (Pmode, index, 1);
7815 if (GET_CODE (index) != REG)
7816 index = copy_to_mode_reg (Pmode, index);
7819 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
7821 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
7823 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
7825 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
7826 emit_move_insn (target, index);
7829 target = gen_rtx_PLUS (Pmode, base, target);
7830 emit_jump_insn (gen_casesi_jump (target, operands[3]));
7837 ;;- Jump to subroutine.
7842 ; untyped call instruction pattern(s).
7845 ;; Call subroutine returning any type.
7846 (define_expand "untyped_call"
7847 [(parallel [(call (match_operand 0 "" "")
7849 (match_operand 1 "" "")
7850 (match_operand 2 "" "")])]
7855 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7857 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7859 rtx set = XVECEXP (operands[2], 0, i);
7860 emit_move_insn (SET_DEST (set), SET_SRC (set));
7863 /* The optimizer does not know that the call sets the function value
7864 registers we stored in the result block. We avoid problems by
7865 claiming that all hard registers are used and clobbered at this
7867 emit_insn (gen_blockage ());
7872 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7873 ;; all of memory. This blocks insns from being moved across this point.
7875 (define_insn "blockage"
7876 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7879 [(set_attr "type" "none")
7880 (set_attr "length" "0")])
7886 (define_expand "sibcall"
7887 [(call (match_operand 0 "" "")
7888 (match_operand 1 "" ""))]
7891 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
7895 (define_insn "*sibcall_br"
7896 [(call (mem:QI (reg SIBCALL_REGNUM))
7897 (match_operand 0 "const_int_operand" "n"))]
7898 "SIBLING_CALL_P (insn)
7899 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
7901 [(set_attr "op_type" "RR")
7902 (set_attr "type" "branch")
7903 (set_attr "atype" "agen")])
7905 (define_insn "*sibcall_brc"
7906 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7907 (match_operand 1 "const_int_operand" "n"))]
7908 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7910 [(set_attr "op_type" "RI")
7911 (set_attr "type" "branch")])
7913 (define_insn "*sibcall_brcl"
7914 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7915 (match_operand 1 "const_int_operand" "n"))]
7916 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7918 [(set_attr "op_type" "RIL")
7919 (set_attr "type" "branch")])
7922 ; sibcall_value patterns
7925 (define_expand "sibcall_value"
7926 [(set (match_operand 0 "" "")
7927 (call (match_operand 1 "" "")
7928 (match_operand 2 "" "")))]
7931 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
7935 (define_insn "*sibcall_value_br"
7936 [(set (match_operand 0 "" "")
7937 (call (mem:QI (reg SIBCALL_REGNUM))
7938 (match_operand 1 "const_int_operand" "n")))]
7939 "SIBLING_CALL_P (insn)
7940 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
7942 [(set_attr "op_type" "RR")
7943 (set_attr "type" "branch")
7944 (set_attr "atype" "agen")])
7946 (define_insn "*sibcall_value_brc"
7947 [(set (match_operand 0 "" "")
7948 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7949 (match_operand 2 "const_int_operand" "n")))]
7950 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7952 [(set_attr "op_type" "RI")
7953 (set_attr "type" "branch")])
7955 (define_insn "*sibcall_value_brcl"
7956 [(set (match_operand 0 "" "")
7957 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7958 (match_operand 2 "const_int_operand" "n")))]
7959 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7961 [(set_attr "op_type" "RIL")
7962 (set_attr "type" "branch")])
7966 ; call instruction pattern(s).
7969 (define_expand "call"
7970 [(call (match_operand 0 "" "")
7971 (match_operand 1 "" ""))
7972 (use (match_operand 2 "" ""))]
7975 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
7976 gen_rtx_REG (Pmode, RETURN_REGNUM));
7980 (define_insn "*bras"
7981 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7982 (match_operand 1 "const_int_operand" "n"))
7983 (clobber (match_operand 2 "register_operand" "=r"))]
7984 "!SIBLING_CALL_P (insn)
7985 && TARGET_SMALL_EXEC
7986 && GET_MODE (operands[2]) == Pmode"
7988 [(set_attr "op_type" "RI")
7989 (set_attr "type" "jsr")])
7991 (define_insn "*brasl"
7992 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7993 (match_operand 1 "const_int_operand" "n"))
7994 (clobber (match_operand 2 "register_operand" "=r"))]
7995 "!SIBLING_CALL_P (insn)
7997 && GET_MODE (operands[2]) == Pmode"
7999 [(set_attr "op_type" "RIL")
8000 (set_attr "type" "jsr")])
8002 (define_insn "*basr"
8003 [(call (mem:QI (match_operand 0 "address_operand" "U"))
8004 (match_operand 1 "const_int_operand" "n"))
8005 (clobber (match_operand 2 "register_operand" "=r"))]
8006 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
8008 if (get_attr_op_type (insn) == OP_TYPE_RR)
8009 return "basr\t%2,%0";
8011 return "bas\t%2,%a0";
8013 [(set (attr "op_type")
8014 (if_then_else (match_operand 0 "register_operand" "")
8015 (const_string "RR") (const_string "RX")))
8016 (set_attr "type" "jsr")
8017 (set_attr "atype" "agen")])
8020 ; call_value instruction pattern(s).
8023 (define_expand "call_value"
8024 [(set (match_operand 0 "" "")
8025 (call (match_operand 1 "" "")
8026 (match_operand 2 "" "")))
8027 (use (match_operand 3 "" ""))]
8030 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
8031 gen_rtx_REG (Pmode, RETURN_REGNUM));
8035 (define_insn "*bras_r"
8036 [(set (match_operand 0 "" "")
8037 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8038 (match_operand:SI 2 "const_int_operand" "n")))
8039 (clobber (match_operand 3 "register_operand" "=r"))]
8040 "!SIBLING_CALL_P (insn)
8041 && TARGET_SMALL_EXEC
8042 && GET_MODE (operands[3]) == Pmode"
8044 [(set_attr "op_type" "RI")
8045 (set_attr "type" "jsr")])
8047 (define_insn "*brasl_r"
8048 [(set (match_operand 0 "" "")
8049 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8050 (match_operand 2 "const_int_operand" "n")))
8051 (clobber (match_operand 3 "register_operand" "=r"))]
8052 "!SIBLING_CALL_P (insn)
8054 && GET_MODE (operands[3]) == Pmode"
8056 [(set_attr "op_type" "RIL")
8057 (set_attr "type" "jsr")])
8059 (define_insn "*basr_r"
8060 [(set (match_operand 0 "" "")
8061 (call (mem:QI (match_operand 1 "address_operand" "U"))
8062 (match_operand 2 "const_int_operand" "n")))
8063 (clobber (match_operand 3 "register_operand" "=r"))]
8064 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8066 if (get_attr_op_type (insn) == OP_TYPE_RR)
8067 return "basr\t%3,%1";
8069 return "bas\t%3,%a1";
8071 [(set (attr "op_type")
8072 (if_then_else (match_operand 1 "register_operand" "")
8073 (const_string "RR") (const_string "RX")))
8074 (set_attr "type" "jsr")
8075 (set_attr "atype" "agen")])
8078 ;;- Thread-local storage support.
8081 (define_expand "get_tp_64"
8082 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
8086 (define_expand "get_tp_31"
8087 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
8091 (define_expand "set_tp_64"
8092 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
8093 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
8097 (define_expand "set_tp_31"
8098 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
8099 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
8103 (define_insn "*set_tp"
8104 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
8107 [(set_attr "type" "none")
8108 (set_attr "length" "0")])
8110 (define_insn "*tls_load_64"
8111 [(set (match_operand:DI 0 "register_operand" "=d")
8112 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
8113 (match_operand:DI 2 "" "")]
8117 [(set_attr "op_type" "RXE")
8118 (set_attr "z10prop" "z10_fwd_A3")])
8120 (define_insn "*tls_load_31"
8121 [(set (match_operand:SI 0 "register_operand" "=d,d")
8122 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
8123 (match_operand:SI 2 "" "")]
8129 [(set_attr "op_type" "RX,RXY")
8130 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
8132 (define_insn "*bras_tls"
8133 [(set (match_operand 0 "" "")
8134 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8135 (match_operand 2 "const_int_operand" "n")))
8136 (clobber (match_operand 3 "register_operand" "=r"))
8137 (use (match_operand 4 "" ""))]
8138 "!SIBLING_CALL_P (insn)
8139 && TARGET_SMALL_EXEC
8140 && GET_MODE (operands[3]) == Pmode"
8142 [(set_attr "op_type" "RI")
8143 (set_attr "type" "jsr")])
8145 (define_insn "*brasl_tls"
8146 [(set (match_operand 0 "" "")
8147 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
8148 (match_operand 2 "const_int_operand" "n")))
8149 (clobber (match_operand 3 "register_operand" "=r"))
8150 (use (match_operand 4 "" ""))]
8151 "!SIBLING_CALL_P (insn)
8153 && GET_MODE (operands[3]) == Pmode"
8155 [(set_attr "op_type" "RIL")
8156 (set_attr "type" "jsr")])
8158 (define_insn "*basr_tls"
8159 [(set (match_operand 0 "" "")
8160 (call (mem:QI (match_operand 1 "address_operand" "U"))
8161 (match_operand 2 "const_int_operand" "n")))
8162 (clobber (match_operand 3 "register_operand" "=r"))
8163 (use (match_operand 4 "" ""))]
8164 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
8166 if (get_attr_op_type (insn) == OP_TYPE_RR)
8167 return "basr\t%3,%1%J4";
8169 return "bas\t%3,%a1%J4";
8171 [(set (attr "op_type")
8172 (if_then_else (match_operand 1 "register_operand" "")
8173 (const_string "RR") (const_string "RX")))
8174 (set_attr "type" "jsr")
8175 (set_attr "atype" "agen")])
8178 ;;- Atomic operations
8182 ; memory barrier pattern.
8185 (define_expand "memory_barrier"
8186 [(set (mem:BLK (match_dup 0))
8187 (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
8190 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
8191 MEM_VOLATILE_P (operands[0]) = 1;
8194 (define_insn "*memory_barrier"
8195 [(set (match_operand:BLK 0 "" "")
8196 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
8199 [(set_attr "op_type" "RR")])
8200 ; Although bcr is superscalar on Z10, this variant will never become part of
8201 ; an execution group.
8204 ; compare and swap patterns.
8207 (define_expand "sync_compare_and_swap<mode>"
8209 [(set (match_operand:TDSI 0 "register_operand" "")
8210 (match_operand:TDSI 1 "memory_operand" ""))
8212 (unspec_volatile:TDSI
8214 (match_operand:TDSI 2 "register_operand" "")
8215 (match_operand:TDSI 3 "register_operand" "")]
8217 (set (reg:CCZ1 CC_REGNUM)
8218 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8221 (define_expand "sync_compare_and_swap<mode>"
8223 [(set (match_operand:HQI 0 "register_operand" "")
8224 (match_operand:HQI 1 "memory_operand" ""))
8226 (unspec_volatile:HQI
8228 (match_operand:HQI 2 "general_operand" "")
8229 (match_operand:HQI 3 "general_operand" "")]
8231 (set (reg:CCZ1 CC_REGNUM)
8232 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8234 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
8235 operands[2], operands[3]); DONE;")
8237 (define_expand "sync_compare_and_swap_cc<mode>"
8239 [(set (match_operand:TDSI 0 "register_operand" "")
8240 (match_operand:TDSI 1 "memory_operand" ""))
8242 (unspec_volatile:TDSI
8244 (match_operand:TDSI 2 "register_operand" "")
8245 (match_operand:TDSI 3 "register_operand" "")]
8248 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
8251 /* Emulate compare. */
8252 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
8253 s390_compare_op0 = operands[1];
8254 s390_compare_op1 = operands[2];
8255 s390_compare_emitted = operands[4];
8259 (define_insn "*sync_compare_and_swap<mode>"
8260 [(set (match_operand:DP 0 "register_operand" "=r")
8261 (match_operand:DP 1 "memory_operand" "+Q"))
8265 (match_operand:DP 2 "register_operand" "0")
8266 (match_operand:DP 3 "register_operand" "r")]
8268 (set (reg:CCZ1 CC_REGNUM)
8269 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8271 "cds<tg>\t%0,%3,%S1"
8272 [(set_attr "op_type" "RS<TE>")
8273 (set_attr "type" "sem")])
8276 (define_insn "*sync_compare_and_swap<mode>"
8277 [(set (match_operand:GPR 0 "register_operand" "=r")
8278 (match_operand:GPR 1 "memory_operand" "+Q"))
8280 (unspec_volatile:GPR
8282 (match_operand:GPR 2 "register_operand" "0")
8283 (match_operand:GPR 3 "register_operand" "r")]
8285 (set (reg:CCZ1 CC_REGNUM)
8286 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
8289 [(set_attr "op_type" "RS<E>")
8290 (set_attr "type" "sem")])
8294 ; Other atomic instruction patterns.
8297 (define_expand "sync_lock_test_and_set<mode>"
8298 [(match_operand:HQI 0 "register_operand")
8299 (match_operand:HQI 1 "memory_operand")
8300 (match_operand:HQI 2 "general_operand")]
8302 "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
8303 operands[2], false); DONE;")
8305 (define_expand "sync_<atomic><mode>"
8306 [(set (match_operand:HQI 0 "memory_operand")
8307 (ATOMIC:HQI (match_dup 0)
8308 (match_operand:HQI 1 "general_operand")))]
8310 "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
8311 operands[1], false); DONE;")
8313 (define_expand "sync_old_<atomic><mode>"
8314 [(set (match_operand:HQI 0 "register_operand")
8315 (match_operand:HQI 1 "memory_operand"))
8317 (ATOMIC:HQI (match_dup 1)
8318 (match_operand:HQI 2 "general_operand")))]
8320 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
8321 operands[2], false); DONE;")
8323 (define_expand "sync_new_<atomic><mode>"
8324 [(set (match_operand:HQI 0 "register_operand")
8325 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
8326 (match_operand:HQI 2 "general_operand")))
8327 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
8329 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
8330 operands[2], true); DONE;")
8333 ;;- Miscellaneous instructions.
8337 ; allocate stack instruction pattern(s).
8340 (define_expand "allocate_stack"
8341 [(match_operand 0 "general_operand" "")
8342 (match_operand 1 "general_operand" "")]
8345 rtx temp = gen_reg_rtx (Pmode);
8347 emit_move_insn (temp, s390_back_chain_rtx ());
8348 anti_adjust_stack (operands[1]);
8349 emit_move_insn (s390_back_chain_rtx (), temp);
8351 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
8357 ; setjmp instruction pattern.
8360 (define_expand "builtin_setjmp_receiver"
8361 [(match_operand 0 "" "")]
8364 emit_insn (s390_load_got ());
8365 emit_use (pic_offset_table_rtx);
8369 ;; These patterns say how to save and restore the stack pointer. We need not
8370 ;; save the stack pointer at function level since we are careful to
8371 ;; preserve the backchain. At block level, we have to restore the backchain
8372 ;; when we restore the stack pointer.
8374 ;; For nonlocal gotos, we must save both the stack pointer and its
8375 ;; backchain and restore both. Note that in the nonlocal case, the
8376 ;; save area is a memory location.
8378 (define_expand "save_stack_function"
8379 [(match_operand 0 "general_operand" "")
8380 (match_operand 1 "general_operand" "")]
8384 (define_expand "restore_stack_function"
8385 [(match_operand 0 "general_operand" "")
8386 (match_operand 1 "general_operand" "")]
8390 (define_expand "restore_stack_block"
8391 [(match_operand 0 "register_operand" "")
8392 (match_operand 1 "register_operand" "")]
8395 rtx temp = gen_reg_rtx (Pmode);
8397 emit_move_insn (temp, s390_back_chain_rtx ());
8398 emit_move_insn (operands[0], operands[1]);
8399 emit_move_insn (s390_back_chain_rtx (), temp);
8404 (define_expand "save_stack_nonlocal"
8405 [(match_operand 0 "memory_operand" "")
8406 (match_operand 1 "register_operand" "")]
8409 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
8410 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8412 /* Copy the backchain to the first word, sp to the second and the
8413 literal pool base to the third. */
8415 if (TARGET_BACKCHAIN)
8417 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
8418 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
8421 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
8422 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
8427 (define_expand "restore_stack_nonlocal"
8428 [(match_operand 0 "register_operand" "")
8429 (match_operand 1 "memory_operand" "")]
8432 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
8433 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
8434 rtx temp = NULL_RTX;
8436 /* Restore the backchain from the first word, sp from the second and the
8437 literal pool base from the third. */
8439 if (TARGET_BACKCHAIN)
8440 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
8442 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
8443 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
8446 emit_move_insn (s390_back_chain_rtx (), temp);
8452 (define_expand "exception_receiver"
8456 s390_set_has_landing_pad_p (true);
8461 ; nop instruction pattern(s).
8468 [(set_attr "op_type" "RR")])
8474 [(set_attr "op_type" "RR")])
8478 ; Special literal pool access instruction pattern(s).
8481 (define_insn "*pool_entry"
8482 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
8483 UNSPECV_POOL_ENTRY)]
8486 enum machine_mode mode = GET_MODE (PATTERN (insn));
8487 unsigned int align = GET_MODE_BITSIZE (mode);
8488 s390_output_pool_entry (operands[0], mode, align);
8491 [(set (attr "length")
8492 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
8494 (define_insn "pool_align"
8495 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
8496 UNSPECV_POOL_ALIGN)]
8499 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8501 (define_insn "pool_section_start"
8502 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
8505 [(set_attr "length" "0")])
8507 (define_insn "pool_section_end"
8508 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
8511 [(set_attr "length" "0")])
8513 (define_insn "main_base_31_small"
8514 [(set (match_operand 0 "register_operand" "=a")
8515 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8516 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8518 [(set_attr "op_type" "RR")
8519 (set_attr "type" "la")])
8521 (define_insn "main_base_31_large"
8522 [(set (match_operand 0 "register_operand" "=a")
8523 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
8524 (set (pc) (label_ref (match_operand 2 "" "")))]
8525 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8527 [(set_attr "op_type" "RI")])
8529 (define_insn "main_base_64"
8530 [(set (match_operand 0 "register_operand" "=a")
8531 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8532 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8534 [(set_attr "op_type" "RIL")
8535 (set_attr "type" "larl")
8536 (set_attr "z10prop" "z10_super_A1")])
8538 (define_insn "main_pool"
8539 [(set (match_operand 0 "register_operand" "=a")
8540 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
8541 "GET_MODE (operands[0]) == Pmode"
8546 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
8547 (const_string "larl") (const_string "la")))])
8549 (define_insn "reload_base_31"
8550 [(set (match_operand 0 "register_operand" "=a")
8551 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8552 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8553 "basr\t%0,0\;la\t%0,%1-.(%0)"
8554 [(set_attr "length" "6")
8555 (set_attr "type" "la")])
8557 (define_insn "reload_base_64"
8558 [(set (match_operand 0 "register_operand" "=a")
8559 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8560 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8562 [(set_attr "op_type" "RIL")
8563 (set_attr "type" "larl")
8564 (set_attr "z10prop" "z10_super_A1")])
8567 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
8572 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8575 ;; Insns related to generating the function prologue and epilogue.
8579 (define_expand "prologue"
8580 [(use (const_int 0))]
8582 "s390_emit_prologue (); DONE;")
8584 (define_expand "epilogue"
8585 [(use (const_int 1))]
8587 "s390_emit_epilogue (false); DONE;")
8589 (define_expand "sibcall_epilogue"
8590 [(use (const_int 0))]
8592 "s390_emit_epilogue (true); DONE;")
8594 (define_insn "*return"
8596 (use (match_operand 0 "register_operand" "a"))]
8597 "GET_MODE (operands[0]) == Pmode"
8599 [(set_attr "op_type" "RR")
8600 (set_attr "type" "jsr")
8601 (set_attr "atype" "agen")])
8604 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
8605 ;; pointer. This is used for compatibility.
8607 (define_expand "ptr_extend"
8608 [(set (match_operand:DI 0 "register_operand" "=r")
8609 (match_operand:SI 1 "register_operand" "r"))]
8612 emit_insn (gen_anddi3 (operands[0],
8613 gen_lowpart (DImode, operands[1]),
8614 GEN_INT (0x7fffffff)));
8618 ;; Instruction definition to expand eh_return macro to support
8619 ;; swapping in special linkage return addresses.
8621 (define_expand "eh_return"
8622 [(use (match_operand 0 "register_operand" ""))]
8625 s390_emit_tpf_eh_return (operands[0]);
8630 ; Stack Protector Patterns
8633 (define_expand "stack_protect_set"
8634 [(set (match_operand 0 "memory_operand" "")
8635 (match_operand 1 "memory_operand" ""))]
8638 #ifdef TARGET_THREAD_SSP_OFFSET
8640 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
8641 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
8644 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
8646 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
8651 (define_insn "stack_protect_set<mode>"
8652 [(set (match_operand:DSI 0 "memory_operand" "=Q")
8653 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
8655 "mvc\t%O0(%G0,%R0),%S1"
8656 [(set_attr "op_type" "SS")])
8658 (define_expand "stack_protect_test"
8659 [(set (reg:CC CC_REGNUM)
8660 (compare (match_operand 0 "memory_operand" "")
8661 (match_operand 1 "memory_operand" "")))
8662 (match_operand 2 "" "")]
8665 #ifdef TARGET_THREAD_SSP_OFFSET
8667 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
8668 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
8670 s390_compare_op0 = operands[0];
8671 s390_compare_op1 = operands[1];
8672 s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM);
8675 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
8677 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
8679 emit_jump_insn (gen_beq (operands[2]));
8684 (define_insn "stack_protect_test<mode>"
8685 [(set (reg:CCZ CC_REGNUM)
8686 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
8687 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
8689 "clc\t%O0(%G0,%R0),%S1"
8690 [(set_attr "op_type" "SS")])
8692 ; This is used in s390_emit_prologue in order to prevent insns
8693 ; adjusting the stack pointer to be moved over insns writing stack
8694 ; slots using a copy of the stack pointer in a different register.
8695 (define_insn "stack_tie"
8696 [(set (match_operand:BLK 0 "memory_operand" "+m")
8697 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
8700 [(set_attr "length" "0")])
8704 ; Data prefetch patterns
8707 (define_insn "prefetch"
8708 [(prefetch (match_operand 0 "address_operand" "UW,X")
8709 (match_operand:SI 1 "const_int_operand" "n,n")
8710 (match_operand:SI 2 "const_int_operand" "n,n"))]
8713 if (larl_operand (operands[0], Pmode))
8714 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
8716 if (s390_mem_constraint ("W", operands[0])
8717 || s390_mem_constraint ("U", operands[0]))
8718 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0";
8720 /* This point might be reached if op0 is a larl operand with an
8721 uneven addend. In this case we simply omit issuing a prefetch
8726 [(set_attr "type" "load,larl")
8727 (set_attr "op_type" "RXY,RIL")
8728 (set_attr "z10prop" "z10_super")])