1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
50 ;; We have a special constraint for pattern matching.
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
66 ; GOT/PLT and lt-relative accesses
67 (UNSPEC_LTREL_OFFSET 100)
68 (UNSPEC_LTREL_BASE 101)
76 (UNSPEC_RELOAD_BASE 210)
77 (UNSPEC_MAIN_BASE 211)
82 ; TLS relocation specifiers
87 (UNSPEC_GOTNTPOFF 504)
88 (UNSPEC_INDNTPOFF 505)
91 (UNSPEC_TLSLDM_NTPOFF 511)
98 ; Stack Smashing Protector
102 ; Copy sign instructions
103 (UNSPEC_COPYSIGN 800)
105 ; Test Data Class (TDC)
106 (UNSPEC_TDC_INSN 900)
110 ;; UNSPEC_VOLATILE usage
118 (UNSPECV_TPF_PROLOGUE 20)
119 (UNSPECV_TPF_EPILOGUE 21)
123 (UNSPECV_POOL_SECTION 201)
124 (UNSPECV_POOL_ALIGN 202)
125 (UNSPECV_POOL_ENTRY 203)
126 (UNSPECV_MAIN_POOL 300)
140 ; Registers with special meaning
144 ; Sibling call register.
146 ; Literal pool base register.
148 ; Return address register.
150 ; Condition code register.
152 ; Thread local storage pointer register.
156 ; Hardware register names
160 ; General purpose registers
162 ; Floating point registers.
168 ;; PFPO GPR0 argument format
173 ; PFPO operation type
174 (PFPO_CONVERT 0x1000000)
176 (PFPO_OP_TYPE_SF 0x5)
177 (PFPO_OP_TYPE_DF 0x6)
178 (PFPO_OP_TYPE_TF 0x7)
179 (PFPO_OP_TYPE_SD 0x8)
180 (PFPO_OP_TYPE_DD 0x9)
181 (PFPO_OP_TYPE_TD 0xa)
182 ; Bitposition of operand types
183 (PFPO_OP0_TYPE_SHIFT 16)
184 (PFPO_OP1_TYPE_SHIFT 8)
188 ;; Instruction operand type as used in the Principles of Operation.
189 ;; Used to determine defaults for length and other attribute values.
191 (define_attr "op_type"
192 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR"
195 ;; Instruction type attribute used for scheduling.
197 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
198 cs,vs,store,sem,idiv,
199 imulhi,imulsi,imuldi,
200 branch,jsr,fsimptf,fsimpdf,fsimpsf,
201 floadtf,floaddf,floadsf,fstoredf,fstoresf,
202 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
203 ftoi,itof,fsqrttf,fsqrtdf,fsqrtsf,
204 ftrunctf,ftruncdf,other"
205 (cond [(eq_attr "op_type" "NN") (const_string "other")
206 (eq_attr "op_type" "SS") (const_string "cs")]
207 (const_string "integer")))
209 ;; Another attribute used for scheduling purposes:
210 ;; agen: Instruction uses the address generation unit
211 ;; reg: Instruction does not use the agen unit
213 (define_attr "atype" "agen,reg"
214 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE")
216 (const_string "agen")))
220 (define_attr "length" ""
221 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
222 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI") (const_int 4)]
226 ;; Processor type. This attribute must exactly match the processor_type
227 ;; enumeration in s390.h. The current machine description does not
228 ;; distinguish between g5 and g6, but there are differences between the two
229 ;; CPUs could in theory be modeled.
231 (define_attr "cpu" "g5,g6,z900,z990,z9_109"
232 (const (symbol_ref "s390_tune")))
234 ;; Pipeline description for z900. For lack of anything better,
235 ;; this description is also used for the g5 and g6.
238 ;; Pipeline description for z990, z9-109 and z9-ec.
242 (include "predicates.md")
244 ;; Constraint definitions
245 (include "constraints.md")
252 ;; This mode macro allows floating point patterns to be generated from the
254 (define_mode_macro FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
255 (define_mode_macro BFP [TF DF SF])
256 (define_mode_macro DFP [TD DD])
257 (define_mode_macro DFP_ALL [TD DD SD])
258 (define_mode_macro DSF [DF SF])
259 (define_mode_macro SD_SF [SF SD])
260 (define_mode_macro DD_DF [DF DD])
261 (define_mode_macro TD_TF [TF TD])
263 ;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated
264 ;; from the same template.
265 (define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI])
267 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
268 ;; from the same template.
269 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
270 (define_mode_macro DSI [DI SI])
272 ;; This mode macro allows :P to be used for patterns that operate on
273 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
274 (define_mode_macro DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
275 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
277 ;; This mode macro allows the QI and HI patterns to be defined from
278 ;; the same template.
279 (define_mode_macro HQI [HI QI])
281 ;; This mode macro allows the integer patterns to be defined from the
283 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
285 ;; This macro allows to unify all 'bCOND' expander patterns.
286 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
287 ordered uneq unlt ungt unle unge ltgt])
289 ;; This macro allows to unify all 'sCOND' patterns.
290 (define_code_macro SCOND [ltu gtu leu geu])
292 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
293 ;; the same template.
294 (define_code_macro SHIFT [ashift lshiftrt])
296 ;; These macros allow to combine most atomic operations.
297 (define_code_macro ATOMIC [and ior xor plus minus mult])
298 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
299 (plus "add") (minus "sub") (mult "nand")])
301 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
302 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
303 (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")])
305 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in
306 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in
308 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")])
310 ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
311 ;; Likewise for "<RXe>".
312 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
313 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
315 ;; The decimal floating point variants of add, sub, div and mul support 3
316 ;; fp register operands. The following macros allow to merge the bfp and
317 ;; dfp variants in a single insn definition.
319 ;; This macro is used to set op_type accordingly.
320 (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
321 (DD "RRR") (SD "RRR")])
323 ;; This macro is used in the operand constraint list in order to have the
324 ;; first and the second operand match for bfp modes.
325 (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
327 ;; This macro is used in the operand list of the instruction to have an
328 ;; additional operand for the dfp instructions.
329 (define_mode_attr op1 [(TF "") (DF "") (SF "")
330 (TD "%1,") (DD "%1,") (SD "%1,")])
333 ;; This attribute is used in the operand constraint list
334 ;; for instructions dealing with the sign bit of 32 or 64bit fp values.
335 ;; TFmode values are represented by a fp register pair. Since the
336 ;; sign bit instructions only handle single source and target fp registers
337 ;; these instructions can only be used for TFmode values if the source and
338 ;; target operand uses the same fp register.
339 (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
341 ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
342 ;; This is used to disable the memory alternative in TFmode patterns.
343 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
345 ;; This macro adds b for bfp instructions and t for dfp instructions and is used
346 ;; within instruction mnemonics.
347 (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
349 ;; Although it is imprecise for z9-ec we handle all dfp instructions like
350 ;; bfp regarding the pipeline description.
351 (define_mode_attr bfp [(TF "tf") (DF "df") (SF "sf")
352 (TD "tf") (DD "df") (SD "sf")])
355 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
356 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
357 ;; version only operates on one register.
358 (define_mode_attr d0 [(DI "d") (SI "0")])
360 ;; In combination with d0 this allows to combine instructions of which the 31bit
361 ;; version only operates on one register. The DImode version needs an additional
362 ;; register for the assembler output.
363 (define_mode_attr 1 [(DI "%1,") (SI "")])
365 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
366 ;; 'ashift' and "srdl" in 'lshiftrt'.
367 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
369 ;; In SHIFT templates, this attribute holds the correct standard name for the
370 ;; pattern itself and the corresponding function calls.
371 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
373 ;; This attribute handles differences in the instruction 'type' and will result
374 ;; in "RRE" for DImode and "RR" for SImode.
375 (define_mode_attr E [(DI "E") (SI "")])
377 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
378 ;; to result in "RXY" for DImode and "RX" for SImode.
379 (define_mode_attr Y [(DI "Y") (SI "")])
381 ;; This attribute handles differences in the instruction 'type' and will result
382 ;; in "RSE" for TImode and "RS" for DImode.
383 (define_mode_attr TE [(TI "E") (DI "")])
385 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
386 ;; and "lcr" in SImode.
387 (define_mode_attr g [(DI "g") (SI "")])
389 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
390 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
391 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
392 ;; variant for long displacements.
393 (define_mode_attr y [(DI "g") (SI "y")])
395 ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
396 ;; and "cds" in DImode.
397 (define_mode_attr tg [(TI "g") (DI "")])
399 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
400 ;; and "cfdbr" in SImode.
401 (define_mode_attr gf [(DI "g") (SI "f")])
403 ;; ICM mask required to load MODE value into the lowest subreg
404 ;; of a SImode register.
405 (define_mode_attr icm_lo [(HI "3") (QI "1")])
407 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
408 ;; HImode and "llgc" in QImode.
409 (define_mode_attr hc [(HI "h") (QI "c")])
411 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
413 (define_mode_attr DBL [(DI "TI") (SI "DI")])
415 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is
416 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies.
417 (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")])
419 ;; Maximum unsigned integer that fits in MODE.
420 (define_mode_attr max_uint [(HI "65535") (QI "255")])
424 ;;- Compare instructions.
427 (define_expand "cmp<mode>"
428 [(set (reg:CC CC_REGNUM)
429 (compare:CC (match_operand:GPR 0 "register_operand" "")
430 (match_operand:GPR 1 "general_operand" "")))]
433 s390_compare_op0 = operands[0];
434 s390_compare_op1 = operands[1];
438 (define_expand "cmp<mode>"
439 [(set (reg:CC CC_REGNUM)
440 (compare:CC (match_operand:FP 0 "register_operand" "")
441 (match_operand:FP 1 "general_operand" "")))]
444 s390_compare_op0 = operands[0];
445 s390_compare_op1 = operands[1];
450 ; Test-under-Mask instructions
452 (define_insn "*tmqi_mem"
453 [(set (reg CC_REGNUM)
454 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
455 (match_operand:QI 1 "immediate_operand" "n,n"))
456 (match_operand:QI 2 "immediate_operand" "n,n")))]
457 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
461 [(set_attr "op_type" "SI,SIY")])
463 (define_insn "*tmdi_reg"
464 [(set (reg CC_REGNUM)
465 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
466 (match_operand:DI 1 "immediate_operand"
467 "N0HD0,N1HD0,N2HD0,N3HD0"))
468 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
470 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
471 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
477 [(set_attr "op_type" "RI")])
479 (define_insn "*tmsi_reg"
480 [(set (reg CC_REGNUM)
481 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
482 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
483 (match_operand:SI 2 "immediate_operand" "n,n")))]
484 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
485 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
489 [(set_attr "op_type" "RI")])
491 (define_insn "*tm<mode>_full"
492 [(set (reg CC_REGNUM)
493 (compare (match_operand:HQI 0 "register_operand" "d")
494 (match_operand:HQI 1 "immediate_operand" "n")))]
495 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
497 [(set_attr "op_type" "RI")])
501 ; Load-and-Test instructions
504 ; tst(di|si) instruction pattern(s).
506 (define_insn "*tstdi_sign"
507 [(set (reg CC_REGNUM)
508 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
509 (const_int 32)) (const_int 32))
510 (match_operand:DI 1 "const0_operand" "")))
511 (set (match_operand:DI 2 "register_operand" "=d")
512 (sign_extend:DI (match_dup 0)))]
513 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
515 [(set_attr "op_type" "RRE")])
518 (define_insn "*tst<mode>_extimm"
519 [(set (reg CC_REGNUM)
520 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
521 (match_operand:GPR 1 "const0_operand" "")))
522 (set (match_operand:GPR 2 "register_operand" "=d,d")
524 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
528 [(set_attr "op_type" "RR<E>,RXY")])
531 (define_insn "*tst<mode>_cconly_extimm"
532 [(set (reg CC_REGNUM)
533 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
534 (match_operand:GPR 1 "const0_operand" "")))
535 (clobber (match_scratch:GPR 2 "=X,d"))]
536 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
540 [(set_attr "op_type" "RR<E>,RXY")])
542 (define_insn "*tstdi"
543 [(set (reg CC_REGNUM)
544 (compare (match_operand:DI 0 "register_operand" "d")
545 (match_operand:DI 1 "const0_operand" "")))
546 (set (match_operand:DI 2 "register_operand" "=d")
548 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
550 [(set_attr "op_type" "RRE")])
552 (define_insn "*tstsi"
553 [(set (reg CC_REGNUM)
554 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
555 (match_operand:SI 1 "const0_operand" "")))
556 (set (match_operand:SI 2 "register_operand" "=d,d,d")
558 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
563 [(set_attr "op_type" "RR,RS,RSY")])
565 (define_insn "*tstsi_cconly"
566 [(set (reg CC_REGNUM)
567 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
568 (match_operand:SI 1 "const0_operand" "")))
569 (clobber (match_scratch:SI 2 "=X,d,d"))]
570 "s390_match_ccmode(insn, CCSmode)"
575 [(set_attr "op_type" "RR,RS,RSY")])
577 (define_insn "*tstdi_cconly_31"
578 [(set (reg CC_REGNUM)
579 (compare (match_operand:DI 0 "register_operand" "d")
580 (match_operand:DI 1 "const0_operand" "")))]
581 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
583 [(set_attr "op_type" "RS")
584 (set_attr "atype" "reg")])
587 (define_insn "*tst<mode>_cconly2"
588 [(set (reg CC_REGNUM)
589 (compare (match_operand:GPR 0 "register_operand" "d")
590 (match_operand:GPR 1 "const0_operand" "")))]
591 "s390_match_ccmode(insn, CCSmode)"
593 [(set_attr "op_type" "RR<E>")])
595 ; tst(hi|qi) instruction pattern(s).
597 (define_insn "*tst<mode>CCT"
598 [(set (reg CC_REGNUM)
599 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
600 (match_operand:HQI 1 "const0_operand" "")))
601 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
603 "s390_match_ccmode(insn, CCTmode)"
606 icmy\t%2,<icm_lo>,%S0
608 [(set_attr "op_type" "RS,RSY,RI")])
610 (define_insn "*tsthiCCT_cconly"
611 [(set (reg CC_REGNUM)
612 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
613 (match_operand:HI 1 "const0_operand" "")))
614 (clobber (match_scratch:HI 2 "=d,d,X"))]
615 "s390_match_ccmode(insn, CCTmode)"
620 [(set_attr "op_type" "RS,RSY,RI")])
622 (define_insn "*tstqiCCT_cconly"
623 [(set (reg CC_REGNUM)
624 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
625 (match_operand:QI 1 "const0_operand" "")))]
626 "s390_match_ccmode(insn, CCTmode)"
631 [(set_attr "op_type" "SI,SIY,RI")])
633 (define_insn "*tst<mode>"
634 [(set (reg CC_REGNUM)
635 (compare (match_operand:HQI 0 "s_operand" "Q,S")
636 (match_operand:HQI 1 "const0_operand" "")))
637 (set (match_operand:HQI 2 "register_operand" "=d,d")
639 "s390_match_ccmode(insn, CCSmode)"
642 icmy\t%2,<icm_lo>,%S0"
643 [(set_attr "op_type" "RS,RSY")])
645 (define_insn "*tst<mode>_cconly"
646 [(set (reg CC_REGNUM)
647 (compare (match_operand:HQI 0 "s_operand" "Q,S")
648 (match_operand:HQI 1 "const0_operand" "")))
649 (clobber (match_scratch:HQI 2 "=d,d"))]
650 "s390_match_ccmode(insn, CCSmode)"
653 icmy\t%2,<icm_lo>,%S0"
654 [(set_attr "op_type" "RS,RSY")])
657 ; Compare (equality) instructions
659 (define_insn "*cmpdi_cct"
660 [(set (reg CC_REGNUM)
661 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
662 (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))]
663 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
670 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")])
672 (define_insn "*cmpsi_cct"
673 [(set (reg CC_REGNUM)
674 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
675 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
676 "s390_match_ccmode (insn, CCTmode)"
684 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")])
687 ; Compare (signed) instructions
689 (define_insn "*cmpdi_ccs_sign"
690 [(set (reg CC_REGNUM)
691 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
692 (match_operand:DI 0 "register_operand" "d,d")))]
693 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
697 [(set_attr "op_type" "RRE,RXY")])
699 (define_insn "*cmpsi_ccs_sign"
700 [(set (reg CC_REGNUM)
701 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
702 (match_operand:SI 0 "register_operand" "d,d")))]
703 "s390_match_ccmode(insn, CCSRmode)"
707 [(set_attr "op_type" "RX,RXY")])
709 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg
710 (define_insn "*cmp<mode>_ccs"
711 [(set (reg CC_REGNUM)
712 (compare (match_operand:GPR 0 "register_operand" "d,d,d,d,d")
713 (match_operand:GPR 1 "general_operand" "d,K,Os,R,T")))]
714 "s390_match_ccmode(insn, CCSmode)"
721 [(set_attr "op_type" "RR<E>,RI,RIL,RX<Y>,RXY")])
724 ; Compare (unsigned) instructions
726 (define_insn "*cmpdi_ccu_zero"
727 [(set (reg CC_REGNUM)
728 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
729 (match_operand:DI 0 "register_operand" "d,d")))]
730 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
734 [(set_attr "op_type" "RRE,RXY")])
736 (define_insn "*cmpdi_ccu"
737 [(set (reg CC_REGNUM)
738 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
739 (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))]
740 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
747 [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")])
749 (define_insn "*cmpsi_ccu"
750 [(set (reg CC_REGNUM)
751 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ")
752 (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))]
753 "s390_match_ccmode (insn, CCUmode)"
761 [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")])
763 (define_insn "*cmphi_ccu"
764 [(set (reg CC_REGNUM)
765 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
766 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
767 "s390_match_ccmode (insn, CCUmode)
768 && !register_operand (operands[1], HImode)"
774 [(set_attr "op_type" "RS,RSY,SS,SS")])
776 (define_insn "*cmpqi_ccu"
777 [(set (reg CC_REGNUM)
778 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
779 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
780 "s390_match_ccmode (insn, CCUmode)
781 && !register_operand (operands[1], QImode)"
789 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
792 ; Block compare (CLC) instruction patterns.
795 [(set (reg CC_REGNUM)
796 (compare (match_operand:BLK 0 "memory_operand" "Q")
797 (match_operand:BLK 1 "memory_operand" "Q")))
798 (use (match_operand 2 "const_int_operand" "n"))]
799 "s390_match_ccmode (insn, CCUmode)
800 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
801 "clc\t%O0(%2,%R0),%S1"
802 [(set_attr "op_type" "SS")])
805 [(set (reg CC_REGNUM)
806 (compare (match_operand 0 "memory_operand" "")
807 (match_operand 1 "memory_operand" "")))]
809 && s390_match_ccmode (insn, CCUmode)
810 && GET_MODE (operands[0]) == GET_MODE (operands[1])
811 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
813 [(set (match_dup 0) (match_dup 1))
814 (use (match_dup 2))])]
816 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
817 operands[0] = adjust_address (operands[0], BLKmode, 0);
818 operands[1] = adjust_address (operands[1], BLKmode, 0);
820 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
821 operands[0], operands[1]);
822 operands[0] = SET_DEST (PATTERN (curr_insn));
826 ; (TF|DF|SF|TD|DD|SD) instructions
828 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
829 (define_insn "*cmp<mode>_ccs_0"
830 [(set (reg CC_REGNUM)
831 (compare (match_operand:FP 0 "register_operand" "f")
832 (match_operand:FP 1 "const0_operand" "")))]
833 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
834 "lt<xde><bt>r\t%0,%0"
835 [(set_attr "op_type" "RRE")
836 (set_attr "type" "fsimp<bfp>")])
838 ; cxtr, cxbr, cdbr, cebr, cxb, cdb, ceb, cxbtr, cdbtr
839 (define_insn "*cmp<mode>_ccs"
840 [(set (reg CC_REGNUM)
841 (compare (match_operand:FP 0 "register_operand" "f,f")
842 (match_operand:FP 1 "general_operand" "f,<Rf>")))]
843 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
847 [(set_attr "op_type" "RRE,RXE")
848 (set_attr "type" "fsimp<bfp>")])
851 ;;- Move instructions.
855 ; movti instruction pattern(s).
859 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
860 (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))]
868 [(set_attr "op_type" "RSY,RSY,*,*,SS")
869 (set_attr "type" "lm,stm,*,*,*")])
872 [(set (match_operand:TI 0 "nonimmediate_operand" "")
873 (match_operand:TI 1 "general_operand" ""))]
874 "TARGET_64BIT && reload_completed
875 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
876 [(set (match_dup 2) (match_dup 4))
877 (set (match_dup 3) (match_dup 5))]
879 operands[2] = operand_subword (operands[0], 0, 0, TImode);
880 operands[3] = operand_subword (operands[0], 1, 0, TImode);
881 operands[4] = operand_subword (operands[1], 0, 0, TImode);
882 operands[5] = operand_subword (operands[1], 1, 0, TImode);
886 [(set (match_operand:TI 0 "nonimmediate_operand" "")
887 (match_operand:TI 1 "general_operand" ""))]
888 "TARGET_64BIT && reload_completed
889 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
890 [(set (match_dup 2) (match_dup 4))
891 (set (match_dup 3) (match_dup 5))]
893 operands[2] = operand_subword (operands[0], 1, 0, TImode);
894 operands[3] = operand_subword (operands[0], 0, 0, TImode);
895 operands[4] = operand_subword (operands[1], 1, 0, TImode);
896 operands[5] = operand_subword (operands[1], 0, 0, TImode);
900 [(set (match_operand:TI 0 "register_operand" "")
901 (match_operand:TI 1 "memory_operand" ""))]
902 "TARGET_64BIT && reload_completed
903 && !s_operand (operands[1], VOIDmode)"
904 [(set (match_dup 0) (match_dup 1))]
906 rtx addr = operand_subword (operands[0], 1, 0, TImode);
907 s390_load_address (addr, XEXP (operands[1], 0));
908 operands[1] = replace_equiv_address (operands[1], addr);
913 ; Patterns used for secondary reloads
916 ; Handles loading a PLUS (load address) expression
918 (define_expand "reload<mode>_plus"
919 [(parallel [(match_operand:P 0 "register_operand" "=a")
920 (match_operand:P 1 "s390_plus_operand" "")
921 (match_operand:P 2 "register_operand" "=&a")])]
924 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
928 ; Handles assessing a non-offsetable memory address
930 (define_expand "reload<mode>_nonoffmem_in"
931 [(parallel [(match_operand 0 "register_operand" "")
932 (match_operand 1 "" "")
933 (match_operand:P 2 "register_operand" "=&a")])]
936 gcc_assert (MEM_P (operands[1]));
937 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0)));
938 operands[1] = replace_equiv_address (operands[1], operands[2]);
939 emit_move_insn (operands[0], operands[1]);
943 (define_expand "reload<mode>_nonoffmem_out"
944 [(parallel [(match_operand 0 "" "")
945 (match_operand 1 "register_operand" "")
946 (match_operand:P 2 "register_operand" "=&a")])]
949 gcc_assert (MEM_P (operands[0]));
950 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
951 operands[0] = replace_equiv_address (operands[0], operands[2]);
952 emit_move_insn (operands[0], operands[1]);
957 ; movdi instruction pattern(s).
960 (define_expand "movdi"
961 [(set (match_operand:DI 0 "general_operand" "")
962 (match_operand:DI 1 "general_operand" ""))]
965 /* Handle symbolic constants. */
967 && (SYMBOLIC_CONST (operands[1])
968 || (GET_CODE (operands[1]) == PLUS
969 && XEXP (operands[1], 0) == pic_offset_table_rtx
970 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
971 emit_symbolic_move (operands);
974 (define_insn "*movdi_larl"
975 [(set (match_operand:DI 0 "register_operand" "=d")
976 (match_operand:DI 1 "larl_operand" "X"))]
978 && !FP_REG_P (operands[0])"
980 [(set_attr "op_type" "RIL")
981 (set_attr "type" "larl")])
983 (define_insn "*movdi_64dfp"
984 [(set (match_operand:DI 0 "nonimmediate_operand"
985 "=d,d,d,d,d,d,d,d,f,d,d,d,d,
986 m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
987 (match_operand:DI 1 "general_operand"
988 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,d,m,
989 d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
990 "TARGET_64BIT && TARGET_DFP"
1016 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RRE,RXY,RXY,
1017 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
1018 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,lr,load,store,
1019 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
1021 (define_insn "*movdi_64extimm"
1022 [(set (match_operand:DI 0 "nonimmediate_operand"
1023 "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1024 (match_operand:DI 1 "general_operand"
1025 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1026 "TARGET_64BIT && TARGET_EXTIMM"
1050 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY,
1051 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
1052 (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store,
1053 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
1055 (define_insn "*movdi_64"
1056 [(set (match_operand:DI 0 "nonimmediate_operand"
1057 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1058 (match_operand:DI 1 "general_operand"
1059 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1060 "TARGET_64BIT && !TARGET_EXTIMM"
1081 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
1082 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
1083 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
1084 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
1087 [(set (match_operand:DI 0 "register_operand" "")
1088 (match_operand:DI 1 "register_operand" ""))]
1089 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
1090 [(set (match_dup 2) (match_dup 3))
1091 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
1092 (set (strict_low_part (match_dup 2)) (match_dup 4))]
1093 "operands[2] = gen_lowpart (SImode, operands[0]);
1094 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
1097 [(set (match_operand:DI 0 "register_operand" "")
1098 (match_operand:DI 1 "register_operand" ""))]
1099 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1100 && dead_or_set_p (insn, operands[1])"
1101 [(set (match_dup 3) (match_dup 2))
1102 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
1103 (set (match_dup 4) (match_dup 2))]
1104 "operands[2] = gen_lowpart (SImode, operands[1]);
1105 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1108 [(set (match_operand:DI 0 "register_operand" "")
1109 (match_operand:DI 1 "register_operand" ""))]
1110 "TARGET_64BIT && ACCESS_REG_P (operands[0])
1111 && !dead_or_set_p (insn, operands[1])"
1112 [(set (match_dup 3) (match_dup 2))
1113 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
1114 (set (match_dup 4) (match_dup 2))
1115 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
1116 "operands[2] = gen_lowpart (SImode, operands[1]);
1117 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
1119 (define_insn "*movdi_31"
1120 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
1121 (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))]
1136 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
1137 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
1140 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1141 (match_operand:DI 1 "general_operand" ""))]
1142 "!TARGET_64BIT && reload_completed
1143 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1144 [(set (match_dup 2) (match_dup 4))
1145 (set (match_dup 3) (match_dup 5))]
1147 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1148 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1149 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1150 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1154 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1155 (match_operand:DI 1 "general_operand" ""))]
1156 "!TARGET_64BIT && reload_completed
1157 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1158 [(set (match_dup 2) (match_dup 4))
1159 (set (match_dup 3) (match_dup 5))]
1161 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1162 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1163 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1164 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1168 [(set (match_operand:DI 0 "register_operand" "")
1169 (match_operand:DI 1 "memory_operand" ""))]
1170 "!TARGET_64BIT && reload_completed
1171 && !FP_REG_P (operands[0])
1172 && !s_operand (operands[1], VOIDmode)"
1173 [(set (match_dup 0) (match_dup 1))]
1175 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1176 s390_load_address (addr, XEXP (operands[1], 0));
1177 operands[1] = replace_equiv_address (operands[1], addr);
1181 [(set (match_operand:DI 0 "register_operand" "")
1182 (mem:DI (match_operand 1 "address_operand" "")))]
1184 && !FP_REG_P (operands[0])
1185 && GET_CODE (operands[1]) == SYMBOL_REF
1186 && CONSTANT_POOL_ADDRESS_P (operands[1])
1187 && get_pool_mode (operands[1]) == DImode
1188 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1189 [(set (match_dup 0) (match_dup 2))]
1190 "operands[2] = get_pool_constant (operands[1]);")
1192 (define_insn "*la_64"
1193 [(set (match_operand:DI 0 "register_operand" "=d,d")
1194 (match_operand:QI 1 "address_operand" "U,W"))]
1199 [(set_attr "op_type" "RX,RXY")
1200 (set_attr "type" "la")])
1204 [(set (match_operand:DI 0 "register_operand" "")
1205 (match_operand:QI 1 "address_operand" ""))
1206 (clobber (reg:CC CC_REGNUM))])]
1208 && preferred_la_operand_p (operands[1], const0_rtx)"
1209 [(set (match_dup 0) (match_dup 1))]
1213 [(set (match_operand:DI 0 "register_operand" "")
1214 (match_operand:DI 1 "register_operand" ""))
1217 (plus:DI (match_dup 0)
1218 (match_operand:DI 2 "nonmemory_operand" "")))
1219 (clobber (reg:CC CC_REGNUM))])]
1221 && !reg_overlap_mentioned_p (operands[0], operands[2])
1222 && preferred_la_operand_p (operands[1], operands[2])"
1223 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1227 ; movsi instruction pattern(s).
1230 (define_expand "movsi"
1231 [(set (match_operand:SI 0 "general_operand" "")
1232 (match_operand:SI 1 "general_operand" ""))]
1235 /* Handle symbolic constants. */
1237 && (SYMBOLIC_CONST (operands[1])
1238 || (GET_CODE (operands[1]) == PLUS
1239 && XEXP (operands[1], 0) == pic_offset_table_rtx
1240 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1241 emit_symbolic_move (operands);
1244 (define_insn "*movsi_larl"
1245 [(set (match_operand:SI 0 "register_operand" "=d")
1246 (match_operand:SI 1 "larl_operand" "X"))]
1247 "!TARGET_64BIT && TARGET_CPU_ZARCH
1248 && !FP_REG_P (operands[0])"
1250 [(set_attr "op_type" "RIL")
1251 (set_attr "type" "larl")])
1253 (define_insn "*movsi_zarch"
1254 [(set (match_operand:SI 0 "nonimmediate_operand"
1255 "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1256 (match_operand:SI 1 "general_operand"
1257 "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1280 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY,
1281 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1282 (set_attr "type" "*,*,*,*,la,lr,load,load,store,store,
1283 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1285 (define_insn "*movsi_esa"
1286 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1287 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1302 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1303 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1306 [(set (match_operand:SI 0 "register_operand" "")
1307 (mem:SI (match_operand 1 "address_operand" "")))]
1308 "!FP_REG_P (operands[0])
1309 && GET_CODE (operands[1]) == SYMBOL_REF
1310 && CONSTANT_POOL_ADDRESS_P (operands[1])
1311 && get_pool_mode (operands[1]) == SImode
1312 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1313 [(set (match_dup 0) (match_dup 2))]
1314 "operands[2] = get_pool_constant (operands[1]);")
1316 (define_insn "*la_31"
1317 [(set (match_operand:SI 0 "register_operand" "=d,d")
1318 (match_operand:QI 1 "address_operand" "U,W"))]
1319 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1323 [(set_attr "op_type" "RX,RXY")
1324 (set_attr "type" "la")])
1328 [(set (match_operand:SI 0 "register_operand" "")
1329 (match_operand:QI 1 "address_operand" ""))
1330 (clobber (reg:CC CC_REGNUM))])]
1332 && preferred_la_operand_p (operands[1], const0_rtx)"
1333 [(set (match_dup 0) (match_dup 1))]
1337 [(set (match_operand:SI 0 "register_operand" "")
1338 (match_operand:SI 1 "register_operand" ""))
1341 (plus:SI (match_dup 0)
1342 (match_operand:SI 2 "nonmemory_operand" "")))
1343 (clobber (reg:CC CC_REGNUM))])]
1345 && !reg_overlap_mentioned_p (operands[0], operands[2])
1346 && preferred_la_operand_p (operands[1], operands[2])"
1347 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1350 (define_insn "*la_31_and"
1351 [(set (match_operand:SI 0 "register_operand" "=d,d")
1352 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1353 (const_int 2147483647)))]
1358 [(set_attr "op_type" "RX,RXY")
1359 (set_attr "type" "la")])
1361 (define_insn_and_split "*la_31_and_cc"
1362 [(set (match_operand:SI 0 "register_operand" "=d")
1363 (and:SI (match_operand:QI 1 "address_operand" "p")
1364 (const_int 2147483647)))
1365 (clobber (reg:CC CC_REGNUM))]
1368 "&& reload_completed"
1370 (and:SI (match_dup 1) (const_int 2147483647)))]
1372 [(set_attr "op_type" "RX")
1373 (set_attr "type" "la")])
1375 (define_insn "force_la_31"
1376 [(set (match_operand:SI 0 "register_operand" "=d,d")
1377 (match_operand:QI 1 "address_operand" "U,W"))
1378 (use (const_int 0))]
1383 [(set_attr "op_type" "RX")
1384 (set_attr "type" "la")])
1387 ; movhi instruction pattern(s).
1390 (define_expand "movhi"
1391 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1392 (match_operand:HI 1 "general_operand" ""))]
1395 /* Make it explicit that loading a register from memory
1396 always sign-extends (at least) to SImode. */
1397 if (optimize && can_create_pseudo_p ()
1398 && register_operand (operands[0], VOIDmode)
1399 && GET_CODE (operands[1]) == MEM)
1401 rtx tmp = gen_reg_rtx (SImode);
1402 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1403 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1404 operands[1] = gen_lowpart (HImode, tmp);
1408 (define_insn "*movhi"
1409 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1410 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1420 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1421 (set_attr "type" "lr,*,*,*,store,store,*")])
1424 [(set (match_operand:HI 0 "register_operand" "")
1425 (mem:HI (match_operand 1 "address_operand" "")))]
1426 "GET_CODE (operands[1]) == SYMBOL_REF
1427 && CONSTANT_POOL_ADDRESS_P (operands[1])
1428 && get_pool_mode (operands[1]) == HImode
1429 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1430 [(set (match_dup 0) (match_dup 2))]
1431 "operands[2] = get_pool_constant (operands[1]);")
1434 ; movqi instruction pattern(s).
1437 (define_expand "movqi"
1438 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1439 (match_operand:QI 1 "general_operand" ""))]
1442 /* On z/Architecture, zero-extending from memory to register
1443 is just as fast as a QImode load. */
1444 if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
1445 && register_operand (operands[0], VOIDmode)
1446 && GET_CODE (operands[1]) == MEM)
1448 rtx tmp = gen_reg_rtx (word_mode);
1449 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1450 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1451 operands[1] = gen_lowpart (QImode, tmp);
1455 (define_insn "*movqi"
1456 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1457 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1469 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1470 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1473 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1474 (mem:QI (match_operand 1 "address_operand" "")))]
1475 "GET_CODE (operands[1]) == SYMBOL_REF
1476 && CONSTANT_POOL_ADDRESS_P (operands[1])
1477 && get_pool_mode (operands[1]) == QImode
1478 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1479 [(set (match_dup 0) (match_dup 2))]
1480 "operands[2] = get_pool_constant (operands[1]);")
1483 ; movstrictqi instruction pattern(s).
1486 (define_insn "*movstrictqi"
1487 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1488 (match_operand:QI 1 "memory_operand" "R,T"))]
1493 [(set_attr "op_type" "RX,RXY")])
1496 ; movstricthi instruction pattern(s).
1499 (define_insn "*movstricthi"
1500 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1501 (match_operand:HI 1 "memory_operand" "Q,S"))
1502 (clobber (reg:CC CC_REGNUM))]
1507 [(set_attr "op_type" "RS,RSY")])
1510 ; movstrictsi instruction pattern(s).
1513 (define_insn "movstrictsi"
1514 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1515 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1522 [(set_attr "op_type" "RR,RX,RXY,RRE")
1523 (set_attr "type" "lr,load,load,*")])
1526 ; mov(tf|td) instruction pattern(s).
1529 (define_expand "mov<mode>"
1530 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1531 (match_operand:TD_TF 1 "general_operand" ""))]
1535 (define_insn "*mov<mode>_64"
1536 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o,Q")
1537 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dm,d,Q"))]
1549 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*,*")
1550 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*,*")])
1552 (define_insn "*mov<mode>_31"
1553 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,Q")
1554 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,Q"))]
1562 [(set_attr "op_type" "RRE,RRE,*,*,*")
1563 (set_attr "type" "fsimptf,fsimptf,*,*,*")])
1565 ; TFmode in GPRs splitters
1568 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1569 (match_operand:TD_TF 1 "general_operand" ""))]
1570 "TARGET_64BIT && reload_completed
1571 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
1572 [(set (match_dup 2) (match_dup 4))
1573 (set (match_dup 3) (match_dup 5))]
1575 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
1576 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
1577 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
1578 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
1582 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
1583 (match_operand:TD_TF 1 "general_operand" ""))]
1584 "TARGET_64BIT && reload_completed
1585 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
1586 [(set (match_dup 2) (match_dup 4))
1587 (set (match_dup 3) (match_dup 5))]
1589 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
1590 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
1591 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
1592 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
1596 [(set (match_operand:TD_TF 0 "register_operand" "")
1597 (match_operand:TD_TF 1 "memory_operand" ""))]
1598 "TARGET_64BIT && reload_completed
1599 && !FP_REG_P (operands[0])
1600 && !s_operand (operands[1], VOIDmode)"
1601 [(set (match_dup 0) (match_dup 1))]
1603 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
1604 s390_load_address (addr, XEXP (operands[1], 0));
1605 operands[1] = replace_equiv_address (operands[1], addr);
1608 ; TFmode in BFPs splitters
1611 [(set (match_operand:TD_TF 0 "register_operand" "")
1612 (match_operand:TD_TF 1 "memory_operand" ""))]
1613 "reload_completed && offsettable_memref_p (operands[1])
1614 && FP_REG_P (operands[0])"
1615 [(set (match_dup 2) (match_dup 4))
1616 (set (match_dup 3) (match_dup 5))]
1618 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
1620 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0],
1622 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0);
1623 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8);
1627 [(set (match_operand:TD_TF 0 "memory_operand" "")
1628 (match_operand:TD_TF 1 "register_operand" ""))]
1629 "reload_completed && offsettable_memref_p (operands[0])
1630 && FP_REG_P (operands[1])"
1631 [(set (match_dup 2) (match_dup 4))
1632 (set (match_dup 3) (match_dup 5))]
1634 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0);
1635 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8);
1636 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
1638 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1],
1643 ; mov(df|dd) instruction pattern(s).
1646 (define_expand "mov<mode>"
1647 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
1648 (match_operand:DD_DF 1 "general_operand" ""))]
1652 (define_insn "*mov<mode>_64dfp"
1653 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
1654 "=f,f,f,d,f,f,R,T,d,d,m,?Q")
1655 (match_operand:DD_DF 1 "general_operand"
1656 "G,f,d,f,R,T,f,f,d,m,d,?Q"))]
1657 "TARGET_64BIT && TARGET_DFP"
1671 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1672 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
1673 fstoredf,fstoredf,lr,load,store,*")])
1675 (define_insn "*mov<mode>_64"
1676 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
1677 (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
1690 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1691 (set_attr "type" "fsimp<bfp>,fload<bfp>,fload<bfp>,fload<bfp>,
1692 fstore<bfp>,fstore<bfp>,lr,load,store,*")])
1694 (define_insn "*mov<mode>_31"
1695 [(set (match_operand:DD_DF 0 "nonimmediate_operand"
1696 "=f,f,f,f,R,T,d,d,Q,S, d,o,Q")
1697 (match_operand:DD_DF 1 "general_operand"
1698 " G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))]
1714 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
1715 (set_attr "type" "fsimp<bfp>,fload<bfp>,fload<bfp>,fload<bfp>,
1716 fstore<bfp>,fstore<bfp>,lm,lm,stm,stm,*,*,*")])
1719 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
1720 (match_operand:DD_DF 1 "general_operand" ""))]
1721 "!TARGET_64BIT && reload_completed
1722 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
1723 [(set (match_dup 2) (match_dup 4))
1724 (set (match_dup 3) (match_dup 5))]
1726 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
1727 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode);
1728 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode);
1729 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode);
1733 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
1734 (match_operand:DD_DF 1 "general_operand" ""))]
1735 "!TARGET_64BIT && reload_completed
1736 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
1737 [(set (match_dup 2) (match_dup 4))
1738 (set (match_dup 3) (match_dup 5))]
1740 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode);
1741 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode);
1742 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode);
1743 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode);
1747 [(set (match_operand:DD_DF 0 "register_operand" "")
1748 (match_operand:DD_DF 1 "memory_operand" ""))]
1749 "!TARGET_64BIT && reload_completed
1750 && !FP_REG_P (operands[0])
1751 && !s_operand (operands[1], VOIDmode)"
1752 [(set (match_dup 0) (match_dup 1))]
1754 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode);
1755 s390_load_address (addr, XEXP (operands[1], 0));
1756 operands[1] = replace_equiv_address (operands[1], addr);
1760 ; mov(sf|sd) instruction pattern(s).
1763 (define_insn "mov<mode>"
1764 [(set (match_operand:SD_SF 0 "nonimmediate_operand"
1765 "=f,f,f,f,R,T,d,d,d,R,T,?Q")
1766 (match_operand:SD_SF 1 "general_operand"
1767 " G,f,R,T,f,f,d,R,T,d,d,?Q"))]
1782 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1783 (set_attr "type" "fsimp<bfp>,fload<bfp>,fload<bfp>,fload<bfp>,
1784 fstore<bfp>,fstore<bfp>,lr,load,load,store,store,*")])
1787 ; movcc instruction pattern
1790 (define_insn "movcc"
1791 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1792 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1802 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1803 (set_attr "type" "lr,*,*,store,store,load,load")])
1806 ; Block move (MVC) patterns.
1810 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1811 (match_operand:BLK 1 "memory_operand" "Q"))
1812 (use (match_operand 2 "const_int_operand" "n"))]
1813 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1814 "mvc\t%O0(%2,%R0),%S1"
1815 [(set_attr "op_type" "SS")])
1818 [(set (match_operand 0 "memory_operand" "")
1819 (match_operand 1 "memory_operand" ""))]
1821 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1822 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1824 [(set (match_dup 0) (match_dup 1))
1825 (use (match_dup 2))])]
1827 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1828 operands[0] = adjust_address (operands[0], BLKmode, 0);
1829 operands[1] = adjust_address (operands[1], BLKmode, 0);
1834 [(set (match_operand:BLK 0 "memory_operand" "")
1835 (match_operand:BLK 1 "memory_operand" ""))
1836 (use (match_operand 2 "const_int_operand" ""))])
1838 [(set (match_operand:BLK 3 "memory_operand" "")
1839 (match_operand:BLK 4 "memory_operand" ""))
1840 (use (match_operand 5 "const_int_operand" ""))])]
1841 "s390_offset_p (operands[0], operands[3], operands[2])
1842 && s390_offset_p (operands[1], operands[4], operands[2])
1843 && !s390_overlap_p (operands[0], operands[1],
1844 INTVAL (operands[2]) + INTVAL (operands[5]))
1845 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1847 [(set (match_dup 6) (match_dup 7))
1848 (use (match_dup 8))])]
1849 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1850 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1851 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1855 ; load_multiple pattern(s).
1857 ; ??? Due to reload problems with replacing registers inside match_parallel
1858 ; we currently support load_multiple/store_multiple only after reload.
1861 (define_expand "load_multiple"
1862 [(match_par_dup 3 [(set (match_operand 0 "" "")
1863 (match_operand 1 "" ""))
1864 (use (match_operand 2 "" ""))])]
1867 enum machine_mode mode;
1873 /* Support only loading a constant number of fixed-point registers from
1874 memory and only bother with this if more than two */
1875 if (GET_CODE (operands[2]) != CONST_INT
1876 || INTVAL (operands[2]) < 2
1877 || INTVAL (operands[2]) > 16
1878 || GET_CODE (operands[1]) != MEM
1879 || GET_CODE (operands[0]) != REG
1880 || REGNO (operands[0]) >= 16)
1883 count = INTVAL (operands[2]);
1884 regno = REGNO (operands[0]);
1885 mode = GET_MODE (operands[0]);
1886 if (mode != SImode && mode != word_mode)
1889 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1890 if (!can_create_pseudo_p ())
1892 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1894 from = XEXP (operands[1], 0);
1897 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1898 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1899 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1901 from = XEXP (XEXP (operands[1], 0), 0);
1902 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1909 from = force_reg (Pmode, XEXP (operands[1], 0));
1913 for (i = 0; i < count; i++)
1914 XVECEXP (operands[3], 0, i)
1915 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1916 change_address (operands[1], mode,
1917 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1920 (define_insn "*load_multiple_di"
1921 [(match_parallel 0 "load_multiple_operation"
1922 [(set (match_operand:DI 1 "register_operand" "=r")
1923 (match_operand:DI 2 "s_operand" "QS"))])]
1924 "reload_completed && word_mode == DImode"
1926 int words = XVECLEN (operands[0], 0);
1927 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1928 return "lmg\t%1,%0,%S2";
1930 [(set_attr "op_type" "RSY")
1931 (set_attr "type" "lm")])
1933 (define_insn "*load_multiple_si"
1934 [(match_parallel 0 "load_multiple_operation"
1935 [(set (match_operand:SI 1 "register_operand" "=r,r")
1936 (match_operand:SI 2 "s_operand" "Q,S"))])]
1939 int words = XVECLEN (operands[0], 0);
1940 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1941 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1943 [(set_attr "op_type" "RS,RSY")
1944 (set_attr "type" "lm")])
1947 ; store multiple pattern(s).
1950 (define_expand "store_multiple"
1951 [(match_par_dup 3 [(set (match_operand 0 "" "")
1952 (match_operand 1 "" ""))
1953 (use (match_operand 2 "" ""))])]
1956 enum machine_mode mode;
1962 /* Support only storing a constant number of fixed-point registers to
1963 memory and only bother with this if more than two. */
1964 if (GET_CODE (operands[2]) != CONST_INT
1965 || INTVAL (operands[2]) < 2
1966 || INTVAL (operands[2]) > 16
1967 || GET_CODE (operands[0]) != MEM
1968 || GET_CODE (operands[1]) != REG
1969 || REGNO (operands[1]) >= 16)
1972 count = INTVAL (operands[2]);
1973 regno = REGNO (operands[1]);
1974 mode = GET_MODE (operands[1]);
1975 if (mode != SImode && mode != word_mode)
1978 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1980 if (!can_create_pseudo_p ())
1982 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1984 to = XEXP (operands[0], 0);
1987 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1988 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1989 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1991 to = XEXP (XEXP (operands[0], 0), 0);
1992 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1999 to = force_reg (Pmode, XEXP (operands[0], 0));
2003 for (i = 0; i < count; i++)
2004 XVECEXP (operands[3], 0, i)
2005 = gen_rtx_SET (VOIDmode,
2006 change_address (operands[0], mode,
2007 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
2008 gen_rtx_REG (mode, regno + i));
2011 (define_insn "*store_multiple_di"
2012 [(match_parallel 0 "store_multiple_operation"
2013 [(set (match_operand:DI 1 "s_operand" "=QS")
2014 (match_operand:DI 2 "register_operand" "r"))])]
2015 "reload_completed && word_mode == DImode"
2017 int words = XVECLEN (operands[0], 0);
2018 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
2019 return "stmg\t%2,%0,%S1";
2021 [(set_attr "op_type" "RSY")
2022 (set_attr "type" "stm")])
2025 (define_insn "*store_multiple_si"
2026 [(match_parallel 0 "store_multiple_operation"
2027 [(set (match_operand:SI 1 "s_operand" "=Q,S")
2028 (match_operand:SI 2 "register_operand" "r,r"))])]
2031 int words = XVECLEN (operands[0], 0);
2032 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
2033 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
2035 [(set_attr "op_type" "RS,RSY")
2036 (set_attr "type" "stm")])
2039 ;; String instructions.
2042 (define_insn "*execute"
2043 [(match_parallel 0 ""
2044 [(unspec [(match_operand 1 "register_operand" "a")
2045 (match_operand:BLK 2 "memory_operand" "R")
2046 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
2047 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
2048 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
2050 [(set_attr "op_type" "RX")
2051 (set_attr "type" "cs")])
2055 ; strlenM instruction pattern(s).
2058 (define_expand "strlen<mode>"
2059 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
2062 (unspec:P [(const_int 0)
2063 (match_operand:BLK 1 "memory_operand" "")
2065 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
2066 (clobber (scratch:P))
2067 (clobber (reg:CC CC_REGNUM))])
2069 [(set (match_operand:P 0 "register_operand" "")
2070 (minus:P (match_dup 4) (match_dup 5)))
2071 (clobber (reg:CC CC_REGNUM))])]
2074 operands[4] = gen_reg_rtx (Pmode);
2075 operands[5] = gen_reg_rtx (Pmode);
2076 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
2077 operands[1] = replace_equiv_address (operands[1], operands[5]);
2080 (define_insn "*strlen<mode>"
2081 [(set (match_operand:P 0 "register_operand" "=a")
2082 (unspec:P [(match_operand:P 2 "general_operand" "0")
2083 (mem:BLK (match_operand:P 3 "register_operand" "1"))
2085 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
2086 (clobber (match_scratch:P 1 "=a"))
2087 (clobber (reg:CC CC_REGNUM))]
2089 "srst\t%0,%1\;jo\t.-4"
2090 [(set_attr "length" "8")
2091 (set_attr "type" "vs")])
2094 ; cmpstrM instruction pattern(s).
2097 (define_expand "cmpstrsi"
2098 [(set (reg:SI 0) (const_int 0))
2100 [(clobber (match_operand 3 "" ""))
2101 (clobber (match_dup 4))
2102 (set (reg:CCU CC_REGNUM)
2103 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2104 (match_operand:BLK 2 "memory_operand" "")))
2107 [(set (match_operand:SI 0 "register_operand" "=d")
2108 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT))
2109 (clobber (reg:CC CC_REGNUM))])]
2112 /* As the result of CMPINT is inverted compared to what we need,
2113 we have to swap the operands. */
2114 rtx op1 = operands[2];
2115 rtx op2 = operands[1];
2116 rtx addr1 = gen_reg_rtx (Pmode);
2117 rtx addr2 = gen_reg_rtx (Pmode);
2119 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2120 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2121 operands[1] = replace_equiv_address_nv (op1, addr1);
2122 operands[2] = replace_equiv_address_nv (op2, addr2);
2123 operands[3] = addr1;
2124 operands[4] = addr2;
2127 (define_insn "*cmpstr<mode>"
2128 [(clobber (match_operand:P 0 "register_operand" "=d"))
2129 (clobber (match_operand:P 1 "register_operand" "=d"))
2130 (set (reg:CCU CC_REGNUM)
2131 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2132 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2135 "clst\t%0,%1\;jo\t.-4"
2136 [(set_attr "length" "8")
2137 (set_attr "type" "vs")])
2140 ; movstr instruction pattern.
2143 (define_expand "movstr"
2144 [(set (reg:SI 0) (const_int 0))
2146 [(clobber (match_dup 3))
2147 (set (match_operand:BLK 1 "memory_operand" "")
2148 (match_operand:BLK 2 "memory_operand" ""))
2149 (set (match_operand 0 "register_operand" "")
2150 (unspec [(match_dup 1)
2152 (reg:SI 0)] UNSPEC_MVST))
2153 (clobber (reg:CC CC_REGNUM))])]
2156 rtx addr1 = gen_reg_rtx (Pmode);
2157 rtx addr2 = gen_reg_rtx (Pmode);
2159 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2160 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2161 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2162 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2163 operands[3] = addr2;
2166 (define_insn "*movstr"
2167 [(clobber (match_operand:P 2 "register_operand" "=d"))
2168 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2169 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2170 (set (match_operand:P 0 "register_operand" "=d")
2171 (unspec [(mem:BLK (match_dup 1))
2172 (mem:BLK (match_dup 3))
2173 (reg:SI 0)] UNSPEC_MVST))
2174 (clobber (reg:CC CC_REGNUM))]
2176 "mvst\t%1,%2\;jo\t.-4"
2177 [(set_attr "length" "8")
2178 (set_attr "type" "vs")])
2182 ; movmemM instruction pattern(s).
2185 (define_expand "movmem<mode>"
2186 [(set (match_operand:BLK 0 "memory_operand" "")
2187 (match_operand:BLK 1 "memory_operand" ""))
2188 (use (match_operand:GPR 2 "general_operand" ""))
2189 (match_operand 3 "" "")]
2191 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2193 ; Move a block that is up to 256 bytes in length.
2194 ; The block length is taken as (operands[2] % 256) + 1.
2196 (define_expand "movmem_short"
2198 [(set (match_operand:BLK 0 "memory_operand" "")
2199 (match_operand:BLK 1 "memory_operand" ""))
2200 (use (match_operand 2 "nonmemory_operand" ""))
2201 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2202 (clobber (match_dup 3))])]
2204 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2206 (define_insn "*movmem_short"
2207 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2208 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
2209 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2210 (use (match_operand 3 "immediate_operand" "X,R,X"))
2211 (clobber (match_scratch 4 "=X,X,&a"))]
2212 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2213 && GET_MODE (operands[4]) == Pmode"
2215 [(set_attr "type" "cs")])
2218 [(set (match_operand:BLK 0 "memory_operand" "")
2219 (match_operand:BLK 1 "memory_operand" ""))
2220 (use (match_operand 2 "const_int_operand" ""))
2221 (use (match_operand 3 "immediate_operand" ""))
2222 (clobber (scratch))]
2225 [(set (match_dup 0) (match_dup 1))
2226 (use (match_dup 2))])]
2227 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2230 [(set (match_operand:BLK 0 "memory_operand" "")
2231 (match_operand:BLK 1 "memory_operand" ""))
2232 (use (match_operand 2 "register_operand" ""))
2233 (use (match_operand 3 "memory_operand" ""))
2234 (clobber (scratch))]
2237 [(unspec [(match_dup 2) (match_dup 3)
2238 (const_int 0)] UNSPEC_EXECUTE)
2239 (set (match_dup 0) (match_dup 1))
2240 (use (const_int 1))])]
2244 [(set (match_operand:BLK 0 "memory_operand" "")
2245 (match_operand:BLK 1 "memory_operand" ""))
2246 (use (match_operand 2 "register_operand" ""))
2247 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2248 (clobber (match_operand 3 "register_operand" ""))]
2249 "reload_completed && TARGET_CPU_ZARCH"
2250 [(set (match_dup 3) (label_ref (match_dup 4)))
2252 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2253 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2254 (set (match_dup 0) (match_dup 1))
2255 (use (const_int 1))])]
2256 "operands[4] = gen_label_rtx ();")
2258 ; Move a block of arbitrary length.
2260 (define_expand "movmem_long"
2262 [(clobber (match_dup 2))
2263 (clobber (match_dup 3))
2264 (set (match_operand:BLK 0 "memory_operand" "")
2265 (match_operand:BLK 1 "memory_operand" ""))
2266 (use (match_operand 2 "general_operand" ""))
2268 (clobber (reg:CC CC_REGNUM))])]
2271 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2272 rtx reg0 = gen_reg_rtx (dword_mode);
2273 rtx reg1 = gen_reg_rtx (dword_mode);
2274 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2275 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2276 rtx len0 = gen_lowpart (Pmode, reg0);
2277 rtx len1 = gen_lowpart (Pmode, reg1);
2279 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2280 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2281 emit_move_insn (len0, operands[2]);
2283 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2284 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2285 emit_move_insn (len1, operands[2]);
2287 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2288 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2293 (define_insn "*movmem_long"
2294 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2295 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2296 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2297 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2300 (clobber (reg:CC CC_REGNUM))]
2302 "mvcle\t%0,%1,0\;jo\t.-4"
2303 [(set_attr "length" "8")
2304 (set_attr "type" "vs")])
2311 (define_expand "signbit<mode>2"
2312 [(set (reg:CCZ CC_REGNUM)
2313 (unspec:CCZ [(match_operand:BFP 1 "register_operand" "f")
2316 (set (match_operand:SI 0 "register_operand" "=d")
2317 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2320 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET);
2323 (define_expand "isinf<mode>2"
2324 [(set (reg:CCZ CC_REGNUM)
2325 (unspec:CCZ [(match_operand:BFP 1 "register_operand" "f")
2328 (set (match_operand:SI 0 "register_operand" "=d")
2329 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
2332 operands[2] = GEN_INT (S390_TDC_INFINITY);
2335 ; This insn is used to generate all variants of the Test Data Class
2336 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand
2337 ; is the register to be tested and the second one is the bit mask
2338 ; specifying the required test(s).
2340 (define_insn "*TDC_insn_<mode>"
2341 [(set (reg:CCZ CC_REGNUM)
2342 (unspec:CCZ [(match_operand:BFP 0 "register_operand" "f")
2343 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
2346 [(set_attr "op_type" "RXE")
2347 (set_attr "type" "fsimp<mode>")])
2349 (define_insn_and_split "*ccz_to_int"
2350 [(set (match_operand:SI 0 "register_operand" "=d")
2351 (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")]
2352 UNSPEC_CCZ_TO_INT))]
2356 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))])
2360 ; setmemM instruction pattern(s).
2363 (define_expand "setmem<mode>"
2364 [(set (match_operand:BLK 0 "memory_operand" "")
2365 (match_operand:QI 2 "general_operand" ""))
2366 (use (match_operand:GPR 1 "general_operand" ""))
2367 (match_operand 3 "" "")]
2369 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2371 ; Clear a block that is up to 256 bytes in length.
2372 ; The block length is taken as (operands[1] % 256) + 1.
2374 (define_expand "clrmem_short"
2376 [(set (match_operand:BLK 0 "memory_operand" "")
2378 (use (match_operand 1 "nonmemory_operand" ""))
2379 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2380 (clobber (match_dup 2))
2381 (clobber (reg:CC CC_REGNUM))])]
2383 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2385 (define_insn "*clrmem_short"
2386 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2388 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
2389 (use (match_operand 2 "immediate_operand" "X,R,X"))
2390 (clobber (match_scratch 3 "=X,X,&a"))
2391 (clobber (reg:CC CC_REGNUM))]
2392 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2393 && GET_MODE (operands[3]) == Pmode"
2395 [(set_attr "type" "cs")])
2398 [(set (match_operand:BLK 0 "memory_operand" "")
2400 (use (match_operand 1 "const_int_operand" ""))
2401 (use (match_operand 2 "immediate_operand" ""))
2403 (clobber (reg:CC CC_REGNUM))]
2406 [(set (match_dup 0) (const_int 0))
2408 (clobber (reg:CC CC_REGNUM))])]
2409 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2412 [(set (match_operand:BLK 0 "memory_operand" "")
2414 (use (match_operand 1 "register_operand" ""))
2415 (use (match_operand 2 "memory_operand" ""))
2417 (clobber (reg:CC CC_REGNUM))]
2420 [(unspec [(match_dup 1) (match_dup 2)
2421 (const_int 0)] UNSPEC_EXECUTE)
2422 (set (match_dup 0) (const_int 0))
2424 (clobber (reg:CC CC_REGNUM))])]
2428 [(set (match_operand:BLK 0 "memory_operand" "")
2430 (use (match_operand 1 "register_operand" ""))
2431 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2432 (clobber (match_operand 2 "register_operand" ""))
2433 (clobber (reg:CC CC_REGNUM))]
2434 "reload_completed && TARGET_CPU_ZARCH"
2435 [(set (match_dup 2) (label_ref (match_dup 3)))
2437 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2438 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2439 (set (match_dup 0) (const_int 0))
2441 (clobber (reg:CC CC_REGNUM))])]
2442 "operands[3] = gen_label_rtx ();")
2444 ; Initialize a block of arbitrary length with (operands[2] % 256).
2446 (define_expand "setmem_long"
2448 [(clobber (match_dup 1))
2449 (set (match_operand:BLK 0 "memory_operand" "")
2450 (match_operand 2 "shift_count_or_setmem_operand" ""))
2451 (use (match_operand 1 "general_operand" ""))
2453 (clobber (reg:CC CC_REGNUM))])]
2456 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2457 rtx reg0 = gen_reg_rtx (dword_mode);
2458 rtx reg1 = gen_reg_rtx (dword_mode);
2459 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2460 rtx len0 = gen_lowpart (Pmode, reg0);
2462 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2463 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2464 emit_move_insn (len0, operands[1]);
2466 emit_move_insn (reg1, const0_rtx);
2468 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2473 (define_insn "*setmem_long"
2474 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2475 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2476 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2478 (use (match_operand:<DBL> 1 "register_operand" "d"))
2479 (clobber (reg:CC CC_REGNUM))]
2481 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2482 [(set_attr "length" "8")
2483 (set_attr "type" "vs")])
2485 (define_insn "*setmem_long_and"
2486 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2487 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2488 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2489 (match_operand 4 "const_int_operand" "n")))
2491 (use (match_operand:<DBL> 1 "register_operand" "d"))
2492 (clobber (reg:CC CC_REGNUM))]
2493 "(INTVAL (operands[4]) & 255) == 255"
2494 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2495 [(set_attr "length" "8")
2496 (set_attr "type" "vs")])
2498 ; cmpmemM instruction pattern(s).
2501 (define_expand "cmpmemsi"
2502 [(set (match_operand:SI 0 "register_operand" "")
2503 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2504 (match_operand:BLK 2 "memory_operand" "") ) )
2505 (use (match_operand:SI 3 "general_operand" ""))
2506 (use (match_operand:SI 4 "" ""))]
2508 "s390_expand_cmpmem (operands[0], operands[1],
2509 operands[2], operands[3]); DONE;")
2511 ; Compare a block that is up to 256 bytes in length.
2512 ; The block length is taken as (operands[2] % 256) + 1.
2514 (define_expand "cmpmem_short"
2516 [(set (reg:CCU CC_REGNUM)
2517 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2518 (match_operand:BLK 1 "memory_operand" "")))
2519 (use (match_operand 2 "nonmemory_operand" ""))
2520 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2521 (clobber (match_dup 3))])]
2523 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2525 (define_insn "*cmpmem_short"
2526 [(set (reg:CCU CC_REGNUM)
2527 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2528 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2529 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2530 (use (match_operand 3 "immediate_operand" "X,R,X"))
2531 (clobber (match_scratch 4 "=X,X,&a"))]
2532 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2533 && GET_MODE (operands[4]) == Pmode"
2535 [(set_attr "type" "cs")])
2538 [(set (reg:CCU CC_REGNUM)
2539 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2540 (match_operand:BLK 1 "memory_operand" "")))
2541 (use (match_operand 2 "const_int_operand" ""))
2542 (use (match_operand 3 "immediate_operand" ""))
2543 (clobber (scratch))]
2546 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2547 (use (match_dup 2))])]
2548 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2551 [(set (reg:CCU CC_REGNUM)
2552 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2553 (match_operand:BLK 1 "memory_operand" "")))
2554 (use (match_operand 2 "register_operand" ""))
2555 (use (match_operand 3 "memory_operand" ""))
2556 (clobber (scratch))]
2559 [(unspec [(match_dup 2) (match_dup 3)
2560 (const_int 0)] UNSPEC_EXECUTE)
2561 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2562 (use (const_int 1))])]
2566 [(set (reg:CCU CC_REGNUM)
2567 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2568 (match_operand:BLK 1 "memory_operand" "")))
2569 (use (match_operand 2 "register_operand" ""))
2570 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2571 (clobber (match_operand 3 "register_operand" ""))]
2572 "reload_completed && TARGET_CPU_ZARCH"
2573 [(set (match_dup 3) (label_ref (match_dup 4)))
2575 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2576 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2577 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2578 (use (const_int 1))])]
2579 "operands[4] = gen_label_rtx ();")
2581 ; Compare a block of arbitrary length.
2583 (define_expand "cmpmem_long"
2585 [(clobber (match_dup 2))
2586 (clobber (match_dup 3))
2587 (set (reg:CCU CC_REGNUM)
2588 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2589 (match_operand:BLK 1 "memory_operand" "")))
2590 (use (match_operand 2 "general_operand" ""))
2591 (use (match_dup 3))])]
2594 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2595 rtx reg0 = gen_reg_rtx (dword_mode);
2596 rtx reg1 = gen_reg_rtx (dword_mode);
2597 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2598 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2599 rtx len0 = gen_lowpart (Pmode, reg0);
2600 rtx len1 = gen_lowpart (Pmode, reg1);
2602 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2603 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2604 emit_move_insn (len0, operands[2]);
2606 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2607 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2608 emit_move_insn (len1, operands[2]);
2610 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2611 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2616 (define_insn "*cmpmem_long"
2617 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2618 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2619 (set (reg:CCU CC_REGNUM)
2620 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2621 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
2623 (use (match_dup 3))]
2625 "clcle\t%0,%1,0\;jo\t.-4"
2626 [(set_attr "length" "8")
2627 (set_attr "type" "vs")])
2629 ; Convert CCUmode condition code to integer.
2630 ; Result is zero if EQ, positive if LTU, negative if GTU.
2632 (define_insn_and_split "cmpint"
2633 [(set (match_operand:SI 0 "register_operand" "=d")
2634 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2636 (clobber (reg:CC CC_REGNUM))]
2640 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2642 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2643 (clobber (reg:CC CC_REGNUM))])])
2645 (define_insn_and_split "*cmpint_cc"
2646 [(set (reg CC_REGNUM)
2647 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2650 (set (match_operand:SI 0 "register_operand" "=d")
2651 (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))]
2652 "s390_match_ccmode (insn, CCSmode)"
2654 "&& reload_completed"
2655 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2657 [(set (match_dup 2) (match_dup 3))
2658 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2660 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2661 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2662 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2665 (define_insn_and_split "*cmpint_sign"
2666 [(set (match_operand:DI 0 "register_operand" "=d")
2667 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2668 UNSPEC_CCU_TO_INT)))
2669 (clobber (reg:CC CC_REGNUM))]
2672 "&& reload_completed"
2673 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2675 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2676 (clobber (reg:CC CC_REGNUM))])])
2678 (define_insn_and_split "*cmpint_sign_cc"
2679 [(set (reg CC_REGNUM)
2680 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2681 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2682 UNSPEC_CCU_TO_INT) 0)
2683 (const_int 32)) (const_int 32))
2685 (set (match_operand:DI 0 "register_operand" "=d")
2686 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
2687 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2689 "&& reload_completed"
2690 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2692 [(set (match_dup 2) (match_dup 3))
2693 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2695 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2696 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2697 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2702 ;;- Conversion instructions.
2705 (define_insn "*sethighpartsi"
2706 [(set (match_operand:SI 0 "register_operand" "=d,d")
2707 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
2708 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2709 (clobber (reg:CC CC_REGNUM))]
2714 [(set_attr "op_type" "RS,RSY")])
2716 (define_insn "*sethighpartdi_64"
2717 [(set (match_operand:DI 0 "register_operand" "=d")
2718 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
2719 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
2720 (clobber (reg:CC CC_REGNUM))]
2723 [(set_attr "op_type" "RSY")])
2725 (define_insn "*sethighpartdi_31"
2726 [(set (match_operand:DI 0 "register_operand" "=d,d")
2727 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
2728 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2729 (clobber (reg:CC CC_REGNUM))]
2734 [(set_attr "op_type" "RS,RSY")])
2736 (define_insn_and_split "*extzv<mode>"
2737 [(set (match_operand:GPR 0 "register_operand" "=d")
2738 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2739 (match_operand 2 "const_int_operand" "n")
2741 (clobber (reg:CC CC_REGNUM))]
2742 "INTVAL (operands[2]) > 0
2743 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2745 "&& reload_completed"
2747 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2748 (clobber (reg:CC CC_REGNUM))])
2749 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
2751 int bitsize = INTVAL (operands[2]);
2752 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2753 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2755 operands[1] = adjust_address (operands[1], BLKmode, 0);
2756 set_mem_size (operands[1], GEN_INT (size));
2757 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
2758 operands[3] = GEN_INT (mask);
2761 (define_insn_and_split "*extv<mode>"
2762 [(set (match_operand:GPR 0 "register_operand" "=d")
2763 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2764 (match_operand 2 "const_int_operand" "n")
2766 (clobber (reg:CC CC_REGNUM))]
2767 "INTVAL (operands[2]) > 0
2768 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2770 "&& reload_completed"
2772 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2773 (clobber (reg:CC CC_REGNUM))])
2775 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
2776 (clobber (reg:CC CC_REGNUM))])]
2778 int bitsize = INTVAL (operands[2]);
2779 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2780 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2782 operands[1] = adjust_address (operands[1], BLKmode, 0);
2783 set_mem_size (operands[1], GEN_INT (size));
2784 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
2785 operands[3] = GEN_INT (mask);
2789 ; insv instruction patterns
2792 (define_expand "insv"
2793 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
2794 (match_operand 1 "const_int_operand" "")
2795 (match_operand 2 "const_int_operand" ""))
2796 (match_operand 3 "general_operand" ""))]
2799 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
2804 (define_insn "*insv<mode>_mem_reg"
2805 [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
2806 (match_operand 1 "const_int_operand" "n,n")
2808 (match_operand:P 2 "register_operand" "d,d"))]
2809 "INTVAL (operands[1]) > 0
2810 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2811 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2813 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2815 operands[1] = GEN_INT ((1ul << size) - 1);
2816 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
2817 : "stcmy\t%2,%1,%S0";
2819 [(set_attr "op_type" "RS,RSY")])
2821 (define_insn "*insvdi_mem_reghigh"
2822 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
2823 (match_operand 1 "const_int_operand" "n")
2825 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
2828 && INTVAL (operands[1]) > 0
2829 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2830 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2832 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2834 operands[1] = GEN_INT ((1ul << size) - 1);
2835 return "stcmh\t%2,%1,%S0";
2837 [(set_attr "op_type" "RSY")])
2839 (define_insn "*insv<mode>_reg_imm"
2840 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2842 (match_operand 1 "const_int_operand" "n"))
2843 (match_operand:P 2 "const_int_operand" "n"))]
2845 && INTVAL (operands[1]) >= 0
2846 && INTVAL (operands[1]) < BITS_PER_WORD
2847 && INTVAL (operands[1]) % 16 == 0"
2849 switch (BITS_PER_WORD - INTVAL (operands[1]))
2851 case 64: return "iihh\t%0,%x2"; break;
2852 case 48: return "iihl\t%0,%x2"; break;
2853 case 32: return "iilh\t%0,%x2"; break;
2854 case 16: return "iill\t%0,%x2"; break;
2855 default: gcc_unreachable();
2858 [(set_attr "op_type" "RI")])
2860 (define_insn "*insv<mode>_reg_extimm"
2861 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2863 (match_operand 1 "const_int_operand" "n"))
2864 (match_operand:P 2 "const_int_operand" "n"))]
2866 && INTVAL (operands[1]) >= 0
2867 && INTVAL (operands[1]) < BITS_PER_WORD
2868 && INTVAL (operands[1]) % 32 == 0"
2870 switch (BITS_PER_WORD - INTVAL (operands[1]))
2872 case 64: return "iihf\t%0,%o2"; break;
2873 case 32: return "iilf\t%0,%o2"; break;
2874 default: gcc_unreachable();
2877 [(set_attr "op_type" "RIL")])
2880 ; extendsidi2 instruction pattern(s).
2883 (define_expand "extendsidi2"
2884 [(set (match_operand:DI 0 "register_operand" "")
2885 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2890 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2891 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2892 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2893 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2898 (define_insn "*extendsidi2"
2899 [(set (match_operand:DI 0 "register_operand" "=d,d")
2900 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2905 [(set_attr "op_type" "RRE,RXY")])
2908 ; extend(hi|qi)(si|di)2 instruction pattern(s).
2911 (define_expand "extend<HQI:mode><DSI:mode>2"
2912 [(set (match_operand:DSI 0 "register_operand" "")
2913 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2916 if (<DSI:MODE>mode == DImode && !TARGET_64BIT)
2918 rtx tmp = gen_reg_rtx (SImode);
2919 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
2920 emit_insn (gen_extendsidi2 (operands[0], tmp));
2923 else if (!TARGET_EXTIMM)
2925 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
2926 GET_MODE_BITSIZE (<HQI:MODE>mode));
2928 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
2929 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
2930 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
2936 ; extendhidi2 instruction pattern(s).
2939 (define_insn "*extendhidi2_extimm"
2940 [(set (match_operand:DI 0 "register_operand" "=d,d")
2941 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
2942 "TARGET_64BIT && TARGET_EXTIMM"
2946 [(set_attr "op_type" "RRE,RXY")])
2948 (define_insn "*extendhidi2"
2949 [(set (match_operand:DI 0 "register_operand" "=d")
2950 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2953 [(set_attr "op_type" "RXY")])
2956 ; extendhisi2 instruction pattern(s).
2959 (define_insn "*extendhisi2_extimm"
2960 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2961 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
2967 [(set_attr "op_type" "RRE,RX,RXY")])
2969 (define_insn "*extendhisi2"
2970 [(set (match_operand:SI 0 "register_operand" "=d,d")
2971 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2976 [(set_attr "op_type" "RX,RXY")])
2979 ; extendqi(si|di)2 instruction pattern(s).
2982 ; lbr, lgbr, lb, lgb
2983 (define_insn "*extendqi<mode>2_extimm"
2984 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2985 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2990 [(set_attr "op_type" "RRE,RXY")])
2993 (define_insn "*extendqi<mode>2"
2994 [(set (match_operand:GPR 0 "register_operand" "=d")
2995 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "m")))]
2996 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
2998 [(set_attr "op_type" "RXY")])
3000 (define_insn_and_split "*extendqi<mode>2_short_displ"
3001 [(set (match_operand:GPR 0 "register_operand" "=d")
3002 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
3003 (clobber (reg:CC CC_REGNUM))]
3004 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
3006 "&& reload_completed"
3008 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
3009 (clobber (reg:CC CC_REGNUM))])
3011 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
3012 (clobber (reg:CC CC_REGNUM))])]
3014 operands[1] = adjust_address (operands[1], BLKmode, 0);
3015 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
3016 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
3017 - GET_MODE_BITSIZE (QImode));
3021 ; zero_extendsidi2 instruction pattern(s).
3024 (define_expand "zero_extendsidi2"
3025 [(set (match_operand:DI 0 "register_operand" "")
3026 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3031 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
3032 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
3033 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
3038 (define_insn "*zero_extendsidi2"
3039 [(set (match_operand:DI 0 "register_operand" "=d,d")
3040 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
3045 [(set_attr "op_type" "RRE,RXY")])
3048 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
3051 (define_insn "*llgt_sidi"
3052 [(set (match_operand:DI 0 "register_operand" "=d")
3053 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
3054 (const_int 2147483647)))]
3057 [(set_attr "op_type" "RXE")])
3059 (define_insn_and_split "*llgt_sidi_split"
3060 [(set (match_operand:DI 0 "register_operand" "=d")
3061 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
3062 (const_int 2147483647)))
3063 (clobber (reg:CC CC_REGNUM))]
3066 "&& reload_completed"
3068 (and:DI (subreg:DI (match_dup 1) 0)
3069 (const_int 2147483647)))]
3072 (define_insn "*llgt_sisi"
3073 [(set (match_operand:SI 0 "register_operand" "=d,d")
3074 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
3075 (const_int 2147483647)))]
3080 [(set_attr "op_type" "RRE,RXE")])
3082 (define_insn "*llgt_didi"
3083 [(set (match_operand:DI 0 "register_operand" "=d,d")
3084 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
3085 (const_int 2147483647)))]
3090 [(set_attr "op_type" "RRE,RXE")])
3093 [(set (match_operand:GPR 0 "register_operand" "")
3094 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
3095 (const_int 2147483647)))
3096 (clobber (reg:CC CC_REGNUM))]
3097 "TARGET_ZARCH && reload_completed"
3099 (and:GPR (match_dup 1)
3100 (const_int 2147483647)))]
3104 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
3107 (define_expand "zero_extend<mode>di2"
3108 [(set (match_operand:DI 0 "register_operand" "")
3109 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3114 rtx tmp = gen_reg_rtx (SImode);
3115 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
3116 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
3119 else if (!TARGET_EXTIMM)
3121 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
3122 GET_MODE_BITSIZE(<MODE>mode));
3123 operands[1] = gen_lowpart (DImode, operands[1]);
3124 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
3125 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
3130 (define_expand "zero_extend<mode>si2"
3131 [(set (match_operand:SI 0 "register_operand" "")
3132 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
3137 operands[1] = gen_lowpart (SImode, operands[1]);
3138 emit_insn (gen_andsi3 (operands[0], operands[1],
3139 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
3144 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3145 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3146 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3147 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
3152 [(set_attr "op_type" "RRE,RXY")])
3155 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3156 [(set (match_operand:GPR 0 "register_operand" "=d")
3157 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "m")))]
3158 "TARGET_ZARCH && !TARGET_EXTIMM"
3160 [(set_attr "op_type" "RXY")])
3162 (define_insn_and_split "*zero_extendhisi2_31"
3163 [(set (match_operand:SI 0 "register_operand" "=&d")
3164 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3165 (clobber (reg:CC CC_REGNUM))]
3168 "&& reload_completed"
3169 [(set (match_dup 0) (const_int 0))
3171 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3172 (clobber (reg:CC CC_REGNUM))])]
3173 "operands[2] = gen_lowpart (HImode, operands[0]);")
3175 (define_insn_and_split "*zero_extendqisi2_31"
3176 [(set (match_operand:SI 0 "register_operand" "=&d")
3177 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
3180 "&& reload_completed"
3181 [(set (match_dup 0) (const_int 0))
3182 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3183 "operands[2] = gen_lowpart (QImode, operands[0]);")
3186 ; zero_extendqihi2 instruction pattern(s).
3189 (define_expand "zero_extendqihi2"
3190 [(set (match_operand:HI 0 "register_operand" "")
3191 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3192 "TARGET_ZARCH && !TARGET_EXTIMM"
3194 operands[1] = gen_lowpart (HImode, operands[1]);
3195 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3199 (define_insn "*zero_extendqihi2_64"
3200 [(set (match_operand:HI 0 "register_operand" "=d")
3201 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3202 "TARGET_ZARCH && !TARGET_EXTIMM"
3204 [(set_attr "op_type" "RXY")])
3206 (define_insn_and_split "*zero_extendqihi2_31"
3207 [(set (match_operand:HI 0 "register_operand" "=&d")
3208 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3211 "&& reload_completed"
3212 [(set (match_dup 0) (const_int 0))
3213 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3214 "operands[2] = gen_lowpart (QImode, operands[0]);")
3217 ; fixuns_trunc(dd|td)di2 instruction pattern(s).
3220 (define_expand "fixuns_truncdddi2"
3222 [(set (match_operand:DI 0 "register_operand" "")
3223 (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
3224 (clobber (match_scratch:TD 2 "=f"))])]
3226 "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
3228 rtx label1 = gen_label_rtx ();
3229 rtx label2 = gen_label_rtx ();
3230 rtx temp = gen_reg_rtx (TDmode);
3231 REAL_VALUE_TYPE cmp, sub;
3233 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3234 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3236 /* 2^63 can't be represented as 64bit DFP number with full precision. The
3237 solution is doing the check and the subtraction in TD mode and using a
3238 TD -> DI convert afterwards. */
3239 emit_insn (gen_extendddtd2 (temp, operands[1]));
3240 temp = force_reg (TDmode, temp);
3241 emit_insn (gen_cmptd (temp,
3242 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode)));
3243 emit_jump_insn (gen_blt (label1));
3244 emit_insn (gen_subtd3 (temp, temp,
3245 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3246 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3249 emit_label (label1);
3250 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3251 emit_label (label2);
3255 (define_expand "fixuns_trunctddi2"
3256 [(set (match_operand:DI 0 "register_operand" "")
3257 (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))]
3258 "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
3260 rtx label1 = gen_label_rtx ();
3261 rtx label2 = gen_label_rtx ();
3262 rtx temp = gen_reg_rtx (TDmode);
3263 REAL_VALUE_TYPE cmp, sub;
3265 operands[1] = force_reg (TDmode, operands[1]);
3266 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
3267 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
3269 emit_insn (gen_cmptd (operands[1],
3270 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode)));
3271 emit_jump_insn (gen_blt (label1));
3272 emit_insn (gen_subtd3 (temp, operands[1],
3273 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
3274 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
3277 emit_label (label1);
3278 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
3279 emit_label (label2);
3284 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2
3285 ; instruction pattern(s).
3288 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
3289 [(set (match_operand:GPR 0 "register_operand" "")
3290 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))]
3293 rtx label1 = gen_label_rtx ();
3294 rtx label2 = gen_label_rtx ();
3295 rtx temp = gen_reg_rtx (<BFP:MODE>mode);
3296 REAL_VALUE_TYPE cmp, sub;
3298 operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
3299 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
3300 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
3302 emit_insn (gen_cmp<BFP:mode> (operands[1],
3303 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode)));
3304 emit_jump_insn (gen_blt (label1));
3305 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
3306 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
3307 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
3311 emit_label (label1);
3312 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
3313 operands[1], GEN_INT (5)));
3314 emit_label (label2);
3318 (define_expand "fix_trunc<DSF:mode><GPR:mode>2"
3319 [(set (match_operand:GPR 0 "register_operand" "")
3320 (fix:GPR (match_operand:DSF 1 "register_operand" "")))]
3323 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
3328 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
3329 (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
3330 [(set (match_operand:GPR 0 "register_operand" "=d")
3331 (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
3332 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
3333 (clobber (reg:CC CC_REGNUM))]
3335 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
3336 [(set_attr "op_type" "RRE")
3337 (set_attr "type" "ftoi")])
3341 ; fix_trunc(td|dd)di2 instruction pattern(s).
3344 (define_expand "fix_trunc<mode>di2"
3345 [(set (match_operand:DI 0 "register_operand" "")
3346 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
3347 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_HARD_DFP"
3349 operands[1] = force_reg (<MODE>mode, operands[1]);
3350 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
3356 (define_insn "fix_trunc<DFP:mode>di2_dfp"
3357 [(set (match_operand:DI 0 "register_operand" "=d")
3358 (fix:DI (match_operand:DFP 1 "register_operand" "f")))
3359 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3360 (clobber (reg:CC CC_REGNUM))]
3361 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_HARD_DFP"
3362 "cg<DFP:xde>tr\t%0,%h2,%1"
3363 [(set_attr "op_type" "RRF")
3364 (set_attr "type" "ftoi")])
3368 ; fix_trunctf(si|di)2 instruction pattern(s).
3371 (define_expand "fix_trunctf<mode>2"
3372 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
3373 (fix:GPR (match_operand:TF 1 "register_operand" "")))
3374 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
3375 (clobber (reg:CC CC_REGNUM))])]
3381 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
3384 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
3385 (define_insn "floatdi<mode>2"
3386 [(set (match_operand:FP 0 "register_operand" "=f")
3387 (float:FP (match_operand:DI 1 "register_operand" "d")))]
3388 "TARGET_64BIT && TARGET_HARD_FLOAT"
3389 "c<xde>g<bt>r\t%0,%1"
3390 [(set_attr "op_type" "RRE")
3391 (set_attr "type" "itof" )])
3393 ; cxfbr, cdfbr, cefbr
3394 (define_insn "floatsi<mode>2"
3395 [(set (match_operand:BFP 0 "register_operand" "=f")
3396 (float:BFP (match_operand:SI 1 "register_operand" "d")))]
3399 [(set_attr "op_type" "RRE")
3400 (set_attr "type" "itof" )])
3404 ; truncdfsf2 instruction pattern(s).
3407 (define_insn "truncdfsf2"
3408 [(set (match_operand:SF 0 "register_operand" "=f")
3409 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3412 [(set_attr "op_type" "RRE")
3413 (set_attr "type" "ftruncdf")])
3416 ; trunctf(df|sf)2 instruction pattern(s).
3420 (define_insn "trunctf<mode>2"
3421 [(set (match_operand:DSF 0 "register_operand" "=f")
3422 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
3423 (clobber (match_scratch:TF 2 "=f"))]
3425 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
3426 [(set_attr "length" "6")
3427 (set_attr "type" "ftrunctf")])
3430 ; trunctddd2 and truncddsd2 instruction pattern(s).
3433 (define_insn "trunctddd2"
3434 [(set (match_operand:DD 0 "register_operand" "=f")
3435 (float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
3436 (clobber (match_scratch:TD 2 "=f"))]
3437 "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
3438 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
3439 [(set_attr "length" "6")
3440 (set_attr "type" "ftrunctf")])
3442 (define_insn "truncddsd2"
3443 [(set (match_operand:SD 0 "register_operand" "=f")
3444 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))]
3445 "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
3447 [(set_attr "op_type" "RRF")
3448 (set_attr "type" "fsimptf")])
3451 ; extend(sf|df)(df|tf)2 instruction pattern(s).
3454 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
3455 (define_insn "extend<DSF:mode><BFP:mode>2"
3456 [(set (match_operand:BFP 0 "register_operand" "=f,f")
3457 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
3459 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
3461 l<BFP:xde><DSF:xde>br\t%0,%1
3462 l<BFP:xde><DSF:xde>b\t%0,%1"
3463 [(set_attr "op_type" "RRE,RXE")
3464 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
3467 ; extendddtd2 and extendsddd2 instruction pattern(s).
3470 (define_insn "extendddtd2"
3471 [(set (match_operand:TD 0 "register_operand" "=f")
3472 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))]
3473 "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
3475 [(set_attr "op_type" "RRF")
3476 (set_attr "type" "fsimptf")])
3478 (define_insn "extendsddd2"
3479 [(set (match_operand:DD 0 "register_operand" "=f")
3480 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))]
3481 "TARGET_HARD_FLOAT && TARGET_HARD_DFP"
3483 [(set_attr "op_type" "RRF")
3484 (set_attr "type" "fsimptf")])
3486 ; Binary <-> Decimal floating point trunc patterns
3489 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2"
3490 [(set (reg:DFP_ALL FPR0_REGNUM)
3491 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
3492 (use (reg:SI GPR0_REGNUM))
3493 (clobber (reg:CC CC_REGNUM))]
3494 "TARGET_HARD_FLOAT && TARGET_DFP"
3497 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2"
3498 [(set (reg:BFP FPR0_REGNUM)
3499 (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
3500 (use (reg:SI GPR0_REGNUM))
3501 (clobber (reg:CC CC_REGNUM))]
3502 "TARGET_HARD_FLOAT && TARGET_DFP"
3505 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2"
3506 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
3507 (set (reg:SI GPR0_REGNUM) (match_dup 2))
3509 [(set (reg:DFP_ALL FPR0_REGNUM)
3510 (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM)))
3511 (use (reg:SI GPR0_REGNUM))
3512 (clobber (reg:CC CC_REGNUM))])
3513 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
3514 (reg:DFP_ALL FPR0_REGNUM))]
3515 "TARGET_HARD_FLOAT && TARGET_DFP
3516 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
3518 HOST_WIDE_INT flags;
3520 flags = (PFPO_CONVERT |
3521 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
3522 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
3524 operands[2] = GEN_INT (flags);
3527 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2"
3528 [(set (reg:DFP_ALL FPR2_REGNUM)
3529 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
3530 (set (reg:SI GPR0_REGNUM) (match_dup 2))
3532 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM)))
3533 (use (reg:SI GPR0_REGNUM))
3534 (clobber (reg:CC CC_REGNUM))])
3535 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
3536 "TARGET_HARD_FLOAT && TARGET_DFP
3537 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
3539 HOST_WIDE_INT flags;
3541 flags = (PFPO_CONVERT |
3542 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
3543 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
3545 operands[2] = GEN_INT (flags);
3549 ; Binary <-> Decimal floating point extend patterns
3552 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
3553 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
3554 (use (reg:SI GPR0_REGNUM))
3555 (clobber (reg:CC CC_REGNUM))]
3556 "TARGET_HARD_FLOAT && TARGET_DFP"
3559 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
3560 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
3561 (use (reg:SI GPR0_REGNUM))
3562 (clobber (reg:CC CC_REGNUM))]
3563 "TARGET_HARD_FLOAT && TARGET_DFP"
3566 (define_expand "extend<BFP:mode><DFP_ALL:mode>2"
3567 [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" ""))
3568 (set (reg:SI GPR0_REGNUM) (match_dup 2))
3570 [(set (reg:DFP_ALL FPR0_REGNUM)
3571 (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM)))
3572 (use (reg:SI GPR0_REGNUM))
3573 (clobber (reg:CC CC_REGNUM))])
3574 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
3575 (reg:DFP_ALL FPR0_REGNUM))]
3576 "TARGET_HARD_FLOAT && TARGET_DFP
3577 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)"
3579 HOST_WIDE_INT flags;
3581 flags = (PFPO_CONVERT |
3582 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
3583 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
3585 operands[2] = GEN_INT (flags);
3588 (define_expand "extend<DFP_ALL:mode><BFP:mode>2"
3589 [(set (reg:DFP_ALL FPR2_REGNUM)
3590 (match_operand:DFP_ALL 1 "nonimmediate_operand" ""))
3591 (set (reg:SI GPR0_REGNUM) (match_dup 2))
3593 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM)))
3594 (use (reg:SI GPR0_REGNUM))
3595 (clobber (reg:CC CC_REGNUM))])
3596 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
3597 "TARGET_HARD_FLOAT && TARGET_DFP
3598 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
3600 HOST_WIDE_INT flags;
3602 flags = (PFPO_CONVERT |
3603 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
3604 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
3606 operands[2] = GEN_INT (flags);
3611 ;; ARITHMETIC OPERATIONS
3613 ; arithmetic operations set the ConditionCode,
3614 ; because of unpredictable Bits in Register for Halfword and Byte
3615 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3618 ;;- Add instructions.
3622 ; addti3 instruction pattern(s).
3625 (define_insn_and_split "addti3"
3626 [(set (match_operand:TI 0 "register_operand" "=&d")
3627 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3628 (match_operand:TI 2 "general_operand" "do") ) )
3629 (clobber (reg:CC CC_REGNUM))]
3632 "&& reload_completed"
3634 [(set (reg:CCL1 CC_REGNUM)
3635 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3637 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3639 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3640 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
3641 (clobber (reg:CC CC_REGNUM))])]
3642 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3643 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3644 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3645 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3646 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3647 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3650 ; adddi3 instruction pattern(s).
3653 (define_expand "adddi3"
3655 [(set (match_operand:DI 0 "register_operand" "")
3656 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3657 (match_operand:DI 2 "general_operand" "")))
3658 (clobber (reg:CC CC_REGNUM))])]
3662 (define_insn "*adddi3_sign"
3663 [(set (match_operand:DI 0 "register_operand" "=d,d")
3664 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3665 (match_operand:DI 1 "register_operand" "0,0")))
3666 (clobber (reg:CC CC_REGNUM))]
3671 [(set_attr "op_type" "RRE,RXY")])
3673 (define_insn "*adddi3_zero_cc"
3674 [(set (reg CC_REGNUM)
3675 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3676 (match_operand:DI 1 "register_operand" "0,0"))
3678 (set (match_operand:DI 0 "register_operand" "=d,d")
3679 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3680 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3684 [(set_attr "op_type" "RRE,RXY")])
3686 (define_insn "*adddi3_zero_cconly"
3687 [(set (reg CC_REGNUM)
3688 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3689 (match_operand:DI 1 "register_operand" "0,0"))
3691 (clobber (match_scratch:DI 0 "=d,d"))]
3692 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3696 [(set_attr "op_type" "RRE,RXY")])
3698 (define_insn "*adddi3_zero"
3699 [(set (match_operand:DI 0 "register_operand" "=d,d")
3700 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3701 (match_operand:DI 1 "register_operand" "0,0")))
3702 (clobber (reg:CC CC_REGNUM))]
3707 [(set_attr "op_type" "RRE,RXY")])
3709 (define_insn_and_split "*adddi3_31z"
3710 [(set (match_operand:DI 0 "register_operand" "=&d")
3711 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3712 (match_operand:DI 2 "general_operand" "do") ) )
3713 (clobber (reg:CC CC_REGNUM))]
3714 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3716 "&& reload_completed"
3718 [(set (reg:CCL1 CC_REGNUM)
3719 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3721 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3723 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3724 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3725 (clobber (reg:CC CC_REGNUM))])]
3726 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3727 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3728 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3729 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3730 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3731 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3733 (define_insn_and_split "*adddi3_31"
3734 [(set (match_operand:DI 0 "register_operand" "=&d")
3735 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3736 (match_operand:DI 2 "general_operand" "do") ) )
3737 (clobber (reg:CC CC_REGNUM))]
3740 "&& reload_completed"
3742 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3743 (clobber (reg:CC CC_REGNUM))])
3745 [(set (reg:CCL1 CC_REGNUM)
3746 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3748 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3750 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3752 (label_ref (match_dup 9))))
3754 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3755 (clobber (reg:CC CC_REGNUM))])
3757 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3758 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3759 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3760 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3761 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3762 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3763 operands[9] = gen_label_rtx ();")
3766 ; addsi3 instruction pattern(s).
3769 (define_expand "addsi3"
3771 [(set (match_operand:SI 0 "register_operand" "")
3772 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
3773 (match_operand:SI 2 "general_operand" "")))
3774 (clobber (reg:CC CC_REGNUM))])]
3778 (define_insn "*addsi3_sign"
3779 [(set (match_operand:SI 0 "register_operand" "=d,d")
3780 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3781 (match_operand:SI 1 "register_operand" "0,0")))
3782 (clobber (reg:CC CC_REGNUM))]
3787 [(set_attr "op_type" "RX,RXY")])
3790 ; add(di|si)3 instruction pattern(s).
3793 ; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag
3794 (define_insn "*add<mode>3"
3795 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d")
3796 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
3797 (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T") ) )
3798 (clobber (reg:CC CC_REGNUM))]
3807 [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY")])
3809 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
3810 (define_insn "*add<mode>3_carry1_cc"
3811 [(set (reg CC_REGNUM)
3812 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
3813 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
3815 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3816 (plus:GPR (match_dup 1) (match_dup 2)))]
3817 "s390_match_ccmode (insn, CCL1mode)"
3824 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
3826 ; alr, al, aly, algr, alg
3827 (define_insn "*add<mode>3_carry1_cconly"
3828 [(set (reg CC_REGNUM)
3829 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3830 (match_operand:GPR 2 "general_operand" "d,R,T"))
3832 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3833 "s390_match_ccmode (insn, CCL1mode)"
3838 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3840 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
3841 (define_insn "*add<mode>3_carry2_cc"
3842 [(set (reg CC_REGNUM)
3843 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
3844 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
3846 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3847 (plus:GPR (match_dup 1) (match_dup 2)))]
3848 "s390_match_ccmode (insn, CCL1mode)"
3855 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
3857 ; alr, al, aly, algr, alg
3858 (define_insn "*add<mode>3_carry2_cconly"
3859 [(set (reg CC_REGNUM)
3860 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3861 (match_operand:GPR 2 "general_operand" "d,R,T"))
3863 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3864 "s390_match_ccmode (insn, CCL1mode)"
3869 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3871 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
3872 (define_insn "*add<mode>3_cc"
3873 [(set (reg CC_REGNUM)
3874 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
3875 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
3877 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3878 (plus:GPR (match_dup 1) (match_dup 2)))]
3879 "s390_match_ccmode (insn, CCLmode)"
3886 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
3888 ; alr, al, aly, algr, alg
3889 (define_insn "*add<mode>3_cconly"
3890 [(set (reg CC_REGNUM)
3891 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3892 (match_operand:GPR 2 "general_operand" "d,R,T"))
3894 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3895 "s390_match_ccmode (insn, CCLmode)"
3900 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3902 ; alr, al, aly, algr, alg
3903 (define_insn "*add<mode>3_cconly2"
3904 [(set (reg CC_REGNUM)
3905 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3906 (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T"))))
3907 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3908 "s390_match_ccmode(insn, CCLmode)"
3913 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3915 ; ahi, afi, aghi, agfi
3916 (define_insn "*add<mode>3_imm_cc"
3917 [(set (reg CC_REGNUM)
3918 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3919 (match_operand:GPR 2 "const_int_operand" "K,Os"))
3921 (set (match_operand:GPR 0 "register_operand" "=d,d")
3922 (plus:GPR (match_dup 1) (match_dup 2)))]
3923 "s390_match_ccmode (insn, CCAmode)
3924 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3925 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
3926 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
3930 [(set_attr "op_type" "RI,RIL")])
3933 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
3936 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
3937 (define_insn "add<mode>3"
3938 [(set (match_operand:FP 0 "register_operand" "=f, f")
3939 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
3940 (match_operand:FP 2 "general_operand" " f,<Rf>")))
3941 (clobber (reg:CC CC_REGNUM))]
3944 a<xde><bt>r\t%0,<op1>%2
3946 [(set_attr "op_type" "<RRer>,RXE")
3947 (set_attr "type" "fsimp<bfp>")])
3949 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
3950 (define_insn "*add<mode>3_cc"
3951 [(set (reg CC_REGNUM)
3952 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
3953 (match_operand:FP 2 "general_operand" " f,<Rf>"))
3954 (match_operand:FP 3 "const0_operand" "")))
3955 (set (match_operand:FP 0 "register_operand" "=f,f")
3956 (plus:FP (match_dup 1) (match_dup 2)))]
3957 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
3959 a<xde><bt>r\t%0,<op1>%2
3961 [(set_attr "op_type" "<RRer>,RXE")
3962 (set_attr "type" "fsimp<bfp>")])
3964 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
3965 (define_insn "*add<mode>3_cconly"
3966 [(set (reg CC_REGNUM)
3967 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
3968 (match_operand:FP 2 "general_operand" " f,<Rf>"))
3969 (match_operand:FP 3 "const0_operand" "")))
3970 (clobber (match_scratch:FP 0 "=f,f"))]
3971 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
3973 a<xde><bt>r\t%0,<op1>%2
3975 [(set_attr "op_type" "<RRer>,RXE")
3976 (set_attr "type" "fsimp<bfp>")])
3980 ;;- Subtract instructions.
3984 ; subti3 instruction pattern(s).
3987 (define_insn_and_split "subti3"
3988 [(set (match_operand:TI 0 "register_operand" "=&d")
3989 (minus:TI (match_operand:TI 1 "register_operand" "0")
3990 (match_operand:TI 2 "general_operand" "do") ) )
3991 (clobber (reg:CC CC_REGNUM))]
3994 "&& reload_completed"
3996 [(set (reg:CCL2 CC_REGNUM)
3997 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3999 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
4001 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
4002 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
4003 (clobber (reg:CC CC_REGNUM))])]
4004 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
4005 operands[4] = operand_subword (operands[1], 0, 0, TImode);
4006 operands[5] = operand_subword (operands[2], 0, 0, TImode);
4007 operands[6] = operand_subword (operands[0], 1, 0, TImode);
4008 operands[7] = operand_subword (operands[1], 1, 0, TImode);
4009 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
4012 ; subdi3 instruction pattern(s).
4015 (define_expand "subdi3"
4017 [(set (match_operand:DI 0 "register_operand" "")
4018 (minus:DI (match_operand:DI 1 "register_operand" "")
4019 (match_operand:DI 2 "general_operand" "")))
4020 (clobber (reg:CC CC_REGNUM))])]
4024 (define_insn "*subdi3_sign"
4025 [(set (match_operand:DI 0 "register_operand" "=d,d")
4026 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4027 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
4028 (clobber (reg:CC CC_REGNUM))]
4033 [(set_attr "op_type" "RRE,RXY")])
4035 (define_insn "*subdi3_zero_cc"
4036 [(set (reg CC_REGNUM)
4037 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4038 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
4040 (set (match_operand:DI 0 "register_operand" "=d,d")
4041 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
4042 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4046 [(set_attr "op_type" "RRE,RXY")])
4048 (define_insn "*subdi3_zero_cconly"
4049 [(set (reg CC_REGNUM)
4050 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4051 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
4053 (clobber (match_scratch:DI 0 "=d,d"))]
4054 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4058 [(set_attr "op_type" "RRE,RXY")])
4060 (define_insn "*subdi3_zero"
4061 [(set (match_operand:DI 0 "register_operand" "=d,d")
4062 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
4063 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
4064 (clobber (reg:CC CC_REGNUM))]
4069 [(set_attr "op_type" "RRE,RXY")])
4071 (define_insn_and_split "*subdi3_31z"
4072 [(set (match_operand:DI 0 "register_operand" "=&d")
4073 (minus:DI (match_operand:DI 1 "register_operand" "0")
4074 (match_operand:DI 2 "general_operand" "do") ) )
4075 (clobber (reg:CC CC_REGNUM))]
4076 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4078 "&& reload_completed"
4080 [(set (reg:CCL2 CC_REGNUM)
4081 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4083 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4085 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
4086 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
4087 (clobber (reg:CC CC_REGNUM))])]
4088 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4089 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4090 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4091 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4092 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4093 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
4095 (define_insn_and_split "*subdi3_31"
4096 [(set (match_operand:DI 0 "register_operand" "=&d")
4097 (minus:DI (match_operand:DI 1 "register_operand" "0")
4098 (match_operand:DI 2 "general_operand" "do") ) )
4099 (clobber (reg:CC CC_REGNUM))]
4102 "&& reload_completed"
4104 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4105 (clobber (reg:CC CC_REGNUM))])
4107 [(set (reg:CCL2 CC_REGNUM)
4108 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4110 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4112 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4114 (label_ref (match_dup 9))))
4116 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4117 (clobber (reg:CC CC_REGNUM))])
4119 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4120 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4121 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4122 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4123 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4124 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4125 operands[9] = gen_label_rtx ();")
4128 ; subsi3 instruction pattern(s).
4131 (define_expand "subsi3"
4133 [(set (match_operand:SI 0 "register_operand" "")
4134 (minus:SI (match_operand:SI 1 "register_operand" "")
4135 (match_operand:SI 2 "general_operand" "")))
4136 (clobber (reg:CC CC_REGNUM))])]
4140 (define_insn "*subsi3_sign"
4141 [(set (match_operand:SI 0 "register_operand" "=d,d")
4142 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4143 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4144 (clobber (reg:CC CC_REGNUM))]
4149 [(set_attr "op_type" "RX,RXY")])
4152 ; sub(di|si)3 instruction pattern(s).
4155 ; sr, s, sy, sgr, sg
4156 (define_insn "*sub<mode>3"
4157 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4158 (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4159 (match_operand:GPR 2 "general_operand" "d,R,T") ) )
4160 (clobber (reg:CC CC_REGNUM))]
4166 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4168 ; slr, sl, sly, slgr, slg
4169 (define_insn "*sub<mode>3_borrow_cc"
4170 [(set (reg CC_REGNUM)
4171 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4172 (match_operand:GPR 2 "general_operand" "d,R,T"))
4174 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4175 (minus:GPR (match_dup 1) (match_dup 2)))]
4176 "s390_match_ccmode (insn, CCL2mode)"
4181 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4183 ; slr, sl, sly, slgr, slg
4184 (define_insn "*sub<mode>3_borrow_cconly"
4185 [(set (reg CC_REGNUM)
4186 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4187 (match_operand:GPR 2 "general_operand" "d,R,T"))
4189 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4190 "s390_match_ccmode (insn, CCL2mode)"
4195 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4197 ; slr, sl, sly, slgr, slg
4198 (define_insn "*sub<mode>3_cc"
4199 [(set (reg CC_REGNUM)
4200 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4201 (match_operand:GPR 2 "general_operand" "d,R,T"))
4203 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4204 (minus:GPR (match_dup 1) (match_dup 2)))]
4205 "s390_match_ccmode (insn, CCLmode)"
4210 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4212 ; slr, sl, sly, slgr, slg
4213 (define_insn "*sub<mode>3_cc2"
4214 [(set (reg CC_REGNUM)
4215 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4216 (match_operand:GPR 2 "general_operand" "d,R,T")))
4217 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4218 (minus:GPR (match_dup 1) (match_dup 2)))]
4219 "s390_match_ccmode (insn, CCL3mode)"
4224 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4226 ; slr, sl, sly, slgr, slg
4227 (define_insn "*sub<mode>3_cconly"
4228 [(set (reg CC_REGNUM)
4229 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4230 (match_operand:GPR 2 "general_operand" "d,R,T"))
4232 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4233 "s390_match_ccmode (insn, CCLmode)"
4238 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4240 ; slr, sl, sly, slgr, slg
4241 (define_insn "*sub<mode>3_cconly2"
4242 [(set (reg CC_REGNUM)
4243 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4244 (match_operand:GPR 2 "general_operand" "d,R,T")))
4245 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4246 "s390_match_ccmode (insn, CCL3mode)"
4251 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4254 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
4257 ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
4258 (define_insn "sub<mode>3"
4259 [(set (match_operand:FP 0 "register_operand" "=f, f")
4260 (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
4261 (match_operand:FP 2 "general_operand" "f,<Rf>")))
4262 (clobber (reg:CC CC_REGNUM))]
4265 s<xde><bt>r\t%0,<op1>%2
4267 [(set_attr "op_type" "<RRer>,RXE")
4268 (set_attr "type" "fsimp<bfp>")])
4270 ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
4271 (define_insn "*sub<mode>3_cc"
4272 [(set (reg CC_REGNUM)
4273 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4274 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4275 (match_operand:FP 3 "const0_operand" "")))
4276 (set (match_operand:FP 0 "register_operand" "=f,f")
4277 (minus:FP (match_dup 1) (match_dup 2)))]
4278 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4280 s<xde><bt>r\t%0,<op1>%2
4282 [(set_attr "op_type" "<RRer>,RXE")
4283 (set_attr "type" "fsimp<bfp>")])
4285 ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
4286 (define_insn "*sub<mode>3_cconly"
4287 [(set (reg CC_REGNUM)
4288 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
4289 (match_operand:FP 2 "general_operand" "f,<Rf>"))
4290 (match_operand:FP 3 "const0_operand" "")))
4291 (clobber (match_scratch:FP 0 "=f,f"))]
4292 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
4294 s<xde><bt>r\t%0,<op1>%2
4296 [(set_attr "op_type" "<RRer>,RXE")
4297 (set_attr "type" "fsimp<bfp>")])
4301 ;;- Conditional add/subtract instructions.
4305 ; add(di|si)cc instruction pattern(s).
4308 ; alcr, alc, alcgr, alcg
4309 (define_insn "*add<mode>3_alc_cc"
4310 [(set (reg CC_REGNUM)
4312 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4313 (match_operand:GPR 2 "general_operand" "d,m"))
4314 (match_operand:GPR 3 "s390_alc_comparison" ""))
4316 (set (match_operand:GPR 0 "register_operand" "=d,d")
4317 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4318 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4322 [(set_attr "op_type" "RRE,RXY")])
4324 ; alcr, alc, alcgr, alcg
4325 (define_insn "*add<mode>3_alc"
4326 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4327 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4328 (match_operand:GPR 2 "general_operand" "d,m"))
4329 (match_operand:GPR 3 "s390_alc_comparison" "")))
4330 (clobber (reg:CC CC_REGNUM))]
4335 [(set_attr "op_type" "RRE,RXY")])
4337 ; slbr, slb, slbgr, slbg
4338 (define_insn "*sub<mode>3_slb_cc"
4339 [(set (reg CC_REGNUM)
4341 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4342 (match_operand:GPR 2 "general_operand" "d,m"))
4343 (match_operand:GPR 3 "s390_slb_comparison" ""))
4345 (set (match_operand:GPR 0 "register_operand" "=d,d")
4346 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4347 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4351 [(set_attr "op_type" "RRE,RXY")])
4353 ; slbr, slb, slbgr, slbg
4354 (define_insn "*sub<mode>3_slb"
4355 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4356 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4357 (match_operand:GPR 2 "general_operand" "d,m"))
4358 (match_operand:GPR 3 "s390_slb_comparison" "")))
4359 (clobber (reg:CC CC_REGNUM))]
4364 [(set_attr "op_type" "RRE,RXY")])
4366 (define_expand "add<mode>cc"
4367 [(match_operand:GPR 0 "register_operand" "")
4368 (match_operand 1 "comparison_operator" "")
4369 (match_operand:GPR 2 "register_operand" "")
4370 (match_operand:GPR 3 "const_int_operand" "")]
4372 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4373 s390_compare_op0, s390_compare_op1,
4374 operands[0], operands[2],
4375 operands[3])) FAIL; DONE;")
4378 ; scond instruction pattern(s).
4381 (define_insn_and_split "*scond<mode>"
4382 [(set (match_operand:GPR 0 "register_operand" "=&d")
4383 (match_operand:GPR 1 "s390_alc_comparison" ""))
4384 (clobber (reg:CC CC_REGNUM))]
4387 "&& reload_completed"
4388 [(set (match_dup 0) (const_int 0))
4390 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
4392 (clobber (reg:CC CC_REGNUM))])]
4395 (define_insn_and_split "*scond<mode>_neg"
4396 [(set (match_operand:GPR 0 "register_operand" "=&d")
4397 (match_operand:GPR 1 "s390_slb_comparison" ""))
4398 (clobber (reg:CC CC_REGNUM))]
4401 "&& reload_completed"
4402 [(set (match_dup 0) (const_int 0))
4404 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
4406 (clobber (reg:CC CC_REGNUM))])
4408 [(set (match_dup 0) (neg:GPR (match_dup 0)))
4409 (clobber (reg:CC CC_REGNUM))])]
4413 (define_expand "s<code>"
4414 [(set (match_operand:SI 0 "register_operand" "")
4415 (SCOND (match_dup 0)
4418 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
4419 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4421 (define_expand "seq"
4423 [(set (match_operand:SI 0 "register_operand" "=d")
4425 (clobber (reg:CC CC_REGNUM))])
4427 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
4428 (clobber (reg:CC CC_REGNUM))])]
4431 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
4433 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
4434 PUT_MODE (operands[1], SImode);
4437 (define_insn_and_split "*sne"
4438 [(set (match_operand:SI 0 "register_operand" "=d")
4439 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
4441 (clobber (reg:CC CC_REGNUM))]
4446 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
4447 (clobber (reg:CC CC_REGNUM))])])
4451 ;;- Multiply instructions.
4455 ; muldi3 instruction pattern(s).
4458 (define_insn "*muldi3_sign"
4459 [(set (match_operand:DI 0 "register_operand" "=d,d")
4460 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4461 (match_operand:DI 1 "register_operand" "0,0")))]
4466 [(set_attr "op_type" "RRE,RXY")
4467 (set_attr "type" "imuldi")])
4469 (define_insn "muldi3"
4470 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4471 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4472 (match_operand:DI 2 "general_operand" "d,K,m")))]
4478 [(set_attr "op_type" "RRE,RI,RXY")
4479 (set_attr "type" "imuldi")])
4482 ; mulsi3 instruction pattern(s).
4485 (define_insn "*mulsi3_sign"
4486 [(set (match_operand:SI 0 "register_operand" "=d")
4487 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4488 (match_operand:SI 1 "register_operand" "0")))]
4491 [(set_attr "op_type" "RX")
4492 (set_attr "type" "imulhi")])
4494 (define_insn "mulsi3"
4495 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4496 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4497 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4504 [(set_attr "op_type" "RRE,RI,RX,RXY")
4505 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4508 ; mulsidi3 instruction pattern(s).
4511 (define_insn "mulsidi3"
4512 [(set (match_operand:DI 0 "register_operand" "=d,d")
4513 (mult:DI (sign_extend:DI
4514 (match_operand:SI 1 "register_operand" "%0,0"))
4516 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4521 [(set_attr "op_type" "RR,RX")
4522 (set_attr "type" "imulsi")])
4525 ; umulsidi3 instruction pattern(s).
4528 (define_insn "umulsidi3"
4529 [(set (match_operand:DI 0 "register_operand" "=d,d")
4530 (mult:DI (zero_extend:DI
4531 (match_operand:SI 1 "register_operand" "%0,0"))
4533 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4534 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4538 [(set_attr "op_type" "RRE,RXY")
4539 (set_attr "type" "imulsi")])
4542 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
4545 ; mxbr mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
4546 (define_insn "mul<mode>3"
4547 [(set (match_operand:FP 0 "register_operand" "=f,f")
4548 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
4549 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
4552 m<xdee><bt>r\t%0,<op1>%2
4554 [(set_attr "op_type" "<RRer>,RXE")
4555 (set_attr "type" "fmul<bfp>")])
4557 ; maxbr, madbr, maebr, maxb, madb, maeb
4558 (define_insn "*fmadd<mode>"
4559 [(set (match_operand:DSF 0 "register_operand" "=f,f")
4560 (plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f")
4561 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
4562 (match_operand:DSF 3 "register_operand" "0,0")))]
4563 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4567 [(set_attr "op_type" "RRE,RXE")
4568 (set_attr "type" "fmul<mode>")])
4570 ; msxbr, msdbr, msebr, msxb, msdb, mseb
4571 (define_insn "*fmsub<mode>"
4572 [(set (match_operand:DSF 0 "register_operand" "=f,f")
4573 (minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f")
4574 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
4575 (match_operand:DSF 3 "register_operand" "0,0")))]
4576 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4580 [(set_attr "op_type" "RRE,RXE")
4581 (set_attr "type" "fmul<mode>")])
4584 ;;- Divide and modulo instructions.
4588 ; divmoddi4 instruction pattern(s).
4591 (define_expand "divmoddi4"
4592 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4593 (div:DI (match_operand:DI 1 "register_operand" "")
4594 (match_operand:DI 2 "general_operand" "")))
4595 (set (match_operand:DI 3 "general_operand" "")
4596 (mod:DI (match_dup 1) (match_dup 2)))])
4597 (clobber (match_dup 4))]
4600 rtx insn, div_equal, mod_equal;
4602 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4603 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4605 operands[4] = gen_reg_rtx(TImode);
4606 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4608 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4609 set_unique_reg_note (insn, REG_EQUAL, div_equal);
4611 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4612 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
4617 (define_insn "divmodtidi3"
4618 [(set (match_operand:TI 0 "register_operand" "=d,d")
4622 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4623 (match_operand:DI 2 "general_operand" "d,m")))
4625 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4630 [(set_attr "op_type" "RRE,RXY")
4631 (set_attr "type" "idiv")])
4633 (define_insn "divmodtisi3"
4634 [(set (match_operand:TI 0 "register_operand" "=d,d")
4638 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4640 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4643 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4648 [(set_attr "op_type" "RRE,RXY")
4649 (set_attr "type" "idiv")])
4652 ; udivmoddi4 instruction pattern(s).
4655 (define_expand "udivmoddi4"
4656 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4657 (udiv:DI (match_operand:DI 1 "general_operand" "")
4658 (match_operand:DI 2 "nonimmediate_operand" "")))
4659 (set (match_operand:DI 3 "general_operand" "")
4660 (umod:DI (match_dup 1) (match_dup 2)))])
4661 (clobber (match_dup 4))]
4664 rtx insn, div_equal, mod_equal, equal;
4666 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4667 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4668 equal = gen_rtx_IOR (TImode,
4669 gen_rtx_ASHIFT (TImode,
4670 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4672 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4674 operands[4] = gen_reg_rtx(TImode);
4675 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4676 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4677 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4679 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4680 set_unique_reg_note (insn, REG_EQUAL, equal);
4682 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4683 set_unique_reg_note (insn, REG_EQUAL, div_equal);
4685 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4686 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
4691 (define_insn "udivmodtidi3"
4692 [(set (match_operand:TI 0 "register_operand" "=d,d")
4697 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4699 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4703 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4708 [(set_attr "op_type" "RRE,RXY")
4709 (set_attr "type" "idiv")])
4712 ; divmodsi4 instruction pattern(s).
4715 (define_expand "divmodsi4"
4716 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4717 (div:SI (match_operand:SI 1 "general_operand" "")
4718 (match_operand:SI 2 "nonimmediate_operand" "")))
4719 (set (match_operand:SI 3 "general_operand" "")
4720 (mod:SI (match_dup 1) (match_dup 2)))])
4721 (clobber (match_dup 4))]
4724 rtx insn, div_equal, mod_equal, equal;
4726 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4727 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4728 equal = gen_rtx_IOR (DImode,
4729 gen_rtx_ASHIFT (DImode,
4730 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4732 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4734 operands[4] = gen_reg_rtx(DImode);
4735 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4737 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4738 set_unique_reg_note (insn, REG_EQUAL, equal);
4740 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4741 set_unique_reg_note (insn, REG_EQUAL, div_equal);
4743 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4744 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
4749 (define_insn "divmoddisi3"
4750 [(set (match_operand:DI 0 "register_operand" "=d,d")
4755 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4757 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4761 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4766 [(set_attr "op_type" "RR,RX")
4767 (set_attr "type" "idiv")])
4770 ; udivsi3 and umodsi3 instruction pattern(s).
4773 (define_expand "udivmodsi4"
4774 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4775 (udiv:SI (match_operand:SI 1 "general_operand" "")
4776 (match_operand:SI 2 "nonimmediate_operand" "")))
4777 (set (match_operand:SI 3 "general_operand" "")
4778 (umod:SI (match_dup 1) (match_dup 2)))])
4779 (clobber (match_dup 4))]
4780 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4782 rtx insn, div_equal, mod_equal, equal;
4784 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4785 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4786 equal = gen_rtx_IOR (DImode,
4787 gen_rtx_ASHIFT (DImode,
4788 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4790 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4792 operands[4] = gen_reg_rtx(DImode);
4793 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4794 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4795 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4797 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4798 set_unique_reg_note (insn, REG_EQUAL, equal);
4800 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4801 set_unique_reg_note (insn, REG_EQUAL, div_equal);
4803 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4804 set_unique_reg_note (insn, REG_EQUAL, mod_equal);
4809 (define_insn "udivmoddisi3"
4810 [(set (match_operand:DI 0 "register_operand" "=d,d")
4815 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4817 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4821 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4822 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4826 [(set_attr "op_type" "RRE,RXY")
4827 (set_attr "type" "idiv")])
4829 (define_expand "udivsi3"
4830 [(set (match_operand:SI 0 "register_operand" "=d")
4831 (udiv:SI (match_operand:SI 1 "general_operand" "")
4832 (match_operand:SI 2 "general_operand" "")))
4833 (clobber (match_dup 3))]
4834 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4836 rtx insn, udiv_equal, umod_equal, equal;
4838 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4839 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4840 equal = gen_rtx_IOR (DImode,
4841 gen_rtx_ASHIFT (DImode,
4842 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4844 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4846 operands[3] = gen_reg_rtx (DImode);
4848 if (CONSTANT_P (operands[2]))
4850 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4852 rtx label1 = gen_label_rtx ();
4854 operands[1] = make_safe_from (operands[1], operands[0]);
4855 emit_move_insn (operands[0], const0_rtx);
4856 emit_insn (gen_cmpsi (operands[1], operands[2]));
4857 emit_jump_insn (gen_bltu (label1));
4858 emit_move_insn (operands[0], const1_rtx);
4859 emit_label (label1);
4863 operands[2] = force_reg (SImode, operands[2]);
4864 operands[2] = make_safe_from (operands[2], operands[0]);
4866 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4867 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4869 set_unique_reg_note (insn, REG_EQUAL, equal);
4871 insn = emit_move_insn (operands[0],
4872 gen_lowpart (SImode, operands[3]));
4873 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
4878 rtx label1 = gen_label_rtx ();
4879 rtx label2 = gen_label_rtx ();
4880 rtx label3 = gen_label_rtx ();
4882 operands[1] = force_reg (SImode, operands[1]);
4883 operands[1] = make_safe_from (operands[1], operands[0]);
4884 operands[2] = force_reg (SImode, operands[2]);
4885 operands[2] = make_safe_from (operands[2], operands[0]);
4887 emit_move_insn (operands[0], const0_rtx);
4888 emit_insn (gen_cmpsi (operands[2], operands[1]));
4889 emit_jump_insn (gen_bgtu (label3));
4890 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4891 emit_jump_insn (gen_blt (label2));
4892 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4893 emit_jump_insn (gen_beq (label1));
4894 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4895 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4897 set_unique_reg_note (insn, REG_EQUAL, equal);
4899 insn = emit_move_insn (operands[0],
4900 gen_lowpart (SImode, operands[3]));
4901 set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
4904 emit_label (label1);
4905 emit_move_insn (operands[0], operands[1]);
4907 emit_label (label2);
4908 emit_move_insn (operands[0], const1_rtx);
4909 emit_label (label3);
4911 emit_move_insn (operands[0], operands[0]);
4915 (define_expand "umodsi3"
4916 [(set (match_operand:SI 0 "register_operand" "=d")
4917 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4918 (match_operand:SI 2 "nonimmediate_operand" "")))
4919 (clobber (match_dup 3))]
4920 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4922 rtx insn, udiv_equal, umod_equal, equal;
4924 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4925 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4926 equal = gen_rtx_IOR (DImode,
4927 gen_rtx_ASHIFT (DImode,
4928 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4930 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4932 operands[3] = gen_reg_rtx (DImode);
4934 if (CONSTANT_P (operands[2]))
4936 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4938 rtx label1 = gen_label_rtx ();
4940 operands[1] = make_safe_from (operands[1], operands[0]);
4941 emit_move_insn (operands[0], operands[1]);
4942 emit_insn (gen_cmpsi (operands[0], operands[2]));
4943 emit_jump_insn (gen_bltu (label1));
4944 emit_insn (gen_abssi2 (operands[0], operands[2]));
4945 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4946 emit_label (label1);
4950 operands[2] = force_reg (SImode, operands[2]);
4951 operands[2] = make_safe_from (operands[2], operands[0]);
4953 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4954 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4956 set_unique_reg_note (insn, REG_EQUAL, equal);
4958 insn = emit_move_insn (operands[0],
4959 gen_highpart (SImode, operands[3]));
4960 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
4965 rtx label1 = gen_label_rtx ();
4966 rtx label2 = gen_label_rtx ();
4967 rtx label3 = gen_label_rtx ();
4969 operands[1] = force_reg (SImode, operands[1]);
4970 operands[1] = make_safe_from (operands[1], operands[0]);
4971 operands[2] = force_reg (SImode, operands[2]);
4972 operands[2] = make_safe_from (operands[2], operands[0]);
4974 emit_move_insn(operands[0], operands[1]);
4975 emit_insn (gen_cmpsi (operands[2], operands[1]));
4976 emit_jump_insn (gen_bgtu (label3));
4977 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4978 emit_jump_insn (gen_blt (label2));
4979 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4980 emit_jump_insn (gen_beq (label1));
4981 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4982 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4984 set_unique_reg_note (insn, REG_EQUAL, equal);
4986 insn = emit_move_insn (operands[0],
4987 gen_highpart (SImode, operands[3]));
4988 set_unique_reg_note (insn, REG_EQUAL, umod_equal);
4991 emit_label (label1);
4992 emit_move_insn (operands[0], const0_rtx);
4994 emit_label (label2);
4995 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4996 emit_label (label3);
5002 ; div(df|sf)3 instruction pattern(s).
5005 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
5006 (define_insn "div<mode>3"
5007 [(set (match_operand:FP 0 "register_operand" "=f,f")
5008 (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
5009 (match_operand:FP 2 "general_operand" "f,<Rf>")))]
5012 d<xde><bt>r\t%0,<op1>%2
5014 [(set_attr "op_type" "<RRer>,RXE")
5015 (set_attr "type" "fdiv<bfp>")])
5019 ;;- And instructions.
5022 (define_expand "and<mode>3"
5023 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5024 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
5025 (match_operand:INT 2 "general_operand" "")))
5026 (clobber (reg:CC CC_REGNUM))]
5028 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
5031 ; anddi3 instruction pattern(s).
5034 (define_insn "*anddi3_cc"
5035 [(set (reg CC_REGNUM)
5036 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5037 (match_operand:DI 2 "general_operand" "d,m"))
5039 (set (match_operand:DI 0 "register_operand" "=d,d")
5040 (and:DI (match_dup 1) (match_dup 2)))]
5041 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5045 [(set_attr "op_type" "RRE,RXY")])
5047 (define_insn "*anddi3_cconly"
5048 [(set (reg CC_REGNUM)
5049 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5050 (match_operand:DI 2 "general_operand" "d,m"))
5052 (clobber (match_scratch:DI 0 "=d,d"))]
5053 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
5054 /* Do not steal TM patterns. */
5055 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5059 [(set_attr "op_type" "RRE,RXY")])
5061 (define_insn "*anddi3_extimm"
5062 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
5063 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5064 "%d,o,0,0,0,0,0,0,0,0,0,0")
5065 (match_operand:DI 2 "general_operand"
5066 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q")))
5067 (clobber (reg:CC CC_REGNUM))]
5068 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5082 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5084 (define_insn "*anddi3"
5085 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5086 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5087 "%d,o,0,0,0,0,0,0,0,0")
5088 (match_operand:DI 2 "general_operand"
5089 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
5090 (clobber (reg:CC CC_REGNUM))]
5091 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5103 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
5106 [(set (match_operand:DI 0 "s_operand" "")
5107 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5108 (clobber (reg:CC CC_REGNUM))]
5111 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5112 (clobber (reg:CC CC_REGNUM))])]
5113 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5117 ; andsi3 instruction pattern(s).
5120 (define_insn "*andsi3_cc"
5121 [(set (reg CC_REGNUM)
5122 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5123 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5125 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5126 (and:SI (match_dup 1) (match_dup 2)))]
5127 "s390_match_ccmode(insn, CCTmode)"
5133 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5135 (define_insn "*andsi3_cconly"
5136 [(set (reg CC_REGNUM)
5137 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5138 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5140 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5141 "s390_match_ccmode(insn, CCTmode)
5142 /* Do not steal TM patterns. */
5143 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5149 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5151 (define_insn "*andsi3_zarch"
5152 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5153 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5154 "%d,o,0,0,0,0,0,0,0,0")
5155 (match_operand:SI 2 "general_operand"
5156 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
5157 (clobber (reg:CC CC_REGNUM))]
5158 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5170 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")])
5172 (define_insn "*andsi3_esa"
5173 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5174 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5175 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5176 (clobber (reg:CC CC_REGNUM))]
5177 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5183 [(set_attr "op_type" "RR,RX,SI,SS")])
5186 [(set (match_operand:SI 0 "s_operand" "")
5187 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5188 (clobber (reg:CC CC_REGNUM))]
5191 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5192 (clobber (reg:CC CC_REGNUM))])]
5193 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5196 ; andhi3 instruction pattern(s).
5199 (define_insn "*andhi3_zarch"
5200 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5201 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5202 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5203 (clobber (reg:CC CC_REGNUM))]
5204 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5210 [(set_attr "op_type" "RR,RI,SI,SS")])
5212 (define_insn "*andhi3_esa"
5213 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5214 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5215 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5216 (clobber (reg:CC CC_REGNUM))]
5217 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5222 [(set_attr "op_type" "RR,SI,SS")])
5225 [(set (match_operand:HI 0 "s_operand" "")
5226 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5227 (clobber (reg:CC CC_REGNUM))]
5230 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5231 (clobber (reg:CC CC_REGNUM))])]
5232 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5235 ; andqi3 instruction pattern(s).
5238 (define_insn "*andqi3_zarch"
5239 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5240 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5241 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5242 (clobber (reg:CC CC_REGNUM))]
5243 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5250 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5252 (define_insn "*andqi3_esa"
5253 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5254 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5255 (match_operand:QI 2 "general_operand" "d,n,Q")))
5256 (clobber (reg:CC CC_REGNUM))]
5257 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5262 [(set_attr "op_type" "RR,SI,SS")])
5265 ; Block and (NC) patterns.
5269 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5270 (and:BLK (match_dup 0)
5271 (match_operand:BLK 1 "memory_operand" "Q")))
5272 (use (match_operand 2 "const_int_operand" "n"))
5273 (clobber (reg:CC CC_REGNUM))]
5274 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5275 "nc\t%O0(%2,%R0),%S1"
5276 [(set_attr "op_type" "SS")])
5279 [(set (match_operand 0 "memory_operand" "")
5281 (match_operand 1 "memory_operand" "")))
5282 (clobber (reg:CC CC_REGNUM))]
5284 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5285 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5287 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
5289 (clobber (reg:CC CC_REGNUM))])]
5291 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5292 operands[0] = adjust_address (operands[0], BLKmode, 0);
5293 operands[1] = adjust_address (operands[1], BLKmode, 0);
5298 [(set (match_operand:BLK 0 "memory_operand" "")
5299 (and:BLK (match_dup 0)
5300 (match_operand:BLK 1 "memory_operand" "")))
5301 (use (match_operand 2 "const_int_operand" ""))
5302 (clobber (reg:CC CC_REGNUM))])
5304 [(set (match_operand:BLK 3 "memory_operand" "")
5305 (and:BLK (match_dup 3)
5306 (match_operand:BLK 4 "memory_operand" "")))
5307 (use (match_operand 5 "const_int_operand" ""))
5308 (clobber (reg:CC CC_REGNUM))])]
5309 "s390_offset_p (operands[0], operands[3], operands[2])
5310 && s390_offset_p (operands[1], operands[4], operands[2])
5311 && !s390_overlap_p (operands[0], operands[1],
5312 INTVAL (operands[2]) + INTVAL (operands[5]))
5313 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5315 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
5317 (clobber (reg:CC CC_REGNUM))])]
5318 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5319 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5320 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5324 ;;- Bit set (inclusive or) instructions.
5327 (define_expand "ior<mode>3"
5328 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5329 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
5330 (match_operand:INT 2 "general_operand" "")))
5331 (clobber (reg:CC CC_REGNUM))]
5333 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
5336 ; iordi3 instruction pattern(s).
5339 (define_insn "*iordi3_cc"
5340 [(set (reg CC_REGNUM)
5341 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5342 (match_operand:DI 2 "general_operand" "d,m"))
5344 (set (match_operand:DI 0 "register_operand" "=d,d")
5345 (ior:DI (match_dup 1) (match_dup 2)))]
5346 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5350 [(set_attr "op_type" "RRE,RXY")])
5352 (define_insn "*iordi3_cconly"
5353 [(set (reg CC_REGNUM)
5354 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5355 (match_operand:DI 2 "general_operand" "d,m"))
5357 (clobber (match_scratch:DI 0 "=d,d"))]
5358 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5362 [(set_attr "op_type" "RRE,RXY")])
5364 (define_insn "*iordi3_extimm"
5365 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5366 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
5367 (match_operand:DI 2 "general_operand"
5368 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q")))
5369 (clobber (reg:CC CC_REGNUM))]
5370 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5382 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5384 (define_insn "*iordi3"
5385 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5386 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5387 (match_operand:DI 2 "general_operand"
5388 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5389 (clobber (reg:CC CC_REGNUM))]
5390 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5400 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5403 [(set (match_operand:DI 0 "s_operand" "")
5404 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5405 (clobber (reg:CC CC_REGNUM))]
5408 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5409 (clobber (reg:CC CC_REGNUM))])]
5410 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5413 ; iorsi3 instruction pattern(s).
5416 (define_insn "*iorsi3_cc"
5417 [(set (reg CC_REGNUM)
5418 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5419 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5421 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5422 (ior:SI (match_dup 1) (match_dup 2)))]
5423 "s390_match_ccmode(insn, CCTmode)"
5429 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5431 (define_insn "*iorsi3_cconly"
5432 [(set (reg CC_REGNUM)
5433 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5434 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5436 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5437 "s390_match_ccmode(insn, CCTmode)"
5443 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5445 (define_insn "*iorsi3_zarch"
5446 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5447 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5448 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
5449 (clobber (reg:CC CC_REGNUM))]
5450 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5460 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")])
5462 (define_insn "*iorsi3_esa"
5463 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5464 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5465 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5466 (clobber (reg:CC CC_REGNUM))]
5467 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5473 [(set_attr "op_type" "RR,RX,SI,SS")])
5476 [(set (match_operand:SI 0 "s_operand" "")
5477 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5478 (clobber (reg:CC CC_REGNUM))]
5481 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5482 (clobber (reg:CC CC_REGNUM))])]
5483 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5486 ; iorhi3 instruction pattern(s).
5489 (define_insn "*iorhi3_zarch"
5490 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5491 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5492 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5493 (clobber (reg:CC CC_REGNUM))]
5494 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5500 [(set_attr "op_type" "RR,RI,SI,SS")])
5502 (define_insn "*iorhi3_esa"
5503 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5504 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5505 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5506 (clobber (reg:CC CC_REGNUM))]
5507 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5512 [(set_attr "op_type" "RR,SI,SS")])
5515 [(set (match_operand:HI 0 "s_operand" "")
5516 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5517 (clobber (reg:CC CC_REGNUM))]
5520 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5521 (clobber (reg:CC CC_REGNUM))])]
5522 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5525 ; iorqi3 instruction pattern(s).
5528 (define_insn "*iorqi3_zarch"
5529 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5530 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5531 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5532 (clobber (reg:CC CC_REGNUM))]
5533 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5540 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5542 (define_insn "*iorqi3_esa"
5543 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5544 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5545 (match_operand:QI 2 "general_operand" "d,n,Q")))
5546 (clobber (reg:CC CC_REGNUM))]
5547 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5552 [(set_attr "op_type" "RR,SI,SS")])
5555 ; Block inclusive or (OC) patterns.
5559 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5560 (ior:BLK (match_dup 0)
5561 (match_operand:BLK 1 "memory_operand" "Q")))
5562 (use (match_operand 2 "const_int_operand" "n"))
5563 (clobber (reg:CC CC_REGNUM))]
5564 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5565 "oc\t%O0(%2,%R0),%S1"
5566 [(set_attr "op_type" "SS")])
5569 [(set (match_operand 0 "memory_operand" "")
5571 (match_operand 1 "memory_operand" "")))
5572 (clobber (reg:CC CC_REGNUM))]
5574 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5575 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5577 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5579 (clobber (reg:CC CC_REGNUM))])]
5581 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5582 operands[0] = adjust_address (operands[0], BLKmode, 0);
5583 operands[1] = adjust_address (operands[1], BLKmode, 0);
5588 [(set (match_operand:BLK 0 "memory_operand" "")
5589 (ior:BLK (match_dup 0)
5590 (match_operand:BLK 1 "memory_operand" "")))
5591 (use (match_operand 2 "const_int_operand" ""))
5592 (clobber (reg:CC CC_REGNUM))])
5594 [(set (match_operand:BLK 3 "memory_operand" "")
5595 (ior:BLK (match_dup 3)
5596 (match_operand:BLK 4 "memory_operand" "")))
5597 (use (match_operand 5 "const_int_operand" ""))
5598 (clobber (reg:CC CC_REGNUM))])]
5599 "s390_offset_p (operands[0], operands[3], operands[2])
5600 && s390_offset_p (operands[1], operands[4], operands[2])
5601 && !s390_overlap_p (operands[0], operands[1],
5602 INTVAL (operands[2]) + INTVAL (operands[5]))
5603 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5605 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5607 (clobber (reg:CC CC_REGNUM))])]
5608 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5609 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5610 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5614 ;;- Xor instructions.
5617 (define_expand "xor<mode>3"
5618 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5619 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5620 (match_operand:INT 2 "general_operand" "")))
5621 (clobber (reg:CC CC_REGNUM))]
5623 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5626 ; xordi3 instruction pattern(s).
5629 (define_insn "*xordi3_cc"
5630 [(set (reg CC_REGNUM)
5631 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5632 (match_operand:DI 2 "general_operand" "d,m"))
5634 (set (match_operand:DI 0 "register_operand" "=d,d")
5635 (xor:DI (match_dup 1) (match_dup 2)))]
5636 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5640 [(set_attr "op_type" "RRE,RXY")])
5642 (define_insn "*xordi3_cconly"
5643 [(set (reg CC_REGNUM)
5644 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5645 (match_operand:DI 2 "general_operand" "d,m"))
5647 (clobber (match_scratch:DI 0 "=d,d"))]
5648 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5652 [(set_attr "op_type" "RRE,RXY")])
5654 (define_insn "*xordi3_extimm"
5655 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5656 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5657 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q")))
5658 (clobber (reg:CC CC_REGNUM))]
5659 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5667 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")])
5669 (define_insn "*xordi3"
5670 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5671 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5672 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5673 (clobber (reg:CC CC_REGNUM))]
5674 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5680 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5683 [(set (match_operand:DI 0 "s_operand" "")
5684 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5685 (clobber (reg:CC CC_REGNUM))]
5688 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5689 (clobber (reg:CC CC_REGNUM))])]
5690 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5693 ; xorsi3 instruction pattern(s).
5696 (define_insn "*xorsi3_cc"
5697 [(set (reg CC_REGNUM)
5698 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5699 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5701 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5702 (xor:SI (match_dup 1) (match_dup 2)))]
5703 "s390_match_ccmode(insn, CCTmode)"
5709 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5711 (define_insn "*xorsi3_cconly"
5712 [(set (reg CC_REGNUM)
5713 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5714 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5716 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5717 "s390_match_ccmode(insn, CCTmode)"
5723 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5725 (define_insn "*xorsi3"
5726 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5727 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5728 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
5729 (clobber (reg:CC CC_REGNUM))]
5730 "s390_logical_operator_ok_p (operands)"
5738 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")])
5741 [(set (match_operand:SI 0 "s_operand" "")
5742 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5743 (clobber (reg:CC CC_REGNUM))]
5746 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5747 (clobber (reg:CC CC_REGNUM))])]
5748 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5751 ; xorhi3 instruction pattern(s).
5754 (define_insn "*xorhi3"
5755 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5756 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5757 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
5758 (clobber (reg:CC CC_REGNUM))]
5759 "s390_logical_operator_ok_p (operands)"
5765 [(set_attr "op_type" "RIL,RR,SI,SS")])
5768 [(set (match_operand:HI 0 "s_operand" "")
5769 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5770 (clobber (reg:CC CC_REGNUM))]
5773 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5774 (clobber (reg:CC CC_REGNUM))])]
5775 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5778 ; xorqi3 instruction pattern(s).
5781 (define_insn "*xorqi3"
5782 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5783 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5784 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
5785 (clobber (reg:CC CC_REGNUM))]
5786 "s390_logical_operator_ok_p (operands)"
5793 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")])
5796 ; Block exclusive or (XC) patterns.
5800 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5801 (xor:BLK (match_dup 0)
5802 (match_operand:BLK 1 "memory_operand" "Q")))
5803 (use (match_operand 2 "const_int_operand" "n"))
5804 (clobber (reg:CC CC_REGNUM))]
5805 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5806 "xc\t%O0(%2,%R0),%S1"
5807 [(set_attr "op_type" "SS")])
5810 [(set (match_operand 0 "memory_operand" "")
5812 (match_operand 1 "memory_operand" "")))
5813 (clobber (reg:CC CC_REGNUM))]
5815 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5816 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5818 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5820 (clobber (reg:CC CC_REGNUM))])]
5822 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5823 operands[0] = adjust_address (operands[0], BLKmode, 0);
5824 operands[1] = adjust_address (operands[1], BLKmode, 0);
5829 [(set (match_operand:BLK 0 "memory_operand" "")
5830 (xor:BLK (match_dup 0)
5831 (match_operand:BLK 1 "memory_operand" "")))
5832 (use (match_operand 2 "const_int_operand" ""))
5833 (clobber (reg:CC CC_REGNUM))])
5835 [(set (match_operand:BLK 3 "memory_operand" "")
5836 (xor:BLK (match_dup 3)
5837 (match_operand:BLK 4 "memory_operand" "")))
5838 (use (match_operand 5 "const_int_operand" ""))
5839 (clobber (reg:CC CC_REGNUM))])]
5840 "s390_offset_p (operands[0], operands[3], operands[2])
5841 && s390_offset_p (operands[1], operands[4], operands[2])
5842 && !s390_overlap_p (operands[0], operands[1],
5843 INTVAL (operands[2]) + INTVAL (operands[5]))
5844 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5846 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5848 (clobber (reg:CC CC_REGNUM))])]
5849 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5850 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5851 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5854 ; Block xor (XC) patterns with src == dest.
5857 (define_insn "*xc_zero"
5858 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5860 (use (match_operand 1 "const_int_operand" "n"))
5861 (clobber (reg:CC CC_REGNUM))]
5862 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5863 "xc\t%O0(%1,%R0),%S0"
5864 [(set_attr "op_type" "SS")])
5868 [(set (match_operand:BLK 0 "memory_operand" "")
5870 (use (match_operand 1 "const_int_operand" ""))
5871 (clobber (reg:CC CC_REGNUM))])
5873 [(set (match_operand:BLK 2 "memory_operand" "")
5875 (use (match_operand 3 "const_int_operand" ""))
5876 (clobber (reg:CC CC_REGNUM))])]
5877 "s390_offset_p (operands[0], operands[2], operands[1])
5878 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5880 [(set (match_dup 4) (const_int 0))
5882 (clobber (reg:CC CC_REGNUM))])]
5883 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5884 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5888 ;;- Negate instructions.
5892 ; neg(di|si)2 instruction pattern(s).
5895 (define_expand "neg<mode>2"
5897 [(set (match_operand:DSI 0 "register_operand" "=d")
5898 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5899 (clobber (reg:CC CC_REGNUM))])]
5903 (define_insn "*negdi2_sign_cc"
5904 [(set (reg CC_REGNUM)
5905 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5906 (match_operand:SI 1 "register_operand" "d") 0)
5907 (const_int 32)) (const_int 32)))
5909 (set (match_operand:DI 0 "register_operand" "=d")
5910 (neg:DI (sign_extend:DI (match_dup 1))))]
5911 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5913 [(set_attr "op_type" "RRE")])
5915 (define_insn "*negdi2_sign"
5916 [(set (match_operand:DI 0 "register_operand" "=d")
5917 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5918 (clobber (reg:CC CC_REGNUM))]
5921 [(set_attr "op_type" "RRE")])
5924 (define_insn "*neg<mode>2_cc"
5925 [(set (reg CC_REGNUM)
5926 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5928 (set (match_operand:GPR 0 "register_operand" "=d")
5929 (neg:GPR (match_dup 1)))]
5930 "s390_match_ccmode (insn, CCAmode)"
5932 [(set_attr "op_type" "RR<E>")])
5935 (define_insn "*neg<mode>2_cconly"
5936 [(set (reg CC_REGNUM)
5937 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5939 (clobber (match_scratch:GPR 0 "=d"))]
5940 "s390_match_ccmode (insn, CCAmode)"
5942 [(set_attr "op_type" "RR<E>")])
5945 (define_insn "*neg<mode>2"
5946 [(set (match_operand:GPR 0 "register_operand" "=d")
5947 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5948 (clobber (reg:CC CC_REGNUM))]
5951 [(set_attr "op_type" "RR<E>")])
5953 (define_insn_and_split "*negdi2_31"
5954 [(set (match_operand:DI 0 "register_operand" "=d")
5955 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5956 (clobber (reg:CC CC_REGNUM))]
5959 "&& reload_completed"
5961 [(set (match_dup 2) (neg:SI (match_dup 3)))
5962 (clobber (reg:CC CC_REGNUM))])
5964 [(set (reg:CCAP CC_REGNUM)
5965 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5966 (set (match_dup 4) (neg:SI (match_dup 5)))])
5968 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
5970 (label_ref (match_dup 6))))
5972 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5973 (clobber (reg:CC CC_REGNUM))])
5975 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5976 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5977 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5978 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5979 operands[6] = gen_label_rtx ();")
5982 ; neg(df|sf)2 instruction pattern(s).
5985 (define_expand "neg<mode>2"
5987 [(set (match_operand:BFP 0 "register_operand" "=f")
5988 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
5989 (clobber (reg:CC CC_REGNUM))])]
5993 ; lcxbr, lcdbr, lcebr
5994 (define_insn "*neg<mode>2_cc"
5995 [(set (reg CC_REGNUM)
5996 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
5997 (match_operand:BFP 2 "const0_operand" "")))
5998 (set (match_operand:BFP 0 "register_operand" "=f")
5999 (neg:BFP (match_dup 1)))]
6000 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6002 [(set_attr "op_type" "RRE")
6003 (set_attr "type" "fsimp<mode>")])
6005 ; lcxbr, lcdbr, lcebr
6006 (define_insn "*neg<mode>2_cconly"
6007 [(set (reg CC_REGNUM)
6008 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
6009 (match_operand:BFP 2 "const0_operand" "")))
6010 (clobber (match_scratch:BFP 0 "=f"))]
6011 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6013 [(set_attr "op_type" "RRE")
6014 (set_attr "type" "fsimp<mode>")])
6017 (define_insn "*neg<mode>2_nocc"
6018 [(set (match_operand:FP 0 "register_operand" "=f")
6019 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6020 "TARGET_HARD_FLOAT && TARGET_DFP"
6022 [(set_attr "op_type" "RRE")
6023 (set_attr "type" "fsimp<bfp>")])
6025 ; lcxbr, lcdbr, lcebr
6026 (define_insn "*neg<mode>2"
6027 [(set (match_operand:BFP 0 "register_operand" "=f")
6028 (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
6029 (clobber (reg:CC CC_REGNUM))]
6032 [(set_attr "op_type" "RRE")
6033 (set_attr "type" "fsimp<mode>")])
6037 ;;- Absolute value instructions.
6041 ; abs(di|si)2 instruction pattern(s).
6044 (define_insn "*absdi2_sign_cc"
6045 [(set (reg CC_REGNUM)
6046 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6047 (match_operand:SI 1 "register_operand" "d") 0)
6048 (const_int 32)) (const_int 32)))
6050 (set (match_operand:DI 0 "register_operand" "=d")
6051 (abs:DI (sign_extend:DI (match_dup 1))))]
6052 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6054 [(set_attr "op_type" "RRE")])
6056 (define_insn "*absdi2_sign"
6057 [(set (match_operand:DI 0 "register_operand" "=d")
6058 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6059 (clobber (reg:CC CC_REGNUM))]
6062 [(set_attr "op_type" "RRE")])
6065 (define_insn "*abs<mode>2_cc"
6066 [(set (reg CC_REGNUM)
6067 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
6069 (set (match_operand:GPR 0 "register_operand" "=d")
6070 (abs:GPR (match_dup 1)))]
6071 "s390_match_ccmode (insn, CCAmode)"
6073 [(set_attr "op_type" "RR<E>")])
6076 (define_insn "*abs<mode>2_cconly"
6077 [(set (reg CC_REGNUM)
6078 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
6080 (clobber (match_scratch:GPR 0 "=d"))]
6081 "s390_match_ccmode (insn, CCAmode)"
6083 [(set_attr "op_type" "RR<E>")])
6086 (define_insn "abs<mode>2"
6087 [(set (match_operand:GPR 0 "register_operand" "=d")
6088 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6089 (clobber (reg:CC CC_REGNUM))]
6092 [(set_attr "op_type" "RR<E>")])
6095 ; abs(df|sf)2 instruction pattern(s).
6098 (define_expand "abs<mode>2"
6100 [(set (match_operand:BFP 0 "register_operand" "=f")
6101 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6102 (clobber (reg:CC CC_REGNUM))])]
6106 ; lpxbr, lpdbr, lpebr
6107 (define_insn "*abs<mode>2_cc"
6108 [(set (reg CC_REGNUM)
6109 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6110 (match_operand:BFP 2 "const0_operand" "")))
6111 (set (match_operand:BFP 0 "register_operand" "=f")
6112 (abs:BFP (match_dup 1)))]
6113 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6115 [(set_attr "op_type" "RRE")
6116 (set_attr "type" "fsimp<mode>")])
6118 ; lpxbr, lpdbr, lpebr
6119 (define_insn "*abs<mode>2_cconly"
6120 [(set (reg CC_REGNUM)
6121 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
6122 (match_operand:BFP 2 "const0_operand" "")))
6123 (clobber (match_scratch:BFP 0 "=f"))]
6124 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6126 [(set_attr "op_type" "RRE")
6127 (set_attr "type" "fsimp<mode>")])
6130 (define_insn "*abs<mode>2_nocc"
6131 [(set (match_operand:FP 0 "register_operand" "=f")
6132 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))]
6133 "TARGET_HARD_FLOAT && TARGET_DFP"
6135 [(set_attr "op_type" "RRE")
6136 (set_attr "type" "fsimp<bfp>")])
6138 ; lpxbr, lpdbr, lpebr
6139 (define_insn "*abs<mode>2"
6140 [(set (match_operand:BFP 0 "register_operand" "=f")
6141 (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6142 (clobber (reg:CC CC_REGNUM))]
6145 [(set_attr "op_type" "RRE")
6146 (set_attr "type" "fsimp<mode>")])
6150 ;;- Negated absolute value instructions
6157 (define_insn "*negabsdi2_sign_cc"
6158 [(set (reg CC_REGNUM)
6159 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6160 (match_operand:SI 1 "register_operand" "d") 0)
6161 (const_int 32)) (const_int 32))))
6163 (set (match_operand:DI 0 "register_operand" "=d")
6164 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6165 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6167 [(set_attr "op_type" "RRE")])
6169 (define_insn "*negabsdi2_sign"
6170 [(set (match_operand:DI 0 "register_operand" "=d")
6171 (neg:DI (abs:DI (sign_extend:DI
6172 (match_operand:SI 1 "register_operand" "d")))))
6173 (clobber (reg:CC CC_REGNUM))]
6176 [(set_attr "op_type" "RRE")])
6179 (define_insn "*negabs<mode>2_cc"
6180 [(set (reg CC_REGNUM)
6181 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6183 (set (match_operand:GPR 0 "register_operand" "=d")
6184 (neg:GPR (abs:GPR (match_dup 1))))]
6185 "s390_match_ccmode (insn, CCAmode)"
6187 [(set_attr "op_type" "RR<E>")])
6190 (define_insn "*negabs<mode>2_cconly"
6191 [(set (reg CC_REGNUM)
6192 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6194 (clobber (match_scratch:GPR 0 "=d"))]
6195 "s390_match_ccmode (insn, CCAmode)"
6197 [(set_attr "op_type" "RR<E>")])
6200 (define_insn "*negabs<mode>2"
6201 [(set (match_operand:GPR 0 "register_operand" "=d")
6202 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
6203 (clobber (reg:CC CC_REGNUM))]
6206 [(set_attr "op_type" "RR<E>")])
6212 ; lnxbr, lndbr, lnebr
6213 (define_insn "*negabs<mode>2_cc"
6214 [(set (reg CC_REGNUM)
6215 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6216 (match_operand:BFP 2 "const0_operand" "")))
6217 (set (match_operand:BFP 0 "register_operand" "=f")
6218 (neg:BFP (abs:BFP (match_dup 1))))]
6219 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6221 [(set_attr "op_type" "RRE")
6222 (set_attr "type" "fsimp<mode>")])
6224 ; lnxbr, lndbr, lnebr
6225 (define_insn "*negabs<mode>2_cconly"
6226 [(set (reg CC_REGNUM)
6227 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
6228 (match_operand:BFP 2 "const0_operand" "")))
6229 (clobber (match_scratch:BFP 0 "=f"))]
6230 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
6232 [(set_attr "op_type" "RRE")
6233 (set_attr "type" "fsimp<mode>")])
6236 (define_insn "*negabs<mode>2_nocc"
6237 [(set (match_operand:FP 0 "register_operand" "=f")
6238 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
6239 "TARGET_HARD_FLOAT && TARGET_DFP"
6241 [(set_attr "op_type" "RRE")
6242 (set_attr "type" "fsimp<bfp>")])
6244 ; lnxbr, lndbr, lnebr
6245 (define_insn "*negabs<mode>2"
6246 [(set (match_operand:BFP 0 "register_operand" "=f")
6247 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
6248 (clobber (reg:CC CC_REGNUM))]
6251 [(set_attr "op_type" "RRE")
6252 (set_attr "type" "fsimp<mode>")])
6255 ;;- Copy sign instructions
6259 (define_insn "copysign<mode>3"
6260 [(set (match_operand:FP 0 "register_operand" "=f")
6261 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
6262 (match_operand:FP 2 "register_operand" "f")]
6264 "TARGET_HARD_FLOAT && TARGET_DFP"
6266 [(set_attr "op_type" "RRF")
6267 (set_attr "type" "fsimp<bfp>")])
6270 ;;- Square root instructions.
6274 ; sqrt(df|sf)2 instruction pattern(s).
6277 ; sqxbr, sqdbr, sqebr, sqxb, sqdb, sqeb
6278 (define_insn "sqrt<mode>2"
6279 [(set (match_operand:BFP 0 "register_operand" "=f,f")
6280 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
6285 [(set_attr "op_type" "RRE,RXE")
6286 (set_attr "type" "fsqrt<mode>")])
6290 ;;- One complement instructions.
6294 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
6297 (define_expand "one_cmpl<mode>2"
6299 [(set (match_operand:INT 0 "register_operand" "")
6300 (xor:INT (match_operand:INT 1 "register_operand" "")
6302 (clobber (reg:CC CC_REGNUM))])]
6308 ;; Find leftmost bit instructions.
6311 (define_expand "clzdi2"
6312 [(set (match_operand:DI 0 "register_operand" "=d")
6313 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
6314 "TARGET_EXTIMM && TARGET_64BIT"
6316 rtx insn, clz_equal;
6317 rtx wide_reg = gen_reg_rtx (TImode);
6318 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
6320 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
6322 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
6324 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
6325 set_unique_reg_note (insn, REG_EQUAL, clz_equal);
6330 (define_insn "clztidi2"
6331 [(set (match_operand:TI 0 "register_operand" "=d")
6335 (xor:DI (match_operand:DI 1 "register_operand" "d")
6336 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
6337 (subreg:SI (clz:DI (match_dup 1)) 4))))
6340 (zero_extend:TI (clz:DI (match_dup 1)))))
6341 (clobber (reg:CC CC_REGNUM))]
6342 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
6343 == (unsigned HOST_WIDE_INT) 1 << 63
6344 && TARGET_EXTIMM && TARGET_64BIT"
6346 [(set_attr "op_type" "RRE")])
6350 ;;- Rotate instructions.
6354 ; rotl(di|si)3 instruction pattern(s).
6358 (define_insn "rotl<mode>3"
6359 [(set (match_operand:GPR 0 "register_operand" "=d")
6360 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6361 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6364 [(set_attr "op_type" "RSE")
6365 (set_attr "atype" "reg")])
6368 (define_insn "*rotl<mode>3_and"
6369 [(set (match_operand:GPR 0 "register_operand" "=d")
6370 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6371 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6372 (match_operand:SI 3 "const_int_operand" "n"))))]
6373 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
6375 [(set_attr "op_type" "RSE")
6376 (set_attr "atype" "reg")])
6380 ;;- Shift instructions.
6384 ; (ashl|lshr)(di|si)3 instruction pattern(s).
6387 (define_expand "<shift><mode>3"
6388 [(set (match_operand:DSI 0 "register_operand" "")
6389 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
6390 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
6395 (define_insn "*<shift>di3_31"
6396 [(set (match_operand:DI 0 "register_operand" "=d")
6397 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6398 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6401 [(set_attr "op_type" "RS")
6402 (set_attr "atype" "reg")])
6404 ; sll, srl, sllg, srlg
6405 (define_insn "*<shift><mode>3"
6406 [(set (match_operand:GPR 0 "register_operand" "=d")
6407 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6408 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6410 "s<lr>l<g>\t%0,<1>%Y2"
6411 [(set_attr "op_type" "RS<E>")
6412 (set_attr "atype" "reg")])
6415 (define_insn "*<shift>di3_31_and"
6416 [(set (match_operand:DI 0 "register_operand" "=d")
6417 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6418 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6419 (match_operand:SI 3 "const_int_operand" "n"))))]
6420 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6422 [(set_attr "op_type" "RS")
6423 (set_attr "atype" "reg")])
6425 ; sll, srl, sllg, srlg
6426 (define_insn "*<shift><mode>3_and"
6427 [(set (match_operand:GPR 0 "register_operand" "=d")
6428 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6429 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6430 (match_operand:SI 3 "const_int_operand" "n"))))]
6431 "(INTVAL (operands[3]) & 63) == 63"
6432 "s<lr>l<g>\t%0,<1>%Y2"
6433 [(set_attr "op_type" "RS<E>")
6434 (set_attr "atype" "reg")])
6437 ; ashr(di|si)3 instruction pattern(s).
6440 (define_expand "ashr<mode>3"
6442 [(set (match_operand:DSI 0 "register_operand" "")
6443 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
6444 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
6445 (clobber (reg:CC CC_REGNUM))])]
6449 (define_insn "*ashrdi3_cc_31"
6450 [(set (reg CC_REGNUM)
6451 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6452 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6454 (set (match_operand:DI 0 "register_operand" "=d")
6455 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6456 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6458 [(set_attr "op_type" "RS")
6459 (set_attr "atype" "reg")])
6461 (define_insn "*ashrdi3_cconly_31"
6462 [(set (reg CC_REGNUM)
6463 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6464 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6466 (clobber (match_scratch:DI 0 "=d"))]
6467 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6469 [(set_attr "op_type" "RS")
6470 (set_attr "atype" "reg")])
6472 (define_insn "*ashrdi3_31"
6473 [(set (match_operand:DI 0 "register_operand" "=d")
6474 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6475 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6476 (clobber (reg:CC CC_REGNUM))]
6479 [(set_attr "op_type" "RS")
6480 (set_attr "atype" "reg")])
6483 (define_insn "*ashr<mode>3_cc"
6484 [(set (reg CC_REGNUM)
6485 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6486 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6488 (set (match_operand:GPR 0 "register_operand" "=d")
6489 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
6490 "s390_match_ccmode(insn, CCSmode)"
6492 [(set_attr "op_type" "RS<E>")
6493 (set_attr "atype" "reg")])
6496 (define_insn "*ashr<mode>3_cconly"
6497 [(set (reg CC_REGNUM)
6498 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6499 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6501 (clobber (match_scratch:GPR 0 "=d"))]
6502 "s390_match_ccmode(insn, CCSmode)"
6504 [(set_attr "op_type" "RS<E>")
6505 (set_attr "atype" "reg")])
6508 (define_insn "*ashr<mode>3"
6509 [(set (match_operand:GPR 0 "register_operand" "=d")
6510 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6511 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6512 (clobber (reg:CC CC_REGNUM))]
6515 [(set_attr "op_type" "RS<E>")
6516 (set_attr "atype" "reg")])
6519 ; shift pattern with implicit ANDs
6521 (define_insn "*ashrdi3_cc_31_and"
6522 [(set (reg CC_REGNUM)
6523 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6524 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6525 (match_operand:SI 3 "const_int_operand" "n")))
6527 (set (match_operand:DI 0 "register_operand" "=d")
6528 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6529 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6530 && (INTVAL (operands[3]) & 63) == 63"
6532 [(set_attr "op_type" "RS")
6533 (set_attr "atype" "reg")])
6535 (define_insn "*ashrdi3_cconly_31_and"
6536 [(set (reg CC_REGNUM)
6537 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6538 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6539 (match_operand:SI 3 "const_int_operand" "n")))
6541 (clobber (match_scratch:DI 0 "=d"))]
6542 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6543 && (INTVAL (operands[3]) & 63) == 63"
6545 [(set_attr "op_type" "RS")
6546 (set_attr "atype" "reg")])
6548 (define_insn "*ashrdi3_31_and"
6549 [(set (match_operand:DI 0 "register_operand" "=d")
6550 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6551 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6552 (match_operand:SI 3 "const_int_operand" "n"))))
6553 (clobber (reg:CC CC_REGNUM))]
6554 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6556 [(set_attr "op_type" "RS")
6557 (set_attr "atype" "reg")])
6560 (define_insn "*ashr<mode>3_cc_and"
6561 [(set (reg CC_REGNUM)
6562 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6563 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6564 (match_operand:SI 3 "const_int_operand" "n")))
6566 (set (match_operand:GPR 0 "register_operand" "=d")
6567 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6568 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
6570 [(set_attr "op_type" "RS<E>")
6571 (set_attr "atype" "reg")])
6574 (define_insn "*ashr<mode>3_cconly_and"
6575 [(set (reg CC_REGNUM)
6576 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6577 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6578 (match_operand:SI 3 "const_int_operand" "n")))
6580 (clobber (match_scratch:GPR 0 "=d"))]
6581 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
6583 [(set_attr "op_type" "RS<E>")
6584 (set_attr "atype" "reg")])
6587 (define_insn "*ashr<mode>3_and"
6588 [(set (match_operand:GPR 0 "register_operand" "=d")
6589 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6590 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6591 (match_operand:SI 3 "const_int_operand" "n"))))
6592 (clobber (reg:CC CC_REGNUM))]
6593 "(INTVAL (operands[3]) & 63) == 63"
6595 [(set_attr "op_type" "RS<E>")
6596 (set_attr "atype" "reg")])
6600 ;; Branch instruction patterns.
6603 (define_expand "b<code>"
6605 (if_then_else (COMPARE (match_operand 0 "" "")
6610 "s390_emit_jump (operands[0],
6611 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
6615 ;;- Conditional jump instructions.
6618 (define_insn "*cjump_64"
6621 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6622 (label_ref (match_operand 0 "" ""))
6626 if (get_attr_length (insn) == 4)
6629 return "jg%C1\t%l0";
6631 [(set_attr "op_type" "RI")
6632 (set_attr "type" "branch")
6633 (set (attr "length")
6634 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6635 (const_int 4) (const_int 6)))])
6637 (define_insn "*cjump_31"
6640 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6641 (label_ref (match_operand 0 "" ""))
6645 gcc_assert (get_attr_length (insn) == 4);
6648 [(set_attr "op_type" "RI")
6649 (set_attr "type" "branch")
6650 (set (attr "length")
6651 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6652 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6653 (const_int 4) (const_int 6))
6654 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6655 (const_int 4) (const_int 8))))])
6657 (define_insn "*cjump_long"
6660 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6661 (match_operand 0 "address_operand" "U")
6665 if (get_attr_op_type (insn) == OP_TYPE_RR)
6670 [(set (attr "op_type")
6671 (if_then_else (match_operand 0 "register_operand" "")
6672 (const_string "RR") (const_string "RX")))
6673 (set_attr "type" "branch")
6674 (set_attr "atype" "agen")])
6678 ;;- Negated conditional jump instructions.
6681 (define_insn "*icjump_64"
6684 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6686 (label_ref (match_operand 0 "" ""))))]
6689 if (get_attr_length (insn) == 4)
6692 return "jg%D1\t%l0";
6694 [(set_attr "op_type" "RI")
6695 (set_attr "type" "branch")
6696 (set (attr "length")
6697 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6698 (const_int 4) (const_int 6)))])
6700 (define_insn "*icjump_31"
6703 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6705 (label_ref (match_operand 0 "" ""))))]
6708 gcc_assert (get_attr_length (insn) == 4);
6711 [(set_attr "op_type" "RI")
6712 (set_attr "type" "branch")
6713 (set (attr "length")
6714 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6715 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6716 (const_int 4) (const_int 6))
6717 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6718 (const_int 4) (const_int 8))))])
6720 (define_insn "*icjump_long"
6723 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6725 (match_operand 0 "address_operand" "U")))]
6728 if (get_attr_op_type (insn) == OP_TYPE_RR)
6733 [(set (attr "op_type")
6734 (if_then_else (match_operand 0 "register_operand" "")
6735 (const_string "RR") (const_string "RX")))
6736 (set_attr "type" "branch")
6737 (set_attr "atype" "agen")])
6740 ;;- Trap instructions.
6744 [(trap_if (const_int 1) (const_int 0))]
6747 [(set_attr "op_type" "RI")
6748 (set_attr "type" "branch")])
6750 (define_expand "conditional_trap"
6751 [(trap_if (match_operand 0 "comparison_operator" "")
6752 (match_operand 1 "general_operand" ""))]
6755 if (operands[1] != const0_rtx) FAIL;
6756 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6757 s390_compare_op0, s390_compare_op1);
6760 (define_insn "*trap"
6761 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6765 [(set_attr "op_type" "RI")
6766 (set_attr "type" "branch")])
6769 ;;- Loop instructions.
6771 ;; This is all complicated by the fact that since this is a jump insn
6772 ;; we must handle our own output reloads.
6774 (define_expand "doloop_end"
6775 [(use (match_operand 0 "" "")) ; loop pseudo
6776 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6777 (use (match_operand 2 "" "")) ; max iterations
6778 (use (match_operand 3 "" "")) ; loop level
6779 (use (match_operand 4 "" ""))] ; label
6782 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6783 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6784 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6785 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6786 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6787 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6794 (define_insn_and_split "doloop_si64"
6797 (ne (match_operand:SI 1 "register_operand" "d,d,d")
6799 (label_ref (match_operand 0 "" ""))
6801 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
6802 (plus:SI (match_dup 1) (const_int -1)))
6803 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
6804 (clobber (reg:CC CC_REGNUM))]
6807 if (which_alternative != 0)
6809 else if (get_attr_length (insn) == 4)
6810 return "brct\t%1,%l0";
6812 return "ahi\t%1,-1\;jgne\t%l0";
6814 "&& reload_completed
6815 && (! REG_P (operands[2])
6816 || ! rtx_equal_p (operands[1], operands[2]))"
6817 [(set (match_dup 3) (match_dup 1))
6818 (parallel [(set (reg:CCAN CC_REGNUM)
6819 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6821 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6822 (set (match_dup 2) (match_dup 3))
6823 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6824 (label_ref (match_dup 0))
6827 [(set_attr "op_type" "RI")
6828 (set_attr "type" "branch")
6829 (set (attr "length")
6830 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6831 (const_int 4) (const_int 10)))])
6833 (define_insn_and_split "doloop_si31"
6836 (ne (match_operand:SI 1 "register_operand" "d,d,d")
6838 (label_ref (match_operand 0 "" ""))
6840 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
6841 (plus:SI (match_dup 1) (const_int -1)))
6842 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
6843 (clobber (reg:CC CC_REGNUM))]
6846 if (which_alternative != 0)
6848 else if (get_attr_length (insn) == 4)
6849 return "brct\t%1,%l0";
6853 "&& reload_completed
6854 && (! REG_P (operands[2])
6855 || ! rtx_equal_p (operands[1], operands[2]))"
6856 [(set (match_dup 3) (match_dup 1))
6857 (parallel [(set (reg:CCAN CC_REGNUM)
6858 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6860 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6861 (set (match_dup 2) (match_dup 3))
6862 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6863 (label_ref (match_dup 0))
6866 [(set_attr "op_type" "RI")
6867 (set_attr "type" "branch")
6868 (set (attr "length")
6869 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6870 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6871 (const_int 4) (const_int 6))
6872 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6873 (const_int 4) (const_int 8))))])
6875 (define_insn "*doloop_si_long"
6878 (ne (match_operand:SI 1 "register_operand" "d")
6880 (match_operand 0 "address_operand" "U")
6882 (set (match_operand:SI 2 "register_operand" "=1")
6883 (plus:SI (match_dup 1) (const_int -1)))
6884 (clobber (match_scratch:SI 3 "=X"))
6885 (clobber (reg:CC CC_REGNUM))]
6888 if (get_attr_op_type (insn) == OP_TYPE_RR)
6889 return "bctr\t%1,%0";
6891 return "bct\t%1,%a0";
6893 [(set (attr "op_type")
6894 (if_then_else (match_operand 0 "register_operand" "")
6895 (const_string "RR") (const_string "RX")))
6896 (set_attr "type" "branch")
6897 (set_attr "atype" "agen")])
6899 (define_insn_and_split "doloop_di"
6902 (ne (match_operand:DI 1 "register_operand" "d,d,d")
6904 (label_ref (match_operand 0 "" ""))
6906 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
6907 (plus:DI (match_dup 1) (const_int -1)))
6908 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
6909 (clobber (reg:CC CC_REGNUM))]
6912 if (which_alternative != 0)
6914 else if (get_attr_length (insn) == 4)
6915 return "brctg\t%1,%l0";
6917 return "aghi\t%1,-1\;jgne\t%l0";
6919 "&& reload_completed
6920 && (! REG_P (operands[2])
6921 || ! rtx_equal_p (operands[1], operands[2]))"
6922 [(set (match_dup 3) (match_dup 1))
6923 (parallel [(set (reg:CCAN CC_REGNUM)
6924 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6926 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6927 (set (match_dup 2) (match_dup 3))
6928 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6929 (label_ref (match_dup 0))
6932 [(set_attr "op_type" "RI")
6933 (set_attr "type" "branch")
6934 (set (attr "length")
6935 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6936 (const_int 4) (const_int 10)))])
6939 ;;- Unconditional jump instructions.
6943 ; jump instruction pattern(s).
6946 (define_expand "jump"
6947 [(match_operand 0 "" "")]
6949 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6951 (define_insn "*jump64"
6952 [(set (pc) (label_ref (match_operand 0 "" "")))]
6955 if (get_attr_length (insn) == 4)
6960 [(set_attr "op_type" "RI")
6961 (set_attr "type" "branch")
6962 (set (attr "length")
6963 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6964 (const_int 4) (const_int 6)))])
6966 (define_insn "*jump31"
6967 [(set (pc) (label_ref (match_operand 0 "" "")))]
6970 gcc_assert (get_attr_length (insn) == 4);
6973 [(set_attr "op_type" "RI")
6974 (set_attr "type" "branch")
6975 (set (attr "length")
6976 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6977 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6978 (const_int 4) (const_int 6))
6979 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6980 (const_int 4) (const_int 8))))])
6983 ; indirect-jump instruction pattern(s).
6986 (define_insn "indirect_jump"
6987 [(set (pc) (match_operand 0 "address_operand" "U"))]
6990 if (get_attr_op_type (insn) == OP_TYPE_RR)
6995 [(set (attr "op_type")
6996 (if_then_else (match_operand 0 "register_operand" "")
6997 (const_string "RR") (const_string "RX")))
6998 (set_attr "type" "branch")
6999 (set_attr "atype" "agen")])
7002 ; casesi instruction pattern(s).
7005 (define_insn "casesi_jump"
7006 [(set (pc) (match_operand 0 "address_operand" "U"))
7007 (use (label_ref (match_operand 1 "" "")))]
7010 if (get_attr_op_type (insn) == OP_TYPE_RR)
7015 [(set (attr "op_type")
7016 (if_then_else (match_operand 0 "register_operand" "")
7017 (const_string "RR") (const_string "RX")))
7018 (set_attr "type" "branch")
7019 (set_attr "atype" "agen")])
7021 (define_expand "casesi"
7022 [(match_operand:SI 0 "general_operand" "")
7023 (match_operand:SI 1 "general_operand" "")
7024 (match_operand:SI 2 "general_operand" "")
7025 (label_ref (match_operand 3 "" ""))
7026 (label_ref (match_operand 4 "" ""))]
7029 rtx index = gen_reg_rtx (SImode);
7030 rtx base = gen_reg_rtx (Pmode);
7031 rtx target = gen_reg_rtx (Pmode);
7033 emit_move_insn (index, operands[0]);
7034 emit_insn (gen_subsi3 (index, index, operands[1]));
7035 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
7038 if (Pmode != SImode)
7039 index = convert_to_mode (Pmode, index, 1);
7040 if (GET_CODE (index) != REG)
7041 index = copy_to_mode_reg (Pmode, index);
7044 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
7046 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
7048 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
7050 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
7051 emit_move_insn (target, index);
7054 target = gen_rtx_PLUS (Pmode, base, target);
7055 emit_jump_insn (gen_casesi_jump (target, operands[3]));
7062 ;;- Jump to subroutine.
7067 ; untyped call instruction pattern(s).
7070 ;; Call subroutine returning any type.
7071 (define_expand "untyped_call"
7072 [(parallel [(call (match_operand 0 "" "")
7074 (match_operand 1 "" "")
7075 (match_operand 2 "" "")])]
7080 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7082 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7084 rtx set = XVECEXP (operands[2], 0, i);
7085 emit_move_insn (SET_DEST (set), SET_SRC (set));
7088 /* The optimizer does not know that the call sets the function value
7089 registers we stored in the result block. We avoid problems by
7090 claiming that all hard registers are used and clobbered at this
7092 emit_insn (gen_blockage ());
7097 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7098 ;; all of memory. This blocks insns from being moved across this point.
7100 (define_insn "blockage"
7101 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7104 [(set_attr "type" "none")
7105 (set_attr "length" "0")])
7111 (define_expand "sibcall"
7112 [(call (match_operand 0 "" "")
7113 (match_operand 1 "" ""))]
7116 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
7120 (define_insn "*sibcall_br"
7121 [(call (mem:QI (reg SIBCALL_REGNUM))
7122 (match_operand 0 "const_int_operand" "n"))]
7123 "SIBLING_CALL_P (insn)
7124 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
7126 [(set_attr "op_type" "RR")
7127 (set_attr "type" "branch")
7128 (set_attr "atype" "agen")])
7130 (define_insn "*sibcall_brc"
7131 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7132 (match_operand 1 "const_int_operand" "n"))]
7133 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7135 [(set_attr "op_type" "RI")
7136 (set_attr "type" "branch")])
7138 (define_insn "*sibcall_brcl"
7139 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7140 (match_operand 1 "const_int_operand" "n"))]
7141 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7143 [(set_attr "op_type" "RIL")
7144 (set_attr "type" "branch")])
7147 ; sibcall_value patterns
7150 (define_expand "sibcall_value"
7151 [(set (match_operand 0 "" "")
7152 (call (match_operand 1 "" "")
7153 (match_operand 2 "" "")))]
7156 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
7160 (define_insn "*sibcall_value_br"
7161 [(set (match_operand 0 "" "")
7162 (call (mem:QI (reg SIBCALL_REGNUM))
7163 (match_operand 1 "const_int_operand" "n")))]
7164 "SIBLING_CALL_P (insn)
7165 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
7167 [(set_attr "op_type" "RR")
7168 (set_attr "type" "branch")
7169 (set_attr "atype" "agen")])
7171 (define_insn "*sibcall_value_brc"
7172 [(set (match_operand 0 "" "")
7173 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7174 (match_operand 2 "const_int_operand" "n")))]
7175 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7177 [(set_attr "op_type" "RI")
7178 (set_attr "type" "branch")])
7180 (define_insn "*sibcall_value_brcl"
7181 [(set (match_operand 0 "" "")
7182 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7183 (match_operand 2 "const_int_operand" "n")))]
7184 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7186 [(set_attr "op_type" "RIL")
7187 (set_attr "type" "branch")])
7191 ; call instruction pattern(s).
7194 (define_expand "call"
7195 [(call (match_operand 0 "" "")
7196 (match_operand 1 "" ""))
7197 (use (match_operand 2 "" ""))]
7200 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
7201 gen_rtx_REG (Pmode, RETURN_REGNUM));
7205 (define_insn "*bras"
7206 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7207 (match_operand 1 "const_int_operand" "n"))
7208 (clobber (match_operand 2 "register_operand" "=r"))]
7209 "!SIBLING_CALL_P (insn)
7210 && TARGET_SMALL_EXEC
7211 && GET_MODE (operands[2]) == Pmode"
7213 [(set_attr "op_type" "RI")
7214 (set_attr "type" "jsr")])
7216 (define_insn "*brasl"
7217 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7218 (match_operand 1 "const_int_operand" "n"))
7219 (clobber (match_operand 2 "register_operand" "=r"))]
7220 "!SIBLING_CALL_P (insn)
7222 && GET_MODE (operands[2]) == Pmode"
7224 [(set_attr "op_type" "RIL")
7225 (set_attr "type" "jsr")])
7227 (define_insn "*basr"
7228 [(call (mem:QI (match_operand 0 "address_operand" "U"))
7229 (match_operand 1 "const_int_operand" "n"))
7230 (clobber (match_operand 2 "register_operand" "=r"))]
7231 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
7233 if (get_attr_op_type (insn) == OP_TYPE_RR)
7234 return "basr\t%2,%0";
7236 return "bas\t%2,%a0";
7238 [(set (attr "op_type")
7239 (if_then_else (match_operand 0 "register_operand" "")
7240 (const_string "RR") (const_string "RX")))
7241 (set_attr "type" "jsr")
7242 (set_attr "atype" "agen")])
7245 ; call_value instruction pattern(s).
7248 (define_expand "call_value"
7249 [(set (match_operand 0 "" "")
7250 (call (match_operand 1 "" "")
7251 (match_operand 2 "" "")))
7252 (use (match_operand 3 "" ""))]
7255 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
7256 gen_rtx_REG (Pmode, RETURN_REGNUM));
7260 (define_insn "*bras_r"
7261 [(set (match_operand 0 "" "")
7262 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7263 (match_operand:SI 2 "const_int_operand" "n")))
7264 (clobber (match_operand 3 "register_operand" "=r"))]
7265 "!SIBLING_CALL_P (insn)
7266 && TARGET_SMALL_EXEC
7267 && GET_MODE (operands[3]) == Pmode"
7269 [(set_attr "op_type" "RI")
7270 (set_attr "type" "jsr")])
7272 (define_insn "*brasl_r"
7273 [(set (match_operand 0 "" "")
7274 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7275 (match_operand 2 "const_int_operand" "n")))
7276 (clobber (match_operand 3 "register_operand" "=r"))]
7277 "!SIBLING_CALL_P (insn)
7279 && GET_MODE (operands[3]) == Pmode"
7281 [(set_attr "op_type" "RIL")
7282 (set_attr "type" "jsr")])
7284 (define_insn "*basr_r"
7285 [(set (match_operand 0 "" "")
7286 (call (mem:QI (match_operand 1 "address_operand" "U"))
7287 (match_operand 2 "const_int_operand" "n")))
7288 (clobber (match_operand 3 "register_operand" "=r"))]
7289 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7291 if (get_attr_op_type (insn) == OP_TYPE_RR)
7292 return "basr\t%3,%1";
7294 return "bas\t%3,%a1";
7296 [(set (attr "op_type")
7297 (if_then_else (match_operand 1 "register_operand" "")
7298 (const_string "RR") (const_string "RX")))
7299 (set_attr "type" "jsr")
7300 (set_attr "atype" "agen")])
7303 ;;- Thread-local storage support.
7306 (define_expand "get_tp_64"
7307 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
7311 (define_expand "get_tp_31"
7312 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
7316 (define_expand "set_tp_64"
7317 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
7318 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
7322 (define_expand "set_tp_31"
7323 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
7324 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
7328 (define_insn "*set_tp"
7329 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
7332 [(set_attr "type" "none")
7333 (set_attr "length" "0")])
7335 (define_insn "*tls_load_64"
7336 [(set (match_operand:DI 0 "register_operand" "=d")
7337 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
7338 (match_operand:DI 2 "" "")]
7342 [(set_attr "op_type" "RXE")])
7344 (define_insn "*tls_load_31"
7345 [(set (match_operand:SI 0 "register_operand" "=d,d")
7346 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
7347 (match_operand:SI 2 "" "")]
7353 [(set_attr "op_type" "RX,RXY")])
7355 (define_insn "*bras_tls"
7356 [(set (match_operand 0 "" "")
7357 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7358 (match_operand 2 "const_int_operand" "n")))
7359 (clobber (match_operand 3 "register_operand" "=r"))
7360 (use (match_operand 4 "" ""))]
7361 "!SIBLING_CALL_P (insn)
7362 && TARGET_SMALL_EXEC
7363 && GET_MODE (operands[3]) == Pmode"
7365 [(set_attr "op_type" "RI")
7366 (set_attr "type" "jsr")])
7368 (define_insn "*brasl_tls"
7369 [(set (match_operand 0 "" "")
7370 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7371 (match_operand 2 "const_int_operand" "n")))
7372 (clobber (match_operand 3 "register_operand" "=r"))
7373 (use (match_operand 4 "" ""))]
7374 "!SIBLING_CALL_P (insn)
7376 && GET_MODE (operands[3]) == Pmode"
7378 [(set_attr "op_type" "RIL")
7379 (set_attr "type" "jsr")])
7381 (define_insn "*basr_tls"
7382 [(set (match_operand 0 "" "")
7383 (call (mem:QI (match_operand 1 "address_operand" "U"))
7384 (match_operand 2 "const_int_operand" "n")))
7385 (clobber (match_operand 3 "register_operand" "=r"))
7386 (use (match_operand 4 "" ""))]
7387 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7389 if (get_attr_op_type (insn) == OP_TYPE_RR)
7390 return "basr\t%3,%1%J4";
7392 return "bas\t%3,%a1%J4";
7394 [(set (attr "op_type")
7395 (if_then_else (match_operand 1 "register_operand" "")
7396 (const_string "RR") (const_string "RX")))
7397 (set_attr "type" "jsr")
7398 (set_attr "atype" "agen")])
7401 ;;- Atomic operations
7405 ; memory barrier pattern.
7408 (define_expand "memory_barrier"
7409 [(set (mem:BLK (match_dup 0))
7410 (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
7413 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
7414 MEM_VOLATILE_P (operands[0]) = 1;
7417 (define_insn "*memory_barrier"
7418 [(set (match_operand:BLK 0 "" "")
7419 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
7422 [(set_attr "op_type" "RR")])
7425 ; compare and swap patterns.
7428 (define_expand "sync_compare_and_swap<mode>"
7430 [(set (match_operand:TDSI 0 "register_operand" "")
7431 (match_operand:TDSI 1 "memory_operand" ""))
7433 (unspec_volatile:TDSI
7435 (match_operand:TDSI 2 "register_operand" "")
7436 (match_operand:TDSI 3 "register_operand" "")]
7438 (set (reg:CCZ1 CC_REGNUM)
7439 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7442 (define_expand "sync_compare_and_swap<mode>"
7444 [(set (match_operand:HQI 0 "register_operand" "")
7445 (match_operand:HQI 1 "memory_operand" ""))
7447 (unspec_volatile:HQI
7449 (match_operand:HQI 2 "general_operand" "")
7450 (match_operand:HQI 3 "general_operand" "")]
7452 (set (reg:CCZ1 CC_REGNUM)
7453 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7455 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
7456 operands[2], operands[3]); DONE;")
7458 (define_expand "sync_compare_and_swap_cc<mode>"
7460 [(set (match_operand:TDSI 0 "register_operand" "")
7461 (match_operand:TDSI 1 "memory_operand" ""))
7463 (unspec_volatile:TDSI
7465 (match_operand:TDSI 2 "register_operand" "")
7466 (match_operand:TDSI 3 "register_operand" "")]
7469 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7472 /* Emulate compare. */
7473 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
7474 s390_compare_op0 = operands[1];
7475 s390_compare_op1 = operands[2];
7476 s390_compare_emitted = operands[4];
7480 (define_insn "*sync_compare_and_swap<mode>"
7481 [(set (match_operand:DP 0 "register_operand" "=r")
7482 (match_operand:DP 1 "memory_operand" "+Q"))
7486 (match_operand:DP 2 "register_operand" "0")
7487 (match_operand:DP 3 "register_operand" "r")]
7489 (set (reg:CCZ1 CC_REGNUM)
7490 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7492 "cds<tg>\t%0,%3,%S1"
7493 [(set_attr "op_type" "RS<TE>")
7494 (set_attr "type" "sem")])
7497 (define_insn "*sync_compare_and_swap<mode>"
7498 [(set (match_operand:GPR 0 "register_operand" "=r")
7499 (match_operand:GPR 1 "memory_operand" "+Q"))
7501 (unspec_volatile:GPR
7503 (match_operand:GPR 2 "register_operand" "0")
7504 (match_operand:GPR 3 "register_operand" "r")]
7506 (set (reg:CCZ1 CC_REGNUM)
7507 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7510 [(set_attr "op_type" "RS<E>")
7511 (set_attr "type" "sem")])
7515 ; Other atomic instruction patterns.
7518 (define_expand "sync_lock_test_and_set<mode>"
7519 [(match_operand:HQI 0 "register_operand")
7520 (match_operand:HQI 1 "memory_operand")
7521 (match_operand:HQI 2 "general_operand")]
7523 "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
7524 operands[2], false); DONE;")
7526 (define_expand "sync_<atomic><mode>"
7527 [(set (match_operand:HQI 0 "memory_operand")
7528 (ATOMIC:HQI (match_dup 0)
7529 (match_operand:HQI 1 "general_operand")))]
7531 "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
7532 operands[1], false); DONE;")
7534 (define_expand "sync_old_<atomic><mode>"
7535 [(set (match_operand:HQI 0 "register_operand")
7536 (match_operand:HQI 1 "memory_operand"))
7538 (ATOMIC:HQI (match_dup 1)
7539 (match_operand:HQI 2 "general_operand")))]
7541 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
7542 operands[2], false); DONE;")
7544 (define_expand "sync_new_<atomic><mode>"
7545 [(set (match_operand:HQI 0 "register_operand")
7546 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
7547 (match_operand:HQI 2 "general_operand")))
7548 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
7550 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
7551 operands[2], true); DONE;")
7554 ;;- Miscellaneous instructions.
7558 ; allocate stack instruction pattern(s).
7561 (define_expand "allocate_stack"
7562 [(match_operand 0 "general_operand" "")
7563 (match_operand 1 "general_operand" "")]
7566 rtx temp = gen_reg_rtx (Pmode);
7568 emit_move_insn (temp, s390_back_chain_rtx ());
7569 anti_adjust_stack (operands[1]);
7570 emit_move_insn (s390_back_chain_rtx (), temp);
7572 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7578 ; setjmp instruction pattern.
7581 (define_expand "builtin_setjmp_receiver"
7582 [(match_operand 0 "" "")]
7585 emit_insn (s390_load_got ());
7586 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
7590 ;; These patterns say how to save and restore the stack pointer. We need not
7591 ;; save the stack pointer at function level since we are careful to
7592 ;; preserve the backchain. At block level, we have to restore the backchain
7593 ;; when we restore the stack pointer.
7595 ;; For nonlocal gotos, we must save both the stack pointer and its
7596 ;; backchain and restore both. Note that in the nonlocal case, the
7597 ;; save area is a memory location.
7599 (define_expand "save_stack_function"
7600 [(match_operand 0 "general_operand" "")
7601 (match_operand 1 "general_operand" "")]
7605 (define_expand "restore_stack_function"
7606 [(match_operand 0 "general_operand" "")
7607 (match_operand 1 "general_operand" "")]
7611 (define_expand "restore_stack_block"
7612 [(match_operand 0 "register_operand" "")
7613 (match_operand 1 "register_operand" "")]
7616 rtx temp = gen_reg_rtx (Pmode);
7618 emit_move_insn (temp, s390_back_chain_rtx ());
7619 emit_move_insn (operands[0], operands[1]);
7620 emit_move_insn (s390_back_chain_rtx (), temp);
7625 (define_expand "save_stack_nonlocal"
7626 [(match_operand 0 "memory_operand" "")
7627 (match_operand 1 "register_operand" "")]
7630 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7631 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7633 /* Copy the backchain to the first word, sp to the second and the
7634 literal pool base to the third. */
7636 if (TARGET_BACKCHAIN)
7638 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
7639 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
7642 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
7643 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
7648 (define_expand "restore_stack_nonlocal"
7649 [(match_operand 0 "register_operand" "")
7650 (match_operand 1 "memory_operand" "")]
7653 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7654 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7655 rtx temp = NULL_RTX;
7657 /* Restore the backchain from the first word, sp from the second and the
7658 literal pool base from the third. */
7660 if (TARGET_BACKCHAIN)
7661 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7663 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7664 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7667 emit_move_insn (s390_back_chain_rtx (), temp);
7669 emit_insn (gen_rtx_USE (VOIDmode, base));
7673 (define_expand "exception_receiver"
7677 s390_set_has_landing_pad_p (true);
7682 ; nop instruction pattern(s).
7689 [(set_attr "op_type" "RR")])
7693 ; Special literal pool access instruction pattern(s).
7696 (define_insn "*pool_entry"
7697 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7698 UNSPECV_POOL_ENTRY)]
7701 enum machine_mode mode = GET_MODE (PATTERN (insn));
7702 unsigned int align = GET_MODE_BITSIZE (mode);
7703 s390_output_pool_entry (operands[0], mode, align);
7706 [(set (attr "length")
7707 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7709 (define_insn "pool_align"
7710 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7711 UNSPECV_POOL_ALIGN)]
7714 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7716 (define_insn "pool_section_start"
7717 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7720 [(set_attr "length" "0")])
7722 (define_insn "pool_section_end"
7723 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
7726 [(set_attr "length" "0")])
7728 (define_insn "main_base_31_small"
7729 [(set (match_operand 0 "register_operand" "=a")
7730 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7731 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7733 [(set_attr "op_type" "RR")
7734 (set_attr "type" "la")])
7736 (define_insn "main_base_31_large"
7737 [(set (match_operand 0 "register_operand" "=a")
7738 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
7739 (set (pc) (label_ref (match_operand 2 "" "")))]
7740 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7742 [(set_attr "op_type" "RI")])
7744 (define_insn "main_base_64"
7745 [(set (match_operand 0 "register_operand" "=a")
7746 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7747 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7749 [(set_attr "op_type" "RIL")
7750 (set_attr "type" "larl")])
7752 (define_insn "main_pool"
7753 [(set (match_operand 0 "register_operand" "=a")
7754 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
7755 "GET_MODE (operands[0]) == Pmode"
7760 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
7761 (const_string "larl") (const_string "la")))])
7763 (define_insn "reload_base_31"
7764 [(set (match_operand 0 "register_operand" "=a")
7765 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7766 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7767 "basr\t%0,0\;la\t%0,%1-.(%0)"
7768 [(set_attr "length" "6")
7769 (set_attr "type" "la")])
7771 (define_insn "reload_base_64"
7772 [(set (match_operand 0 "register_operand" "=a")
7773 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7774 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7776 [(set_attr "op_type" "RIL")
7777 (set_attr "type" "larl")])
7780 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7785 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7788 ;; Insns related to generating the function prologue and epilogue.
7792 (define_expand "prologue"
7793 [(use (const_int 0))]
7795 "s390_emit_prologue (); DONE;")
7797 (define_expand "epilogue"
7798 [(use (const_int 1))]
7800 "s390_emit_epilogue (false); DONE;")
7802 (define_expand "sibcall_epilogue"
7803 [(use (const_int 0))]
7805 "s390_emit_epilogue (true); DONE;")
7807 (define_insn "*return"
7809 (use (match_operand 0 "register_operand" "a"))]
7810 "GET_MODE (operands[0]) == Pmode"
7812 [(set_attr "op_type" "RR")
7813 (set_attr "type" "jsr")
7814 (set_attr "atype" "agen")])
7817 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7818 ;; pointer. This is used for compatibility.
7820 (define_expand "ptr_extend"
7821 [(set (match_operand:DI 0 "register_operand" "=r")
7822 (match_operand:SI 1 "register_operand" "r"))]
7825 emit_insn (gen_anddi3 (operands[0],
7826 gen_lowpart (DImode, operands[1]),
7827 GEN_INT (0x7fffffff)));
7831 ;; Instruction definition to expand eh_return macro to support
7832 ;; swapping in special linkage return addresses.
7834 (define_expand "eh_return"
7835 [(use (match_operand 0 "register_operand" ""))]
7838 s390_emit_tpf_eh_return (operands[0]);
7843 ; Stack Protector Patterns
7846 (define_expand "stack_protect_set"
7847 [(set (match_operand 0 "memory_operand" "")
7848 (match_operand 1 "memory_operand" ""))]
7851 #ifdef TARGET_THREAD_SSP_OFFSET
7853 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7854 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7857 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
7859 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
7864 (define_insn "stack_protect_set<mode>"
7865 [(set (match_operand:DSI 0 "memory_operand" "=Q")
7866 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
7868 "mvc\t%O0(%G0,%R0),%S1"
7869 [(set_attr "op_type" "SS")])
7871 (define_expand "stack_protect_test"
7872 [(set (reg:CC CC_REGNUM)
7873 (compare (match_operand 0 "memory_operand" "")
7874 (match_operand 1 "memory_operand" "")))
7875 (match_operand 2 "" "")]
7878 #ifdef TARGET_THREAD_SSP_OFFSET
7880 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7881 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7883 s390_compare_op0 = operands[0];
7884 s390_compare_op1 = operands[1];
7885 s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM);
7888 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
7890 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
7892 emit_jump_insn (gen_beq (operands[2]));
7897 (define_insn "stack_protect_test<mode>"
7898 [(set (reg:CCZ CC_REGNUM)
7899 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
7900 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
7902 "clc\t%O0(%G0,%R0),%S1"
7903 [(set_attr "op_type" "SS")])