1 /* Definitions of target machine for GNU compiler, for IBM S/390
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
27 /* Override the __fixdfdi etc. routines when building libgcc2.
28 ??? This should be done in a cleaner way ... */
29 #if defined (IN_LIBGCC2) && !defined (__s390x__)
30 #include <config/s390/fixdfdi.h>
33 /* Which processor to generate code or schedule for. The cpu attribute
34 defines a list that mirrors this list, so changes to s390.md must be
35 made at the same time. */
46 /* Optional architectural facilities supported by the processor. */
52 PF_LONG_DISPLACEMENT = 4
55 extern enum processor_type s390_tune;
56 extern enum processor_flags s390_tune_flags;
57 extern const char *s390_tune_string;
59 extern enum processor_type s390_arch;
60 extern enum processor_flags s390_arch_flags;
61 extern const char *s390_arch_string;
63 #define TARGET_CPU_IEEE_FLOAT \
64 (s390_arch_flags & PF_IEEE_FLOAT)
65 #define TARGET_CPU_ZARCH \
66 (s390_arch_flags & PF_ZARCH)
67 #define TARGET_CPU_LONG_DISPLACEMENT \
68 (s390_arch_flags & PF_LONG_DISPLACEMENT)
70 #define TARGET_LONG_DISPLACEMENT \
71 (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT)
74 /* Run-time target specification. */
76 /* Target CPU builtins. */
77 #define TARGET_CPU_CPP_BUILTINS() \
80 builtin_assert ("cpu=s390"); \
81 builtin_assert ("machine=s390"); \
82 builtin_define ("__s390__"); \
84 builtin_define ("__s390x__"); \
88 /* Optional target features. */
89 extern int target_flags;
91 #define MASK_HARD_FLOAT 0x01
92 #define MASK_BACKCHAIN 0x02
93 #define MASK_SMALL_EXEC 0x04
94 #define MASK_DEBUG_ARG 0x08
95 #define MASK_64BIT 0x10
96 #define MASK_ZARCH 0x20
97 #define MASK_MVCLE 0x40
99 #define MASK_NO_FUSED_MADD 0x100
101 #define TARGET_HARD_FLOAT (target_flags & MASK_HARD_FLOAT)
102 #define TARGET_SOFT_FLOAT (!(target_flags & MASK_HARD_FLOAT))
103 #define TARGET_BACKCHAIN (target_flags & MASK_BACKCHAIN)
104 #define TARGET_SMALL_EXEC (target_flags & MASK_SMALL_EXEC)
105 #define TARGET_DEBUG_ARG (target_flags & MASK_DEBUG_ARG)
106 #define TARGET_64BIT (target_flags & MASK_64BIT)
107 #define TARGET_ZARCH (target_flags & MASK_ZARCH)
108 #define TARGET_MVCLE (target_flags & MASK_MVCLE)
109 #define TARGET_TPF (target_flags & MASK_TPF)
110 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
111 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
113 /* ??? Once this actually works, it could be made a runtime option. */
114 #define TARGET_IBM_FLOAT 0
115 #define TARGET_IEEE_FLOAT 1
117 #ifdef DEFAULT_TARGET_64BIT
118 #define TARGET_DEFAULT 0x31
120 #define TARGET_DEFAULT 0x1
123 #define TARGET_SWITCHES \
124 { { "hard-float", 1, N_("Use hardware fp")}, \
125 { "soft-float", -1, N_("Don't use hardware fp")}, \
126 { "backchain", 2, N_("Set backchain")}, \
127 { "no-backchain", -2, N_("Don't set backchain (faster, but debug harder")},\
128 { "small-exec", 4, N_("Use bras for executable < 64k")}, \
129 { "no-small-exec", -4, N_("Don't use bras")}, \
130 { "debug", 8, N_("Additional debug prints")}, \
131 { "no-debug", -8, N_("Don't print additional debug prints")}, \
132 { "64", 16, N_("64 bit ABI")}, \
133 { "31", -16, N_("31 bit ABI")}, \
134 { "zarch", 32, N_("z/Architecture")}, \
135 { "esa", -32, N_("ESA/390 architecture")}, \
136 { "mvcle", 64, N_("mvcle use")}, \
137 { "no-mvcle", -64, N_("mvc&ex")}, \
138 { "tpf", 128, N_("enable tpf OS code")}, \
139 { "no-tpf", -128, N_("disable tpf OS code")}, \
140 { "no-fused-madd", 256, N_("disable fused multiply/add instructions")},\
141 { "fused-madd", -256, N_("enable fused multiply/add instructions")}, \
142 { "", TARGET_DEFAULT, 0 } }
144 #define TARGET_OPTIONS \
145 { { "tune=", &s390_tune_string, \
146 N_("Schedule code for given CPU"), 0}, \
147 { "arch=", &s390_arch_string, \
148 N_("Generate code for given CPU"), 0}, \
151 /* Support for configure-time defaults. */
152 #define OPTION_DEFAULT_SPECS \
153 { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \
154 { "arch", "%{!march=*:-march=%(VALUE)}" }, \
155 { "tune", "%{!mtune=*:-mtune=%(VALUE)}" }
157 /* Defaulting rules. */
158 #ifdef DEFAULT_TARGET_64BIT
159 #define DRIVER_SELF_SPECS \
160 "%{!m31:%{!m64:-m64}}", \
161 "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \
162 "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}"
164 #define DRIVER_SELF_SPECS \
165 "%{!m31:%{!m64:-m31}}", \
166 "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \
167 "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}"
170 /* Target version string. Overridden by the OS header. */
171 #ifdef DEFAULT_TARGET_64BIT
172 #define TARGET_VERSION fprintf (stderr, " (zSeries)");
174 #define TARGET_VERSION fprintf (stderr, " (S/390)");
177 /* Hooks to override options. */
178 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) optimization_options(LEVEL, SIZE)
179 #define OVERRIDE_OPTIONS override_options ()
181 /* Frame pointer is not used for debugging. */
182 #define CAN_DEBUG_WITHOUT_FP
185 /* In libgcc2, determine target settings as compile-time constants. */
189 #define TARGET_64BIT 1
191 #define TARGET_64BIT 0
196 /* Target machine storage layout. */
198 /* Everything is big-endian. */
199 #define BITS_BIG_ENDIAN 1
200 #define BYTES_BIG_ENDIAN 1
201 #define WORDS_BIG_ENDIAN 1
203 /* Width of a word, in units (bytes). */
204 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
206 #define MIN_UNITS_PER_WORD 4
208 #define MAX_BITS_PER_WORD 64
210 /* Function arguments and return values are promoted to word size. */
211 #define PROMOTE_FOR_CALL_ONLY
213 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
214 if (INTEGRAL_MODE_P (MODE) && \
215 GET_MODE_SIZE (MODE) < UNITS_PER_WORD) { \
219 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
220 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
222 /* Boundary (in *bits*) on which stack pointer should be aligned. */
223 #define STACK_BOUNDARY 64
225 /* Allocation boundary (in *bits*) for the code of a function. */
226 #define FUNCTION_BOUNDARY 32
228 /* There is no point aligning anything to a rounder boundary than this. */
229 #define BIGGEST_ALIGNMENT 64
231 /* Alignment of field after `int : 0' in a structure. */
232 #define EMPTY_FIELD_BOUNDARY 32
234 /* Alignment on even addresses for LARL instruction. */
235 #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
236 #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN)
238 /* Alignment is not required by the hardware. */
239 #define STRICT_ALIGNMENT 0
241 /* Mode of stack savearea.
242 FUNCTION is VOIDmode because calling convention maintains SP.
243 BLOCK needs Pmode for SP.
244 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
245 #define STACK_SAVEAREA_MODE(LEVEL) \
246 (LEVEL == SAVE_FUNCTION ? VOIDmode \
247 : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode)
249 /* Define target floating point format. */
250 #define TARGET_FLOAT_FORMAT \
251 (TARGET_IEEE_FLOAT? IEEE_FLOAT_FORMAT : IBM_FLOAT_FORMAT)
256 /* Sizes in bits of the source language data types. */
257 #define SHORT_TYPE_SIZE 16
258 #define INT_TYPE_SIZE 32
259 #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32)
260 #define LONG_LONG_TYPE_SIZE 64
261 #define FLOAT_TYPE_SIZE 32
262 #define DOUBLE_TYPE_SIZE 64
263 #define LONG_DOUBLE_TYPE_SIZE 64 /* ??? Should support extended format. */
265 /* We use "unsigned char" as default. */
266 #define DEFAULT_SIGNED_CHAR 0
269 /* Register usage. */
271 /* We have 16 general purpose registers (registers 0-15),
272 and 16 floating point registers (registers 16-31).
273 (On non-IEEE machines, we have only 4 fp registers.)
275 Amongst the general purpose registers, some are used
276 for specific purposes:
277 GPR 11: Hard frame pointer (if needed)
278 GPR 12: Global offset table pointer (if needed)
279 GPR 13: Literal pool base register
280 GPR 14: Return address register
281 GPR 15: Stack pointer
283 Registers 32-34 are 'fake' hard registers that do not
284 correspond to actual hardware:
285 Reg 32: Argument pointer
286 Reg 33: Condition code
287 Reg 34: Frame pointer */
289 #define FIRST_PSEUDO_REGISTER 35
291 /* Standard register usage. */
292 #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16)
293 #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16)
294 #define FP_REGNO_P(N) ((N) >= 16 && (N) < (TARGET_IEEE_FLOAT? 32 : 20))
295 #define CC_REGNO_P(N) ((N) == 33)
296 #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34)
298 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
299 #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X)))
300 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
301 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
302 #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X)))
304 #define BASE_REGISTER 13
305 #define RETURN_REGNUM 14
308 /* Set up fixed registers and calling convention:
310 GPRs 0-5 are always call-clobbered,
311 GPRs 6-15 are always call-saved.
312 GPR 12 is fixed if used as GOT pointer.
313 GPR 13 is always fixed (as literal pool pointer).
314 GPR 14 is always fixed on S/390 machines (as return address).
315 GPR 15 is always fixed (as stack pointer).
316 The 'fake' hard registers are call-clobbered and fixed.
318 On 31-bit, FPRs 18-19 are call-clobbered;
319 on 64-bit, FPRs 24-31 are call-clobbered.
320 The remaining FPRs are call-saved. */
322 #define FIXED_REGISTERS \
333 #define CALL_USED_REGISTERS \
344 #define CALL_REALLY_USED_REGISTERS \
355 #define CONDITIONAL_REGISTER_USAGE \
362 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
363 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
365 if (TARGET_CPU_ZARCH) \
367 fixed_regs[RETURN_REGNUM] = 0; \
368 call_used_regs[RETURN_REGNUM] = 0; \
372 for (i = 24; i < 32; i++) \
373 call_used_regs[i] = call_really_used_regs[i] = 0; \
377 for (i = 18; i < 20; i++) \
378 call_used_regs[i] = call_really_used_regs[i] = 0; \
382 /* Preferred register allocation order. */
383 #define REG_ALLOC_ORDER \
384 { 1, 2, 3, 4, 5, 0, 13, 12, 11, 10, 9, 8, 7, 6, 14, \
385 16, 17, 18, 19, 20, 21, 22, 23, \
386 24, 25, 26, 27, 28, 29, 30, 31, \
390 /* Fitting values into registers. */
392 /* Integer modes <= word size fit into any GPR.
393 Integer modes > word size fit into successive GPRs, starting with
394 an even-numbered register.
395 SImode and DImode fit into FPRs as well.
397 Floating point modes <= word size fit into any FPR or GPR.
398 Floating point modes > word size (i.e. DFmode on 32-bit) fit
399 into any FPR, or an even-odd GPR pair.
401 Complex floating point modes fit either into two FPRs, or into
402 successive GPRs (again starting with an even number).
404 Condition code modes fit only into the CC register. */
406 #define HARD_REGNO_NREGS(REGNO, MODE) \
407 (FP_REGNO_P(REGNO)? \
408 (GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \
409 GENERAL_REGNO_P(REGNO)? \
410 ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1) / UNITS_PER_WORD) : \
413 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
414 (FP_REGNO_P(REGNO)? \
415 ((MODE) == SImode || (MODE) == DImode || \
416 GET_MODE_CLASS(MODE) == MODE_FLOAT || \
417 GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT) : \
418 GENERAL_REGNO_P(REGNO)? \
419 (HARD_REGNO_NREGS(REGNO, MODE) == 1 || !((REGNO) & 1)) : \
421 GET_MODE_CLASS (MODE) == MODE_CC : \
422 FRAME_REGNO_P(REGNO)? \
423 (enum machine_mode) (MODE) == Pmode : \
426 #define MODES_TIEABLE_P(MODE1, MODE2) \
427 (((MODE1) == SFmode || (MODE1) == DFmode) \
428 == ((MODE2) == SFmode || (MODE2) == DFmode))
430 /* Maximum number of registers to represent a value of mode MODE
431 in a register of class CLASS. */
432 #define CLASS_MAX_NREGS(CLASS, MODE) \
433 ((CLASS) == FP_REGS ? \
434 (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \
435 (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
437 /* If a 4-byte value is loaded into a FPR, it is placed into the
438 *upper* half of the register, not the lower. Therefore, we
439 cannot use SUBREGs to switch between modes in FP registers. */
440 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
441 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
442 ? reg_classes_intersect_p (FP_REGS, CLASS) : 0)
444 /* Register classes. */
446 /* We use the following register classes:
447 GENERAL_REGS All general purpose registers
448 ADDR_REGS All general purpose registers except %r0
449 (These registers can be used in address generation)
450 FP_REGS All floating point registers
452 GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS
453 ADDR_FP_REGS Union of ADDR_REGS and FP_REGS
456 ALL_REGS All registers
458 Note that the 'fake' frame pointer and argument pointer registers
459 are included amongst the address registers here. The condition
460 code register is only included in ALL_REGS. */
464 NO_REGS, ADDR_REGS, GENERAL_REGS,
465 FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS,
466 ALL_REGS, LIM_REG_CLASSES
468 #define N_REG_CLASSES (int) LIM_REG_CLASSES
470 #define REG_CLASS_NAMES \
471 { "NO_REGS", "ADDR_REGS", "GENERAL_REGS", \
472 "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" }
474 /* Class -> register mapping. */
475 #define REG_CLASS_CONTENTS \
477 { 0x00000000, 0x00000000 }, /* NO_REGS */ \
478 { 0x0000fffe, 0x00000005 }, /* ADDR_REGS */ \
479 { 0x0000ffff, 0x00000005 }, /* GENERAL_REGS */ \
480 { 0xffff0000, 0x00000000 }, /* FP_REGS */ \
481 { 0xfffffffe, 0x00000005 }, /* ADDR_FP_REGS */ \
482 { 0xffffffff, 0x00000005 }, /* GENERAL_FP_REGS */ \
483 { 0xffffffff, 0x00000007 }, /* ALL_REGS */ \
486 /* Register -> class mapping. */
487 extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
488 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
490 /* ADDR_REGS can be used as base or index register. */
491 #define INDEX_REG_CLASS ADDR_REGS
492 #define BASE_REG_CLASS ADDR_REGS
494 /* Check whether REGNO is a hard register of the suitable class
495 or a pseudo register currently allocated to one such. */
496 #define REGNO_OK_FOR_INDEX_P(REGNO) \
497 (((REGNO) < FIRST_PSEUDO_REGISTER \
498 && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \
499 || (reg_renumber[REGNO] > 0 && reg_renumber[REGNO] < 16))
500 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
503 /* Given an rtx X being reloaded into a reg required to be in class CLASS,
504 return the class of reg to actually use. */
505 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
506 s390_preferred_reload_class ((X), (CLASS))
508 /* We need a secondary reload when loading a PLUS which is
509 not a valid operand for LOAD ADDRESS. */
510 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
511 s390_secondary_input_reload_class ((CLASS), (MODE), (IN))
513 /* We need a secondary reload when storing a double-word
514 to a non-offsettable memory address. */
515 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
516 s390_secondary_output_reload_class ((CLASS), (MODE), (OUT))
518 /* We need secondary memory to move data between GPRs and FPRs. */
519 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
520 ((CLASS1) != (CLASS2) && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS))
522 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit
523 because the movsi and movsf patterns don't handle r/f moves. */
524 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
525 (GET_MODE_BITSIZE (MODE) < 32 \
526 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
530 /* Define various machine-dependent constraint letters. */
532 #define REG_CLASS_FROM_LETTER(C) \
533 ((C) == 'a' ? ADDR_REGS : \
534 (C) == 'd' ? GENERAL_REGS : \
535 (C) == 'f' ? FP_REGS : NO_REGS)
537 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
538 s390_const_ok_for_constraint_p ((VALUE), (C), (STR))
540 #define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE, C, STR) 1
542 #define EXTRA_CONSTRAINT_STR(OP, C, STR) \
543 s390_extra_constraint_str ((OP), (C), (STR))
544 #define EXTRA_MEMORY_CONSTRAINT(C, STR) \
545 ((C) == 'Q' || (C) == 'R' || (C) == 'S' || (C) == 'T')
546 #define EXTRA_ADDRESS_CONSTRAINT(C, STR) \
547 ((C) == 'U' || (C) == 'W' || (C) == 'Y')
549 #define CONSTRAINT_LEN(C, STR) \
550 ((C) == 'N' ? 5 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
552 /* Stack layout and calling conventions. */
554 /* Our stack grows from higher to lower addresses. However, local variables
555 are accessed by positive offsets, and function arguments are stored at
556 increasing addresses. */
557 #define STACK_GROWS_DOWNWARD
558 /* #undef FRAME_GROWS_DOWNWARD */
559 /* #undef ARGS_GROW_DOWNWARD */
561 /* The basic stack layout looks like this: the stack pointer points
562 to the register save area for called functions. Above that area
563 is the location to place outgoing arguments. Above those follow
564 dynamic allocations (alloca), and finally the local variables. */
566 /* Offset from stack-pointer to first location of outgoing args. */
567 #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96)
569 /* Offset within stack frame to start allocating local variables at. */
570 extern int current_function_outgoing_args_size;
571 #define STARTING_FRAME_OFFSET \
572 (STACK_POINTER_OFFSET + current_function_outgoing_args_size)
574 /* Offset from the stack pointer register to an item dynamically
575 allocated on the stack, e.g., by `alloca'. */
576 #define STACK_DYNAMIC_OFFSET(FUNDECL) (STARTING_FRAME_OFFSET)
578 /* Offset of first parameter from the argument pointer register value.
579 We have a fake argument pointer register that points directly to
580 the argument area. */
581 #define FIRST_PARM_OFFSET(FNDECL) 0
583 /* The return address of the current frame is retrieved
584 from the initial value of register RETURN_REGNUM.
585 For frames farther back, we use the stack slot where
586 the corresponding RETURN_REGNUM register was saved. */
588 #define DYNAMIC_CHAIN_ADDRESS(FRAME) \
589 ((FRAME) != hard_frame_pointer_rtx ? (FRAME) : \
590 plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET))
592 #define RETURN_ADDR_RTX(COUNT, FRAME) \
593 s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME)))
595 /* In 31-bit mode, we need to mask off the high bit of return addresses. */
596 #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff))
599 /* Exception handling. */
601 /* Describe calling conventions for DWARF-2 exception handling. */
602 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM)
603 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
604 #define DWARF_FRAME_RETURN_COLUMN 14
606 /* Describe how we implement __builtin_eh_return. */
607 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM)
608 #define EH_RETURN_HANDLER_RTX \
609 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, \
610 -STACK_POINTER_OFFSET + UNITS_PER_WORD*RETURN_REGNUM))
612 /* Select a format to encode pointers in exception handling data. */
613 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
615 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
619 /* Frame registers. */
621 #define STACK_POINTER_REGNUM 15
622 #define FRAME_POINTER_REGNUM 34
623 #define HARD_FRAME_POINTER_REGNUM 11
624 #define ARG_POINTER_REGNUM 32
626 /* The static chain must be call-clobbered, but not used for
627 function argument passing. As register 1 is clobbered by
628 the trampoline code, we only have one option. */
629 #define STATIC_CHAIN_REGNUM 0
631 /* Number of hardware registers that go into the DWARF-2 unwind info.
632 To avoid ABI incompatibility, this number must not change even as
633 'fake' hard registers are added or removed. */
634 #define DWARF_FRAME_REGISTERS 34
637 /* Frame pointer and argument pointer elimination. */
639 #define FRAME_POINTER_REQUIRED 0
641 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0
643 #define ELIMINABLE_REGS \
644 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
645 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
646 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
647 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
649 #define CAN_ELIMINATE(FROM, TO) (1)
651 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
652 { if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
654 else if ((FROM) == FRAME_POINTER_REGNUM \
655 && (TO) == HARD_FRAME_POINTER_REGNUM) \
657 else if ((FROM) == ARG_POINTER_REGNUM \
658 && (TO) == HARD_FRAME_POINTER_REGNUM) \
659 { (OFFSET) = s390_arg_frame_offset (); } \
660 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
661 { (OFFSET) = s390_arg_frame_offset (); } \
667 /* Stack arguments. */
669 /* We need current_function_outgoing_args to be valid. */
670 #define ACCUMULATE_OUTGOING_ARGS 1
672 /* Return doesn't modify the stack. */
673 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
676 /* Register arguments. */
678 typedef struct s390_arg_structure
680 int gprs; /* gpr so far */
681 int fprs; /* fpr so far */
685 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \
686 ((CUM).gprs=0, (CUM).fprs=0)
688 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
689 s390_function_arg_advance (&CUM, MODE, TYPE, NAMED)
691 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
692 s390_function_arg (&CUM, MODE, TYPE, NAMED)
694 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
695 s390_function_arg_pass_by_reference (MODE, TYPE)
697 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
699 /* Arguments can be placed in general registers 2 to 6,
700 or in floating point registers 0 and 2. */
701 #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \
702 (N) == 16 || (N) == 17)
705 /* Scalar return values. */
707 #define FUNCTION_VALUE(VALTYPE, FUNC) \
708 s390_function_value ((VALTYPE), VOIDmode)
710 #define LIBCALL_VALUE(MODE) \
711 s390_function_value (NULL, (MODE))
713 /* Only gpr 2 and fpr 0 are ever used as return registers. */
714 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16)
717 /* Function entry and exit. */
719 /* When returning from a function, the stack pointer does not matter. */
720 #define EXIT_IGNORE_STACK 1
725 #define FUNCTION_PROFILER(FILE, LABELNO) \
726 s390_function_profiler ((FILE), ((LABELNO)))
728 #define PROFILE_BEFORE_PROLOGUE 1
731 /* Implementing the varargs macros. */
733 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
734 s390_va_start (valist, nextarg)
736 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
737 s390_va_arg (valist, type)
740 /* Trampolines for nested functions. */
742 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 36 : 20)
744 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
745 s390_initialize_trampoline ((ADDR), (FNADDR), (CXT))
747 #define TRAMPOLINE_TEMPLATE(FILE) \
748 s390_trampoline_template (FILE)
753 /* We should use memcpy, not bcopy. */
754 #define TARGET_MEM_FUNCTIONS
757 /* Addressing modes, and classification of registers for them. */
759 /* Recognize any constant value that is a valid address. */
760 #define CONSTANT_ADDRESS_P(X) 0
762 /* Maximum number of registers that can appear in a valid memory address. */
763 #define MAX_REGS_PER_ADDRESS 2
765 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check
766 its validity for a certain class. We have two alternate definitions
767 for each of them. The usual definition accepts all pseudo regs; the
768 other rejects them all. The symbol REG_OK_STRICT causes the latter
769 definition to be used.
771 Most source files want to accept pseudo regs in the hope that they will
772 get allocated to the class that the insn wants them to be in.
773 Some source files that are used after register allocation
774 need to be strict. */
776 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
777 ((GET_MODE (X) == Pmode) && \
778 ((REGNO (X) >= FIRST_PSEUDO_REGISTER) \
779 || REGNO_REG_CLASS (REGNO (X)) == ADDR_REGS))
781 #define REG_OK_FOR_BASE_NONSTRICT_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
783 #define REG_OK_FOR_INDEX_STRICT_P(X) \
784 ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_INDEX_P (REGNO (X))))
786 #define REG_OK_FOR_BASE_STRICT_P(X) \
787 ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_BASE_P (REGNO (X))))
789 #ifndef REG_OK_STRICT
790 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
791 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
793 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
794 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
797 /* S/390 has no mode dependent addresses. */
798 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
800 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
801 valid memory address for an instruction.
802 The MODE argument is the machine mode for the MEM expression
803 that wants to use this address. */
805 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
807 if (legitimate_address_p (MODE, X, 1)) \
811 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
813 if (legitimate_address_p (MODE, X, 0)) \
818 /* Try machine-dependent ways of modifying an illegitimate address
819 to be legitimate. If we find one, return the new, valid address.
820 This macro is used in only one place: `memory_address' in explow.c. */
821 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
823 (X) = legitimize_address (X, OLDX, MODE); \
824 if (memory_address_p (MODE, X)) \
828 /* Nonzero if the constant value X is a legitimate general operand.
829 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
830 #define LEGITIMATE_CONSTANT_P(X) \
831 legitimate_constant_p (X)
833 /* Helper macro for s390.c and s390.md to check for symbolic constants. */
834 #define SYMBOLIC_CONST(X) \
835 (GET_CODE (X) == SYMBOL_REF \
836 || GET_CODE (X) == LABEL_REF \
837 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
839 #define TLS_SYMBOLIC_CONST(X) \
840 ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \
841 || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X)))
844 /* Condition codes. */
846 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
847 return the mode to be used for the comparison. */
848 #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y))
850 /* Define the information needed to generate branch and scc insns. This is
851 stored from the compare operation. Note that we can't use "rtx" here
852 since it hasn't been defined! */
853 extern struct rtx_def *s390_compare_op0, *s390_compare_op1;
856 /* Relative costs of operations. */
858 /* On s390, copy between fprs and gprs is expensive. */
859 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
860 (( ( reg_classes_intersect_p ((CLASS1), GENERAL_REGS) \
861 && reg_classes_intersect_p ((CLASS2), FP_REGS)) \
862 || ( reg_classes_intersect_p ((CLASS1), FP_REGS) \
863 && reg_classes_intersect_p ((CLASS2), GENERAL_REGS))) ? 10 : 1)
865 /* A C expression for the cost of moving data of mode M between a
866 register and memory. A value of 2 is the default; this cost is
867 relative to those in `REGISTER_MOVE_COST'. */
868 #define MEMORY_MOVE_COST(M, C, I) 1
870 /* A C expression for the cost of a branch instruction. A value of 1
871 is the default; other values are interpreted relative to that. */
872 #define BRANCH_COST 1
874 /* Nonzero if access to memory by bytes is slow and undesirable. */
875 #define SLOW_BYTE_ACCESS 1
877 /* The maximum number of bytes that a single instruction can move quickly
878 between memory and registers or between two memory locations. */
879 #define MOVE_MAX (TARGET_64BIT ? 16 : 8)
880 #define MAX_MOVE_MAX 16
882 /* Determine whether to use move_by_pieces or block move insn. */
883 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
884 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
885 || (TARGET_64BIT && (SIZE) == 8) )
887 /* Determine whether to use clear_by_pieces or block clear insn. */
888 #define CLEAR_BY_PIECES_P(SIZE, ALIGN) \
889 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \
890 || (TARGET_64BIT && (SIZE) == 8) )
892 /* Don't perform CSE on function addresses. */
893 #define NO_FUNCTION_CSE
898 /* Output before read-only data. */
899 #define TEXT_SECTION_ASM_OP ".text"
901 /* Output before writable (initialized) data. */
902 #define DATA_SECTION_ASM_OP ".data"
904 /* Output before writable (uninitialized) data. */
905 #define BSS_SECTION_ASM_OP ".bss"
907 /* S/390 constant pool breaks the devices in crtstuff.c to control section
908 in where code resides. We have to write it as asm code. */
910 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
913 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\
915 bas\t%r14,0(%r3,%r2)\n\
920 /* Position independent code. */
924 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM)
926 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
929 /* Assembler file format. */
931 /* Character to start a comment. */
932 #define ASM_COMMENT_START "#"
934 /* Declare an uninitialized external linkage data object. */
935 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
936 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
938 /* Globalizing directive for a label. */
939 #define GLOBAL_ASM_OP ".globl "
941 /* Advance the location counter to a multiple of 2**LOG bytes. */
942 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
943 if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG))
945 /* Advance the location counter by SIZE bytes. */
946 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
947 fprintf ((FILE), "\t.set\t.,.+"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
949 /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */
950 #define LOCAL_LABEL_PREFIX "."
952 /* How to refer to registers in assembler output. This sequence is
953 indexed by compiler's hard-register-number (see above). */
954 #define REGISTER_NAMES \
955 { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \
956 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \
957 "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \
958 "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \
959 "%ap", "%cc", "%fp" \
962 /* Emit a dtp-relative reference to a TLS variable. */
965 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
966 s390_output_dwarf_dtprel (FILE, SIZE, X)
969 /* Print operand X (an rtx) in assembler syntax to file FILE. */
970 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
971 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
973 /* Output an element of a case-vector that is absolute. */
974 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
977 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \
978 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
979 assemble_name ((FILE), buf); \
980 fputc ('\n', (FILE)); \
983 /* Output an element of a case-vector that is relative. */
984 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
987 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \
988 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \
989 assemble_name ((FILE), buf); \
990 fputc ('-', (FILE)); \
991 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \
992 assemble_name ((FILE), buf); \
993 fputc ('\n', (FILE)); \
997 /* Miscellaneous parameters. */
999 /* Define the codes that are matched by predicates in aux-output.c. */
1000 #define PREDICATE_CODES \
1001 {"s_operand", { SUBREG, MEM }}, \
1002 {"s_imm_operand", { CONST_INT, CONST_DOUBLE, SUBREG, MEM }}, \
1003 {"shift_count_operand", { REG, SUBREG, PLUS, CONST_INT }}, \
1004 {"bras_sym_operand",{ SYMBOL_REF, CONST }}, \
1005 {"larl_operand", { SYMBOL_REF, CONST, CONST_INT, CONST_DOUBLE }}, \
1006 {"load_multiple_operation", {PARALLEL}}, \
1007 {"store_multiple_operation", {PARALLEL}}, \
1008 {"const0_operand", { CONST_INT, CONST_DOUBLE }}, \
1009 {"consttable_operand", { SYMBOL_REF, LABEL_REF, CONST, \
1010 CONST_INT, CONST_DOUBLE }}, \
1011 {"s390_plus_operand", { PLUS }}, \
1012 {"s390_alc_comparison", { LTU, GTU, LEU, GEU }}, \
1013 {"s390_slb_comparison", { LTU, GTU, LEU, GEU }},
1015 /* Specify the machine mode that this machine uses for the index in the
1016 tablejump instruction. */
1017 #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode)
1019 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1020 is done just by pretending it is already truncated. */
1021 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1023 /* Specify the machine mode that pointers have.
1024 After generation of rtl, the compiler makes no further distinction
1025 between pointers and any other objects of this machine mode. */
1026 #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode))
1028 /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */
1029 #define POINTERS_EXTEND_UNSIGNED -1
1031 /* A function address in a call instruction is a byte address (for
1032 indexing purposes) so give the MEM rtx a byte's mode. */
1033 #define FUNCTION_MODE QImode
1035 /* This macro definition sets up a default value for `main' to return. */
1036 #define DEFAULT_MAIN_RETURN c_expand_return (integer_zero_node)