1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
26 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
45 #include "basic-block.h"
46 #include "integrate.h"
49 #include "target-def.h"
51 #include "langhooks.h"
53 #include "tree-gimple.h"
56 /* Define the specific costs for a given cpu. */
58 struct processor_costs
61 const int m; /* cost of an M instruction. */
62 const int mghi; /* cost of an MGHI instruction. */
63 const int mh; /* cost of an MH instruction. */
64 const int mhi; /* cost of an MHI instruction. */
65 const int ml; /* cost of an ML instruction. */
66 const int mr; /* cost of an MR instruction. */
67 const int ms; /* cost of an MS instruction. */
68 const int msg; /* cost of an MSG instruction. */
69 const int msgf; /* cost of an MSGF instruction. */
70 const int msgfr; /* cost of an MSGFR instruction. */
71 const int msgr; /* cost of an MSGR instruction. */
72 const int msr; /* cost of an MSR instruction. */
73 const int mult_df; /* cost of multiplication in DFmode. */
76 const int sqxbr; /* cost of square root in TFmode. */
77 const int sqdbr; /* cost of square root in DFmode. */
78 const int sqebr; /* cost of square root in SFmode. */
79 /* multiply and add */
80 const int madbr; /* cost of multiply and add in DFmode. */
81 const int maebr; /* cost of multiply and add in SFmode. */
96 const struct processor_costs *s390_cost;
99 struct processor_costs z900_cost =
101 COSTS_N_INSNS (5), /* M */
102 COSTS_N_INSNS (10), /* MGHI */
103 COSTS_N_INSNS (5), /* MH */
104 COSTS_N_INSNS (4), /* MHI */
105 COSTS_N_INSNS (5), /* ML */
106 COSTS_N_INSNS (5), /* MR */
107 COSTS_N_INSNS (4), /* MS */
108 COSTS_N_INSNS (15), /* MSG */
109 COSTS_N_INSNS (7), /* MSGF */
110 COSTS_N_INSNS (7), /* MSGFR */
111 COSTS_N_INSNS (10), /* MSGR */
112 COSTS_N_INSNS (4), /* MSR */
113 COSTS_N_INSNS (7), /* multiplication in DFmode */
114 COSTS_N_INSNS (13), /* MXBR */
115 COSTS_N_INSNS (136), /* SQXBR */
116 COSTS_N_INSNS (44), /* SQDBR */
117 COSTS_N_INSNS (35), /* SQEBR */
118 COSTS_N_INSNS (18), /* MADBR */
119 COSTS_N_INSNS (13), /* MAEBR */
120 COSTS_N_INSNS (134), /* DXBR */
121 COSTS_N_INSNS (135), /* DXR */
122 COSTS_N_INSNS (30), /* DDBR */
123 COSTS_N_INSNS (30), /* DDR */
124 COSTS_N_INSNS (27), /* DEBR */
125 COSTS_N_INSNS (26), /* DER */
126 COSTS_N_INSNS (220), /* DLGR */
127 COSTS_N_INSNS (34), /* DLR */
128 COSTS_N_INSNS (34), /* DR */
129 COSTS_N_INSNS (32), /* DSGFR */
130 COSTS_N_INSNS (32), /* DSGR */
134 struct processor_costs z990_cost =
136 COSTS_N_INSNS (4), /* M */
137 COSTS_N_INSNS (2), /* MGHI */
138 COSTS_N_INSNS (2), /* MH */
139 COSTS_N_INSNS (2), /* MHI */
140 COSTS_N_INSNS (4), /* ML */
141 COSTS_N_INSNS (4), /* MR */
142 COSTS_N_INSNS (5), /* MS */
143 COSTS_N_INSNS (6), /* MSG */
144 COSTS_N_INSNS (4), /* MSGF */
145 COSTS_N_INSNS (4), /* MSGFR */
146 COSTS_N_INSNS (4), /* MSGR */
147 COSTS_N_INSNS (4), /* MSR */
148 COSTS_N_INSNS (1), /* multiplication in DFmode */
149 COSTS_N_INSNS (28), /* MXBR */
150 COSTS_N_INSNS (130), /* SQXBR */
151 COSTS_N_INSNS (66), /* SQDBR */
152 COSTS_N_INSNS (38), /* SQEBR */
153 COSTS_N_INSNS (1), /* MADBR */
154 COSTS_N_INSNS (1), /* MAEBR */
155 COSTS_N_INSNS (60), /* DXBR */
156 COSTS_N_INSNS (72), /* DXR */
157 COSTS_N_INSNS (40), /* DDBR */
158 COSTS_N_INSNS (44), /* DDR */
159 COSTS_N_INSNS (26), /* DDBR */
160 COSTS_N_INSNS (28), /* DER */
161 COSTS_N_INSNS (176), /* DLGR */
162 COSTS_N_INSNS (31), /* DLR */
163 COSTS_N_INSNS (31), /* DR */
164 COSTS_N_INSNS (31), /* DSGFR */
165 COSTS_N_INSNS (31), /* DSGR */
169 struct processor_costs z9_109_cost =
171 COSTS_N_INSNS (4), /* M */
172 COSTS_N_INSNS (2), /* MGHI */
173 COSTS_N_INSNS (2), /* MH */
174 COSTS_N_INSNS (2), /* MHI */
175 COSTS_N_INSNS (4), /* ML */
176 COSTS_N_INSNS (4), /* MR */
177 COSTS_N_INSNS (5), /* MS */
178 COSTS_N_INSNS (6), /* MSG */
179 COSTS_N_INSNS (4), /* MSGF */
180 COSTS_N_INSNS (4), /* MSGFR */
181 COSTS_N_INSNS (4), /* MSGR */
182 COSTS_N_INSNS (4), /* MSR */
183 COSTS_N_INSNS (1), /* multiplication in DFmode */
184 COSTS_N_INSNS (28), /* MXBR */
185 COSTS_N_INSNS (130), /* SQXBR */
186 COSTS_N_INSNS (66), /* SQDBR */
187 COSTS_N_INSNS (38), /* SQEBR */
188 COSTS_N_INSNS (1), /* MADBR */
189 COSTS_N_INSNS (1), /* MAEBR */
190 COSTS_N_INSNS (60), /* DXBR */
191 COSTS_N_INSNS (72), /* DXR */
192 COSTS_N_INSNS (40), /* DDBR */
193 COSTS_N_INSNS (37), /* DDR */
194 COSTS_N_INSNS (26), /* DDBR */
195 COSTS_N_INSNS (28), /* DER */
196 COSTS_N_INSNS (30), /* DLGR */
197 COSTS_N_INSNS (23), /* DLR */
198 COSTS_N_INSNS (23), /* DR */
199 COSTS_N_INSNS (24), /* DSGFR */
200 COSTS_N_INSNS (24), /* DSGR */
203 extern int reload_completed;
205 /* Save information from a "cmpxx" operation until the branch or scc is
207 rtx s390_compare_op0, s390_compare_op1;
209 /* Save the result of a compare_and_swap until the branch or scc is
211 rtx s390_compare_emitted = NULL_RTX;
213 /* Structure used to hold the components of a S/390 memory
214 address. A legitimate address on S/390 is of the general
216 base + index + displacement
217 where any of the components is optional.
219 base and index are registers of the class ADDR_REGS,
220 displacement is an unsigned 12-bit immediate constant. */
231 /* Which cpu are we tuning for. */
232 enum processor_type s390_tune = PROCESSOR_max;
233 enum processor_flags s390_tune_flags;
234 /* Which instruction set architecture to use. */
235 enum processor_type s390_arch;
236 enum processor_flags s390_arch_flags;
238 HOST_WIDE_INT s390_warn_framesize = 0;
239 HOST_WIDE_INT s390_stack_size = 0;
240 HOST_WIDE_INT s390_stack_guard = 0;
242 /* The following structure is embedded in the machine
243 specific part of struct function. */
245 struct s390_frame_layout GTY (())
247 /* Offset within stack frame. */
248 HOST_WIDE_INT gprs_offset;
249 HOST_WIDE_INT f0_offset;
250 HOST_WIDE_INT f4_offset;
251 HOST_WIDE_INT f8_offset;
252 HOST_WIDE_INT backchain_offset;
254 /* Number of first and last gpr where slots in the register
255 save area are reserved for. */
256 int first_save_gpr_slot;
257 int last_save_gpr_slot;
259 /* Number of first and last gpr to be saved, restored. */
261 int first_restore_gpr;
263 int last_restore_gpr;
265 /* Bits standing for floating point registers. Set, if the
266 respective register has to be saved. Starting with reg 16 (f0)
267 at the rightmost bit.
268 Bit 15 - 8 7 6 5 4 3 2 1 0
269 fpr 15 - 8 7 5 3 1 6 4 2 0
270 reg 31 - 24 23 22 21 20 19 18 17 16 */
271 unsigned int fpr_bitmap;
273 /* Number of floating point registers f8-f15 which must be saved. */
276 /* Set if return address needs to be saved.
277 This flag is set by s390_return_addr_rtx if it could not use
278 the initial value of r14 and therefore depends on r14 saved
280 bool save_return_addr_p;
282 /* Size of stack frame. */
283 HOST_WIDE_INT frame_size;
286 /* Define the structure for the machine field in struct function. */
288 struct machine_function GTY(())
290 struct s390_frame_layout frame_layout;
292 /* Literal pool base register. */
295 /* True if we may need to perform branch splitting. */
296 bool split_branches_pending_p;
298 /* True during final stage of literal pool processing. */
299 bool decomposed_literal_pool_addresses_ok_p;
301 /* Some local-dynamic TLS symbol name. */
302 const char *some_ld_name;
304 bool has_landing_pad_p;
307 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
309 #define cfun_frame_layout (cfun->machine->frame_layout)
310 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
311 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
312 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
313 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
315 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
318 /* Number of GPRs and FPRs used for argument passing. */
319 #define GP_ARG_NUM_REG 5
320 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
322 /* A couple of shortcuts. */
323 #define CONST_OK_FOR_J(x) \
324 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
325 #define CONST_OK_FOR_K(x) \
326 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
327 #define CONST_OK_FOR_Os(x) \
328 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
329 #define CONST_OK_FOR_Op(x) \
330 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
331 #define CONST_OK_FOR_On(x) \
332 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
334 #define REGNO_PAIR_OK(REGNO, MODE) \
335 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
337 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
340 s390_set_has_landing_pad_p (bool value)
342 cfun->machine->has_landing_pad_p = value;
345 /* If two condition code modes are compatible, return a condition code
346 mode which is compatible with both. Otherwise, return
349 static enum machine_mode
350 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
358 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
359 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
380 /* Return true if SET either doesn't set the CC register, or else
381 the source and destination have matching CC modes and that
382 CC mode is at least as constrained as REQ_MODE. */
385 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
387 enum machine_mode set_mode;
389 gcc_assert (GET_CODE (set) == SET);
391 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
394 set_mode = GET_MODE (SET_DEST (set));
408 if (req_mode != set_mode)
413 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
414 && req_mode != CCSRmode && req_mode != CCURmode)
420 if (req_mode != CCAmode)
428 return (GET_MODE (SET_SRC (set)) == set_mode);
431 /* Return true if every SET in INSN that sets the CC register
432 has source and destination with matching CC modes and that
433 CC mode is at least as constrained as REQ_MODE.
434 If REQ_MODE is VOIDmode, always return false. */
437 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
441 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
442 if (req_mode == VOIDmode)
445 if (GET_CODE (PATTERN (insn)) == SET)
446 return s390_match_ccmode_set (PATTERN (insn), req_mode);
448 if (GET_CODE (PATTERN (insn)) == PARALLEL)
449 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
451 rtx set = XVECEXP (PATTERN (insn), 0, i);
452 if (GET_CODE (set) == SET)
453 if (!s390_match_ccmode_set (set, req_mode))
460 /* If a test-under-mask instruction can be used to implement
461 (compare (and ... OP1) OP2), return the CC mode required
462 to do that. Otherwise, return VOIDmode.
463 MIXED is true if the instruction can distinguish between
464 CC1 and CC2 for mixed selected bits (TMxx), it is false
465 if the instruction cannot (TM). */
468 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
472 /* ??? Fixme: should work on CONST_DOUBLE as well. */
473 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
476 /* Selected bits all zero: CC0.
477 e.g.: int a; if ((a & (16 + 128)) == 0) */
478 if (INTVAL (op2) == 0)
481 /* Selected bits all one: CC3.
482 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
483 if (INTVAL (op2) == INTVAL (op1))
486 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
488 if ((a & (16 + 128)) == 16) -> CCT1
489 if ((a & (16 + 128)) == 128) -> CCT2 */
492 bit1 = exact_log2 (INTVAL (op2));
493 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
494 if (bit0 != -1 && bit1 != -1)
495 return bit0 > bit1 ? CCT1mode : CCT2mode;
501 /* Given a comparison code OP (EQ, NE, etc.) and the operands
502 OP0 and OP1 of a COMPARE, return the mode to be used for the
506 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
512 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
513 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
515 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
516 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
518 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
519 || GET_CODE (op1) == NEG)
520 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
523 if (GET_CODE (op0) == AND)
525 /* Check whether we can potentially do it via TM. */
526 enum machine_mode ccmode;
527 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
528 if (ccmode != VOIDmode)
530 /* Relax CCTmode to CCZmode to allow fall-back to AND
531 if that turns out to be beneficial. */
532 return ccmode == CCTmode ? CCZmode : ccmode;
536 if (register_operand (op0, HImode)
537 && GET_CODE (op1) == CONST_INT
538 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
540 if (register_operand (op0, QImode)
541 && GET_CODE (op1) == CONST_INT
542 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
551 /* The only overflow condition of NEG and ABS happens when
552 -INT_MAX is used as parameter, which stays negative. So
553 we have an overflow from a positive value to a negative.
554 Using CCAP mode the resulting cc can be used for comparisons. */
555 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
556 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
559 /* If constants are involved in an add instruction it is possible to use
560 the resulting cc for comparisons with zero. Knowing the sign of the
561 constant the overflow behavior gets predictable. e.g.:
562 int a, b; if ((b = a + c) > 0)
563 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
564 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
565 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
567 if (INTVAL (XEXP((op0), 1)) < 0)
581 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
582 && GET_CODE (op1) != CONST_INT)
588 if (GET_CODE (op0) == PLUS
589 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
592 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
593 && GET_CODE (op1) != CONST_INT)
599 if (GET_CODE (op0) == MINUS
600 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
603 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
604 && GET_CODE (op1) != CONST_INT)
613 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
614 that we can implement more efficiently. */
617 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
619 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
620 if ((*code == EQ || *code == NE)
621 && *op1 == const0_rtx
622 && GET_CODE (*op0) == ZERO_EXTRACT
623 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
624 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
625 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
627 rtx inner = XEXP (*op0, 0);
628 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
629 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
630 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
632 if (len > 0 && len < modesize
633 && pos >= 0 && pos + len <= modesize
634 && modesize <= HOST_BITS_PER_WIDE_INT)
636 unsigned HOST_WIDE_INT block;
637 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
638 block <<= modesize - pos - len;
640 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
641 gen_int_mode (block, GET_MODE (inner)));
645 /* Narrow AND of memory against immediate to enable TM. */
646 if ((*code == EQ || *code == NE)
647 && *op1 == const0_rtx
648 && GET_CODE (*op0) == AND
649 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
650 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
652 rtx inner = XEXP (*op0, 0);
653 rtx mask = XEXP (*op0, 1);
655 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
656 if (GET_CODE (inner) == SUBREG
657 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
658 && (GET_MODE_SIZE (GET_MODE (inner))
659 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
661 & GET_MODE_MASK (GET_MODE (inner))
662 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
664 inner = SUBREG_REG (inner);
666 /* Do not change volatile MEMs. */
667 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
669 int part = s390_single_part (XEXP (*op0, 1),
670 GET_MODE (inner), QImode, 0);
673 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
674 inner = adjust_address_nv (inner, QImode, part);
675 *op0 = gen_rtx_AND (QImode, inner, mask);
680 /* Narrow comparisons against 0xffff to HImode if possible. */
681 if ((*code == EQ || *code == NE)
682 && GET_CODE (*op1) == CONST_INT
683 && INTVAL (*op1) == 0xffff
684 && SCALAR_INT_MODE_P (GET_MODE (*op0))
685 && (nonzero_bits (*op0, GET_MODE (*op0))
686 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
688 *op0 = gen_lowpart (HImode, *op0);
693 /* Remove redundant UNSPEC_CMPINT conversions if possible. */
694 if (GET_CODE (*op0) == UNSPEC
695 && XINT (*op0, 1) == UNSPEC_CMPINT
696 && XVECLEN (*op0, 0) == 1
697 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
698 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
699 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
700 && *op1 == const0_rtx)
702 enum rtx_code new_code = UNKNOWN;
705 case EQ: new_code = EQ; break;
706 case NE: new_code = NE; break;
707 case LT: new_code = GTU; break;
708 case GT: new_code = LTU; break;
709 case LE: new_code = GEU; break;
710 case GE: new_code = LEU; break;
714 if (new_code != UNKNOWN)
716 *op0 = XVECEXP (*op0, 0, 0);
721 /* Simplify cascaded EQ, NE with const0_rtx. */
722 if ((*code == NE || *code == EQ)
723 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
724 && GET_MODE (*op0) == SImode
725 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
726 && REG_P (XEXP (*op0, 0))
727 && XEXP (*op0, 1) == const0_rtx
728 && *op1 == const0_rtx)
730 if ((*code == EQ && GET_CODE (*op0) == NE)
731 || (*code == NE && GET_CODE (*op0) == EQ))
735 *op0 = XEXP (*op0, 0);
738 /* Prefer register over memory as first operand. */
739 if (MEM_P (*op0) && REG_P (*op1))
741 rtx tem = *op0; *op0 = *op1; *op1 = tem;
742 *code = swap_condition (*code);
746 /* Emit a compare instruction suitable to implement the comparison
747 OP0 CODE OP1. Return the correct condition RTL to be placed in
748 the IF_THEN_ELSE of the conditional branch testing the result. */
751 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
753 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
756 /* Do not output a redundant compare instruction if a compare_and_swap
757 pattern already computed the result and the machine modes are compatible. */
758 if (s390_compare_emitted
759 && (s390_cc_modes_compatible (GET_MODE (s390_compare_emitted), mode)
760 == GET_MODE (s390_compare_emitted)))
761 ret = gen_rtx_fmt_ee (code, VOIDmode, s390_compare_emitted, const0_rtx);
764 rtx cc = gen_rtx_REG (mode, CC_REGNUM);
766 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
767 ret = gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
769 s390_compare_emitted = NULL_RTX;
773 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
774 unconditional jump, else a conditional jump under condition COND. */
777 s390_emit_jump (rtx target, rtx cond)
781 target = gen_rtx_LABEL_REF (VOIDmode, target);
783 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
785 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
786 emit_jump_insn (insn);
789 /* Return branch condition mask to implement a branch
790 specified by CODE. Return -1 for invalid comparisons. */
793 s390_branch_condition_mask (rtx code)
795 const int CC0 = 1 << 3;
796 const int CC1 = 1 << 2;
797 const int CC2 = 1 << 1;
798 const int CC3 = 1 << 0;
800 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
801 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
802 gcc_assert (XEXP (code, 1) == const0_rtx);
804 switch (GET_MODE (XEXP (code, 0)))
808 switch (GET_CODE (code))
811 case NE: return CC1 | CC2 | CC3;
817 switch (GET_CODE (code))
820 case NE: return CC0 | CC2 | CC3;
826 switch (GET_CODE (code))
829 case NE: return CC0 | CC1 | CC3;
835 switch (GET_CODE (code))
838 case NE: return CC0 | CC1 | CC2;
844 switch (GET_CODE (code))
846 case EQ: return CC0 | CC2;
847 case NE: return CC1 | CC3;
853 switch (GET_CODE (code))
855 case LTU: return CC2 | CC3; /* carry */
856 case GEU: return CC0 | CC1; /* no carry */
862 switch (GET_CODE (code))
864 case GTU: return CC0 | CC1; /* borrow */
865 case LEU: return CC2 | CC3; /* no borrow */
871 switch (GET_CODE (code))
873 case EQ: return CC0 | CC2;
874 case NE: return CC1 | CC3;
875 case LTU: return CC1;
876 case GTU: return CC3;
877 case LEU: return CC1 | CC2;
878 case GEU: return CC2 | CC3;
883 switch (GET_CODE (code))
886 case NE: return CC1 | CC2 | CC3;
887 case LTU: return CC1;
888 case GTU: return CC2;
889 case LEU: return CC0 | CC1;
890 case GEU: return CC0 | CC2;
896 switch (GET_CODE (code))
899 case NE: return CC2 | CC1 | CC3;
900 case LTU: return CC2;
901 case GTU: return CC1;
902 case LEU: return CC0 | CC2;
903 case GEU: return CC0 | CC1;
909 switch (GET_CODE (code))
912 case NE: return CC1 | CC2 | CC3;
913 case LT: return CC1 | CC3;
915 case LE: return CC0 | CC1 | CC3;
916 case GE: return CC0 | CC2;
922 switch (GET_CODE (code))
925 case NE: return CC1 | CC2 | CC3;
927 case GT: return CC2 | CC3;
928 case LE: return CC0 | CC1;
929 case GE: return CC0 | CC2 | CC3;
935 switch (GET_CODE (code))
938 case NE: return CC1 | CC2 | CC3;
941 case LE: return CC0 | CC1;
942 case GE: return CC0 | CC2;
943 case UNORDERED: return CC3;
944 case ORDERED: return CC0 | CC1 | CC2;
945 case UNEQ: return CC0 | CC3;
946 case UNLT: return CC1 | CC3;
947 case UNGT: return CC2 | CC3;
948 case UNLE: return CC0 | CC1 | CC3;
949 case UNGE: return CC0 | CC2 | CC3;
950 case LTGT: return CC1 | CC2;
956 switch (GET_CODE (code))
959 case NE: return CC2 | CC1 | CC3;
962 case LE: return CC0 | CC2;
963 case GE: return CC0 | CC1;
964 case UNORDERED: return CC3;
965 case ORDERED: return CC0 | CC2 | CC1;
966 case UNEQ: return CC0 | CC3;
967 case UNLT: return CC2 | CC3;
968 case UNGT: return CC1 | CC3;
969 case UNLE: return CC0 | CC2 | CC3;
970 case UNGE: return CC0 | CC1 | CC3;
971 case LTGT: return CC2 | CC1;
981 /* If INV is false, return assembler mnemonic string to implement
982 a branch specified by CODE. If INV is true, return mnemonic
983 for the corresponding inverted branch. */
986 s390_branch_condition_mnemonic (rtx code, int inv)
988 static const char *const mnemonic[16] =
990 NULL, "o", "h", "nle",
991 "l", "nhe", "lh", "ne",
992 "e", "nlh", "he", "nl",
993 "le", "nh", "no", NULL
996 int mask = s390_branch_condition_mask (code);
997 gcc_assert (mask >= 0);
1002 gcc_assert (mask >= 1 && mask <= 14);
1004 return mnemonic[mask];
1007 /* Return the part of op which has a value different from def.
1008 The size of the part is determined by mode.
1009 Use this function only if you already know that op really
1010 contains such a part. */
1012 unsigned HOST_WIDE_INT
1013 s390_extract_part (rtx op, enum machine_mode mode, int def)
1015 unsigned HOST_WIDE_INT value = 0;
1016 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1017 int part_bits = GET_MODE_BITSIZE (mode);
1018 unsigned HOST_WIDE_INT part_mask
1019 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1022 for (i = 0; i < max_parts; i++)
1025 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1027 value >>= part_bits;
1029 if ((value & part_mask) != (def & part_mask))
1030 return value & part_mask;
1036 /* If OP is an integer constant of mode MODE with exactly one
1037 part of mode PART_MODE unequal to DEF, return the number of that
1038 part. Otherwise, return -1. */
1041 s390_single_part (rtx op,
1042 enum machine_mode mode,
1043 enum machine_mode part_mode,
1046 unsigned HOST_WIDE_INT value = 0;
1047 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1048 unsigned HOST_WIDE_INT part_mask
1049 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1052 if (GET_CODE (op) != CONST_INT)
1055 for (i = 0; i < n_parts; i++)
1058 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1060 value >>= GET_MODE_BITSIZE (part_mode);
1062 if ((value & part_mask) != (def & part_mask))
1070 return part == -1 ? -1 : n_parts - 1 - part;
1073 /* Check whether we can (and want to) split a double-word
1074 move in mode MODE from SRC to DST into two single-word
1075 moves, moving the subword FIRST_SUBWORD first. */
1078 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1080 /* Floating point registers cannot be split. */
1081 if (FP_REG_P (src) || FP_REG_P (dst))
1084 /* We don't need to split if operands are directly accessible. */
1085 if (s_operand (src, mode) || s_operand (dst, mode))
1088 /* Non-offsettable memory references cannot be split. */
1089 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1090 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1093 /* Moving the first subword must not clobber a register
1094 needed to move the second subword. */
1095 if (register_operand (dst, mode))
1097 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1098 if (reg_overlap_mentioned_p (subreg, src))
1105 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1106 and [MEM2, MEM2 + SIZE] do overlap and false
1110 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1112 rtx addr1, addr2, addr_delta;
1113 HOST_WIDE_INT delta;
1115 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1121 addr1 = XEXP (mem1, 0);
1122 addr2 = XEXP (mem2, 0);
1124 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1126 /* This overlapping check is used by peepholes merging memory block operations.
1127 Overlapping operations would otherwise be recognized by the S/390 hardware
1128 and would fall back to a slower implementation. Allowing overlapping
1129 operations would lead to slow code but not to wrong code. Therefore we are
1130 somewhat optimistic if we cannot prove that the memory blocks are
1132 That's why we return false here although this may accept operations on
1133 overlapping memory areas. */
1134 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1137 delta = INTVAL (addr_delta);
1140 || (delta > 0 && delta < size)
1141 || (delta < 0 && -delta < size))
1147 /* Check whether the address of memory reference MEM2 equals exactly
1148 the address of memory reference MEM1 plus DELTA. Return true if
1149 we can prove this to be the case, false otherwise. */
1152 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1154 rtx addr1, addr2, addr_delta;
1156 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1159 addr1 = XEXP (mem1, 0);
1160 addr2 = XEXP (mem2, 0);
1162 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1163 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1169 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1172 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1175 enum machine_mode wmode = mode;
1176 rtx dst = operands[0];
1177 rtx src1 = operands[1];
1178 rtx src2 = operands[2];
1181 /* If we cannot handle the operation directly, use a temp register. */
1182 if (!s390_logical_operator_ok_p (operands))
1183 dst = gen_reg_rtx (mode);
1185 /* QImode and HImode patterns make sense only if we have a destination
1186 in memory. Otherwise perform the operation in SImode. */
1187 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1190 /* Widen operands if required. */
1193 if (GET_CODE (dst) == SUBREG
1194 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1196 else if (REG_P (dst))
1197 dst = gen_rtx_SUBREG (wmode, dst, 0);
1199 dst = gen_reg_rtx (wmode);
1201 if (GET_CODE (src1) == SUBREG
1202 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1204 else if (GET_MODE (src1) != VOIDmode)
1205 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1207 if (GET_CODE (src2) == SUBREG
1208 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1210 else if (GET_MODE (src2) != VOIDmode)
1211 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1214 /* Emit the instruction. */
1215 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1216 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1217 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1219 /* Fix up the destination if needed. */
1220 if (dst != operands[0])
1221 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1224 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1227 s390_logical_operator_ok_p (rtx *operands)
1229 /* If the destination operand is in memory, it needs to coincide
1230 with one of the source operands. After reload, it has to be
1231 the first source operand. */
1232 if (GET_CODE (operands[0]) == MEM)
1233 return rtx_equal_p (operands[0], operands[1])
1234 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1239 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1240 operand IMMOP to switch from SS to SI type instructions. */
1243 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1245 int def = code == AND ? -1 : 0;
1249 gcc_assert (GET_CODE (*memop) == MEM);
1250 gcc_assert (!MEM_VOLATILE_P (*memop));
1252 mask = s390_extract_part (*immop, QImode, def);
1253 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1254 gcc_assert (part >= 0);
1256 *memop = adjust_address (*memop, QImode, part);
1257 *immop = gen_int_mode (mask, QImode);
1261 /* How to allocate a 'struct machine_function'. */
1263 static struct machine_function *
1264 s390_init_machine_status (void)
1266 return ggc_alloc_cleared (sizeof (struct machine_function));
1269 /* Change optimizations to be performed, depending on the
1272 LEVEL is the optimization level specified; 2 if `-O2' is
1273 specified, 1 if `-O' is specified, and 0 if neither is specified.
1275 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1278 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1280 /* ??? There are apparently still problems with -fcaller-saves. */
1281 flag_caller_saves = 0;
1283 /* By default, always emit DWARF-2 unwind info. This allows debugging
1284 without maintaining a stack frame back-chain. */
1285 flag_asynchronous_unwind_tables = 1;
1287 /* Use MVCLE instructions to decrease code size if requested. */
1289 target_flags |= MASK_MVCLE;
1292 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1293 to the associated processor_type and processor_flags if so. */
1296 s390_handle_arch_option (const char *arg,
1297 enum processor_type *type,
1298 enum processor_flags *flags)
1302 const char *const name; /* processor name or nickname. */
1303 const enum processor_type processor;
1304 const enum processor_flags flags;
1306 const processor_alias_table[] =
1308 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1309 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1310 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1311 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1312 | PF_LONG_DISPLACEMENT},
1313 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1314 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1318 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1319 if (strcmp (arg, processor_alias_table[i].name) == 0)
1321 *type = processor_alias_table[i].processor;
1322 *flags = processor_alias_table[i].flags;
1328 /* Implement TARGET_HANDLE_OPTION. */
1331 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1336 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1338 case OPT_mstack_guard_:
1339 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1341 if (exact_log2 (s390_stack_guard) == -1)
1342 error ("stack guard value must be an exact power of 2");
1345 case OPT_mstack_size_:
1346 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1348 if (exact_log2 (s390_stack_size) == -1)
1349 error ("stack size must be an exact power of 2");
1353 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1355 case OPT_mwarn_framesize_:
1356 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1364 override_options (void)
1366 /* Set up function hooks. */
1367 init_machine_status = s390_init_machine_status;
1369 /* Architecture mode defaults according to ABI. */
1370 if (!(target_flags_explicit & MASK_ZARCH))
1373 target_flags |= MASK_ZARCH;
1375 target_flags &= ~MASK_ZARCH;
1378 /* Determine processor architectural level. */
1379 if (!s390_arch_string)
1381 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1382 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1385 /* Determine processor to tune for. */
1386 if (s390_tune == PROCESSOR_max)
1388 s390_tune = s390_arch;
1389 s390_tune_flags = s390_arch_flags;
1392 /* Sanity checks. */
1393 if (TARGET_ZARCH && !(s390_arch_flags & PF_ZARCH))
1394 error ("z/Architecture mode not supported on %s", s390_arch_string);
1395 if (TARGET_64BIT && !TARGET_ZARCH)
1396 error ("64-bit ABI not supported in ESA/390 mode");
1398 /* Set processor cost function. */
1399 if (s390_tune == PROCESSOR_2094_Z9_109)
1400 s390_cost = &z9_109_cost;
1401 else if (s390_tune == PROCESSOR_2084_Z990)
1402 s390_cost = &z990_cost;
1404 s390_cost = &z900_cost;
1406 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1407 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1410 if (s390_stack_size)
1412 if (!s390_stack_guard)
1413 error ("-mstack-size implies use of -mstack-guard");
1414 else if (s390_stack_guard >= s390_stack_size)
1415 error ("stack size must be greater than the stack guard value");
1416 else if (s390_stack_size > 1 << 16)
1417 error ("stack size must not be greater than 64k");
1419 else if (s390_stack_guard)
1420 error ("-mstack-guard implies use of -mstack-size");
1422 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1423 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1424 target_flags |= MASK_LONG_DOUBLE_128;
1428 /* Map for smallest class containing reg regno. */
1430 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1431 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1432 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1433 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1434 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1435 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1436 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1437 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1438 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1439 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1440 ACCESS_REGS, ACCESS_REGS
1443 /* Return attribute type of insn. */
1445 static enum attr_type
1446 s390_safe_attr_type (rtx insn)
1448 if (recog_memoized (insn) >= 0)
1449 return get_attr_type (insn);
1454 /* Return true if DISP is a valid short displacement. */
1457 s390_short_displacement (rtx disp)
1459 /* No displacement is OK. */
1463 /* Integer displacement in range. */
1464 if (GET_CODE (disp) == CONST_INT)
1465 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1467 /* GOT offset is not OK, the GOT can be large. */
1468 if (GET_CODE (disp) == CONST
1469 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1470 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1471 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1474 /* All other symbolic constants are literal pool references,
1475 which are OK as the literal pool must be small. */
1476 if (GET_CODE (disp) == CONST)
1482 /* Decompose a RTL expression ADDR for a memory address into
1483 its components, returned in OUT.
1485 Returns false if ADDR is not a valid memory address, true
1486 otherwise. If OUT is NULL, don't return the components,
1487 but check for validity only.
1489 Note: Only addresses in canonical form are recognized.
1490 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1491 canonical form so that they will be recognized. */
1494 s390_decompose_address (rtx addr, struct s390_address *out)
1496 HOST_WIDE_INT offset = 0;
1497 rtx base = NULL_RTX;
1498 rtx indx = NULL_RTX;
1499 rtx disp = NULL_RTX;
1501 bool pointer = false;
1502 bool base_ptr = false;
1503 bool indx_ptr = false;
1504 bool literal_pool = false;
1506 /* We may need to substitute the literal pool base register into the address
1507 below. However, at this point we do not know which register is going to
1508 be used as base, so we substitute the arg pointer register. This is going
1509 to be treated as holding a pointer below -- it shouldn't be used for any
1511 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1513 /* Decompose address into base + index + displacement. */
1515 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1518 else if (GET_CODE (addr) == PLUS)
1520 rtx op0 = XEXP (addr, 0);
1521 rtx op1 = XEXP (addr, 1);
1522 enum rtx_code code0 = GET_CODE (op0);
1523 enum rtx_code code1 = GET_CODE (op1);
1525 if (code0 == REG || code0 == UNSPEC)
1527 if (code1 == REG || code1 == UNSPEC)
1529 indx = op0; /* index + base */
1535 base = op0; /* base + displacement */
1540 else if (code0 == PLUS)
1542 indx = XEXP (op0, 0); /* index + base + disp */
1543 base = XEXP (op0, 1);
1554 disp = addr; /* displacement */
1556 /* Extract integer part of displacement. */
1560 if (GET_CODE (disp) == CONST_INT)
1562 offset = INTVAL (disp);
1565 else if (GET_CODE (disp) == CONST
1566 && GET_CODE (XEXP (disp, 0)) == PLUS
1567 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1569 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1570 disp = XEXP (XEXP (disp, 0), 0);
1574 /* Strip off CONST here to avoid special case tests later. */
1575 if (disp && GET_CODE (disp) == CONST)
1576 disp = XEXP (disp, 0);
1578 /* We can convert literal pool addresses to
1579 displacements by basing them off the base register. */
1580 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1582 /* Either base or index must be free to hold the base register. */
1584 base = fake_pool_base, literal_pool = true;
1586 indx = fake_pool_base, literal_pool = true;
1590 /* Mark up the displacement. */
1591 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1592 UNSPEC_LTREL_OFFSET);
1595 /* Validate base register. */
1598 if (GET_CODE (base) == UNSPEC)
1599 switch (XINT (base, 1))
1603 disp = gen_rtx_UNSPEC (Pmode,
1604 gen_rtvec (1, XVECEXP (base, 0, 0)),
1605 UNSPEC_LTREL_OFFSET);
1609 base = XVECEXP (base, 0, 1);
1612 case UNSPEC_LTREL_BASE:
1613 if (XVECLEN (base, 0) == 1)
1614 base = fake_pool_base, literal_pool = true;
1616 base = XVECEXP (base, 0, 1);
1624 || (GET_MODE (base) != SImode
1625 && GET_MODE (base) != Pmode))
1628 if (REGNO (base) == STACK_POINTER_REGNUM
1629 || REGNO (base) == FRAME_POINTER_REGNUM
1630 || ((reload_completed || reload_in_progress)
1631 && frame_pointer_needed
1632 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1633 || REGNO (base) == ARG_POINTER_REGNUM
1635 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1636 pointer = base_ptr = true;
1638 if ((reload_completed || reload_in_progress)
1639 && base == cfun->machine->base_reg)
1640 pointer = base_ptr = literal_pool = true;
1643 /* Validate index register. */
1646 if (GET_CODE (indx) == UNSPEC)
1647 switch (XINT (indx, 1))
1651 disp = gen_rtx_UNSPEC (Pmode,
1652 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1653 UNSPEC_LTREL_OFFSET);
1657 indx = XVECEXP (indx, 0, 1);
1660 case UNSPEC_LTREL_BASE:
1661 if (XVECLEN (indx, 0) == 1)
1662 indx = fake_pool_base, literal_pool = true;
1664 indx = XVECEXP (indx, 0, 1);
1672 || (GET_MODE (indx) != SImode
1673 && GET_MODE (indx) != Pmode))
1676 if (REGNO (indx) == STACK_POINTER_REGNUM
1677 || REGNO (indx) == FRAME_POINTER_REGNUM
1678 || ((reload_completed || reload_in_progress)
1679 && frame_pointer_needed
1680 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1681 || REGNO (indx) == ARG_POINTER_REGNUM
1683 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1684 pointer = indx_ptr = true;
1686 if ((reload_completed || reload_in_progress)
1687 && indx == cfun->machine->base_reg)
1688 pointer = indx_ptr = literal_pool = true;
1691 /* Prefer to use pointer as base, not index. */
1692 if (base && indx && !base_ptr
1693 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1700 /* Validate displacement. */
1703 /* If virtual registers are involved, the displacement will change later
1704 anyway as the virtual registers get eliminated. This could make a
1705 valid displacement invalid, but it is more likely to make an invalid
1706 displacement valid, because we sometimes access the register save area
1707 via negative offsets to one of those registers.
1708 Thus we don't check the displacement for validity here. If after
1709 elimination the displacement turns out to be invalid after all,
1710 this is fixed up by reload in any case. */
1711 if (base != arg_pointer_rtx
1712 && indx != arg_pointer_rtx
1713 && base != return_address_pointer_rtx
1714 && indx != return_address_pointer_rtx
1715 && base != frame_pointer_rtx
1716 && indx != frame_pointer_rtx
1717 && base != virtual_stack_vars_rtx
1718 && indx != virtual_stack_vars_rtx)
1719 if (!DISP_IN_RANGE (offset))
1724 /* All the special cases are pointers. */
1727 /* In the small-PIC case, the linker converts @GOT
1728 and @GOTNTPOFF offsets to possible displacements. */
1729 if (GET_CODE (disp) == UNSPEC
1730 && (XINT (disp, 1) == UNSPEC_GOT
1731 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1738 /* Accept chunkified literal pool symbol references. */
1739 else if (cfun && cfun->machine
1740 && cfun->machine->decomposed_literal_pool_addresses_ok_p
1741 && GET_CODE (disp) == MINUS
1742 && GET_CODE (XEXP (disp, 0)) == LABEL_REF
1743 && GET_CODE (XEXP (disp, 1)) == LABEL_REF)
1748 /* Accept literal pool references. */
1749 else if (GET_CODE (disp) == UNSPEC
1750 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1752 orig_disp = gen_rtx_CONST (Pmode, disp);
1755 /* If we have an offset, make sure it does not
1756 exceed the size of the constant pool entry. */
1757 rtx sym = XVECEXP (disp, 0, 0);
1758 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1761 orig_disp = plus_constant (orig_disp, offset);
1776 out->disp = orig_disp;
1777 out->pointer = pointer;
1778 out->literal_pool = literal_pool;
1784 /* Decompose a RTL expression OP for a shift count into its components,
1785 and return the base register in BASE and the offset in OFFSET.
1787 Return true if OP is a valid shift count, false if not. */
1790 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
1792 HOST_WIDE_INT off = 0;
1794 /* We can have an integer constant, an address register,
1795 or a sum of the two. */
1796 if (GET_CODE (op) == CONST_INT)
1801 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
1803 off = INTVAL (XEXP (op, 1));
1806 while (op && GET_CODE (op) == SUBREG)
1807 op = SUBREG_REG (op);
1809 if (op && GET_CODE (op) != REG)
1821 /* Return true if CODE is a valid address without index. */
1824 s390_legitimate_address_without_index_p (rtx op)
1826 struct s390_address addr;
1828 if (!s390_decompose_address (XEXP (op, 0), &addr))
1836 /* Return 1 if OP is a valid operand for a C constraint, 0 else. */
1839 s390_extra_constraint_str (rtx op, int c, const char * str)
1841 struct s390_address addr;
1843 gcc_assert (c == str[0]);
1845 /* Check for offsettable variants of memory constraints. */
1848 /* Only accept non-volatile MEMs. */
1849 if (!MEM_P (op) || MEM_VOLATILE_P (op))
1852 if ((reload_completed || reload_in_progress)
1853 ? !offsettable_memref_p (op)
1854 : !offsettable_nonstrict_memref_p (op))
1860 /* Check for non-literal-pool variants of memory constraints. */
1863 if (GET_CODE (op) != MEM)
1865 if (!s390_decompose_address (XEXP (op, 0), &addr))
1867 if (addr.literal_pool)
1876 if (GET_CODE (op) != MEM)
1878 if (!s390_decompose_address (XEXP (op, 0), &addr))
1883 if (TARGET_LONG_DISPLACEMENT)
1885 if (!s390_short_displacement (addr.disp))
1891 if (GET_CODE (op) != MEM)
1894 if (TARGET_LONG_DISPLACEMENT)
1896 if (!s390_decompose_address (XEXP (op, 0), &addr))
1898 if (!s390_short_displacement (addr.disp))
1904 if (!TARGET_LONG_DISPLACEMENT)
1906 if (GET_CODE (op) != MEM)
1908 if (!s390_decompose_address (XEXP (op, 0), &addr))
1912 if (s390_short_displacement (addr.disp))
1917 if (!TARGET_LONG_DISPLACEMENT)
1919 if (GET_CODE (op) != MEM)
1921 /* Any invalid address here will be fixed up by reload,
1922 so accept it for the most generic constraint. */
1923 if (s390_decompose_address (XEXP (op, 0), &addr)
1924 && s390_short_displacement (addr.disp))
1929 if (TARGET_LONG_DISPLACEMENT)
1931 if (!s390_decompose_address (op, &addr))
1933 if (!s390_short_displacement (addr.disp))
1939 if (!TARGET_LONG_DISPLACEMENT)
1941 /* Any invalid address here will be fixed up by reload,
1942 so accept it for the most generic constraint. */
1943 if (s390_decompose_address (op, &addr)
1944 && s390_short_displacement (addr.disp))
1949 /* Simply check for the basic form of a shift count. Reload will
1950 take care of making sure we have a proper base register. */
1951 if (!s390_decompose_shift_count (op, NULL, NULL))
1962 /* Return true if VALUE matches the constraint STR. */
1965 s390_const_double_ok_for_constraint_p (rtx value,
1969 gcc_assert (c == str[0]);
1974 /* The floating point zero constant. */
1975 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
1976 && value == CONST0_RTX (GET_MODE (value)));
1983 /* Return true if VALUE matches the constraint STR. */
1986 s390_const_ok_for_constraint_p (HOST_WIDE_INT value,
1990 enum machine_mode mode, part_mode;
1992 int part, part_goal;
1994 gcc_assert (c == str[0]);
1999 return (unsigned int)value < 256;
2002 return (unsigned int)value < 4096;
2005 return value >= -32768 && value < 32768;
2008 return (TARGET_LONG_DISPLACEMENT ?
2009 (value >= -524288 && value <= 524287)
2010 : (value >= 0 && value <= 4095));
2012 return value == 2147483647;
2018 part_goal = str[1] - '0';
2022 case 'Q': part_mode = QImode; break;
2023 case 'H': part_mode = HImode; break;
2024 case 'S': part_mode = SImode; break;
2030 case 'H': mode = HImode; break;
2031 case 'S': mode = SImode; break;
2032 case 'D': mode = DImode; break;
2038 case '0': def = 0; break;
2039 case 'F': def = -1; break;
2043 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2046 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2049 if (part_goal != -1 && part_goal != part)
2061 return trunc_int_for_mode (value, SImode) == value;
2065 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2069 || s390_single_part (GEN_INT (value), DImode, SImode, -1) == 1;
2077 return legitimate_reload_constant_p (GEN_INT (value));
2086 /* Compute a (partial) cost for rtx X. Return true if the complete
2087 cost has been computed, and false if subexpressions should be
2088 scanned. In either case, *TOTAL contains the cost result.
2089 CODE contains GET_CODE (x), OUTER_CODE contains the code
2090 of the superexpression of x. */
2093 s390_rtx_costs (rtx x, int code, int outer_code, int *total)
2116 *total = COSTS_N_INSNS (1);
2121 /* Check for multiply and add. */
2122 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2123 && GET_CODE (XEXP (x, 0)) == MULT
2124 && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD)
2126 /* This is the multiply and add case. */
2127 if (GET_MODE (x) == DFmode)
2128 *total = s390_cost->madbr;
2130 *total = s390_cost->maebr;
2131 *total += rtx_cost (XEXP (XEXP (x, 0), 0), MULT)
2132 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT)
2133 + rtx_cost (XEXP (x, 1), code);
2134 return true; /* Do not do an additional recursive descent. */
2136 *total = COSTS_N_INSNS (1);
2140 switch (GET_MODE (x))
2144 rtx left = XEXP (x, 0);
2145 rtx right = XEXP (x, 1);
2146 if (GET_CODE (right) == CONST_INT
2147 && CONST_OK_FOR_K (INTVAL (right)))
2148 *total = s390_cost->mhi;
2149 else if (GET_CODE (left) == SIGN_EXTEND)
2150 *total = s390_cost->mh;
2152 *total = s390_cost->ms; /* msr, ms, msy */
2157 rtx left = XEXP (x, 0);
2158 rtx right = XEXP (x, 1);
2161 if (GET_CODE (right) == CONST_INT
2162 && CONST_OK_FOR_K (INTVAL (right)))
2163 *total = s390_cost->mghi;
2164 else if (GET_CODE (left) == SIGN_EXTEND)
2165 *total = s390_cost->msgf;
2167 *total = s390_cost->msg; /* msgr, msg */
2169 else /* TARGET_31BIT */
2171 if (GET_CODE (left) == SIGN_EXTEND
2172 && GET_CODE (right) == SIGN_EXTEND)
2173 /* mulsidi case: mr, m */
2174 *total = s390_cost->m;
2175 else if (GET_CODE (left) == ZERO_EXTEND
2176 && GET_CODE (right) == ZERO_EXTEND
2177 && TARGET_CPU_ZARCH)
2178 /* umulsidi case: ml, mlr */
2179 *total = s390_cost->ml;
2181 /* Complex calculation is required. */
2182 *total = COSTS_N_INSNS (40);
2188 *total = s390_cost->mult_df;
2191 *total = s390_cost->mxbr;
2200 if (GET_MODE (x) == TImode) /* 128 bit division */
2201 *total = s390_cost->dlgr;
2202 else if (GET_MODE (x) == DImode)
2204 rtx right = XEXP (x, 1);
2205 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2206 *total = s390_cost->dlr;
2207 else /* 64 by 64 bit division */
2208 *total = s390_cost->dlgr;
2210 else if (GET_MODE (x) == SImode) /* 32 bit division */
2211 *total = s390_cost->dlr;
2216 if (GET_MODE (x) == DImode)
2218 rtx right = XEXP (x, 1);
2219 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2221 *total = s390_cost->dsgfr;
2223 *total = s390_cost->dr;
2224 else /* 64 by 64 bit division */
2225 *total = s390_cost->dsgr;
2227 else if (GET_MODE (x) == SImode) /* 32 bit division */
2228 *total = s390_cost->dlr;
2229 else if (GET_MODE (x) == SFmode)
2231 if (TARGET_IEEE_FLOAT)
2232 *total = s390_cost->debr;
2233 else /* TARGET_IBM_FLOAT */
2234 *total = s390_cost->der;
2236 else if (GET_MODE (x) == DFmode)
2238 if (TARGET_IEEE_FLOAT)
2239 *total = s390_cost->ddbr;
2240 else /* TARGET_IBM_FLOAT */
2241 *total = s390_cost->ddr;
2243 else if (GET_MODE (x) == TFmode)
2245 if (TARGET_IEEE_FLOAT)
2246 *total = s390_cost->dxbr;
2247 else /* TARGET_IBM_FLOAT */
2248 *total = s390_cost->dxr;
2253 if (GET_MODE (x) == SFmode)
2254 *total = s390_cost->sqebr;
2255 else if (GET_MODE (x) == DFmode)
2256 *total = s390_cost->sqdbr;
2258 *total = s390_cost->sqxbr;
2263 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2264 || outer_code == PLUS || outer_code == MINUS
2265 || outer_code == COMPARE)
2270 *total = COSTS_N_INSNS (1);
2271 if (GET_CODE (XEXP (x, 0)) == AND
2272 && GET_CODE (XEXP (x, 1)) == CONST_INT
2273 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2275 rtx op0 = XEXP (XEXP (x, 0), 0);
2276 rtx op1 = XEXP (XEXP (x, 0), 1);
2277 rtx op2 = XEXP (x, 1);
2279 if (memory_operand (op0, GET_MODE (op0))
2280 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2282 if (register_operand (op0, GET_MODE (op0))
2283 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2293 /* Return the cost of an address rtx ADDR. */
2296 s390_address_cost (rtx addr)
2298 struct s390_address ad;
2299 if (!s390_decompose_address (addr, &ad))
2302 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2305 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2306 otherwise return 0. */
2309 tls_symbolic_operand (rtx op)
2311 if (GET_CODE (op) != SYMBOL_REF)
2313 return SYMBOL_REF_TLS_MODEL (op);
2316 /* Split DImode access register reference REG (on 64-bit) into its constituent
2317 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2318 gen_highpart cannot be used as they assume all registers are word-sized,
2319 while our access registers have only half that size. */
2322 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2324 gcc_assert (TARGET_64BIT);
2325 gcc_assert (ACCESS_REG_P (reg));
2326 gcc_assert (GET_MODE (reg) == DImode);
2327 gcc_assert (!(REGNO (reg) & 1));
2329 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2330 *hi = gen_rtx_REG (SImode, REGNO (reg));
2333 /* Return true if OP contains a symbol reference */
2336 symbolic_reference_mentioned_p (rtx op)
2341 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2344 fmt = GET_RTX_FORMAT (GET_CODE (op));
2345 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2351 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2352 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2356 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2363 /* Return true if OP contains a reference to a thread-local symbol. */
2366 tls_symbolic_reference_mentioned_p (rtx op)
2371 if (GET_CODE (op) == SYMBOL_REF)
2372 return tls_symbolic_operand (op);
2374 fmt = GET_RTX_FORMAT (GET_CODE (op));
2375 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2381 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2382 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2386 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2394 /* Return true if OP is a legitimate general operand when
2395 generating PIC code. It is given that flag_pic is on
2396 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2399 legitimate_pic_operand_p (rtx op)
2401 /* Accept all non-symbolic constants. */
2402 if (!SYMBOLIC_CONST (op))
2405 /* Reject everything else; must be handled
2406 via emit_symbolic_move. */
2410 /* Returns true if the constant value OP is a legitimate general operand.
2411 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2414 legitimate_constant_p (rtx op)
2416 /* Accept all non-symbolic constants. */
2417 if (!SYMBOLIC_CONST (op))
2420 /* Accept immediate LARL operands. */
2421 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2424 /* Thread-local symbols are never legal constants. This is
2425 so that emit_call knows that computing such addresses
2426 might require a function call. */
2427 if (TLS_SYMBOLIC_CONST (op))
2430 /* In the PIC case, symbolic constants must *not* be
2431 forced into the literal pool. We accept them here,
2432 so that they will be handled by emit_symbolic_move. */
2436 /* All remaining non-PIC symbolic constants are
2437 forced into the literal pool. */
2441 /* Determine if it's legal to put X into the constant pool. This
2442 is not possible if X contains the address of a symbol that is
2443 not constant (TLS) or not known at final link time (PIC). */
2446 s390_cannot_force_const_mem (rtx x)
2448 switch (GET_CODE (x))
2452 /* Accept all non-symbolic constants. */
2456 /* Labels are OK iff we are non-PIC. */
2457 return flag_pic != 0;
2460 /* 'Naked' TLS symbol references are never OK,
2461 non-TLS symbols are OK iff we are non-PIC. */
2462 if (tls_symbolic_operand (x))
2465 return flag_pic != 0;
2468 return s390_cannot_force_const_mem (XEXP (x, 0));
2471 return s390_cannot_force_const_mem (XEXP (x, 0))
2472 || s390_cannot_force_const_mem (XEXP (x, 1));
2475 switch (XINT (x, 1))
2477 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2478 case UNSPEC_LTREL_OFFSET:
2486 case UNSPEC_GOTNTPOFF:
2487 case UNSPEC_INDNTPOFF:
2490 /* If the literal pool shares the code section, be put
2491 execute template placeholders into the pool as well. */
2493 return TARGET_CPU_ZARCH;
2505 /* Returns true if the constant value OP is a legitimate general
2506 operand during and after reload. The difference to
2507 legitimate_constant_p is that this function will not accept
2508 a constant that would need to be forced to the literal pool
2509 before it can be used as operand. */
2512 legitimate_reload_constant_p (rtx op)
2514 /* Accept la(y) operands. */
2515 if (GET_CODE (op) == CONST_INT
2516 && DISP_IN_RANGE (INTVAL (op)))
2519 /* Accept l(g)hi/l(g)fi operands. */
2520 if (GET_CODE (op) == CONST_INT
2521 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2524 /* Accept lliXX operands. */
2526 && GET_CODE (op) == CONST_INT
2527 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2528 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2532 && GET_CODE (op) == CONST_INT
2533 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2534 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2537 /* Accept larl operands. */
2538 if (TARGET_CPU_ZARCH
2539 && larl_operand (op, VOIDmode))
2542 /* Accept lzXX operands. */
2543 if (GET_CODE (op) == CONST_DOUBLE
2544 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
2547 /* Accept double-word operands that can be split. */
2548 if (GET_CODE (op) == CONST_INT
2549 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2551 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2552 rtx hi = operand_subword (op, 0, 0, dword_mode);
2553 rtx lo = operand_subword (op, 1, 0, dword_mode);
2554 return legitimate_reload_constant_p (hi)
2555 && legitimate_reload_constant_p (lo);
2558 /* Everything else cannot be handled without reload. */
2562 /* Given an rtx OP being reloaded into a reg required to be in class CLASS,
2563 return the class of reg to actually use. */
2566 s390_preferred_reload_class (rtx op, enum reg_class class)
2568 switch (GET_CODE (op))
2570 /* Constants we cannot reload must be forced into the
2575 if (legitimate_reload_constant_p (op))
2580 /* If a symbolic constant or a PLUS is reloaded,
2581 it is most likely being used as an address, so
2582 prefer ADDR_REGS. If 'class' is not a superset
2583 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2588 if (reg_class_subset_p (ADDR_REGS, class))
2600 /* Return the register class of a scratch register needed to
2601 load IN into a register of class CLASS in MODE.
2603 We need a temporary when loading a PLUS expression which
2604 is not a legitimate operand of the LOAD ADDRESS instruction. */
2607 s390_secondary_input_reload_class (enum reg_class class,
2608 enum machine_mode mode, rtx in)
2610 if (s390_plus_operand (in, mode))
2613 if (reg_classes_intersect_p (FP_REGS, class)
2615 && GET_CODE (in) == MEM
2616 && GET_CODE (XEXP (in, 0)) == PLUS
2617 && GET_CODE (XEXP (XEXP (in, 0), 1)) == CONST_INT
2618 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (in, 0), 1))
2619 + GET_MODE_SIZE (mode) - 1))
2622 if (reg_classes_intersect_p (CC_REGS, class))
2623 return GENERAL_REGS;
2628 /* Return the register class of a scratch register needed to
2629 store a register of class CLASS in MODE into OUT:
2631 We need a temporary when storing a double-word to a
2632 non-offsettable memory address. */
2635 s390_secondary_output_reload_class (enum reg_class class,
2636 enum machine_mode mode, rtx out)
2638 if ((TARGET_64BIT ? (mode == TImode || mode == TFmode)
2639 : (mode == DImode || mode == DFmode))
2640 && reg_classes_intersect_p (GENERAL_REGS, class)
2641 && GET_CODE (out) == MEM
2642 && GET_CODE (XEXP (out, 0)) == PLUS
2643 && GET_CODE (XEXP (XEXP (out, 0), 0)) == PLUS
2644 && GET_CODE (XEXP (XEXP (out, 0), 1)) == CONST_INT
2645 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (out, 0), 1))
2646 + GET_MODE_SIZE (mode) - 1))
2649 if (reg_classes_intersect_p (FP_REGS, class)
2651 && GET_CODE (out) == MEM
2652 && GET_CODE (XEXP (out, 0)) == PLUS
2653 && GET_CODE (XEXP (XEXP (out, 0), 1)) == CONST_INT
2654 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (out, 0), 1))
2655 + GET_MODE_SIZE (mode) - 1))
2658 if (reg_classes_intersect_p (CC_REGS, class))
2659 return GENERAL_REGS;
2664 /* Generate code to load SRC, which is PLUS that is not a
2665 legitimate operand for the LA instruction, into TARGET.
2666 SCRATCH may be used as scratch register. */
2669 s390_expand_plus_operand (rtx target, rtx src,
2673 struct s390_address ad;
2675 /* src must be a PLUS; get its two operands. */
2676 gcc_assert (GET_CODE (src) == PLUS);
2677 gcc_assert (GET_MODE (src) == Pmode);
2679 /* Check if any of the two operands is already scheduled
2680 for replacement by reload. This can happen e.g. when
2681 float registers occur in an address. */
2682 sum1 = find_replacement (&XEXP (src, 0));
2683 sum2 = find_replacement (&XEXP (src, 1));
2684 src = gen_rtx_PLUS (Pmode, sum1, sum2);
2686 /* If the address is already strictly valid, there's nothing to do. */
2687 if (!s390_decompose_address (src, &ad)
2688 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
2689 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
2691 /* Otherwise, one of the operands cannot be an address register;
2692 we reload its value into the scratch register. */
2693 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
2695 emit_move_insn (scratch, sum1);
2698 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
2700 emit_move_insn (scratch, sum2);
2704 /* According to the way these invalid addresses are generated
2705 in reload.c, it should never happen (at least on s390) that
2706 *neither* of the PLUS components, after find_replacements
2707 was applied, is an address register. */
2708 if (sum1 == scratch && sum2 == scratch)
2714 src = gen_rtx_PLUS (Pmode, sum1, sum2);
2717 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
2718 is only ever performed on addresses, so we can mark the
2719 sum as legitimate for LA in any case. */
2720 s390_load_address (target, src);
2724 /* Return true if ADDR is a valid memory address.
2725 STRICT specifies whether strict register checking applies. */
2728 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2729 rtx addr, int strict)
2731 struct s390_address ad;
2732 if (!s390_decompose_address (addr, &ad))
2737 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
2740 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
2746 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
2747 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
2751 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
2752 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
2758 /* Return true if OP is a valid operand for the LA instruction.
2759 In 31-bit, we need to prove that the result is used as an
2760 address, as LA performs only a 31-bit addition. */
2763 legitimate_la_operand_p (rtx op)
2765 struct s390_address addr;
2766 if (!s390_decompose_address (op, &addr))
2769 return (TARGET_64BIT || addr.pointer);
2772 /* Return true if it is valid *and* preferable to use LA to
2773 compute the sum of OP1 and OP2. */
2776 preferred_la_operand_p (rtx op1, rtx op2)
2778 struct s390_address addr;
2780 if (op2 != const0_rtx)
2781 op1 = gen_rtx_PLUS (Pmode, op1, op2);
2783 if (!s390_decompose_address (op1, &addr))
2785 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
2787 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
2790 if (!TARGET_64BIT && !addr.pointer)
2796 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
2797 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
2803 /* Emit a forced load-address operation to load SRC into DST.
2804 This will use the LOAD ADDRESS instruction even in situations
2805 where legitimate_la_operand_p (SRC) returns false. */
2808 s390_load_address (rtx dst, rtx src)
2811 emit_move_insn (dst, src);
2813 emit_insn (gen_force_la_31 (dst, src));
2816 /* Return a legitimate reference for ORIG (an address) using the
2817 register REG. If REG is 0, a new pseudo is generated.
2819 There are two types of references that must be handled:
2821 1. Global data references must load the address from the GOT, via
2822 the PIC reg. An insn is emitted to do this load, and the reg is
2825 2. Static data references, constant pool addresses, and code labels
2826 compute the address as an offset from the GOT, whose base is in
2827 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
2828 differentiate them from global data objects. The returned
2829 address is the PIC reg + an unspec constant.
2831 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2832 reg also appears in the address. */
2835 legitimize_pic_address (rtx orig, rtx reg)
2841 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
2843 if (GET_CODE (addr) == LABEL_REF
2844 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
2846 /* This is a local symbol. */
2847 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
2849 /* Access local symbols PC-relative via LARL.
2850 This is the same as in the non-PIC case, so it is
2851 handled automatically ... */
2855 /* Access local symbols relative to the GOT. */
2857 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2859 if (reload_in_progress || reload_completed)
2860 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2862 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
2863 addr = gen_rtx_CONST (Pmode, addr);
2864 addr = force_const_mem (Pmode, addr);
2865 emit_move_insn (temp, addr);
2867 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2870 s390_load_address (reg, new);
2875 else if (GET_CODE (addr) == SYMBOL_REF)
2878 reg = gen_reg_rtx (Pmode);
2882 /* Assume GOT offset < 4k. This is handled the same way
2883 in both 31- and 64-bit code (@GOT). */
2885 if (reload_in_progress || reload_completed)
2886 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2888 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2889 new = gen_rtx_CONST (Pmode, new);
2890 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2891 new = gen_const_mem (Pmode, new);
2892 emit_move_insn (reg, new);
2895 else if (TARGET_CPU_ZARCH)
2897 /* If the GOT offset might be >= 4k, we determine the position
2898 of the GOT entry via a PC-relative LARL (@GOTENT). */
2900 rtx temp = gen_reg_rtx (Pmode);
2902 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
2903 new = gen_rtx_CONST (Pmode, new);
2904 emit_move_insn (temp, new);
2906 new = gen_const_mem (Pmode, temp);
2907 emit_move_insn (reg, new);
2912 /* If the GOT offset might be >= 4k, we have to load it
2913 from the literal pool (@GOT). */
2915 rtx temp = gen_reg_rtx (Pmode);
2917 if (reload_in_progress || reload_completed)
2918 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2920 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2921 addr = gen_rtx_CONST (Pmode, addr);
2922 addr = force_const_mem (Pmode, addr);
2923 emit_move_insn (temp, addr);
2925 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2926 new = gen_const_mem (Pmode, new);
2927 emit_move_insn (reg, new);
2933 if (GET_CODE (addr) == CONST)
2935 addr = XEXP (addr, 0);
2936 if (GET_CODE (addr) == UNSPEC)
2938 gcc_assert (XVECLEN (addr, 0) == 1);
2939 switch (XINT (addr, 1))
2941 /* If someone moved a GOT-relative UNSPEC
2942 out of the literal pool, force them back in. */
2945 new = force_const_mem (Pmode, orig);
2948 /* @GOT is OK as is if small. */
2951 new = force_const_mem (Pmode, orig);
2954 /* @GOTENT is OK as is. */
2958 /* @PLT is OK as is on 64-bit, must be converted to
2959 GOT-relative @PLTOFF on 31-bit. */
2961 if (!TARGET_CPU_ZARCH)
2963 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2965 if (reload_in_progress || reload_completed)
2966 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2968 addr = XVECEXP (addr, 0, 0);
2969 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
2971 addr = gen_rtx_CONST (Pmode, addr);
2972 addr = force_const_mem (Pmode, addr);
2973 emit_move_insn (temp, addr);
2975 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2978 s390_load_address (reg, new);
2984 /* Everything else cannot happen. */
2990 gcc_assert (GET_CODE (addr) == PLUS);
2992 if (GET_CODE (addr) == PLUS)
2994 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
2996 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
2997 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
2999 /* Check first to see if this is a constant offset
3000 from a local symbol reference. */
3001 if ((GET_CODE (op0) == LABEL_REF
3002 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3003 && GET_CODE (op1) == CONST_INT)
3005 if (TARGET_CPU_ZARCH && larl_operand (op0, VOIDmode))
3007 if (INTVAL (op1) & 1)
3009 /* LARL can't handle odd offsets, so emit a
3010 pair of LARL and LA. */
3011 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3013 if (!DISP_IN_RANGE (INTVAL (op1)))
3015 int even = INTVAL (op1) - 1;
3016 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3017 op0 = gen_rtx_CONST (Pmode, op0);
3021 emit_move_insn (temp, op0);
3022 new = gen_rtx_PLUS (Pmode, temp, op1);
3026 s390_load_address (reg, new);
3032 /* If the offset is even, we can just use LARL.
3033 This will happen automatically. */
3038 /* Access local symbols relative to the GOT. */
3040 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3042 if (reload_in_progress || reload_completed)
3043 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3045 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3047 addr = gen_rtx_PLUS (Pmode, addr, op1);
3048 addr = gen_rtx_CONST (Pmode, addr);
3049 addr = force_const_mem (Pmode, addr);
3050 emit_move_insn (temp, addr);
3052 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3055 s390_load_address (reg, new);
3061 /* Now, check whether it is a GOT relative symbol plus offset
3062 that was pulled out of the literal pool. Force it back in. */
3064 else if (GET_CODE (op0) == UNSPEC
3065 && GET_CODE (op1) == CONST_INT
3066 && XINT (op0, 1) == UNSPEC_GOTOFF)
3068 gcc_assert (XVECLEN (op0, 0) == 1);
3070 new = force_const_mem (Pmode, orig);
3073 /* Otherwise, compute the sum. */
3076 base = legitimize_pic_address (XEXP (addr, 0), reg);
3077 new = legitimize_pic_address (XEXP (addr, 1),
3078 base == reg ? NULL_RTX : reg);
3079 if (GET_CODE (new) == CONST_INT)
3080 new = plus_constant (base, INTVAL (new));
3083 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
3085 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
3086 new = XEXP (new, 1);
3088 new = gen_rtx_PLUS (Pmode, base, new);
3091 if (GET_CODE (new) == CONST)
3092 new = XEXP (new, 0);
3093 new = force_operand (new, 0);
3100 /* Load the thread pointer into a register. */
3103 s390_get_thread_pointer (void)
3105 rtx tp = gen_reg_rtx (Pmode);
3107 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3108 mark_reg_pointer (tp, BITS_PER_WORD);
3113 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3114 in s390_tls_symbol which always refers to __tls_get_offset.
3115 The returned offset is written to RESULT_REG and an USE rtx is
3116 generated for TLS_CALL. */
3118 static GTY(()) rtx s390_tls_symbol;
3121 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3125 gcc_assert (flag_pic);
3127 if (!s390_tls_symbol)
3128 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3130 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3131 gen_rtx_REG (Pmode, RETURN_REGNUM));
3133 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3134 CONST_OR_PURE_CALL_P (insn) = 1;
3137 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3138 this (thread-local) address. REG may be used as temporary. */
3141 legitimize_tls_address (rtx addr, rtx reg)
3143 rtx new, tls_call, temp, base, r2, insn;
3145 if (GET_CODE (addr) == SYMBOL_REF)
3146 switch (tls_symbolic_operand (addr))
3148 case TLS_MODEL_GLOBAL_DYNAMIC:
3150 r2 = gen_rtx_REG (Pmode, 2);
3151 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3152 new = gen_rtx_CONST (Pmode, tls_call);
3153 new = force_const_mem (Pmode, new);
3154 emit_move_insn (r2, new);
3155 s390_emit_tls_call_insn (r2, tls_call);
3156 insn = get_insns ();
3159 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3160 temp = gen_reg_rtx (Pmode);
3161 emit_libcall_block (insn, temp, r2, new);
3163 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3166 s390_load_address (reg, new);
3171 case TLS_MODEL_LOCAL_DYNAMIC:
3173 r2 = gen_rtx_REG (Pmode, 2);
3174 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3175 new = gen_rtx_CONST (Pmode, tls_call);
3176 new = force_const_mem (Pmode, new);
3177 emit_move_insn (r2, new);
3178 s390_emit_tls_call_insn (r2, tls_call);
3179 insn = get_insns ();
3182 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3183 temp = gen_reg_rtx (Pmode);
3184 emit_libcall_block (insn, temp, r2, new);
3186 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3187 base = gen_reg_rtx (Pmode);
3188 s390_load_address (base, new);
3190 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3191 new = gen_rtx_CONST (Pmode, new);
3192 new = force_const_mem (Pmode, new);
3193 temp = gen_reg_rtx (Pmode);
3194 emit_move_insn (temp, new);
3196 new = gen_rtx_PLUS (Pmode, base, temp);
3199 s390_load_address (reg, new);
3204 case TLS_MODEL_INITIAL_EXEC:
3207 /* Assume GOT offset < 4k. This is handled the same way
3208 in both 31- and 64-bit code. */
3210 if (reload_in_progress || reload_completed)
3211 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3213 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3214 new = gen_rtx_CONST (Pmode, new);
3215 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
3216 new = gen_const_mem (Pmode, new);
3217 temp = gen_reg_rtx (Pmode);
3218 emit_move_insn (temp, new);
3220 else if (TARGET_CPU_ZARCH)
3222 /* If the GOT offset might be >= 4k, we determine the position
3223 of the GOT entry via a PC-relative LARL. */
3225 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3226 new = gen_rtx_CONST (Pmode, new);
3227 temp = gen_reg_rtx (Pmode);
3228 emit_move_insn (temp, new);
3230 new = gen_const_mem (Pmode, temp);
3231 temp = gen_reg_rtx (Pmode);
3232 emit_move_insn (temp, new);
3236 /* If the GOT offset might be >= 4k, we have to load it
3237 from the literal pool. */
3239 if (reload_in_progress || reload_completed)
3240 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3242 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3243 new = gen_rtx_CONST (Pmode, new);
3244 new = force_const_mem (Pmode, new);
3245 temp = gen_reg_rtx (Pmode);
3246 emit_move_insn (temp, new);
3248 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3249 new = gen_const_mem (Pmode, new);
3251 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3252 temp = gen_reg_rtx (Pmode);
3253 emit_insn (gen_rtx_SET (Pmode, temp, new));
3257 /* In position-dependent code, load the absolute address of
3258 the GOT entry from the literal pool. */
3260 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3261 new = gen_rtx_CONST (Pmode, new);
3262 new = force_const_mem (Pmode, new);
3263 temp = gen_reg_rtx (Pmode);
3264 emit_move_insn (temp, new);
3267 new = gen_const_mem (Pmode, new);
3268 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3269 temp = gen_reg_rtx (Pmode);
3270 emit_insn (gen_rtx_SET (Pmode, temp, new));
3273 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3276 s390_load_address (reg, new);
3281 case TLS_MODEL_LOCAL_EXEC:
3282 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3283 new = gen_rtx_CONST (Pmode, new);
3284 new = force_const_mem (Pmode, new);
3285 temp = gen_reg_rtx (Pmode);
3286 emit_move_insn (temp, new);
3288 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3291 s390_load_address (reg, new);
3300 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3302 switch (XINT (XEXP (addr, 0), 1))
3304 case UNSPEC_INDNTPOFF:
3305 gcc_assert (TARGET_CPU_ZARCH);
3314 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3315 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3317 new = XEXP (XEXP (addr, 0), 0);
3318 if (GET_CODE (new) != SYMBOL_REF)
3319 new = gen_rtx_CONST (Pmode, new);
3321 new = legitimize_tls_address (new, reg);
3322 new = plus_constant (new, INTVAL (XEXP (XEXP (addr, 0), 1)));
3323 new = force_operand (new, 0);
3327 gcc_unreachable (); /* for now ... */
3332 /* Emit insns to move operands[1] into operands[0]. */
3335 emit_symbolic_move (rtx *operands)
3337 rtx temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
3339 if (GET_CODE (operands[0]) == MEM)
3340 operands[1] = force_reg (Pmode, operands[1]);
3341 else if (TLS_SYMBOLIC_CONST (operands[1]))
3342 operands[1] = legitimize_tls_address (operands[1], temp);
3344 operands[1] = legitimize_pic_address (operands[1], temp);
3347 /* Try machine-dependent ways of modifying an illegitimate address X
3348 to be legitimate. If we find one, return the new, valid address.
3350 OLDX is the address as it was before break_out_memory_refs was called.
3351 In some cases it is useful to look at this to decide what needs to be done.
3353 MODE is the mode of the operand pointed to by X.
3355 When -fpic is used, special handling is needed for symbolic references.
3356 See comments by legitimize_pic_address for details. */
3359 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3360 enum machine_mode mode ATTRIBUTE_UNUSED)
3362 rtx constant_term = const0_rtx;
3364 if (TLS_SYMBOLIC_CONST (x))
3366 x = legitimize_tls_address (x, 0);
3368 if (legitimate_address_p (mode, x, FALSE))
3371 else if (GET_CODE (x) == PLUS
3372 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3373 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3379 if (SYMBOLIC_CONST (x)
3380 || (GET_CODE (x) == PLUS
3381 && (SYMBOLIC_CONST (XEXP (x, 0))
3382 || SYMBOLIC_CONST (XEXP (x, 1)))))
3383 x = legitimize_pic_address (x, 0);
3385 if (legitimate_address_p (mode, x, FALSE))
3389 x = eliminate_constant_term (x, &constant_term);
3391 /* Optimize loading of large displacements by splitting them
3392 into the multiple of 4K and the rest; this allows the
3393 former to be CSE'd if possible.
3395 Don't do this if the displacement is added to a register
3396 pointing into the stack frame, as the offsets will
3397 change later anyway. */
3399 if (GET_CODE (constant_term) == CONST_INT
3400 && !TARGET_LONG_DISPLACEMENT
3401 && !DISP_IN_RANGE (INTVAL (constant_term))
3402 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3404 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3405 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3407 rtx temp = gen_reg_rtx (Pmode);
3408 rtx val = force_operand (GEN_INT (upper), temp);
3410 emit_move_insn (temp, val);
3412 x = gen_rtx_PLUS (Pmode, x, temp);
3413 constant_term = GEN_INT (lower);
3416 if (GET_CODE (x) == PLUS)
3418 if (GET_CODE (XEXP (x, 0)) == REG)
3420 rtx temp = gen_reg_rtx (Pmode);
3421 rtx val = force_operand (XEXP (x, 1), temp);
3423 emit_move_insn (temp, val);
3425 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3428 else if (GET_CODE (XEXP (x, 1)) == REG)
3430 rtx temp = gen_reg_rtx (Pmode);
3431 rtx val = force_operand (XEXP (x, 0), temp);
3433 emit_move_insn (temp, val);
3435 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3439 if (constant_term != const0_rtx)
3440 x = gen_rtx_PLUS (Pmode, x, constant_term);
3445 /* Try a machine-dependent way of reloading an illegitimate address AD
3446 operand. If we find one, push the reload and and return the new address.
3448 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3449 and TYPE is the reload type of the current reload. */
3452 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3453 int opnum, int type)
3455 if (!optimize || TARGET_LONG_DISPLACEMENT)
3458 if (GET_CODE (ad) == PLUS)
3460 rtx tem = simplify_binary_operation (PLUS, Pmode,
3461 XEXP (ad, 0), XEXP (ad, 1));
3466 if (GET_CODE (ad) == PLUS
3467 && GET_CODE (XEXP (ad, 0)) == REG
3468 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3469 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3471 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3472 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3475 cst = GEN_INT (upper);
3476 if (!legitimate_reload_constant_p (cst))
3477 cst = force_const_mem (Pmode, cst);
3479 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3480 new = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3482 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3483 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3484 opnum, (enum reload_type) type);
3491 /* Emit code to move LEN bytes from DST to SRC. */
3494 s390_expand_movmem (rtx dst, rtx src, rtx len)
3496 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3498 if (INTVAL (len) > 0)
3499 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3502 else if (TARGET_MVCLE)
3504 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3509 rtx dst_addr, src_addr, count, blocks, temp;
3510 rtx loop_start_label = gen_label_rtx ();
3511 rtx loop_end_label = gen_label_rtx ();
3512 rtx end_label = gen_label_rtx ();
3513 enum machine_mode mode;
3515 mode = GET_MODE (len);
3516 if (mode == VOIDmode)
3519 dst_addr = gen_reg_rtx (Pmode);
3520 src_addr = gen_reg_rtx (Pmode);
3521 count = gen_reg_rtx (mode);
3522 blocks = gen_reg_rtx (mode);
3524 convert_move (count, len, 1);
3525 emit_cmp_and_jump_insns (count, const0_rtx,
3526 EQ, NULL_RTX, mode, 1, end_label);
3528 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3529 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3530 dst = change_address (dst, VOIDmode, dst_addr);
3531 src = change_address (src, VOIDmode, src_addr);
3533 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3535 emit_move_insn (count, temp);
3537 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3539 emit_move_insn (blocks, temp);
3541 emit_cmp_and_jump_insns (blocks, const0_rtx,
3542 EQ, NULL_RTX, mode, 1, loop_end_label);
3544 emit_label (loop_start_label);
3546 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3547 s390_load_address (dst_addr,
3548 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3549 s390_load_address (src_addr,
3550 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
3552 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3554 emit_move_insn (blocks, temp);
3556 emit_cmp_and_jump_insns (blocks, const0_rtx,
3557 EQ, NULL_RTX, mode, 1, loop_end_label);
3559 emit_jump (loop_start_label);
3560 emit_label (loop_end_label);
3562 emit_insn (gen_movmem_short (dst, src,
3563 convert_to_mode (Pmode, count, 1)));
3564 emit_label (end_label);
3568 /* Emit code to set LEN bytes at DST to VAL.
3569 Make use of clrmem if VAL is zero. */
3572 s390_expand_setmem (rtx dst, rtx len, rtx val)
3574 gcc_assert (GET_CODE (len) != CONST_INT || INTVAL (len) > 0);
3575 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
3577 if (GET_CODE (len) == CONST_INT && INTVAL (len) <= 257)
3579 if (val == const0_rtx && INTVAL (len) <= 256)
3580 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
3583 /* Initialize memory by storing the first byte. */
3584 emit_move_insn (adjust_address (dst, QImode, 0), val);
3586 if (INTVAL (len) > 1)
3588 /* Initiate 1 byte overlap move.
3589 The first byte of DST is propagated through DSTP1.
3590 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3591 DST is set to size 1 so the rest of the memory location
3592 does not count as source operand. */
3593 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
3594 set_mem_size (dst, const1_rtx);
3596 emit_insn (gen_movmem_short (dstp1, dst,
3597 GEN_INT (INTVAL (len) - 2)));
3602 else if (TARGET_MVCLE)
3604 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
3605 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
3610 rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
3611 rtx loop_start_label = gen_label_rtx ();
3612 rtx loop_end_label = gen_label_rtx ();
3613 rtx end_label = gen_label_rtx ();
3614 enum machine_mode mode;
3616 mode = GET_MODE (len);
3617 if (mode == VOIDmode)
3620 dst_addr = gen_reg_rtx (Pmode);
3621 src_addr = gen_reg_rtx (Pmode);
3622 count = gen_reg_rtx (mode);
3623 blocks = gen_reg_rtx (mode);
3625 convert_move (count, len, 1);
3626 emit_cmp_and_jump_insns (count, const0_rtx,
3627 EQ, NULL_RTX, mode, 1, end_label);
3629 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3630 dst = change_address (dst, VOIDmode, dst_addr);
3632 if (val == const0_rtx)
3633 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3636 dstp1 = adjust_address (dst, VOIDmode, 1);
3637 set_mem_size (dst, const1_rtx);
3639 /* Initialize memory by storing the first byte. */
3640 emit_move_insn (adjust_address (dst, QImode, 0), val);
3642 /* If count is 1 we are done. */
3643 emit_cmp_and_jump_insns (count, const1_rtx,
3644 EQ, NULL_RTX, mode, 1, end_label);
3646 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1, 0);
3649 emit_move_insn (count, temp);
3651 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3653 emit_move_insn (blocks, temp);
3655 emit_cmp_and_jump_insns (blocks, const0_rtx,
3656 EQ, NULL_RTX, mode, 1, loop_end_label);
3658 emit_label (loop_start_label);
3660 if (val == const0_rtx)
3661 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
3663 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
3664 s390_load_address (dst_addr,
3665 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3667 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3669 emit_move_insn (blocks, temp);
3671 emit_cmp_and_jump_insns (blocks, const0_rtx,
3672 EQ, NULL_RTX, mode, 1, loop_end_label);
3674 emit_jump (loop_start_label);
3675 emit_label (loop_end_label);
3677 if (val == const0_rtx)
3678 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
3680 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
3681 emit_label (end_label);
3685 /* Emit code to compare LEN bytes at OP0 with those at OP1,
3686 and return the result in TARGET. */
3689 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
3691 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
3694 /* As the result of CMPINT is inverted compared to what we need,
3695 we have to swap the operands. */
3696 tmp = op0; op0 = op1; op1 = tmp;
3698 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3700 if (INTVAL (len) > 0)
3702 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
3703 emit_insn (gen_cmpint (target, ccreg));
3706 emit_move_insn (target, const0_rtx);
3708 else if (TARGET_MVCLE)
3710 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
3711 emit_insn (gen_cmpint (target, ccreg));
3715 rtx addr0, addr1, count, blocks, temp;
3716 rtx loop_start_label = gen_label_rtx ();
3717 rtx loop_end_label = gen_label_rtx ();
3718 rtx end_label = gen_label_rtx ();
3719 enum machine_mode mode;
3721 mode = GET_MODE (len);
3722 if (mode == VOIDmode)
3725 addr0 = gen_reg_rtx (Pmode);
3726 addr1 = gen_reg_rtx (Pmode);
3727 count = gen_reg_rtx (mode);
3728 blocks = gen_reg_rtx (mode);
3730 convert_move (count, len, 1);
3731 emit_cmp_and_jump_insns (count, const0_rtx,
3732 EQ, NULL_RTX, mode, 1, end_label);
3734 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
3735 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
3736 op0 = change_address (op0, VOIDmode, addr0);
3737 op1 = change_address (op1, VOIDmode, addr1);
3739 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3741 emit_move_insn (count, temp);
3743 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3745 emit_move_insn (blocks, temp);
3747 emit_cmp_and_jump_insns (blocks, const0_rtx,
3748 EQ, NULL_RTX, mode, 1, loop_end_label);
3750 emit_label (loop_start_label);
3752 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
3753 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
3754 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
3755 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
3756 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
3757 emit_jump_insn (temp);
3759 s390_load_address (addr0,
3760 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
3761 s390_load_address (addr1,
3762 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
3764 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3766 emit_move_insn (blocks, temp);
3768 emit_cmp_and_jump_insns (blocks, const0_rtx,
3769 EQ, NULL_RTX, mode, 1, loop_end_label);
3771 emit_jump (loop_start_label);
3772 emit_label (loop_end_label);
3774 emit_insn (gen_cmpmem_short (op0, op1,
3775 convert_to_mode (Pmode, count, 1)));
3776 emit_label (end_label);
3778 emit_insn (gen_cmpint (target, ccreg));
3783 /* Expand conditional increment or decrement using alc/slb instructions.
3784 Should generate code setting DST to either SRC or SRC + INCREMENT,
3785 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
3786 Returns true if successful, false otherwise.
3788 That makes it possible to implement some if-constructs without jumps e.g.:
3789 (borrow = CC0 | CC1 and carry = CC2 | CC3)
3790 unsigned int a, b, c;
3791 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
3792 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
3793 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
3794 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
3796 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
3797 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
3798 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
3799 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
3800 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
3803 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
3804 rtx dst, rtx src, rtx increment)
3806 enum machine_mode cmp_mode;
3807 enum machine_mode cc_mode;
3813 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
3814 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
3816 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
3817 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
3822 /* Try ADD LOGICAL WITH CARRY. */
3823 if (increment == const1_rtx)
3825 /* Determine CC mode to use. */
3826 if (cmp_code == EQ || cmp_code == NE)
3828 if (cmp_op1 != const0_rtx)
3830 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3831 NULL_RTX, 0, OPTAB_WIDEN);
3832 cmp_op1 = const0_rtx;
3835 cmp_code = cmp_code == EQ ? LEU : GTU;
3838 if (cmp_code == LTU || cmp_code == LEU)
3843 cmp_code = swap_condition (cmp_code);
3860 /* Emit comparison instruction pattern. */
3861 if (!register_operand (cmp_op0, cmp_mode))
3862 cmp_op0 = force_reg (cmp_mode, cmp_op0);
3864 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3865 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3866 /* We use insn_invalid_p here to add clobbers if required. */
3867 ret = insn_invalid_p (emit_insn (insn));
3870 /* Emit ALC instruction pattern. */
3871 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3872 gen_rtx_REG (cc_mode, CC_REGNUM),
3875 if (src != const0_rtx)
3877 if (!register_operand (src, GET_MODE (dst)))
3878 src = force_reg (GET_MODE (dst), src);
3880 src = gen_rtx_PLUS (GET_MODE (dst), src, const0_rtx);
3881 op_res = gen_rtx_PLUS (GET_MODE (dst), src, op_res);
3884 p = rtvec_alloc (2);
3886 gen_rtx_SET (VOIDmode, dst, op_res);
3888 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3889 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3894 /* Try SUBTRACT LOGICAL WITH BORROW. */
3895 if (increment == constm1_rtx)
3897 /* Determine CC mode to use. */
3898 if (cmp_code == EQ || cmp_code == NE)
3900 if (cmp_op1 != const0_rtx)
3902 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3903 NULL_RTX, 0, OPTAB_WIDEN);
3904 cmp_op1 = const0_rtx;
3907 cmp_code = cmp_code == EQ ? LEU : GTU;
3910 if (cmp_code == GTU || cmp_code == GEU)
3915 cmp_code = swap_condition (cmp_code);
3932 /* Emit comparison instruction pattern. */
3933 if (!register_operand (cmp_op0, cmp_mode))
3934 cmp_op0 = force_reg (cmp_mode, cmp_op0);
3936 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3937 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3938 /* We use insn_invalid_p here to add clobbers if required. */
3939 ret = insn_invalid_p (emit_insn (insn));
3942 /* Emit SLB instruction pattern. */
3943 if (!register_operand (src, GET_MODE (dst)))
3944 src = force_reg (GET_MODE (dst), src);
3946 op_res = gen_rtx_MINUS (GET_MODE (dst),
3947 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
3948 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3949 gen_rtx_REG (cc_mode, CC_REGNUM),
3951 p = rtvec_alloc (2);
3953 gen_rtx_SET (VOIDmode, dst, op_res);
3955 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3956 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3964 /* Expand code for the insv template. Return true if successful, false else. */
3967 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
3969 int bitsize = INTVAL (op1);
3970 int bitpos = INTVAL (op2);
3972 /* We need byte alignment. */
3973 if (bitsize % BITS_PER_UNIT)
3977 && memory_operand (dest, VOIDmode)
3978 && (register_operand (src, word_mode)
3979 || const_int_operand (src, VOIDmode)))
3981 /* Emit standard pattern if possible. */
3982 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
3983 if (GET_MODE_BITSIZE (mode) == bitsize)
3984 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
3986 /* (set (ze (mem)) (const_int)). */
3987 else if (const_int_operand (src, VOIDmode))
3989 int size = bitsize / BITS_PER_UNIT;
3990 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
3991 GET_MODE_SIZE (word_mode) - size);
3993 dest = adjust_address (dest, BLKmode, 0);
3994 set_mem_size (dest, GEN_INT (size));
3995 s390_expand_movmem (dest, src_mem, GEN_INT (size));
3998 /* (set (ze (mem)) (reg)). */
3999 else if (register_operand (src, word_mode))
4001 if (bitsize <= GET_MODE_BITSIZE (SImode))
4002 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4006 /* Emit st,stcmh sequence. */
4007 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4008 int size = stcmh_width / BITS_PER_UNIT;
4010 emit_move_insn (adjust_address (dest, SImode, size),
4011 gen_lowpart (SImode, src));
4012 set_mem_size (dest, GEN_INT (size));
4013 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4014 (stcmh_width), const0_rtx),
4015 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4016 (GET_MODE_BITSIZE (SImode))));
4025 /* (set (ze (reg)) (const_int)). */
4027 && register_operand (dest, word_mode)
4028 && (bitpos % 16) == 0
4029 && (bitsize % 16) == 0
4030 && const_int_operand (src, VOIDmode))
4032 HOST_WIDE_INT val = INTVAL (src);
4033 int regpos = bitpos + bitsize;
4035 while (regpos > bitpos)
4037 enum machine_mode putmode;
4040 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4045 putsize = GET_MODE_BITSIZE (putmode);
4047 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4050 gen_int_mode (val, putmode));
4053 gcc_assert (regpos == bitpos);
4060 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4061 register that holds VAL of mode MODE shifted by COUNT bits. */
4064 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4066 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4067 NULL_RTX, 1, OPTAB_DIRECT);
4068 return expand_simple_binop (SImode, ASHIFT, val, count,
4069 NULL_RTX, 1, OPTAB_DIRECT);
4072 /* Structure to hold the initial parameters for a compare_and_swap operation
4073 in HImode and QImode. */
4075 struct alignment_context
4077 rtx memsi; /* SI aligned memory location. */
4078 rtx shift; /* Bit offset with regard to lsb. */
4079 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4080 rtx modemaski; /* ~modemask */
4081 bool aligned; /* True if memory is aligned, false else. */
4084 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4085 structure AC for transparent simplifying, if the memory alignment is known
4086 to be at least 32bit. MEM is the memory location for the actual operation
4087 and MODE its mode. */
4090 init_alignment_context (struct alignment_context *ac, rtx mem,
4091 enum machine_mode mode)
4093 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4094 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4097 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4100 /* Alignment is unknown. */
4101 rtx byteoffset, addr, align;
4103 /* Force the address into a register. */
4104 addr = force_reg (Pmode, XEXP (mem, 0));
4106 /* Align it to SImode. */
4107 align = expand_simple_binop (Pmode, AND, addr,
4108 GEN_INT (-GET_MODE_SIZE (SImode)),
4109 NULL_RTX, 1, OPTAB_DIRECT);
4111 ac->memsi = gen_rtx_MEM (SImode, align);
4112 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4113 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4114 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4116 /* Calculate shiftcount. */
4117 byteoffset = expand_simple_binop (Pmode, AND, addr,
4118 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4119 NULL_RTX, 1, OPTAB_DIRECT);
4120 /* As we already have some offset, evaluate the remaining distance. */
4121 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4122 NULL_RTX, 1, OPTAB_DIRECT);
4125 /* Shift is the byte count, but we need the bitcount. */
4126 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4127 NULL_RTX, 1, OPTAB_DIRECT);
4128 /* Calculate masks. */
4129 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4130 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4131 NULL_RTX, 1, OPTAB_DIRECT);
4132 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4135 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4136 the memory location, CMP the old value to compare MEM with and NEW the value
4137 to set if CMP == MEM.
4138 CMP is never in memory for compare_and_swap_cc because
4139 expand_bool_compare_and_swap puts it into a register for later compare. */
4142 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new)
4144 struct alignment_context ac;
4145 rtx cmpv, newv, val, resv, cc;
4146 rtx res = gen_reg_rtx (SImode);
4147 rtx csloop = gen_label_rtx ();
4148 rtx csend = gen_label_rtx ();
4150 gcc_assert (register_operand (target, VOIDmode));
4151 gcc_assert (MEM_P (mem));
4153 init_alignment_context (&ac, mem, mode);
4155 /* Shift the values to the correct bit positions. */
4156 if (!(ac.aligned && MEM_P (cmp)))
4157 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4158 if (!(ac.aligned && MEM_P (new)))
4159 new = s390_expand_mask_and_shift (new, mode, ac.shift);
4161 /* Load full word. Subsequent loads are performed by CS. */
4162 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4163 NULL_RTX, 1, OPTAB_DIRECT);
4165 /* Start CS loop. */
4166 emit_label (csloop);
4167 /* val = "<mem>00..0<mem>"
4168 * cmp = "00..0<cmp>00..0"
4169 * new = "00..0<new>00..0"
4172 /* Patch cmp and new with val at correct position. */
4173 if (ac.aligned && MEM_P (cmp))
4175 cmpv = force_reg (SImode, val);
4176 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4179 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4180 NULL_RTX, 1, OPTAB_DIRECT));
4181 if (ac.aligned && MEM_P (new))
4183 newv = force_reg (SImode, val);
4184 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new);
4187 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new, val,
4188 NULL_RTX, 1, OPTAB_DIRECT));
4190 /* Emit compare_and_swap pattern. */
4191 emit_insn (gen_sync_compare_and_swap_ccsi (res, ac.memsi, cmpv, newv));
4193 /* Jump to end if we're done (likely?). */
4194 s390_emit_jump (csend, s390_emit_compare (EQ, cmpv, ac.memsi));
4196 /* Check for changes outside mode. */
4197 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4198 NULL_RTX, 1, OPTAB_DIRECT);
4199 cc = s390_emit_compare (NE, resv, val);
4200 emit_move_insn (val, resv);
4201 /* Loop internal if so. */
4202 s390_emit_jump (csloop, cc);
4206 /* Return the correct part of the bitfield. */
4207 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4208 NULL_RTX, 1, OPTAB_DIRECT), 1);
4211 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4212 and VAL the value to play with. If AFTER is true then store the the value
4213 MEM holds after the operation, if AFTER is false then store the value MEM
4214 holds before the operation. If TARGET is zero then discard that value, else
4215 store it to TARGET. */
4218 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4219 rtx target, rtx mem, rtx val, bool after)
4221 struct alignment_context ac;
4223 rtx new = gen_reg_rtx (SImode);
4224 rtx orig = gen_reg_rtx (SImode);
4225 rtx csloop = gen_label_rtx ();
4227 gcc_assert (!target || register_operand (target, VOIDmode));
4228 gcc_assert (MEM_P (mem));
4230 init_alignment_context (&ac, mem, mode);
4232 /* Shift val to the correct bit positions.
4233 Preserve "icm", but prevent "ex icm". */
4234 if (!(ac.aligned && code == SET && MEM_P (val)))
4235 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4237 /* Further preparation insns. */
4238 if (code == PLUS || code == MINUS)
4239 emit_move_insn (orig, val);
4240 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4241 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4242 NULL_RTX, 1, OPTAB_DIRECT);
4244 /* Load full word. Subsequent loads are performed by CS. */
4245 cmp = force_reg (SImode, ac.memsi);
4247 /* Start CS loop. */
4248 emit_label (csloop);
4249 emit_move_insn (new, cmp);
4251 /* Patch new with val at correct position. */
4256 val = expand_simple_binop (SImode, code, new, orig,
4257 NULL_RTX, 1, OPTAB_DIRECT);
4258 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4259 NULL_RTX, 1, OPTAB_DIRECT);
4262 if (ac.aligned && MEM_P (val))
4263 store_bit_field (new, GET_MODE_BITSIZE (mode), 0, SImode, val);
4266 new = expand_simple_binop (SImode, AND, new, ac.modemaski,
4267 NULL_RTX, 1, OPTAB_DIRECT);
4268 new = expand_simple_binop (SImode, IOR, new, val,
4269 NULL_RTX, 1, OPTAB_DIRECT);
4275 new = expand_simple_binop (SImode, code, new, val,
4276 NULL_RTX, 1, OPTAB_DIRECT);
4278 case MULT: /* NAND */
4279 new = expand_simple_binop (SImode, XOR, new, ac.modemask,
4280 NULL_RTX, 1, OPTAB_DIRECT);
4281 new = expand_simple_binop (SImode, AND, new, val,
4282 NULL_RTX, 1, OPTAB_DIRECT);
4287 /* Emit compare_and_swap pattern. */
4288 emit_insn (gen_sync_compare_and_swap_ccsi (cmp, ac.memsi, cmp, new));
4290 /* Loop until swapped (unlikely?). */
4291 s390_emit_jump (csloop, gen_rtx_fmt_ee (NE, CCZ1mode,
4292 gen_rtx_REG (CCZ1mode, CC_REGNUM),
4295 /* Return the correct part of the bitfield. */
4297 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4298 after ? new : cmp, ac.shift,
4299 NULL_RTX, 1, OPTAB_DIRECT), 1);
4302 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4303 We need to emit DTP-relative relocations. */
4305 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4308 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4313 fputs ("\t.long\t", file);
4316 fputs ("\t.quad\t", file);
4321 output_addr_const (file, x);
4322 fputs ("@DTPOFF", file);
4325 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4326 /* Implement TARGET_MANGLE_FUNDAMENTAL_TYPE. */
4329 s390_mangle_fundamental_type (tree type)
4331 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4332 && TARGET_LONG_DOUBLE_128)
4335 /* For all other types, use normal C++ mangling. */
4340 /* In the name of slightly smaller debug output, and to cater to
4341 general assembler lossage, recognize various UNSPEC sequences
4342 and turn them back into a direct symbol reference. */
4345 s390_delegitimize_address (rtx orig_x)
4349 if (GET_CODE (x) != MEM)
4353 if (GET_CODE (x) == PLUS
4354 && GET_CODE (XEXP (x, 1)) == CONST
4355 && GET_CODE (XEXP (x, 0)) == REG
4356 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4358 y = XEXP (XEXP (x, 1), 0);
4359 if (GET_CODE (y) == UNSPEC
4360 && XINT (y, 1) == UNSPEC_GOT)
4361 return XVECEXP (y, 0, 0);
4365 if (GET_CODE (x) == CONST)
4368 if (GET_CODE (y) == UNSPEC
4369 && XINT (y, 1) == UNSPEC_GOTENT)
4370 return XVECEXP (y, 0, 0);
4377 /* Output operand OP to stdio stream FILE.
4378 OP is an address (register + offset) which is not used to address data;
4379 instead the rightmost bits are interpreted as the value. */
4382 print_shift_count_operand (FILE *file, rtx op)
4384 HOST_WIDE_INT offset;
4387 /* Extract base register and offset. */
4388 if (!s390_decompose_shift_count (op, &base, &offset))
4394 gcc_assert (GET_CODE (base) == REG);
4395 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4396 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4399 /* Offsets are constricted to twelve bits. */
4400 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4402 fprintf (file, "(%s)", reg_names[REGNO (base)]);
4405 /* See 'get_some_local_dynamic_name'. */
4408 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4412 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4414 x = get_pool_constant (x);
4415 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4418 if (GET_CODE (x) == SYMBOL_REF
4419 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4421 cfun->machine->some_ld_name = XSTR (x, 0);
4428 /* Locate some local-dynamic symbol still in use by this function
4429 so that we can print its name in local-dynamic base patterns. */
4432 get_some_local_dynamic_name (void)
4436 if (cfun->machine->some_ld_name)
4437 return cfun->machine->some_ld_name;
4439 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4441 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4442 return cfun->machine->some_ld_name;
4447 /* Output machine-dependent UNSPECs occurring in address constant X
4448 in assembler syntax to stdio stream FILE. Returns true if the
4449 constant X could be recognized, false otherwise. */
4452 s390_output_addr_const_extra (FILE *file, rtx x)
4454 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4455 switch (XINT (x, 1))
4458 output_addr_const (file, XVECEXP (x, 0, 0));
4459 fprintf (file, "@GOTENT");
4462 output_addr_const (file, XVECEXP (x, 0, 0));
4463 fprintf (file, "@GOT");
4466 output_addr_const (file, XVECEXP (x, 0, 0));
4467 fprintf (file, "@GOTOFF");
4470 output_addr_const (file, XVECEXP (x, 0, 0));
4471 fprintf (file, "@PLT");
4474 output_addr_const (file, XVECEXP (x, 0, 0));
4475 fprintf (file, "@PLTOFF");
4478 output_addr_const (file, XVECEXP (x, 0, 0));
4479 fprintf (file, "@TLSGD");
4482 assemble_name (file, get_some_local_dynamic_name ());
4483 fprintf (file, "@TLSLDM");
4486 output_addr_const (file, XVECEXP (x, 0, 0));
4487 fprintf (file, "@DTPOFF");
4490 output_addr_const (file, XVECEXP (x, 0, 0));
4491 fprintf (file, "@NTPOFF");
4493 case UNSPEC_GOTNTPOFF:
4494 output_addr_const (file, XVECEXP (x, 0, 0));
4495 fprintf (file, "@GOTNTPOFF");
4497 case UNSPEC_INDNTPOFF:
4498 output_addr_const (file, XVECEXP (x, 0, 0));
4499 fprintf (file, "@INDNTPOFF");
4506 /* Output address operand ADDR in assembler syntax to
4507 stdio stream FILE. */
4510 print_operand_address (FILE *file, rtx addr)
4512 struct s390_address ad;
4514 if (!s390_decompose_address (addr, &ad)
4515 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
4516 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
4517 output_operand_lossage ("cannot decompose address");
4520 output_addr_const (file, ad.disp);
4522 fprintf (file, "0");
4524 if (ad.base && ad.indx)
4525 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
4526 reg_names[REGNO (ad.base)]);
4528 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4531 /* Output operand X in assembler syntax to stdio stream FILE.
4532 CODE specified the format flag. The following format flags
4535 'C': print opcode suffix for branch condition.
4536 'D': print opcode suffix for inverse branch condition.
4537 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4538 'G': print the size of the operand in bytes.
4539 'O': print only the displacement of a memory reference.
4540 'R': print only the base register of a memory reference.
4541 'S': print S-type memory reference (base+displacement).
4542 'N': print the second word of a DImode operand.
4543 'M': print the second word of a TImode operand.
4544 'Y': print shift count operand.
4546 'b': print integer X as if it's an unsigned byte.
4547 'x': print integer X as if it's an unsigned halfword.
4548 'h': print integer X as if it's a signed halfword.
4549 'i': print the first nonzero HImode part of X.
4550 'j': print the first HImode part unequal to -1 of X.
4551 'k': print the first nonzero SImode part of X.
4552 'm': print the first SImode part unequal to -1 of X.
4553 'o': print integer X as if it's an unsigned 32bit word. */
4556 print_operand (FILE *file, rtx x, int code)
4561 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
4565 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
4569 if (GET_CODE (x) == SYMBOL_REF)
4571 fprintf (file, "%s", ":tls_load:");
4572 output_addr_const (file, x);
4574 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
4576 fprintf (file, "%s", ":tls_gdcall:");
4577 output_addr_const (file, XVECEXP (x, 0, 0));
4579 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
4581 fprintf (file, "%s", ":tls_ldcall:");
4582 assemble_name (file, get_some_local_dynamic_name ());
4589 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
4594 struct s390_address ad;
4597 gcc_assert (GET_CODE (x) == MEM);
4598 ret = s390_decompose_address (XEXP (x, 0), &ad);
4600 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
4601 gcc_assert (!ad.indx);
4604 output_addr_const (file, ad.disp);
4606 fprintf (file, "0");
4612 struct s390_address ad;
4615 gcc_assert (GET_CODE (x) == MEM);
4616 ret = s390_decompose_address (XEXP (x, 0), &ad);
4618 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
4619 gcc_assert (!ad.indx);
4622 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
4624 fprintf (file, "0");
4630 struct s390_address ad;
4633 gcc_assert (GET_CODE (x) == MEM);
4634 ret = s390_decompose_address (XEXP (x, 0), &ad);
4636 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
4637 gcc_assert (!ad.indx);
4640 output_addr_const (file, ad.disp);
4642 fprintf (file, "0");
4645 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4650 if (GET_CODE (x) == REG)
4651 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4652 else if (GET_CODE (x) == MEM)
4653 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
4659 if (GET_CODE (x) == REG)
4660 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4661 else if (GET_CODE (x) == MEM)
4662 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
4668 print_shift_count_operand (file, x);
4672 switch (GET_CODE (x))
4675 fprintf (file, "%s", reg_names[REGNO (x)]);
4679 output_address (XEXP (x, 0));
4686 output_addr_const (file, x);
4691 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
4692 else if (code == 'x')
4693 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
4694 else if (code == 'h')
4695 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
4696 else if (code == 'i')
4697 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4698 s390_extract_part (x, HImode, 0));
4699 else if (code == 'j')
4700 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4701 s390_extract_part (x, HImode, -1));
4702 else if (code == 'k')
4703 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4704 s390_extract_part (x, SImode, 0));
4705 else if (code == 'm')
4706 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4707 s390_extract_part (x, SImode, -1));
4708 else if (code == 'o')
4709 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
4711 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
4715 gcc_assert (GET_MODE (x) == VOIDmode);
4717 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
4718 else if (code == 'x')
4719 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
4720 else if (code == 'h')
4721 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
4727 fatal_insn ("UNKNOWN in print_operand !?", x);
4732 /* Target hook for assembling integer objects. We need to define it
4733 here to work a round a bug in some versions of GAS, which couldn't
4734 handle values smaller than INT_MIN when printed in decimal. */
4737 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
4739 if (size == 8 && aligned_p
4740 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
4742 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
4746 return default_assemble_integer (x, size, aligned_p);
4749 /* Returns true if register REGNO is used for forming
4750 a memory address in expression X. */
4753 reg_used_in_mem_p (int regno, rtx x)
4755 enum rtx_code code = GET_CODE (x);
4761 if (refers_to_regno_p (regno, regno+1,
4765 else if (code == SET
4766 && GET_CODE (SET_DEST (x)) == PC)
4768 if (refers_to_regno_p (regno, regno+1,
4773 fmt = GET_RTX_FORMAT (code);
4774 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4777 && reg_used_in_mem_p (regno, XEXP (x, i)))
4780 else if (fmt[i] == 'E')
4781 for (j = 0; j < XVECLEN (x, i); j++)
4782 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
4788 /* Returns true if expression DEP_RTX sets an address register
4789 used by instruction INSN to address memory. */
4792 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
4796 if (GET_CODE (dep_rtx) == INSN)
4797 dep_rtx = PATTERN (dep_rtx);
4799 if (GET_CODE (dep_rtx) == SET)
4801 target = SET_DEST (dep_rtx);
4802 if (GET_CODE (target) == STRICT_LOW_PART)
4803 target = XEXP (target, 0);
4804 while (GET_CODE (target) == SUBREG)
4805 target = SUBREG_REG (target);
4807 if (GET_CODE (target) == REG)
4809 int regno = REGNO (target);
4811 if (s390_safe_attr_type (insn) == TYPE_LA)
4813 pat = PATTERN (insn);
4814 if (GET_CODE (pat) == PARALLEL)
4816 gcc_assert (XVECLEN (pat, 0) == 2);
4817 pat = XVECEXP (pat, 0, 0);
4819 gcc_assert (GET_CODE (pat) == SET);
4820 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
4822 else if (get_attr_atype (insn) == ATYPE_AGEN)
4823 return reg_used_in_mem_p (regno, PATTERN (insn));
4829 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
4832 s390_agen_dep_p (rtx dep_insn, rtx insn)
4834 rtx dep_rtx = PATTERN (dep_insn);
4837 if (GET_CODE (dep_rtx) == SET
4838 && addr_generation_dependency_p (dep_rtx, insn))
4840 else if (GET_CODE (dep_rtx) == PARALLEL)
4842 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
4844 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
4851 /* A C statement (sans semicolon) to update the integer scheduling priority
4852 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
4853 reduce the priority to execute INSN later. Do not define this macro if
4854 you do not need to adjust the scheduling priorities of insns.
4856 A STD instruction should be scheduled earlier,
4857 in order to use the bypass. */
4860 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
4862 if (! INSN_P (insn))
4865 if (s390_tune != PROCESSOR_2084_Z990
4866 && s390_tune != PROCESSOR_2094_Z9_109)
4869 switch (s390_safe_attr_type (insn))
4873 priority = priority << 3;
4877 priority = priority << 1;
4885 /* The number of instructions that can be issued per cycle. */
4888 s390_issue_rate (void)
4890 if (s390_tune == PROCESSOR_2084_Z990
4891 || s390_tune == PROCESSOR_2094_Z9_109)
4897 s390_first_cycle_multipass_dfa_lookahead (void)
4903 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
4904 Fix up MEMs as required. */
4907 annotate_constant_pool_refs (rtx *x)
4912 gcc_assert (GET_CODE (*x) != SYMBOL_REF
4913 || !CONSTANT_POOL_ADDRESS_P (*x));
4915 /* Literal pool references can only occur inside a MEM ... */
4916 if (GET_CODE (*x) == MEM)
4918 rtx memref = XEXP (*x, 0);
4920 if (GET_CODE (memref) == SYMBOL_REF
4921 && CONSTANT_POOL_ADDRESS_P (memref))
4923 rtx base = cfun->machine->base_reg;
4924 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
4927 *x = replace_equiv_address (*x, addr);
4931 if (GET_CODE (memref) == CONST
4932 && GET_CODE (XEXP (memref, 0)) == PLUS
4933 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
4934 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
4935 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
4937 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
4938 rtx sym = XEXP (XEXP (memref, 0), 0);
4939 rtx base = cfun->machine->base_reg;
4940 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4943 *x = replace_equiv_address (*x, plus_constant (addr, off));
4948 /* ... or a load-address type pattern. */
4949 if (GET_CODE (*x) == SET)
4951 rtx addrref = SET_SRC (*x);
4953 if (GET_CODE (addrref) == SYMBOL_REF
4954 && CONSTANT_POOL_ADDRESS_P (addrref))
4956 rtx base = cfun->machine->base_reg;
4957 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
4960 SET_SRC (*x) = addr;
4964 if (GET_CODE (addrref) == CONST
4965 && GET_CODE (XEXP (addrref, 0)) == PLUS
4966 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
4967 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
4968 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
4970 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
4971 rtx sym = XEXP (XEXP (addrref, 0), 0);
4972 rtx base = cfun->machine->base_reg;
4973 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4976 SET_SRC (*x) = plus_constant (addr, off);
4981 /* Annotate LTREL_BASE as well. */
4982 if (GET_CODE (*x) == UNSPEC
4983 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
4985 rtx base = cfun->machine->base_reg;
4986 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
4991 fmt = GET_RTX_FORMAT (GET_CODE (*x));
4992 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
4996 annotate_constant_pool_refs (&XEXP (*x, i));
4998 else if (fmt[i] == 'E')
5000 for (j = 0; j < XVECLEN (*x, i); j++)
5001 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5006 /* Split all branches that exceed the maximum distance.
5007 Returns true if this created a new literal pool entry. */
5010 s390_split_branches (void)
5012 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5013 int new_literal = 0, ret;
5014 rtx insn, pat, tmp, target;
5017 /* We need correct insn addresses. */
5019 shorten_branches (get_insns ());
5021 /* Find all branches that exceed 64KB, and split them. */
5023 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5025 if (GET_CODE (insn) != JUMP_INSN)
5028 pat = PATTERN (insn);
5029 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5030 pat = XVECEXP (pat, 0, 0);
5031 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5034 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5036 label = &SET_SRC (pat);
5038 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5040 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5041 label = &XEXP (SET_SRC (pat), 1);
5042 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5043 label = &XEXP (SET_SRC (pat), 2);
5050 if (get_attr_length (insn) <= 4)
5053 /* We are going to use the return register as scratch register,
5054 make sure it will be saved/restored by the prologue/epilogue. */
5055 cfun_frame_layout.save_return_addr_p = 1;
5060 tmp = force_const_mem (Pmode, *label);
5061 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5062 INSN_ADDRESSES_NEW (tmp, -1);
5063 annotate_constant_pool_refs (&PATTERN (tmp));
5070 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5071 UNSPEC_LTREL_OFFSET);
5072 target = gen_rtx_CONST (Pmode, target);
5073 target = force_const_mem (Pmode, target);
5074 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5075 INSN_ADDRESSES_NEW (tmp, -1);
5076 annotate_constant_pool_refs (&PATTERN (tmp));
5078 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5079 cfun->machine->base_reg),
5081 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5084 ret = validate_change (insn, label, target, 0);
5092 /* Find an annotated literal pool symbol referenced in RTX X,
5093 and store it at REF. Will abort if X contains references to
5094 more than one such pool symbol; multiple references to the same
5095 symbol are allowed, however.
5097 The rtx pointed to by REF must be initialized to NULL_RTX
5098 by the caller before calling this routine. */
5101 find_constant_pool_ref (rtx x, rtx *ref)
5106 /* Ignore LTREL_BASE references. */
5107 if (GET_CODE (x) == UNSPEC
5108 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5110 /* Likewise POOL_ENTRY insns. */
5111 if (GET_CODE (x) == UNSPEC_VOLATILE
5112 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5115 gcc_assert (GET_CODE (x) != SYMBOL_REF
5116 || !CONSTANT_POOL_ADDRESS_P (x));
5118 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5120 rtx sym = XVECEXP (x, 0, 0);
5121 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5122 && CONSTANT_POOL_ADDRESS_P (sym));
5124 if (*ref == NULL_RTX)
5127 gcc_assert (*ref == sym);
5132 fmt = GET_RTX_FORMAT (GET_CODE (x));
5133 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5137 find_constant_pool_ref (XEXP (x, i), ref);
5139 else if (fmt[i] == 'E')
5141 for (j = 0; j < XVECLEN (x, i); j++)
5142 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5147 /* Replace every reference to the annotated literal pool
5148 symbol REF in X by its base plus OFFSET. */
5151 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5156 gcc_assert (*x != ref);
5158 if (GET_CODE (*x) == UNSPEC
5159 && XINT (*x, 1) == UNSPEC_LTREF
5160 && XVECEXP (*x, 0, 0) == ref)
5162 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5166 if (GET_CODE (*x) == PLUS
5167 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5168 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5169 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5170 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5172 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5173 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5177 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5178 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5182 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5184 else if (fmt[i] == 'E')
5186 for (j = 0; j < XVECLEN (*x, i); j++)
5187 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5192 /* Check whether X contains an UNSPEC_LTREL_BASE.
5193 Return its constant pool symbol if found, NULL_RTX otherwise. */
5196 find_ltrel_base (rtx x)
5201 if (GET_CODE (x) == UNSPEC
5202 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5203 return XVECEXP (x, 0, 0);
5205 fmt = GET_RTX_FORMAT (GET_CODE (x));
5206 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5210 rtx fnd = find_ltrel_base (XEXP (x, i));
5214 else if (fmt[i] == 'E')
5216 for (j = 0; j < XVECLEN (x, i); j++)
5218 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5228 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5231 replace_ltrel_base (rtx *x)
5236 if (GET_CODE (*x) == UNSPEC
5237 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5239 *x = XVECEXP (*x, 0, 1);
5243 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5244 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5248 replace_ltrel_base (&XEXP (*x, i));
5250 else if (fmt[i] == 'E')
5252 for (j = 0; j < XVECLEN (*x, i); j++)
5253 replace_ltrel_base (&XVECEXP (*x, i, j));
5259 /* We keep a list of constants which we have to add to internal
5260 constant tables in the middle of large functions. */
5262 #define NR_C_MODES 8
5263 enum machine_mode constant_modes[NR_C_MODES] =
5274 struct constant *next;
5279 struct constant_pool
5281 struct constant_pool *next;
5286 struct constant *constants[NR_C_MODES];
5287 struct constant *execute;
5292 /* Allocate new constant_pool structure. */
5294 static struct constant_pool *
5295 s390_alloc_pool (void)
5297 struct constant_pool *pool;
5300 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5302 for (i = 0; i < NR_C_MODES; i++)
5303 pool->constants[i] = NULL;
5305 pool->execute = NULL;
5306 pool->label = gen_label_rtx ();
5307 pool->first_insn = NULL_RTX;
5308 pool->pool_insn = NULL_RTX;
5309 pool->insns = BITMAP_ALLOC (NULL);
5315 /* Create new constant pool covering instructions starting at INSN
5316 and chain it to the end of POOL_LIST. */
5318 static struct constant_pool *
5319 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5321 struct constant_pool *pool, **prev;
5323 pool = s390_alloc_pool ();
5324 pool->first_insn = insn;
5326 for (prev = pool_list; *prev; prev = &(*prev)->next)
5333 /* End range of instructions covered by POOL at INSN and emit
5334 placeholder insn representing the pool. */
5337 s390_end_pool (struct constant_pool *pool, rtx insn)
5339 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5342 insn = get_last_insn ();
5344 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5345 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5348 /* Add INSN to the list of insns covered by POOL. */
5351 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5353 bitmap_set_bit (pool->insns, INSN_UID (insn));
5356 /* Return pool out of POOL_LIST that covers INSN. */
5358 static struct constant_pool *
5359 s390_find_pool (struct constant_pool *pool_list, rtx insn)
5361 struct constant_pool *pool;
5363 for (pool = pool_list; pool; pool = pool->next)
5364 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5370 /* Add constant VAL of mode MODE to the constant pool POOL. */
5373 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5378 for (i = 0; i < NR_C_MODES; i++)
5379 if (constant_modes[i] == mode)
5381 gcc_assert (i != NR_C_MODES);
5383 for (c = pool->constants[i]; c != NULL; c = c->next)
5384 if (rtx_equal_p (val, c->value))
5389 c = (struct constant *) xmalloc (sizeof *c);
5391 c->label = gen_label_rtx ();
5392 c->next = pool->constants[i];
5393 pool->constants[i] = c;
5394 pool->size += GET_MODE_SIZE (mode);
5398 /* Find constant VAL of mode MODE in the constant pool POOL.
5399 Return an RTX describing the distance from the start of
5400 the pool to the location of the new constant. */
5403 s390_find_constant (struct constant_pool *pool, rtx val,
5404 enum machine_mode mode)
5410 for (i = 0; i < NR_C_MODES; i++)
5411 if (constant_modes[i] == mode)
5413 gcc_assert (i != NR_C_MODES);
5415 for (c = pool->constants[i]; c != NULL; c = c->next)
5416 if (rtx_equal_p (val, c->value))
5421 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5422 gen_rtx_LABEL_REF (Pmode, pool->label));
5423 offset = gen_rtx_CONST (Pmode, offset);
5427 /* Check whether INSN is an execute. Return the label_ref to its
5428 execute target template if so, NULL_RTX otherwise. */
5431 s390_execute_label (rtx insn)
5433 if (GET_CODE (insn) == INSN
5434 && GET_CODE (PATTERN (insn)) == PARALLEL
5435 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5436 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5437 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5442 /* Add execute target for INSN to the constant pool POOL. */
5445 s390_add_execute (struct constant_pool *pool, rtx insn)
5449 for (c = pool->execute; c != NULL; c = c->next)
5450 if (INSN_UID (insn) == INSN_UID (c->value))
5455 c = (struct constant *) xmalloc (sizeof *c);
5457 c->label = gen_label_rtx ();
5458 c->next = pool->execute;
5464 /* Find execute target for INSN in the constant pool POOL.
5465 Return an RTX describing the distance from the start of
5466 the pool to the location of the execute target. */
5469 s390_find_execute (struct constant_pool *pool, rtx insn)
5474 for (c = pool->execute; c != NULL; c = c->next)
5475 if (INSN_UID (insn) == INSN_UID (c->value))
5480 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5481 gen_rtx_LABEL_REF (Pmode, pool->label));
5482 offset = gen_rtx_CONST (Pmode, offset);
5486 /* For an execute INSN, extract the execute target template. */
5489 s390_execute_target (rtx insn)
5491 rtx pattern = PATTERN (insn);
5492 gcc_assert (s390_execute_label (insn));
5494 if (XVECLEN (pattern, 0) == 2)
5496 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
5500 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
5503 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
5504 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
5506 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
5512 /* Indicate that INSN cannot be duplicated. This is the case for
5513 execute insns that carry a unique label. */
5516 s390_cannot_copy_insn_p (rtx insn)
5518 rtx label = s390_execute_label (insn);
5519 return label && label != const0_rtx;
5522 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5523 do not emit the pool base label. */
5526 s390_dump_pool (struct constant_pool *pool, bool remote_label)
5529 rtx insn = pool->pool_insn;
5532 /* Switch to rodata section. */
5533 if (TARGET_CPU_ZARCH)
5535 insn = emit_insn_after (gen_pool_section_start (), insn);
5536 INSN_ADDRESSES_NEW (insn, -1);
5539 /* Ensure minimum pool alignment. */
5540 if (TARGET_CPU_ZARCH)
5541 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
5543 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
5544 INSN_ADDRESSES_NEW (insn, -1);
5546 /* Emit pool base label. */
5549 insn = emit_label_after (pool->label, insn);
5550 INSN_ADDRESSES_NEW (insn, -1);
5553 /* Dump constants in descending alignment requirement order,
5554 ensuring proper alignment for every constant. */
5555 for (i = 0; i < NR_C_MODES; i++)
5556 for (c = pool->constants[i]; c; c = c->next)
5558 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
5559 rtx value = c->value;
5560 if (GET_CODE (value) == CONST
5561 && GET_CODE (XEXP (value, 0)) == UNSPEC
5562 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
5563 && XVECLEN (XEXP (value, 0), 0) == 1)
5565 value = gen_rtx_MINUS (Pmode, XVECEXP (XEXP (value, 0), 0, 0),
5566 gen_rtx_LABEL_REF (VOIDmode, pool->label));
5567 value = gen_rtx_CONST (VOIDmode, value);
5570 insn = emit_label_after (c->label, insn);
5571 INSN_ADDRESSES_NEW (insn, -1);
5573 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
5574 gen_rtvec (1, value),
5575 UNSPECV_POOL_ENTRY);
5576 insn = emit_insn_after (value, insn);
5577 INSN_ADDRESSES_NEW (insn, -1);
5580 /* Ensure minimum alignment for instructions. */
5581 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
5582 INSN_ADDRESSES_NEW (insn, -1);
5584 /* Output in-pool execute template insns. */
5585 for (c = pool->execute; c; c = c->next)
5587 insn = emit_label_after (c->label, insn);
5588 INSN_ADDRESSES_NEW (insn, -1);
5590 insn = emit_insn_after (s390_execute_target (c->value), insn);
5591 INSN_ADDRESSES_NEW (insn, -1);
5594 /* Switch back to previous section. */
5595 if (TARGET_CPU_ZARCH)
5597 insn = emit_insn_after (gen_pool_section_end (), insn);
5598 INSN_ADDRESSES_NEW (insn, -1);
5601 insn = emit_barrier_after (insn);
5602 INSN_ADDRESSES_NEW (insn, -1);
5604 /* Remove placeholder insn. */
5605 remove_insn (pool->pool_insn);
5608 /* Free all memory used by POOL. */
5611 s390_free_pool (struct constant_pool *pool)
5613 struct constant *c, *next;
5616 for (i = 0; i < NR_C_MODES; i++)
5617 for (c = pool->constants[i]; c; c = next)
5623 for (c = pool->execute; c; c = next)
5629 BITMAP_FREE (pool->insns);
5634 /* Collect main literal pool. Return NULL on overflow. */
5636 static struct constant_pool *
5637 s390_mainpool_start (void)
5639 struct constant_pool *pool;
5642 pool = s390_alloc_pool ();
5644 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5646 if (GET_CODE (insn) == INSN
5647 && GET_CODE (PATTERN (insn)) == SET
5648 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
5649 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
5651 gcc_assert (!pool->pool_insn);
5652 pool->pool_insn = insn;
5655 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5657 s390_add_execute (pool, insn);
5659 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5661 rtx pool_ref = NULL_RTX;
5662 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5665 rtx constant = get_pool_constant (pool_ref);
5666 enum machine_mode mode = get_pool_mode (pool_ref);
5667 s390_add_constant (pool, constant, mode);
5672 gcc_assert (pool->pool_insn || pool->size == 0);
5674 if (pool->size >= 4096)
5676 /* We're going to chunkify the pool, so remove the main
5677 pool placeholder insn. */
5678 remove_insn (pool->pool_insn);
5680 s390_free_pool (pool);
5687 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5688 Modify the current function to output the pool constants as well as
5689 the pool register setup instruction. */
5692 s390_mainpool_finish (struct constant_pool *pool)
5694 rtx base_reg = cfun->machine->base_reg;
5697 /* If the pool is empty, we're done. */
5698 if (pool->size == 0)
5700 /* We don't actually need a base register after all. */
5701 cfun->machine->base_reg = NULL_RTX;
5703 if (pool->pool_insn)
5704 remove_insn (pool->pool_insn);
5705 s390_free_pool (pool);
5709 /* We need correct insn addresses. */
5710 shorten_branches (get_insns ());
5712 /* On zSeries, we use a LARL to load the pool register. The pool is
5713 located in the .rodata section, so we emit it after the function. */
5714 if (TARGET_CPU_ZARCH)
5716 insn = gen_main_base_64 (base_reg, pool->label);
5717 insn = emit_insn_after (insn, pool->pool_insn);
5718 INSN_ADDRESSES_NEW (insn, -1);
5719 remove_insn (pool->pool_insn);
5721 insn = get_last_insn ();
5722 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5723 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5725 s390_dump_pool (pool, 0);
5728 /* On S/390, if the total size of the function's code plus literal pool
5729 does not exceed 4096 bytes, we use BASR to set up a function base
5730 pointer, and emit the literal pool at the end of the function. */
5731 else if (INSN_ADDRESSES (INSN_UID (get_last_insn ()))
5732 + pool->size + 8 /* alignment slop */ < 4096)
5734 insn = gen_main_base_31_small (base_reg, pool->label);
5735 insn = emit_insn_after (insn, pool->pool_insn);
5736 INSN_ADDRESSES_NEW (insn, -1);
5737 remove_insn (pool->pool_insn);
5739 insn = emit_label_after (pool->label, insn);
5740 INSN_ADDRESSES_NEW (insn, -1);
5742 insn = get_last_insn ();
5743 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5744 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5746 s390_dump_pool (pool, 1);
5749 /* Otherwise, we emit an inline literal pool and use BASR to branch
5750 over it, setting up the pool register at the same time. */
5753 rtx pool_end = gen_label_rtx ();
5755 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
5756 insn = emit_insn_after (insn, pool->pool_insn);
5757 INSN_ADDRESSES_NEW (insn, -1);
5758 remove_insn (pool->pool_insn);
5760 insn = emit_label_after (pool->label, insn);
5761 INSN_ADDRESSES_NEW (insn, -1);
5763 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5764 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5766 insn = emit_label_after (pool_end, pool->pool_insn);
5767 INSN_ADDRESSES_NEW (insn, -1);
5769 s390_dump_pool (pool, 1);
5773 /* Replace all literal pool references. */
5775 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5778 replace_ltrel_base (&PATTERN (insn));
5780 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5782 rtx addr, pool_ref = NULL_RTX;
5783 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5786 if (s390_execute_label (insn))
5787 addr = s390_find_execute (pool, insn);
5789 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
5790 get_pool_mode (pool_ref));
5792 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
5793 INSN_CODE (insn) = -1;
5799 /* Free the pool. */
5800 s390_free_pool (pool);
5803 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5804 We have decided we cannot use this pool, so revert all changes
5805 to the current function that were done by s390_mainpool_start. */
5807 s390_mainpool_cancel (struct constant_pool *pool)
5809 /* We didn't actually change the instruction stream, so simply
5810 free the pool memory. */
5811 s390_free_pool (pool);
5815 /* Chunkify the literal pool. */
5817 #define S390_POOL_CHUNK_MIN 0xc00
5818 #define S390_POOL_CHUNK_MAX 0xe00
5820 static struct constant_pool *
5821 s390_chunkify_start (void)
5823 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
5826 rtx pending_ltrel = NULL_RTX;
5829 rtx (*gen_reload_base) (rtx, rtx) =
5830 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
5833 /* We need correct insn addresses. */
5835 shorten_branches (get_insns ());
5837 /* Scan all insns and move literals to pool chunks. */
5839 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5841 /* Check for pending LTREL_BASE. */
5844 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
5847 gcc_assert (ltrel_base == pending_ltrel);
5848 pending_ltrel = NULL_RTX;
5852 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5855 curr_pool = s390_start_pool (&pool_list, insn);
5857 s390_add_execute (curr_pool, insn);
5858 s390_add_pool_insn (curr_pool, insn);
5860 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5862 rtx pool_ref = NULL_RTX;
5863 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5866 rtx constant = get_pool_constant (pool_ref);
5867 enum machine_mode mode = get_pool_mode (pool_ref);
5870 curr_pool = s390_start_pool (&pool_list, insn);
5872 s390_add_constant (curr_pool, constant, mode);
5873 s390_add_pool_insn (curr_pool, insn);
5875 /* Don't split the pool chunk between a LTREL_OFFSET load
5876 and the corresponding LTREL_BASE. */
5877 if (GET_CODE (constant) == CONST
5878 && GET_CODE (XEXP (constant, 0)) == UNSPEC
5879 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
5881 gcc_assert (!pending_ltrel);
5882 pending_ltrel = pool_ref;
5887 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
5890 s390_add_pool_insn (curr_pool, insn);
5891 /* An LTREL_BASE must follow within the same basic block. */
5892 gcc_assert (!pending_ltrel);
5896 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
5897 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
5900 if (TARGET_CPU_ZARCH)
5902 if (curr_pool->size < S390_POOL_CHUNK_MAX)
5905 s390_end_pool (curr_pool, NULL_RTX);
5910 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
5911 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
5914 /* We will later have to insert base register reload insns.
5915 Those will have an effect on code size, which we need to
5916 consider here. This calculation makes rather pessimistic
5917 worst-case assumptions. */
5918 if (GET_CODE (insn) == CODE_LABEL)
5921 if (chunk_size < S390_POOL_CHUNK_MIN
5922 && curr_pool->size < S390_POOL_CHUNK_MIN)
5925 /* Pool chunks can only be inserted after BARRIERs ... */
5926 if (GET_CODE (insn) == BARRIER)
5928 s390_end_pool (curr_pool, insn);
5933 /* ... so if we don't find one in time, create one. */
5934 else if ((chunk_size > S390_POOL_CHUNK_MAX
5935 || curr_pool->size > S390_POOL_CHUNK_MAX))
5937 rtx label, jump, barrier;
5939 /* We can insert the barrier only after a 'real' insn. */
5940 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
5942 if (get_attr_length (insn) == 0)
5945 /* Don't separate LTREL_BASE from the corresponding
5946 LTREL_OFFSET load. */
5950 label = gen_label_rtx ();
5951 jump = emit_jump_insn_after (gen_jump (label), insn);
5952 barrier = emit_barrier_after (jump);
5953 insn = emit_label_after (label, barrier);
5954 JUMP_LABEL (jump) = label;
5955 LABEL_NUSES (label) = 1;
5957 INSN_ADDRESSES_NEW (jump, -1);
5958 INSN_ADDRESSES_NEW (barrier, -1);
5959 INSN_ADDRESSES_NEW (insn, -1);
5961 s390_end_pool (curr_pool, barrier);
5969 s390_end_pool (curr_pool, NULL_RTX);
5970 gcc_assert (!pending_ltrel);
5972 /* Find all labels that are branched into
5973 from an insn belonging to a different chunk. */
5975 far_labels = BITMAP_ALLOC (NULL);
5977 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5979 /* Labels marked with LABEL_PRESERVE_P can be target
5980 of non-local jumps, so we have to mark them.
5981 The same holds for named labels.
5983 Don't do that, however, if it is the label before
5986 if (GET_CODE (insn) == CODE_LABEL
5987 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
5989 rtx vec_insn = next_real_insn (insn);
5990 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
5991 PATTERN (vec_insn) : NULL_RTX;
5993 || !(GET_CODE (vec_pat) == ADDR_VEC
5994 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
5995 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
5998 /* If we have a direct jump (conditional or unconditional)
5999 or a casesi jump, check all potential targets. */
6000 else if (GET_CODE (insn) == JUMP_INSN)
6002 rtx pat = PATTERN (insn);
6003 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6004 pat = XVECEXP (pat, 0, 0);
6006 if (GET_CODE (pat) == SET)
6008 rtx label = JUMP_LABEL (insn);
6011 if (s390_find_pool (pool_list, label)
6012 != s390_find_pool (pool_list, insn))
6013 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6016 else if (GET_CODE (pat) == PARALLEL
6017 && XVECLEN (pat, 0) == 2
6018 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6019 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6020 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6022 /* Find the jump table used by this casesi jump. */
6023 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6024 rtx vec_insn = next_real_insn (vec_label);
6025 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6026 PATTERN (vec_insn) : NULL_RTX;
6028 && (GET_CODE (vec_pat) == ADDR_VEC
6029 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6031 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6033 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6035 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6037 if (s390_find_pool (pool_list, label)
6038 != s390_find_pool (pool_list, insn))
6039 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6046 /* Insert base register reload insns before every pool. */
6048 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6050 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6052 rtx insn = curr_pool->first_insn;
6053 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6056 /* Insert base register reload insns at every far label. */
6058 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6059 if (GET_CODE (insn) == CODE_LABEL
6060 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6062 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6065 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6067 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6072 BITMAP_FREE (far_labels);
6075 /* Recompute insn addresses. */
6077 init_insn_lengths ();
6078 shorten_branches (get_insns ());
6083 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6084 After we have decided to use this list, finish implementing
6085 all changes to the current function as required. */
6088 s390_chunkify_finish (struct constant_pool *pool_list)
6090 struct constant_pool *curr_pool = NULL;
6094 /* Replace all literal pool references. */
6096 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6099 replace_ltrel_base (&PATTERN (insn));
6101 curr_pool = s390_find_pool (pool_list, insn);
6105 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6107 rtx addr, pool_ref = NULL_RTX;
6108 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6111 if (s390_execute_label (insn))
6112 addr = s390_find_execute (curr_pool, insn);
6114 addr = s390_find_constant (curr_pool,
6115 get_pool_constant (pool_ref),
6116 get_pool_mode (pool_ref));
6118 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6119 INSN_CODE (insn) = -1;
6124 /* Dump out all literal pools. */
6126 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6127 s390_dump_pool (curr_pool, 0);
6129 /* Free pool list. */
6133 struct constant_pool *next = pool_list->next;
6134 s390_free_pool (pool_list);
6139 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6140 We have decided we cannot use this list, so revert all changes
6141 to the current function that were done by s390_chunkify_start. */
6144 s390_chunkify_cancel (struct constant_pool *pool_list)
6146 struct constant_pool *curr_pool = NULL;
6149 /* Remove all pool placeholder insns. */
6151 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6153 /* Did we insert an extra barrier? Remove it. */
6154 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6155 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6156 rtx label = NEXT_INSN (curr_pool->pool_insn);
6158 if (jump && GET_CODE (jump) == JUMP_INSN
6159 && barrier && GET_CODE (barrier) == BARRIER
6160 && label && GET_CODE (label) == CODE_LABEL
6161 && GET_CODE (PATTERN (jump)) == SET
6162 && SET_DEST (PATTERN (jump)) == pc_rtx
6163 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6164 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6167 remove_insn (barrier);
6168 remove_insn (label);
6171 remove_insn (curr_pool->pool_insn);
6174 /* Remove all base register reload insns. */
6176 for (insn = get_insns (); insn; )
6178 rtx next_insn = NEXT_INSN (insn);
6180 if (GET_CODE (insn) == INSN
6181 && GET_CODE (PATTERN (insn)) == SET
6182 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6183 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6189 /* Free pool list. */
6193 struct constant_pool *next = pool_list->next;
6194 s390_free_pool (pool_list);
6200 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6203 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6207 switch (GET_MODE_CLASS (mode))
6210 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6212 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6213 assemble_real (r, mode, align);
6217 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6226 /* Return an RTL expression representing the value of the return address
6227 for the frame COUNT steps up from the current frame. FRAME is the
6228 frame pointer of that frame. */
6231 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6236 /* Without backchain, we fail for all but the current frame. */
6238 if (!TARGET_BACKCHAIN && count > 0)
6241 /* For the current frame, we need to make sure the initial
6242 value of RETURN_REGNUM is actually saved. */
6246 /* On non-z architectures branch splitting could overwrite r14. */
6247 if (TARGET_CPU_ZARCH)
6248 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6251 cfun_frame_layout.save_return_addr_p = true;
6252 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6256 if (TARGET_PACKED_STACK)
6257 offset = -2 * UNITS_PER_WORD;
6259 offset = RETURN_REGNUM * UNITS_PER_WORD;
6261 addr = plus_constant (frame, offset);
6262 addr = memory_address (Pmode, addr);
6263 return gen_rtx_MEM (Pmode, addr);
6266 /* Return an RTL expression representing the back chain stored in
6267 the current stack frame. */
6270 s390_back_chain_rtx (void)
6274 gcc_assert (TARGET_BACKCHAIN);
6276 if (TARGET_PACKED_STACK)
6277 chain = plus_constant (stack_pointer_rtx,
6278 STACK_POINTER_OFFSET - UNITS_PER_WORD);
6280 chain = stack_pointer_rtx;
6282 chain = gen_rtx_MEM (Pmode, chain);
6286 /* Find first call clobbered register unused in a function.
6287 This could be used as base register in a leaf function
6288 or for holding the return address before epilogue. */
6291 find_unused_clobbered_reg (void)
6294 for (i = 0; i < 6; i++)
6295 if (!regs_ever_live[i])
6301 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6302 clobbered hard regs in SETREG. */
6305 s390_reg_clobbered_rtx (rtx setreg, rtx set_insn ATTRIBUTE_UNUSED, void *data)
6307 int *regs_ever_clobbered = (int *)data;
6308 unsigned int i, regno;
6309 enum machine_mode mode = GET_MODE (setreg);
6311 if (GET_CODE (setreg) == SUBREG)
6313 rtx inner = SUBREG_REG (setreg);
6314 if (!GENERAL_REG_P (inner))
6316 regno = subreg_regno (setreg);
6318 else if (GENERAL_REG_P (setreg))
6319 regno = REGNO (setreg);
6324 i < regno + HARD_REGNO_NREGS (regno, mode);
6326 regs_ever_clobbered[i] = 1;
6329 /* Walks through all basic blocks of the current function looking
6330 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6331 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6332 each of those regs. */
6335 s390_regs_ever_clobbered (int *regs_ever_clobbered)
6341 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6343 /* For non-leaf functions we have to consider all call clobbered regs to be
6345 if (!current_function_is_leaf)
6347 for (i = 0; i < 16; i++)
6348 regs_ever_clobbered[i] = call_really_used_regs[i];
6351 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6352 this work is done by liveness analysis (mark_regs_live_at_end).
6353 Special care is needed for functions containing landing pads. Landing pads
6354 may use the eh registers, but the code which sets these registers is not
6355 contained in that function. Hence s390_regs_ever_clobbered is not able to
6356 deal with this automatically. */
6357 if (current_function_calls_eh_return || cfun->machine->has_landing_pad_p)
6358 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6359 if (current_function_calls_eh_return
6360 || (cfun->machine->has_landing_pad_p
6361 && regs_ever_live [EH_RETURN_DATA_REGNO (i)]))
6362 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6364 /* For nonlocal gotos all call-saved registers have to be saved.
6365 This flag is also set for the unwinding code in libgcc.
6366 See expand_builtin_unwind_init. For regs_ever_live this is done by
6368 if (current_function_has_nonlocal_label)
6369 for (i = 0; i < 16; i++)
6370 if (!call_really_used_regs[i])
6371 regs_ever_clobbered[i] = 1;
6373 FOR_EACH_BB (cur_bb)
6375 FOR_BB_INSNS (cur_bb, cur_insn)
6377 if (INSN_P (cur_insn))
6378 note_stores (PATTERN (cur_insn),
6379 s390_reg_clobbered_rtx,
6380 regs_ever_clobbered);
6385 /* Determine the frame area which actually has to be accessed
6386 in the function epilogue. The values are stored at the
6387 given pointers AREA_BOTTOM (address of the lowest used stack
6388 address) and AREA_TOP (address of the first item which does
6389 not belong to the stack frame). */
6392 s390_frame_area (int *area_bottom, int *area_top)
6400 if (cfun_frame_layout.first_restore_gpr != -1)
6402 b = (cfun_frame_layout.gprs_offset
6403 + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
6404 t = b + (cfun_frame_layout.last_restore_gpr
6405 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
6408 if (TARGET_64BIT && cfun_save_high_fprs_p)
6410 b = MIN (b, cfun_frame_layout.f8_offset);
6411 t = MAX (t, (cfun_frame_layout.f8_offset
6412 + cfun_frame_layout.high_fprs * 8));
6416 for (i = 2; i < 4; i++)
6417 if (cfun_fpr_bit_p (i))
6419 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
6420 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
6427 /* Fill cfun->machine with info about register usage of current function.
6428 Return in CLOBBERED_REGS which GPRs are currently considered set. */
6431 s390_register_info (int clobbered_regs[])
6435 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
6436 cfun_frame_layout.fpr_bitmap = 0;
6437 cfun_frame_layout.high_fprs = 0;
6439 for (i = 24; i < 32; i++)
6440 if (regs_ever_live[i] && !global_regs[i])
6442 cfun_set_fpr_bit (i - 16);
6443 cfun_frame_layout.high_fprs++;
6446 /* Find first and last gpr to be saved. We trust regs_ever_live
6447 data, except that we don't save and restore global registers.
6449 Also, all registers with special meaning to the compiler need
6450 to be handled extra. */
6452 s390_regs_ever_clobbered (clobbered_regs);
6454 for (i = 0; i < 16; i++)
6455 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
6457 if (frame_pointer_needed)
6458 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
6461 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
6462 |= regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
6464 clobbered_regs[BASE_REGNUM]
6465 |= (cfun->machine->base_reg
6466 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
6468 clobbered_regs[RETURN_REGNUM]
6469 |= (!current_function_is_leaf
6470 || TARGET_TPF_PROFILING
6471 || cfun->machine->split_branches_pending_p
6472 || cfun_frame_layout.save_return_addr_p
6473 || current_function_calls_eh_return
6474 || current_function_stdarg);
6476 clobbered_regs[STACK_POINTER_REGNUM]
6477 |= (!current_function_is_leaf
6478 || TARGET_TPF_PROFILING
6479 || cfun_save_high_fprs_p
6480 || get_frame_size () > 0
6481 || current_function_calls_alloca
6482 || current_function_stdarg);
6484 for (i = 6; i < 16; i++)
6485 if (regs_ever_live[i] || clobbered_regs[i])
6487 for (j = 15; j > i; j--)
6488 if (regs_ever_live[j] || clobbered_regs[j])
6493 /* Nothing to save/restore. */
6494 cfun_frame_layout.first_save_gpr_slot = -1;
6495 cfun_frame_layout.last_save_gpr_slot = -1;
6496 cfun_frame_layout.first_save_gpr = -1;
6497 cfun_frame_layout.first_restore_gpr = -1;
6498 cfun_frame_layout.last_save_gpr = -1;
6499 cfun_frame_layout.last_restore_gpr = -1;
6503 /* Save slots for gprs from i to j. */
6504 cfun_frame_layout.first_save_gpr_slot = i;
6505 cfun_frame_layout.last_save_gpr_slot = j;
6507 for (i = cfun_frame_layout.first_save_gpr_slot;
6508 i < cfun_frame_layout.last_save_gpr_slot + 1;
6510 if (clobbered_regs[i])
6513 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
6514 if (clobbered_regs[j])
6517 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
6519 /* Nothing to save/restore. */
6520 cfun_frame_layout.first_save_gpr = -1;
6521 cfun_frame_layout.first_restore_gpr = -1;
6522 cfun_frame_layout.last_save_gpr = -1;
6523 cfun_frame_layout.last_restore_gpr = -1;
6527 /* Save / Restore from gpr i to j. */
6528 cfun_frame_layout.first_save_gpr = i;
6529 cfun_frame_layout.first_restore_gpr = i;
6530 cfun_frame_layout.last_save_gpr = j;
6531 cfun_frame_layout.last_restore_gpr = j;
6535 if (current_function_stdarg)
6537 /* Varargs functions need to save gprs 2 to 6. */
6538 if (cfun->va_list_gpr_size
6539 && current_function_args_info.gprs < GP_ARG_NUM_REG)
6541 int min_gpr = current_function_args_info.gprs;
6542 int max_gpr = min_gpr + cfun->va_list_gpr_size;
6543 if (max_gpr > GP_ARG_NUM_REG)
6544 max_gpr = GP_ARG_NUM_REG;
6546 if (cfun_frame_layout.first_save_gpr == -1
6547 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
6549 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
6550 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
6553 if (cfun_frame_layout.last_save_gpr == -1
6554 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
6556 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
6557 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
6561 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
6562 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
6563 && current_function_args_info.fprs < FP_ARG_NUM_REG)
6565 int min_fpr = current_function_args_info.fprs;
6566 int max_fpr = min_fpr + cfun->va_list_fpr_size;
6567 if (max_fpr > FP_ARG_NUM_REG)
6568 max_fpr = FP_ARG_NUM_REG;
6570 /* ??? This is currently required to ensure proper location
6571 of the fpr save slots within the va_list save area. */
6572 if (TARGET_PACKED_STACK)
6575 for (i = min_fpr; i < max_fpr; i++)
6576 cfun_set_fpr_bit (i);
6581 for (i = 2; i < 4; i++)
6582 if (regs_ever_live[i + 16] && !global_regs[i + 16])
6583 cfun_set_fpr_bit (i);
6586 /* Fill cfun->machine with info about frame of current function. */
6589 s390_frame_info (void)
6593 cfun_frame_layout.frame_size = get_frame_size ();
6594 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
6595 fatal_error ("total size of local variables exceeds architecture limit");
6597 if (!TARGET_PACKED_STACK)
6599 cfun_frame_layout.backchain_offset = 0;
6600 cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
6601 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
6602 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
6603 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
6606 else if (TARGET_BACKCHAIN) /* kernel stack layout */
6608 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
6610 cfun_frame_layout.gprs_offset
6611 = (cfun_frame_layout.backchain_offset
6612 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
6617 cfun_frame_layout.f4_offset
6618 = (cfun_frame_layout.gprs_offset
6619 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6621 cfun_frame_layout.f0_offset
6622 = (cfun_frame_layout.f4_offset
6623 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6627 /* On 31 bit we have to care about alignment of the
6628 floating point regs to provide fastest access. */
6629 cfun_frame_layout.f0_offset
6630 = ((cfun_frame_layout.gprs_offset
6631 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
6632 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6634 cfun_frame_layout.f4_offset
6635 = (cfun_frame_layout.f0_offset
6636 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6639 else /* no backchain */
6641 cfun_frame_layout.f4_offset
6642 = (STACK_POINTER_OFFSET
6643 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6645 cfun_frame_layout.f0_offset
6646 = (cfun_frame_layout.f4_offset
6647 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6649 cfun_frame_layout.gprs_offset
6650 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
6653 if (current_function_is_leaf
6654 && !TARGET_TPF_PROFILING
6655 && cfun_frame_layout.frame_size == 0
6656 && !cfun_save_high_fprs_p
6657 && !current_function_calls_alloca
6658 && !current_function_stdarg)
6661 if (!TARGET_PACKED_STACK)
6662 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
6663 + current_function_outgoing_args_size
6664 + cfun_frame_layout.high_fprs * 8);
6667 if (TARGET_BACKCHAIN)
6668 cfun_frame_layout.frame_size += UNITS_PER_WORD;
6670 /* No alignment trouble here because f8-f15 are only saved under
6672 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
6673 cfun_frame_layout.f4_offset),
6674 cfun_frame_layout.gprs_offset)
6675 - cfun_frame_layout.high_fprs * 8);
6677 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
6679 for (i = 0; i < 8; i++)
6680 if (cfun_fpr_bit_p (i))
6681 cfun_frame_layout.frame_size += 8;
6683 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
6685 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
6686 the frame size to sustain 8 byte alignment of stack frames. */
6687 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
6688 STACK_BOUNDARY / BITS_PER_UNIT - 1)
6689 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
6691 cfun_frame_layout.frame_size += current_function_outgoing_args_size;
6695 /* Generate frame layout. Fills in register and frame data for the current
6696 function in cfun->machine. This routine can be called multiple times;
6697 it will re-do the complete frame layout every time. */
6700 s390_init_frame_layout (void)
6702 HOST_WIDE_INT frame_size;
6704 int clobbered_regs[16];
6706 /* On S/390 machines, we may need to perform branch splitting, which
6707 will require both base and return address register. We have no
6708 choice but to assume we're going to need them until right at the
6709 end of the machine dependent reorg phase. */
6710 if (!TARGET_CPU_ZARCH)
6711 cfun->machine->split_branches_pending_p = true;
6715 frame_size = cfun_frame_layout.frame_size;
6717 /* Try to predict whether we'll need the base register. */
6718 base_used = cfun->machine->split_branches_pending_p
6719 || current_function_uses_const_pool
6720 || (!DISP_IN_RANGE (-frame_size)
6721 && !CONST_OK_FOR_K (-frame_size));
6723 /* Decide which register to use as literal pool base. In small
6724 leaf functions, try to use an unused call-clobbered register
6725 as base register to avoid save/restore overhead. */
6727 cfun->machine->base_reg = NULL_RTX;
6728 else if (current_function_is_leaf && !regs_ever_live[5])
6729 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
6731 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
6733 s390_register_info (clobbered_regs);
6736 while (frame_size != cfun_frame_layout.frame_size);
6739 /* Update frame layout. Recompute actual register save data based on
6740 current info and update regs_ever_live for the special registers.
6741 May be called multiple times, but may never cause *more* registers
6742 to be saved than s390_init_frame_layout allocated room for. */
6745 s390_update_frame_layout (void)
6747 int clobbered_regs[16];
6749 s390_register_info (clobbered_regs);
6751 regs_ever_live[BASE_REGNUM] = clobbered_regs[BASE_REGNUM];
6752 regs_ever_live[RETURN_REGNUM] = clobbered_regs[RETURN_REGNUM];
6753 regs_ever_live[STACK_POINTER_REGNUM] = clobbered_regs[STACK_POINTER_REGNUM];
6755 if (cfun->machine->base_reg)
6756 regs_ever_live[REGNO (cfun->machine->base_reg)] = 1;
6759 /* Return true if it is legal to put a value with MODE into REGNO. */
6762 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
6764 switch (REGNO_REG_CLASS (regno))
6767 if (REGNO_PAIR_OK (regno, mode))
6769 if (mode == SImode || mode == DImode)
6772 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
6777 if (FRAME_REGNO_P (regno) && mode == Pmode)
6782 if (REGNO_PAIR_OK (regno, mode))
6785 || (mode != TFmode && mode != TCmode))
6790 if (GET_MODE_CLASS (mode) == MODE_CC)
6794 if (REGNO_PAIR_OK (regno, mode))
6796 if (mode == SImode || mode == Pmode)
6807 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
6810 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
6812 /* Once we've decided upon a register to use as base register, it must
6813 no longer be used for any other purpose. */
6814 if (cfun->machine->base_reg)
6815 if (REGNO (cfun->machine->base_reg) == old_reg
6816 || REGNO (cfun->machine->base_reg) == new_reg)
6822 /* Maximum number of registers to represent a value of mode MODE
6823 in a register of class CLASS. */
6826 s390_class_max_nregs (enum reg_class class, enum machine_mode mode)
6831 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
6832 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
6834 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
6836 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
6840 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6843 /* Return true if register FROM can be eliminated via register TO. */
6846 s390_can_eliminate (int from, int to)
6848 /* On zSeries machines, we have not marked the base register as fixed.
6849 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
6850 If a function requires the base register, we say here that this
6851 elimination cannot be performed. This will cause reload to free
6852 up the base register (as if it were fixed). On the other hand,
6853 if the current function does *not* require the base register, we
6854 say here the elimination succeeds, which in turn allows reload
6855 to allocate the base register for any other purpose. */
6856 if (from == BASE_REGNUM && to == BASE_REGNUM)
6858 if (TARGET_CPU_ZARCH)
6860 s390_init_frame_layout ();
6861 return cfun->machine->base_reg == NULL_RTX;
6867 /* Everything else must point into the stack frame. */
6868 gcc_assert (to == STACK_POINTER_REGNUM
6869 || to == HARD_FRAME_POINTER_REGNUM);
6871 gcc_assert (from == FRAME_POINTER_REGNUM
6872 || from == ARG_POINTER_REGNUM
6873 || from == RETURN_ADDRESS_POINTER_REGNUM);
6875 /* Make sure we actually saved the return address. */
6876 if (from == RETURN_ADDRESS_POINTER_REGNUM)
6877 if (!current_function_calls_eh_return
6878 && !current_function_stdarg
6879 && !cfun_frame_layout.save_return_addr_p)
6885 /* Return offset between register FROM and TO initially after prolog. */
6888 s390_initial_elimination_offset (int from, int to)
6890 HOST_WIDE_INT offset;
6893 /* ??? Why are we called for non-eliminable pairs? */
6894 if (!s390_can_eliminate (from, to))
6899 case FRAME_POINTER_REGNUM:
6900 offset = (get_frame_size()
6901 + STACK_POINTER_OFFSET
6902 + current_function_outgoing_args_size);
6905 case ARG_POINTER_REGNUM:
6906 s390_init_frame_layout ();
6907 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
6910 case RETURN_ADDRESS_POINTER_REGNUM:
6911 s390_init_frame_layout ();
6912 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
6913 gcc_assert (index >= 0);
6914 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
6915 offset += index * UNITS_PER_WORD;
6929 /* Emit insn to save fpr REGNUM at offset OFFSET relative
6930 to register BASE. Return generated insn. */
6933 save_fpr (rtx base, int offset, int regnum)
6936 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6938 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
6939 set_mem_alias_set (addr, get_varargs_alias_set ());
6941 set_mem_alias_set (addr, get_frame_alias_set ());
6943 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
6946 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
6947 to register BASE. Return generated insn. */
6950 restore_fpr (rtx base, int offset, int regnum)
6953 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6954 set_mem_alias_set (addr, get_frame_alias_set ());
6956 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
6959 /* Generate insn to save registers FIRST to LAST into
6960 the register save area located at offset OFFSET
6961 relative to register BASE. */
6964 save_gprs (rtx base, int offset, int first, int last)
6966 rtx addr, insn, note;
6969 addr = plus_constant (base, offset);
6970 addr = gen_rtx_MEM (Pmode, addr);
6972 set_mem_alias_set (addr, get_frame_alias_set ());
6974 /* Special-case single register. */
6978 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
6980 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
6982 RTX_FRAME_RELATED_P (insn) = 1;
6987 insn = gen_store_multiple (addr,
6988 gen_rtx_REG (Pmode, first),
6989 GEN_INT (last - first + 1));
6991 if (first <= 6 && current_function_stdarg)
6992 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
6994 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
6997 set_mem_alias_set (mem, get_varargs_alias_set ());
7000 /* We need to set the FRAME_RELATED flag on all SETs
7001 inside the store-multiple pattern.
7003 However, we must not emit DWARF records for registers 2..5
7004 if they are stored for use by variable arguments ...
7006 ??? Unfortunately, it is not enough to simply not the
7007 FRAME_RELATED flags for those SETs, because the first SET
7008 of the PARALLEL is always treated as if it had the flag
7009 set, even if it does not. Therefore we emit a new pattern
7010 without those registers as REG_FRAME_RELATED_EXPR note. */
7014 rtx pat = PATTERN (insn);
7016 for (i = 0; i < XVECLEN (pat, 0); i++)
7017 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
7018 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7020 RTX_FRAME_RELATED_P (insn) = 1;
7024 addr = plus_constant (base, offset + (6 - first) * UNITS_PER_WORD);
7025 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7026 gen_rtx_REG (Pmode, 6),
7027 GEN_INT (last - 6 + 1));
7028 note = PATTERN (note);
7031 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7032 note, REG_NOTES (insn));
7034 for (i = 0; i < XVECLEN (note, 0); i++)
7035 if (GET_CODE (XVECEXP (note, 0, i)) == SET)
7036 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7038 RTX_FRAME_RELATED_P (insn) = 1;
7044 /* Generate insn to restore registers FIRST to LAST from
7045 the register save area located at offset OFFSET
7046 relative to register BASE. */
7049 restore_gprs (rtx base, int offset, int first, int last)
7053 addr = plus_constant (base, offset);
7054 addr = gen_rtx_MEM (Pmode, addr);
7055 set_mem_alias_set (addr, get_frame_alias_set ());
7057 /* Special-case single register. */
7061 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7063 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7068 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7070 GEN_INT (last - first + 1));
7074 /* Return insn sequence to load the GOT register. */
7076 static GTY(()) rtx got_symbol;
7078 s390_load_got (void)
7084 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7085 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7090 if (TARGET_CPU_ZARCH)
7092 emit_move_insn (pic_offset_table_rtx, got_symbol);
7098 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7099 UNSPEC_LTREL_OFFSET);
7100 offset = gen_rtx_CONST (Pmode, offset);
7101 offset = force_const_mem (Pmode, offset);
7103 emit_move_insn (pic_offset_table_rtx, offset);
7105 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7107 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7109 emit_move_insn (pic_offset_table_rtx, offset);
7112 insns = get_insns ();
7117 /* Expand the prologue into a bunch of separate insns. */
7120 s390_emit_prologue (void)
7128 /* Complete frame layout. */
7130 s390_update_frame_layout ();
7132 /* Annotate all constant pool references to let the scheduler know
7133 they implicitly use the base register. */
7135 push_topmost_sequence ();
7137 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7139 annotate_constant_pool_refs (&PATTERN (insn));
7141 pop_topmost_sequence ();
7143 /* Choose best register to use for temp use within prologue.
7144 See below for why TPF must use the register 1. */
7146 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7147 && !current_function_is_leaf
7148 && !TARGET_TPF_PROFILING)
7149 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7151 temp_reg = gen_rtx_REG (Pmode, 1);
7153 /* Save call saved gprs. */
7154 if (cfun_frame_layout.first_save_gpr != -1)
7156 insn = save_gprs (stack_pointer_rtx,
7157 cfun_frame_layout.gprs_offset +
7158 UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr
7159 - cfun_frame_layout.first_save_gpr_slot),
7160 cfun_frame_layout.first_save_gpr,
7161 cfun_frame_layout.last_save_gpr);
7165 /* Dummy insn to mark literal pool slot. */
7167 if (cfun->machine->base_reg)
7168 emit_insn (gen_main_pool (cfun->machine->base_reg));
7170 offset = cfun_frame_layout.f0_offset;
7172 /* Save f0 and f2. */
7173 for (i = 0; i < 2; i++)
7175 if (cfun_fpr_bit_p (i))
7177 save_fpr (stack_pointer_rtx, offset, i + 16);
7180 else if (!TARGET_PACKED_STACK)
7184 /* Save f4 and f6. */
7185 offset = cfun_frame_layout.f4_offset;
7186 for (i = 2; i < 4; i++)
7188 if (cfun_fpr_bit_p (i))
7190 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7193 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7194 therefore are not frame related. */
7195 if (!call_really_used_regs[i + 16])
7196 RTX_FRAME_RELATED_P (insn) = 1;
7198 else if (!TARGET_PACKED_STACK)
7202 if (TARGET_PACKED_STACK
7203 && cfun_save_high_fprs_p
7204 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7206 offset = (cfun_frame_layout.f8_offset
7207 + (cfun_frame_layout.high_fprs - 1) * 8);
7209 for (i = 15; i > 7 && offset >= 0; i--)
7210 if (cfun_fpr_bit_p (i))
7212 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7214 RTX_FRAME_RELATED_P (insn) = 1;
7217 if (offset >= cfun_frame_layout.f8_offset)
7221 if (!TARGET_PACKED_STACK)
7222 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7224 /* Decrement stack pointer. */
7226 if (cfun_frame_layout.frame_size > 0)
7228 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7230 if (s390_stack_size)
7232 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7233 & ~(s390_stack_guard - 1));
7234 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7235 GEN_INT (stack_check_mask));
7238 gen_cmpdi (t, const0_rtx);
7240 gen_cmpsi (t, const0_rtx);
7242 emit_insn (gen_conditional_trap (gen_rtx_EQ (CCmode,
7243 gen_rtx_REG (CCmode,
7249 if (s390_warn_framesize > 0
7250 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7251 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7252 current_function_name (), cfun_frame_layout.frame_size);
7254 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7255 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7257 /* Save incoming stack pointer into temp reg. */
7258 if (TARGET_BACKCHAIN || next_fpr)
7259 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7261 /* Subtract frame size from stack pointer. */
7263 if (DISP_IN_RANGE (INTVAL (frame_off)))
7265 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7266 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7268 insn = emit_insn (insn);
7272 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7273 frame_off = force_const_mem (Pmode, frame_off);
7275 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7276 annotate_constant_pool_refs (&PATTERN (insn));
7279 RTX_FRAME_RELATED_P (insn) = 1;
7281 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7282 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7283 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7284 GEN_INT (-cfun_frame_layout.frame_size))),
7287 /* Set backchain. */
7289 if (TARGET_BACKCHAIN)
7291 if (cfun_frame_layout.backchain_offset)
7292 addr = gen_rtx_MEM (Pmode,
7293 plus_constant (stack_pointer_rtx,
7294 cfun_frame_layout.backchain_offset));
7296 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7297 set_mem_alias_set (addr, get_frame_alias_set ());
7298 insn = emit_insn (gen_move_insn (addr, temp_reg));
7301 /* If we support asynchronous exceptions (e.g. for Java),
7302 we need to make sure the backchain pointer is set up
7303 before any possibly trapping memory access. */
7305 if (TARGET_BACKCHAIN && flag_non_call_exceptions)
7307 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7308 emit_insn (gen_rtx_CLOBBER (VOIDmode, addr));
7312 /* Save fprs 8 - 15 (64 bit ABI). */
7314 if (cfun_save_high_fprs_p && next_fpr)
7316 insn = emit_insn (gen_add2_insn (temp_reg,
7317 GEN_INT (cfun_frame_layout.f8_offset)));
7321 for (i = 24; i <= next_fpr; i++)
7322 if (cfun_fpr_bit_p (i - 16))
7324 rtx addr = plus_constant (stack_pointer_rtx,
7325 cfun_frame_layout.frame_size
7326 + cfun_frame_layout.f8_offset
7329 insn = save_fpr (temp_reg, offset, i);
7331 RTX_FRAME_RELATED_P (insn) = 1;
7333 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7334 gen_rtx_SET (VOIDmode,
7335 gen_rtx_MEM (DFmode, addr),
7336 gen_rtx_REG (DFmode, i)),
7341 /* Set frame pointer, if needed. */
7343 if (frame_pointer_needed)
7345 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7346 RTX_FRAME_RELATED_P (insn) = 1;
7349 /* Set up got pointer, if needed. */
7351 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
7353 rtx insns = s390_load_got ();
7355 for (insn = insns; insn; insn = NEXT_INSN (insn))
7357 annotate_constant_pool_refs (&PATTERN (insn));
7359 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
7366 if (TARGET_TPF_PROFILING)
7368 /* Generate a BAS instruction to serve as a function
7369 entry intercept to facilitate the use of tracing
7370 algorithms located at the branch target. */
7371 emit_insn (gen_prologue_tpf ());
7373 /* Emit a blockage here so that all code
7374 lies between the profiling mechanisms. */
7375 emit_insn (gen_blockage ());
7379 /* Expand the epilogue into a bunch of separate insns. */
7382 s390_emit_epilogue (bool sibcall)
7384 rtx frame_pointer, return_reg;
7385 int area_bottom, area_top, offset = 0;
7390 if (TARGET_TPF_PROFILING)
7393 /* Generate a BAS instruction to serve as a function
7394 entry intercept to facilitate the use of tracing
7395 algorithms located at the branch target. */
7397 /* Emit a blockage here so that all code
7398 lies between the profiling mechanisms. */
7399 emit_insn (gen_blockage ());
7401 emit_insn (gen_epilogue_tpf ());
7404 /* Check whether to use frame or stack pointer for restore. */
7406 frame_pointer = (frame_pointer_needed
7407 ? hard_frame_pointer_rtx : stack_pointer_rtx);
7409 s390_frame_area (&area_bottom, &area_top);
7411 /* Check whether we can access the register save area.
7412 If not, increment the frame pointer as required. */
7414 if (area_top <= area_bottom)
7416 /* Nothing to restore. */
7418 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
7419 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
7421 /* Area is in range. */
7422 offset = cfun_frame_layout.frame_size;
7426 rtx insn, frame_off;
7428 offset = area_bottom < 0 ? -area_bottom : 0;
7429 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
7431 if (DISP_IN_RANGE (INTVAL (frame_off)))
7433 insn = gen_rtx_SET (VOIDmode, frame_pointer,
7434 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
7435 insn = emit_insn (insn);
7439 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7440 frame_off = force_const_mem (Pmode, frame_off);
7442 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
7443 annotate_constant_pool_refs (&PATTERN (insn));
7447 /* Restore call saved fprs. */
7451 if (cfun_save_high_fprs_p)
7453 next_offset = cfun_frame_layout.f8_offset;
7454 for (i = 24; i < 32; i++)
7456 if (cfun_fpr_bit_p (i - 16))
7458 restore_fpr (frame_pointer,
7459 offset + next_offset, i);
7468 next_offset = cfun_frame_layout.f4_offset;
7469 for (i = 18; i < 20; i++)
7471 if (cfun_fpr_bit_p (i - 16))
7473 restore_fpr (frame_pointer,
7474 offset + next_offset, i);
7477 else if (!TARGET_PACKED_STACK)
7483 /* Return register. */
7485 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7487 /* Restore call saved gprs. */
7489 if (cfun_frame_layout.first_restore_gpr != -1)
7494 /* Check for global register and save them
7495 to stack location from where they get restored. */
7497 for (i = cfun_frame_layout.first_restore_gpr;
7498 i <= cfun_frame_layout.last_restore_gpr;
7501 /* These registers are special and need to be
7502 restored in any case. */
7503 if (i == STACK_POINTER_REGNUM
7504 || i == RETURN_REGNUM
7506 || (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
7511 addr = plus_constant (frame_pointer,
7512 offset + cfun_frame_layout.gprs_offset
7513 + (i - cfun_frame_layout.first_save_gpr_slot)
7515 addr = gen_rtx_MEM (Pmode, addr);
7516 set_mem_alias_set (addr, get_frame_alias_set ());
7517 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
7523 /* Fetch return address from stack before load multiple,
7524 this will do good for scheduling. */
7526 if (cfun_frame_layout.save_return_addr_p
7527 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
7528 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
7530 int return_regnum = find_unused_clobbered_reg();
7533 return_reg = gen_rtx_REG (Pmode, return_regnum);
7535 addr = plus_constant (frame_pointer,
7536 offset + cfun_frame_layout.gprs_offset
7538 - cfun_frame_layout.first_save_gpr_slot)
7540 addr = gen_rtx_MEM (Pmode, addr);
7541 set_mem_alias_set (addr, get_frame_alias_set ());
7542 emit_move_insn (return_reg, addr);
7546 insn = restore_gprs (frame_pointer,
7547 offset + cfun_frame_layout.gprs_offset
7548 + (cfun_frame_layout.first_restore_gpr
7549 - cfun_frame_layout.first_save_gpr_slot)
7551 cfun_frame_layout.first_restore_gpr,
7552 cfun_frame_layout.last_restore_gpr);
7559 /* Return to caller. */
7561 p = rtvec_alloc (2);
7563 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
7564 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
7565 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
7570 /* Return the size in bytes of a function argument of
7571 type TYPE and/or mode MODE. At least one of TYPE or
7572 MODE must be specified. */
7575 s390_function_arg_size (enum machine_mode mode, tree type)
7578 return int_size_in_bytes (type);
7580 /* No type info available for some library calls ... */
7581 if (mode != BLKmode)
7582 return GET_MODE_SIZE (mode);
7584 /* If we have neither type nor mode, abort */
7588 /* Return true if a function argument of type TYPE and mode MODE
7589 is to be passed in a floating-point register, if available. */
7592 s390_function_arg_float (enum machine_mode mode, tree type)
7594 int size = s390_function_arg_size (mode, type);
7598 /* Soft-float changes the ABI: no floating-point registers are used. */
7599 if (TARGET_SOFT_FLOAT)
7602 /* No type info available for some library calls ... */
7604 return mode == SFmode || mode == DFmode;
7606 /* The ABI says that record types with a single member are treated
7607 just like that member would be. */
7608 while (TREE_CODE (type) == RECORD_TYPE)
7610 tree field, single = NULL_TREE;
7612 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7614 if (TREE_CODE (field) != FIELD_DECL)
7617 if (single == NULL_TREE)
7618 single = TREE_TYPE (field);
7623 if (single == NULL_TREE)
7629 return TREE_CODE (type) == REAL_TYPE;
7632 /* Return true if a function argument of type TYPE and mode MODE
7633 is to be passed in an integer register, or a pair of integer
7634 registers, if available. */
7637 s390_function_arg_integer (enum machine_mode mode, tree type)
7639 int size = s390_function_arg_size (mode, type);
7643 /* No type info available for some library calls ... */
7645 return GET_MODE_CLASS (mode) == MODE_INT
7646 || (TARGET_SOFT_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT);
7648 /* We accept small integral (and similar) types. */
7649 if (INTEGRAL_TYPE_P (type)
7650 || POINTER_TYPE_P (type)
7651 || TREE_CODE (type) == OFFSET_TYPE
7652 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
7655 /* We also accept structs of size 1, 2, 4, 8 that are not
7656 passed in floating-point registers. */
7657 if (AGGREGATE_TYPE_P (type)
7658 && exact_log2 (size) >= 0
7659 && !s390_function_arg_float (mode, type))
7665 /* Return 1 if a function argument of type TYPE and mode MODE
7666 is to be passed by reference. The ABI specifies that only
7667 structures of size 1, 2, 4, or 8 bytes are passed by value,
7668 all other structures (and complex numbers) are passed by
7672 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
7673 enum machine_mode mode, tree type,
7674 bool named ATTRIBUTE_UNUSED)
7676 int size = s390_function_arg_size (mode, type);
7682 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
7685 if (TREE_CODE (type) == COMPLEX_TYPE
7686 || TREE_CODE (type) == VECTOR_TYPE)
7693 /* Update the data in CUM to advance over an argument of mode MODE and
7694 data type TYPE. (TYPE is null for libcalls where that information
7695 may not be available.). The boolean NAMED specifies whether the
7696 argument is a named argument (as opposed to an unnamed argument
7697 matching an ellipsis). */
7700 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7701 tree type, int named ATTRIBUTE_UNUSED)
7703 if (s390_function_arg_float (mode, type))
7707 else if (s390_function_arg_integer (mode, type))
7709 int size = s390_function_arg_size (mode, type);
7710 cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
7716 /* Define where to put the arguments to a function.
7717 Value is zero to push the argument on the stack,
7718 or a hard register in which to store the argument.
7720 MODE is the argument's machine mode.
7721 TYPE is the data type of the argument (as a tree).
7722 This is null for libcalls where that information may
7724 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7725 the preceding args and about the function being called.
7726 NAMED is nonzero if this argument is a named parameter
7727 (otherwise it is an extra parameter matching an ellipsis).
7729 On S/390, we use general purpose registers 2 through 6 to
7730 pass integer, pointer, and certain structure arguments, and
7731 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
7732 to pass floating point arguments. All remaining arguments
7733 are pushed to the stack. */
7736 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
7737 int named ATTRIBUTE_UNUSED)
7739 if (s390_function_arg_float (mode, type))
7741 if (cum->fprs + 1 > FP_ARG_NUM_REG)
7744 return gen_rtx_REG (mode, cum->fprs + 16);
7746 else if (s390_function_arg_integer (mode, type))
7748 int size = s390_function_arg_size (mode, type);
7749 int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
7751 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
7754 return gen_rtx_REG (mode, cum->gprs + 2);
7757 /* After the real arguments, expand_call calls us once again
7758 with a void_type_node type. Whatever we return here is
7759 passed as operand 2 to the call expanders.
7761 We don't need this feature ... */
7762 else if (type == void_type_node)
7768 /* Return true if return values of type TYPE should be returned
7769 in a memory buffer whose address is passed by the caller as
7770 hidden first argument. */
7773 s390_return_in_memory (tree type, tree fundecl ATTRIBUTE_UNUSED)
7775 /* We accept small integral (and similar) types. */
7776 if (INTEGRAL_TYPE_P (type)
7777 || POINTER_TYPE_P (type)
7778 || TREE_CODE (type) == OFFSET_TYPE
7779 || TREE_CODE (type) == REAL_TYPE)
7780 return int_size_in_bytes (type) > 8;
7782 /* Aggregates and similar constructs are always returned
7784 if (AGGREGATE_TYPE_P (type)
7785 || TREE_CODE (type) == COMPLEX_TYPE
7786 || TREE_CODE (type) == VECTOR_TYPE)
7789 /* ??? We get called on all sorts of random stuff from
7790 aggregate_value_p. We can't abort, but it's not clear
7791 what's safe to return. Pretend it's a struct I guess. */
7795 /* Define where to return a (scalar) value of type TYPE.
7796 If TYPE is null, define where to return a (scalar)
7797 value of mode MODE from a libcall. */
7800 s390_function_value (tree type, enum machine_mode mode)
7804 int unsignedp = TYPE_UNSIGNED (type);
7805 mode = promote_mode (type, TYPE_MODE (type), &unsignedp, 1);
7808 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT
7809 || GET_MODE_CLASS (mode) == MODE_FLOAT);
7810 gcc_assert (GET_MODE_SIZE (mode) <= 8);
7812 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
7813 return gen_rtx_REG (mode, 16);
7815 return gen_rtx_REG (mode, 2);
7819 /* Create and return the va_list datatype.
7821 On S/390, va_list is an array type equivalent to
7823 typedef struct __va_list_tag
7827 void *__overflow_arg_area;
7828 void *__reg_save_area;
7831 where __gpr and __fpr hold the number of general purpose
7832 or floating point arguments used up to now, respectively,
7833 __overflow_arg_area points to the stack location of the
7834 next argument passed on the stack, and __reg_save_area
7835 always points to the start of the register area in the
7836 call frame of the current function. The function prologue
7837 saves all registers used for argument passing into this
7838 area if the function uses variable arguments. */
7841 s390_build_builtin_va_list (void)
7843 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
7845 record = lang_hooks.types.make_type (RECORD_TYPE);
7848 build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
7850 f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"),
7851 long_integer_type_node);
7852 f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"),
7853 long_integer_type_node);
7854 f_ovf = build_decl (FIELD_DECL, get_identifier ("__overflow_arg_area"),
7856 f_sav = build_decl (FIELD_DECL, get_identifier ("__reg_save_area"),
7859 va_list_gpr_counter_field = f_gpr;
7860 va_list_fpr_counter_field = f_fpr;
7862 DECL_FIELD_CONTEXT (f_gpr) = record;
7863 DECL_FIELD_CONTEXT (f_fpr) = record;
7864 DECL_FIELD_CONTEXT (f_ovf) = record;
7865 DECL_FIELD_CONTEXT (f_sav) = record;
7867 TREE_CHAIN (record) = type_decl;
7868 TYPE_NAME (record) = type_decl;
7869 TYPE_FIELDS (record) = f_gpr;
7870 TREE_CHAIN (f_gpr) = f_fpr;
7871 TREE_CHAIN (f_fpr) = f_ovf;
7872 TREE_CHAIN (f_ovf) = f_sav;
7874 layout_type (record);
7876 /* The correct type is an array type of one element. */
7877 return build_array_type (record, build_index_type (size_zero_node));
7880 /* Implement va_start by filling the va_list structure VALIST.
7881 STDARG_P is always true, and ignored.
7882 NEXTARG points to the first anonymous stack argument.
7884 The following global variables are used to initialize
7885 the va_list structure:
7887 current_function_args_info:
7888 holds number of gprs and fprs used for named arguments.
7889 current_function_arg_offset_rtx:
7890 holds the offset of the first anonymous stack argument
7891 (relative to the virtual arg pointer). */
7894 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
7896 HOST_WIDE_INT n_gpr, n_fpr;
7898 tree f_gpr, f_fpr, f_ovf, f_sav;
7899 tree gpr, fpr, ovf, sav, t;
7901 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7902 f_fpr = TREE_CHAIN (f_gpr);
7903 f_ovf = TREE_CHAIN (f_fpr);
7904 f_sav = TREE_CHAIN (f_ovf);
7906 valist = build_va_arg_indirect_ref (valist);
7907 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7908 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7909 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7910 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7912 /* Count number of gp and fp argument registers used. */
7914 n_gpr = current_function_args_info.gprs;
7915 n_fpr = current_function_args_info.fprs;
7917 if (cfun->va_list_gpr_size)
7919 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
7920 build_int_cst (NULL_TREE, n_gpr));
7921 TREE_SIDE_EFFECTS (t) = 1;
7922 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7925 if (cfun->va_list_fpr_size)
7927 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
7928 build_int_cst (NULL_TREE, n_fpr));
7929 TREE_SIDE_EFFECTS (t) = 1;
7930 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7933 /* Find the overflow area. */
7934 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
7935 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
7937 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
7939 off = INTVAL (current_function_arg_offset_rtx);
7940 off = off < 0 ? 0 : off;
7941 if (TARGET_DEBUG_ARG)
7942 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
7943 (int)n_gpr, (int)n_fpr, off);
7945 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t, build_int_cst (NULL_TREE, off));
7947 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
7948 TREE_SIDE_EFFECTS (t) = 1;
7949 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7952 /* Find the register save area. */
7953 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
7954 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
7956 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
7957 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
7958 build_int_cst (NULL_TREE, -RETURN_REGNUM * UNITS_PER_WORD));
7960 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
7961 TREE_SIDE_EFFECTS (t) = 1;
7962 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7966 /* Implement va_arg by updating the va_list structure
7967 VALIST as required to retrieve an argument of type
7968 TYPE, and returning that argument.
7970 Generates code equivalent to:
7972 if (integral value) {
7973 if (size <= 4 && args.gpr < 5 ||
7974 size > 4 && args.gpr < 4 )
7975 ret = args.reg_save_area[args.gpr+8]
7977 ret = *args.overflow_arg_area++;
7978 } else if (float value) {
7980 ret = args.reg_save_area[args.fpr+64]
7982 ret = *args.overflow_arg_area++;
7983 } else if (aggregate value) {
7985 ret = *args.reg_save_area[args.gpr]
7987 ret = **args.overflow_arg_area++;
7991 s390_gimplify_va_arg (tree valist, tree type, tree *pre_p,
7992 tree *post_p ATTRIBUTE_UNUSED)
7994 tree f_gpr, f_fpr, f_ovf, f_sav;
7995 tree gpr, fpr, ovf, sav, reg, t, u;
7996 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
7997 tree lab_false, lab_over, addr;
7999 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8000 f_fpr = TREE_CHAIN (f_gpr);
8001 f_ovf = TREE_CHAIN (f_fpr);
8002 f_sav = TREE_CHAIN (f_ovf);
8004 valist = build_va_arg_indirect_ref (valist);
8005 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8006 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8007 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8008 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8010 size = int_size_in_bytes (type);
8012 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8014 if (TARGET_DEBUG_ARG)
8016 fprintf (stderr, "va_arg: aggregate type");
8020 /* Aggregates are passed by reference. */
8025 /* kernel stack layout on 31 bit: It is assumed here that no padding
8026 will be added by s390_frame_info because for va_args always an even
8027 number of gprs has to be saved r15-r2 = 14 regs. */
8028 sav_ofs = 2 * UNITS_PER_WORD;
8029 sav_scale = UNITS_PER_WORD;
8030 size = UNITS_PER_WORD;
8031 max_reg = GP_ARG_NUM_REG - n_reg;
8033 else if (s390_function_arg_float (TYPE_MODE (type), type))
8035 if (TARGET_DEBUG_ARG)
8037 fprintf (stderr, "va_arg: float type");
8041 /* FP args go in FP registers, if present. */
8045 sav_ofs = 16 * UNITS_PER_WORD;
8047 max_reg = FP_ARG_NUM_REG - n_reg;
8051 if (TARGET_DEBUG_ARG)
8053 fprintf (stderr, "va_arg: other type");
8057 /* Otherwise into GP registers. */
8060 n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8062 /* kernel stack layout on 31 bit: It is assumed here that no padding
8063 will be added by s390_frame_info because for va_args always an even
8064 number of gprs has to be saved r15-r2 = 14 regs. */
8065 sav_ofs = 2 * UNITS_PER_WORD;
8067 if (size < UNITS_PER_WORD)
8068 sav_ofs += UNITS_PER_WORD - size;
8070 sav_scale = UNITS_PER_WORD;
8071 max_reg = GP_ARG_NUM_REG - n_reg;
8074 /* Pull the value out of the saved registers ... */
8076 lab_false = create_artificial_label ();
8077 lab_over = create_artificial_label ();
8078 addr = create_tmp_var (ptr_type_node, "addr");
8079 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
8081 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
8082 t = build2 (GT_EXPR, boolean_type_node, reg, t);
8083 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8084 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8085 gimplify_and_add (t, pre_p);
8087 t = build2 (PLUS_EXPR, ptr_type_node, sav,
8088 fold_convert (ptr_type_node, size_int (sav_ofs)));
8089 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
8090 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
8091 t = build2 (PLUS_EXPR, ptr_type_node, t, fold_convert (ptr_type_node, u));
8093 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
8094 gimplify_and_add (t, pre_p);
8096 t = build1 (GOTO_EXPR, void_type_node, lab_over);
8097 gimplify_and_add (t, pre_p);
8099 t = build1 (LABEL_EXPR, void_type_node, lab_false);
8100 append_to_statement_list (t, pre_p);
8103 /* ... Otherwise out of the overflow area. */
8106 if (size < UNITS_PER_WORD)
8107 t = build2 (PLUS_EXPR, ptr_type_node, t,
8108 fold_convert (ptr_type_node, size_int (UNITS_PER_WORD - size)));
8110 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8112 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
8113 gimplify_and_add (u, pre_p);
8115 t = build2 (PLUS_EXPR, ptr_type_node, t,
8116 fold_convert (ptr_type_node, size_int (size)));
8117 t = build2 (MODIFY_EXPR, ptr_type_node, ovf, t);
8118 gimplify_and_add (t, pre_p);
8120 t = build1 (LABEL_EXPR, void_type_node, lab_over);
8121 append_to_statement_list (t, pre_p);
8124 /* Increment register save count. */
8126 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8127 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8128 gimplify_and_add (u, pre_p);
8132 t = build_pointer_type (build_pointer_type (type));
8133 addr = fold_convert (t, addr);
8134 addr = build_va_arg_indirect_ref (addr);
8138 t = build_pointer_type (type);
8139 addr = fold_convert (t, addr);
8142 return build_va_arg_indirect_ref (addr);
8150 S390_BUILTIN_THREAD_POINTER,
8151 S390_BUILTIN_SET_THREAD_POINTER,
8156 static unsigned int const code_for_builtin_64[S390_BUILTIN_max] = {
8161 static unsigned int const code_for_builtin_31[S390_BUILTIN_max] = {
8167 s390_init_builtins (void)
8171 ftype = build_function_type (ptr_type_node, void_list_node);
8172 lang_hooks.builtin_function ("__builtin_thread_pointer", ftype,
8173 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8176 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8177 lang_hooks.builtin_function ("__builtin_set_thread_pointer", ftype,
8178 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8182 /* Expand an expression EXP that calls a built-in function,
8183 with result going to TARGET if that's convenient
8184 (and in mode MODE if that's convenient).
8185 SUBTARGET may be used as the target for computing one of EXP's operands.
8186 IGNORE is nonzero if the value is to be ignored. */
8189 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8190 enum machine_mode mode ATTRIBUTE_UNUSED,
8191 int ignore ATTRIBUTE_UNUSED)
8195 unsigned int const *code_for_builtin =
8196 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8198 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8199 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8200 tree arglist = TREE_OPERAND (exp, 1);
8201 enum insn_code icode;
8202 rtx op[MAX_ARGS], pat;
8206 if (fcode >= S390_BUILTIN_max)
8207 internal_error ("bad builtin fcode");
8208 icode = code_for_builtin[fcode];
8210 internal_error ("bad builtin fcode");
8212 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8214 for (arglist = TREE_OPERAND (exp, 1), arity = 0;
8216 arglist = TREE_CHAIN (arglist), arity++)
8218 const struct insn_operand_data *insn_op;
8220 tree arg = TREE_VALUE (arglist);
8221 if (arg == error_mark_node)
8223 if (arity > MAX_ARGS)
8226 insn_op = &insn_data[icode].operand[arity + nonvoid];
8228 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
8230 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8231 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8236 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8238 || GET_MODE (target) != tmode
8239 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8240 target = gen_reg_rtx (tmode);
8246 pat = GEN_FCN (icode) (target);
8250 pat = GEN_FCN (icode) (target, op[0]);
8252 pat = GEN_FCN (icode) (op[0]);
8255 pat = GEN_FCN (icode) (target, op[0], op[1]);
8271 /* Output assembly code for the trampoline template to
8274 On S/390, we use gpr 1 internally in the trampoline code;
8275 gpr 0 is used to hold the static chain. */
8278 s390_trampoline_template (FILE *file)
8281 op[0] = gen_rtx_REG (Pmode, 0);
8282 op[1] = gen_rtx_REG (Pmode, 1);
8286 output_asm_insn ("basr\t%1,0", op);
8287 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
8288 output_asm_insn ("br\t%1", op);
8289 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
8293 output_asm_insn ("basr\t%1,0", op);
8294 output_asm_insn ("lm\t%0,%1,6(%1)", op);
8295 output_asm_insn ("br\t%1", op);
8296 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
8300 /* Emit RTL insns to initialize the variable parts of a trampoline.
8301 FNADDR is an RTX for the address of the function's pure code.
8302 CXT is an RTX for the static chain value for the function. */
8305 s390_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
8307 emit_move_insn (gen_rtx_MEM (Pmode,
8308 memory_address (Pmode,
8309 plus_constant (addr, (TARGET_64BIT ? 16 : 8)))), cxt);
8310 emit_move_insn (gen_rtx_MEM (Pmode,
8311 memory_address (Pmode,
8312 plus_constant (addr, (TARGET_64BIT ? 24 : 12)))), fnaddr);
8315 /* Return rtx for 64-bit constant formed from the 32-bit subwords
8316 LOW and HIGH, independent of the host word size. */
8319 s390_gen_rtx_const_DI (int high, int low)
8321 #if HOST_BITS_PER_WIDE_INT >= 64
8323 val = (HOST_WIDE_INT)high;
8325 val |= (HOST_WIDE_INT)low;
8327 return GEN_INT (val);
8329 #if HOST_BITS_PER_WIDE_INT >= 32
8330 return immed_double_const ((HOST_WIDE_INT)low, (HOST_WIDE_INT)high, DImode);
8337 /* Output assembler code to FILE to increment profiler label # LABELNO
8338 for profiling a function entry. */
8341 s390_function_profiler (FILE *file, int labelno)
8346 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
8348 fprintf (file, "# function profiler \n");
8350 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
8351 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
8352 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
8354 op[2] = gen_rtx_REG (Pmode, 1);
8355 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8356 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
8358 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
8361 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
8362 op[4] = gen_rtx_CONST (Pmode, op[4]);
8367 output_asm_insn ("stg\t%0,%1", op);
8368 output_asm_insn ("larl\t%2,%3", op);
8369 output_asm_insn ("brasl\t%0,%4", op);
8370 output_asm_insn ("lg\t%0,%1", op);
8374 op[6] = gen_label_rtx ();
8376 output_asm_insn ("st\t%0,%1", op);
8377 output_asm_insn ("bras\t%2,%l6", op);
8378 output_asm_insn (".long\t%4", op);
8379 output_asm_insn (".long\t%3", op);
8380 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8381 output_asm_insn ("l\t%0,0(%2)", op);
8382 output_asm_insn ("l\t%2,4(%2)", op);
8383 output_asm_insn ("basr\t%0,%0", op);
8384 output_asm_insn ("l\t%0,%1", op);
8388 op[5] = gen_label_rtx ();
8389 op[6] = gen_label_rtx ();
8391 output_asm_insn ("st\t%0,%1", op);
8392 output_asm_insn ("bras\t%2,%l6", op);
8393 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
8394 output_asm_insn (".long\t%4-%l5", op);
8395 output_asm_insn (".long\t%3-%l5", op);
8396 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8397 output_asm_insn ("lr\t%0,%2", op);
8398 output_asm_insn ("a\t%0,0(%2)", op);
8399 output_asm_insn ("a\t%2,4(%2)", op);
8400 output_asm_insn ("basr\t%0,%0", op);
8401 output_asm_insn ("l\t%0,%1", op);
8405 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
8406 into its SYMBOL_REF_FLAGS. */
8409 s390_encode_section_info (tree decl, rtx rtl, int first)
8411 default_encode_section_info (decl, rtl, first);
8413 /* If a variable has a forced alignment to < 2 bytes, mark it with
8414 SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL operand. */
8415 if (TREE_CODE (decl) == VAR_DECL
8416 && DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
8417 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
8420 /* Output thunk to FILE that implements a C++ virtual function call (with
8421 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
8422 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
8423 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
8424 relative to the resulting this pointer. */
8427 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
8428 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8434 /* Operand 0 is the target function. */
8435 op[0] = XEXP (DECL_RTL (function), 0);
8436 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
8439 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
8440 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
8441 op[0] = gen_rtx_CONST (Pmode, op[0]);
8444 /* Operand 1 is the 'this' pointer. */
8445 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8446 op[1] = gen_rtx_REG (Pmode, 3);
8448 op[1] = gen_rtx_REG (Pmode, 2);
8450 /* Operand 2 is the delta. */
8451 op[2] = GEN_INT (delta);
8453 /* Operand 3 is the vcall_offset. */
8454 op[3] = GEN_INT (vcall_offset);
8456 /* Operand 4 is the temporary register. */
8457 op[4] = gen_rtx_REG (Pmode, 1);
8459 /* Operands 5 to 8 can be used as labels. */
8465 /* Operand 9 can be used for temporary register. */
8468 /* Generate code. */
8471 /* Setup literal pool pointer if required. */
8472 if ((!DISP_IN_RANGE (delta)
8473 && !CONST_OK_FOR_K (delta)
8474 && !CONST_OK_FOR_Os (delta))
8475 || (!DISP_IN_RANGE (vcall_offset)
8476 && !CONST_OK_FOR_K (vcall_offset)
8477 && !CONST_OK_FOR_Os (vcall_offset)))
8479 op[5] = gen_label_rtx ();
8480 output_asm_insn ("larl\t%4,%5", op);
8483 /* Add DELTA to this pointer. */
8486 if (CONST_OK_FOR_J (delta))
8487 output_asm_insn ("la\t%1,%2(%1)", op);
8488 else if (DISP_IN_RANGE (delta))
8489 output_asm_insn ("lay\t%1,%2(%1)", op);
8490 else if (CONST_OK_FOR_K (delta))
8491 output_asm_insn ("aghi\t%1,%2", op);
8492 else if (CONST_OK_FOR_Os (delta))
8493 output_asm_insn ("agfi\t%1,%2", op);
8496 op[6] = gen_label_rtx ();
8497 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
8501 /* Perform vcall adjustment. */
8504 if (DISP_IN_RANGE (vcall_offset))
8506 output_asm_insn ("lg\t%4,0(%1)", op);
8507 output_asm_insn ("ag\t%1,%3(%4)", op);
8509 else if (CONST_OK_FOR_K (vcall_offset))
8511 output_asm_insn ("lghi\t%4,%3", op);
8512 output_asm_insn ("ag\t%4,0(%1)", op);
8513 output_asm_insn ("ag\t%1,0(%4)", op);
8515 else if (CONST_OK_FOR_Os (vcall_offset))
8517 output_asm_insn ("lgfi\t%4,%3", op);
8518 output_asm_insn ("ag\t%4,0(%1)", op);
8519 output_asm_insn ("ag\t%1,0(%4)", op);
8523 op[7] = gen_label_rtx ();
8524 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
8525 output_asm_insn ("ag\t%4,0(%1)", op);
8526 output_asm_insn ("ag\t%1,0(%4)", op);
8530 /* Jump to target. */
8531 output_asm_insn ("jg\t%0", op);
8533 /* Output literal pool if required. */
8536 output_asm_insn (".align\t4", op);
8537 targetm.asm_out.internal_label (file, "L",
8538 CODE_LABEL_NUMBER (op[5]));
8542 targetm.asm_out.internal_label (file, "L",
8543 CODE_LABEL_NUMBER (op[6]));
8544 output_asm_insn (".long\t%2", op);
8548 targetm.asm_out.internal_label (file, "L",
8549 CODE_LABEL_NUMBER (op[7]));
8550 output_asm_insn (".long\t%3", op);
8555 /* Setup base pointer if required. */
8557 || (!DISP_IN_RANGE (delta)
8558 && !CONST_OK_FOR_K (delta)
8559 && !CONST_OK_FOR_Os (delta))
8560 || (!DISP_IN_RANGE (delta)
8561 && !CONST_OK_FOR_K (vcall_offset)
8562 && !CONST_OK_FOR_Os (vcall_offset)))
8564 op[5] = gen_label_rtx ();
8565 output_asm_insn ("basr\t%4,0", op);
8566 targetm.asm_out.internal_label (file, "L",
8567 CODE_LABEL_NUMBER (op[5]));
8570 /* Add DELTA to this pointer. */
8573 if (CONST_OK_FOR_J (delta))
8574 output_asm_insn ("la\t%1,%2(%1)", op);
8575 else if (DISP_IN_RANGE (delta))
8576 output_asm_insn ("lay\t%1,%2(%1)", op);
8577 else if (CONST_OK_FOR_K (delta))
8578 output_asm_insn ("ahi\t%1,%2", op);
8579 else if (CONST_OK_FOR_Os (delta))
8580 output_asm_insn ("afi\t%1,%2", op);
8583 op[6] = gen_label_rtx ();
8584 output_asm_insn ("a\t%1,%6-%5(%4)", op);
8588 /* Perform vcall adjustment. */
8591 if (CONST_OK_FOR_J (vcall_offset))
8593 output_asm_insn ("l\t%4,0(%1)", op);
8594 output_asm_insn ("a\t%1,%3(%4)", op);
8596 else if (DISP_IN_RANGE (vcall_offset))
8598 output_asm_insn ("l\t%4,0(%1)", op);
8599 output_asm_insn ("ay\t%1,%3(%4)", op);
8601 else if (CONST_OK_FOR_K (vcall_offset))
8603 output_asm_insn ("lhi\t%4,%3", op);
8604 output_asm_insn ("a\t%4,0(%1)", op);
8605 output_asm_insn ("a\t%1,0(%4)", op);
8607 else if (CONST_OK_FOR_Os (vcall_offset))
8609 output_asm_insn ("iilf\t%4,%3", op);
8610 output_asm_insn ("a\t%4,0(%1)", op);
8611 output_asm_insn ("a\t%1,0(%4)", op);
8615 op[7] = gen_label_rtx ();
8616 output_asm_insn ("l\t%4,%7-%5(%4)", op);
8617 output_asm_insn ("a\t%4,0(%1)", op);
8618 output_asm_insn ("a\t%1,0(%4)", op);
8621 /* We had to clobber the base pointer register.
8622 Re-setup the base pointer (with a different base). */
8623 op[5] = gen_label_rtx ();
8624 output_asm_insn ("basr\t%4,0", op);
8625 targetm.asm_out.internal_label (file, "L",
8626 CODE_LABEL_NUMBER (op[5]));
8629 /* Jump to target. */
8630 op[8] = gen_label_rtx ();
8633 output_asm_insn ("l\t%4,%8-%5(%4)", op);
8635 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8636 /* We cannot call through .plt, since .plt requires %r12 loaded. */
8637 else if (flag_pic == 1)
8639 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8640 output_asm_insn ("l\t%4,%0(%4)", op);
8642 else if (flag_pic == 2)
8644 op[9] = gen_rtx_REG (Pmode, 0);
8645 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
8646 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8647 output_asm_insn ("ar\t%4,%9", op);
8648 output_asm_insn ("l\t%4,0(%4)", op);
8651 output_asm_insn ("br\t%4", op);
8653 /* Output literal pool. */
8654 output_asm_insn (".align\t4", op);
8656 if (nonlocal && flag_pic == 2)
8657 output_asm_insn (".long\t%0", op);
8660 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8661 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
8664 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
8666 output_asm_insn (".long\t%0", op);
8668 output_asm_insn (".long\t%0-%5", op);
8672 targetm.asm_out.internal_label (file, "L",
8673 CODE_LABEL_NUMBER (op[6]));
8674 output_asm_insn (".long\t%2", op);
8678 targetm.asm_out.internal_label (file, "L",
8679 CODE_LABEL_NUMBER (op[7]));
8680 output_asm_insn (".long\t%3", op);
8686 s390_valid_pointer_mode (enum machine_mode mode)
8688 return (mode == SImode || (TARGET_64BIT && mode == DImode));
8691 /* Checks whether the given ARGUMENT_LIST would use a caller
8692 saved register. This is used to decide whether sibling call
8693 optimization could be performed on the respective function
8697 s390_call_saved_register_used (tree argument_list)
8699 CUMULATIVE_ARGS cum;
8701 enum machine_mode mode;
8706 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
8708 while (argument_list)
8710 parameter = TREE_VALUE (argument_list);
8711 argument_list = TREE_CHAIN (argument_list);
8713 gcc_assert (parameter);
8715 /* For an undeclared variable passed as parameter we will get
8716 an ERROR_MARK node here. */
8717 if (TREE_CODE (parameter) == ERROR_MARK)
8720 type = TREE_TYPE (parameter);
8723 mode = TYPE_MODE (type);
8726 if (pass_by_reference (&cum, mode, type, true))
8729 type = build_pointer_type (type);
8732 parm_rtx = s390_function_arg (&cum, mode, type, 0);
8734 s390_function_arg_advance (&cum, mode, type, 0);
8736 if (parm_rtx && REG_P (parm_rtx))
8739 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
8741 if (! call_used_regs[reg + REGNO (parm_rtx)])
8748 /* Return true if the given call expression can be
8749 turned into a sibling call.
8750 DECL holds the declaration of the function to be called whereas
8751 EXP is the call expression itself. */
8754 s390_function_ok_for_sibcall (tree decl, tree exp)
8756 /* The TPF epilogue uses register 1. */
8757 if (TARGET_TPF_PROFILING)
8760 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
8761 which would have to be restored before the sibcall. */
8762 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
8765 /* Register 6 on s390 is available as an argument register but unfortunately
8766 "caller saved". This makes functions needing this register for arguments
8767 not suitable for sibcalls. */
8768 if (TREE_OPERAND (exp, 1)
8769 && s390_call_saved_register_used (TREE_OPERAND (exp, 1)))
8775 /* Return the fixed registers used for condition codes. */
8778 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
8781 *p2 = INVALID_REGNUM;
8786 /* This function is used by the call expanders of the machine description.
8787 It emits the call insn itself together with the necessary operations
8788 to adjust the target address and returns the emitted insn.
8789 ADDR_LOCATION is the target address rtx
8790 TLS_CALL the location of the thread-local symbol
8791 RESULT_REG the register where the result of the call should be stored
8792 RETADDR_REG the register where the return address should be stored
8793 If this parameter is NULL_RTX the call is considered
8794 to be a sibling call. */
8797 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
8800 bool plt_call = false;
8806 /* Direct function calls need special treatment. */
8807 if (GET_CODE (addr_location) == SYMBOL_REF)
8809 /* When calling a global routine in PIC mode, we must
8810 replace the symbol itself with the PLT stub. */
8811 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
8813 addr_location = gen_rtx_UNSPEC (Pmode,
8814 gen_rtvec (1, addr_location),
8816 addr_location = gen_rtx_CONST (Pmode, addr_location);
8820 /* Unless we can use the bras(l) insn, force the
8821 routine address into a register. */
8822 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
8825 addr_location = legitimize_pic_address (addr_location, 0);
8827 addr_location = force_reg (Pmode, addr_location);
8831 /* If it is already an indirect call or the code above moved the
8832 SYMBOL_REF to somewhere else make sure the address can be found in
8834 if (retaddr_reg == NULL_RTX
8835 && GET_CODE (addr_location) != SYMBOL_REF
8838 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
8839 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
8842 addr_location = gen_rtx_MEM (QImode, addr_location);
8843 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
8845 if (result_reg != NULL_RTX)
8846 call = gen_rtx_SET (VOIDmode, result_reg, call);
8848 if (retaddr_reg != NULL_RTX)
8850 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
8852 if (tls_call != NULL_RTX)
8853 vec = gen_rtvec (3, call, clobber,
8854 gen_rtx_USE (VOIDmode, tls_call));
8856 vec = gen_rtvec (2, call, clobber);
8858 call = gen_rtx_PARALLEL (VOIDmode, vec);
8861 insn = emit_call_insn (call);
8863 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
8864 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
8866 /* s390_function_ok_for_sibcall should
8867 have denied sibcalls in this case. */
8868 gcc_assert (retaddr_reg != NULL_RTX);
8870 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
8875 /* Implement CONDITIONAL_REGISTER_USAGE. */
8878 s390_conditional_register_usage (void)
8884 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8885 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8887 if (TARGET_CPU_ZARCH)
8889 fixed_regs[BASE_REGNUM] = 0;
8890 call_used_regs[BASE_REGNUM] = 0;
8891 fixed_regs[RETURN_REGNUM] = 0;
8892 call_used_regs[RETURN_REGNUM] = 0;
8896 for (i = 24; i < 32; i++)
8897 call_used_regs[i] = call_really_used_regs[i] = 0;
8901 for (i = 18; i < 20; i++)
8902 call_used_regs[i] = call_really_used_regs[i] = 0;
8905 if (TARGET_SOFT_FLOAT)
8907 for (i = 16; i < 32; i++)
8908 call_used_regs[i] = fixed_regs[i] = 1;
8912 /* Corresponding function to eh_return expander. */
8914 static GTY(()) rtx s390_tpf_eh_return_symbol;
8916 s390_emit_tpf_eh_return (rtx target)
8920 if (!s390_tpf_eh_return_symbol)
8921 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
8923 reg = gen_rtx_REG (Pmode, 2);
8925 emit_move_insn (reg, target);
8926 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
8927 gen_rtx_REG (Pmode, RETURN_REGNUM));
8928 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
8930 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
8933 /* Rework the prologue/epilogue to avoid saving/restoring
8934 registers unnecessarily. */
8937 s390_optimize_prologue (void)
8939 rtx insn, new_insn, next_insn;
8941 /* Do a final recompute of the frame-related data. */
8943 s390_update_frame_layout ();
8945 /* If all special registers are in fact used, there's nothing we
8946 can do, so no point in walking the insn list. */
8948 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
8949 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
8950 && (TARGET_CPU_ZARCH
8951 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
8952 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
8955 /* Search for prologue/epilogue insns and replace them. */
8957 for (insn = get_insns (); insn; insn = next_insn)
8959 int first, last, off;
8960 rtx set, base, offset;
8962 next_insn = NEXT_INSN (insn);
8964 if (GET_CODE (insn) != INSN)
8967 if (GET_CODE (PATTERN (insn)) == PARALLEL
8968 && store_multiple_operation (PATTERN (insn), VOIDmode))
8970 set = XVECEXP (PATTERN (insn), 0, 0);
8971 first = REGNO (SET_SRC (set));
8972 last = first + XVECLEN (PATTERN (insn), 0) - 1;
8973 offset = const0_rtx;
8974 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8975 off = INTVAL (offset);
8977 if (GET_CODE (base) != REG || off < 0)
8979 if (cfun_frame_layout.first_save_gpr != -1
8980 && (cfun_frame_layout.first_save_gpr < first
8981 || cfun_frame_layout.last_save_gpr > last))
8983 if (REGNO (base) != STACK_POINTER_REGNUM
8984 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8986 if (first > BASE_REGNUM || last < BASE_REGNUM)
8989 if (cfun_frame_layout.first_save_gpr != -1)
8991 new_insn = save_gprs (base,
8992 off + (cfun_frame_layout.first_save_gpr
8993 - first) * UNITS_PER_WORD,
8994 cfun_frame_layout.first_save_gpr,
8995 cfun_frame_layout.last_save_gpr);
8996 new_insn = emit_insn_before (new_insn, insn);
8997 INSN_ADDRESSES_NEW (new_insn, -1);
9004 if (cfun_frame_layout.first_save_gpr == -1
9005 && GET_CODE (PATTERN (insn)) == SET
9006 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9007 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9008 || (!TARGET_CPU_ZARCH
9009 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
9010 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
9012 set = PATTERN (insn);
9013 first = REGNO (SET_SRC (set));
9014 offset = const0_rtx;
9015 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9016 off = INTVAL (offset);
9018 if (GET_CODE (base) != REG || off < 0)
9020 if (REGNO (base) != STACK_POINTER_REGNUM
9021 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9028 if (GET_CODE (PATTERN (insn)) == PARALLEL
9029 && load_multiple_operation (PATTERN (insn), VOIDmode))
9031 set = XVECEXP (PATTERN (insn), 0, 0);
9032 first = REGNO (SET_DEST (set));
9033 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9034 offset = const0_rtx;
9035 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9036 off = INTVAL (offset);
9038 if (GET_CODE (base) != REG || off < 0)
9040 if (cfun_frame_layout.first_restore_gpr != -1
9041 && (cfun_frame_layout.first_restore_gpr < first
9042 || cfun_frame_layout.last_restore_gpr > last))
9044 if (REGNO (base) != STACK_POINTER_REGNUM
9045 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9047 if (first > BASE_REGNUM || last < BASE_REGNUM)
9050 if (cfun_frame_layout.first_restore_gpr != -1)
9052 new_insn = restore_gprs (base,
9053 off + (cfun_frame_layout.first_restore_gpr
9054 - first) * UNITS_PER_WORD,
9055 cfun_frame_layout.first_restore_gpr,
9056 cfun_frame_layout.last_restore_gpr);
9057 new_insn = emit_insn_before (new_insn, insn);
9058 INSN_ADDRESSES_NEW (new_insn, -1);
9065 if (cfun_frame_layout.first_restore_gpr == -1
9066 && GET_CODE (PATTERN (insn)) == SET
9067 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
9068 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
9069 || (!TARGET_CPU_ZARCH
9070 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
9071 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
9073 set = PATTERN (insn);
9074 first = REGNO (SET_DEST (set));
9075 offset = const0_rtx;
9076 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9077 off = INTVAL (offset);
9079 if (GET_CODE (base) != REG || off < 0)
9081 if (REGNO (base) != STACK_POINTER_REGNUM
9082 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9091 /* Perform machine-dependent processing. */
9096 bool pool_overflow = false;
9098 /* Make sure all splits have been performed; splits after
9099 machine_dependent_reorg might confuse insn length counts. */
9100 split_all_insns_noflow ();
9102 /* From here on decomposed literal pool addresses must be accepted. */
9103 cfun->machine->decomposed_literal_pool_addresses_ok_p = true;
9105 /* Install the main literal pool and the associated base
9106 register load insns.
9108 In addition, there are two problematic situations we need
9111 - the literal pool might be > 4096 bytes in size, so that
9112 some of its elements cannot be directly accessed
9114 - a branch target might be > 64K away from the branch, so that
9115 it is not possible to use a PC-relative instruction.
9117 To fix those, we split the single literal pool into multiple
9118 pool chunks, reloading the pool base register at various
9119 points throughout the function to ensure it always points to
9120 the pool chunk the following code expects, and / or replace
9121 PC-relative branches by absolute branches.
9123 However, the two problems are interdependent: splitting the
9124 literal pool can move a branch further away from its target,
9125 causing the 64K limit to overflow, and on the other hand,
9126 replacing a PC-relative branch by an absolute branch means
9127 we need to put the branch target address into the literal
9128 pool, possibly causing it to overflow.
9130 So, we loop trying to fix up both problems until we manage
9131 to satisfy both conditions at the same time. Note that the
9132 loop is guaranteed to terminate as every pass of the loop
9133 strictly decreases the total number of PC-relative branches
9134 in the function. (This is not completely true as there
9135 might be branch-over-pool insns introduced by chunkify_start.
9136 Those never need to be split however.) */
9140 struct constant_pool *pool = NULL;
9142 /* Collect the literal pool. */
9145 pool = s390_mainpool_start ();
9147 pool_overflow = true;
9150 /* If literal pool overflowed, start to chunkify it. */
9152 pool = s390_chunkify_start ();
9154 /* Split out-of-range branches. If this has created new
9155 literal pool entries, cancel current chunk list and
9156 recompute it. zSeries machines have large branch
9157 instructions, so we never need to split a branch. */
9158 if (!TARGET_CPU_ZARCH && s390_split_branches ())
9161 s390_chunkify_cancel (pool);
9163 s390_mainpool_cancel (pool);
9168 /* If we made it up to here, both conditions are satisfied.
9169 Finish up literal pool related changes. */
9171 s390_chunkify_finish (pool);
9173 s390_mainpool_finish (pool);
9175 /* We're done splitting branches. */
9176 cfun->machine->split_branches_pending_p = false;
9180 /* Generate out-of-pool execute target insns. */
9181 if (TARGET_CPU_ZARCH)
9183 rtx insn, label, target;
9185 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9187 label = s390_execute_label (insn);
9191 gcc_assert (label != const0_rtx);
9193 target = emit_label (XEXP (label, 0));
9194 INSN_ADDRESSES_NEW (target, -1);
9196 target = emit_insn (s390_execute_target (insn));
9197 INSN_ADDRESSES_NEW (target, -1);
9201 /* Try to optimize prologue and epilogue further. */
9202 s390_optimize_prologue ();
9206 /* Initialize GCC target structure. */
9208 #undef TARGET_ASM_ALIGNED_HI_OP
9209 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9210 #undef TARGET_ASM_ALIGNED_DI_OP
9211 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9212 #undef TARGET_ASM_INTEGER
9213 #define TARGET_ASM_INTEGER s390_assemble_integer
9215 #undef TARGET_ASM_OPEN_PAREN
9216 #define TARGET_ASM_OPEN_PAREN ""
9218 #undef TARGET_ASM_CLOSE_PAREN
9219 #define TARGET_ASM_CLOSE_PAREN ""
9221 #undef TARGET_DEFAULT_TARGET_FLAGS
9222 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
9223 #undef TARGET_HANDLE_OPTION
9224 #define TARGET_HANDLE_OPTION s390_handle_option
9226 #undef TARGET_ENCODE_SECTION_INFO
9227 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
9230 #undef TARGET_HAVE_TLS
9231 #define TARGET_HAVE_TLS true
9233 #undef TARGET_CANNOT_FORCE_CONST_MEM
9234 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
9236 #undef TARGET_DELEGITIMIZE_ADDRESS
9237 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
9239 #undef TARGET_RETURN_IN_MEMORY
9240 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
9242 #undef TARGET_INIT_BUILTINS
9243 #define TARGET_INIT_BUILTINS s390_init_builtins
9244 #undef TARGET_EXPAND_BUILTIN
9245 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
9247 #undef TARGET_ASM_OUTPUT_MI_THUNK
9248 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
9249 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9250 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
9252 #undef TARGET_SCHED_ADJUST_PRIORITY
9253 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
9254 #undef TARGET_SCHED_ISSUE_RATE
9255 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
9256 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9257 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
9259 #undef TARGET_CANNOT_COPY_INSN_P
9260 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
9261 #undef TARGET_RTX_COSTS
9262 #define TARGET_RTX_COSTS s390_rtx_costs
9263 #undef TARGET_ADDRESS_COST
9264 #define TARGET_ADDRESS_COST s390_address_cost
9266 #undef TARGET_MACHINE_DEPENDENT_REORG
9267 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
9269 #undef TARGET_VALID_POINTER_MODE
9270 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
9272 #undef TARGET_BUILD_BUILTIN_VA_LIST
9273 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
9274 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
9275 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
9277 #undef TARGET_PROMOTE_FUNCTION_ARGS
9278 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
9279 #undef TARGET_PROMOTE_FUNCTION_RETURN
9280 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
9281 #undef TARGET_PASS_BY_REFERENCE
9282 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
9284 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
9285 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
9287 #undef TARGET_FIXED_CONDITION_CODE_REGS
9288 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
9290 #undef TARGET_CC_MODES_COMPATIBLE
9291 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
9293 #undef TARGET_INVALID_WITHIN_DOLOOP
9294 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_rtx_null
9297 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
9298 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
9301 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
9302 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
9303 #define TARGET_MANGLE_FUNDAMENTAL_TYPE s390_mangle_fundamental_type
9306 struct gcc_target targetm = TARGET_INITIALIZER;
9308 #include "gt-s390.h"