1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
45 #include "basic-block.h"
46 #include "integrate.h"
49 #include "target-def.h"
51 #include "langhooks.h"
58 /* Define the specific costs for a given cpu. */
60 struct processor_costs
63 const int m; /* cost of an M instruction. */
64 const int mghi; /* cost of an MGHI instruction. */
65 const int mh; /* cost of an MH instruction. */
66 const int mhi; /* cost of an MHI instruction. */
67 const int ml; /* cost of an ML instruction. */
68 const int mr; /* cost of an MR instruction. */
69 const int ms; /* cost of an MS instruction. */
70 const int msg; /* cost of an MSG instruction. */
71 const int msgf; /* cost of an MSGF instruction. */
72 const int msgfr; /* cost of an MSGFR instruction. */
73 const int msgr; /* cost of an MSGR instruction. */
74 const int msr; /* cost of an MSR instruction. */
75 const int mult_df; /* cost of multiplication in DFmode. */
78 const int sqxbr; /* cost of square root in TFmode. */
79 const int sqdbr; /* cost of square root in DFmode. */
80 const int sqebr; /* cost of square root in SFmode. */
81 /* multiply and add */
82 const int madbr; /* cost of multiply and add in DFmode. */
83 const int maebr; /* cost of multiply and add in SFmode. */
95 const struct processor_costs *s390_cost;
98 struct processor_costs z900_cost =
100 COSTS_N_INSNS (5), /* M */
101 COSTS_N_INSNS (10), /* MGHI */
102 COSTS_N_INSNS (5), /* MH */
103 COSTS_N_INSNS (4), /* MHI */
104 COSTS_N_INSNS (5), /* ML */
105 COSTS_N_INSNS (5), /* MR */
106 COSTS_N_INSNS (4), /* MS */
107 COSTS_N_INSNS (15), /* MSG */
108 COSTS_N_INSNS (7), /* MSGF */
109 COSTS_N_INSNS (7), /* MSGFR */
110 COSTS_N_INSNS (10), /* MSGR */
111 COSTS_N_INSNS (4), /* MSR */
112 COSTS_N_INSNS (7), /* multiplication in DFmode */
113 COSTS_N_INSNS (13), /* MXBR */
114 COSTS_N_INSNS (136), /* SQXBR */
115 COSTS_N_INSNS (44), /* SQDBR */
116 COSTS_N_INSNS (35), /* SQEBR */
117 COSTS_N_INSNS (18), /* MADBR */
118 COSTS_N_INSNS (13), /* MAEBR */
119 COSTS_N_INSNS (134), /* DXBR */
120 COSTS_N_INSNS (30), /* DDBR */
121 COSTS_N_INSNS (27), /* DEBR */
122 COSTS_N_INSNS (220), /* DLGR */
123 COSTS_N_INSNS (34), /* DLR */
124 COSTS_N_INSNS (34), /* DR */
125 COSTS_N_INSNS (32), /* DSGFR */
126 COSTS_N_INSNS (32), /* DSGR */
130 struct processor_costs z990_cost =
132 COSTS_N_INSNS (4), /* M */
133 COSTS_N_INSNS (2), /* MGHI */
134 COSTS_N_INSNS (2), /* MH */
135 COSTS_N_INSNS (2), /* MHI */
136 COSTS_N_INSNS (4), /* ML */
137 COSTS_N_INSNS (4), /* MR */
138 COSTS_N_INSNS (5), /* MS */
139 COSTS_N_INSNS (6), /* MSG */
140 COSTS_N_INSNS (4), /* MSGF */
141 COSTS_N_INSNS (4), /* MSGFR */
142 COSTS_N_INSNS (4), /* MSGR */
143 COSTS_N_INSNS (4), /* MSR */
144 COSTS_N_INSNS (1), /* multiplication in DFmode */
145 COSTS_N_INSNS (28), /* MXBR */
146 COSTS_N_INSNS (130), /* SQXBR */
147 COSTS_N_INSNS (66), /* SQDBR */
148 COSTS_N_INSNS (38), /* SQEBR */
149 COSTS_N_INSNS (1), /* MADBR */
150 COSTS_N_INSNS (1), /* MAEBR */
151 COSTS_N_INSNS (60), /* DXBR */
152 COSTS_N_INSNS (40), /* DDBR */
153 COSTS_N_INSNS (26), /* DEBR */
154 COSTS_N_INSNS (176), /* DLGR */
155 COSTS_N_INSNS (31), /* DLR */
156 COSTS_N_INSNS (31), /* DR */
157 COSTS_N_INSNS (31), /* DSGFR */
158 COSTS_N_INSNS (31), /* DSGR */
162 struct processor_costs z9_109_cost =
164 COSTS_N_INSNS (4), /* M */
165 COSTS_N_INSNS (2), /* MGHI */
166 COSTS_N_INSNS (2), /* MH */
167 COSTS_N_INSNS (2), /* MHI */
168 COSTS_N_INSNS (4), /* ML */
169 COSTS_N_INSNS (4), /* MR */
170 COSTS_N_INSNS (5), /* MS */
171 COSTS_N_INSNS (6), /* MSG */
172 COSTS_N_INSNS (4), /* MSGF */
173 COSTS_N_INSNS (4), /* MSGFR */
174 COSTS_N_INSNS (4), /* MSGR */
175 COSTS_N_INSNS (4), /* MSR */
176 COSTS_N_INSNS (1), /* multiplication in DFmode */
177 COSTS_N_INSNS (28), /* MXBR */
178 COSTS_N_INSNS (130), /* SQXBR */
179 COSTS_N_INSNS (66), /* SQDBR */
180 COSTS_N_INSNS (38), /* SQEBR */
181 COSTS_N_INSNS (1), /* MADBR */
182 COSTS_N_INSNS (1), /* MAEBR */
183 COSTS_N_INSNS (60), /* DXBR */
184 COSTS_N_INSNS (40), /* DDBR */
185 COSTS_N_INSNS (26), /* DEBR */
186 COSTS_N_INSNS (30), /* DLGR */
187 COSTS_N_INSNS (23), /* DLR */
188 COSTS_N_INSNS (23), /* DR */
189 COSTS_N_INSNS (24), /* DSGFR */
190 COSTS_N_INSNS (24), /* DSGR */
194 struct processor_costs z10_cost =
196 COSTS_N_INSNS (10), /* M */
197 COSTS_N_INSNS (10), /* MGHI */
198 COSTS_N_INSNS (10), /* MH */
199 COSTS_N_INSNS (10), /* MHI */
200 COSTS_N_INSNS (10), /* ML */
201 COSTS_N_INSNS (10), /* MR */
202 COSTS_N_INSNS (10), /* MS */
203 COSTS_N_INSNS (10), /* MSG */
204 COSTS_N_INSNS (10), /* MSGF */
205 COSTS_N_INSNS (10), /* MSGFR */
206 COSTS_N_INSNS (10), /* MSGR */
207 COSTS_N_INSNS (10), /* MSR */
208 COSTS_N_INSNS (1) , /* multiplication in DFmode */
209 COSTS_N_INSNS (50), /* MXBR */
210 COSTS_N_INSNS (120), /* SQXBR */
211 COSTS_N_INSNS (52), /* SQDBR */
212 COSTS_N_INSNS (38), /* SQEBR */
213 COSTS_N_INSNS (1), /* MADBR */
214 COSTS_N_INSNS (1), /* MAEBR */
215 COSTS_N_INSNS (111), /* DXBR */
216 COSTS_N_INSNS (39), /* DDBR */
217 COSTS_N_INSNS (32), /* DEBR */
218 COSTS_N_INSNS (160), /* DLGR */
219 COSTS_N_INSNS (71), /* DLR */
220 COSTS_N_INSNS (71), /* DR */
221 COSTS_N_INSNS (71), /* DSGFR */
222 COSTS_N_INSNS (71), /* DSGR */
225 extern int reload_completed;
227 /* Structure used to hold the components of a S/390 memory
228 address. A legitimate address on S/390 is of the general
230 base + index + displacement
231 where any of the components is optional.
233 base and index are registers of the class ADDR_REGS,
234 displacement is an unsigned 12-bit immediate constant. */
245 /* Which cpu are we tuning for. */
246 enum processor_type s390_tune = PROCESSOR_max;
248 /* Which instruction set architecture to use. */
249 enum processor_type s390_arch;
252 HOST_WIDE_INT s390_warn_framesize = 0;
253 HOST_WIDE_INT s390_stack_size = 0;
254 HOST_WIDE_INT s390_stack_guard = 0;
256 /* The following structure is embedded in the machine
257 specific part of struct function. */
259 struct GTY (()) s390_frame_layout
261 /* Offset within stack frame. */
262 HOST_WIDE_INT gprs_offset;
263 HOST_WIDE_INT f0_offset;
264 HOST_WIDE_INT f4_offset;
265 HOST_WIDE_INT f8_offset;
266 HOST_WIDE_INT backchain_offset;
268 /* Number of first and last gpr where slots in the register
269 save area are reserved for. */
270 int first_save_gpr_slot;
271 int last_save_gpr_slot;
273 /* Number of first and last gpr to be saved, restored. */
275 int first_restore_gpr;
277 int last_restore_gpr;
279 /* Bits standing for floating point registers. Set, if the
280 respective register has to be saved. Starting with reg 16 (f0)
281 at the rightmost bit.
282 Bit 15 - 8 7 6 5 4 3 2 1 0
283 fpr 15 - 8 7 5 3 1 6 4 2 0
284 reg 31 - 24 23 22 21 20 19 18 17 16 */
285 unsigned int fpr_bitmap;
287 /* Number of floating point registers f8-f15 which must be saved. */
290 /* Set if return address needs to be saved.
291 This flag is set by s390_return_addr_rtx if it could not use
292 the initial value of r14 and therefore depends on r14 saved
294 bool save_return_addr_p;
296 /* Size of stack frame. */
297 HOST_WIDE_INT frame_size;
300 /* Define the structure for the machine field in struct function. */
302 struct GTY(()) machine_function
304 struct s390_frame_layout frame_layout;
306 /* Literal pool base register. */
309 /* True if we may need to perform branch splitting. */
310 bool split_branches_pending_p;
312 /* Some local-dynamic TLS symbol name. */
313 const char *some_ld_name;
315 bool has_landing_pad_p;
318 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
320 #define cfun_frame_layout (cfun->machine->frame_layout)
321 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
322 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
323 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
324 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
326 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
329 /* Number of GPRs and FPRs used for argument passing. */
330 #define GP_ARG_NUM_REG 5
331 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
333 /* A couple of shortcuts. */
334 #define CONST_OK_FOR_J(x) \
335 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
336 #define CONST_OK_FOR_K(x) \
337 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
338 #define CONST_OK_FOR_Os(x) \
339 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
340 #define CONST_OK_FOR_Op(x) \
341 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
342 #define CONST_OK_FOR_On(x) \
343 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
345 #define REGNO_PAIR_OK(REGNO, MODE) \
346 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
348 /* That's the read ahead of the dynamic branch prediction unit in
349 bytes on a z10 CPU. */
350 #define Z10_PREDICT_DISTANCE 384
352 static enum machine_mode
353 s390_libgcc_cmp_return_mode (void)
355 return TARGET_64BIT ? DImode : SImode;
358 static enum machine_mode
359 s390_libgcc_shift_count_mode (void)
361 return TARGET_64BIT ? DImode : SImode;
364 /* Return true if the back end supports mode MODE. */
366 s390_scalar_mode_supported_p (enum machine_mode mode)
368 if (DECIMAL_FLOAT_MODE_P (mode))
371 return default_scalar_mode_supported_p (mode);
374 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
377 s390_set_has_landing_pad_p (bool value)
379 cfun->machine->has_landing_pad_p = value;
382 /* If two condition code modes are compatible, return a condition code
383 mode which is compatible with both. Otherwise, return
386 static enum machine_mode
387 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
395 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
396 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
417 /* Return true if SET either doesn't set the CC register, or else
418 the source and destination have matching CC modes and that
419 CC mode is at least as constrained as REQ_MODE. */
422 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
424 enum machine_mode set_mode;
426 gcc_assert (GET_CODE (set) == SET);
428 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
431 set_mode = GET_MODE (SET_DEST (set));
445 if (req_mode != set_mode)
450 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
451 && req_mode != CCSRmode && req_mode != CCURmode)
457 if (req_mode != CCAmode)
465 return (GET_MODE (SET_SRC (set)) == set_mode);
468 /* Return true if every SET in INSN that sets the CC register
469 has source and destination with matching CC modes and that
470 CC mode is at least as constrained as REQ_MODE.
471 If REQ_MODE is VOIDmode, always return false. */
474 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
478 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
479 if (req_mode == VOIDmode)
482 if (GET_CODE (PATTERN (insn)) == SET)
483 return s390_match_ccmode_set (PATTERN (insn), req_mode);
485 if (GET_CODE (PATTERN (insn)) == PARALLEL)
486 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
488 rtx set = XVECEXP (PATTERN (insn), 0, i);
489 if (GET_CODE (set) == SET)
490 if (!s390_match_ccmode_set (set, req_mode))
497 /* If a test-under-mask instruction can be used to implement
498 (compare (and ... OP1) OP2), return the CC mode required
499 to do that. Otherwise, return VOIDmode.
500 MIXED is true if the instruction can distinguish between
501 CC1 and CC2 for mixed selected bits (TMxx), it is false
502 if the instruction cannot (TM). */
505 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
509 /* ??? Fixme: should work on CONST_DOUBLE as well. */
510 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
513 /* Selected bits all zero: CC0.
514 e.g.: int a; if ((a & (16 + 128)) == 0) */
515 if (INTVAL (op2) == 0)
518 /* Selected bits all one: CC3.
519 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
520 if (INTVAL (op2) == INTVAL (op1))
523 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
525 if ((a & (16 + 128)) == 16) -> CCT1
526 if ((a & (16 + 128)) == 128) -> CCT2 */
529 bit1 = exact_log2 (INTVAL (op2));
530 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
531 if (bit0 != -1 && bit1 != -1)
532 return bit0 > bit1 ? CCT1mode : CCT2mode;
538 /* Given a comparison code OP (EQ, NE, etc.) and the operands
539 OP0 and OP1 of a COMPARE, return the mode to be used for the
543 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
549 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
550 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
552 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
553 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
555 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
556 || GET_CODE (op1) == NEG)
557 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
560 if (GET_CODE (op0) == AND)
562 /* Check whether we can potentially do it via TM. */
563 enum machine_mode ccmode;
564 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
565 if (ccmode != VOIDmode)
567 /* Relax CCTmode to CCZmode to allow fall-back to AND
568 if that turns out to be beneficial. */
569 return ccmode == CCTmode ? CCZmode : ccmode;
573 if (register_operand (op0, HImode)
574 && GET_CODE (op1) == CONST_INT
575 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
577 if (register_operand (op0, QImode)
578 && GET_CODE (op1) == CONST_INT
579 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
588 /* The only overflow condition of NEG and ABS happens when
589 -INT_MAX is used as parameter, which stays negative. So
590 we have an overflow from a positive value to a negative.
591 Using CCAP mode the resulting cc can be used for comparisons. */
592 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
593 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
596 /* If constants are involved in an add instruction it is possible to use
597 the resulting cc for comparisons with zero. Knowing the sign of the
598 constant the overflow behavior gets predictable. e.g.:
599 int a, b; if ((b = a + c) > 0)
600 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
601 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
602 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
604 if (INTVAL (XEXP((op0), 1)) < 0)
618 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
619 && GET_CODE (op1) != CONST_INT)
625 if (GET_CODE (op0) == PLUS
626 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
629 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
630 && GET_CODE (op1) != CONST_INT)
636 if (GET_CODE (op0) == MINUS
637 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
640 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
641 && GET_CODE (op1) != CONST_INT)
650 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
651 that we can implement more efficiently. */
654 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
656 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
657 if ((*code == EQ || *code == NE)
658 && *op1 == const0_rtx
659 && GET_CODE (*op0) == ZERO_EXTRACT
660 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
661 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
662 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
664 rtx inner = XEXP (*op0, 0);
665 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
666 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
667 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
669 if (len > 0 && len < modesize
670 && pos >= 0 && pos + len <= modesize
671 && modesize <= HOST_BITS_PER_WIDE_INT)
673 unsigned HOST_WIDE_INT block;
674 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
675 block <<= modesize - pos - len;
677 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
678 gen_int_mode (block, GET_MODE (inner)));
682 /* Narrow AND of memory against immediate to enable TM. */
683 if ((*code == EQ || *code == NE)
684 && *op1 == const0_rtx
685 && GET_CODE (*op0) == AND
686 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
687 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
689 rtx inner = XEXP (*op0, 0);
690 rtx mask = XEXP (*op0, 1);
692 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
693 if (GET_CODE (inner) == SUBREG
694 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
695 && (GET_MODE_SIZE (GET_MODE (inner))
696 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
698 & GET_MODE_MASK (GET_MODE (inner))
699 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
701 inner = SUBREG_REG (inner);
703 /* Do not change volatile MEMs. */
704 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
706 int part = s390_single_part (XEXP (*op0, 1),
707 GET_MODE (inner), QImode, 0);
710 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
711 inner = adjust_address_nv (inner, QImode, part);
712 *op0 = gen_rtx_AND (QImode, inner, mask);
717 /* Narrow comparisons against 0xffff to HImode if possible. */
718 if ((*code == EQ || *code == NE)
719 && GET_CODE (*op1) == CONST_INT
720 && INTVAL (*op1) == 0xffff
721 && SCALAR_INT_MODE_P (GET_MODE (*op0))
722 && (nonzero_bits (*op0, GET_MODE (*op0))
723 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
725 *op0 = gen_lowpart (HImode, *op0);
729 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
730 if (GET_CODE (*op0) == UNSPEC
731 && XINT (*op0, 1) == UNSPEC_CCU_TO_INT
732 && XVECLEN (*op0, 0) == 1
733 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
734 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
735 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
736 && *op1 == const0_rtx)
738 enum rtx_code new_code = UNKNOWN;
741 case EQ: new_code = EQ; break;
742 case NE: new_code = NE; break;
743 case LT: new_code = GTU; break;
744 case GT: new_code = LTU; break;
745 case LE: new_code = GEU; break;
746 case GE: new_code = LEU; break;
750 if (new_code != UNKNOWN)
752 *op0 = XVECEXP (*op0, 0, 0);
757 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
758 if (GET_CODE (*op0) == UNSPEC
759 && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT
760 && XVECLEN (*op0, 0) == 1
761 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode
762 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
763 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
764 && *op1 == const0_rtx)
766 enum rtx_code new_code = UNKNOWN;
769 case EQ: new_code = EQ; break;
770 case NE: new_code = NE; break;
774 if (new_code != UNKNOWN)
776 *op0 = XVECEXP (*op0, 0, 0);
781 /* Simplify cascaded EQ, NE with const0_rtx. */
782 if ((*code == NE || *code == EQ)
783 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
784 && GET_MODE (*op0) == SImode
785 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
786 && REG_P (XEXP (*op0, 0))
787 && XEXP (*op0, 1) == const0_rtx
788 && *op1 == const0_rtx)
790 if ((*code == EQ && GET_CODE (*op0) == NE)
791 || (*code == NE && GET_CODE (*op0) == EQ))
795 *op0 = XEXP (*op0, 0);
798 /* Prefer register over memory as first operand. */
799 if (MEM_P (*op0) && REG_P (*op1))
801 rtx tem = *op0; *op0 = *op1; *op1 = tem;
802 *code = swap_condition (*code);
806 /* Emit a compare instruction suitable to implement the comparison
807 OP0 CODE OP1. Return the correct condition RTL to be placed in
808 the IF_THEN_ELSE of the conditional branch testing the result. */
811 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
813 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
816 /* Do not output a redundant compare instruction if a compare_and_swap
817 pattern already computed the result and the machine modes are compatible. */
818 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
820 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
826 cc = gen_rtx_REG (mode, CC_REGNUM);
827 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
830 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
833 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
835 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
836 conditional branch testing the result. */
839 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx)
841 emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx));
842 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx);
845 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
846 unconditional jump, else a conditional jump under condition COND. */
849 s390_emit_jump (rtx target, rtx cond)
853 target = gen_rtx_LABEL_REF (VOIDmode, target);
855 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
857 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
858 emit_jump_insn (insn);
861 /* Return branch condition mask to implement a branch
862 specified by CODE. Return -1 for invalid comparisons. */
865 s390_branch_condition_mask (rtx code)
867 const int CC0 = 1 << 3;
868 const int CC1 = 1 << 2;
869 const int CC2 = 1 << 1;
870 const int CC3 = 1 << 0;
872 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
873 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
874 gcc_assert (XEXP (code, 1) == const0_rtx);
876 switch (GET_MODE (XEXP (code, 0)))
880 switch (GET_CODE (code))
883 case NE: return CC1 | CC2 | CC3;
889 switch (GET_CODE (code))
892 case NE: return CC0 | CC2 | CC3;
898 switch (GET_CODE (code))
901 case NE: return CC0 | CC1 | CC3;
907 switch (GET_CODE (code))
910 case NE: return CC0 | CC1 | CC2;
916 switch (GET_CODE (code))
918 case EQ: return CC0 | CC2;
919 case NE: return CC1 | CC3;
925 switch (GET_CODE (code))
927 case LTU: return CC2 | CC3; /* carry */
928 case GEU: return CC0 | CC1; /* no carry */
934 switch (GET_CODE (code))
936 case GTU: return CC0 | CC1; /* borrow */
937 case LEU: return CC2 | CC3; /* no borrow */
943 switch (GET_CODE (code))
945 case EQ: return CC0 | CC2;
946 case NE: return CC1 | CC3;
947 case LTU: return CC1;
948 case GTU: return CC3;
949 case LEU: return CC1 | CC2;
950 case GEU: return CC2 | CC3;
955 switch (GET_CODE (code))
958 case NE: return CC1 | CC2 | CC3;
959 case LTU: return CC1;
960 case GTU: return CC2;
961 case LEU: return CC0 | CC1;
962 case GEU: return CC0 | CC2;
968 switch (GET_CODE (code))
971 case NE: return CC2 | CC1 | CC3;
972 case LTU: return CC2;
973 case GTU: return CC1;
974 case LEU: return CC0 | CC2;
975 case GEU: return CC0 | CC1;
981 switch (GET_CODE (code))
984 case NE: return CC1 | CC2 | CC3;
985 case LT: return CC1 | CC3;
987 case LE: return CC0 | CC1 | CC3;
988 case GE: return CC0 | CC2;
994 switch (GET_CODE (code))
997 case NE: return CC1 | CC2 | CC3;
999 case GT: return CC2 | CC3;
1000 case LE: return CC0 | CC1;
1001 case GE: return CC0 | CC2 | CC3;
1007 switch (GET_CODE (code))
1009 case EQ: return CC0;
1010 case NE: return CC1 | CC2 | CC3;
1011 case LT: return CC1;
1012 case GT: return CC2;
1013 case LE: return CC0 | CC1;
1014 case GE: return CC0 | CC2;
1015 case UNORDERED: return CC3;
1016 case ORDERED: return CC0 | CC1 | CC2;
1017 case UNEQ: return CC0 | CC3;
1018 case UNLT: return CC1 | CC3;
1019 case UNGT: return CC2 | CC3;
1020 case UNLE: return CC0 | CC1 | CC3;
1021 case UNGE: return CC0 | CC2 | CC3;
1022 case LTGT: return CC1 | CC2;
1028 switch (GET_CODE (code))
1030 case EQ: return CC0;
1031 case NE: return CC2 | CC1 | CC3;
1032 case LT: return CC2;
1033 case GT: return CC1;
1034 case LE: return CC0 | CC2;
1035 case GE: return CC0 | CC1;
1036 case UNORDERED: return CC3;
1037 case ORDERED: return CC0 | CC2 | CC1;
1038 case UNEQ: return CC0 | CC3;
1039 case UNLT: return CC2 | CC3;
1040 case UNGT: return CC1 | CC3;
1041 case UNLE: return CC0 | CC2 | CC3;
1042 case UNGE: return CC0 | CC1 | CC3;
1043 case LTGT: return CC2 | CC1;
1054 /* Return branch condition mask to implement a compare and branch
1055 specified by CODE. Return -1 for invalid comparisons. */
1058 s390_compare_and_branch_condition_mask (rtx code)
1060 const int CC0 = 1 << 3;
1061 const int CC1 = 1 << 2;
1062 const int CC2 = 1 << 1;
1064 switch (GET_CODE (code))
1088 /* If INV is false, return assembler mnemonic string to implement
1089 a branch specified by CODE. If INV is true, return mnemonic
1090 for the corresponding inverted branch. */
1093 s390_branch_condition_mnemonic (rtx code, int inv)
1097 static const char *const mnemonic[16] =
1099 NULL, "o", "h", "nle",
1100 "l", "nhe", "lh", "ne",
1101 "e", "nlh", "he", "nl",
1102 "le", "nh", "no", NULL
1105 if (GET_CODE (XEXP (code, 0)) == REG
1106 && REGNO (XEXP (code, 0)) == CC_REGNUM
1107 && XEXP (code, 1) == const0_rtx)
1108 mask = s390_branch_condition_mask (code);
1110 mask = s390_compare_and_branch_condition_mask (code);
1112 gcc_assert (mask >= 0);
1117 gcc_assert (mask >= 1 && mask <= 14);
1119 return mnemonic[mask];
1122 /* Return the part of op which has a value different from def.
1123 The size of the part is determined by mode.
1124 Use this function only if you already know that op really
1125 contains such a part. */
1127 unsigned HOST_WIDE_INT
1128 s390_extract_part (rtx op, enum machine_mode mode, int def)
1130 unsigned HOST_WIDE_INT value = 0;
1131 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1132 int part_bits = GET_MODE_BITSIZE (mode);
1133 unsigned HOST_WIDE_INT part_mask
1134 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1137 for (i = 0; i < max_parts; i++)
1140 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1142 value >>= part_bits;
1144 if ((value & part_mask) != (def & part_mask))
1145 return value & part_mask;
1151 /* If OP is an integer constant of mode MODE with exactly one
1152 part of mode PART_MODE unequal to DEF, return the number of that
1153 part. Otherwise, return -1. */
1156 s390_single_part (rtx op,
1157 enum machine_mode mode,
1158 enum machine_mode part_mode,
1161 unsigned HOST_WIDE_INT value = 0;
1162 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1163 unsigned HOST_WIDE_INT part_mask
1164 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1167 if (GET_CODE (op) != CONST_INT)
1170 for (i = 0; i < n_parts; i++)
1173 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1175 value >>= GET_MODE_BITSIZE (part_mode);
1177 if ((value & part_mask) != (def & part_mask))
1185 return part == -1 ? -1 : n_parts - 1 - part;
1188 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1189 bits and no other bits are set in IN. POS and LENGTH can be used
1190 to obtain the start position and the length of the bitfield.
1192 POS gives the position of the first bit of the bitfield counting
1193 from the lowest order bit starting with zero. In order to use this
1194 value for S/390 instructions this has to be converted to "bits big
1198 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1199 int *pos, int *length)
1204 unsigned HOST_WIDE_INT mask = 1ULL;
1205 bool contiguous = false;
1207 for (i = 0; i < size; mask <<= 1, i++)
1231 /* Calculate a mask for all bits beyond the contiguous bits. */
1232 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1237 if (tmp_length + tmp_pos - 1 > size)
1241 *length = tmp_length;
1249 /* Check whether we can (and want to) split a double-word
1250 move in mode MODE from SRC to DST into two single-word
1251 moves, moving the subword FIRST_SUBWORD first. */
1254 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1256 /* Floating point registers cannot be split. */
1257 if (FP_REG_P (src) || FP_REG_P (dst))
1260 /* We don't need to split if operands are directly accessible. */
1261 if (s_operand (src, mode) || s_operand (dst, mode))
1264 /* Non-offsettable memory references cannot be split. */
1265 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1266 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1269 /* Moving the first subword must not clobber a register
1270 needed to move the second subword. */
1271 if (register_operand (dst, mode))
1273 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1274 if (reg_overlap_mentioned_p (subreg, src))
1281 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1282 and [MEM2, MEM2 + SIZE] do overlap and false
1286 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1288 rtx addr1, addr2, addr_delta;
1289 HOST_WIDE_INT delta;
1291 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1297 addr1 = XEXP (mem1, 0);
1298 addr2 = XEXP (mem2, 0);
1300 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1302 /* This overlapping check is used by peepholes merging memory block operations.
1303 Overlapping operations would otherwise be recognized by the S/390 hardware
1304 and would fall back to a slower implementation. Allowing overlapping
1305 operations would lead to slow code but not to wrong code. Therefore we are
1306 somewhat optimistic if we cannot prove that the memory blocks are
1308 That's why we return false here although this may accept operations on
1309 overlapping memory areas. */
1310 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1313 delta = INTVAL (addr_delta);
1316 || (delta > 0 && delta < size)
1317 || (delta < 0 && -delta < size))
1323 /* Check whether the address of memory reference MEM2 equals exactly
1324 the address of memory reference MEM1 plus DELTA. Return true if
1325 we can prove this to be the case, false otherwise. */
1328 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1330 rtx addr1, addr2, addr_delta;
1332 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1335 addr1 = XEXP (mem1, 0);
1336 addr2 = XEXP (mem2, 0);
1338 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1339 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1345 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1348 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1351 enum machine_mode wmode = mode;
1352 rtx dst = operands[0];
1353 rtx src1 = operands[1];
1354 rtx src2 = operands[2];
1357 /* If we cannot handle the operation directly, use a temp register. */
1358 if (!s390_logical_operator_ok_p (operands))
1359 dst = gen_reg_rtx (mode);
1361 /* QImode and HImode patterns make sense only if we have a destination
1362 in memory. Otherwise perform the operation in SImode. */
1363 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1366 /* Widen operands if required. */
1369 if (GET_CODE (dst) == SUBREG
1370 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1372 else if (REG_P (dst))
1373 dst = gen_rtx_SUBREG (wmode, dst, 0);
1375 dst = gen_reg_rtx (wmode);
1377 if (GET_CODE (src1) == SUBREG
1378 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1380 else if (GET_MODE (src1) != VOIDmode)
1381 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1383 if (GET_CODE (src2) == SUBREG
1384 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1386 else if (GET_MODE (src2) != VOIDmode)
1387 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1390 /* Emit the instruction. */
1391 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1392 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1393 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1395 /* Fix up the destination if needed. */
1396 if (dst != operands[0])
1397 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1400 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1403 s390_logical_operator_ok_p (rtx *operands)
1405 /* If the destination operand is in memory, it needs to coincide
1406 with one of the source operands. After reload, it has to be
1407 the first source operand. */
1408 if (GET_CODE (operands[0]) == MEM)
1409 return rtx_equal_p (operands[0], operands[1])
1410 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1415 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1416 operand IMMOP to switch from SS to SI type instructions. */
1419 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1421 int def = code == AND ? -1 : 0;
1425 gcc_assert (GET_CODE (*memop) == MEM);
1426 gcc_assert (!MEM_VOLATILE_P (*memop));
1428 mask = s390_extract_part (*immop, QImode, def);
1429 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1430 gcc_assert (part >= 0);
1432 *memop = adjust_address (*memop, QImode, part);
1433 *immop = gen_int_mode (mask, QImode);
1437 /* How to allocate a 'struct machine_function'. */
1439 static struct machine_function *
1440 s390_init_machine_status (void)
1442 return GGC_CNEW (struct machine_function);
1445 /* Change optimizations to be performed, depending on the
1448 LEVEL is the optimization level specified; 2 if `-O2' is
1449 specified, 1 if `-O' is specified, and 0 if neither is specified.
1451 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1454 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1456 /* ??? There are apparently still problems with -fcaller-saves. */
1457 flag_caller_saves = 0;
1459 /* By default, always emit DWARF-2 unwind info. This allows debugging
1460 without maintaining a stack frame back-chain. */
1461 flag_asynchronous_unwind_tables = 1;
1463 /* Use MVCLE instructions to decrease code size if requested. */
1465 target_flags |= MASK_MVCLE;
1468 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1469 to the associated processor_type and processor_flags if so. */
1472 s390_handle_arch_option (const char *arg,
1473 enum processor_type *type,
1478 const char *const name; /* processor name or nickname. */
1479 const enum processor_type processor;
1480 const int flags; /* From enum processor_flags. */
1482 const processor_alias_table[] =
1484 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1485 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1486 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1487 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1488 | PF_LONG_DISPLACEMENT},
1489 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1490 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1491 {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1492 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP },
1493 {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH
1494 | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10},
1498 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1499 if (strcmp (arg, processor_alias_table[i].name) == 0)
1501 *type = processor_alias_table[i].processor;
1502 *flags = processor_alias_table[i].flags;
1508 /* Implement TARGET_HANDLE_OPTION. */
1511 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1516 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1518 case OPT_mstack_guard_:
1519 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1521 if (exact_log2 (s390_stack_guard) == -1)
1522 error ("stack guard value must be an exact power of 2");
1525 case OPT_mstack_size_:
1526 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1528 if (exact_log2 (s390_stack_size) == -1)
1529 error ("stack size must be an exact power of 2");
1533 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1535 case OPT_mwarn_framesize_:
1536 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1544 override_options (void)
1546 /* Set up function hooks. */
1547 init_machine_status = s390_init_machine_status;
1549 /* Architecture mode defaults according to ABI. */
1550 if (!(target_flags_explicit & MASK_ZARCH))
1553 target_flags |= MASK_ZARCH;
1555 target_flags &= ~MASK_ZARCH;
1558 /* Determine processor architectural level. */
1559 if (!s390_arch_string)
1561 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1562 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1565 /* Determine processor to tune for. */
1566 if (s390_tune == PROCESSOR_max)
1568 s390_tune = s390_arch;
1569 s390_tune_flags = s390_arch_flags;
1572 /* Sanity checks. */
1573 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
1574 error ("z/Architecture mode not supported on %s", s390_arch_string);
1575 if (TARGET_64BIT && !TARGET_ZARCH)
1576 error ("64-bit ABI not supported in ESA/390 mode");
1578 if (TARGET_HARD_DFP && !TARGET_DFP)
1580 if (target_flags_explicit & MASK_HARD_DFP)
1582 if (!TARGET_CPU_DFP)
1583 error ("Hardware decimal floating point instructions"
1584 " not available on %s", s390_arch_string);
1586 error ("Hardware decimal floating point instructions"
1587 " not available in ESA/390 mode");
1590 target_flags &= ~MASK_HARD_DFP;
1593 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1595 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
1596 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1598 target_flags &= ~MASK_HARD_DFP;
1601 /* Set processor cost function. */
1604 case PROCESSOR_2084_Z990:
1605 s390_cost = &z990_cost;
1607 case PROCESSOR_2094_Z9_109:
1608 s390_cost = &z9_109_cost;
1610 case PROCESSOR_2097_Z10:
1611 s390_cost = &z10_cost;
1614 s390_cost = &z900_cost;
1617 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1618 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1621 if (s390_stack_size)
1623 if (s390_stack_guard >= s390_stack_size)
1624 error ("stack size must be greater than the stack guard value");
1625 else if (s390_stack_size > 1 << 16)
1626 error ("stack size must not be greater than 64k");
1628 else if (s390_stack_guard)
1629 error ("-mstack-guard implies use of -mstack-size");
1631 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1632 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1633 target_flags |= MASK_LONG_DOUBLE_128;
1636 if (s390_tune == PROCESSOR_2097_Z10
1637 && !PARAM_SET_P (PARAM_MAX_UNROLLED_INSNS))
1638 set_param_value ("max-unrolled-insns", 100);
1641 /* Map for smallest class containing reg regno. */
1643 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1644 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1645 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1646 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1647 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1648 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1649 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1650 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1651 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1652 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1653 ACCESS_REGS, ACCESS_REGS
1656 /* Return attribute type of insn. */
1658 static enum attr_type
1659 s390_safe_attr_type (rtx insn)
1661 if (recog_memoized (insn) >= 0)
1662 return get_attr_type (insn);
1667 /* Return true if DISP is a valid short displacement. */
1670 s390_short_displacement (rtx disp)
1672 /* No displacement is OK. */
1676 /* Without the long displacement facility we don't need to
1677 distingiush between long and short displacement. */
1678 if (!TARGET_LONG_DISPLACEMENT)
1681 /* Integer displacement in range. */
1682 if (GET_CODE (disp) == CONST_INT)
1683 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1685 /* GOT offset is not OK, the GOT can be large. */
1686 if (GET_CODE (disp) == CONST
1687 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1688 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1689 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1692 /* All other symbolic constants are literal pool references,
1693 which are OK as the literal pool must be small. */
1694 if (GET_CODE (disp) == CONST)
1700 /* Decompose a RTL expression ADDR for a memory address into
1701 its components, returned in OUT.
1703 Returns false if ADDR is not a valid memory address, true
1704 otherwise. If OUT is NULL, don't return the components,
1705 but check for validity only.
1707 Note: Only addresses in canonical form are recognized.
1708 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1709 canonical form so that they will be recognized. */
1712 s390_decompose_address (rtx addr, struct s390_address *out)
1714 HOST_WIDE_INT offset = 0;
1715 rtx base = NULL_RTX;
1716 rtx indx = NULL_RTX;
1717 rtx disp = NULL_RTX;
1719 bool pointer = false;
1720 bool base_ptr = false;
1721 bool indx_ptr = false;
1722 bool literal_pool = false;
1724 /* We may need to substitute the literal pool base register into the address
1725 below. However, at this point we do not know which register is going to
1726 be used as base, so we substitute the arg pointer register. This is going
1727 to be treated as holding a pointer below -- it shouldn't be used for any
1729 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1731 /* Decompose address into base + index + displacement. */
1733 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1736 else if (GET_CODE (addr) == PLUS)
1738 rtx op0 = XEXP (addr, 0);
1739 rtx op1 = XEXP (addr, 1);
1740 enum rtx_code code0 = GET_CODE (op0);
1741 enum rtx_code code1 = GET_CODE (op1);
1743 if (code0 == REG || code0 == UNSPEC)
1745 if (code1 == REG || code1 == UNSPEC)
1747 indx = op0; /* index + base */
1753 base = op0; /* base + displacement */
1758 else if (code0 == PLUS)
1760 indx = XEXP (op0, 0); /* index + base + disp */
1761 base = XEXP (op0, 1);
1772 disp = addr; /* displacement */
1774 /* Extract integer part of displacement. */
1778 if (GET_CODE (disp) == CONST_INT)
1780 offset = INTVAL (disp);
1783 else if (GET_CODE (disp) == CONST
1784 && GET_CODE (XEXP (disp, 0)) == PLUS
1785 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1787 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1788 disp = XEXP (XEXP (disp, 0), 0);
1792 /* Strip off CONST here to avoid special case tests later. */
1793 if (disp && GET_CODE (disp) == CONST)
1794 disp = XEXP (disp, 0);
1796 /* We can convert literal pool addresses to
1797 displacements by basing them off the base register. */
1798 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1800 /* Either base or index must be free to hold the base register. */
1802 base = fake_pool_base, literal_pool = true;
1804 indx = fake_pool_base, literal_pool = true;
1808 /* Mark up the displacement. */
1809 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1810 UNSPEC_LTREL_OFFSET);
1813 /* Validate base register. */
1816 if (GET_CODE (base) == UNSPEC)
1817 switch (XINT (base, 1))
1821 disp = gen_rtx_UNSPEC (Pmode,
1822 gen_rtvec (1, XVECEXP (base, 0, 0)),
1823 UNSPEC_LTREL_OFFSET);
1827 base = XVECEXP (base, 0, 1);
1830 case UNSPEC_LTREL_BASE:
1831 if (XVECLEN (base, 0) == 1)
1832 base = fake_pool_base, literal_pool = true;
1834 base = XVECEXP (base, 0, 1);
1842 || (GET_MODE (base) != SImode
1843 && GET_MODE (base) != Pmode))
1846 if (REGNO (base) == STACK_POINTER_REGNUM
1847 || REGNO (base) == FRAME_POINTER_REGNUM
1848 || ((reload_completed || reload_in_progress)
1849 && frame_pointer_needed
1850 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1851 || REGNO (base) == ARG_POINTER_REGNUM
1853 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1854 pointer = base_ptr = true;
1856 if ((reload_completed || reload_in_progress)
1857 && base == cfun->machine->base_reg)
1858 pointer = base_ptr = literal_pool = true;
1861 /* Validate index register. */
1864 if (GET_CODE (indx) == UNSPEC)
1865 switch (XINT (indx, 1))
1869 disp = gen_rtx_UNSPEC (Pmode,
1870 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1871 UNSPEC_LTREL_OFFSET);
1875 indx = XVECEXP (indx, 0, 1);
1878 case UNSPEC_LTREL_BASE:
1879 if (XVECLEN (indx, 0) == 1)
1880 indx = fake_pool_base, literal_pool = true;
1882 indx = XVECEXP (indx, 0, 1);
1890 || (GET_MODE (indx) != SImode
1891 && GET_MODE (indx) != Pmode))
1894 if (REGNO (indx) == STACK_POINTER_REGNUM
1895 || REGNO (indx) == FRAME_POINTER_REGNUM
1896 || ((reload_completed || reload_in_progress)
1897 && frame_pointer_needed
1898 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1899 || REGNO (indx) == ARG_POINTER_REGNUM
1901 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1902 pointer = indx_ptr = true;
1904 if ((reload_completed || reload_in_progress)
1905 && indx == cfun->machine->base_reg)
1906 pointer = indx_ptr = literal_pool = true;
1909 /* Prefer to use pointer as base, not index. */
1910 if (base && indx && !base_ptr
1911 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1918 /* Validate displacement. */
1921 /* If virtual registers are involved, the displacement will change later
1922 anyway as the virtual registers get eliminated. This could make a
1923 valid displacement invalid, but it is more likely to make an invalid
1924 displacement valid, because we sometimes access the register save area
1925 via negative offsets to one of those registers.
1926 Thus we don't check the displacement for validity here. If after
1927 elimination the displacement turns out to be invalid after all,
1928 this is fixed up by reload in any case. */
1929 if (base != arg_pointer_rtx
1930 && indx != arg_pointer_rtx
1931 && base != return_address_pointer_rtx
1932 && indx != return_address_pointer_rtx
1933 && base != frame_pointer_rtx
1934 && indx != frame_pointer_rtx
1935 && base != virtual_stack_vars_rtx
1936 && indx != virtual_stack_vars_rtx)
1937 if (!DISP_IN_RANGE (offset))
1942 /* All the special cases are pointers. */
1945 /* In the small-PIC case, the linker converts @GOT
1946 and @GOTNTPOFF offsets to possible displacements. */
1947 if (GET_CODE (disp) == UNSPEC
1948 && (XINT (disp, 1) == UNSPEC_GOT
1949 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1955 /* Accept pool label offsets. */
1956 else if (GET_CODE (disp) == UNSPEC
1957 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
1960 /* Accept literal pool references. */
1961 else if (GET_CODE (disp) == UNSPEC
1962 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1964 orig_disp = gen_rtx_CONST (Pmode, disp);
1967 /* If we have an offset, make sure it does not
1968 exceed the size of the constant pool entry. */
1969 rtx sym = XVECEXP (disp, 0, 0);
1970 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1973 orig_disp = plus_constant (orig_disp, offset);
1988 out->disp = orig_disp;
1989 out->pointer = pointer;
1990 out->literal_pool = literal_pool;
1996 /* Decompose a RTL expression OP for a shift count into its components,
1997 and return the base register in BASE and the offset in OFFSET.
1999 Return true if OP is a valid shift count, false if not. */
2002 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2004 HOST_WIDE_INT off = 0;
2006 /* We can have an integer constant, an address register,
2007 or a sum of the two. */
2008 if (GET_CODE (op) == CONST_INT)
2013 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2015 off = INTVAL (XEXP (op, 1));
2018 while (op && GET_CODE (op) == SUBREG)
2019 op = SUBREG_REG (op);
2021 if (op && GET_CODE (op) != REG)
2033 /* Return true if CODE is a valid address without index. */
2036 s390_legitimate_address_without_index_p (rtx op)
2038 struct s390_address addr;
2040 if (!s390_decompose_address (XEXP (op, 0), &addr))
2049 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2050 and return these parts in SYMREF and ADDEND. You can pass NULL in
2051 SYMREF and/or ADDEND if you are not interested in these values. */
2054 s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2056 HOST_WIDE_INT tmpaddend = 0;
2058 if (GET_CODE (addr) == CONST)
2059 addr = XEXP (addr, 0);
2061 if (GET_CODE (addr) == PLUS)
2063 if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
2064 && CONST_INT_P (XEXP (addr, 1)))
2066 tmpaddend = INTVAL (XEXP (addr, 1));
2067 addr = XEXP (addr, 0);
2073 if (GET_CODE (addr) != SYMBOL_REF)
2079 *addend = tmpaddend;
2085 /* Return true if the address in OP is valid for constraint letter C
2086 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2087 pool MEMs should be accepted. Only the Q, R, S, T constraint
2088 letters are allowed for C. */
2091 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2093 struct s390_address addr;
2094 bool decomposed = false;
2096 /* This check makes sure that no symbolic address (except literal
2097 pool references) are accepted by the R or T constraints. */
2098 if (s390_symref_operand_p (op, NULL, NULL))
2102 if (!s390_decompose_address (op, &addr))
2104 if (!addr.literal_pool)
2111 case 'Q': /* no index short displacement */
2112 if (!decomposed && !s390_decompose_address (op, &addr))
2116 if (!s390_short_displacement (addr.disp))
2120 case 'R': /* with index short displacement */
2121 if (TARGET_LONG_DISPLACEMENT)
2123 if (!decomposed && !s390_decompose_address (op, &addr))
2125 if (!s390_short_displacement (addr.disp))
2128 /* Any invalid address here will be fixed up by reload,
2129 so accept it for the most generic constraint. */
2132 case 'S': /* no index long displacement */
2133 if (!TARGET_LONG_DISPLACEMENT)
2135 if (!decomposed && !s390_decompose_address (op, &addr))
2139 if (s390_short_displacement (addr.disp))
2143 case 'T': /* with index long displacement */
2144 if (!TARGET_LONG_DISPLACEMENT)
2146 /* Any invalid address here will be fixed up by reload,
2147 so accept it for the most generic constraint. */
2148 if ((decomposed || s390_decompose_address (op, &addr))
2149 && s390_short_displacement (addr.disp))
2159 /* Evaluates constraint strings described by the regular expression
2160 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2161 the constraint given in STR, or 0 else. */
2164 s390_mem_constraint (const char *str, rtx op)
2171 /* Check for offsettable variants of memory constraints. */
2172 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2174 if ((reload_completed || reload_in_progress)
2175 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2177 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2179 /* Check for non-literal-pool variants of memory constraints. */
2182 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2187 if (GET_CODE (op) != MEM)
2189 return s390_check_qrst_address (c, XEXP (op, 0), true);
2191 return (s390_check_qrst_address ('Q', op, true)
2192 || s390_check_qrst_address ('R', op, true));
2194 return (s390_check_qrst_address ('S', op, true)
2195 || s390_check_qrst_address ('T', op, true));
2197 /* Simply check for the basic form of a shift count. Reload will
2198 take care of making sure we have a proper base register. */
2199 if (!s390_decompose_shift_count (op, NULL, NULL))
2203 return s390_check_qrst_address (str[1], op, true);
2211 /* Evaluates constraint strings starting with letter O. Input
2212 parameter C is the second letter following the "O" in the constraint
2213 string. Returns 1 if VALUE meets the respective constraint and 0
2217 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2225 return trunc_int_for_mode (value, SImode) == value;
2229 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2232 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2240 /* Evaluates constraint strings starting with letter N. Parameter STR
2241 contains the letters following letter "N" in the constraint string.
2242 Returns true if VALUE matches the constraint. */
2245 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2247 enum machine_mode mode, part_mode;
2249 int part, part_goal;
2255 part_goal = str[0] - '0';
2299 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2302 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2305 if (part_goal != -1 && part_goal != part)
2312 /* Returns true if the input parameter VALUE is a float zero. */
2315 s390_float_const_zero_p (rtx value)
2317 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2318 && value == CONST0_RTX (GET_MODE (value)));
2322 /* Compute a (partial) cost for rtx X. Return true if the complete
2323 cost has been computed, and false if subexpressions should be
2324 scanned. In either case, *TOTAL contains the cost result.
2325 CODE contains GET_CODE (x), OUTER_CODE contains the code
2326 of the superexpression of x. */
2329 s390_rtx_costs (rtx x, int code, int outer_code, int *total,
2330 bool speed ATTRIBUTE_UNUSED)
2353 *total = COSTS_N_INSNS (1);
2358 /* Check for multiply and add. */
2359 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2360 && GET_CODE (XEXP (x, 0)) == MULT
2361 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD)
2363 /* This is the multiply and add case. */
2364 if (GET_MODE (x) == DFmode)
2365 *total = s390_cost->madbr;
2367 *total = s390_cost->maebr;
2368 *total += (rtx_cost (XEXP (XEXP (x, 0), 0), MULT, speed)
2369 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT, speed)
2370 + rtx_cost (XEXP (x, 1), (enum rtx_code) code, speed));
2371 return true; /* Do not do an additional recursive descent. */
2373 *total = COSTS_N_INSNS (1);
2377 switch (GET_MODE (x))
2381 rtx left = XEXP (x, 0);
2382 rtx right = XEXP (x, 1);
2383 if (GET_CODE (right) == CONST_INT
2384 && CONST_OK_FOR_K (INTVAL (right)))
2385 *total = s390_cost->mhi;
2386 else if (GET_CODE (left) == SIGN_EXTEND)
2387 *total = s390_cost->mh;
2389 *total = s390_cost->ms; /* msr, ms, msy */
2394 rtx left = XEXP (x, 0);
2395 rtx right = XEXP (x, 1);
2398 if (GET_CODE (right) == CONST_INT
2399 && CONST_OK_FOR_K (INTVAL (right)))
2400 *total = s390_cost->mghi;
2401 else if (GET_CODE (left) == SIGN_EXTEND)
2402 *total = s390_cost->msgf;
2404 *total = s390_cost->msg; /* msgr, msg */
2406 else /* TARGET_31BIT */
2408 if (GET_CODE (left) == SIGN_EXTEND
2409 && GET_CODE (right) == SIGN_EXTEND)
2410 /* mulsidi case: mr, m */
2411 *total = s390_cost->m;
2412 else if (GET_CODE (left) == ZERO_EXTEND
2413 && GET_CODE (right) == ZERO_EXTEND
2414 && TARGET_CPU_ZARCH)
2415 /* umulsidi case: ml, mlr */
2416 *total = s390_cost->ml;
2418 /* Complex calculation is required. */
2419 *total = COSTS_N_INSNS (40);
2425 *total = s390_cost->mult_df;
2428 *total = s390_cost->mxbr;
2437 if (GET_MODE (x) == TImode) /* 128 bit division */
2438 *total = s390_cost->dlgr;
2439 else if (GET_MODE (x) == DImode)
2441 rtx right = XEXP (x, 1);
2442 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2443 *total = s390_cost->dlr;
2444 else /* 64 by 64 bit division */
2445 *total = s390_cost->dlgr;
2447 else if (GET_MODE (x) == SImode) /* 32 bit division */
2448 *total = s390_cost->dlr;
2453 if (GET_MODE (x) == DImode)
2455 rtx right = XEXP (x, 1);
2456 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2458 *total = s390_cost->dsgfr;
2460 *total = s390_cost->dr;
2461 else /* 64 by 64 bit division */
2462 *total = s390_cost->dsgr;
2464 else if (GET_MODE (x) == SImode) /* 32 bit division */
2465 *total = s390_cost->dlr;
2466 else if (GET_MODE (x) == SFmode)
2468 *total = s390_cost->debr;
2470 else if (GET_MODE (x) == DFmode)
2472 *total = s390_cost->ddbr;
2474 else if (GET_MODE (x) == TFmode)
2476 *total = s390_cost->dxbr;
2481 if (GET_MODE (x) == SFmode)
2482 *total = s390_cost->sqebr;
2483 else if (GET_MODE (x) == DFmode)
2484 *total = s390_cost->sqdbr;
2486 *total = s390_cost->sqxbr;
2491 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2492 || outer_code == PLUS || outer_code == MINUS
2493 || outer_code == COMPARE)
2498 *total = COSTS_N_INSNS (1);
2499 if (GET_CODE (XEXP (x, 0)) == AND
2500 && GET_CODE (XEXP (x, 1)) == CONST_INT
2501 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2503 rtx op0 = XEXP (XEXP (x, 0), 0);
2504 rtx op1 = XEXP (XEXP (x, 0), 1);
2505 rtx op2 = XEXP (x, 1);
2507 if (memory_operand (op0, GET_MODE (op0))
2508 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2510 if (register_operand (op0, GET_MODE (op0))
2511 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2521 /* Return the cost of an address rtx ADDR. */
2524 s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
2526 struct s390_address ad;
2527 if (!s390_decompose_address (addr, &ad))
2530 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2533 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2534 otherwise return 0. */
2537 tls_symbolic_operand (rtx op)
2539 if (GET_CODE (op) != SYMBOL_REF)
2541 return SYMBOL_REF_TLS_MODEL (op);
2544 /* Split DImode access register reference REG (on 64-bit) into its constituent
2545 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2546 gen_highpart cannot be used as they assume all registers are word-sized,
2547 while our access registers have only half that size. */
2550 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2552 gcc_assert (TARGET_64BIT);
2553 gcc_assert (ACCESS_REG_P (reg));
2554 gcc_assert (GET_MODE (reg) == DImode);
2555 gcc_assert (!(REGNO (reg) & 1));
2557 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2558 *hi = gen_rtx_REG (SImode, REGNO (reg));
2561 /* Return true if OP contains a symbol reference */
2564 symbolic_reference_mentioned_p (rtx op)
2569 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2572 fmt = GET_RTX_FORMAT (GET_CODE (op));
2573 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2579 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2580 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2584 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2591 /* Return true if OP contains a reference to a thread-local symbol. */
2594 tls_symbolic_reference_mentioned_p (rtx op)
2599 if (GET_CODE (op) == SYMBOL_REF)
2600 return tls_symbolic_operand (op);
2602 fmt = GET_RTX_FORMAT (GET_CODE (op));
2603 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2609 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2610 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2614 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2622 /* Return true if OP is a legitimate general operand when
2623 generating PIC code. It is given that flag_pic is on
2624 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2627 legitimate_pic_operand_p (rtx op)
2629 /* Accept all non-symbolic constants. */
2630 if (!SYMBOLIC_CONST (op))
2633 /* Reject everything else; must be handled
2634 via emit_symbolic_move. */
2638 /* Returns true if the constant value OP is a legitimate general operand.
2639 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2642 legitimate_constant_p (rtx op)
2644 /* Accept all non-symbolic constants. */
2645 if (!SYMBOLIC_CONST (op))
2648 /* Accept immediate LARL operands. */
2649 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2652 /* Thread-local symbols are never legal constants. This is
2653 so that emit_call knows that computing such addresses
2654 might require a function call. */
2655 if (TLS_SYMBOLIC_CONST (op))
2658 /* In the PIC case, symbolic constants must *not* be
2659 forced into the literal pool. We accept them here,
2660 so that they will be handled by emit_symbolic_move. */
2664 /* All remaining non-PIC symbolic constants are
2665 forced into the literal pool. */
2669 /* Determine if it's legal to put X into the constant pool. This
2670 is not possible if X contains the address of a symbol that is
2671 not constant (TLS) or not known at final link time (PIC). */
2674 s390_cannot_force_const_mem (rtx x)
2676 switch (GET_CODE (x))
2680 /* Accept all non-symbolic constants. */
2684 /* Labels are OK iff we are non-PIC. */
2685 return flag_pic != 0;
2688 /* 'Naked' TLS symbol references are never OK,
2689 non-TLS symbols are OK iff we are non-PIC. */
2690 if (tls_symbolic_operand (x))
2693 return flag_pic != 0;
2696 return s390_cannot_force_const_mem (XEXP (x, 0));
2699 return s390_cannot_force_const_mem (XEXP (x, 0))
2700 || s390_cannot_force_const_mem (XEXP (x, 1));
2703 switch (XINT (x, 1))
2705 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2706 case UNSPEC_LTREL_OFFSET:
2714 case UNSPEC_GOTNTPOFF:
2715 case UNSPEC_INDNTPOFF:
2718 /* If the literal pool shares the code section, be put
2719 execute template placeholders into the pool as well. */
2721 return TARGET_CPU_ZARCH;
2733 /* Returns true if the constant value OP is a legitimate general
2734 operand during and after reload. The difference to
2735 legitimate_constant_p is that this function will not accept
2736 a constant that would need to be forced to the literal pool
2737 before it can be used as operand. */
2740 legitimate_reload_constant_p (rtx op)
2742 /* Accept la(y) operands. */
2743 if (GET_CODE (op) == CONST_INT
2744 && DISP_IN_RANGE (INTVAL (op)))
2747 /* Accept l(g)hi/l(g)fi operands. */
2748 if (GET_CODE (op) == CONST_INT
2749 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2752 /* Accept lliXX operands. */
2754 && GET_CODE (op) == CONST_INT
2755 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2756 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2760 && GET_CODE (op) == CONST_INT
2761 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2762 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2765 /* Accept larl operands. */
2766 if (TARGET_CPU_ZARCH
2767 && larl_operand (op, VOIDmode))
2770 /* Accept lzXX operands. */
2771 if (GET_CODE (op) == CONST_DOUBLE
2772 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
2775 /* Accept double-word operands that can be split. */
2776 if (GET_CODE (op) == CONST_INT
2777 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2779 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2780 rtx hi = operand_subword (op, 0, 0, dword_mode);
2781 rtx lo = operand_subword (op, 1, 0, dword_mode);
2782 return legitimate_reload_constant_p (hi)
2783 && legitimate_reload_constant_p (lo);
2786 /* Everything else cannot be handled without reload. */
2790 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2791 return the class of reg to actually use. */
2794 s390_preferred_reload_class (rtx op, enum reg_class rclass)
2796 switch (GET_CODE (op))
2798 /* Constants we cannot reload must be forced into the
2803 if (legitimate_reload_constant_p (op))
2808 /* If a symbolic constant or a PLUS is reloaded,
2809 it is most likely being used as an address, so
2810 prefer ADDR_REGS. If 'class' is not a superset
2811 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2816 if (reg_class_subset_p (ADDR_REGS, rclass))
2828 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2829 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2833 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2835 HOST_WIDE_INT addend;
2838 if (!s390_symref_operand_p (addr, &symref, &addend))
2841 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref)
2842 && !(addend & (alignment - 1)));
2845 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2846 operand SCRATCH is used to reload the even part of the address and
2850 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
2852 HOST_WIDE_INT addend;
2855 if (!s390_symref_operand_p (addr, &symref, &addend))
2859 /* Easy case. The addend is even so larl will do fine. */
2860 emit_move_insn (reg, addr);
2863 /* We can leave the scratch register untouched if the target
2864 register is a valid base register. */
2865 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
2866 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
2869 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
2870 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
2873 emit_move_insn (scratch,
2874 gen_rtx_CONST (Pmode,
2875 gen_rtx_PLUS (Pmode, symref,
2876 GEN_INT (addend - 1))));
2878 emit_move_insn (scratch, symref);
2880 /* Increment the address using la in order to avoid clobbering cc. */
2881 emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
2885 /* Generate what is necessary to move between REG and MEM using
2886 SCRATCH. The direction is given by TOMEM. */
2889 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
2891 /* Reload might have pulled a constant out of the literal pool.
2892 Force it back in. */
2893 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
2894 || GET_CODE (mem) == CONST)
2895 mem = force_const_mem (GET_MODE (reg), mem);
2897 gcc_assert (MEM_P (mem));
2899 /* For a load from memory we can leave the scratch register
2900 untouched if the target register is a valid base register. */
2902 && REGNO (reg) < FIRST_PSEUDO_REGISTER
2903 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
2904 && GET_MODE (reg) == GET_MODE (scratch))
2907 /* Load address into scratch register. Since we can't have a
2908 secondary reload for a secondary reload we have to cover the case
2909 where larl would need a secondary reload here as well. */
2910 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
2912 /* Now we can use a standard load/store to do the move. */
2914 emit_move_insn (replace_equiv_address (mem, scratch), reg);
2916 emit_move_insn (reg, replace_equiv_address (mem, scratch));
2919 /* Inform reload about cases where moving X with a mode MODE to a register in
2920 RCLASS requires an extra scratch or immediate register. Return the class
2921 needed for the immediate register. */
2923 static enum reg_class
2924 s390_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
2925 enum machine_mode mode, secondary_reload_info *sri)
2927 /* Intermediate register needed. */
2928 if (reg_classes_intersect_p (CC_REGS, rclass))
2929 return GENERAL_REGS;
2933 /* On z10 several optimizer steps may generate larl operands with
2936 && s390_symref_operand_p (x, NULL, NULL)
2938 && !s390_check_symref_alignment (x, 2))
2939 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
2940 : CODE_FOR_reloadsi_larl_odd_addend_z10);
2942 /* On z10 we need a scratch register when moving QI, TI or floating
2943 point mode values from or to a memory location with a SYMBOL_REF
2944 or if the symref addend of a SI or DI move is not aligned to the
2945 width of the access. */
2947 && s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
2948 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
2949 || (!TARGET_64BIT && mode == DImode)
2950 || ((mode == HImode || mode == SImode || mode == DImode)
2951 && (!s390_check_symref_alignment (XEXP (x, 0),
2952 GET_MODE_SIZE (mode))))))
2954 #define __SECONDARY_RELOAD_CASE(M,m) \
2957 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
2958 CODE_FOR_reload##m##di_tomem_z10; \
2960 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
2961 CODE_FOR_reload##m##si_tomem_z10; \
2964 switch (GET_MODE (x))
2966 __SECONDARY_RELOAD_CASE (QI, qi);
2967 __SECONDARY_RELOAD_CASE (HI, hi);
2968 __SECONDARY_RELOAD_CASE (SI, si);
2969 __SECONDARY_RELOAD_CASE (DI, di);
2970 __SECONDARY_RELOAD_CASE (TI, ti);
2971 __SECONDARY_RELOAD_CASE (SF, sf);
2972 __SECONDARY_RELOAD_CASE (DF, df);
2973 __SECONDARY_RELOAD_CASE (TF, tf);
2974 __SECONDARY_RELOAD_CASE (SD, sd);
2975 __SECONDARY_RELOAD_CASE (DD, dd);
2976 __SECONDARY_RELOAD_CASE (TD, td);
2981 #undef __SECONDARY_RELOAD_CASE
2985 /* We need a scratch register when loading a PLUS expression which
2986 is not a legitimate operand of the LOAD ADDRESS instruction. */
2987 if (in_p && s390_plus_operand (x, mode))
2988 sri->icode = (TARGET_64BIT ?
2989 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
2991 /* Performing a multiword move from or to memory we have to make sure the
2992 second chunk in memory is addressable without causing a displacement
2993 overflow. If that would be the case we calculate the address in
2994 a scratch register. */
2996 && GET_CODE (XEXP (x, 0)) == PLUS
2997 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2998 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
2999 + GET_MODE_SIZE (mode) - 1))
3001 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3002 in a s_operand address since we may fallback to lm/stm. So we only
3003 have to care about overflows in the b+i+d case. */
3004 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3005 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3006 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3007 /* For FP_REGS no lm/stm is available so this check is triggered
3008 for displacement overflows in b+i+d and b+d like addresses. */
3009 || (reg_classes_intersect_p (FP_REGS, rclass)
3010 && s390_class_max_nregs (FP_REGS, mode) > 1))
3013 sri->icode = (TARGET_64BIT ?
3014 CODE_FOR_reloaddi_nonoffmem_in :
3015 CODE_FOR_reloadsi_nonoffmem_in);
3017 sri->icode = (TARGET_64BIT ?
3018 CODE_FOR_reloaddi_nonoffmem_out :
3019 CODE_FOR_reloadsi_nonoffmem_out);
3023 /* A scratch address register is needed when a symbolic constant is
3024 copied to r0 compiling with -fPIC. In other cases the target
3025 register might be used as temporary (see legitimize_pic_address). */
3026 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3027 sri->icode = (TARGET_64BIT ?
3028 CODE_FOR_reloaddi_PIC_addr :
3029 CODE_FOR_reloadsi_PIC_addr);
3031 /* Either scratch or no register needed. */
3035 /* Generate code to load SRC, which is PLUS that is not a
3036 legitimate operand for the LA instruction, into TARGET.
3037 SCRATCH may be used as scratch register. */
3040 s390_expand_plus_operand (rtx target, rtx src,
3044 struct s390_address ad;
3046 /* src must be a PLUS; get its two operands. */
3047 gcc_assert (GET_CODE (src) == PLUS);
3048 gcc_assert (GET_MODE (src) == Pmode);
3050 /* Check if any of the two operands is already scheduled
3051 for replacement by reload. This can happen e.g. when
3052 float registers occur in an address. */
3053 sum1 = find_replacement (&XEXP (src, 0));
3054 sum2 = find_replacement (&XEXP (src, 1));
3055 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3057 /* If the address is already strictly valid, there's nothing to do. */
3058 if (!s390_decompose_address (src, &ad)
3059 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3060 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3062 /* Otherwise, one of the operands cannot be an address register;
3063 we reload its value into the scratch register. */
3064 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3066 emit_move_insn (scratch, sum1);
3069 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3071 emit_move_insn (scratch, sum2);
3075 /* According to the way these invalid addresses are generated
3076 in reload.c, it should never happen (at least on s390) that
3077 *neither* of the PLUS components, after find_replacements
3078 was applied, is an address register. */
3079 if (sum1 == scratch && sum2 == scratch)
3085 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3088 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3089 is only ever performed on addresses, so we can mark the
3090 sum as legitimate for LA in any case. */
3091 s390_load_address (target, src);
3095 /* Return true if ADDR is a valid memory address.
3096 STRICT specifies whether strict register checking applies. */
3099 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3101 struct s390_address ad;
3104 && larl_operand (addr, VOIDmode)
3105 && (mode == VOIDmode
3106 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3109 if (!s390_decompose_address (addr, &ad))
3114 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3117 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3123 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3124 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3128 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3129 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3135 /* Return true if OP is a valid operand for the LA instruction.
3136 In 31-bit, we need to prove that the result is used as an
3137 address, as LA performs only a 31-bit addition. */
3140 legitimate_la_operand_p (rtx op)
3142 struct s390_address addr;
3143 if (!s390_decompose_address (op, &addr))
3146 return (TARGET_64BIT || addr.pointer);
3149 /* Return true if it is valid *and* preferable to use LA to
3150 compute the sum of OP1 and OP2. */
3153 preferred_la_operand_p (rtx op1, rtx op2)
3155 struct s390_address addr;
3157 if (op2 != const0_rtx)
3158 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3160 if (!s390_decompose_address (op1, &addr))
3162 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3164 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3167 if (!TARGET_64BIT && !addr.pointer)
3173 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3174 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3180 /* Emit a forced load-address operation to load SRC into DST.
3181 This will use the LOAD ADDRESS instruction even in situations
3182 where legitimate_la_operand_p (SRC) returns false. */
3185 s390_load_address (rtx dst, rtx src)
3188 emit_move_insn (dst, src);
3190 emit_insn (gen_force_la_31 (dst, src));
3193 /* Return a legitimate reference for ORIG (an address) using the
3194 register REG. If REG is 0, a new pseudo is generated.
3196 There are two types of references that must be handled:
3198 1. Global data references must load the address from the GOT, via
3199 the PIC reg. An insn is emitted to do this load, and the reg is
3202 2. Static data references, constant pool addresses, and code labels
3203 compute the address as an offset from the GOT, whose base is in
3204 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3205 differentiate them from global data objects. The returned
3206 address is the PIC reg + an unspec constant.
3208 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3209 reg also appears in the address. */
3212 legitimize_pic_address (rtx orig, rtx reg)
3218 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3220 if (GET_CODE (addr) == LABEL_REF
3221 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
3223 /* This is a local symbol. */
3224 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
3226 /* Access local symbols PC-relative via LARL.
3227 This is the same as in the non-PIC case, so it is
3228 handled automatically ... */
3232 /* Access local symbols relative to the GOT. */
3234 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3236 if (reload_in_progress || reload_completed)
3237 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3239 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3240 addr = gen_rtx_CONST (Pmode, addr);
3241 addr = force_const_mem (Pmode, addr);
3242 emit_move_insn (temp, addr);
3244 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3247 s390_load_address (reg, new_rtx);
3252 else if (GET_CODE (addr) == SYMBOL_REF)
3255 reg = gen_reg_rtx (Pmode);
3259 /* Assume GOT offset < 4k. This is handled the same way
3260 in both 31- and 64-bit code (@GOT). */
3262 if (reload_in_progress || reload_completed)
3263 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3265 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3266 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3267 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3268 new_rtx = gen_const_mem (Pmode, new_rtx);
3269 emit_move_insn (reg, new_rtx);
3272 else if (TARGET_CPU_ZARCH)
3274 /* If the GOT offset might be >= 4k, we determine the position
3275 of the GOT entry via a PC-relative LARL (@GOTENT). */
3277 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3279 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3280 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3282 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3283 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3284 emit_move_insn (temp, new_rtx);
3286 new_rtx = gen_const_mem (Pmode, temp);
3287 emit_move_insn (reg, new_rtx);
3292 /* If the GOT offset might be >= 4k, we have to load it
3293 from the literal pool (@GOT). */
3295 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3297 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3298 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3300 if (reload_in_progress || reload_completed)
3301 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3303 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3304 addr = gen_rtx_CONST (Pmode, addr);
3305 addr = force_const_mem (Pmode, addr);
3306 emit_move_insn (temp, addr);
3308 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3309 new_rtx = gen_const_mem (Pmode, new_rtx);
3310 emit_move_insn (reg, new_rtx);
3316 if (GET_CODE (addr) == CONST)
3318 addr = XEXP (addr, 0);
3319 if (GET_CODE (addr) == UNSPEC)
3321 gcc_assert (XVECLEN (addr, 0) == 1);
3322 switch (XINT (addr, 1))
3324 /* If someone moved a GOT-relative UNSPEC
3325 out of the literal pool, force them back in. */
3328 new_rtx = force_const_mem (Pmode, orig);
3331 /* @GOT is OK as is if small. */
3334 new_rtx = force_const_mem (Pmode, orig);
3337 /* @GOTENT is OK as is. */
3341 /* @PLT is OK as is on 64-bit, must be converted to
3342 GOT-relative @PLTOFF on 31-bit. */
3344 if (!TARGET_CPU_ZARCH)
3346 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3348 if (reload_in_progress || reload_completed)
3349 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3351 addr = XVECEXP (addr, 0, 0);
3352 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3354 addr = gen_rtx_CONST (Pmode, addr);
3355 addr = force_const_mem (Pmode, addr);
3356 emit_move_insn (temp, addr);
3358 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3361 s390_load_address (reg, new_rtx);
3367 /* Everything else cannot happen. */
3373 gcc_assert (GET_CODE (addr) == PLUS);
3375 if (GET_CODE (addr) == PLUS)
3377 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
3379 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
3380 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
3382 /* Check first to see if this is a constant offset
3383 from a local symbol reference. */
3384 if ((GET_CODE (op0) == LABEL_REF
3385 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3386 && GET_CODE (op1) == CONST_INT)
3388 if (TARGET_CPU_ZARCH
3389 && larl_operand (op0, VOIDmode)
3390 && INTVAL (op1) < (HOST_WIDE_INT)1 << 31
3391 && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31))
3393 if (INTVAL (op1) & 1)
3395 /* LARL can't handle odd offsets, so emit a
3396 pair of LARL and LA. */
3397 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3399 if (!DISP_IN_RANGE (INTVAL (op1)))
3401 HOST_WIDE_INT even = INTVAL (op1) - 1;
3402 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3403 op0 = gen_rtx_CONST (Pmode, op0);
3407 emit_move_insn (temp, op0);
3408 new_rtx = gen_rtx_PLUS (Pmode, temp, op1);
3412 s390_load_address (reg, new_rtx);
3418 /* If the offset is even, we can just use LARL.
3419 This will happen automatically. */
3424 /* Access local symbols relative to the GOT. */
3426 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3428 if (reload_in_progress || reload_completed)
3429 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3431 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3433 addr = gen_rtx_PLUS (Pmode, addr, op1);
3434 addr = gen_rtx_CONST (Pmode, addr);
3435 addr = force_const_mem (Pmode, addr);
3436 emit_move_insn (temp, addr);
3438 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3441 s390_load_address (reg, new_rtx);
3447 /* Now, check whether it is a GOT relative symbol plus offset
3448 that was pulled out of the literal pool. Force it back in. */
3450 else if (GET_CODE (op0) == UNSPEC
3451 && GET_CODE (op1) == CONST_INT
3452 && XINT (op0, 1) == UNSPEC_GOTOFF)
3454 gcc_assert (XVECLEN (op0, 0) == 1);
3456 new_rtx = force_const_mem (Pmode, orig);
3459 /* Otherwise, compute the sum. */
3462 base = legitimize_pic_address (XEXP (addr, 0), reg);
3463 new_rtx = legitimize_pic_address (XEXP (addr, 1),
3464 base == reg ? NULL_RTX : reg);
3465 if (GET_CODE (new_rtx) == CONST_INT)
3466 new_rtx = plus_constant (base, INTVAL (new_rtx));
3469 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3471 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3472 new_rtx = XEXP (new_rtx, 1);
3474 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3477 if (GET_CODE (new_rtx) == CONST)
3478 new_rtx = XEXP (new_rtx, 0);
3479 new_rtx = force_operand (new_rtx, 0);
3486 /* Load the thread pointer into a register. */
3489 s390_get_thread_pointer (void)
3491 rtx tp = gen_reg_rtx (Pmode);
3493 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3494 mark_reg_pointer (tp, BITS_PER_WORD);
3499 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3500 in s390_tls_symbol which always refers to __tls_get_offset.
3501 The returned offset is written to RESULT_REG and an USE rtx is
3502 generated for TLS_CALL. */
3504 static GTY(()) rtx s390_tls_symbol;
3507 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3511 gcc_assert (flag_pic);
3513 if (!s390_tls_symbol)
3514 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3516 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3517 gen_rtx_REG (Pmode, RETURN_REGNUM));
3519 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3520 RTL_CONST_CALL_P (insn) = 1;
3523 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3524 this (thread-local) address. REG may be used as temporary. */
3527 legitimize_tls_address (rtx addr, rtx reg)
3529 rtx new_rtx, tls_call, temp, base, r2, insn;
3531 if (GET_CODE (addr) == SYMBOL_REF)
3532 switch (tls_symbolic_operand (addr))
3534 case TLS_MODEL_GLOBAL_DYNAMIC:
3536 r2 = gen_rtx_REG (Pmode, 2);
3537 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3538 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3539 new_rtx = force_const_mem (Pmode, new_rtx);
3540 emit_move_insn (r2, new_rtx);
3541 s390_emit_tls_call_insn (r2, tls_call);
3542 insn = get_insns ();
3545 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3546 temp = gen_reg_rtx (Pmode);
3547 emit_libcall_block (insn, temp, r2, new_rtx);
3549 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3552 s390_load_address (reg, new_rtx);
3557 case TLS_MODEL_LOCAL_DYNAMIC:
3559 r2 = gen_rtx_REG (Pmode, 2);
3560 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3561 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3562 new_rtx = force_const_mem (Pmode, new_rtx);
3563 emit_move_insn (r2, new_rtx);
3564 s390_emit_tls_call_insn (r2, tls_call);
3565 insn = get_insns ();
3568 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3569 temp = gen_reg_rtx (Pmode);
3570 emit_libcall_block (insn, temp, r2, new_rtx);
3572 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3573 base = gen_reg_rtx (Pmode);
3574 s390_load_address (base, new_rtx);
3576 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3577 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3578 new_rtx = force_const_mem (Pmode, new_rtx);
3579 temp = gen_reg_rtx (Pmode);
3580 emit_move_insn (temp, new_rtx);
3582 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3585 s390_load_address (reg, new_rtx);
3590 case TLS_MODEL_INITIAL_EXEC:
3593 /* Assume GOT offset < 4k. This is handled the same way
3594 in both 31- and 64-bit code. */
3596 if (reload_in_progress || reload_completed)
3597 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3599 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3600 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3601 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3602 new_rtx = gen_const_mem (Pmode, new_rtx);
3603 temp = gen_reg_rtx (Pmode);
3604 emit_move_insn (temp, new_rtx);
3606 else if (TARGET_CPU_ZARCH)
3608 /* If the GOT offset might be >= 4k, we determine the position
3609 of the GOT entry via a PC-relative LARL. */
3611 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3612 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3613 temp = gen_reg_rtx (Pmode);
3614 emit_move_insn (temp, new_rtx);
3616 new_rtx = gen_const_mem (Pmode, temp);
3617 temp = gen_reg_rtx (Pmode);
3618 emit_move_insn (temp, new_rtx);
3622 /* If the GOT offset might be >= 4k, we have to load it
3623 from the literal pool. */
3625 if (reload_in_progress || reload_completed)
3626 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3628 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3629 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3630 new_rtx = force_const_mem (Pmode, new_rtx);
3631 temp = gen_reg_rtx (Pmode);
3632 emit_move_insn (temp, new_rtx);
3634 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3635 new_rtx = gen_const_mem (Pmode, new_rtx);
3637 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3638 temp = gen_reg_rtx (Pmode);
3639 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3643 /* In position-dependent code, load the absolute address of
3644 the GOT entry from the literal pool. */
3646 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3647 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3648 new_rtx = force_const_mem (Pmode, new_rtx);
3649 temp = gen_reg_rtx (Pmode);
3650 emit_move_insn (temp, new_rtx);
3653 new_rtx = gen_const_mem (Pmode, new_rtx);
3654 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3655 temp = gen_reg_rtx (Pmode);
3656 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3659 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3662 s390_load_address (reg, new_rtx);
3667 case TLS_MODEL_LOCAL_EXEC:
3668 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3669 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3670 new_rtx = force_const_mem (Pmode, new_rtx);
3671 temp = gen_reg_rtx (Pmode);
3672 emit_move_insn (temp, new_rtx);
3674 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3677 s390_load_address (reg, new_rtx);
3686 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3688 switch (XINT (XEXP (addr, 0), 1))
3690 case UNSPEC_INDNTPOFF:
3691 gcc_assert (TARGET_CPU_ZARCH);
3700 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3701 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3703 new_rtx = XEXP (XEXP (addr, 0), 0);
3704 if (GET_CODE (new_rtx) != SYMBOL_REF)
3705 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3707 new_rtx = legitimize_tls_address (new_rtx, reg);
3708 new_rtx = plus_constant (new_rtx, INTVAL (XEXP (XEXP (addr, 0), 1)));
3709 new_rtx = force_operand (new_rtx, 0);
3713 gcc_unreachable (); /* for now ... */
3718 /* Emit insns making the address in operands[1] valid for a standard
3719 move to operands[0]. operands[1] is replaced by an address which
3720 should be used instead of the former RTX to emit the move
3724 emit_symbolic_move (rtx *operands)
3726 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3728 if (GET_CODE (operands[0]) == MEM)
3729 operands[1] = force_reg (Pmode, operands[1]);
3730 else if (TLS_SYMBOLIC_CONST (operands[1]))
3731 operands[1] = legitimize_tls_address (operands[1], temp);
3733 operands[1] = legitimize_pic_address (operands[1], temp);
3736 /* Try machine-dependent ways of modifying an illegitimate address X
3737 to be legitimate. If we find one, return the new, valid address.
3739 OLDX is the address as it was before break_out_memory_refs was called.
3740 In some cases it is useful to look at this to decide what needs to be done.
3742 MODE is the mode of the operand pointed to by X.
3744 When -fpic is used, special handling is needed for symbolic references.
3745 See comments by legitimize_pic_address for details. */
3748 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3749 enum machine_mode mode ATTRIBUTE_UNUSED)
3751 rtx constant_term = const0_rtx;
3753 if (TLS_SYMBOLIC_CONST (x))
3755 x = legitimize_tls_address (x, 0);
3757 if (s390_legitimate_address_p (mode, x, FALSE))
3760 else if (GET_CODE (x) == PLUS
3761 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3762 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3768 if (SYMBOLIC_CONST (x)
3769 || (GET_CODE (x) == PLUS
3770 && (SYMBOLIC_CONST (XEXP (x, 0))
3771 || SYMBOLIC_CONST (XEXP (x, 1)))))
3772 x = legitimize_pic_address (x, 0);
3774 if (s390_legitimate_address_p (mode, x, FALSE))
3778 x = eliminate_constant_term (x, &constant_term);
3780 /* Optimize loading of large displacements by splitting them
3781 into the multiple of 4K and the rest; this allows the
3782 former to be CSE'd if possible.
3784 Don't do this if the displacement is added to a register
3785 pointing into the stack frame, as the offsets will
3786 change later anyway. */
3788 if (GET_CODE (constant_term) == CONST_INT
3789 && !TARGET_LONG_DISPLACEMENT
3790 && !DISP_IN_RANGE (INTVAL (constant_term))
3791 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3793 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3794 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3796 rtx temp = gen_reg_rtx (Pmode);
3797 rtx val = force_operand (GEN_INT (upper), temp);
3799 emit_move_insn (temp, val);
3801 x = gen_rtx_PLUS (Pmode, x, temp);
3802 constant_term = GEN_INT (lower);
3805 if (GET_CODE (x) == PLUS)
3807 if (GET_CODE (XEXP (x, 0)) == REG)
3809 rtx temp = gen_reg_rtx (Pmode);
3810 rtx val = force_operand (XEXP (x, 1), temp);
3812 emit_move_insn (temp, val);
3814 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3817 else if (GET_CODE (XEXP (x, 1)) == REG)
3819 rtx temp = gen_reg_rtx (Pmode);
3820 rtx val = force_operand (XEXP (x, 0), temp);
3822 emit_move_insn (temp, val);
3824 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3828 if (constant_term != const0_rtx)
3829 x = gen_rtx_PLUS (Pmode, x, constant_term);
3834 /* Try a machine-dependent way of reloading an illegitimate address AD
3835 operand. If we find one, push the reload and and return the new address.
3837 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3838 and TYPE is the reload type of the current reload. */
3841 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3842 int opnum, int type)
3844 if (!optimize || TARGET_LONG_DISPLACEMENT)
3847 if (GET_CODE (ad) == PLUS)
3849 rtx tem = simplify_binary_operation (PLUS, Pmode,
3850 XEXP (ad, 0), XEXP (ad, 1));
3855 if (GET_CODE (ad) == PLUS
3856 && GET_CODE (XEXP (ad, 0)) == REG
3857 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3858 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3860 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3861 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3862 rtx cst, tem, new_rtx;
3864 cst = GEN_INT (upper);
3865 if (!legitimate_reload_constant_p (cst))
3866 cst = force_const_mem (Pmode, cst);
3868 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3869 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3871 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3872 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3873 opnum, (enum reload_type) type);
3880 /* Emit code to move LEN bytes from DST to SRC. */
3883 s390_expand_movmem (rtx dst, rtx src, rtx len)
3885 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3887 if (INTVAL (len) > 0)
3888 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3891 else if (TARGET_MVCLE)
3893 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3898 rtx dst_addr, src_addr, count, blocks, temp;
3899 rtx loop_start_label = gen_label_rtx ();
3900 rtx loop_end_label = gen_label_rtx ();
3901 rtx end_label = gen_label_rtx ();
3902 enum machine_mode mode;
3904 mode = GET_MODE (len);
3905 if (mode == VOIDmode)
3908 dst_addr = gen_reg_rtx (Pmode);
3909 src_addr = gen_reg_rtx (Pmode);
3910 count = gen_reg_rtx (mode);
3911 blocks = gen_reg_rtx (mode);
3913 convert_move (count, len, 1);
3914 emit_cmp_and_jump_insns (count, const0_rtx,
3915 EQ, NULL_RTX, mode, 1, end_label);
3917 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3918 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3919 dst = change_address (dst, VOIDmode, dst_addr);
3920 src = change_address (src, VOIDmode, src_addr);
3922 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
3925 emit_move_insn (count, temp);
3927 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
3930 emit_move_insn (blocks, temp);
3932 emit_cmp_and_jump_insns (blocks, const0_rtx,
3933 EQ, NULL_RTX, mode, 1, loop_end_label);
3935 emit_label (loop_start_label);
3937 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3938 s390_load_address (dst_addr,
3939 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3940 s390_load_address (src_addr,
3941 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
3943 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
3946 emit_move_insn (blocks, temp);
3948 emit_cmp_and_jump_insns (blocks, const0_rtx,
3949 EQ, NULL_RTX, mode, 1, loop_end_label);
3951 emit_jump (loop_start_label);
3952 emit_label (loop_end_label);
3954 emit_insn (gen_movmem_short (dst, src,
3955 convert_to_mode (Pmode, count, 1)));
3956 emit_label (end_label);
3960 /* Emit code to set LEN bytes at DST to VAL.
3961 Make use of clrmem if VAL is zero. */
3964 s390_expand_setmem (rtx dst, rtx len, rtx val)
3966 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
3969 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
3971 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
3973 if (val == const0_rtx && INTVAL (len) <= 256)
3974 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
3977 /* Initialize memory by storing the first byte. */
3978 emit_move_insn (adjust_address (dst, QImode, 0), val);
3980 if (INTVAL (len) > 1)
3982 /* Initiate 1 byte overlap move.
3983 The first byte of DST is propagated through DSTP1.
3984 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3985 DST is set to size 1 so the rest of the memory location
3986 does not count as source operand. */
3987 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
3988 set_mem_size (dst, const1_rtx);
3990 emit_insn (gen_movmem_short (dstp1, dst,
3991 GEN_INT (INTVAL (len) - 2)));
3996 else if (TARGET_MVCLE)
3998 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
3999 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4004 rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
4005 rtx loop_start_label = gen_label_rtx ();
4006 rtx loop_end_label = gen_label_rtx ();
4007 rtx end_label = gen_label_rtx ();
4008 enum machine_mode mode;
4010 mode = GET_MODE (len);
4011 if (mode == VOIDmode)
4014 dst_addr = gen_reg_rtx (Pmode);
4015 src_addr = gen_reg_rtx (Pmode);
4016 count = gen_reg_rtx (mode);
4017 blocks = gen_reg_rtx (mode);
4019 convert_move (count, len, 1);
4020 emit_cmp_and_jump_insns (count, const0_rtx,
4021 EQ, NULL_RTX, mode, 1, end_label);
4023 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4024 dst = change_address (dst, VOIDmode, dst_addr);
4026 if (val == const0_rtx)
4027 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4031 dstp1 = adjust_address (dst, VOIDmode, 1);
4032 set_mem_size (dst, const1_rtx);
4034 /* Initialize memory by storing the first byte. */
4035 emit_move_insn (adjust_address (dst, QImode, 0), val);
4037 /* If count is 1 we are done. */
4038 emit_cmp_and_jump_insns (count, const1_rtx,
4039 EQ, NULL_RTX, mode, 1, end_label);
4041 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4045 emit_move_insn (count, temp);
4047 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4050 emit_move_insn (blocks, temp);
4052 emit_cmp_and_jump_insns (blocks, const0_rtx,
4053 EQ, NULL_RTX, mode, 1, loop_end_label);
4055 emit_label (loop_start_label);
4057 if (val == const0_rtx)
4058 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4060 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4061 s390_load_address (dst_addr,
4062 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4064 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4067 emit_move_insn (blocks, temp);
4069 emit_cmp_and_jump_insns (blocks, const0_rtx,
4070 EQ, NULL_RTX, mode, 1, loop_end_label);
4072 emit_jump (loop_start_label);
4073 emit_label (loop_end_label);
4075 if (val == const0_rtx)
4076 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4078 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4079 emit_label (end_label);
4083 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4084 and return the result in TARGET. */
4087 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4089 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4092 /* As the result of CMPINT is inverted compared to what we need,
4093 we have to swap the operands. */
4094 tmp = op0; op0 = op1; op1 = tmp;
4096 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4098 if (INTVAL (len) > 0)
4100 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4101 emit_insn (gen_cmpint (target, ccreg));
4104 emit_move_insn (target, const0_rtx);
4106 else if (TARGET_MVCLE)
4108 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4109 emit_insn (gen_cmpint (target, ccreg));
4113 rtx addr0, addr1, count, blocks, temp;
4114 rtx loop_start_label = gen_label_rtx ();
4115 rtx loop_end_label = gen_label_rtx ();
4116 rtx end_label = gen_label_rtx ();
4117 enum machine_mode mode;
4119 mode = GET_MODE (len);
4120 if (mode == VOIDmode)
4123 addr0 = gen_reg_rtx (Pmode);
4124 addr1 = gen_reg_rtx (Pmode);
4125 count = gen_reg_rtx (mode);
4126 blocks = gen_reg_rtx (mode);
4128 convert_move (count, len, 1);
4129 emit_cmp_and_jump_insns (count, const0_rtx,
4130 EQ, NULL_RTX, mode, 1, end_label);
4132 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4133 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4134 op0 = change_address (op0, VOIDmode, addr0);
4135 op1 = change_address (op1, VOIDmode, addr1);
4137 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4140 emit_move_insn (count, temp);
4142 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4145 emit_move_insn (blocks, temp);
4147 emit_cmp_and_jump_insns (blocks, const0_rtx,
4148 EQ, NULL_RTX, mode, 1, loop_end_label);
4150 emit_label (loop_start_label);
4152 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4153 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4154 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4155 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4156 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4157 emit_jump_insn (temp);
4159 s390_load_address (addr0,
4160 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4161 s390_load_address (addr1,
4162 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4164 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4167 emit_move_insn (blocks, temp);
4169 emit_cmp_and_jump_insns (blocks, const0_rtx,
4170 EQ, NULL_RTX, mode, 1, loop_end_label);
4172 emit_jump (loop_start_label);
4173 emit_label (loop_end_label);
4175 emit_insn (gen_cmpmem_short (op0, op1,
4176 convert_to_mode (Pmode, count, 1)));
4177 emit_label (end_label);
4179 emit_insn (gen_cmpint (target, ccreg));
4184 /* Expand conditional increment or decrement using alc/slb instructions.
4185 Should generate code setting DST to either SRC or SRC + INCREMENT,
4186 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4187 Returns true if successful, false otherwise.
4189 That makes it possible to implement some if-constructs without jumps e.g.:
4190 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4191 unsigned int a, b, c;
4192 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4193 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4194 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4195 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4197 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4198 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4199 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4200 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4201 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4204 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4205 rtx dst, rtx src, rtx increment)
4207 enum machine_mode cmp_mode;
4208 enum machine_mode cc_mode;
4214 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4215 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4217 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4218 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4223 /* Try ADD LOGICAL WITH CARRY. */
4224 if (increment == const1_rtx)
4226 /* Determine CC mode to use. */
4227 if (cmp_code == EQ || cmp_code == NE)
4229 if (cmp_op1 != const0_rtx)
4231 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4232 NULL_RTX, 0, OPTAB_WIDEN);
4233 cmp_op1 = const0_rtx;
4236 cmp_code = cmp_code == EQ ? LEU : GTU;
4239 if (cmp_code == LTU || cmp_code == LEU)
4244 cmp_code = swap_condition (cmp_code);
4261 /* Emit comparison instruction pattern. */
4262 if (!register_operand (cmp_op0, cmp_mode))
4263 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4265 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4266 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4267 /* We use insn_invalid_p here to add clobbers if required. */
4268 ret = insn_invalid_p (emit_insn (insn));
4271 /* Emit ALC instruction pattern. */
4272 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4273 gen_rtx_REG (cc_mode, CC_REGNUM),
4276 if (src != const0_rtx)
4278 if (!register_operand (src, GET_MODE (dst)))
4279 src = force_reg (GET_MODE (dst), src);
4281 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4282 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4285 p = rtvec_alloc (2);
4287 gen_rtx_SET (VOIDmode, dst, op_res);
4289 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4290 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4295 /* Try SUBTRACT LOGICAL WITH BORROW. */
4296 if (increment == constm1_rtx)
4298 /* Determine CC mode to use. */
4299 if (cmp_code == EQ || cmp_code == NE)
4301 if (cmp_op1 != const0_rtx)
4303 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4304 NULL_RTX, 0, OPTAB_WIDEN);
4305 cmp_op1 = const0_rtx;
4308 cmp_code = cmp_code == EQ ? LEU : GTU;
4311 if (cmp_code == GTU || cmp_code == GEU)
4316 cmp_code = swap_condition (cmp_code);
4333 /* Emit comparison instruction pattern. */
4334 if (!register_operand (cmp_op0, cmp_mode))
4335 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4337 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4338 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4339 /* We use insn_invalid_p here to add clobbers if required. */
4340 ret = insn_invalid_p (emit_insn (insn));
4343 /* Emit SLB instruction pattern. */
4344 if (!register_operand (src, GET_MODE (dst)))
4345 src = force_reg (GET_MODE (dst), src);
4347 op_res = gen_rtx_MINUS (GET_MODE (dst),
4348 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4349 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4350 gen_rtx_REG (cc_mode, CC_REGNUM),
4352 p = rtvec_alloc (2);
4354 gen_rtx_SET (VOIDmode, dst, op_res);
4356 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4357 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4365 /* Expand code for the insv template. Return true if successful. */
4368 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4370 int bitsize = INTVAL (op1);
4371 int bitpos = INTVAL (op2);
4373 /* On z10 we can use the risbg instruction to implement insv. */
4375 && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode)
4376 || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode)))
4381 op = gen_rtx_SET (GET_MODE(src),
4382 gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2),
4384 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4385 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4390 /* We need byte alignment. */
4391 if (bitsize % BITS_PER_UNIT)
4395 && memory_operand (dest, VOIDmode)
4396 && (register_operand (src, word_mode)
4397 || const_int_operand (src, VOIDmode)))
4399 /* Emit standard pattern if possible. */
4400 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
4401 if (GET_MODE_BITSIZE (mode) == bitsize)
4402 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
4404 /* (set (ze (mem)) (const_int)). */
4405 else if (const_int_operand (src, VOIDmode))
4407 int size = bitsize / BITS_PER_UNIT;
4408 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
4409 GET_MODE_SIZE (word_mode) - size);
4411 dest = adjust_address (dest, BLKmode, 0);
4412 set_mem_size (dest, GEN_INT (size));
4413 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4416 /* (set (ze (mem)) (reg)). */
4417 else if (register_operand (src, word_mode))
4419 if (bitsize <= GET_MODE_BITSIZE (SImode))
4420 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4424 /* Emit st,stcmh sequence. */
4425 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4426 int size = stcmh_width / BITS_PER_UNIT;
4428 emit_move_insn (adjust_address (dest, SImode, size),
4429 gen_lowpart (SImode, src));
4430 set_mem_size (dest, GEN_INT (size));
4431 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4432 (stcmh_width), const0_rtx),
4433 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4434 (GET_MODE_BITSIZE (SImode))));
4443 /* (set (ze (reg)) (const_int)). */
4445 && register_operand (dest, word_mode)
4446 && (bitpos % 16) == 0
4447 && (bitsize % 16) == 0
4448 && const_int_operand (src, VOIDmode))
4450 HOST_WIDE_INT val = INTVAL (src);
4451 int regpos = bitpos + bitsize;
4453 while (regpos > bitpos)
4455 enum machine_mode putmode;
4458 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4463 putsize = GET_MODE_BITSIZE (putmode);
4465 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4468 gen_int_mode (val, putmode));
4471 gcc_assert (regpos == bitpos);
4478 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4479 register that holds VAL of mode MODE shifted by COUNT bits. */
4482 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4484 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4485 NULL_RTX, 1, OPTAB_DIRECT);
4486 return expand_simple_binop (SImode, ASHIFT, val, count,
4487 NULL_RTX, 1, OPTAB_DIRECT);
4490 /* Structure to hold the initial parameters for a compare_and_swap operation
4491 in HImode and QImode. */
4493 struct alignment_context
4495 rtx memsi; /* SI aligned memory location. */
4496 rtx shift; /* Bit offset with regard to lsb. */
4497 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4498 rtx modemaski; /* ~modemask */
4499 bool aligned; /* True if memory is aligned, false else. */
4502 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4503 structure AC for transparent simplifying, if the memory alignment is known
4504 to be at least 32bit. MEM is the memory location for the actual operation
4505 and MODE its mode. */
4508 init_alignment_context (struct alignment_context *ac, rtx mem,
4509 enum machine_mode mode)
4511 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4512 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4515 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4518 /* Alignment is unknown. */
4519 rtx byteoffset, addr, align;
4521 /* Force the address into a register. */
4522 addr = force_reg (Pmode, XEXP (mem, 0));
4524 /* Align it to SImode. */
4525 align = expand_simple_binop (Pmode, AND, addr,
4526 GEN_INT (-GET_MODE_SIZE (SImode)),
4527 NULL_RTX, 1, OPTAB_DIRECT);
4529 ac->memsi = gen_rtx_MEM (SImode, align);
4530 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4531 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4532 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4534 /* Calculate shiftcount. */
4535 byteoffset = expand_simple_binop (Pmode, AND, addr,
4536 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4537 NULL_RTX, 1, OPTAB_DIRECT);
4538 /* As we already have some offset, evaluate the remaining distance. */
4539 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4540 NULL_RTX, 1, OPTAB_DIRECT);
4543 /* Shift is the byte count, but we need the bitcount. */
4544 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4545 NULL_RTX, 1, OPTAB_DIRECT);
4546 /* Calculate masks. */
4547 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4548 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4549 NULL_RTX, 1, OPTAB_DIRECT);
4550 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4553 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4554 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4555 to set if CMP == MEM.
4556 CMP is never in memory for compare_and_swap_cc because
4557 expand_bool_compare_and_swap puts it into a register for later compare. */
4560 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx)
4562 struct alignment_context ac;
4563 rtx cmpv, newv, val, resv, cc;
4564 rtx res = gen_reg_rtx (SImode);
4565 rtx csloop = gen_label_rtx ();
4566 rtx csend = gen_label_rtx ();
4568 gcc_assert (register_operand (target, VOIDmode));
4569 gcc_assert (MEM_P (mem));
4571 init_alignment_context (&ac, mem, mode);
4573 /* Shift the values to the correct bit positions. */
4574 if (!(ac.aligned && MEM_P (cmp)))
4575 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4576 if (!(ac.aligned && MEM_P (new_rtx)))
4577 new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift);
4579 /* Load full word. Subsequent loads are performed by CS. */
4580 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4581 NULL_RTX, 1, OPTAB_DIRECT);
4583 /* Start CS loop. */
4584 emit_label (csloop);
4585 /* val = "<mem>00..0<mem>"
4586 * cmp = "00..0<cmp>00..0"
4587 * new = "00..0<new>00..0"
4590 /* Patch cmp and new with val at correct position. */
4591 if (ac.aligned && MEM_P (cmp))
4593 cmpv = force_reg (SImode, val);
4594 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4597 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4598 NULL_RTX, 1, OPTAB_DIRECT));
4599 if (ac.aligned && MEM_P (new_rtx))
4601 newv = force_reg (SImode, val);
4602 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new_rtx);
4605 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val,
4606 NULL_RTX, 1, OPTAB_DIRECT));
4608 /* Jump to end if we're done (likely?). */
4609 s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi,
4612 /* Check for changes outside mode. */
4613 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4614 NULL_RTX, 1, OPTAB_DIRECT);
4615 cc = s390_emit_compare (NE, resv, val);
4616 emit_move_insn (val, resv);
4617 /* Loop internal if so. */
4618 s390_emit_jump (csloop, cc);
4622 /* Return the correct part of the bitfield. */
4623 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4624 NULL_RTX, 1, OPTAB_DIRECT), 1);
4627 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4628 and VAL the value to play with. If AFTER is true then store the value
4629 MEM holds after the operation, if AFTER is false then store the value MEM
4630 holds before the operation. If TARGET is zero then discard that value, else
4631 store it to TARGET. */
4634 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4635 rtx target, rtx mem, rtx val, bool after)
4637 struct alignment_context ac;
4639 rtx new_rtx = gen_reg_rtx (SImode);
4640 rtx orig = gen_reg_rtx (SImode);
4641 rtx csloop = gen_label_rtx ();
4643 gcc_assert (!target || register_operand (target, VOIDmode));
4644 gcc_assert (MEM_P (mem));
4646 init_alignment_context (&ac, mem, mode);
4648 /* Shift val to the correct bit positions.
4649 Preserve "icm", but prevent "ex icm". */
4650 if (!(ac.aligned && code == SET && MEM_P (val)))
4651 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4653 /* Further preparation insns. */
4654 if (code == PLUS || code == MINUS)
4655 emit_move_insn (orig, val);
4656 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4657 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4658 NULL_RTX, 1, OPTAB_DIRECT);
4660 /* Load full word. Subsequent loads are performed by CS. */
4661 cmp = force_reg (SImode, ac.memsi);
4663 /* Start CS loop. */
4664 emit_label (csloop);
4665 emit_move_insn (new_rtx, cmp);
4667 /* Patch new with val at correct position. */
4672 val = expand_simple_binop (SImode, code, new_rtx, orig,
4673 NULL_RTX, 1, OPTAB_DIRECT);
4674 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4675 NULL_RTX, 1, OPTAB_DIRECT);
4678 if (ac.aligned && MEM_P (val))
4679 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0, SImode, val);
4682 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
4683 NULL_RTX, 1, OPTAB_DIRECT);
4684 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
4685 NULL_RTX, 1, OPTAB_DIRECT);
4691 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
4692 NULL_RTX, 1, OPTAB_DIRECT);
4694 case MULT: /* NAND */
4695 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
4696 NULL_RTX, 1, OPTAB_DIRECT);
4697 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
4698 NULL_RTX, 1, OPTAB_DIRECT);
4704 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
4705 ac.memsi, cmp, new_rtx));
4707 /* Return the correct part of the bitfield. */
4709 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4710 after ? new_rtx : cmp, ac.shift,
4711 NULL_RTX, 1, OPTAB_DIRECT), 1);
4714 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4715 We need to emit DTP-relative relocations. */
4717 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4720 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4725 fputs ("\t.long\t", file);
4728 fputs ("\t.quad\t", file);
4733 output_addr_const (file, x);
4734 fputs ("@DTPOFF", file);
4737 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4738 /* Implement TARGET_MANGLE_TYPE. */
4741 s390_mangle_type (const_tree type)
4743 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4744 && TARGET_LONG_DOUBLE_128)
4747 /* For all other types, use normal C++ mangling. */
4752 /* In the name of slightly smaller debug output, and to cater to
4753 general assembler lossage, recognize various UNSPEC sequences
4754 and turn them back into a direct symbol reference. */
4757 s390_delegitimize_address (rtx orig_x)
4761 if (GET_CODE (x) != MEM)
4765 if (GET_CODE (x) == PLUS
4766 && GET_CODE (XEXP (x, 1)) == CONST
4767 && GET_CODE (XEXP (x, 0)) == REG
4768 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4770 y = XEXP (XEXP (x, 1), 0);
4771 if (GET_CODE (y) == UNSPEC
4772 && XINT (y, 1) == UNSPEC_GOT)
4773 return XVECEXP (y, 0, 0);
4777 if (GET_CODE (x) == CONST)
4780 if (GET_CODE (y) == UNSPEC
4781 && XINT (y, 1) == UNSPEC_GOTENT)
4782 return XVECEXP (y, 0, 0);
4789 /* Output operand OP to stdio stream FILE.
4790 OP is an address (register + offset) which is not used to address data;
4791 instead the rightmost bits are interpreted as the value. */
4794 print_shift_count_operand (FILE *file, rtx op)
4796 HOST_WIDE_INT offset;
4799 /* Extract base register and offset. */
4800 if (!s390_decompose_shift_count (op, &base, &offset))
4806 gcc_assert (GET_CODE (base) == REG);
4807 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4808 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4811 /* Offsets are constricted to twelve bits. */
4812 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4814 fprintf (file, "(%s)", reg_names[REGNO (base)]);
4817 /* See 'get_some_local_dynamic_name'. */
4820 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4824 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4826 x = get_pool_constant (x);
4827 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4830 if (GET_CODE (x) == SYMBOL_REF
4831 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4833 cfun->machine->some_ld_name = XSTR (x, 0);
4840 /* Locate some local-dynamic symbol still in use by this function
4841 so that we can print its name in local-dynamic base patterns. */
4844 get_some_local_dynamic_name (void)
4848 if (cfun->machine->some_ld_name)
4849 return cfun->machine->some_ld_name;
4851 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4853 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4854 return cfun->machine->some_ld_name;
4859 /* Output machine-dependent UNSPECs occurring in address constant X
4860 in assembler syntax to stdio stream FILE. Returns true if the
4861 constant X could be recognized, false otherwise. */
4864 s390_output_addr_const_extra (FILE *file, rtx x)
4866 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4867 switch (XINT (x, 1))
4870 output_addr_const (file, XVECEXP (x, 0, 0));
4871 fprintf (file, "@GOTENT");
4874 output_addr_const (file, XVECEXP (x, 0, 0));
4875 fprintf (file, "@GOT");
4878 output_addr_const (file, XVECEXP (x, 0, 0));
4879 fprintf (file, "@GOTOFF");
4882 output_addr_const (file, XVECEXP (x, 0, 0));
4883 fprintf (file, "@PLT");
4886 output_addr_const (file, XVECEXP (x, 0, 0));
4887 fprintf (file, "@PLTOFF");
4890 output_addr_const (file, XVECEXP (x, 0, 0));
4891 fprintf (file, "@TLSGD");
4894 assemble_name (file, get_some_local_dynamic_name ());
4895 fprintf (file, "@TLSLDM");
4898 output_addr_const (file, XVECEXP (x, 0, 0));
4899 fprintf (file, "@DTPOFF");
4902 output_addr_const (file, XVECEXP (x, 0, 0));
4903 fprintf (file, "@NTPOFF");
4905 case UNSPEC_GOTNTPOFF:
4906 output_addr_const (file, XVECEXP (x, 0, 0));
4907 fprintf (file, "@GOTNTPOFF");
4909 case UNSPEC_INDNTPOFF:
4910 output_addr_const (file, XVECEXP (x, 0, 0));
4911 fprintf (file, "@INDNTPOFF");
4915 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
4916 switch (XINT (x, 1))
4918 case UNSPEC_POOL_OFFSET:
4919 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
4920 output_addr_const (file, x);
4926 /* Output address operand ADDR in assembler syntax to
4927 stdio stream FILE. */
4930 print_operand_address (FILE *file, rtx addr)
4932 struct s390_address ad;
4934 if (s390_symref_operand_p (addr, NULL, NULL))
4936 gcc_assert (TARGET_Z10);
4937 output_addr_const (file, addr);
4941 if (!s390_decompose_address (addr, &ad)
4942 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
4943 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
4944 output_operand_lossage ("cannot decompose address");
4947 output_addr_const (file, ad.disp);
4949 fprintf (file, "0");
4951 if (ad.base && ad.indx)
4952 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
4953 reg_names[REGNO (ad.base)]);
4955 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4958 /* Output operand X in assembler syntax to stdio stream FILE.
4959 CODE specified the format flag. The following format flags
4962 'C': print opcode suffix for branch condition.
4963 'D': print opcode suffix for inverse branch condition.
4964 'E': print opcode suffix for branch on index instruction.
4965 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4966 'G': print the size of the operand in bytes.
4967 'O': print only the displacement of a memory reference.
4968 'R': print only the base register of a memory reference.
4969 'S': print S-type memory reference (base+displacement).
4970 'N': print the second word of a DImode operand.
4971 'M': print the second word of a TImode operand.
4972 'Y': print shift count operand.
4974 'b': print integer X as if it's an unsigned byte.
4975 'c': print integer X as if it's an signed byte.
4976 'x': print integer X as if it's an unsigned halfword.
4977 'h': print integer X as if it's a signed halfword.
4978 'i': print the first nonzero HImode part of X.
4979 'j': print the first HImode part unequal to -1 of X.
4980 'k': print the first nonzero SImode part of X.
4981 'm': print the first SImode part unequal to -1 of X.
4982 'o': print integer X as if it's an unsigned 32bit word. */
4985 print_operand (FILE *file, rtx x, int code)
4990 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
4994 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
4998 if (GET_CODE (x) == LE)
4999 fprintf (file, "l");
5000 else if (GET_CODE (x) == GT)
5001 fprintf (file, "h");
5007 if (GET_CODE (x) == SYMBOL_REF)
5009 fprintf (file, "%s", ":tls_load:");
5010 output_addr_const (file, x);
5012 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5014 fprintf (file, "%s", ":tls_gdcall:");
5015 output_addr_const (file, XVECEXP (x, 0, 0));
5017 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5019 fprintf (file, "%s", ":tls_ldcall:");
5020 assemble_name (file, get_some_local_dynamic_name ());
5027 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5032 struct s390_address ad;
5035 gcc_assert (GET_CODE (x) == MEM);
5036 ret = s390_decompose_address (XEXP (x, 0), &ad);
5038 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5039 gcc_assert (!ad.indx);
5042 output_addr_const (file, ad.disp);
5044 fprintf (file, "0");
5050 struct s390_address ad;
5053 gcc_assert (GET_CODE (x) == MEM);
5054 ret = s390_decompose_address (XEXP (x, 0), &ad);
5056 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5057 gcc_assert (!ad.indx);
5060 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5062 fprintf (file, "0");
5068 struct s390_address ad;
5071 gcc_assert (GET_CODE (x) == MEM);
5072 ret = s390_decompose_address (XEXP (x, 0), &ad);
5074 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
5075 gcc_assert (!ad.indx);
5078 output_addr_const (file, ad.disp);
5080 fprintf (file, "0");
5083 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5088 if (GET_CODE (x) == REG)
5089 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5090 else if (GET_CODE (x) == MEM)
5091 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
5097 if (GET_CODE (x) == REG)
5098 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5099 else if (GET_CODE (x) == MEM)
5100 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
5106 print_shift_count_operand (file, x);
5110 switch (GET_CODE (x))
5113 fprintf (file, "%s", reg_names[REGNO (x)]);
5117 output_address (XEXP (x, 0));
5124 output_addr_const (file, x);
5129 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
5130 else if (code == 'c')
5131 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80);
5132 else if (code == 'x')
5133 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
5134 else if (code == 'h')
5135 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
5136 else if (code == 'i')
5137 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5138 s390_extract_part (x, HImode, 0));
5139 else if (code == 'j')
5140 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5141 s390_extract_part (x, HImode, -1));
5142 else if (code == 'k')
5143 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5144 s390_extract_part (x, SImode, 0));
5145 else if (code == 'm')
5146 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5147 s390_extract_part (x, SImode, -1));
5148 else if (code == 'o')
5149 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
5151 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
5155 gcc_assert (GET_MODE (x) == VOIDmode);
5157 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5158 else if (code == 'x')
5159 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5160 else if (code == 'h')
5161 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5167 fatal_insn ("UNKNOWN in print_operand !?", x);
5172 /* Target hook for assembling integer objects. We need to define it
5173 here to work a round a bug in some versions of GAS, which couldn't
5174 handle values smaller than INT_MIN when printed in decimal. */
5177 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5179 if (size == 8 && aligned_p
5180 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5182 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5186 return default_assemble_integer (x, size, aligned_p);
5189 /* Returns true if register REGNO is used for forming
5190 a memory address in expression X. */
5193 reg_used_in_mem_p (int regno, rtx x)
5195 enum rtx_code code = GET_CODE (x);
5201 if (refers_to_regno_p (regno, regno+1,
5205 else if (code == SET
5206 && GET_CODE (SET_DEST (x)) == PC)
5208 if (refers_to_regno_p (regno, regno+1,
5213 fmt = GET_RTX_FORMAT (code);
5214 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5217 && reg_used_in_mem_p (regno, XEXP (x, i)))
5220 else if (fmt[i] == 'E')
5221 for (j = 0; j < XVECLEN (x, i); j++)
5222 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5228 /* Returns true if expression DEP_RTX sets an address register
5229 used by instruction INSN to address memory. */
5232 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
5236 if (GET_CODE (dep_rtx) == INSN)
5237 dep_rtx = PATTERN (dep_rtx);
5239 if (GET_CODE (dep_rtx) == SET)
5241 target = SET_DEST (dep_rtx);
5242 if (GET_CODE (target) == STRICT_LOW_PART)
5243 target = XEXP (target, 0);
5244 while (GET_CODE (target) == SUBREG)
5245 target = SUBREG_REG (target);
5247 if (GET_CODE (target) == REG)
5249 int regno = REGNO (target);
5251 if (s390_safe_attr_type (insn) == TYPE_LA)
5253 pat = PATTERN (insn);
5254 if (GET_CODE (pat) == PARALLEL)
5256 gcc_assert (XVECLEN (pat, 0) == 2);
5257 pat = XVECEXP (pat, 0, 0);
5259 gcc_assert (GET_CODE (pat) == SET);
5260 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5262 else if (get_attr_atype (insn) == ATYPE_AGEN)
5263 return reg_used_in_mem_p (regno, PATTERN (insn));
5269 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5272 s390_agen_dep_p (rtx dep_insn, rtx insn)
5274 rtx dep_rtx = PATTERN (dep_insn);
5277 if (GET_CODE (dep_rtx) == SET
5278 && addr_generation_dependency_p (dep_rtx, insn))
5280 else if (GET_CODE (dep_rtx) == PARALLEL)
5282 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5284 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5292 /* A C statement (sans semicolon) to update the integer scheduling priority
5293 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5294 reduce the priority to execute INSN later. Do not define this macro if
5295 you do not need to adjust the scheduling priorities of insns.
5297 A STD instruction should be scheduled earlier,
5298 in order to use the bypass. */
5302 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
5304 if (! INSN_P (insn))
5307 if (s390_tune != PROCESSOR_2084_Z990
5308 && s390_tune != PROCESSOR_2094_Z9_109
5309 && s390_tune != PROCESSOR_2097_Z10)
5312 switch (s390_safe_attr_type (insn))
5316 priority = priority << 3;
5320 priority = priority << 1;
5329 /* The number of instructions that can be issued per cycle. */
5332 s390_issue_rate (void)
5336 case PROCESSOR_2084_Z990:
5337 case PROCESSOR_2094_Z9_109:
5339 case PROCESSOR_2097_Z10:
5347 s390_first_cycle_multipass_dfa_lookahead (void)
5353 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5354 Fix up MEMs as required. */
5357 annotate_constant_pool_refs (rtx *x)
5362 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5363 || !CONSTANT_POOL_ADDRESS_P (*x));
5365 /* Literal pool references can only occur inside a MEM ... */
5366 if (GET_CODE (*x) == MEM)
5368 rtx memref = XEXP (*x, 0);
5370 if (GET_CODE (memref) == SYMBOL_REF
5371 && CONSTANT_POOL_ADDRESS_P (memref))
5373 rtx base = cfun->machine->base_reg;
5374 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5377 *x = replace_equiv_address (*x, addr);
5381 if (GET_CODE (memref) == CONST
5382 && GET_CODE (XEXP (memref, 0)) == PLUS
5383 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5384 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5385 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5387 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5388 rtx sym = XEXP (XEXP (memref, 0), 0);
5389 rtx base = cfun->machine->base_reg;
5390 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5393 *x = replace_equiv_address (*x, plus_constant (addr, off));
5398 /* ... or a load-address type pattern. */
5399 if (GET_CODE (*x) == SET)
5401 rtx addrref = SET_SRC (*x);
5403 if (GET_CODE (addrref) == SYMBOL_REF
5404 && CONSTANT_POOL_ADDRESS_P (addrref))
5406 rtx base = cfun->machine->base_reg;
5407 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5410 SET_SRC (*x) = addr;
5414 if (GET_CODE (addrref) == CONST
5415 && GET_CODE (XEXP (addrref, 0)) == PLUS
5416 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5417 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5418 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5420 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5421 rtx sym = XEXP (XEXP (addrref, 0), 0);
5422 rtx base = cfun->machine->base_reg;
5423 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5426 SET_SRC (*x) = plus_constant (addr, off);
5431 /* Annotate LTREL_BASE as well. */
5432 if (GET_CODE (*x) == UNSPEC
5433 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5435 rtx base = cfun->machine->base_reg;
5436 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5441 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5442 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5446 annotate_constant_pool_refs (&XEXP (*x, i));
5448 else if (fmt[i] == 'E')
5450 for (j = 0; j < XVECLEN (*x, i); j++)
5451 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5456 /* Split all branches that exceed the maximum distance.
5457 Returns true if this created a new literal pool entry. */
5460 s390_split_branches (void)
5462 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5463 int new_literal = 0, ret;
5464 rtx insn, pat, tmp, target;
5467 /* We need correct insn addresses. */
5469 shorten_branches (get_insns ());
5471 /* Find all branches that exceed 64KB, and split them. */
5473 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5475 if (GET_CODE (insn) != JUMP_INSN)
5478 pat = PATTERN (insn);
5479 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5480 pat = XVECEXP (pat, 0, 0);
5481 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5484 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5486 label = &SET_SRC (pat);
5488 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5490 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5491 label = &XEXP (SET_SRC (pat), 1);
5492 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5493 label = &XEXP (SET_SRC (pat), 2);
5500 if (get_attr_length (insn) <= 4)
5503 /* We are going to use the return register as scratch register,
5504 make sure it will be saved/restored by the prologue/epilogue. */
5505 cfun_frame_layout.save_return_addr_p = 1;
5510 tmp = force_const_mem (Pmode, *label);
5511 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5512 INSN_ADDRESSES_NEW (tmp, -1);
5513 annotate_constant_pool_refs (&PATTERN (tmp));
5520 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5521 UNSPEC_LTREL_OFFSET);
5522 target = gen_rtx_CONST (Pmode, target);
5523 target = force_const_mem (Pmode, target);
5524 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5525 INSN_ADDRESSES_NEW (tmp, -1);
5526 annotate_constant_pool_refs (&PATTERN (tmp));
5528 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5529 cfun->machine->base_reg),
5531 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5534 ret = validate_change (insn, label, target, 0);
5542 /* Find an annotated literal pool symbol referenced in RTX X,
5543 and store it at REF. Will abort if X contains references to
5544 more than one such pool symbol; multiple references to the same
5545 symbol are allowed, however.
5547 The rtx pointed to by REF must be initialized to NULL_RTX
5548 by the caller before calling this routine. */
5551 find_constant_pool_ref (rtx x, rtx *ref)
5556 /* Ignore LTREL_BASE references. */
5557 if (GET_CODE (x) == UNSPEC
5558 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5560 /* Likewise POOL_ENTRY insns. */
5561 if (GET_CODE (x) == UNSPEC_VOLATILE
5562 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5565 gcc_assert (GET_CODE (x) != SYMBOL_REF
5566 || !CONSTANT_POOL_ADDRESS_P (x));
5568 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5570 rtx sym = XVECEXP (x, 0, 0);
5571 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5572 && CONSTANT_POOL_ADDRESS_P (sym));
5574 if (*ref == NULL_RTX)
5577 gcc_assert (*ref == sym);
5582 fmt = GET_RTX_FORMAT (GET_CODE (x));
5583 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5587 find_constant_pool_ref (XEXP (x, i), ref);
5589 else if (fmt[i] == 'E')
5591 for (j = 0; j < XVECLEN (x, i); j++)
5592 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5597 /* Replace every reference to the annotated literal pool
5598 symbol REF in X by its base plus OFFSET. */
5601 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5606 gcc_assert (*x != ref);
5608 if (GET_CODE (*x) == UNSPEC
5609 && XINT (*x, 1) == UNSPEC_LTREF
5610 && XVECEXP (*x, 0, 0) == ref)
5612 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5616 if (GET_CODE (*x) == PLUS
5617 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5618 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5619 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5620 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5622 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5623 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5627 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5628 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5632 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5634 else if (fmt[i] == 'E')
5636 for (j = 0; j < XVECLEN (*x, i); j++)
5637 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5642 /* Check whether X contains an UNSPEC_LTREL_BASE.
5643 Return its constant pool symbol if found, NULL_RTX otherwise. */
5646 find_ltrel_base (rtx x)
5651 if (GET_CODE (x) == UNSPEC
5652 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5653 return XVECEXP (x, 0, 0);
5655 fmt = GET_RTX_FORMAT (GET_CODE (x));
5656 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5660 rtx fnd = find_ltrel_base (XEXP (x, i));
5664 else if (fmt[i] == 'E')
5666 for (j = 0; j < XVECLEN (x, i); j++)
5668 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5678 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5681 replace_ltrel_base (rtx *x)
5686 if (GET_CODE (*x) == UNSPEC
5687 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5689 *x = XVECEXP (*x, 0, 1);
5693 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5694 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5698 replace_ltrel_base (&XEXP (*x, i));
5700 else if (fmt[i] == 'E')
5702 for (j = 0; j < XVECLEN (*x, i); j++)
5703 replace_ltrel_base (&XVECEXP (*x, i, j));
5709 /* We keep a list of constants which we have to add to internal
5710 constant tables in the middle of large functions. */
5712 #define NR_C_MODES 11
5713 enum machine_mode constant_modes[NR_C_MODES] =
5715 TFmode, TImode, TDmode,
5716 DFmode, DImode, DDmode,
5717 SFmode, SImode, SDmode,
5724 struct constant *next;
5729 struct constant_pool
5731 struct constant_pool *next;
5735 rtx emit_pool_after;
5737 struct constant *constants[NR_C_MODES];
5738 struct constant *execute;
5743 /* Allocate new constant_pool structure. */
5745 static struct constant_pool *
5746 s390_alloc_pool (void)
5748 struct constant_pool *pool;
5751 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5753 for (i = 0; i < NR_C_MODES; i++)
5754 pool->constants[i] = NULL;
5756 pool->execute = NULL;
5757 pool->label = gen_label_rtx ();
5758 pool->first_insn = NULL_RTX;
5759 pool->pool_insn = NULL_RTX;
5760 pool->insns = BITMAP_ALLOC (NULL);
5762 pool->emit_pool_after = NULL_RTX;
5767 /* Create new constant pool covering instructions starting at INSN
5768 and chain it to the end of POOL_LIST. */
5770 static struct constant_pool *
5771 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5773 struct constant_pool *pool, **prev;
5775 pool = s390_alloc_pool ();
5776 pool->first_insn = insn;
5778 for (prev = pool_list; *prev; prev = &(*prev)->next)
5785 /* End range of instructions covered by POOL at INSN and emit
5786 placeholder insn representing the pool. */
5789 s390_end_pool (struct constant_pool *pool, rtx insn)
5791 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5794 insn = get_last_insn ();
5796 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5797 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5800 /* Add INSN to the list of insns covered by POOL. */
5803 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5805 bitmap_set_bit (pool->insns, INSN_UID (insn));
5808 /* Return pool out of POOL_LIST that covers INSN. */
5810 static struct constant_pool *
5811 s390_find_pool (struct constant_pool *pool_list, rtx insn)
5813 struct constant_pool *pool;
5815 for (pool = pool_list; pool; pool = pool->next)
5816 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5822 /* Add constant VAL of mode MODE to the constant pool POOL. */
5825 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5830 for (i = 0; i < NR_C_MODES; i++)
5831 if (constant_modes[i] == mode)
5833 gcc_assert (i != NR_C_MODES);
5835 for (c = pool->constants[i]; c != NULL; c = c->next)
5836 if (rtx_equal_p (val, c->value))
5841 c = (struct constant *) xmalloc (sizeof *c);
5843 c->label = gen_label_rtx ();
5844 c->next = pool->constants[i];
5845 pool->constants[i] = c;
5846 pool->size += GET_MODE_SIZE (mode);
5850 /* Return an rtx that represents the offset of X from the start of
5854 s390_pool_offset (struct constant_pool *pool, rtx x)
5858 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
5859 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
5860 UNSPEC_POOL_OFFSET);
5861 return gen_rtx_CONST (GET_MODE (x), x);
5864 /* Find constant VAL of mode MODE in the constant pool POOL.
5865 Return an RTX describing the distance from the start of
5866 the pool to the location of the new constant. */
5869 s390_find_constant (struct constant_pool *pool, rtx val,
5870 enum machine_mode mode)
5875 for (i = 0; i < NR_C_MODES; i++)
5876 if (constant_modes[i] == mode)
5878 gcc_assert (i != NR_C_MODES);
5880 for (c = pool->constants[i]; c != NULL; c = c->next)
5881 if (rtx_equal_p (val, c->value))
5886 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
5889 /* Check whether INSN is an execute. Return the label_ref to its
5890 execute target template if so, NULL_RTX otherwise. */
5893 s390_execute_label (rtx insn)
5895 if (GET_CODE (insn) == INSN
5896 && GET_CODE (PATTERN (insn)) == PARALLEL
5897 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5898 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5899 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5904 /* Add execute target for INSN to the constant pool POOL. */
5907 s390_add_execute (struct constant_pool *pool, rtx insn)
5911 for (c = pool->execute; c != NULL; c = c->next)
5912 if (INSN_UID (insn) == INSN_UID (c->value))
5917 c = (struct constant *) xmalloc (sizeof *c);
5919 c->label = gen_label_rtx ();
5920 c->next = pool->execute;
5926 /* Find execute target for INSN in the constant pool POOL.
5927 Return an RTX describing the distance from the start of
5928 the pool to the location of the execute target. */
5931 s390_find_execute (struct constant_pool *pool, rtx insn)
5935 for (c = pool->execute; c != NULL; c = c->next)
5936 if (INSN_UID (insn) == INSN_UID (c->value))
5941 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
5944 /* For an execute INSN, extract the execute target template. */
5947 s390_execute_target (rtx insn)
5949 rtx pattern = PATTERN (insn);
5950 gcc_assert (s390_execute_label (insn));
5952 if (XVECLEN (pattern, 0) == 2)
5954 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
5958 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
5961 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
5962 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
5964 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
5970 /* Indicate that INSN cannot be duplicated. This is the case for
5971 execute insns that carry a unique label. */
5974 s390_cannot_copy_insn_p (rtx insn)
5976 rtx label = s390_execute_label (insn);
5977 return label && label != const0_rtx;
5980 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5981 do not emit the pool base label. */
5984 s390_dump_pool (struct constant_pool *pool, bool remote_label)
5987 rtx insn = pool->pool_insn;
5990 /* Switch to rodata section. */
5991 if (TARGET_CPU_ZARCH)
5993 insn = emit_insn_after (gen_pool_section_start (), insn);
5994 INSN_ADDRESSES_NEW (insn, -1);
5997 /* Ensure minimum pool alignment. */
5998 if (TARGET_CPU_ZARCH)
5999 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6001 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6002 INSN_ADDRESSES_NEW (insn, -1);
6004 /* Emit pool base label. */
6007 insn = emit_label_after (pool->label, insn);
6008 INSN_ADDRESSES_NEW (insn, -1);
6011 /* Dump constants in descending alignment requirement order,
6012 ensuring proper alignment for every constant. */
6013 for (i = 0; i < NR_C_MODES; i++)
6014 for (c = pool->constants[i]; c; c = c->next)
6016 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6017 rtx value = copy_rtx (c->value);
6018 if (GET_CODE (value) == CONST
6019 && GET_CODE (XEXP (value, 0)) == UNSPEC
6020 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6021 && XVECLEN (XEXP (value, 0), 0) == 1)
6022 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6024 insn = emit_label_after (c->label, insn);
6025 INSN_ADDRESSES_NEW (insn, -1);
6027 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6028 gen_rtvec (1, value),
6029 UNSPECV_POOL_ENTRY);
6030 insn = emit_insn_after (value, insn);
6031 INSN_ADDRESSES_NEW (insn, -1);
6034 /* Ensure minimum alignment for instructions. */
6035 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6036 INSN_ADDRESSES_NEW (insn, -1);
6038 /* Output in-pool execute template insns. */
6039 for (c = pool->execute; c; c = c->next)
6041 insn = emit_label_after (c->label, insn);
6042 INSN_ADDRESSES_NEW (insn, -1);
6044 insn = emit_insn_after (s390_execute_target (c->value), insn);
6045 INSN_ADDRESSES_NEW (insn, -1);
6048 /* Switch back to previous section. */
6049 if (TARGET_CPU_ZARCH)
6051 insn = emit_insn_after (gen_pool_section_end (), insn);
6052 INSN_ADDRESSES_NEW (insn, -1);
6055 insn = emit_barrier_after (insn);
6056 INSN_ADDRESSES_NEW (insn, -1);
6058 /* Remove placeholder insn. */
6059 remove_insn (pool->pool_insn);
6062 /* Free all memory used by POOL. */
6065 s390_free_pool (struct constant_pool *pool)
6067 struct constant *c, *next;
6070 for (i = 0; i < NR_C_MODES; i++)
6071 for (c = pool->constants[i]; c; c = next)
6077 for (c = pool->execute; c; c = next)
6083 BITMAP_FREE (pool->insns);
6088 /* Collect main literal pool. Return NULL on overflow. */
6090 static struct constant_pool *
6091 s390_mainpool_start (void)
6093 struct constant_pool *pool;
6096 pool = s390_alloc_pool ();
6098 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6100 if (GET_CODE (insn) == INSN
6101 && GET_CODE (PATTERN (insn)) == SET
6102 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6103 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6105 gcc_assert (!pool->pool_insn);
6106 pool->pool_insn = insn;
6109 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6111 s390_add_execute (pool, insn);
6113 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6115 rtx pool_ref = NULL_RTX;
6116 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6119 rtx constant = get_pool_constant (pool_ref);
6120 enum machine_mode mode = get_pool_mode (pool_ref);
6121 s390_add_constant (pool, constant, mode);
6125 /* If hot/cold partitioning is enabled we have to make sure that
6126 the literal pool is emitted in the same section where the
6127 initialization of the literal pool base pointer takes place.
6128 emit_pool_after is only used in the non-overflow case on non
6129 Z cpus where we can emit the literal pool at the end of the
6130 function body within the text section. */
6132 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6133 && !pool->emit_pool_after)
6134 pool->emit_pool_after = PREV_INSN (insn);
6137 gcc_assert (pool->pool_insn || pool->size == 0);
6139 if (pool->size >= 4096)
6141 /* We're going to chunkify the pool, so remove the main
6142 pool placeholder insn. */
6143 remove_insn (pool->pool_insn);
6145 s390_free_pool (pool);
6149 /* If the functions ends with the section where the literal pool
6150 should be emitted set the marker to its end. */
6151 if (pool && !pool->emit_pool_after)
6152 pool->emit_pool_after = get_last_insn ();
6157 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6158 Modify the current function to output the pool constants as well as
6159 the pool register setup instruction. */
6162 s390_mainpool_finish (struct constant_pool *pool)
6164 rtx base_reg = cfun->machine->base_reg;
6167 /* If the pool is empty, we're done. */
6168 if (pool->size == 0)
6170 /* We don't actually need a base register after all. */
6171 cfun->machine->base_reg = NULL_RTX;
6173 if (pool->pool_insn)
6174 remove_insn (pool->pool_insn);
6175 s390_free_pool (pool);
6179 /* We need correct insn addresses. */
6180 shorten_branches (get_insns ());
6182 /* On zSeries, we use a LARL to load the pool register. The pool is
6183 located in the .rodata section, so we emit it after the function. */
6184 if (TARGET_CPU_ZARCH)
6186 insn = gen_main_base_64 (base_reg, pool->label);
6187 insn = emit_insn_after (insn, pool->pool_insn);
6188 INSN_ADDRESSES_NEW (insn, -1);
6189 remove_insn (pool->pool_insn);
6191 insn = get_last_insn ();
6192 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6193 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6195 s390_dump_pool (pool, 0);
6198 /* On S/390, if the total size of the function's code plus literal pool
6199 does not exceed 4096 bytes, we use BASR to set up a function base
6200 pointer, and emit the literal pool at the end of the function. */
6201 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6202 + pool->size + 8 /* alignment slop */ < 4096)
6204 insn = gen_main_base_31_small (base_reg, pool->label);
6205 insn = emit_insn_after (insn, pool->pool_insn);
6206 INSN_ADDRESSES_NEW (insn, -1);
6207 remove_insn (pool->pool_insn);
6209 insn = emit_label_after (pool->label, insn);
6210 INSN_ADDRESSES_NEW (insn, -1);
6212 /* emit_pool_after will be set by s390_mainpool_start to the
6213 last insn of the section where the literal pool should be
6215 insn = pool->emit_pool_after;
6217 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6218 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6220 s390_dump_pool (pool, 1);
6223 /* Otherwise, we emit an inline literal pool and use BASR to branch
6224 over it, setting up the pool register at the same time. */
6227 rtx pool_end = gen_label_rtx ();
6229 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
6230 insn = emit_insn_after (insn, pool->pool_insn);
6231 INSN_ADDRESSES_NEW (insn, -1);
6232 remove_insn (pool->pool_insn);
6234 insn = emit_label_after (pool->label, insn);
6235 INSN_ADDRESSES_NEW (insn, -1);
6237 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6238 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6240 insn = emit_label_after (pool_end, pool->pool_insn);
6241 INSN_ADDRESSES_NEW (insn, -1);
6243 s390_dump_pool (pool, 1);
6247 /* Replace all literal pool references. */
6249 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6252 replace_ltrel_base (&PATTERN (insn));
6254 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6256 rtx addr, pool_ref = NULL_RTX;
6257 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6260 if (s390_execute_label (insn))
6261 addr = s390_find_execute (pool, insn);
6263 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6264 get_pool_mode (pool_ref));
6266 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6267 INSN_CODE (insn) = -1;
6273 /* Free the pool. */
6274 s390_free_pool (pool);
6277 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6278 We have decided we cannot use this pool, so revert all changes
6279 to the current function that were done by s390_mainpool_start. */
6281 s390_mainpool_cancel (struct constant_pool *pool)
6283 /* We didn't actually change the instruction stream, so simply
6284 free the pool memory. */
6285 s390_free_pool (pool);
6289 /* Chunkify the literal pool. */
6291 #define S390_POOL_CHUNK_MIN 0xc00
6292 #define S390_POOL_CHUNK_MAX 0xe00
6294 static struct constant_pool *
6295 s390_chunkify_start (void)
6297 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6300 rtx pending_ltrel = NULL_RTX;
6303 rtx (*gen_reload_base) (rtx, rtx) =
6304 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6307 /* We need correct insn addresses. */
6309 shorten_branches (get_insns ());
6311 /* Scan all insns and move literals to pool chunks. */
6313 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6315 bool section_switch_p = false;
6317 /* Check for pending LTREL_BASE. */
6320 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6323 gcc_assert (ltrel_base == pending_ltrel);
6324 pending_ltrel = NULL_RTX;
6328 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6331 curr_pool = s390_start_pool (&pool_list, insn);
6333 s390_add_execute (curr_pool, insn);
6334 s390_add_pool_insn (curr_pool, insn);
6336 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6338 rtx pool_ref = NULL_RTX;
6339 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6342 rtx constant = get_pool_constant (pool_ref);
6343 enum machine_mode mode = get_pool_mode (pool_ref);
6346 curr_pool = s390_start_pool (&pool_list, insn);
6348 s390_add_constant (curr_pool, constant, mode);
6349 s390_add_pool_insn (curr_pool, insn);
6351 /* Don't split the pool chunk between a LTREL_OFFSET load
6352 and the corresponding LTREL_BASE. */
6353 if (GET_CODE (constant) == CONST
6354 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6355 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6357 gcc_assert (!pending_ltrel);
6358 pending_ltrel = pool_ref;
6363 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
6366 s390_add_pool_insn (curr_pool, insn);
6367 /* An LTREL_BASE must follow within the same basic block. */
6368 gcc_assert (!pending_ltrel);
6371 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
6372 section_switch_p = true;
6375 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6376 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6379 if (TARGET_CPU_ZARCH)
6381 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6384 s390_end_pool (curr_pool, NULL_RTX);
6389 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6390 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6393 /* We will later have to insert base register reload insns.
6394 Those will have an effect on code size, which we need to
6395 consider here. This calculation makes rather pessimistic
6396 worst-case assumptions. */
6397 if (GET_CODE (insn) == CODE_LABEL)
6400 if (chunk_size < S390_POOL_CHUNK_MIN
6401 && curr_pool->size < S390_POOL_CHUNK_MIN
6402 && !section_switch_p)
6405 /* Pool chunks can only be inserted after BARRIERs ... */
6406 if (GET_CODE (insn) == BARRIER)
6408 s390_end_pool (curr_pool, insn);
6413 /* ... so if we don't find one in time, create one. */
6414 else if (chunk_size > S390_POOL_CHUNK_MAX
6415 || curr_pool->size > S390_POOL_CHUNK_MAX
6416 || section_switch_p)
6418 rtx label, jump, barrier;
6420 if (!section_switch_p)
6422 /* We can insert the barrier only after a 'real' insn. */
6423 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
6425 if (get_attr_length (insn) == 0)
6427 /* Don't separate LTREL_BASE from the corresponding
6428 LTREL_OFFSET load. */
6434 gcc_assert (!pending_ltrel);
6436 /* The old pool has to end before the section switch
6437 note in order to make it part of the current
6439 insn = PREV_INSN (insn);
6442 label = gen_label_rtx ();
6443 jump = emit_jump_insn_after (gen_jump (label), insn);
6444 barrier = emit_barrier_after (jump);
6445 insn = emit_label_after (label, barrier);
6446 JUMP_LABEL (jump) = label;
6447 LABEL_NUSES (label) = 1;
6449 INSN_ADDRESSES_NEW (jump, -1);
6450 INSN_ADDRESSES_NEW (barrier, -1);
6451 INSN_ADDRESSES_NEW (insn, -1);
6453 s390_end_pool (curr_pool, barrier);
6461 s390_end_pool (curr_pool, NULL_RTX);
6462 gcc_assert (!pending_ltrel);
6464 /* Find all labels that are branched into
6465 from an insn belonging to a different chunk. */
6467 far_labels = BITMAP_ALLOC (NULL);
6469 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6471 /* Labels marked with LABEL_PRESERVE_P can be target
6472 of non-local jumps, so we have to mark them.
6473 The same holds for named labels.
6475 Don't do that, however, if it is the label before
6478 if (GET_CODE (insn) == CODE_LABEL
6479 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
6481 rtx vec_insn = next_real_insn (insn);
6482 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6483 PATTERN (vec_insn) : NULL_RTX;
6485 || !(GET_CODE (vec_pat) == ADDR_VEC
6486 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6487 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
6490 /* If we have a direct jump (conditional or unconditional)
6491 or a casesi jump, check all potential targets. */
6492 else if (GET_CODE (insn) == JUMP_INSN)
6494 rtx pat = PATTERN (insn);
6495 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6496 pat = XVECEXP (pat, 0, 0);
6498 if (GET_CODE (pat) == SET)
6500 rtx label = JUMP_LABEL (insn);
6503 if (s390_find_pool (pool_list, label)
6504 != s390_find_pool (pool_list, insn))
6505 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6508 else if (GET_CODE (pat) == PARALLEL
6509 && XVECLEN (pat, 0) == 2
6510 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6511 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6512 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6514 /* Find the jump table used by this casesi jump. */
6515 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6516 rtx vec_insn = next_real_insn (vec_label);
6517 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6518 PATTERN (vec_insn) : NULL_RTX;
6520 && (GET_CODE (vec_pat) == ADDR_VEC
6521 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6523 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6525 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6527 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6529 if (s390_find_pool (pool_list, label)
6530 != s390_find_pool (pool_list, insn))
6531 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6538 /* Insert base register reload insns before every pool. */
6540 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6542 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6544 rtx insn = curr_pool->first_insn;
6545 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6548 /* Insert base register reload insns at every far label. */
6550 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6551 if (GET_CODE (insn) == CODE_LABEL
6552 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6554 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6557 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6559 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6564 BITMAP_FREE (far_labels);
6567 /* Recompute insn addresses. */
6569 init_insn_lengths ();
6570 shorten_branches (get_insns ());
6575 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6576 After we have decided to use this list, finish implementing
6577 all changes to the current function as required. */
6580 s390_chunkify_finish (struct constant_pool *pool_list)
6582 struct constant_pool *curr_pool = NULL;
6586 /* Replace all literal pool references. */
6588 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6591 replace_ltrel_base (&PATTERN (insn));
6593 curr_pool = s390_find_pool (pool_list, insn);
6597 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6599 rtx addr, pool_ref = NULL_RTX;
6600 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6603 if (s390_execute_label (insn))
6604 addr = s390_find_execute (curr_pool, insn);
6606 addr = s390_find_constant (curr_pool,
6607 get_pool_constant (pool_ref),
6608 get_pool_mode (pool_ref));
6610 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6611 INSN_CODE (insn) = -1;
6616 /* Dump out all literal pools. */
6618 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6619 s390_dump_pool (curr_pool, 0);
6621 /* Free pool list. */
6625 struct constant_pool *next = pool_list->next;
6626 s390_free_pool (pool_list);
6631 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6632 We have decided we cannot use this list, so revert all changes
6633 to the current function that were done by s390_chunkify_start. */
6636 s390_chunkify_cancel (struct constant_pool *pool_list)
6638 struct constant_pool *curr_pool = NULL;
6641 /* Remove all pool placeholder insns. */
6643 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6645 /* Did we insert an extra barrier? Remove it. */
6646 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6647 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6648 rtx label = NEXT_INSN (curr_pool->pool_insn);
6650 if (jump && GET_CODE (jump) == JUMP_INSN
6651 && barrier && GET_CODE (barrier) == BARRIER
6652 && label && GET_CODE (label) == CODE_LABEL
6653 && GET_CODE (PATTERN (jump)) == SET
6654 && SET_DEST (PATTERN (jump)) == pc_rtx
6655 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6656 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6659 remove_insn (barrier);
6660 remove_insn (label);
6663 remove_insn (curr_pool->pool_insn);
6666 /* Remove all base register reload insns. */
6668 for (insn = get_insns (); insn; )
6670 rtx next_insn = NEXT_INSN (insn);
6672 if (GET_CODE (insn) == INSN
6673 && GET_CODE (PATTERN (insn)) == SET
6674 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6675 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6681 /* Free pool list. */
6685 struct constant_pool *next = pool_list->next;
6686 s390_free_pool (pool_list);
6691 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6694 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6698 switch (GET_MODE_CLASS (mode))
6701 case MODE_DECIMAL_FLOAT:
6702 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6704 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6705 assemble_real (r, mode, align);
6709 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6710 mark_symbol_refs_as_used (exp);
6719 /* Return an RTL expression representing the value of the return address
6720 for the frame COUNT steps up from the current frame. FRAME is the
6721 frame pointer of that frame. */
6724 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6729 /* Without backchain, we fail for all but the current frame. */
6731 if (!TARGET_BACKCHAIN && count > 0)
6734 /* For the current frame, we need to make sure the initial
6735 value of RETURN_REGNUM is actually saved. */
6739 /* On non-z architectures branch splitting could overwrite r14. */
6740 if (TARGET_CPU_ZARCH)
6741 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6744 cfun_frame_layout.save_return_addr_p = true;
6745 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6749 if (TARGET_PACKED_STACK)
6750 offset = -2 * UNITS_PER_WORD;
6752 offset = RETURN_REGNUM * UNITS_PER_WORD;
6754 addr = plus_constant (frame, offset);
6755 addr = memory_address (Pmode, addr);
6756 return gen_rtx_MEM (Pmode, addr);
6759 /* Return an RTL expression representing the back chain stored in
6760 the current stack frame. */
6763 s390_back_chain_rtx (void)
6767 gcc_assert (TARGET_BACKCHAIN);
6769 if (TARGET_PACKED_STACK)
6770 chain = plus_constant (stack_pointer_rtx,
6771 STACK_POINTER_OFFSET - UNITS_PER_WORD);
6773 chain = stack_pointer_rtx;
6775 chain = gen_rtx_MEM (Pmode, chain);
6779 /* Find first call clobbered register unused in a function.
6780 This could be used as base register in a leaf function
6781 or for holding the return address before epilogue. */
6784 find_unused_clobbered_reg (void)
6787 for (i = 0; i < 6; i++)
6788 if (!df_regs_ever_live_p (i))
6794 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6795 clobbered hard regs in SETREG. */
6798 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
6800 int *regs_ever_clobbered = (int *)data;
6801 unsigned int i, regno;
6802 enum machine_mode mode = GET_MODE (setreg);
6804 if (GET_CODE (setreg) == SUBREG)
6806 rtx inner = SUBREG_REG (setreg);
6807 if (!GENERAL_REG_P (inner))
6809 regno = subreg_regno (setreg);
6811 else if (GENERAL_REG_P (setreg))
6812 regno = REGNO (setreg);
6817 i < regno + HARD_REGNO_NREGS (regno, mode);
6819 regs_ever_clobbered[i] = 1;
6822 /* Walks through all basic blocks of the current function looking
6823 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6824 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6825 each of those regs. */
6828 s390_regs_ever_clobbered (int *regs_ever_clobbered)
6834 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6836 /* For non-leaf functions we have to consider all call clobbered regs to be
6838 if (!current_function_is_leaf)
6840 for (i = 0; i < 16; i++)
6841 regs_ever_clobbered[i] = call_really_used_regs[i];
6844 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6845 this work is done by liveness analysis (mark_regs_live_at_end).
6846 Special care is needed for functions containing landing pads. Landing pads
6847 may use the eh registers, but the code which sets these registers is not
6848 contained in that function. Hence s390_regs_ever_clobbered is not able to
6849 deal with this automatically. */
6850 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
6851 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6852 if (crtl->calls_eh_return
6853 || (cfun->machine->has_landing_pad_p
6854 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
6855 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6857 /* For nonlocal gotos all call-saved registers have to be saved.
6858 This flag is also set for the unwinding code in libgcc.
6859 See expand_builtin_unwind_init. For regs_ever_live this is done by
6861 if (cfun->has_nonlocal_label)
6862 for (i = 0; i < 16; i++)
6863 if (!call_really_used_regs[i])
6864 regs_ever_clobbered[i] = 1;
6866 FOR_EACH_BB (cur_bb)
6868 FOR_BB_INSNS (cur_bb, cur_insn)
6870 if (INSN_P (cur_insn))
6871 note_stores (PATTERN (cur_insn),
6872 s390_reg_clobbered_rtx,
6873 regs_ever_clobbered);
6878 /* Determine the frame area which actually has to be accessed
6879 in the function epilogue. The values are stored at the
6880 given pointers AREA_BOTTOM (address of the lowest used stack
6881 address) and AREA_TOP (address of the first item which does
6882 not belong to the stack frame). */
6885 s390_frame_area (int *area_bottom, int *area_top)
6893 if (cfun_frame_layout.first_restore_gpr != -1)
6895 b = (cfun_frame_layout.gprs_offset
6896 + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
6897 t = b + (cfun_frame_layout.last_restore_gpr
6898 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
6901 if (TARGET_64BIT && cfun_save_high_fprs_p)
6903 b = MIN (b, cfun_frame_layout.f8_offset);
6904 t = MAX (t, (cfun_frame_layout.f8_offset
6905 + cfun_frame_layout.high_fprs * 8));
6909 for (i = 2; i < 4; i++)
6910 if (cfun_fpr_bit_p (i))
6912 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
6913 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
6920 /* Fill cfun->machine with info about register usage of current function.
6921 Return in CLOBBERED_REGS which GPRs are currently considered set. */
6924 s390_register_info (int clobbered_regs[])
6928 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
6929 cfun_frame_layout.fpr_bitmap = 0;
6930 cfun_frame_layout.high_fprs = 0;
6932 for (i = 24; i < 32; i++)
6933 if (df_regs_ever_live_p (i) && !global_regs[i])
6935 cfun_set_fpr_bit (i - 16);
6936 cfun_frame_layout.high_fprs++;
6939 /* Find first and last gpr to be saved. We trust regs_ever_live
6940 data, except that we don't save and restore global registers.
6942 Also, all registers with special meaning to the compiler need
6943 to be handled extra. */
6945 s390_regs_ever_clobbered (clobbered_regs);
6947 for (i = 0; i < 16; i++)
6948 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
6950 if (frame_pointer_needed)
6951 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
6954 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
6955 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
6957 clobbered_regs[BASE_REGNUM]
6958 |= (cfun->machine->base_reg
6959 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
6961 clobbered_regs[RETURN_REGNUM]
6962 |= (!current_function_is_leaf
6963 || TARGET_TPF_PROFILING
6964 || cfun->machine->split_branches_pending_p
6965 || cfun_frame_layout.save_return_addr_p
6966 || crtl->calls_eh_return
6969 clobbered_regs[STACK_POINTER_REGNUM]
6970 |= (!current_function_is_leaf
6971 || TARGET_TPF_PROFILING
6972 || cfun_save_high_fprs_p
6973 || get_frame_size () > 0
6974 || cfun->calls_alloca
6977 for (i = 6; i < 16; i++)
6978 if (df_regs_ever_live_p (i) || clobbered_regs[i])
6980 for (j = 15; j > i; j--)
6981 if (df_regs_ever_live_p (j) || clobbered_regs[j])
6986 /* Nothing to save/restore. */
6987 cfun_frame_layout.first_save_gpr_slot = -1;
6988 cfun_frame_layout.last_save_gpr_slot = -1;
6989 cfun_frame_layout.first_save_gpr = -1;
6990 cfun_frame_layout.first_restore_gpr = -1;
6991 cfun_frame_layout.last_save_gpr = -1;
6992 cfun_frame_layout.last_restore_gpr = -1;
6996 /* Save slots for gprs from i to j. */
6997 cfun_frame_layout.first_save_gpr_slot = i;
6998 cfun_frame_layout.last_save_gpr_slot = j;
7000 for (i = cfun_frame_layout.first_save_gpr_slot;
7001 i < cfun_frame_layout.last_save_gpr_slot + 1;
7003 if (clobbered_regs[i])
7006 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
7007 if (clobbered_regs[j])
7010 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
7012 /* Nothing to save/restore. */
7013 cfun_frame_layout.first_save_gpr = -1;
7014 cfun_frame_layout.first_restore_gpr = -1;
7015 cfun_frame_layout.last_save_gpr = -1;
7016 cfun_frame_layout.last_restore_gpr = -1;
7020 /* Save / Restore from gpr i to j. */
7021 cfun_frame_layout.first_save_gpr = i;
7022 cfun_frame_layout.first_restore_gpr = i;
7023 cfun_frame_layout.last_save_gpr = j;
7024 cfun_frame_layout.last_restore_gpr = j;
7030 /* Varargs functions need to save gprs 2 to 6. */
7031 if (cfun->va_list_gpr_size
7032 && crtl->args.info.gprs < GP_ARG_NUM_REG)
7034 int min_gpr = crtl->args.info.gprs;
7035 int max_gpr = min_gpr + cfun->va_list_gpr_size;
7036 if (max_gpr > GP_ARG_NUM_REG)
7037 max_gpr = GP_ARG_NUM_REG;
7039 if (cfun_frame_layout.first_save_gpr == -1
7040 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
7042 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
7043 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
7046 if (cfun_frame_layout.last_save_gpr == -1
7047 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
7049 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
7050 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
7054 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7055 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
7056 && crtl->args.info.fprs < FP_ARG_NUM_REG)
7058 int min_fpr = crtl->args.info.fprs;
7059 int max_fpr = min_fpr + cfun->va_list_fpr_size;
7060 if (max_fpr > FP_ARG_NUM_REG)
7061 max_fpr = FP_ARG_NUM_REG;
7063 /* ??? This is currently required to ensure proper location
7064 of the fpr save slots within the va_list save area. */
7065 if (TARGET_PACKED_STACK)
7068 for (i = min_fpr; i < max_fpr; i++)
7069 cfun_set_fpr_bit (i);
7074 for (i = 2; i < 4; i++)
7075 if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16])
7076 cfun_set_fpr_bit (i);
7079 /* Fill cfun->machine with info about frame of current function. */
7082 s390_frame_info (void)
7086 cfun_frame_layout.frame_size = get_frame_size ();
7087 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7088 fatal_error ("total size of local variables exceeds architecture limit");
7090 if (!TARGET_PACKED_STACK)
7092 cfun_frame_layout.backchain_offset = 0;
7093 cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
7094 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7095 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7096 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7099 else if (TARGET_BACKCHAIN) /* kernel stack layout */
7101 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7103 cfun_frame_layout.gprs_offset
7104 = (cfun_frame_layout.backchain_offset
7105 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
7110 cfun_frame_layout.f4_offset
7111 = (cfun_frame_layout.gprs_offset
7112 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7114 cfun_frame_layout.f0_offset
7115 = (cfun_frame_layout.f4_offset
7116 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7120 /* On 31 bit we have to care about alignment of the
7121 floating point regs to provide fastest access. */
7122 cfun_frame_layout.f0_offset
7123 = ((cfun_frame_layout.gprs_offset
7124 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
7125 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7127 cfun_frame_layout.f4_offset
7128 = (cfun_frame_layout.f0_offset
7129 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7132 else /* no backchain */
7134 cfun_frame_layout.f4_offset
7135 = (STACK_POINTER_OFFSET
7136 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7138 cfun_frame_layout.f0_offset
7139 = (cfun_frame_layout.f4_offset
7140 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7142 cfun_frame_layout.gprs_offset
7143 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7146 if (current_function_is_leaf
7147 && !TARGET_TPF_PROFILING
7148 && cfun_frame_layout.frame_size == 0
7149 && !cfun_save_high_fprs_p
7150 && !cfun->calls_alloca
7154 if (!TARGET_PACKED_STACK)
7155 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
7156 + crtl->outgoing_args_size
7157 + cfun_frame_layout.high_fprs * 8);
7160 if (TARGET_BACKCHAIN)
7161 cfun_frame_layout.frame_size += UNITS_PER_WORD;
7163 /* No alignment trouble here because f8-f15 are only saved under
7165 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
7166 cfun_frame_layout.f4_offset),
7167 cfun_frame_layout.gprs_offset)
7168 - cfun_frame_layout.high_fprs * 8);
7170 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7172 for (i = 0; i < 8; i++)
7173 if (cfun_fpr_bit_p (i))
7174 cfun_frame_layout.frame_size += 8;
7176 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
7178 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7179 the frame size to sustain 8 byte alignment of stack frames. */
7180 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7181 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7182 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7184 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7188 /* Generate frame layout. Fills in register and frame data for the current
7189 function in cfun->machine. This routine can be called multiple times;
7190 it will re-do the complete frame layout every time. */
7193 s390_init_frame_layout (void)
7195 HOST_WIDE_INT frame_size;
7197 int clobbered_regs[16];
7199 /* On S/390 machines, we may need to perform branch splitting, which
7200 will require both base and return address register. We have no
7201 choice but to assume we're going to need them until right at the
7202 end of the machine dependent reorg phase. */
7203 if (!TARGET_CPU_ZARCH)
7204 cfun->machine->split_branches_pending_p = true;
7208 frame_size = cfun_frame_layout.frame_size;
7210 /* Try to predict whether we'll need the base register. */
7211 base_used = cfun->machine->split_branches_pending_p
7212 || crtl->uses_const_pool
7213 || (!DISP_IN_RANGE (frame_size)
7214 && !CONST_OK_FOR_K (frame_size));
7216 /* Decide which register to use as literal pool base. In small
7217 leaf functions, try to use an unused call-clobbered register
7218 as base register to avoid save/restore overhead. */
7220 cfun->machine->base_reg = NULL_RTX;
7221 else if (current_function_is_leaf && !df_regs_ever_live_p (5))
7222 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7224 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7226 s390_register_info (clobbered_regs);
7229 while (frame_size != cfun_frame_layout.frame_size);
7232 /* Update frame layout. Recompute actual register save data based on
7233 current info and update regs_ever_live for the special registers.
7234 May be called multiple times, but may never cause *more* registers
7235 to be saved than s390_init_frame_layout allocated room for. */
7238 s390_update_frame_layout (void)
7240 int clobbered_regs[16];
7242 s390_register_info (clobbered_regs);
7244 df_set_regs_ever_live (BASE_REGNUM,
7245 clobbered_regs[BASE_REGNUM] ? true : false);
7246 df_set_regs_ever_live (RETURN_REGNUM,
7247 clobbered_regs[RETURN_REGNUM] ? true : false);
7248 df_set_regs_ever_live (STACK_POINTER_REGNUM,
7249 clobbered_regs[STACK_POINTER_REGNUM] ? true : false);
7251 if (cfun->machine->base_reg)
7252 df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true);
7255 /* Return true if it is legal to put a value with MODE into REGNO. */
7258 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
7260 switch (REGNO_REG_CLASS (regno))
7263 if (REGNO_PAIR_OK (regno, mode))
7265 if (mode == SImode || mode == DImode)
7268 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
7273 if (FRAME_REGNO_P (regno) && mode == Pmode)
7278 if (REGNO_PAIR_OK (regno, mode))
7281 || (mode != TFmode && mode != TCmode && mode != TDmode))
7286 if (GET_MODE_CLASS (mode) == MODE_CC)
7290 if (REGNO_PAIR_OK (regno, mode))
7292 if (mode == SImode || mode == Pmode)
7303 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7306 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
7308 /* Once we've decided upon a register to use as base register, it must
7309 no longer be used for any other purpose. */
7310 if (cfun->machine->base_reg)
7311 if (REGNO (cfun->machine->base_reg) == old_reg
7312 || REGNO (cfun->machine->base_reg) == new_reg)
7318 /* Maximum number of registers to represent a value of mode MODE
7319 in a register of class RCLASS. */
7322 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
7327 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
7328 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
7330 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
7332 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
7336 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7339 /* Return true if register FROM can be eliminated via register TO. */
7342 s390_can_eliminate (const int from, const int to)
7344 /* On zSeries machines, we have not marked the base register as fixed.
7345 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7346 If a function requires the base register, we say here that this
7347 elimination cannot be performed. This will cause reload to free
7348 up the base register (as if it were fixed). On the other hand,
7349 if the current function does *not* require the base register, we
7350 say here the elimination succeeds, which in turn allows reload
7351 to allocate the base register for any other purpose. */
7352 if (from == BASE_REGNUM && to == BASE_REGNUM)
7354 if (TARGET_CPU_ZARCH)
7356 s390_init_frame_layout ();
7357 return cfun->machine->base_reg == NULL_RTX;
7363 /* Everything else must point into the stack frame. */
7364 gcc_assert (to == STACK_POINTER_REGNUM
7365 || to == HARD_FRAME_POINTER_REGNUM);
7367 gcc_assert (from == FRAME_POINTER_REGNUM
7368 || from == ARG_POINTER_REGNUM
7369 || from == RETURN_ADDRESS_POINTER_REGNUM);
7371 /* Make sure we actually saved the return address. */
7372 if (from == RETURN_ADDRESS_POINTER_REGNUM)
7373 if (!crtl->calls_eh_return
7375 && !cfun_frame_layout.save_return_addr_p)
7381 /* Return offset between register FROM and TO initially after prolog. */
7384 s390_initial_elimination_offset (int from, int to)
7386 HOST_WIDE_INT offset;
7389 /* ??? Why are we called for non-eliminable pairs? */
7390 if (!s390_can_eliminate (from, to))
7395 case FRAME_POINTER_REGNUM:
7396 offset = (get_frame_size()
7397 + STACK_POINTER_OFFSET
7398 + crtl->outgoing_args_size);
7401 case ARG_POINTER_REGNUM:
7402 s390_init_frame_layout ();
7403 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
7406 case RETURN_ADDRESS_POINTER_REGNUM:
7407 s390_init_frame_layout ();
7408 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
7409 gcc_assert (index >= 0);
7410 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
7411 offset += index * UNITS_PER_WORD;
7425 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7426 to register BASE. Return generated insn. */
7429 save_fpr (rtx base, int offset, int regnum)
7432 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7434 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
7435 set_mem_alias_set (addr, get_varargs_alias_set ());
7437 set_mem_alias_set (addr, get_frame_alias_set ());
7439 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
7442 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7443 to register BASE. Return generated insn. */
7446 restore_fpr (rtx base, int offset, int regnum)
7449 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
7450 set_mem_alias_set (addr, get_frame_alias_set ());
7452 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
7455 /* Return true if REGNO is a global register, but not one
7456 of the special ones that need to be saved/restored in anyway. */
7459 global_not_special_regno_p (int regno)
7461 return (global_regs[regno]
7462 /* These registers are special and need to be
7463 restored in any case. */
7464 && !(regno == STACK_POINTER_REGNUM
7465 || regno == RETURN_REGNUM
7466 || regno == BASE_REGNUM
7467 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
7470 /* Generate insn to save registers FIRST to LAST into
7471 the register save area located at offset OFFSET
7472 relative to register BASE. */
7475 save_gprs (rtx base, int offset, int first, int last)
7477 rtx addr, insn, note;
7480 addr = plus_constant (base, offset);
7481 addr = gen_rtx_MEM (Pmode, addr);
7483 set_mem_alias_set (addr, get_frame_alias_set ());
7485 /* Special-case single register. */
7489 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
7491 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
7493 if (!global_not_special_regno_p (first))
7494 RTX_FRAME_RELATED_P (insn) = 1;
7499 insn = gen_store_multiple (addr,
7500 gen_rtx_REG (Pmode, first),
7501 GEN_INT (last - first + 1));
7503 if (first <= 6 && cfun->stdarg)
7504 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
7506 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
7509 set_mem_alias_set (mem, get_varargs_alias_set ());
7512 /* We need to set the FRAME_RELATED flag on all SETs
7513 inside the store-multiple pattern.
7515 However, we must not emit DWARF records for registers 2..5
7516 if they are stored for use by variable arguments ...
7518 ??? Unfortunately, it is not enough to simply not the
7519 FRAME_RELATED flags for those SETs, because the first SET
7520 of the PARALLEL is always treated as if it had the flag
7521 set, even if it does not. Therefore we emit a new pattern
7522 without those registers as REG_FRAME_RELATED_EXPR note. */
7524 if (first >= 6 && !global_not_special_regno_p (first))
7526 rtx pat = PATTERN (insn);
7528 for (i = 0; i < XVECLEN (pat, 0); i++)
7529 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
7530 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
7532 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
7534 RTX_FRAME_RELATED_P (insn) = 1;
7540 for (start = first >= 6 ? first : 6; start <= last; start++)
7541 if (!global_not_special_regno_p (start))
7547 addr = plus_constant (base, offset + (start - first) * UNITS_PER_WORD);
7548 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
7549 gen_rtx_REG (Pmode, start),
7550 GEN_INT (last - start + 1));
7551 note = PATTERN (note);
7553 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
7555 for (i = 0; i < XVECLEN (note, 0); i++)
7556 if (GET_CODE (XVECEXP (note, 0, i)) == SET
7557 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
7559 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
7561 RTX_FRAME_RELATED_P (insn) = 1;
7567 /* Generate insn to restore registers FIRST to LAST from
7568 the register save area located at offset OFFSET
7569 relative to register BASE. */
7572 restore_gprs (rtx base, int offset, int first, int last)
7576 addr = plus_constant (base, offset);
7577 addr = gen_rtx_MEM (Pmode, addr);
7578 set_mem_alias_set (addr, get_frame_alias_set ());
7580 /* Special-case single register. */
7584 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
7586 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
7591 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
7593 GEN_INT (last - first + 1));
7597 /* Return insn sequence to load the GOT register. */
7599 static GTY(()) rtx got_symbol;
7601 s390_load_got (void)
7607 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7608 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7613 if (TARGET_CPU_ZARCH)
7615 emit_move_insn (pic_offset_table_rtx, got_symbol);
7621 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7622 UNSPEC_LTREL_OFFSET);
7623 offset = gen_rtx_CONST (Pmode, offset);
7624 offset = force_const_mem (Pmode, offset);
7626 emit_move_insn (pic_offset_table_rtx, offset);
7628 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7630 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7632 emit_move_insn (pic_offset_table_rtx, offset);
7635 insns = get_insns ();
7640 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7641 and the change to the stack pointer. */
7644 s390_emit_stack_tie (void)
7646 rtx mem = gen_frame_mem (BLKmode,
7647 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
7649 emit_insn (gen_stack_tie (mem));
7652 /* Expand the prologue into a bunch of separate insns. */
7655 s390_emit_prologue (void)
7663 /* Complete frame layout. */
7665 s390_update_frame_layout ();
7667 /* Annotate all constant pool references to let the scheduler know
7668 they implicitly use the base register. */
7670 push_topmost_sequence ();
7672 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7675 annotate_constant_pool_refs (&PATTERN (insn));
7676 df_insn_rescan (insn);
7679 pop_topmost_sequence ();
7681 /* Choose best register to use for temp use within prologue.
7682 See below for why TPF must use the register 1. */
7684 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7685 && !current_function_is_leaf
7686 && !TARGET_TPF_PROFILING)
7687 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7689 temp_reg = gen_rtx_REG (Pmode, 1);
7691 /* Save call saved gprs. */
7692 if (cfun_frame_layout.first_save_gpr != -1)
7694 insn = save_gprs (stack_pointer_rtx,
7695 cfun_frame_layout.gprs_offset +
7696 UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr
7697 - cfun_frame_layout.first_save_gpr_slot),
7698 cfun_frame_layout.first_save_gpr,
7699 cfun_frame_layout.last_save_gpr);
7703 /* Dummy insn to mark literal pool slot. */
7705 if (cfun->machine->base_reg)
7706 emit_insn (gen_main_pool (cfun->machine->base_reg));
7708 offset = cfun_frame_layout.f0_offset;
7710 /* Save f0 and f2. */
7711 for (i = 0; i < 2; i++)
7713 if (cfun_fpr_bit_p (i))
7715 save_fpr (stack_pointer_rtx, offset, i + 16);
7718 else if (!TARGET_PACKED_STACK)
7722 /* Save f4 and f6. */
7723 offset = cfun_frame_layout.f4_offset;
7724 for (i = 2; i < 4; i++)
7726 if (cfun_fpr_bit_p (i))
7728 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7731 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7732 therefore are not frame related. */
7733 if (!call_really_used_regs[i + 16])
7734 RTX_FRAME_RELATED_P (insn) = 1;
7736 else if (!TARGET_PACKED_STACK)
7740 if (TARGET_PACKED_STACK
7741 && cfun_save_high_fprs_p
7742 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7744 offset = (cfun_frame_layout.f8_offset
7745 + (cfun_frame_layout.high_fprs - 1) * 8);
7747 for (i = 15; i > 7 && offset >= 0; i--)
7748 if (cfun_fpr_bit_p (i))
7750 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7752 RTX_FRAME_RELATED_P (insn) = 1;
7755 if (offset >= cfun_frame_layout.f8_offset)
7759 if (!TARGET_PACKED_STACK)
7760 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7762 /* Decrement stack pointer. */
7764 if (cfun_frame_layout.frame_size > 0)
7766 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7769 if (s390_stack_size)
7771 HOST_WIDE_INT stack_guard;
7773 if (s390_stack_guard)
7774 stack_guard = s390_stack_guard;
7777 /* If no value for stack guard is provided the smallest power of 2
7778 larger than the current frame size is chosen. */
7780 while (stack_guard < cfun_frame_layout.frame_size)
7784 if (cfun_frame_layout.frame_size >= s390_stack_size)
7786 warning (0, "frame size of function %qs is "
7787 HOST_WIDE_INT_PRINT_DEC
7788 " bytes exceeding user provided stack limit of "
7789 HOST_WIDE_INT_PRINT_DEC " bytes. "
7790 "An unconditional trap is added.",
7791 current_function_name(), cfun_frame_layout.frame_size,
7793 emit_insn (gen_trap ());
7797 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7798 & ~(stack_guard - 1));
7799 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7800 GEN_INT (stack_check_mask));
7802 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode, t, const0_rtx),
7803 t, const0_rtx, const0_rtx));
7805 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode, t, const0_rtx),
7806 t, const0_rtx, const0_rtx));
7810 if (s390_warn_framesize > 0
7811 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7812 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7813 current_function_name (), cfun_frame_layout.frame_size);
7815 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7816 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7818 /* Save incoming stack pointer into temp reg. */
7819 if (TARGET_BACKCHAIN || next_fpr)
7820 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7822 /* Subtract frame size from stack pointer. */
7824 if (DISP_IN_RANGE (INTVAL (frame_off)))
7826 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7827 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7829 insn = emit_insn (insn);
7833 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7834 frame_off = force_const_mem (Pmode, frame_off);
7836 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7837 annotate_constant_pool_refs (&PATTERN (insn));
7840 RTX_FRAME_RELATED_P (insn) = 1;
7841 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7842 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
7843 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7844 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7847 /* Set backchain. */
7849 if (TARGET_BACKCHAIN)
7851 if (cfun_frame_layout.backchain_offset)
7852 addr = gen_rtx_MEM (Pmode,
7853 plus_constant (stack_pointer_rtx,
7854 cfun_frame_layout.backchain_offset));
7856 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7857 set_mem_alias_set (addr, get_frame_alias_set ());
7858 insn = emit_insn (gen_move_insn (addr, temp_reg));
7861 /* If we support asynchronous exceptions (e.g. for Java),
7862 we need to make sure the backchain pointer is set up
7863 before any possibly trapping memory access. */
7865 if (TARGET_BACKCHAIN && flag_non_call_exceptions)
7867 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7868 emit_clobber (addr);
7872 /* Save fprs 8 - 15 (64 bit ABI). */
7874 if (cfun_save_high_fprs_p && next_fpr)
7876 /* If the stack might be accessed through a different register
7877 we have to make sure that the stack pointer decrement is not
7878 moved below the use of the stack slots. */
7879 s390_emit_stack_tie ();
7881 insn = emit_insn (gen_add2_insn (temp_reg,
7882 GEN_INT (cfun_frame_layout.f8_offset)));
7886 for (i = 24; i <= next_fpr; i++)
7887 if (cfun_fpr_bit_p (i - 16))
7889 rtx addr = plus_constant (stack_pointer_rtx,
7890 cfun_frame_layout.frame_size
7891 + cfun_frame_layout.f8_offset
7894 insn = save_fpr (temp_reg, offset, i);
7896 RTX_FRAME_RELATED_P (insn) = 1;
7897 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
7898 gen_rtx_SET (VOIDmode,
7899 gen_rtx_MEM (DFmode, addr),
7900 gen_rtx_REG (DFmode, i)));
7904 /* Set frame pointer, if needed. */
7906 if (frame_pointer_needed)
7908 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7909 RTX_FRAME_RELATED_P (insn) = 1;
7912 /* Set up got pointer, if needed. */
7914 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
7916 rtx insns = s390_load_got ();
7918 for (insn = insns; insn; insn = NEXT_INSN (insn))
7919 annotate_constant_pool_refs (&PATTERN (insn));
7924 if (TARGET_TPF_PROFILING)
7926 /* Generate a BAS instruction to serve as a function
7927 entry intercept to facilitate the use of tracing
7928 algorithms located at the branch target. */
7929 emit_insn (gen_prologue_tpf ());
7931 /* Emit a blockage here so that all code
7932 lies between the profiling mechanisms. */
7933 emit_insn (gen_blockage ());
7937 /* Expand the epilogue into a bunch of separate insns. */
7940 s390_emit_epilogue (bool sibcall)
7942 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
7943 int area_bottom, area_top, offset = 0;
7948 if (TARGET_TPF_PROFILING)
7951 /* Generate a BAS instruction to serve as a function
7952 entry intercept to facilitate the use of tracing
7953 algorithms located at the branch target. */
7955 /* Emit a blockage here so that all code
7956 lies between the profiling mechanisms. */
7957 emit_insn (gen_blockage ());
7959 emit_insn (gen_epilogue_tpf ());
7962 /* Check whether to use frame or stack pointer for restore. */
7964 frame_pointer = (frame_pointer_needed
7965 ? hard_frame_pointer_rtx : stack_pointer_rtx);
7967 s390_frame_area (&area_bottom, &area_top);
7969 /* Check whether we can access the register save area.
7970 If not, increment the frame pointer as required. */
7972 if (area_top <= area_bottom)
7974 /* Nothing to restore. */
7976 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
7977 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
7979 /* Area is in range. */
7980 offset = cfun_frame_layout.frame_size;
7984 rtx insn, frame_off, cfa;
7986 offset = area_bottom < 0 ? -area_bottom : 0;
7987 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
7989 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
7990 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
7991 if (DISP_IN_RANGE (INTVAL (frame_off)))
7993 insn = gen_rtx_SET (VOIDmode, frame_pointer,
7994 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
7995 insn = emit_insn (insn);
7999 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8000 frame_off = force_const_mem (Pmode, frame_off);
8002 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
8003 annotate_constant_pool_refs (&PATTERN (insn));
8005 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
8006 RTX_FRAME_RELATED_P (insn) = 1;
8009 /* Restore call saved fprs. */
8013 if (cfun_save_high_fprs_p)
8015 next_offset = cfun_frame_layout.f8_offset;
8016 for (i = 24; i < 32; i++)
8018 if (cfun_fpr_bit_p (i - 16))
8020 restore_fpr (frame_pointer,
8021 offset + next_offset, i);
8023 = alloc_reg_note (REG_CFA_RESTORE,
8024 gen_rtx_REG (DFmode, i), cfa_restores);
8033 next_offset = cfun_frame_layout.f4_offset;
8034 for (i = 18; i < 20; i++)
8036 if (cfun_fpr_bit_p (i - 16))
8038 restore_fpr (frame_pointer,
8039 offset + next_offset, i);
8041 = alloc_reg_note (REG_CFA_RESTORE,
8042 gen_rtx_REG (DFmode, i), cfa_restores);
8045 else if (!TARGET_PACKED_STACK)
8051 /* Return register. */
8053 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8055 /* Restore call saved gprs. */
8057 if (cfun_frame_layout.first_restore_gpr != -1)
8062 /* Check for global register and save them
8063 to stack location from where they get restored. */
8065 for (i = cfun_frame_layout.first_restore_gpr;
8066 i <= cfun_frame_layout.last_restore_gpr;
8069 if (global_not_special_regno_p (i))
8071 addr = plus_constant (frame_pointer,
8072 offset + cfun_frame_layout.gprs_offset
8073 + (i - cfun_frame_layout.first_save_gpr_slot)
8075 addr = gen_rtx_MEM (Pmode, addr);
8076 set_mem_alias_set (addr, get_frame_alias_set ());
8077 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
8081 = alloc_reg_note (REG_CFA_RESTORE,
8082 gen_rtx_REG (Pmode, i), cfa_restores);
8087 /* Fetch return address from stack before load multiple,
8088 this will do good for scheduling. */
8090 if (cfun_frame_layout.save_return_addr_p
8091 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
8092 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
8094 int return_regnum = find_unused_clobbered_reg();
8097 return_reg = gen_rtx_REG (Pmode, return_regnum);
8099 addr = plus_constant (frame_pointer,
8100 offset + cfun_frame_layout.gprs_offset
8102 - cfun_frame_layout.first_save_gpr_slot)
8104 addr = gen_rtx_MEM (Pmode, addr);
8105 set_mem_alias_set (addr, get_frame_alias_set ());
8106 emit_move_insn (return_reg, addr);
8110 insn = restore_gprs (frame_pointer,
8111 offset + cfun_frame_layout.gprs_offset
8112 + (cfun_frame_layout.first_restore_gpr
8113 - cfun_frame_layout.first_save_gpr_slot)
8115 cfun_frame_layout.first_restore_gpr,
8116 cfun_frame_layout.last_restore_gpr);
8117 insn = emit_insn (insn);
8118 REG_NOTES (insn) = cfa_restores;
8119 add_reg_note (insn, REG_CFA_DEF_CFA,
8120 plus_constant (stack_pointer_rtx, STACK_POINTER_OFFSET));
8121 RTX_FRAME_RELATED_P (insn) = 1;
8127 /* Return to caller. */
8129 p = rtvec_alloc (2);
8131 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
8132 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
8133 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
8138 /* Return the size in bytes of a function argument of
8139 type TYPE and/or mode MODE. At least one of TYPE or
8140 MODE must be specified. */
8143 s390_function_arg_size (enum machine_mode mode, const_tree type)
8146 return int_size_in_bytes (type);
8148 /* No type info available for some library calls ... */
8149 if (mode != BLKmode)
8150 return GET_MODE_SIZE (mode);
8152 /* If we have neither type nor mode, abort */
8156 /* Return true if a function argument of type TYPE and mode MODE
8157 is to be passed in a floating-point register, if available. */
8160 s390_function_arg_float (enum machine_mode mode, tree type)
8162 int size = s390_function_arg_size (mode, type);
8166 /* Soft-float changes the ABI: no floating-point registers are used. */
8167 if (TARGET_SOFT_FLOAT)
8170 /* No type info available for some library calls ... */
8172 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
8174 /* The ABI says that record types with a single member are treated
8175 just like that member would be. */
8176 while (TREE_CODE (type) == RECORD_TYPE)
8178 tree field, single = NULL_TREE;
8180 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
8182 if (TREE_CODE (field) != FIELD_DECL)
8185 if (single == NULL_TREE)
8186 single = TREE_TYPE (field);
8191 if (single == NULL_TREE)
8197 return TREE_CODE (type) == REAL_TYPE;
8200 /* Return true if a function argument of type TYPE and mode MODE
8201 is to be passed in an integer register, or a pair of integer
8202 registers, if available. */
8205 s390_function_arg_integer (enum machine_mode mode, tree type)
8207 int size = s390_function_arg_size (mode, type);
8211 /* No type info available for some library calls ... */
8213 return GET_MODE_CLASS (mode) == MODE_INT
8214 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8216 /* We accept small integral (and similar) types. */
8217 if (INTEGRAL_TYPE_P (type)
8218 || POINTER_TYPE_P (type)
8219 || TREE_CODE (type) == OFFSET_TYPE
8220 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
8223 /* We also accept structs of size 1, 2, 4, 8 that are not
8224 passed in floating-point registers. */
8225 if (AGGREGATE_TYPE_P (type)
8226 && exact_log2 (size) >= 0
8227 && !s390_function_arg_float (mode, type))
8233 /* Return 1 if a function argument of type TYPE and mode MODE
8234 is to be passed by reference. The ABI specifies that only
8235 structures of size 1, 2, 4, or 8 bytes are passed by value,
8236 all other structures (and complex numbers) are passed by
8240 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
8241 enum machine_mode mode, const_tree type,
8242 bool named ATTRIBUTE_UNUSED)
8244 int size = s390_function_arg_size (mode, type);
8250 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
8253 if (TREE_CODE (type) == COMPLEX_TYPE
8254 || TREE_CODE (type) == VECTOR_TYPE)
8261 /* Update the data in CUM to advance over an argument of mode MODE and
8262 data type TYPE. (TYPE is null for libcalls where that information
8263 may not be available.). The boolean NAMED specifies whether the
8264 argument is a named argument (as opposed to an unnamed argument
8265 matching an ellipsis). */
8268 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8269 tree type, int named ATTRIBUTE_UNUSED)
8271 if (s390_function_arg_float (mode, type))
8275 else if (s390_function_arg_integer (mode, type))
8277 int size = s390_function_arg_size (mode, type);
8278 cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
8284 /* Define where to put the arguments to a function.
8285 Value is zero to push the argument on the stack,
8286 or a hard register in which to store the argument.
8288 MODE is the argument's machine mode.
8289 TYPE is the data type of the argument (as a tree).
8290 This is null for libcalls where that information may
8292 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8293 the preceding args and about the function being called.
8294 NAMED is nonzero if this argument is a named parameter
8295 (otherwise it is an extra parameter matching an ellipsis).
8297 On S/390, we use general purpose registers 2 through 6 to
8298 pass integer, pointer, and certain structure arguments, and
8299 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8300 to pass floating point arguments. All remaining arguments
8301 are pushed to the stack. */
8304 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8305 int named ATTRIBUTE_UNUSED)
8307 if (s390_function_arg_float (mode, type))
8309 if (cum->fprs + 1 > FP_ARG_NUM_REG)
8312 return gen_rtx_REG (mode, cum->fprs + 16);
8314 else if (s390_function_arg_integer (mode, type))
8316 int size = s390_function_arg_size (mode, type);
8317 int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
8319 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
8322 return gen_rtx_REG (mode, cum->gprs + 2);
8325 /* After the real arguments, expand_call calls us once again
8326 with a void_type_node type. Whatever we return here is
8327 passed as operand 2 to the call expanders.
8329 We don't need this feature ... */
8330 else if (type == void_type_node)
8336 /* Return true if return values of type TYPE should be returned
8337 in a memory buffer whose address is passed by the caller as
8338 hidden first argument. */
8341 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8343 /* We accept small integral (and similar) types. */
8344 if (INTEGRAL_TYPE_P (type)
8345 || POINTER_TYPE_P (type)
8346 || TREE_CODE (type) == OFFSET_TYPE
8347 || TREE_CODE (type) == REAL_TYPE)
8348 return int_size_in_bytes (type) > 8;
8350 /* Aggregates and similar constructs are always returned
8352 if (AGGREGATE_TYPE_P (type)
8353 || TREE_CODE (type) == COMPLEX_TYPE
8354 || TREE_CODE (type) == VECTOR_TYPE)
8357 /* ??? We get called on all sorts of random stuff from
8358 aggregate_value_p. We can't abort, but it's not clear
8359 what's safe to return. Pretend it's a struct I guess. */
8363 /* Function arguments and return values are promoted to word size. */
8365 static enum machine_mode
8366 s390_promote_function_mode (const_tree type, enum machine_mode mode,
8368 const_tree fntype ATTRIBUTE_UNUSED,
8369 int for_return ATTRIBUTE_UNUSED)
8371 if (INTEGRAL_MODE_P (mode)
8372 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
8374 if (POINTER_TYPE_P (type))
8375 *punsignedp = POINTERS_EXTEND_UNSIGNED;
8382 /* Define where to return a (scalar) value of type TYPE.
8383 If TYPE is null, define where to return a (scalar)
8384 value of mode MODE from a libcall. */
8387 s390_function_value (const_tree type, const_tree fn, enum machine_mode mode)
8391 int unsignedp = TYPE_UNSIGNED (type);
8392 mode = promote_function_mode (type, TYPE_MODE (type), &unsignedp, fn, 1);
8395 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8396 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8398 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8399 return gen_rtx_REG (mode, 16);
8401 return gen_rtx_REG (mode, 2);
8405 /* Create and return the va_list datatype.
8407 On S/390, va_list is an array type equivalent to
8409 typedef struct __va_list_tag
8413 void *__overflow_arg_area;
8414 void *__reg_save_area;
8417 where __gpr and __fpr hold the number of general purpose
8418 or floating point arguments used up to now, respectively,
8419 __overflow_arg_area points to the stack location of the
8420 next argument passed on the stack, and __reg_save_area
8421 always points to the start of the register area in the
8422 call frame of the current function. The function prologue
8423 saves all registers used for argument passing into this
8424 area if the function uses variable arguments. */
8427 s390_build_builtin_va_list (void)
8429 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
8431 record = lang_hooks.types.make_type (RECORD_TYPE);
8434 build_decl (BUILTINS_LOCATION,
8435 TYPE_DECL, get_identifier ("__va_list_tag"), record);
8437 f_gpr = build_decl (BUILTINS_LOCATION,
8438 FIELD_DECL, get_identifier ("__gpr"),
8439 long_integer_type_node);
8440 f_fpr = build_decl (BUILTINS_LOCATION,
8441 FIELD_DECL, get_identifier ("__fpr"),
8442 long_integer_type_node);
8443 f_ovf = build_decl (BUILTINS_LOCATION,
8444 FIELD_DECL, get_identifier ("__overflow_arg_area"),
8446 f_sav = build_decl (BUILTINS_LOCATION,
8447 FIELD_DECL, get_identifier ("__reg_save_area"),
8450 va_list_gpr_counter_field = f_gpr;
8451 va_list_fpr_counter_field = f_fpr;
8453 DECL_FIELD_CONTEXT (f_gpr) = record;
8454 DECL_FIELD_CONTEXT (f_fpr) = record;
8455 DECL_FIELD_CONTEXT (f_ovf) = record;
8456 DECL_FIELD_CONTEXT (f_sav) = record;
8458 TREE_CHAIN (record) = type_decl;
8459 TYPE_NAME (record) = type_decl;
8460 TYPE_FIELDS (record) = f_gpr;
8461 TREE_CHAIN (f_gpr) = f_fpr;
8462 TREE_CHAIN (f_fpr) = f_ovf;
8463 TREE_CHAIN (f_ovf) = f_sav;
8465 layout_type (record);
8467 /* The correct type is an array type of one element. */
8468 return build_array_type (record, build_index_type (size_zero_node));
8471 /* Implement va_start by filling the va_list structure VALIST.
8472 STDARG_P is always true, and ignored.
8473 NEXTARG points to the first anonymous stack argument.
8475 The following global variables are used to initialize
8476 the va_list structure:
8479 holds number of gprs and fprs used for named arguments.
8480 crtl->args.arg_offset_rtx:
8481 holds the offset of the first anonymous stack argument
8482 (relative to the virtual arg pointer). */
8485 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
8487 HOST_WIDE_INT n_gpr, n_fpr;
8489 tree f_gpr, f_fpr, f_ovf, f_sav;
8490 tree gpr, fpr, ovf, sav, t;
8492 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8493 f_fpr = TREE_CHAIN (f_gpr);
8494 f_ovf = TREE_CHAIN (f_fpr);
8495 f_sav = TREE_CHAIN (f_ovf);
8497 valist = build_va_arg_indirect_ref (valist);
8498 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8499 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8500 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8501 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8503 /* Count number of gp and fp argument registers used. */
8505 n_gpr = crtl->args.info.gprs;
8506 n_fpr = crtl->args.info.fprs;
8508 if (cfun->va_list_gpr_size)
8510 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
8511 build_int_cst (NULL_TREE, n_gpr));
8512 TREE_SIDE_EFFECTS (t) = 1;
8513 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8516 if (cfun->va_list_fpr_size)
8518 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
8519 build_int_cst (NULL_TREE, n_fpr));
8520 TREE_SIDE_EFFECTS (t) = 1;
8521 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8524 /* Find the overflow area. */
8525 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
8526 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
8528 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
8530 off = INTVAL (crtl->args.arg_offset_rtx);
8531 off = off < 0 ? 0 : off;
8532 if (TARGET_DEBUG_ARG)
8533 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8534 (int)n_gpr, (int)n_fpr, off);
8536 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t, size_int (off));
8538 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
8539 TREE_SIDE_EFFECTS (t) = 1;
8540 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8543 /* Find the register save area. */
8544 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
8545 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
8547 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
8548 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
8549 size_int (-RETURN_REGNUM * UNITS_PER_WORD));
8551 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
8552 TREE_SIDE_EFFECTS (t) = 1;
8553 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
8557 /* Implement va_arg by updating the va_list structure
8558 VALIST as required to retrieve an argument of type
8559 TYPE, and returning that argument.
8561 Generates code equivalent to:
8563 if (integral value) {
8564 if (size <= 4 && args.gpr < 5 ||
8565 size > 4 && args.gpr < 4 )
8566 ret = args.reg_save_area[args.gpr+8]
8568 ret = *args.overflow_arg_area++;
8569 } else if (float value) {
8571 ret = args.reg_save_area[args.fpr+64]
8573 ret = *args.overflow_arg_area++;
8574 } else if (aggregate value) {
8576 ret = *args.reg_save_area[args.gpr]
8578 ret = **args.overflow_arg_area++;
8582 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
8583 gimple_seq *post_p ATTRIBUTE_UNUSED)
8585 tree f_gpr, f_fpr, f_ovf, f_sav;
8586 tree gpr, fpr, ovf, sav, reg, t, u;
8587 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
8588 tree lab_false, lab_over, addr;
8590 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
8591 f_fpr = TREE_CHAIN (f_gpr);
8592 f_ovf = TREE_CHAIN (f_fpr);
8593 f_sav = TREE_CHAIN (f_ovf);
8595 valist = build_va_arg_indirect_ref (valist);
8596 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
8597 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
8598 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
8600 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8601 both appear on a lhs. */
8602 valist = unshare_expr (valist);
8603 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
8605 size = int_size_in_bytes (type);
8607 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
8609 if (TARGET_DEBUG_ARG)
8611 fprintf (stderr, "va_arg: aggregate type");
8615 /* Aggregates are passed by reference. */
8620 /* kernel stack layout on 31 bit: It is assumed here that no padding
8621 will be added by s390_frame_info because for va_args always an even
8622 number of gprs has to be saved r15-r2 = 14 regs. */
8623 sav_ofs = 2 * UNITS_PER_WORD;
8624 sav_scale = UNITS_PER_WORD;
8625 size = UNITS_PER_WORD;
8626 max_reg = GP_ARG_NUM_REG - n_reg;
8628 else if (s390_function_arg_float (TYPE_MODE (type), type))
8630 if (TARGET_DEBUG_ARG)
8632 fprintf (stderr, "va_arg: float type");
8636 /* FP args go in FP registers, if present. */
8640 sav_ofs = 16 * UNITS_PER_WORD;
8642 max_reg = FP_ARG_NUM_REG - n_reg;
8646 if (TARGET_DEBUG_ARG)
8648 fprintf (stderr, "va_arg: other type");
8652 /* Otherwise into GP registers. */
8655 n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8657 /* kernel stack layout on 31 bit: It is assumed here that no padding
8658 will be added by s390_frame_info because for va_args always an even
8659 number of gprs has to be saved r15-r2 = 14 regs. */
8660 sav_ofs = 2 * UNITS_PER_WORD;
8662 if (size < UNITS_PER_WORD)
8663 sav_ofs += UNITS_PER_WORD - size;
8665 sav_scale = UNITS_PER_WORD;
8666 max_reg = GP_ARG_NUM_REG - n_reg;
8669 /* Pull the value out of the saved registers ... */
8671 lab_false = create_artificial_label (UNKNOWN_LOCATION);
8672 lab_over = create_artificial_label (UNKNOWN_LOCATION);
8673 addr = create_tmp_var (ptr_type_node, "addr");
8675 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
8676 t = build2 (GT_EXPR, boolean_type_node, reg, t);
8677 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8678 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8679 gimplify_and_add (t, pre_p);
8681 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav,
8682 size_int (sav_ofs));
8683 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
8684 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
8685 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, fold_convert (sizetype, u));
8687 gimplify_assign (addr, t, pre_p);
8689 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
8691 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
8694 /* ... Otherwise out of the overflow area. */
8697 if (size < UNITS_PER_WORD)
8698 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8699 size_int (UNITS_PER_WORD - size));
8701 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8703 gimplify_assign (addr, t, pre_p);
8705 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
8707 gimplify_assign (ovf, t, pre_p);
8709 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
8712 /* Increment register save count. */
8714 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8715 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8716 gimplify_and_add (u, pre_p);
8720 t = build_pointer_type_for_mode (build_pointer_type (type),
8722 addr = fold_convert (t, addr);
8723 addr = build_va_arg_indirect_ref (addr);
8727 t = build_pointer_type_for_mode (type, ptr_mode, true);
8728 addr = fold_convert (t, addr);
8731 return build_va_arg_indirect_ref (addr);
8739 S390_BUILTIN_THREAD_POINTER,
8740 S390_BUILTIN_SET_THREAD_POINTER,
8745 static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = {
8750 static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = {
8756 s390_init_builtins (void)
8760 ftype = build_function_type (ptr_type_node, void_list_node);
8761 add_builtin_function ("__builtin_thread_pointer", ftype,
8762 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8765 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8766 add_builtin_function ("__builtin_set_thread_pointer", ftype,
8767 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8771 /* Expand an expression EXP that calls a built-in function,
8772 with result going to TARGET if that's convenient
8773 (and in mode MODE if that's convenient).
8774 SUBTARGET may be used as the target for computing one of EXP's operands.
8775 IGNORE is nonzero if the value is to be ignored. */
8778 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8779 enum machine_mode mode ATTRIBUTE_UNUSED,
8780 int ignore ATTRIBUTE_UNUSED)
8784 enum insn_code const *code_for_builtin =
8785 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8787 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8788 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8789 enum insn_code icode;
8790 rtx op[MAX_ARGS], pat;
8794 call_expr_arg_iterator iter;
8796 if (fcode >= S390_BUILTIN_max)
8797 internal_error ("bad builtin fcode");
8798 icode = code_for_builtin[fcode];
8800 internal_error ("bad builtin fcode");
8802 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8805 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
8807 const struct insn_operand_data *insn_op;
8809 if (arg == error_mark_node)
8811 if (arity > MAX_ARGS)
8814 insn_op = &insn_data[icode].operand[arity + nonvoid];
8816 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
8818 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8819 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8825 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8827 || GET_MODE (target) != tmode
8828 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8829 target = gen_reg_rtx (tmode);
8835 pat = GEN_FCN (icode) (target);
8839 pat = GEN_FCN (icode) (target, op[0]);
8841 pat = GEN_FCN (icode) (op[0]);
8844 pat = GEN_FCN (icode) (target, op[0], op[1]);
8860 /* Output assembly code for the trampoline template to
8863 On S/390, we use gpr 1 internally in the trampoline code;
8864 gpr 0 is used to hold the static chain. */
8867 s390_asm_trampoline_template (FILE *file)
8870 op[0] = gen_rtx_REG (Pmode, 0);
8871 op[1] = gen_rtx_REG (Pmode, 1);
8875 output_asm_insn ("basr\t%1,0", op);
8876 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
8877 output_asm_insn ("br\t%1", op);
8878 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
8882 output_asm_insn ("basr\t%1,0", op);
8883 output_asm_insn ("lm\t%0,%1,6(%1)", op);
8884 output_asm_insn ("br\t%1", op);
8885 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
8889 /* Emit RTL insns to initialize the variable parts of a trampoline.
8890 FNADDR is an RTX for the address of the function's pure code.
8891 CXT is an RTX for the static chain value for the function. */
8894 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
8896 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
8899 emit_block_move (m_tramp, assemble_trampoline_template (),
8900 GEN_INT (2*UNITS_PER_WORD), BLOCK_OP_NORMAL);
8902 mem = adjust_address (m_tramp, Pmode, 2*UNITS_PER_WORD);
8903 emit_move_insn (mem, cxt);
8904 mem = adjust_address (m_tramp, Pmode, 3*UNITS_PER_WORD);
8905 emit_move_insn (mem, fnaddr);
8908 /* Output assembler code to FILE to increment profiler label # LABELNO
8909 for profiling a function entry. */
8912 s390_function_profiler (FILE *file, int labelno)
8917 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
8919 fprintf (file, "# function profiler \n");
8921 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
8922 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
8923 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
8925 op[2] = gen_rtx_REG (Pmode, 1);
8926 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8927 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
8929 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
8932 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
8933 op[4] = gen_rtx_CONST (Pmode, op[4]);
8938 output_asm_insn ("stg\t%0,%1", op);
8939 output_asm_insn ("larl\t%2,%3", op);
8940 output_asm_insn ("brasl\t%0,%4", op);
8941 output_asm_insn ("lg\t%0,%1", op);
8945 op[6] = gen_label_rtx ();
8947 output_asm_insn ("st\t%0,%1", op);
8948 output_asm_insn ("bras\t%2,%l6", op);
8949 output_asm_insn (".long\t%4", op);
8950 output_asm_insn (".long\t%3", op);
8951 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8952 output_asm_insn ("l\t%0,0(%2)", op);
8953 output_asm_insn ("l\t%2,4(%2)", op);
8954 output_asm_insn ("basr\t%0,%0", op);
8955 output_asm_insn ("l\t%0,%1", op);
8959 op[5] = gen_label_rtx ();
8960 op[6] = gen_label_rtx ();
8962 output_asm_insn ("st\t%0,%1", op);
8963 output_asm_insn ("bras\t%2,%l6", op);
8964 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
8965 output_asm_insn (".long\t%4-%l5", op);
8966 output_asm_insn (".long\t%3-%l5", op);
8967 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8968 output_asm_insn ("lr\t%0,%2", op);
8969 output_asm_insn ("a\t%0,0(%2)", op);
8970 output_asm_insn ("a\t%2,4(%2)", op);
8971 output_asm_insn ("basr\t%0,%0", op);
8972 output_asm_insn ("l\t%0,%1", op);
8976 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
8977 into its SYMBOL_REF_FLAGS. */
8980 s390_encode_section_info (tree decl, rtx rtl, int first)
8982 default_encode_section_info (decl, rtl, first);
8984 if (TREE_CODE (decl) == VAR_DECL)
8986 /* If a variable has a forced alignment to < 2 bytes, mark it
8987 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
8989 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
8990 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
8991 if (!DECL_SIZE (decl)
8992 || !DECL_ALIGN (decl)
8993 || !host_integerp (DECL_SIZE (decl), 0)
8994 || (DECL_ALIGN (decl) <= 64
8995 && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0)))
8996 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
8999 /* Literal pool references don't have a decl so they are handled
9000 differently here. We rely on the information in the MEM_ALIGN
9001 entry to decide upon natural alignment. */
9003 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
9004 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
9005 && (MEM_ALIGN (rtl) == 0
9006 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
9007 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
9010 /* Output thunk to FILE that implements a C++ virtual function call (with
9011 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9012 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9013 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9014 relative to the resulting this pointer. */
9017 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
9018 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9024 /* Operand 0 is the target function. */
9025 op[0] = XEXP (DECL_RTL (function), 0);
9026 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
9029 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
9030 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
9031 op[0] = gen_rtx_CONST (Pmode, op[0]);
9034 /* Operand 1 is the 'this' pointer. */
9035 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9036 op[1] = gen_rtx_REG (Pmode, 3);
9038 op[1] = gen_rtx_REG (Pmode, 2);
9040 /* Operand 2 is the delta. */
9041 op[2] = GEN_INT (delta);
9043 /* Operand 3 is the vcall_offset. */
9044 op[3] = GEN_INT (vcall_offset);
9046 /* Operand 4 is the temporary register. */
9047 op[4] = gen_rtx_REG (Pmode, 1);
9049 /* Operands 5 to 8 can be used as labels. */
9055 /* Operand 9 can be used for temporary register. */
9058 /* Generate code. */
9061 /* Setup literal pool pointer if required. */
9062 if ((!DISP_IN_RANGE (delta)
9063 && !CONST_OK_FOR_K (delta)
9064 && !CONST_OK_FOR_Os (delta))
9065 || (!DISP_IN_RANGE (vcall_offset)
9066 && !CONST_OK_FOR_K (vcall_offset)
9067 && !CONST_OK_FOR_Os (vcall_offset)))
9069 op[5] = gen_label_rtx ();
9070 output_asm_insn ("larl\t%4,%5", op);
9073 /* Add DELTA to this pointer. */
9076 if (CONST_OK_FOR_J (delta))
9077 output_asm_insn ("la\t%1,%2(%1)", op);
9078 else if (DISP_IN_RANGE (delta))
9079 output_asm_insn ("lay\t%1,%2(%1)", op);
9080 else if (CONST_OK_FOR_K (delta))
9081 output_asm_insn ("aghi\t%1,%2", op);
9082 else if (CONST_OK_FOR_Os (delta))
9083 output_asm_insn ("agfi\t%1,%2", op);
9086 op[6] = gen_label_rtx ();
9087 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
9091 /* Perform vcall adjustment. */
9094 if (DISP_IN_RANGE (vcall_offset))
9096 output_asm_insn ("lg\t%4,0(%1)", op);
9097 output_asm_insn ("ag\t%1,%3(%4)", op);
9099 else if (CONST_OK_FOR_K (vcall_offset))
9101 output_asm_insn ("lghi\t%4,%3", op);
9102 output_asm_insn ("ag\t%4,0(%1)", op);
9103 output_asm_insn ("ag\t%1,0(%4)", op);
9105 else if (CONST_OK_FOR_Os (vcall_offset))
9107 output_asm_insn ("lgfi\t%4,%3", op);
9108 output_asm_insn ("ag\t%4,0(%1)", op);
9109 output_asm_insn ("ag\t%1,0(%4)", op);
9113 op[7] = gen_label_rtx ();
9114 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
9115 output_asm_insn ("ag\t%4,0(%1)", op);
9116 output_asm_insn ("ag\t%1,0(%4)", op);
9120 /* Jump to target. */
9121 output_asm_insn ("jg\t%0", op);
9123 /* Output literal pool if required. */
9126 output_asm_insn (".align\t4", op);
9127 targetm.asm_out.internal_label (file, "L",
9128 CODE_LABEL_NUMBER (op[5]));
9132 targetm.asm_out.internal_label (file, "L",
9133 CODE_LABEL_NUMBER (op[6]));
9134 output_asm_insn (".long\t%2", op);
9138 targetm.asm_out.internal_label (file, "L",
9139 CODE_LABEL_NUMBER (op[7]));
9140 output_asm_insn (".long\t%3", op);
9145 /* Setup base pointer if required. */
9147 || (!DISP_IN_RANGE (delta)
9148 && !CONST_OK_FOR_K (delta)
9149 && !CONST_OK_FOR_Os (delta))
9150 || (!DISP_IN_RANGE (delta)
9151 && !CONST_OK_FOR_K (vcall_offset)
9152 && !CONST_OK_FOR_Os (vcall_offset)))
9154 op[5] = gen_label_rtx ();
9155 output_asm_insn ("basr\t%4,0", op);
9156 targetm.asm_out.internal_label (file, "L",
9157 CODE_LABEL_NUMBER (op[5]));
9160 /* Add DELTA to this pointer. */
9163 if (CONST_OK_FOR_J (delta))
9164 output_asm_insn ("la\t%1,%2(%1)", op);
9165 else if (DISP_IN_RANGE (delta))
9166 output_asm_insn ("lay\t%1,%2(%1)", op);
9167 else if (CONST_OK_FOR_K (delta))
9168 output_asm_insn ("ahi\t%1,%2", op);
9169 else if (CONST_OK_FOR_Os (delta))
9170 output_asm_insn ("afi\t%1,%2", op);
9173 op[6] = gen_label_rtx ();
9174 output_asm_insn ("a\t%1,%6-%5(%4)", op);
9178 /* Perform vcall adjustment. */
9181 if (CONST_OK_FOR_J (vcall_offset))
9183 output_asm_insn ("l\t%4,0(%1)", op);
9184 output_asm_insn ("a\t%1,%3(%4)", op);
9186 else if (DISP_IN_RANGE (vcall_offset))
9188 output_asm_insn ("l\t%4,0(%1)", op);
9189 output_asm_insn ("ay\t%1,%3(%4)", op);
9191 else if (CONST_OK_FOR_K (vcall_offset))
9193 output_asm_insn ("lhi\t%4,%3", op);
9194 output_asm_insn ("a\t%4,0(%1)", op);
9195 output_asm_insn ("a\t%1,0(%4)", op);
9197 else if (CONST_OK_FOR_Os (vcall_offset))
9199 output_asm_insn ("iilf\t%4,%3", op);
9200 output_asm_insn ("a\t%4,0(%1)", op);
9201 output_asm_insn ("a\t%1,0(%4)", op);
9205 op[7] = gen_label_rtx ();
9206 output_asm_insn ("l\t%4,%7-%5(%4)", op);
9207 output_asm_insn ("a\t%4,0(%1)", op);
9208 output_asm_insn ("a\t%1,0(%4)", op);
9211 /* We had to clobber the base pointer register.
9212 Re-setup the base pointer (with a different base). */
9213 op[5] = gen_label_rtx ();
9214 output_asm_insn ("basr\t%4,0", op);
9215 targetm.asm_out.internal_label (file, "L",
9216 CODE_LABEL_NUMBER (op[5]));
9219 /* Jump to target. */
9220 op[8] = gen_label_rtx ();
9223 output_asm_insn ("l\t%4,%8-%5(%4)", op);
9225 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9226 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9227 else if (flag_pic == 1)
9229 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9230 output_asm_insn ("l\t%4,%0(%4)", op);
9232 else if (flag_pic == 2)
9234 op[9] = gen_rtx_REG (Pmode, 0);
9235 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
9236 output_asm_insn ("a\t%4,%8-%5(%4)", op);
9237 output_asm_insn ("ar\t%4,%9", op);
9238 output_asm_insn ("l\t%4,0(%4)", op);
9241 output_asm_insn ("br\t%4", op);
9243 /* Output literal pool. */
9244 output_asm_insn (".align\t4", op);
9246 if (nonlocal && flag_pic == 2)
9247 output_asm_insn (".long\t%0", op);
9250 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9251 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
9254 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
9256 output_asm_insn (".long\t%0", op);
9258 output_asm_insn (".long\t%0-%5", op);
9262 targetm.asm_out.internal_label (file, "L",
9263 CODE_LABEL_NUMBER (op[6]));
9264 output_asm_insn (".long\t%2", op);
9268 targetm.asm_out.internal_label (file, "L",
9269 CODE_LABEL_NUMBER (op[7]));
9270 output_asm_insn (".long\t%3", op);
9276 s390_valid_pointer_mode (enum machine_mode mode)
9278 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9281 /* Checks whether the given CALL_EXPR would use a caller
9282 saved register. This is used to decide whether sibling call
9283 optimization could be performed on the respective function
9287 s390_call_saved_register_used (tree call_expr)
9289 CUMULATIVE_ARGS cum;
9291 enum machine_mode mode;
9296 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
9298 for (i = 0; i < call_expr_nargs (call_expr); i++)
9300 parameter = CALL_EXPR_ARG (call_expr, i);
9301 gcc_assert (parameter);
9303 /* For an undeclared variable passed as parameter we will get
9304 an ERROR_MARK node here. */
9305 if (TREE_CODE (parameter) == ERROR_MARK)
9308 type = TREE_TYPE (parameter);
9311 mode = TYPE_MODE (type);
9314 if (pass_by_reference (&cum, mode, type, true))
9317 type = build_pointer_type (type);
9320 parm_rtx = s390_function_arg (&cum, mode, type, 0);
9322 s390_function_arg_advance (&cum, mode, type, 0);
9324 if (parm_rtx && REG_P (parm_rtx))
9327 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
9329 if (! call_used_regs[reg + REGNO (parm_rtx)])
9336 /* Return true if the given call expression can be
9337 turned into a sibling call.
9338 DECL holds the declaration of the function to be called whereas
9339 EXP is the call expression itself. */
9342 s390_function_ok_for_sibcall (tree decl, tree exp)
9344 /* The TPF epilogue uses register 1. */
9345 if (TARGET_TPF_PROFILING)
9348 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9349 which would have to be restored before the sibcall. */
9350 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
9353 /* Register 6 on s390 is available as an argument register but unfortunately
9354 "caller saved". This makes functions needing this register for arguments
9355 not suitable for sibcalls. */
9356 return !s390_call_saved_register_used (exp);
9359 /* Return the fixed registers used for condition codes. */
9362 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
9365 *p2 = INVALID_REGNUM;
9370 /* This function is used by the call expanders of the machine description.
9371 It emits the call insn itself together with the necessary operations
9372 to adjust the target address and returns the emitted insn.
9373 ADDR_LOCATION is the target address rtx
9374 TLS_CALL the location of the thread-local symbol
9375 RESULT_REG the register where the result of the call should be stored
9376 RETADDR_REG the register where the return address should be stored
9377 If this parameter is NULL_RTX the call is considered
9378 to be a sibling call. */
9381 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
9384 bool plt_call = false;
9390 /* Direct function calls need special treatment. */
9391 if (GET_CODE (addr_location) == SYMBOL_REF)
9393 /* When calling a global routine in PIC mode, we must
9394 replace the symbol itself with the PLT stub. */
9395 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
9397 addr_location = gen_rtx_UNSPEC (Pmode,
9398 gen_rtvec (1, addr_location),
9400 addr_location = gen_rtx_CONST (Pmode, addr_location);
9404 /* Unless we can use the bras(l) insn, force the
9405 routine address into a register. */
9406 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
9409 addr_location = legitimize_pic_address (addr_location, 0);
9411 addr_location = force_reg (Pmode, addr_location);
9415 /* If it is already an indirect call or the code above moved the
9416 SYMBOL_REF to somewhere else make sure the address can be found in
9418 if (retaddr_reg == NULL_RTX
9419 && GET_CODE (addr_location) != SYMBOL_REF
9422 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
9423 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9426 addr_location = gen_rtx_MEM (QImode, addr_location);
9427 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
9429 if (result_reg != NULL_RTX)
9430 call = gen_rtx_SET (VOIDmode, result_reg, call);
9432 if (retaddr_reg != NULL_RTX)
9434 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
9436 if (tls_call != NULL_RTX)
9437 vec = gen_rtvec (3, call, clobber,
9438 gen_rtx_USE (VOIDmode, tls_call));
9440 vec = gen_rtvec (2, call, clobber);
9442 call = gen_rtx_PARALLEL (VOIDmode, vec);
9445 insn = emit_call_insn (call);
9447 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9448 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
9450 /* s390_function_ok_for_sibcall should
9451 have denied sibcalls in this case. */
9452 gcc_assert (retaddr_reg != NULL_RTX);
9454 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
9459 /* Implement CONDITIONAL_REGISTER_USAGE. */
9462 s390_conditional_register_usage (void)
9468 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9469 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
9471 if (TARGET_CPU_ZARCH)
9473 fixed_regs[BASE_REGNUM] = 0;
9474 call_used_regs[BASE_REGNUM] = 0;
9475 fixed_regs[RETURN_REGNUM] = 0;
9476 call_used_regs[RETURN_REGNUM] = 0;
9480 for (i = 24; i < 32; i++)
9481 call_used_regs[i] = call_really_used_regs[i] = 0;
9485 for (i = 18; i < 20; i++)
9486 call_used_regs[i] = call_really_used_regs[i] = 0;
9489 if (TARGET_SOFT_FLOAT)
9491 for (i = 16; i < 32; i++)
9492 call_used_regs[i] = fixed_regs[i] = 1;
9496 /* Corresponding function to eh_return expander. */
9498 static GTY(()) rtx s390_tpf_eh_return_symbol;
9500 s390_emit_tpf_eh_return (rtx target)
9504 if (!s390_tpf_eh_return_symbol)
9505 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
9507 reg = gen_rtx_REG (Pmode, 2);
9509 emit_move_insn (reg, target);
9510 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
9511 gen_rtx_REG (Pmode, RETURN_REGNUM));
9512 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
9514 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
9517 /* Rework the prologue/epilogue to avoid saving/restoring
9518 registers unnecessarily. */
9521 s390_optimize_prologue (void)
9523 rtx insn, new_insn, next_insn;
9525 /* Do a final recompute of the frame-related data. */
9527 s390_update_frame_layout ();
9529 /* If all special registers are in fact used, there's nothing we
9530 can do, so no point in walking the insn list. */
9532 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
9533 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
9534 && (TARGET_CPU_ZARCH
9535 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
9536 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
9539 /* Search for prologue/epilogue insns and replace them. */
9541 for (insn = get_insns (); insn; insn = next_insn)
9543 int first, last, off;
9544 rtx set, base, offset;
9546 next_insn = NEXT_INSN (insn);
9548 if (GET_CODE (insn) != INSN)
9551 if (GET_CODE (PATTERN (insn)) == PARALLEL
9552 && store_multiple_operation (PATTERN (insn), VOIDmode))
9554 set = XVECEXP (PATTERN (insn), 0, 0);
9555 first = REGNO (SET_SRC (set));
9556 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9557 offset = const0_rtx;
9558 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9559 off = INTVAL (offset);
9561 if (GET_CODE (base) != REG || off < 0)
9563 if (cfun_frame_layout.first_save_gpr != -1
9564 && (cfun_frame_layout.first_save_gpr < first
9565 || cfun_frame_layout.last_save_gpr > last))
9567 if (REGNO (base) != STACK_POINTER_REGNUM
9568 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9570 if (first > BASE_REGNUM || last < BASE_REGNUM)
9573 if (cfun_frame_layout.first_save_gpr != -1)
9575 new_insn = save_gprs (base,
9576 off + (cfun_frame_layout.first_save_gpr
9577 - first) * UNITS_PER_WORD,
9578 cfun_frame_layout.first_save_gpr,
9579 cfun_frame_layout.last_save_gpr);
9580 new_insn = emit_insn_before (new_insn, insn);
9581 INSN_ADDRESSES_NEW (new_insn, -1);
9588 if (cfun_frame_layout.first_save_gpr == -1
9589 && GET_CODE (PATTERN (insn)) == SET
9590 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
9591 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
9592 || (!TARGET_CPU_ZARCH
9593 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
9594 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
9596 set = PATTERN (insn);
9597 first = REGNO (SET_SRC (set));
9598 offset = const0_rtx;
9599 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9600 off = INTVAL (offset);
9602 if (GET_CODE (base) != REG || off < 0)
9604 if (REGNO (base) != STACK_POINTER_REGNUM
9605 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9612 if (GET_CODE (PATTERN (insn)) == PARALLEL
9613 && load_multiple_operation (PATTERN (insn), VOIDmode))
9615 set = XVECEXP (PATTERN (insn), 0, 0);
9616 first = REGNO (SET_DEST (set));
9617 last = first + XVECLEN (PATTERN (insn), 0) - 1;
9618 offset = const0_rtx;
9619 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9620 off = INTVAL (offset);
9622 if (GET_CODE (base) != REG || off < 0)
9624 if (cfun_frame_layout.first_restore_gpr != -1
9625 && (cfun_frame_layout.first_restore_gpr < first
9626 || cfun_frame_layout.last_restore_gpr > last))
9628 if (REGNO (base) != STACK_POINTER_REGNUM
9629 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9631 if (first > BASE_REGNUM || last < BASE_REGNUM)
9634 if (cfun_frame_layout.first_restore_gpr != -1)
9636 new_insn = restore_gprs (base,
9637 off + (cfun_frame_layout.first_restore_gpr
9638 - first) * UNITS_PER_WORD,
9639 cfun_frame_layout.first_restore_gpr,
9640 cfun_frame_layout.last_restore_gpr);
9641 new_insn = emit_insn_before (new_insn, insn);
9642 INSN_ADDRESSES_NEW (new_insn, -1);
9649 if (cfun_frame_layout.first_restore_gpr == -1
9650 && GET_CODE (PATTERN (insn)) == SET
9651 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
9652 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
9653 || (!TARGET_CPU_ZARCH
9654 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
9655 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
9657 set = PATTERN (insn);
9658 first = REGNO (SET_DEST (set));
9659 offset = const0_rtx;
9660 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9661 off = INTVAL (offset);
9663 if (GET_CODE (base) != REG || off < 0)
9665 if (REGNO (base) != STACK_POINTER_REGNUM
9666 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9675 /* On z10 the dynamic branch prediction must see the backward jump in
9676 a window of 384 bytes. If not it falls back to the static
9677 prediction. This function rearranges the loop backward branch in a
9678 way which makes the static prediction always correct. The function
9679 returns true if it added an instruction. */
9681 s390_z10_fix_long_loop_prediction (rtx insn)
9683 rtx set = single_set (insn);
9684 rtx code_label, label_ref, new_label;
9690 /* This will exclude branch on count and branch on index patterns
9691 since these are correctly statically predicted. */
9693 || SET_DEST (set) != pc_rtx
9694 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
9697 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
9698 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
9700 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
9702 code_label = XEXP (label_ref, 0);
9704 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
9705 || INSN_ADDRESSES (INSN_UID (insn)) == -1
9706 || (INSN_ADDRESSES (INSN_UID (insn))
9707 - INSN_ADDRESSES (INSN_UID (code_label)) < Z10_PREDICT_DISTANCE))
9710 for (distance = 0, cur_insn = PREV_INSN (insn);
9711 distance < Z10_PREDICT_DISTANCE - 6;
9712 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
9713 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
9716 new_label = gen_label_rtx ();
9717 uncond_jump = emit_jump_insn_after (
9718 gen_rtx_SET (VOIDmode, pc_rtx,
9719 gen_rtx_LABEL_REF (VOIDmode, code_label)),
9721 emit_label_after (new_label, uncond_jump);
9723 tmp = XEXP (SET_SRC (set), 1);
9724 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
9725 XEXP (SET_SRC (set), 2) = tmp;
9726 INSN_CODE (insn) = -1;
9728 XEXP (label_ref, 0) = new_label;
9729 JUMP_LABEL (insn) = new_label;
9730 JUMP_LABEL (uncond_jump) = code_label;
9735 /* Returns 1 if INSN reads the value of REG for purposes not related
9736 to addressing of memory, and 0 otherwise. */
9738 s390_non_addr_reg_read_p (rtx reg, rtx insn)
9740 return reg_referenced_p (reg, PATTERN (insn))
9741 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
9744 /* Starting from INSN find_cond_jump looks downwards in the insn
9745 stream for a single jump insn which is the last user of the
9746 condition code set in INSN. */
9748 find_cond_jump (rtx insn)
9750 for (; insn; insn = NEXT_INSN (insn))
9759 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
9764 /* This will be triggered by a return. */
9765 if (GET_CODE (PATTERN (insn)) != SET)
9768 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
9769 ite = SET_SRC (PATTERN (insn));
9771 if (GET_CODE (ite) != IF_THEN_ELSE)
9774 cc = XEXP (XEXP (ite, 0), 0);
9775 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
9778 if (find_reg_note (insn, REG_DEAD, cc))
9786 /* Swap the condition in COND and the operands in OP0 and OP1 so that
9787 the semantics does not change. If NULL_RTX is passed as COND the
9788 function tries to find the conditional jump starting with INSN. */
9790 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
9794 if (cond == NULL_RTX)
9796 rtx jump = find_cond_jump (NEXT_INSN (insn));
9797 jump = jump ? single_set (jump) : NULL_RTX;
9799 if (jump == NULL_RTX)
9802 cond = XEXP (XEXP (jump, 1), 0);
9807 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
9810 /* On z10, instructions of the compare-and-branch family have the
9811 property to access the register occurring as second operand with
9812 its bits complemented. If such a compare is grouped with a second
9813 instruction that accesses the same register non-complemented, and
9814 if that register's value is delivered via a bypass, then the
9815 pipeline recycles, thereby causing significant performance decline.
9816 This function locates such situations and exchanges the two
9817 operands of the compare. The function return true whenever it
9820 s390_z10_optimize_cmp (rtx insn)
9822 rtx prev_insn, next_insn;
9823 bool insn_added_p = false;
9824 rtx cond, *op0, *op1;
9826 if (GET_CODE (PATTERN (insn)) == PARALLEL)
9828 /* Handle compare and branch and branch on count
9830 rtx pattern = single_set (insn);
9833 || SET_DEST (pattern) != pc_rtx
9834 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
9837 cond = XEXP (SET_SRC (pattern), 0);
9838 op0 = &XEXP (cond, 0);
9839 op1 = &XEXP (cond, 1);
9841 else if (GET_CODE (PATTERN (insn)) == SET)
9845 /* Handle normal compare instructions. */
9846 src = SET_SRC (PATTERN (insn));
9847 dest = SET_DEST (PATTERN (insn));
9850 || !CC_REGNO_P (REGNO (dest))
9851 || GET_CODE (src) != COMPARE)
9854 /* s390_swap_cmp will try to find the conditional
9855 jump when passing NULL_RTX as condition. */
9857 op0 = &XEXP (src, 0);
9858 op1 = &XEXP (src, 1);
9863 if (!REG_P (*op0) || !REG_P (*op1))
9866 /* Swap the COMPARE arguments and its mask if there is a
9867 conflicting access in the previous insn. */
9868 prev_insn = PREV_INSN (insn);
9869 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
9870 && reg_referenced_p (*op1, PATTERN (prev_insn)))
9871 s390_swap_cmp (cond, op0, op1, insn);
9873 /* Check if there is a conflict with the next insn. If there
9874 was no conflict with the previous insn, then swap the
9875 COMPARE arguments and its mask. If we already swapped
9876 the operands, or if swapping them would cause a conflict
9877 with the previous insn, issue a NOP after the COMPARE in
9878 order to separate the two instuctions. */
9879 next_insn = NEXT_INSN (insn);
9880 if (next_insn != NULL_RTX && INSN_P (next_insn)
9881 && s390_non_addr_reg_read_p (*op1, next_insn))
9883 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
9884 && s390_non_addr_reg_read_p (*op0, prev_insn))
9886 if (REGNO (*op1) == 0)
9887 emit_insn_after (gen_nop1 (), insn);
9889 emit_insn_after (gen_nop (), insn);
9890 insn_added_p = true;
9893 s390_swap_cmp (cond, op0, op1, insn);
9895 return insn_added_p;
9898 /* Perform machine-dependent processing. */
9903 bool pool_overflow = false;
9905 /* Make sure all splits have been performed; splits after
9906 machine_dependent_reorg might confuse insn length counts. */
9907 split_all_insns_noflow ();
9909 /* Install the main literal pool and the associated base
9910 register load insns.
9912 In addition, there are two problematic situations we need
9915 - the literal pool might be > 4096 bytes in size, so that
9916 some of its elements cannot be directly accessed
9918 - a branch target might be > 64K away from the branch, so that
9919 it is not possible to use a PC-relative instruction.
9921 To fix those, we split the single literal pool into multiple
9922 pool chunks, reloading the pool base register at various
9923 points throughout the function to ensure it always points to
9924 the pool chunk the following code expects, and / or replace
9925 PC-relative branches by absolute branches.
9927 However, the two problems are interdependent: splitting the
9928 literal pool can move a branch further away from its target,
9929 causing the 64K limit to overflow, and on the other hand,
9930 replacing a PC-relative branch by an absolute branch means
9931 we need to put the branch target address into the literal
9932 pool, possibly causing it to overflow.
9934 So, we loop trying to fix up both problems until we manage
9935 to satisfy both conditions at the same time. Note that the
9936 loop is guaranteed to terminate as every pass of the loop
9937 strictly decreases the total number of PC-relative branches
9938 in the function. (This is not completely true as there
9939 might be branch-over-pool insns introduced by chunkify_start.
9940 Those never need to be split however.) */
9944 struct constant_pool *pool = NULL;
9946 /* Collect the literal pool. */
9949 pool = s390_mainpool_start ();
9951 pool_overflow = true;
9954 /* If literal pool overflowed, start to chunkify it. */
9956 pool = s390_chunkify_start ();
9958 /* Split out-of-range branches. If this has created new
9959 literal pool entries, cancel current chunk list and
9960 recompute it. zSeries machines have large branch
9961 instructions, so we never need to split a branch. */
9962 if (!TARGET_CPU_ZARCH && s390_split_branches ())
9965 s390_chunkify_cancel (pool);
9967 s390_mainpool_cancel (pool);
9972 /* If we made it up to here, both conditions are satisfied.
9973 Finish up literal pool related changes. */
9975 s390_chunkify_finish (pool);
9977 s390_mainpool_finish (pool);
9979 /* We're done splitting branches. */
9980 cfun->machine->split_branches_pending_p = false;
9984 /* Generate out-of-pool execute target insns. */
9985 if (TARGET_CPU_ZARCH)
9987 rtx insn, label, target;
9989 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9991 label = s390_execute_label (insn);
9995 gcc_assert (label != const0_rtx);
9997 target = emit_label (XEXP (label, 0));
9998 INSN_ADDRESSES_NEW (target, -1);
10000 target = emit_insn (s390_execute_target (insn));
10001 INSN_ADDRESSES_NEW (target, -1);
10005 /* Try to optimize prologue and epilogue further. */
10006 s390_optimize_prologue ();
10008 /* Walk over the insns and do some z10 specific changes. */
10009 if (s390_tune == PROCESSOR_2097_Z10)
10012 bool insn_added_p = false;
10014 /* The insn lengths and addresses have to be up to date for the
10015 following manipulations. */
10016 shorten_branches (get_insns ());
10018 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10020 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
10024 insn_added_p |= s390_z10_fix_long_loop_prediction (insn);
10026 if (GET_CODE (PATTERN (insn)) == PARALLEL
10027 || GET_CODE (PATTERN (insn)) == SET)
10028 insn_added_p |= s390_z10_optimize_cmp (insn);
10031 /* Adjust branches if we added new instructions. */
10033 shorten_branches (get_insns ());
10038 /* Initialize GCC target structure. */
10040 #undef TARGET_ASM_ALIGNED_HI_OP
10041 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10042 #undef TARGET_ASM_ALIGNED_DI_OP
10043 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10044 #undef TARGET_ASM_INTEGER
10045 #define TARGET_ASM_INTEGER s390_assemble_integer
10047 #undef TARGET_ASM_OPEN_PAREN
10048 #define TARGET_ASM_OPEN_PAREN ""
10050 #undef TARGET_ASM_CLOSE_PAREN
10051 #define TARGET_ASM_CLOSE_PAREN ""
10053 #undef TARGET_DEFAULT_TARGET_FLAGS
10054 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
10055 #undef TARGET_HANDLE_OPTION
10056 #define TARGET_HANDLE_OPTION s390_handle_option
10058 #undef TARGET_ENCODE_SECTION_INFO
10059 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10062 #undef TARGET_HAVE_TLS
10063 #define TARGET_HAVE_TLS true
10065 #undef TARGET_CANNOT_FORCE_CONST_MEM
10066 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10068 #undef TARGET_DELEGITIMIZE_ADDRESS
10069 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10071 #undef TARGET_LEGITIMIZE_ADDRESS
10072 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10074 #undef TARGET_RETURN_IN_MEMORY
10075 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10077 #undef TARGET_INIT_BUILTINS
10078 #define TARGET_INIT_BUILTINS s390_init_builtins
10079 #undef TARGET_EXPAND_BUILTIN
10080 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10082 #undef TARGET_ASM_OUTPUT_MI_THUNK
10083 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10084 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10085 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10087 #undef TARGET_SCHED_ADJUST_PRIORITY
10088 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10089 #undef TARGET_SCHED_ISSUE_RATE
10090 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10091 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10092 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10094 #undef TARGET_CANNOT_COPY_INSN_P
10095 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10096 #undef TARGET_RTX_COSTS
10097 #define TARGET_RTX_COSTS s390_rtx_costs
10098 #undef TARGET_ADDRESS_COST
10099 #define TARGET_ADDRESS_COST s390_address_cost
10101 #undef TARGET_MACHINE_DEPENDENT_REORG
10102 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10104 #undef TARGET_VALID_POINTER_MODE
10105 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10107 #undef TARGET_BUILD_BUILTIN_VA_LIST
10108 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10109 #undef TARGET_EXPAND_BUILTIN_VA_START
10110 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10111 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10112 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10114 #undef TARGET_PROMOTE_FUNCTION_MODE
10115 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10116 #undef TARGET_PASS_BY_REFERENCE
10117 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10119 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10120 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10122 #undef TARGET_FIXED_CONDITION_CODE_REGS
10123 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10125 #undef TARGET_CC_MODES_COMPATIBLE
10126 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10128 #undef TARGET_INVALID_WITHIN_DOLOOP
10129 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10132 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10133 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10136 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10137 #undef TARGET_MANGLE_TYPE
10138 #define TARGET_MANGLE_TYPE s390_mangle_type
10141 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10142 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10144 #undef TARGET_SECONDARY_RELOAD
10145 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10147 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10148 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10150 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10151 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10153 #undef TARGET_LEGITIMATE_ADDRESS_P
10154 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10156 #undef TARGET_CAN_ELIMINATE
10157 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10159 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10160 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10161 #undef TARGET_TRAMPOLINE_INIT
10162 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10164 struct gcc_target targetm = TARGET_INITIALIZER;
10166 #include "gt-s390.h"