1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
26 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
45 #include "basic-block.h"
46 #include "integrate.h"
49 #include "target-def.h"
51 #include "langhooks.h"
53 #include "tree-gimple.h"
56 /* Define the specific costs for a given cpu. */
58 struct processor_costs
61 const int m; /* cost of an M instruction. */
62 const int mghi; /* cost of an MGHI instruction. */
63 const int mh; /* cost of an MH instruction. */
64 const int mhi; /* cost of an MHI instruction. */
65 const int ml; /* cost of an ML instruction. */
66 const int mr; /* cost of an MR instruction. */
67 const int ms; /* cost of an MS instruction. */
68 const int msg; /* cost of an MSG instruction. */
69 const int msgf; /* cost of an MSGF instruction. */
70 const int msgfr; /* cost of an MSGFR instruction. */
71 const int msgr; /* cost of an MSGR instruction. */
72 const int msr; /* cost of an MSR instruction. */
73 const int mult_df; /* cost of multiplication in DFmode. */
76 const int sqxbr; /* cost of square root in TFmode. */
77 const int sqdbr; /* cost of square root in DFmode. */
78 const int sqebr; /* cost of square root in SFmode. */
79 /* multiply and add */
80 const int madbr; /* cost of multiply and add in DFmode. */
81 const int maebr; /* cost of multiply and add in SFmode. */
96 const struct processor_costs *s390_cost;
99 struct processor_costs z900_cost =
101 COSTS_N_INSNS (5), /* M */
102 COSTS_N_INSNS (10), /* MGHI */
103 COSTS_N_INSNS (5), /* MH */
104 COSTS_N_INSNS (4), /* MHI */
105 COSTS_N_INSNS (5), /* ML */
106 COSTS_N_INSNS (5), /* MR */
107 COSTS_N_INSNS (4), /* MS */
108 COSTS_N_INSNS (15), /* MSG */
109 COSTS_N_INSNS (7), /* MSGF */
110 COSTS_N_INSNS (7), /* MSGFR */
111 COSTS_N_INSNS (10), /* MSGR */
112 COSTS_N_INSNS (4), /* MSR */
113 COSTS_N_INSNS (7), /* multiplication in DFmode */
114 COSTS_N_INSNS (13), /* MXBR */
115 COSTS_N_INSNS (136), /* SQXBR */
116 COSTS_N_INSNS (44), /* SQDBR */
117 COSTS_N_INSNS (35), /* SQEBR */
118 COSTS_N_INSNS (18), /* MADBR */
119 COSTS_N_INSNS (13), /* MAEBR */
120 COSTS_N_INSNS (134), /* DXBR */
121 COSTS_N_INSNS (135), /* DXR */
122 COSTS_N_INSNS (30), /* DDBR */
123 COSTS_N_INSNS (30), /* DDR */
124 COSTS_N_INSNS (27), /* DEBR */
125 COSTS_N_INSNS (26), /* DER */
126 COSTS_N_INSNS (220), /* DLGR */
127 COSTS_N_INSNS (34), /* DLR */
128 COSTS_N_INSNS (34), /* DR */
129 COSTS_N_INSNS (32), /* DSGFR */
130 COSTS_N_INSNS (32), /* DSGR */
134 struct processor_costs z990_cost =
136 COSTS_N_INSNS (4), /* M */
137 COSTS_N_INSNS (2), /* MGHI */
138 COSTS_N_INSNS (2), /* MH */
139 COSTS_N_INSNS (2), /* MHI */
140 COSTS_N_INSNS (4), /* ML */
141 COSTS_N_INSNS (4), /* MR */
142 COSTS_N_INSNS (5), /* MS */
143 COSTS_N_INSNS (6), /* MSG */
144 COSTS_N_INSNS (4), /* MSGF */
145 COSTS_N_INSNS (4), /* MSGFR */
146 COSTS_N_INSNS (4), /* MSGR */
147 COSTS_N_INSNS (4), /* MSR */
148 COSTS_N_INSNS (1), /* multiplication in DFmode */
149 COSTS_N_INSNS (28), /* MXBR */
150 COSTS_N_INSNS (130), /* SQXBR */
151 COSTS_N_INSNS (66), /* SQDBR */
152 COSTS_N_INSNS (38), /* SQEBR */
153 COSTS_N_INSNS (1), /* MADBR */
154 COSTS_N_INSNS (1), /* MAEBR */
155 COSTS_N_INSNS (60), /* DXBR */
156 COSTS_N_INSNS (72), /* DXR */
157 COSTS_N_INSNS (40), /* DDBR */
158 COSTS_N_INSNS (44), /* DDR */
159 COSTS_N_INSNS (26), /* DDBR */
160 COSTS_N_INSNS (28), /* DER */
161 COSTS_N_INSNS (176), /* DLGR */
162 COSTS_N_INSNS (31), /* DLR */
163 COSTS_N_INSNS (31), /* DR */
164 COSTS_N_INSNS (31), /* DSGFR */
165 COSTS_N_INSNS (31), /* DSGR */
169 struct processor_costs z9_109_cost =
171 COSTS_N_INSNS (4), /* M */
172 COSTS_N_INSNS (2), /* MGHI */
173 COSTS_N_INSNS (2), /* MH */
174 COSTS_N_INSNS (2), /* MHI */
175 COSTS_N_INSNS (4), /* ML */
176 COSTS_N_INSNS (4), /* MR */
177 COSTS_N_INSNS (5), /* MS */
178 COSTS_N_INSNS (6), /* MSG */
179 COSTS_N_INSNS (4), /* MSGF */
180 COSTS_N_INSNS (4), /* MSGFR */
181 COSTS_N_INSNS (4), /* MSGR */
182 COSTS_N_INSNS (4), /* MSR */
183 COSTS_N_INSNS (1), /* multiplication in DFmode */
184 COSTS_N_INSNS (28), /* MXBR */
185 COSTS_N_INSNS (130), /* SQXBR */
186 COSTS_N_INSNS (66), /* SQDBR */
187 COSTS_N_INSNS (38), /* SQEBR */
188 COSTS_N_INSNS (1), /* MADBR */
189 COSTS_N_INSNS (1), /* MAEBR */
190 COSTS_N_INSNS (60), /* DXBR */
191 COSTS_N_INSNS (72), /* DXR */
192 COSTS_N_INSNS (40), /* DDBR */
193 COSTS_N_INSNS (37), /* DDR */
194 COSTS_N_INSNS (26), /* DDBR */
195 COSTS_N_INSNS (28), /* DER */
196 COSTS_N_INSNS (30), /* DLGR */
197 COSTS_N_INSNS (23), /* DLR */
198 COSTS_N_INSNS (23), /* DR */
199 COSTS_N_INSNS (24), /* DSGFR */
200 COSTS_N_INSNS (24), /* DSGR */
203 extern int reload_completed;
205 /* Save information from a "cmpxx" operation until the branch or scc is
207 rtx s390_compare_op0, s390_compare_op1;
209 /* Save the result of a compare_and_swap until the branch or scc is
211 rtx s390_compare_emitted = NULL_RTX;
213 /* Structure used to hold the components of a S/390 memory
214 address. A legitimate address on S/390 is of the general
216 base + index + displacement
217 where any of the components is optional.
219 base and index are registers of the class ADDR_REGS,
220 displacement is an unsigned 12-bit immediate constant. */
231 /* Which cpu are we tuning for. */
232 enum processor_type s390_tune = PROCESSOR_max;
233 enum processor_flags s390_tune_flags;
234 /* Which instruction set architecture to use. */
235 enum processor_type s390_arch;
236 enum processor_flags s390_arch_flags;
238 HOST_WIDE_INT s390_warn_framesize = 0;
239 HOST_WIDE_INT s390_stack_size = 0;
240 HOST_WIDE_INT s390_stack_guard = 0;
242 /* The following structure is embedded in the machine
243 specific part of struct function. */
245 struct s390_frame_layout GTY (())
247 /* Offset within stack frame. */
248 HOST_WIDE_INT gprs_offset;
249 HOST_WIDE_INT f0_offset;
250 HOST_WIDE_INT f4_offset;
251 HOST_WIDE_INT f8_offset;
252 HOST_WIDE_INT backchain_offset;
254 /* Number of first and last gpr where slots in the register
255 save area are reserved for. */
256 int first_save_gpr_slot;
257 int last_save_gpr_slot;
259 /* Number of first and last gpr to be saved, restored. */
261 int first_restore_gpr;
263 int last_restore_gpr;
265 /* Bits standing for floating point registers. Set, if the
266 respective register has to be saved. Starting with reg 16 (f0)
267 at the rightmost bit.
268 Bit 15 - 8 7 6 5 4 3 2 1 0
269 fpr 15 - 8 7 5 3 1 6 4 2 0
270 reg 31 - 24 23 22 21 20 19 18 17 16 */
271 unsigned int fpr_bitmap;
273 /* Number of floating point registers f8-f15 which must be saved. */
276 /* Set if return address needs to be saved.
277 This flag is set by s390_return_addr_rtx if it could not use
278 the initial value of r14 and therefore depends on r14 saved
280 bool save_return_addr_p;
282 /* Size of stack frame. */
283 HOST_WIDE_INT frame_size;
286 /* Define the structure for the machine field in struct function. */
288 struct machine_function GTY(())
290 struct s390_frame_layout frame_layout;
292 /* Literal pool base register. */
295 /* True if we may need to perform branch splitting. */
296 bool split_branches_pending_p;
298 /* True during final stage of literal pool processing. */
299 bool decomposed_literal_pool_addresses_ok_p;
301 /* Some local-dynamic TLS symbol name. */
302 const char *some_ld_name;
304 bool has_landing_pad_p;
307 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
309 #define cfun_frame_layout (cfun->machine->frame_layout)
310 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
311 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
312 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
313 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
315 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
318 /* Number of GPRs and FPRs used for argument passing. */
319 #define GP_ARG_NUM_REG 5
320 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
322 /* A couple of shortcuts. */
323 #define CONST_OK_FOR_J(x) \
324 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
325 #define CONST_OK_FOR_K(x) \
326 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
327 #define CONST_OK_FOR_Os(x) \
328 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
329 #define CONST_OK_FOR_Op(x) \
330 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
331 #define CONST_OK_FOR_On(x) \
332 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
334 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
337 s390_set_has_landing_pad_p (bool value)
339 cfun->machine->has_landing_pad_p = value;
342 /* If two condition code modes are compatible, return a condition code
343 mode which is compatible with both. Otherwise, return
346 static enum machine_mode
347 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
355 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
356 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
377 /* Return true if SET either doesn't set the CC register, or else
378 the source and destination have matching CC modes and that
379 CC mode is at least as constrained as REQ_MODE. */
382 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
384 enum machine_mode set_mode;
386 gcc_assert (GET_CODE (set) == SET);
388 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
391 set_mode = GET_MODE (SET_DEST (set));
405 if (req_mode != set_mode)
410 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
411 && req_mode != CCSRmode && req_mode != CCURmode)
417 if (req_mode != CCAmode)
425 return (GET_MODE (SET_SRC (set)) == set_mode);
428 /* Return true if every SET in INSN that sets the CC register
429 has source and destination with matching CC modes and that
430 CC mode is at least as constrained as REQ_MODE.
431 If REQ_MODE is VOIDmode, always return false. */
434 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
438 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
439 if (req_mode == VOIDmode)
442 if (GET_CODE (PATTERN (insn)) == SET)
443 return s390_match_ccmode_set (PATTERN (insn), req_mode);
445 if (GET_CODE (PATTERN (insn)) == PARALLEL)
446 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
448 rtx set = XVECEXP (PATTERN (insn), 0, i);
449 if (GET_CODE (set) == SET)
450 if (!s390_match_ccmode_set (set, req_mode))
457 /* If a test-under-mask instruction can be used to implement
458 (compare (and ... OP1) OP2), return the CC mode required
459 to do that. Otherwise, return VOIDmode.
460 MIXED is true if the instruction can distinguish between
461 CC1 and CC2 for mixed selected bits (TMxx), it is false
462 if the instruction cannot (TM). */
465 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
469 /* ??? Fixme: should work on CONST_DOUBLE as well. */
470 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
473 /* Selected bits all zero: CC0.
474 e.g.: int a; if ((a & (16 + 128)) == 0) */
475 if (INTVAL (op2) == 0)
478 /* Selected bits all one: CC3.
479 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
480 if (INTVAL (op2) == INTVAL (op1))
483 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
485 if ((a & (16 + 128)) == 16) -> CCT1
486 if ((a & (16 + 128)) == 128) -> CCT2 */
489 bit1 = exact_log2 (INTVAL (op2));
490 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
491 if (bit0 != -1 && bit1 != -1)
492 return bit0 > bit1 ? CCT1mode : CCT2mode;
498 /* Given a comparison code OP (EQ, NE, etc.) and the operands
499 OP0 and OP1 of a COMPARE, return the mode to be used for the
503 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
509 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
510 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
512 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
513 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
515 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
516 || GET_CODE (op1) == NEG)
517 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
520 if (GET_CODE (op0) == AND)
522 /* Check whether we can potentially do it via TM. */
523 enum machine_mode ccmode;
524 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
525 if (ccmode != VOIDmode)
527 /* Relax CCTmode to CCZmode to allow fall-back to AND
528 if that turns out to be beneficial. */
529 return ccmode == CCTmode ? CCZmode : ccmode;
533 if (register_operand (op0, HImode)
534 && GET_CODE (op1) == CONST_INT
535 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
537 if (register_operand (op0, QImode)
538 && GET_CODE (op1) == CONST_INT
539 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
548 /* The only overflow condition of NEG and ABS happens when
549 -INT_MAX is used as parameter, which stays negative. So
550 we have an overflow from a positive value to a negative.
551 Using CCAP mode the resulting cc can be used for comparisons. */
552 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
553 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
556 /* If constants are involved in an add instruction it is possible to use
557 the resulting cc for comparisons with zero. Knowing the sign of the
558 constant the overflow behavior gets predictable. e.g.:
559 int a, b; if ((b = a + c) > 0)
560 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
561 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
562 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
564 if (INTVAL (XEXP((op0), 1)) < 0)
578 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
579 && GET_CODE (op1) != CONST_INT)
585 if (GET_CODE (op0) == PLUS
586 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
589 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
590 && GET_CODE (op1) != CONST_INT)
596 if (GET_CODE (op0) == MINUS
597 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
600 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
601 && GET_CODE (op1) != CONST_INT)
610 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
611 that we can implement more efficiently. */
614 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
616 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
617 if ((*code == EQ || *code == NE)
618 && *op1 == const0_rtx
619 && GET_CODE (*op0) == ZERO_EXTRACT
620 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
621 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
622 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
624 rtx inner = XEXP (*op0, 0);
625 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
626 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
627 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
629 if (len > 0 && len < modesize
630 && pos >= 0 && pos + len <= modesize
631 && modesize <= HOST_BITS_PER_WIDE_INT)
633 unsigned HOST_WIDE_INT block;
634 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
635 block <<= modesize - pos - len;
637 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
638 gen_int_mode (block, GET_MODE (inner)));
642 /* Narrow AND of memory against immediate to enable TM. */
643 if ((*code == EQ || *code == NE)
644 && *op1 == const0_rtx
645 && GET_CODE (*op0) == AND
646 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
647 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
649 rtx inner = XEXP (*op0, 0);
650 rtx mask = XEXP (*op0, 1);
652 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
653 if (GET_CODE (inner) == SUBREG
654 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
655 && (GET_MODE_SIZE (GET_MODE (inner))
656 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
658 & GET_MODE_MASK (GET_MODE (inner))
659 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
661 inner = SUBREG_REG (inner);
663 /* Do not change volatile MEMs. */
664 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
666 int part = s390_single_part (XEXP (*op0, 1),
667 GET_MODE (inner), QImode, 0);
670 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
671 inner = adjust_address_nv (inner, QImode, part);
672 *op0 = gen_rtx_AND (QImode, inner, mask);
677 /* Narrow comparisons against 0xffff to HImode if possible. */
678 if ((*code == EQ || *code == NE)
679 && GET_CODE (*op1) == CONST_INT
680 && INTVAL (*op1) == 0xffff
681 && SCALAR_INT_MODE_P (GET_MODE (*op0))
682 && (nonzero_bits (*op0, GET_MODE (*op0))
683 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
685 *op0 = gen_lowpart (HImode, *op0);
690 /* Remove redundant UNSPEC_CMPINT conversions if possible. */
691 if (GET_CODE (*op0) == UNSPEC
692 && XINT (*op0, 1) == UNSPEC_CMPINT
693 && XVECLEN (*op0, 0) == 1
694 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
695 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
696 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
697 && *op1 == const0_rtx)
699 enum rtx_code new_code = UNKNOWN;
702 case EQ: new_code = EQ; break;
703 case NE: new_code = NE; break;
704 case LT: new_code = GTU; break;
705 case GT: new_code = LTU; break;
706 case LE: new_code = GEU; break;
707 case GE: new_code = LEU; break;
711 if (new_code != UNKNOWN)
713 *op0 = XVECEXP (*op0, 0, 0);
718 /* Simplify cascaded EQ, NE with const0_rtx. */
719 if ((*code == NE || *code == EQ)
720 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
721 && GET_MODE (*op0) == SImode
722 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
723 && REG_P (XEXP (*op0, 0))
724 && XEXP (*op0, 1) == const0_rtx
725 && *op1 == const0_rtx)
727 if ((*code == EQ && GET_CODE (*op0) == NE)
728 || (*code == NE && GET_CODE (*op0) == EQ))
732 *op0 = XEXP (*op0, 0);
735 /* Prefer register over memory as first operand. */
736 if (MEM_P (*op0) && REG_P (*op1))
738 rtx tem = *op0; *op0 = *op1; *op1 = tem;
739 *code = swap_condition (*code);
743 /* Emit a compare instruction suitable to implement the comparison
744 OP0 CODE OP1. Return the correct condition RTL to be placed in
745 the IF_THEN_ELSE of the conditional branch testing the result. */
748 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
750 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
753 /* Do not output a redundant compare instruction if a compare_and_swap
754 pattern already computed the result and the machine modes are compatible. */
755 if (s390_compare_emitted
756 && (s390_cc_modes_compatible (GET_MODE (s390_compare_emitted), mode)
757 == GET_MODE (s390_compare_emitted)))
758 ret = gen_rtx_fmt_ee (code, VOIDmode, s390_compare_emitted, const0_rtx);
761 rtx cc = gen_rtx_REG (mode, CC_REGNUM);
763 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
764 ret = gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
766 s390_compare_emitted = NULL_RTX;
770 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
771 unconditional jump, else a conditional jump under condition COND. */
774 s390_emit_jump (rtx target, rtx cond)
778 target = gen_rtx_LABEL_REF (VOIDmode, target);
780 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
782 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
783 emit_jump_insn (insn);
786 /* Return branch condition mask to implement a branch
787 specified by CODE. Return -1 for invalid comparisons. */
790 s390_branch_condition_mask (rtx code)
792 const int CC0 = 1 << 3;
793 const int CC1 = 1 << 2;
794 const int CC2 = 1 << 1;
795 const int CC3 = 1 << 0;
797 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
798 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
799 gcc_assert (XEXP (code, 1) == const0_rtx);
801 switch (GET_MODE (XEXP (code, 0)))
805 switch (GET_CODE (code))
808 case NE: return CC1 | CC2 | CC3;
814 switch (GET_CODE (code))
817 case NE: return CC0 | CC2 | CC3;
823 switch (GET_CODE (code))
826 case NE: return CC0 | CC1 | CC3;
832 switch (GET_CODE (code))
835 case NE: return CC0 | CC1 | CC2;
841 switch (GET_CODE (code))
843 case EQ: return CC0 | CC2;
844 case NE: return CC1 | CC3;
850 switch (GET_CODE (code))
852 case LTU: return CC2 | CC3; /* carry */
853 case GEU: return CC0 | CC1; /* no carry */
859 switch (GET_CODE (code))
861 case GTU: return CC0 | CC1; /* borrow */
862 case LEU: return CC2 | CC3; /* no borrow */
868 switch (GET_CODE (code))
870 case EQ: return CC0 | CC2;
871 case NE: return CC1 | CC3;
872 case LTU: return CC1;
873 case GTU: return CC3;
874 case LEU: return CC1 | CC2;
875 case GEU: return CC2 | CC3;
880 switch (GET_CODE (code))
883 case NE: return CC1 | CC2 | CC3;
884 case LTU: return CC1;
885 case GTU: return CC2;
886 case LEU: return CC0 | CC1;
887 case GEU: return CC0 | CC2;
893 switch (GET_CODE (code))
896 case NE: return CC2 | CC1 | CC3;
897 case LTU: return CC2;
898 case GTU: return CC1;
899 case LEU: return CC0 | CC2;
900 case GEU: return CC0 | CC1;
906 switch (GET_CODE (code))
909 case NE: return CC1 | CC2 | CC3;
910 case LT: return CC1 | CC3;
912 case LE: return CC0 | CC1 | CC3;
913 case GE: return CC0 | CC2;
919 switch (GET_CODE (code))
922 case NE: return CC1 | CC2 | CC3;
924 case GT: return CC2 | CC3;
925 case LE: return CC0 | CC1;
926 case GE: return CC0 | CC2 | CC3;
932 switch (GET_CODE (code))
935 case NE: return CC1 | CC2 | CC3;
938 case LE: return CC0 | CC1;
939 case GE: return CC0 | CC2;
940 case UNORDERED: return CC3;
941 case ORDERED: return CC0 | CC1 | CC2;
942 case UNEQ: return CC0 | CC3;
943 case UNLT: return CC1 | CC3;
944 case UNGT: return CC2 | CC3;
945 case UNLE: return CC0 | CC1 | CC3;
946 case UNGE: return CC0 | CC2 | CC3;
947 case LTGT: return CC1 | CC2;
953 switch (GET_CODE (code))
956 case NE: return CC2 | CC1 | CC3;
959 case LE: return CC0 | CC2;
960 case GE: return CC0 | CC1;
961 case UNORDERED: return CC3;
962 case ORDERED: return CC0 | CC2 | CC1;
963 case UNEQ: return CC0 | CC3;
964 case UNLT: return CC2 | CC3;
965 case UNGT: return CC1 | CC3;
966 case UNLE: return CC0 | CC2 | CC3;
967 case UNGE: return CC0 | CC1 | CC3;
968 case LTGT: return CC2 | CC1;
978 /* If INV is false, return assembler mnemonic string to implement
979 a branch specified by CODE. If INV is true, return mnemonic
980 for the corresponding inverted branch. */
983 s390_branch_condition_mnemonic (rtx code, int inv)
985 static const char *const mnemonic[16] =
987 NULL, "o", "h", "nle",
988 "l", "nhe", "lh", "ne",
989 "e", "nlh", "he", "nl",
990 "le", "nh", "no", NULL
993 int mask = s390_branch_condition_mask (code);
994 gcc_assert (mask >= 0);
999 gcc_assert (mask >= 1 && mask <= 14);
1001 return mnemonic[mask];
1004 /* Return the part of op which has a value different from def.
1005 The size of the part is determined by mode.
1006 Use this function only if you already know that op really
1007 contains such a part. */
1009 unsigned HOST_WIDE_INT
1010 s390_extract_part (rtx op, enum machine_mode mode, int def)
1012 unsigned HOST_WIDE_INT value = 0;
1013 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1014 int part_bits = GET_MODE_BITSIZE (mode);
1015 unsigned HOST_WIDE_INT part_mask
1016 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1019 for (i = 0; i < max_parts; i++)
1022 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1024 value >>= part_bits;
1026 if ((value & part_mask) != (def & part_mask))
1027 return value & part_mask;
1033 /* If OP is an integer constant of mode MODE with exactly one
1034 part of mode PART_MODE unequal to DEF, return the number of that
1035 part. Otherwise, return -1. */
1038 s390_single_part (rtx op,
1039 enum machine_mode mode,
1040 enum machine_mode part_mode,
1043 unsigned HOST_WIDE_INT value = 0;
1044 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1045 unsigned HOST_WIDE_INT part_mask
1046 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1049 if (GET_CODE (op) != CONST_INT)
1052 for (i = 0; i < n_parts; i++)
1055 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1057 value >>= GET_MODE_BITSIZE (part_mode);
1059 if ((value & part_mask) != (def & part_mask))
1067 return part == -1 ? -1 : n_parts - 1 - part;
1070 /* Check whether we can (and want to) split a double-word
1071 move in mode MODE from SRC to DST into two single-word
1072 moves, moving the subword FIRST_SUBWORD first. */
1075 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1077 /* Floating point registers cannot be split. */
1078 if (FP_REG_P (src) || FP_REG_P (dst))
1081 /* We don't need to split if operands are directly accessible. */
1082 if (s_operand (src, mode) || s_operand (dst, mode))
1085 /* Non-offsettable memory references cannot be split. */
1086 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1087 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1090 /* Moving the first subword must not clobber a register
1091 needed to move the second subword. */
1092 if (register_operand (dst, mode))
1094 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1095 if (reg_overlap_mentioned_p (subreg, src))
1102 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1103 and [MEM2, MEM2 + SIZE] do overlap and false
1107 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1109 rtx addr1, addr2, addr_delta;
1110 HOST_WIDE_INT delta;
1112 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1118 addr1 = XEXP (mem1, 0);
1119 addr2 = XEXP (mem2, 0);
1121 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1123 /* This overlapping check is used by peepholes merging memory block operations.
1124 Overlapping operations would otherwise be recognized by the S/390 hardware
1125 and would fall back to a slower implementation. Allowing overlapping
1126 operations would lead to slow code but not to wrong code. Therefore we are
1127 somewhat optimistic if we cannot prove that the memory blocks are
1129 That's why we return false here although this may accept operations on
1130 overlapping memory areas. */
1131 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1134 delta = INTVAL (addr_delta);
1137 || (delta > 0 && delta < size)
1138 || (delta < 0 && -delta < size))
1144 /* Check whether the address of memory reference MEM2 equals exactly
1145 the address of memory reference MEM1 plus DELTA. Return true if
1146 we can prove this to be the case, false otherwise. */
1149 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1151 rtx addr1, addr2, addr_delta;
1153 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1156 addr1 = XEXP (mem1, 0);
1157 addr2 = XEXP (mem2, 0);
1159 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1160 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1166 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1169 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1172 enum machine_mode wmode = mode;
1173 rtx dst = operands[0];
1174 rtx src1 = operands[1];
1175 rtx src2 = operands[2];
1178 /* If we cannot handle the operation directly, use a temp register. */
1179 if (!s390_logical_operator_ok_p (operands))
1180 dst = gen_reg_rtx (mode);
1182 /* QImode and HImode patterns make sense only if we have a destination
1183 in memory. Otherwise perform the operation in SImode. */
1184 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1187 /* Widen operands if required. */
1190 if (GET_CODE (dst) == SUBREG
1191 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1193 else if (REG_P (dst))
1194 dst = gen_rtx_SUBREG (wmode, dst, 0);
1196 dst = gen_reg_rtx (wmode);
1198 if (GET_CODE (src1) == SUBREG
1199 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1201 else if (GET_MODE (src1) != VOIDmode)
1202 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1204 if (GET_CODE (src2) == SUBREG
1205 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1207 else if (GET_MODE (src2) != VOIDmode)
1208 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1211 /* Emit the instruction. */
1212 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1213 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1214 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1216 /* Fix up the destination if needed. */
1217 if (dst != operands[0])
1218 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1221 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1224 s390_logical_operator_ok_p (rtx *operands)
1226 /* If the destination operand is in memory, it needs to coincide
1227 with one of the source operands. After reload, it has to be
1228 the first source operand. */
1229 if (GET_CODE (operands[0]) == MEM)
1230 return rtx_equal_p (operands[0], operands[1])
1231 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1236 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1237 operand IMMOP to switch from SS to SI type instructions. */
1240 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1242 int def = code == AND ? -1 : 0;
1246 gcc_assert (GET_CODE (*memop) == MEM);
1247 gcc_assert (!MEM_VOLATILE_P (*memop));
1249 mask = s390_extract_part (*immop, QImode, def);
1250 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1251 gcc_assert (part >= 0);
1253 *memop = adjust_address (*memop, QImode, part);
1254 *immop = gen_int_mode (mask, QImode);
1258 /* How to allocate a 'struct machine_function'. */
1260 static struct machine_function *
1261 s390_init_machine_status (void)
1263 return ggc_alloc_cleared (sizeof (struct machine_function));
1266 /* Change optimizations to be performed, depending on the
1269 LEVEL is the optimization level specified; 2 if `-O2' is
1270 specified, 1 if `-O' is specified, and 0 if neither is specified.
1272 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1275 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1277 /* ??? There are apparently still problems with -fcaller-saves. */
1278 flag_caller_saves = 0;
1280 /* By default, always emit DWARF-2 unwind info. This allows debugging
1281 without maintaining a stack frame back-chain. */
1282 flag_asynchronous_unwind_tables = 1;
1284 /* Use MVCLE instructions to decrease code size if requested. */
1286 target_flags |= MASK_MVCLE;
1289 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1290 to the associated processor_type and processor_flags if so. */
1293 s390_handle_arch_option (const char *arg,
1294 enum processor_type *type,
1295 enum processor_flags *flags)
1299 const char *const name; /* processor name or nickname. */
1300 const enum processor_type processor;
1301 const enum processor_flags flags;
1303 const processor_alias_table[] =
1305 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1306 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1307 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1308 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1309 | PF_LONG_DISPLACEMENT},
1310 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1311 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1315 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1316 if (strcmp (arg, processor_alias_table[i].name) == 0)
1318 *type = processor_alias_table[i].processor;
1319 *flags = processor_alias_table[i].flags;
1325 /* Implement TARGET_HANDLE_OPTION. */
1328 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1333 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1335 case OPT_mstack_guard_:
1336 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1338 if (exact_log2 (s390_stack_guard) == -1)
1339 error ("stack guard value must be an exact power of 2");
1342 case OPT_mstack_size_:
1343 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1345 if (exact_log2 (s390_stack_size) == -1)
1346 error ("stack size must be an exact power of 2");
1350 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1352 case OPT_mwarn_framesize_:
1353 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1361 override_options (void)
1363 /* Set up function hooks. */
1364 init_machine_status = s390_init_machine_status;
1366 /* Architecture mode defaults according to ABI. */
1367 if (!(target_flags_explicit & MASK_ZARCH))
1370 target_flags |= MASK_ZARCH;
1372 target_flags &= ~MASK_ZARCH;
1375 /* Determine processor architectural level. */
1376 if (!s390_arch_string)
1378 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1379 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1382 /* Determine processor to tune for. */
1383 if (s390_tune == PROCESSOR_max)
1385 s390_tune = s390_arch;
1386 s390_tune_flags = s390_arch_flags;
1389 /* Sanity checks. */
1390 if (TARGET_ZARCH && !(s390_arch_flags & PF_ZARCH))
1391 error ("z/Architecture mode not supported on %s", s390_arch_string);
1392 if (TARGET_64BIT && !TARGET_ZARCH)
1393 error ("64-bit ABI not supported in ESA/390 mode");
1395 /* Set processor cost function. */
1396 if (s390_tune == PROCESSOR_2094_Z9_109)
1397 s390_cost = &z9_109_cost;
1398 else if (s390_tune == PROCESSOR_2084_Z990)
1399 s390_cost = &z990_cost;
1401 s390_cost = &z900_cost;
1403 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1404 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1407 if (s390_stack_size)
1409 if (!s390_stack_guard)
1410 error ("-mstack-size implies use of -mstack-guard");
1411 else if (s390_stack_guard >= s390_stack_size)
1412 error ("stack size must be greater than the stack guard value");
1413 else if (s390_stack_size > 1 << 16)
1414 error ("stack size must not be greater than 64k");
1416 else if (s390_stack_guard)
1417 error ("-mstack-guard implies use of -mstack-size");
1419 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1420 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1421 target_flags |= MASK_LONG_DOUBLE_128;
1425 /* Map for smallest class containing reg regno. */
1427 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1428 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1429 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1430 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1431 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1432 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1433 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1434 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1435 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1436 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1437 ACCESS_REGS, ACCESS_REGS
1440 /* Return attribute type of insn. */
1442 static enum attr_type
1443 s390_safe_attr_type (rtx insn)
1445 if (recog_memoized (insn) >= 0)
1446 return get_attr_type (insn);
1451 /* Return true if DISP is a valid short displacement. */
1454 s390_short_displacement (rtx disp)
1456 /* No displacement is OK. */
1460 /* Integer displacement in range. */
1461 if (GET_CODE (disp) == CONST_INT)
1462 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1464 /* GOT offset is not OK, the GOT can be large. */
1465 if (GET_CODE (disp) == CONST
1466 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1467 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1468 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1471 /* All other symbolic constants are literal pool references,
1472 which are OK as the literal pool must be small. */
1473 if (GET_CODE (disp) == CONST)
1479 /* Decompose a RTL expression ADDR for a memory address into
1480 its components, returned in OUT.
1482 Returns false if ADDR is not a valid memory address, true
1483 otherwise. If OUT is NULL, don't return the components,
1484 but check for validity only.
1486 Note: Only addresses in canonical form are recognized.
1487 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1488 canonical form so that they will be recognized. */
1491 s390_decompose_address (rtx addr, struct s390_address *out)
1493 HOST_WIDE_INT offset = 0;
1494 rtx base = NULL_RTX;
1495 rtx indx = NULL_RTX;
1496 rtx disp = NULL_RTX;
1498 bool pointer = false;
1499 bool base_ptr = false;
1500 bool indx_ptr = false;
1501 bool literal_pool = false;
1503 /* We may need to substitute the literal pool base register into the address
1504 below. However, at this point we do not know which register is going to
1505 be used as base, so we substitute the arg pointer register. This is going
1506 to be treated as holding a pointer below -- it shouldn't be used for any
1508 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1510 /* Decompose address into base + index + displacement. */
1512 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1515 else if (GET_CODE (addr) == PLUS)
1517 rtx op0 = XEXP (addr, 0);
1518 rtx op1 = XEXP (addr, 1);
1519 enum rtx_code code0 = GET_CODE (op0);
1520 enum rtx_code code1 = GET_CODE (op1);
1522 if (code0 == REG || code0 == UNSPEC)
1524 if (code1 == REG || code1 == UNSPEC)
1526 indx = op0; /* index + base */
1532 base = op0; /* base + displacement */
1537 else if (code0 == PLUS)
1539 indx = XEXP (op0, 0); /* index + base + disp */
1540 base = XEXP (op0, 1);
1551 disp = addr; /* displacement */
1553 /* Extract integer part of displacement. */
1557 if (GET_CODE (disp) == CONST_INT)
1559 offset = INTVAL (disp);
1562 else if (GET_CODE (disp) == CONST
1563 && GET_CODE (XEXP (disp, 0)) == PLUS
1564 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1566 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1567 disp = XEXP (XEXP (disp, 0), 0);
1571 /* Strip off CONST here to avoid special case tests later. */
1572 if (disp && GET_CODE (disp) == CONST)
1573 disp = XEXP (disp, 0);
1575 /* We can convert literal pool addresses to
1576 displacements by basing them off the base register. */
1577 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1579 /* Either base or index must be free to hold the base register. */
1581 base = fake_pool_base, literal_pool = true;
1583 indx = fake_pool_base, literal_pool = true;
1587 /* Mark up the displacement. */
1588 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1589 UNSPEC_LTREL_OFFSET);
1592 /* Validate base register. */
1595 if (GET_CODE (base) == UNSPEC)
1596 switch (XINT (base, 1))
1600 disp = gen_rtx_UNSPEC (Pmode,
1601 gen_rtvec (1, XVECEXP (base, 0, 0)),
1602 UNSPEC_LTREL_OFFSET);
1606 base = XVECEXP (base, 0, 1);
1609 case UNSPEC_LTREL_BASE:
1610 if (XVECLEN (base, 0) == 1)
1611 base = fake_pool_base, literal_pool = true;
1613 base = XVECEXP (base, 0, 1);
1621 || (GET_MODE (base) != SImode
1622 && GET_MODE (base) != Pmode))
1625 if (REGNO (base) == STACK_POINTER_REGNUM
1626 || REGNO (base) == FRAME_POINTER_REGNUM
1627 || ((reload_completed || reload_in_progress)
1628 && frame_pointer_needed
1629 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1630 || REGNO (base) == ARG_POINTER_REGNUM
1632 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1633 pointer = base_ptr = true;
1635 if ((reload_completed || reload_in_progress)
1636 && base == cfun->machine->base_reg)
1637 pointer = base_ptr = literal_pool = true;
1640 /* Validate index register. */
1643 if (GET_CODE (indx) == UNSPEC)
1644 switch (XINT (indx, 1))
1648 disp = gen_rtx_UNSPEC (Pmode,
1649 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1650 UNSPEC_LTREL_OFFSET);
1654 indx = XVECEXP (indx, 0, 1);
1657 case UNSPEC_LTREL_BASE:
1658 if (XVECLEN (indx, 0) == 1)
1659 indx = fake_pool_base, literal_pool = true;
1661 indx = XVECEXP (indx, 0, 1);
1669 || (GET_MODE (indx) != SImode
1670 && GET_MODE (indx) != Pmode))
1673 if (REGNO (indx) == STACK_POINTER_REGNUM
1674 || REGNO (indx) == FRAME_POINTER_REGNUM
1675 || ((reload_completed || reload_in_progress)
1676 && frame_pointer_needed
1677 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1678 || REGNO (indx) == ARG_POINTER_REGNUM
1680 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1681 pointer = indx_ptr = true;
1683 if ((reload_completed || reload_in_progress)
1684 && indx == cfun->machine->base_reg)
1685 pointer = indx_ptr = literal_pool = true;
1688 /* Prefer to use pointer as base, not index. */
1689 if (base && indx && !base_ptr
1690 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1697 /* Validate displacement. */
1700 /* If virtual registers are involved, the displacement will change later
1701 anyway as the virtual registers get eliminated. This could make a
1702 valid displacement invalid, but it is more likely to make an invalid
1703 displacement valid, because we sometimes access the register save area
1704 via negative offsets to one of those registers.
1705 Thus we don't check the displacement for validity here. If after
1706 elimination the displacement turns out to be invalid after all,
1707 this is fixed up by reload in any case. */
1708 if (base != arg_pointer_rtx
1709 && indx != arg_pointer_rtx
1710 && base != return_address_pointer_rtx
1711 && indx != return_address_pointer_rtx
1712 && base != frame_pointer_rtx
1713 && indx != frame_pointer_rtx
1714 && base != virtual_stack_vars_rtx
1715 && indx != virtual_stack_vars_rtx)
1716 if (!DISP_IN_RANGE (offset))
1721 /* All the special cases are pointers. */
1724 /* In the small-PIC case, the linker converts @GOT
1725 and @GOTNTPOFF offsets to possible displacements. */
1726 if (GET_CODE (disp) == UNSPEC
1727 && (XINT (disp, 1) == UNSPEC_GOT
1728 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1735 /* Accept chunkified literal pool symbol references. */
1736 else if (cfun && cfun->machine
1737 && cfun->machine->decomposed_literal_pool_addresses_ok_p
1738 && GET_CODE (disp) == MINUS
1739 && GET_CODE (XEXP (disp, 0)) == LABEL_REF
1740 && GET_CODE (XEXP (disp, 1)) == LABEL_REF)
1745 /* Accept literal pool references. */
1746 else if (GET_CODE (disp) == UNSPEC
1747 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1749 orig_disp = gen_rtx_CONST (Pmode, disp);
1752 /* If we have an offset, make sure it does not
1753 exceed the size of the constant pool entry. */
1754 rtx sym = XVECEXP (disp, 0, 0);
1755 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1758 orig_disp = plus_constant (orig_disp, offset);
1773 out->disp = orig_disp;
1774 out->pointer = pointer;
1775 out->literal_pool = literal_pool;
1781 /* Decompose a RTL expression OP for a shift count into its components,
1782 and return the base register in BASE and the offset in OFFSET.
1784 Return true if OP is a valid shift count, false if not. */
1787 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
1789 HOST_WIDE_INT off = 0;
1791 /* We can have an integer constant, an address register,
1792 or a sum of the two. */
1793 if (GET_CODE (op) == CONST_INT)
1798 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
1800 off = INTVAL (XEXP (op, 1));
1803 while (op && GET_CODE (op) == SUBREG)
1804 op = SUBREG_REG (op);
1806 if (op && GET_CODE (op) != REG)
1818 /* Return true if CODE is a valid address without index. */
1821 s390_legitimate_address_without_index_p (rtx op)
1823 struct s390_address addr;
1825 if (!s390_decompose_address (XEXP (op, 0), &addr))
1833 /* Return 1 if OP is a valid operand for a C constraint, 0 else. */
1836 s390_extra_constraint_str (rtx op, int c, const char * str)
1838 struct s390_address addr;
1840 gcc_assert (c == str[0]);
1842 /* Check for offsettable variants of memory constraints. */
1845 /* Only accept non-volatile MEMs. */
1846 if (!MEM_P (op) || MEM_VOLATILE_P (op))
1849 if ((reload_completed || reload_in_progress)
1850 ? !offsettable_memref_p (op)
1851 : !offsettable_nonstrict_memref_p (op))
1857 /* Check for non-literal-pool variants of memory constraints. */
1860 if (GET_CODE (op) != MEM)
1862 if (!s390_decompose_address (XEXP (op, 0), &addr))
1864 if (addr.literal_pool)
1873 if (GET_CODE (op) != MEM)
1875 if (!s390_decompose_address (XEXP (op, 0), &addr))
1880 if (TARGET_LONG_DISPLACEMENT)
1882 if (!s390_short_displacement (addr.disp))
1888 if (GET_CODE (op) != MEM)
1891 if (TARGET_LONG_DISPLACEMENT)
1893 if (!s390_decompose_address (XEXP (op, 0), &addr))
1895 if (!s390_short_displacement (addr.disp))
1901 if (!TARGET_LONG_DISPLACEMENT)
1903 if (GET_CODE (op) != MEM)
1905 if (!s390_decompose_address (XEXP (op, 0), &addr))
1909 if (s390_short_displacement (addr.disp))
1914 if (!TARGET_LONG_DISPLACEMENT)
1916 if (GET_CODE (op) != MEM)
1918 /* Any invalid address here will be fixed up by reload,
1919 so accept it for the most generic constraint. */
1920 if (s390_decompose_address (XEXP (op, 0), &addr)
1921 && s390_short_displacement (addr.disp))
1926 if (TARGET_LONG_DISPLACEMENT)
1928 if (!s390_decompose_address (op, &addr))
1930 if (!s390_short_displacement (addr.disp))
1936 if (!TARGET_LONG_DISPLACEMENT)
1938 /* Any invalid address here will be fixed up by reload,
1939 so accept it for the most generic constraint. */
1940 if (s390_decompose_address (op, &addr)
1941 && s390_short_displacement (addr.disp))
1946 /* Simply check for the basic form of a shift count. Reload will
1947 take care of making sure we have a proper base register. */
1948 if (!s390_decompose_shift_count (op, NULL, NULL))
1959 /* Return true if VALUE matches the constraint STR. */
1962 s390_const_double_ok_for_constraint_p (rtx value,
1966 gcc_assert (c == str[0]);
1971 /* The floating point zero constant. */
1972 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
1973 && value == CONST0_RTX (GET_MODE (value)));
1980 /* Return true if VALUE matches the constraint STR. */
1983 s390_const_ok_for_constraint_p (HOST_WIDE_INT value,
1987 enum machine_mode mode, part_mode;
1989 int part, part_goal;
1991 gcc_assert (c == str[0]);
1996 return (unsigned int)value < 256;
1999 return (unsigned int)value < 4096;
2002 return value >= -32768 && value < 32768;
2005 return (TARGET_LONG_DISPLACEMENT ?
2006 (value >= -524288 && value <= 524287)
2007 : (value >= 0 && value <= 4095));
2009 return value == 2147483647;
2015 part_goal = str[1] - '0';
2019 case 'Q': part_mode = QImode; break;
2020 case 'H': part_mode = HImode; break;
2021 case 'S': part_mode = SImode; break;
2027 case 'H': mode = HImode; break;
2028 case 'S': mode = SImode; break;
2029 case 'D': mode = DImode; break;
2035 case '0': def = 0; break;
2036 case 'F': def = -1; break;
2040 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2043 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2046 if (part_goal != -1 && part_goal != part)
2058 return trunc_int_for_mode (value, SImode) == value;
2062 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2066 || s390_single_part (GEN_INT (value), DImode, SImode, -1) == 1;
2074 return legitimate_reload_constant_p (GEN_INT (value));
2083 /* Compute a (partial) cost for rtx X. Return true if the complete
2084 cost has been computed, and false if subexpressions should be
2085 scanned. In either case, *TOTAL contains the cost result.
2086 CODE contains GET_CODE (x), OUTER_CODE contains the code
2087 of the superexpression of x. */
2090 s390_rtx_costs (rtx x, int code, int outer_code, int *total)
2113 *total = COSTS_N_INSNS (1);
2118 /* Check for multiply and add. */
2119 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2120 && GET_CODE (XEXP (x, 0)) == MULT
2121 && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD)
2123 /* This is the multiply and add case. */
2124 if (GET_MODE (x) == DFmode)
2125 *total = s390_cost->madbr;
2127 *total = s390_cost->maebr;
2128 *total += rtx_cost (XEXP (XEXP (x, 0), 0), MULT)
2129 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT)
2130 + rtx_cost (XEXP (x, 1), code);
2131 return true; /* Do not do an additional recursive descent. */
2133 *total = COSTS_N_INSNS (1);
2137 switch (GET_MODE (x))
2141 rtx left = XEXP (x, 0);
2142 rtx right = XEXP (x, 1);
2143 if (GET_CODE (right) == CONST_INT
2144 && CONST_OK_FOR_K (INTVAL (right)))
2145 *total = s390_cost->mhi;
2146 else if (GET_CODE (left) == SIGN_EXTEND)
2147 *total = s390_cost->mh;
2149 *total = s390_cost->ms; /* msr, ms, msy */
2154 rtx left = XEXP (x, 0);
2155 rtx right = XEXP (x, 1);
2158 if (GET_CODE (right) == CONST_INT
2159 && CONST_OK_FOR_K (INTVAL (right)))
2160 *total = s390_cost->mghi;
2161 else if (GET_CODE (left) == SIGN_EXTEND)
2162 *total = s390_cost->msgf;
2164 *total = s390_cost->msg; /* msgr, msg */
2166 else /* TARGET_31BIT */
2168 if (GET_CODE (left) == SIGN_EXTEND
2169 && GET_CODE (right) == SIGN_EXTEND)
2170 /* mulsidi case: mr, m */
2171 *total = s390_cost->m;
2172 else if (GET_CODE (left) == ZERO_EXTEND
2173 && GET_CODE (right) == ZERO_EXTEND
2174 && TARGET_CPU_ZARCH)
2175 /* umulsidi case: ml, mlr */
2176 *total = s390_cost->ml;
2178 /* Complex calculation is required. */
2179 *total = COSTS_N_INSNS (40);
2185 *total = s390_cost->mult_df;
2188 *total = s390_cost->mxbr;
2197 if (GET_MODE (x) == TImode) /* 128 bit division */
2198 *total = s390_cost->dlgr;
2199 else if (GET_MODE (x) == DImode)
2201 rtx right = XEXP (x, 1);
2202 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2203 *total = s390_cost->dlr;
2204 else /* 64 by 64 bit division */
2205 *total = s390_cost->dlgr;
2207 else if (GET_MODE (x) == SImode) /* 32 bit division */
2208 *total = s390_cost->dlr;
2213 if (GET_MODE (x) == DImode)
2215 rtx right = XEXP (x, 1);
2216 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2218 *total = s390_cost->dsgfr;
2220 *total = s390_cost->dr;
2221 else /* 64 by 64 bit division */
2222 *total = s390_cost->dsgr;
2224 else if (GET_MODE (x) == SImode) /* 32 bit division */
2225 *total = s390_cost->dlr;
2226 else if (GET_MODE (x) == SFmode)
2228 if (TARGET_IEEE_FLOAT)
2229 *total = s390_cost->debr;
2230 else /* TARGET_IBM_FLOAT */
2231 *total = s390_cost->der;
2233 else if (GET_MODE (x) == DFmode)
2235 if (TARGET_IEEE_FLOAT)
2236 *total = s390_cost->ddbr;
2237 else /* TARGET_IBM_FLOAT */
2238 *total = s390_cost->ddr;
2240 else if (GET_MODE (x) == TFmode)
2242 if (TARGET_IEEE_FLOAT)
2243 *total = s390_cost->dxbr;
2244 else /* TARGET_IBM_FLOAT */
2245 *total = s390_cost->dxr;
2250 if (GET_MODE (x) == SFmode)
2251 *total = s390_cost->sqebr;
2252 else if (GET_MODE (x) == DFmode)
2253 *total = s390_cost->sqdbr;
2255 *total = s390_cost->sqxbr;
2260 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2261 || outer_code == PLUS || outer_code == MINUS
2262 || outer_code == COMPARE)
2267 *total = COSTS_N_INSNS (1);
2268 if (GET_CODE (XEXP (x, 0)) == AND
2269 && GET_CODE (XEXP (x, 1)) == CONST_INT
2270 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2272 rtx op0 = XEXP (XEXP (x, 0), 0);
2273 rtx op1 = XEXP (XEXP (x, 0), 1);
2274 rtx op2 = XEXP (x, 1);
2276 if (memory_operand (op0, GET_MODE (op0))
2277 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2279 if (register_operand (op0, GET_MODE (op0))
2280 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2290 /* Return the cost of an address rtx ADDR. */
2293 s390_address_cost (rtx addr)
2295 struct s390_address ad;
2296 if (!s390_decompose_address (addr, &ad))
2299 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2302 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2303 otherwise return 0. */
2306 tls_symbolic_operand (rtx op)
2308 if (GET_CODE (op) != SYMBOL_REF)
2310 return SYMBOL_REF_TLS_MODEL (op);
2313 /* Split DImode access register reference REG (on 64-bit) into its constituent
2314 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2315 gen_highpart cannot be used as they assume all registers are word-sized,
2316 while our access registers have only half that size. */
2319 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2321 gcc_assert (TARGET_64BIT);
2322 gcc_assert (ACCESS_REG_P (reg));
2323 gcc_assert (GET_MODE (reg) == DImode);
2324 gcc_assert (!(REGNO (reg) & 1));
2326 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2327 *hi = gen_rtx_REG (SImode, REGNO (reg));
2330 /* Return true if OP contains a symbol reference */
2333 symbolic_reference_mentioned_p (rtx op)
2338 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2341 fmt = GET_RTX_FORMAT (GET_CODE (op));
2342 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2348 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2349 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2353 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2360 /* Return true if OP contains a reference to a thread-local symbol. */
2363 tls_symbolic_reference_mentioned_p (rtx op)
2368 if (GET_CODE (op) == SYMBOL_REF)
2369 return tls_symbolic_operand (op);
2371 fmt = GET_RTX_FORMAT (GET_CODE (op));
2372 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2378 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2379 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2383 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2391 /* Return true if OP is a legitimate general operand when
2392 generating PIC code. It is given that flag_pic is on
2393 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2396 legitimate_pic_operand_p (rtx op)
2398 /* Accept all non-symbolic constants. */
2399 if (!SYMBOLIC_CONST (op))
2402 /* Reject everything else; must be handled
2403 via emit_symbolic_move. */
2407 /* Returns true if the constant value OP is a legitimate general operand.
2408 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2411 legitimate_constant_p (rtx op)
2413 /* Accept all non-symbolic constants. */
2414 if (!SYMBOLIC_CONST (op))
2417 /* Accept immediate LARL operands. */
2418 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2421 /* Thread-local symbols are never legal constants. This is
2422 so that emit_call knows that computing such addresses
2423 might require a function call. */
2424 if (TLS_SYMBOLIC_CONST (op))
2427 /* In the PIC case, symbolic constants must *not* be
2428 forced into the literal pool. We accept them here,
2429 so that they will be handled by emit_symbolic_move. */
2433 /* All remaining non-PIC symbolic constants are
2434 forced into the literal pool. */
2438 /* Determine if it's legal to put X into the constant pool. This
2439 is not possible if X contains the address of a symbol that is
2440 not constant (TLS) or not known at final link time (PIC). */
2443 s390_cannot_force_const_mem (rtx x)
2445 switch (GET_CODE (x))
2449 /* Accept all non-symbolic constants. */
2453 /* Labels are OK iff we are non-PIC. */
2454 return flag_pic != 0;
2457 /* 'Naked' TLS symbol references are never OK,
2458 non-TLS symbols are OK iff we are non-PIC. */
2459 if (tls_symbolic_operand (x))
2462 return flag_pic != 0;
2465 return s390_cannot_force_const_mem (XEXP (x, 0));
2468 return s390_cannot_force_const_mem (XEXP (x, 0))
2469 || s390_cannot_force_const_mem (XEXP (x, 1));
2472 switch (XINT (x, 1))
2474 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2475 case UNSPEC_LTREL_OFFSET:
2483 case UNSPEC_GOTNTPOFF:
2484 case UNSPEC_INDNTPOFF:
2487 /* If the literal pool shares the code section, be put
2488 execute template placeholders into the pool as well. */
2490 return TARGET_CPU_ZARCH;
2502 /* Returns true if the constant value OP is a legitimate general
2503 operand during and after reload. The difference to
2504 legitimate_constant_p is that this function will not accept
2505 a constant that would need to be forced to the literal pool
2506 before it can be used as operand. */
2509 legitimate_reload_constant_p (rtx op)
2511 /* Accept la(y) operands. */
2512 if (GET_CODE (op) == CONST_INT
2513 && DISP_IN_RANGE (INTVAL (op)))
2516 /* Accept l(g)hi/l(g)fi operands. */
2517 if (GET_CODE (op) == CONST_INT
2518 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2521 /* Accept lliXX operands. */
2523 && GET_CODE (op) == CONST_INT
2524 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2525 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2529 && GET_CODE (op) == CONST_INT
2530 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2531 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2534 /* Accept larl operands. */
2535 if (TARGET_CPU_ZARCH
2536 && larl_operand (op, VOIDmode))
2539 /* Accept lzXX operands. */
2540 if (GET_CODE (op) == CONST_DOUBLE
2541 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
2544 /* Accept double-word operands that can be split. */
2545 if (GET_CODE (op) == CONST_INT
2546 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2548 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2549 rtx hi = operand_subword (op, 0, 0, dword_mode);
2550 rtx lo = operand_subword (op, 1, 0, dword_mode);
2551 return legitimate_reload_constant_p (hi)
2552 && legitimate_reload_constant_p (lo);
2555 /* Everything else cannot be handled without reload. */
2559 /* Given an rtx OP being reloaded into a reg required to be in class CLASS,
2560 return the class of reg to actually use. */
2563 s390_preferred_reload_class (rtx op, enum reg_class class)
2565 switch (GET_CODE (op))
2567 /* Constants we cannot reload must be forced into the
2572 if (legitimate_reload_constant_p (op))
2577 /* If a symbolic constant or a PLUS is reloaded,
2578 it is most likely being used as an address, so
2579 prefer ADDR_REGS. If 'class' is not a superset
2580 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2585 if (reg_class_subset_p (ADDR_REGS, class))
2597 /* Return the register class of a scratch register needed to
2598 load IN into a register of class CLASS in MODE.
2600 We need a temporary when loading a PLUS expression which
2601 is not a legitimate operand of the LOAD ADDRESS instruction. */
2604 s390_secondary_input_reload_class (enum reg_class class,
2605 enum machine_mode mode, rtx in)
2607 if (s390_plus_operand (in, mode))
2610 if (reg_classes_intersect_p (FP_REGS, class)
2612 && GET_CODE (in) == MEM
2613 && GET_CODE (XEXP (in, 0)) == PLUS
2614 && GET_CODE (XEXP (XEXP (in, 0), 1)) == CONST_INT
2615 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (in, 0), 1))
2616 + GET_MODE_SIZE (mode) - 1))
2619 if (reg_classes_intersect_p (CC_REGS, class))
2620 return GENERAL_REGS;
2625 /* Return the register class of a scratch register needed to
2626 store a register of class CLASS in MODE into OUT:
2628 We need a temporary when storing a double-word to a
2629 non-offsettable memory address. */
2632 s390_secondary_output_reload_class (enum reg_class class,
2633 enum machine_mode mode, rtx out)
2635 if ((TARGET_64BIT ? (mode == TImode || mode == TFmode)
2636 : (mode == DImode || mode == DFmode))
2637 && reg_classes_intersect_p (GENERAL_REGS, class)
2638 && GET_CODE (out) == MEM
2639 && GET_CODE (XEXP (out, 0)) == PLUS
2640 && GET_CODE (XEXP (XEXP (out, 0), 0)) == PLUS
2641 && GET_CODE (XEXP (XEXP (out, 0), 1)) == CONST_INT
2642 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (out, 0), 1))
2643 + GET_MODE_SIZE (mode) - 1))
2646 if (reg_classes_intersect_p (FP_REGS, class)
2648 && GET_CODE (out) == MEM
2649 && GET_CODE (XEXP (out, 0)) == PLUS
2650 && GET_CODE (XEXP (XEXP (out, 0), 1)) == CONST_INT
2651 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (out, 0), 1))
2652 + GET_MODE_SIZE (mode) - 1))
2655 if (reg_classes_intersect_p (CC_REGS, class))
2656 return GENERAL_REGS;
2661 /* Generate code to load SRC, which is PLUS that is not a
2662 legitimate operand for the LA instruction, into TARGET.
2663 SCRATCH may be used as scratch register. */
2666 s390_expand_plus_operand (rtx target, rtx src,
2670 struct s390_address ad;
2672 /* src must be a PLUS; get its two operands. */
2673 gcc_assert (GET_CODE (src) == PLUS);
2674 gcc_assert (GET_MODE (src) == Pmode);
2676 /* Check if any of the two operands is already scheduled
2677 for replacement by reload. This can happen e.g. when
2678 float registers occur in an address. */
2679 sum1 = find_replacement (&XEXP (src, 0));
2680 sum2 = find_replacement (&XEXP (src, 1));
2681 src = gen_rtx_PLUS (Pmode, sum1, sum2);
2683 /* If the address is already strictly valid, there's nothing to do. */
2684 if (!s390_decompose_address (src, &ad)
2685 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
2686 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
2688 /* Otherwise, one of the operands cannot be an address register;
2689 we reload its value into the scratch register. */
2690 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
2692 emit_move_insn (scratch, sum1);
2695 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
2697 emit_move_insn (scratch, sum2);
2701 /* According to the way these invalid addresses are generated
2702 in reload.c, it should never happen (at least on s390) that
2703 *neither* of the PLUS components, after find_replacements
2704 was applied, is an address register. */
2705 if (sum1 == scratch && sum2 == scratch)
2711 src = gen_rtx_PLUS (Pmode, sum1, sum2);
2714 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
2715 is only ever performed on addresses, so we can mark the
2716 sum as legitimate for LA in any case. */
2717 s390_load_address (target, src);
2721 /* Return true if ADDR is a valid memory address.
2722 STRICT specifies whether strict register checking applies. */
2725 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2726 rtx addr, int strict)
2728 struct s390_address ad;
2729 if (!s390_decompose_address (addr, &ad))
2734 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
2737 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
2743 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
2744 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
2748 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
2749 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
2755 /* Return true if OP is a valid operand for the LA instruction.
2756 In 31-bit, we need to prove that the result is used as an
2757 address, as LA performs only a 31-bit addition. */
2760 legitimate_la_operand_p (rtx op)
2762 struct s390_address addr;
2763 if (!s390_decompose_address (op, &addr))
2766 return (TARGET_64BIT || addr.pointer);
2769 /* Return true if it is valid *and* preferable to use LA to
2770 compute the sum of OP1 and OP2. */
2773 preferred_la_operand_p (rtx op1, rtx op2)
2775 struct s390_address addr;
2777 if (op2 != const0_rtx)
2778 op1 = gen_rtx_PLUS (Pmode, op1, op2);
2780 if (!s390_decompose_address (op1, &addr))
2782 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
2784 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
2787 if (!TARGET_64BIT && !addr.pointer)
2793 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
2794 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
2800 /* Emit a forced load-address operation to load SRC into DST.
2801 This will use the LOAD ADDRESS instruction even in situations
2802 where legitimate_la_operand_p (SRC) returns false. */
2805 s390_load_address (rtx dst, rtx src)
2808 emit_move_insn (dst, src);
2810 emit_insn (gen_force_la_31 (dst, src));
2813 /* Return a legitimate reference for ORIG (an address) using the
2814 register REG. If REG is 0, a new pseudo is generated.
2816 There are two types of references that must be handled:
2818 1. Global data references must load the address from the GOT, via
2819 the PIC reg. An insn is emitted to do this load, and the reg is
2822 2. Static data references, constant pool addresses, and code labels
2823 compute the address as an offset from the GOT, whose base is in
2824 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
2825 differentiate them from global data objects. The returned
2826 address is the PIC reg + an unspec constant.
2828 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2829 reg also appears in the address. */
2832 legitimize_pic_address (rtx orig, rtx reg)
2838 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
2840 if (GET_CODE (addr) == LABEL_REF
2841 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
2843 /* This is a local symbol. */
2844 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
2846 /* Access local symbols PC-relative via LARL.
2847 This is the same as in the non-PIC case, so it is
2848 handled automatically ... */
2852 /* Access local symbols relative to the GOT. */
2854 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2856 if (reload_in_progress || reload_completed)
2857 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2859 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
2860 addr = gen_rtx_CONST (Pmode, addr);
2861 addr = force_const_mem (Pmode, addr);
2862 emit_move_insn (temp, addr);
2864 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2867 s390_load_address (reg, new);
2872 else if (GET_CODE (addr) == SYMBOL_REF)
2875 reg = gen_reg_rtx (Pmode);
2879 /* Assume GOT offset < 4k. This is handled the same way
2880 in both 31- and 64-bit code (@GOT). */
2882 if (reload_in_progress || reload_completed)
2883 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2885 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2886 new = gen_rtx_CONST (Pmode, new);
2887 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2888 new = gen_const_mem (Pmode, new);
2889 emit_move_insn (reg, new);
2892 else if (TARGET_CPU_ZARCH)
2894 /* If the GOT offset might be >= 4k, we determine the position
2895 of the GOT entry via a PC-relative LARL (@GOTENT). */
2897 rtx temp = gen_reg_rtx (Pmode);
2899 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
2900 new = gen_rtx_CONST (Pmode, new);
2901 emit_move_insn (temp, new);
2903 new = gen_const_mem (Pmode, temp);
2904 emit_move_insn (reg, new);
2909 /* If the GOT offset might be >= 4k, we have to load it
2910 from the literal pool (@GOT). */
2912 rtx temp = gen_reg_rtx (Pmode);
2914 if (reload_in_progress || reload_completed)
2915 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2917 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2918 addr = gen_rtx_CONST (Pmode, addr);
2919 addr = force_const_mem (Pmode, addr);
2920 emit_move_insn (temp, addr);
2922 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2923 new = gen_const_mem (Pmode, new);
2924 emit_move_insn (reg, new);
2930 if (GET_CODE (addr) == CONST)
2932 addr = XEXP (addr, 0);
2933 if (GET_CODE (addr) == UNSPEC)
2935 gcc_assert (XVECLEN (addr, 0) == 1);
2936 switch (XINT (addr, 1))
2938 /* If someone moved a GOT-relative UNSPEC
2939 out of the literal pool, force them back in. */
2942 new = force_const_mem (Pmode, orig);
2945 /* @GOT is OK as is if small. */
2948 new = force_const_mem (Pmode, orig);
2951 /* @GOTENT is OK as is. */
2955 /* @PLT is OK as is on 64-bit, must be converted to
2956 GOT-relative @PLTOFF on 31-bit. */
2958 if (!TARGET_CPU_ZARCH)
2960 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2962 if (reload_in_progress || reload_completed)
2963 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2965 addr = XVECEXP (addr, 0, 0);
2966 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
2968 addr = gen_rtx_CONST (Pmode, addr);
2969 addr = force_const_mem (Pmode, addr);
2970 emit_move_insn (temp, addr);
2972 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2975 s390_load_address (reg, new);
2981 /* Everything else cannot happen. */
2987 gcc_assert (GET_CODE (addr) == PLUS);
2989 if (GET_CODE (addr) == PLUS)
2991 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
2993 gcc_assert (!TLS_SYMBOLIC_CONST (op0));
2994 gcc_assert (!TLS_SYMBOLIC_CONST (op1));
2996 /* Check first to see if this is a constant offset
2997 from a local symbol reference. */
2998 if ((GET_CODE (op0) == LABEL_REF
2999 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
3000 && GET_CODE (op1) == CONST_INT)
3002 if (TARGET_CPU_ZARCH && larl_operand (op0, VOIDmode))
3004 if (INTVAL (op1) & 1)
3006 /* LARL can't handle odd offsets, so emit a
3007 pair of LARL and LA. */
3008 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3010 if (!DISP_IN_RANGE (INTVAL (op1)))
3012 int even = INTVAL (op1) - 1;
3013 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
3014 op0 = gen_rtx_CONST (Pmode, op0);
3018 emit_move_insn (temp, op0);
3019 new = gen_rtx_PLUS (Pmode, temp, op1);
3023 s390_load_address (reg, new);
3029 /* If the offset is even, we can just use LARL.
3030 This will happen automatically. */
3035 /* Access local symbols relative to the GOT. */
3037 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3039 if (reload_in_progress || reload_completed)
3040 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3042 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
3044 addr = gen_rtx_PLUS (Pmode, addr, op1);
3045 addr = gen_rtx_CONST (Pmode, addr);
3046 addr = force_const_mem (Pmode, addr);
3047 emit_move_insn (temp, addr);
3049 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3052 s390_load_address (reg, new);
3058 /* Now, check whether it is a GOT relative symbol plus offset
3059 that was pulled out of the literal pool. Force it back in. */
3061 else if (GET_CODE (op0) == UNSPEC
3062 && GET_CODE (op1) == CONST_INT
3063 && XINT (op0, 1) == UNSPEC_GOTOFF)
3065 gcc_assert (XVECLEN (op0, 0) == 1);
3067 new = force_const_mem (Pmode, orig);
3070 /* Otherwise, compute the sum. */
3073 base = legitimize_pic_address (XEXP (addr, 0), reg);
3074 new = legitimize_pic_address (XEXP (addr, 1),
3075 base == reg ? NULL_RTX : reg);
3076 if (GET_CODE (new) == CONST_INT)
3077 new = plus_constant (base, INTVAL (new));
3080 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
3082 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
3083 new = XEXP (new, 1);
3085 new = gen_rtx_PLUS (Pmode, base, new);
3088 if (GET_CODE (new) == CONST)
3089 new = XEXP (new, 0);
3090 new = force_operand (new, 0);
3097 /* Load the thread pointer into a register. */
3100 s390_get_thread_pointer (void)
3102 rtx tp = gen_reg_rtx (Pmode);
3104 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3105 mark_reg_pointer (tp, BITS_PER_WORD);
3110 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3111 in s390_tls_symbol which always refers to __tls_get_offset.
3112 The returned offset is written to RESULT_REG and an USE rtx is
3113 generated for TLS_CALL. */
3115 static GTY(()) rtx s390_tls_symbol;
3118 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3122 gcc_assert (flag_pic);
3124 if (!s390_tls_symbol)
3125 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3127 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3128 gen_rtx_REG (Pmode, RETURN_REGNUM));
3130 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3131 CONST_OR_PURE_CALL_P (insn) = 1;
3134 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3135 this (thread-local) address. REG may be used as temporary. */
3138 legitimize_tls_address (rtx addr, rtx reg)
3140 rtx new, tls_call, temp, base, r2, insn;
3142 if (GET_CODE (addr) == SYMBOL_REF)
3143 switch (tls_symbolic_operand (addr))
3145 case TLS_MODEL_GLOBAL_DYNAMIC:
3147 r2 = gen_rtx_REG (Pmode, 2);
3148 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3149 new = gen_rtx_CONST (Pmode, tls_call);
3150 new = force_const_mem (Pmode, new);
3151 emit_move_insn (r2, new);
3152 s390_emit_tls_call_insn (r2, tls_call);
3153 insn = get_insns ();
3156 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3157 temp = gen_reg_rtx (Pmode);
3158 emit_libcall_block (insn, temp, r2, new);
3160 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3163 s390_load_address (reg, new);
3168 case TLS_MODEL_LOCAL_DYNAMIC:
3170 r2 = gen_rtx_REG (Pmode, 2);
3171 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3172 new = gen_rtx_CONST (Pmode, tls_call);
3173 new = force_const_mem (Pmode, new);
3174 emit_move_insn (r2, new);
3175 s390_emit_tls_call_insn (r2, tls_call);
3176 insn = get_insns ();
3179 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3180 temp = gen_reg_rtx (Pmode);
3181 emit_libcall_block (insn, temp, r2, new);
3183 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3184 base = gen_reg_rtx (Pmode);
3185 s390_load_address (base, new);
3187 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3188 new = gen_rtx_CONST (Pmode, new);
3189 new = force_const_mem (Pmode, new);
3190 temp = gen_reg_rtx (Pmode);
3191 emit_move_insn (temp, new);
3193 new = gen_rtx_PLUS (Pmode, base, temp);
3196 s390_load_address (reg, new);
3201 case TLS_MODEL_INITIAL_EXEC:
3204 /* Assume GOT offset < 4k. This is handled the same way
3205 in both 31- and 64-bit code. */
3207 if (reload_in_progress || reload_completed)
3208 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3210 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3211 new = gen_rtx_CONST (Pmode, new);
3212 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
3213 new = gen_const_mem (Pmode, new);
3214 temp = gen_reg_rtx (Pmode);
3215 emit_move_insn (temp, new);
3217 else if (TARGET_CPU_ZARCH)
3219 /* If the GOT offset might be >= 4k, we determine the position
3220 of the GOT entry via a PC-relative LARL. */
3222 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3223 new = gen_rtx_CONST (Pmode, new);
3224 temp = gen_reg_rtx (Pmode);
3225 emit_move_insn (temp, new);
3227 new = gen_const_mem (Pmode, temp);
3228 temp = gen_reg_rtx (Pmode);
3229 emit_move_insn (temp, new);
3233 /* If the GOT offset might be >= 4k, we have to load it
3234 from the literal pool. */
3236 if (reload_in_progress || reload_completed)
3237 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3239 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3240 new = gen_rtx_CONST (Pmode, new);
3241 new = force_const_mem (Pmode, new);
3242 temp = gen_reg_rtx (Pmode);
3243 emit_move_insn (temp, new);
3245 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3246 new = gen_const_mem (Pmode, new);
3248 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3249 temp = gen_reg_rtx (Pmode);
3250 emit_insn (gen_rtx_SET (Pmode, temp, new));
3254 /* In position-dependent code, load the absolute address of
3255 the GOT entry from the literal pool. */
3257 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3258 new = gen_rtx_CONST (Pmode, new);
3259 new = force_const_mem (Pmode, new);
3260 temp = gen_reg_rtx (Pmode);
3261 emit_move_insn (temp, new);
3264 new = gen_const_mem (Pmode, new);
3265 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3266 temp = gen_reg_rtx (Pmode);
3267 emit_insn (gen_rtx_SET (Pmode, temp, new));
3270 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3273 s390_load_address (reg, new);
3278 case TLS_MODEL_LOCAL_EXEC:
3279 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3280 new = gen_rtx_CONST (Pmode, new);
3281 new = force_const_mem (Pmode, new);
3282 temp = gen_reg_rtx (Pmode);
3283 emit_move_insn (temp, new);
3285 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3288 s390_load_address (reg, new);
3297 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3299 switch (XINT (XEXP (addr, 0), 1))
3301 case UNSPEC_INDNTPOFF:
3302 gcc_assert (TARGET_CPU_ZARCH);
3311 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3312 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3314 new = XEXP (XEXP (addr, 0), 0);
3315 if (GET_CODE (new) != SYMBOL_REF)
3316 new = gen_rtx_CONST (Pmode, new);
3318 new = legitimize_tls_address (new, reg);
3319 new = plus_constant (new, INTVAL (XEXP (XEXP (addr, 0), 1)));
3320 new = force_operand (new, 0);
3324 gcc_unreachable (); /* for now ... */
3329 /* Emit insns to move operands[1] into operands[0]. */
3332 emit_symbolic_move (rtx *operands)
3334 rtx temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
3336 if (GET_CODE (operands[0]) == MEM)
3337 operands[1] = force_reg (Pmode, operands[1]);
3338 else if (TLS_SYMBOLIC_CONST (operands[1]))
3339 operands[1] = legitimize_tls_address (operands[1], temp);
3341 operands[1] = legitimize_pic_address (operands[1], temp);
3344 /* Try machine-dependent ways of modifying an illegitimate address X
3345 to be legitimate. If we find one, return the new, valid address.
3347 OLDX is the address as it was before break_out_memory_refs was called.
3348 In some cases it is useful to look at this to decide what needs to be done.
3350 MODE is the mode of the operand pointed to by X.
3352 When -fpic is used, special handling is needed for symbolic references.
3353 See comments by legitimize_pic_address for details. */
3356 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3357 enum machine_mode mode ATTRIBUTE_UNUSED)
3359 rtx constant_term = const0_rtx;
3361 if (TLS_SYMBOLIC_CONST (x))
3363 x = legitimize_tls_address (x, 0);
3365 if (legitimate_address_p (mode, x, FALSE))
3368 else if (GET_CODE (x) == PLUS
3369 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3370 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3376 if (SYMBOLIC_CONST (x)
3377 || (GET_CODE (x) == PLUS
3378 && (SYMBOLIC_CONST (XEXP (x, 0))
3379 || SYMBOLIC_CONST (XEXP (x, 1)))))
3380 x = legitimize_pic_address (x, 0);
3382 if (legitimate_address_p (mode, x, FALSE))
3386 x = eliminate_constant_term (x, &constant_term);
3388 /* Optimize loading of large displacements by splitting them
3389 into the multiple of 4K and the rest; this allows the
3390 former to be CSE'd if possible.
3392 Don't do this if the displacement is added to a register
3393 pointing into the stack frame, as the offsets will
3394 change later anyway. */
3396 if (GET_CODE (constant_term) == CONST_INT
3397 && !TARGET_LONG_DISPLACEMENT
3398 && !DISP_IN_RANGE (INTVAL (constant_term))
3399 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3401 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3402 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3404 rtx temp = gen_reg_rtx (Pmode);
3405 rtx val = force_operand (GEN_INT (upper), temp);
3407 emit_move_insn (temp, val);
3409 x = gen_rtx_PLUS (Pmode, x, temp);
3410 constant_term = GEN_INT (lower);
3413 if (GET_CODE (x) == PLUS)
3415 if (GET_CODE (XEXP (x, 0)) == REG)
3417 rtx temp = gen_reg_rtx (Pmode);
3418 rtx val = force_operand (XEXP (x, 1), temp);
3420 emit_move_insn (temp, val);
3422 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3425 else if (GET_CODE (XEXP (x, 1)) == REG)
3427 rtx temp = gen_reg_rtx (Pmode);
3428 rtx val = force_operand (XEXP (x, 0), temp);
3430 emit_move_insn (temp, val);
3432 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3436 if (constant_term != const0_rtx)
3437 x = gen_rtx_PLUS (Pmode, x, constant_term);
3442 /* Try a machine-dependent way of reloading an illegitimate address AD
3443 operand. If we find one, push the reload and and return the new address.
3445 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3446 and TYPE is the reload type of the current reload. */
3449 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3450 int opnum, int type)
3452 if (!optimize || TARGET_LONG_DISPLACEMENT)
3455 if (GET_CODE (ad) == PLUS)
3457 rtx tem = simplify_binary_operation (PLUS, Pmode,
3458 XEXP (ad, 0), XEXP (ad, 1));
3463 if (GET_CODE (ad) == PLUS
3464 && GET_CODE (XEXP (ad, 0)) == REG
3465 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3466 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3468 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3469 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3472 cst = GEN_INT (upper);
3473 if (!legitimate_reload_constant_p (cst))
3474 cst = force_const_mem (Pmode, cst);
3476 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3477 new = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3479 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3480 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3481 opnum, (enum reload_type) type);
3488 /* Emit code to move LEN bytes from DST to SRC. */
3491 s390_expand_movmem (rtx dst, rtx src, rtx len)
3493 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3495 if (INTVAL (len) > 0)
3496 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3499 else if (TARGET_MVCLE)
3501 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3506 rtx dst_addr, src_addr, count, blocks, temp;
3507 rtx loop_start_label = gen_label_rtx ();
3508 rtx loop_end_label = gen_label_rtx ();
3509 rtx end_label = gen_label_rtx ();
3510 enum machine_mode mode;
3512 mode = GET_MODE (len);
3513 if (mode == VOIDmode)
3516 dst_addr = gen_reg_rtx (Pmode);
3517 src_addr = gen_reg_rtx (Pmode);
3518 count = gen_reg_rtx (mode);
3519 blocks = gen_reg_rtx (mode);
3521 convert_move (count, len, 1);
3522 emit_cmp_and_jump_insns (count, const0_rtx,
3523 EQ, NULL_RTX, mode, 1, end_label);
3525 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3526 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3527 dst = change_address (dst, VOIDmode, dst_addr);
3528 src = change_address (src, VOIDmode, src_addr);
3530 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3532 emit_move_insn (count, temp);
3534 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3536 emit_move_insn (blocks, temp);
3538 emit_cmp_and_jump_insns (blocks, const0_rtx,
3539 EQ, NULL_RTX, mode, 1, loop_end_label);
3541 emit_label (loop_start_label);
3543 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3544 s390_load_address (dst_addr,
3545 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3546 s390_load_address (src_addr,
3547 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
3549 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3551 emit_move_insn (blocks, temp);
3553 emit_cmp_and_jump_insns (blocks, const0_rtx,
3554 EQ, NULL_RTX, mode, 1, loop_end_label);
3556 emit_jump (loop_start_label);
3557 emit_label (loop_end_label);
3559 emit_insn (gen_movmem_short (dst, src,
3560 convert_to_mode (Pmode, count, 1)));
3561 emit_label (end_label);
3565 /* Emit code to set LEN bytes at DST to VAL.
3566 Make use of clrmem if VAL is zero. */
3569 s390_expand_setmem (rtx dst, rtx len, rtx val)
3571 gcc_assert (GET_CODE (len) != CONST_INT || INTVAL (len) > 0);
3572 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
3574 if (GET_CODE (len) == CONST_INT && INTVAL (len) <= 257)
3576 if (val == const0_rtx && INTVAL (len) <= 256)
3577 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
3580 /* Initialize memory by storing the first byte. */
3581 emit_move_insn (adjust_address (dst, QImode, 0), val);
3583 if (INTVAL (len) > 1)
3585 /* Initiate 1 byte overlap move.
3586 The first byte of DST is propagated through DSTP1.
3587 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3588 DST is set to size 1 so the rest of the memory location
3589 does not count as source operand. */
3590 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
3591 set_mem_size (dst, const1_rtx);
3593 emit_insn (gen_movmem_short (dstp1, dst,
3594 GEN_INT (INTVAL (len) - 2)));
3599 else if (TARGET_MVCLE)
3601 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
3602 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
3607 rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
3608 rtx loop_start_label = gen_label_rtx ();
3609 rtx loop_end_label = gen_label_rtx ();
3610 rtx end_label = gen_label_rtx ();
3611 enum machine_mode mode;
3613 mode = GET_MODE (len);
3614 if (mode == VOIDmode)
3617 dst_addr = gen_reg_rtx (Pmode);
3618 src_addr = gen_reg_rtx (Pmode);
3619 count = gen_reg_rtx (mode);
3620 blocks = gen_reg_rtx (mode);
3622 convert_move (count, len, 1);
3623 emit_cmp_and_jump_insns (count, const0_rtx,
3624 EQ, NULL_RTX, mode, 1, end_label);
3626 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3627 dst = change_address (dst, VOIDmode, dst_addr);
3629 if (val == const0_rtx)
3630 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3633 dstp1 = adjust_address (dst, VOIDmode, 1);
3634 set_mem_size (dst, const1_rtx);
3636 /* Initialize memory by storing the first byte. */
3637 emit_move_insn (adjust_address (dst, QImode, 0), val);
3639 /* If count is 1 we are done. */
3640 emit_cmp_and_jump_insns (count, const1_rtx,
3641 EQ, NULL_RTX, mode, 1, end_label);
3643 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1, 0);
3646 emit_move_insn (count, temp);
3648 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3650 emit_move_insn (blocks, temp);
3652 emit_cmp_and_jump_insns (blocks, const0_rtx,
3653 EQ, NULL_RTX, mode, 1, loop_end_label);
3655 emit_label (loop_start_label);
3657 if (val == const0_rtx)
3658 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
3660 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
3661 s390_load_address (dst_addr,
3662 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3664 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3666 emit_move_insn (blocks, temp);
3668 emit_cmp_and_jump_insns (blocks, const0_rtx,
3669 EQ, NULL_RTX, mode, 1, loop_end_label);
3671 emit_jump (loop_start_label);
3672 emit_label (loop_end_label);
3674 if (val == const0_rtx)
3675 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
3677 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
3678 emit_label (end_label);
3682 /* Emit code to compare LEN bytes at OP0 with those at OP1,
3683 and return the result in TARGET. */
3686 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
3688 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
3691 /* As the result of CMPINT is inverted compared to what we need,
3692 we have to swap the operands. */
3693 tmp = op0; op0 = op1; op1 = tmp;
3695 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3697 if (INTVAL (len) > 0)
3699 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
3700 emit_insn (gen_cmpint (target, ccreg));
3703 emit_move_insn (target, const0_rtx);
3705 else if (TARGET_MVCLE)
3707 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
3708 emit_insn (gen_cmpint (target, ccreg));
3712 rtx addr0, addr1, count, blocks, temp;
3713 rtx loop_start_label = gen_label_rtx ();
3714 rtx loop_end_label = gen_label_rtx ();
3715 rtx end_label = gen_label_rtx ();
3716 enum machine_mode mode;
3718 mode = GET_MODE (len);
3719 if (mode == VOIDmode)
3722 addr0 = gen_reg_rtx (Pmode);
3723 addr1 = gen_reg_rtx (Pmode);
3724 count = gen_reg_rtx (mode);
3725 blocks = gen_reg_rtx (mode);
3727 convert_move (count, len, 1);
3728 emit_cmp_and_jump_insns (count, const0_rtx,
3729 EQ, NULL_RTX, mode, 1, end_label);
3731 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
3732 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
3733 op0 = change_address (op0, VOIDmode, addr0);
3734 op1 = change_address (op1, VOIDmode, addr1);
3736 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3738 emit_move_insn (count, temp);
3740 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3742 emit_move_insn (blocks, temp);
3744 emit_cmp_and_jump_insns (blocks, const0_rtx,
3745 EQ, NULL_RTX, mode, 1, loop_end_label);
3747 emit_label (loop_start_label);
3749 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
3750 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
3751 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
3752 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
3753 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
3754 emit_jump_insn (temp);
3756 s390_load_address (addr0,
3757 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
3758 s390_load_address (addr1,
3759 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
3761 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3763 emit_move_insn (blocks, temp);
3765 emit_cmp_and_jump_insns (blocks, const0_rtx,
3766 EQ, NULL_RTX, mode, 1, loop_end_label);
3768 emit_jump (loop_start_label);
3769 emit_label (loop_end_label);
3771 emit_insn (gen_cmpmem_short (op0, op1,
3772 convert_to_mode (Pmode, count, 1)));
3773 emit_label (end_label);
3775 emit_insn (gen_cmpint (target, ccreg));
3780 /* Expand conditional increment or decrement using alc/slb instructions.
3781 Should generate code setting DST to either SRC or SRC + INCREMENT,
3782 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
3783 Returns true if successful, false otherwise.
3785 That makes it possible to implement some if-constructs without jumps e.g.:
3786 (borrow = CC0 | CC1 and carry = CC2 | CC3)
3787 unsigned int a, b, c;
3788 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
3789 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
3790 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
3791 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
3793 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
3794 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
3795 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
3796 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
3797 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
3800 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
3801 rtx dst, rtx src, rtx increment)
3803 enum machine_mode cmp_mode;
3804 enum machine_mode cc_mode;
3810 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
3811 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
3813 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
3814 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
3819 /* Try ADD LOGICAL WITH CARRY. */
3820 if (increment == const1_rtx)
3822 /* Determine CC mode to use. */
3823 if (cmp_code == EQ || cmp_code == NE)
3825 if (cmp_op1 != const0_rtx)
3827 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3828 NULL_RTX, 0, OPTAB_WIDEN);
3829 cmp_op1 = const0_rtx;
3832 cmp_code = cmp_code == EQ ? LEU : GTU;
3835 if (cmp_code == LTU || cmp_code == LEU)
3840 cmp_code = swap_condition (cmp_code);
3857 /* Emit comparison instruction pattern. */
3858 if (!register_operand (cmp_op0, cmp_mode))
3859 cmp_op0 = force_reg (cmp_mode, cmp_op0);
3861 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3862 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3863 /* We use insn_invalid_p here to add clobbers if required. */
3864 ret = insn_invalid_p (emit_insn (insn));
3867 /* Emit ALC instruction pattern. */
3868 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3869 gen_rtx_REG (cc_mode, CC_REGNUM),
3872 if (src != const0_rtx)
3874 if (!register_operand (src, GET_MODE (dst)))
3875 src = force_reg (GET_MODE (dst), src);
3877 src = gen_rtx_PLUS (GET_MODE (dst), src, const0_rtx);
3878 op_res = gen_rtx_PLUS (GET_MODE (dst), src, op_res);
3881 p = rtvec_alloc (2);
3883 gen_rtx_SET (VOIDmode, dst, op_res);
3885 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3886 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3891 /* Try SUBTRACT LOGICAL WITH BORROW. */
3892 if (increment == constm1_rtx)
3894 /* Determine CC mode to use. */
3895 if (cmp_code == EQ || cmp_code == NE)
3897 if (cmp_op1 != const0_rtx)
3899 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3900 NULL_RTX, 0, OPTAB_WIDEN);
3901 cmp_op1 = const0_rtx;
3904 cmp_code = cmp_code == EQ ? LEU : GTU;
3907 if (cmp_code == GTU || cmp_code == GEU)
3912 cmp_code = swap_condition (cmp_code);
3929 /* Emit comparison instruction pattern. */
3930 if (!register_operand (cmp_op0, cmp_mode))
3931 cmp_op0 = force_reg (cmp_mode, cmp_op0);
3933 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3934 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3935 /* We use insn_invalid_p here to add clobbers if required. */
3936 ret = insn_invalid_p (emit_insn (insn));
3939 /* Emit SLB instruction pattern. */
3940 if (!register_operand (src, GET_MODE (dst)))
3941 src = force_reg (GET_MODE (dst), src);
3943 op_res = gen_rtx_MINUS (GET_MODE (dst),
3944 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
3945 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3946 gen_rtx_REG (cc_mode, CC_REGNUM),
3948 p = rtvec_alloc (2);
3950 gen_rtx_SET (VOIDmode, dst, op_res);
3952 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3953 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3961 /* Expand code for the insv template. Return true if successful, false else. */
3964 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
3966 int bitsize = INTVAL (op1);
3967 int bitpos = INTVAL (op2);
3969 /* We need byte alignment. */
3970 if (bitsize % BITS_PER_UNIT)
3974 && memory_operand (dest, VOIDmode)
3975 && (register_operand (src, word_mode)
3976 || const_int_operand (src, VOIDmode)))
3978 /* Emit standard pattern if possible. */
3979 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
3980 if (GET_MODE_BITSIZE (mode) == bitsize)
3981 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
3983 /* (set (ze (mem)) (const_int)). */
3984 else if (const_int_operand (src, VOIDmode))
3986 int size = bitsize / BITS_PER_UNIT;
3987 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
3988 GET_MODE_SIZE (word_mode) - size);
3990 dest = adjust_address (dest, BLKmode, 0);
3991 set_mem_size (dest, GEN_INT (size));
3992 s390_expand_movmem (dest, src_mem, GEN_INT (size));
3995 /* (set (ze (mem)) (reg)). */
3996 else if (register_operand (src, word_mode))
3998 if (bitsize <= GET_MODE_BITSIZE (SImode))
3999 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4003 /* Emit st,stcmh sequence. */
4004 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
4005 int size = stcmh_width / BITS_PER_UNIT;
4007 emit_move_insn (adjust_address (dest, SImode, size),
4008 gen_lowpart (SImode, src));
4009 set_mem_size (dest, GEN_INT (size));
4010 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
4011 (stcmh_width), const0_rtx),
4012 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
4013 (GET_MODE_BITSIZE (SImode))));
4022 /* (set (ze (reg)) (const_int)). */
4024 && register_operand (dest, word_mode)
4025 && (bitpos % 16) == 0
4026 && (bitsize % 16) == 0
4027 && const_int_operand (src, VOIDmode))
4029 HOST_WIDE_INT val = INTVAL (src);
4030 int regpos = bitpos + bitsize;
4032 while (regpos > bitpos)
4034 enum machine_mode putmode;
4037 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4042 putsize = GET_MODE_BITSIZE (putmode);
4044 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4047 gen_int_mode (val, putmode));
4050 gcc_assert (regpos == bitpos);
4057 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4058 register that holds VAL of mode MODE shifted by COUNT bits. */
4061 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4063 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4064 NULL_RTX, 1, OPTAB_DIRECT);
4065 return expand_simple_binop (SImode, ASHIFT, val, count,
4066 NULL_RTX, 1, OPTAB_DIRECT);
4069 /* Structure to hold the initial parameters for a compare_and_swap operation
4070 in HImode and QImode. */
4072 struct alignment_context
4074 rtx memsi; /* SI aligned memory location. */
4075 rtx shift; /* Bit offset with regard to lsb. */
4076 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4077 rtx modemaski; /* ~modemask */
4078 bool aligned; /* True if memory is aligned, false else. */
4081 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4082 structure AC for transparent simplifying, if the memory alignment is known
4083 to be at least 32bit. MEM is the memory location for the actual operation
4084 and MODE its mode. */
4087 init_alignment_context (struct alignment_context *ac, rtx mem,
4088 enum machine_mode mode)
4090 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4091 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4094 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4097 /* Alignment is unknown. */
4098 rtx byteoffset, addr, align;
4100 /* Force the address into a register. */
4101 addr = force_reg (Pmode, XEXP (mem, 0));
4103 /* Align it to SImode. */
4104 align = expand_simple_binop (Pmode, AND, addr,
4105 GEN_INT (-GET_MODE_SIZE (SImode)),
4106 NULL_RTX, 1, OPTAB_DIRECT);
4108 ac->memsi = gen_rtx_MEM (SImode, align);
4109 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4110 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4111 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4113 /* Calculate shiftcount. */
4114 byteoffset = expand_simple_binop (Pmode, AND, addr,
4115 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4116 NULL_RTX, 1, OPTAB_DIRECT);
4117 /* As we already have some offset, evaluate the remaining distance. */
4118 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4119 NULL_RTX, 1, OPTAB_DIRECT);
4122 /* Shift is the byte count, but we need the bitcount. */
4123 ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT),
4124 NULL_RTX, 1, OPTAB_DIRECT);
4125 /* Calculate masks. */
4126 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4127 GEN_INT (GET_MODE_MASK (mode)), ac->shift,
4128 NULL_RTX, 1, OPTAB_DIRECT);
4129 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1);
4132 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4133 the memory location, CMP the old value to compare MEM with and NEW the value
4134 to set if CMP == MEM.
4135 CMP is never in memory for compare_and_swap_cc because
4136 expand_bool_compare_and_swap puts it into a register for later compare. */
4139 s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new)
4141 struct alignment_context ac;
4142 rtx cmpv, newv, val, resv, cc;
4143 rtx res = gen_reg_rtx (SImode);
4144 rtx csloop = gen_label_rtx ();
4145 rtx csend = gen_label_rtx ();
4147 gcc_assert (register_operand (target, VOIDmode));
4148 gcc_assert (MEM_P (mem));
4150 init_alignment_context (&ac, mem, mode);
4152 /* Shift the values to the correct bit positions. */
4153 if (!(ac.aligned && MEM_P (cmp)))
4154 cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift);
4155 if (!(ac.aligned && MEM_P (new)))
4156 new = s390_expand_mask_and_shift (new, mode, ac.shift);
4158 /* Load full word. Subsequent loads are performed by CS. */
4159 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4160 NULL_RTX, 1, OPTAB_DIRECT);
4162 /* Start CS loop. */
4163 emit_label (csloop);
4164 /* val = "<mem>00..0<mem>"
4165 * cmp = "00..0<cmp>00..0"
4166 * new = "00..0<new>00..0"
4169 /* Patch cmp and new with val at correct position. */
4170 if (ac.aligned && MEM_P (cmp))
4172 cmpv = force_reg (SImode, val);
4173 store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp);
4176 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val,
4177 NULL_RTX, 1, OPTAB_DIRECT));
4178 if (ac.aligned && MEM_P (new))
4180 newv = force_reg (SImode, val);
4181 store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new);
4184 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new, val,
4185 NULL_RTX, 1, OPTAB_DIRECT));
4187 /* Emit compare_and_swap pattern. */
4188 emit_insn (gen_sync_compare_and_swap_ccsi (res, ac.memsi, cmpv, newv));
4190 /* Jump to end if we're done (likely?). */
4191 s390_emit_jump (csend, s390_emit_compare (EQ, cmpv, ac.memsi));
4193 /* Check for changes outside mode. */
4194 resv = expand_simple_binop (SImode, AND, res, ac.modemaski,
4195 NULL_RTX, 1, OPTAB_DIRECT);
4196 cc = s390_emit_compare (NE, resv, val);
4197 emit_move_insn (val, resv);
4198 /* Loop internal if so. */
4199 s390_emit_jump (csloop, cc);
4203 /* Return the correct part of the bitfield. */
4204 convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4205 NULL_RTX, 1, OPTAB_DIRECT), 1);
4208 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4209 and VAL the value to play with. If AFTER is true then store the the value
4210 MEM holds after the operation, if AFTER is false then store the value MEM
4211 holds before the operation. If TARGET is zero then discard that value, else
4212 store it to TARGET. */
4215 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4216 rtx target, rtx mem, rtx val, bool after)
4218 struct alignment_context ac;
4220 rtx new = gen_reg_rtx (SImode);
4221 rtx orig = gen_reg_rtx (SImode);
4222 rtx csloop = gen_label_rtx ();
4224 gcc_assert (!target || register_operand (target, VOIDmode));
4225 gcc_assert (MEM_P (mem));
4227 init_alignment_context (&ac, mem, mode);
4229 /* Shift val to the correct bit positions.
4230 Preserve "icm", but prevent "ex icm". */
4231 if (!(ac.aligned && code == SET && MEM_P (val)))
4232 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4234 /* Further preparation insns. */
4235 if (code == PLUS || code == MINUS)
4236 emit_move_insn (orig, val);
4237 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4238 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4239 NULL_RTX, 1, OPTAB_DIRECT);
4241 /* Load full word. Subsequent loads are performed by CS. */
4242 cmp = force_reg (SImode, ac.memsi);
4244 /* Start CS loop. */
4245 emit_label (csloop);
4246 emit_move_insn (new, cmp);
4248 /* Patch new with val at correct position. */
4253 val = expand_simple_binop (SImode, code, new, orig,
4254 NULL_RTX, 1, OPTAB_DIRECT);
4255 val = expand_simple_binop (SImode, AND, val, ac.modemask,
4256 NULL_RTX, 1, OPTAB_DIRECT);
4259 if (ac.aligned && MEM_P (val))
4260 store_bit_field (new, GET_MODE_BITSIZE (mode), 0, SImode, val);
4263 new = expand_simple_binop (SImode, AND, new, ac.modemaski,
4264 NULL_RTX, 1, OPTAB_DIRECT);
4265 new = expand_simple_binop (SImode, IOR, new, val,
4266 NULL_RTX, 1, OPTAB_DIRECT);
4272 new = expand_simple_binop (SImode, code, new, val,
4273 NULL_RTX, 1, OPTAB_DIRECT);
4275 case MULT: /* NAND */
4276 new = expand_simple_binop (SImode, XOR, new, ac.modemask,
4277 NULL_RTX, 1, OPTAB_DIRECT);
4278 new = expand_simple_binop (SImode, AND, new, val,
4279 NULL_RTX, 1, OPTAB_DIRECT);
4284 /* Emit compare_and_swap pattern. */
4285 emit_insn (gen_sync_compare_and_swap_ccsi (cmp, ac.memsi, cmp, new));
4287 /* Loop until swapped (unlikely?). */
4288 s390_emit_jump (csloop, gen_rtx_fmt_ee (NE, CCZ1mode,
4289 gen_rtx_REG (CCZ1mode, CC_REGNUM),
4292 /* Return the correct part of the bitfield. */
4294 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
4295 after ? new : cmp, ac.shift,
4296 NULL_RTX, 1, OPTAB_DIRECT), 1);
4299 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4300 We need to emit DTP-relative relocations. */
4302 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
4305 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
4310 fputs ("\t.long\t", file);
4313 fputs ("\t.quad\t", file);
4318 output_addr_const (file, x);
4319 fputs ("@DTPOFF", file);
4322 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4323 /* Implement TARGET_MANGLE_FUNDAMENTAL_TYPE. */
4326 s390_mangle_fundamental_type (tree type)
4328 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
4329 && TARGET_LONG_DOUBLE_128)
4332 /* For all other types, use normal C++ mangling. */
4337 /* In the name of slightly smaller debug output, and to cater to
4338 general assembler lossage, recognize various UNSPEC sequences
4339 and turn them back into a direct symbol reference. */
4342 s390_delegitimize_address (rtx orig_x)
4346 if (GET_CODE (x) != MEM)
4350 if (GET_CODE (x) == PLUS
4351 && GET_CODE (XEXP (x, 1)) == CONST
4352 && GET_CODE (XEXP (x, 0)) == REG
4353 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
4355 y = XEXP (XEXP (x, 1), 0);
4356 if (GET_CODE (y) == UNSPEC
4357 && XINT (y, 1) == UNSPEC_GOT)
4358 return XVECEXP (y, 0, 0);
4362 if (GET_CODE (x) == CONST)
4365 if (GET_CODE (y) == UNSPEC
4366 && XINT (y, 1) == UNSPEC_GOTENT)
4367 return XVECEXP (y, 0, 0);
4374 /* Output operand OP to stdio stream FILE.
4375 OP is an address (register + offset) which is not used to address data;
4376 instead the rightmost bits are interpreted as the value. */
4379 print_shift_count_operand (FILE *file, rtx op)
4381 HOST_WIDE_INT offset;
4384 /* Extract base register and offset. */
4385 if (!s390_decompose_shift_count (op, &base, &offset))
4391 gcc_assert (GET_CODE (base) == REG);
4392 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
4393 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
4396 /* Offsets are constricted to twelve bits. */
4397 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4399 fprintf (file, "(%s)", reg_names[REGNO (base)]);
4402 /* See 'get_some_local_dynamic_name'. */
4405 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4409 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4411 x = get_pool_constant (x);
4412 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4415 if (GET_CODE (x) == SYMBOL_REF
4416 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4418 cfun->machine->some_ld_name = XSTR (x, 0);
4425 /* Locate some local-dynamic symbol still in use by this function
4426 so that we can print its name in local-dynamic base patterns. */
4429 get_some_local_dynamic_name (void)
4433 if (cfun->machine->some_ld_name)
4434 return cfun->machine->some_ld_name;
4436 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4438 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4439 return cfun->machine->some_ld_name;
4444 /* Output machine-dependent UNSPECs occurring in address constant X
4445 in assembler syntax to stdio stream FILE. Returns true if the
4446 constant X could be recognized, false otherwise. */
4449 s390_output_addr_const_extra (FILE *file, rtx x)
4451 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4452 switch (XINT (x, 1))
4455 output_addr_const (file, XVECEXP (x, 0, 0));
4456 fprintf (file, "@GOTENT");
4459 output_addr_const (file, XVECEXP (x, 0, 0));
4460 fprintf (file, "@GOT");
4463 output_addr_const (file, XVECEXP (x, 0, 0));
4464 fprintf (file, "@GOTOFF");
4467 output_addr_const (file, XVECEXP (x, 0, 0));
4468 fprintf (file, "@PLT");
4471 output_addr_const (file, XVECEXP (x, 0, 0));
4472 fprintf (file, "@PLTOFF");
4475 output_addr_const (file, XVECEXP (x, 0, 0));
4476 fprintf (file, "@TLSGD");
4479 assemble_name (file, get_some_local_dynamic_name ());
4480 fprintf (file, "@TLSLDM");
4483 output_addr_const (file, XVECEXP (x, 0, 0));
4484 fprintf (file, "@DTPOFF");
4487 output_addr_const (file, XVECEXP (x, 0, 0));
4488 fprintf (file, "@NTPOFF");
4490 case UNSPEC_GOTNTPOFF:
4491 output_addr_const (file, XVECEXP (x, 0, 0));
4492 fprintf (file, "@GOTNTPOFF");
4494 case UNSPEC_INDNTPOFF:
4495 output_addr_const (file, XVECEXP (x, 0, 0));
4496 fprintf (file, "@INDNTPOFF");
4503 /* Output address operand ADDR in assembler syntax to
4504 stdio stream FILE. */
4507 print_operand_address (FILE *file, rtx addr)
4509 struct s390_address ad;
4511 if (!s390_decompose_address (addr, &ad)
4512 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
4513 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
4514 output_operand_lossage ("cannot decompose address");
4517 output_addr_const (file, ad.disp);
4519 fprintf (file, "0");
4521 if (ad.base && ad.indx)
4522 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
4523 reg_names[REGNO (ad.base)]);
4525 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4528 /* Output operand X in assembler syntax to stdio stream FILE.
4529 CODE specified the format flag. The following format flags
4532 'C': print opcode suffix for branch condition.
4533 'D': print opcode suffix for inverse branch condition.
4534 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4535 'G': print the size of the operand in bytes.
4536 'O': print only the displacement of a memory reference.
4537 'R': print only the base register of a memory reference.
4538 'S': print S-type memory reference (base+displacement).
4539 'N': print the second word of a DImode operand.
4540 'M': print the second word of a TImode operand.
4541 'Y': print shift count operand.
4543 'b': print integer X as if it's an unsigned byte.
4544 'x': print integer X as if it's an unsigned halfword.
4545 'h': print integer X as if it's a signed halfword.
4546 'i': print the first nonzero HImode part of X.
4547 'j': print the first HImode part unequal to -1 of X.
4548 'k': print the first nonzero SImode part of X.
4549 'm': print the first SImode part unequal to -1 of X.
4550 'o': print integer X as if it's an unsigned 32bit word. */
4553 print_operand (FILE *file, rtx x, int code)
4558 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
4562 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
4566 if (GET_CODE (x) == SYMBOL_REF)
4568 fprintf (file, "%s", ":tls_load:");
4569 output_addr_const (file, x);
4571 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
4573 fprintf (file, "%s", ":tls_gdcall:");
4574 output_addr_const (file, XVECEXP (x, 0, 0));
4576 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
4578 fprintf (file, "%s", ":tls_ldcall:");
4579 assemble_name (file, get_some_local_dynamic_name ());
4586 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
4591 struct s390_address ad;
4594 gcc_assert (GET_CODE (x) == MEM);
4595 ret = s390_decompose_address (XEXP (x, 0), &ad);
4597 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
4598 gcc_assert (!ad.indx);
4601 output_addr_const (file, ad.disp);
4603 fprintf (file, "0");
4609 struct s390_address ad;
4612 gcc_assert (GET_CODE (x) == MEM);
4613 ret = s390_decompose_address (XEXP (x, 0), &ad);
4615 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
4616 gcc_assert (!ad.indx);
4619 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
4621 fprintf (file, "0");
4627 struct s390_address ad;
4630 gcc_assert (GET_CODE (x) == MEM);
4631 ret = s390_decompose_address (XEXP (x, 0), &ad);
4633 gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base)));
4634 gcc_assert (!ad.indx);
4637 output_addr_const (file, ad.disp);
4639 fprintf (file, "0");
4642 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4647 if (GET_CODE (x) == REG)
4648 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4649 else if (GET_CODE (x) == MEM)
4650 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
4656 if (GET_CODE (x) == REG)
4657 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4658 else if (GET_CODE (x) == MEM)
4659 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
4665 print_shift_count_operand (file, x);
4669 switch (GET_CODE (x))
4672 fprintf (file, "%s", reg_names[REGNO (x)]);
4676 output_address (XEXP (x, 0));
4683 output_addr_const (file, x);
4688 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
4689 else if (code == 'x')
4690 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
4691 else if (code == 'h')
4692 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
4693 else if (code == 'i')
4694 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4695 s390_extract_part (x, HImode, 0));
4696 else if (code == 'j')
4697 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4698 s390_extract_part (x, HImode, -1));
4699 else if (code == 'k')
4700 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4701 s390_extract_part (x, SImode, 0));
4702 else if (code == 'm')
4703 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4704 s390_extract_part (x, SImode, -1));
4705 else if (code == 'o')
4706 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
4708 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
4712 gcc_assert (GET_MODE (x) == VOIDmode);
4714 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
4715 else if (code == 'x')
4716 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
4717 else if (code == 'h')
4718 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
4724 fatal_insn ("UNKNOWN in print_operand !?", x);
4729 /* Target hook for assembling integer objects. We need to define it
4730 here to work a round a bug in some versions of GAS, which couldn't
4731 handle values smaller than INT_MIN when printed in decimal. */
4734 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
4736 if (size == 8 && aligned_p
4737 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
4739 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
4743 return default_assemble_integer (x, size, aligned_p);
4746 /* Returns true if register REGNO is used for forming
4747 a memory address in expression X. */
4750 reg_used_in_mem_p (int regno, rtx x)
4752 enum rtx_code code = GET_CODE (x);
4758 if (refers_to_regno_p (regno, regno+1,
4762 else if (code == SET
4763 && GET_CODE (SET_DEST (x)) == PC)
4765 if (refers_to_regno_p (regno, regno+1,
4770 fmt = GET_RTX_FORMAT (code);
4771 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4774 && reg_used_in_mem_p (regno, XEXP (x, i)))
4777 else if (fmt[i] == 'E')
4778 for (j = 0; j < XVECLEN (x, i); j++)
4779 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
4785 /* Returns true if expression DEP_RTX sets an address register
4786 used by instruction INSN to address memory. */
4789 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
4793 if (GET_CODE (dep_rtx) == INSN)
4794 dep_rtx = PATTERN (dep_rtx);
4796 if (GET_CODE (dep_rtx) == SET)
4798 target = SET_DEST (dep_rtx);
4799 if (GET_CODE (target) == STRICT_LOW_PART)
4800 target = XEXP (target, 0);
4801 while (GET_CODE (target) == SUBREG)
4802 target = SUBREG_REG (target);
4804 if (GET_CODE (target) == REG)
4806 int regno = REGNO (target);
4808 if (s390_safe_attr_type (insn) == TYPE_LA)
4810 pat = PATTERN (insn);
4811 if (GET_CODE (pat) == PARALLEL)
4813 gcc_assert (XVECLEN (pat, 0) == 2);
4814 pat = XVECEXP (pat, 0, 0);
4816 gcc_assert (GET_CODE (pat) == SET);
4817 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
4819 else if (get_attr_atype (insn) == ATYPE_AGEN)
4820 return reg_used_in_mem_p (regno, PATTERN (insn));
4826 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
4829 s390_agen_dep_p (rtx dep_insn, rtx insn)
4831 rtx dep_rtx = PATTERN (dep_insn);
4834 if (GET_CODE (dep_rtx) == SET
4835 && addr_generation_dependency_p (dep_rtx, insn))
4837 else if (GET_CODE (dep_rtx) == PARALLEL)
4839 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
4841 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
4848 /* A C statement (sans semicolon) to update the integer scheduling priority
4849 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
4850 reduce the priority to execute INSN later. Do not define this macro if
4851 you do not need to adjust the scheduling priorities of insns.
4853 A STD instruction should be scheduled earlier,
4854 in order to use the bypass. */
4857 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
4859 if (! INSN_P (insn))
4862 if (s390_tune != PROCESSOR_2084_Z990
4863 && s390_tune != PROCESSOR_2094_Z9_109)
4866 switch (s390_safe_attr_type (insn))
4870 priority = priority << 3;
4874 priority = priority << 1;
4882 /* The number of instructions that can be issued per cycle. */
4885 s390_issue_rate (void)
4887 if (s390_tune == PROCESSOR_2084_Z990
4888 || s390_tune == PROCESSOR_2094_Z9_109)
4894 s390_first_cycle_multipass_dfa_lookahead (void)
4900 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
4901 Fix up MEMs as required. */
4904 annotate_constant_pool_refs (rtx *x)
4909 gcc_assert (GET_CODE (*x) != SYMBOL_REF
4910 || !CONSTANT_POOL_ADDRESS_P (*x));
4912 /* Literal pool references can only occur inside a MEM ... */
4913 if (GET_CODE (*x) == MEM)
4915 rtx memref = XEXP (*x, 0);
4917 if (GET_CODE (memref) == SYMBOL_REF
4918 && CONSTANT_POOL_ADDRESS_P (memref))
4920 rtx base = cfun->machine->base_reg;
4921 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
4924 *x = replace_equiv_address (*x, addr);
4928 if (GET_CODE (memref) == CONST
4929 && GET_CODE (XEXP (memref, 0)) == PLUS
4930 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
4931 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
4932 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
4934 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
4935 rtx sym = XEXP (XEXP (memref, 0), 0);
4936 rtx base = cfun->machine->base_reg;
4937 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4940 *x = replace_equiv_address (*x, plus_constant (addr, off));
4945 /* ... or a load-address type pattern. */
4946 if (GET_CODE (*x) == SET)
4948 rtx addrref = SET_SRC (*x);
4950 if (GET_CODE (addrref) == SYMBOL_REF
4951 && CONSTANT_POOL_ADDRESS_P (addrref))
4953 rtx base = cfun->machine->base_reg;
4954 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
4957 SET_SRC (*x) = addr;
4961 if (GET_CODE (addrref) == CONST
4962 && GET_CODE (XEXP (addrref, 0)) == PLUS
4963 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
4964 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
4965 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
4967 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
4968 rtx sym = XEXP (XEXP (addrref, 0), 0);
4969 rtx base = cfun->machine->base_reg;
4970 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4973 SET_SRC (*x) = plus_constant (addr, off);
4978 /* Annotate LTREL_BASE as well. */
4979 if (GET_CODE (*x) == UNSPEC
4980 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
4982 rtx base = cfun->machine->base_reg;
4983 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
4988 fmt = GET_RTX_FORMAT (GET_CODE (*x));
4989 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
4993 annotate_constant_pool_refs (&XEXP (*x, i));
4995 else if (fmt[i] == 'E')
4997 for (j = 0; j < XVECLEN (*x, i); j++)
4998 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5003 /* Split all branches that exceed the maximum distance.
5004 Returns true if this created a new literal pool entry. */
5007 s390_split_branches (void)
5009 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5010 int new_literal = 0, ret;
5011 rtx insn, pat, tmp, target;
5014 /* We need correct insn addresses. */
5016 shorten_branches (get_insns ());
5018 /* Find all branches that exceed 64KB, and split them. */
5020 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5022 if (GET_CODE (insn) != JUMP_INSN)
5025 pat = PATTERN (insn);
5026 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5027 pat = XVECEXP (pat, 0, 0);
5028 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
5031 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
5033 label = &SET_SRC (pat);
5035 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
5037 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
5038 label = &XEXP (SET_SRC (pat), 1);
5039 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
5040 label = &XEXP (SET_SRC (pat), 2);
5047 if (get_attr_length (insn) <= 4)
5050 /* We are going to use the return register as scratch register,
5051 make sure it will be saved/restored by the prologue/epilogue. */
5052 cfun_frame_layout.save_return_addr_p = 1;
5057 tmp = force_const_mem (Pmode, *label);
5058 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
5059 INSN_ADDRESSES_NEW (tmp, -1);
5060 annotate_constant_pool_refs (&PATTERN (tmp));
5067 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
5068 UNSPEC_LTREL_OFFSET);
5069 target = gen_rtx_CONST (Pmode, target);
5070 target = force_const_mem (Pmode, target);
5071 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
5072 INSN_ADDRESSES_NEW (tmp, -1);
5073 annotate_constant_pool_refs (&PATTERN (tmp));
5075 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
5076 cfun->machine->base_reg),
5078 target = gen_rtx_PLUS (Pmode, temp_reg, target);
5081 ret = validate_change (insn, label, target, 0);
5089 /* Find an annotated literal pool symbol referenced in RTX X,
5090 and store it at REF. Will abort if X contains references to
5091 more than one such pool symbol; multiple references to the same
5092 symbol are allowed, however.
5094 The rtx pointed to by REF must be initialized to NULL_RTX
5095 by the caller before calling this routine. */
5098 find_constant_pool_ref (rtx x, rtx *ref)
5103 /* Ignore LTREL_BASE references. */
5104 if (GET_CODE (x) == UNSPEC
5105 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5107 /* Likewise POOL_ENTRY insns. */
5108 if (GET_CODE (x) == UNSPEC_VOLATILE
5109 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
5112 gcc_assert (GET_CODE (x) != SYMBOL_REF
5113 || !CONSTANT_POOL_ADDRESS_P (x));
5115 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
5117 rtx sym = XVECEXP (x, 0, 0);
5118 gcc_assert (GET_CODE (sym) == SYMBOL_REF
5119 && CONSTANT_POOL_ADDRESS_P (sym));
5121 if (*ref == NULL_RTX)
5124 gcc_assert (*ref == sym);
5129 fmt = GET_RTX_FORMAT (GET_CODE (x));
5130 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5134 find_constant_pool_ref (XEXP (x, i), ref);
5136 else if (fmt[i] == 'E')
5138 for (j = 0; j < XVECLEN (x, i); j++)
5139 find_constant_pool_ref (XVECEXP (x, i, j), ref);
5144 /* Replace every reference to the annotated literal pool
5145 symbol REF in X by its base plus OFFSET. */
5148 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
5153 gcc_assert (*x != ref);
5155 if (GET_CODE (*x) == UNSPEC
5156 && XINT (*x, 1) == UNSPEC_LTREF
5157 && XVECEXP (*x, 0, 0) == ref)
5159 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
5163 if (GET_CODE (*x) == PLUS
5164 && GET_CODE (XEXP (*x, 1)) == CONST_INT
5165 && GET_CODE (XEXP (*x, 0)) == UNSPEC
5166 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
5167 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
5169 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
5170 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
5174 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5175 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5179 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
5181 else if (fmt[i] == 'E')
5183 for (j = 0; j < XVECLEN (*x, i); j++)
5184 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
5189 /* Check whether X contains an UNSPEC_LTREL_BASE.
5190 Return its constant pool symbol if found, NULL_RTX otherwise. */
5193 find_ltrel_base (rtx x)
5198 if (GET_CODE (x) == UNSPEC
5199 && XINT (x, 1) == UNSPEC_LTREL_BASE)
5200 return XVECEXP (x, 0, 0);
5202 fmt = GET_RTX_FORMAT (GET_CODE (x));
5203 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5207 rtx fnd = find_ltrel_base (XEXP (x, i));
5211 else if (fmt[i] == 'E')
5213 for (j = 0; j < XVECLEN (x, i); j++)
5215 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
5225 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5228 replace_ltrel_base (rtx *x)
5233 if (GET_CODE (*x) == UNSPEC
5234 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5236 *x = XVECEXP (*x, 0, 1);
5240 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5241 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5245 replace_ltrel_base (&XEXP (*x, i));
5247 else if (fmt[i] == 'E')
5249 for (j = 0; j < XVECLEN (*x, i); j++)
5250 replace_ltrel_base (&XVECEXP (*x, i, j));
5256 /* We keep a list of constants which we have to add to internal
5257 constant tables in the middle of large functions. */
5259 #define NR_C_MODES 8
5260 enum machine_mode constant_modes[NR_C_MODES] =
5271 struct constant *next;
5276 struct constant_pool
5278 struct constant_pool *next;
5283 struct constant *constants[NR_C_MODES];
5284 struct constant *execute;
5289 /* Allocate new constant_pool structure. */
5291 static struct constant_pool *
5292 s390_alloc_pool (void)
5294 struct constant_pool *pool;
5297 pool = (struct constant_pool *) xmalloc (sizeof *pool);
5299 for (i = 0; i < NR_C_MODES; i++)
5300 pool->constants[i] = NULL;
5302 pool->execute = NULL;
5303 pool->label = gen_label_rtx ();
5304 pool->first_insn = NULL_RTX;
5305 pool->pool_insn = NULL_RTX;
5306 pool->insns = BITMAP_ALLOC (NULL);
5312 /* Create new constant pool covering instructions starting at INSN
5313 and chain it to the end of POOL_LIST. */
5315 static struct constant_pool *
5316 s390_start_pool (struct constant_pool **pool_list, rtx insn)
5318 struct constant_pool *pool, **prev;
5320 pool = s390_alloc_pool ();
5321 pool->first_insn = insn;
5323 for (prev = pool_list; *prev; prev = &(*prev)->next)
5330 /* End range of instructions covered by POOL at INSN and emit
5331 placeholder insn representing the pool. */
5334 s390_end_pool (struct constant_pool *pool, rtx insn)
5336 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
5339 insn = get_last_insn ();
5341 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
5342 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5345 /* Add INSN to the list of insns covered by POOL. */
5348 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
5350 bitmap_set_bit (pool->insns, INSN_UID (insn));
5353 /* Return pool out of POOL_LIST that covers INSN. */
5355 static struct constant_pool *
5356 s390_find_pool (struct constant_pool *pool_list, rtx insn)
5358 struct constant_pool *pool;
5360 for (pool = pool_list; pool; pool = pool->next)
5361 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
5367 /* Add constant VAL of mode MODE to the constant pool POOL. */
5370 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
5375 for (i = 0; i < NR_C_MODES; i++)
5376 if (constant_modes[i] == mode)
5378 gcc_assert (i != NR_C_MODES);
5380 for (c = pool->constants[i]; c != NULL; c = c->next)
5381 if (rtx_equal_p (val, c->value))
5386 c = (struct constant *) xmalloc (sizeof *c);
5388 c->label = gen_label_rtx ();
5389 c->next = pool->constants[i];
5390 pool->constants[i] = c;
5391 pool->size += GET_MODE_SIZE (mode);
5395 /* Find constant VAL of mode MODE in the constant pool POOL.
5396 Return an RTX describing the distance from the start of
5397 the pool to the location of the new constant. */
5400 s390_find_constant (struct constant_pool *pool, rtx val,
5401 enum machine_mode mode)
5407 for (i = 0; i < NR_C_MODES; i++)
5408 if (constant_modes[i] == mode)
5410 gcc_assert (i != NR_C_MODES);
5412 for (c = pool->constants[i]; c != NULL; c = c->next)
5413 if (rtx_equal_p (val, c->value))
5418 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5419 gen_rtx_LABEL_REF (Pmode, pool->label));
5420 offset = gen_rtx_CONST (Pmode, offset);
5424 /* Check whether INSN is an execute. Return the label_ref to its
5425 execute target template if so, NULL_RTX otherwise. */
5428 s390_execute_label (rtx insn)
5430 if (GET_CODE (insn) == INSN
5431 && GET_CODE (PATTERN (insn)) == PARALLEL
5432 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5433 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5434 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5439 /* Add execute target for INSN to the constant pool POOL. */
5442 s390_add_execute (struct constant_pool *pool, rtx insn)
5446 for (c = pool->execute; c != NULL; c = c->next)
5447 if (INSN_UID (insn) == INSN_UID (c->value))
5452 c = (struct constant *) xmalloc (sizeof *c);
5454 c->label = gen_label_rtx ();
5455 c->next = pool->execute;
5461 /* Find execute target for INSN in the constant pool POOL.
5462 Return an RTX describing the distance from the start of
5463 the pool to the location of the execute target. */
5466 s390_find_execute (struct constant_pool *pool, rtx insn)
5471 for (c = pool->execute; c != NULL; c = c->next)
5472 if (INSN_UID (insn) == INSN_UID (c->value))
5477 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5478 gen_rtx_LABEL_REF (Pmode, pool->label));
5479 offset = gen_rtx_CONST (Pmode, offset);
5483 /* For an execute INSN, extract the execute target template. */
5486 s390_execute_target (rtx insn)
5488 rtx pattern = PATTERN (insn);
5489 gcc_assert (s390_execute_label (insn));
5491 if (XVECLEN (pattern, 0) == 2)
5493 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
5497 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
5500 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
5501 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
5503 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
5509 /* Indicate that INSN cannot be duplicated. This is the case for
5510 execute insns that carry a unique label. */
5513 s390_cannot_copy_insn_p (rtx insn)
5515 rtx label = s390_execute_label (insn);
5516 return label && label != const0_rtx;
5519 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5520 do not emit the pool base label. */
5523 s390_dump_pool (struct constant_pool *pool, bool remote_label)
5526 rtx insn = pool->pool_insn;
5529 /* Switch to rodata section. */
5530 if (TARGET_CPU_ZARCH)
5532 insn = emit_insn_after (gen_pool_section_start (), insn);
5533 INSN_ADDRESSES_NEW (insn, -1);
5536 /* Ensure minimum pool alignment. */
5537 if (TARGET_CPU_ZARCH)
5538 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
5540 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
5541 INSN_ADDRESSES_NEW (insn, -1);
5543 /* Emit pool base label. */
5546 insn = emit_label_after (pool->label, insn);
5547 INSN_ADDRESSES_NEW (insn, -1);
5550 /* Dump constants in descending alignment requirement order,
5551 ensuring proper alignment for every constant. */
5552 for (i = 0; i < NR_C_MODES; i++)
5553 for (c = pool->constants[i]; c; c = c->next)
5555 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
5556 rtx value = c->value;
5557 if (GET_CODE (value) == CONST
5558 && GET_CODE (XEXP (value, 0)) == UNSPEC
5559 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
5560 && XVECLEN (XEXP (value, 0), 0) == 1)
5562 value = gen_rtx_MINUS (Pmode, XVECEXP (XEXP (value, 0), 0, 0),
5563 gen_rtx_LABEL_REF (VOIDmode, pool->label));
5564 value = gen_rtx_CONST (VOIDmode, value);
5567 insn = emit_label_after (c->label, insn);
5568 INSN_ADDRESSES_NEW (insn, -1);
5570 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
5571 gen_rtvec (1, value),
5572 UNSPECV_POOL_ENTRY);
5573 insn = emit_insn_after (value, insn);
5574 INSN_ADDRESSES_NEW (insn, -1);
5577 /* Ensure minimum alignment for instructions. */
5578 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
5579 INSN_ADDRESSES_NEW (insn, -1);
5581 /* Output in-pool execute template insns. */
5582 for (c = pool->execute; c; c = c->next)
5584 insn = emit_label_after (c->label, insn);
5585 INSN_ADDRESSES_NEW (insn, -1);
5587 insn = emit_insn_after (s390_execute_target (c->value), insn);
5588 INSN_ADDRESSES_NEW (insn, -1);
5591 /* Switch back to previous section. */
5592 if (TARGET_CPU_ZARCH)
5594 insn = emit_insn_after (gen_pool_section_end (), insn);
5595 INSN_ADDRESSES_NEW (insn, -1);
5598 insn = emit_barrier_after (insn);
5599 INSN_ADDRESSES_NEW (insn, -1);
5601 /* Remove placeholder insn. */
5602 remove_insn (pool->pool_insn);
5605 /* Free all memory used by POOL. */
5608 s390_free_pool (struct constant_pool *pool)
5610 struct constant *c, *next;
5613 for (i = 0; i < NR_C_MODES; i++)
5614 for (c = pool->constants[i]; c; c = next)
5620 for (c = pool->execute; c; c = next)
5626 BITMAP_FREE (pool->insns);
5631 /* Collect main literal pool. Return NULL on overflow. */
5633 static struct constant_pool *
5634 s390_mainpool_start (void)
5636 struct constant_pool *pool;
5639 pool = s390_alloc_pool ();
5641 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5643 if (GET_CODE (insn) == INSN
5644 && GET_CODE (PATTERN (insn)) == SET
5645 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
5646 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
5648 gcc_assert (!pool->pool_insn);
5649 pool->pool_insn = insn;
5652 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5654 s390_add_execute (pool, insn);
5656 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5658 rtx pool_ref = NULL_RTX;
5659 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5662 rtx constant = get_pool_constant (pool_ref);
5663 enum machine_mode mode = get_pool_mode (pool_ref);
5664 s390_add_constant (pool, constant, mode);
5669 gcc_assert (pool->pool_insn || pool->size == 0);
5671 if (pool->size >= 4096)
5673 /* We're going to chunkify the pool, so remove the main
5674 pool placeholder insn. */
5675 remove_insn (pool->pool_insn);
5677 s390_free_pool (pool);
5684 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5685 Modify the current function to output the pool constants as well as
5686 the pool register setup instruction. */
5689 s390_mainpool_finish (struct constant_pool *pool)
5691 rtx base_reg = cfun->machine->base_reg;
5694 /* If the pool is empty, we're done. */
5695 if (pool->size == 0)
5697 /* We don't actually need a base register after all. */
5698 cfun->machine->base_reg = NULL_RTX;
5700 if (pool->pool_insn)
5701 remove_insn (pool->pool_insn);
5702 s390_free_pool (pool);
5706 /* We need correct insn addresses. */
5707 shorten_branches (get_insns ());
5709 /* On zSeries, we use a LARL to load the pool register. The pool is
5710 located in the .rodata section, so we emit it after the function. */
5711 if (TARGET_CPU_ZARCH)
5713 insn = gen_main_base_64 (base_reg, pool->label);
5714 insn = emit_insn_after (insn, pool->pool_insn);
5715 INSN_ADDRESSES_NEW (insn, -1);
5716 remove_insn (pool->pool_insn);
5718 insn = get_last_insn ();
5719 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5720 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5722 s390_dump_pool (pool, 0);
5725 /* On S/390, if the total size of the function's code plus literal pool
5726 does not exceed 4096 bytes, we use BASR to set up a function base
5727 pointer, and emit the literal pool at the end of the function. */
5728 else if (INSN_ADDRESSES (INSN_UID (get_last_insn ()))
5729 + pool->size + 8 /* alignment slop */ < 4096)
5731 insn = gen_main_base_31_small (base_reg, pool->label);
5732 insn = emit_insn_after (insn, pool->pool_insn);
5733 INSN_ADDRESSES_NEW (insn, -1);
5734 remove_insn (pool->pool_insn);
5736 insn = emit_label_after (pool->label, insn);
5737 INSN_ADDRESSES_NEW (insn, -1);
5739 insn = get_last_insn ();
5740 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5741 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5743 s390_dump_pool (pool, 1);
5746 /* Otherwise, we emit an inline literal pool and use BASR to branch
5747 over it, setting up the pool register at the same time. */
5750 rtx pool_end = gen_label_rtx ();
5752 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
5753 insn = emit_insn_after (insn, pool->pool_insn);
5754 INSN_ADDRESSES_NEW (insn, -1);
5755 remove_insn (pool->pool_insn);
5757 insn = emit_label_after (pool->label, insn);
5758 INSN_ADDRESSES_NEW (insn, -1);
5760 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5761 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5763 insn = emit_label_after (pool_end, pool->pool_insn);
5764 INSN_ADDRESSES_NEW (insn, -1);
5766 s390_dump_pool (pool, 1);
5770 /* Replace all literal pool references. */
5772 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5775 replace_ltrel_base (&PATTERN (insn));
5777 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5779 rtx addr, pool_ref = NULL_RTX;
5780 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5783 if (s390_execute_label (insn))
5784 addr = s390_find_execute (pool, insn);
5786 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
5787 get_pool_mode (pool_ref));
5789 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
5790 INSN_CODE (insn) = -1;
5796 /* Free the pool. */
5797 s390_free_pool (pool);
5800 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5801 We have decided we cannot use this pool, so revert all changes
5802 to the current function that were done by s390_mainpool_start. */
5804 s390_mainpool_cancel (struct constant_pool *pool)
5806 /* We didn't actually change the instruction stream, so simply
5807 free the pool memory. */
5808 s390_free_pool (pool);
5812 /* Chunkify the literal pool. */
5814 #define S390_POOL_CHUNK_MIN 0xc00
5815 #define S390_POOL_CHUNK_MAX 0xe00
5817 static struct constant_pool *
5818 s390_chunkify_start (void)
5820 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
5823 rtx pending_ltrel = NULL_RTX;
5826 rtx (*gen_reload_base) (rtx, rtx) =
5827 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
5830 /* We need correct insn addresses. */
5832 shorten_branches (get_insns ());
5834 /* Scan all insns and move literals to pool chunks. */
5836 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5838 /* Check for pending LTREL_BASE. */
5841 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
5844 gcc_assert (ltrel_base == pending_ltrel);
5845 pending_ltrel = NULL_RTX;
5849 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5852 curr_pool = s390_start_pool (&pool_list, insn);
5854 s390_add_execute (curr_pool, insn);
5855 s390_add_pool_insn (curr_pool, insn);
5857 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5859 rtx pool_ref = NULL_RTX;
5860 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5863 rtx constant = get_pool_constant (pool_ref);
5864 enum machine_mode mode = get_pool_mode (pool_ref);
5867 curr_pool = s390_start_pool (&pool_list, insn);
5869 s390_add_constant (curr_pool, constant, mode);
5870 s390_add_pool_insn (curr_pool, insn);
5872 /* Don't split the pool chunk between a LTREL_OFFSET load
5873 and the corresponding LTREL_BASE. */
5874 if (GET_CODE (constant) == CONST
5875 && GET_CODE (XEXP (constant, 0)) == UNSPEC
5876 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
5878 gcc_assert (!pending_ltrel);
5879 pending_ltrel = pool_ref;
5884 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
5887 s390_add_pool_insn (curr_pool, insn);
5888 /* An LTREL_BASE must follow within the same basic block. */
5889 gcc_assert (!pending_ltrel);
5893 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
5894 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
5897 if (TARGET_CPU_ZARCH)
5899 if (curr_pool->size < S390_POOL_CHUNK_MAX)
5902 s390_end_pool (curr_pool, NULL_RTX);
5907 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
5908 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
5911 /* We will later have to insert base register reload insns.
5912 Those will have an effect on code size, which we need to
5913 consider here. This calculation makes rather pessimistic
5914 worst-case assumptions. */
5915 if (GET_CODE (insn) == CODE_LABEL)
5918 if (chunk_size < S390_POOL_CHUNK_MIN
5919 && curr_pool->size < S390_POOL_CHUNK_MIN)
5922 /* Pool chunks can only be inserted after BARRIERs ... */
5923 if (GET_CODE (insn) == BARRIER)
5925 s390_end_pool (curr_pool, insn);
5930 /* ... so if we don't find one in time, create one. */
5931 else if ((chunk_size > S390_POOL_CHUNK_MAX
5932 || curr_pool->size > S390_POOL_CHUNK_MAX))
5934 rtx label, jump, barrier;
5936 /* We can insert the barrier only after a 'real' insn. */
5937 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
5939 if (get_attr_length (insn) == 0)
5942 /* Don't separate LTREL_BASE from the corresponding
5943 LTREL_OFFSET load. */
5947 label = gen_label_rtx ();
5948 jump = emit_jump_insn_after (gen_jump (label), insn);
5949 barrier = emit_barrier_after (jump);
5950 insn = emit_label_after (label, barrier);
5951 JUMP_LABEL (jump) = label;
5952 LABEL_NUSES (label) = 1;
5954 INSN_ADDRESSES_NEW (jump, -1);
5955 INSN_ADDRESSES_NEW (barrier, -1);
5956 INSN_ADDRESSES_NEW (insn, -1);
5958 s390_end_pool (curr_pool, barrier);
5966 s390_end_pool (curr_pool, NULL_RTX);
5967 gcc_assert (!pending_ltrel);
5969 /* Find all labels that are branched into
5970 from an insn belonging to a different chunk. */
5972 far_labels = BITMAP_ALLOC (NULL);
5974 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5976 /* Labels marked with LABEL_PRESERVE_P can be target
5977 of non-local jumps, so we have to mark them.
5978 The same holds for named labels.
5980 Don't do that, however, if it is the label before
5983 if (GET_CODE (insn) == CODE_LABEL
5984 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
5986 rtx vec_insn = next_real_insn (insn);
5987 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
5988 PATTERN (vec_insn) : NULL_RTX;
5990 || !(GET_CODE (vec_pat) == ADDR_VEC
5991 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
5992 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
5995 /* If we have a direct jump (conditional or unconditional)
5996 or a casesi jump, check all potential targets. */
5997 else if (GET_CODE (insn) == JUMP_INSN)
5999 rtx pat = PATTERN (insn);
6000 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
6001 pat = XVECEXP (pat, 0, 0);
6003 if (GET_CODE (pat) == SET)
6005 rtx label = JUMP_LABEL (insn);
6008 if (s390_find_pool (pool_list, label)
6009 != s390_find_pool (pool_list, insn))
6010 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6013 else if (GET_CODE (pat) == PARALLEL
6014 && XVECLEN (pat, 0) == 2
6015 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
6016 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
6017 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
6019 /* Find the jump table used by this casesi jump. */
6020 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
6021 rtx vec_insn = next_real_insn (vec_label);
6022 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
6023 PATTERN (vec_insn) : NULL_RTX;
6025 && (GET_CODE (vec_pat) == ADDR_VEC
6026 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
6028 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
6030 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
6032 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
6034 if (s390_find_pool (pool_list, label)
6035 != s390_find_pool (pool_list, insn))
6036 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
6043 /* Insert base register reload insns before every pool. */
6045 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6047 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6049 rtx insn = curr_pool->first_insn;
6050 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
6053 /* Insert base register reload insns at every far label. */
6055 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6056 if (GET_CODE (insn) == CODE_LABEL
6057 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
6059 struct constant_pool *pool = s390_find_pool (pool_list, insn);
6062 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
6064 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
6069 BITMAP_FREE (far_labels);
6072 /* Recompute insn addresses. */
6074 init_insn_lengths ();
6075 shorten_branches (get_insns ());
6080 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6081 After we have decided to use this list, finish implementing
6082 all changes to the current function as required. */
6085 s390_chunkify_finish (struct constant_pool *pool_list)
6087 struct constant_pool *curr_pool = NULL;
6091 /* Replace all literal pool references. */
6093 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6096 replace_ltrel_base (&PATTERN (insn));
6098 curr_pool = s390_find_pool (pool_list, insn);
6102 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
6104 rtx addr, pool_ref = NULL_RTX;
6105 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6108 if (s390_execute_label (insn))
6109 addr = s390_find_execute (curr_pool, insn);
6111 addr = s390_find_constant (curr_pool,
6112 get_pool_constant (pool_ref),
6113 get_pool_mode (pool_ref));
6115 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6116 INSN_CODE (insn) = -1;
6121 /* Dump out all literal pools. */
6123 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6124 s390_dump_pool (curr_pool, 0);
6126 /* Free pool list. */
6130 struct constant_pool *next = pool_list->next;
6131 s390_free_pool (pool_list);
6136 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6137 We have decided we cannot use this list, so revert all changes
6138 to the current function that were done by s390_chunkify_start. */
6141 s390_chunkify_cancel (struct constant_pool *pool_list)
6143 struct constant_pool *curr_pool = NULL;
6146 /* Remove all pool placeholder insns. */
6148 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
6150 /* Did we insert an extra barrier? Remove it. */
6151 rtx barrier = PREV_INSN (curr_pool->pool_insn);
6152 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
6153 rtx label = NEXT_INSN (curr_pool->pool_insn);
6155 if (jump && GET_CODE (jump) == JUMP_INSN
6156 && barrier && GET_CODE (barrier) == BARRIER
6157 && label && GET_CODE (label) == CODE_LABEL
6158 && GET_CODE (PATTERN (jump)) == SET
6159 && SET_DEST (PATTERN (jump)) == pc_rtx
6160 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
6161 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
6164 remove_insn (barrier);
6165 remove_insn (label);
6168 remove_insn (curr_pool->pool_insn);
6171 /* Remove all base register reload insns. */
6173 for (insn = get_insns (); insn; )
6175 rtx next_insn = NEXT_INSN (insn);
6177 if (GET_CODE (insn) == INSN
6178 && GET_CODE (PATTERN (insn)) == SET
6179 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
6180 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
6186 /* Free pool list. */
6190 struct constant_pool *next = pool_list->next;
6191 s390_free_pool (pool_list);
6197 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6200 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
6204 switch (GET_MODE_CLASS (mode))
6207 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
6209 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
6210 assemble_real (r, mode, align);
6214 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
6223 /* Return an RTL expression representing the value of the return address
6224 for the frame COUNT steps up from the current frame. FRAME is the
6225 frame pointer of that frame. */
6228 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
6233 /* Without backchain, we fail for all but the current frame. */
6235 if (!TARGET_BACKCHAIN && count > 0)
6238 /* For the current frame, we need to make sure the initial
6239 value of RETURN_REGNUM is actually saved. */
6243 /* On non-z architectures branch splitting could overwrite r14. */
6244 if (TARGET_CPU_ZARCH)
6245 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
6248 cfun_frame_layout.save_return_addr_p = true;
6249 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
6253 if (TARGET_PACKED_STACK)
6254 offset = -2 * UNITS_PER_WORD;
6256 offset = RETURN_REGNUM * UNITS_PER_WORD;
6258 addr = plus_constant (frame, offset);
6259 addr = memory_address (Pmode, addr);
6260 return gen_rtx_MEM (Pmode, addr);
6263 /* Return an RTL expression representing the back chain stored in
6264 the current stack frame. */
6267 s390_back_chain_rtx (void)
6271 gcc_assert (TARGET_BACKCHAIN);
6273 if (TARGET_PACKED_STACK)
6274 chain = plus_constant (stack_pointer_rtx,
6275 STACK_POINTER_OFFSET - UNITS_PER_WORD);
6277 chain = stack_pointer_rtx;
6279 chain = gen_rtx_MEM (Pmode, chain);
6283 /* Find first call clobbered register unused in a function.
6284 This could be used as base register in a leaf function
6285 or for holding the return address before epilogue. */
6288 find_unused_clobbered_reg (void)
6291 for (i = 0; i < 6; i++)
6292 if (!regs_ever_live[i])
6298 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6299 clobbered hard regs in SETREG. */
6302 s390_reg_clobbered_rtx (rtx setreg, rtx set_insn ATTRIBUTE_UNUSED, void *data)
6304 int *regs_ever_clobbered = (int *)data;
6305 unsigned int i, regno;
6306 enum machine_mode mode = GET_MODE (setreg);
6308 if (GET_CODE (setreg) == SUBREG)
6310 rtx inner = SUBREG_REG (setreg);
6311 if (!GENERAL_REG_P (inner))
6313 regno = subreg_regno (setreg);
6315 else if (GENERAL_REG_P (setreg))
6316 regno = REGNO (setreg);
6321 i < regno + HARD_REGNO_NREGS (regno, mode);
6323 regs_ever_clobbered[i] = 1;
6326 /* Walks through all basic blocks of the current function looking
6327 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6328 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6329 each of those regs. */
6332 s390_regs_ever_clobbered (int *regs_ever_clobbered)
6338 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
6340 /* For non-leaf functions we have to consider all call clobbered regs to be
6342 if (!current_function_is_leaf)
6344 for (i = 0; i < 16; i++)
6345 regs_ever_clobbered[i] = call_really_used_regs[i];
6348 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6349 this work is done by liveness analysis (mark_regs_live_at_end).
6350 Special care is needed for functions containing landing pads. Landing pads
6351 may use the eh registers, but the code which sets these registers is not
6352 contained in that function. Hence s390_regs_ever_clobbered is not able to
6353 deal with this automatically. */
6354 if (current_function_calls_eh_return || cfun->machine->has_landing_pad_p)
6355 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
6356 if (current_function_calls_eh_return
6357 || (cfun->machine->has_landing_pad_p
6358 && regs_ever_live [EH_RETURN_DATA_REGNO (i)]))
6359 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
6361 /* For nonlocal gotos all call-saved registers have to be saved.
6362 This flag is also set for the unwinding code in libgcc.
6363 See expand_builtin_unwind_init. For regs_ever_live this is done by
6365 if (current_function_has_nonlocal_label)
6366 for (i = 0; i < 16; i++)
6367 if (!call_really_used_regs[i])
6368 regs_ever_clobbered[i] = 1;
6370 FOR_EACH_BB (cur_bb)
6372 FOR_BB_INSNS (cur_bb, cur_insn)
6374 if (INSN_P (cur_insn))
6375 note_stores (PATTERN (cur_insn),
6376 s390_reg_clobbered_rtx,
6377 regs_ever_clobbered);
6382 /* Determine the frame area which actually has to be accessed
6383 in the function epilogue. The values are stored at the
6384 given pointers AREA_BOTTOM (address of the lowest used stack
6385 address) and AREA_TOP (address of the first item which does
6386 not belong to the stack frame). */
6389 s390_frame_area (int *area_bottom, int *area_top)
6397 if (cfun_frame_layout.first_restore_gpr != -1)
6399 b = (cfun_frame_layout.gprs_offset
6400 + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
6401 t = b + (cfun_frame_layout.last_restore_gpr
6402 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
6405 if (TARGET_64BIT && cfun_save_high_fprs_p)
6407 b = MIN (b, cfun_frame_layout.f8_offset);
6408 t = MAX (t, (cfun_frame_layout.f8_offset
6409 + cfun_frame_layout.high_fprs * 8));
6413 for (i = 2; i < 4; i++)
6414 if (cfun_fpr_bit_p (i))
6416 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
6417 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
6424 /* Fill cfun->machine with info about register usage of current function.
6425 Return in CLOBBERED_REGS which GPRs are currently considered set. */
6428 s390_register_info (int clobbered_regs[])
6432 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
6433 cfun_frame_layout.fpr_bitmap = 0;
6434 cfun_frame_layout.high_fprs = 0;
6436 for (i = 24; i < 32; i++)
6437 if (regs_ever_live[i] && !global_regs[i])
6439 cfun_set_fpr_bit (i - 16);
6440 cfun_frame_layout.high_fprs++;
6443 /* Find first and last gpr to be saved. We trust regs_ever_live
6444 data, except that we don't save and restore global registers.
6446 Also, all registers with special meaning to the compiler need
6447 to be handled extra. */
6449 s390_regs_ever_clobbered (clobbered_regs);
6451 for (i = 0; i < 16; i++)
6452 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
6454 if (frame_pointer_needed)
6455 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
6458 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
6459 |= regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
6461 clobbered_regs[BASE_REGNUM]
6462 |= (cfun->machine->base_reg
6463 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
6465 clobbered_regs[RETURN_REGNUM]
6466 |= (!current_function_is_leaf
6467 || TARGET_TPF_PROFILING
6468 || cfun->machine->split_branches_pending_p
6469 || cfun_frame_layout.save_return_addr_p
6470 || current_function_calls_eh_return
6471 || current_function_stdarg);
6473 clobbered_regs[STACK_POINTER_REGNUM]
6474 |= (!current_function_is_leaf
6475 || TARGET_TPF_PROFILING
6476 || cfun_save_high_fprs_p
6477 || get_frame_size () > 0
6478 || current_function_calls_alloca
6479 || current_function_stdarg);
6481 for (i = 6; i < 16; i++)
6482 if (regs_ever_live[i] || clobbered_regs[i])
6484 for (j = 15; j > i; j--)
6485 if (regs_ever_live[j] || clobbered_regs[j])
6490 /* Nothing to save/restore. */
6491 cfun_frame_layout.first_save_gpr_slot = -1;
6492 cfun_frame_layout.last_save_gpr_slot = -1;
6493 cfun_frame_layout.first_save_gpr = -1;
6494 cfun_frame_layout.first_restore_gpr = -1;
6495 cfun_frame_layout.last_save_gpr = -1;
6496 cfun_frame_layout.last_restore_gpr = -1;
6500 /* Save slots for gprs from i to j. */
6501 cfun_frame_layout.first_save_gpr_slot = i;
6502 cfun_frame_layout.last_save_gpr_slot = j;
6504 for (i = cfun_frame_layout.first_save_gpr_slot;
6505 i < cfun_frame_layout.last_save_gpr_slot + 1;
6507 if (clobbered_regs[i])
6510 for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--)
6511 if (clobbered_regs[j])
6514 if (i == cfun_frame_layout.last_save_gpr_slot + 1)
6516 /* Nothing to save/restore. */
6517 cfun_frame_layout.first_save_gpr = -1;
6518 cfun_frame_layout.first_restore_gpr = -1;
6519 cfun_frame_layout.last_save_gpr = -1;
6520 cfun_frame_layout.last_restore_gpr = -1;
6524 /* Save / Restore from gpr i to j. */
6525 cfun_frame_layout.first_save_gpr = i;
6526 cfun_frame_layout.first_restore_gpr = i;
6527 cfun_frame_layout.last_save_gpr = j;
6528 cfun_frame_layout.last_restore_gpr = j;
6532 if (current_function_stdarg)
6534 /* Varargs functions need to save gprs 2 to 6. */
6535 if (cfun->va_list_gpr_size
6536 && current_function_args_info.gprs < GP_ARG_NUM_REG)
6538 int min_gpr = current_function_args_info.gprs;
6539 int max_gpr = min_gpr + cfun->va_list_gpr_size;
6540 if (max_gpr > GP_ARG_NUM_REG)
6541 max_gpr = GP_ARG_NUM_REG;
6543 if (cfun_frame_layout.first_save_gpr == -1
6544 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
6546 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
6547 cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr;
6550 if (cfun_frame_layout.last_save_gpr == -1
6551 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
6553 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
6554 cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1;
6558 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
6559 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
6560 && current_function_args_info.fprs < FP_ARG_NUM_REG)
6562 int min_fpr = current_function_args_info.fprs;
6563 int max_fpr = min_fpr + cfun->va_list_fpr_size;
6564 if (max_fpr > FP_ARG_NUM_REG)
6565 max_fpr = FP_ARG_NUM_REG;
6567 /* ??? This is currently required to ensure proper location
6568 of the fpr save slots within the va_list save area. */
6569 if (TARGET_PACKED_STACK)
6572 for (i = min_fpr; i < max_fpr; i++)
6573 cfun_set_fpr_bit (i);
6578 for (i = 2; i < 4; i++)
6579 if (regs_ever_live[i + 16] && !global_regs[i + 16])
6580 cfun_set_fpr_bit (i);
6583 /* Fill cfun->machine with info about frame of current function. */
6586 s390_frame_info (void)
6590 cfun_frame_layout.frame_size = get_frame_size ();
6591 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
6592 fatal_error ("total size of local variables exceeds architecture limit");
6594 if (!TARGET_PACKED_STACK)
6596 cfun_frame_layout.backchain_offset = 0;
6597 cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
6598 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
6599 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
6600 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
6603 else if (TARGET_BACKCHAIN) /* kernel stack layout */
6605 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
6607 cfun_frame_layout.gprs_offset
6608 = (cfun_frame_layout.backchain_offset
6609 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
6614 cfun_frame_layout.f4_offset
6615 = (cfun_frame_layout.gprs_offset
6616 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6618 cfun_frame_layout.f0_offset
6619 = (cfun_frame_layout.f4_offset
6620 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6624 /* On 31 bit we have to care about alignment of the
6625 floating point regs to provide fastest access. */
6626 cfun_frame_layout.f0_offset
6627 = ((cfun_frame_layout.gprs_offset
6628 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
6629 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6631 cfun_frame_layout.f4_offset
6632 = (cfun_frame_layout.f0_offset
6633 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6636 else /* no backchain */
6638 cfun_frame_layout.f4_offset
6639 = (STACK_POINTER_OFFSET
6640 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6642 cfun_frame_layout.f0_offset
6643 = (cfun_frame_layout.f4_offset
6644 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6646 cfun_frame_layout.gprs_offset
6647 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
6650 if (current_function_is_leaf
6651 && !TARGET_TPF_PROFILING
6652 && cfun_frame_layout.frame_size == 0
6653 && !cfun_save_high_fprs_p
6654 && !current_function_calls_alloca
6655 && !current_function_stdarg)
6658 if (!TARGET_PACKED_STACK)
6659 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
6660 + current_function_outgoing_args_size
6661 + cfun_frame_layout.high_fprs * 8);
6664 if (TARGET_BACKCHAIN)
6665 cfun_frame_layout.frame_size += UNITS_PER_WORD;
6667 /* No alignment trouble here because f8-f15 are only saved under
6669 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
6670 cfun_frame_layout.f4_offset),
6671 cfun_frame_layout.gprs_offset)
6672 - cfun_frame_layout.high_fprs * 8);
6674 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
6676 for (i = 0; i < 8; i++)
6677 if (cfun_fpr_bit_p (i))
6678 cfun_frame_layout.frame_size += 8;
6680 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
6682 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
6683 the frame size to sustain 8 byte alignment of stack frames. */
6684 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
6685 STACK_BOUNDARY / BITS_PER_UNIT - 1)
6686 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
6688 cfun_frame_layout.frame_size += current_function_outgoing_args_size;
6692 /* Generate frame layout. Fills in register and frame data for the current
6693 function in cfun->machine. This routine can be called multiple times;
6694 it will re-do the complete frame layout every time. */
6697 s390_init_frame_layout (void)
6699 HOST_WIDE_INT frame_size;
6701 int clobbered_regs[16];
6703 /* On S/390 machines, we may need to perform branch splitting, which
6704 will require both base and return address register. We have no
6705 choice but to assume we're going to need them until right at the
6706 end of the machine dependent reorg phase. */
6707 if (!TARGET_CPU_ZARCH)
6708 cfun->machine->split_branches_pending_p = true;
6712 frame_size = cfun_frame_layout.frame_size;
6714 /* Try to predict whether we'll need the base register. */
6715 base_used = cfun->machine->split_branches_pending_p
6716 || current_function_uses_const_pool
6717 || (!DISP_IN_RANGE (-frame_size)
6718 && !CONST_OK_FOR_K (-frame_size));
6720 /* Decide which register to use as literal pool base. In small
6721 leaf functions, try to use an unused call-clobbered register
6722 as base register to avoid save/restore overhead. */
6724 cfun->machine->base_reg = NULL_RTX;
6725 else if (current_function_is_leaf && !regs_ever_live[5])
6726 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
6728 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
6730 s390_register_info (clobbered_regs);
6733 while (frame_size != cfun_frame_layout.frame_size);
6736 /* Update frame layout. Recompute actual register save data based on
6737 current info and update regs_ever_live for the special registers.
6738 May be called multiple times, but may never cause *more* registers
6739 to be saved than s390_init_frame_layout allocated room for. */
6742 s390_update_frame_layout (void)
6744 int clobbered_regs[16];
6746 s390_register_info (clobbered_regs);
6748 regs_ever_live[BASE_REGNUM] = clobbered_regs[BASE_REGNUM];
6749 regs_ever_live[RETURN_REGNUM] = clobbered_regs[RETURN_REGNUM];
6750 regs_ever_live[STACK_POINTER_REGNUM] = clobbered_regs[STACK_POINTER_REGNUM];
6752 if (cfun->machine->base_reg)
6753 regs_ever_live[REGNO (cfun->machine->base_reg)] = 1;
6756 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
6759 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
6761 /* Once we've decided upon a register to use as base register, it must
6762 no longer be used for any other purpose. */
6763 if (cfun->machine->base_reg)
6764 if (REGNO (cfun->machine->base_reg) == old_reg
6765 || REGNO (cfun->machine->base_reg) == new_reg)
6771 /* Return true if register FROM can be eliminated via register TO. */
6774 s390_can_eliminate (int from, int to)
6776 /* On zSeries machines, we have not marked the base register as fixed.
6777 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
6778 If a function requires the base register, we say here that this
6779 elimination cannot be performed. This will cause reload to free
6780 up the base register (as if it were fixed). On the other hand,
6781 if the current function does *not* require the base register, we
6782 say here the elimination succeeds, which in turn allows reload
6783 to allocate the base register for any other purpose. */
6784 if (from == BASE_REGNUM && to == BASE_REGNUM)
6786 if (TARGET_CPU_ZARCH)
6788 s390_init_frame_layout ();
6789 return cfun->machine->base_reg == NULL_RTX;
6795 /* Everything else must point into the stack frame. */
6796 gcc_assert (to == STACK_POINTER_REGNUM
6797 || to == HARD_FRAME_POINTER_REGNUM);
6799 gcc_assert (from == FRAME_POINTER_REGNUM
6800 || from == ARG_POINTER_REGNUM
6801 || from == RETURN_ADDRESS_POINTER_REGNUM);
6803 /* Make sure we actually saved the return address. */
6804 if (from == RETURN_ADDRESS_POINTER_REGNUM)
6805 if (!current_function_calls_eh_return
6806 && !current_function_stdarg
6807 && !cfun_frame_layout.save_return_addr_p)
6813 /* Return offset between register FROM and TO initially after prolog. */
6816 s390_initial_elimination_offset (int from, int to)
6818 HOST_WIDE_INT offset;
6821 /* ??? Why are we called for non-eliminable pairs? */
6822 if (!s390_can_eliminate (from, to))
6827 case FRAME_POINTER_REGNUM:
6828 offset = (get_frame_size()
6829 + STACK_POINTER_OFFSET
6830 + current_function_outgoing_args_size);
6833 case ARG_POINTER_REGNUM:
6834 s390_init_frame_layout ();
6835 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
6838 case RETURN_ADDRESS_POINTER_REGNUM:
6839 s390_init_frame_layout ();
6840 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
6841 gcc_assert (index >= 0);
6842 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
6843 offset += index * UNITS_PER_WORD;
6857 /* Emit insn to save fpr REGNUM at offset OFFSET relative
6858 to register BASE. Return generated insn. */
6861 save_fpr (rtx base, int offset, int regnum)
6864 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6866 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
6867 set_mem_alias_set (addr, get_varargs_alias_set ());
6869 set_mem_alias_set (addr, get_frame_alias_set ());
6871 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
6874 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
6875 to register BASE. Return generated insn. */
6878 restore_fpr (rtx base, int offset, int regnum)
6881 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6882 set_mem_alias_set (addr, get_frame_alias_set ());
6884 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
6887 /* Generate insn to save registers FIRST to LAST into
6888 the register save area located at offset OFFSET
6889 relative to register BASE. */
6892 save_gprs (rtx base, int offset, int first, int last)
6894 rtx addr, insn, note;
6897 addr = plus_constant (base, offset);
6898 addr = gen_rtx_MEM (Pmode, addr);
6900 set_mem_alias_set (addr, get_frame_alias_set ());
6902 /* Special-case single register. */
6906 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
6908 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
6910 RTX_FRAME_RELATED_P (insn) = 1;
6915 insn = gen_store_multiple (addr,
6916 gen_rtx_REG (Pmode, first),
6917 GEN_INT (last - first + 1));
6919 if (first <= 6 && current_function_stdarg)
6920 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
6922 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
6925 set_mem_alias_set (mem, get_varargs_alias_set ());
6928 /* We need to set the FRAME_RELATED flag on all SETs
6929 inside the store-multiple pattern.
6931 However, we must not emit DWARF records for registers 2..5
6932 if they are stored for use by variable arguments ...
6934 ??? Unfortunately, it is not enough to simply not the
6935 FRAME_RELATED flags for those SETs, because the first SET
6936 of the PARALLEL is always treated as if it had the flag
6937 set, even if it does not. Therefore we emit a new pattern
6938 without those registers as REG_FRAME_RELATED_EXPR note. */
6942 rtx pat = PATTERN (insn);
6944 for (i = 0; i < XVECLEN (pat, 0); i++)
6945 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
6946 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
6948 RTX_FRAME_RELATED_P (insn) = 1;
6952 addr = plus_constant (base, offset + (6 - first) * UNITS_PER_WORD);
6953 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
6954 gen_rtx_REG (Pmode, 6),
6955 GEN_INT (last - 6 + 1));
6956 note = PATTERN (note);
6959 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6960 note, REG_NOTES (insn));
6962 for (i = 0; i < XVECLEN (note, 0); i++)
6963 if (GET_CODE (XVECEXP (note, 0, i)) == SET)
6964 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
6966 RTX_FRAME_RELATED_P (insn) = 1;
6972 /* Generate insn to restore registers FIRST to LAST from
6973 the register save area located at offset OFFSET
6974 relative to register BASE. */
6977 restore_gprs (rtx base, int offset, int first, int last)
6981 addr = plus_constant (base, offset);
6982 addr = gen_rtx_MEM (Pmode, addr);
6983 set_mem_alias_set (addr, get_frame_alias_set ());
6985 /* Special-case single register. */
6989 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
6991 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
6996 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
6998 GEN_INT (last - first + 1));
7002 /* Return insn sequence to load the GOT register. */
7004 static GTY(()) rtx got_symbol;
7006 s390_load_got (void)
7012 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7013 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
7018 if (TARGET_CPU_ZARCH)
7020 emit_move_insn (pic_offset_table_rtx, got_symbol);
7026 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
7027 UNSPEC_LTREL_OFFSET);
7028 offset = gen_rtx_CONST (Pmode, offset);
7029 offset = force_const_mem (Pmode, offset);
7031 emit_move_insn (pic_offset_table_rtx, offset);
7033 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
7035 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
7037 emit_move_insn (pic_offset_table_rtx, offset);
7040 insns = get_insns ();
7045 /* Expand the prologue into a bunch of separate insns. */
7048 s390_emit_prologue (void)
7056 /* Complete frame layout. */
7058 s390_update_frame_layout ();
7060 /* Annotate all constant pool references to let the scheduler know
7061 they implicitly use the base register. */
7063 push_topmost_sequence ();
7065 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7067 annotate_constant_pool_refs (&PATTERN (insn));
7069 pop_topmost_sequence ();
7071 /* Choose best register to use for temp use within prologue.
7072 See below for why TPF must use the register 1. */
7074 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
7075 && !current_function_is_leaf
7076 && !TARGET_TPF_PROFILING)
7077 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7079 temp_reg = gen_rtx_REG (Pmode, 1);
7081 /* Save call saved gprs. */
7082 if (cfun_frame_layout.first_save_gpr != -1)
7084 insn = save_gprs (stack_pointer_rtx,
7085 cfun_frame_layout.gprs_offset +
7086 UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr
7087 - cfun_frame_layout.first_save_gpr_slot),
7088 cfun_frame_layout.first_save_gpr,
7089 cfun_frame_layout.last_save_gpr);
7093 /* Dummy insn to mark literal pool slot. */
7095 if (cfun->machine->base_reg)
7096 emit_insn (gen_main_pool (cfun->machine->base_reg));
7098 offset = cfun_frame_layout.f0_offset;
7100 /* Save f0 and f2. */
7101 for (i = 0; i < 2; i++)
7103 if (cfun_fpr_bit_p (i))
7105 save_fpr (stack_pointer_rtx, offset, i + 16);
7108 else if (!TARGET_PACKED_STACK)
7112 /* Save f4 and f6. */
7113 offset = cfun_frame_layout.f4_offset;
7114 for (i = 2; i < 4; i++)
7116 if (cfun_fpr_bit_p (i))
7118 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7121 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7122 therefore are not frame related. */
7123 if (!call_really_used_regs[i + 16])
7124 RTX_FRAME_RELATED_P (insn) = 1;
7126 else if (!TARGET_PACKED_STACK)
7130 if (TARGET_PACKED_STACK
7131 && cfun_save_high_fprs_p
7132 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
7134 offset = (cfun_frame_layout.f8_offset
7135 + (cfun_frame_layout.high_fprs - 1) * 8);
7137 for (i = 15; i > 7 && offset >= 0; i--)
7138 if (cfun_fpr_bit_p (i))
7140 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
7142 RTX_FRAME_RELATED_P (insn) = 1;
7145 if (offset >= cfun_frame_layout.f8_offset)
7149 if (!TARGET_PACKED_STACK)
7150 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
7152 /* Decrement stack pointer. */
7154 if (cfun_frame_layout.frame_size > 0)
7156 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
7158 if (s390_stack_size)
7160 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
7161 & ~(s390_stack_guard - 1));
7162 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
7163 GEN_INT (stack_check_mask));
7166 gen_cmpdi (t, const0_rtx);
7168 gen_cmpsi (t, const0_rtx);
7170 emit_insn (gen_conditional_trap (gen_rtx_EQ (CCmode,
7171 gen_rtx_REG (CCmode,
7177 if (s390_warn_framesize > 0
7178 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7179 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
7180 current_function_name (), cfun_frame_layout.frame_size);
7182 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
7183 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7185 /* Save incoming stack pointer into temp reg. */
7186 if (TARGET_BACKCHAIN || next_fpr)
7187 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
7189 /* Subtract frame size from stack pointer. */
7191 if (DISP_IN_RANGE (INTVAL (frame_off)))
7193 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7194 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7196 insn = emit_insn (insn);
7200 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7201 frame_off = force_const_mem (Pmode, frame_off);
7203 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
7204 annotate_constant_pool_refs (&PATTERN (insn));
7207 RTX_FRAME_RELATED_P (insn) = 1;
7209 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7210 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7211 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7212 GEN_INT (-cfun_frame_layout.frame_size))),
7215 /* Set backchain. */
7217 if (TARGET_BACKCHAIN)
7219 if (cfun_frame_layout.backchain_offset)
7220 addr = gen_rtx_MEM (Pmode,
7221 plus_constant (stack_pointer_rtx,
7222 cfun_frame_layout.backchain_offset));
7224 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7225 set_mem_alias_set (addr, get_frame_alias_set ());
7226 insn = emit_insn (gen_move_insn (addr, temp_reg));
7229 /* If we support asynchronous exceptions (e.g. for Java),
7230 we need to make sure the backchain pointer is set up
7231 before any possibly trapping memory access. */
7233 if (TARGET_BACKCHAIN && flag_non_call_exceptions)
7235 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
7236 emit_insn (gen_rtx_CLOBBER (VOIDmode, addr));
7240 /* Save fprs 8 - 15 (64 bit ABI). */
7242 if (cfun_save_high_fprs_p && next_fpr)
7244 insn = emit_insn (gen_add2_insn (temp_reg,
7245 GEN_INT (cfun_frame_layout.f8_offset)));
7249 for (i = 24; i <= next_fpr; i++)
7250 if (cfun_fpr_bit_p (i - 16))
7252 rtx addr = plus_constant (stack_pointer_rtx,
7253 cfun_frame_layout.frame_size
7254 + cfun_frame_layout.f8_offset
7257 insn = save_fpr (temp_reg, offset, i);
7259 RTX_FRAME_RELATED_P (insn) = 1;
7261 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7262 gen_rtx_SET (VOIDmode,
7263 gen_rtx_MEM (DFmode, addr),
7264 gen_rtx_REG (DFmode, i)),
7269 /* Set frame pointer, if needed. */
7271 if (frame_pointer_needed)
7273 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7274 RTX_FRAME_RELATED_P (insn) = 1;
7277 /* Set up got pointer, if needed. */
7279 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
7281 rtx insns = s390_load_got ();
7283 for (insn = insns; insn; insn = NEXT_INSN (insn))
7285 annotate_constant_pool_refs (&PATTERN (insn));
7287 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
7294 if (TARGET_TPF_PROFILING)
7296 /* Generate a BAS instruction to serve as a function
7297 entry intercept to facilitate the use of tracing
7298 algorithms located at the branch target. */
7299 emit_insn (gen_prologue_tpf ());
7301 /* Emit a blockage here so that all code
7302 lies between the profiling mechanisms. */
7303 emit_insn (gen_blockage ());
7307 /* Expand the epilogue into a bunch of separate insns. */
7310 s390_emit_epilogue (bool sibcall)
7312 rtx frame_pointer, return_reg;
7313 int area_bottom, area_top, offset = 0;
7318 if (TARGET_TPF_PROFILING)
7321 /* Generate a BAS instruction to serve as a function
7322 entry intercept to facilitate the use of tracing
7323 algorithms located at the branch target. */
7325 /* Emit a blockage here so that all code
7326 lies between the profiling mechanisms. */
7327 emit_insn (gen_blockage ());
7329 emit_insn (gen_epilogue_tpf ());
7332 /* Check whether to use frame or stack pointer for restore. */
7334 frame_pointer = (frame_pointer_needed
7335 ? hard_frame_pointer_rtx : stack_pointer_rtx);
7337 s390_frame_area (&area_bottom, &area_top);
7339 /* Check whether we can access the register save area.
7340 If not, increment the frame pointer as required. */
7342 if (area_top <= area_bottom)
7344 /* Nothing to restore. */
7346 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
7347 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
7349 /* Area is in range. */
7350 offset = cfun_frame_layout.frame_size;
7354 rtx insn, frame_off;
7356 offset = area_bottom < 0 ? -area_bottom : 0;
7357 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
7359 if (DISP_IN_RANGE (INTVAL (frame_off)))
7361 insn = gen_rtx_SET (VOIDmode, frame_pointer,
7362 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
7363 insn = emit_insn (insn);
7367 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
7368 frame_off = force_const_mem (Pmode, frame_off);
7370 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
7371 annotate_constant_pool_refs (&PATTERN (insn));
7375 /* Restore call saved fprs. */
7379 if (cfun_save_high_fprs_p)
7381 next_offset = cfun_frame_layout.f8_offset;
7382 for (i = 24; i < 32; i++)
7384 if (cfun_fpr_bit_p (i - 16))
7386 restore_fpr (frame_pointer,
7387 offset + next_offset, i);
7396 next_offset = cfun_frame_layout.f4_offset;
7397 for (i = 18; i < 20; i++)
7399 if (cfun_fpr_bit_p (i - 16))
7401 restore_fpr (frame_pointer,
7402 offset + next_offset, i);
7405 else if (!TARGET_PACKED_STACK)
7411 /* Return register. */
7413 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
7415 /* Restore call saved gprs. */
7417 if (cfun_frame_layout.first_restore_gpr != -1)
7422 /* Check for global register and save them
7423 to stack location from where they get restored. */
7425 for (i = cfun_frame_layout.first_restore_gpr;
7426 i <= cfun_frame_layout.last_restore_gpr;
7429 /* These registers are special and need to be
7430 restored in any case. */
7431 if (i == STACK_POINTER_REGNUM
7432 || i == RETURN_REGNUM
7434 || (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
7439 addr = plus_constant (frame_pointer,
7440 offset + cfun_frame_layout.gprs_offset
7441 + (i - cfun_frame_layout.first_save_gpr_slot)
7443 addr = gen_rtx_MEM (Pmode, addr);
7444 set_mem_alias_set (addr, get_frame_alias_set ());
7445 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
7451 /* Fetch return address from stack before load multiple,
7452 this will do good for scheduling. */
7454 if (cfun_frame_layout.save_return_addr_p
7455 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
7456 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
7458 int return_regnum = find_unused_clobbered_reg();
7461 return_reg = gen_rtx_REG (Pmode, return_regnum);
7463 addr = plus_constant (frame_pointer,
7464 offset + cfun_frame_layout.gprs_offset
7466 - cfun_frame_layout.first_save_gpr_slot)
7468 addr = gen_rtx_MEM (Pmode, addr);
7469 set_mem_alias_set (addr, get_frame_alias_set ());
7470 emit_move_insn (return_reg, addr);
7474 insn = restore_gprs (frame_pointer,
7475 offset + cfun_frame_layout.gprs_offset
7476 + (cfun_frame_layout.first_restore_gpr
7477 - cfun_frame_layout.first_save_gpr_slot)
7479 cfun_frame_layout.first_restore_gpr,
7480 cfun_frame_layout.last_restore_gpr);
7487 /* Return to caller. */
7489 p = rtvec_alloc (2);
7491 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
7492 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
7493 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
7498 /* Return the size in bytes of a function argument of
7499 type TYPE and/or mode MODE. At least one of TYPE or
7500 MODE must be specified. */
7503 s390_function_arg_size (enum machine_mode mode, tree type)
7506 return int_size_in_bytes (type);
7508 /* No type info available for some library calls ... */
7509 if (mode != BLKmode)
7510 return GET_MODE_SIZE (mode);
7512 /* If we have neither type nor mode, abort */
7516 /* Return true if a function argument of type TYPE and mode MODE
7517 is to be passed in a floating-point register, if available. */
7520 s390_function_arg_float (enum machine_mode mode, tree type)
7522 int size = s390_function_arg_size (mode, type);
7526 /* Soft-float changes the ABI: no floating-point registers are used. */
7527 if (TARGET_SOFT_FLOAT)
7530 /* No type info available for some library calls ... */
7532 return mode == SFmode || mode == DFmode;
7534 /* The ABI says that record types with a single member are treated
7535 just like that member would be. */
7536 while (TREE_CODE (type) == RECORD_TYPE)
7538 tree field, single = NULL_TREE;
7540 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7542 if (TREE_CODE (field) != FIELD_DECL)
7545 if (single == NULL_TREE)
7546 single = TREE_TYPE (field);
7551 if (single == NULL_TREE)
7557 return TREE_CODE (type) == REAL_TYPE;
7560 /* Return true if a function argument of type TYPE and mode MODE
7561 is to be passed in an integer register, or a pair of integer
7562 registers, if available. */
7565 s390_function_arg_integer (enum machine_mode mode, tree type)
7567 int size = s390_function_arg_size (mode, type);
7571 /* No type info available for some library calls ... */
7573 return GET_MODE_CLASS (mode) == MODE_INT
7574 || (TARGET_SOFT_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT);
7576 /* We accept small integral (and similar) types. */
7577 if (INTEGRAL_TYPE_P (type)
7578 || POINTER_TYPE_P (type)
7579 || TREE_CODE (type) == OFFSET_TYPE
7580 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
7583 /* We also accept structs of size 1, 2, 4, 8 that are not
7584 passed in floating-point registers. */
7585 if (AGGREGATE_TYPE_P (type)
7586 && exact_log2 (size) >= 0
7587 && !s390_function_arg_float (mode, type))
7593 /* Return 1 if a function argument of type TYPE and mode MODE
7594 is to be passed by reference. The ABI specifies that only
7595 structures of size 1, 2, 4, or 8 bytes are passed by value,
7596 all other structures (and complex numbers) are passed by
7600 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
7601 enum machine_mode mode, tree type,
7602 bool named ATTRIBUTE_UNUSED)
7604 int size = s390_function_arg_size (mode, type);
7610 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
7613 if (TREE_CODE (type) == COMPLEX_TYPE
7614 || TREE_CODE (type) == VECTOR_TYPE)
7621 /* Update the data in CUM to advance over an argument of mode MODE and
7622 data type TYPE. (TYPE is null for libcalls where that information
7623 may not be available.). The boolean NAMED specifies whether the
7624 argument is a named argument (as opposed to an unnamed argument
7625 matching an ellipsis). */
7628 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7629 tree type, int named ATTRIBUTE_UNUSED)
7631 if (s390_function_arg_float (mode, type))
7635 else if (s390_function_arg_integer (mode, type))
7637 int size = s390_function_arg_size (mode, type);
7638 cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
7644 /* Define where to put the arguments to a function.
7645 Value is zero to push the argument on the stack,
7646 or a hard register in which to store the argument.
7648 MODE is the argument's machine mode.
7649 TYPE is the data type of the argument (as a tree).
7650 This is null for libcalls where that information may
7652 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7653 the preceding args and about the function being called.
7654 NAMED is nonzero if this argument is a named parameter
7655 (otherwise it is an extra parameter matching an ellipsis).
7657 On S/390, we use general purpose registers 2 through 6 to
7658 pass integer, pointer, and certain structure arguments, and
7659 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
7660 to pass floating point arguments. All remaining arguments
7661 are pushed to the stack. */
7664 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
7665 int named ATTRIBUTE_UNUSED)
7667 if (s390_function_arg_float (mode, type))
7669 if (cum->fprs + 1 > FP_ARG_NUM_REG)
7672 return gen_rtx_REG (mode, cum->fprs + 16);
7674 else if (s390_function_arg_integer (mode, type))
7676 int size = s390_function_arg_size (mode, type);
7677 int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
7679 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
7682 return gen_rtx_REG (mode, cum->gprs + 2);
7685 /* After the real arguments, expand_call calls us once again
7686 with a void_type_node type. Whatever we return here is
7687 passed as operand 2 to the call expanders.
7689 We don't need this feature ... */
7690 else if (type == void_type_node)
7696 /* Return true if return values of type TYPE should be returned
7697 in a memory buffer whose address is passed by the caller as
7698 hidden first argument. */
7701 s390_return_in_memory (tree type, tree fundecl ATTRIBUTE_UNUSED)
7703 /* We accept small integral (and similar) types. */
7704 if (INTEGRAL_TYPE_P (type)
7705 || POINTER_TYPE_P (type)
7706 || TREE_CODE (type) == OFFSET_TYPE
7707 || TREE_CODE (type) == REAL_TYPE)
7708 return int_size_in_bytes (type) > 8;
7710 /* Aggregates and similar constructs are always returned
7712 if (AGGREGATE_TYPE_P (type)
7713 || TREE_CODE (type) == COMPLEX_TYPE
7714 || TREE_CODE (type) == VECTOR_TYPE)
7717 /* ??? We get called on all sorts of random stuff from
7718 aggregate_value_p. We can't abort, but it's not clear
7719 what's safe to return. Pretend it's a struct I guess. */
7723 /* Define where to return a (scalar) value of type TYPE.
7724 If TYPE is null, define where to return a (scalar)
7725 value of mode MODE from a libcall. */
7728 s390_function_value (tree type, enum machine_mode mode)
7732 int unsignedp = TYPE_UNSIGNED (type);
7733 mode = promote_mode (type, TYPE_MODE (type), &unsignedp, 1);
7736 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT
7737 || GET_MODE_CLASS (mode) == MODE_FLOAT);
7738 gcc_assert (GET_MODE_SIZE (mode) <= 8);
7740 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
7741 return gen_rtx_REG (mode, 16);
7743 return gen_rtx_REG (mode, 2);
7747 /* Create and return the va_list datatype.
7749 On S/390, va_list is an array type equivalent to
7751 typedef struct __va_list_tag
7755 void *__overflow_arg_area;
7756 void *__reg_save_area;
7759 where __gpr and __fpr hold the number of general purpose
7760 or floating point arguments used up to now, respectively,
7761 __overflow_arg_area points to the stack location of the
7762 next argument passed on the stack, and __reg_save_area
7763 always points to the start of the register area in the
7764 call frame of the current function. The function prologue
7765 saves all registers used for argument passing into this
7766 area if the function uses variable arguments. */
7769 s390_build_builtin_va_list (void)
7771 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
7773 record = lang_hooks.types.make_type (RECORD_TYPE);
7776 build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
7778 f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"),
7779 long_integer_type_node);
7780 f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"),
7781 long_integer_type_node);
7782 f_ovf = build_decl (FIELD_DECL, get_identifier ("__overflow_arg_area"),
7784 f_sav = build_decl (FIELD_DECL, get_identifier ("__reg_save_area"),
7787 va_list_gpr_counter_field = f_gpr;
7788 va_list_fpr_counter_field = f_fpr;
7790 DECL_FIELD_CONTEXT (f_gpr) = record;
7791 DECL_FIELD_CONTEXT (f_fpr) = record;
7792 DECL_FIELD_CONTEXT (f_ovf) = record;
7793 DECL_FIELD_CONTEXT (f_sav) = record;
7795 TREE_CHAIN (record) = type_decl;
7796 TYPE_NAME (record) = type_decl;
7797 TYPE_FIELDS (record) = f_gpr;
7798 TREE_CHAIN (f_gpr) = f_fpr;
7799 TREE_CHAIN (f_fpr) = f_ovf;
7800 TREE_CHAIN (f_ovf) = f_sav;
7802 layout_type (record);
7804 /* The correct type is an array type of one element. */
7805 return build_array_type (record, build_index_type (size_zero_node));
7808 /* Implement va_start by filling the va_list structure VALIST.
7809 STDARG_P is always true, and ignored.
7810 NEXTARG points to the first anonymous stack argument.
7812 The following global variables are used to initialize
7813 the va_list structure:
7815 current_function_args_info:
7816 holds number of gprs and fprs used for named arguments.
7817 current_function_arg_offset_rtx:
7818 holds the offset of the first anonymous stack argument
7819 (relative to the virtual arg pointer). */
7822 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
7824 HOST_WIDE_INT n_gpr, n_fpr;
7826 tree f_gpr, f_fpr, f_ovf, f_sav;
7827 tree gpr, fpr, ovf, sav, t;
7829 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7830 f_fpr = TREE_CHAIN (f_gpr);
7831 f_ovf = TREE_CHAIN (f_fpr);
7832 f_sav = TREE_CHAIN (f_ovf);
7834 valist = build_va_arg_indirect_ref (valist);
7835 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7836 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7837 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7838 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7840 /* Count number of gp and fp argument registers used. */
7842 n_gpr = current_function_args_info.gprs;
7843 n_fpr = current_function_args_info.fprs;
7845 if (cfun->va_list_gpr_size)
7847 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
7848 build_int_cst (NULL_TREE, n_gpr));
7849 TREE_SIDE_EFFECTS (t) = 1;
7850 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7853 if (cfun->va_list_fpr_size)
7855 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
7856 build_int_cst (NULL_TREE, n_fpr));
7857 TREE_SIDE_EFFECTS (t) = 1;
7858 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7861 /* Find the overflow area. */
7862 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
7863 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
7865 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
7867 off = INTVAL (current_function_arg_offset_rtx);
7868 off = off < 0 ? 0 : off;
7869 if (TARGET_DEBUG_ARG)
7870 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
7871 (int)n_gpr, (int)n_fpr, off);
7873 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t, build_int_cst (NULL_TREE, off));
7875 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
7876 TREE_SIDE_EFFECTS (t) = 1;
7877 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7880 /* Find the register save area. */
7881 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
7882 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
7884 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
7885 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
7886 build_int_cst (NULL_TREE, -RETURN_REGNUM * UNITS_PER_WORD));
7888 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
7889 TREE_SIDE_EFFECTS (t) = 1;
7890 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7894 /* Implement va_arg by updating the va_list structure
7895 VALIST as required to retrieve an argument of type
7896 TYPE, and returning that argument.
7898 Generates code equivalent to:
7900 if (integral value) {
7901 if (size <= 4 && args.gpr < 5 ||
7902 size > 4 && args.gpr < 4 )
7903 ret = args.reg_save_area[args.gpr+8]
7905 ret = *args.overflow_arg_area++;
7906 } else if (float value) {
7908 ret = args.reg_save_area[args.fpr+64]
7910 ret = *args.overflow_arg_area++;
7911 } else if (aggregate value) {
7913 ret = *args.reg_save_area[args.gpr]
7915 ret = **args.overflow_arg_area++;
7919 s390_gimplify_va_arg (tree valist, tree type, tree *pre_p,
7920 tree *post_p ATTRIBUTE_UNUSED)
7922 tree f_gpr, f_fpr, f_ovf, f_sav;
7923 tree gpr, fpr, ovf, sav, reg, t, u;
7924 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
7925 tree lab_false, lab_over, addr;
7927 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7928 f_fpr = TREE_CHAIN (f_gpr);
7929 f_ovf = TREE_CHAIN (f_fpr);
7930 f_sav = TREE_CHAIN (f_ovf);
7932 valist = build_va_arg_indirect_ref (valist);
7933 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7934 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7935 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7936 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7938 size = int_size_in_bytes (type);
7940 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
7942 if (TARGET_DEBUG_ARG)
7944 fprintf (stderr, "va_arg: aggregate type");
7948 /* Aggregates are passed by reference. */
7953 /* kernel stack layout on 31 bit: It is assumed here that no padding
7954 will be added by s390_frame_info because for va_args always an even
7955 number of gprs has to be saved r15-r2 = 14 regs. */
7956 sav_ofs = 2 * UNITS_PER_WORD;
7957 sav_scale = UNITS_PER_WORD;
7958 size = UNITS_PER_WORD;
7959 max_reg = GP_ARG_NUM_REG - n_reg;
7961 else if (s390_function_arg_float (TYPE_MODE (type), type))
7963 if (TARGET_DEBUG_ARG)
7965 fprintf (stderr, "va_arg: float type");
7969 /* FP args go in FP registers, if present. */
7973 sav_ofs = 16 * UNITS_PER_WORD;
7975 max_reg = FP_ARG_NUM_REG - n_reg;
7979 if (TARGET_DEBUG_ARG)
7981 fprintf (stderr, "va_arg: other type");
7985 /* Otherwise into GP registers. */
7988 n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7990 /* kernel stack layout on 31 bit: It is assumed here that no padding
7991 will be added by s390_frame_info because for va_args always an even
7992 number of gprs has to be saved r15-r2 = 14 regs. */
7993 sav_ofs = 2 * UNITS_PER_WORD;
7995 if (size < UNITS_PER_WORD)
7996 sav_ofs += UNITS_PER_WORD - size;
7998 sav_scale = UNITS_PER_WORD;
7999 max_reg = GP_ARG_NUM_REG - n_reg;
8002 /* Pull the value out of the saved registers ... */
8004 lab_false = create_artificial_label ();
8005 lab_over = create_artificial_label ();
8006 addr = create_tmp_var (ptr_type_node, "addr");
8007 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
8009 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
8010 t = build2 (GT_EXPR, boolean_type_node, reg, t);
8011 u = build1 (GOTO_EXPR, void_type_node, lab_false);
8012 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
8013 gimplify_and_add (t, pre_p);
8015 t = build2 (PLUS_EXPR, ptr_type_node, sav,
8016 fold_convert (ptr_type_node, size_int (sav_ofs)));
8017 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
8018 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
8019 t = build2 (PLUS_EXPR, ptr_type_node, t, fold_convert (ptr_type_node, u));
8021 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
8022 gimplify_and_add (t, pre_p);
8024 t = build1 (GOTO_EXPR, void_type_node, lab_over);
8025 gimplify_and_add (t, pre_p);
8027 t = build1 (LABEL_EXPR, void_type_node, lab_false);
8028 append_to_statement_list (t, pre_p);
8031 /* ... Otherwise out of the overflow area. */
8034 if (size < UNITS_PER_WORD)
8035 t = build2 (PLUS_EXPR, ptr_type_node, t,
8036 fold_convert (ptr_type_node, size_int (UNITS_PER_WORD - size)));
8038 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
8040 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
8041 gimplify_and_add (u, pre_p);
8043 t = build2 (PLUS_EXPR, ptr_type_node, t,
8044 fold_convert (ptr_type_node, size_int (size)));
8045 t = build2 (MODIFY_EXPR, ptr_type_node, ovf, t);
8046 gimplify_and_add (t, pre_p);
8048 t = build1 (LABEL_EXPR, void_type_node, lab_over);
8049 append_to_statement_list (t, pre_p);
8052 /* Increment register save count. */
8054 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
8055 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
8056 gimplify_and_add (u, pre_p);
8060 t = build_pointer_type (build_pointer_type (type));
8061 addr = fold_convert (t, addr);
8062 addr = build_va_arg_indirect_ref (addr);
8066 t = build_pointer_type (type);
8067 addr = fold_convert (t, addr);
8070 return build_va_arg_indirect_ref (addr);
8078 S390_BUILTIN_THREAD_POINTER,
8079 S390_BUILTIN_SET_THREAD_POINTER,
8084 static unsigned int const code_for_builtin_64[S390_BUILTIN_max] = {
8089 static unsigned int const code_for_builtin_31[S390_BUILTIN_max] = {
8095 s390_init_builtins (void)
8099 ftype = build_function_type (ptr_type_node, void_list_node);
8100 lang_hooks.builtin_function ("__builtin_thread_pointer", ftype,
8101 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
8104 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
8105 lang_hooks.builtin_function ("__builtin_set_thread_pointer", ftype,
8106 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
8110 /* Expand an expression EXP that calls a built-in function,
8111 with result going to TARGET if that's convenient
8112 (and in mode MODE if that's convenient).
8113 SUBTARGET may be used as the target for computing one of EXP's operands.
8114 IGNORE is nonzero if the value is to be ignored. */
8117 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8118 enum machine_mode mode ATTRIBUTE_UNUSED,
8119 int ignore ATTRIBUTE_UNUSED)
8123 unsigned int const *code_for_builtin =
8124 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
8126 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8127 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8128 tree arglist = TREE_OPERAND (exp, 1);
8129 enum insn_code icode;
8130 rtx op[MAX_ARGS], pat;
8134 if (fcode >= S390_BUILTIN_max)
8135 internal_error ("bad builtin fcode");
8136 icode = code_for_builtin[fcode];
8138 internal_error ("bad builtin fcode");
8140 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
8142 for (arglist = TREE_OPERAND (exp, 1), arity = 0;
8144 arglist = TREE_CHAIN (arglist), arity++)
8146 const struct insn_operand_data *insn_op;
8148 tree arg = TREE_VALUE (arglist);
8149 if (arg == error_mark_node)
8151 if (arity > MAX_ARGS)
8154 insn_op = &insn_data[icode].operand[arity + nonvoid];
8156 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
8158 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
8159 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
8164 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8166 || GET_MODE (target) != tmode
8167 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
8168 target = gen_reg_rtx (tmode);
8174 pat = GEN_FCN (icode) (target);
8178 pat = GEN_FCN (icode) (target, op[0]);
8180 pat = GEN_FCN (icode) (op[0]);
8183 pat = GEN_FCN (icode) (target, op[0], op[1]);
8199 /* Output assembly code for the trampoline template to
8202 On S/390, we use gpr 1 internally in the trampoline code;
8203 gpr 0 is used to hold the static chain. */
8206 s390_trampoline_template (FILE *file)
8209 op[0] = gen_rtx_REG (Pmode, 0);
8210 op[1] = gen_rtx_REG (Pmode, 1);
8214 output_asm_insn ("basr\t%1,0", op);
8215 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
8216 output_asm_insn ("br\t%1", op);
8217 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
8221 output_asm_insn ("basr\t%1,0", op);
8222 output_asm_insn ("lm\t%0,%1,6(%1)", op);
8223 output_asm_insn ("br\t%1", op);
8224 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
8228 /* Emit RTL insns to initialize the variable parts of a trampoline.
8229 FNADDR is an RTX for the address of the function's pure code.
8230 CXT is an RTX for the static chain value for the function. */
8233 s390_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
8235 emit_move_insn (gen_rtx_MEM (Pmode,
8236 memory_address (Pmode,
8237 plus_constant (addr, (TARGET_64BIT ? 16 : 8)))), cxt);
8238 emit_move_insn (gen_rtx_MEM (Pmode,
8239 memory_address (Pmode,
8240 plus_constant (addr, (TARGET_64BIT ? 24 : 12)))), fnaddr);
8243 /* Return rtx for 64-bit constant formed from the 32-bit subwords
8244 LOW and HIGH, independent of the host word size. */
8247 s390_gen_rtx_const_DI (int high, int low)
8249 #if HOST_BITS_PER_WIDE_INT >= 64
8251 val = (HOST_WIDE_INT)high;
8253 val |= (HOST_WIDE_INT)low;
8255 return GEN_INT (val);
8257 #if HOST_BITS_PER_WIDE_INT >= 32
8258 return immed_double_const ((HOST_WIDE_INT)low, (HOST_WIDE_INT)high, DImode);
8265 /* Output assembler code to FILE to increment profiler label # LABELNO
8266 for profiling a function entry. */
8269 s390_function_profiler (FILE *file, int labelno)
8274 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
8276 fprintf (file, "# function profiler \n");
8278 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
8279 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
8280 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
8282 op[2] = gen_rtx_REG (Pmode, 1);
8283 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8284 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
8286 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
8289 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
8290 op[4] = gen_rtx_CONST (Pmode, op[4]);
8295 output_asm_insn ("stg\t%0,%1", op);
8296 output_asm_insn ("larl\t%2,%3", op);
8297 output_asm_insn ("brasl\t%0,%4", op);
8298 output_asm_insn ("lg\t%0,%1", op);
8302 op[6] = gen_label_rtx ();
8304 output_asm_insn ("st\t%0,%1", op);
8305 output_asm_insn ("bras\t%2,%l6", op);
8306 output_asm_insn (".long\t%4", op);
8307 output_asm_insn (".long\t%3", op);
8308 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8309 output_asm_insn ("l\t%0,0(%2)", op);
8310 output_asm_insn ("l\t%2,4(%2)", op);
8311 output_asm_insn ("basr\t%0,%0", op);
8312 output_asm_insn ("l\t%0,%1", op);
8316 op[5] = gen_label_rtx ();
8317 op[6] = gen_label_rtx ();
8319 output_asm_insn ("st\t%0,%1", op);
8320 output_asm_insn ("bras\t%2,%l6", op);
8321 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
8322 output_asm_insn (".long\t%4-%l5", op);
8323 output_asm_insn (".long\t%3-%l5", op);
8324 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
8325 output_asm_insn ("lr\t%0,%2", op);
8326 output_asm_insn ("a\t%0,0(%2)", op);
8327 output_asm_insn ("a\t%2,4(%2)", op);
8328 output_asm_insn ("basr\t%0,%0", op);
8329 output_asm_insn ("l\t%0,%1", op);
8333 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
8334 into its SYMBOL_REF_FLAGS. */
8337 s390_encode_section_info (tree decl, rtx rtl, int first)
8339 default_encode_section_info (decl, rtl, first);
8341 /* If a variable has a forced alignment to < 2 bytes, mark it with
8342 SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL operand. */
8343 if (TREE_CODE (decl) == VAR_DECL
8344 && DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
8345 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
8348 /* Output thunk to FILE that implements a C++ virtual function call (with
8349 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
8350 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
8351 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
8352 relative to the resulting this pointer. */
8355 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
8356 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8362 /* Operand 0 is the target function. */
8363 op[0] = XEXP (DECL_RTL (function), 0);
8364 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
8367 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
8368 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
8369 op[0] = gen_rtx_CONST (Pmode, op[0]);
8372 /* Operand 1 is the 'this' pointer. */
8373 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8374 op[1] = gen_rtx_REG (Pmode, 3);
8376 op[1] = gen_rtx_REG (Pmode, 2);
8378 /* Operand 2 is the delta. */
8379 op[2] = GEN_INT (delta);
8381 /* Operand 3 is the vcall_offset. */
8382 op[3] = GEN_INT (vcall_offset);
8384 /* Operand 4 is the temporary register. */
8385 op[4] = gen_rtx_REG (Pmode, 1);
8387 /* Operands 5 to 8 can be used as labels. */
8393 /* Operand 9 can be used for temporary register. */
8396 /* Generate code. */
8399 /* Setup literal pool pointer if required. */
8400 if ((!DISP_IN_RANGE (delta)
8401 && !CONST_OK_FOR_K (delta)
8402 && !CONST_OK_FOR_Os (delta))
8403 || (!DISP_IN_RANGE (vcall_offset)
8404 && !CONST_OK_FOR_K (vcall_offset)
8405 && !CONST_OK_FOR_Os (vcall_offset)))
8407 op[5] = gen_label_rtx ();
8408 output_asm_insn ("larl\t%4,%5", op);
8411 /* Add DELTA to this pointer. */
8414 if (CONST_OK_FOR_J (delta))
8415 output_asm_insn ("la\t%1,%2(%1)", op);
8416 else if (DISP_IN_RANGE (delta))
8417 output_asm_insn ("lay\t%1,%2(%1)", op);
8418 else if (CONST_OK_FOR_K (delta))
8419 output_asm_insn ("aghi\t%1,%2", op);
8420 else if (CONST_OK_FOR_Os (delta))
8421 output_asm_insn ("agfi\t%1,%2", op);
8424 op[6] = gen_label_rtx ();
8425 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
8429 /* Perform vcall adjustment. */
8432 if (DISP_IN_RANGE (vcall_offset))
8434 output_asm_insn ("lg\t%4,0(%1)", op);
8435 output_asm_insn ("ag\t%1,%3(%4)", op);
8437 else if (CONST_OK_FOR_K (vcall_offset))
8439 output_asm_insn ("lghi\t%4,%3", op);
8440 output_asm_insn ("ag\t%4,0(%1)", op);
8441 output_asm_insn ("ag\t%1,0(%4)", op);
8443 else if (CONST_OK_FOR_Os (vcall_offset))
8445 output_asm_insn ("lgfi\t%4,%3", op);
8446 output_asm_insn ("ag\t%4,0(%1)", op);
8447 output_asm_insn ("ag\t%1,0(%4)", op);
8451 op[7] = gen_label_rtx ();
8452 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
8453 output_asm_insn ("ag\t%4,0(%1)", op);
8454 output_asm_insn ("ag\t%1,0(%4)", op);
8458 /* Jump to target. */
8459 output_asm_insn ("jg\t%0", op);
8461 /* Output literal pool if required. */
8464 output_asm_insn (".align\t4", op);
8465 targetm.asm_out.internal_label (file, "L",
8466 CODE_LABEL_NUMBER (op[5]));
8470 targetm.asm_out.internal_label (file, "L",
8471 CODE_LABEL_NUMBER (op[6]));
8472 output_asm_insn (".long\t%2", op);
8476 targetm.asm_out.internal_label (file, "L",
8477 CODE_LABEL_NUMBER (op[7]));
8478 output_asm_insn (".long\t%3", op);
8483 /* Setup base pointer if required. */
8485 || (!DISP_IN_RANGE (delta)
8486 && !CONST_OK_FOR_K (delta)
8487 && !CONST_OK_FOR_Os (delta))
8488 || (!DISP_IN_RANGE (delta)
8489 && !CONST_OK_FOR_K (vcall_offset)
8490 && !CONST_OK_FOR_Os (vcall_offset)))
8492 op[5] = gen_label_rtx ();
8493 output_asm_insn ("basr\t%4,0", op);
8494 targetm.asm_out.internal_label (file, "L",
8495 CODE_LABEL_NUMBER (op[5]));
8498 /* Add DELTA to this pointer. */
8501 if (CONST_OK_FOR_J (delta))
8502 output_asm_insn ("la\t%1,%2(%1)", op);
8503 else if (DISP_IN_RANGE (delta))
8504 output_asm_insn ("lay\t%1,%2(%1)", op);
8505 else if (CONST_OK_FOR_K (delta))
8506 output_asm_insn ("ahi\t%1,%2", op);
8507 else if (CONST_OK_FOR_Os (delta))
8508 output_asm_insn ("afi\t%1,%2", op);
8511 op[6] = gen_label_rtx ();
8512 output_asm_insn ("a\t%1,%6-%5(%4)", op);
8516 /* Perform vcall adjustment. */
8519 if (CONST_OK_FOR_J (vcall_offset))
8521 output_asm_insn ("l\t%4,0(%1)", op);
8522 output_asm_insn ("a\t%1,%3(%4)", op);
8524 else if (DISP_IN_RANGE (vcall_offset))
8526 output_asm_insn ("l\t%4,0(%1)", op);
8527 output_asm_insn ("ay\t%1,%3(%4)", op);
8529 else if (CONST_OK_FOR_K (vcall_offset))
8531 output_asm_insn ("lhi\t%4,%3", op);
8532 output_asm_insn ("a\t%4,0(%1)", op);
8533 output_asm_insn ("a\t%1,0(%4)", op);
8535 else if (CONST_OK_FOR_Os (vcall_offset))
8537 output_asm_insn ("iilf\t%4,%3", op);
8538 output_asm_insn ("a\t%4,0(%1)", op);
8539 output_asm_insn ("a\t%1,0(%4)", op);
8543 op[7] = gen_label_rtx ();
8544 output_asm_insn ("l\t%4,%7-%5(%4)", op);
8545 output_asm_insn ("a\t%4,0(%1)", op);
8546 output_asm_insn ("a\t%1,0(%4)", op);
8549 /* We had to clobber the base pointer register.
8550 Re-setup the base pointer (with a different base). */
8551 op[5] = gen_label_rtx ();
8552 output_asm_insn ("basr\t%4,0", op);
8553 targetm.asm_out.internal_label (file, "L",
8554 CODE_LABEL_NUMBER (op[5]));
8557 /* Jump to target. */
8558 op[8] = gen_label_rtx ();
8561 output_asm_insn ("l\t%4,%8-%5(%4)", op);
8563 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8564 /* We cannot call through .plt, since .plt requires %r12 loaded. */
8565 else if (flag_pic == 1)
8567 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8568 output_asm_insn ("l\t%4,%0(%4)", op);
8570 else if (flag_pic == 2)
8572 op[9] = gen_rtx_REG (Pmode, 0);
8573 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
8574 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8575 output_asm_insn ("ar\t%4,%9", op);
8576 output_asm_insn ("l\t%4,0(%4)", op);
8579 output_asm_insn ("br\t%4", op);
8581 /* Output literal pool. */
8582 output_asm_insn (".align\t4", op);
8584 if (nonlocal && flag_pic == 2)
8585 output_asm_insn (".long\t%0", op);
8588 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8589 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
8592 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
8594 output_asm_insn (".long\t%0", op);
8596 output_asm_insn (".long\t%0-%5", op);
8600 targetm.asm_out.internal_label (file, "L",
8601 CODE_LABEL_NUMBER (op[6]));
8602 output_asm_insn (".long\t%2", op);
8606 targetm.asm_out.internal_label (file, "L",
8607 CODE_LABEL_NUMBER (op[7]));
8608 output_asm_insn (".long\t%3", op);
8614 s390_valid_pointer_mode (enum machine_mode mode)
8616 return (mode == SImode || (TARGET_64BIT && mode == DImode));
8619 /* Checks whether the given ARGUMENT_LIST would use a caller
8620 saved register. This is used to decide whether sibling call
8621 optimization could be performed on the respective function
8625 s390_call_saved_register_used (tree argument_list)
8627 CUMULATIVE_ARGS cum;
8629 enum machine_mode mode;
8634 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
8636 while (argument_list)
8638 parameter = TREE_VALUE (argument_list);
8639 argument_list = TREE_CHAIN (argument_list);
8641 gcc_assert (parameter);
8643 /* For an undeclared variable passed as parameter we will get
8644 an ERROR_MARK node here. */
8645 if (TREE_CODE (parameter) == ERROR_MARK)
8648 type = TREE_TYPE (parameter);
8651 mode = TYPE_MODE (type);
8654 if (pass_by_reference (&cum, mode, type, true))
8657 type = build_pointer_type (type);
8660 parm_rtx = s390_function_arg (&cum, mode, type, 0);
8662 s390_function_arg_advance (&cum, mode, type, 0);
8664 if (parm_rtx && REG_P (parm_rtx))
8667 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
8669 if (! call_used_regs[reg + REGNO (parm_rtx)])
8676 /* Return true if the given call expression can be
8677 turned into a sibling call.
8678 DECL holds the declaration of the function to be called whereas
8679 EXP is the call expression itself. */
8682 s390_function_ok_for_sibcall (tree decl, tree exp)
8684 /* The TPF epilogue uses register 1. */
8685 if (TARGET_TPF_PROFILING)
8688 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
8689 which would have to be restored before the sibcall. */
8690 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
8693 /* Register 6 on s390 is available as an argument register but unfortunately
8694 "caller saved". This makes functions needing this register for arguments
8695 not suitable for sibcalls. */
8696 if (TREE_OPERAND (exp, 1)
8697 && s390_call_saved_register_used (TREE_OPERAND (exp, 1)))
8703 /* Return the fixed registers used for condition codes. */
8706 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
8709 *p2 = INVALID_REGNUM;
8714 /* This function is used by the call expanders of the machine description.
8715 It emits the call insn itself together with the necessary operations
8716 to adjust the target address and returns the emitted insn.
8717 ADDR_LOCATION is the target address rtx
8718 TLS_CALL the location of the thread-local symbol
8719 RESULT_REG the register where the result of the call should be stored
8720 RETADDR_REG the register where the return address should be stored
8721 If this parameter is NULL_RTX the call is considered
8722 to be a sibling call. */
8725 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
8728 bool plt_call = false;
8734 /* Direct function calls need special treatment. */
8735 if (GET_CODE (addr_location) == SYMBOL_REF)
8737 /* When calling a global routine in PIC mode, we must
8738 replace the symbol itself with the PLT stub. */
8739 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
8741 addr_location = gen_rtx_UNSPEC (Pmode,
8742 gen_rtvec (1, addr_location),
8744 addr_location = gen_rtx_CONST (Pmode, addr_location);
8748 /* Unless we can use the bras(l) insn, force the
8749 routine address into a register. */
8750 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
8753 addr_location = legitimize_pic_address (addr_location, 0);
8755 addr_location = force_reg (Pmode, addr_location);
8759 /* If it is already an indirect call or the code above moved the
8760 SYMBOL_REF to somewhere else make sure the address can be found in
8762 if (retaddr_reg == NULL_RTX
8763 && GET_CODE (addr_location) != SYMBOL_REF
8766 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
8767 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
8770 addr_location = gen_rtx_MEM (QImode, addr_location);
8771 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
8773 if (result_reg != NULL_RTX)
8774 call = gen_rtx_SET (VOIDmode, result_reg, call);
8776 if (retaddr_reg != NULL_RTX)
8778 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
8780 if (tls_call != NULL_RTX)
8781 vec = gen_rtvec (3, call, clobber,
8782 gen_rtx_USE (VOIDmode, tls_call));
8784 vec = gen_rtvec (2, call, clobber);
8786 call = gen_rtx_PARALLEL (VOIDmode, vec);
8789 insn = emit_call_insn (call);
8791 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
8792 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
8794 /* s390_function_ok_for_sibcall should
8795 have denied sibcalls in this case. */
8796 gcc_assert (retaddr_reg != NULL_RTX);
8798 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
8803 /* Implement CONDITIONAL_REGISTER_USAGE. */
8806 s390_conditional_register_usage (void)
8812 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8813 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8815 if (TARGET_CPU_ZARCH)
8817 fixed_regs[BASE_REGNUM] = 0;
8818 call_used_regs[BASE_REGNUM] = 0;
8819 fixed_regs[RETURN_REGNUM] = 0;
8820 call_used_regs[RETURN_REGNUM] = 0;
8824 for (i = 24; i < 32; i++)
8825 call_used_regs[i] = call_really_used_regs[i] = 0;
8829 for (i = 18; i < 20; i++)
8830 call_used_regs[i] = call_really_used_regs[i] = 0;
8833 if (TARGET_SOFT_FLOAT)
8835 for (i = 16; i < 32; i++)
8836 call_used_regs[i] = fixed_regs[i] = 1;
8840 /* Corresponding function to eh_return expander. */
8842 static GTY(()) rtx s390_tpf_eh_return_symbol;
8844 s390_emit_tpf_eh_return (rtx target)
8848 if (!s390_tpf_eh_return_symbol)
8849 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
8851 reg = gen_rtx_REG (Pmode, 2);
8853 emit_move_insn (reg, target);
8854 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
8855 gen_rtx_REG (Pmode, RETURN_REGNUM));
8856 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
8858 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
8861 /* Rework the prologue/epilogue to avoid saving/restoring
8862 registers unnecessarily. */
8865 s390_optimize_prologue (void)
8867 rtx insn, new_insn, next_insn;
8869 /* Do a final recompute of the frame-related data. */
8871 s390_update_frame_layout ();
8873 /* If all special registers are in fact used, there's nothing we
8874 can do, so no point in walking the insn list. */
8876 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
8877 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
8878 && (TARGET_CPU_ZARCH
8879 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
8880 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
8883 /* Search for prologue/epilogue insns and replace them. */
8885 for (insn = get_insns (); insn; insn = next_insn)
8887 int first, last, off;
8888 rtx set, base, offset;
8890 next_insn = NEXT_INSN (insn);
8892 if (GET_CODE (insn) != INSN)
8895 if (GET_CODE (PATTERN (insn)) == PARALLEL
8896 && store_multiple_operation (PATTERN (insn), VOIDmode))
8898 set = XVECEXP (PATTERN (insn), 0, 0);
8899 first = REGNO (SET_SRC (set));
8900 last = first + XVECLEN (PATTERN (insn), 0) - 1;
8901 offset = const0_rtx;
8902 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8903 off = INTVAL (offset);
8905 if (GET_CODE (base) != REG || off < 0)
8907 if (cfun_frame_layout.first_save_gpr != -1
8908 && (cfun_frame_layout.first_save_gpr < first
8909 || cfun_frame_layout.last_save_gpr > last))
8911 if (REGNO (base) != STACK_POINTER_REGNUM
8912 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8914 if (first > BASE_REGNUM || last < BASE_REGNUM)
8917 if (cfun_frame_layout.first_save_gpr != -1)
8919 new_insn = save_gprs (base,
8920 off + (cfun_frame_layout.first_save_gpr
8921 - first) * UNITS_PER_WORD,
8922 cfun_frame_layout.first_save_gpr,
8923 cfun_frame_layout.last_save_gpr);
8924 new_insn = emit_insn_before (new_insn, insn);
8925 INSN_ADDRESSES_NEW (new_insn, -1);
8932 if (cfun_frame_layout.first_save_gpr == -1
8933 && GET_CODE (PATTERN (insn)) == SET
8934 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
8935 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
8936 || (!TARGET_CPU_ZARCH
8937 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
8938 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
8940 set = PATTERN (insn);
8941 first = REGNO (SET_SRC (set));
8942 offset = const0_rtx;
8943 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8944 off = INTVAL (offset);
8946 if (GET_CODE (base) != REG || off < 0)
8948 if (REGNO (base) != STACK_POINTER_REGNUM
8949 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8956 if (GET_CODE (PATTERN (insn)) == PARALLEL
8957 && load_multiple_operation (PATTERN (insn), VOIDmode))
8959 set = XVECEXP (PATTERN (insn), 0, 0);
8960 first = REGNO (SET_DEST (set));
8961 last = first + XVECLEN (PATTERN (insn), 0) - 1;
8962 offset = const0_rtx;
8963 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
8964 off = INTVAL (offset);
8966 if (GET_CODE (base) != REG || off < 0)
8968 if (cfun_frame_layout.first_restore_gpr != -1
8969 && (cfun_frame_layout.first_restore_gpr < first
8970 || cfun_frame_layout.last_restore_gpr > last))
8972 if (REGNO (base) != STACK_POINTER_REGNUM
8973 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8975 if (first > BASE_REGNUM || last < BASE_REGNUM)
8978 if (cfun_frame_layout.first_restore_gpr != -1)
8980 new_insn = restore_gprs (base,
8981 off + (cfun_frame_layout.first_restore_gpr
8982 - first) * UNITS_PER_WORD,
8983 cfun_frame_layout.first_restore_gpr,
8984 cfun_frame_layout.last_restore_gpr);
8985 new_insn = emit_insn_before (new_insn, insn);
8986 INSN_ADDRESSES_NEW (new_insn, -1);
8993 if (cfun_frame_layout.first_restore_gpr == -1
8994 && GET_CODE (PATTERN (insn)) == SET
8995 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
8996 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
8997 || (!TARGET_CPU_ZARCH
8998 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
8999 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
9001 set = PATTERN (insn);
9002 first = REGNO (SET_DEST (set));
9003 offset = const0_rtx;
9004 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
9005 off = INTVAL (offset);
9007 if (GET_CODE (base) != REG || off < 0)
9009 if (REGNO (base) != STACK_POINTER_REGNUM
9010 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
9019 /* Perform machine-dependent processing. */
9024 bool pool_overflow = false;
9026 /* Make sure all splits have been performed; splits after
9027 machine_dependent_reorg might confuse insn length counts. */
9028 split_all_insns_noflow ();
9030 /* From here on decomposed literal pool addresses must be accepted. */
9031 cfun->machine->decomposed_literal_pool_addresses_ok_p = true;
9033 /* Install the main literal pool and the associated base
9034 register load insns.
9036 In addition, there are two problematic situations we need
9039 - the literal pool might be > 4096 bytes in size, so that
9040 some of its elements cannot be directly accessed
9042 - a branch target might be > 64K away from the branch, so that
9043 it is not possible to use a PC-relative instruction.
9045 To fix those, we split the single literal pool into multiple
9046 pool chunks, reloading the pool base register at various
9047 points throughout the function to ensure it always points to
9048 the pool chunk the following code expects, and / or replace
9049 PC-relative branches by absolute branches.
9051 However, the two problems are interdependent: splitting the
9052 literal pool can move a branch further away from its target,
9053 causing the 64K limit to overflow, and on the other hand,
9054 replacing a PC-relative branch by an absolute branch means
9055 we need to put the branch target address into the literal
9056 pool, possibly causing it to overflow.
9058 So, we loop trying to fix up both problems until we manage
9059 to satisfy both conditions at the same time. Note that the
9060 loop is guaranteed to terminate as every pass of the loop
9061 strictly decreases the total number of PC-relative branches
9062 in the function. (This is not completely true as there
9063 might be branch-over-pool insns introduced by chunkify_start.
9064 Those never need to be split however.) */
9068 struct constant_pool *pool = NULL;
9070 /* Collect the literal pool. */
9073 pool = s390_mainpool_start ();
9075 pool_overflow = true;
9078 /* If literal pool overflowed, start to chunkify it. */
9080 pool = s390_chunkify_start ();
9082 /* Split out-of-range branches. If this has created new
9083 literal pool entries, cancel current chunk list and
9084 recompute it. zSeries machines have large branch
9085 instructions, so we never need to split a branch. */
9086 if (!TARGET_CPU_ZARCH && s390_split_branches ())
9089 s390_chunkify_cancel (pool);
9091 s390_mainpool_cancel (pool);
9096 /* If we made it up to here, both conditions are satisfied.
9097 Finish up literal pool related changes. */
9099 s390_chunkify_finish (pool);
9101 s390_mainpool_finish (pool);
9103 /* We're done splitting branches. */
9104 cfun->machine->split_branches_pending_p = false;
9108 /* Generate out-of-pool execute target insns. */
9109 if (TARGET_CPU_ZARCH)
9111 rtx insn, label, target;
9113 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9115 label = s390_execute_label (insn);
9119 gcc_assert (label != const0_rtx);
9121 target = emit_label (XEXP (label, 0));
9122 INSN_ADDRESSES_NEW (target, -1);
9124 target = emit_insn (s390_execute_target (insn));
9125 INSN_ADDRESSES_NEW (target, -1);
9129 /* Try to optimize prologue and epilogue further. */
9130 s390_optimize_prologue ();
9134 /* Initialize GCC target structure. */
9136 #undef TARGET_ASM_ALIGNED_HI_OP
9137 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9138 #undef TARGET_ASM_ALIGNED_DI_OP
9139 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9140 #undef TARGET_ASM_INTEGER
9141 #define TARGET_ASM_INTEGER s390_assemble_integer
9143 #undef TARGET_ASM_OPEN_PAREN
9144 #define TARGET_ASM_OPEN_PAREN ""
9146 #undef TARGET_ASM_CLOSE_PAREN
9147 #define TARGET_ASM_CLOSE_PAREN ""
9149 #undef TARGET_DEFAULT_TARGET_FLAGS
9150 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
9151 #undef TARGET_HANDLE_OPTION
9152 #define TARGET_HANDLE_OPTION s390_handle_option
9154 #undef TARGET_ENCODE_SECTION_INFO
9155 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
9158 #undef TARGET_HAVE_TLS
9159 #define TARGET_HAVE_TLS true
9161 #undef TARGET_CANNOT_FORCE_CONST_MEM
9162 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
9164 #undef TARGET_DELEGITIMIZE_ADDRESS
9165 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
9167 #undef TARGET_RETURN_IN_MEMORY
9168 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
9170 #undef TARGET_INIT_BUILTINS
9171 #define TARGET_INIT_BUILTINS s390_init_builtins
9172 #undef TARGET_EXPAND_BUILTIN
9173 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
9175 #undef TARGET_ASM_OUTPUT_MI_THUNK
9176 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
9177 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9178 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
9180 #undef TARGET_SCHED_ADJUST_PRIORITY
9181 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
9182 #undef TARGET_SCHED_ISSUE_RATE
9183 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
9184 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9185 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
9187 #undef TARGET_CANNOT_COPY_INSN_P
9188 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
9189 #undef TARGET_RTX_COSTS
9190 #define TARGET_RTX_COSTS s390_rtx_costs
9191 #undef TARGET_ADDRESS_COST
9192 #define TARGET_ADDRESS_COST s390_address_cost
9194 #undef TARGET_MACHINE_DEPENDENT_REORG
9195 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
9197 #undef TARGET_VALID_POINTER_MODE
9198 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
9200 #undef TARGET_BUILD_BUILTIN_VA_LIST
9201 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
9202 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
9203 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
9205 #undef TARGET_PROMOTE_FUNCTION_ARGS
9206 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
9207 #undef TARGET_PROMOTE_FUNCTION_RETURN
9208 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
9209 #undef TARGET_PASS_BY_REFERENCE
9210 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
9212 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
9213 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
9215 #undef TARGET_FIXED_CONDITION_CODE_REGS
9216 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
9218 #undef TARGET_CC_MODES_COMPATIBLE
9219 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
9221 #undef TARGET_INVALID_WITHIN_DOLOOP
9222 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_rtx_null
9225 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
9226 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
9229 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
9230 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
9231 #define TARGET_MANGLE_FUNDAMENTAL_TYPE s390_mangle_fundamental_type
9234 struct gcc_target targetm = TARGET_INITIALIZER;
9236 #include "gt-s390.h"