1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
26 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
45 #include "basic-block.h"
46 #include "integrate.h"
49 #include "target-def.h"
51 #include "langhooks.h"
53 #include "tree-gimple.h"
56 /* Define the specific costs for a given cpu. */
58 struct processor_costs
61 const int m; /* cost of an M instruction. */
62 const int mghi; /* cost of an MGHI instruction. */
63 const int mh; /* cost of an MH instruction. */
64 const int mhi; /* cost of an MHI instruction. */
65 const int ml; /* cost of an ML instruction. */
66 const int mr; /* cost of an MR instruction. */
67 const int ms; /* cost of an MS instruction. */
68 const int msg; /* cost of an MSG instruction. */
69 const int msgf; /* cost of an MSGF instruction. */
70 const int msgfr; /* cost of an MSGFR instruction. */
71 const int msgr; /* cost of an MSGR instruction. */
72 const int msr; /* cost of an MSR instruction. */
73 const int mult_df; /* cost of multiplication in DFmode. */
75 const int sqdbr; /* cost of square root in DFmode. */
76 const int sqebr; /* cost of square root in SFmode. */
77 /* multiply and add */
78 const int madbr; /* cost of multiply and add in DFmode. */
79 const int maebr; /* cost of multiply and add in SFmode. */
92 const struct processor_costs *s390_cost;
95 struct processor_costs z900_cost =
97 COSTS_N_INSNS (5), /* M */
98 COSTS_N_INSNS (10), /* MGHI */
99 COSTS_N_INSNS (5), /* MH */
100 COSTS_N_INSNS (4), /* MHI */
101 COSTS_N_INSNS (5), /* ML */
102 COSTS_N_INSNS (5), /* MR */
103 COSTS_N_INSNS (4), /* MS */
104 COSTS_N_INSNS (15), /* MSG */
105 COSTS_N_INSNS (7), /* MSGF */
106 COSTS_N_INSNS (7), /* MSGFR */
107 COSTS_N_INSNS (10), /* MSGR */
108 COSTS_N_INSNS (4), /* MSR */
109 COSTS_N_INSNS (7), /* multiplication in DFmode */
110 COSTS_N_INSNS (44), /* SQDBR */
111 COSTS_N_INSNS (35), /* SQEBR */
112 COSTS_N_INSNS (18), /* MADBR */
113 COSTS_N_INSNS (13), /* MAEBR */
114 COSTS_N_INSNS (30), /* DDBR */
115 COSTS_N_INSNS (30), /* DDR */
116 COSTS_N_INSNS (27), /* DEBR */
117 COSTS_N_INSNS (26), /* DER */
118 COSTS_N_INSNS (220), /* DLGR */
119 COSTS_N_INSNS (34), /* DLR */
120 COSTS_N_INSNS (34), /* DR */
121 COSTS_N_INSNS (32), /* DSGFR */
122 COSTS_N_INSNS (32), /* DSGR */
126 struct processor_costs z990_cost =
128 COSTS_N_INSNS (4), /* M */
129 COSTS_N_INSNS (2), /* MGHI */
130 COSTS_N_INSNS (2), /* MH */
131 COSTS_N_INSNS (2), /* MHI */
132 COSTS_N_INSNS (4), /* ML */
133 COSTS_N_INSNS (4), /* MR */
134 COSTS_N_INSNS (5), /* MS */
135 COSTS_N_INSNS (6), /* MSG */
136 COSTS_N_INSNS (4), /* MSGF */
137 COSTS_N_INSNS (4), /* MSGFR */
138 COSTS_N_INSNS (4), /* MSGR */
139 COSTS_N_INSNS (4), /* MSR */
140 COSTS_N_INSNS (1), /* multiplication in DFmode */
141 COSTS_N_INSNS (66), /* SQDBR */
142 COSTS_N_INSNS (38), /* SQEBR */
143 COSTS_N_INSNS (1), /* MADBR */
144 COSTS_N_INSNS (1), /* MAEBR */
145 COSTS_N_INSNS (40), /* DDBR */
146 COSTS_N_INSNS (44), /* DDR */
147 COSTS_N_INSNS (26), /* DDBR */
148 COSTS_N_INSNS (28), /* DER */
149 COSTS_N_INSNS (176), /* DLGR */
150 COSTS_N_INSNS (31), /* DLR */
151 COSTS_N_INSNS (31), /* DR */
152 COSTS_N_INSNS (31), /* DSGFR */
153 COSTS_N_INSNS (31), /* DSGR */
157 struct processor_costs z9_109_cost =
159 COSTS_N_INSNS (4), /* M */
160 COSTS_N_INSNS (2), /* MGHI */
161 COSTS_N_INSNS (2), /* MH */
162 COSTS_N_INSNS (2), /* MHI */
163 COSTS_N_INSNS (4), /* ML */
164 COSTS_N_INSNS (4), /* MR */
165 COSTS_N_INSNS (5), /* MS */
166 COSTS_N_INSNS (6), /* MSG */
167 COSTS_N_INSNS (4), /* MSGF */
168 COSTS_N_INSNS (4), /* MSGFR */
169 COSTS_N_INSNS (4), /* MSGR */
170 COSTS_N_INSNS (4), /* MSR */
171 COSTS_N_INSNS (1), /* multiplication in DFmode */
172 COSTS_N_INSNS (66), /* SQDBR */
173 COSTS_N_INSNS (38), /* SQEBR */
174 COSTS_N_INSNS (1), /* MADBR */
175 COSTS_N_INSNS (1), /* MAEBR */
176 COSTS_N_INSNS (40), /* DDBR */
177 COSTS_N_INSNS (37), /* DDR */
178 COSTS_N_INSNS (26), /* DDBR */
179 COSTS_N_INSNS (28), /* DER */
180 COSTS_N_INSNS (30), /* DLGR */
181 COSTS_N_INSNS (23), /* DLR */
182 COSTS_N_INSNS (23), /* DR */
183 COSTS_N_INSNS (24), /* DSGFR */
184 COSTS_N_INSNS (24), /* DSGR */
187 extern int reload_completed;
189 /* Save information from a "cmpxx" operation until the branch or scc is
191 rtx s390_compare_op0, s390_compare_op1;
193 /* Save the result of a compare_and_swap until the branch or scc is
195 rtx s390_compare_emitted = NULL_RTX;
197 /* Structure used to hold the components of a S/390 memory
198 address. A legitimate address on S/390 is of the general
200 base + index + displacement
201 where any of the components is optional.
203 base and index are registers of the class ADDR_REGS,
204 displacement is an unsigned 12-bit immediate constant. */
214 /* Which cpu are we tuning for. */
215 enum processor_type s390_tune = PROCESSOR_max;
216 enum processor_flags s390_tune_flags;
217 /* Which instruction set architecture to use. */
218 enum processor_type s390_arch;
219 enum processor_flags s390_arch_flags;
221 HOST_WIDE_INT s390_warn_framesize = 0;
222 HOST_WIDE_INT s390_stack_size = 0;
223 HOST_WIDE_INT s390_stack_guard = 0;
225 /* The following structure is embedded in the machine
226 specific part of struct function. */
228 struct s390_frame_layout GTY (())
230 /* Offset within stack frame. */
231 HOST_WIDE_INT gprs_offset;
232 HOST_WIDE_INT f0_offset;
233 HOST_WIDE_INT f4_offset;
234 HOST_WIDE_INT f8_offset;
235 HOST_WIDE_INT backchain_offset;
237 /* Number of first and last gpr to be saved, restored. */
239 int first_restore_gpr;
241 int last_restore_gpr;
243 /* Bits standing for floating point registers. Set, if the
244 respective register has to be saved. Starting with reg 16 (f0)
245 at the rightmost bit.
246 Bit 15 - 8 7 6 5 4 3 2 1 0
247 fpr 15 - 8 7 5 3 1 6 4 2 0
248 reg 31 - 24 23 22 21 20 19 18 17 16 */
249 unsigned int fpr_bitmap;
251 /* Number of floating point registers f8-f15 which must be saved. */
254 /* Set if return address needs to be saved.
255 This flag is set by s390_return_addr_rtx if it could not use
256 the initial value of r14 and therefore depends on r14 saved
258 bool save_return_addr_p;
260 /* Size of stack frame. */
261 HOST_WIDE_INT frame_size;
264 /* Define the structure for the machine field in struct function. */
266 struct machine_function GTY(())
268 struct s390_frame_layout frame_layout;
270 /* Literal pool base register. */
273 /* True if we may need to perform branch splitting. */
274 bool split_branches_pending_p;
276 /* Some local-dynamic TLS symbol name. */
277 const char *some_ld_name;
279 bool has_landing_pad_p;
282 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
284 #define cfun_frame_layout (cfun->machine->frame_layout)
285 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
286 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr - \
287 cfun_frame_layout.first_save_gpr + 1) * UNITS_PER_WORD)
288 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
290 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
293 /* Number of GPRs and FPRs used for argument passing. */
294 #define GP_ARG_NUM_REG 5
295 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
297 /* A couple of shortcuts. */
298 #define CONST_OK_FOR_J(x) \
299 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
300 #define CONST_OK_FOR_K(x) \
301 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
302 #define CONST_OK_FOR_Os(x) \
303 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
304 #define CONST_OK_FOR_Op(x) \
305 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
306 #define CONST_OK_FOR_On(x) \
307 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
309 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
312 s390_set_has_landing_pad_p (bool value)
314 cfun->machine->has_landing_pad_p = value;
317 /* If two condition code modes are compatible, return a condition code
318 mode which is compatible with both. Otherwise, return
321 static enum machine_mode
322 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
330 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
331 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
352 /* Return true if SET either doesn't set the CC register, or else
353 the source and destination have matching CC modes and that
354 CC mode is at least as constrained as REQ_MODE. */
357 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
359 enum machine_mode set_mode;
361 gcc_assert (GET_CODE (set) == SET);
363 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
366 set_mode = GET_MODE (SET_DEST (set));
380 if (req_mode != set_mode)
385 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
386 && req_mode != CCSRmode && req_mode != CCURmode)
392 if (req_mode != CCAmode)
400 return (GET_MODE (SET_SRC (set)) == set_mode);
403 /* Return true if every SET in INSN that sets the CC register
404 has source and destination with matching CC modes and that
405 CC mode is at least as constrained as REQ_MODE.
406 If REQ_MODE is VOIDmode, always return false. */
409 s390_match_ccmode (rtx insn, enum machine_mode req_mode)
413 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
414 if (req_mode == VOIDmode)
417 if (GET_CODE (PATTERN (insn)) == SET)
418 return s390_match_ccmode_set (PATTERN (insn), req_mode);
420 if (GET_CODE (PATTERN (insn)) == PARALLEL)
421 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
423 rtx set = XVECEXP (PATTERN (insn), 0, i);
424 if (GET_CODE (set) == SET)
425 if (!s390_match_ccmode_set (set, req_mode))
432 /* If a test-under-mask instruction can be used to implement
433 (compare (and ... OP1) OP2), return the CC mode required
434 to do that. Otherwise, return VOIDmode.
435 MIXED is true if the instruction can distinguish between
436 CC1 and CC2 for mixed selected bits (TMxx), it is false
437 if the instruction cannot (TM). */
440 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
444 /* ??? Fixme: should work on CONST_DOUBLE as well. */
445 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
448 /* Selected bits all zero: CC0.
449 e.g.: int a; if ((a & (16 + 128)) == 0) */
450 if (INTVAL (op2) == 0)
453 /* Selected bits all one: CC3.
454 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
455 if (INTVAL (op2) == INTVAL (op1))
458 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
460 if ((a & (16 + 128)) == 16) -> CCT1
461 if ((a & (16 + 128)) == 128) -> CCT2 */
464 bit1 = exact_log2 (INTVAL (op2));
465 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
466 if (bit0 != -1 && bit1 != -1)
467 return bit0 > bit1 ? CCT1mode : CCT2mode;
473 /* Given a comparison code OP (EQ, NE, etc.) and the operands
474 OP0 and OP1 of a COMPARE, return the mode to be used for the
478 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
484 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
485 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
487 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
488 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
490 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
491 || GET_CODE (op1) == NEG)
492 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
495 if (GET_CODE (op0) == AND)
497 /* Check whether we can potentially do it via TM. */
498 enum machine_mode ccmode;
499 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
500 if (ccmode != VOIDmode)
502 /* Relax CCTmode to CCZmode to allow fall-back to AND
503 if that turns out to be beneficial. */
504 return ccmode == CCTmode ? CCZmode : ccmode;
508 if (register_operand (op0, HImode)
509 && GET_CODE (op1) == CONST_INT
510 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
512 if (register_operand (op0, QImode)
513 && GET_CODE (op1) == CONST_INT
514 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
523 /* The only overflow condition of NEG and ABS happens when
524 -INT_MAX is used as parameter, which stays negative. So
525 we have an overflow from a positive value to a negative.
526 Using CCAP mode the resulting cc can be used for comparisons. */
527 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
528 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
531 /* If constants are involved in an add instruction it is possible to use
532 the resulting cc for comparisons with zero. Knowing the sign of the
533 constant the overflow behavior gets predictable. e.g.:
534 int a, b; if ((b = a + c) > 0)
535 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
536 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
537 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
539 if (INTVAL (XEXP((op0), 1)) < 0)
553 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
554 && GET_CODE (op1) != CONST_INT)
560 if (GET_CODE (op0) == PLUS
561 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
564 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
565 && GET_CODE (op1) != CONST_INT)
571 if (GET_CODE (op0) == MINUS
572 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
575 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
576 && GET_CODE (op1) != CONST_INT)
585 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
586 that we can implement more efficiently. */
589 s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1)
591 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
592 if ((*code == EQ || *code == NE)
593 && *op1 == const0_rtx
594 && GET_CODE (*op0) == ZERO_EXTRACT
595 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
596 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
597 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
599 rtx inner = XEXP (*op0, 0);
600 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
601 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
602 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
604 if (len > 0 && len < modesize
605 && pos >= 0 && pos + len <= modesize
606 && modesize <= HOST_BITS_PER_WIDE_INT)
608 unsigned HOST_WIDE_INT block;
609 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
610 block <<= modesize - pos - len;
612 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
613 gen_int_mode (block, GET_MODE (inner)));
617 /* Narrow AND of memory against immediate to enable TM. */
618 if ((*code == EQ || *code == NE)
619 && *op1 == const0_rtx
620 && GET_CODE (*op0) == AND
621 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
622 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
624 rtx inner = XEXP (*op0, 0);
625 rtx mask = XEXP (*op0, 1);
627 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
628 if (GET_CODE (inner) == SUBREG
629 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
630 && (GET_MODE_SIZE (GET_MODE (inner))
631 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
633 & GET_MODE_MASK (GET_MODE (inner))
634 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
636 inner = SUBREG_REG (inner);
638 /* Do not change volatile MEMs. */
639 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
641 int part = s390_single_part (XEXP (*op0, 1),
642 GET_MODE (inner), QImode, 0);
645 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
646 inner = adjust_address_nv (inner, QImode, part);
647 *op0 = gen_rtx_AND (QImode, inner, mask);
652 /* Narrow comparisons against 0xffff to HImode if possible. */
653 if ((*code == EQ || *code == NE)
654 && GET_CODE (*op1) == CONST_INT
655 && INTVAL (*op1) == 0xffff
656 && SCALAR_INT_MODE_P (GET_MODE (*op0))
657 && (nonzero_bits (*op0, GET_MODE (*op0))
658 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
660 *op0 = gen_lowpart (HImode, *op0);
665 /* Remove redundant UNSPEC_CMPINT conversions if possible. */
666 if (GET_CODE (*op0) == UNSPEC
667 && XINT (*op0, 1) == UNSPEC_CMPINT
668 && XVECLEN (*op0, 0) == 1
669 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
670 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
671 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
672 && *op1 == const0_rtx)
674 enum rtx_code new_code = UNKNOWN;
677 case EQ: new_code = EQ; break;
678 case NE: new_code = NE; break;
679 case LT: new_code = GTU; break;
680 case GT: new_code = LTU; break;
681 case LE: new_code = GEU; break;
682 case GE: new_code = LEU; break;
686 if (new_code != UNKNOWN)
688 *op0 = XVECEXP (*op0, 0, 0);
693 /* Simplify cascaded EQ, NE with const0_rtx. */
694 if ((*code == NE || *code == EQ)
695 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
696 && GET_MODE (*op0) == SImode
697 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
698 && REG_P (XEXP (*op0, 0))
699 && XEXP (*op0, 1) == const0_rtx
700 && *op1 == const0_rtx)
702 if ((*code == EQ && GET_CODE (*op0) == NE)
703 || (*code == NE && GET_CODE (*op0) == EQ))
707 *op0 = XEXP (*op0, 0);
710 /* Prefer register over memory as first operand. */
711 if (MEM_P (*op0) && REG_P (*op1))
713 rtx tem = *op0; *op0 = *op1; *op1 = tem;
714 *code = swap_condition (*code);
718 /* Emit a compare instruction suitable to implement the comparison
719 OP0 CODE OP1. Return the correct condition RTL to be placed in
720 the IF_THEN_ELSE of the conditional branch testing the result. */
723 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
725 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
728 /* Do not output a redundant compare instruction if a compare_and_swap
729 pattern already computed the result and the machine modes are compatible. */
730 if (s390_compare_emitted
731 && (s390_cc_modes_compatible (GET_MODE (s390_compare_emitted), mode)
732 == GET_MODE (s390_compare_emitted)))
733 ret = gen_rtx_fmt_ee (code, VOIDmode, s390_compare_emitted, const0_rtx);
736 rtx cc = gen_rtx_REG (mode, CC_REGNUM);
738 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
739 ret = gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
741 s390_compare_emitted = NULL_RTX;
745 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
746 unconditional jump, else a conditional jump under condition COND. */
749 s390_emit_jump (rtx target, rtx cond)
753 target = gen_rtx_LABEL_REF (VOIDmode, target);
755 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
757 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
758 emit_jump_insn (insn);
761 /* Return branch condition mask to implement a branch
762 specified by CODE. Return -1 for invalid comparisons. */
765 s390_branch_condition_mask (rtx code)
767 const int CC0 = 1 << 3;
768 const int CC1 = 1 << 2;
769 const int CC2 = 1 << 1;
770 const int CC3 = 1 << 0;
772 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
773 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
774 gcc_assert (XEXP (code, 1) == const0_rtx);
776 switch (GET_MODE (XEXP (code, 0)))
780 switch (GET_CODE (code))
783 case NE: return CC1 | CC2 | CC3;
789 switch (GET_CODE (code))
792 case NE: return CC0 | CC2 | CC3;
798 switch (GET_CODE (code))
801 case NE: return CC0 | CC1 | CC3;
807 switch (GET_CODE (code))
810 case NE: return CC0 | CC1 | CC2;
816 switch (GET_CODE (code))
818 case EQ: return CC0 | CC2;
819 case NE: return CC1 | CC3;
825 switch (GET_CODE (code))
827 case LTU: return CC2 | CC3; /* carry */
828 case GEU: return CC0 | CC1; /* no carry */
834 switch (GET_CODE (code))
836 case GTU: return CC0 | CC1; /* borrow */
837 case LEU: return CC2 | CC3; /* no borrow */
843 switch (GET_CODE (code))
845 case EQ: return CC0 | CC2;
846 case NE: return CC1 | CC3;
847 case LTU: return CC1;
848 case GTU: return CC3;
849 case LEU: return CC1 | CC2;
850 case GEU: return CC2 | CC3;
855 switch (GET_CODE (code))
858 case NE: return CC1 | CC2 | CC3;
859 case LTU: return CC1;
860 case GTU: return CC2;
861 case LEU: return CC0 | CC1;
862 case GEU: return CC0 | CC2;
868 switch (GET_CODE (code))
871 case NE: return CC2 | CC1 | CC3;
872 case LTU: return CC2;
873 case GTU: return CC1;
874 case LEU: return CC0 | CC2;
875 case GEU: return CC0 | CC1;
881 switch (GET_CODE (code))
884 case NE: return CC1 | CC2 | CC3;
885 case LT: return CC1 | CC3;
887 case LE: return CC0 | CC1 | CC3;
888 case GE: return CC0 | CC2;
894 switch (GET_CODE (code))
897 case NE: return CC1 | CC2 | CC3;
899 case GT: return CC2 | CC3;
900 case LE: return CC0 | CC1;
901 case GE: return CC0 | CC2 | CC3;
907 switch (GET_CODE (code))
910 case NE: return CC1 | CC2 | CC3;
913 case LE: return CC0 | CC1;
914 case GE: return CC0 | CC2;
915 case UNORDERED: return CC3;
916 case ORDERED: return CC0 | CC1 | CC2;
917 case UNEQ: return CC0 | CC3;
918 case UNLT: return CC1 | CC3;
919 case UNGT: return CC2 | CC3;
920 case UNLE: return CC0 | CC1 | CC3;
921 case UNGE: return CC0 | CC2 | CC3;
922 case LTGT: return CC1 | CC2;
928 switch (GET_CODE (code))
931 case NE: return CC2 | CC1 | CC3;
934 case LE: return CC0 | CC2;
935 case GE: return CC0 | CC1;
936 case UNORDERED: return CC3;
937 case ORDERED: return CC0 | CC2 | CC1;
938 case UNEQ: return CC0 | CC3;
939 case UNLT: return CC2 | CC3;
940 case UNGT: return CC1 | CC3;
941 case UNLE: return CC0 | CC2 | CC3;
942 case UNGE: return CC0 | CC1 | CC3;
943 case LTGT: return CC2 | CC1;
953 /* If INV is false, return assembler mnemonic string to implement
954 a branch specified by CODE. If INV is true, return mnemonic
955 for the corresponding inverted branch. */
958 s390_branch_condition_mnemonic (rtx code, int inv)
960 static const char *const mnemonic[16] =
962 NULL, "o", "h", "nle",
963 "l", "nhe", "lh", "ne",
964 "e", "nlh", "he", "nl",
965 "le", "nh", "no", NULL
968 int mask = s390_branch_condition_mask (code);
969 gcc_assert (mask >= 0);
974 gcc_assert (mask >= 1 && mask <= 14);
976 return mnemonic[mask];
979 /* Return the part of op which has a value different from def.
980 The size of the part is determined by mode.
981 Use this function only if you already know that op really
982 contains such a part. */
984 unsigned HOST_WIDE_INT
985 s390_extract_part (rtx op, enum machine_mode mode, int def)
987 unsigned HOST_WIDE_INT value = 0;
988 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
989 int part_bits = GET_MODE_BITSIZE (mode);
990 unsigned HOST_WIDE_INT part_mask
991 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
994 for (i = 0; i < max_parts; i++)
997 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1001 if ((value & part_mask) != (def & part_mask))
1002 return value & part_mask;
1008 /* If OP is an integer constant of mode MODE with exactly one
1009 part of mode PART_MODE unequal to DEF, return the number of that
1010 part. Otherwise, return -1. */
1013 s390_single_part (rtx op,
1014 enum machine_mode mode,
1015 enum machine_mode part_mode,
1018 unsigned HOST_WIDE_INT value = 0;
1019 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1020 unsigned HOST_WIDE_INT part_mask
1021 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1024 if (GET_CODE (op) != CONST_INT)
1027 for (i = 0; i < n_parts; i++)
1030 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1032 value >>= GET_MODE_BITSIZE (part_mode);
1034 if ((value & part_mask) != (def & part_mask))
1042 return part == -1 ? -1 : n_parts - 1 - part;
1045 /* Check whether we can (and want to) split a double-word
1046 move in mode MODE from SRC to DST into two single-word
1047 moves, moving the subword FIRST_SUBWORD first. */
1050 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1052 /* Floating point registers cannot be split. */
1053 if (FP_REG_P (src) || FP_REG_P (dst))
1056 /* We don't need to split if operands are directly accessible. */
1057 if (s_operand (src, mode) || s_operand (dst, mode))
1060 /* Non-offsettable memory references cannot be split. */
1061 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1062 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1065 /* Moving the first subword must not clobber a register
1066 needed to move the second subword. */
1067 if (register_operand (dst, mode))
1069 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1070 if (reg_overlap_mentioned_p (subreg, src))
1077 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1078 and [MEM2, MEM2 + SIZE] do overlap and false
1082 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1084 rtx addr1, addr2, addr_delta;
1085 HOST_WIDE_INT delta;
1087 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1093 addr1 = XEXP (mem1, 0);
1094 addr2 = XEXP (mem2, 0);
1096 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1098 /* This overlapping check is used by peepholes merging memory block operations.
1099 Overlapping operations would otherwise be recognized by the S/390 hardware
1100 and would fall back to a slower implementation. Allowing overlapping
1101 operations would lead to slow code but not to wrong code. Therefore we are
1102 somewhat optimistic if we cannot prove that the memory blocks are
1104 That's why we return false here although this may accept operations on
1105 overlapping memory areas. */
1106 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1109 delta = INTVAL (addr_delta);
1112 || (delta > 0 && delta < size)
1113 || (delta < 0 && -delta < size))
1119 /* Check whether the address of memory reference MEM2 equals exactly
1120 the address of memory reference MEM1 plus DELTA. Return true if
1121 we can prove this to be the case, false otherwise. */
1124 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1126 rtx addr1, addr2, addr_delta;
1128 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1131 addr1 = XEXP (mem1, 0);
1132 addr2 = XEXP (mem2, 0);
1134 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1135 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1141 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1144 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1147 enum machine_mode wmode = mode;
1148 rtx dst = operands[0];
1149 rtx src1 = operands[1];
1150 rtx src2 = operands[2];
1153 /* If we cannot handle the operation directly, use a temp register. */
1154 if (!s390_logical_operator_ok_p (operands))
1155 dst = gen_reg_rtx (mode);
1157 /* QImode and HImode patterns make sense only if we have a destination
1158 in memory. Otherwise perform the operation in SImode. */
1159 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1162 /* Widen operands if required. */
1165 if (GET_CODE (dst) == SUBREG
1166 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1168 else if (REG_P (dst))
1169 dst = gen_rtx_SUBREG (wmode, dst, 0);
1171 dst = gen_reg_rtx (wmode);
1173 if (GET_CODE (src1) == SUBREG
1174 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1176 else if (GET_MODE (src1) != VOIDmode)
1177 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1179 if (GET_CODE (src2) == SUBREG
1180 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1182 else if (GET_MODE (src2) != VOIDmode)
1183 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1186 /* Emit the instruction. */
1187 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1188 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1189 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1191 /* Fix up the destination if needed. */
1192 if (dst != operands[0])
1193 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1196 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1199 s390_logical_operator_ok_p (rtx *operands)
1201 /* If the destination operand is in memory, it needs to coincide
1202 with one of the source operands. After reload, it has to be
1203 the first source operand. */
1204 if (GET_CODE (operands[0]) == MEM)
1205 return rtx_equal_p (operands[0], operands[1])
1206 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1211 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1212 operand IMMOP to switch from SS to SI type instructions. */
1215 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1217 int def = code == AND ? -1 : 0;
1221 gcc_assert (GET_CODE (*memop) == MEM);
1222 gcc_assert (!MEM_VOLATILE_P (*memop));
1224 mask = s390_extract_part (*immop, QImode, def);
1225 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1226 gcc_assert (part >= 0);
1228 *memop = adjust_address (*memop, QImode, part);
1229 *immop = gen_int_mode (mask, QImode);
1233 /* How to allocate a 'struct machine_function'. */
1235 static struct machine_function *
1236 s390_init_machine_status (void)
1238 return ggc_alloc_cleared (sizeof (struct machine_function));
1241 /* Change optimizations to be performed, depending on the
1244 LEVEL is the optimization level specified; 2 if `-O2' is
1245 specified, 1 if `-O' is specified, and 0 if neither is specified.
1247 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1250 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1252 /* ??? There are apparently still problems with -fcaller-saves. */
1253 flag_caller_saves = 0;
1255 /* By default, always emit DWARF-2 unwind info. This allows debugging
1256 without maintaining a stack frame back-chain. */
1257 flag_asynchronous_unwind_tables = 1;
1259 /* Use MVCLE instructions to decrease code size if requested. */
1261 target_flags |= MASK_MVCLE;
1264 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1265 to the associated processor_type and processor_flags if so. */
1268 s390_handle_arch_option (const char *arg,
1269 enum processor_type *type,
1270 enum processor_flags *flags)
1274 const char *const name; /* processor name or nickname. */
1275 const enum processor_type processor;
1276 const enum processor_flags flags;
1278 const processor_alias_table[] =
1280 {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
1281 {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
1282 {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
1283 {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
1284 | PF_LONG_DISPLACEMENT},
1285 {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH
1286 | PF_LONG_DISPLACEMENT | PF_EXTIMM},
1290 for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++)
1291 if (strcmp (arg, processor_alias_table[i].name) == 0)
1293 *type = processor_alias_table[i].processor;
1294 *flags = processor_alias_table[i].flags;
1300 /* Implement TARGET_HANDLE_OPTION. */
1303 s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
1308 return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags);
1310 case OPT_mstack_guard_:
1311 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1)
1313 if (exact_log2 (s390_stack_guard) == -1)
1314 error ("stack guard value must be an exact power of 2");
1317 case OPT_mstack_size_:
1318 if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1)
1320 if (exact_log2 (s390_stack_size) == -1)
1321 error ("stack size must be an exact power of 2");
1325 return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags);
1327 case OPT_mwarn_framesize_:
1328 return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1;
1336 override_options (void)
1338 /* Set up function hooks. */
1339 init_machine_status = s390_init_machine_status;
1341 /* Architecture mode defaults according to ABI. */
1342 if (!(target_flags_explicit & MASK_ZARCH))
1345 target_flags |= MASK_ZARCH;
1347 target_flags &= ~MASK_ZARCH;
1350 /* Determine processor architectural level. */
1351 if (!s390_arch_string)
1353 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
1354 s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags);
1357 /* Determine processor to tune for. */
1358 if (s390_tune == PROCESSOR_max)
1360 s390_tune = s390_arch;
1361 s390_tune_flags = s390_arch_flags;
1364 /* Sanity checks. */
1365 if (TARGET_ZARCH && !(s390_arch_flags & PF_ZARCH))
1366 error ("z/Architecture mode not supported on %s", s390_arch_string);
1367 if (TARGET_64BIT && !TARGET_ZARCH)
1368 error ("64-bit ABI not supported in ESA/390 mode");
1370 /* Set processor cost function. */
1371 if (s390_tune == PROCESSOR_2094_Z9_109)
1372 s390_cost = &z9_109_cost;
1373 else if (s390_tune == PROCESSOR_2084_Z990)
1374 s390_cost = &z990_cost;
1376 s390_cost = &z900_cost;
1378 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1379 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1382 if (s390_stack_size)
1384 if (!s390_stack_guard)
1385 error ("-mstack-size implies use of -mstack-guard");
1386 else if (s390_stack_guard >= s390_stack_size)
1387 error ("stack size must be greater than the stack guard value");
1388 else if (s390_stack_size > 1 << 16)
1389 error ("stack size must not be greater than 64k");
1391 else if (s390_stack_guard)
1392 error ("-mstack-guard implies use of -mstack-size");
1395 /* Map for smallest class containing reg regno. */
1397 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1398 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1399 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1400 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1401 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1402 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1403 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1404 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1405 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1406 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1407 ACCESS_REGS, ACCESS_REGS
1410 /* Return attribute type of insn. */
1412 static enum attr_type
1413 s390_safe_attr_type (rtx insn)
1415 if (recog_memoized (insn) >= 0)
1416 return get_attr_type (insn);
1421 /* Return true if DISP is a valid short displacement. */
1424 s390_short_displacement (rtx disp)
1426 /* No displacement is OK. */
1430 /* Integer displacement in range. */
1431 if (GET_CODE (disp) == CONST_INT)
1432 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1434 /* GOT offset is not OK, the GOT can be large. */
1435 if (GET_CODE (disp) == CONST
1436 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1437 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1438 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1441 /* All other symbolic constants are literal pool references,
1442 which are OK as the literal pool must be small. */
1443 if (GET_CODE (disp) == CONST)
1449 /* Decompose a RTL expression ADDR for a memory address into
1450 its components, returned in OUT.
1452 Returns false if ADDR is not a valid memory address, true
1453 otherwise. If OUT is NULL, don't return the components,
1454 but check for validity only.
1456 Note: Only addresses in canonical form are recognized.
1457 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1458 canonical form so that they will be recognized. */
1461 s390_decompose_address (rtx addr, struct s390_address *out)
1463 HOST_WIDE_INT offset = 0;
1464 rtx base = NULL_RTX;
1465 rtx indx = NULL_RTX;
1466 rtx disp = NULL_RTX;
1468 bool pointer = false;
1469 bool base_ptr = false;
1470 bool indx_ptr = false;
1472 /* Decompose address into base + index + displacement. */
1474 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1477 else if (GET_CODE (addr) == PLUS)
1479 rtx op0 = XEXP (addr, 0);
1480 rtx op1 = XEXP (addr, 1);
1481 enum rtx_code code0 = GET_CODE (op0);
1482 enum rtx_code code1 = GET_CODE (op1);
1484 if (code0 == REG || code0 == UNSPEC)
1486 if (code1 == REG || code1 == UNSPEC)
1488 indx = op0; /* index + base */
1494 base = op0; /* base + displacement */
1499 else if (code0 == PLUS)
1501 indx = XEXP (op0, 0); /* index + base + disp */
1502 base = XEXP (op0, 1);
1513 disp = addr; /* displacement */
1515 /* Extract integer part of displacement. */
1519 if (GET_CODE (disp) == CONST_INT)
1521 offset = INTVAL (disp);
1524 else if (GET_CODE (disp) == CONST
1525 && GET_CODE (XEXP (disp, 0)) == PLUS
1526 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1528 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1529 disp = XEXP (XEXP (disp, 0), 0);
1533 /* Strip off CONST here to avoid special case tests later. */
1534 if (disp && GET_CODE (disp) == CONST)
1535 disp = XEXP (disp, 0);
1537 /* We can convert literal pool addresses to
1538 displacements by basing them off the base register. */
1539 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1541 /* Either base or index must be free to hold the base register. */
1543 base = gen_rtx_REG (Pmode, BASE_REGNUM);
1545 indx = gen_rtx_REG (Pmode, BASE_REGNUM);
1549 /* Mark up the displacement. */
1550 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1551 UNSPEC_LTREL_OFFSET);
1554 /* Validate base register. */
1557 if (GET_CODE (base) == UNSPEC)
1558 switch (XINT (base, 1))
1562 disp = gen_rtx_UNSPEC (Pmode,
1563 gen_rtvec (1, XVECEXP (base, 0, 0)),
1564 UNSPEC_LTREL_OFFSET);
1568 base = gen_rtx_REG (Pmode, BASE_REGNUM);
1571 case UNSPEC_LTREL_BASE:
1572 base = gen_rtx_REG (Pmode, BASE_REGNUM);
1579 if (GET_CODE (base) != REG || GET_MODE (base) != Pmode)
1582 if (REGNO (base) == BASE_REGNUM
1583 || REGNO (base) == STACK_POINTER_REGNUM
1584 || REGNO (base) == FRAME_POINTER_REGNUM
1585 || ((reload_completed || reload_in_progress)
1586 && frame_pointer_needed
1587 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1588 || REGNO (base) == ARG_POINTER_REGNUM
1590 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1591 pointer = base_ptr = true;
1594 /* Validate index register. */
1597 if (GET_CODE (indx) == UNSPEC)
1598 switch (XINT (indx, 1))
1602 disp = gen_rtx_UNSPEC (Pmode,
1603 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1604 UNSPEC_LTREL_OFFSET);
1608 indx = gen_rtx_REG (Pmode, BASE_REGNUM);
1611 case UNSPEC_LTREL_BASE:
1612 indx = gen_rtx_REG (Pmode, BASE_REGNUM);
1619 if (GET_CODE (indx) != REG || GET_MODE (indx) != Pmode)
1622 if (REGNO (indx) == BASE_REGNUM
1623 || REGNO (indx) == STACK_POINTER_REGNUM
1624 || REGNO (indx) == FRAME_POINTER_REGNUM
1625 || ((reload_completed || reload_in_progress)
1626 && frame_pointer_needed
1627 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1628 || REGNO (indx) == ARG_POINTER_REGNUM
1630 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1631 pointer = indx_ptr = true;
1634 /* Prefer to use pointer as base, not index. */
1635 if (base && indx && !base_ptr
1636 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1643 /* Validate displacement. */
1646 /* If virtual registers are involved, the displacement will change later
1647 anyway as the virtual registers get eliminated. This could make a
1648 valid displacement invalid, but it is more likely to make an invalid
1649 displacement valid, because we sometimes access the register save area
1650 via negative offsets to one of those registers.
1651 Thus we don't check the displacement for validity here. If after
1652 elimination the displacement turns out to be invalid after all,
1653 this is fixed up by reload in any case. */
1654 if (base != arg_pointer_rtx
1655 && indx != arg_pointer_rtx
1656 && base != return_address_pointer_rtx
1657 && indx != return_address_pointer_rtx
1658 && base != frame_pointer_rtx
1659 && indx != frame_pointer_rtx
1660 && base != virtual_stack_vars_rtx
1661 && indx != virtual_stack_vars_rtx)
1662 if (!DISP_IN_RANGE (offset))
1667 /* All the special cases are pointers. */
1670 /* In the small-PIC case, the linker converts @GOT
1671 and @GOTNTPOFF offsets to possible displacements. */
1672 if (GET_CODE (disp) == UNSPEC
1673 && (XINT (disp, 1) == UNSPEC_GOT
1674 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1681 /* Accept chunkified literal pool symbol references. */
1682 else if (GET_CODE (disp) == MINUS
1683 && GET_CODE (XEXP (disp, 0)) == LABEL_REF
1684 && GET_CODE (XEXP (disp, 1)) == LABEL_REF)
1689 /* Accept literal pool references. */
1690 else if (GET_CODE (disp) == UNSPEC
1691 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
1693 orig_disp = gen_rtx_CONST (Pmode, disp);
1696 /* If we have an offset, make sure it does not
1697 exceed the size of the constant pool entry. */
1698 rtx sym = XVECEXP (disp, 0, 0);
1699 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
1702 orig_disp = plus_constant (orig_disp, offset);
1717 out->disp = orig_disp;
1718 out->pointer = pointer;
1724 /* Return true if CODE is a valid address without index. */
1727 s390_legitimate_address_without_index_p (rtx op)
1729 struct s390_address addr;
1731 if (!s390_decompose_address (XEXP (op, 0), &addr))
1739 /* Return 1 if OP is a valid operand for a C constraint, 0 else. */
1742 s390_extra_constraint_str (rtx op, int c, const char * str)
1744 struct s390_address addr;
1746 gcc_assert (c == str[0]);
1748 /* Check for offsettable variants of memory constraints. */
1751 /* Only accept non-volatile MEMs. */
1752 if (!MEM_P (op) || MEM_VOLATILE_P (op))
1755 if ((reload_completed || reload_in_progress)
1756 ? !offsettable_memref_p (op)
1757 : !offsettable_nonstrict_memref_p (op))
1763 /* Check for non-literal-pool variants of memory constraints. */
1766 if (GET_CODE (op) != MEM)
1768 if (!s390_decompose_address (XEXP (op, 0), &addr))
1770 if (addr.base && REG_P (addr.base) && REGNO (addr.base) == BASE_REGNUM)
1772 if (addr.indx && REG_P (addr.indx) && REGNO (addr.indx) == BASE_REGNUM)
1781 if (GET_CODE (op) != MEM)
1783 if (!s390_decompose_address (XEXP (op, 0), &addr))
1788 if (TARGET_LONG_DISPLACEMENT)
1790 if (!s390_short_displacement (addr.disp))
1796 if (GET_CODE (op) != MEM)
1799 if (TARGET_LONG_DISPLACEMENT)
1801 if (!s390_decompose_address (XEXP (op, 0), &addr))
1803 if (!s390_short_displacement (addr.disp))
1809 if (!TARGET_LONG_DISPLACEMENT)
1811 if (GET_CODE (op) != MEM)
1813 if (!s390_decompose_address (XEXP (op, 0), &addr))
1817 if (s390_short_displacement (addr.disp))
1822 if (!TARGET_LONG_DISPLACEMENT)
1824 if (GET_CODE (op) != MEM)
1826 /* Any invalid address here will be fixed up by reload,
1827 so accept it for the most generic constraint. */
1828 if (s390_decompose_address (XEXP (op, 0), &addr)
1829 && s390_short_displacement (addr.disp))
1834 if (TARGET_LONG_DISPLACEMENT)
1836 if (!s390_decompose_address (op, &addr))
1838 if (!s390_short_displacement (addr.disp))
1844 if (!TARGET_LONG_DISPLACEMENT)
1846 /* Any invalid address here will be fixed up by reload,
1847 so accept it for the most generic constraint. */
1848 if (s390_decompose_address (op, &addr)
1849 && s390_short_displacement (addr.disp))
1854 return shift_count_operand (op, VOIDmode);
1863 /* Return true if VALUE matches the constraint STR. */
1866 s390_const_double_ok_for_constraint_p (rtx value,
1870 gcc_assert (c == str[0]);
1875 /* The floating point zero constant. */
1876 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
1877 && value == CONST0_RTX (GET_MODE (value)));
1884 /* Return true if VALUE matches the constraint STR. */
1887 s390_const_ok_for_constraint_p (HOST_WIDE_INT value,
1891 enum machine_mode mode, part_mode;
1893 int part, part_goal;
1895 gcc_assert (c == str[0]);
1900 return (unsigned int)value < 256;
1903 return (unsigned int)value < 4096;
1906 return value >= -32768 && value < 32768;
1909 return (TARGET_LONG_DISPLACEMENT ?
1910 (value >= -524288 && value <= 524287)
1911 : (value >= 0 && value <= 4095));
1913 return value == 2147483647;
1919 part_goal = str[1] - '0';
1923 case 'Q': part_mode = QImode; break;
1924 case 'H': part_mode = HImode; break;
1925 case 'S': part_mode = SImode; break;
1931 case 'H': mode = HImode; break;
1932 case 'S': mode = SImode; break;
1933 case 'D': mode = DImode; break;
1939 case '0': def = 0; break;
1940 case 'F': def = -1; break;
1944 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
1947 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
1950 if (part_goal != -1 && part_goal != part)
1962 return trunc_int_for_mode (value, SImode) == value;
1966 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
1970 || s390_single_part (GEN_INT (value), DImode, SImode, -1) == 1;
1978 return legitimate_reload_constant_p (GEN_INT (value));
1987 /* Compute a (partial) cost for rtx X. Return true if the complete
1988 cost has been computed, and false if subexpressions should be
1989 scanned. In either case, *TOTAL contains the cost result.
1990 CODE contains GET_CODE (x), OUTER_CODE contains the code
1991 of the superexpression of x. */
1994 s390_rtx_costs (rtx x, int code, int outer_code, int *total)
2017 *total = COSTS_N_INSNS (1);
2022 /* Check for multiply and add. */
2023 if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
2024 && GET_CODE (XEXP (x, 0)) == MULT
2025 && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD)
2027 /* This is the multiply and add case. */
2028 if (GET_MODE (x) == DFmode)
2029 *total = s390_cost->madbr;
2031 *total = s390_cost->maebr;
2032 *total += rtx_cost (XEXP (XEXP (x, 0), 0), MULT)
2033 + rtx_cost (XEXP (XEXP (x, 0), 1), MULT)
2034 + rtx_cost (XEXP (x, 1), code);
2035 return true; /* Do not do an additional recursive descent. */
2037 *total = COSTS_N_INSNS (1);
2041 switch (GET_MODE (x))
2045 rtx left = XEXP (x, 0);
2046 rtx right = XEXP (x, 1);
2047 if (GET_CODE (right) == CONST_INT
2048 && CONST_OK_FOR_K (INTVAL (right)))
2049 *total = s390_cost->mhi;
2050 else if (GET_CODE (left) == SIGN_EXTEND)
2051 *total = s390_cost->mh;
2053 *total = s390_cost->ms; /* msr, ms, msy */
2058 rtx left = XEXP (x, 0);
2059 rtx right = XEXP (x, 1);
2062 if (GET_CODE (right) == CONST_INT
2063 && CONST_OK_FOR_K (INTVAL (right)))
2064 *total = s390_cost->mghi;
2065 else if (GET_CODE (left) == SIGN_EXTEND)
2066 *total = s390_cost->msgf;
2068 *total = s390_cost->msg; /* msgr, msg */
2070 else /* TARGET_31BIT */
2072 if (GET_CODE (left) == SIGN_EXTEND
2073 && GET_CODE (right) == SIGN_EXTEND)
2074 /* mulsidi case: mr, m */
2075 *total = s390_cost->m;
2076 else if (GET_CODE (left) == ZERO_EXTEND
2077 && GET_CODE (right) == ZERO_EXTEND
2078 && TARGET_CPU_ZARCH)
2079 /* umulsidi case: ml, mlr */
2080 *total = s390_cost->ml;
2082 /* Complex calculation is required. */
2083 *total = COSTS_N_INSNS (40);
2089 *total = s390_cost->mult_df;
2098 if (GET_MODE (x) == TImode) /* 128 bit division */
2099 *total = s390_cost->dlgr;
2100 else if (GET_MODE (x) == DImode)
2102 rtx right = XEXP (x, 1);
2103 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2104 *total = s390_cost->dlr;
2105 else /* 64 by 64 bit division */
2106 *total = s390_cost->dlgr;
2108 else if (GET_MODE (x) == SImode) /* 32 bit division */
2109 *total = s390_cost->dlr;
2114 if (GET_MODE (x) == DImode)
2116 rtx right = XEXP (x, 1);
2117 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2119 *total = s390_cost->dsgfr;
2121 *total = s390_cost->dr;
2122 else /* 64 by 64 bit division */
2123 *total = s390_cost->dsgr;
2125 else if (GET_MODE (x) == SImode) /* 32 bit division */
2126 *total = s390_cost->dlr;
2127 else if (GET_MODE (x) == SFmode)
2129 if (TARGET_IEEE_FLOAT)
2130 *total = s390_cost->debr;
2131 else /* TARGET_IBM_FLOAT */
2132 *total = s390_cost->der;
2134 else if (GET_MODE (x) == DFmode)
2136 if (TARGET_IEEE_FLOAT)
2137 *total = s390_cost->ddbr;
2138 else /* TARGET_IBM_FLOAT */
2139 *total = s390_cost->ddr;
2144 if (GET_MODE (x) == SFmode)
2145 *total = s390_cost->sqebr;
2147 *total = s390_cost->sqdbr;
2152 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2153 || outer_code == PLUS || outer_code == MINUS
2154 || outer_code == COMPARE)
2159 *total = COSTS_N_INSNS (1);
2160 if (GET_CODE (XEXP (x, 0)) == AND
2161 && GET_CODE (XEXP (x, 1)) == CONST_INT
2162 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2164 rtx op0 = XEXP (XEXP (x, 0), 0);
2165 rtx op1 = XEXP (XEXP (x, 0), 1);
2166 rtx op2 = XEXP (x, 1);
2168 if (memory_operand (op0, GET_MODE (op0))
2169 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2171 if (register_operand (op0, GET_MODE (op0))
2172 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2182 /* Return the cost of an address rtx ADDR. */
2185 s390_address_cost (rtx addr)
2187 struct s390_address ad;
2188 if (!s390_decompose_address (addr, &ad))
2191 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2194 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2195 otherwise return 0. */
2198 tls_symbolic_operand (rtx op)
2200 if (GET_CODE (op) != SYMBOL_REF)
2202 return SYMBOL_REF_TLS_MODEL (op);
2205 /* Split DImode access register reference REG (on 64-bit) into its constituent
2206 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2207 gen_highpart cannot be used as they assume all registers are word-sized,
2208 while our access registers have only half that size. */
2211 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2213 gcc_assert (TARGET_64BIT);
2214 gcc_assert (ACCESS_REG_P (reg));
2215 gcc_assert (GET_MODE (reg) == DImode);
2216 gcc_assert (!(REGNO (reg) & 1));
2218 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2219 *hi = gen_rtx_REG (SImode, REGNO (reg));
2222 /* Return true if OP contains a symbol reference */
2225 symbolic_reference_mentioned_p (rtx op)
2230 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2233 fmt = GET_RTX_FORMAT (GET_CODE (op));
2234 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2240 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2241 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2245 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2252 /* Return true if OP contains a reference to a thread-local symbol. */
2255 tls_symbolic_reference_mentioned_p (rtx op)
2260 if (GET_CODE (op) == SYMBOL_REF)
2261 return tls_symbolic_operand (op);
2263 fmt = GET_RTX_FORMAT (GET_CODE (op));
2264 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2270 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2271 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2275 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2283 /* Return true if OP is a legitimate general operand when
2284 generating PIC code. It is given that flag_pic is on
2285 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2288 legitimate_pic_operand_p (rtx op)
2290 /* Accept all non-symbolic constants. */
2291 if (!SYMBOLIC_CONST (op))
2294 /* Reject everything else; must be handled
2295 via emit_symbolic_move. */
2299 /* Returns true if the constant value OP is a legitimate general operand.
2300 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2303 legitimate_constant_p (rtx op)
2305 /* Accept all non-symbolic constants. */
2306 if (!SYMBOLIC_CONST (op))
2309 /* Accept immediate LARL operands. */
2310 if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
2313 /* Thread-local symbols are never legal constants. This is
2314 so that emit_call knows that computing such addresses
2315 might require a function call. */
2316 if (TLS_SYMBOLIC_CONST (op))
2319 /* In the PIC case, symbolic constants must *not* be
2320 forced into the literal pool. We accept them here,
2321 so that they will be handled by emit_symbolic_move. */
2325 /* All remaining non-PIC symbolic constants are
2326 forced into the literal pool. */
2330 /* Determine if it's legal to put X into the constant pool. This
2331 is not possible if X contains the address of a symbol that is
2332 not constant (TLS) or not known at final link time (PIC). */
2335 s390_cannot_force_const_mem (rtx x)
2337 switch (GET_CODE (x))
2341 /* Accept all non-symbolic constants. */
2345 /* Labels are OK iff we are non-PIC. */
2346 return flag_pic != 0;
2349 /* 'Naked' TLS symbol references are never OK,
2350 non-TLS symbols are OK iff we are non-PIC. */
2351 if (tls_symbolic_operand (x))
2354 return flag_pic != 0;
2357 return s390_cannot_force_const_mem (XEXP (x, 0));
2360 return s390_cannot_force_const_mem (XEXP (x, 0))
2361 || s390_cannot_force_const_mem (XEXP (x, 1));
2364 switch (XINT (x, 1))
2366 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2367 case UNSPEC_LTREL_OFFSET:
2375 case UNSPEC_GOTNTPOFF:
2376 case UNSPEC_INDNTPOFF:
2379 /* If the literal pool shares the code section, be put
2380 execute template placeholders into the pool as well. */
2382 return TARGET_CPU_ZARCH;
2394 /* Returns true if the constant value OP is a legitimate general
2395 operand during and after reload. The difference to
2396 legitimate_constant_p is that this function will not accept
2397 a constant that would need to be forced to the literal pool
2398 before it can be used as operand. */
2401 legitimate_reload_constant_p (rtx op)
2403 /* Accept la(y) operands. */
2404 if (GET_CODE (op) == CONST_INT
2405 && DISP_IN_RANGE (INTVAL (op)))
2408 /* Accept l(g)hi/l(g)fi operands. */
2409 if (GET_CODE (op) == CONST_INT
2410 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2413 /* Accept lliXX operands. */
2415 && GET_CODE (op) == CONST_INT
2416 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2417 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2421 && GET_CODE (op) == CONST_INT
2422 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2423 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2426 /* Accept larl operands. */
2427 if (TARGET_CPU_ZARCH
2428 && larl_operand (op, VOIDmode))
2431 /* Accept lzXX operands. */
2432 if (GET_CODE (op) == CONST_DOUBLE
2433 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
2436 /* Accept double-word operands that can be split. */
2437 if (GET_CODE (op) == CONST_INT
2438 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2440 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2441 rtx hi = operand_subword (op, 0, 0, dword_mode);
2442 rtx lo = operand_subword (op, 1, 0, dword_mode);
2443 return legitimate_reload_constant_p (hi)
2444 && legitimate_reload_constant_p (lo);
2447 /* Everything else cannot be handled without reload. */
2451 /* Given an rtx OP being reloaded into a reg required to be in class CLASS,
2452 return the class of reg to actually use. */
2455 s390_preferred_reload_class (rtx op, enum reg_class class)
2457 switch (GET_CODE (op))
2459 /* Constants we cannot reload must be forced into the
2464 if (legitimate_reload_constant_p (op))
2469 /* If a symbolic constant or a PLUS is reloaded,
2470 it is most likely being used as an address, so
2471 prefer ADDR_REGS. If 'class' is not a superset
2472 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2477 if (reg_class_subset_p (ADDR_REGS, class))
2489 /* Return the register class of a scratch register needed to
2490 load IN into a register of class CLASS in MODE.
2492 We need a temporary when loading a PLUS expression which
2493 is not a legitimate operand of the LOAD ADDRESS instruction. */
2496 s390_secondary_input_reload_class (enum reg_class class,
2497 enum machine_mode mode, rtx in)
2499 if (s390_plus_operand (in, mode))
2502 if (reg_classes_intersect_p (CC_REGS, class))
2503 return GENERAL_REGS;
2508 /* Return the register class of a scratch register needed to
2509 store a register of class CLASS in MODE into OUT:
2511 We need a temporary when storing a double-word to a
2512 non-offsettable memory address. */
2515 s390_secondary_output_reload_class (enum reg_class class,
2516 enum machine_mode mode, rtx out)
2518 if ((TARGET_64BIT ? mode == TImode
2519 : (mode == DImode || mode == DFmode))
2520 && reg_classes_intersect_p (GENERAL_REGS, class)
2521 && GET_CODE (out) == MEM
2522 && GET_CODE (XEXP (out, 0)) == PLUS
2523 && GET_CODE (XEXP (XEXP (out, 0), 0)) == PLUS
2524 && GET_CODE (XEXP (XEXP (out, 0), 1)) == CONST_INT
2525 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (out, 0), 1))
2526 + GET_MODE_SIZE (mode) - 1))
2529 if (reg_classes_intersect_p (CC_REGS, class))
2530 return GENERAL_REGS;
2535 /* Generate code to load SRC, which is PLUS that is not a
2536 legitimate operand for the LA instruction, into TARGET.
2537 SCRATCH may be used as scratch register. */
2540 s390_expand_plus_operand (rtx target, rtx src,
2544 struct s390_address ad;
2546 /* src must be a PLUS; get its two operands. */
2547 gcc_assert (GET_CODE (src) == PLUS);
2548 gcc_assert (GET_MODE (src) == Pmode);
2550 /* Check if any of the two operands is already scheduled
2551 for replacement by reload. This can happen e.g. when
2552 float registers occur in an address. */
2553 sum1 = find_replacement (&XEXP (src, 0));
2554 sum2 = find_replacement (&XEXP (src, 1));
2555 src = gen_rtx_PLUS (Pmode, sum1, sum2);
2557 /* If the address is already strictly valid, there's nothing to do. */
2558 if (!s390_decompose_address (src, &ad)
2559 || (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
2560 || (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx)))
2562 /* Otherwise, one of the operands cannot be an address register;
2563 we reload its value into the scratch register. */
2564 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
2566 emit_move_insn (scratch, sum1);
2569 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
2571 emit_move_insn (scratch, sum2);
2575 /* According to the way these invalid addresses are generated
2576 in reload.c, it should never happen (at least on s390) that
2577 *neither* of the PLUS components, after find_replacements
2578 was applied, is an address register. */
2579 if (sum1 == scratch && sum2 == scratch)
2585 src = gen_rtx_PLUS (Pmode, sum1, sum2);
2588 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
2589 is only ever performed on addresses, so we can mark the
2590 sum as legitimate for LA in any case. */
2591 s390_load_address (target, src);
2595 /* Return true if ADDR is a valid memory address.
2596 STRICT specifies whether strict register checking applies. */
2599 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2600 rtx addr, int strict)
2602 struct s390_address ad;
2603 if (!s390_decompose_address (addr, &ad))
2608 if (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
2610 if (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx))
2615 if (ad.base && !REG_OK_FOR_BASE_NONSTRICT_P (ad.base))
2617 if (ad.indx && !REG_OK_FOR_INDEX_NONSTRICT_P (ad.indx))
2624 /* Return true if OP is a valid operand for the LA instruction.
2625 In 31-bit, we need to prove that the result is used as an
2626 address, as LA performs only a 31-bit addition. */
2629 legitimate_la_operand_p (rtx op)
2631 struct s390_address addr;
2632 if (!s390_decompose_address (op, &addr))
2635 return (TARGET_64BIT || addr.pointer);
2638 /* Return true if it is valid *and* preferable to use LA to
2639 compute the sum of OP1 and OP2. */
2642 preferred_la_operand_p (rtx op1, rtx op2)
2644 struct s390_address addr;
2646 if (op2 != const0_rtx)
2647 op1 = gen_rtx_PLUS (Pmode, op1, op2);
2649 if (!s390_decompose_address (op1, &addr))
2651 if (addr.base && !REG_OK_FOR_BASE_STRICT_P (addr.base))
2653 if (addr.indx && !REG_OK_FOR_INDEX_STRICT_P (addr.indx))
2656 if (!TARGET_64BIT && !addr.pointer)
2662 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
2663 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
2669 /* Emit a forced load-address operation to load SRC into DST.
2670 This will use the LOAD ADDRESS instruction even in situations
2671 where legitimate_la_operand_p (SRC) returns false. */
2674 s390_load_address (rtx dst, rtx src)
2677 emit_move_insn (dst, src);
2679 emit_insn (gen_force_la_31 (dst, src));
2682 /* Return a legitimate reference for ORIG (an address) using the
2683 register REG. If REG is 0, a new pseudo is generated.
2685 There are two types of references that must be handled:
2687 1. Global data references must load the address from the GOT, via
2688 the PIC reg. An insn is emitted to do this load, and the reg is
2691 2. Static data references, constant pool addresses, and code labels
2692 compute the address as an offset from the GOT, whose base is in
2693 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
2694 differentiate them from global data objects. The returned
2695 address is the PIC reg + an unspec constant.
2697 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2698 reg also appears in the address. */
2701 legitimize_pic_address (rtx orig, rtx reg)
2707 if (GET_CODE (addr) == LABEL_REF
2708 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
2710 /* This is a local symbol. */
2711 if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
2713 /* Access local symbols PC-relative via LARL.
2714 This is the same as in the non-PIC case, so it is
2715 handled automatically ... */
2719 /* Access local symbols relative to the GOT. */
2721 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2723 if (reload_in_progress || reload_completed)
2724 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2726 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
2727 addr = gen_rtx_CONST (Pmode, addr);
2728 addr = force_const_mem (Pmode, addr);
2729 emit_move_insn (temp, addr);
2731 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2734 s390_load_address (reg, new);
2739 else if (GET_CODE (addr) == SYMBOL_REF)
2742 reg = gen_reg_rtx (Pmode);
2746 /* Assume GOT offset < 4k. This is handled the same way
2747 in both 31- and 64-bit code (@GOT). */
2749 if (reload_in_progress || reload_completed)
2750 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2752 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2753 new = gen_rtx_CONST (Pmode, new);
2754 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2755 new = gen_const_mem (Pmode, new);
2756 emit_move_insn (reg, new);
2759 else if (TARGET_CPU_ZARCH)
2761 /* If the GOT offset might be >= 4k, we determine the position
2762 of the GOT entry via a PC-relative LARL (@GOTENT). */
2764 rtx temp = gen_reg_rtx (Pmode);
2766 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
2767 new = gen_rtx_CONST (Pmode, new);
2768 emit_move_insn (temp, new);
2770 new = gen_const_mem (Pmode, temp);
2771 emit_move_insn (reg, new);
2776 /* If the GOT offset might be >= 4k, we have to load it
2777 from the literal pool (@GOT). */
2779 rtx temp = gen_reg_rtx (Pmode);
2781 if (reload_in_progress || reload_completed)
2782 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2784 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
2785 addr = gen_rtx_CONST (Pmode, addr);
2786 addr = force_const_mem (Pmode, addr);
2787 emit_move_insn (temp, addr);
2789 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2790 new = gen_const_mem (Pmode, new);
2791 emit_move_insn (reg, new);
2797 if (GET_CODE (addr) == CONST)
2799 addr = XEXP (addr, 0);
2800 if (GET_CODE (addr) == UNSPEC)
2802 gcc_assert (XVECLEN (addr, 0) == 1);
2803 switch (XINT (addr, 1))
2805 /* If someone moved a GOT-relative UNSPEC
2806 out of the literal pool, force them back in. */
2809 new = force_const_mem (Pmode, orig);
2812 /* @GOT is OK as is if small. */
2815 new = force_const_mem (Pmode, orig);
2818 /* @GOTENT is OK as is. */
2822 /* @PLT is OK as is on 64-bit, must be converted to
2823 GOT-relative @PLTOFF on 31-bit. */
2825 if (!TARGET_CPU_ZARCH)
2827 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2829 if (reload_in_progress || reload_completed)
2830 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2832 addr = XVECEXP (addr, 0, 0);
2833 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
2835 addr = gen_rtx_CONST (Pmode, addr);
2836 addr = force_const_mem (Pmode, addr);
2837 emit_move_insn (temp, addr);
2839 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2842 s390_load_address (reg, new);
2848 /* Everything else cannot happen. */
2854 gcc_assert (GET_CODE (addr) == PLUS);
2856 if (GET_CODE (addr) == PLUS)
2858 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
2859 /* Check first to see if this is a constant offset
2860 from a local symbol reference. */
2861 if ((GET_CODE (op0) == LABEL_REF
2862 || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
2863 && GET_CODE (op1) == CONST_INT)
2865 if (TARGET_CPU_ZARCH && larl_operand (op0, VOIDmode))
2867 if (INTVAL (op1) & 1)
2869 /* LARL can't handle odd offsets, so emit a
2870 pair of LARL and LA. */
2871 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2873 if (!DISP_IN_RANGE (INTVAL (op1)))
2875 int even = INTVAL (op1) - 1;
2876 op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even));
2877 op0 = gen_rtx_CONST (Pmode, op0);
2881 emit_move_insn (temp, op0);
2882 new = gen_rtx_PLUS (Pmode, temp, op1);
2886 s390_load_address (reg, new);
2892 /* If the offset is even, we can just use LARL.
2893 This will happen automatically. */
2898 /* Access local symbols relative to the GOT. */
2900 rtx temp = reg? reg : gen_reg_rtx (Pmode);
2902 if (reload_in_progress || reload_completed)
2903 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
2905 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
2907 addr = gen_rtx_PLUS (Pmode, addr, op1);
2908 addr = gen_rtx_CONST (Pmode, addr);
2909 addr = force_const_mem (Pmode, addr);
2910 emit_move_insn (temp, addr);
2912 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
2915 s390_load_address (reg, new);
2921 /* Now, check whether it is a GOT relative symbol plus offset
2922 that was pulled out of the literal pool. Force it back in. */
2924 else if (GET_CODE (op0) == UNSPEC
2925 && GET_CODE (op1) == CONST_INT
2926 && XINT (op0, 1) == UNSPEC_GOTOFF)
2928 gcc_assert (XVECLEN (op0, 0) == 1);
2930 new = force_const_mem (Pmode, orig);
2933 /* Otherwise, compute the sum. */
2936 base = legitimize_pic_address (XEXP (addr, 0), reg);
2937 new = legitimize_pic_address (XEXP (addr, 1),
2938 base == reg ? NULL_RTX : reg);
2939 if (GET_CODE (new) == CONST_INT)
2940 new = plus_constant (base, INTVAL (new));
2943 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
2945 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
2946 new = XEXP (new, 1);
2948 new = gen_rtx_PLUS (Pmode, base, new);
2951 if (GET_CODE (new) == CONST)
2952 new = XEXP (new, 0);
2953 new = force_operand (new, 0);
2960 /* Load the thread pointer into a register. */
2963 s390_get_thread_pointer (void)
2965 rtx tp = gen_reg_rtx (Pmode);
2967 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
2968 mark_reg_pointer (tp, BITS_PER_WORD);
2973 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
2974 in s390_tls_symbol which always refers to __tls_get_offset.
2975 The returned offset is written to RESULT_REG and an USE rtx is
2976 generated for TLS_CALL. */
2978 static GTY(()) rtx s390_tls_symbol;
2981 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
2985 gcc_assert (flag_pic);
2987 if (!s390_tls_symbol)
2988 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
2990 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
2991 gen_rtx_REG (Pmode, RETURN_REGNUM));
2993 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
2994 CONST_OR_PURE_CALL_P (insn) = 1;
2997 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2998 this (thread-local) address. REG may be used as temporary. */
3001 legitimize_tls_address (rtx addr, rtx reg)
3003 rtx new, tls_call, temp, base, r2, insn;
3005 if (GET_CODE (addr) == SYMBOL_REF)
3006 switch (tls_symbolic_operand (addr))
3008 case TLS_MODEL_GLOBAL_DYNAMIC:
3010 r2 = gen_rtx_REG (Pmode, 2);
3011 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3012 new = gen_rtx_CONST (Pmode, tls_call);
3013 new = force_const_mem (Pmode, new);
3014 emit_move_insn (r2, new);
3015 s390_emit_tls_call_insn (r2, tls_call);
3016 insn = get_insns ();
3019 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3020 temp = gen_reg_rtx (Pmode);
3021 emit_libcall_block (insn, temp, r2, new);
3023 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3026 s390_load_address (reg, new);
3031 case TLS_MODEL_LOCAL_DYNAMIC:
3033 r2 = gen_rtx_REG (Pmode, 2);
3034 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3035 new = gen_rtx_CONST (Pmode, tls_call);
3036 new = force_const_mem (Pmode, new);
3037 emit_move_insn (r2, new);
3038 s390_emit_tls_call_insn (r2, tls_call);
3039 insn = get_insns ();
3042 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3043 temp = gen_reg_rtx (Pmode);
3044 emit_libcall_block (insn, temp, r2, new);
3046 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3047 base = gen_reg_rtx (Pmode);
3048 s390_load_address (base, new);
3050 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3051 new = gen_rtx_CONST (Pmode, new);
3052 new = force_const_mem (Pmode, new);
3053 temp = gen_reg_rtx (Pmode);
3054 emit_move_insn (temp, new);
3056 new = gen_rtx_PLUS (Pmode, base, temp);
3059 s390_load_address (reg, new);
3064 case TLS_MODEL_INITIAL_EXEC:
3067 /* Assume GOT offset < 4k. This is handled the same way
3068 in both 31- and 64-bit code. */
3070 if (reload_in_progress || reload_completed)
3071 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3073 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3074 new = gen_rtx_CONST (Pmode, new);
3075 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
3076 new = gen_const_mem (Pmode, new);
3077 temp = gen_reg_rtx (Pmode);
3078 emit_move_insn (temp, new);
3080 else if (TARGET_CPU_ZARCH)
3082 /* If the GOT offset might be >= 4k, we determine the position
3083 of the GOT entry via a PC-relative LARL. */
3085 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3086 new = gen_rtx_CONST (Pmode, new);
3087 temp = gen_reg_rtx (Pmode);
3088 emit_move_insn (temp, new);
3090 new = gen_const_mem (Pmode, temp);
3091 temp = gen_reg_rtx (Pmode);
3092 emit_move_insn (temp, new);
3096 /* If the GOT offset might be >= 4k, we have to load it
3097 from the literal pool. */
3099 if (reload_in_progress || reload_completed)
3100 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
3102 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3103 new = gen_rtx_CONST (Pmode, new);
3104 new = force_const_mem (Pmode, new);
3105 temp = gen_reg_rtx (Pmode);
3106 emit_move_insn (temp, new);
3108 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3109 new = gen_const_mem (Pmode, new);
3111 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3112 temp = gen_reg_rtx (Pmode);
3113 emit_insn (gen_rtx_SET (Pmode, temp, new));
3117 /* In position-dependent code, load the absolute address of
3118 the GOT entry from the literal pool. */
3120 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3121 new = gen_rtx_CONST (Pmode, new);
3122 new = force_const_mem (Pmode, new);
3123 temp = gen_reg_rtx (Pmode);
3124 emit_move_insn (temp, new);
3127 new = gen_const_mem (Pmode, new);
3128 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new, addr), UNSPEC_TLS_LOAD);
3129 temp = gen_reg_rtx (Pmode);
3130 emit_insn (gen_rtx_SET (Pmode, temp, new));
3133 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3136 s390_load_address (reg, new);
3141 case TLS_MODEL_LOCAL_EXEC:
3142 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3143 new = gen_rtx_CONST (Pmode, new);
3144 new = force_const_mem (Pmode, new);
3145 temp = gen_reg_rtx (Pmode);
3146 emit_move_insn (temp, new);
3148 new = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3151 s390_load_address (reg, new);
3160 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3162 switch (XINT (XEXP (addr, 0), 1))
3164 case UNSPEC_INDNTPOFF:
3165 gcc_assert (TARGET_CPU_ZARCH);
3174 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3175 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3177 new = XEXP (XEXP (addr, 0), 0);
3178 if (GET_CODE (new) != SYMBOL_REF)
3179 new = gen_rtx_CONST (Pmode, new);
3181 new = legitimize_tls_address (new, reg);
3182 new = plus_constant (new, INTVAL (XEXP (XEXP (addr, 0), 1)));
3183 new = force_operand (new, 0);
3187 gcc_unreachable (); /* for now ... */
3192 /* Emit insns to move operands[1] into operands[0]. */
3195 emit_symbolic_move (rtx *operands)
3197 rtx temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
3199 if (GET_CODE (operands[0]) == MEM)
3200 operands[1] = force_reg (Pmode, operands[1]);
3201 else if (TLS_SYMBOLIC_CONST (operands[1]))
3202 operands[1] = legitimize_tls_address (operands[1], temp);
3204 operands[1] = legitimize_pic_address (operands[1], temp);
3207 /* Try machine-dependent ways of modifying an illegitimate address X
3208 to be legitimate. If we find one, return the new, valid address.
3210 OLDX is the address as it was before break_out_memory_refs was called.
3211 In some cases it is useful to look at this to decide what needs to be done.
3213 MODE is the mode of the operand pointed to by X.
3215 When -fpic is used, special handling is needed for symbolic references.
3216 See comments by legitimize_pic_address for details. */
3219 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3220 enum machine_mode mode ATTRIBUTE_UNUSED)
3222 rtx constant_term = const0_rtx;
3224 if (TLS_SYMBOLIC_CONST (x))
3226 x = legitimize_tls_address (x, 0);
3228 if (legitimate_address_p (mode, x, FALSE))
3233 if (SYMBOLIC_CONST (x)
3234 || (GET_CODE (x) == PLUS
3235 && (SYMBOLIC_CONST (XEXP (x, 0))
3236 || SYMBOLIC_CONST (XEXP (x, 1)))))
3237 x = legitimize_pic_address (x, 0);
3239 if (legitimate_address_p (mode, x, FALSE))
3243 x = eliminate_constant_term (x, &constant_term);
3245 /* Optimize loading of large displacements by splitting them
3246 into the multiple of 4K and the rest; this allows the
3247 former to be CSE'd if possible.
3249 Don't do this if the displacement is added to a register
3250 pointing into the stack frame, as the offsets will
3251 change later anyway. */
3253 if (GET_CODE (constant_term) == CONST_INT
3254 && !TARGET_LONG_DISPLACEMENT
3255 && !DISP_IN_RANGE (INTVAL (constant_term))
3256 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3258 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3259 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3261 rtx temp = gen_reg_rtx (Pmode);
3262 rtx val = force_operand (GEN_INT (upper), temp);
3264 emit_move_insn (temp, val);
3266 x = gen_rtx_PLUS (Pmode, x, temp);
3267 constant_term = GEN_INT (lower);
3270 if (GET_CODE (x) == PLUS)
3272 if (GET_CODE (XEXP (x, 0)) == REG)
3274 rtx temp = gen_reg_rtx (Pmode);
3275 rtx val = force_operand (XEXP (x, 1), temp);
3277 emit_move_insn (temp, val);
3279 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3282 else if (GET_CODE (XEXP (x, 1)) == REG)
3284 rtx temp = gen_reg_rtx (Pmode);
3285 rtx val = force_operand (XEXP (x, 0), temp);
3287 emit_move_insn (temp, val);
3289 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
3293 if (constant_term != const0_rtx)
3294 x = gen_rtx_PLUS (Pmode, x, constant_term);
3299 /* Try a machine-dependent way of reloading an illegitimate address AD
3300 operand. If we find one, push the reload and and return the new address.
3302 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3303 and TYPE is the reload type of the current reload. */
3306 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
3307 int opnum, int type)
3309 if (!optimize || TARGET_LONG_DISPLACEMENT)
3312 if (GET_CODE (ad) == PLUS)
3314 rtx tem = simplify_binary_operation (PLUS, Pmode,
3315 XEXP (ad, 0), XEXP (ad, 1));
3320 if (GET_CODE (ad) == PLUS
3321 && GET_CODE (XEXP (ad, 0)) == REG
3322 && GET_CODE (XEXP (ad, 1)) == CONST_INT
3323 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
3325 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
3326 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
3329 cst = GEN_INT (upper);
3330 if (!legitimate_reload_constant_p (cst))
3331 cst = force_const_mem (Pmode, cst);
3333 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
3334 new = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
3336 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
3337 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3338 opnum, (enum reload_type) type);
3345 /* Emit code to move LEN bytes from DST to SRC. */
3348 s390_expand_movmem (rtx dst, rtx src, rtx len)
3350 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3352 if (INTVAL (len) > 0)
3353 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
3356 else if (TARGET_MVCLE)
3358 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
3363 rtx dst_addr, src_addr, count, blocks, temp;
3364 rtx loop_start_label = gen_label_rtx ();
3365 rtx loop_end_label = gen_label_rtx ();
3366 rtx end_label = gen_label_rtx ();
3367 enum machine_mode mode;
3369 mode = GET_MODE (len);
3370 if (mode == VOIDmode)
3373 dst_addr = gen_reg_rtx (Pmode);
3374 src_addr = gen_reg_rtx (Pmode);
3375 count = gen_reg_rtx (mode);
3376 blocks = gen_reg_rtx (mode);
3378 convert_move (count, len, 1);
3379 emit_cmp_and_jump_insns (count, const0_rtx,
3380 EQ, NULL_RTX, mode, 1, end_label);
3382 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3383 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
3384 dst = change_address (dst, VOIDmode, dst_addr);
3385 src = change_address (src, VOIDmode, src_addr);
3387 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3389 emit_move_insn (count, temp);
3391 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3393 emit_move_insn (blocks, temp);
3395 emit_cmp_and_jump_insns (blocks, const0_rtx,
3396 EQ, NULL_RTX, mode, 1, loop_end_label);
3398 emit_label (loop_start_label);
3400 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
3401 s390_load_address (dst_addr,
3402 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3403 s390_load_address (src_addr,
3404 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
3406 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3408 emit_move_insn (blocks, temp);
3410 emit_cmp_and_jump_insns (blocks, const0_rtx,
3411 EQ, NULL_RTX, mode, 1, loop_end_label);
3413 emit_jump (loop_start_label);
3414 emit_label (loop_end_label);
3416 emit_insn (gen_movmem_short (dst, src,
3417 convert_to_mode (Pmode, count, 1)));
3418 emit_label (end_label);
3422 /* Emit code to set LEN bytes at DST to VAL.
3423 Make use of clrmem if VAL is zero. */
3426 s390_expand_setmem (rtx dst, rtx len, rtx val)
3428 gcc_assert (GET_CODE (len) != CONST_INT || INTVAL (len) > 0);
3429 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
3431 if (GET_CODE (len) == CONST_INT && INTVAL (len) <= 257)
3433 if (val == const0_rtx && INTVAL (len) <= 256)
3434 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
3437 /* Initialize memory by storing the first byte. */
3438 emit_move_insn (adjust_address (dst, QImode, 0), val);
3440 if (INTVAL (len) > 1)
3442 /* Initiate 1 byte overlap move.
3443 The first byte of DST is propagated through DSTP1.
3444 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3445 DST is set to size 1 so the rest of the memory location
3446 does not count as source operand. */
3447 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
3448 set_mem_size (dst, const1_rtx);
3450 emit_insn (gen_movmem_short (dstp1, dst,
3451 GEN_INT (INTVAL (len) - 2)));
3456 else if (TARGET_MVCLE)
3458 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
3459 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
3464 rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
3465 rtx loop_start_label = gen_label_rtx ();
3466 rtx loop_end_label = gen_label_rtx ();
3467 rtx end_label = gen_label_rtx ();
3468 enum machine_mode mode;
3470 mode = GET_MODE (len);
3471 if (mode == VOIDmode)
3474 dst_addr = gen_reg_rtx (Pmode);
3475 src_addr = gen_reg_rtx (Pmode);
3476 count = gen_reg_rtx (mode);
3477 blocks = gen_reg_rtx (mode);
3479 convert_move (count, len, 1);
3480 emit_cmp_and_jump_insns (count, const0_rtx,
3481 EQ, NULL_RTX, mode, 1, end_label);
3483 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
3484 dst = change_address (dst, VOIDmode, dst_addr);
3486 if (val == const0_rtx)
3487 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3490 dstp1 = adjust_address (dst, VOIDmode, 1);
3491 set_mem_size (dst, const1_rtx);
3493 /* Initialize memory by storing the first byte. */
3494 emit_move_insn (adjust_address (dst, QImode, 0), val);
3496 /* If count is 1 we are done. */
3497 emit_cmp_and_jump_insns (count, const1_rtx,
3498 EQ, NULL_RTX, mode, 1, end_label);
3500 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1, 0);
3503 emit_move_insn (count, temp);
3505 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3507 emit_move_insn (blocks, temp);
3509 emit_cmp_and_jump_insns (blocks, const0_rtx,
3510 EQ, NULL_RTX, mode, 1, loop_end_label);
3512 emit_label (loop_start_label);
3514 if (val == const0_rtx)
3515 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
3517 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
3518 s390_load_address (dst_addr,
3519 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
3521 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3523 emit_move_insn (blocks, temp);
3525 emit_cmp_and_jump_insns (blocks, const0_rtx,
3526 EQ, NULL_RTX, mode, 1, loop_end_label);
3528 emit_jump (loop_start_label);
3529 emit_label (loop_end_label);
3531 if (val == const0_rtx)
3532 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
3534 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
3535 emit_label (end_label);
3539 /* Emit code to compare LEN bytes at OP0 with those at OP1,
3540 and return the result in TARGET. */
3543 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
3545 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
3548 /* As the result of CMPINT is inverted compared to what we need,
3549 we have to swap the operands. */
3550 tmp = op0; op0 = op1; op1 = tmp;
3552 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
3554 if (INTVAL (len) > 0)
3556 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
3557 emit_insn (gen_cmpint (target, ccreg));
3560 emit_move_insn (target, const0_rtx);
3562 else if (TARGET_MVCLE)
3564 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
3565 emit_insn (gen_cmpint (target, ccreg));
3569 rtx addr0, addr1, count, blocks, temp;
3570 rtx loop_start_label = gen_label_rtx ();
3571 rtx loop_end_label = gen_label_rtx ();
3572 rtx end_label = gen_label_rtx ();
3573 enum machine_mode mode;
3575 mode = GET_MODE (len);
3576 if (mode == VOIDmode)
3579 addr0 = gen_reg_rtx (Pmode);
3580 addr1 = gen_reg_rtx (Pmode);
3581 count = gen_reg_rtx (mode);
3582 blocks = gen_reg_rtx (mode);
3584 convert_move (count, len, 1);
3585 emit_cmp_and_jump_insns (count, const0_rtx,
3586 EQ, NULL_RTX, mode, 1, end_label);
3588 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
3589 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
3590 op0 = change_address (op0, VOIDmode, addr0);
3591 op1 = change_address (op1, VOIDmode, addr1);
3593 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
3595 emit_move_insn (count, temp);
3597 temp = expand_binop (mode, ashr_optab, count, GEN_INT (8), blocks, 1, 0);
3599 emit_move_insn (blocks, temp);
3601 emit_cmp_and_jump_insns (blocks, const0_rtx,
3602 EQ, NULL_RTX, mode, 1, loop_end_label);
3604 emit_label (loop_start_label);
3606 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
3607 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
3608 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
3609 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
3610 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
3611 emit_jump_insn (temp);
3613 s390_load_address (addr0,
3614 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
3615 s390_load_address (addr1,
3616 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
3618 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
3620 emit_move_insn (blocks, temp);
3622 emit_cmp_and_jump_insns (blocks, const0_rtx,
3623 EQ, NULL_RTX, mode, 1, loop_end_label);
3625 emit_jump (loop_start_label);
3626 emit_label (loop_end_label);
3628 emit_insn (gen_cmpmem_short (op0, op1,
3629 convert_to_mode (Pmode, count, 1)));
3630 emit_label (end_label);
3632 emit_insn (gen_cmpint (target, ccreg));
3637 /* Expand conditional increment or decrement using alc/slb instructions.
3638 Should generate code setting DST to either SRC or SRC + INCREMENT,
3639 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
3640 Returns true if successful, false otherwise.
3642 That makes it possible to implement some if-constructs without jumps e.g.:
3643 (borrow = CC0 | CC1 and carry = CC2 | CC3)
3644 unsigned int a, b, c;
3645 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
3646 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
3647 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
3648 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
3650 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
3651 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
3652 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
3653 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
3654 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
3657 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
3658 rtx dst, rtx src, rtx increment)
3660 enum machine_mode cmp_mode;
3661 enum machine_mode cc_mode;
3667 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
3668 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
3670 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
3671 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
3676 /* Try ADD LOGICAL WITH CARRY. */
3677 if (increment == const1_rtx)
3679 /* Determine CC mode to use. */
3680 if (cmp_code == EQ || cmp_code == NE)
3682 if (cmp_op1 != const0_rtx)
3684 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3685 NULL_RTX, 0, OPTAB_WIDEN);
3686 cmp_op1 = const0_rtx;
3689 cmp_code = cmp_code == EQ ? LEU : GTU;
3692 if (cmp_code == LTU || cmp_code == LEU)
3697 cmp_code = swap_condition (cmp_code);
3714 /* Emit comparison instruction pattern. */
3715 if (!register_operand (cmp_op0, cmp_mode))
3716 cmp_op0 = force_reg (cmp_mode, cmp_op0);
3718 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3719 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3720 /* We use insn_invalid_p here to add clobbers if required. */
3721 ret = insn_invalid_p (emit_insn (insn));
3724 /* Emit ALC instruction pattern. */
3725 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3726 gen_rtx_REG (cc_mode, CC_REGNUM),
3729 if (src != const0_rtx)
3731 if (!register_operand (src, GET_MODE (dst)))
3732 src = force_reg (GET_MODE (dst), src);
3734 src = gen_rtx_PLUS (GET_MODE (dst), src, const0_rtx);
3735 op_res = gen_rtx_PLUS (GET_MODE (dst), src, op_res);
3738 p = rtvec_alloc (2);
3740 gen_rtx_SET (VOIDmode, dst, op_res);
3742 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3743 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3748 /* Try SUBTRACT LOGICAL WITH BORROW. */
3749 if (increment == constm1_rtx)
3751 /* Determine CC mode to use. */
3752 if (cmp_code == EQ || cmp_code == NE)
3754 if (cmp_op1 != const0_rtx)
3756 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3757 NULL_RTX, 0, OPTAB_WIDEN);
3758 cmp_op1 = const0_rtx;
3761 cmp_code = cmp_code == EQ ? LEU : GTU;
3764 if (cmp_code == GTU || cmp_code == GEU)
3769 cmp_code = swap_condition (cmp_code);
3786 /* Emit comparison instruction pattern. */
3787 if (!register_operand (cmp_op0, cmp_mode))
3788 cmp_op0 = force_reg (cmp_mode, cmp_op0);
3790 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
3791 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
3792 /* We use insn_invalid_p here to add clobbers if required. */
3793 ret = insn_invalid_p (emit_insn (insn));
3796 /* Emit SLB instruction pattern. */
3797 if (!register_operand (src, GET_MODE (dst)))
3798 src = force_reg (GET_MODE (dst), src);
3800 op_res = gen_rtx_MINUS (GET_MODE (dst),
3801 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
3802 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
3803 gen_rtx_REG (cc_mode, CC_REGNUM),
3805 p = rtvec_alloc (2);
3807 gen_rtx_SET (VOIDmode, dst, op_res);
3809 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
3810 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
3818 /* Expand code for the insv template. Return true if successful, false else. */
3821 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
3823 int bitsize = INTVAL (op1);
3824 int bitpos = INTVAL (op2);
3826 /* We need byte alignement. */
3827 if (bitsize % BITS_PER_UNIT)
3831 && memory_operand (dest, VOIDmode)
3832 && (register_operand (src, word_mode)
3833 || const_int_operand (src, VOIDmode)))
3835 /* Emit standard pattern if possible. */
3836 enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT);
3837 if (GET_MODE_BITSIZE (mode) == bitsize)
3838 emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src));
3840 /* (set (ze (mem)) (const_int)). */
3841 else if (const_int_operand (src, VOIDmode))
3843 int size = bitsize / BITS_PER_UNIT;
3844 rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode,
3845 GET_MODE_SIZE (word_mode) - size);
3847 dest = adjust_address (dest, BLKmode, 0);
3848 set_mem_size (dest, GEN_INT (size));
3849 s390_expand_movmem (dest, src_mem, GEN_INT (size));
3852 /* (set (ze (mem)) (reg)). */
3853 else if (register_operand (src, word_mode))
3855 if (bitsize <= GET_MODE_BITSIZE (SImode))
3856 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
3860 /* Emit st,stcmh sequence. */
3861 int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode);
3862 int size = stcmh_width / BITS_PER_UNIT;
3864 emit_move_insn (adjust_address (dest, SImode, size),
3865 gen_lowpart (SImode, src));
3866 set_mem_size (dest, GEN_INT (size));
3867 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT
3868 (stcmh_width), const0_rtx),
3869 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT
3870 (GET_MODE_BITSIZE (SImode))));
3879 /* (set (ze (reg)) (const_int)). */
3881 && register_operand (dest, word_mode)
3882 && (bitpos % 16) == 0
3883 && (bitsize % 16) == 0
3884 && const_int_operand (src, VOIDmode))
3886 HOST_WIDE_INT val = INTVAL (src);
3887 int regpos = bitpos + bitsize;
3889 while (regpos > bitpos)
3891 enum machine_mode putmode;
3894 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
3899 putsize = GET_MODE_BITSIZE (putmode);
3901 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
3904 gen_int_mode (val, putmode));
3907 gcc_assert (regpos == bitpos);
3914 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3915 We need to emit DTP-relative relocations. */
3917 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
3920 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
3925 fputs ("\t.long\t", file);
3928 fputs ("\t.quad\t", file);
3933 output_addr_const (file, x);
3934 fputs ("@DTPOFF", file);
3937 /* In the name of slightly smaller debug output, and to cater to
3938 general assembler lossage, recognize various UNSPEC sequences
3939 and turn them back into a direct symbol reference. */
3942 s390_delegitimize_address (rtx orig_x)
3946 if (GET_CODE (x) != MEM)
3950 if (GET_CODE (x) == PLUS
3951 && GET_CODE (XEXP (x, 1)) == CONST
3952 && GET_CODE (XEXP (x, 0)) == REG
3953 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
3955 y = XEXP (XEXP (x, 1), 0);
3956 if (GET_CODE (y) == UNSPEC
3957 && XINT (y, 1) == UNSPEC_GOT)
3958 return XVECEXP (y, 0, 0);
3962 if (GET_CODE (x) == CONST)
3965 if (GET_CODE (y) == UNSPEC
3966 && XINT (y, 1) == UNSPEC_GOTENT)
3967 return XVECEXP (y, 0, 0);
3974 /* Output operand OP to stdio stream FILE.
3975 OP is an address (register + offset) which is not used to address data;
3976 instead the rightmost bits are interpreted as the value. */
3979 print_shift_count_operand (FILE *file, rtx op)
3981 HOST_WIDE_INT offset = 0;
3983 /* Shift count operands are always truncated to the 6 least significant bits and
3984 the setmem padding byte to the least 8 significant bits. Hence we can drop
3986 if (GET_CODE (op) == AND && GET_CODE (XEXP (op, 1)) == CONST_INT)
3988 if ((INTVAL (XEXP (op, 1)) & 63) != 63)
3994 /* We can have an integer constant, an address register,
3995 or a sum of the two. */
3996 if (GET_CODE (op) == CONST_INT)
3998 offset = INTVAL (op);
4001 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
4003 offset = INTVAL (XEXP (op, 1));
4006 while (op && GET_CODE (op) == SUBREG)
4007 op = SUBREG_REG (op);
4012 gcc_assert (GET_CODE (op) == REG);
4013 gcc_assert (REGNO (op) < FIRST_PSEUDO_REGISTER);
4014 gcc_assert (REGNO_REG_CLASS (REGNO (op)) == ADDR_REGS);
4017 /* Offsets are constricted to twelve bits. */
4018 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
4020 fprintf (file, "(%s)", reg_names[REGNO (op)]);
4023 /* See 'get_some_local_dynamic_name'. */
4026 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
4030 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4032 x = get_pool_constant (x);
4033 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
4036 if (GET_CODE (x) == SYMBOL_REF
4037 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
4039 cfun->machine->some_ld_name = XSTR (x, 0);
4046 /* Locate some local-dynamic symbol still in use by this function
4047 so that we can print its name in local-dynamic base patterns. */
4050 get_some_local_dynamic_name (void)
4054 if (cfun->machine->some_ld_name)
4055 return cfun->machine->some_ld_name;
4057 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
4059 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
4060 return cfun->machine->some_ld_name;
4065 /* Output machine-dependent UNSPECs occurring in address constant X
4066 in assembler syntax to stdio stream FILE. Returns true if the
4067 constant X could be recognized, false otherwise. */
4070 s390_output_addr_const_extra (FILE *file, rtx x)
4072 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
4073 switch (XINT (x, 1))
4076 output_addr_const (file, XVECEXP (x, 0, 0));
4077 fprintf (file, "@GOTENT");
4080 output_addr_const (file, XVECEXP (x, 0, 0));
4081 fprintf (file, "@GOT");
4084 output_addr_const (file, XVECEXP (x, 0, 0));
4085 fprintf (file, "@GOTOFF");
4088 output_addr_const (file, XVECEXP (x, 0, 0));
4089 fprintf (file, "@PLT");
4092 output_addr_const (file, XVECEXP (x, 0, 0));
4093 fprintf (file, "@PLTOFF");
4096 output_addr_const (file, XVECEXP (x, 0, 0));
4097 fprintf (file, "@TLSGD");
4100 assemble_name (file, get_some_local_dynamic_name ());
4101 fprintf (file, "@TLSLDM");
4104 output_addr_const (file, XVECEXP (x, 0, 0));
4105 fprintf (file, "@DTPOFF");
4108 output_addr_const (file, XVECEXP (x, 0, 0));
4109 fprintf (file, "@NTPOFF");
4111 case UNSPEC_GOTNTPOFF:
4112 output_addr_const (file, XVECEXP (x, 0, 0));
4113 fprintf (file, "@GOTNTPOFF");
4115 case UNSPEC_INDNTPOFF:
4116 output_addr_const (file, XVECEXP (x, 0, 0));
4117 fprintf (file, "@INDNTPOFF");
4124 /* Output address operand ADDR in assembler syntax to
4125 stdio stream FILE. */
4128 print_operand_address (FILE *file, rtx addr)
4130 struct s390_address ad;
4132 if (!s390_decompose_address (addr, &ad)
4133 || (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
4134 || (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx)))
4135 output_operand_lossage ("cannot decompose address");
4138 output_addr_const (file, ad.disp);
4140 fprintf (file, "0");
4142 if (ad.base && ad.indx)
4143 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
4144 reg_names[REGNO (ad.base)]);
4146 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4149 /* Output operand X in assembler syntax to stdio stream FILE.
4150 CODE specified the format flag. The following format flags
4153 'C': print opcode suffix for branch condition.
4154 'D': print opcode suffix for inverse branch condition.
4155 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4156 'G': print the size of the operand in bytes.
4157 'O': print only the displacement of a memory reference.
4158 'R': print only the base register of a memory reference.
4159 'S': print S-type memory reference (base+displacement).
4160 'N': print the second word of a DImode operand.
4161 'M': print the second word of a TImode operand.
4162 'Y': print shift count operand.
4164 'b': print integer X as if it's an unsigned byte.
4165 'x': print integer X as if it's an unsigned halfword.
4166 'h': print integer X as if it's a signed halfword.
4167 'i': print the first nonzero HImode part of X.
4168 'j': print the first HImode part unequal to -1 of X.
4169 'k': print the first nonzero SImode part of X.
4170 'm': print the first SImode part unequal to -1 of X.
4171 'o': print integer X as if it's an unsigned 32bit word. */
4174 print_operand (FILE *file, rtx x, int code)
4179 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
4183 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
4187 if (GET_CODE (x) == SYMBOL_REF)
4189 fprintf (file, "%s", ":tls_load:");
4190 output_addr_const (file, x);
4192 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
4194 fprintf (file, "%s", ":tls_gdcall:");
4195 output_addr_const (file, XVECEXP (x, 0, 0));
4197 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
4199 fprintf (file, "%s", ":tls_ldcall:");
4200 assemble_name (file, get_some_local_dynamic_name ());
4207 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
4212 struct s390_address ad;
4215 gcc_assert (GET_CODE (x) == MEM);
4216 ret = s390_decompose_address (XEXP (x, 0), &ad);
4218 gcc_assert (!ad.base || REG_OK_FOR_BASE_STRICT_P (ad.base));
4219 gcc_assert (!ad.indx);
4222 output_addr_const (file, ad.disp);
4224 fprintf (file, "0");
4230 struct s390_address ad;
4233 gcc_assert (GET_CODE (x) == MEM);
4234 ret = s390_decompose_address (XEXP (x, 0), &ad);
4236 gcc_assert (!ad.base || REG_OK_FOR_BASE_STRICT_P (ad.base));
4237 gcc_assert (!ad.indx);
4240 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
4242 fprintf (file, "0");
4248 struct s390_address ad;
4251 gcc_assert (GET_CODE (x) == MEM);
4252 ret = s390_decompose_address (XEXP (x, 0), &ad);
4254 gcc_assert (!ad.base || REG_OK_FOR_BASE_STRICT_P (ad.base));
4255 gcc_assert (!ad.indx);
4258 output_addr_const (file, ad.disp);
4260 fprintf (file, "0");
4263 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
4268 if (GET_CODE (x) == REG)
4269 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4270 else if (GET_CODE (x) == MEM)
4271 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4));
4277 if (GET_CODE (x) == REG)
4278 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
4279 else if (GET_CODE (x) == MEM)
4280 x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8));
4286 print_shift_count_operand (file, x);
4290 switch (GET_CODE (x))
4293 fprintf (file, "%s", reg_names[REGNO (x)]);
4297 output_address (XEXP (x, 0));
4304 output_addr_const (file, x);
4309 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff);
4310 else if (code == 'x')
4311 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
4312 else if (code == 'h')
4313 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
4314 else if (code == 'i')
4315 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4316 s390_extract_part (x, HImode, 0));
4317 else if (code == 'j')
4318 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4319 s390_extract_part (x, HImode, -1));
4320 else if (code == 'k')
4321 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4322 s390_extract_part (x, SImode, 0));
4323 else if (code == 'm')
4324 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
4325 s390_extract_part (x, SImode, -1));
4326 else if (code == 'o')
4327 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff);
4329 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
4333 gcc_assert (GET_MODE (x) == VOIDmode);
4335 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
4336 else if (code == 'x')
4337 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
4338 else if (code == 'h')
4339 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
4345 fatal_insn ("UNKNOWN in print_operand !?", x);
4350 /* Target hook for assembling integer objects. We need to define it
4351 here to work a round a bug in some versions of GAS, which couldn't
4352 handle values smaller than INT_MIN when printed in decimal. */
4355 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
4357 if (size == 8 && aligned_p
4358 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
4360 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
4364 return default_assemble_integer (x, size, aligned_p);
4367 /* Returns true if register REGNO is used for forming
4368 a memory address in expression X. */
4371 reg_used_in_mem_p (int regno, rtx x)
4373 enum rtx_code code = GET_CODE (x);
4379 if (refers_to_regno_p (regno, regno+1,
4383 else if (code == SET
4384 && GET_CODE (SET_DEST (x)) == PC)
4386 if (refers_to_regno_p (regno, regno+1,
4391 fmt = GET_RTX_FORMAT (code);
4392 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4395 && reg_used_in_mem_p (regno, XEXP (x, i)))
4398 else if (fmt[i] == 'E')
4399 for (j = 0; j < XVECLEN (x, i); j++)
4400 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
4406 /* Returns true if expression DEP_RTX sets an address register
4407 used by instruction INSN to address memory. */
4410 addr_generation_dependency_p (rtx dep_rtx, rtx insn)
4414 if (GET_CODE (dep_rtx) == INSN)
4415 dep_rtx = PATTERN (dep_rtx);
4417 if (GET_CODE (dep_rtx) == SET)
4419 target = SET_DEST (dep_rtx);
4420 if (GET_CODE (target) == STRICT_LOW_PART)
4421 target = XEXP (target, 0);
4422 while (GET_CODE (target) == SUBREG)
4423 target = SUBREG_REG (target);
4425 if (GET_CODE (target) == REG)
4427 int regno = REGNO (target);
4429 if (s390_safe_attr_type (insn) == TYPE_LA)
4431 pat = PATTERN (insn);
4432 if (GET_CODE (pat) == PARALLEL)
4434 gcc_assert (XVECLEN (pat, 0) == 2);
4435 pat = XVECEXP (pat, 0, 0);
4437 gcc_assert (GET_CODE (pat) == SET);
4438 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
4440 else if (get_attr_atype (insn) == ATYPE_AGEN)
4441 return reg_used_in_mem_p (regno, PATTERN (insn));
4447 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
4450 s390_agen_dep_p (rtx dep_insn, rtx insn)
4452 rtx dep_rtx = PATTERN (dep_insn);
4455 if (GET_CODE (dep_rtx) == SET
4456 && addr_generation_dependency_p (dep_rtx, insn))
4458 else if (GET_CODE (dep_rtx) == PARALLEL)
4460 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
4462 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
4469 /* A C statement (sans semicolon) to update the integer scheduling priority
4470 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
4471 reduce the priority to execute INSN later. Do not define this macro if
4472 you do not need to adjust the scheduling priorities of insns.
4474 A STD instruction should be scheduled earlier,
4475 in order to use the bypass. */
4478 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
4480 if (! INSN_P (insn))
4483 if (s390_tune != PROCESSOR_2084_Z990
4484 && s390_tune != PROCESSOR_2094_Z9_109)
4487 switch (s390_safe_attr_type (insn))
4491 priority = priority << 3;
4495 priority = priority << 1;
4503 /* The number of instructions that can be issued per cycle. */
4506 s390_issue_rate (void)
4508 if (s390_tune == PROCESSOR_2084_Z990
4509 || s390_tune == PROCESSOR_2094_Z9_109)
4515 s390_first_cycle_multipass_dfa_lookahead (void)
4521 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
4522 Fix up MEMs as required. */
4525 annotate_constant_pool_refs (rtx *x)
4530 gcc_assert (GET_CODE (*x) != SYMBOL_REF
4531 || !CONSTANT_POOL_ADDRESS_P (*x));
4533 /* Literal pool references can only occur inside a MEM ... */
4534 if (GET_CODE (*x) == MEM)
4536 rtx memref = XEXP (*x, 0);
4538 if (GET_CODE (memref) == SYMBOL_REF
4539 && CONSTANT_POOL_ADDRESS_P (memref))
4541 rtx base = cfun->machine->base_reg;
4542 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
4545 *x = replace_equiv_address (*x, addr);
4549 if (GET_CODE (memref) == CONST
4550 && GET_CODE (XEXP (memref, 0)) == PLUS
4551 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
4552 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
4553 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
4555 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
4556 rtx sym = XEXP (XEXP (memref, 0), 0);
4557 rtx base = cfun->machine->base_reg;
4558 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4561 *x = replace_equiv_address (*x, plus_constant (addr, off));
4566 /* ... or a load-address type pattern. */
4567 if (GET_CODE (*x) == SET)
4569 rtx addrref = SET_SRC (*x);
4571 if (GET_CODE (addrref) == SYMBOL_REF
4572 && CONSTANT_POOL_ADDRESS_P (addrref))
4574 rtx base = cfun->machine->base_reg;
4575 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
4578 SET_SRC (*x) = addr;
4582 if (GET_CODE (addrref) == CONST
4583 && GET_CODE (XEXP (addrref, 0)) == PLUS
4584 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
4585 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
4586 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
4588 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
4589 rtx sym = XEXP (XEXP (addrref, 0), 0);
4590 rtx base = cfun->machine->base_reg;
4591 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
4594 SET_SRC (*x) = plus_constant (addr, off);
4599 /* Annotate LTREL_BASE as well. */
4600 if (GET_CODE (*x) == UNSPEC
4601 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
4603 rtx base = cfun->machine->base_reg;
4604 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
4609 fmt = GET_RTX_FORMAT (GET_CODE (*x));
4610 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
4614 annotate_constant_pool_refs (&XEXP (*x, i));
4616 else if (fmt[i] == 'E')
4618 for (j = 0; j < XVECLEN (*x, i); j++)
4619 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
4624 /* Split all branches that exceed the maximum distance.
4625 Returns true if this created a new literal pool entry. */
4628 s390_split_branches (void)
4630 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
4631 int new_literal = 0, ret;
4632 rtx insn, pat, tmp, target;
4635 /* We need correct insn addresses. */
4637 shorten_branches (get_insns ());
4639 /* Find all branches that exceed 64KB, and split them. */
4641 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
4643 if (GET_CODE (insn) != JUMP_INSN)
4646 pat = PATTERN (insn);
4647 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
4648 pat = XVECEXP (pat, 0, 0);
4649 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
4652 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
4654 label = &SET_SRC (pat);
4656 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
4658 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
4659 label = &XEXP (SET_SRC (pat), 1);
4660 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
4661 label = &XEXP (SET_SRC (pat), 2);
4668 if (get_attr_length (insn) <= 4)
4671 /* We are going to use the return register as scratch register,
4672 make sure it will be saved/restored by the prologue/epilogue. */
4673 cfun_frame_layout.save_return_addr_p = 1;
4678 tmp = force_const_mem (Pmode, *label);
4679 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
4680 INSN_ADDRESSES_NEW (tmp, -1);
4681 annotate_constant_pool_refs (&PATTERN (tmp));
4688 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
4689 UNSPEC_LTREL_OFFSET);
4690 target = gen_rtx_CONST (Pmode, target);
4691 target = force_const_mem (Pmode, target);
4692 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
4693 INSN_ADDRESSES_NEW (tmp, -1);
4694 annotate_constant_pool_refs (&PATTERN (tmp));
4696 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
4697 cfun->machine->base_reg),
4699 target = gen_rtx_PLUS (Pmode, temp_reg, target);
4702 ret = validate_change (insn, label, target, 0);
4710 /* Find an annotated literal pool symbol referenced in RTX X,
4711 and store it at REF. Will abort if X contains references to
4712 more than one such pool symbol; multiple references to the same
4713 symbol are allowed, however.
4715 The rtx pointed to by REF must be initialized to NULL_RTX
4716 by the caller before calling this routine. */
4719 find_constant_pool_ref (rtx x, rtx *ref)
4724 /* Ignore LTREL_BASE references. */
4725 if (GET_CODE (x) == UNSPEC
4726 && XINT (x, 1) == UNSPEC_LTREL_BASE)
4728 /* Likewise POOL_ENTRY insns. */
4729 if (GET_CODE (x) == UNSPEC_VOLATILE
4730 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
4733 gcc_assert (GET_CODE (x) != SYMBOL_REF
4734 || !CONSTANT_POOL_ADDRESS_P (x));
4736 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
4738 rtx sym = XVECEXP (x, 0, 0);
4739 gcc_assert (GET_CODE (sym) == SYMBOL_REF
4740 && CONSTANT_POOL_ADDRESS_P (sym));
4742 if (*ref == NULL_RTX)
4745 gcc_assert (*ref == sym);
4750 fmt = GET_RTX_FORMAT (GET_CODE (x));
4751 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4755 find_constant_pool_ref (XEXP (x, i), ref);
4757 else if (fmt[i] == 'E')
4759 for (j = 0; j < XVECLEN (x, i); j++)
4760 find_constant_pool_ref (XVECEXP (x, i, j), ref);
4765 /* Replace every reference to the annotated literal pool
4766 symbol REF in X by its base plus OFFSET. */
4769 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
4774 gcc_assert (*x != ref);
4776 if (GET_CODE (*x) == UNSPEC
4777 && XINT (*x, 1) == UNSPEC_LTREF
4778 && XVECEXP (*x, 0, 0) == ref)
4780 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
4784 if (GET_CODE (*x) == PLUS
4785 && GET_CODE (XEXP (*x, 1)) == CONST_INT
4786 && GET_CODE (XEXP (*x, 0)) == UNSPEC
4787 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
4788 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
4790 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
4791 *x = plus_constant (addr, INTVAL (XEXP (*x, 1)));
4795 fmt = GET_RTX_FORMAT (GET_CODE (*x));
4796 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
4800 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
4802 else if (fmt[i] == 'E')
4804 for (j = 0; j < XVECLEN (*x, i); j++)
4805 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
4810 /* Check whether X contains an UNSPEC_LTREL_BASE.
4811 Return its constant pool symbol if found, NULL_RTX otherwise. */
4814 find_ltrel_base (rtx x)
4819 if (GET_CODE (x) == UNSPEC
4820 && XINT (x, 1) == UNSPEC_LTREL_BASE)
4821 return XVECEXP (x, 0, 0);
4823 fmt = GET_RTX_FORMAT (GET_CODE (x));
4824 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4828 rtx fnd = find_ltrel_base (XEXP (x, i));
4832 else if (fmt[i] == 'E')
4834 for (j = 0; j < XVECLEN (x, i); j++)
4836 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
4846 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
4849 replace_ltrel_base (rtx *x)
4854 if (GET_CODE (*x) == UNSPEC
4855 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
4857 *x = XVECEXP (*x, 0, 1);
4861 fmt = GET_RTX_FORMAT (GET_CODE (*x));
4862 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
4866 replace_ltrel_base (&XEXP (*x, i));
4868 else if (fmt[i] == 'E')
4870 for (j = 0; j < XVECLEN (*x, i); j++)
4871 replace_ltrel_base (&XVECEXP (*x, i, j));
4877 /* We keep a list of constants which we have to add to internal
4878 constant tables in the middle of large functions. */
4880 #define NR_C_MODES 7
4881 enum machine_mode constant_modes[NR_C_MODES] =
4892 struct constant *next;
4897 struct constant_pool
4899 struct constant_pool *next;
4904 struct constant *constants[NR_C_MODES];
4905 struct constant *execute;
4910 /* Allocate new constant_pool structure. */
4912 static struct constant_pool *
4913 s390_alloc_pool (void)
4915 struct constant_pool *pool;
4918 pool = (struct constant_pool *) xmalloc (sizeof *pool);
4920 for (i = 0; i < NR_C_MODES; i++)
4921 pool->constants[i] = NULL;
4923 pool->execute = NULL;
4924 pool->label = gen_label_rtx ();
4925 pool->first_insn = NULL_RTX;
4926 pool->pool_insn = NULL_RTX;
4927 pool->insns = BITMAP_ALLOC (NULL);
4933 /* Create new constant pool covering instructions starting at INSN
4934 and chain it to the end of POOL_LIST. */
4936 static struct constant_pool *
4937 s390_start_pool (struct constant_pool **pool_list, rtx insn)
4939 struct constant_pool *pool, **prev;
4941 pool = s390_alloc_pool ();
4942 pool->first_insn = insn;
4944 for (prev = pool_list; *prev; prev = &(*prev)->next)
4951 /* End range of instructions covered by POOL at INSN and emit
4952 placeholder insn representing the pool. */
4955 s390_end_pool (struct constant_pool *pool, rtx insn)
4957 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
4960 insn = get_last_insn ();
4962 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
4963 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
4966 /* Add INSN to the list of insns covered by POOL. */
4969 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
4971 bitmap_set_bit (pool->insns, INSN_UID (insn));
4974 /* Return pool out of POOL_LIST that covers INSN. */
4976 static struct constant_pool *
4977 s390_find_pool (struct constant_pool *pool_list, rtx insn)
4979 struct constant_pool *pool;
4981 for (pool = pool_list; pool; pool = pool->next)
4982 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
4988 /* Add constant VAL of mode MODE to the constant pool POOL. */
4991 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
4996 for (i = 0; i < NR_C_MODES; i++)
4997 if (constant_modes[i] == mode)
4999 gcc_assert (i != NR_C_MODES);
5001 for (c = pool->constants[i]; c != NULL; c = c->next)
5002 if (rtx_equal_p (val, c->value))
5007 c = (struct constant *) xmalloc (sizeof *c);
5009 c->label = gen_label_rtx ();
5010 c->next = pool->constants[i];
5011 pool->constants[i] = c;
5012 pool->size += GET_MODE_SIZE (mode);
5016 /* Find constant VAL of mode MODE in the constant pool POOL.
5017 Return an RTX describing the distance from the start of
5018 the pool to the location of the new constant. */
5021 s390_find_constant (struct constant_pool *pool, rtx val,
5022 enum machine_mode mode)
5028 for (i = 0; i < NR_C_MODES; i++)
5029 if (constant_modes[i] == mode)
5031 gcc_assert (i != NR_C_MODES);
5033 for (c = pool->constants[i]; c != NULL; c = c->next)
5034 if (rtx_equal_p (val, c->value))
5039 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5040 gen_rtx_LABEL_REF (Pmode, pool->label));
5041 offset = gen_rtx_CONST (Pmode, offset);
5045 /* Check whether INSN is an execute. Return the label_ref to its
5046 execute target template if so, NULL_RTX otherwise. */
5049 s390_execute_label (rtx insn)
5051 if (GET_CODE (insn) == INSN
5052 && GET_CODE (PATTERN (insn)) == PARALLEL
5053 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
5054 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
5055 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
5060 /* Add execute target for INSN to the constant pool POOL. */
5063 s390_add_execute (struct constant_pool *pool, rtx insn)
5067 for (c = pool->execute; c != NULL; c = c->next)
5068 if (INSN_UID (insn) == INSN_UID (c->value))
5073 c = (struct constant *) xmalloc (sizeof *c);
5075 c->label = gen_label_rtx ();
5076 c->next = pool->execute;
5082 /* Find execute target for INSN in the constant pool POOL.
5083 Return an RTX describing the distance from the start of
5084 the pool to the location of the execute target. */
5087 s390_find_execute (struct constant_pool *pool, rtx insn)
5092 for (c = pool->execute; c != NULL; c = c->next)
5093 if (INSN_UID (insn) == INSN_UID (c->value))
5098 offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
5099 gen_rtx_LABEL_REF (Pmode, pool->label));
5100 offset = gen_rtx_CONST (Pmode, offset);
5104 /* For an execute INSN, extract the execute target template. */
5107 s390_execute_target (rtx insn)
5109 rtx pattern = PATTERN (insn);
5110 gcc_assert (s390_execute_label (insn));
5112 if (XVECLEN (pattern, 0) == 2)
5114 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
5118 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
5121 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
5122 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
5124 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
5130 /* Indicate that INSN cannot be duplicated. This is the case for
5131 execute insns that carry a unique label. */
5134 s390_cannot_copy_insn_p (rtx insn)
5136 rtx label = s390_execute_label (insn);
5137 return label && label != const0_rtx;
5140 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5141 do not emit the pool base label. */
5144 s390_dump_pool (struct constant_pool *pool, bool remote_label)
5147 rtx insn = pool->pool_insn;
5150 /* Switch to rodata section. */
5151 if (TARGET_CPU_ZARCH)
5153 insn = emit_insn_after (gen_pool_section_start (), insn);
5154 INSN_ADDRESSES_NEW (insn, -1);
5157 /* Ensure minimum pool alignment. */
5158 if (TARGET_CPU_ZARCH)
5159 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
5161 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
5162 INSN_ADDRESSES_NEW (insn, -1);
5164 /* Emit pool base label. */
5167 insn = emit_label_after (pool->label, insn);
5168 INSN_ADDRESSES_NEW (insn, -1);
5171 /* Dump constants in descending alignment requirement order,
5172 ensuring proper alignment for every constant. */
5173 for (i = 0; i < NR_C_MODES; i++)
5174 for (c = pool->constants[i]; c; c = c->next)
5176 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
5177 rtx value = c->value;
5178 if (GET_CODE (value) == CONST
5179 && GET_CODE (XEXP (value, 0)) == UNSPEC
5180 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
5181 && XVECLEN (XEXP (value, 0), 0) == 1)
5183 value = gen_rtx_MINUS (Pmode, XVECEXP (XEXP (value, 0), 0, 0),
5184 gen_rtx_LABEL_REF (VOIDmode, pool->label));
5185 value = gen_rtx_CONST (VOIDmode, value);
5188 insn = emit_label_after (c->label, insn);
5189 INSN_ADDRESSES_NEW (insn, -1);
5191 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
5192 gen_rtvec (1, value),
5193 UNSPECV_POOL_ENTRY);
5194 insn = emit_insn_after (value, insn);
5195 INSN_ADDRESSES_NEW (insn, -1);
5198 /* Ensure minimum alignment for instructions. */
5199 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
5200 INSN_ADDRESSES_NEW (insn, -1);
5202 /* Output in-pool execute template insns. */
5203 for (c = pool->execute; c; c = c->next)
5205 insn = emit_label_after (c->label, insn);
5206 INSN_ADDRESSES_NEW (insn, -1);
5208 insn = emit_insn_after (s390_execute_target (c->value), insn);
5209 INSN_ADDRESSES_NEW (insn, -1);
5212 /* Switch back to previous section. */
5213 if (TARGET_CPU_ZARCH)
5215 insn = emit_insn_after (gen_pool_section_end (), insn);
5216 INSN_ADDRESSES_NEW (insn, -1);
5219 insn = emit_barrier_after (insn);
5220 INSN_ADDRESSES_NEW (insn, -1);
5222 /* Remove placeholder insn. */
5223 remove_insn (pool->pool_insn);
5226 /* Free all memory used by POOL. */
5229 s390_free_pool (struct constant_pool *pool)
5231 struct constant *c, *next;
5234 for (i = 0; i < NR_C_MODES; i++)
5235 for (c = pool->constants[i]; c; c = next)
5241 for (c = pool->execute; c; c = next)
5247 BITMAP_FREE (pool->insns);
5252 /* Collect main literal pool. Return NULL on overflow. */
5254 static struct constant_pool *
5255 s390_mainpool_start (void)
5257 struct constant_pool *pool;
5260 pool = s390_alloc_pool ();
5262 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5264 if (GET_CODE (insn) == INSN
5265 && GET_CODE (PATTERN (insn)) == SET
5266 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
5267 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
5269 gcc_assert (!pool->pool_insn);
5270 pool->pool_insn = insn;
5273 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5275 s390_add_execute (pool, insn);
5277 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5279 rtx pool_ref = NULL_RTX;
5280 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5283 rtx constant = get_pool_constant (pool_ref);
5284 enum machine_mode mode = get_pool_mode (pool_ref);
5285 s390_add_constant (pool, constant, mode);
5290 gcc_assert (pool->pool_insn || pool->size == 0);
5292 if (pool->size >= 4096)
5294 /* We're going to chunkify the pool, so remove the main
5295 pool placeholder insn. */
5296 remove_insn (pool->pool_insn);
5298 s390_free_pool (pool);
5305 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5306 Modify the current function to output the pool constants as well as
5307 the pool register setup instruction. */
5310 s390_mainpool_finish (struct constant_pool *pool)
5312 rtx base_reg = cfun->machine->base_reg;
5315 /* If the pool is empty, we're done. */
5316 if (pool->size == 0)
5318 /* We don't actually need a base register after all. */
5319 cfun->machine->base_reg = NULL_RTX;
5321 if (pool->pool_insn)
5322 remove_insn (pool->pool_insn);
5323 s390_free_pool (pool);
5327 /* We need correct insn addresses. */
5328 shorten_branches (get_insns ());
5330 /* On zSeries, we use a LARL to load the pool register. The pool is
5331 located in the .rodata section, so we emit it after the function. */
5332 if (TARGET_CPU_ZARCH)
5334 insn = gen_main_base_64 (base_reg, pool->label);
5335 insn = emit_insn_after (insn, pool->pool_insn);
5336 INSN_ADDRESSES_NEW (insn, -1);
5337 remove_insn (pool->pool_insn);
5339 insn = get_last_insn ();
5340 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5341 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5343 s390_dump_pool (pool, 0);
5346 /* On S/390, if the total size of the function's code plus literal pool
5347 does not exceed 4096 bytes, we use BASR to set up a function base
5348 pointer, and emit the literal pool at the end of the function. */
5349 else if (INSN_ADDRESSES (INSN_UID (get_last_insn ()))
5350 + pool->size + 8 /* alignment slop */ < 4096)
5352 insn = gen_main_base_31_small (base_reg, pool->label);
5353 insn = emit_insn_after (insn, pool->pool_insn);
5354 INSN_ADDRESSES_NEW (insn, -1);
5355 remove_insn (pool->pool_insn);
5357 insn = emit_label_after (pool->label, insn);
5358 INSN_ADDRESSES_NEW (insn, -1);
5360 insn = get_last_insn ();
5361 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5362 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5364 s390_dump_pool (pool, 1);
5367 /* Otherwise, we emit an inline literal pool and use BASR to branch
5368 over it, setting up the pool register at the same time. */
5371 rtx pool_end = gen_label_rtx ();
5373 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
5374 insn = emit_insn_after (insn, pool->pool_insn);
5375 INSN_ADDRESSES_NEW (insn, -1);
5376 remove_insn (pool->pool_insn);
5378 insn = emit_label_after (pool->label, insn);
5379 INSN_ADDRESSES_NEW (insn, -1);
5381 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
5382 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
5384 insn = emit_label_after (pool_end, pool->pool_insn);
5385 INSN_ADDRESSES_NEW (insn, -1);
5387 s390_dump_pool (pool, 1);
5391 /* Replace all literal pool references. */
5393 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5396 replace_ltrel_base (&PATTERN (insn));
5398 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5400 rtx addr, pool_ref = NULL_RTX;
5401 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5404 if (s390_execute_label (insn))
5405 addr = s390_find_execute (pool, insn);
5407 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
5408 get_pool_mode (pool_ref));
5410 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
5411 INSN_CODE (insn) = -1;
5417 /* Free the pool. */
5418 s390_free_pool (pool);
5421 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5422 We have decided we cannot use this pool, so revert all changes
5423 to the current function that were done by s390_mainpool_start. */
5425 s390_mainpool_cancel (struct constant_pool *pool)
5427 /* We didn't actually change the instruction stream, so simply
5428 free the pool memory. */
5429 s390_free_pool (pool);
5433 /* Chunkify the literal pool. */
5435 #define S390_POOL_CHUNK_MIN 0xc00
5436 #define S390_POOL_CHUNK_MAX 0xe00
5438 static struct constant_pool *
5439 s390_chunkify_start (void)
5441 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
5444 rtx pending_ltrel = NULL_RTX;
5447 rtx (*gen_reload_base) (rtx, rtx) =
5448 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
5451 /* We need correct insn addresses. */
5453 shorten_branches (get_insns ());
5455 /* Scan all insns and move literals to pool chunks. */
5457 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5459 /* Check for pending LTREL_BASE. */
5462 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
5465 gcc_assert (ltrel_base == pending_ltrel);
5466 pending_ltrel = NULL_RTX;
5470 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
5473 curr_pool = s390_start_pool (&pool_list, insn);
5475 s390_add_execute (curr_pool, insn);
5476 s390_add_pool_insn (curr_pool, insn);
5478 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5480 rtx pool_ref = NULL_RTX;
5481 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5484 rtx constant = get_pool_constant (pool_ref);
5485 enum machine_mode mode = get_pool_mode (pool_ref);
5488 curr_pool = s390_start_pool (&pool_list, insn);
5490 s390_add_constant (curr_pool, constant, mode);
5491 s390_add_pool_insn (curr_pool, insn);
5493 /* Don't split the pool chunk between a LTREL_OFFSET load
5494 and the corresponding LTREL_BASE. */
5495 if (GET_CODE (constant) == CONST
5496 && GET_CODE (XEXP (constant, 0)) == UNSPEC
5497 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
5499 gcc_assert (!pending_ltrel);
5500 pending_ltrel = pool_ref;
5505 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
5508 s390_add_pool_insn (curr_pool, insn);
5509 /* An LTREL_BASE must follow within the same basic block. */
5510 gcc_assert (!pending_ltrel);
5514 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
5515 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
5518 if (TARGET_CPU_ZARCH)
5520 if (curr_pool->size < S390_POOL_CHUNK_MAX)
5523 s390_end_pool (curr_pool, NULL_RTX);
5528 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
5529 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
5532 /* We will later have to insert base register reload insns.
5533 Those will have an effect on code size, which we need to
5534 consider here. This calculation makes rather pessimistic
5535 worst-case assumptions. */
5536 if (GET_CODE (insn) == CODE_LABEL)
5539 if (chunk_size < S390_POOL_CHUNK_MIN
5540 && curr_pool->size < S390_POOL_CHUNK_MIN)
5543 /* Pool chunks can only be inserted after BARRIERs ... */
5544 if (GET_CODE (insn) == BARRIER)
5546 s390_end_pool (curr_pool, insn);
5551 /* ... so if we don't find one in time, create one. */
5552 else if ((chunk_size > S390_POOL_CHUNK_MAX
5553 || curr_pool->size > S390_POOL_CHUNK_MAX))
5555 rtx label, jump, barrier;
5557 /* We can insert the barrier only after a 'real' insn. */
5558 if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN)
5560 if (get_attr_length (insn) == 0)
5563 /* Don't separate LTREL_BASE from the corresponding
5564 LTREL_OFFSET load. */
5568 label = gen_label_rtx ();
5569 jump = emit_jump_insn_after (gen_jump (label), insn);
5570 barrier = emit_barrier_after (jump);
5571 insn = emit_label_after (label, barrier);
5572 JUMP_LABEL (jump) = label;
5573 LABEL_NUSES (label) = 1;
5575 INSN_ADDRESSES_NEW (jump, -1);
5576 INSN_ADDRESSES_NEW (barrier, -1);
5577 INSN_ADDRESSES_NEW (insn, -1);
5579 s390_end_pool (curr_pool, barrier);
5587 s390_end_pool (curr_pool, NULL_RTX);
5588 gcc_assert (!pending_ltrel);
5590 /* Find all labels that are branched into
5591 from an insn belonging to a different chunk. */
5593 far_labels = BITMAP_ALLOC (NULL);
5595 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5597 /* Labels marked with LABEL_PRESERVE_P can be target
5598 of non-local jumps, so we have to mark them.
5599 The same holds for named labels.
5601 Don't do that, however, if it is the label before
5604 if (GET_CODE (insn) == CODE_LABEL
5605 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
5607 rtx vec_insn = next_real_insn (insn);
5608 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
5609 PATTERN (vec_insn) : NULL_RTX;
5611 || !(GET_CODE (vec_pat) == ADDR_VEC
5612 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
5613 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
5616 /* If we have a direct jump (conditional or unconditional)
5617 or a casesi jump, check all potential targets. */
5618 else if (GET_CODE (insn) == JUMP_INSN)
5620 rtx pat = PATTERN (insn);
5621 if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
5622 pat = XVECEXP (pat, 0, 0);
5624 if (GET_CODE (pat) == SET)
5626 rtx label = JUMP_LABEL (insn);
5629 if (s390_find_pool (pool_list, label)
5630 != s390_find_pool (pool_list, insn))
5631 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
5634 else if (GET_CODE (pat) == PARALLEL
5635 && XVECLEN (pat, 0) == 2
5636 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
5637 && GET_CODE (XVECEXP (pat, 0, 1)) == USE
5638 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF)
5640 /* Find the jump table used by this casesi jump. */
5641 rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
5642 rtx vec_insn = next_real_insn (vec_label);
5643 rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
5644 PATTERN (vec_insn) : NULL_RTX;
5646 && (GET_CODE (vec_pat) == ADDR_VEC
5647 || GET_CODE (vec_pat) == ADDR_DIFF_VEC))
5649 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
5651 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
5653 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
5655 if (s390_find_pool (pool_list, label)
5656 != s390_find_pool (pool_list, insn))
5657 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
5664 /* Insert base register reload insns before every pool. */
5666 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
5668 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
5670 rtx insn = curr_pool->first_insn;
5671 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
5674 /* Insert base register reload insns at every far label. */
5676 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5677 if (GET_CODE (insn) == CODE_LABEL
5678 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
5680 struct constant_pool *pool = s390_find_pool (pool_list, insn);
5683 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
5685 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
5690 BITMAP_FREE (far_labels);
5693 /* Recompute insn addresses. */
5695 init_insn_lengths ();
5696 shorten_branches (get_insns ());
5701 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
5702 After we have decided to use this list, finish implementing
5703 all changes to the current function as required. */
5706 s390_chunkify_finish (struct constant_pool *pool_list)
5708 struct constant_pool *curr_pool = NULL;
5712 /* Replace all literal pool references. */
5714 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5717 replace_ltrel_base (&PATTERN (insn));
5719 curr_pool = s390_find_pool (pool_list, insn);
5723 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
5725 rtx addr, pool_ref = NULL_RTX;
5726 find_constant_pool_ref (PATTERN (insn), &pool_ref);
5729 if (s390_execute_label (insn))
5730 addr = s390_find_execute (curr_pool, insn);
5732 addr = s390_find_constant (curr_pool,
5733 get_pool_constant (pool_ref),
5734 get_pool_mode (pool_ref));
5736 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
5737 INSN_CODE (insn) = -1;
5742 /* Dump out all literal pools. */
5744 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
5745 s390_dump_pool (curr_pool, 0);
5747 /* Free pool list. */
5751 struct constant_pool *next = pool_list->next;
5752 s390_free_pool (pool_list);
5757 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
5758 We have decided we cannot use this list, so revert all changes
5759 to the current function that were done by s390_chunkify_start. */
5762 s390_chunkify_cancel (struct constant_pool *pool_list)
5764 struct constant_pool *curr_pool = NULL;
5767 /* Remove all pool placeholder insns. */
5769 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
5771 /* Did we insert an extra barrier? Remove it. */
5772 rtx barrier = PREV_INSN (curr_pool->pool_insn);
5773 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
5774 rtx label = NEXT_INSN (curr_pool->pool_insn);
5776 if (jump && GET_CODE (jump) == JUMP_INSN
5777 && barrier && GET_CODE (barrier) == BARRIER
5778 && label && GET_CODE (label) == CODE_LABEL
5779 && GET_CODE (PATTERN (jump)) == SET
5780 && SET_DEST (PATTERN (jump)) == pc_rtx
5781 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
5782 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
5785 remove_insn (barrier);
5786 remove_insn (label);
5789 remove_insn (curr_pool->pool_insn);
5792 /* Remove all base register reload insns. */
5794 for (insn = get_insns (); insn; )
5796 rtx next_insn = NEXT_INSN (insn);
5798 if (GET_CODE (insn) == INSN
5799 && GET_CODE (PATTERN (insn)) == SET
5800 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
5801 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
5807 /* Free pool list. */
5811 struct constant_pool *next = pool_list->next;
5812 s390_free_pool (pool_list);
5818 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
5821 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
5825 switch (GET_MODE_CLASS (mode))
5828 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
5830 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
5831 assemble_real (r, mode, align);
5835 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
5844 /* Return an RTL expression representing the value of the return address
5845 for the frame COUNT steps up from the current frame. FRAME is the
5846 frame pointer of that frame. */
5849 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
5854 /* Without backchain, we fail for all but the current frame. */
5856 if (!TARGET_BACKCHAIN && count > 0)
5859 /* For the current frame, we need to make sure the initial
5860 value of RETURN_REGNUM is actually saved. */
5864 /* On non-z architectures branch splitting could overwrite r14. */
5865 if (TARGET_CPU_ZARCH)
5866 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
5869 cfun_frame_layout.save_return_addr_p = true;
5870 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
5874 if (TARGET_PACKED_STACK)
5875 offset = -2 * UNITS_PER_WORD;
5877 offset = RETURN_REGNUM * UNITS_PER_WORD;
5879 addr = plus_constant (frame, offset);
5880 addr = memory_address (Pmode, addr);
5881 return gen_rtx_MEM (Pmode, addr);
5884 /* Return an RTL expression representing the back chain stored in
5885 the current stack frame. */
5888 s390_back_chain_rtx (void)
5892 gcc_assert (TARGET_BACKCHAIN);
5894 if (TARGET_PACKED_STACK)
5895 chain = plus_constant (stack_pointer_rtx,
5896 STACK_POINTER_OFFSET - UNITS_PER_WORD);
5898 chain = stack_pointer_rtx;
5900 chain = gen_rtx_MEM (Pmode, chain);
5904 /* Find first call clobbered register unused in a function.
5905 This could be used as base register in a leaf function
5906 or for holding the return address before epilogue. */
5909 find_unused_clobbered_reg (void)
5912 for (i = 0; i < 6; i++)
5913 if (!regs_ever_live[i])
5919 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
5920 clobbered hard regs in SETREG. */
5923 s390_reg_clobbered_rtx (rtx setreg, rtx set_insn ATTRIBUTE_UNUSED, void *data)
5925 int *regs_ever_clobbered = (int *)data;
5926 unsigned int i, regno;
5927 enum machine_mode mode = GET_MODE (setreg);
5929 if (GET_CODE (setreg) == SUBREG)
5931 rtx inner = SUBREG_REG (setreg);
5932 if (!GENERAL_REG_P (inner))
5934 regno = subreg_regno (setreg);
5936 else if (GENERAL_REG_P (setreg))
5937 regno = REGNO (setreg);
5942 i < regno + HARD_REGNO_NREGS (regno, mode);
5944 regs_ever_clobbered[i] = 1;
5947 /* Walks through all basic blocks of the current function looking
5948 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
5949 of the passed integer array REGS_EVER_CLOBBERED are set to one for
5950 each of those regs. */
5953 s390_regs_ever_clobbered (int *regs_ever_clobbered)
5959 memset (regs_ever_clobbered, 0, 16 * sizeof (int));
5961 /* For non-leaf functions we have to consider all call clobbered regs to be
5963 if (!current_function_is_leaf)
5965 for (i = 0; i < 16; i++)
5966 regs_ever_clobbered[i] = call_really_used_regs[i];
5969 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
5970 this work is done by liveness analysis (mark_regs_live_at_end).
5971 Special care is needed for functions containing landing pads. Landing pads
5972 may use the eh registers, but the code which sets these registers is not
5973 contained in that function. Hence s390_regs_ever_clobbered is not able to
5974 deal with this automatically. */
5975 if (current_function_calls_eh_return || cfun->machine->has_landing_pad_p)
5976 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
5977 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
5979 /* For nonlocal gotos all call-saved registers have to be saved.
5980 This flag is also set for the unwinding code in libgcc.
5981 See expand_builtin_unwind_init. For regs_ever_live this is done by
5983 if (current_function_has_nonlocal_label)
5984 for (i = 0; i < 16; i++)
5985 if (!call_really_used_regs[i])
5986 regs_ever_clobbered[i] = 1;
5988 FOR_EACH_BB (cur_bb)
5990 FOR_BB_INSNS (cur_bb, cur_insn)
5992 if (INSN_P (cur_insn))
5993 note_stores (PATTERN (cur_insn),
5994 s390_reg_clobbered_rtx,
5995 regs_ever_clobbered);
6000 /* Determine the frame area which actually has to be accessed
6001 in the function epilogue. The values are stored at the
6002 given pointers AREA_BOTTOM (address of the lowest used stack
6003 address) and AREA_TOP (address of the first item which does
6004 not belong to the stack frame). */
6007 s390_frame_area (int *area_bottom, int *area_top)
6015 if (cfun_frame_layout.first_restore_gpr != -1)
6017 b = (cfun_frame_layout.gprs_offset
6018 + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
6019 t = b + (cfun_frame_layout.last_restore_gpr
6020 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
6023 if (TARGET_64BIT && cfun_save_high_fprs_p)
6025 b = MIN (b, cfun_frame_layout.f8_offset);
6026 t = MAX (t, (cfun_frame_layout.f8_offset
6027 + cfun_frame_layout.high_fprs * 8));
6031 for (i = 2; i < 4; i++)
6032 if (cfun_fpr_bit_p (i))
6034 b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8);
6035 t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8);
6042 /* Fill cfun->machine with info about register usage of current function.
6043 Return in CLOBBERED_REGS which GPRs are currently considered set. */
6046 s390_register_info (int clobbered_regs[])
6050 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
6051 cfun_frame_layout.fpr_bitmap = 0;
6052 cfun_frame_layout.high_fprs = 0;
6054 for (i = 24; i < 32; i++)
6055 if (regs_ever_live[i] && !global_regs[i])
6057 cfun_set_fpr_bit (i - 16);
6058 cfun_frame_layout.high_fprs++;
6061 /* Find first and last gpr to be saved. We trust regs_ever_live
6062 data, except that we don't save and restore global registers.
6064 Also, all registers with special meaning to the compiler need
6065 to be handled extra. */
6067 s390_regs_ever_clobbered (clobbered_regs);
6069 for (i = 0; i < 16; i++)
6070 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i];
6072 if (frame_pointer_needed)
6073 clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1;
6076 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
6077 |= regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
6079 clobbered_regs[BASE_REGNUM]
6080 |= (cfun->machine->base_reg
6081 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
6083 clobbered_regs[RETURN_REGNUM]
6084 |= (!current_function_is_leaf
6085 || TARGET_TPF_PROFILING
6086 || cfun->machine->split_branches_pending_p
6087 || cfun_frame_layout.save_return_addr_p
6088 || current_function_calls_eh_return
6089 || current_function_stdarg);
6091 clobbered_regs[STACK_POINTER_REGNUM]
6092 |= (!current_function_is_leaf
6093 || TARGET_TPF_PROFILING
6094 || cfun_save_high_fprs_p
6095 || get_frame_size () > 0
6096 || current_function_calls_alloca
6097 || current_function_stdarg);
6099 for (i = 6; i < 16; i++)
6100 if (clobbered_regs[i])
6102 for (j = 15; j > i; j--)
6103 if (clobbered_regs[j])
6108 /* Nothing to save/restore. */
6109 cfun_frame_layout.first_save_gpr = -1;
6110 cfun_frame_layout.first_restore_gpr = -1;
6111 cfun_frame_layout.last_save_gpr = -1;
6112 cfun_frame_layout.last_restore_gpr = -1;
6116 /* Save / Restore from gpr i to j. */
6117 cfun_frame_layout.first_save_gpr = i;
6118 cfun_frame_layout.first_restore_gpr = i;
6119 cfun_frame_layout.last_save_gpr = j;
6120 cfun_frame_layout.last_restore_gpr = j;
6123 if (current_function_stdarg)
6125 /* Varargs functions need to save gprs 2 to 6. */
6126 if (cfun->va_list_gpr_size
6127 && current_function_args_info.gprs < GP_ARG_NUM_REG)
6129 int min_gpr = current_function_args_info.gprs;
6130 int max_gpr = min_gpr + cfun->va_list_gpr_size;
6131 if (max_gpr > GP_ARG_NUM_REG)
6132 max_gpr = GP_ARG_NUM_REG;
6134 if (cfun_frame_layout.first_save_gpr == -1
6135 || cfun_frame_layout.first_save_gpr > 2 + min_gpr)
6136 cfun_frame_layout.first_save_gpr = 2 + min_gpr;
6138 if (cfun_frame_layout.last_save_gpr == -1
6139 || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1)
6140 cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1;
6143 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
6144 if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size
6145 && current_function_args_info.fprs < FP_ARG_NUM_REG)
6147 int min_fpr = current_function_args_info.fprs;
6148 int max_fpr = min_fpr + cfun->va_list_fpr_size;
6149 if (max_fpr > FP_ARG_NUM_REG)
6150 max_fpr = FP_ARG_NUM_REG;
6152 /* ??? This is currently required to ensure proper location
6153 of the fpr save slots within the va_list save area. */
6154 if (TARGET_PACKED_STACK)
6157 for (i = min_fpr; i < max_fpr; i++)
6158 cfun_set_fpr_bit (i);
6163 for (i = 2; i < 4; i++)
6164 if (regs_ever_live[i + 16] && !global_regs[i + 16])
6165 cfun_set_fpr_bit (i);
6168 /* Fill cfun->machine with info about frame of current function. */
6171 s390_frame_info (void)
6175 cfun_frame_layout.frame_size = get_frame_size ();
6176 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
6177 fatal_error ("total size of local variables exceeds architecture limit");
6179 if (!TARGET_PACKED_STACK)
6181 cfun_frame_layout.backchain_offset = 0;
6182 cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
6183 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
6184 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
6185 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr
6188 else if (TARGET_BACKCHAIN) /* kernel stack layout */
6190 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
6192 cfun_frame_layout.gprs_offset
6193 = (cfun_frame_layout.backchain_offset
6194 - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr + 1)
6199 cfun_frame_layout.f4_offset
6200 = (cfun_frame_layout.gprs_offset
6201 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6203 cfun_frame_layout.f0_offset
6204 = (cfun_frame_layout.f4_offset
6205 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6209 /* On 31 bit we have to care about alignment of the
6210 floating point regs to provide fastest access. */
6211 cfun_frame_layout.f0_offset
6212 = ((cfun_frame_layout.gprs_offset
6213 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1))
6214 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6216 cfun_frame_layout.f4_offset
6217 = (cfun_frame_layout.f0_offset
6218 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6221 else /* no backchain */
6223 cfun_frame_layout.f4_offset
6224 = (STACK_POINTER_OFFSET
6225 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6227 cfun_frame_layout.f0_offset
6228 = (cfun_frame_layout.f4_offset
6229 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6231 cfun_frame_layout.gprs_offset
6232 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
6235 if (current_function_is_leaf
6236 && !TARGET_TPF_PROFILING
6237 && cfun_frame_layout.frame_size == 0
6238 && !cfun_save_high_fprs_p
6239 && !current_function_calls_alloca
6240 && !current_function_stdarg)
6243 if (!TARGET_PACKED_STACK)
6244 cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET
6245 + current_function_outgoing_args_size
6246 + cfun_frame_layout.high_fprs * 8);
6249 if (TARGET_BACKCHAIN)
6250 cfun_frame_layout.frame_size += UNITS_PER_WORD;
6252 /* No alignment trouble here because f8-f15 are only saved under
6254 cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset,
6255 cfun_frame_layout.f4_offset),
6256 cfun_frame_layout.gprs_offset)
6257 - cfun_frame_layout.high_fprs * 8);
6259 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
6261 for (i = 0; i < 8; i++)
6262 if (cfun_fpr_bit_p (i))
6263 cfun_frame_layout.frame_size += 8;
6265 cfun_frame_layout.frame_size += cfun_gprs_save_area_size;
6267 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
6268 the frame size to sustain 8 byte alignment of stack frames. */
6269 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
6270 STACK_BOUNDARY / BITS_PER_UNIT - 1)
6271 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
6273 cfun_frame_layout.frame_size += current_function_outgoing_args_size;
6277 /* Generate frame layout. Fills in register and frame data for the current
6278 function in cfun->machine. This routine can be called multiple times;
6279 it will re-do the complete frame layout every time. */
6282 s390_init_frame_layout (void)
6284 HOST_WIDE_INT frame_size;
6286 int clobbered_regs[16];
6288 /* On S/390 machines, we may need to perform branch splitting, which
6289 will require both base and return address register. We have no
6290 choice but to assume we're going to need them until right at the
6291 end of the machine dependent reorg phase. */
6292 if (!TARGET_CPU_ZARCH)
6293 cfun->machine->split_branches_pending_p = true;
6297 frame_size = cfun_frame_layout.frame_size;
6299 /* Try to predict whether we'll need the base register. */
6300 base_used = cfun->machine->split_branches_pending_p
6301 || current_function_uses_const_pool
6302 || (!DISP_IN_RANGE (-frame_size)
6303 && !CONST_OK_FOR_K (-frame_size));
6305 /* Decide which register to use as literal pool base. In small
6306 leaf functions, try to use an unused call-clobbered register
6307 as base register to avoid save/restore overhead. */
6309 cfun->machine->base_reg = NULL_RTX;
6310 else if (current_function_is_leaf && !regs_ever_live[5])
6311 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
6313 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
6315 s390_register_info (clobbered_regs);
6318 while (frame_size != cfun_frame_layout.frame_size);
6321 /* Update frame layout. Recompute actual register save data based on
6322 current info and update regs_ever_live for the special registers.
6323 May be called multiple times, but may never cause *more* registers
6324 to be saved than s390_init_frame_layout allocated room for. */
6327 s390_update_frame_layout (void)
6329 int clobbered_regs[16];
6331 s390_register_info (clobbered_regs);
6333 regs_ever_live[BASE_REGNUM] = clobbered_regs[BASE_REGNUM];
6334 regs_ever_live[RETURN_REGNUM] = clobbered_regs[RETURN_REGNUM];
6335 regs_ever_live[STACK_POINTER_REGNUM] = clobbered_regs[STACK_POINTER_REGNUM];
6337 if (cfun->machine->base_reg)
6338 regs_ever_live[REGNO (cfun->machine->base_reg)] = 1;
6341 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
6344 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
6346 /* Once we've decided upon a register to use as base register, it must
6347 no longer be used for any other purpose. */
6348 if (cfun->machine->base_reg)
6349 if (REGNO (cfun->machine->base_reg) == old_reg
6350 || REGNO (cfun->machine->base_reg) == new_reg)
6356 /* Return true if register FROM can be eliminated via register TO. */
6359 s390_can_eliminate (int from, int to)
6361 /* On zSeries machines, we have not marked the base register as fixed.
6362 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
6363 If a function requires the base register, we say here that this
6364 elimination cannot be performed. This will cause reload to free
6365 up the base register (as if it were fixed). On the other hand,
6366 if the current function does *not* require the base register, we
6367 say here the elimination succeeds, which in turn allows reload
6368 to allocate the base register for any other purpose. */
6369 if (from == BASE_REGNUM && to == BASE_REGNUM)
6371 if (TARGET_CPU_ZARCH)
6373 s390_init_frame_layout ();
6374 return cfun->machine->base_reg == NULL_RTX;
6380 /* Everything else must point into the stack frame. */
6381 gcc_assert (to == STACK_POINTER_REGNUM
6382 || to == HARD_FRAME_POINTER_REGNUM);
6384 gcc_assert (from == FRAME_POINTER_REGNUM
6385 || from == ARG_POINTER_REGNUM
6386 || from == RETURN_ADDRESS_POINTER_REGNUM);
6388 /* Make sure we actually saved the return address. */
6389 if (from == RETURN_ADDRESS_POINTER_REGNUM)
6390 if (!current_function_calls_eh_return
6391 && !current_function_stdarg
6392 && !cfun_frame_layout.save_return_addr_p)
6398 /* Return offset between register FROM and TO initially after prolog. */
6401 s390_initial_elimination_offset (int from, int to)
6403 HOST_WIDE_INT offset;
6406 /* ??? Why are we called for non-eliminable pairs? */
6407 if (!s390_can_eliminate (from, to))
6412 case FRAME_POINTER_REGNUM:
6413 offset = (get_frame_size()
6414 + STACK_POINTER_OFFSET
6415 + current_function_outgoing_args_size);
6418 case ARG_POINTER_REGNUM:
6419 s390_init_frame_layout ();
6420 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
6423 case RETURN_ADDRESS_POINTER_REGNUM:
6424 s390_init_frame_layout ();
6425 index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr;
6426 gcc_assert (index >= 0);
6427 offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
6428 offset += index * UNITS_PER_WORD;
6442 /* Emit insn to save fpr REGNUM at offset OFFSET relative
6443 to register BASE. Return generated insn. */
6446 save_fpr (rtx base, int offset, int regnum)
6449 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6451 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
6452 set_mem_alias_set (addr, get_varargs_alias_set ());
6454 set_mem_alias_set (addr, get_frame_alias_set ());
6456 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
6459 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
6460 to register BASE. Return generated insn. */
6463 restore_fpr (rtx base, int offset, int regnum)
6466 addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
6467 set_mem_alias_set (addr, get_frame_alias_set ());
6469 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
6472 /* Generate insn to save registers FIRST to LAST into
6473 the register save area located at offset OFFSET
6474 relative to register BASE. */
6477 save_gprs (rtx base, int offset, int first, int last)
6479 rtx addr, insn, note;
6482 addr = plus_constant (base, offset);
6483 addr = gen_rtx_MEM (Pmode, addr);
6485 set_mem_alias_set (addr, get_frame_alias_set ());
6487 /* Special-case single register. */
6491 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
6493 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
6495 RTX_FRAME_RELATED_P (insn) = 1;
6500 insn = gen_store_multiple (addr,
6501 gen_rtx_REG (Pmode, first),
6502 GEN_INT (last - first + 1));
6504 if (first <= 6 && current_function_stdarg)
6505 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
6507 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
6510 set_mem_alias_set (mem, get_varargs_alias_set ());
6513 /* We need to set the FRAME_RELATED flag on all SETs
6514 inside the store-multiple pattern.
6516 However, we must not emit DWARF records for registers 2..5
6517 if they are stored for use by variable arguments ...
6519 ??? Unfortunately, it is not enough to simply not the
6520 FRAME_RELATED flags for those SETs, because the first SET
6521 of the PARALLEL is always treated as if it had the flag
6522 set, even if it does not. Therefore we emit a new pattern
6523 without those registers as REG_FRAME_RELATED_EXPR note. */
6527 rtx pat = PATTERN (insn);
6529 for (i = 0; i < XVECLEN (pat, 0); i++)
6530 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
6531 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
6533 RTX_FRAME_RELATED_P (insn) = 1;
6537 addr = plus_constant (base, offset + (6 - first) * UNITS_PER_WORD);
6538 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
6539 gen_rtx_REG (Pmode, 6),
6540 GEN_INT (last - 6 + 1));
6541 note = PATTERN (note);
6544 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6545 note, REG_NOTES (insn));
6547 for (i = 0; i < XVECLEN (note, 0); i++)
6548 if (GET_CODE (XVECEXP (note, 0, i)) == SET)
6549 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
6551 RTX_FRAME_RELATED_P (insn) = 1;
6557 /* Generate insn to restore registers FIRST to LAST from
6558 the register save area located at offset OFFSET
6559 relative to register BASE. */
6562 restore_gprs (rtx base, int offset, int first, int last)
6566 addr = plus_constant (base, offset);
6567 addr = gen_rtx_MEM (Pmode, addr);
6568 set_mem_alias_set (addr, get_frame_alias_set ());
6570 /* Special-case single register. */
6574 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
6576 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
6581 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
6583 GEN_INT (last - first + 1));
6587 /* Return insn sequence to load the GOT register. */
6589 static GTY(()) rtx got_symbol;
6591 s390_load_got (void)
6597 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
6598 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
6603 if (TARGET_CPU_ZARCH)
6605 emit_move_insn (pic_offset_table_rtx, got_symbol);
6611 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
6612 UNSPEC_LTREL_OFFSET);
6613 offset = gen_rtx_CONST (Pmode, offset);
6614 offset = force_const_mem (Pmode, offset);
6616 emit_move_insn (pic_offset_table_rtx, offset);
6618 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
6620 offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
6622 emit_move_insn (pic_offset_table_rtx, offset);
6625 insns = get_insns ();
6630 /* Expand the prologue into a bunch of separate insns. */
6633 s390_emit_prologue (void)
6641 /* Complete frame layout. */
6643 s390_update_frame_layout ();
6645 /* Annotate all constant pool references to let the scheduler know
6646 they implicitly use the base register. */
6648 push_topmost_sequence ();
6650 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6652 annotate_constant_pool_refs (&PATTERN (insn));
6654 pop_topmost_sequence ();
6656 /* Choose best register to use for temp use within prologue.
6657 See below for why TPF must use the register 1. */
6659 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
6660 && !current_function_is_leaf
6661 && !TARGET_TPF_PROFILING)
6662 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
6664 temp_reg = gen_rtx_REG (Pmode, 1);
6666 /* Save call saved gprs. */
6667 if (cfun_frame_layout.first_save_gpr != -1)
6669 insn = save_gprs (stack_pointer_rtx,
6670 cfun_frame_layout.gprs_offset,
6671 cfun_frame_layout.first_save_gpr,
6672 cfun_frame_layout.last_save_gpr);
6676 /* Dummy insn to mark literal pool slot. */
6678 if (cfun->machine->base_reg)
6679 emit_insn (gen_main_pool (cfun->machine->base_reg));
6681 offset = cfun_frame_layout.f0_offset;
6683 /* Save f0 and f2. */
6684 for (i = 0; i < 2; i++)
6686 if (cfun_fpr_bit_p (i))
6688 save_fpr (stack_pointer_rtx, offset, i + 16);
6691 else if (!TARGET_PACKED_STACK)
6695 /* Save f4 and f6. */
6696 offset = cfun_frame_layout.f4_offset;
6697 for (i = 2; i < 4; i++)
6699 if (cfun_fpr_bit_p (i))
6701 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
6704 /* If f4 and f6 are call clobbered they are saved due to stdargs and
6705 therefore are not frame related. */
6706 if (!call_really_used_regs[i + 16])
6707 RTX_FRAME_RELATED_P (insn) = 1;
6709 else if (!TARGET_PACKED_STACK)
6713 if (TARGET_PACKED_STACK
6714 && cfun_save_high_fprs_p
6715 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
6717 offset = (cfun_frame_layout.f8_offset
6718 + (cfun_frame_layout.high_fprs - 1) * 8);
6720 for (i = 15; i > 7 && offset >= 0; i--)
6721 if (cfun_fpr_bit_p (i))
6723 insn = save_fpr (stack_pointer_rtx, offset, i + 16);
6725 RTX_FRAME_RELATED_P (insn) = 1;
6728 if (offset >= cfun_frame_layout.f8_offset)
6732 if (!TARGET_PACKED_STACK)
6733 next_fpr = cfun_save_high_fprs_p ? 31 : 0;
6735 /* Decrement stack pointer. */
6737 if (cfun_frame_layout.frame_size > 0)
6739 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
6741 if (s390_stack_size)
6743 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
6744 & ~(s390_stack_guard - 1));
6745 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
6746 GEN_INT (stack_check_mask));
6749 gen_cmpdi (t, const0_rtx);
6751 gen_cmpsi (t, const0_rtx);
6753 emit_insn (gen_conditional_trap (gen_rtx_EQ (CCmode,
6754 gen_rtx_REG (CCmode,
6760 if (s390_warn_framesize > 0
6761 && cfun_frame_layout.frame_size >= s390_warn_framesize)
6762 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes",
6763 current_function_name (), cfun_frame_layout.frame_size);
6765 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
6766 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
6768 /* Save incoming stack pointer into temp reg. */
6769 if (TARGET_BACKCHAIN || next_fpr)
6770 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
6772 /* Subtract frame size from stack pointer. */
6774 if (DISP_IN_RANGE (INTVAL (frame_off)))
6776 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6777 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
6779 insn = emit_insn (insn);
6783 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
6784 frame_off = force_const_mem (Pmode, frame_off);
6786 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
6787 annotate_constant_pool_refs (&PATTERN (insn));
6790 RTX_FRAME_RELATED_P (insn) = 1;
6792 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6793 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6794 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
6795 GEN_INT (-cfun_frame_layout.frame_size))),
6798 /* Set backchain. */
6800 if (TARGET_BACKCHAIN)
6802 if (cfun_frame_layout.backchain_offset)
6803 addr = gen_rtx_MEM (Pmode,
6804 plus_constant (stack_pointer_rtx,
6805 cfun_frame_layout.backchain_offset));
6807 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
6808 set_mem_alias_set (addr, get_frame_alias_set ());
6809 insn = emit_insn (gen_move_insn (addr, temp_reg));
6812 /* If we support asynchronous exceptions (e.g. for Java),
6813 we need to make sure the backchain pointer is set up
6814 before any possibly trapping memory access. */
6816 if (TARGET_BACKCHAIN && flag_non_call_exceptions)
6818 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
6819 emit_insn (gen_rtx_CLOBBER (VOIDmode, addr));
6823 /* Save fprs 8 - 15 (64 bit ABI). */
6825 if (cfun_save_high_fprs_p && next_fpr)
6827 insn = emit_insn (gen_add2_insn (temp_reg,
6828 GEN_INT (cfun_frame_layout.f8_offset)));
6832 for (i = 24; i <= next_fpr; i++)
6833 if (cfun_fpr_bit_p (i - 16))
6835 rtx addr = plus_constant (stack_pointer_rtx,
6836 cfun_frame_layout.frame_size
6837 + cfun_frame_layout.f8_offset
6840 insn = save_fpr (temp_reg, offset, i);
6842 RTX_FRAME_RELATED_P (insn) = 1;
6844 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6845 gen_rtx_SET (VOIDmode,
6846 gen_rtx_MEM (DFmode, addr),
6847 gen_rtx_REG (DFmode, i)),
6852 /* Set frame pointer, if needed. */
6854 if (frame_pointer_needed)
6856 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6857 RTX_FRAME_RELATED_P (insn) = 1;
6860 /* Set up got pointer, if needed. */
6862 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
6864 rtx insns = s390_load_got ();
6866 for (insn = insns; insn; insn = NEXT_INSN (insn))
6868 annotate_constant_pool_refs (&PATTERN (insn));
6870 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
6877 if (TARGET_TPF_PROFILING)
6879 /* Generate a BAS instruction to serve as a function
6880 entry intercept to facilitate the use of tracing
6881 algorithms located at the branch target. */
6882 emit_insn (gen_prologue_tpf ());
6884 /* Emit a blockage here so that all code
6885 lies between the profiling mechanisms. */
6886 emit_insn (gen_blockage ());
6890 /* Expand the epilogue into a bunch of separate insns. */
6893 s390_emit_epilogue (bool sibcall)
6895 rtx frame_pointer, return_reg;
6896 int area_bottom, area_top, offset = 0;
6901 if (TARGET_TPF_PROFILING)
6904 /* Generate a BAS instruction to serve as a function
6905 entry intercept to facilitate the use of tracing
6906 algorithms located at the branch target. */
6908 /* Emit a blockage here so that all code
6909 lies between the profiling mechanisms. */
6910 emit_insn (gen_blockage ());
6912 emit_insn (gen_epilogue_tpf ());
6915 /* Check whether to use frame or stack pointer for restore. */
6917 frame_pointer = (frame_pointer_needed
6918 ? hard_frame_pointer_rtx : stack_pointer_rtx);
6920 s390_frame_area (&area_bottom, &area_top);
6922 /* Check whether we can access the register save area.
6923 If not, increment the frame pointer as required. */
6925 if (area_top <= area_bottom)
6927 /* Nothing to restore. */
6929 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
6930 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
6932 /* Area is in range. */
6933 offset = cfun_frame_layout.frame_size;
6937 rtx insn, frame_off;
6939 offset = area_bottom < 0 ? -area_bottom : 0;
6940 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
6942 if (DISP_IN_RANGE (INTVAL (frame_off)))
6944 insn = gen_rtx_SET (VOIDmode, frame_pointer,
6945 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
6946 insn = emit_insn (insn);
6950 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
6951 frame_off = force_const_mem (Pmode, frame_off);
6953 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
6954 annotate_constant_pool_refs (&PATTERN (insn));
6958 /* Restore call saved fprs. */
6962 if (cfun_save_high_fprs_p)
6964 next_offset = cfun_frame_layout.f8_offset;
6965 for (i = 24; i < 32; i++)
6967 if (cfun_fpr_bit_p (i - 16))
6969 restore_fpr (frame_pointer,
6970 offset + next_offset, i);
6979 next_offset = cfun_frame_layout.f4_offset;
6980 for (i = 18; i < 20; i++)
6982 if (cfun_fpr_bit_p (i - 16))
6984 restore_fpr (frame_pointer,
6985 offset + next_offset, i);
6988 else if (!TARGET_PACKED_STACK)
6994 /* Return register. */
6996 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
6998 /* Restore call saved gprs. */
7000 if (cfun_frame_layout.first_restore_gpr != -1)
7005 /* Check for global register and save them
7006 to stack location from where they get restored. */
7008 for (i = cfun_frame_layout.first_restore_gpr;
7009 i <= cfun_frame_layout.last_restore_gpr;
7012 /* These registers are special and need to be
7013 restored in any case. */
7014 if (i == STACK_POINTER_REGNUM
7015 || i == RETURN_REGNUM
7017 || (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
7022 addr = plus_constant (frame_pointer,
7023 offset + cfun_frame_layout.gprs_offset
7024 + (i - cfun_frame_layout.first_save_gpr)
7026 addr = gen_rtx_MEM (Pmode, addr);
7027 set_mem_alias_set (addr, get_frame_alias_set ());
7028 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
7034 /* Fetch return address from stack before load multiple,
7035 this will do good for scheduling. */
7037 if (cfun_frame_layout.save_return_addr_p
7038 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
7039 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
7041 int return_regnum = find_unused_clobbered_reg();
7044 return_reg = gen_rtx_REG (Pmode, return_regnum);
7046 addr = plus_constant (frame_pointer,
7047 offset + cfun_frame_layout.gprs_offset
7049 - cfun_frame_layout.first_save_gpr)
7051 addr = gen_rtx_MEM (Pmode, addr);
7052 set_mem_alias_set (addr, get_frame_alias_set ());
7053 emit_move_insn (return_reg, addr);
7057 insn = restore_gprs (frame_pointer,
7058 offset + cfun_frame_layout.gprs_offset
7059 + (cfun_frame_layout.first_restore_gpr
7060 - cfun_frame_layout.first_save_gpr)
7062 cfun_frame_layout.first_restore_gpr,
7063 cfun_frame_layout.last_restore_gpr);
7070 /* Return to caller. */
7072 p = rtvec_alloc (2);
7074 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
7075 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
7076 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
7081 /* Return the size in bytes of a function argument of
7082 type TYPE and/or mode MODE. At least one of TYPE or
7083 MODE must be specified. */
7086 s390_function_arg_size (enum machine_mode mode, tree type)
7089 return int_size_in_bytes (type);
7091 /* No type info available for some library calls ... */
7092 if (mode != BLKmode)
7093 return GET_MODE_SIZE (mode);
7095 /* If we have neither type nor mode, abort */
7099 /* Return true if a function argument of type TYPE and mode MODE
7100 is to be passed in a floating-point register, if available. */
7103 s390_function_arg_float (enum machine_mode mode, tree type)
7105 int size = s390_function_arg_size (mode, type);
7109 /* Soft-float changes the ABI: no floating-point registers are used. */
7110 if (TARGET_SOFT_FLOAT)
7113 /* No type info available for some library calls ... */
7115 return mode == SFmode || mode == DFmode;
7117 /* The ABI says that record types with a single member are treated
7118 just like that member would be. */
7119 while (TREE_CODE (type) == RECORD_TYPE)
7121 tree field, single = NULL_TREE;
7123 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
7125 if (TREE_CODE (field) != FIELD_DECL)
7128 if (single == NULL_TREE)
7129 single = TREE_TYPE (field);
7134 if (single == NULL_TREE)
7140 return TREE_CODE (type) == REAL_TYPE;
7143 /* Return true if a function argument of type TYPE and mode MODE
7144 is to be passed in an integer register, or a pair of integer
7145 registers, if available. */
7148 s390_function_arg_integer (enum machine_mode mode, tree type)
7150 int size = s390_function_arg_size (mode, type);
7154 /* No type info available for some library calls ... */
7156 return GET_MODE_CLASS (mode) == MODE_INT
7157 || (TARGET_SOFT_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT);
7159 /* We accept small integral (and similar) types. */
7160 if (INTEGRAL_TYPE_P (type)
7161 || POINTER_TYPE_P (type)
7162 || TREE_CODE (type) == OFFSET_TYPE
7163 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
7166 /* We also accept structs of size 1, 2, 4, 8 that are not
7167 passed in floating-point registers. */
7168 if (AGGREGATE_TYPE_P (type)
7169 && exact_log2 (size) >= 0
7170 && !s390_function_arg_float (mode, type))
7176 /* Return 1 if a function argument of type TYPE and mode MODE
7177 is to be passed by reference. The ABI specifies that only
7178 structures of size 1, 2, 4, or 8 bytes are passed by value,
7179 all other structures (and complex numbers) are passed by
7183 s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
7184 enum machine_mode mode, tree type,
7185 bool named ATTRIBUTE_UNUSED)
7187 int size = s390_function_arg_size (mode, type);
7193 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
7196 if (TREE_CODE (type) == COMPLEX_TYPE
7197 || TREE_CODE (type) == VECTOR_TYPE)
7204 /* Update the data in CUM to advance over an argument of mode MODE and
7205 data type TYPE. (TYPE is null for libcalls where that information
7206 may not be available.). The boolean NAMED specifies whether the
7207 argument is a named argument (as opposed to an unnamed argument
7208 matching an ellipsis). */
7211 s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7212 tree type, int named ATTRIBUTE_UNUSED)
7214 if (s390_function_arg_float (mode, type))
7218 else if (s390_function_arg_integer (mode, type))
7220 int size = s390_function_arg_size (mode, type);
7221 cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
7227 /* Define where to put the arguments to a function.
7228 Value is zero to push the argument on the stack,
7229 or a hard register in which to store the argument.
7231 MODE is the argument's machine mode.
7232 TYPE is the data type of the argument (as a tree).
7233 This is null for libcalls where that information may
7235 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7236 the preceding args and about the function being called.
7237 NAMED is nonzero if this argument is a named parameter
7238 (otherwise it is an extra parameter matching an ellipsis).
7240 On S/390, we use general purpose registers 2 through 6 to
7241 pass integer, pointer, and certain structure arguments, and
7242 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
7243 to pass floating point arguments. All remaining arguments
7244 are pushed to the stack. */
7247 s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
7248 int named ATTRIBUTE_UNUSED)
7250 if (s390_function_arg_float (mode, type))
7252 if (cum->fprs + 1 > FP_ARG_NUM_REG)
7255 return gen_rtx_REG (mode, cum->fprs + 16);
7257 else if (s390_function_arg_integer (mode, type))
7259 int size = s390_function_arg_size (mode, type);
7260 int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
7262 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
7265 return gen_rtx_REG (mode, cum->gprs + 2);
7268 /* After the real arguments, expand_call calls us once again
7269 with a void_type_node type. Whatever we return here is
7270 passed as operand 2 to the call expanders.
7272 We don't need this feature ... */
7273 else if (type == void_type_node)
7279 /* Return true if return values of type TYPE should be returned
7280 in a memory buffer whose address is passed by the caller as
7281 hidden first argument. */
7284 s390_return_in_memory (tree type, tree fundecl ATTRIBUTE_UNUSED)
7286 /* We accept small integral (and similar) types. */
7287 if (INTEGRAL_TYPE_P (type)
7288 || POINTER_TYPE_P (type)
7289 || TREE_CODE (type) == OFFSET_TYPE
7290 || TREE_CODE (type) == REAL_TYPE)
7291 return int_size_in_bytes (type) > 8;
7293 /* Aggregates and similar constructs are always returned
7295 if (AGGREGATE_TYPE_P (type)
7296 || TREE_CODE (type) == COMPLEX_TYPE
7297 || TREE_CODE (type) == VECTOR_TYPE)
7300 /* ??? We get called on all sorts of random stuff from
7301 aggregate_value_p. We can't abort, but it's not clear
7302 what's safe to return. Pretend it's a struct I guess. */
7306 /* Define where to return a (scalar) value of type TYPE.
7307 If TYPE is null, define where to return a (scalar)
7308 value of mode MODE from a libcall. */
7311 s390_function_value (tree type, enum machine_mode mode)
7315 int unsignedp = TYPE_UNSIGNED (type);
7316 mode = promote_mode (type, TYPE_MODE (type), &unsignedp, 1);
7319 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT
7320 || GET_MODE_CLASS (mode) == MODE_FLOAT);
7321 gcc_assert (GET_MODE_SIZE (mode) <= 8);
7323 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
7324 return gen_rtx_REG (mode, 16);
7326 return gen_rtx_REG (mode, 2);
7330 /* Create and return the va_list datatype.
7332 On S/390, va_list is an array type equivalent to
7334 typedef struct __va_list_tag
7338 void *__overflow_arg_area;
7339 void *__reg_save_area;
7342 where __gpr and __fpr hold the number of general purpose
7343 or floating point arguments used up to now, respectively,
7344 __overflow_arg_area points to the stack location of the
7345 next argument passed on the stack, and __reg_save_area
7346 always points to the start of the register area in the
7347 call frame of the current function. The function prologue
7348 saves all registers used for argument passing into this
7349 area if the function uses variable arguments. */
7352 s390_build_builtin_va_list (void)
7354 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
7356 record = lang_hooks.types.make_type (RECORD_TYPE);
7359 build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
7361 f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"),
7362 long_integer_type_node);
7363 f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"),
7364 long_integer_type_node);
7365 f_ovf = build_decl (FIELD_DECL, get_identifier ("__overflow_arg_area"),
7367 f_sav = build_decl (FIELD_DECL, get_identifier ("__reg_save_area"),
7370 va_list_gpr_counter_field = f_gpr;
7371 va_list_fpr_counter_field = f_fpr;
7373 DECL_FIELD_CONTEXT (f_gpr) = record;
7374 DECL_FIELD_CONTEXT (f_fpr) = record;
7375 DECL_FIELD_CONTEXT (f_ovf) = record;
7376 DECL_FIELD_CONTEXT (f_sav) = record;
7378 TREE_CHAIN (record) = type_decl;
7379 TYPE_NAME (record) = type_decl;
7380 TYPE_FIELDS (record) = f_gpr;
7381 TREE_CHAIN (f_gpr) = f_fpr;
7382 TREE_CHAIN (f_fpr) = f_ovf;
7383 TREE_CHAIN (f_ovf) = f_sav;
7385 layout_type (record);
7387 /* The correct type is an array type of one element. */
7388 return build_array_type (record, build_index_type (size_zero_node));
7391 /* Implement va_start by filling the va_list structure VALIST.
7392 STDARG_P is always true, and ignored.
7393 NEXTARG points to the first anonymous stack argument.
7395 The following global variables are used to initialize
7396 the va_list structure:
7398 current_function_args_info:
7399 holds number of gprs and fprs used for named arguments.
7400 current_function_arg_offset_rtx:
7401 holds the offset of the first anonymous stack argument
7402 (relative to the virtual arg pointer). */
7405 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
7407 HOST_WIDE_INT n_gpr, n_fpr;
7409 tree f_gpr, f_fpr, f_ovf, f_sav;
7410 tree gpr, fpr, ovf, sav, t;
7412 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7413 f_fpr = TREE_CHAIN (f_gpr);
7414 f_ovf = TREE_CHAIN (f_fpr);
7415 f_sav = TREE_CHAIN (f_ovf);
7417 valist = build_va_arg_indirect_ref (valist);
7418 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7419 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7420 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7421 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7423 /* Count number of gp and fp argument registers used. */
7425 n_gpr = current_function_args_info.gprs;
7426 n_fpr = current_function_args_info.fprs;
7428 if (cfun->va_list_gpr_size)
7430 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
7431 build_int_cst (NULL_TREE, n_gpr));
7432 TREE_SIDE_EFFECTS (t) = 1;
7433 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7436 if (cfun->va_list_fpr_size)
7438 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
7439 build_int_cst (NULL_TREE, n_fpr));
7440 TREE_SIDE_EFFECTS (t) = 1;
7441 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7444 /* Find the overflow area. */
7445 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
7446 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
7448 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
7450 off = INTVAL (current_function_arg_offset_rtx);
7451 off = off < 0 ? 0 : off;
7452 if (TARGET_DEBUG_ARG)
7453 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
7454 (int)n_gpr, (int)n_fpr, off);
7456 t = build (PLUS_EXPR, TREE_TYPE (ovf), t, build_int_cst (NULL_TREE, off));
7458 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
7459 TREE_SIDE_EFFECTS (t) = 1;
7460 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7463 /* Find the register save area. */
7464 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
7465 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
7467 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
7468 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
7469 build_int_cst (NULL_TREE, -RETURN_REGNUM * UNITS_PER_WORD));
7471 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
7472 TREE_SIDE_EFFECTS (t) = 1;
7473 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7477 /* Implement va_arg by updating the va_list structure
7478 VALIST as required to retrieve an argument of type
7479 TYPE, and returning that argument.
7481 Generates code equivalent to:
7483 if (integral value) {
7484 if (size <= 4 && args.gpr < 5 ||
7485 size > 4 && args.gpr < 4 )
7486 ret = args.reg_save_area[args.gpr+8]
7488 ret = *args.overflow_arg_area++;
7489 } else if (float value) {
7491 ret = args.reg_save_area[args.fpr+64]
7493 ret = *args.overflow_arg_area++;
7494 } else if (aggregate value) {
7496 ret = *args.reg_save_area[args.gpr]
7498 ret = **args.overflow_arg_area++;
7502 s390_gimplify_va_arg (tree valist, tree type, tree *pre_p,
7503 tree *post_p ATTRIBUTE_UNUSED)
7505 tree f_gpr, f_fpr, f_ovf, f_sav;
7506 tree gpr, fpr, ovf, sav, reg, t, u;
7507 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
7508 tree lab_false, lab_over, addr;
7510 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
7511 f_fpr = TREE_CHAIN (f_gpr);
7512 f_ovf = TREE_CHAIN (f_fpr);
7513 f_sav = TREE_CHAIN (f_ovf);
7515 valist = build_va_arg_indirect_ref (valist);
7516 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
7517 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7518 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7519 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7521 size = int_size_in_bytes (type);
7523 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
7525 if (TARGET_DEBUG_ARG)
7527 fprintf (stderr, "va_arg: aggregate type");
7531 /* Aggregates are passed by reference. */
7536 /* kernel stack layout on 31 bit: It is assumed here that no padding
7537 will be added by s390_frame_info because for va_args always an even
7538 number of gprs has to be saved r15-r2 = 14 regs. */
7539 sav_ofs = 2 * UNITS_PER_WORD;
7540 sav_scale = UNITS_PER_WORD;
7541 size = UNITS_PER_WORD;
7542 max_reg = GP_ARG_NUM_REG - n_reg;
7544 else if (s390_function_arg_float (TYPE_MODE (type), type))
7546 if (TARGET_DEBUG_ARG)
7548 fprintf (stderr, "va_arg: float type");
7552 /* FP args go in FP registers, if present. */
7556 sav_ofs = 16 * UNITS_PER_WORD;
7558 max_reg = FP_ARG_NUM_REG - n_reg;
7562 if (TARGET_DEBUG_ARG)
7564 fprintf (stderr, "va_arg: other type");
7568 /* Otherwise into GP registers. */
7571 n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7573 /* kernel stack layout on 31 bit: It is assumed here that no padding
7574 will be added by s390_frame_info because for va_args always an even
7575 number of gprs has to be saved r15-r2 = 14 regs. */
7576 sav_ofs = 2 * UNITS_PER_WORD;
7578 if (size < UNITS_PER_WORD)
7579 sav_ofs += UNITS_PER_WORD - size;
7581 sav_scale = UNITS_PER_WORD;
7582 max_reg = GP_ARG_NUM_REG - n_reg;
7585 /* Pull the value out of the saved registers ... */
7587 lab_false = create_artificial_label ();
7588 lab_over = create_artificial_label ();
7589 addr = create_tmp_var (ptr_type_node, "addr");
7590 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
7592 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
7593 t = build2 (GT_EXPR, boolean_type_node, reg, t);
7594 u = build1 (GOTO_EXPR, void_type_node, lab_false);
7595 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
7596 gimplify_and_add (t, pre_p);
7598 t = build2 (PLUS_EXPR, ptr_type_node, sav,
7599 fold_convert (ptr_type_node, size_int (sav_ofs)));
7600 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
7601 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
7602 t = build2 (PLUS_EXPR, ptr_type_node, t, fold_convert (ptr_type_node, u));
7604 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
7605 gimplify_and_add (t, pre_p);
7607 t = build1 (GOTO_EXPR, void_type_node, lab_over);
7608 gimplify_and_add (t, pre_p);
7610 t = build1 (LABEL_EXPR, void_type_node, lab_false);
7611 append_to_statement_list (t, pre_p);
7614 /* ... Otherwise out of the overflow area. */
7617 if (size < UNITS_PER_WORD)
7618 t = build2 (PLUS_EXPR, ptr_type_node, t,
7619 fold_convert (ptr_type_node, size_int (UNITS_PER_WORD - size)));
7621 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
7623 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
7624 gimplify_and_add (u, pre_p);
7626 t = build2 (PLUS_EXPR, ptr_type_node, t,
7627 fold_convert (ptr_type_node, size_int (size)));
7628 t = build2 (MODIFY_EXPR, ptr_type_node, ovf, t);
7629 gimplify_and_add (t, pre_p);
7631 t = build1 (LABEL_EXPR, void_type_node, lab_over);
7632 append_to_statement_list (t, pre_p);
7635 /* Increment register save count. */
7637 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
7638 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
7639 gimplify_and_add (u, pre_p);
7643 t = build_pointer_type (build_pointer_type (type));
7644 addr = fold_convert (t, addr);
7645 addr = build_va_arg_indirect_ref (addr);
7649 t = build_pointer_type (type);
7650 addr = fold_convert (t, addr);
7653 return build_va_arg_indirect_ref (addr);
7661 S390_BUILTIN_THREAD_POINTER,
7662 S390_BUILTIN_SET_THREAD_POINTER,
7667 static unsigned int const code_for_builtin_64[S390_BUILTIN_max] = {
7672 static unsigned int const code_for_builtin_31[S390_BUILTIN_max] = {
7678 s390_init_builtins (void)
7682 ftype = build_function_type (ptr_type_node, void_list_node);
7683 lang_hooks.builtin_function ("__builtin_thread_pointer", ftype,
7684 S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
7687 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
7688 lang_hooks.builtin_function ("__builtin_set_thread_pointer", ftype,
7689 S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
7693 /* Expand an expression EXP that calls a built-in function,
7694 with result going to TARGET if that's convenient
7695 (and in mode MODE if that's convenient).
7696 SUBTARGET may be used as the target for computing one of EXP's operands.
7697 IGNORE is nonzero if the value is to be ignored. */
7700 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7701 enum machine_mode mode ATTRIBUTE_UNUSED,
7702 int ignore ATTRIBUTE_UNUSED)
7706 unsigned int const *code_for_builtin =
7707 TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
7709 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7710 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7711 tree arglist = TREE_OPERAND (exp, 1);
7712 enum insn_code icode;
7713 rtx op[MAX_ARGS], pat;
7717 if (fcode >= S390_BUILTIN_max)
7718 internal_error ("bad builtin fcode");
7719 icode = code_for_builtin[fcode];
7721 internal_error ("bad builtin fcode");
7723 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
7725 for (arglist = TREE_OPERAND (exp, 1), arity = 0;
7727 arglist = TREE_CHAIN (arglist), arity++)
7729 const struct insn_operand_data *insn_op;
7731 tree arg = TREE_VALUE (arglist);
7732 if (arg == error_mark_node)
7734 if (arity > MAX_ARGS)
7737 insn_op = &insn_data[icode].operand[arity + nonvoid];
7739 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
7741 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
7742 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
7747 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7749 || GET_MODE (target) != tmode
7750 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
7751 target = gen_reg_rtx (tmode);
7757 pat = GEN_FCN (icode) (target);
7761 pat = GEN_FCN (icode) (target, op[0]);
7763 pat = GEN_FCN (icode) (op[0]);
7766 pat = GEN_FCN (icode) (target, op[0], op[1]);
7782 /* Output assembly code for the trampoline template to
7785 On S/390, we use gpr 1 internally in the trampoline code;
7786 gpr 0 is used to hold the static chain. */
7789 s390_trampoline_template (FILE *file)
7792 op[0] = gen_rtx_REG (Pmode, 0);
7793 op[1] = gen_rtx_REG (Pmode, 1);
7797 output_asm_insn ("basr\t%1,0", op);
7798 output_asm_insn ("lmg\t%0,%1,14(%1)", op);
7799 output_asm_insn ("br\t%1", op);
7800 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
7804 output_asm_insn ("basr\t%1,0", op);
7805 output_asm_insn ("lm\t%0,%1,6(%1)", op);
7806 output_asm_insn ("br\t%1", op);
7807 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
7811 /* Emit RTL insns to initialize the variable parts of a trampoline.
7812 FNADDR is an RTX for the address of the function's pure code.
7813 CXT is an RTX for the static chain value for the function. */
7816 s390_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
7818 emit_move_insn (gen_rtx_MEM (Pmode,
7819 memory_address (Pmode,
7820 plus_constant (addr, (TARGET_64BIT ? 16 : 8)))), cxt);
7821 emit_move_insn (gen_rtx_MEM (Pmode,
7822 memory_address (Pmode,
7823 plus_constant (addr, (TARGET_64BIT ? 24 : 12)))), fnaddr);
7826 /* Return rtx for 64-bit constant formed from the 32-bit subwords
7827 LOW and HIGH, independent of the host word size. */
7830 s390_gen_rtx_const_DI (int high, int low)
7832 #if HOST_BITS_PER_WIDE_INT >= 64
7834 val = (HOST_WIDE_INT)high;
7836 val |= (HOST_WIDE_INT)low;
7838 return GEN_INT (val);
7840 #if HOST_BITS_PER_WIDE_INT >= 32
7841 return immed_double_const ((HOST_WIDE_INT)low, (HOST_WIDE_INT)high, DImode);
7848 /* Output assembler code to FILE to increment profiler label # LABELNO
7849 for profiling a function entry. */
7852 s390_function_profiler (FILE *file, int labelno)
7857 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
7859 fprintf (file, "# function profiler \n");
7861 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
7862 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
7863 op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
7865 op[2] = gen_rtx_REG (Pmode, 1);
7866 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
7867 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
7869 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
7872 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
7873 op[4] = gen_rtx_CONST (Pmode, op[4]);
7878 output_asm_insn ("stg\t%0,%1", op);
7879 output_asm_insn ("larl\t%2,%3", op);
7880 output_asm_insn ("brasl\t%0,%4", op);
7881 output_asm_insn ("lg\t%0,%1", op);
7885 op[6] = gen_label_rtx ();
7887 output_asm_insn ("st\t%0,%1", op);
7888 output_asm_insn ("bras\t%2,%l6", op);
7889 output_asm_insn (".long\t%4", op);
7890 output_asm_insn (".long\t%3", op);
7891 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
7892 output_asm_insn ("l\t%0,0(%2)", op);
7893 output_asm_insn ("l\t%2,4(%2)", op);
7894 output_asm_insn ("basr\t%0,%0", op);
7895 output_asm_insn ("l\t%0,%1", op);
7899 op[5] = gen_label_rtx ();
7900 op[6] = gen_label_rtx ();
7902 output_asm_insn ("st\t%0,%1", op);
7903 output_asm_insn ("bras\t%2,%l6", op);
7904 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
7905 output_asm_insn (".long\t%4-%l5", op);
7906 output_asm_insn (".long\t%3-%l5", op);
7907 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
7908 output_asm_insn ("lr\t%0,%2", op);
7909 output_asm_insn ("a\t%0,0(%2)", op);
7910 output_asm_insn ("a\t%2,4(%2)", op);
7911 output_asm_insn ("basr\t%0,%0", op);
7912 output_asm_insn ("l\t%0,%1", op);
7916 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
7917 into its SYMBOL_REF_FLAGS. */
7920 s390_encode_section_info (tree decl, rtx rtl, int first)
7922 default_encode_section_info (decl, rtl, first);
7924 /* If a variable has a forced alignment to < 2 bytes, mark it with
7925 SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL operand. */
7926 if (TREE_CODE (decl) == VAR_DECL
7927 && DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
7928 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
7931 /* Output thunk to FILE that implements a C++ virtual function call (with
7932 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
7933 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
7934 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
7935 relative to the resulting this pointer. */
7938 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
7939 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7945 /* Operand 0 is the target function. */
7946 op[0] = XEXP (DECL_RTL (function), 0);
7947 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
7950 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
7951 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
7952 op[0] = gen_rtx_CONST (Pmode, op[0]);
7955 /* Operand 1 is the 'this' pointer. */
7956 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7957 op[1] = gen_rtx_REG (Pmode, 3);
7959 op[1] = gen_rtx_REG (Pmode, 2);
7961 /* Operand 2 is the delta. */
7962 op[2] = GEN_INT (delta);
7964 /* Operand 3 is the vcall_offset. */
7965 op[3] = GEN_INT (vcall_offset);
7967 /* Operand 4 is the temporary register. */
7968 op[4] = gen_rtx_REG (Pmode, 1);
7970 /* Operands 5 to 8 can be used as labels. */
7976 /* Operand 9 can be used for temporary register. */
7979 /* Generate code. */
7982 /* Setup literal pool pointer if required. */
7983 if ((!DISP_IN_RANGE (delta)
7984 && !CONST_OK_FOR_K (delta)
7985 && !CONST_OK_FOR_Os (delta))
7986 || (!DISP_IN_RANGE (vcall_offset)
7987 && !CONST_OK_FOR_K (vcall_offset)
7988 && !CONST_OK_FOR_Os (vcall_offset)))
7990 op[5] = gen_label_rtx ();
7991 output_asm_insn ("larl\t%4,%5", op);
7994 /* Add DELTA to this pointer. */
7997 if (CONST_OK_FOR_J (delta))
7998 output_asm_insn ("la\t%1,%2(%1)", op);
7999 else if (DISP_IN_RANGE (delta))
8000 output_asm_insn ("lay\t%1,%2(%1)", op);
8001 else if (CONST_OK_FOR_K (delta))
8002 output_asm_insn ("aghi\t%1,%2", op);
8003 else if (CONST_OK_FOR_Os (delta))
8004 output_asm_insn ("agfi\t%1,%2", op);
8007 op[6] = gen_label_rtx ();
8008 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
8012 /* Perform vcall adjustment. */
8015 if (DISP_IN_RANGE (vcall_offset))
8017 output_asm_insn ("lg\t%4,0(%1)", op);
8018 output_asm_insn ("ag\t%1,%3(%4)", op);
8020 else if (CONST_OK_FOR_K (vcall_offset))
8022 output_asm_insn ("lghi\t%4,%3", op);
8023 output_asm_insn ("ag\t%4,0(%1)", op);
8024 output_asm_insn ("ag\t%1,0(%4)", op);
8026 else if (CONST_OK_FOR_Os (vcall_offset))
8028 output_asm_insn ("lgfi\t%4,%3", op);
8029 output_asm_insn ("ag\t%4,0(%1)", op);
8030 output_asm_insn ("ag\t%1,0(%4)", op);
8034 op[7] = gen_label_rtx ();
8035 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
8036 output_asm_insn ("ag\t%4,0(%1)", op);
8037 output_asm_insn ("ag\t%1,0(%4)", op);
8041 /* Jump to target. */
8042 output_asm_insn ("jg\t%0", op);
8044 /* Output literal pool if required. */
8047 output_asm_insn (".align\t4", op);
8048 targetm.asm_out.internal_label (file, "L",
8049 CODE_LABEL_NUMBER (op[5]));
8053 targetm.asm_out.internal_label (file, "L",
8054 CODE_LABEL_NUMBER (op[6]));
8055 output_asm_insn (".long\t%2", op);
8059 targetm.asm_out.internal_label (file, "L",
8060 CODE_LABEL_NUMBER (op[7]));
8061 output_asm_insn (".long\t%3", op);
8066 /* Setup base pointer if required. */
8068 || (!DISP_IN_RANGE (delta)
8069 && !CONST_OK_FOR_K (delta)
8070 && !CONST_OK_FOR_Os (delta))
8071 || (!DISP_IN_RANGE (delta)
8072 && !CONST_OK_FOR_K (vcall_offset)
8073 && !CONST_OK_FOR_Os (vcall_offset)))
8075 op[5] = gen_label_rtx ();
8076 output_asm_insn ("basr\t%4,0", op);
8077 targetm.asm_out.internal_label (file, "L",
8078 CODE_LABEL_NUMBER (op[5]));
8081 /* Add DELTA to this pointer. */
8084 if (CONST_OK_FOR_J (delta))
8085 output_asm_insn ("la\t%1,%2(%1)", op);
8086 else if (DISP_IN_RANGE (delta))
8087 output_asm_insn ("lay\t%1,%2(%1)", op);
8088 else if (CONST_OK_FOR_K (delta))
8089 output_asm_insn ("ahi\t%1,%2", op);
8090 else if (CONST_OK_FOR_Os (delta))
8091 output_asm_insn ("afi\t%1,%2", op);
8094 op[6] = gen_label_rtx ();
8095 output_asm_insn ("a\t%1,%6-%5(%4)", op);
8099 /* Perform vcall adjustment. */
8102 if (CONST_OK_FOR_J (vcall_offset))
8104 output_asm_insn ("l\t%4,0(%1)", op);
8105 output_asm_insn ("a\t%1,%3(%4)", op);
8107 else if (DISP_IN_RANGE (vcall_offset))
8109 output_asm_insn ("l\t%4,0(%1)", op);
8110 output_asm_insn ("ay\t%1,%3(%4)", op);
8112 else if (CONST_OK_FOR_K (vcall_offset))
8114 output_asm_insn ("lhi\t%4,%3", op);
8115 output_asm_insn ("a\t%4,0(%1)", op);
8116 output_asm_insn ("a\t%1,0(%4)", op);
8118 else if (CONST_OK_FOR_Os (vcall_offset))
8120 output_asm_insn ("iilf\t%4,%3", op);
8121 output_asm_insn ("a\t%4,0(%1)", op);
8122 output_asm_insn ("a\t%1,0(%4)", op);
8126 op[7] = gen_label_rtx ();
8127 output_asm_insn ("l\t%4,%7-%5(%4)", op);
8128 output_asm_insn ("a\t%4,0(%1)", op);
8129 output_asm_insn ("a\t%1,0(%4)", op);
8132 /* We had to clobber the base pointer register.
8133 Re-setup the base pointer (with a different base). */
8134 op[5] = gen_label_rtx ();
8135 output_asm_insn ("basr\t%4,0", op);
8136 targetm.asm_out.internal_label (file, "L",
8137 CODE_LABEL_NUMBER (op[5]));
8140 /* Jump to target. */
8141 op[8] = gen_label_rtx ();
8144 output_asm_insn ("l\t%4,%8-%5(%4)", op);
8146 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8147 /* We cannot call through .plt, since .plt requires %r12 loaded. */
8148 else if (flag_pic == 1)
8150 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8151 output_asm_insn ("l\t%4,%0(%4)", op);
8153 else if (flag_pic == 2)
8155 op[9] = gen_rtx_REG (Pmode, 0);
8156 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
8157 output_asm_insn ("a\t%4,%8-%5(%4)", op);
8158 output_asm_insn ("ar\t%4,%9", op);
8159 output_asm_insn ("l\t%4,0(%4)", op);
8162 output_asm_insn ("br\t%4", op);
8164 /* Output literal pool. */
8165 output_asm_insn (".align\t4", op);
8167 if (nonlocal && flag_pic == 2)
8168 output_asm_insn (".long\t%0", op);
8171 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8172 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
8175 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
8177 output_asm_insn (".long\t%0", op);
8179 output_asm_insn (".long\t%0-%5", op);
8183 targetm.asm_out.internal_label (file, "L",
8184 CODE_LABEL_NUMBER (op[6]));
8185 output_asm_insn (".long\t%2", op);
8189 targetm.asm_out.internal_label (file, "L",
8190 CODE_LABEL_NUMBER (op[7]));
8191 output_asm_insn (".long\t%3", op);
8197 s390_valid_pointer_mode (enum machine_mode mode)
8199 return (mode == SImode || (TARGET_64BIT && mode == DImode));
8202 /* Checks whether the given ARGUMENT_LIST would use a caller
8203 saved register. This is used to decide whether sibling call
8204 optimization could be performed on the respective function
8208 s390_call_saved_register_used (tree argument_list)
8210 CUMULATIVE_ARGS cum;
8212 enum machine_mode mode;
8217 INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0);
8219 while (argument_list)
8221 parameter = TREE_VALUE (argument_list);
8222 argument_list = TREE_CHAIN (argument_list);
8224 gcc_assert (parameter);
8226 /* For an undeclared variable passed as parameter we will get
8227 an ERROR_MARK node here. */
8228 if (TREE_CODE (parameter) == ERROR_MARK)
8231 type = TREE_TYPE (parameter);
8234 mode = TYPE_MODE (type);
8237 if (pass_by_reference (&cum, mode, type, true))
8240 type = build_pointer_type (type);
8243 parm_rtx = s390_function_arg (&cum, mode, type, 0);
8245 s390_function_arg_advance (&cum, mode, type, 0);
8247 if (parm_rtx && REG_P (parm_rtx))
8250 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
8252 if (! call_used_regs[reg + REGNO (parm_rtx)])
8259 /* Return true if the given call expression can be
8260 turned into a sibling call.
8261 DECL holds the declaration of the function to be called whereas
8262 EXP is the call expression itself. */
8265 s390_function_ok_for_sibcall (tree decl, tree exp)
8267 /* The TPF epilogue uses register 1. */
8268 if (TARGET_TPF_PROFILING)
8271 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
8272 which would have to be restored before the sibcall. */
8273 if (!TARGET_64BIT && flag_pic && decl && TREE_PUBLIC (decl))
8276 /* Register 6 on s390 is available as an argument register but unfortunately
8277 "caller saved". This makes functions needing this register for arguments
8278 not suitable for sibcalls. */
8279 if (TREE_OPERAND (exp, 1)
8280 && s390_call_saved_register_used (TREE_OPERAND (exp, 1)))
8286 /* Return the fixed registers used for condition codes. */
8289 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
8292 *p2 = INVALID_REGNUM;
8297 /* This function is used by the call expanders of the machine description.
8298 It emits the call insn itself together with the necessary operations
8299 to adjust the target address and returns the emitted insn.
8300 ADDR_LOCATION is the target address rtx
8301 TLS_CALL the location of the thread-local symbol
8302 RESULT_REG the register where the result of the call should be stored
8303 RETADDR_REG the register where the return address should be stored
8304 If this parameter is NULL_RTX the call is considered
8305 to be a sibling call. */
8308 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
8311 bool plt_call = false;
8317 /* Direct function calls need special treatment. */
8318 if (GET_CODE (addr_location) == SYMBOL_REF)
8320 /* When calling a global routine in PIC mode, we must
8321 replace the symbol itself with the PLT stub. */
8322 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
8324 addr_location = gen_rtx_UNSPEC (Pmode,
8325 gen_rtvec (1, addr_location),
8327 addr_location = gen_rtx_CONST (Pmode, addr_location);
8331 /* Unless we can use the bras(l) insn, force the
8332 routine address into a register. */
8333 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
8336 addr_location = legitimize_pic_address (addr_location, 0);
8338 addr_location = force_reg (Pmode, addr_location);
8342 /* If it is already an indirect call or the code above moved the
8343 SYMBOL_REF to somewhere else make sure the address can be found in
8345 if (retaddr_reg == NULL_RTX
8346 && GET_CODE (addr_location) != SYMBOL_REF
8349 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
8350 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
8353 addr_location = gen_rtx_MEM (QImode, addr_location);
8354 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
8356 if (result_reg != NULL_RTX)
8357 call = gen_rtx_SET (VOIDmode, result_reg, call);
8359 if (retaddr_reg != NULL_RTX)
8361 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
8363 if (tls_call != NULL_RTX)
8364 vec = gen_rtvec (3, call, clobber,
8365 gen_rtx_USE (VOIDmode, tls_call));
8367 vec = gen_rtvec (2, call, clobber);
8369 call = gen_rtx_PARALLEL (VOIDmode, vec);
8372 insn = emit_call_insn (call);
8374 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
8375 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
8377 /* s390_function_ok_for_sibcall should
8378 have denied sibcalls in this case. */
8379 gcc_assert (retaddr_reg != NULL_RTX);
8381 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
8386 /* Implement CONDITIONAL_REGISTER_USAGE. */
8389 s390_conditional_register_usage (void)
8395 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8396 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8398 if (TARGET_CPU_ZARCH)
8400 fixed_regs[BASE_REGNUM] = 0;
8401 call_used_regs[BASE_REGNUM] = 0;
8402 fixed_regs[RETURN_REGNUM] = 0;
8403 call_used_regs[RETURN_REGNUM] = 0;
8407 for (i = 24; i < 32; i++)
8408 call_used_regs[i] = call_really_used_regs[i] = 0;
8412 for (i = 18; i < 20; i++)
8413 call_used_regs[i] = call_really_used_regs[i] = 0;
8416 if (TARGET_SOFT_FLOAT)
8418 for (i = 16; i < 32; i++)
8419 call_used_regs[i] = fixed_regs[i] = 1;
8423 /* Corresponding function to eh_return expander. */
8425 static GTY(()) rtx s390_tpf_eh_return_symbol;
8427 s390_emit_tpf_eh_return (rtx target)
8431 if (!s390_tpf_eh_return_symbol)
8432 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
8434 reg = gen_rtx_REG (Pmode, 2);
8436 emit_move_insn (reg, target);
8437 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
8438 gen_rtx_REG (Pmode, RETURN_REGNUM));
8439 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
8441 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
8444 /* Rework the prologue/epilogue to avoid saving/restoring
8445 registers unnecessarily. */
8448 s390_optimize_prologue (void)
8450 rtx insn, new_insn, next_insn;
8452 /* Do a final recompute of the frame-related data. */
8454 s390_update_frame_layout ();
8456 /* If all special registers are in fact used, there's nothing we
8457 can do, so no point in walking the insn list. */
8459 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
8460 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
8461 && (TARGET_CPU_ZARCH
8462 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
8463 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
8466 /* Search for prologue/epilogue insns and replace them. */
8468 for (insn = get_insns (); insn; insn = next_insn)
8470 int first, last, off;
8471 rtx set, base, offset;
8473 next_insn = NEXT_INSN (insn);
8475 if (GET_CODE (insn) != INSN)
8478 if (GET_CODE (PATTERN (insn)) == PARALLEL
8479 && store_multiple_operation (PATTERN (insn), VOIDmode))
8481 set = XVECEXP (PATTERN (insn), 0, 0);
8482 first = REGNO (SET_SRC (set));
8483 last = first + XVECLEN (PATTERN (insn), 0) - 1;
8484 offset = const0_rtx;
8485 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8486 off = INTVAL (offset);
8488 if (GET_CODE (base) != REG || off < 0)
8490 if (cfun_frame_layout.first_save_gpr != -1
8491 && (cfun_frame_layout.first_save_gpr < first
8492 || cfun_frame_layout.last_save_gpr > last))
8494 if (REGNO (base) != STACK_POINTER_REGNUM
8495 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8497 if (first > BASE_REGNUM || last < BASE_REGNUM)
8500 if (cfun_frame_layout.first_save_gpr != -1)
8502 new_insn = save_gprs (base,
8503 off + (cfun_frame_layout.first_save_gpr
8504 - first) * UNITS_PER_WORD,
8505 cfun_frame_layout.first_save_gpr,
8506 cfun_frame_layout.last_save_gpr);
8507 new_insn = emit_insn_before (new_insn, insn);
8508 INSN_ADDRESSES_NEW (new_insn, -1);
8515 if (cfun_frame_layout.first_save_gpr == -1
8516 && GET_CODE (PATTERN (insn)) == SET
8517 && GET_CODE (SET_SRC (PATTERN (insn))) == REG
8518 && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM
8519 || (!TARGET_CPU_ZARCH
8520 && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM))
8521 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
8523 set = PATTERN (insn);
8524 first = REGNO (SET_SRC (set));
8525 offset = const0_rtx;
8526 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8527 off = INTVAL (offset);
8529 if (GET_CODE (base) != REG || off < 0)
8531 if (REGNO (base) != STACK_POINTER_REGNUM
8532 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8539 if (GET_CODE (PATTERN (insn)) == PARALLEL
8540 && load_multiple_operation (PATTERN (insn), VOIDmode))
8542 set = XVECEXP (PATTERN (insn), 0, 0);
8543 first = REGNO (SET_DEST (set));
8544 last = first + XVECLEN (PATTERN (insn), 0) - 1;
8545 offset = const0_rtx;
8546 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
8547 off = INTVAL (offset);
8549 if (GET_CODE (base) != REG || off < 0)
8551 if (cfun_frame_layout.first_restore_gpr != -1
8552 && (cfun_frame_layout.first_restore_gpr < first
8553 || cfun_frame_layout.last_restore_gpr > last))
8555 if (REGNO (base) != STACK_POINTER_REGNUM
8556 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8558 if (first > BASE_REGNUM || last < BASE_REGNUM)
8561 if (cfun_frame_layout.first_restore_gpr != -1)
8563 new_insn = restore_gprs (base,
8564 off + (cfun_frame_layout.first_restore_gpr
8565 - first) * UNITS_PER_WORD,
8566 cfun_frame_layout.first_restore_gpr,
8567 cfun_frame_layout.last_restore_gpr);
8568 new_insn = emit_insn_before (new_insn, insn);
8569 INSN_ADDRESSES_NEW (new_insn, -1);
8576 if (cfun_frame_layout.first_restore_gpr == -1
8577 && GET_CODE (PATTERN (insn)) == SET
8578 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
8579 && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM
8580 || (!TARGET_CPU_ZARCH
8581 && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM))
8582 && GET_CODE (SET_SRC (PATTERN (insn))) == MEM)
8584 set = PATTERN (insn);
8585 first = REGNO (SET_DEST (set));
8586 offset = const0_rtx;
8587 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
8588 off = INTVAL (offset);
8590 if (GET_CODE (base) != REG || off < 0)
8592 if (REGNO (base) != STACK_POINTER_REGNUM
8593 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
8602 /* Perform machine-dependent processing. */
8607 bool pool_overflow = false;
8609 /* Make sure all splits have been performed; splits after
8610 machine_dependent_reorg might confuse insn length counts. */
8611 split_all_insns_noflow ();
8614 /* Install the main literal pool and the associated base
8615 register load insns.
8617 In addition, there are two problematic situations we need
8620 - the literal pool might be > 4096 bytes in size, so that
8621 some of its elements cannot be directly accessed
8623 - a branch target might be > 64K away from the branch, so that
8624 it is not possible to use a PC-relative instruction.
8626 To fix those, we split the single literal pool into multiple
8627 pool chunks, reloading the pool base register at various
8628 points throughout the function to ensure it always points to
8629 the pool chunk the following code expects, and / or replace
8630 PC-relative branches by absolute branches.
8632 However, the two problems are interdependent: splitting the
8633 literal pool can move a branch further away from its target,
8634 causing the 64K limit to overflow, and on the other hand,
8635 replacing a PC-relative branch by an absolute branch means
8636 we need to put the branch target address into the literal
8637 pool, possibly causing it to overflow.
8639 So, we loop trying to fix up both problems until we manage
8640 to satisfy both conditions at the same time. Note that the
8641 loop is guaranteed to terminate as every pass of the loop
8642 strictly decreases the total number of PC-relative branches
8643 in the function. (This is not completely true as there
8644 might be branch-over-pool insns introduced by chunkify_start.
8645 Those never need to be split however.) */
8649 struct constant_pool *pool = NULL;
8651 /* Collect the literal pool. */
8654 pool = s390_mainpool_start ();
8656 pool_overflow = true;
8659 /* If literal pool overflowed, start to chunkify it. */
8661 pool = s390_chunkify_start ();
8663 /* Split out-of-range branches. If this has created new
8664 literal pool entries, cancel current chunk list and
8665 recompute it. zSeries machines have large branch
8666 instructions, so we never need to split a branch. */
8667 if (!TARGET_CPU_ZARCH && s390_split_branches ())
8670 s390_chunkify_cancel (pool);
8672 s390_mainpool_cancel (pool);
8677 /* If we made it up to here, both conditions are satisfied.
8678 Finish up literal pool related changes. */
8680 s390_chunkify_finish (pool);
8682 s390_mainpool_finish (pool);
8684 /* We're done splitting branches. */
8685 cfun->machine->split_branches_pending_p = false;
8689 /* Generate out-of-pool execute target insns. */
8690 if (TARGET_CPU_ZARCH)
8692 rtx insn, label, target;
8694 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8696 label = s390_execute_label (insn);
8700 gcc_assert (label != const0_rtx);
8702 target = emit_label (XEXP (label, 0));
8703 INSN_ADDRESSES_NEW (target, -1);
8705 target = emit_insn (s390_execute_target (insn));
8706 INSN_ADDRESSES_NEW (target, -1);
8710 /* Try to optimize prologue and epilogue further. */
8711 s390_optimize_prologue ();
8715 /* Initialize GCC target structure. */
8717 #undef TARGET_ASM_ALIGNED_HI_OP
8718 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
8719 #undef TARGET_ASM_ALIGNED_DI_OP
8720 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
8721 #undef TARGET_ASM_INTEGER
8722 #define TARGET_ASM_INTEGER s390_assemble_integer
8724 #undef TARGET_ASM_OPEN_PAREN
8725 #define TARGET_ASM_OPEN_PAREN ""
8727 #undef TARGET_ASM_CLOSE_PAREN
8728 #define TARGET_ASM_CLOSE_PAREN ""
8730 #undef TARGET_DEFAULT_TARGET_FLAGS
8731 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
8732 #undef TARGET_HANDLE_OPTION
8733 #define TARGET_HANDLE_OPTION s390_handle_option
8735 #undef TARGET_ENCODE_SECTION_INFO
8736 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
8739 #undef TARGET_HAVE_TLS
8740 #define TARGET_HAVE_TLS true
8742 #undef TARGET_CANNOT_FORCE_CONST_MEM
8743 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
8745 #undef TARGET_DELEGITIMIZE_ADDRESS
8746 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
8748 #undef TARGET_RETURN_IN_MEMORY
8749 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
8751 #undef TARGET_INIT_BUILTINS
8752 #define TARGET_INIT_BUILTINS s390_init_builtins
8753 #undef TARGET_EXPAND_BUILTIN
8754 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
8756 #undef TARGET_ASM_OUTPUT_MI_THUNK
8757 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
8758 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
8759 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
8761 #undef TARGET_SCHED_ADJUST_PRIORITY
8762 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
8763 #undef TARGET_SCHED_ISSUE_RATE
8764 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
8765 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
8766 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
8768 #undef TARGET_CANNOT_COPY_INSN_P
8769 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
8770 #undef TARGET_RTX_COSTS
8771 #define TARGET_RTX_COSTS s390_rtx_costs
8772 #undef TARGET_ADDRESS_COST
8773 #define TARGET_ADDRESS_COST s390_address_cost
8775 #undef TARGET_MACHINE_DEPENDENT_REORG
8776 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
8778 #undef TARGET_VALID_POINTER_MODE
8779 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
8781 #undef TARGET_BUILD_BUILTIN_VA_LIST
8782 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
8783 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
8784 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
8786 #undef TARGET_PROMOTE_FUNCTION_ARGS
8787 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
8788 #undef TARGET_PROMOTE_FUNCTION_RETURN
8789 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
8790 #undef TARGET_PASS_BY_REFERENCE
8791 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
8793 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
8794 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
8796 #undef TARGET_FIXED_CONDITION_CODE_REGS
8797 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
8799 #undef TARGET_CC_MODES_COMPATIBLE
8800 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
8802 #undef TARGET_INVALID_WITHIN_DOLOOP
8803 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_rtx_null
8806 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
8807 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
8810 struct gcc_target targetm = TARGET_INITIALIZER;
8812 #include "gt-s390.h"