1 ;; Machine Description for Renesas RX processors
2 ;; Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
3 ;; Contributed by Red Hat.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
22 ;; This code iterator is used for sign- and zero- extensions.
23 (define_mode_iterator small_int_modes [(HI "") (QI "")])
25 ;; We do not handle DFmode here because it is either
26 ;; the same as SFmode, or if -m64bit-doubles is active
27 ;; then all operations on doubles have to be handled by
29 (define_mode_iterator register_modes
30 [(SF "ALLOW_RX_FPU_INSNS") (SI "") (HI "") (QI "")])
33 ;; Used to map RX condition names to GCC
34 ;; condition names for builtin instructions.
35 (define_code_iterator gcc_conds [eq ne gt ge lt le gtu geu ltu leu
37 (define_code_attr rx_conds [(eq "eq") (ne "ne") (gt "gt") (ge "ge") (lt "lt")
38 (le "le") (gtu "gtu") (geu "geu") (ltu "ltu")
39 (leu "leu") (unge "pz") (unlt "n") (uneq "o")
60 (UNSPEC_BUILTIN_BRK 30)
61 (UNSPEC_BUILTIN_CLRPSW 31)
62 (UNSPEC_BUILTIN_INT 32)
63 (UNSPEC_BUILTIN_MACHI 33)
64 (UNSPEC_BUILTIN_MACLO 34)
65 (UNSPEC_BUILTIN_MULHI 35)
66 (UNSPEC_BUILTIN_MULLO 36)
67 (UNSPEC_BUILTIN_MVFACHI 37)
68 (UNSPEC_BUILTIN_MVFACMI 38)
69 (UNSPEC_BUILTIN_MVFC 39)
70 (UNSPEC_BUILTIN_MVFCP 40)
71 (UNSPEC_BUILTIN_MVTACHI 41)
72 (UNSPEC_BUILTIN_MVTACLO 42)
73 (UNSPEC_BUILTIN_MVTC 43)
74 (UNSPEC_BUILTIN_MVTIPL 44)
75 (UNSPEC_BUILTIN_RACW 45)
76 (UNSPEC_BUILTIN_REVW 46)
77 (UNSPEC_BUILTIN_RMPA 47)
78 (UNSPEC_BUILTIN_ROUND 48)
79 (UNSPEC_BUILTIN_SAT 49)
80 (UNSPEC_BUILTIN_SETPSW 50)
81 (UNSPEC_BUILTIN_WAIT 51)
85 (define_attr "length" "" (const_int 8))
87 (include "predicates.md")
88 (include "constraints.md")
90 ;; Pipeline description.
92 ;; The RX only has a single pipeline. It has five stages (fetch,
93 ;; decode, execute, memory access, writeback) each of which normally
94 ;; takes a single CPU clock cycle.
96 ;; The timings attribute consists of two numbers, the first is the
97 ;; throughput, which is the number of cycles the instruction takes
98 ;; to execute and generate a result. The second is the latency
99 ;; which is the effective number of cycles the instruction takes to
100 ;; execute if its result is used by the following instruction. The
101 ;; latency is always greater than or equal to the throughput.
102 ;; These values were taken from tables 2.13 and 2.14 in section 2.8
103 ;; of the RX610 Group Hardware Manual v0.11
105 ;; Note - it would be nice to use strings rather than integers for
106 ;; the possible values of this attribute, so that we can have the
107 ;; gcc build mechanism check for values that are not supported by
108 ;; the reservations below. But this will not work because the code
109 ;; in rx_adjust_sched_cost() needs integers not strings.
111 (define_attr "timings" "" (const_int 11))
113 (define_automaton "pipelining")
114 (define_cpu_unit "throughput" "pipelining")
116 (define_insn_reservation "throughput__1_latency__1" 1
117 (eq_attr "timings" "11") "throughput")
118 (define_insn_reservation "throughput__1_latency__2" 2
119 (eq_attr "timings" "12") "throughput,nothing")
120 (define_insn_reservation "throughput__2_latency__2" 1
121 (eq_attr "timings" "22") "throughput*2")
122 (define_insn_reservation "throughput__3_latency__3" 1
123 (eq_attr "timings" "33") "throughput*3")
124 (define_insn_reservation "throughput__3_latency__4" 2
125 (eq_attr "timings" "34") "throughput*3,nothing")
126 (define_insn_reservation "throughput__4_latency__4" 1
127 (eq_attr "timings" "44") "throughput*4")
128 (define_insn_reservation "throughput__4_latency__5" 2
129 (eq_attr "timings" "45") "throughput*4,nothing")
130 (define_insn_reservation "throughput__5_latency__5" 1
131 (eq_attr "timings" "55") "throughput*5")
132 (define_insn_reservation "throughput__5_latency__6" 2
133 (eq_attr "timings" "56") "throughput*5,nothing")
134 (define_insn_reservation "throughput__6_latency__6" 1
135 (eq_attr "timings" "66") "throughput*6")
136 (define_insn_reservation "throughput_10_latency_10" 1
137 (eq_attr "timings" "1010") "throughput*10")
138 (define_insn_reservation "throughput_11_latency_11" 1
139 (eq_attr "timings" "1111") "throughput*11")
140 (define_insn_reservation "throughput_16_latency_16" 1
141 (eq_attr "timings" "1616") "throughput*16")
142 (define_insn_reservation "throughput_18_latency_18" 1
143 (eq_attr "timings" "1818") "throughput*18")
145 ;; ----------------------------------------------------------------------------
149 ;; Note - we do not specify the two instructions necessary to perform
150 ;; a compare-and-branch in the cbranchsi4 pattern because that would
151 ;; allow the comparison to be moved away from the jump before the reload
152 ;; pass has completed. That would be problematical because reload can
153 ;; generate ADDSI3 instructions which would corrupt the PSW flags.
155 (define_expand "cbranchsi4"
158 (match_operator 0 "comparison_operator"
159 [(match_operand:SI 1 "register_operand")
160 (match_operand:SI 2 "rx_source_operand")])
161 (label_ref (match_operand 3 ""))
166 (define_insn_and_split "*cbranchsi4"
169 (match_operator 3 "comparison_operator"
170 [(match_operand:SI 0 "register_operand" "r")
171 (match_operand:SI 1 "rx_source_operand" "riQ")])
172 (match_operand 2 "label_ref_operand" "")
179 rx_split_cbranch (CCmode, GET_CODE (operands[3]),
180 operands[0], operands[1], operands[2]);
184 (define_insn "*cmpsi"
185 [(set (reg:CC CC_REG)
186 (compare:CC (match_operand:SI 0 "register_operand" "r,r,r,r,r,r,r")
187 (match_operand:SI 1 "rx_source_operand" "r,Uint04,Int08,Sint16,Sint24,i,Q")))]
190 [(set_attr "timings" "11,11,11,11,11,11,33")
191 (set_attr "length" "2,2,3,4,5,6,5")]
194 ;; Canonical method for representing TST.
195 (define_insn_and_split "*cbranchsi4_tst"
198 (match_operator 3 "rx_zs_comparison_operator"
199 [(and:SI (match_operand:SI 0 "register_operand" "r")
200 (match_operand:SI 1 "rx_source_operand" "riQ"))
202 (match_operand 2 "label_ref_operand" "")
209 rx_split_cbranch (CC_ZSmode, GET_CODE (operands[3]),
210 XEXP (operands[3], 0), XEXP (operands[3], 1),
215 ;; Various other ways that GCC codes "var & const"
216 (define_insn_and_split "*cbranchsi4_tst_ext"
219 (match_operator 4 "rx_z_comparison_operator"
221 (match_operand:SI 0 "register_operand" "r")
222 (match_operand:SI 1 "rx_constshift_operand" "")
223 (match_operand:SI 2 "rx_constshift_operand" ""))
225 (match_operand 3 "label_ref_operand" "")
236 mask <<= INTVAL (operands[1]);
238 mask <<= INTVAL (operands[2]);
239 x = gen_rtx_AND (SImode, operands[0], gen_int_mode (mask, SImode));
241 rx_split_cbranch (CC_ZSmode, GET_CODE (operands[4]),
242 x, const0_rtx, operands[3]);
246 (define_insn "*tstsi"
247 [(set (reg:CC_ZS CC_REG)
249 (and:SI (match_operand:SI 0 "register_operand" "r,r,r")
250 (match_operand:SI 1 "rx_source_operand" "r,i,Q"))
254 [(set_attr "timings" "11,11,33")
255 (set_attr "length" "3,7,6")]
258 (define_expand "cbranchsf4"
261 (match_operator 0 "comparison_operator"
262 [(match_operand:SF 1 "register_operand")
263 (match_operand:SF 2 "register_operand")])
264 (label_ref (match_operand 3 ""))
268 enum rtx_code cmp1, cmp2;
270 /* If the comparison needs swapping of operands, do that now.
271 Do not split the comparison in two yet. */
272 if (rx_split_fp_compare (GET_CODE (operands[0]), &cmp1, &cmp2))
278 gcc_assert (cmp1 == UNORDERED);
289 operands[0] = gen_rtx_fmt_ee (cmp1, VOIDmode, op1, op2);
295 (define_insn_and_split "*cbranchsf4"
298 (match_operator 3 "rx_fp_comparison_operator"
299 [(match_operand:SF 0 "register_operand" "r")
300 (match_operand:SF 1 "rx_source_operand" "rFiQ")])
301 (match_operand 2 "label_ref_operand" "")
305 "&& reload_completed"
308 enum rtx_code cmp0, cmp1, cmp2;
309 rtx flags, lab1, lab2, over, x;
312 cmp0 = GET_CODE (operands[3]);
313 swap = rx_split_fp_compare (cmp0, &cmp1, &cmp2);
316 flags = gen_rtx_REG (CC_Fmode, CC_REG);
317 x = gen_rtx_COMPARE (CC_Fmode, operands[0], operands[1]);
318 x = gen_rtx_SET (VOIDmode, flags, x);
322 lab1 = lab2 = operands[2];
324 /* The one case of LTGT needs to be split into cmp1 && cmp2. */
327 over = gen_label_rtx ();
328 lab1 = gen_rtx_LABEL_REF (VOIDmode, over);
329 cmp1 = reverse_condition_maybe_unordered (cmp1);
332 /* Otherwise we split into cmp1 || cmp2. */
333 x = gen_rtx_fmt_ee (cmp1, VOIDmode, flags, const0_rtx);
334 x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, lab1, pc_rtx);
335 x = gen_rtx_SET (VOIDmode, pc_rtx, x);
340 x = gen_rtx_fmt_ee (cmp2, VOIDmode, flags, const0_rtx);
341 x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, lab2, pc_rtx);
342 x = gen_rtx_SET (VOIDmode, pc_rtx, x);
351 (define_insn "*cmpsf"
352 [(set (reg:CC_F CC_REG)
354 (match_operand:SF 0 "register_operand" "r,r,r")
355 (match_operand:SF 1 "rx_source_operand" "r,iF,Q")))]
356 "ALLOW_RX_FPU_INSNS && reload_completed"
358 [(set_attr "timings" "11,11,33")
359 (set_attr "length" "3,7,5")]
362 ;; Flow Control Instructions:
364 (define_insn "*conditional_branch"
367 (match_operator 1 "comparison_operator"
368 [(reg CC_REG) (const_int 0)])
369 (label_ref (match_operand 0 "" ""))
373 [(set_attr "length" "8") ;; This length is wrong, but it is
374 ;; too hard to compute statically.
375 (set_attr "timings" "33")] ;; The timing assumes that the branch is taken.
378 ;; ----------------------------------------------------------------------------
382 (label_ref (match_operand 0 "" "")))]
385 [(set_attr "length" "4")
386 (set_attr "timings" "33")]
389 (define_insn "indirect_jump"
391 (match_operand:SI 0 "register_operand" "r"))]
394 [(set_attr "length" "2")
395 (set_attr "timings" "33")]
398 (define_insn "tablejump"
400 (match_operand:SI 0 "register_operand" "r"))
401 (use (label_ref (match_operand 1 "" "")))]
403 { return flag_pic ? (TARGET_AS100_SYNTAX ? "\n?:\tbra\t%0"
407 [(set_attr "timings" "33")
408 (set_attr "length" "2")]
411 (define_insn "simple_return"
415 [(set_attr "length" "1")
416 (set_attr "timings" "55")]
419 (define_insn "deallocate_and_return"
420 [(set (reg:SI SP_REG)
421 (plus:SI (reg:SI SP_REG)
422 (match_operand:SI 0 "immediate_operand" "i")))
426 [(set_attr "length" "2")
427 (set_attr "timings" "55")]
430 (define_insn "pop_and_return"
431 [(match_parallel 1 "rx_rtsd_vector"
432 [(set:SI (reg:SI SP_REG)
433 (plus:SI (reg:SI SP_REG)
434 (match_operand:SI 0 "const_int_operand" "n")))])]
437 rx_emit_stack_popm (operands, false);
440 [(set_attr "length" "3")
441 (set_attr "timings" "56")]
444 (define_insn "fast_interrupt_return"
445 [(unspec_volatile [(return)] UNSPEC_RTFI) ]
448 [(set_attr "length" "2")
449 (set_attr "timings" "33")]
452 (define_insn "exception_return"
453 [(unspec_volatile [(return)] UNSPEC_RTE) ]
456 [(set_attr "length" "2")
457 (set_attr "timings" "66")]
460 (define_insn "naked_return"
461 [(unspec_volatile [(return)] UNSPEC_NAKED) ]
463 "; Naked function: epilogue provided by programmer."
467 ;; Note - the following set of patterns do not use the "memory_operand"
468 ;; predicate or an "m" constraint because we do not allow symbol_refs
469 ;; or label_refs as legitmate memory addresses. This matches the
470 ;; behaviour of most of the RX instructions. Only the call/branch
471 ;; instructions are allowed to refer to symbols/labels directly.
472 ;; The call operands are in QImode because that is the value of
475 (define_expand "call"
476 [(call (match_operand:QI 0 "general_operand")
477 (match_operand:SI 1 "general_operand"))]
480 rtx dest = XEXP (operands[0], 0);
482 if (! rx_call_operand (dest, Pmode))
483 dest = force_reg (Pmode, dest);
484 emit_call_insn (gen_call_internal (dest, operands[1]));
489 (define_insn "call_internal"
490 [(call (mem:QI (match_operand:SI 0 "rx_call_operand" "r,Symbol"))
491 (match_operand:SI 1 "general_operand" "g,g"))
492 (clobber (reg:CC CC_REG))]
497 [(set_attr "length" "2,4")
498 (set_attr "timings" "33")]
501 (define_expand "call_value"
502 [(set (match_operand 0 "register_operand")
503 (call (match_operand:QI 1 "general_operand")
504 (match_operand:SI 2 "general_operand")))]
507 rtx dest = XEXP (operands[1], 0);
509 if (! rx_call_operand (dest, Pmode))
510 dest = force_reg (Pmode, dest);
511 emit_call_insn (gen_call_value_internal (operands[0], dest, operands[2]));
516 (define_insn "call_value_internal"
517 [(set (match_operand 0 "register_operand" "=r,r")
518 (call (mem:QI (match_operand:SI 1 "rx_call_operand" "r,Symbol"))
519 (match_operand:SI 2 "general_operand" "g,g")))
520 (clobber (reg:CC CC_REG))]
525 [(set_attr "length" "2,4")
526 (set_attr "timings" "33")]
529 ;; Note - we do not allow indirect sibcalls (with the address
530 ;; held in a register) because we cannot guarantee that the register
531 ;; chosen will be a call-used one. If it is a call-saved register,
532 ;; then the epilogue code will corrupt it by popping the saved value
534 (define_expand "sibcall"
536 [(call (mem:QI (match_operand:SI 0 "rx_symbolic_call_operand"))
537 (match_operand:SI 1 "general_operand"))
541 if (MEM_P (operands[0]))
542 operands[0] = XEXP (operands[0], 0);
546 (define_insn "sibcall_internal"
547 [(call (mem:QI (match_operand:SI 0 "rx_symbolic_call_operand" "Symbol"))
548 (match_operand:SI 1 "general_operand" "g"))
552 [(set_attr "length" "4")
553 (set_attr "timings" "33")]
556 (define_expand "sibcall_value"
558 [(set (match_operand 0 "register_operand")
559 (call (mem:QI (match_operand:SI 1 "rx_symbolic_call_operand"))
560 (match_operand:SI 2 "general_operand")))
564 if (MEM_P (operands[1]))
565 operands[1] = XEXP (operands[1], 0);
569 (define_insn "sibcall_value_internal"
570 [(set (match_operand 0 "register_operand" "=r")
571 (call (mem:QI (match_operand:SI 1 "rx_symbolic_call_operand" "Symbol"))
572 (match_operand:SI 2 "general_operand" "g")))
576 [(set_attr "length" "4")
577 (set_attr "timings" "33")]
580 ;; Function Prologue/Epilogue Instructions
582 (define_expand "prologue"
585 "rx_expand_prologue (); DONE;"
588 (define_expand "epilogue"
591 "rx_expand_epilogue (false); DONE;"
594 (define_expand "sibcall_epilogue"
597 "rx_expand_epilogue (true); DONE;"
602 ;; Note - we do not allow memory to memory moves, even though the ISA
603 ;; supports them. The reason is that the conditions on such moves are
604 ;; too restrictive, specifically the source addressing mode is limited
605 ;; by the destination addressing mode and vice versa. (For example it
606 ;; is not possible to use indexed register indirect addressing for one
607 ;; of the operands if the other operand is anything other than a register,
608 ;; but it is possible to use register relative addressing when the other
609 ;; operand also uses register relative or register indirect addressing).
611 ;; GCC does not support computing legitimate addresses based on the
612 ;; nature of other operands involved in the instruction, and reload is
613 ;; not smart enough to cope with a whole variety of different memory
614 ;; addressing constraints, so it is simpler and safer to just refuse
615 ;; to support memory to memory moves.
617 (define_expand "mov<register_modes:mode>"
618 [(set (match_operand:register_modes 0 "general_operand")
619 (match_operand:register_modes 1 "general_operand"))]
622 if (MEM_P (operand0) && MEM_P (operand1))
623 operands[1] = copy_to_mode_reg (<register_modes:MODE>mode, operand1);
627 (define_insn "*mov<register_modes:mode>_internal"
628 [(set (match_operand:register_modes
629 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,Q,Q,Q,Q")
630 (match_operand:register_modes
631 1 "general_operand" "Int08,Sint16,Sint24,i,r,m,r,Int08,Sint16,Sint24,i"))]
633 { return rx_gen_move_template (operands, false); }
634 [(set_attr "length" "3,4,5,6,2,4,6,5,6,7,8")
635 (set_attr "timings" "11,11,11,11,11,12,11,11,11,11,11")]
638 (define_insn "extend<small_int_modes:mode>si2"
639 [(set (match_operand:SI 0 "register_operand" "=r,r")
640 (sign_extend:SI (match_operand:small_int_modes
641 1 "nonimmediate_operand" "r,m")))]
643 { return rx_gen_move_template (operands, false); }
644 [(set_attr "length" "2,6")
645 (set_attr "timings" "11,12")]
648 (define_insn "zero_extend<small_int_modes:mode>si2"
649 [(set (match_operand:SI 0 "register_operand" "=r,r")
650 (zero_extend:SI (match_operand:small_int_modes
651 1 "nonimmediate_operand" "r,m")))]
653 { return rx_gen_move_template (operands, true); }
654 [(set_attr "length" "2,4")
655 (set_attr "timings" "11,12")]
658 (define_insn "stack_push"
659 [(set:SI (reg:SI SP_REG)
660 (minus:SI (reg:SI SP_REG)
662 (set:SI (mem:SI (reg:SI SP_REG))
663 (match_operand:SI 0 "register_operand" "r"))]
666 [(set_attr "length" "2")]
669 (define_insn "stack_pushm"
670 [(match_parallel 1 "rx_store_multiple_vector"
671 [(set:SI (reg:SI SP_REG)
672 (minus:SI (reg:SI SP_REG)
673 (match_operand:SI 0 "const_int_operand" "n")))])]
676 rx_emit_stack_pushm (operands);
679 [(set_attr "length" "2")
680 (set_attr "timings" "44")] ;; The timing is a guesstimate average timing.
683 (define_insn "stack_pop"
684 [(set:SI (match_operand:SI 0 "register_operand" "=r")
685 (mem:SI (reg:SI SP_REG)))
686 (set:SI (reg:SI SP_REG)
687 (plus:SI (reg:SI SP_REG)
691 [(set_attr "length" "2")
692 (set_attr "timings" "12")]
695 (define_insn "stack_popm"
696 [(match_parallel 1 "rx_load_multiple_vector"
697 [(set:SI (reg:SI SP_REG)
698 (plus:SI (reg:SI SP_REG)
699 (match_operand:SI 0 "const_int_operand" "n")))])]
702 rx_emit_stack_popm (operands, true);
705 [(set_attr "length" "2")
706 (set_attr "timings" "45")] ;; The timing is a guesstimate average timing.
709 (define_insn_and_split "cstoresi4"
710 [(set (match_operand:SI 0 "register_operand" "=r")
711 (match_operator:SI 1 "comparison_operator"
712 [(match_operand:SI 2 "register_operand" "r")
713 (match_operand:SI 3 "rx_source_operand" "riQ")]))
714 (clobber (reg:CC CC_REG))]
722 flags = gen_rtx_REG (CCmode, CC_REG);
723 x = gen_rtx_COMPARE (CCmode, operands[2], operands[3]);
724 x = gen_rtx_SET (VOIDmode, flags, x);
727 x = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, flags, const0_rtx);
728 x = gen_rtx_SET (VOIDmode, operands[0], x);
734 [(set (match_operand:SI 0 "register_operand" "=r")
735 (match_operator:SI 1 "comparison_operator"
736 [(reg CC_REG) (const_int 0)]))]
739 [(set_attr "length" "3")]
742 (define_expand "cstoresf4"
743 [(parallel [(set (match_operand:SI 0 "register_operand" "")
744 (match_operator:SI 1 "comparison_operator"
745 [(match_operand:SF 2 "register_operand" "")
746 (match_operand:SF 3 "register_operand" "")]))
747 (clobber (match_scratch:SI 4))])]
750 enum rtx_code cmp1, cmp2;
752 /* If the comparison needs swapping of operands, do that now.
753 Do not split the comparison in two yet. */
754 if (rx_split_fp_compare (GET_CODE (operands[0]), &cmp1, &cmp2))
760 gcc_assert (cmp1 == UNORDERED);
771 operands[0] = gen_rtx_fmt_ee (cmp1, VOIDmode, op2, op3);
777 (define_insn_and_split "*cstoresf4"
778 [(set (match_operand:SI 0 "register_operand" "=r")
779 (match_operator:SI 4 "rx_fp_comparison_operator"
780 [(match_operand:SF 2 "register_operand" "r")
781 (match_operand:SF 3 "rx_source_operand" "rFiQ")]))
782 (clobber (match_scratch:SI 1 "=r"))]
788 enum rtx_code cmp0, cmp1, cmp2;
792 cmp0 = GET_CODE (operands[4]);
793 swap = rx_split_fp_compare (cmp0, &cmp1, &cmp2);
796 flags = gen_rtx_REG (CC_Fmode, CC_REG);
797 x = gen_rtx_COMPARE (CC_Fmode, operands[2], operands[3]);
798 x = gen_rtx_SET (VOIDmode, flags, x);
801 x = gen_rtx_fmt_ee (cmp1, SImode, flags, const0_rtx);
802 x = gen_rtx_SET (VOIDmode, operands[0], x);
807 /* The one case of LTGT needs to be split into ORDERED && NE. */
808 x = gen_rtx_fmt_ee (EQ, VOIDmode, flags, const0_rtx);
809 x = gen_rtx_IF_THEN_ELSE (SImode, x, const0_rtx, operands[0]);
810 x = gen_rtx_SET (VOIDmode, operands[0], x);
813 else if (cmp2 == EQ || cmp2 == NE)
815 /* Oring the two flags can be performed with a movcc operation. */
816 x = gen_rtx_fmt_ee (cmp2, VOIDmode, flags, const0_rtx);
817 x = gen_rtx_IF_THEN_ELSE (SImode, x, const1_rtx, operands[0]);
818 x = gen_rtx_SET (VOIDmode, operands[0], x);
821 else if (cmp2 != UNKNOWN)
823 /* We can't use movcc, but need to or in another compare.
824 Do this by storing the second operation into the scratch. */
825 x = gen_rtx_fmt_ee (cmp2, SImode, flags, const0_rtx);
826 x = gen_rtx_SET (VOIDmode, operands[1], x);
829 emit_insn (gen_iorsi3 (operands[0], operands[0], operands[1]));
834 (define_expand "movsicc"
836 [(set (match_operand:SI 0 "register_operand")
837 (if_then_else:SI (match_operand:SI 1 "comparison_operator")
838 (match_operand:SI 2 "nonmemory_operand")
839 (match_operand:SI 3 "nonmemory_operand")))
840 (clobber (reg:CC CC_REG))])]
843 /* ??? Support other conditions via cstore into a temporary? */
844 if (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE)
846 /* One operand must be a constant. */
847 if (!CONSTANT_P (operands[2]) && !CONSTANT_P (operands[3]))
851 (define_insn_and_split "*movsicc"
852 [(set (match_operand:SI 0 "register_operand" "=r,r")
854 (match_operator 5 "rx_z_comparison_operator"
855 [(match_operand:SI 3 "register_operand" "r,r")
856 (match_operand:SI 4 "rx_source_operand" "riQ,riQ")])
857 (match_operand:SI 1 "nonmemory_operand" "i,ri")
858 (match_operand:SI 2 "nonmemory_operand" "ri,i")))
859 (clobber (reg:CC CC_REG))]
860 "CONSTANT_P (operands[1]) || CONSTANT_P (operands[2])"
862 "&& reload_completed"
865 rtx x, flags, op0, op1, op2;
866 enum rtx_code cmp_code;
868 flags = gen_rtx_REG (CCmode, CC_REG);
869 x = gen_rtx_COMPARE (CCmode, operands[3], operands[4]);
870 emit_insn (gen_rtx_SET (VOIDmode, flags, x));
872 cmp_code = GET_CODE (operands[5]);
877 /* If OP2 is the constant, reverse the sense of the move. */
878 if (!CONSTANT_P (operands[1]))
880 x = op1, op1 = op2, op2 = x;
881 cmp_code = reverse_condition (cmp_code);
884 /* If OP2 does not match the output, copy it into place. We have allowed
885 these alternatives so that the destination can legitimately be one of
886 the comparison operands without increasing register pressure. */
887 if (!rtx_equal_p (op0, op2))
888 emit_move_insn (op0, op2);
890 x = gen_rtx_fmt_ee (cmp_code, VOIDmode, flags, const0_rtx);
891 x = gen_rtx_IF_THEN_ELSE (SImode, x, op1, op0);
892 emit_insn (gen_rtx_SET (VOIDmode, op0, x));
897 [(set (match_operand:SI 0 "register_operand" "+r,r,r,r")
899 (match_operator 2 "rx_z_comparison_operator"
900 [(reg CC_REG) (const_int 0)])
901 (match_operand:SI 1 "immediate_operand" "Sint08,Sint16,Sint24,i")
905 if (GET_CODE (operands[2]) == EQ)
906 return "stz\t%1, %0";
908 return "stnz\t%1, %0";
910 [(set_attr "length" "4,5,6,7")]
913 ;; Arithmetic Instructions
915 (define_insn "abssi2"
916 [(set (match_operand:SI 0 "register_operand" "=r,r")
917 (abs:SI (match_operand:SI 1 "register_operand" "0,r")))
918 (set (reg:CC_ZSO CC_REG)
919 (compare:CC_ZSO (abs:SI (match_dup 1))
925 [(set_attr "length" "2,3")]
928 (define_insn "addsi3"
929 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r,r,r,r,r,r")
930 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r,r,r,r,r,0")
931 (match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q")))
932 (set (reg:CC_ZSC CC_REG) ;; See subsi3
933 (compare:CC_ZSC (plus:SI (match_dup 1) (match_dup 2))
951 [(set_attr "timings" "11,11,11,11,11,11,11,11,11,11,11,11,11,33")
952 (set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")]
955 (define_insn "adddi3"
956 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r")
957 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,0,0")
958 (match_operand:DI 2 "rx_source_operand"
959 "r,Sint08,Sint16,Sint24,i,Q")))
960 (set (reg:CC_ZSC CC_REG) ;; See subsi3
961 (compare:CC_ZSC (plus:DI (match_dup 1) (match_dup 2))
964 "add\t%L2, %L0\n\tadc\t%H2, %H0"
965 [(set_attr "timings" "22,22,22,22,22,44")
966 (set_attr "length" "5,7,9,11,13,11")]
969 (define_insn "andsi3"
970 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
971 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
972 (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
973 (set (reg:CC_ZS CC_REG)
974 (compare:CC_ZS (and:SI (match_dup 1) (match_dup 2))
987 [(set_attr "timings" "11,11,11,11,11,11,11,33,33")
988 (set_attr "length" "2,2,3,4,5,6,2,5,5")]
991 ;; Byte swap (single 32-bit value).
992 (define_insn "bswapsi2"
993 [(set (match_operand:SI 0 "register_operand" "+r")
994 (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
997 [(set_attr "length" "3")]
1000 ;; Byte swap (single 16-bit value). Note - we ignore the swapping of the high 16-bits.
1001 (define_insn "bswaphi2"
1002 [(set (match_operand:HI 0 "register_operand" "+r")
1003 (bswap:HI (match_operand:HI 1 "register_operand" "r")))]
1006 [(set_attr "length" "3")]
1009 (define_insn "divsi3"
1010 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1011 (div:SI (match_operand:SI 1 "register_operand" "0,0,0,0,0,0")
1012 (match_operand:SI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q")))
1013 (clobber (reg:CC CC_REG))]
1016 [(set_attr "timings" "1111") ;; Strictly speaking the timing should be
1017 ;; 2222, but that is a worst case sceanario.
1018 (set_attr "length" "3,4,5,6,7,6")]
1021 (define_insn "udivsi3"
1022 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1023 (udiv:SI (match_operand:SI 1 "register_operand" "0,0,0,0,0,0")
1024 (match_operand:SI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q")))
1025 (clobber (reg:CC CC_REG))]
1028 [(set_attr "timings" "1010") ;; Strictly speaking the timing should be
1029 ;; 2020, but that is a worst case sceanario.
1030 (set_attr "length" "3,4,5,6,7,6")]
1033 ;; Note - these patterns are suppressed in big-endian mode because they
1034 ;; generate a little endian result. ie the most significant word of the
1035 ;; result is placed in the higher numbered register of the destination
1038 (define_insn "mulsidi3"
1039 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r")
1040 (mult:DI (sign_extend:DI (match_operand:SI
1041 1 "register_operand" "%0,0,0,0,0,0"))
1042 (sign_extend:DI (match_operand:SI
1043 2 "rx_source_operand"
1044 "r,Sint08,Sint16,Sint24,i,Q"))))]
1045 "! TARGET_BIG_ENDIAN_DATA"
1047 [(set_attr "length" "3,4,5,6,7,6")
1048 (set_attr "timings" "22,22,22,22,22,44")]
1051 ;; See comment for mulsidi3.
1052 ;; Note - the zero_extends are to distinguish this pattern from the
1053 ;; mulsidi3 pattern. Immediate mode addressing is not supported
1054 ;; because gcc cannot handle the expression: (zero_extend (const_int)).
1055 (define_insn "umulsidi3"
1056 [(set (match_operand:DI 0 "register_operand" "=r,r")
1057 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,0"))
1058 (zero_extend:DI (match_operand:SI 2 "rx_compare_operand" "r,Q"))))]
1059 "! TARGET_BIG_ENDIAN_DATA"
1061 [(set_attr "length" "3,6")
1062 (set_attr "timings" "22,44")]
1065 (define_insn "smaxsi3"
1066 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1067 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
1068 (match_operand:SI 2 "rx_source_operand"
1069 "r,Sint08,Sint16,Sint24,i,Q")))]
1072 [(set_attr "length" "3,4,5,6,7,6")
1073 (set_attr "timings" "11,11,11,11,11,33")]
1076 (define_insn "sminsi3"
1077 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1078 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
1079 (match_operand:SI 2 "rx_source_operand"
1080 "r,Sint08,Sint16,Sint24,i,Q")))]
1083 [(set_attr "length" "3,4,5,6,7,6")
1084 (set_attr "timings" "11,11,11,11,11,33")]
1087 (define_insn "mulsi3"
1088 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
1089 (mult:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r")
1090 (match_operand:SI 2 "rx_source_operand"
1091 "r,Uint04,Sint08,Sint16,Sint24,i,Q,0,r")))]
1103 [(set_attr "length" "2,2,3,4,5,6,5,2,3")
1104 (set_attr "timings" "11,11,11,11,11,11,33,11,11")]
1107 (define_insn "negsi2"
1108 [(set (match_operand:SI 0 "register_operand" "=r,r")
1109 (neg:SI (match_operand:SI 1 "register_operand" "0,r")))
1110 (set (reg:CC CC_REG)
1111 (compare:CC (neg:SI (match_dup 1))
1113 ;; The NEG instruction does not comply with -fwrapv semantics.
1114 ;; See gcc.c-torture/execute/pr22493-1.c for an example of this.
1119 [(set_attr "length" "2,3")]
1122 (define_insn "one_cmplsi2"
1123 [(set (match_operand:SI 0 "register_operand" "=r,r")
1124 (not:SI (match_operand:SI 1 "register_operand" "0,r")))
1125 (set (reg:CC_ZS CC_REG)
1126 (compare:CC_ZS (not:SI (match_dup 1))
1132 [(set_attr "length" "2,3")]
1135 (define_insn "iorsi3"
1136 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
1137 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
1138 (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
1139 (set (reg:CC_ZS CC_REG)
1140 (compare:CC_ZS (ior:SI (match_dup 1) (match_dup 2))
1153 [(set_attr "timings" "11,11,11,11,11,11,11,11,33")
1154 (set_attr "length" "2,2,3,4,5,6,2,3,5")]
1157 (define_insn "rotlsi3"
1158 [(set (match_operand:SI 0 "register_operand" "=r")
1159 (rotate:SI (match_operand:SI 1 "register_operand" "0")
1160 (match_operand:SI 2 "rx_shift_operand" "rn")))
1161 (set (reg:CC_ZS CC_REG)
1162 (compare:CC_ZS (rotate:SI (match_dup 1) (match_dup 2))
1166 [(set_attr "length" "3")]
1169 (define_insn "rotrsi3"
1170 [(set (match_operand:SI 0 "register_operand" "=r")
1171 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
1172 (match_operand:SI 2 "rx_shift_operand" "rn")))
1173 (set (reg:CC_ZS CC_REG)
1174 (compare:CC_ZS (rotatert:SI (match_dup 1) (match_dup 2))
1178 [(set_attr "length" "3")]
1181 (define_insn "ashrsi3"
1182 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1183 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
1184 (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
1185 (set (reg:CC_ZS CC_REG)
1186 (compare:CC_ZS (ashiftrt:SI (match_dup 1) (match_dup 2))
1193 [(set_attr "length" "3,2,3")]
1196 (define_insn "lshrsi3"
1197 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1198 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
1199 (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
1200 (set (reg:CC_ZS CC_REG)
1201 (compare:CC_ZS (lshiftrt:SI (match_dup 1) (match_dup 2))
1208 [(set_attr "length" "3,2,3")]
1211 (define_insn "ashlsi3"
1212 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1213 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
1214 (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
1215 (set (reg:CC_ZS CC_REG)
1216 (compare:CC_ZS (ashift:SI (match_dup 1) (match_dup 2))
1223 [(set_attr "length" "3,2,3")]
1226 (define_insn "subsi3"
1227 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
1228 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0")
1229 (match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q")))
1230 (set (reg:CC_ZSC CC_REG)
1231 ;; Note - we do not acknowledge that the SUB instruction sets the Overflow
1232 ;; flag because its interpretation is different from comparing the result
1233 ;; against zero. Compile and run gcc.c-torture/execute/cmpsi-1.c to see this.
1234 (compare:CC_ZSC (minus:SI (match_dup 1) (match_dup 2))
1243 [(set_attr "timings" "11,11,11,11,33")
1244 (set_attr "length" "2,2,6,3,5")]
1247 (define_insn "subdi3"
1248 [(set (match_operand:DI 0 "register_operand" "=r,r")
1249 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
1250 (match_operand:DI 2 "rx_source_operand" "r,Q")))
1251 (set (reg:CC_ZSC CC_REG) ;; See subsi3
1252 (compare:CC_ZSC (minus:DI (match_dup 1) (match_dup 2))
1255 "sub\t%L2, %L0\n\tsbb\t%H2, %H0"
1256 [(set_attr "timings" "22,44")
1257 (set_attr "length" "5,11")]
1260 (define_insn "xorsi3"
1261 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1262 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
1263 (match_operand:SI 2 "rx_source_operand"
1264 "r,Sint08,Sint16,Sint24,i,Q")))
1265 (set (reg:CC_ZS CC_REG)
1266 (compare:CC_ZS (xor:SI (match_dup 1) (match_dup 2))
1270 [(set_attr "timings" "11,11,11,11,11,33")
1271 (set_attr "length" "3,4,5,6,7,6")]
1274 ;; Floating Point Instructions
1276 (define_insn "addsf3"
1277 [(set (match_operand:SF 0 "register_operand" "=r,r,r")
1278 (plus:SF (match_operand:SF 1 "register_operand" "%0,0,0")
1279 (match_operand:SF 2 "rx_source_operand" "r,F,Q")))
1280 (set (reg:CC_ZS CC_REG)
1281 (compare:CC_ZS (plus:SF (match_dup 1) (match_dup 2))
1283 "ALLOW_RX_FPU_INSNS"
1285 [(set_attr "timings" "44,44,66")
1286 (set_attr "length" "3,7,5")]
1289 (define_insn "divsf3"
1290 [(set (match_operand:SF 0 "register_operand" "=r,r,r")
1291 (div:SF (match_operand:SF 1 "register_operand" "0,0,0")
1292 (match_operand:SF 2 "rx_source_operand" "r,F,Q")))
1293 (set (reg:CC_ZS CC_REG)
1294 (compare:CC_ZS (div:SF (match_dup 1) (match_dup 2))
1296 "ALLOW_RX_FPU_INSNS"
1298 [(set_attr "timings" "1616,1616,1818")
1299 (set_attr "length" "3,7,5")]
1302 (define_insn "mulsf3"
1303 [(set (match_operand:SF 0 "register_operand" "=r,r,r")
1304 (mult:SF (match_operand:SF 1 "register_operand" "%0,0,0")
1305 (match_operand:SF 2 "rx_source_operand" "r,F,Q")))
1306 (set (reg:CC_ZS CC_REG)
1307 (compare:CC_ZS (mult:SF (match_dup 1) (match_dup 2))
1309 "ALLOW_RX_FPU_INSNS"
1311 [(set_attr "timings" "33,33,55")
1312 (set_attr "length" "3,7,5")]
1315 (define_insn "subsf3"
1316 [(set (match_operand:SF 0 "register_operand" "=r,r,r")
1317 (minus:SF (match_operand:SF 1 "register_operand" "0,0,0")
1318 (match_operand:SF 2 "rx_source_operand" "r,F,Q")))
1319 (set (reg:CC_ZS CC_REG)
1320 (compare:CC_ZS (minus:SF (match_dup 1) (match_dup 2))
1322 "ALLOW_RX_FPU_INSNS"
1324 [(set_attr "timings" "44,44,66")
1325 (set_attr "length" "3,7,5")]
1328 (define_insn "fix_truncsfsi2"
1329 [(set (match_operand:SI 0 "register_operand" "=r,r")
1330 (fix:SI (match_operand:SF 1 "rx_compare_operand" "r,Q")))
1331 (set (reg:CC_ZS CC_REG)
1332 (compare:CC_ZS (fix:SI (match_dup 1))
1334 "ALLOW_RX_FPU_INSNS"
1336 [(set_attr "timings" "22,44")
1337 (set_attr "length" "3,5")]
1340 (define_insn "floatsisf2"
1341 [(set (match_operand:SF 0 "register_operand" "=r,r")
1342 (float:SF (match_operand:SI 1 "rx_compare_operand" "r,Q")))
1343 (set (reg:CC_ZS CC_REG)
1344 (compare:CC_ZS (float:SF (match_dup 1))
1346 "ALLOW_RX_FPU_INSNS"
1348 [(set_attr "timings" "22,44")
1349 (set_attr "length" "3,6")]
1352 ;; Bit manipulation instructions.
1353 ;; Note - there are two versions of each pattern because the memory
1354 ;; accessing versions use QImode whilst the register accessing
1355 ;; versions use SImode.
1356 ;; The peephole are here because the combiner only looks at a maximum
1357 ;; of three instructions at a time.
1359 (define_insn "bitset"
1360 [(set:SI (match_operand:SI 0 "register_operand" "=r")
1361 (ior:SI (match_operand:SI 1 "register_operand" "0")
1362 (ashift:SI (const_int 1)
1363 (match_operand:SI 2 "nonmemory_operand" "ri"))))]
1366 [(set_attr "length" "3")]
1369 (define_insn "bitset_in_memory"
1370 [(set:QI (match_operand:QI 0 "memory_operand" "=m")
1371 (ior:QI (match_operand:QI 1 "memory_operand" "0")
1372 (ashift:QI (const_int 1)
1373 (match_operand:QI 2 "nonmemory_operand" "ri"))))]
1376 [(set_attr "length" "3")
1377 (set_attr "timings" "34")]
1380 ;; (set (reg A) (const_int 1))
1381 ;; (set (reg A) (ashift (reg A) (reg B)))
1382 ;; (set (reg C) (ior (reg A) (reg C)))
1384 [(set:SI (match_operand:SI 0 "register_operand" "")
1386 (set:SI (match_dup 0)
1387 (ashift:SI (match_dup 0)
1388 (match_operand:SI 1 "register_operand" "")))
1389 (set:SI (match_operand:SI 2 "register_operand" "")
1390 (ior:SI (match_dup 0)
1392 "dead_or_set_p (insn, operands[0])"
1393 [(set:SI (match_dup 2)
1394 (ior:SI (match_dup 2)
1395 (ashift:SI (const_int 1)
1399 ;; (set (reg A) (const_int 1))
1400 ;; (set (reg A) (ashift (reg A) (reg B)))
1401 ;; (set (reg A) (ior (reg A) (reg C)))
1402 ;; (set (reg C) (reg A)
1404 [(set:SI (match_operand:SI 0 "register_operand" "")
1406 (set:SI (match_dup 0)
1407 (ashift:SI (match_dup 0)
1408 (match_operand:SI 1 "register_operand" "")))
1409 (set:SI (match_dup 0)
1410 (ior:SI (match_dup 0)
1411 (match_operand:SI 2 "register_operand" "")))
1412 (set:SI (match_dup 2) (match_dup 0))]
1413 "dead_or_set_p (insn, operands[0])"
1414 [(set:SI (match_dup 2)
1415 (ior:SI (match_dup 2)
1416 (ashift:SI (const_int 1)
1420 (define_insn "bitinvert"
1421 [(set:SI (match_operand:SI 0 "register_operand" "+r")
1422 (xor:SI (match_operand:SI 1 "register_operand" "0")
1423 (ashift:SI (const_int 1)
1424 (match_operand:SI 2 "nonmemory_operand" "ri"))))]
1427 [(set_attr "length" "3")]
1430 (define_insn "bitinvert_in_memory"
1431 [(set:QI (match_operand:QI 0 "memory_operand" "+m")
1432 (xor:QI (match_operand:QI 1 "register_operand" "0")
1433 (ashift:QI (const_int 1)
1434 (match_operand:QI 2 "nonmemory_operand" "ri"))))]
1437 [(set_attr "length" "5")
1438 (set_attr "timings" "33")]
1441 ;; (set (reg A) (const_int 1))
1442 ;; (set (reg A) (ashift (reg A) (reg B)))
1443 ;; (set (reg C) (xor (reg A) (reg C)))
1445 [(set:SI (match_operand:SI 0 "register_operand" "")
1447 (set:SI (match_dup 0)
1448 (ashift:SI (match_dup 0)
1449 (match_operand:SI 1 "register_operand" "")))
1450 (set:SI (match_operand:SI 2 "register_operand" "")
1451 (xor:SI (match_dup 0)
1453 "dead_or_set_p (insn, operands[0])"
1454 [(set:SI (match_dup 2)
1455 (xor:SI (match_dup 2)
1456 (ashift:SI (const_int 1)
1461 ;; (set (reg A) (const_int 1))
1462 ;; (set (reg A) (ashift (reg A) (reg B)))
1463 ;; (set (reg A) (xor (reg A) (reg C)))
1464 ;; (set (reg C) (reg A))
1466 [(set:SI (match_operand:SI 0 "register_operand" "")
1468 (set:SI (match_dup 0)
1469 (ashift:SI (match_dup 0)
1470 (match_operand:SI 1 "register_operand" "")))
1471 (set:SI (match_dup 0)
1472 (xor:SI (match_dup 0)
1473 (match_operand:SI 2 "register_operand" "")))
1474 (set:SI (match_dup 2) (match_dup 0))]
1475 "dead_or_set_p (insn, operands[0])"
1476 [(set:SI (match_dup 2)
1477 (xor:SI (match_dup 2)
1478 (ashift:SI (const_int 1)
1483 (define_insn "bitclr"
1484 [(set:SI (match_operand:SI 0 "register_operand" "=r")
1485 (and:SI (match_operand:SI 1 "register_operand" "0")
1486 (not:SI (ashift:SI (const_int 1)
1487 (match_operand:SI 2 "nonmemory_operand" "ri")))))]
1490 [(set_attr "length" "3")]
1493 (define_insn "bitclr_in_memory"
1494 [(set:QI (match_operand:QI 0 "memory_operand" "=m")
1495 (and:QI (match_operand:QI 1 "memory_operand" "0")
1496 (not:QI (ashift:QI (const_int 1)
1497 (match_operand:QI 2 "nonmemory_operand" "ri")))))]
1500 [(set_attr "length" "3")
1501 (set_attr "timings" "34")]
1504 ;; (set (reg A) (const_int -2))
1505 ;; (set (reg A) (rotate (reg A) (reg B)))
1506 ;; (set (reg C) (and (reg A) (reg C)))
1508 [(set:SI (match_operand:SI 0 "register_operand" "")
1510 (set:SI (match_dup 0)
1511 (rotate:SI (match_dup 0)
1512 (match_operand:SI 1 "register_operand" "")))
1513 (set:SI (match_operand:SI 2 "register_operand" "")
1514 (and:SI (match_dup 0)
1516 "dead_or_set_p (insn, operands[0])"
1517 [(set:SI (match_dup 2)
1518 (and:SI (match_dup 2)
1519 (not:SI (ashift:SI (const_int 1)
1523 ;; (set (reg A) (const_int -2))
1524 ;; (set (reg A) (rotate (reg A) (reg B)))
1525 ;; (set (reg A) (and (reg A) (reg C)))
1526 ;; (set (reg C) (reg A)
1528 [(set:SI (match_operand:SI 0 "register_operand" "")
1530 (set:SI (match_dup 0)
1531 (rotate:SI (match_dup 0)
1532 (match_operand:SI 1 "register_operand" "")))
1533 (set:SI (match_dup 0)
1534 (and:SI (match_dup 0)
1535 (match_operand:SI 2 "register_operand" "")))
1536 (set:SI (match_dup 2) (match_dup 0))]
1537 "dead_or_set_p (insn, operands[0])"
1538 [(set:SI (match_dup 2)
1539 (and:SI (match_dup 2)
1540 (not:SI (ashift:SI (const_int 1)
1544 (define_expand "insv"
1545 [(set:SI (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand") ;; Destination
1546 (match_operand 1 "immediate_operand") ;; # of bits to set
1547 (match_operand 2 "immediate_operand")) ;; Starting bit
1548 (match_operand 3 "immediate_operand"))] ;; Bits to insert
1551 if (rx_expand_insv (operands))
1557 ;; Atomic exchange operation.
1559 (define_insn "sync_lock_test_and_setsi"
1560 [(set:SI (match_operand:SI 0 "register_operand" "=r,r")
1561 (match_operand:SI 1 "rx_compare_operand" "=r,Q"))
1562 (set:SI (match_dup 1)
1563 (match_operand:SI 2 "register_operand" "0,0"))]
1566 [(set_attr "length" "3,6")
1567 (set_attr "timings" "22")]
1570 ;; Block move functions.
1572 (define_expand "movstr"
1573 [(set:SI (match_operand:BLK 1 "memory_operand") ;; Dest
1574 (match_operand:BLK 2 "memory_operand")) ;; Source
1575 (use (match_operand:SI 0 "register_operand")) ;; Updated Dest
1579 rtx addr1 = gen_rtx_REG (SImode, 1);
1580 rtx addr2 = gen_rtx_REG (SImode, 2);
1581 rtx len = gen_rtx_REG (SImode, 3);
1582 rtx dest_copy = gen_reg_rtx (SImode);
1584 emit_move_insn (len, GEN_INT (-1));
1585 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1586 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
1587 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1588 operands[2] = replace_equiv_address_nv (operands[2], addr2);
1589 emit_move_insn (dest_copy, addr1);
1590 emit_insn (gen_rx_movstr ());
1591 emit_move_insn (len, GEN_INT (-1));
1592 emit_insn (gen_rx_strend (operands[0], dest_copy));
1597 (define_insn "rx_movstr"
1598 [(set:SI (mem:BLK (reg:SI 1))
1599 (mem:BLK (reg:SI 2)))
1600 (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_MOVSTR)
1601 (clobber (reg:SI 1))
1602 (clobber (reg:SI 2))
1603 (clobber (reg:SI 3))]
1606 [(set_attr "length" "2")
1607 (set_attr "timings" "1111")] ;; The timing is a guesstimate.
1610 (define_insn "rx_strend"
1611 [(set:SI (match_operand:SI 0 "register_operand" "=r")
1612 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
1613 (reg:SI 3)] UNSPEC_STRLEN))
1614 (clobber (reg:SI 1))
1615 (clobber (reg:SI 2))
1616 (clobber (reg:SI 3))
1617 (clobber (reg:CC CC_REG))
1620 "mov\t%1, r1\n\tmov\t#0, r2\n\tsuntil.b\n\tmov\tr1, %0\n\tsub\t#1, %0"
1621 [(set_attr "length" "10")
1622 (set_attr "timings" "1111")] ;; The timing is a guesstimate.
1625 (define_expand "movmemsi"
1627 [(set (match_operand:BLK 0 "memory_operand") ;; Dest
1628 (match_operand:BLK 1 "memory_operand")) ;; Source
1629 (use (match_operand:SI 2 "register_operand")) ;; Length in bytes
1630 (match_operand 3 "immediate_operand") ;; Align
1631 (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_MOVMEM)]
1635 rtx addr1 = gen_rtx_REG (SImode, 1);
1636 rtx addr2 = gen_rtx_REG (SImode, 2);
1637 rtx len = gen_rtx_REG (SImode, 3);
1639 if (REG_P (operands[0]) && (REGNO (operands[0]) == 2
1640 || REGNO (operands[0]) == 3))
1642 if (REG_P (operands[1]) && (REGNO (operands[1]) == 1
1643 || REGNO (operands[1]) == 3))
1645 if (REG_P (operands[2]) && (REGNO (operands[2]) == 1
1646 || REGNO (operands[2]) == 2))
1648 emit_move_insn (addr1, force_operand (XEXP (operands[0], 0), NULL_RTX));
1649 emit_move_insn (addr2, force_operand (XEXP (operands[1], 0), NULL_RTX));
1650 emit_move_insn (len, force_operand (operands[2], NULL_RTX));
1651 operands[0] = replace_equiv_address_nv (operands[0], addr1);
1652 operands[1] = replace_equiv_address_nv (operands[1], addr2);
1653 emit_insn (gen_rx_movmem ());
1658 (define_insn "rx_movmem"
1659 [(set (mem:BLK (reg:SI 1))
1660 (mem:BLK (reg:SI 2)))
1662 (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_MOVMEM)
1663 (clobber (reg:SI 1))
1664 (clobber (reg:SI 2))
1665 (clobber (reg:SI 3))]
1668 [(set_attr "length" "2")
1669 (set_attr "timings" "1111")] ;; The timing is a guesstimate.
1672 (define_expand "setmemsi"
1673 [(set (match_operand:BLK 0 "memory_operand") ;; Dest
1674 (match_operand:QI 2 "nonmemory_operand")) ;; Value
1675 (use (match_operand:SI 1 "nonmemory_operand")) ;; Length
1676 (match_operand 3 "immediate_operand") ;; Align
1677 (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_SETMEM)]
1680 rtx addr = gen_rtx_REG (SImode, 1);
1681 rtx val = gen_rtx_REG (QImode, 2);
1682 rtx len = gen_rtx_REG (SImode, 3);
1684 emit_move_insn (addr, force_operand (XEXP (operands[0], 0), NULL_RTX));
1685 emit_move_insn (len, force_operand (operands[1], NULL_RTX));
1686 emit_move_insn (val, operands[2]);
1687 emit_insn (gen_rx_setmem ());
1692 (define_insn "rx_setmem"
1693 [(set:BLK (mem:BLK (reg:SI 1)) (reg 2))
1694 (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_SETMEM)
1695 (clobber (reg:SI 1))
1696 (clobber (reg:SI 3))]
1699 [(set_attr "length" "2")
1700 (set_attr "timings" "1111")] ;; The timing is a guesstimate.
1703 (define_expand "cmpstrnsi"
1704 [(set (match_operand:SI 0 "register_operand") ;; Result
1705 (unspec_volatile:SI [(match_operand:BLK 1 "memory_operand") ;; String1
1706 (match_operand:BLK 2 "memory_operand")] ;; String2
1708 (use (match_operand:SI 3 "register_operand")) ;; Max Length
1709 (match_operand:SI 4 "immediate_operand")] ;; Known Align
1712 rtx str1 = gen_rtx_REG (SImode, 1);
1713 rtx str2 = gen_rtx_REG (SImode, 2);
1714 rtx len = gen_rtx_REG (SImode, 3);
1716 emit_move_insn (str1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1717 emit_move_insn (str2, force_operand (XEXP (operands[2], 0), NULL_RTX));
1718 emit_move_insn (len, force_operand (operands[3], NULL_RTX));
1720 emit_insn (gen_rx_cmpstrn (operands[0], operands[1], operands[2]));
1725 (define_expand "cmpstrsi"
1726 [(set (match_operand:SI 0 "register_operand") ;; Result
1727 (unspec_volatile:SI [(match_operand:BLK 1 "memory_operand") ;; String1
1728 (match_operand:BLK 2 "memory_operand")] ;; String2
1730 (match_operand:SI 3 "immediate_operand")] ;; Known Align
1733 rtx str1 = gen_rtx_REG (SImode, 1);
1734 rtx str2 = gen_rtx_REG (SImode, 2);
1735 rtx len = gen_rtx_REG (SImode, 3);
1737 emit_move_insn (str1, force_reg (SImode, XEXP (operands[1], 0)));
1738 emit_move_insn (str2, force_reg (SImode, XEXP (operands[2], 0)));
1739 emit_move_insn (len, GEN_INT (-1));
1741 emit_insn (gen_rx_cmpstrn (operands[0], operands[1], operands[2]));
1746 (define_insn "rx_cmpstrn"
1747 [(set:SI (match_operand:SI 0 "register_operand" "=r")
1748 (unspec_volatile:SI [(reg:SI 1) (reg:SI 2) (reg:SI 3)]
1750 (use (match_operand:BLK 1 "memory_operand" "m"))
1751 (use (match_operand:BLK 2 "memory_operand" "m"))
1752 (clobber (reg:SI 1))
1753 (clobber (reg:SI 2))
1754 (clobber (reg:SI 3))
1755 (clobber (reg:CC CC_REG))]
1757 "scmpu ; Perform the string comparison
1758 mov #-1, %0 ; Set up -1 result (which cannot be created
1760 bnc ?+ ; If Carry is not set skip over
1761 scne.L %0 ; Set result based on Z flag
1764 [(set_attr "length" "9")
1765 (set_attr "timings" "1111")] ;; The timing is a guesstimate.
1768 ;; Builtin Functions
1770 ;; GCC does not have the ability to generate the following instructions
1771 ;; on its own so they are provided as builtins instead. To use them from
1772 ;; a program for example invoke them as __builtin_rx_<insn_name>. For
1775 ;; int short_byte_swap (int arg) { return __builtin_rx_revw (arg); }
1777 ;;---------- Accumulator Support ------------------------
1779 ;; Multiply & Accumulate (high)
1780 (define_insn "machi"
1781 [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
1782 (match_operand:SI 1 "register_operand" "r")]
1783 UNSPEC_BUILTIN_MACHI)]
1786 [(set_attr "length" "3")]
1789 ;; Multiply & Accumulate (low)
1790 (define_insn "maclo"
1791 [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
1792 (match_operand:SI 1 "register_operand" "r")]
1793 UNSPEC_BUILTIN_MACLO)]
1796 [(set_attr "length" "3")]
1800 (define_insn "mulhi"
1801 [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
1802 (match_operand:SI 1 "register_operand" "r")]
1803 UNSPEC_BUILTIN_MULHI)]
1806 [(set_attr "length" "3")]
1810 (define_insn "mullo"
1811 [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
1812 (match_operand:SI 1 "register_operand" "r")]
1813 UNSPEC_BUILTIN_MULLO)]
1816 [(set_attr "length" "3")]
1819 ;; Move from Accumulator (high)
1820 (define_insn "mvfachi"
1821 [(set (match_operand:SI 0 "register_operand" "=r")
1822 (unspec:SI [(const_int 0)]
1823 UNSPEC_BUILTIN_MVFACHI))]
1826 [(set_attr "length" "3")]
1829 ;; Move from Accumulator (middle)
1830 (define_insn "mvfacmi"
1831 [(set (match_operand:SI 0 "register_operand" "=r")
1832 (unspec:SI [(const_int 0)]
1833 UNSPEC_BUILTIN_MVFACMI))]
1836 [(set_attr "length" "3")]
1839 ;; Move to Accumulator (high)
1840 (define_insn "mvtachi"
1841 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
1842 UNSPEC_BUILTIN_MVTACHI)]
1845 [(set_attr "length" "3")]
1848 ;; Move to Accumulator (low)
1849 (define_insn "mvtaclo"
1850 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
1851 UNSPEC_BUILTIN_MVTACLO)]
1854 [(set_attr "length" "3")]
1857 ;; Round Accumulator
1859 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")]
1860 UNSPEC_BUILTIN_RACW)]
1863 [(set_attr "length" "3")]
1866 ;; Repeat multiply and accumulate
1868 [(unspec:SI [(const_int 0) (reg:SI 1) (reg:SI 2) (reg:SI 3)
1869 (reg:SI 4) (reg:SI 5) (reg:SI 6)]
1870 UNSPEC_BUILTIN_RMPA)
1871 (clobber (reg:SI 1))
1872 (clobber (reg:SI 2))
1873 (clobber (reg:SI 3))]
1876 [(set_attr "length" "2")
1877 (set_attr "timings" "1010")]
1880 ;;---------- Arithmetic ------------------------
1882 ;; Byte swap (two 16-bit values).
1884 [(set (match_operand:SI 0 "register_operand" "+r")
1885 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
1886 UNSPEC_BUILTIN_REVW))]
1889 [(set_attr "length" "3")]
1892 ;; Round to integer.
1893 (define_insn "lrintsf2"
1894 [(set (match_operand:SI 0 "register_operand" "=r,r")
1895 (unspec:SI [(match_operand:SF 1 "rx_compare_operand" "r,Q")]
1896 UNSPEC_BUILTIN_ROUND))
1897 (clobber (reg:CC CC_REG))]
1900 [(set_attr "timings" "22,44")
1901 (set_attr "length" "3,5")]
1904 ;; Saturate to 32-bits
1906 [(set (match_operand:SI 0 "register_operand" "=r")
1907 (unspec:SI [(match_operand:SI 1 "register_operand" "0")]
1908 UNSPEC_BUILTIN_SAT))]
1911 [(set_attr "length" "2")]
1914 ;;---------- Control Registers ------------------------
1916 ;; Clear Processor Status Word
1917 (define_insn "clrpsw"
1918 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")]
1919 UNSPEC_BUILTIN_CLRPSW)
1920 (clobber (reg:CC CC_REG))]
1923 [(set_attr "length" "2")]
1926 ;; Set Processor Status Word
1927 (define_insn "setpsw"
1928 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")]
1929 UNSPEC_BUILTIN_SETPSW)
1930 (clobber (reg:CC CC_REG))]
1933 [(set_attr "length" "2")]
1936 ;; Move from control register
1938 [(set (match_operand:SI 0 "register_operand" "=r")
1939 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")]
1940 UNSPEC_BUILTIN_MVFC))]
1943 [(set_attr "length" "3")]
1946 ;; Move to control register
1948 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i,i")
1949 (match_operand:SI 1 "nonmemory_operand" "r,i")]
1950 UNSPEC_BUILTIN_MVTC)]
1953 [(set_attr "length" "3,7")]
1954 ;; Ignore possible clobbering of the comparison flags in the
1955 ;; PSW register. This is a cc0 target so any cc0 setting
1956 ;; instruction will always be paired with a cc0 user, without
1957 ;; the possibility of this instruction being placed in between
1961 ;; Move to interrupt priority level
1962 (define_insn "mvtipl"
1963 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "Uint04")]
1964 UNSPEC_BUILTIN_MVTIPL)]
1967 [(set_attr "length" "3")]
1970 ;;---------- Interrupts ------------------------
1974 [(unspec_volatile [(const_int 0)]
1975 UNSPEC_BUILTIN_BRK)]
1978 [(set_attr "length" "1")
1979 (set_attr "timings" "66")]
1984 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")]
1985 UNSPEC_BUILTIN_INT)]
1988 [(set_attr "length" "3")]
1993 [(unspec_volatile [(const_int 0)]
1994 UNSPEC_BUILTIN_WAIT)]
1997 [(set_attr "length" "2")]
2000 ;;---------- CoProcessor Support ------------------------
2002 ;; FIXME: The instructions are currently commented out because
2003 ;; the bit patterns have not been finalized, so the assembler
2004 ;; does not support them. Once they are decided and the assembler
2005 ;; supports them, enable the instructions here.
2007 ;; Move from co-processor register
2008 (define_insn "mvfcp"
2009 [(set (match_operand:SI 0 "register_operand" "=r")
2010 (unspec:SI [(match_operand:SI 1 "immediate_operand" "i")
2011 (match_operand:SI 2 "immediate_operand" "i")]
2012 UNSPEC_BUILTIN_MVFCP))]
2014 "; mvfcp\t%1, %0, %2"
2015 [(set_attr "length" "5")]
2018 ;;---------- Misc ------------------------
2020 ;; Required by cfglayout.c...
2025 [(set_attr "length" "1")]