1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 91, 92, 93, 94, 1995 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;; Define an insn type attribute. This is used in function unit delay
25 (define_attr "type" "integer,load,fpload,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
26 (const_string "integer"))
29 (define_attr "length" ""
30 (if_then_else (eq_attr "type" "branch")
31 (if_then_else (and (ge (minus (pc) (match_dup 0))
33 (lt (minus (pc) (match_dup 0))
39 ;; Processor type -- this attribute must exactly match the processor_type
40 ;; enumeration in rs6000.h.
42 (define_attr "cpu" "rios1,rios2,ppc403,ppc601,ppc603,ppc604,ppc620"
43 (const (symbol_ref "rs6000_cpu_attr")))
45 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
46 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
48 ; Load/Store Unit -- POWER/2 and pure PowerPC only
49 ; (POWER and 601 use Integer Unit)
50 (define_function_unit "lsu" 1 0
51 (and (eq_attr "type" "load")
52 (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620"))
55 (define_function_unit "lsu" 1 0
56 (and (eq_attr "type" "fpload")
57 (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620"))
60 (define_function_unit "iu" 1 0
61 (and (eq_attr "type" "load")
62 (eq_attr "cpu" "rios1,ppc403,ppc601"))
65 (define_function_unit "iu" 1 0
66 (and (eq_attr "type" "fpload")
67 (eq_attr "cpu" "rios1,ppc601"))
70 ; Integer Unit (RIOS1, PPC601, PPC603)
71 ; Trivial operations take one cycle which need not be listed here.
72 (define_function_unit "iu" 1 0
73 (and (eq_attr "type" "imul")
74 (eq_attr "cpu" "rios1"))
77 (define_function_unit "iu" 1 0
78 (and (eq_attr "type" "imul")
79 (eq_attr "cpu" "ppc403"))
82 (define_function_unit "iu" 1 0
83 (and (eq_attr "type" "imul")
84 (eq_attr "cpu" "ppc601,ppc603"))
87 (define_function_unit "iu" 1 0
88 (and (eq_attr "type" "idiv")
89 (eq_attr "cpu" "rios1"))
92 (define_function_unit "iu" 1 0
93 (and (eq_attr "type" "idiv")
94 (eq_attr "cpu" "ppc403"))
97 (define_function_unit "iu" 1 0
98 (and (eq_attr "type" "idiv")
99 (eq_attr "cpu" "ppc601"))
102 (define_function_unit "iu" 1 0
103 (and (eq_attr "type" "idiv")
104 (eq_attr "cpu" "ppc603"))
107 ; RIOS2 has two integer units: a primary one which can perform all
108 ; operations and a secondary one which is fed in lock step with the first
109 ; and can perform "simple" integer operations.
110 (define_function_unit "iu2" 2 0
111 (and (eq_attr "type" "integer")
112 (eq_attr "cpu" "rios2"))
114 [(eq_attr "type" "imul,idiv")])
116 (define_function_unit "imuldiv" 1 0
117 (and (eq_attr "type" "imul")
118 (eq_attr "cpu" "rios2"))
120 [(eq_attr "type" "integer")])
122 (define_function_unit "imuldiv" 1 0
123 (and (eq_attr "type" "idiv")
124 (eq_attr "cpu" "rios2"))
126 [(eq_attr "type" "integer")])
128 ; PPC604 has three integer units: one primary and two secondary.
129 (define_function_unit "iu3" 3 0
130 (and (eq_attr "type" "integer")
131 (eq_attr "cpu" "ppc604,ppc620"))
133 [(eq_attr "type" "imul,idiv")])
135 (define_function_unit "imuldiv" 1 0
136 (and (eq_attr "type" "imul")
137 (eq_attr "cpu" "ppc604,ppc620"))
139 [(eq_attr "type" "integer")])
141 (define_function_unit "imuldiv" 1 0
142 (and (eq_attr "type" "idiv")
143 (eq_attr "cpu" "ppc604,ppc620"))
145 [(eq_attr "type" "integer")])
147 ; Branch Processing Unit
148 (define_function_unit "bpu" 1 0
149 (eq_attr "type" "compare")
152 (define_function_unit "bpu" 1 0
153 (eq_attr "type" "delayed_compare")
156 (define_function_unit "bpu" 1 0
157 (and (eq_attr "type" "fpcompare")
158 (eq_attr "cpu" "rios1,rios2"))
161 (define_function_unit "bpu" 1 0
162 (and (eq_attr "type" "fpcompare")
163 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
166 (define_function_unit "bpu" 1 0
167 (and (eq_attr "type" "mtjmpr")
168 (eq_attr "cpu" "rios1,rios2"))
171 (define_function_unit "bpu" 1 0
172 (and (eq_attr "type" "mtjmpr")
173 (eq_attr "cpu" "ppc403,ppc601,ppc603,ppc604,ppc620"))
176 ; Floating Point Unit (RIOS1, PPC601, PPC603, PPC604).
177 (define_function_unit "fpu" 1 0
178 (and (eq_attr "type" "fp,dmul")
179 (eq_attr "cpu" "rios1"))
182 (define_function_unit "fpu" 1 0
183 (and (eq_attr "type" "fp")
184 (eq_attr "cpu" "ppc601"))
187 (define_function_unit "fpu" 1 0
188 (and (eq_attr "type" "fp")
189 (eq_attr "cpu" "ppc603,ppc604,ppc620"))
192 (define_function_unit "fpu" 1 0
193 (and (eq_attr "type" "dmul")
194 (eq_attr "cpu" "ppc601"))
197 (define_function_unit "fpu" 1 0
198 (and (eq_attr "type" "dmul")
199 (eq_attr "cpu" "ppc603"))
202 (define_function_unit "fpu" 1 0
203 (and (eq_attr "type" "dmul")
204 (eq_attr "cpu" "ppc604,ppc620"))
207 (define_function_unit "fpu" 1 0
208 (and (eq_attr "type" "sdiv,ddiv")
209 (eq_attr "cpu" "rios1"))
212 (define_function_unit "fpu" 1 0
213 (and (eq_attr "type" "sdiv")
214 (eq_attr "cpu" "ppc601"))
217 (define_function_unit "fpu" 1 0
218 (and (eq_attr "type" "sdiv")
219 (eq_attr "cpu" "ppc603,ppc604,ppc620"))
222 (define_function_unit "fpu" 1 0
223 (and (eq_attr "type" "ddiv")
224 (eq_attr "cpu" "ppc601,ppc604,ppc620"))
227 (define_function_unit "fpu" 1 0
228 (and (eq_attr "type" "ddiv")
229 (eq_attr "cpu" "ppc603"))
232 (define_function_unit "fpu" 1 0
233 (and (eq_attr "type" "ssqrt")
234 (eq_attr "cpu" "ppc620"))
237 (define_function_unit "fpu" 1 0
238 (and (eq_attr "type" "dsqrt")
239 (eq_attr "cpu" "ppc620"))
242 ; RIOS2 has two symmetric FPUs.
243 (define_function_unit "fpu2" 2 0
244 (and (eq_attr "type" "fp")
245 (eq_attr "cpu" "rios2"))
248 (define_function_unit "fpu2" 2 0
249 (and (eq_attr "type" "dmul")
250 (eq_attr "cpu" "rios2"))
253 (define_function_unit "fpu2" 2 0
254 (and (eq_attr "type" "sdiv,ddiv")
255 (eq_attr "cpu" "rios2"))
258 (define_function_unit "fpu2" 2 0
259 (and (eq_attr "type" "ssqrt,dsqrt")
260 (eq_attr "cpu" "rios2"))
263 ;; Start with fixed-point load and store insns. Here we put only the more
264 ;; complex forms. Basic data transfer is done later.
266 (define_expand "zero_extendqidi2"
267 [(set (match_operand:DI 0 "gpc_reg_operand" "")
268 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
273 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
274 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
279 [(set_attr "type" "load,*")])
282 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
283 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
285 (clobber (match_scratch:DI 2 "=r"))]
288 [(set_attr "type" "compare")])
291 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
292 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
294 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
295 (zero_extend:DI (match_dup 1)))]
298 [(set_attr "type" "compare")])
300 (define_insn "extendqidi2"
301 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
302 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
307 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
308 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
310 (clobber (match_scratch:DI 2 "=r"))]
313 [(set_attr "type" "compare")])
316 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
317 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
319 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
320 (sign_extend:DI (match_dup 1)))]
323 [(set_attr "type" "compare")])
325 (define_expand "zero_extendhidi2"
326 [(set (match_operand:DI 0 "gpc_reg_operand" "")
327 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
332 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
333 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
338 [(set_attr "type" "load,*")])
341 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
342 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
344 (clobber (match_scratch:DI 2 "=r"))]
347 [(set_attr "type" "compare")])
350 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
351 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
353 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
354 (zero_extend:DI (match_dup 1)))]
357 [(set_attr "type" "compare")])
359 (define_expand "extendhidi2"
360 [(set (match_operand:DI 0 "gpc_reg_operand" "")
361 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
366 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
367 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
372 [(set_attr "type" "load,*")])
375 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
376 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
378 (clobber (match_scratch:DI 2 "=r"))]
381 [(set_attr "type" "compare")])
384 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
385 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
387 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
388 (sign_extend:DI (match_dup 1)))]
391 [(set_attr "type" "compare")])
393 (define_expand "zero_extendsidi2"
394 [(set (match_operand:DI 0 "gpc_reg_operand" "")
395 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
400 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
401 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
406 [(set_attr "type" "load,*")])
409 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
410 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
412 (clobber (match_scratch:DI 2 "=r"))]
415 [(set_attr "type" "compare")])
418 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
419 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
421 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
422 (zero_extend:DI (match_dup 1)))]
425 [(set_attr "type" "compare")])
427 (define_expand "extendsidi2"
428 [(set (match_operand:DI 0 "gpc_reg_operand" "")
429 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
434 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
435 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
440 [(set_attr "type" "load,*")])
443 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
444 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
446 (clobber (match_scratch:DI 2 "=r"))]
449 [(set_attr "type" "compare")])
452 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
453 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
455 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
456 (sign_extend:DI (match_dup 1)))]
459 [(set_attr "type" "compare")])
461 (define_expand "zero_extendqisi2"
462 [(set (match_operand:SI 0 "gpc_reg_operand" "")
463 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
468 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
469 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
473 {rlinm|rlwinm} %0,%1,0,0xff"
474 [(set_attr "type" "load,*")])
477 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
478 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
480 (clobber (match_scratch:SI 2 "=r"))]
482 "{andil.|andi.} %2,%1,0xff"
483 [(set_attr "type" "compare")])
486 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
487 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
489 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
490 (zero_extend:SI (match_dup 1)))]
492 "{andil.|andi.} %0,%1,0xff"
493 [(set_attr "type" "compare")])
495 (define_expand "extendqisi2"
496 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
497 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
502 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
503 else if (TARGET_POWER)
504 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
506 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
510 (define_insn "extendqisi2_ppc"
511 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
512 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
517 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
518 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
520 (clobber (match_scratch:SI 2 "=r"))]
523 [(set_attr "type" "compare")])
526 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
527 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
529 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
530 (sign_extend:SI (match_dup 1)))]
533 [(set_attr "type" "compare")])
535 (define_expand "extendqisi2_power"
536 [(parallel [(set (match_dup 2)
537 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
539 (clobber (scratch:SI))])
540 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
541 (ashiftrt:SI (match_dup 2)
543 (clobber (scratch:SI))])]
546 { operands[1] = gen_lowpart (SImode, operands[1]);
547 operands[2] = gen_reg_rtx (SImode); }")
549 (define_expand "extendqisi2_no_power"
551 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
553 (set (match_operand:SI 0 "gpc_reg_operand" "")
554 (ashiftrt:SI (match_dup 2)
556 "! TARGET_POWER && ! TARGET_POWERPC"
558 { operands[1] = gen_lowpart (SImode, operands[1]);
559 operands[2] = gen_reg_rtx (SImode); }")
561 (define_expand "zero_extendqihi2"
562 [(set (match_operand:HI 0 "gpc_reg_operand" "")
563 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
568 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
569 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
573 {rlinm|rlwinm} %0,%1,0,0xff"
574 [(set_attr "type" "load,*")])
577 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
578 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
580 (clobber (match_scratch:HI 2 "=r"))]
582 "{andil.|andi.} %2,%1,0xff"
583 [(set_attr "type" "compare")])
586 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
587 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
589 (set (match_operand:HI 0 "gpc_reg_operand" "=r")
590 (zero_extend:HI (match_dup 1)))]
592 "{andil.|andi.} %0,%1,0xff"
593 [(set_attr "type" "compare")])
595 (define_expand "extendqihi2"
596 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
597 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
602 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
603 else if (TARGET_POWER)
604 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
606 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
610 (define_insn "extendqihi2_ppc"
611 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
612 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
617 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
618 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
620 (clobber (match_scratch:HI 2 "=r"))]
623 [(set_attr "type" "compare")])
626 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
627 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
629 (set (match_operand:HI 0 "gpc_reg_operand" "=r")
630 (sign_extend:HI (match_dup 1)))]
633 [(set_attr "type" "compare")])
635 (define_expand "extendqihi2_power"
636 [(parallel [(set (match_dup 2)
637 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
639 (clobber (scratch:SI))])
640 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
641 (ashiftrt:SI (match_dup 2)
643 (clobber (scratch:SI))])]
646 { operands[0] = gen_lowpart (SImode, operands[0]);
647 operands[1] = gen_lowpart (SImode, operands[1]);
648 operands[2] = gen_reg_rtx (SImode); }")
650 (define_expand "extendqihi2_no_power"
652 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
654 (set (match_operand:HI 0 "gpc_reg_operand" "")
655 (ashiftrt:SI (match_dup 2)
657 "! TARGET_POWER && ! TARGET_POWERPC"
659 { operands[0] = gen_lowpart (SImode, operands[0]);
660 operands[1] = gen_lowpart (SImode, operands[1]);
661 operands[2] = gen_reg_rtx (SImode); }")
663 (define_expand "zero_extendhisi2"
664 [(set (match_operand:SI 0 "gpc_reg_operand" "")
665 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
670 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
671 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
675 {rlinm|rlwinm} %0,%1,0,0xffff"
676 [(set_attr "type" "load,*")])
679 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
680 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
682 (clobber (match_scratch:SI 2 "=r"))]
684 "{andil.|andi.} %2,%1,0xffff"
685 [(set_attr "type" "compare")])
688 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
689 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
691 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
692 (zero_extend:SI (match_dup 1)))]
694 "{andil.|andi.} %0,%1,0xffff"
695 [(set_attr "type" "compare")])
697 (define_expand "extendhisi2"
698 [(set (match_operand:SI 0 "gpc_reg_operand" "")
699 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
704 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
705 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
710 [(set_attr "type" "load,*")])
713 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
714 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
716 (clobber (match_scratch:SI 2 "=r"))]
718 "{exts.|extsh.} %2,%1"
719 [(set_attr "type" "compare")])
722 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
723 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
725 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
726 (sign_extend:SI (match_dup 1)))]
728 "{exts.|extsh.} %0,%1"
729 [(set_attr "type" "compare")])
731 ;; Fixed-point arithmetic insns.
733 ;; Discourage ai/addic because of carry but provide it in an alternative
734 ;; allowing register zero as source.
735 (define_insn "addsi3"
736 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
737 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
738 (match_operand:SI 2 "add_operand" "r,I,I,J")))]
742 {cal %0,%2(%1)|addi %0,%1,%2}
744 {cau|addis} %0,%1,%u2")
747 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
748 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
749 (match_operand:SI 2 "reg_or_short_operand" "r,I"))
751 (clobber (match_scratch:SI 3 "=r,r"))]
755 {ai.|addic.} %3,%1,%2"
756 [(set_attr "type" "compare")])
759 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
760 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
761 (match_operand:SI 2 "reg_or_short_operand" "r,I"))
763 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
764 (plus:SI (match_dup 1) (match_dup 2)))]
768 {ai.|addic.} %0,%1,%2"
769 [(set_attr "type" "compare")])
771 ;; Split an add that we can't do in one insn into two insns, each of which
772 ;; does one 16-bit part. This is used by combine. Note that the low-order
773 ;; add should be last in case the result gets used in an address.
776 [(set (match_operand:SI 0 "gpc_reg_operand" "")
777 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
778 (match_operand:SI 2 "non_add_cint_operand" "")))]
780 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
781 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
784 int low = INTVAL (operands[2]) & 0xffff;
785 int high = (unsigned) INTVAL (operands[2]) >> 16;
788 high++, low |= 0xffff0000;
790 operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16);
791 operands[4] = gen_rtx (CONST_INT, VOIDmode, low);
794 (define_insn "one_cmplsi2"
795 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
796 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
801 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
802 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
804 (clobber (match_scratch:SI 2 "=r"))]
807 [(set_attr "type" "compare")])
810 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
811 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
813 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
814 (not:SI (match_dup 1)))]
817 [(set_attr "type" "compare")])
820 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
821 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
822 (match_operand:SI 2 "gpc_reg_operand" "r")))]
824 "{sf%I1|subf%I1c} %0,%2,%1")
827 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
828 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
829 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
836 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
837 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
838 (match_operand:SI 2 "gpc_reg_operand" "r"))
840 (clobber (match_scratch:SI 3 "=r"))]
842 "{sf.|subfc.} %3,%2,%1"
843 [(set_attr "type" "compare")])
846 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
847 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
848 (match_operand:SI 2 "gpc_reg_operand" "r"))
850 (clobber (match_scratch:SI 3 "=r"))]
853 [(set_attr "type" "compare")])
856 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
857 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
858 (match_operand:SI 2 "gpc_reg_operand" "r"))
860 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
861 (minus:SI (match_dup 1) (match_dup 2)))]
863 "{sf.|subfc.} %0,%2,%1"
864 [(set_attr "type" "compare")])
867 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
868 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
869 (match_operand:SI 2 "gpc_reg_operand" "r"))
871 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
872 (minus:SI (match_dup 1) (match_dup 2)))]
875 [(set_attr "type" "compare")])
877 (define_expand "subsi3"
878 [(set (match_operand:SI 0 "gpc_reg_operand" "")
879 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
880 (match_operand:SI 2 "reg_or_cint_operand" "")))]
884 if (GET_CODE (operands[2]) == CONST_INT)
886 emit_insn (gen_addsi3 (operands[0], operands[1],
887 negate_rtx (SImode, operands[2])));
892 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
893 ;; instruction and some auxiliary computations. Then we just have a single
894 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
897 (define_expand "sminsi3"
899 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
900 (match_operand:SI 2 "reg_or_short_operand" ""))
902 (minus:SI (match_dup 2) (match_dup 1))))
903 (set (match_operand:SI 0 "gpc_reg_operand" "")
904 (minus:SI (match_dup 2) (match_dup 3)))]
907 { operands[3] = gen_reg_rtx (SImode); }")
910 [(set (match_operand:SI 0 "gpc_reg_operand" "")
911 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
912 (match_operand:SI 2 "reg_or_short_operand" "")))
913 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
916 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
918 (minus:SI (match_dup 2) (match_dup 1))))
919 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
922 (define_expand "smaxsi3"
924 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
925 (match_operand:SI 2 "reg_or_short_operand" ""))
927 (minus:SI (match_dup 2) (match_dup 1))))
928 (set (match_operand:SI 0 "gpc_reg_operand" "")
929 (plus:SI (match_dup 3) (match_dup 1)))]
932 { operands[3] = gen_reg_rtx (SImode); }")
935 [(set (match_operand:SI 0 "gpc_reg_operand" "")
936 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
937 (match_operand:SI 2 "reg_or_short_operand" "")))
938 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
941 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
943 (minus:SI (match_dup 2) (match_dup 1))))
944 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
947 (define_expand "uminsi3"
948 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
950 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
952 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
954 (minus:SI (match_dup 4) (match_dup 3))))
955 (set (match_operand:SI 0 "gpc_reg_operand" "")
956 (minus:SI (match_dup 2) (match_dup 3)))]
960 operands[3] = gen_reg_rtx (SImode);
961 operands[4] = gen_reg_rtx (SImode);
962 operands[5] = GEN_INT (-2147483647 - 1);
965 (define_expand "umaxsi3"
966 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
968 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
970 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
972 (minus:SI (match_dup 4) (match_dup 3))))
973 (set (match_operand:SI 0 "gpc_reg_operand" "")
974 (plus:SI (match_dup 3) (match_dup 1)))]
978 operands[3] = gen_reg_rtx (SImode);
979 operands[4] = gen_reg_rtx (SImode);
980 operands[5] = GEN_INT (-2147483647 - 1);
984 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
985 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
986 (match_operand:SI 2 "reg_or_short_operand" "rI"))
988 (minus:SI (match_dup 2) (match_dup 1))))]
993 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
995 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
996 (match_operand:SI 2 "reg_or_short_operand" "rI"))
998 (minus:SI (match_dup 2) (match_dup 1)))
1000 (clobber (match_scratch:SI 3 "=r"))]
1003 [(set_attr "type" "delayed_compare")])
1006 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1008 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1009 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1011 (minus:SI (match_dup 2) (match_dup 1)))
1013 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1014 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1016 (minus:SI (match_dup 2) (match_dup 1))))]
1019 [(set_attr "type" "delayed_compare")])
1021 ;; We don't need abs with condition code because such comparisons should
1023 (define_expand "abssi2"
1024 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1025 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1031 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1036 (define_insn "abssi2_power"
1037 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1038 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1042 (define_insn "abssi2_nopower"
1043 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1044 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1045 (clobber (match_scratch:SI 2 "=&r,&r"))]
1047 "{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0"
1048 [(set_attr "length" "12")])
1051 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1052 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1053 (clobber (match_scratch:SI 2 "=&r,&r"))]
1054 "!TARGET_POWER && reload_completed"
1055 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1056 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1057 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1061 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1062 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1067 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1068 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1069 (clobber (match_scratch:SI 2 "=&r,&r"))]
1071 "{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2"
1072 [(set_attr "length" "12")])
1075 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1076 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1077 (clobber (match_scratch:SI 2 "=&r,&r"))]
1078 "!TARGET_POWER && reload_completed"
1079 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1080 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1081 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1084 (define_insn "negsi2"
1085 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1086 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1091 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1092 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1094 (clobber (match_scratch:SI 2 "=r"))]
1097 [(set_attr "type" "compare")])
1100 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
1101 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1103 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1104 (neg:SI (match_dup 1)))]
1107 [(set_attr "type" "compare")])
1109 (define_insn "ffssi2"
1110 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
1111 (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1113 "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32"
1114 [(set_attr "length" "16")])
1116 (define_expand "mulsi3"
1117 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1118 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1119 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1124 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1126 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1130 (define_insn "mulsi3_mq"
1131 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1132 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1133 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1134 (clobber (match_scratch:SI 3 "=q,q"))]
1137 {muls|mullw} %0,%1,%2
1138 {muli|mulli} %0,%1,%2"
1139 [(set_attr "type" "imul")])
1141 (define_insn "mulsi3_no_mq"
1142 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1143 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1144 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1149 [(set_attr "type" "imul")])
1152 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1153 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1154 (match_operand:SI 2 "gpc_reg_operand" "r"))
1156 (clobber (match_scratch:SI 3 "=r"))
1157 (clobber (match_scratch:SI 4 "=q"))]
1159 "{muls.|mullw.} %3,%1,%2"
1160 [(set_attr "type" "delayed_compare")])
1163 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1164 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1165 (match_operand:SI 2 "gpc_reg_operand" "r"))
1167 (clobber (match_scratch:SI 3 "=r"))]
1170 [(set_attr "type" "delayed_compare")])
1173 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1174 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1175 (match_operand:SI 2 "gpc_reg_operand" "r"))
1177 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1178 (mult:SI (match_dup 1) (match_dup 2)))
1179 (clobber (match_scratch:SI 4 "=q"))]
1181 "{muls.|mullw.} %0,%1,%2"
1182 [(set_attr "type" "delayed_compare")])
1185 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1186 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1187 (match_operand:SI 2 "gpc_reg_operand" "r"))
1189 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1190 (mult:SI (match_dup 1) (match_dup 2)))]
1193 [(set_attr "type" "delayed_compare")])
1195 ;; Operand 1 is divided by operand 2; quotient goes to operand
1196 ;; 0 and remainder to operand 3.
1197 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1199 (define_expand "divmodsi4"
1200 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1201 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1202 (match_operand:SI 2 "gpc_reg_operand" "")))
1203 (set (match_operand:SI 3 "gpc_reg_operand" "")
1204 (mod:SI (match_dup 1) (match_dup 2)))])]
1205 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1208 if (! TARGET_POWER && ! TARGET_POWERPC)
1210 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1211 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1212 emit_insn (gen_divss_call ());
1213 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1214 emit_move_insn (operands[3], gen_rtx (REG, SImode, 4));
1220 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1221 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1222 (match_operand:SI 2 "gpc_reg_operand" "r")))
1223 (set (match_operand:SI 3 "gpc_reg_operand" "=q")
1224 (mod:SI (match_dup 1) (match_dup 2)))]
1227 [(set_attr "type" "idiv")])
1230 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1231 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1232 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1235 [(set_attr "type" "idiv")])
1237 (define_expand "udivsi3"
1238 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1239 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1240 (match_operand:SI 2 "gpc_reg_operand" "")))]
1241 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1244 if (! TARGET_POWER && ! TARGET_POWERPC)
1246 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1247 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1248 emit_insn (gen_quous_call ());
1249 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1255 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1256 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1257 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1260 [(set_attr "type" "idiv")])
1262 ;; For powers of two we can do srai/aze for divide and then adjust for
1263 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1264 ;; used; for PowerPC, force operands into register and do a normal divide;
1265 ;; for AIX common-mode, use quoss call on register operands.
1266 (define_expand "divsi3"
1267 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1268 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1269 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1273 if (GET_CODE (operands[2]) == CONST_INT
1274 && exact_log2 (INTVAL (operands[2])) >= 0)
1276 else if (TARGET_POWER && ! TARGET_POWERPC)
1279 operands[2] = force_reg (SImode, operands[2]);
1281 if (! TARGET_POWER && ! TARGET_POWERPC)
1283 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1284 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1285 emit_insn (gen_quoss_call ());
1286 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1291 (define_expand "modsi3"
1292 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1293 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1294 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1298 int i = exact_log2 (INTVAL (operands[2]));
1302 if (GET_CODE (operands[2]) != CONST_INT || i < 0)
1305 temp1 = gen_reg_rtx (SImode);
1306 temp2 = gen_reg_rtx (SImode);
1308 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1309 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1310 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1315 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1316 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1317 (match_operand:SI 2 "const_int_operand" "N")))]
1318 "exact_log2 (INTVAL (operands[2])) >= 0"
1319 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1320 [(set_attr "length" "8")])
1323 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1324 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1325 (match_operand:SI 2 "const_int_operand" "N"))
1327 (clobber (match_scratch:SI 3 "=r"))]
1328 "exact_log2 (INTVAL (operands[2])) >= 0"
1329 "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3"
1330 [(set_attr "type" "compare")
1331 (set_attr "length" "8")])
1334 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1335 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1336 (match_operand:SI 2 "const_int_operand" "N"))
1338 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1339 (div:SI (match_dup 1) (match_dup 2)))]
1340 "exact_log2 (INTVAL (operands[2])) >= 0"
1341 "{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0"
1342 [(set_attr "type" "compare")
1343 (set_attr "length" "8")])
1346 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1349 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1351 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
1352 (match_operand:SI 3 "gpc_reg_operand" "r")))
1353 (set (match_operand:SI 2 "register_operand" "=*q")
1356 (zero_extend:DI (match_dup 1)) (const_int 32))
1357 (zero_extend:DI (match_dup 4)))
1361 [(set_attr "type" "idiv")])
1363 ;; To do unsigned divide we handle the cases of the divisor looking like a
1364 ;; negative number. If it is a constant that is less than 2**31, we don't
1365 ;; have to worry about the branches. So make a few subroutines here.
1367 ;; First comes the normal case.
1368 (define_expand "udivmodsi4_normal"
1369 [(set (match_dup 4) (const_int 0))
1370 (parallel [(set (match_operand:SI 0 "" "")
1371 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1373 (zero_extend:DI (match_operand:SI 1 "" "")))
1374 (match_operand:SI 2 "" "")))
1375 (set (match_operand:SI 3 "" "")
1376 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1378 (zero_extend:DI (match_dup 1)))
1382 { operands[4] = gen_reg_rtx (SImode); }")
1384 ;; This handles the branches.
1385 (define_expand "udivmodsi4_tests"
1386 [(set (match_operand:SI 0 "" "") (const_int 0))
1387 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
1388 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
1389 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
1390 (label_ref (match_operand:SI 4 "" "")) (pc)))
1391 (set (match_dup 0) (const_int 1))
1392 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
1393 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
1394 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
1395 (label_ref (match_dup 4)) (pc)))]
1398 { operands[5] = gen_reg_rtx (CCUNSmode);
1399 operands[6] = gen_reg_rtx (CCmode);
1402 (define_expand "udivmodsi4"
1403 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1404 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1405 (match_operand:SI 2 "reg_or_cint_operand" "")))
1406 (set (match_operand:SI 3 "gpc_reg_operand" "")
1407 (umod:SI (match_dup 1) (match_dup 2)))])]
1414 if (! TARGET_POWERPC)
1416 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1417 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1418 emit_insn (gen_divus_call ());
1419 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1420 emit_move_insn (operands[3], gen_rtx (REG, SImode, 4));
1426 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
1428 operands[2] = force_reg (SImode, operands[2]);
1429 label = gen_label_rtx ();
1430 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
1431 operands[3], label));
1434 operands[2] = force_reg (SImode, operands[2]);
1436 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
1444 ;; AIX architecture-independent common-mode multiply (DImode),
1445 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
1446 ;; R4; results in R3 and somtimes R4; link register always clobbered by bla
1447 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
1448 ;; assumed unused if generating common-mode, so ignore.
1449 (define_insn "mulh_call"
1452 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
1453 (sign_extend:DI (reg:SI 4)))
1455 (clobber (match_scratch:SI 0 "=l"))]
1456 "! TARGET_POWER && ! TARGET_POWERPC"
1459 (define_insn "mull_call"
1461 (mult:DI (sign_extend:DI (reg:SI 3))
1462 (sign_extend:DI (reg:SI 4))))
1463 (clobber (match_scratch:SI 0 "=l"))
1464 (clobber (reg:SI 0))]
1465 "! TARGET_POWER && ! TARGET_POWERPC"
1468 (define_insn "divss_call"
1470 (div:SI (reg:SI 3) (reg:SI 4)))
1472 (mod:SI (reg:SI 3) (reg:SI 4)))
1473 (clobber (match_scratch:SI 0 "=l"))
1474 (clobber (reg:SI 0))]
1475 "! TARGET_POWER && ! TARGET_POWERPC"
1478 (define_insn "divus_call"
1480 (udiv:SI (reg:SI 3) (reg:SI 4)))
1482 (umod:SI (reg:SI 3) (reg:SI 4)))
1483 (clobber (match_scratch:SI 0 "=l"))
1484 (clobber (reg:SI 0))]
1485 "! TARGET_POWER && ! TARGET_POWERPC"
1488 (define_insn "quoss_call"
1490 (div:SI (reg:SI 3) (reg:SI 4)))
1491 (clobber (match_scratch:SI 0 "=l"))]
1492 "! TARGET_POWER && ! TARGET_POWERPC"
1495 (define_insn "quous_call"
1497 (udiv:SI (reg:SI 3) (reg:SI 4)))
1498 (clobber (match_scratch:SI 0 "=l"))
1499 (clobber (reg:SI 0))]
1500 "! TARGET_POWER && ! TARGET_POWERPC"
1503 (define_insn "andsi3"
1504 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1505 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1506 (match_operand:SI 2 "and_operand" "?r,L,K,J")))
1507 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
1511 {rlinm|rlwinm} %0,%1,0,%m2,%M2
1512 {andil.|andi.} %0,%1,%b2
1513 {andiu.|andis.} %0,%1,%u2")
1516 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
1517 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1518 (match_operand:SI 2 "and_operand" "r,K,J,L"))
1520 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1524 {andil.|andi.} %3,%1,%b2
1525 {andiu.|andis.} %3,%1,%u2
1526 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2"
1527 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1530 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x")
1531 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1532 (match_operand:SI 2 "and_operand" "r,K,J,L"))
1534 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1535 (and:SI (match_dup 1) (match_dup 2)))]
1539 {andil.|andi.} %0,%1,%b2
1540 {andiu.|andis.} %0,%1,%u2
1541 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2"
1542 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1544 ;; Take a AND with a constant that cannot be done in a single insn and try to
1545 ;; split it into two insns. This does not verify that the insns are valid
1546 ;; since this need not be done as combine will do it.
1549 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1550 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
1551 (match_operand:SI 2 "non_and_cint_operand" "")))]
1553 [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))
1554 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))]
1557 int maskval = INTVAL (operands[2]);
1558 int i, transitions, last_bit_value;
1559 int orig = maskval, first_c = maskval, second_c;
1561 /* We know that MASKVAL must have more than 2 bit-transitions. Start at
1562 the low-order bit and count for the third transition. When we get there,
1563 make a first mask that has everything to the left of that position
1564 a one. Then make the second mask to turn off whatever else is needed. */
1566 for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++)
1568 if (((maskval >>= 1) & 1) != last_bit_value)
1569 last_bit_value ^= 1, transitions++;
1571 if (transitions > 2)
1573 first_c |= (~0) << i;
1578 second_c = orig | ~ first_c;
1580 operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c);
1581 operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c);
1584 (define_insn "iorsi3"
1585 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1586 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
1587 (match_operand:SI 2 "logical_operand" "r,K,J")))]
1591 {oril|ori} %0,%1,%b2
1592 {oriu|oris} %0,%1,%u2")
1595 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1596 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1597 (match_operand:SI 2 "gpc_reg_operand" "r"))
1599 (clobber (match_scratch:SI 3 "=r"))]
1602 [(set_attr "type" "compare")])
1605 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1606 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1607 (match_operand:SI 2 "gpc_reg_operand" "r"))
1609 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1610 (ior:SI (match_dup 1) (match_dup 2)))]
1613 [(set_attr "type" "compare")])
1615 ;; Split an IOR that we can't do in one insn into two insns, each of which
1616 ;; does one 16-bit part. This is used by combine.
1619 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1620 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1621 (match_operand:SI 2 "non_logical_cint_operand" "")))]
1623 [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))
1624 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))]
1627 operands[3] = gen_rtx (CONST_INT, VOIDmode,
1628 INTVAL (operands[2]) & 0xffff0000);
1629 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
1632 (define_insn "xorsi3"
1633 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1634 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
1635 (match_operand:SI 2 "logical_operand" "r,K,J")))]
1639 {xoril|xori} %0,%1,%b2
1640 {xoriu|xoris} %0,%1,%u2")
1643 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1644 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1645 (match_operand:SI 2 "gpc_reg_operand" "r"))
1647 (clobber (match_scratch:SI 3 "=r"))]
1650 [(set_attr "type" "compare")])
1653 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1654 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1655 (match_operand:SI 2 "gpc_reg_operand" "r"))
1657 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1658 (xor:SI (match_dup 1) (match_dup 2)))]
1661 [(set_attr "type" "compare")])
1663 ;; Split an XOR that we can't do in one insn into two insns, each of which
1664 ;; does one 16-bit part. This is used by combine.
1667 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1668 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1669 (match_operand:SI 2 "non_logical_cint_operand" "")))]
1671 [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))
1672 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))]
1675 operands[3] = gen_rtx (CONST_INT, VOIDmode,
1676 INTVAL (operands[2]) & 0xffff0000);
1677 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
1681 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1682 (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1683 (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1688 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1689 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1690 (match_operand:SI 2 "gpc_reg_operand" "r")))
1692 (clobber (match_scratch:SI 3 "=r"))]
1695 [(set_attr "type" "compare")])
1698 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1699 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1700 (match_operand:SI 2 "gpc_reg_operand" "r")))
1702 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1703 (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
1706 [(set_attr "type" "compare")])
1709 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1710 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1711 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1716 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1717 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1718 (match_operand:SI 2 "gpc_reg_operand" "r"))
1720 (clobber (match_scratch:SI 3 "=r"))]
1723 [(set_attr "type" "compare")])
1726 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1727 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1728 (match_operand:SI 2 "gpc_reg_operand" "r"))
1730 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1731 (and:SI (not:SI (match_dup 1)) (match_dup 2)))]
1734 [(set_attr "type" "compare")])
1737 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1738 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1739 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1744 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1745 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1746 (match_operand:SI 2 "gpc_reg_operand" "r"))
1748 (clobber (match_scratch:SI 3 "=r"))]
1751 [(set_attr "type" "compare")])
1754 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1755 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1756 (match_operand:SI 2 "gpc_reg_operand" "r"))
1758 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1759 (ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
1762 [(set_attr "type" "compare")])
1765 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1766 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1767 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1772 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1773 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1774 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1776 (clobber (match_scratch:SI 3 "=r"))]
1779 [(set_attr "type" "compare")])
1782 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1783 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1784 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1786 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1787 (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
1790 [(set_attr "type" "compare")])
1793 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1794 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1795 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1800 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1801 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1802 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1804 (clobber (match_scratch:SI 3 "=r"))]
1807 [(set_attr "type" "compare")])
1810 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1811 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1812 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1814 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1815 (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
1818 [(set_attr "type" "compare")])
1820 ;; maskir insn. We need four forms because things might be in arbitrary
1821 ;; orders. Don't define forms that only set CR fields because these
1822 ;; would modify an input register.
1825 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1826 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1827 (match_operand:SI 1 "gpc_reg_operand" "0"))
1828 (and:SI (match_dup 2)
1829 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
1834 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1835 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1836 (match_operand:SI 1 "gpc_reg_operand" "0"))
1837 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1843 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1844 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1845 (match_operand:SI 3 "gpc_reg_operand" "r"))
1846 (and:SI (not:SI (match_dup 2))
1847 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
1852 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1853 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1854 (match_operand:SI 2 "gpc_reg_operand" "r"))
1855 (and:SI (not:SI (match_dup 2))
1856 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
1861 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1863 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1864 (match_operand:SI 1 "gpc_reg_operand" "0"))
1865 (and:SI (match_dup 2)
1866 (match_operand:SI 3 "gpc_reg_operand" "r")))
1868 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1869 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
1870 (and:SI (match_dup 2) (match_dup 3))))]
1873 [(set_attr "type" "compare")])
1876 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1878 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1879 (match_operand:SI 1 "gpc_reg_operand" "0"))
1880 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1883 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1884 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
1885 (and:SI (match_dup 3) (match_dup 2))))]
1888 [(set_attr "type" "compare")])
1891 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1893 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1894 (match_operand:SI 3 "gpc_reg_operand" "r"))
1895 (and:SI (not:SI (match_dup 2))
1896 (match_operand:SI 1 "gpc_reg_operand" "0")))
1898 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1899 (ior:SI (and:SI (match_dup 2) (match_dup 3))
1900 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
1903 [(set_attr "type" "compare")])
1906 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1908 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1909 (match_operand:SI 2 "gpc_reg_operand" "r"))
1910 (and:SI (not:SI (match_dup 2))
1911 (match_operand:SI 1 "gpc_reg_operand" "0")))
1913 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1914 (ior:SI (and:SI (match_dup 3) (match_dup 2))
1915 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
1918 [(set_attr "type" "compare")])
1920 ;; Rotate and shift insns, in all their variants. These support shifts,
1921 ;; field inserts and extracts, and various combinations thereof.
1923 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1924 (match_operand:SI 1 "const_int_operand" "i")
1925 (match_operand:SI 2 "const_int_operand" "i"))
1926 (match_operand:SI 3 "gpc_reg_operand" "r"))]
1930 int start = INTVAL (operands[2]) & 31;
1931 int size = INTVAL (operands[1]) & 31;
1933 operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size);
1934 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
1935 return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
1939 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1940 (match_operand:SI 1 "const_int_operand" "i")
1941 (match_operand:SI 2 "const_int_operand" "i"))
1942 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1943 (match_operand:SI 4 "const_int_operand" "i")))]
1947 int shift = INTVAL (operands[4]) & 31;
1948 int start = INTVAL (operands[2]) & 31;
1949 int size = INTVAL (operands[1]) & 31;
1951 operands[4] = gen_rtx (CONST_INT, VOIDmode, (shift - start - size) & 31);
1952 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
1953 return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
1957 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1958 (match_operand:SI 1 "const_int_operand" "i")
1959 (match_operand:SI 2 "const_int_operand" "i"))
1960 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1961 (match_operand:SI 4 "const_int_operand" "i")))]
1965 int shift = INTVAL (operands[4]) & 31;
1966 int start = INTVAL (operands[2]) & 31;
1967 int size = INTVAL (operands[1]) & 31;
1969 operands[4] = gen_rtx (CONST_INT, VOIDmode, (32 - shift - start - size) & 31);
1970 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
1971 return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
1975 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1976 (match_operand:SI 1 "const_int_operand" "i")
1977 (match_operand:SI 2 "const_int_operand" "i"))
1978 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1979 (match_operand:SI 4 "const_int_operand" "i")))]
1983 int shift = INTVAL (operands[4]) & 31;
1984 int start = INTVAL (operands[2]) & 31;
1985 int size = INTVAL (operands[1]) & 31;
1987 operands[4] = gen_rtx (CONST_INT, VOIDmode, (32 - shift - start - size) & 31);
1988 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
1989 return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
1993 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1994 (match_operand:SI 1 "const_int_operand" "i")
1995 (match_operand:SI 2 "const_int_operand" "i"))
1996 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1997 (match_operand:SI 4 "const_int_operand" "i")
1998 (match_operand:SI 5 "const_int_operand" "i")))]
1999 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2002 int extract_start = INTVAL (operands[5]) & 31;
2003 int extract_size = INTVAL (operands[4]) & 31;
2004 int insert_start = INTVAL (operands[2]) & 31;
2005 int insert_size = INTVAL (operands[1]) & 31;
2007 /* Align extract field with insert field */
2008 operands[5] = gen_rtx (CONST_INT, VOIDmode,
2009 (extract_start + extract_size - insert_start - insert_size) & 31);
2010 operands[1] = gen_rtx (CONST_INT, VOIDmode, insert_start + insert_size - 1);
2011 return \"{rlimi|rlwimi} %0,%3,%5,%h2,%h1\";
2014 (define_insn "extzv"
2015 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2016 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2017 (match_operand:SI 2 "const_int_operand" "i")
2018 (match_operand:SI 3 "const_int_operand" "i")))]
2022 int start = INTVAL (operands[3]) & 31;
2023 int size = INTVAL (operands[2]) & 31;
2025 if (start + size >= 32)
2026 operands[3] = const0_rtx;
2028 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2029 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
2033 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2034 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2035 (match_operand:SI 2 "const_int_operand" "i")
2036 (match_operand:SI 3 "const_int_operand" "i"))
2038 (clobber (match_scratch:SI 4 "=r"))]
2042 int start = INTVAL (operands[3]) & 31;
2043 int size = INTVAL (operands[2]) & 31;
2045 /* If the bitfield being tested fits in the upper or lower half of a
2046 word, it is possible to use andiu. or andil. to test it. This is
2047 useful because the condition register set-use delay is smaller for
2048 andi[ul]. than for rlinm. This doesn't work when the starting bit
2049 position is 0 because the LT and GT bits may be set wrong. */
2051 if ((start > 0 && start + size <= 16) || start >= 16)
2053 operands[3] = gen_rtx (CONST_INT, VOIDmode,
2054 ((1 << (16 - (start & 15)))
2055 - (1 << (16 - (start & 15) - size))));
2057 return \"{andiu.|andis.} %4,%1,%3\";
2059 return \"{andil.|andi.} %4,%1,%3\";
2062 if (start + size >= 32)
2063 operands[3] = const0_rtx;
2065 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2066 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
2068 [(set_attr "type" "compare")])
2071 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2072 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2073 (match_operand:SI 2 "const_int_operand" "i")
2074 (match_operand:SI 3 "const_int_operand" "i"))
2076 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2077 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
2081 int start = INTVAL (operands[3]) & 31;
2082 int size = INTVAL (operands[2]) & 31;
2084 if (start >= 16 && start + size == 32)
2086 operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1);
2087 return \"{andil.|andi.} %0,%1,%3\";
2090 if (start + size >= 32)
2091 operands[3] = const0_rtx;
2093 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2094 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
2096 [(set_attr "type" "delayed_compare")])
2098 (define_insn "rotlsi3"
2099 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2100 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2101 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2103 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
2106 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2107 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2108 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2110 (clobber (match_scratch:SI 3 "=r"))]
2112 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff"
2113 [(set_attr "type" "delayed_compare")])
2116 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2117 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2118 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2120 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2121 (rotate:SI (match_dup 1) (match_dup 2)))]
2123 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff"
2124 [(set_attr "type" "delayed_compare")])
2127 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2128 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2129 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2130 (match_operand:SI 3 "mask_operand" "L")))]
2132 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
2135 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2137 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2138 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2139 (match_operand:SI 3 "mask_operand" "L"))
2141 (clobber (match_scratch:SI 4 "=r"))]
2143 "{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3"
2144 [(set_attr "type" "delayed_compare")])
2147 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2149 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2150 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2151 (match_operand:SI 3 "mask_operand" "L"))
2153 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2154 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
2156 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3"
2157 [(set_attr "type" "delayed_compare")])
2160 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2163 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2164 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
2166 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
2169 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2170 (compare:CC (zero_extend:SI
2172 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2173 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2175 (clobber (match_scratch:SI 3 "=r"))]
2177 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff"
2178 [(set_attr "type" "delayed_compare")])
2181 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2182 (compare:CC (zero_extend:SI
2184 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2185 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2187 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2188 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
2190 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff"
2191 [(set_attr "type" "delayed_compare")])
2194 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2197 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2198 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
2200 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
2203 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2204 (compare:CC (zero_extend:SI
2206 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2207 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2209 (clobber (match_scratch:SI 3 "=r"))]
2211 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff"
2212 [(set_attr "type" "delayed_compare")])
2215 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2216 (compare:CC (zero_extend:SI
2218 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2219 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2221 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2222 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
2224 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff"
2225 [(set_attr "type" "delayed_compare")])
2227 ;; Note that we use "sle." instead of "sl." so that we can set
2228 ;; SHIFT_COUNT_TRUNCATED.
2230 (define_expand "ashlsi3"
2231 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2232 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2233 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2238 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
2240 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
2244 (define_insn "ashlsi3_power"
2245 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2246 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2247 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
2248 (clobber (match_scratch:SI 3 "=q,X"))]
2252 {sli|slwi} %0,%1,%h2"
2253 [(set_attr "length" "8")])
2255 (define_insn "ashlsi3_no_power"
2256 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2257 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2258 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2261 [(set_attr "length" "8")])
2264 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
2265 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2266 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2268 (clobber (match_scratch:SI 3 "=r,r"))
2269 (clobber (match_scratch:SI 4 "=q,X"))]
2273 {sli.|slwi.} %3,%1,%h2"
2274 [(set_attr "type" "delayed_compare")])
2277 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2278 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2279 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2281 (clobber (match_scratch:SI 3 "=r"))]
2284 [(set_attr "type" "delayed_compare")])
2287 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
2288 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2289 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2291 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2292 (ashift:SI (match_dup 1) (match_dup 2)))
2293 (clobber (match_scratch:SI 4 "=q,X"))]
2297 {sli.|slwi.} %0,%1,%h2"
2298 [(set_attr "type" "delayed_compare")])
2301 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2302 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2303 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2305 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2306 (ashift:SI (match_dup 1) (match_dup 2)))]
2309 [(set_attr "type" "delayed_compare")])
2312 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2313 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2314 (match_operand:SI 2 "const_int_operand" "i"))
2315 (match_operand:SI 3 "mask_operand" "L")))]
2316 "includes_lshift_p (operands[2], operands[3])"
2317 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
2320 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2322 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2323 (match_operand:SI 2 "const_int_operand" "i"))
2324 (match_operand:SI 3 "mask_operand" "L"))
2326 (clobber (match_scratch:SI 4 "=r"))]
2327 "includes_lshift_p (operands[2], operands[3])"
2328 "{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3"
2329 [(set_attr "type" "delayed_compare")])
2332 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2334 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2335 (match_operand:SI 2 "const_int_operand" "i"))
2336 (match_operand:SI 3 "mask_operand" "L"))
2338 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2339 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
2340 "includes_lshift_p (operands[2], operands[3])"
2341 "{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3"
2342 [(set_attr "type" "delayed_compare")])
2344 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
2346 (define_expand "lshrsi3"
2347 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2348 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2349 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2354 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
2356 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
2360 (define_insn "lshrsi3_power"
2361 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2362 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2363 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
2364 (clobber (match_scratch:SI 3 "=q,X"))]
2368 {s%A2i|s%A2wi} %0,%1,%h2")
2370 (define_insn "lshrsi3_no_power"
2371 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2372 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2373 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2378 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
2379 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2380 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2382 (clobber (match_scratch:SI 3 "=r,r"))
2383 (clobber (match_scratch:SI 4 "=q,X"))]
2387 {s%A2i.|s%A2wi.} %3,%1,%h2"
2388 [(set_attr "type" "delayed_compare")])
2391 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2392 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2393 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2395 (clobber (match_scratch:SI 3 "=r"))]
2398 [(set_attr "type" "delayed_compare")])
2401 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
2402 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2403 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2405 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2406 (lshiftrt:SI (match_dup 1) (match_dup 2)))
2407 (clobber (match_scratch:SI 4 "=q,X"))]
2411 {s%A2i.|s%A2wi.} %0,%1,%h2"
2412 [(set_attr "type" "delayed_compare")])
2415 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2416 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2417 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2419 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2420 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
2423 [(set_attr "type" "delayed_compare")])
2426 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2427 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2428 (match_operand:SI 2 "const_int_operand" "i"))
2429 (match_operand:SI 3 "mask_operand" "L")))]
2430 "includes_rshift_p (operands[2], operands[3])"
2431 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
2434 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2436 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2437 (match_operand:SI 2 "const_int_operand" "i"))
2438 (match_operand:SI 3 "mask_operand" "L"))
2440 (clobber (match_scratch:SI 4 "=r"))]
2441 "includes_rshift_p (operands[2], operands[3])"
2442 "{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3"
2443 [(set_attr "type" "delayed_compare")])
2446 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2448 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2449 (match_operand:SI 2 "const_int_operand" "i"))
2450 (match_operand:SI 3 "mask_operand" "L"))
2452 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2453 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
2454 "includes_rshift_p (operands[2], operands[3])"
2455 "{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3"
2456 [(set_attr "type" "delayed_compare")])
2459 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2462 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2463 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
2464 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
2465 "{rlinm|rlwinm} %0,%1,%s2,0xff")
2468 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2472 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2473 (match_operand:SI 2 "const_int_operand" "i")) 0))
2475 (clobber (match_scratch:SI 3 "=r"))]
2476 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
2477 "{rlinm.|rlwinm.} %3,%1,%s2,0xff"
2478 [(set_attr "type" "delayed_compare")])
2481 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2485 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2486 (match_operand:SI 2 "const_int_operand" "i")) 0))
2488 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2489 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
2490 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
2491 "{rlinm.|rlwinm.} %0,%1,%s2,0xff"
2492 [(set_attr "type" "delayed_compare")])
2495 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2498 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2499 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
2500 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
2501 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
2504 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2508 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2509 (match_operand:SI 2 "const_int_operand" "i")) 0))
2511 (clobber (match_scratch:SI 3 "=r"))]
2512 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
2513 "{rlinm.|rlwinm.} %3,%1,%s2,0xffff"
2514 [(set_attr "type" "delayed_compare")])
2517 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2521 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2522 (match_operand:SI 2 "const_int_operand" "i")) 0))
2524 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2525 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
2526 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
2527 "{rlinm.|rlwinm.} %0,%1,%s2,0xffff"
2528 [(set_attr "type" "delayed_compare")])
2531 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2533 (match_operand:SI 1 "gpc_reg_operand" "r"))
2534 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2540 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2542 (match_operand:SI 1 "gpc_reg_operand" "r"))
2543 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2549 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2551 (match_operand:SI 1 "gpc_reg_operand" "r"))
2552 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2558 (define_expand "ashrsi3"
2559 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2560 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
2561 (match_operand:SI 2 "reg_or_cint_operand" "")))]
2566 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
2568 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
2572 (define_insn "ashrsi3_power"
2573 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2574 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2575 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
2576 (clobber (match_scratch:SI 3 "=q,X"))]
2580 {srai|srawi} %0,%1,%h2")
2582 (define_insn "ashrsi3_no_power"
2583 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2584 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2585 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2587 "sraw%I2 %0,%1,%h2")
2590 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
2591 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2592 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2594 (clobber (match_scratch:SI 3 "=r,r"))
2595 (clobber (match_scratch:SI 4 "=q,X"))]
2599 {srai.|srawi.} %3,%1,%h2"
2600 [(set_attr "type" "delayed_compare")])
2603 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2604 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2605 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2607 (clobber (match_scratch:SI 3 "=r"))]
2609 "sraw%I2. %3,%1,%h2"
2610 [(set_attr "type" "delayed_compare")])
2613 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
2614 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2615 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2617 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2618 (ashiftrt:SI (match_dup 1) (match_dup 2)))
2619 (clobber (match_scratch:SI 4 "=q,X"))]
2623 {srai.|srawi.} %0,%1,%h2"
2624 [(set_attr "type" "delayed_compare")])
2627 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2628 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2629 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2631 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2632 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
2634 "sraw%I2. %0,%1,%h2"
2635 [(set_attr "type" "delayed_compare")])
2637 ;; Floating-point insns, excluding normal data motion.
2639 ;; PowerPC has a full set of single-precision floating point instructions.
2641 ;; For the POWER architecture, we pretend that we have both SFmode and
2642 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
2643 ;; The only conversions we will do will be when storing to memory. In that
2644 ;; case, we will use the "frsp" instruction before storing.
2646 ;; Note that when we store into a single-precision memory location, we need to
2647 ;; use the frsp insn first. If the register being stored isn't dead, we
2648 ;; need a scratch register for the frsp. But this is difficult when the store
2649 ;; is done by reload. It is not incorrect to do the frsp on the register in
2650 ;; this case, we just lose precision that we would have otherwise gotten but
2651 ;; is not guaranteed. Perhaps this should be tightened up at some point.
2653 (define_insn "extendsfdf2"
2654 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2655 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2659 if (REGNO (operands[0]) == REGNO (operands[1]))
2662 return \"fmr %0,%1\";
2664 [(set_attr "type" "fp")])
2666 (define_insn "truncdfsf2"
2667 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2668 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
2671 [(set_attr "type" "fp")])
2673 (define_insn "negsf2"
2674 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2675 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2678 [(set_attr "type" "fp")])
2680 (define_insn "abssf2"
2681 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2682 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2685 [(set_attr "type" "fp")])
2688 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2689 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
2692 [(set_attr "type" "fp")])
2694 (define_expand "addsf3"
2695 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2696 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
2697 (match_operand:SF 2 "gpc_reg_operand" "")))]
2702 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2703 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2704 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2705 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2707 [(set_attr "type" "fp")])
2710 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2711 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2712 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2713 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2714 "{fa|fadd} %0,%1,%2"
2715 [(set_attr "type" "fp")])
2717 (define_expand "subsf3"
2718 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2719 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
2720 (match_operand:SF 2 "gpc_reg_operand" "")))]
2725 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2726 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
2727 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2728 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2730 [(set_attr "type" "fp")])
2733 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2734 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
2735 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2736 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2737 "{fs|fsub} %0,%1,%2"
2738 [(set_attr "type" "fp")])
2740 (define_expand "mulsf3"
2741 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2742 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
2743 (match_operand:SF 2 "gpc_reg_operand" "")))]
2748 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2749 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2750 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2751 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2753 [(set_attr "type" "fp")])
2756 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2757 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2758 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2759 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2760 "{fm|fmul} %0,%1,%2"
2761 [(set_attr "type" "fp")])
2763 (define_expand "divsf3"
2764 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2765 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
2766 (match_operand:SF 2 "gpc_reg_operand" "")))]
2771 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2772 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
2773 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2774 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2776 [(set_attr "type" "sdiv")])
2779 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2780 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
2781 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2782 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2783 "{fd|fdiv} %0,%1,%2"
2784 [(set_attr "type" "sdiv")])
2787 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2788 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2789 (match_operand:SF 2 "gpc_reg_operand" "f"))
2790 (match_operand:SF 3 "gpc_reg_operand" "f")))]
2791 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2792 "fmadds %0,%1,%2,%3"
2793 [(set_attr "type" "fp")])
2796 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2797 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2798 (match_operand:SF 2 "gpc_reg_operand" "f"))
2799 (match_operand:SF 3 "gpc_reg_operand" "f")))]
2800 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2801 "{fma|fmadd} %0,%1,%2,%3"
2802 [(set_attr "type" "fp")])
2805 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2806 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2807 (match_operand:SF 2 "gpc_reg_operand" "f"))
2808 (match_operand:SF 3 "gpc_reg_operand" "f")))]
2809 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2810 "fmsubs %0,%1,%2,%3"
2811 [(set_attr "type" "fp")])
2814 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2815 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2816 (match_operand:SF 2 "gpc_reg_operand" "f"))
2817 (match_operand:SF 3 "gpc_reg_operand" "f")))]
2818 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2819 "{fms|fmsub} %0,%1,%2,%3"
2820 [(set_attr "type" "fp")])
2823 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2824 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2825 (match_operand:SF 2 "gpc_reg_operand" "f"))
2826 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
2827 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2828 "fnmadds %0,%1,%2,%3"
2829 [(set_attr "type" "fp")])
2832 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2833 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2834 (match_operand:SF 2 "gpc_reg_operand" "f"))
2835 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
2836 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2837 "{fnma|fnmadd} %0,%1,%2,%3"
2838 [(set_attr "type" "fp")])
2841 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2842 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2843 (match_operand:SF 2 "gpc_reg_operand" "f"))
2844 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
2845 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2846 "fnmsubs %0,%1,%2,%3"
2847 [(set_attr "type" "fp")])
2850 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2851 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2852 (match_operand:SF 2 "gpc_reg_operand" "f"))
2853 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
2854 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2855 "{fnms|fnmsub} %0,%1,%2,%3"
2856 [(set_attr "type" "fp")])
2858 (define_expand "sqrtsf2"
2859 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2860 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
2861 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
2865 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2866 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2867 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT"
2869 [(set_attr "type" "ssqrt")])
2872 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2873 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2874 "TARGET_POWER2 && TARGET_HARD_FLOAT"
2876 [(set_attr "type" "dsqrt")])
2878 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
2879 ;; fsel instruction and some auxiliary computations. Then we just have a
2880 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
2882 (define_expand "maxsf3"
2884 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
2885 (match_operand:SF 2 "gpc_reg_operand" "")))
2886 (set (match_operand:SF 0 "gpc_reg_operand" "")
2887 (if_then_else:SF (ge (match_dup 3)
2891 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
2893 { operands[3] = gen_reg_rtx (SFmode); }")
2896 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2897 (smax:SF (match_operand:SF 1 "gpc_reg_operand" "")
2898 (match_operand:SF 2 "gpc_reg_operand" "")))
2899 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
2900 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
2902 (minus:SF (match_dup 1) (match_dup 2)))
2904 (if_then_else:SF (ge (match_dup 3)
2910 (define_expand "minsf3"
2912 (minus:SF (match_operand:SF 2 "gpc_reg_operand" "")
2913 (match_operand:SF 1 "gpc_reg_operand" "")))
2914 (set (match_operand:SF 0 "gpc_reg_operand" "")
2915 (if_then_else:SF (ge (match_dup 3)
2919 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
2921 { operands[3] = gen_reg_rtx (SFmode); }")
2924 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2925 (smin:SF (match_operand:SF 1 "gpc_reg_operand" "")
2926 (match_operand:SF 2 "gpc_reg_operand" "")))
2927 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
2928 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
2930 (minus:SF (match_dup 2) (match_dup 1)))
2932 (if_then_else:SF (ge (match_dup 3)
2938 (define_expand "movsfcc"
2939 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2940 (if_then_else:SF (match_operand 1 "comparison_operator" "")
2941 (match_operand:SF 2 "gpc_reg_operand" "f")
2942 (match_operand:SF 3 "gpc_reg_operand" "f")))]
2943 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
2947 enum rtx_code code = GET_CODE (operands[1]);
2948 if (! rs6000_compare_fp_p)
2952 case GE: case EQ: case NE:
2953 op0 = rs6000_compare_op0;
2954 op1 = rs6000_compare_op1;
2957 op0 = rs6000_compare_op1;
2958 op1 = rs6000_compare_op0;
2959 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
2962 op0 = rs6000_compare_op1;
2963 op1 = rs6000_compare_op0;
2966 op0 = rs6000_compare_op0;
2967 op1 = rs6000_compare_op1;
2968 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
2973 if (GET_MODE (rs6000_compare_op0) == DFmode)
2975 temp = gen_reg_rtx (DFmode);
2976 emit_insn (gen_subdf3 (temp, op0, op1));
2977 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[2], operands[3]));
2980 emit_insn (gen_negdf2 (temp, temp));
2981 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[0], operands[3]));
2985 emit_insn (gen_negdf2 (temp, temp));
2986 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[3], operands[0]));
2991 temp = gen_reg_rtx (SFmode);
2992 emit_insn (gen_subsf3 (temp, op0, op1));
2993 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[2], operands[3]));
2996 emit_insn (gen_negsf2 (temp, temp));
2997 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[0], operands[3]));
3001 emit_insn (gen_negsf2 (temp, temp));
3002 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[3], operands[0]));
3008 (define_insn "fselsfsf4"
3009 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3010 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
3012 (match_operand:SF 2 "gpc_reg_operand" "f")
3013 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3014 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3016 [(set_attr "type" "fp")])
3018 (define_insn "fseldfsf4"
3019 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3020 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
3022 (match_operand:SF 2 "gpc_reg_operand" "f")
3023 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3024 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3026 [(set_attr "type" "fp")])
3028 (define_insn "negdf2"
3029 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3030 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3033 [(set_attr "type" "fp")])
3035 (define_insn "absdf2"
3036 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3037 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3040 [(set_attr "type" "fp")])
3043 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3044 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
3047 [(set_attr "type" "fp")])
3049 (define_insn "adddf3"
3050 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3051 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3052 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3054 "{fa|fadd} %0,%1,%2"
3055 [(set_attr "type" "fp")])
3057 (define_insn "subdf3"
3058 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3059 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
3060 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3062 "{fs|fsub} %0,%1,%2"
3063 [(set_attr "type" "fp")])
3065 (define_insn "muldf3"
3066 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3067 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3068 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3070 "{fm|fmul} %0,%1,%2"
3071 [(set_attr "type" "dmul")])
3073 (define_insn "divdf3"
3074 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3075 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
3076 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3078 "{fd|fdiv} %0,%1,%2"
3079 [(set_attr "type" "ddiv")])
3082 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3083 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3084 (match_operand:DF 2 "gpc_reg_operand" "f"))
3085 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3087 "{fma|fmadd} %0,%1,%2,%3"
3088 [(set_attr "type" "dmul")])
3091 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3092 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3093 (match_operand:DF 2 "gpc_reg_operand" "f"))
3094 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3096 "{fms|fmsub} %0,%1,%2,%3"
3097 [(set_attr "type" "dmul")])
3100 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3101 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3102 (match_operand:DF 2 "gpc_reg_operand" "f"))
3103 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
3105 "{fnma|fnmadd} %0,%1,%2,%3"
3106 [(set_attr "type" "dmul")])
3109 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3110 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3111 (match_operand:DF 2 "gpc_reg_operand" "f"))
3112 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
3114 "{fnms|fnmsub} %0,%1,%2,%3"
3115 [(set_attr "type" "dmul")])
3117 (define_insn "sqrtdf2"
3118 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3119 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3120 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
3122 [(set_attr "type" "dsqrt")])
3124 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
3125 ;; fsel instruction and some auxiliary computations. Then we just have a
3126 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
3129 (define_expand "maxdf3"
3131 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
3132 (match_operand:DF 2 "gpc_reg_operand" "")))
3133 (set (match_operand:DF 0 "gpc_reg_operand" "")
3134 (if_then_else:DF (ge (match_dup 3)
3138 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3140 { operands[3] = gen_reg_rtx (DFmode); }")
3143 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3144 (smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
3145 (match_operand:DF 2 "gpc_reg_operand" "")))
3146 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
3147 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3149 (minus:DF (match_dup 1) (match_dup 2)))
3151 (if_then_else:DF (ge (match_dup 3)
3157 (define_expand "mindf3"
3159 (minus:DF (match_operand:DF 2 "gpc_reg_operand" "")
3160 (match_operand:DF 1 "gpc_reg_operand" "")))
3161 (set (match_operand:DF 0 "gpc_reg_operand" "")
3162 (if_then_else:DF (ge (match_dup 3)
3166 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3168 { operands[3] = gen_reg_rtx (DFmode); }")
3171 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3172 (smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
3173 (match_operand:DF 2 "gpc_reg_operand" "")))
3174 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
3175 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3177 (minus:DF (match_dup 2) (match_dup 1)))
3179 (if_then_else:DF (ge (match_dup 3)
3185 (define_expand "movdfcc"
3186 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3187 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3188 (match_operand:DF 2 "gpc_reg_operand" "f")
3189 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3190 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3194 enum rtx_code code = GET_CODE (operands[1]);
3195 if (! rs6000_compare_fp_p)
3199 case GE: case EQ: case NE:
3200 op0 = rs6000_compare_op0;
3201 op1 = rs6000_compare_op1;
3204 op0 = rs6000_compare_op1;
3205 op1 = rs6000_compare_op0;
3206 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3209 op0 = rs6000_compare_op1;
3210 op1 = rs6000_compare_op0;
3213 op0 = rs6000_compare_op0;
3214 op1 = rs6000_compare_op1;
3215 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3220 if (GET_MODE (rs6000_compare_op0) == DFmode)
3222 temp = gen_reg_rtx (DFmode);
3223 emit_insn (gen_subdf3 (temp, op0, op1));
3224 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[2], operands[3]));
3227 emit_insn (gen_negdf2 (temp, temp));
3228 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[0], operands[3]));
3232 emit_insn (gen_negdf2 (temp, temp));
3233 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[3], operands[0]));
3238 temp = gen_reg_rtx (SFmode);
3239 emit_insn (gen_subsf3 (temp, op0, op1));
3240 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[2], operands[3]));
3243 emit_insn (gen_negsf2 (temp, temp));
3244 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[0], operands[3]));
3248 emit_insn (gen_negsf2 (temp, temp));
3249 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[3], operands[0]));
3255 (define_insn "fseldfdf4"
3256 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3257 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
3259 (match_operand:DF 2 "gpc_reg_operand" "f")
3260 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3261 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3263 [(set_attr "type" "fp")])
3265 (define_insn "fselsfdf4"
3266 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3267 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
3269 (match_operand:DF 2 "gpc_reg_operand" "f")
3270 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3273 [(set_attr "type" "fp")])
3275 ;; Conversions to and from floating-point.
3276 (define_expand "floatsidf2"
3278 (plus:DI (zero_extend:DI
3279 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3282 (set (match_operand:DF 0 "gpc_reg_operand" "")
3283 (minus:DF (subreg:DF (match_dup 2) 0)
3285 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3288 operands[2] = gen_reg_rtx (DImode);
3289 operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000);
3290 operands[4] = immed_double_const (0, 0x43300000, DImode);
3291 operands[5] = force_reg (DFmode, immed_double_const (0x43300000,
3292 0x80000000, DFmode));
3295 (define_expand "floatunssidf2"
3297 (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
3299 (set (match_operand:DF 0 "gpc_reg_operand" "")
3300 (minus:DF (subreg:DF (match_dup 2) 0)
3302 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3305 operands[2] = gen_reg_rtx (DImode);
3306 operands[3] = immed_double_const (0, 0x43300000, DImode);
3307 operands[4] = force_reg (DFmode, immed_double_const (0x43300000, 0, DFmode));
3310 ;; For the above two cases, we always split.
3312 [(set (match_operand:DI 0 "gpc_reg_operand" "")
3313 (plus:DI (zero_extend:DI
3314 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3315 (match_operand:SI 2 "logical_operand" "")))
3316 (match_operand:DI 3 "low_32_bit_operand" "")))]
3318 [(set (match_dup 6) (xor:SI (match_dup 1) (match_dup 2)))
3319 (set (match_dup 4) (match_dup 5))]
3321 { operands[4] = operand_subword (operands[0], 0, 0, DImode);
3322 operands[5] = operand_subword (operands[3], 0, 0, DImode);
3323 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3327 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3328 (plus:DI (zero_extend:DI
3329 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
3330 (match_operand:SI 2 "logical_operand" "rKJ")))
3331 (match_operand:DI 3 "low_32_bit_operand" "n")))]
3334 [(set_attr "length" "8")])
3337 [(set (match_operand:DI 0 "gpc_reg_operand" "=")
3338 (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
3339 (match_operand:DI 2 "low_32_bit_operand" "")))]
3341 [(set (match_dup 3) (match_dup 4))
3342 (set (match_dup 5) (match_dup 1))]
3344 { operands[3] = operand_subword (operands[0], 0, 0, DImode);
3345 operands[4] = operand_subword (operands[2], 0, 0, DImode);
3346 operands[5] = operand_subword (operands[0], 1, 0, DImode);
3348 if (rtx_equal_p (operands[1], operands[5]))
3350 emit_move_insn (operands[3], operands[4]);
3354 if (rtx_equal_p (operands[1], operands[3]))
3358 temp = operands[3]; operands[3] = operands[5]; operands[5] = temp;
3359 temp = operands[4]; operands[4] = operands[1]; operands[1] = temp;
3364 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3365 (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
3366 (match_operand:DI 2 "low_32_bit_operand" "n")))]
3369 [(set_attr "length" "8")])
3371 (define_expand "fix_truncdfsi2"
3372 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3373 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
3377 if (TARGET_POWER2 || TARGET_POWERPC)
3379 rtx stack_slot = assign_stack_temp (DImode, 8, 0),
3380 temp = gen_reg_rtx (DImode);
3382 emit_insn (gen_fpcvtsi (temp, operands[1]));
3383 emit_move_insn (stack_slot, temp);
3384 emit_move_insn (operands[0],
3385 operand_subword (stack_slot, 1, 0, DImode));
3390 emit_insn (gen_trunc_call (operands[0], operands[1],
3391 gen_rtx (SYMBOL_REF, Pmode, RS6000_ITRUNC)));
3396 (define_insn "fpcvtsi"
3397 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
3399 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))))]
3400 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
3401 "{fcirz|fctiwz} %0,%1"
3402 [(set_attr "type" "fp")])
3404 (define_expand "fixuns_truncdfsi2"
3405 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3406 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
3407 "! TARGET_POWER2 && ! TARGET_POWERPC && TARGET_HARD_FLOAT"
3410 emit_insn (gen_trunc_call (operands[0], operands[1],
3411 gen_rtx (SYMBOL_REF, Pmode, RS6000_UITRUNC)));
3415 (define_expand "trunc_call"
3416 [(parallel [(set (match_operand:SI 0 "" "")
3417 (fix:SI (match_operand:DF 1 "" "")))
3418 (use (match_operand:SI 2 "" ""))])]
3422 rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]);
3423 rtx first = XVECEXP (insns, 0, 0);
3424 rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
3426 REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
3428 REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last));
3434 (define_expand "trunc_call_rtl"
3435 [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" ""))
3437 (parallel [(set (reg:SI 3)
3438 (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
3439 (clobber (scratch:SI))])
3440 (set (match_operand:SI 0 "gpc_reg_operand" "")
3445 rs6000_trunc_used = 1;
3448 (define_insn "floatdidf2"
3449 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3450 (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
3451 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3453 [(set_attr "type" "fp")])
3455 (define_insn "fix_truncdfdi2"
3456 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
3457 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
3458 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3460 [(set_attr "type" "fp")])
3462 ;; Define the DImode operations that can be done in a small number
3464 (define_expand "adddi3"
3465 [(set (match_operand:DI 0 "gpc_reg_operand" "")
3466 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
3467 (match_operand:DI 2 "reg_or_short_operand" "")))]
3471 if (! TARGET_POWER && ! TARGET_POWERPC64
3472 && short_cint_operand (operands[2], DImode))
3477 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3478 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
3479 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
3480 "TARGET_POWER && ! TARGET_POWERPC64"
3482 {a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2
3483 {ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1"
3484 [(set_attr "length" "8")])
3487 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3488 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
3489 (match_operand:DI 2 "gpc_reg_operand" "r")))]
3490 "! TARGET_POWER && ! TARGET_POWERPC64"
3491 "addc %L0,%L1,%L2\;adde %0,%1,%2"
3492 [(set_attr "length" "8")])
3494 (define_expand "subdi3"
3495 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3496 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
3497 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
3501 if (! TARGET_POWER && ! TARGET_POWERPC64
3502 && short_cint_operand (operands[1], DImode))
3507 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3508 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
3509 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
3510 "TARGET_POWER && ! TARGET_POWERPC64"
3512 {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1
3513 {sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2"
3514 [(set_attr "length" "8")])
3517 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3518 (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3519 (match_operand:DI 2 "gpc_reg_operand" "r")))]
3520 "! TARGET_POWER && ! TARGET_POWERPC64"
3521 "subfc %L0,%L2,%L1\;subfe %0,%2,%1"
3522 [(set_attr "length" "8")])
3524 (define_expand "negdi2"
3525 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3526 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
3531 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3532 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
3533 "! TARGET_POWERPC64"
3534 "{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1"
3535 [(set_attr "length" "8")])
3537 (define_expand "mulsidi3"
3538 [(set (match_operand:DI 0 "gpc_reg_operand" "")
3539 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
3540 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
3544 if (! TARGET_POWER && ! TARGET_POWERPC)
3546 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
3547 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
3548 emit_insn (gen_mull_call ());
3549 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
3550 gen_rtx (REG, SImode, 3));
3551 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
3552 gen_rtx (REG, SImode, 4));
3555 else if (TARGET_POWER)
3557 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
3562 (define_insn "mulsidi3_mq"
3563 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3564 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
3565 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
3566 (clobber (match_scratch:SI 3 "=q"))]
3568 "mul %0,%1,%2\;mfmq %L0"
3569 [(set_attr "type" "imul")
3570 (set_attr "length" "8")])
3573 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
3574 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
3575 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
3576 "TARGET_POWERPC && ! TARGET_POWERPC64"
3577 "mulhw %0,%1,%2\;mullw %L0,%1,%2"
3578 [(set_attr "type" "imul")
3579 (set_attr "length" "8")])
3581 (define_expand "smulsi3_highpart"
3582 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3584 (lshiftrt:DI (mult:DI (sign_extend:DI
3585 (match_operand:SI 1 "gpc_reg_operand" "%r"))
3587 (match_operand:SI 2 "gpc_reg_operand" "r")))
3592 if (! TARGET_POWER && ! TARGET_POWERPC)
3594 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
3595 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
3596 emit_insn (gen_mulh_call ());
3597 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
3600 else if (TARGET_POWER)
3602 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
3607 (define_insn "smulsi3_highpart_mq"
3608 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3610 (lshiftrt:DI (mult:DI (sign_extend:DI
3611 (match_operand:SI 1 "gpc_reg_operand" "%r"))
3613 (match_operand:SI 2 "gpc_reg_operand" "r")))
3615 (clobber (match_scratch:SI 3 "=q"))]
3618 [(set_attr "type" "imul")])
3621 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3623 (lshiftrt:DI (mult:DI (sign_extend:DI
3624 (match_operand:SI 1 "gpc_reg_operand" "%r"))
3626 (match_operand:SI 2 "gpc_reg_operand" "r")))
3630 [(set_attr "type" "imul")])
3632 (define_insn "umulsi3_highpart"
3633 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3635 (lshiftrt:DI (mult:DI (zero_extend:DI
3636 (match_operand:SI 1 "gpc_reg_operand" "%r"))
3638 (match_operand:SI 2 "gpc_reg_operand" "r")))
3642 [(set_attr "type" "imul")])
3644 ;; If operands 0 and 2 are in the same register, we have a problem. But
3645 ;; operands 0 and 1 (the usual case) can be in the same register. That's
3646 ;; why we have the strange constraints below.
3647 (define_insn "ashldi3"
3648 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
3649 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
3650 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
3651 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
3654 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
3655 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
3656 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
3657 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
3658 [(set_attr "length" "8")])
3660 (define_insn "lshrdi3"
3661 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r")
3662 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
3663 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
3664 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
3667 {cal %0,0(0)|li %0,0}\;{s%A2i|s%A2wi} %L0,%1,%h2
3668 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
3669 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
3670 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
3671 [(set_attr "length" "8")])
3673 ;; Shift by a variable amount is too complex to be worth open-coding. We
3674 ;; just handle shifts by constants.
3676 (define_expand "ashrdi3"
3677 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "")
3678 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
3679 (match_operand:SI 2 "general_operand" "")))
3680 (clobber (match_scratch:SI 3 ""))])]
3683 { if (GET_CODE (operands[2]) != CONST_INT)
3688 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3689 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
3690 (match_operand:SI 2 "const_int_operand" "M,i")))
3691 (clobber (match_scratch:SI 3 "=X,q"))]
3694 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
3695 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
3696 [(set_attr "length" "8")])
3698 ;; PowerPC64 DImode operations.
3700 (define_insn "ffsdi2"
3701 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
3702 (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
3704 "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
3705 [(set_attr "length" "16")])
3707 (define_insn "muldi3"
3708 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3709 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
3710 (match_operand:DI 2 "gpc_reg_operand" "r")))]
3713 [(set_attr "type" "imul")])
3715 (define_insn "smuldi3_highpart"
3716 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3718 (lshiftrt:TI (mult:TI (sign_extend:TI
3719 (match_operand:DI 1 "gpc_reg_operand" "%r"))
3721 (match_operand:DI 2 "gpc_reg_operand" "r")))
3725 [(set_attr "type" "imul")])
3727 (define_insn "umuldi3_highpart"
3728 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3730 (lshiftrt:TI (mult:TI (zero_extend:TI
3731 (match_operand:DI 1 "gpc_reg_operand" "%r"))
3733 (match_operand:DI 2 "gpc_reg_operand" "r")))
3737 [(set_attr "type" "imul")])
3739 (define_insn "divdi3"
3740 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3741 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3742 (match_operand:DI 2 "gpc_reg_operand" "r")))]
3745 [(set_attr "type" "idiv")])
3747 (define_insn "udivdi3"
3748 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3749 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3750 (match_operand:DI 2 "gpc_reg_operand" "r")))]
3753 [(set_attr "type" "idiv")])
3755 (define_insn "rotldi3"
3756 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3757 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3758 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
3760 "rld%I2cl %0,%1,%h2,0")
3763 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3764 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3765 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
3767 (clobber (match_scratch:DI 3 "=r"))]
3769 "rld%I2cl. %3,%1,%h2,0"
3770 [(set_attr "type" "delayed_compare")])
3773 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
3774 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3775 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
3777 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3778 (rotate:DI (match_dup 1) (match_dup 2)))]
3780 "rld%I2cl. %0,%1,%h2,0"
3781 [(set_attr "type" "delayed_compare")])
3783 ;; Now define ways of moving data around.
3785 ;; For SI, we special-case integers that can't be loaded in one insn. We
3786 ;; do the load 16-bits at a time. We could do this by loading from memory,
3787 ;; and this is even supposed to be faster, but it is simpler not to get
3788 ;; integers in the TOC.
3789 (define_expand "movsi"
3790 [(set (match_operand:SI 0 "general_operand" "")
3791 (match_operand:SI 1 "any_operand" ""))]
3795 if (GET_CODE (operands[0]) != REG)
3796 operands[1] = force_reg (SImode, operands[1]);
3798 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT
3799 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]))
3801 /* If we are to limit the number of things we put in the TOC and
3802 this is a symbol plus a constant we can add in one insn,
3803 just put the sumbol in the TOC and add the constant. Don't do
3804 this if reload is in progress. */
3805 if (GET_CODE (operands[1]) == CONST
3806 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3807 && GET_CODE (XEXP (operands[1], 0)) == PLUS
3808 && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode)
3809 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3810 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3811 && ! side_effects_p (operands[0]))
3813 rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0));
3814 rtx other = XEXP (XEXP (operands[1], 0), 1);
3816 emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other));
3820 operands[1] = force_const_mem (SImode, operands[1]);
3821 if (! memory_address_p (SImode, XEXP (operands[1], 0))
3822 && ! reload_in_progress)
3823 operands[1] = change_address (operands[1], SImode,
3824 XEXP (operands[1], 0));
3827 if (GET_CODE (operands[1]) == CONST_INT
3828 && (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
3829 && (INTVAL (operands[1]) & 0xffff) != 0)
3831 emit_move_insn (operands[0],
3832 gen_rtx (CONST_INT, VOIDmode,
3833 INTVAL (operands[1]) & 0xffff0000));
3834 emit_insn (gen_iorsi3 (operands[0], operands[0],
3835 gen_rtx (CONST_INT, VOIDmode,
3836 INTVAL (operands[1]) & 0xffff)));
3842 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*q,*c*l,*h")
3843 (match_operand:SI 1 "input_operand" "r,m,r,I,J,R,*h,r,r,0"))]
3844 "gpc_reg_operand (operands[0], SImode)
3845 || gpc_reg_operand (operands[1], SImode)"
3848 {l%U1%X1|lwz%U1%X1} %0,%1
3849 {st%U0%X0|stw%U0%X0} %1,%0
3857 [(set_attr "type" "*,load,*,*,*,*,*,*,mtjmpr,*")])
3859 ;; Split a load of a large constant into the appropriate two-insn
3863 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3864 (match_operand:SI 1 "const_int_operand" ""))]
3865 "(unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
3866 && (INTVAL (operands[1]) & 0xffff) != 0"
3870 (ior:SI (match_dup 0)
3874 operands[2] = gen_rtx (CONST_INT, VOIDmode,
3875 INTVAL (operands[1]) & 0xffff0000);
3876 operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff);
3880 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
3881 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
3883 (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
3886 [(set_attr "type" "compare")])
3888 (define_expand "movhi"
3889 [(set (match_operand:HI 0 "general_operand" "")
3890 (match_operand:HI 1 "any_operand" ""))]
3894 if (GET_CODE (operands[0]) != REG)
3895 operands[1] = force_reg (HImode, operands[1]);
3897 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
3899 operands[1] = force_const_mem (HImode, operands[1]);
3900 if (! memory_address_p (HImode, XEXP (operands[1], 0))
3901 && ! reload_in_progress)
3902 operands[1] = change_address (operands[1], HImode,
3903 XEXP (operands[1], 0));
3908 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
3909 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
3910 "gpc_reg_operand (operands[0], HImode)
3911 || gpc_reg_operand (operands[1], HImode)"
3921 [(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")])
3923 (define_expand "movqi"
3924 [(set (match_operand:QI 0 "general_operand" "")
3925 (match_operand:QI 1 "any_operand" ""))]
3929 if (GET_CODE (operands[0]) != REG)
3930 operands[1] = force_reg (QImode, operands[1]);
3932 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
3934 operands[1] = force_const_mem (QImode, operands[1]);
3935 if (! memory_address_p (QImode, XEXP (operands[1], 0))
3936 && ! reload_in_progress)
3937 operands[1] = change_address (operands[1], QImode,
3938 XEXP (operands[1], 0));
3943 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
3944 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
3945 "gpc_reg_operand (operands[0], QImode)
3946 || gpc_reg_operand (operands[1], QImode)"
3956 [(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")])
3958 ;; Here is how to move condition codes around. When we store CC data in
3959 ;; an integer register or memory, we store just the high-order 4 bits.
3960 ;; This lets us not shift in the most common case of CR0.
3961 (define_expand "movcc"
3962 [(set (match_operand:CC 0 "nonimmediate_operand" "")
3963 (match_operand:CC 1 "nonimmediate_operand" ""))]
3968 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
3969 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
3970 "register_operand (operands[0], CCmode)
3971 || register_operand (operands[1], CCmode)"
3975 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
3977 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
3979 {l%U1%X1|lwz%U1%X1} %0,%1
3980 {st%U0%U1|stw%U0%U1} %1,%0"
3981 [(set_attr "type" "*,*,*,compare,*,*,load,*")
3982 (set_attr "length" "*,*,12,*,8,*,*,*")])
3984 ;; For floating-point, we normally deal with the floating-point registers
3985 ;; unless -msoft-float is used. The sole exception is that parameter passing
3986 ;; can produce floating-point values in fixed-point registers. Unless the
3987 ;; value is a simple constant or already in memory, we deal with this by
3988 ;; allocating memory and copying the value explicitly via that memory location.
3989 (define_expand "movsf"
3990 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3991 (match_operand:SF 1 "any_operand" ""))]
3995 /* If we are called from reload, we might be getting a SUBREG of a hard
3996 reg. So expand it. */
3997 if (GET_CODE (operands[0]) == SUBREG
3998 && GET_CODE (SUBREG_REG (operands[0])) == REG
3999 && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
4000 operands[0] = alter_subreg (operands[0]);
4001 if (GET_CODE (operands[1]) == SUBREG
4002 && GET_CODE (SUBREG_REG (operands[1])) == REG
4003 && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
4004 operands[1] = alter_subreg (operands[1]);
4006 if (TARGET_SOFT_FLOAT && GET_CODE (operands[0]) == MEM)
4007 operands[1] = force_reg (SFmode, operands[1]);
4009 else if (TARGET_HARD_FLOAT)
4011 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
4013 /* If this is a store to memory or another integer register do the
4014 move directly. Otherwise store to a temporary stack slot and
4015 load from there into a floating point register. */
4017 if (GET_CODE (operands[0]) == MEM
4018 || (GET_CODE (operands[0]) == REG
4019 && (REGNO (operands[0]) < 32
4020 || (reload_in_progress
4021 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))))
4023 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
4024 operand_subword (operands[1], 0, 0, SFmode));
4029 rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
4031 emit_move_insn (stack_slot, operands[1]);
4032 emit_move_insn (operands[0], stack_slot);
4037 if (GET_CODE (operands[0]) == MEM)
4039 /* If operands[1] is a register, it may have double-precision data
4040 in it, so truncate it to single precision. We need not do
4041 this for POWERPC. */
4042 if (! TARGET_POWERPC && GET_CODE (operands[1]) == REG)
4044 rtx newreg = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
4045 emit_insn (gen_truncdfsf2 (newreg,
4046 gen_rtx (SUBREG, DFmode, operands[1], 0)));
4047 operands[1] = newreg;
4050 operands[1] = force_reg (SFmode, operands[1]);
4053 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
4055 if (GET_CODE (operands[1]) == MEM
4056 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
4057 || GET_CODE (operands[1]) == CONST_DOUBLE
4059 || (GET_CODE (operands[1]) == REG
4060 && (REGNO (operands[1]) < 32
4061 || (reload_in_progress
4062 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))))
4064 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
4065 operand_subword (operands[1], 0, 0, SFmode));
4070 rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
4072 emit_move_insn (stack_slot, operands[1]);
4073 emit_move_insn (operands[0], stack_slot);
4079 if (CONSTANT_P (operands[1]))
4081 operands[1] = force_const_mem (SFmode, operands[1]);
4082 if (! memory_address_p (SFmode, XEXP (operands[1], 0))
4083 && ! reload_in_progress)
4084 operands[1] = change_address (operands[1], SFmode,
4085 XEXP (operands[1], 0));
4090 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4091 (match_operand:SF 1 "easy_fp_constant" ""))]
4092 "reload_completed && REGNO (operands[0]) <= 31"
4093 [(set (match_dup 2) (match_dup 3))]
4095 { operands[2] = operand_subword (operands[0], 0, 0, SFmode);
4096 operands[3] = operand_subword (operands[1], 0, 0, SFmode); }")
4099 [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m")
4100 (match_operand:SF 1 "input_operand" "f,m,f"))]
4101 "(gpc_reg_operand (operands[0], SFmode)
4102 || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT"
4107 [(set_attr "type" "fp,fpload,*")])
4110 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
4111 (match_operand:SF 1 "input_operand" "r,m,r,I,J,R"))]
4112 "(gpc_reg_operand (operands[0], SFmode)
4113 || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT"
4116 {l%U1%X1|lwz%U1%X1} %0,%1
4117 {st%U0%X0|stw%U0%X0} %1,%0
4121 [(set_attr "type" "*,load,*,*,*,*")])
4124 (define_expand "movdf"
4125 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4126 (match_operand:DF 1 "any_operand" ""))]
4130 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4132 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4133 operand_subword_force (operands[1], 1, DFmode));
4134 emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
4135 operand_subword_force (operands[1], 0, DFmode));
4139 if (GET_CODE (operands[0]) != REG)
4140 operands[1] = force_reg (DFmode, operands[1]);
4142 if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode))
4144 operands[1] = force_const_mem (DFmode, operands[1]);
4145 if (! memory_address_p (DFmode, XEXP (operands[1], 0))
4146 && ! reload_in_progress)
4147 operands[1] = change_address (operands[1], DFmode,
4148 XEXP (operands[1], 0));
4153 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4154 (match_operand:DF 1 "easy_fp_constant" ""))]
4155 "reload_completed && REGNO (operands[0]) <= 31"
4156 [(set (match_dup 2) (match_dup 3))
4157 (set (match_dup 4) (match_dup 5))]
4159 { operands[2] = operand_subword (operands[0], 0, 0, DFmode);
4160 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
4161 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
4162 operands[5] = operand_subword (operands[1], 1, 0, DFmode); }")
4164 ;; Don't have reload use general registers to load a constant. First,
4165 ;; it might not work if the output operand has is the equivalent of
4166 ;; a non-offsettable memref, but also it is less efficient than loading
4167 ;; the constant into an FP register, since it will probably be used there.
4168 ;; The "??" is a kludge until we can figure out a more reasonable way
4169 ;; of handling these non-offsettable values.
4171 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m")
4172 (match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))]
4173 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
4174 && (register_operand (operands[0], DFmode)
4175 || register_operand (operands[1], DFmode))"
4178 switch (which_alternative)
4181 /* We normally copy the low-numbered register first. However, if
4182 the first register operand 0 is the same as the second register of
4183 operand 1, we must copy in the opposite order. */
4184 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
4185 return \"mr %L0,%L1\;mr %0,%1\";
4187 return \"mr %0,%1\;mr %L0,%L1\";
4189 /* If the low-address word is used in the address, we must load it
4190 last. Otherwise, load it first. Note that we cannot have
4191 auto-increment in that case since the address register is known to be
4193 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
4195 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
4197 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
4199 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
4203 return \"fmr %0,%1\";
4205 return \"lfd%U1%X1 %0,%1\";
4207 return \"stfd%U0%X0 %1,%0\";
4210 [(set_attr "type" "*,load,*,*,fp,fpload,*")
4211 (set_attr "length" "8,8,8,8,*,*,*")])
4214 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r")
4215 (match_operand:DF 1 "input_operand" "r,o,r,G"))]
4216 "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
4217 && (register_operand (operands[0], DFmode)
4218 || register_operand (operands[1], DFmode))"
4221 switch (which_alternative)
4224 /* We normally copy the low-numbered register first. However, if
4225 the first register operand 0 is the same as the second register of
4226 operand 1, we must copy in the opposite order. */
4227 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
4228 return \"mr %L0,%L1\;mr %0,%1\";
4230 return \"mr %0,%1\;mr %L0,%L1\";
4232 /* If the low-address word is used in the address, we must load it
4233 last. Otherwise, load it first. Note that we cannot have
4234 auto-increment in that case since the address register is known to be
4236 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
4238 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
4240 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
4242 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
4247 [(set_attr "type" "*,load,*,*")
4248 (set_attr "length" "8,8,8,8")])
4251 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m")
4252 (match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))]
4253 "TARGET_POWERPC64 && TARGET_HARD_FLOAT
4254 && (register_operand (operands[0], DFmode)
4255 || register_operand (operands[1], DFmode))"
4264 [(set_attr "type" "*,load,*,*,fp,fpload,*")])
4267 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r")
4268 (match_operand:DF 1 "input_operand" "r,o,r,G"))]
4269 "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
4270 && (register_operand (operands[0], DFmode)
4271 || register_operand (operands[1], DFmode))"
4277 [(set_attr "type" "*,load,*,*")])
4279 ;; Next come the multi-word integer load and store and the load and store
4281 (define_expand "movdi"
4282 [(set (match_operand:DI 0 "general_operand" "")
4283 (match_operand:DI 1 "general_operand" ""))]
4287 if (GET_CODE (operands[1]) == CONST_DOUBLE
4288 || GET_CODE (operands[1]) == CONST_INT)
4290 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
4291 operand_subword (operands[1], 0, 0, DImode));
4292 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
4293 operand_subword (operands[1], 1, 0, DImode));
4297 if (GET_CODE (operands[0]) == MEM)
4298 operands[1] = force_reg (DImode, operands[1]);
4300 /* Stores between FPR and any non-FPR registers must go through a
4301 temporary stack slot. */
4303 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
4304 && ((FP_REGNO_P (REGNO (operands[0]))
4305 && ! FP_REGNO_P (REGNO (operands[1])))
4306 || (FP_REGNO_P (REGNO (operands[1]))
4307 && ! FP_REGNO_P (REGNO (operands[0])))))
4309 rtx stack_slot = assign_stack_temp (DImode, 8, 0);
4311 emit_move_insn (stack_slot, operands[1]);
4312 emit_move_insn (operands[0], stack_slot);
4318 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m")
4319 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f"))]
4320 "! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode)
4321 || gpc_reg_operand (operands[1], DImode))"
4324 switch (which_alternative)
4327 /* We normally copy the low-numbered register first. However, if
4328 the first register operand 0 is the same as the second register of
4329 operand 1, we must copy in the opposite order. */
4330 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
4331 return \"mr %L0,%L1\;mr %0,%1\";
4333 return \"mr %0,%1\;mr %L0,%L1\";
4335 /* If the low-address word is used in the address, we must load it
4336 last. Otherwise, load it first. Note that we cannot have
4337 auto-increment in that case since the address register is known to be
4339 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
4341 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
4343 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
4345 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
4347 return \"fmr %0,%1\";
4349 return \"lfd%U1%X1 %0,%1\";
4351 return \"stfd%U0%X0 %1,%0\";
4354 [(set_attr "type" "*,load,*,fp,fpload,*")
4355 (set_attr "length" "8,8,8,*,*,*")])
4358 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,f,f,m,r,*h")
4359 (match_operand:DI 1 "input_operand" "r,m,r,I,J,R,f,m,f,*h,r"))]
4360 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode)
4361 || gpc_reg_operand (operands[1], DImode))"
4374 [(set_attr "type" "*,load,*,*,*,*,fp,fpload,*,*,mtjmpr")])
4376 ;; TImode is similar, except that we usually want to compute the address into
4377 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
4378 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
4379 (define_expand "movti"
4380 [(parallel [(set (match_operand:TI 0 "general_operand" "")
4381 (match_operand:TI 1 "general_operand" ""))
4382 (clobber (scratch:SI))])]
4383 "TARGET_MULTIPLE || TARGET_POWERPC64"
4386 if (GET_CODE (operands[0]) == MEM)
4387 operands[1] = force_reg (TImode, operands[1]);
4389 if (GET_CODE (operands[0]) == MEM
4390 && GET_CODE (XEXP (operands[0], 0)) != REG
4391 && ! reload_in_progress)
4392 operands[0] = change_address (operands[0], TImode,
4393 copy_addr_to_reg (XEXP (operands[0], 0)));
4395 if (GET_CODE (operands[1]) == MEM
4396 && GET_CODE (XEXP (operands[1], 0)) != REG
4397 && ! reload_in_progress)
4398 operands[1] = change_address (operands[1], TImode,
4399 copy_addr_to_reg (XEXP (operands[1], 0)));
4402 ;; We say that MQ is clobbered in the last alternative because the first
4403 ;; alternative would never get used otherwise since it would need a reload
4404 ;; while the 2nd alternative would not. We put memory cases first so they
4405 ;; are preferred. Otherwise, we'd try to reload the output instead of
4406 ;; giving the SCRATCH mq.
4408 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
4409 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
4410 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
4411 "TARGET_MULTIPLE && TARGET_POWER && ! TARGET_POWERPC64
4412 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
4415 switch (which_alternative)
4421 return \"{stsi|stswi} %1,%P0,16\";
4424 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
4427 /* Normally copy registers with lowest numbered register copied first.
4428 But copy in the other order if the first register of the output
4429 is the second, third, or fourth register in the input. */
4430 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
4431 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
4432 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
4434 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
4436 /* If the address is not used in the output, we can use lsi. Otherwise,
4437 fall through to generating four loads. */
4438 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
4439 return \"{lsi|lswi} %0,%P1,16\";
4440 /* ... fall through ... */
4442 /* If the address register is the same as the register for the lowest-
4443 addressed word, load it last. Similarly for the next two words.
4444 Otherwise load lowest address to highest. */
4445 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
4447 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
4448 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
4449 REGNO (operands[0]) + 2, operands[1], 0))
4450 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
4451 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
4452 REGNO (operands[0]) + 3, operands[1], 0))
4453 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
4455 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
4458 [(set_attr "type" "*,load,load,*,*")
4459 (set_attr "length" "*,16,16,*,16")])
4462 [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
4463 (match_operand:TI 1 "reg_or_mem_operand" "r,r,m"))
4464 (clobber (match_scratch:SI 2 "=X,X,X"))]
4465 "TARGET_MULTIPLE && !TARGET_POWER && ! TARGET_POWERPC64
4466 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
4469 switch (which_alternative)
4475 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
4478 /* Normally copy registers with lowest numbered register copied first.
4479 But copy in the other order if the first register of the output
4480 is the second, third, or fourth register in the input. */
4481 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
4482 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
4483 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
4485 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
4487 /* If the address register is the same as the register for the lowest-
4488 addressed word, load it last. Similarly for the next two words.
4489 Otherwise load lowest address to highest. */
4490 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
4492 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
4493 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
4494 REGNO (operands[0]) + 2, operands[1], 0))
4495 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
4496 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
4497 REGNO (operands[0]) + 3, operands[1], 0))
4498 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
4500 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
4503 [(set_attr "type" "load,*,*")
4504 (set_attr "length" "16,16,16")])
4507 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
4508 (match_operand:TI 1 "input_operand" "r,m,r"))]
4509 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
4510 || gpc_reg_operand (operands[1], TImode))"
4513 switch (which_alternative)
4516 /* We normally copy the low-numbered register first. However, if
4517 the first register operand 0 is the same as the second register of
4518 operand 1, we must copy in the opposite order. */
4519 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
4520 return \"mr %L0,%L1\;mr %0,%1\";
4522 return \"mr %0,%1\;mr %L0,%L1\";
4524 /* If the low-address word is used in the address, we must load it
4525 last. Otherwise, load it first. Note that we cannot have
4526 auto-increment in that case since the address register is known to be
4528 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
4530 return \"ld %L0,%L1\;ld %0,%1\";
4532 return \"ld%U1 %0,%1\;ld %L0,%L1\";
4534 return \"std%U0 %1,%0\;std %L1,%L0\";
4537 [(set_attr "type" "*,load,*")
4538 (set_attr "length" "8,8,8")])
4540 (define_expand "load_multiple"
4541 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
4542 (match_operand:SI 1 "" ""))
4543 (use (match_operand:SI 2 "" ""))])]
4552 /* Support only loading a constant number of fixed-point registers from
4553 memory and only bother with this if more than two; the machine
4554 doesn't support more than eight. */
4555 if (GET_CODE (operands[2]) != CONST_INT
4556 || INTVAL (operands[2]) <= 2
4557 || INTVAL (operands[2]) > 8
4558 || GET_CODE (operands[1]) != MEM
4559 || GET_CODE (operands[0]) != REG
4560 || REGNO (operands[0]) >= 32)
4563 count = INTVAL (operands[2]);
4564 regno = REGNO (operands[0]);
4566 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
4567 from = force_reg (SImode, XEXP (operands[1], 0));
4569 for (i = 0; i < count; i++)
4570 XVECEXP (operands[3], 0, i)
4571 = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
4572 gen_rtx (MEM, SImode, plus_constant (from, i * 4)));
4576 [(match_parallel 0 "load_multiple_operation"
4577 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
4578 (match_operand:SI 2 "indirect_operand" "Q"))])]
4582 /* We have to handle the case where the pseudo used to contain the address
4583 is assigned to one of the output registers. In that case, do the
4584 lsi, but then load the correct value. This is a bit of a mess, but is
4586 We set the length attribute to the maximum possible size (8 bytes). */
4587 static char result[100];
4591 strcpy (result, \"{lsi|lswi} %1,%P2,%N0\");
4592 for (i = 0; i < XVECLEN (operands[0], 0); i++)
4593 if (refers_to_regno_p (REGNO (operands[1]) + i,
4594 REGNO (operands[1]) + i + 1, operands[2], 0))
4596 sprintf (newload, \"\;{l|lwz} %d,%d(%d)\",
4597 REGNO (operands[1]) + i,
4598 i * 4, REGNO (XEXP (operands[2], 0)));
4599 strcat (result, newload);
4604 [(set_attr "type" "load")
4605 (set_attr "length" "8")])
4608 (define_expand "store_multiple"
4609 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
4610 (match_operand:SI 1 "" ""))
4611 (clobber (scratch:SI))
4612 (use (match_operand:SI 2 "" ""))])]
4621 /* Support only storing a constant number of fixed-point registers to
4622 memory and only bother with this if more than two; the machine
4623 doesn't support more than eight. */
4624 if (GET_CODE (operands[2]) != CONST_INT
4625 || INTVAL (operands[2]) <= 2
4626 || INTVAL (operands[2]) > 8
4627 || GET_CODE (operands[0]) != MEM
4628 || GET_CODE (operands[1]) != REG
4629 || REGNO (operands[1]) >= 32)
4632 count = INTVAL (operands[2]);
4633 regno = REGNO (operands[1]);
4635 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1));
4636 to = force_reg (SImode, XEXP (operands[0], 0));
4638 XVECEXP (operands[3], 0, 0)
4639 = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]);
4640 XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode,
4641 gen_rtx (SCRATCH, SImode));
4643 for (i = 1; i < count; i++)
4644 XVECEXP (operands[3], 0, i + 1)
4645 = gen_rtx (SET, VOIDmode,
4646 gen_rtx (MEM, SImode, plus_constant (to, i * 4)),
4647 gen_rtx (REG, SImode, regno + i));
4651 [(match_parallel 0 "store_multiple_operation"
4652 [(set (match_operand:SI 1 "indirect_operand" "=Q")
4653 (match_operand:SI 2 "gpc_reg_operand" "r"))
4654 (clobber (match_scratch:SI 3 "=q"))])]
4655 "TARGET_MULTIPLE && TARGET_POWER"
4656 "{stsi|stswi} %2,%P1,%O0")
4659 [(match_parallel 0 "store_multiple_operation"
4660 [(set (match_operand:SI 1 "indirect_operand" "=Q")
4661 (match_operand:SI 2 "gpc_reg_operand" "r"))
4662 (clobber (match_scratch:SI 3 "X"))])]
4663 "TARGET_MULTIPLE && !TARGET_POWER"
4664 "{stsi|stswi} %2,%P1,%O0")
4666 ;; Define insns that do load or store with update. Some of these we can
4667 ;; get by using pre-decrement or pre-increment, but the hardware can also
4668 ;; do cases where the increment is not the size of the object.
4670 ;; In all these cases, we use operands 0 and 1 for the register being
4671 ;; incremented because those are the operands that local-alloc will
4672 ;; tie and these are the pair most likely to be tieable (and the ones
4673 ;; that will benefit the most).
4676 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
4677 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
4678 (match_operand:DI 2 "reg_or_short_operand" "r,I"))))
4679 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
4680 (plus:DI (match_dup 1) (match_dup 2)))]
4685 [(set_attr "type" "load")])
4688 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
4690 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
4691 (match_operand:DI 2 "gpc_reg_operand" "r")))))
4692 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
4693 (plus:DI (match_dup 1) (match_dup 2)))]
4696 [(set_attr "type" "load")])
4699 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
4700 (match_operand:DI 2 "reg_or_short_operand" "r,I")))
4701 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
4702 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
4703 (plus:DI (match_dup 1) (match_dup 2)))]
4710 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
4711 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4712 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
4713 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4714 (plus:SI (match_dup 1) (match_dup 2)))]
4717 {lux|lwzux} %3,%0,%2
4718 {lu|lwzu} %3,%2(%0)"
4719 [(set_attr "type" "load")])
4722 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4723 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
4724 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
4725 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4726 (plus:SI (match_dup 1) (match_dup 2)))]
4729 {stux|stwux} %3,%0,%2
4730 {stu|stwu} %3,%2(%0)")
4733 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
4734 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4735 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
4736 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4737 (plus:SI (match_dup 1) (match_dup 2)))]
4742 [(set_attr "type" "load")])
4745 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
4747 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4748 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
4749 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4750 (plus:SI (match_dup 1) (match_dup 2)))]
4755 [(set_attr "type" "load")])
4758 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
4760 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4761 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
4762 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4763 (plus:SI (match_dup 1) (match_dup 2)))]
4768 [(set_attr "type" "load")])
4771 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4772 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
4773 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
4774 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4775 (plus:SI (match_dup 1) (match_dup 2)))]
4782 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
4783 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4784 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
4785 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4786 (plus:SI (match_dup 1) (match_dup 2)))]
4791 [(set_attr "type" "load")])
4794 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
4796 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4797 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
4798 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4799 (plus:SI (match_dup 1) (match_dup 2)))]
4804 [(set_attr "type" "load")])
4807 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4808 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
4809 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
4810 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4811 (plus:SI (match_dup 1) (match_dup 2)))]
4818 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
4819 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4820 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
4821 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4822 (plus:SI (match_dup 1) (match_dup 2)))]
4827 [(set_attr "type" "fpload")])
4830 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4831 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
4832 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
4833 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4834 (plus:SI (match_dup 1) (match_dup 2)))]
4841 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
4842 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4843 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
4844 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4845 (plus:SI (match_dup 1) (match_dup 2)))]
4850 [(set_attr "type" "fpload")])
4853 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4854 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
4855 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
4856 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4857 (plus:SI (match_dup 1) (match_dup 2)))]
4863 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
4866 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4867 (match_operand:DF 1 "memory_operand" ""))
4868 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
4869 (match_operand:DF 3 "memory_operand" ""))]
4871 && TARGET_HARD_FLOAT
4872 && registers_ok_for_quad_peep (operands[0], operands[2])
4873 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
4874 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
4878 [(set (match_operand:DF 0 "memory_operand" "")
4879 (match_operand:DF 1 "gpc_reg_operand" "f"))
4880 (set (match_operand:DF 2 "memory_operand" "")
4881 (match_operand:DF 3 "gpc_reg_operand" "f"))]
4883 && TARGET_HARD_FLOAT
4884 && registers_ok_for_quad_peep (operands[1], operands[3])
4885 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
4886 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
4889 ;; Next come insns related to the calling sequence.
4891 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
4892 ;; We move the back-chain and decrement the stack pointer.
4894 (define_expand "allocate_stack"
4896 (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_short_operand" "")))]
4899 { rtx chain = gen_reg_rtx (SImode);
4900 rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx);
4902 emit_move_insn (chain, stack_bot);
4903 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, operands[0]));
4904 emit_move_insn (stack_bot, chain);
4908 ;; These patterns say how to save and restore the stack pointer. We need not
4909 ;; save the stack pointer at function level since we are careful to
4910 ;; preserve the backchain. At block level, we have to restore the backchain
4911 ;; when we restore the stack pointer.
4913 ;; For nonlocal gotos, we must save both the stack pointer and its
4914 ;; backchain and restore both. Note that in the nonlocal case, the
4915 ;; save area is a memory location.
4917 (define_expand "save_stack_function"
4918 [(use (const_int 0))]
4922 (define_expand "restore_stack_function"
4923 [(use (const_int 0))]
4927 (define_expand "restore_stack_block"
4928 [(set (match_dup 2) (mem:SI (match_operand:SI 0 "register_operand" "")))
4929 (set (match_dup 0) (match_operand:SI 1 "register_operand" ""))
4930 (set (mem:SI (match_dup 0)) (match_dup 2))]
4933 { operands[2] = gen_reg_rtx (SImode); }")
4935 (define_expand "save_stack_nonlocal"
4936 [(match_operand:DI 0 "memory_operand" "")
4937 (match_operand:SI 1 "register_operand" "")]
4941 rtx temp = gen_reg_rtx (SImode);
4943 /* Copy the backchain to the first word, sp to the second. */
4944 emit_move_insn (temp, gen_rtx (MEM, SImode, operands[1]));
4945 emit_move_insn (operand_subword (operands[0], 0, 0, DImode), temp);
4946 emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]);
4950 (define_expand "restore_stack_nonlocal"
4951 [(match_operand:SI 0 "register_operand" "")
4952 (match_operand:DI 1 "memory_operand" "")]
4956 rtx temp = gen_reg_rtx (SImode);
4958 /* Restore the backchain from the first word, sp from the second. */
4959 emit_move_insn (temp, operand_subword (operands[1], 0, 0, DImode));
4960 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode));
4961 emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp);
4965 ;; A function pointer is a pointer to a data area whose first word contains
4966 ;; the actual address of the function, whose second word contains a pointer
4967 ;; to its TOC, and whose third word contains a value to place in the static
4968 ;; chain register (r11). Note that if we load the static chain, our
4969 ;; "trampoline" need not have any executable code.
4971 ;; operands[0] is an SImode pseudo in which we place the address of the
4973 ;; operands[1] is the address of data area of the function to call
4975 (define_expand "call_via_ptr"
4976 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4977 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
4978 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
4981 (mem:SI (plus:SI (match_dup 1)
4984 (mem:SI (plus:SI (match_dup 1)
4991 (define_expand "call"
4992 [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" ""))
4993 (match_operand 1 "" ""))
4994 (clobber (scratch:SI))])]
4998 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
5001 operands[0] = XEXP (operands[0], 0);
5002 if (GET_CODE (operands[0]) != SYMBOL_REF)
5004 #ifndef USING_SVR4_H
5005 /* AIX function pointers are really pointers to a three word area */
5006 rtx temp = gen_reg_rtx (SImode);
5008 emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[0])));
5010 #endif /* !USING_SVR4_H */
5014 (define_expand "call_value"
5015 [(parallel [(set (match_operand 0 "" "")
5016 (call (mem:SI (match_operand:SI 1 "address_operand" ""))
5017 (match_operand 2 "" "")))
5018 (clobber (scratch:SI))])]
5022 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
5025 operands[1] = XEXP (operands[1], 0);
5026 if (GET_CODE (operands[1]) != SYMBOL_REF)
5028 #ifndef USING_SVR4_H
5029 /* AIX function pointers are really pointers to a three word area */
5030 rtx temp = gen_reg_rtx (SImode);
5032 emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[1])));
5034 #endif /* !USING_SVR4_H */
5038 ;; Call to function in current module. No TOC pointer reload needed.
5041 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s"))
5042 (match_operand 1 "" "g"))
5043 (clobber (match_scratch:SI 2 "=l"))]
5047 ;; Call to function which may be in another module. Restore the TOC
5048 ;; pointer (r2) after the call unless this is System V.
5051 [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s"))
5052 (match_operand 1 "" "fg,fg"))
5053 (clobber (match_scratch:SI 2 "=l,l"))]
5057 #ifndef USING_SVR4_H
5058 if (GET_CODE (operands[0]) == REG)
5059 return \"{brl|blrl}\;{l|lwz} 2,20(1)\";
5061 return \"bl %z0\;%.\";
5064 if (GET_CODE (operands[0]) == REG)
5065 return \"{brl|blrl}\";
5070 [(set_attr "length" "8")])
5073 [(set (match_operand 0 "" "=fg")
5074 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s"))
5075 (match_operand 2 "" "g")))
5076 (clobber (match_scratch:SI 3 "=l"))]
5081 [(set (match_operand 0 "" "=fg,fg")
5082 (call (mem:SI (match_operand:SI 1 "call_operand" "l,s"))
5083 (match_operand 2 "" "fg,fg")))
5084 (clobber (match_scratch:SI 3 "=l,l"))]
5088 #ifndef USING_SVR4_H
5089 if (GET_CODE (operands[1]) == REG)
5090 return \"{brl|blrl}\;{l|lwz} 2,20(1)\";
5092 return \"bl %z1\;%.\";
5095 if (GET_CODE (operands[1]) == REG)
5096 return \"{brl|blrl}\";
5101 [(set_attr "length" "8")])
5103 ;; Call subroutine returning any type.
5105 (define_expand "untyped_call"
5106 [(parallel [(call (match_operand 0 "" "")
5108 (match_operand 1 "" "")
5109 (match_operand 2 "" "")])]
5115 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
5117 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5119 rtx set = XVECEXP (operands[2], 0, i);
5120 emit_move_insn (SET_DEST (set), SET_SRC (set));
5123 /* The optimizer does not know that the call sets the function value
5124 registers we stored in the result block. We avoid problems by
5125 claiming that all hard registers are used and clobbered at this
5127 emit_insn (gen_blockage ());
5132 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
5133 ;; all of memory. This blocks insns from being moved across this point.
5135 (define_insn "blockage"
5136 [(unspec_volatile [(const_int 0)] 0)]
5140 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
5141 ;; signed & unsigned, and one type of branch.
5143 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
5144 ;; insns, and branches. We store the operands of compares until we see
5146 (define_expand "cmpsi"
5148 (compare (match_operand:SI 0 "gpc_reg_operand" "")
5149 (match_operand:SI 1 "reg_or_short_operand" "")))]
5153 /* Take care of the possibility that operands[1] might be negative but
5154 this might be a logical operation. That insn doesn't exist. */
5155 if (GET_CODE (operands[1]) == CONST_INT
5156 && INTVAL (operands[1]) < 0)
5157 operands[1] = force_reg (SImode, operands[1]);
5159 rs6000_compare_op0 = operands[0];
5160 rs6000_compare_op1 = operands[1];
5161 rs6000_compare_fp_p = 0;
5165 (define_expand "cmpsf"
5166 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
5167 (match_operand:SF 1 "gpc_reg_operand" "")))]
5171 rs6000_compare_op0 = operands[0];
5172 rs6000_compare_op1 = operands[1];
5173 rs6000_compare_fp_p = 1;
5177 (define_expand "cmpdf"
5178 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
5179 (match_operand:DF 1 "gpc_reg_operand" "")))]
5183 rs6000_compare_op0 = operands[0];
5184 rs6000_compare_op1 = operands[1];
5185 rs6000_compare_fp_p = 1;
5189 (define_expand "beq"
5190 [(set (match_dup 2) (match_dup 1))
5192 (if_then_else (eq (match_dup 2)
5194 (label_ref (match_operand 0 "" ""))
5198 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5199 operands[1] = gen_rtx (COMPARE, mode,
5200 rs6000_compare_op0, rs6000_compare_op1);
5201 operands[2] = gen_reg_rtx (mode);
5204 (define_expand "bne"
5205 [(set (match_dup 2) (match_dup 1))
5207 (if_then_else (ne (match_dup 2)
5209 (label_ref (match_operand 0 "" ""))
5213 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5214 operands[1] = gen_rtx (COMPARE, mode,
5215 rs6000_compare_op0, rs6000_compare_op1);
5216 operands[2] = gen_reg_rtx (mode);
5219 (define_expand "blt"
5220 [(set (match_dup 2) (match_dup 1))
5222 (if_then_else (lt (match_dup 2)
5224 (label_ref (match_operand 0 "" ""))
5228 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5229 operands[1] = gen_rtx (COMPARE, mode,
5230 rs6000_compare_op0, rs6000_compare_op1);
5231 operands[2] = gen_reg_rtx (mode);
5234 (define_expand "bgt"
5235 [(set (match_dup 2) (match_dup 1))
5237 (if_then_else (gt (match_dup 2)
5239 (label_ref (match_operand 0 "" ""))
5243 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5244 operands[1] = gen_rtx (COMPARE, mode,
5245 rs6000_compare_op0, rs6000_compare_op1);
5246 operands[2] = gen_reg_rtx (mode);
5249 (define_expand "ble"
5250 [(set (match_dup 2) (match_dup 1))
5252 (if_then_else (le (match_dup 2)
5254 (label_ref (match_operand 0 "" ""))
5258 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5259 operands[1] = gen_rtx (COMPARE, mode,
5260 rs6000_compare_op0, rs6000_compare_op1);
5261 operands[2] = gen_reg_rtx (mode);
5264 (define_expand "bge"
5265 [(set (match_dup 2) (match_dup 1))
5267 (if_then_else (ge (match_dup 2)
5269 (label_ref (match_operand 0 "" ""))
5273 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5274 operands[1] = gen_rtx (COMPARE, mode,
5275 rs6000_compare_op0, rs6000_compare_op1);
5276 operands[2] = gen_reg_rtx (mode);
5279 (define_expand "bgtu"
5280 [(set (match_dup 2) (match_dup 1))
5282 (if_then_else (gtu (match_dup 2)
5284 (label_ref (match_operand 0 "" ""))
5288 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
5289 rs6000_compare_op0, rs6000_compare_op1);
5290 operands[2] = gen_reg_rtx (CCUNSmode);
5293 (define_expand "bltu"
5294 [(set (match_dup 2) (match_dup 1))
5296 (if_then_else (ltu (match_dup 2)
5298 (label_ref (match_operand 0 "" ""))
5302 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
5303 rs6000_compare_op0, rs6000_compare_op1);
5304 operands[2] = gen_reg_rtx (CCUNSmode);
5307 (define_expand "bgeu"
5308 [(set (match_dup 2) (match_dup 1))
5310 (if_then_else (geu (match_dup 2)
5312 (label_ref (match_operand 0 "" ""))
5316 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
5317 rs6000_compare_op0, rs6000_compare_op1);
5318 operands[2] = gen_reg_rtx (CCUNSmode);
5321 (define_expand "bleu"
5322 [(set (match_dup 2) (match_dup 1))
5324 (if_then_else (leu (match_dup 2)
5326 (label_ref (match_operand 0 "" ""))
5330 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
5331 rs6000_compare_op0, rs6000_compare_op1);
5332 operands[2] = gen_reg_rtx (CCUNSmode);
5335 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
5336 ;; For SEQ, likewise, except that comparisons with zero should be done
5337 ;; with an scc insns. However, due to the order that combine see the
5338 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
5339 ;; the cases we don't want to handle.
5340 (define_expand "seq"
5341 [(set (match_dup 2) (match_dup 1))
5342 (set (match_operand:SI 0 "gpc_reg_operand" "")
5343 (eq:SI (match_dup 2) (const_int 0)))]
5346 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5347 operands[1] = gen_rtx (COMPARE, mode,
5348 rs6000_compare_op0, rs6000_compare_op1);
5349 operands[2] = gen_reg_rtx (mode);
5352 (define_expand "sne"
5353 [(set (match_dup 2) (match_dup 1))
5354 (set (match_operand:SI 0 "gpc_reg_operand" "")
5355 (ne:SI (match_dup 2) (const_int 0)))]
5358 { if (! rs6000_compare_fp_p)
5361 operands[1] = gen_rtx (COMPARE, CCFPmode,
5362 rs6000_compare_op0, rs6000_compare_op1);
5363 operands[2] = gen_reg_rtx (CCFPmode);
5366 ;; A > 0 is best done using the portable sequence, so fail in that case.
5367 (define_expand "sgt"
5368 [(set (match_dup 2) (match_dup 1))
5369 (set (match_operand:SI 0 "gpc_reg_operand" "")
5370 (gt:SI (match_dup 2) (const_int 0)))]
5373 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5375 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
5378 operands[1] = gen_rtx (COMPARE, mode,
5379 rs6000_compare_op0, rs6000_compare_op1);
5380 operands[2] = gen_reg_rtx (mode);
5383 ;; A < 0 is best done in the portable way for A an integer.
5384 (define_expand "slt"
5385 [(set (match_dup 2) (match_dup 1))
5386 (set (match_operand:SI 0 "gpc_reg_operand" "")
5387 (lt:SI (match_dup 2) (const_int 0)))]
5390 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5392 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
5395 operands[1] = gen_rtx (COMPARE, mode,
5396 rs6000_compare_op0, rs6000_compare_op1);
5397 operands[2] = gen_reg_rtx (mode);
5400 (define_expand "sge"
5401 [(set (match_dup 2) (match_dup 1))
5402 (set (match_operand:SI 0 "gpc_reg_operand" "")
5403 (ge:SI (match_dup 2) (const_int 0)))]
5406 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5407 operands[1] = gen_rtx (COMPARE, mode,
5408 rs6000_compare_op0, rs6000_compare_op1);
5409 operands[2] = gen_reg_rtx (mode);
5412 ;; A <= 0 is best done the portable way for A an integer.
5413 (define_expand "sle"
5414 [(set (match_dup 2) (match_dup 1))
5415 (set (match_operand:SI 0 "gpc_reg_operand" "")
5416 (le:SI (match_dup 2) (const_int 0)))]
5419 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5421 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
5424 operands[1] = gen_rtx (COMPARE, mode,
5425 rs6000_compare_op0, rs6000_compare_op1);
5426 operands[2] = gen_reg_rtx (mode);
5429 (define_expand "sgtu"
5430 [(set (match_dup 2) (match_dup 1))
5431 (set (match_operand:SI 0 "gpc_reg_operand" "")
5432 (gtu:SI (match_dup 2) (const_int 0)))]
5435 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
5436 rs6000_compare_op0, rs6000_compare_op1);
5437 operands[2] = gen_reg_rtx (CCUNSmode);
5440 (define_expand "sltu"
5441 [(set (match_dup 2) (match_dup 1))
5442 (set (match_operand:SI 0 "gpc_reg_operand" "")
5443 (ltu:SI (match_dup 2) (const_int 0)))]
5446 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
5447 rs6000_compare_op0, rs6000_compare_op1);
5448 operands[2] = gen_reg_rtx (CCUNSmode);
5451 (define_expand "sgeu"
5452 [(set (match_dup 2) (match_dup 1))
5453 (set (match_operand:SI 0 "gpc_reg_operand" "")
5454 (geu:SI (match_dup 2) (const_int 0)))]
5457 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
5458 rs6000_compare_op0, rs6000_compare_op1);
5459 operands[2] = gen_reg_rtx (CCUNSmode);
5462 (define_expand "sleu"
5463 [(set (match_dup 2) (match_dup 1))
5464 (set (match_operand:SI 0 "gpc_reg_operand" "")
5465 (leu:SI (match_dup 2) (const_int 0)))]
5468 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
5469 rs6000_compare_op0, rs6000_compare_op1);
5470 operands[2] = gen_reg_rtx (CCUNSmode);
5473 ;; Here are the actual compare insns.
5475 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
5476 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
5477 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
5479 "{cmp%I2|cmpw%I2} %0,%1,%2"
5480 [(set_attr "type" "compare")])
5482 ;; If we are comparing a register for equality with a large constant,
5483 ;; we can do this with an XOR followed by a compare. But we need a scratch
5484 ;; register for the result of the XOR.
5487 [(set (match_operand:CC 0 "cc_reg_operand" "")
5488 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
5489 (match_operand:SI 2 "non_short_cint_operand" "")))
5490 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
5491 "find_single_use (operands[0], insn, 0)
5492 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
5493 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
5494 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
5495 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
5498 /* Get the constant we are comparing against, C, and see what it looks like
5499 sign-extended to 16 bits. Then see what constant could be XOR'ed
5500 with C to get the sign-extended value. */
5502 int c = INTVAL (operands[2]);
5503 int sextc = (c << 16) >> 16;
5504 int xorv = c ^ sextc;
5506 operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv);
5507 operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc);
5511 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
5512 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
5513 (match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
5515 "{cmpl%I2|cmplw%I2} %0,%1,%W2"
5516 [(set_attr "type" "compare")])
5518 ;; The following two insns don't exist as single insns, but if we provide
5519 ;; them, we can swap an add and compare, which will enable us to overlap more
5520 ;; of the required delay between a compare and branch. We generate code for
5521 ;; them by splitting.
5524 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
5525 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
5526 (match_operand:SI 2 "short_cint_operand" "i")))
5527 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
5528 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
5531 [(set_attr "length" "8")])
5534 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
5535 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
5536 (match_operand:SI 2 "u_short_cint_operand" "i")))
5537 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
5538 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
5541 [(set_attr "length" "8")])
5544 [(set (match_operand:CC 3 "cc_reg_operand" "")
5545 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
5546 (match_operand:SI 2 "short_cint_operand" "")))
5547 (set (match_operand:SI 0 "gpc_reg_operand" "")
5548 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
5550 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
5551 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
5554 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
5555 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
5556 (match_operand:SI 2 "u_short_cint_operand" "")))
5557 (set (match_operand:SI 0 "gpc_reg_operand" "")
5558 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
5560 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
5561 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
5564 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
5565 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
5566 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5569 [(set_attr "type" "fpcompare")])
5572 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
5573 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
5574 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5577 [(set_attr "type" "fpcompare")])
5579 ;; Now we have the scc insns. We can do some combinations because of the
5580 ;; way the machine works.
5582 ;; Note that this is probably faster if we can put an insn between the
5583 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
5584 ;; cases the insns below which don't use an intermediate CR field will
5587 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5588 (match_operator:SI 1 "scc_comparison_operator"
5589 [(match_operand 2 "cc_reg_operand" "y")
5592 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
5593 [(set_attr "length" "12")])
5596 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5597 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
5598 [(match_operand 2 "cc_reg_operand" "y")
5601 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
5602 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
5604 "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1"
5605 [(set_attr "type" "delayed_compare")
5606 (set_attr "length" "12")])
5609 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5610 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
5611 [(match_operand 2 "cc_reg_operand" "y")
5613 (match_operand:SI 3 "const_int_operand" "n")))]
5617 int is_bit = ccr_bit (operands[1], 1);
5618 int put_bit = 31 - (INTVAL (operands[3]) & 31);
5621 if (is_bit >= put_bit)
5622 count = is_bit - put_bit;
5624 count = 32 - (put_bit - is_bit);
5626 operands[4] = gen_rtx (CONST_INT, VOIDmode, count);
5627 operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
5629 return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
5631 [(set_attr "length" "12")])
5634 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5636 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
5637 [(match_operand 2 "cc_reg_operand" "y")
5639 (match_operand:SI 3 "const_int_operand" "n"))
5641 (set (match_operand:SI 4 "gpc_reg_operand" "=r")
5642 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
5647 int is_bit = ccr_bit (operands[1], 1);
5648 int put_bit = 31 - (INTVAL (operands[3]) & 31);
5651 if (is_bit >= put_bit)
5652 count = is_bit - put_bit;
5654 count = 32 - (put_bit - is_bit);
5656 operands[5] = gen_rtx (CONST_INT, VOIDmode, count);
5657 operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit);
5659 return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
5661 [(set_attr "type" "delayed_compare")
5662 (set_attr "length" "12")])
5664 ;; If we are comparing the result of two comparisons, this can be done
5665 ;; using creqv or crxor.
5668 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
5669 (compare:CCEQ (match_operator 1 "scc_comparison_operator"
5670 [(match_operand 2 "cc_reg_operand" "y")
5672 (match_operator 3 "scc_comparison_operator"
5673 [(match_operand 4 "cc_reg_operand" "y")
5675 "REGNO (operands[2]) != REGNO (operands[4])"
5678 enum rtx_code code1, code2;
5680 code1 = GET_CODE (operands[1]);
5681 code2 = GET_CODE (operands[3]);
5683 if ((code1 == EQ || code1 == LT || code1 == GT
5684 || code1 == LTU || code1 == GTU
5685 || (code1 != NE && GET_MODE (operands[2]) == CCFPmode))
5687 (code2 == EQ || code2 == LT || code2 == GT
5688 || code2 == LTU || code2 == GTU
5689 || (code2 != NE && GET_MODE (operands[4]) == CCFPmode)))
5690 return \"%C1%C3crxor %E0,%j1,%j3\";
5692 return \"%C1%C3creqv %E0,%j1,%j3\";
5694 [(set_attr "length" "12")])
5696 ;; There is a 3 cycle delay between consecutive mfcr instructions
5697 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
5700 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5701 (match_operator:SI 1 "scc_comparison_operator"
5702 [(match_operand 2 "cc_reg_operand" "y")
5704 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
5705 (match_operator:SI 4 "scc_comparison_operator"
5706 [(match_operand 5 "cc_reg_operand" "y")
5708 "REGNO (operands[2]) != REGNO (operands[5])"
5709 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
5710 [(set_attr "length" "20")])
5712 ;; There are some scc insns that can be done directly, without a compare.
5713 ;; These are faster because they don't involve the communications between
5714 ;; the FXU and branch units. In fact, we will be replacing all of the
5715 ;; integer scc insns here or in the portable methods in emit_store_flag.
5717 ;; Also support (neg (scc ..)) since that construct is used to replace
5718 ;; branches, (plus (scc ..) ..) since that construct is common and
5719 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
5720 ;; cases where it is no more expensive than (neg (scc ..)).
5722 ;; Have reload force a constant into a register for the simple insns that
5723 ;; otherwise won't accept constants. We do this because it is faster than
5724 ;; the cmp/mfcr sequence we would otherwise generate.
5727 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
5728 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5729 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
5730 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
5733 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
5734 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
5735 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
5736 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
5737 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
5738 [(set_attr "length" "12,8,12,12,12")])
5741 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
5743 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5744 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
5746 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
5747 (eq:SI (match_dup 1) (match_dup 2)))
5748 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
5751 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
5752 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
5753 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
5754 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
5755 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0"
5756 [(set_attr "type" "compare")
5757 (set_attr "length" "12,8,12,12,12")])
5759 ;; We have insns of the form shown by the first define_insn below. If
5760 ;; there is something inside the comparison operation, we must split it.
5762 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5763 (plus:SI (match_operator 1 "comparison_operator"
5764 [(match_operand:SI 2 "" "")
5766 "reg_or_cint_operand" "")])
5767 (match_operand:SI 4 "gpc_reg_operand" "")))
5768 (clobber (match_operand:SI 5 "register_operand" ""))]
5769 "! gpc_reg_operand (operands[2], SImode)"
5770 [(set (match_dup 5) (match_dup 2))
5771 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
5775 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
5776 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5777 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
5778 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
5779 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
5782 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
5783 {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3
5784 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
5785 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
5786 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
5787 [(set_attr "length" "12,8,12,12,12")])
5790 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
5793 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5794 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
5795 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
5797 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
5800 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
5801 {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3
5802 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
5803 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
5804 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
5805 [(set_attr "type" "compare")
5806 (set_attr "length" "12,8,12,12,12")])
5809 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
5812 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5813 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
5814 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
5816 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
5817 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5818 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
5821 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
5822 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
5823 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
5824 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
5825 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
5826 [(set_attr "type" "compare")
5827 (set_attr "length" "12,8,12,12,12")])
5830 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
5831 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5832 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
5835 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
5836 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
5837 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
5838 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
5839 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
5840 [(set_attr "length" "12,8,12,12,12")])
5842 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
5843 ;; since it nabs/sr is just as fast.
5845 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5846 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
5848 (clobber (match_scratch:SI 2 "=&r"))]
5850 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
5851 [(set_attr "length" "8")])
5853 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
5855 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5856 (plus:SI (lshiftrt:SI
5857 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
5859 (match_operand:SI 2 "gpc_reg_operand" "r")))
5860 (clobber (match_scratch:SI 3 "=&r"))]
5862 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
5863 [(set_attr "length" "8")])
5866 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5868 (plus:SI (lshiftrt:SI
5869 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
5871 (match_operand:SI 2 "gpc_reg_operand" "r"))
5873 (clobber (match_scratch:SI 3 "=&r"))]
5875 "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2"
5876 [(set_attr "type" "compare")
5877 (set_attr "length" "8")])
5880 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
5882 (plus:SI (lshiftrt:SI
5883 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
5885 (match_operand:SI 2 "gpc_reg_operand" "r"))
5887 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
5888 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
5890 (clobber (match_scratch:SI 3 "=&r"))]
5892 "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2"
5893 [(set_attr "type" "compare")
5894 (set_attr "length" "8")])
5897 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5898 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5899 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
5900 (clobber (match_scratch:SI 3 "=r,X"))]
5903 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
5904 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
5905 [(set_attr "length" "12")])
5908 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x")
5910 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5911 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
5913 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5914 (le:SI (match_dup 1) (match_dup 2)))
5915 (clobber (match_scratch:SI 3 "=r,X"))]
5918 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
5919 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31"
5920 [(set_attr "type" "compare,delayed_compare")
5921 (set_attr "length" "12")])
5924 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5925 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5926 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
5927 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
5928 (clobber (match_scratch:SI 4 "=&r,&r"))]
5931 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
5932 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3"
5933 [(set_attr "length" "12")])
5936 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
5938 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5939 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
5940 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
5942 (clobber (match_scratch:SI 4 "=&r,&r"))]
5945 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
5946 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3"
5947 [(set_attr "type" "compare")
5948 (set_attr "length" "12")])
5951 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
5953 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5954 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
5955 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
5957 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5958 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5959 (clobber (match_scratch:SI 4 "=&r,&r"))]
5962 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
5963 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3"
5964 [(set_attr "type" "compare")
5965 (set_attr "length" "12")])
5968 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5969 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5970 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
5973 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
5974 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
5975 [(set_attr "length" "12")])
5978 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5979 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5980 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
5982 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
5983 [(set_attr "length" "12")])
5986 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5988 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5989 (match_operand:SI 2 "reg_or_short_operand" "rI"))
5991 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
5992 (leu:SI (match_dup 1) (match_dup 2)))]
5994 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
5995 [(set_attr "type" "compare")
5996 (set_attr "length" "12")])
5999 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6000 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6001 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6002 (match_operand:SI 3 "gpc_reg_operand" "r")))
6003 (clobber (match_scratch:SI 4 "=&r"))]
6005 "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3"
6006 [(set_attr "length" "8")])
6009 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
6011 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6012 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6013 (match_operand:SI 3 "gpc_reg_operand" "r"))
6015 (clobber (match_scratch:SI 4 "=&r"))]
6017 "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3"
6018 [(set_attr "type" "compare")
6019 (set_attr "length" "8")])
6022 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
6024 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6025 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6026 (match_operand:SI 3 "gpc_reg_operand" "r"))
6028 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6029 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
6030 (clobber (match_scratch:SI 4 "=&r"))]
6032 "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3"
6033 [(set_attr "type" "compare")
6034 (set_attr "length" "8")])
6037 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6038 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6039 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
6041 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
6042 [(set_attr "length" "12")])
6045 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6047 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6048 (match_operand:SI 2 "reg_or_short_operand" "rI")))
6049 (match_operand:SI 3 "gpc_reg_operand" "r")))
6050 (clobber (match_scratch:SI 4 "=&r"))]
6052 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
6053 [(set_attr "length" "12")])
6056 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
6059 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6060 (match_operand:SI 2 "reg_or_short_operand" "rI")))
6061 (match_operand:SI 3 "gpc_reg_operand" "r"))
6063 (clobber (match_scratch:SI 4 "=&r"))]
6065 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
6066 [(set_attr "type" "compare")
6067 (set_attr "length" "12")])
6070 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
6073 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6074 (match_operand:SI 2 "reg_or_short_operand" "rI")))
6075 (match_operand:SI 3 "gpc_reg_operand" "r"))
6077 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6078 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
6079 (clobber (match_scratch:SI 4 "=&r"))]
6081 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
6082 [(set_attr "type" "compare")
6083 (set_attr "length" "12")])
6086 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6087 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6088 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
6090 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
6091 [(set_attr "length" "12")])
6094 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
6096 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6097 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6099 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6100 (lt:SI (match_dup 1) (match_dup 2)))]
6102 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31"
6103 [(set_attr "type" "delayed_compare")
6104 (set_attr "length" "12")])
6107 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6108 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6109 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6110 (match_operand:SI 3 "gpc_reg_operand" "r")))
6111 (clobber (match_scratch:SI 4 "=&r"))]
6113 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
6114 [(set_attr "length" "12")])
6117 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
6119 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6120 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6121 (match_operand:SI 3 "gpc_reg_operand" "r"))
6123 (clobber (match_scratch:SI 4 "=&r"))]
6125 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3"
6126 [(set_attr "type" "compare")
6127 (set_attr "length" "12")])
6130 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
6132 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6133 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6134 (match_operand:SI 3 "gpc_reg_operand" "r"))
6136 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6137 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
6138 (clobber (match_scratch:SI 4 "=&r"))]
6140 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3"
6141 [(set_attr "type" "compare")
6142 (set_attr "length" "12")])
6145 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6146 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6147 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
6149 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
6150 [(set_attr "length" "12")])
6153 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6154 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6155 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
6158 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
6159 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
6160 [(set_attr "length" "12")])
6163 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
6165 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6166 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
6168 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6169 (ltu:SI (match_dup 1) (match_dup 2)))]
6172 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
6173 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
6174 [(set_attr "type" "compare")
6175 (set_attr "length" "12")])
6178 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
6179 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
6180 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
6181 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
6182 (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
6185 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
6186 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
6187 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
6188 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
6189 [(set_attr "length" "12")])
6192 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
6194 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6195 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
6196 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6198 (clobber (match_scratch:SI 4 "=&r,&r"))]
6201 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
6202 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3"
6203 [(set_attr "type" "compare")
6204 (set_attr "length" "12")])
6207 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
6209 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6210 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
6211 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6213 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6214 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
6215 (clobber (match_scratch:SI 4 "=&r,&r"))]
6218 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
6219 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
6220 [(set_attr "type" "compare")
6221 (set_attr "length" "12")])
6224 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6225 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6226 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
6229 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
6230 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
6231 [(set_attr "length" "8")])
6234 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6235 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6236 (match_operand:SI 2 "reg_or_short_operand" "rI")))
6237 (clobber (match_scratch:SI 3 "=r"))]
6239 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
6240 [(set_attr "length" "12")])
6243 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
6245 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6246 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6248 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6249 (ge:SI (match_dup 1) (match_dup 2)))
6250 (clobber (match_scratch:SI 3 "=r"))]
6252 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3"
6253 [(set_attr "type" "compare")
6254 (set_attr "length" "12")])
6257 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6258 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6259 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6260 (match_operand:SI 3 "gpc_reg_operand" "r")))
6261 (clobber (match_scratch:SI 4 "=&r"))]
6263 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
6264 [(set_attr "length" "12")])
6267 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
6269 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6270 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6271 (match_operand:SI 3 "gpc_reg_operand" "r"))
6273 (clobber (match_scratch:SI 4 "=&r"))]
6275 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
6276 [(set_attr "type" "compare")
6277 (set_attr "length" "12")])
6280 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
6282 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6283 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6284 (match_operand:SI 3 "gpc_reg_operand" "r"))
6286 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6287 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
6288 (clobber (match_scratch:SI 4 "=&r"))]
6290 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
6291 [(set_attr "type" "compare")
6292 (set_attr "length" "12")])
6295 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6296 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6297 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
6299 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
6300 [(set_attr "length" "12")])
6302 ;; This is (and (neg (ge X (const_int 0))) Y).
6304 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6307 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
6309 (match_operand:SI 2 "gpc_reg_operand" "r")))
6310 (clobber (match_scratch:SI 3 "=&r"))]
6312 "{srai|srawi} %3,%1,31\;andc %0,%2,%3"
6313 [(set_attr "length" "8")])
6316 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
6320 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
6322 (match_operand:SI 2 "gpc_reg_operand" "r"))
6324 (clobber (match_scratch:SI 3 "=&r"))]
6326 "{srai|srawi} %3,%1,31\;andc. %3,%2,%3"
6327 [(set_attr "type" "compare")
6328 (set_attr "length" "8")])
6331 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
6335 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
6337 (match_operand:SI 2 "gpc_reg_operand" "r"))
6339 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6340 (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
6343 (clobber (match_scratch:SI 3 "=&r"))]
6345 "{srai|srawi} %3,%1,31\;andc. %0,%2,%3"
6346 [(set_attr "type" "compare")
6347 (set_attr "length" "8")])
6350 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6351 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6352 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
6355 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
6356 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
6357 [(set_attr "length" "12")])
6360 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
6362 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6363 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
6365 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6366 (geu:SI (match_dup 1) (match_dup 2)))]
6369 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
6370 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
6371 [(set_attr "type" "compare")
6372 (set_attr "length" "12")])
6375 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6376 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6377 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
6378 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
6379 (clobber (match_scratch:SI 4 "=&r,&r"))]
6382 {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3
6383 {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3"
6384 [(set_attr "length" "8")])
6387 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
6389 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6390 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
6391 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6393 (clobber (match_scratch:SI 4 "=&r,&r"))]
6396 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
6397 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
6398 [(set_attr "type" "compare")
6399 (set_attr "length" "8")])
6402 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
6404 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6405 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
6406 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6408 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6409 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
6410 (clobber (match_scratch:SI 4 "=&r,&r"))]
6413 {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
6414 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
6415 [(set_attr "type" "compare")
6416 (set_attr "length" "8")])
6419 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6420 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6421 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
6424 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
6425 {sfi|subfic} %0,%1,-1\;a%I2 %0,%0,%2\;{sfe|subfe} %0,%0,%0"
6426 [(set_attr "length" "12")])
6429 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6431 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6432 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
6433 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
6434 (clobber (match_scratch:SI 4 "=&r,&r"))]
6437 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4
6438 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
6439 [(set_attr "length" "12")])
6442 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
6445 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6446 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
6447 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6449 (clobber (match_scratch:SI 4 "=&r,&r"))]
6452 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
6453 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
6454 [(set_attr "type" "compare")
6455 (set_attr "length" "12")])
6458 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
6461 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6462 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
6463 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6465 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6466 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
6467 (clobber (match_scratch:SI 4 "=&r,&r"))]
6470 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
6471 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
6472 [(set_attr "type" "compare")
6473 (set_attr "length" "12")])
6476 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6477 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6480 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
6481 [(set_attr "length" "12")])
6484 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
6486 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6489 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6490 (gt:SI (match_dup 1) (const_int 0)))]
6492 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31"
6493 [(set_attr "type" "delayed_compare")
6494 (set_attr "length" "12")])
6497 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6498 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6499 (match_operand:SI 2 "reg_or_short_operand" "r")))]
6501 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
6502 [(set_attr "length" "12")])
6505 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
6507 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6508 (match_operand:SI 2 "reg_or_short_operand" "r"))
6510 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6511 (gt:SI (match_dup 1) (match_dup 2)))]
6513 "doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31"
6514 [(set_attr "type" "delayed_compare")
6515 (set_attr "length" "12")])
6518 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6519 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6521 (match_operand:SI 2 "gpc_reg_operand" "r")))
6522 (clobber (match_scratch:SI 3 "=&r"))]
6524 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2"
6525 [(set_attr "length" "12")])
6528 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
6530 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6532 (match_operand:SI 2 "gpc_reg_operand" "r"))
6534 (clobber (match_scratch:SI 3 "=&r"))]
6536 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2"
6537 [(set_attr "type" "compare")
6538 (set_attr "length" "12")])
6541 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
6543 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6545 (match_operand:SI 2 "gpc_reg_operand" "r"))
6547 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6548 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
6549 (clobber (match_scratch:SI 3 "=&r"))]
6551 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2"
6552 [(set_attr "type" "compare")
6553 (set_attr "length" "12")])
6556 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6557 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6558 (match_operand:SI 2 "reg_or_short_operand" "r"))
6559 (match_operand:SI 3 "gpc_reg_operand" "r")))
6560 (clobber (match_scratch:SI 4 "=&r"))]
6562 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
6563 [(set_attr "length" "12")])
6566 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
6568 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6569 (match_operand:SI 2 "reg_or_short_operand" "r"))
6570 (match_operand:SI 3 "gpc_reg_operand" "r"))
6572 (clobber (match_scratch:SI 4 "=&r"))]
6574 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3"
6575 [(set_attr "type" "compare")
6576 (set_attr "length" "12")])
6579 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
6581 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6582 (match_operand:SI 2 "reg_or_short_operand" "r"))
6583 (match_operand:SI 3 "gpc_reg_operand" "r"))
6585 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6586 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
6587 (clobber (match_scratch:SI 4 "=&r"))]
6589 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3"
6590 [(set_attr "type" "compare")
6591 (set_attr "length" "12")])
6594 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6595 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6598 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
6599 [(set_attr "length" "12")])
6602 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6603 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6604 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
6606 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
6607 [(set_attr "length" "12")])
6610 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6611 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6612 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
6614 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
6615 [(set_attr "length" "12")])
6618 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
6620 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6621 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6623 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6624 (gtu:SI (match_dup 1) (match_dup 2)))]
6626 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
6627 [(set_attr "type" "compare")
6628 (set_attr "length" "12")])
6631 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
6632 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
6633 (match_operand:SI 2 "reg_or_short_operand" "I,r,rI"))
6634 (match_operand:SI 3 "reg_or_short_operand" "r,r,I")))
6635 (clobber (match_scratch:SI 4 "=&r,&r,&r"))]
6638 {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
6639 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
6640 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
6641 [(set_attr "length" "8,12,12")])
6644 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
6646 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6647 (match_operand:SI 2 "reg_or_short_operand" "I,r"))
6648 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6650 (clobber (match_scratch:SI 4 "=&r,&r"))]
6653 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
6654 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
6655 [(set_attr "type" "compare")
6656 (set_attr "length" "8,12")])
6659 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
6661 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6662 (match_operand:SI 2 "reg_or_short_operand" "I,r"))
6663 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6665 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6666 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
6667 (clobber (match_scratch:SI 4 "=&r,&r"))]
6670 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
6671 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
6672 [(set_attr "type" "compare")
6673 (set_attr "length" "8,12")])
6676 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6677 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6678 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
6680 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
6681 [(set_attr "length" "8")])
6683 ;; Define both directions of branch and return. If we need a reload
6684 ;; register, we'd rather use CR0 since it is much easier to copy a
6685 ;; register CC value to there.
6689 (if_then_else (match_operator 1 "branch_comparison_operator"
6691 "cc_reg_operand" "x,?y")
6693 (label_ref (match_operand 0 "" ""))
6698 if (get_attr_length (insn) == 8)
6699 return \"%C1bc %t1,%j1,%l0\";
6701 return \"%C1bc %T1,%j1,$+8\;b %l0\";
6703 [(set_attr "type" "branch")])
6707 (if_then_else (match_operator 0 "branch_comparison_operator"
6709 "cc_reg_operand" "x,?y")
6714 "{%C0bcr|%C0bclr} %t0,%j0"
6715 [(set_attr "length" "8")])
6719 (if_then_else (match_operator 1 "branch_comparison_operator"
6721 "cc_reg_operand" "x,?y")
6724 (label_ref (match_operand 0 "" ""))))]
6728 if (get_attr_length (insn) == 8)
6729 return \"%C1bc %T1,%j1,%l0\";
6731 return \"%C1bc %t1,%j1,$+8\;b %l0\";
6733 [(set_attr "type" "branch")])
6737 (if_then_else (match_operator 0 "branch_comparison_operator"
6739 "cc_reg_operand" "x,?y")
6744 "{%C0bcr|%C0bclr} %T0,%j0"
6745 [(set_attr "length" "8")])
6747 ;; Unconditional branch and return.
6751 (label_ref (match_operand 0 "" "")))]
6755 (define_insn "return"
6759 [(set_attr "type" "jmpreg")])
6761 (define_insn "indirect_jump"
6762 [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
6767 [(set_attr "type" "jmpreg")])
6769 ;; Table jump for switch statements:
6770 (define_expand "tablejump"
6772 (plus:SI (match_operand:SI 0 "" "")
6774 (parallel [(set (pc) (match_dup 3))
6775 (use (label_ref (match_operand 1 "" "")))])]
6778 { operands[0] = force_reg (SImode, operands[0]);
6779 operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1]));
6780 operands[3] = gen_reg_rtx (SImode);
6785 (match_operand:SI 0 "register_operand" "c,l"))
6786 (use (label_ref (match_operand 1 "" "")))]
6797 ;; Define the subtract-one-and-jump insns, starting with the template
6798 ;; so loop.c knows what to generate.
6800 (define_expand "decrement_and_branchsi"
6801 [(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "c")
6803 (label_ref (match_operand 1 "" ""))
6805 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))])]
6809 ;; We need to be able to do this for any operand, including MEM, or we
6810 ;; will cause reload to blow up since we don't allow output reloads on
6814 (if_then_else (ne (match_operand:SI 1 "register_operand" "0,*r,*r")
6816 (label_ref (match_operand 2 "" ""))
6818 (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
6819 (plus:SI (match_dup 1) (const_int -1)))
6820 (clobber (match_scratch:CC 3 "=X,&x,&x"))
6821 (clobber (match_scratch:SI 4 "=X,X,r"))]
6825 if (which_alternative != 0)
6827 else if (get_attr_length (insn) == 8)
6828 return \"{bdn|bdnz} %l2\";
6830 return \"bdz $+8\;b %l2\";
6832 [(set_attr "type" "branch")
6833 (set_attr "length" "*,12,16")])
6835 ;; Similar, but we can use GE since we have a REG_NONNEG.
6838 (if_then_else (ge (match_operand:SI 1 "register_operand" "0,*r,*r")
6840 (label_ref (match_operand 2 "" ""))
6842 (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
6843 (plus:SI (match_dup 1) (const_int -1)))
6844 (clobber (match_scratch:CC 3 "=X,&x,&X"))
6845 (clobber (match_scratch:SI 4 "=X,X,r"))]
6846 "find_reg_note (insn, REG_NONNEG, 0)"
6849 if (which_alternative != 0)
6851 else if (get_attr_length (insn) == 8)
6852 return \"{bdn|bdnz} %l2\";
6854 return \"bdz $+8\;b %l2\";
6856 [(set_attr "type" "branch")
6857 (set_attr "length" "*,12,16")])
6861 (if_then_else (eq (match_operand:SI 1 "register_operand" "0,*r,*r")
6863 (label_ref (match_operand 2 "" ""))
6865 (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
6866 (plus:SI (match_dup 1) (const_int -1)))
6867 (clobber (match_scratch:CC 3 "=X,&x,&x"))
6868 (clobber (match_scratch:SI 4 "=X,X,r"))]
6872 if (which_alternative != 0)
6874 else if (get_attr_length (insn) == 8)
6877 return \"{bdn|bdnz} $+8\;b %l2\";
6879 [(set_attr "type" "branch")
6880 (set_attr "length" "*,12,16")])
6884 (if_then_else (match_operator 2 "comparison_operator"
6885 [(match_operand:SI 1 "gpc_reg_operand" "")
6887 (match_operand 5 "" "")
6888 (match_operand 6 "" "")))
6889 (set (match_operand:SI 0 "gpc_reg_operand" "")
6890 (plus:SI (match_dup 1) (const_int -1)))
6891 (clobber (match_scratch:CC 3 ""))
6892 (clobber (match_scratch:SI 4 ""))]
6894 [(parallel [(set (match_dup 3)
6895 (compare:CC (plus:SI (match_dup 1) (const_int -1))
6897 (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))])
6898 (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
6900 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
6905 (if_then_else (match_operator 2 "comparison_operator"
6906 [(match_operand:SI 1 "gpc_reg_operand" "")
6908 (match_operand 5 "" "")
6909 (match_operand 6 "" "")))
6910 (set (match_operand:SI 0 "general_operand" "")
6911 (plus:SI (match_dup 1) (const_int -1)))
6912 (clobber (match_scratch:CC 3 ""))
6913 (clobber (match_scratch:SI 4 ""))]
6914 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
6915 [(parallel [(set (match_dup 3)
6916 (compare:CC (plus:SI (match_dup 1) (const_int -1))
6918 (set (match_dup 4) (plus:SI (match_dup 1) (const_int -1)))])
6919 (set (match_dup 0) (match_dup 4))
6920 (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
6922 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],