1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24 ;; Define an insn type attribute. This is used in function unit delay
26 (define_attr "type" "integer,load,store,fpload,fpstore,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
27 (const_string "integer"))
30 (define_attr "length" ""
31 (if_then_else (eq_attr "type" "branch")
32 (if_then_else (and (ge (minus (pc) (match_dup 0))
34 (lt (minus (pc) (match_dup 0))
40 ;; Processor type -- this attribute must exactly match the processor_type
41 ;; enumeration in rs6000.h.
43 (define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"
44 (const (symbol_ref "rs6000_cpu_attr")))
46 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
47 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
49 ; Load/Store Unit -- pure PowerPC only
50 ; (POWER and 601 use Integer Unit)
51 (define_function_unit "lsu" 1 0
52 (and (eq_attr "type" "load")
53 (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc620"))
56 (define_function_unit "lsu" 1 0
57 (and (eq_attr "type" "store,fpstore")
58 (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc620"))
61 (define_function_unit "lsu" 1 0
62 (and (eq_attr "type" "fpload")
63 (eq_attr "cpu" "mpccore,ppc603"))
66 (define_function_unit "lsu" 1 0
67 (and (eq_attr "type" "fpload")
68 (eq_attr "cpu" "ppc604,ppc620"))
71 (define_function_unit "iu" 1 0
72 (and (eq_attr "type" "load")
73 (eq_attr "cpu" "rios1,ppc403,ppc601"))
76 (define_function_unit "iu" 1 0
77 (and (eq_attr "type" "store,fpstore")
78 (eq_attr "cpu" "rios1,ppc403,ppc601"))
81 (define_function_unit "fpu" 1 0
82 (and (eq_attr "type" "fpstore")
83 (eq_attr "cpu" "rios1,ppc601"))
86 (define_function_unit "iu" 1 0
87 (and (eq_attr "type" "fpload")
88 (eq_attr "cpu" "rios1"))
91 (define_function_unit "iu" 1 0
92 (and (eq_attr "type" "fpload")
93 (eq_attr "cpu" "ppc601"))
96 (define_function_unit "iu2" 2 0
97 (and (eq_attr "type" "load,fpload")
98 (eq_attr "cpu" "rios2"))
101 (define_function_unit "iu2" 2 0
102 (and (eq_attr "type" "store,fpstore")
103 (eq_attr "cpu" "rios2"))
106 ; Integer Unit (RIOS1, PPC601, PPC603)
107 (define_function_unit "iu" 1 0
108 (and (eq_attr "type" "integer")
109 (eq_attr "cpu" "rios1,mpccore,ppc403,ppc601,ppc603"))
112 (define_function_unit "iu" 1 0
113 (and (eq_attr "type" "imul")
114 (eq_attr "cpu" "ppc403"))
117 (define_function_unit "iu" 1 0
118 (and (eq_attr "type" "imul")
119 (eq_attr "cpu" "rios1,ppc601,ppc603"))
122 (define_function_unit "iu" 1 0
123 (and (eq_attr "type" "idiv")
124 (eq_attr "cpu" "rios1"))
127 (define_function_unit "iu" 1 0
128 (and (eq_attr "type" "idiv")
129 (eq_attr "cpu" "ppc403"))
132 (define_function_unit "iu" 1 0
133 (and (eq_attr "type" "idiv")
134 (eq_attr "cpu" "ppc601"))
137 (define_function_unit "iu" 1 0
138 (and (eq_attr "type" "idiv")
139 (eq_attr "cpu" "ppc603"))
142 ; RIOS2 has two integer units: a primary one which can perform all
143 ; operations and a secondary one which is fed in lock step with the first
144 ; and can perform "simple" integer operations.
145 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
146 ; for the complex insns.
147 (define_function_unit "iu2" 2 0
148 (and (eq_attr "type" "integer")
149 (eq_attr "cpu" "rios2"))
152 (define_function_unit "iu2" 2 0
153 (and (eq_attr "type" "imul")
154 (eq_attr "cpu" "rios2"))
157 (define_function_unit "iu2" 2 0
158 (and (eq_attr "type" "idiv")
159 (eq_attr "cpu" "rios2"))
162 (define_function_unit "imuldiv" 1 0
163 (and (eq_attr "type" "imul")
164 (eq_attr "cpu" "rios2"))
167 (define_function_unit "imuldiv" 1 0
168 (and (eq_attr "type" "idiv")
169 (eq_attr "cpu" "rios2"))
172 ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
173 ; Divide latency varies greatly from 2-11, use 6 as average
174 (define_function_unit "imuldiv" 1 0
175 (and (eq_attr "type" "imul")
176 (eq_attr "cpu" "mpccore"))
179 (define_function_unit "imuldiv" 1 0
180 (and (eq_attr "type" "idiv")
181 (eq_attr "cpu" "mpccore"))
184 ; PPC604 has two units that perform integer operations
185 ; and one unit for divide/multiply operations (and move
187 (define_function_unit "iu2" 2 0
188 (and (eq_attr "type" "integer")
189 (eq_attr "cpu" "ppc604,ppc620"))
192 (define_function_unit "imuldiv" 1 0
193 (and (eq_attr "type" "imul")
194 (eq_attr "cpu" "ppc604,ppc620"))
197 (define_function_unit "imuldiv" 1 0
198 (and (eq_attr "type" "idiv")
199 (eq_attr "cpu" "ppc604,ppc620"))
202 ; compare is done on integer unit, but feeds insns which
203 ; execute on the branch unit.
204 (define_function_unit "iu" 1 0
205 (and (eq_attr "type" "compare")
206 (eq_attr "cpu" "rios1"))
209 (define_function_unit "iu" 1 0
210 (and (eq_attr "type" "delayed_compare")
211 (eq_attr "cpu" "rios1"))
214 (define_function_unit "iu" 1 0
215 (and (eq_attr "type" "compare,delayed_compare")
216 (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"))
219 (define_function_unit "iu2" 2 0
220 (and (eq_attr "type" "compare,delayed_compare")
221 (eq_attr "cpu" "rios2"))
224 (define_function_unit "iu2" 2 0
225 (and (eq_attr "type" "compare,delayed_compare")
226 (eq_attr "cpu" "ppc604,ppc620"))
229 ; fp compare uses fp unit
230 (define_function_unit "fpu" 1 0
231 (and (eq_attr "type" "fpcompare")
232 (eq_attr "cpu" "rios1"))
235 ; rios1 and rios2 have different fpcompare delays
236 (define_function_unit "fpu2" 2 0
237 (and (eq_attr "type" "fpcompare")
238 (eq_attr "cpu" "rios2"))
241 ; on ppc601 and ppc603, fpcompare takes also 2 cycles from
243 ; here we do not define delays, just occupy the unit. The dependencies
244 ; will be assigned by the fpcompare definition in the fpu.
245 (define_function_unit "iu" 1 0
246 (and (eq_attr "type" "fpcompare")
247 (eq_attr "cpu" "ppc601,ppc603"))
250 ; fp compare uses fp unit
251 (define_function_unit "fpu" 1 0
252 (and (eq_attr "type" "fpcompare")
253 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
256 (define_function_unit "fpu" 1 0
257 (and (eq_attr "type" "fpcompare")
258 (eq_attr "cpu" "mpccore"))
261 (define_function_unit "bpu" 1 0
262 (and (eq_attr "type" "mtjmpr")
263 (eq_attr "cpu" "rios1,rios2"))
266 (define_function_unit "bpu" 1 0
267 (and (eq_attr "type" "mtjmpr")
268 (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"))
271 ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
272 (define_function_unit "bpu" 1 0
273 (eq_attr "type" "jmpreg")
276 (define_function_unit "bpu" 1 0
277 (eq_attr "type" "branch")
280 ; Floating Point Unit
281 (define_function_unit "fpu" 1 0
282 (and (eq_attr "type" "fp,dmul")
283 (eq_attr "cpu" "rios1"))
286 (define_function_unit "fpu" 1 0
287 (and (eq_attr "type" "fp")
288 (eq_attr "cpu" "mpccore"))
291 (define_function_unit "fpu" 1 0
292 (and (eq_attr "type" "fp")
293 (eq_attr "cpu" "ppc601"))
296 (define_function_unit "fpu" 1 0
297 (and (eq_attr "type" "fp")
298 (eq_attr "cpu" "ppc603,ppc604,ppc620"))
301 (define_function_unit "fpu" 1 0
302 (and (eq_attr "type" "dmul")
303 (eq_attr "cpu" "mpccore"))
306 (define_function_unit "fpu" 1 0
307 (and (eq_attr "type" "dmul")
308 (eq_attr "cpu" "ppc601"))
312 (define_function_unit "fpu" 1 0
313 (and (eq_attr "type" "dmul")
314 (eq_attr "cpu" "ppc603"))
317 (define_function_unit "fpu" 1 0
318 (and (eq_attr "type" "dmul")
319 (eq_attr "cpu" "ppc604,ppc620"))
322 (define_function_unit "fpu" 1 0
323 (and (eq_attr "type" "sdiv,ddiv")
324 (eq_attr "cpu" "rios1"))
327 (define_function_unit "fpu" 1 0
328 (and (eq_attr "type" "sdiv")
329 (eq_attr "cpu" "ppc601"))
332 (define_function_unit "fpu" 1 0
333 (and (eq_attr "type" "sdiv")
334 (eq_attr "cpu" "mpccore"))
337 (define_function_unit "fpu" 1 0
338 (and (eq_attr "type" "sdiv")
339 (eq_attr "cpu" "ppc603,ppc604,ppc620"))
342 (define_function_unit "fpu" 1 0
343 (and (eq_attr "type" "ddiv")
344 (eq_attr "cpu" "mpccore"))
347 (define_function_unit "fpu" 1 0
348 (and (eq_attr "type" "ddiv")
349 (eq_attr "cpu" "ppc601,ppc604,ppc620"))
352 (define_function_unit "fpu" 1 0
353 (and (eq_attr "type" "ddiv")
354 (eq_attr "cpu" "ppc603"))
357 (define_function_unit "fpu" 1 0
358 (and (eq_attr "type" "ssqrt")
359 (eq_attr "cpu" "ppc620"))
362 (define_function_unit "fpu" 1 0
363 (and (eq_attr "type" "dsqrt")
364 (eq_attr "cpu" "ppc620"))
367 ; RIOS2 has two symmetric FPUs.
368 (define_function_unit "fpu2" 2 0
369 (and (eq_attr "type" "fp")
370 (eq_attr "cpu" "rios2"))
373 (define_function_unit "fpu2" 2 0
374 (and (eq_attr "type" "dmul")
375 (eq_attr "cpu" "rios2"))
378 (define_function_unit "fpu2" 2 0
379 (and (eq_attr "type" "sdiv,ddiv")
380 (eq_attr "cpu" "rios2"))
383 (define_function_unit "fpu2" 2 0
384 (and (eq_attr "type" "ssqrt,dsqrt")
385 (eq_attr "cpu" "rios2"))
389 ;; Start with fixed-point load and store insns. Here we put only the more
390 ;; complex forms. Basic data transfer is done later.
392 (define_expand "zero_extendqidi2"
393 [(set (match_operand:DI 0 "gpc_reg_operand" "")
394 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
399 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
400 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
405 [(set_attr "type" "load,*")])
408 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
409 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
411 (clobber (match_scratch:DI 2 "=r"))]
414 [(set_attr "type" "compare")])
417 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
418 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
420 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
421 (zero_extend:DI (match_dup 1)))]
424 [(set_attr "type" "compare")])
426 (define_insn "extendqidi2"
427 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
428 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
433 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
434 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
436 (clobber (match_scratch:DI 2 "=r"))]
439 [(set_attr "type" "compare")])
442 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
443 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
445 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
446 (sign_extend:DI (match_dup 1)))]
449 [(set_attr "type" "compare")])
451 (define_expand "zero_extendhidi2"
452 [(set (match_operand:DI 0 "gpc_reg_operand" "")
453 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
458 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
459 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
464 [(set_attr "type" "load,*")])
467 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
468 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
470 (clobber (match_scratch:DI 2 "=r"))]
473 [(set_attr "type" "compare")])
476 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
477 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
479 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
480 (zero_extend:DI (match_dup 1)))]
483 [(set_attr "type" "compare")])
485 (define_expand "extendhidi2"
486 [(set (match_operand:DI 0 "gpc_reg_operand" "")
487 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
492 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
493 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
498 [(set_attr "type" "load,*")])
501 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
502 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
504 (clobber (match_scratch:DI 2 "=r"))]
507 [(set_attr "type" "compare")])
510 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
511 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
513 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
514 (sign_extend:DI (match_dup 1)))]
517 [(set_attr "type" "compare")])
519 (define_expand "zero_extendsidi2"
520 [(set (match_operand:DI 0 "gpc_reg_operand" "")
521 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
526 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
527 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
532 [(set_attr "type" "load,*")])
535 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
536 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
538 (clobber (match_scratch:DI 2 "=r"))]
541 [(set_attr "type" "compare")])
544 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
545 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
547 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
548 (zero_extend:DI (match_dup 1)))]
551 [(set_attr "type" "compare")])
553 (define_expand "extendsidi2"
554 [(set (match_operand:DI 0 "gpc_reg_operand" "")
555 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
560 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
561 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
566 [(set_attr "type" "load,*")])
569 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
570 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
572 (clobber (match_scratch:DI 2 "=r"))]
575 [(set_attr "type" "compare")])
578 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
579 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
581 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
582 (sign_extend:DI (match_dup 1)))]
585 [(set_attr "type" "compare")])
587 (define_expand "zero_extendqisi2"
588 [(set (match_operand:SI 0 "gpc_reg_operand" "")
589 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
594 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
595 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
599 {rlinm|rlwinm} %0,%1,0,0xff"
600 [(set_attr "type" "load,*")])
603 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
604 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
606 (clobber (match_scratch:SI 2 "=r"))]
608 "{andil.|andi.} %2,%1,0xff"
609 [(set_attr "type" "compare")])
612 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
613 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
615 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
616 (zero_extend:SI (match_dup 1)))]
618 "{andil.|andi.} %0,%1,0xff"
619 [(set_attr "type" "compare")])
621 (define_expand "extendqisi2"
622 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
623 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
628 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
629 else if (TARGET_POWER)
630 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
632 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
636 (define_insn "extendqisi2_ppc"
637 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
638 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
643 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
644 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
646 (clobber (match_scratch:SI 2 "=r"))]
649 [(set_attr "type" "compare")])
652 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
653 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
655 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
656 (sign_extend:SI (match_dup 1)))]
659 [(set_attr "type" "compare")])
661 (define_expand "extendqisi2_power"
662 [(parallel [(set (match_dup 2)
663 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
665 (clobber (scratch:SI))])
666 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
667 (ashiftrt:SI (match_dup 2)
669 (clobber (scratch:SI))])]
672 { operands[1] = gen_lowpart (SImode, operands[1]);
673 operands[2] = gen_reg_rtx (SImode); }")
675 (define_expand "extendqisi2_no_power"
677 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
679 (set (match_operand:SI 0 "gpc_reg_operand" "")
680 (ashiftrt:SI (match_dup 2)
682 "! TARGET_POWER && ! TARGET_POWERPC"
684 { operands[1] = gen_lowpart (SImode, operands[1]);
685 operands[2] = gen_reg_rtx (SImode); }")
687 (define_expand "zero_extendqihi2"
688 [(set (match_operand:HI 0 "gpc_reg_operand" "")
689 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
694 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
695 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
699 {rlinm|rlwinm} %0,%1,0,0xff"
700 [(set_attr "type" "load,*")])
703 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
704 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
706 (clobber (match_scratch:HI 2 "=r"))]
708 "{andil.|andi.} %2,%1,0xff"
709 [(set_attr "type" "compare")])
712 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
713 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
715 (set (match_operand:HI 0 "gpc_reg_operand" "=r")
716 (zero_extend:HI (match_dup 1)))]
718 "{andil.|andi.} %0,%1,0xff"
719 [(set_attr "type" "compare")])
721 (define_expand "extendqihi2"
722 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
723 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
728 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
729 else if (TARGET_POWER)
730 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
732 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
736 (define_insn "extendqihi2_ppc"
737 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
738 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
743 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
744 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
746 (clobber (match_scratch:HI 2 "=r"))]
749 [(set_attr "type" "compare")])
752 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
753 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
755 (set (match_operand:HI 0 "gpc_reg_operand" "=r")
756 (sign_extend:HI (match_dup 1)))]
759 [(set_attr "type" "compare")])
761 (define_expand "extendqihi2_power"
762 [(parallel [(set (match_dup 2)
763 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
765 (clobber (scratch:SI))])
766 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
767 (ashiftrt:SI (match_dup 2)
769 (clobber (scratch:SI))])]
772 { operands[0] = gen_lowpart (SImode, operands[0]);
773 operands[1] = gen_lowpart (SImode, operands[1]);
774 operands[2] = gen_reg_rtx (SImode); }")
776 (define_expand "extendqihi2_no_power"
778 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
780 (set (match_operand:HI 0 "gpc_reg_operand" "")
781 (ashiftrt:SI (match_dup 2)
783 "! TARGET_POWER && ! TARGET_POWERPC"
785 { operands[0] = gen_lowpart (SImode, operands[0]);
786 operands[1] = gen_lowpart (SImode, operands[1]);
787 operands[2] = gen_reg_rtx (SImode); }")
789 (define_expand "zero_extendhisi2"
790 [(set (match_operand:SI 0 "gpc_reg_operand" "")
791 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
796 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
797 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
801 {rlinm|rlwinm} %0,%1,0,0xffff"
802 [(set_attr "type" "load,*")])
805 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
806 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
808 (clobber (match_scratch:SI 2 "=r"))]
810 "{andil.|andi.} %2,%1,0xffff"
811 [(set_attr "type" "compare")])
814 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
815 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
817 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
818 (zero_extend:SI (match_dup 1)))]
820 "{andil.|andi.} %0,%1,0xffff"
821 [(set_attr "type" "compare")])
823 (define_expand "extendhisi2"
824 [(set (match_operand:SI 0 "gpc_reg_operand" "")
825 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
830 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
831 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
836 [(set_attr "type" "load,*")])
839 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
840 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
842 (clobber (match_scratch:SI 2 "=r"))]
844 "{exts.|extsh.} %2,%1"
845 [(set_attr "type" "compare")])
848 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
849 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
851 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
852 (sign_extend:SI (match_dup 1)))]
854 "{exts.|extsh.} %0,%1"
855 [(set_attr "type" "compare")])
857 ;; Fixed-point arithmetic insns.
859 ;; Discourage ai/addic because of carry but provide it in an alternative
860 ;; allowing register zero as source.
861 (define_insn "addsi3"
862 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
863 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
864 (match_operand:SI 2 "add_operand" "r,I,I,J")))]
868 {cal %0,%2(%1)|addi %0,%1,%2}
870 {cau|addis} %0,%1,%v2")
873 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
874 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
875 (match_operand:SI 2 "reg_or_short_operand" "r,I"))
877 (clobber (match_scratch:SI 3 "=r,r"))]
881 {ai.|addic.} %3,%1,%2"
882 [(set_attr "type" "compare")])
885 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
886 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
887 (match_operand:SI 2 "reg_or_short_operand" "r,I"))
889 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
890 (plus:SI (match_dup 1) (match_dup 2)))]
894 {ai.|addic.} %0,%1,%2"
895 [(set_attr "type" "compare")])
897 ;; Split an add that we can't do in one insn into two insns, each of which
898 ;; does one 16-bit part. This is used by combine. Note that the low-order
899 ;; add should be last in case the result gets used in an address.
902 [(set (match_operand:SI 0 "gpc_reg_operand" "")
903 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
904 (match_operand:SI 2 "non_add_cint_operand" "")))]
906 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
907 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
910 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
911 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
914 high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
916 operands[3] = GEN_INT (high);
917 operands[4] = GEN_INT (low);
920 (define_insn "one_cmplsi2"
921 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
922 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
927 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
928 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
930 (clobber (match_scratch:SI 2 "=r"))]
933 [(set_attr "type" "compare")])
936 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
937 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
939 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
940 (not:SI (match_dup 1)))]
943 [(set_attr "type" "compare")])
946 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
947 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
948 (match_operand:SI 2 "gpc_reg_operand" "r")))]
950 "{sf%I1|subf%I1c} %0,%2,%1")
953 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
954 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
955 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
962 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
963 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
964 (match_operand:SI 2 "gpc_reg_operand" "r"))
966 (clobber (match_scratch:SI 3 "=r"))]
968 "{sf.|subfc.} %3,%2,%1"
969 [(set_attr "type" "compare")])
972 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
973 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
974 (match_operand:SI 2 "gpc_reg_operand" "r"))
976 (clobber (match_scratch:SI 3 "=r"))]
979 [(set_attr "type" "compare")])
982 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
983 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
984 (match_operand:SI 2 "gpc_reg_operand" "r"))
986 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
987 (minus:SI (match_dup 1) (match_dup 2)))]
989 "{sf.|subfc.} %0,%2,%1"
990 [(set_attr "type" "compare")])
993 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
994 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
995 (match_operand:SI 2 "gpc_reg_operand" "r"))
997 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
998 (minus:SI (match_dup 1) (match_dup 2)))]
1001 [(set_attr "type" "compare")])
1003 (define_expand "subsi3"
1004 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1005 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1006 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1010 if (GET_CODE (operands[2]) == CONST_INT)
1012 emit_insn (gen_addsi3 (operands[0], operands[1],
1013 negate_rtx (SImode, operands[2])));
1018 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1019 ;; instruction and some auxiliary computations. Then we just have a single
1020 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1023 (define_expand "sminsi3"
1025 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1026 (match_operand:SI 2 "reg_or_short_operand" ""))
1028 (minus:SI (match_dup 2) (match_dup 1))))
1029 (set (match_operand:SI 0 "gpc_reg_operand" "")
1030 (minus:SI (match_dup 2) (match_dup 3)))]
1033 { operands[3] = gen_reg_rtx (SImode); }")
1036 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1037 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1038 (match_operand:SI 2 "reg_or_short_operand" "")))
1039 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1042 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1044 (minus:SI (match_dup 2) (match_dup 1))))
1045 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1048 (define_expand "smaxsi3"
1050 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1051 (match_operand:SI 2 "reg_or_short_operand" ""))
1053 (minus:SI (match_dup 2) (match_dup 1))))
1054 (set (match_operand:SI 0 "gpc_reg_operand" "")
1055 (plus:SI (match_dup 3) (match_dup 1)))]
1058 { operands[3] = gen_reg_rtx (SImode); }")
1061 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1062 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1063 (match_operand:SI 2 "reg_or_short_operand" "")))
1064 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1067 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1069 (minus:SI (match_dup 2) (match_dup 1))))
1070 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1073 (define_expand "uminsi3"
1074 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1076 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1078 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1080 (minus:SI (match_dup 4) (match_dup 3))))
1081 (set (match_operand:SI 0 "gpc_reg_operand" "")
1082 (minus:SI (match_dup 2) (match_dup 3)))]
1086 operands[3] = gen_reg_rtx (SImode);
1087 operands[4] = gen_reg_rtx (SImode);
1088 operands[5] = GEN_INT (-2147483647 - 1);
1091 (define_expand "umaxsi3"
1092 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1094 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1096 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1098 (minus:SI (match_dup 4) (match_dup 3))))
1099 (set (match_operand:SI 0 "gpc_reg_operand" "")
1100 (plus:SI (match_dup 3) (match_dup 1)))]
1104 operands[3] = gen_reg_rtx (SImode);
1105 operands[4] = gen_reg_rtx (SImode);
1106 operands[5] = GEN_INT (-2147483647 - 1);
1110 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1111 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1112 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1114 (minus:SI (match_dup 2) (match_dup 1))))]
1119 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1121 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1122 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1124 (minus:SI (match_dup 2) (match_dup 1)))
1126 (clobber (match_scratch:SI 3 "=r"))]
1129 [(set_attr "type" "delayed_compare")])
1132 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1134 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1135 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1137 (minus:SI (match_dup 2) (match_dup 1)))
1139 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1140 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1142 (minus:SI (match_dup 2) (match_dup 1))))]
1145 [(set_attr "type" "delayed_compare")])
1147 ;; We don't need abs with condition code because such comparisons should
1149 (define_expand "abssi2"
1150 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1151 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1157 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1162 (define_insn "abssi2_power"
1163 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1164 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1168 (define_insn "abssi2_nopower"
1169 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1170 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1171 (clobber (match_scratch:SI 2 "=&r,&r"))]
1175 return (TARGET_POWERPC)
1176 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\"
1177 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\";
1179 [(set_attr "length" "12")])
1182 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1183 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1184 (clobber (match_scratch:SI 2 "=&r,&r"))]
1185 "!TARGET_POWER && reload_completed"
1186 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1187 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1188 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1192 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1193 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1198 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1199 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1200 (clobber (match_scratch:SI 2 "=&r,&r"))]
1204 return (TARGET_POWERPC)
1205 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\"
1206 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\";
1208 [(set_attr "length" "12")])
1211 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1212 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1213 (clobber (match_scratch:SI 2 "=&r,&r"))]
1214 "!TARGET_POWER && reload_completed"
1215 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1216 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1217 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1220 (define_insn "negsi2"
1221 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1222 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1227 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1228 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1230 (clobber (match_scratch:SI 2 "=r"))]
1233 [(set_attr "type" "compare")])
1236 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
1237 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1239 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1240 (neg:SI (match_dup 1)))]
1243 [(set_attr "type" "compare")])
1245 (define_insn "ffssi2"
1246 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
1247 (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1249 "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32"
1250 [(set_attr "length" "16")])
1252 (define_expand "mulsi3"
1253 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1254 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1255 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1260 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1262 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1266 (define_insn "mulsi3_mq"
1267 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1268 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1269 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1270 (clobber (match_scratch:SI 3 "=q,q"))]
1273 {muls|mullw} %0,%1,%2
1274 {muli|mulli} %0,%1,%2"
1275 [(set_attr "type" "imul")])
1277 (define_insn "mulsi3_no_mq"
1278 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1279 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1280 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1283 {muls|mullw} %0,%1,%2
1284 {muli|mulli} %0,%1,%2"
1285 [(set_attr "type" "imul")])
1288 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1289 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1290 (match_operand:SI 2 "gpc_reg_operand" "r"))
1292 (clobber (match_scratch:SI 3 "=r"))
1293 (clobber (match_scratch:SI 4 "=q"))]
1295 "{muls.|mullw.} %3,%1,%2"
1296 [(set_attr "type" "delayed_compare")])
1299 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1300 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1301 (match_operand:SI 2 "gpc_reg_operand" "r"))
1303 (clobber (match_scratch:SI 3 "=r"))]
1305 "{muls.|mullw.} %3,%1,%2"
1306 [(set_attr "type" "delayed_compare")])
1309 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1310 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1311 (match_operand:SI 2 "gpc_reg_operand" "r"))
1313 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1314 (mult:SI (match_dup 1) (match_dup 2)))
1315 (clobber (match_scratch:SI 4 "=q"))]
1317 "{muls.|mullw.} %0,%1,%2"
1318 [(set_attr "type" "delayed_compare")])
1321 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1322 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1323 (match_operand:SI 2 "gpc_reg_operand" "r"))
1325 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1326 (mult:SI (match_dup 1) (match_dup 2)))]
1328 "{muls.|mullw.} %0,%1,%2"
1329 [(set_attr "type" "delayed_compare")])
1331 ;; Operand 1 is divided by operand 2; quotient goes to operand
1332 ;; 0 and remainder to operand 3.
1333 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1335 (define_expand "divmodsi4"
1336 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1337 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1338 (match_operand:SI 2 "gpc_reg_operand" "")))
1339 (set (match_operand:SI 3 "gpc_reg_operand" "")
1340 (mod:SI (match_dup 1) (match_dup 2)))])]
1341 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1344 if (! TARGET_POWER && ! TARGET_POWERPC)
1346 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1347 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1348 emit_insn (gen_divss_call ());
1349 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1350 emit_move_insn (operands[3], gen_rtx (REG, SImode, 4));
1356 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1357 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1358 (match_operand:SI 2 "gpc_reg_operand" "r")))
1359 (set (match_operand:SI 3 "gpc_reg_operand" "=q")
1360 (mod:SI (match_dup 1) (match_dup 2)))]
1363 [(set_attr "type" "idiv")])
1366 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1367 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1368 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1371 [(set_attr "type" "idiv")])
1373 (define_expand "udivsi3"
1374 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1375 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1376 (match_operand:SI 2 "gpc_reg_operand" "")))]
1377 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1380 if (! TARGET_POWER && ! TARGET_POWERPC)
1382 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1383 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1384 emit_insn (gen_quous_call ());
1385 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1391 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1392 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1393 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1396 [(set_attr "type" "idiv")])
1398 ;; For powers of two we can do srai/aze for divide and then adjust for
1399 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1400 ;; used; for PowerPC, force operands into register and do a normal divide;
1401 ;; for AIX common-mode, use quoss call on register operands.
1402 (define_expand "divsi3"
1403 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1404 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1405 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1409 if (GET_CODE (operands[2]) == CONST_INT
1410 && exact_log2 (INTVAL (operands[2])) >= 0)
1412 else if (TARGET_POWERPC)
1413 operands[2] = force_reg (SImode, operands[2]);
1414 else if (TARGET_POWER)
1418 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1419 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1420 emit_insn (gen_quoss_call ());
1421 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1426 (define_expand "modsi3"
1427 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1428 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1429 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1433 int i = exact_log2 (INTVAL (operands[2]));
1437 if (GET_CODE (operands[2]) != CONST_INT || i < 0)
1440 temp1 = gen_reg_rtx (SImode);
1441 temp2 = gen_reg_rtx (SImode);
1443 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1444 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1445 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1450 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1451 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1452 (match_operand:SI 2 "const_int_operand" "N")))]
1453 "exact_log2 (INTVAL (operands[2])) >= 0"
1454 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1455 [(set_attr "length" "8")])
1458 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1459 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1460 (match_operand:SI 2 "const_int_operand" "N"))
1462 (clobber (match_scratch:SI 3 "=r"))]
1463 "exact_log2 (INTVAL (operands[2])) >= 0"
1464 "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3"
1465 [(set_attr "type" "compare")
1466 (set_attr "length" "8")])
1469 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1470 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1471 (match_operand:SI 2 "const_int_operand" "N"))
1473 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1474 (div:SI (match_dup 1) (match_dup 2)))]
1475 "exact_log2 (INTVAL (operands[2])) >= 0"
1476 "{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0"
1477 [(set_attr "type" "compare")
1478 (set_attr "length" "8")])
1481 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1484 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1486 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
1487 (match_operand:SI 3 "gpc_reg_operand" "r")))
1488 (set (match_operand:SI 2 "register_operand" "=*q")
1491 (zero_extend:DI (match_dup 1)) (const_int 32))
1492 (zero_extend:DI (match_dup 4)))
1496 [(set_attr "type" "idiv")])
1498 ;; To do unsigned divide we handle the cases of the divisor looking like a
1499 ;; negative number. If it is a constant that is less than 2**31, we don't
1500 ;; have to worry about the branches. So make a few subroutines here.
1502 ;; First comes the normal case.
1503 (define_expand "udivmodsi4_normal"
1504 [(set (match_dup 4) (const_int 0))
1505 (parallel [(set (match_operand:SI 0 "" "")
1506 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1508 (zero_extend:DI (match_operand:SI 1 "" "")))
1509 (match_operand:SI 2 "" "")))
1510 (set (match_operand:SI 3 "" "")
1511 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1513 (zero_extend:DI (match_dup 1)))
1517 { operands[4] = gen_reg_rtx (SImode); }")
1519 ;; This handles the branches.
1520 (define_expand "udivmodsi4_tests"
1521 [(set (match_operand:SI 0 "" "") (const_int 0))
1522 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
1523 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
1524 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
1525 (label_ref (match_operand:SI 4 "" "")) (pc)))
1526 (set (match_dup 0) (const_int 1))
1527 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
1528 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
1529 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
1530 (label_ref (match_dup 4)) (pc)))]
1533 { operands[5] = gen_reg_rtx (CCUNSmode);
1534 operands[6] = gen_reg_rtx (CCmode);
1537 (define_expand "udivmodsi4"
1538 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1539 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1540 (match_operand:SI 2 "reg_or_cint_operand" "")))
1541 (set (match_operand:SI 3 "gpc_reg_operand" "")
1542 (umod:SI (match_dup 1) (match_dup 2)))])]
1549 if (! TARGET_POWERPC)
1551 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1552 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1553 emit_insn (gen_divus_call ());
1554 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1555 emit_move_insn (operands[3], gen_rtx (REG, SImode, 4));
1561 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
1563 operands[2] = force_reg (SImode, operands[2]);
1564 label = gen_label_rtx ();
1565 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
1566 operands[3], label));
1569 operands[2] = force_reg (SImode, operands[2]);
1571 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
1579 ;; AIX architecture-independent common-mode multiply (DImode),
1580 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
1581 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
1582 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
1583 ;; assumed unused if generating common-mode, so ignore.
1584 (define_insn "mulh_call"
1587 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
1588 (sign_extend:DI (reg:SI 4)))
1590 (clobber (match_scratch:SI 0 "=l"))]
1591 "! TARGET_POWER && ! TARGET_POWERPC"
1593 [(set_attr "type" "imul")])
1595 (define_insn "mull_call"
1597 (mult:DI (sign_extend:DI (reg:SI 3))
1598 (sign_extend:DI (reg:SI 4))))
1599 (clobber (match_scratch:SI 0 "=l"))
1600 (clobber (reg:SI 0))]
1601 "! TARGET_POWER && ! TARGET_POWERPC"
1603 [(set_attr "type" "imul")])
1605 (define_insn "divss_call"
1607 (div:SI (reg:SI 3) (reg:SI 4)))
1609 (mod:SI (reg:SI 3) (reg:SI 4)))
1610 (clobber (match_scratch:SI 0 "=l"))
1611 (clobber (reg:SI 0))]
1612 "! TARGET_POWER && ! TARGET_POWERPC"
1614 [(set_attr "type" "idiv")])
1616 (define_insn "divus_call"
1618 (udiv:SI (reg:SI 3) (reg:SI 4)))
1620 (umod:SI (reg:SI 3) (reg:SI 4)))
1621 (clobber (match_scratch:SI 0 "=l"))
1622 (clobber (reg:SI 0))
1623 (clobber (match_scratch:CC 1 "=x"))
1624 (clobber (reg:CC 69))]
1625 "! TARGET_POWER && ! TARGET_POWERPC"
1627 [(set_attr "type" "idiv")])
1629 (define_insn "quoss_call"
1631 (div:SI (reg:SI 3) (reg:SI 4)))
1632 (clobber (match_scratch:SI 0 "=l"))]
1633 "! TARGET_POWER && ! TARGET_POWERPC"
1635 [(set_attr "type" "idiv")])
1637 (define_insn "quous_call"
1639 (udiv:SI (reg:SI 3) (reg:SI 4)))
1640 (clobber (match_scratch:SI 0 "=l"))
1641 (clobber (reg:SI 0))
1642 (clobber (match_scratch:CC 1 "=x"))
1643 (clobber (reg:CC 69))]
1644 "! TARGET_POWER && ! TARGET_POWERPC"
1646 [(set_attr "type" "idiv")])
1648 (define_insn "andsi3"
1649 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1650 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1651 (match_operand:SI 2 "and_operand" "?r,L,K,J")))
1652 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
1656 {rlinm|rlwinm} %0,%1,0,%m2,%M2
1657 {andil.|andi.} %0,%1,%b2
1658 {andiu.|andis.} %0,%1,%u2")
1661 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
1662 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1663 (match_operand:SI 2 "and_operand" "r,K,J,L"))
1665 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1669 {andil.|andi.} %3,%1,%b2
1670 {andiu.|andis.} %3,%1,%u2
1671 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2"
1672 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1675 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x")
1676 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1677 (match_operand:SI 2 "and_operand" "r,K,J,L"))
1679 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1680 (and:SI (match_dup 1) (match_dup 2)))]
1684 {andil.|andi.} %0,%1,%b2
1685 {andiu.|andis.} %0,%1,%u2
1686 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2"
1687 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1689 ;; Take a AND with a constant that cannot be done in a single insn and try to
1690 ;; split it into two insns. This does not verify that the insns are valid
1691 ;; since this need not be done as combine will do it.
1694 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1695 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
1696 (match_operand:SI 2 "non_and_cint_operand" "")))]
1698 [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))
1699 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))]
1702 int maskval = INTVAL (operands[2]);
1703 int i, transitions, last_bit_value;
1704 int orig = maskval, first_c = maskval, second_c;
1706 /* We know that MASKVAL must have more than 2 bit-transitions. Start at
1707 the low-order bit and count for the third transition. When we get there,
1708 make a first mask that has everything to the left of that position
1709 a one. Then make the second mask to turn off whatever else is needed. */
1711 for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++)
1713 if (((maskval >>= 1) & 1) != last_bit_value)
1714 last_bit_value ^= 1, transitions++;
1716 if (transitions > 2)
1718 first_c |= (~0) << i;
1723 second_c = orig | ~ first_c;
1725 operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c);
1726 operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c);
1729 (define_insn "iorsi3"
1730 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1731 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
1732 (match_operand:SI 2 "logical_operand" "r,K,J")))]
1736 {oril|ori} %0,%1,%b2
1737 {oriu|oris} %0,%1,%u2")
1740 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1741 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1742 (match_operand:SI 2 "gpc_reg_operand" "r"))
1744 (clobber (match_scratch:SI 3 "=r"))]
1747 [(set_attr "type" "compare")])
1750 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1751 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1752 (match_operand:SI 2 "gpc_reg_operand" "r"))
1754 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1755 (ior:SI (match_dup 1) (match_dup 2)))]
1758 [(set_attr "type" "compare")])
1760 ;; Split an IOR that we can't do in one insn into two insns, each of which
1761 ;; does one 16-bit part. This is used by combine.
1764 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1765 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1766 (match_operand:SI 2 "non_logical_cint_operand" "")))]
1768 [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))
1769 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))]
1772 operands[3] = gen_rtx (CONST_INT, VOIDmode,
1773 INTVAL (operands[2]) & 0xffff0000);
1774 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
1777 (define_insn "xorsi3"
1778 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1779 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
1780 (match_operand:SI 2 "logical_operand" "r,K,J")))]
1784 {xoril|xori} %0,%1,%b2
1785 {xoriu|xoris} %0,%1,%u2")
1788 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1789 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1790 (match_operand:SI 2 "gpc_reg_operand" "r"))
1792 (clobber (match_scratch:SI 3 "=r"))]
1795 [(set_attr "type" "compare")])
1798 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1799 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1800 (match_operand:SI 2 "gpc_reg_operand" "r"))
1802 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1803 (xor:SI (match_dup 1) (match_dup 2)))]
1806 [(set_attr "type" "compare")])
1808 ;; Split an XOR that we can't do in one insn into two insns, each of which
1809 ;; does one 16-bit part. This is used by combine.
1812 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1813 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1814 (match_operand:SI 2 "non_logical_cint_operand" "")))]
1816 [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))
1817 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))]
1820 operands[3] = gen_rtx (CONST_INT, VOIDmode,
1821 INTVAL (operands[2]) & 0xffff0000);
1822 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
1826 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1827 (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1828 (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1833 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1834 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1835 (match_operand:SI 2 "gpc_reg_operand" "r")))
1837 (clobber (match_scratch:SI 3 "=r"))]
1840 [(set_attr "type" "compare")])
1843 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1844 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1845 (match_operand:SI 2 "gpc_reg_operand" "r")))
1847 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1848 (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
1851 [(set_attr "type" "compare")])
1854 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1855 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1856 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1861 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1862 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1863 (match_operand:SI 2 "gpc_reg_operand" "r"))
1865 (clobber (match_scratch:SI 3 "=r"))]
1868 [(set_attr "type" "compare")])
1871 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1872 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1873 (match_operand:SI 2 "gpc_reg_operand" "r"))
1875 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1876 (and:SI (not:SI (match_dup 1)) (match_dup 2)))]
1879 [(set_attr "type" "compare")])
1882 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1883 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1884 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1889 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1890 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1891 (match_operand:SI 2 "gpc_reg_operand" "r"))
1893 (clobber (match_scratch:SI 3 "=r"))]
1896 [(set_attr "type" "compare")])
1899 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1900 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1901 (match_operand:SI 2 "gpc_reg_operand" "r"))
1903 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1904 (ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
1907 [(set_attr "type" "compare")])
1910 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1911 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1912 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1917 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1918 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1919 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1921 (clobber (match_scratch:SI 3 "=r"))]
1924 [(set_attr "type" "compare")])
1927 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1928 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1929 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1931 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1932 (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
1935 [(set_attr "type" "compare")])
1938 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1939 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1940 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1945 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1946 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1947 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1949 (clobber (match_scratch:SI 3 "=r"))]
1952 [(set_attr "type" "compare")])
1955 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1956 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1957 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1959 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1960 (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
1963 [(set_attr "type" "compare")])
1965 ;; maskir insn. We need four forms because things might be in arbitrary
1966 ;; orders. Don't define forms that only set CR fields because these
1967 ;; would modify an input register.
1970 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1971 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1972 (match_operand:SI 1 "gpc_reg_operand" "0"))
1973 (and:SI (match_dup 2)
1974 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
1979 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1980 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1981 (match_operand:SI 1 "gpc_reg_operand" "0"))
1982 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1988 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1989 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1990 (match_operand:SI 3 "gpc_reg_operand" "r"))
1991 (and:SI (not:SI (match_dup 2))
1992 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
1997 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1998 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1999 (match_operand:SI 2 "gpc_reg_operand" "r"))
2000 (and:SI (not:SI (match_dup 2))
2001 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2006 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2008 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2009 (match_operand:SI 1 "gpc_reg_operand" "0"))
2010 (and:SI (match_dup 2)
2011 (match_operand:SI 3 "gpc_reg_operand" "r")))
2013 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2014 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2015 (and:SI (match_dup 2) (match_dup 3))))]
2018 [(set_attr "type" "compare")])
2021 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2023 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2024 (match_operand:SI 1 "gpc_reg_operand" "0"))
2025 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2028 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2029 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2030 (and:SI (match_dup 3) (match_dup 2))))]
2033 [(set_attr "type" "compare")])
2036 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2038 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2039 (match_operand:SI 3 "gpc_reg_operand" "r"))
2040 (and:SI (not:SI (match_dup 2))
2041 (match_operand:SI 1 "gpc_reg_operand" "0")))
2043 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2044 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2045 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2048 [(set_attr "type" "compare")])
2051 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2053 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2054 (match_operand:SI 2 "gpc_reg_operand" "r"))
2055 (and:SI (not:SI (match_dup 2))
2056 (match_operand:SI 1 "gpc_reg_operand" "0")))
2058 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2059 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2060 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2063 [(set_attr "type" "compare")])
2065 ;; Rotate and shift insns, in all their variants. These support shifts,
2066 ;; field inserts and extracts, and various combinations thereof.
2067 (define_expand "insv"
2068 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2069 (match_operand:SI 1 "const_int_operand" "i")
2070 (match_operand:SI 2 "const_int_operand" "i"))
2071 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2075 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2076 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2077 compiler if the address of the structure is taken later. */
2078 if (GET_CODE (operands[0]) == SUBREG
2079 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2084 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2085 (match_operand:SI 1 "const_int_operand" "i")
2086 (match_operand:SI 2 "const_int_operand" "i"))
2087 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2091 int start = INTVAL (operands[2]) & 31;
2092 int size = INTVAL (operands[1]) & 31;
2094 operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size);
2095 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
2096 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2100 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2101 (match_operand:SI 1 "const_int_operand" "i")
2102 (match_operand:SI 2 "const_int_operand" "i"))
2103 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2104 (match_operand:SI 4 "const_int_operand" "i")))]
2108 int shift = INTVAL (operands[4]) & 31;
2109 int start = INTVAL (operands[2]) & 31;
2110 int size = INTVAL (operands[1]) & 31;
2112 operands[4] = gen_rtx (CONST_INT, VOIDmode, shift - start - size);
2113 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
2114 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2118 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2119 (match_operand:SI 1 "const_int_operand" "i")
2120 (match_operand:SI 2 "const_int_operand" "i"))
2121 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2122 (match_operand:SI 4 "const_int_operand" "i")))]
2126 int shift = INTVAL (operands[4]) & 31;
2127 int start = INTVAL (operands[2]) & 31;
2128 int size = INTVAL (operands[1]) & 31;
2130 operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - shift - start - size);
2131 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
2132 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2136 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2137 (match_operand:SI 1 "const_int_operand" "i")
2138 (match_operand:SI 2 "const_int_operand" "i"))
2139 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2140 (match_operand:SI 4 "const_int_operand" "i")))]
2144 int shift = INTVAL (operands[4]) & 31;
2145 int start = INTVAL (operands[2]) & 31;
2146 int size = INTVAL (operands[1]) & 31;
2148 operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - shift - start - size);
2149 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
2150 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2154 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2155 (match_operand:SI 1 "const_int_operand" "i")
2156 (match_operand:SI 2 "const_int_operand" "i"))
2157 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2158 (match_operand:SI 4 "const_int_operand" "i")
2159 (match_operand:SI 5 "const_int_operand" "i")))]
2160 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2163 int extract_start = INTVAL (operands[5]) & 31;
2164 int extract_size = INTVAL (operands[4]) & 31;
2165 int insert_start = INTVAL (operands[2]) & 31;
2166 int insert_size = INTVAL (operands[1]) & 31;
2168 /* Align extract field with insert field */
2169 operands[5] = gen_rtx (CONST_INT, VOIDmode,
2170 extract_start + extract_size - insert_start - insert_size);
2171 operands[1] = gen_rtx (CONST_INT, VOIDmode, insert_start + insert_size - 1);
2172 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
2176 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
2177 (match_operand:DI 1 "const_int_operand" "i")
2178 (match_operand:DI 2 "const_int_operand" "i"))
2179 (match_operand:DI 3 "gpc_reg_operand" "r"))]
2183 int start = INTVAL (operands[2]) & 63;
2184 int size = INTVAL (operands[1]) & 63;
2186 operands[2] = gen_rtx (CONST_INT, VOIDmode, 64 - start - size);
2187 return \"rldimi %0,%3,%H2,%H1\";
2190 (define_expand "extzv"
2191 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2192 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2193 (match_operand:SI 2 "const_int_operand" "i")
2194 (match_operand:SI 3 "const_int_operand" "i")))]
2198 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2199 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2200 compiler if the address of the structure is taken later. */
2201 if (GET_CODE (operands[0]) == SUBREG
2202 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2207 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2208 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2209 (match_operand:SI 2 "const_int_operand" "i")
2210 (match_operand:SI 3 "const_int_operand" "i")))]
2214 int start = INTVAL (operands[3]) & 31;
2215 int size = INTVAL (operands[2]) & 31;
2217 if (start + size >= 32)
2218 operands[3] = const0_rtx;
2220 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2221 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
2225 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2226 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2227 (match_operand:SI 2 "const_int_operand" "i")
2228 (match_operand:SI 3 "const_int_operand" "i"))
2230 (clobber (match_scratch:SI 4 "=r"))]
2234 int start = INTVAL (operands[3]) & 31;
2235 int size = INTVAL (operands[2]) & 31;
2237 /* If the bitfield being tested fits in the upper or lower half of a
2238 word, it is possible to use andiu. or andil. to test it. This is
2239 useful because the condition register set-use delay is smaller for
2240 andi[ul]. than for rlinm. This doesn't work when the starting bit
2241 position is 0 because the LT and GT bits may be set wrong. */
2243 if ((start > 0 && start + size <= 16) || start >= 16)
2245 operands[3] = gen_rtx (CONST_INT, VOIDmode,
2246 ((1 << (16 - (start & 15)))
2247 - (1 << (16 - (start & 15) - size))));
2249 return \"{andiu.|andis.} %4,%1,%3\";
2251 return \"{andil.|andi.} %4,%1,%3\";
2254 if (start + size >= 32)
2255 operands[3] = const0_rtx;
2257 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2258 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
2260 [(set_attr "type" "compare")])
2263 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2264 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2265 (match_operand:SI 2 "const_int_operand" "i")
2266 (match_operand:SI 3 "const_int_operand" "i"))
2268 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2269 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
2273 int start = INTVAL (operands[3]) & 31;
2274 int size = INTVAL (operands[2]) & 31;
2276 if (start >= 16 && start + size == 32)
2278 operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1);
2279 return \"{andil.|andi.} %0,%1,%3\";
2282 if (start + size >= 32)
2283 operands[3] = const0_rtx;
2285 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2286 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
2288 [(set_attr "type" "delayed_compare")])
2291 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2292 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
2293 (match_operand:DI 2 "const_int_operand" "i")
2294 (match_operand:DI 3 "const_int_operand" "i")))]
2298 int start = INTVAL (operands[3]) & 63;
2299 int size = INTVAL (operands[2]) & 63;
2301 if (start + size >= 64)
2302 operands[3] = const0_rtx;
2304 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2305 operands[2] = gen_rtx (CONST_INT, VOIDmode, 64 - size);
2306 return \"rldicl %0,%1,%3,%2\";
2310 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
2311 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
2312 (match_operand:DI 2 "const_int_operand" "i")
2313 (match_operand:DI 3 "const_int_operand" "i"))
2315 (clobber (match_scratch:DI 4 "=r"))]
2319 int start = INTVAL (operands[3]) & 63;
2320 int size = INTVAL (operands[2]) & 63;
2322 if (start + size >= 64)
2323 operands[3] = const0_rtx;
2325 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2326 operands[2] = gen_rtx (CONST_INT, VOIDmode, 64 - size);
2327 return \"rldicl. %4,%1,%3,%2\";
2331 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
2332 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
2333 (match_operand:DI 2 "const_int_operand" "i")
2334 (match_operand:DI 3 "const_int_operand" "i"))
2336 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
2337 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
2341 int start = INTVAL (operands[3]) & 63;
2342 int size = INTVAL (operands[2]) & 63;
2344 if (start + size >= 64)
2345 operands[3] = const0_rtx;
2347 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2348 operands[2] = gen_rtx (CONST_INT, VOIDmode, 64 - size);
2349 return \"rldicl. %0,%1,%3,%2\";
2352 (define_insn "rotlsi3"
2353 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2354 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2355 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2357 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
2360 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2361 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2362 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2364 (clobber (match_scratch:SI 3 "=r"))]
2366 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff"
2367 [(set_attr "type" "delayed_compare")])
2370 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2371 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2372 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2374 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2375 (rotate:SI (match_dup 1) (match_dup 2)))]
2377 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff"
2378 [(set_attr "type" "delayed_compare")])
2381 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2382 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2383 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2384 (match_operand:SI 3 "mask_operand" "L")))]
2386 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
2389 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2391 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2392 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2393 (match_operand:SI 3 "mask_operand" "L"))
2395 (clobber (match_scratch:SI 4 "=r"))]
2397 "{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3"
2398 [(set_attr "type" "delayed_compare")])
2401 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2403 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2404 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2405 (match_operand:SI 3 "mask_operand" "L"))
2407 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2408 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
2410 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3"
2411 [(set_attr "type" "delayed_compare")])
2414 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2417 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2418 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
2420 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
2423 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2424 (compare:CC (zero_extend:SI
2426 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2427 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2429 (clobber (match_scratch:SI 3 "=r"))]
2431 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff"
2432 [(set_attr "type" "delayed_compare")])
2435 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2436 (compare:CC (zero_extend:SI
2438 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2439 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2441 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2442 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
2444 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff"
2445 [(set_attr "type" "delayed_compare")])
2448 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2451 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2452 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
2454 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
2457 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2458 (compare:CC (zero_extend:SI
2460 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2461 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2463 (clobber (match_scratch:SI 3 "=r"))]
2465 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff"
2466 [(set_attr "type" "delayed_compare")])
2469 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2470 (compare:CC (zero_extend:SI
2472 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2473 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2475 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2476 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
2478 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff"
2479 [(set_attr "type" "delayed_compare")])
2481 ;; Note that we use "sle." instead of "sl." so that we can set
2482 ;; SHIFT_COUNT_TRUNCATED.
2484 (define_expand "ashlsi3"
2485 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2486 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2487 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2492 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
2494 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
2498 (define_insn "ashlsi3_power"
2499 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2500 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2501 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
2502 (clobber (match_scratch:SI 3 "=q,X"))]
2506 {sli|slwi} %0,%1,%h2"
2507 [(set_attr "length" "8")])
2509 (define_insn "ashlsi3_no_power"
2510 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2511 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2512 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2514 "{sl|slw}%I2 %0,%1,%h2"
2515 [(set_attr "length" "8")])
2518 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
2519 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2520 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2522 (clobber (match_scratch:SI 3 "=r,r"))
2523 (clobber (match_scratch:SI 4 "=q,X"))]
2527 {sli.|slwi.} %3,%1,%h2"
2528 [(set_attr "type" "delayed_compare")])
2531 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2532 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2533 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2535 (clobber (match_scratch:SI 3 "=r"))]
2537 "{sl|slw}%I2. %3,%1,%h2"
2538 [(set_attr "type" "delayed_compare")])
2541 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
2542 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2543 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2545 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2546 (ashift:SI (match_dup 1) (match_dup 2)))
2547 (clobber (match_scratch:SI 4 "=q,X"))]
2551 {sli.|slwi.} %0,%1,%h2"
2552 [(set_attr "type" "delayed_compare")])
2555 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2556 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2557 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2559 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2560 (ashift:SI (match_dup 1) (match_dup 2)))]
2562 "{sl|slw}%I2. %0,%1,%h2"
2563 [(set_attr "type" "delayed_compare")])
2566 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2567 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2568 (match_operand:SI 2 "const_int_operand" "i"))
2569 (match_operand:SI 3 "mask_operand" "L")))]
2570 "includes_lshift_p (operands[2], operands[3])"
2571 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
2574 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2576 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2577 (match_operand:SI 2 "const_int_operand" "i"))
2578 (match_operand:SI 3 "mask_operand" "L"))
2580 (clobber (match_scratch:SI 4 "=r"))]
2581 "includes_lshift_p (operands[2], operands[3])"
2582 "{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3"
2583 [(set_attr "type" "delayed_compare")])
2586 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2588 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2589 (match_operand:SI 2 "const_int_operand" "i"))
2590 (match_operand:SI 3 "mask_operand" "L"))
2592 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2593 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
2594 "includes_lshift_p (operands[2], operands[3])"
2595 "{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3"
2596 [(set_attr "type" "delayed_compare")])
2598 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
2600 (define_expand "lshrsi3"
2601 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2602 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2603 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2608 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
2610 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
2614 (define_insn "lshrsi3_power"
2615 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2616 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
2617 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
2618 (clobber (match_scratch:SI 3 "=q,X,X"))]
2623 {s%A2i|s%A2wi} %0,%1,%h2")
2625 (define_insn "lshrsi3_no_power"
2626 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2627 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2628 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
2632 {sr|srw}%I2 %0,%1,%h2")
2635 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x")
2636 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
2637 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))
2639 (clobber (match_scratch:SI 3 "=r,X,r"))
2640 (clobber (match_scratch:SI 4 "=q,X,X"))]
2645 {s%A2i.|s%A2wi.} %3,%1,%h2"
2646 [(set_attr "type" "delayed_compare")])
2649 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
2650 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2651 (match_operand:SI 2 "reg_or_cint_operand" "O,ri"))
2653 (clobber (match_scratch:SI 3 "=X,r"))]
2657 {sr|srw}%I2. %3,%1,%h2"
2658 [(set_attr "type" "delayed_compare")])
2661 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x")
2662 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
2663 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))
2665 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2666 (lshiftrt:SI (match_dup 1) (match_dup 2)))
2667 (clobber (match_scratch:SI 4 "=q,X,X"))]
2672 {s%A2i.|s%A2wi.} %0,%1,%h2"
2673 [(set_attr "type" "delayed_compare")])
2676 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
2677 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2678 (match_operand:SI 2 "reg_or_cint_operand" "O,ri"))
2680 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2681 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
2685 {sr|srw}%I2. %0,%1,%h2"
2686 [(set_attr "type" "delayed_compare")])
2689 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2690 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2691 (match_operand:SI 2 "const_int_operand" "i"))
2692 (match_operand:SI 3 "mask_operand" "L")))]
2693 "includes_rshift_p (operands[2], operands[3])"
2694 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
2697 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2699 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2700 (match_operand:SI 2 "const_int_operand" "i"))
2701 (match_operand:SI 3 "mask_operand" "L"))
2703 (clobber (match_scratch:SI 4 "=r"))]
2704 "includes_rshift_p (operands[2], operands[3])"
2705 "{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3"
2706 [(set_attr "type" "delayed_compare")])
2709 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2711 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2712 (match_operand:SI 2 "const_int_operand" "i"))
2713 (match_operand:SI 3 "mask_operand" "L"))
2715 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2716 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
2717 "includes_rshift_p (operands[2], operands[3])"
2718 "{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3"
2719 [(set_attr "type" "delayed_compare")])
2722 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2725 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2726 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
2727 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
2728 "{rlinm|rlwinm} %0,%1,%s2,0xff")
2731 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2735 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2736 (match_operand:SI 2 "const_int_operand" "i")) 0))
2738 (clobber (match_scratch:SI 3 "=r"))]
2739 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
2740 "{rlinm.|rlwinm.} %3,%1,%s2,0xff"
2741 [(set_attr "type" "delayed_compare")])
2744 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2748 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2749 (match_operand:SI 2 "const_int_operand" "i")) 0))
2751 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2752 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
2753 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
2754 "{rlinm.|rlwinm.} %0,%1,%s2,0xff"
2755 [(set_attr "type" "delayed_compare")])
2758 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2761 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2762 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
2763 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
2764 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
2767 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2771 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2772 (match_operand:SI 2 "const_int_operand" "i")) 0))
2774 (clobber (match_scratch:SI 3 "=r"))]
2775 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
2776 "{rlinm.|rlwinm.} %3,%1,%s2,0xffff"
2777 [(set_attr "type" "delayed_compare")])
2780 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2784 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2785 (match_operand:SI 2 "const_int_operand" "i")) 0))
2787 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2788 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
2789 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
2790 "{rlinm.|rlwinm.} %0,%1,%s2,0xffff"
2791 [(set_attr "type" "delayed_compare")])
2794 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2796 (match_operand:SI 1 "gpc_reg_operand" "r"))
2797 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2803 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2805 (match_operand:SI 1 "gpc_reg_operand" "r"))
2806 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2812 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2814 (match_operand:SI 1 "gpc_reg_operand" "r"))
2815 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2821 (define_expand "ashrsi3"
2822 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2823 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
2824 (match_operand:SI 2 "reg_or_cint_operand" "")))]
2829 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
2831 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
2835 (define_insn "ashrsi3_power"
2836 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2837 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2838 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
2839 (clobber (match_scratch:SI 3 "=q,X"))]
2843 {srai|srawi} %0,%1,%h2")
2845 (define_insn "ashrsi3_no_power"
2846 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2847 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2848 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2850 "{sra|sraw}%I2 %0,%1,%h2")
2853 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
2854 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2855 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2857 (clobber (match_scratch:SI 3 "=r,r"))
2858 (clobber (match_scratch:SI 4 "=q,X"))]
2862 {srai.|srawi.} %3,%1,%h2"
2863 [(set_attr "type" "delayed_compare")])
2866 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2867 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2868 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2870 (clobber (match_scratch:SI 3 "=r"))]
2872 "{sra|sraw}%I2. %3,%1,%h2"
2873 [(set_attr "type" "delayed_compare")])
2876 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
2877 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2878 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2880 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2881 (ashiftrt:SI (match_dup 1) (match_dup 2)))
2882 (clobber (match_scratch:SI 4 "=q,X"))]
2886 {srai.|srawi.} %0,%1,%h2"
2887 [(set_attr "type" "delayed_compare")])
2890 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2891 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2892 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2894 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2895 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
2897 "{sra|sraw}%I2. %0,%1,%h2"
2898 [(set_attr "type" "delayed_compare")])
2900 ;; Floating-point insns, excluding normal data motion.
2902 ;; PowerPC has a full set of single-precision floating point instructions.
2904 ;; For the POWER architecture, we pretend that we have both SFmode and
2905 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
2906 ;; The only conversions we will do will be when storing to memory. In that
2907 ;; case, we will use the "frsp" instruction before storing.
2909 ;; Note that when we store into a single-precision memory location, we need to
2910 ;; use the frsp insn first. If the register being stored isn't dead, we
2911 ;; need a scratch register for the frsp. But this is difficult when the store
2912 ;; is done by reload. It is not incorrect to do the frsp on the register in
2913 ;; this case, we just lose precision that we would have otherwise gotten but
2914 ;; is not guaranteed. Perhaps this should be tightened up at some point.
2916 (define_insn "extendsfdf2"
2917 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2918 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2922 if (REGNO (operands[0]) == REGNO (operands[1]))
2925 return \"fmr %0,%1\";
2927 [(set_attr "type" "fp")])
2929 (define_insn "truncdfsf2"
2930 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2931 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
2934 [(set_attr "type" "fp")])
2936 (define_insn "aux_truncdfsf2"
2937 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2938 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
2939 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2941 [(set_attr "type" "fp")])
2943 (define_insn "negsf2"
2944 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2945 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2948 [(set_attr "type" "fp")])
2950 (define_insn "abssf2"
2951 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2952 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2955 [(set_attr "type" "fp")])
2958 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2959 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
2962 [(set_attr "type" "fp")])
2964 (define_expand "addsf3"
2965 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2966 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
2967 (match_operand:SF 2 "gpc_reg_operand" "")))]
2972 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2973 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2974 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2975 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2977 [(set_attr "type" "fp")])
2980 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2981 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2982 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2983 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2984 "{fa|fadd} %0,%1,%2"
2985 [(set_attr "type" "fp")])
2987 (define_expand "subsf3"
2988 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2989 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
2990 (match_operand:SF 2 "gpc_reg_operand" "")))]
2995 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2996 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
2997 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2998 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3000 [(set_attr "type" "fp")])
3003 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3004 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
3005 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3006 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3007 "{fs|fsub} %0,%1,%2"
3008 [(set_attr "type" "fp")])
3010 (define_expand "mulsf3"
3011 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3012 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
3013 (match_operand:SF 2 "gpc_reg_operand" "")))]
3018 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3019 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3020 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3021 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3023 [(set_attr "type" "fp")])
3026 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3027 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3028 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3029 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3030 "{fm|fmul} %0,%1,%2"
3031 [(set_attr "type" "dmul")])
3033 (define_expand "divsf3"
3034 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3035 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
3036 (match_operand:SF 2 "gpc_reg_operand" "")))]
3041 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3042 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
3043 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3044 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3046 [(set_attr "type" "sdiv")])
3049 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3050 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
3051 (match_operand:SF 2 "gpc_reg_operand" "f")))]
3052 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3053 "{fd|fdiv} %0,%1,%2"
3054 [(set_attr "type" "ddiv")])
3057 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3058 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3059 (match_operand:SF 2 "gpc_reg_operand" "f"))
3060 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3061 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3062 "fmadds %0,%1,%2,%3"
3063 [(set_attr "type" "fp")])
3066 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3067 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3068 (match_operand:SF 2 "gpc_reg_operand" "f"))
3069 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3070 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3071 "{fma|fmadd} %0,%1,%2,%3"
3072 [(set_attr "type" "dmul")])
3075 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3076 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3077 (match_operand:SF 2 "gpc_reg_operand" "f"))
3078 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3079 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3080 "fmsubs %0,%1,%2,%3"
3081 [(set_attr "type" "fp")])
3084 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3085 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3086 (match_operand:SF 2 "gpc_reg_operand" "f"))
3087 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3088 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3089 "{fms|fmsub} %0,%1,%2,%3"
3090 [(set_attr "type" "dmul")])
3093 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3094 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3095 (match_operand:SF 2 "gpc_reg_operand" "f"))
3096 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
3097 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3098 "fnmadds %0,%1,%2,%3"
3099 [(set_attr "type" "fp")])
3102 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3103 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3104 (match_operand:SF 2 "gpc_reg_operand" "f"))
3105 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
3106 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3107 "{fnma|fnmadd} %0,%1,%2,%3"
3108 [(set_attr "type" "dmul")])
3111 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3112 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3113 (match_operand:SF 2 "gpc_reg_operand" "f"))
3114 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
3115 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3116 "fnmsubs %0,%1,%2,%3"
3117 [(set_attr "type" "fp")])
3120 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3121 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3122 (match_operand:SF 2 "gpc_reg_operand" "f"))
3123 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
3124 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3125 "{fnms|fnmsub} %0,%1,%2,%3"
3126 [(set_attr "type" "dmul")])
3128 (define_expand "sqrtsf2"
3129 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3130 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
3131 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
3135 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3136 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
3137 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT"
3139 [(set_attr "type" "ssqrt")])
3142 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3143 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
3144 "TARGET_POWER2 && TARGET_HARD_FLOAT"
3146 [(set_attr "type" "dsqrt")])
3148 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
3149 ;; fsel instruction and some auxiliary computations. Then we just have a
3150 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
3152 (define_expand "maxsf3"
3154 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
3155 (match_operand:SF 2 "gpc_reg_operand" "")))
3156 (set (match_operand:SF 0 "gpc_reg_operand" "")
3157 (if_then_else:SF (ge (match_dup 3)
3161 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3163 { operands[3] = gen_reg_rtx (SFmode); }")
3166 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3167 (smax:SF (match_operand:SF 1 "gpc_reg_operand" "")
3168 (match_operand:SF 2 "gpc_reg_operand" "")))
3169 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
3170 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3172 (minus:SF (match_dup 1) (match_dup 2)))
3174 (if_then_else:SF (ge (match_dup 3)
3180 (define_expand "minsf3"
3182 (minus:SF (match_operand:SF 2 "gpc_reg_operand" "")
3183 (match_operand:SF 1 "gpc_reg_operand" "")))
3184 (set (match_operand:SF 0 "gpc_reg_operand" "")
3185 (if_then_else:SF (ge (match_dup 3)
3189 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3191 { operands[3] = gen_reg_rtx (SFmode); }")
3194 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3195 (smin:SF (match_operand:SF 1 "gpc_reg_operand" "")
3196 (match_operand:SF 2 "gpc_reg_operand" "")))
3197 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
3198 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3200 (minus:SF (match_dup 2) (match_dup 1)))
3202 (if_then_else:SF (ge (match_dup 3)
3208 (define_expand "movsfcc"
3209 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3210 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3211 (match_operand:SF 2 "gpc_reg_operand" "f")
3212 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3213 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3217 enum rtx_code code = GET_CODE (operands[1]);
3218 if (! rs6000_compare_fp_p)
3222 case GE: case EQ: case NE:
3223 op0 = rs6000_compare_op0;
3224 op1 = rs6000_compare_op1;
3227 op0 = rs6000_compare_op1;
3228 op1 = rs6000_compare_op0;
3229 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3232 op0 = rs6000_compare_op1;
3233 op1 = rs6000_compare_op0;
3236 op0 = rs6000_compare_op0;
3237 op1 = rs6000_compare_op1;
3238 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3243 if (GET_MODE (rs6000_compare_op0) == DFmode)
3245 temp = gen_reg_rtx (DFmode);
3246 emit_insn (gen_subdf3 (temp, op0, op1));
3247 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[2], operands[3]));
3250 emit_insn (gen_negdf2 (temp, temp));
3251 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[0], operands[3]));
3255 emit_insn (gen_negdf2 (temp, temp));
3256 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[3], operands[0]));
3261 temp = gen_reg_rtx (SFmode);
3262 emit_insn (gen_subsf3 (temp, op0, op1));
3263 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[2], operands[3]));
3266 emit_insn (gen_negsf2 (temp, temp));
3267 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[0], operands[3]));
3271 emit_insn (gen_negsf2 (temp, temp));
3272 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[3], operands[0]));
3278 (define_insn "fselsfsf4"
3279 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3280 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
3282 (match_operand:SF 2 "gpc_reg_operand" "f")
3283 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3284 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3286 [(set_attr "type" "fp")])
3288 (define_insn "fseldfsf4"
3289 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3290 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
3292 (match_operand:SF 2 "gpc_reg_operand" "f")
3293 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3294 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3296 [(set_attr "type" "fp")])
3298 (define_insn "negdf2"
3299 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3300 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3303 [(set_attr "type" "fp")])
3305 (define_insn "absdf2"
3306 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3307 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3310 [(set_attr "type" "fp")])
3313 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3314 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
3317 [(set_attr "type" "fp")])
3319 (define_insn "adddf3"
3320 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3321 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3322 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3324 "{fa|fadd} %0,%1,%2"
3325 [(set_attr "type" "fp")])
3327 (define_insn "subdf3"
3328 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3329 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
3330 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3332 "{fs|fsub} %0,%1,%2"
3333 [(set_attr "type" "fp")])
3335 (define_insn "muldf3"
3336 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3337 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3338 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3340 "{fm|fmul} %0,%1,%2"
3341 [(set_attr "type" "dmul")])
3343 (define_insn "divdf3"
3344 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3345 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
3346 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3348 "{fd|fdiv} %0,%1,%2"
3349 [(set_attr "type" "ddiv")])
3352 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3353 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3354 (match_operand:DF 2 "gpc_reg_operand" "f"))
3355 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3357 "{fma|fmadd} %0,%1,%2,%3"
3358 [(set_attr "type" "dmul")])
3361 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3362 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3363 (match_operand:DF 2 "gpc_reg_operand" "f"))
3364 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3366 "{fms|fmsub} %0,%1,%2,%3"
3367 [(set_attr "type" "dmul")])
3370 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3371 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3372 (match_operand:DF 2 "gpc_reg_operand" "f"))
3373 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
3375 "{fnma|fnmadd} %0,%1,%2,%3"
3376 [(set_attr "type" "dmul")])
3379 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3380 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3381 (match_operand:DF 2 "gpc_reg_operand" "f"))
3382 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
3384 "{fnms|fnmsub} %0,%1,%2,%3"
3385 [(set_attr "type" "dmul")])
3387 (define_insn "sqrtdf2"
3388 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3389 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3390 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
3392 [(set_attr "type" "dsqrt")])
3394 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
3395 ;; fsel instruction and some auxiliary computations. Then we just have a
3396 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
3399 (define_expand "maxdf3"
3401 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
3402 (match_operand:DF 2 "gpc_reg_operand" "")))
3403 (set (match_operand:DF 0 "gpc_reg_operand" "")
3404 (if_then_else:DF (ge (match_dup 3)
3408 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3410 { operands[3] = gen_reg_rtx (DFmode); }")
3413 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3414 (smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
3415 (match_operand:DF 2 "gpc_reg_operand" "")))
3416 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
3417 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3419 (minus:DF (match_dup 1) (match_dup 2)))
3421 (if_then_else:DF (ge (match_dup 3)
3427 (define_expand "mindf3"
3429 (minus:DF (match_operand:DF 2 "gpc_reg_operand" "")
3430 (match_operand:DF 1 "gpc_reg_operand" "")))
3431 (set (match_operand:DF 0 "gpc_reg_operand" "")
3432 (if_then_else:DF (ge (match_dup 3)
3436 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3438 { operands[3] = gen_reg_rtx (DFmode); }")
3441 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3442 (smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
3443 (match_operand:DF 2 "gpc_reg_operand" "")))
3444 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
3445 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3447 (minus:DF (match_dup 2) (match_dup 1)))
3449 (if_then_else:DF (ge (match_dup 3)
3455 (define_expand "movdfcc"
3456 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3457 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3458 (match_operand:DF 2 "gpc_reg_operand" "f")
3459 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3460 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3464 enum rtx_code code = GET_CODE (operands[1]);
3465 if (! rs6000_compare_fp_p)
3469 case GE: case EQ: case NE:
3470 op0 = rs6000_compare_op0;
3471 op1 = rs6000_compare_op1;
3474 op0 = rs6000_compare_op1;
3475 op1 = rs6000_compare_op0;
3476 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3479 op0 = rs6000_compare_op1;
3480 op1 = rs6000_compare_op0;
3483 op0 = rs6000_compare_op0;
3484 op1 = rs6000_compare_op1;
3485 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3490 if (GET_MODE (rs6000_compare_op0) == DFmode)
3492 temp = gen_reg_rtx (DFmode);
3493 emit_insn (gen_subdf3 (temp, op0, op1));
3494 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[2], operands[3]));
3497 emit_insn (gen_negdf2 (temp, temp));
3498 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[0], operands[3]));
3502 emit_insn (gen_negdf2 (temp, temp));
3503 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[3], operands[0]));
3508 temp = gen_reg_rtx (SFmode);
3509 emit_insn (gen_subsf3 (temp, op0, op1));
3510 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[2], operands[3]));
3513 emit_insn (gen_negsf2 (temp, temp));
3514 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[0], operands[3]));
3518 emit_insn (gen_negsf2 (temp, temp));
3519 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[3], operands[0]));
3525 (define_insn "fseldfdf4"
3526 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3527 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
3529 (match_operand:DF 2 "gpc_reg_operand" "f")
3530 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3531 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3533 [(set_attr "type" "fp")])
3535 (define_insn "fselsfdf4"
3536 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3537 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
3539 (match_operand:DF 2 "gpc_reg_operand" "f")
3540 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3543 [(set_attr "type" "fp")])
3545 ;; Conversions to and from floating-point.
3547 (define_expand "floatsidf2"
3548 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
3549 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
3552 (clobber (match_dup 4))
3553 (clobber (match_dup 5))
3554 (clobber (reg:DF 76))])]
3555 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3558 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
3559 operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode));
3560 operands[4] = gen_reg_rtx (SImode);
3561 operands[5] = gen_reg_rtx (Pmode);
3564 (define_insn "*floatsidf2_internal"
3565 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
3566 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
3567 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
3568 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
3569 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
3570 (clobber (match_operand:SI 5 "gpc_reg_operand" "=b"))
3571 (clobber (reg:DF 76))]
3572 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3574 [(set_attr "length" "24")])
3577 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3578 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
3579 (use (match_operand:SI 2 "gpc_reg_operand" ""))
3580 (use (match_operand:DF 3 "gpc_reg_operand" ""))
3581 (clobber (match_operand:SI 4 "gpc_reg_operand" ""))
3582 (clobber (match_operand:SI 5 "gpc_reg_operand" ""))
3583 (clobber (reg:DF 76))]
3584 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3586 (xor:SI (match_dup 1)
3589 (unspec [(const_int 0)] 11))
3591 (unspec [(match_dup 4)
3592 (match_dup 5)] 12)) ;; low word
3594 (unspec [(match_dup 2)
3596 (match_dup 7)] 13)) ;; high word
3598 (unspec [(match_dup 7)
3601 (minus:DF (match_dup 0)
3605 operands[6] = GEN_INT (0x80000000);
3606 operands[7] = gen_rtx (REG, DFmode, FPMEM_REGNUM);
3609 (define_expand "floatunssidf2"
3610 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
3611 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
3614 (clobber (match_dup 4))
3615 (clobber (reg:DF 76))])]
3616 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3619 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
3620 operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode));
3621 operands[4] = gen_reg_rtx (Pmode);
3624 (define_insn "*floatunssidf2_internal"
3625 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
3626 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
3627 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
3628 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
3629 (clobber (match_operand:SI 4 "gpc_reg_operand" "=b"))
3630 (clobber (reg:DF 76))]
3631 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3633 [(set_attr "length" "20")])
3636 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3637 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
3638 (use (match_operand:SI 2 "gpc_reg_operand" ""))
3639 (use (match_operand:DF 3 "gpc_reg_operand" ""))
3640 (clobber (match_operand:SI 4 "gpc_reg_operand" "=b"))
3641 (clobber (reg:DF 76))]
3642 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3644 (unspec [(const_int 0)] 11))
3646 (unspec [(match_dup 1)
3647 (match_dup 4)] 12)) ;; low word
3649 (unspec [(match_dup 2)
3651 (match_dup 5)] 13)) ;; high word
3653 (unspec [(match_dup 5)
3656 (minus:DF (match_dup 0)
3658 "operands[5] = gen_rtx (REG, DFmode, FPMEM_REGNUM);")
3660 ;; Load up scratch register with base address + offset if needed
3661 (define_insn "*floatsidf2_loadaddr"
3662 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
3663 (unspec [(const_int 0)] 11))]
3667 if (rs6000_fpmem_offset > 32760)
3671 xop[0] = operands[0];
3672 xop[1] = (frame_pointer_needed) ? frame_pointer_rtx : stack_pointer_rtx;
3673 xop[2] = GEN_INT ((rs6000_fpmem_offset >> 16) & 0xffff);
3674 output_asm_insn (\"{cau %0,%2(%1)|addis %0,%1,%2}\", xop);
3676 else if (rs6000_fpmem_offset < 0)
3681 [(set_attr "length" "4")])
3683 (define_insn "*floatsidf2_store1"
3685 (unspec [(match_operand:SI 0 "gpc_reg_operand" "r")
3686 (match_operand:SI 1 "gpc_reg_operand" "r")] 12))]
3687 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3692 if (rs6000_fpmem_offset > 32760)
3694 else if (frame_pointer_needed)
3695 indx = frame_pointer_rtx;
3697 indx = stack_pointer_rtx;
3699 operands[2] = gen_rtx (MEM, SImode,
3700 gen_rtx (PLUS, Pmode,
3702 GEN_INT ((rs6000_fpmem_offset & 0xffff)
3703 + ((WORDS_BIG_ENDIAN != 0) * 4))));
3705 return \"{st|stw} %0,%2\";
3707 [(set_attr "type" "store")])
3709 (define_insn "*floatsidf2_store2"
3711 (unspec [(match_operand:SI 0 "gpc_reg_operand" "r")
3712 (match_operand:SI 1 "gpc_reg_operand" "r")
3714 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3719 if (rs6000_fpmem_offset > 32760)
3721 else if (frame_pointer_needed)
3722 indx = frame_pointer_rtx;
3724 indx = stack_pointer_rtx;
3726 operands[2] = gen_rtx (MEM, SImode,
3727 gen_rtx (PLUS, Pmode,
3729 GEN_INT ((rs6000_fpmem_offset & 0xffff)
3730 + ((WORDS_BIG_ENDIAN == 0) * 4))));
3732 return \"{st|stw} %0,%2\";
3734 [(set_attr "type" "store")])
3736 (define_insn "*floatsidf2_load"
3737 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3738 (unspec [(reg:DF 76)
3739 (match_operand:SI 1 "gpc_reg_operand" "b")] 14))]
3740 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3744 HOST_WIDE_INT offset = rs6000_fpmem_offset;
3746 if (rs6000_fpmem_offset > 32760)
3751 else if (frame_pointer_needed)
3752 indx = frame_pointer_rtx;
3754 indx = stack_pointer_rtx;
3756 operands[2] = gen_rtx (MEM, SImode,
3757 gen_rtx (PLUS, Pmode, indx, GEN_INT (offset)));
3759 return \"lfd %0,%2\";
3761 [(set_attr "type" "fpload")])
3763 (define_expand "fix_truncdfsi2"
3764 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
3765 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
3766 (clobber (match_dup 2))
3767 (clobber (match_dup 3))
3768 (clobber (match_dup 4))])]
3772 if (!TARGET_POWER2 && !TARGET_POWERPC)
3774 emit_insn (gen_trunc_call (operands[0], operands[1],
3775 gen_rtx (SYMBOL_REF, Pmode, RS6000_ITRUNC)));
3779 operands[2] = gen_reg_rtx (DImode);
3780 operands[3] = gen_reg_rtx (Pmode);
3781 operands[4] = gen_rtx (REG, DImode, FPMEM_REGNUM);
3784 (define_insn "*fix_truncdfsi2_internal"
3785 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3786 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
3787 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
3788 (clobber (match_operand:SI 3 "gpc_reg_operand" "=b"))
3789 (clobber (reg:DI 76))]
3792 [(set_attr "length" "12")])
3795 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3796 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
3797 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
3798 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))
3799 (clobber (reg:DI 76))]
3802 (sign_extend:DI (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))))
3804 (unspec [(const_int 0)] 11))
3806 (unspec [(match_dup 2)
3808 (set (match_operand:SI 0 "gpc_reg_operand" "")
3809 (unspec [(match_dup 4)
3810 (match_dup 3)] 16))]
3811 "operands[4] = gen_rtx (REG, DImode, FPMEM_REGNUM);")
3813 (define_insn "*fctiwz"
3814 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
3815 (sign_extend:DI (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))))]
3816 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
3817 "{fcirz|fctiwz} %0,%1"
3818 [(set_attr "type" "fp")])
3820 (define_insn "*fix_truncdfsi2_store"
3822 (unspec [(match_operand:DI 0 "gpc_reg_operand" "f")
3823 (match_operand:SI 1 "gpc_reg_operand" "b")] 15))]
3824 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
3829 if (rs6000_fpmem_offset > 32760)
3831 else if (frame_pointer_needed)
3832 indx = frame_pointer_rtx;
3834 indx = stack_pointer_rtx;
3836 operands[2] = gen_rtx (MEM, DFmode,
3837 gen_rtx (PLUS, Pmode,
3839 GEN_INT ((rs6000_fpmem_offset & 0xffff))));
3841 return \"stfd %0,%2\";
3843 [(set_attr "type" "fpstore")])
3845 (define_insn "*fix_truncdfsi2_load"
3846 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3847 (unspec [(reg:DI 76)
3848 (match_operand:SI 1 "gpc_reg_operand" "b")] 16))]
3849 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
3854 if (rs6000_fpmem_offset > 32760)
3856 else if (frame_pointer_needed)
3857 indx = frame_pointer_rtx;
3859 indx = stack_pointer_rtx;
3861 operands[2] = gen_rtx (MEM, DFmode,
3862 gen_rtx (PLUS, Pmode,
3864 GEN_INT ((rs6000_fpmem_offset & 0xffff)
3865 + ((WORDS_BIG_ENDIAN) ? 4 : 0))));
3867 return \"{l|lwz} %0,%2\";
3869 [(set_attr "type" "load")])
3871 (define_expand "fixuns_truncdfsi2"
3872 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3873 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
3874 "! TARGET_POWER2 && ! TARGET_POWERPC && TARGET_HARD_FLOAT"
3877 emit_insn (gen_trunc_call (operands[0], operands[1],
3878 gen_rtx (SYMBOL_REF, Pmode, RS6000_UITRUNC)));
3882 (define_expand "trunc_call"
3883 [(parallel [(set (match_operand:SI 0 "" "")
3884 (fix:SI (match_operand:DF 1 "" "")))
3885 (use (match_operand:SI 2 "" ""))])]
3889 rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]);
3890 rtx first = XVECEXP (insns, 0, 0);
3891 rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
3893 REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
3895 REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last));
3901 (define_expand "trunc_call_rtl"
3902 [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" ""))
3904 (parallel [(set (reg:SI 3)
3905 (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
3907 (clobber (scratch:SI))])
3908 (set (match_operand:SI 0 "gpc_reg_operand" "")
3913 rs6000_trunc_used = 1;
3916 (define_insn "floatdidf2"
3917 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3918 (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
3919 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3921 [(set_attr "type" "fp")])
3923 (define_insn "fix_truncdfdi2"
3924 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
3925 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
3926 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3928 [(set_attr "type" "fp")])
3930 ;; Define the DImode operations that can be done in a small number
3931 ;; of instructions. The & constraints are to prevent the register
3932 ;; allocator from allocating registers that overlap with the inputs
3933 ;; (for example, having an input in 7,8 and an output in 6,7). We
3934 ;; also allow for the the output being the same as one of the inputs.
3936 (define_insn "*adddi3_noppc64"
3937 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
3938 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
3939 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
3940 "! TARGET_POWERPC64"
3943 if (WORDS_BIG_ENDIAN)
3944 return (GET_CODE (operands[2])) != CONST_INT
3945 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
3946 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
3948 return (GET_CODE (operands[2])) != CONST_INT
3949 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
3950 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
3952 [(set_attr "length" "8")])
3954 (define_insn "*subdi3_noppc64"
3955 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
3956 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
3957 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
3958 "! TARGET_POWERPC64"
3961 if (WORDS_BIG_ENDIAN)
3962 return (GET_CODE (operands[1]) != CONST_INT)
3963 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
3964 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
3966 return (GET_CODE (operands[1]) != CONST_INT)
3967 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
3968 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
3970 [(set_attr "length" "8")])
3972 (define_insn "*negdi2_noppc64"
3973 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
3974 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
3975 "! TARGET_POWERPC64"
3978 return (WORDS_BIG_ENDIAN)
3979 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
3980 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
3982 [(set_attr "length" "8")])
3984 (define_expand "mulsidi3"
3985 [(set (match_operand:DI 0 "gpc_reg_operand" "")
3986 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
3987 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
3991 if (! TARGET_POWER && ! TARGET_POWERPC)
3993 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
3994 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
3995 emit_insn (gen_mull_call ());
3996 if (WORDS_BIG_ENDIAN)
3997 emit_move_insn (operands[0], gen_rtx (REG, DImode, 3));
4000 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
4001 gen_rtx (REG, SImode, 3));
4002 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
4003 gen_rtx (REG, SImode, 4));
4007 else if (TARGET_POWER)
4009 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
4014 (define_insn "mulsidi3_mq"
4015 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4016 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
4017 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
4018 (clobber (match_scratch:SI 3 "=q"))]
4020 "mul %0,%1,%2\;mfmq %L0"
4021 [(set_attr "type" "imul")
4022 (set_attr "length" "8")])
4024 (define_insn "*mulsidi3_powerpc"
4025 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
4026 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
4027 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
4028 "TARGET_POWERPC && ! TARGET_POWERPC64"
4031 return (WORDS_BIG_ENDIAN)
4032 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
4033 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
4035 [(set_attr "type" "imul")
4036 (set_attr "length" "8")])
4039 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4040 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
4041 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
4042 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
4045 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
4046 (sign_extend:DI (match_dup 2)))
4049 (mult:SI (match_dup 1)
4053 int endian = (WORDS_BIG_ENDIAN == 0);
4054 operands[3] = operand_subword (operands[0], endian, 0, DImode);
4055 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
4058 (define_insn "umulsidi3"
4059 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
4060 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
4061 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
4062 "TARGET_POWERPC && ! TARGET_POWERPC64"
4065 return (WORDS_BIG_ENDIAN)
4066 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
4067 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
4069 [(set_attr "type" "imul")
4070 (set_attr "length" "8")])
4073 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4074 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
4075 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
4076 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
4079 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
4080 (zero_extend:DI (match_dup 2)))
4083 (mult:SI (match_dup 1)
4087 int endian = (WORDS_BIG_ENDIAN == 0);
4088 operands[3] = operand_subword (operands[0], endian, 0, DImode);
4089 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
4092 (define_expand "smulsi3_highpart"
4093 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4095 (lshiftrt:DI (mult:DI (sign_extend:DI
4096 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4098 (match_operand:SI 2 "gpc_reg_operand" "r")))
4103 if (! TARGET_POWER && ! TARGET_POWERPC)
4105 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
4106 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
4107 emit_insn (gen_mulh_call ());
4108 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
4111 else if (TARGET_POWER)
4113 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
4118 (define_insn "smulsi3_highpart_mq"
4119 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4121 (lshiftrt:DI (mult:DI (sign_extend:DI
4122 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4124 (match_operand:SI 2 "gpc_reg_operand" "r")))
4126 (clobber (match_scratch:SI 3 "=q"))]
4129 [(set_attr "type" "imul")])
4132 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4134 (lshiftrt:DI (mult:DI (sign_extend:DI
4135 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4137 (match_operand:SI 2 "gpc_reg_operand" "r")))
4141 [(set_attr "type" "imul")])
4143 (define_insn "umulsi3_highpart"
4144 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4146 (lshiftrt:DI (mult:DI (zero_extend:DI
4147 (match_operand:SI 1 "gpc_reg_operand" "%r"))
4149 (match_operand:SI 2 "gpc_reg_operand" "r")))
4153 [(set_attr "type" "imul")])
4155 ;; If operands 0 and 2 are in the same register, we have a problem. But
4156 ;; operands 0 and 1 (the usual case) can be in the same register. That's
4157 ;; why we have the strange constraints below.
4158 (define_insn "ashldi3_power"
4159 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
4160 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
4161 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
4162 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
4165 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
4166 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
4167 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
4168 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
4169 [(set_attr "length" "8")])
4171 (define_insn "lshrdi3_power"
4172 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r")
4173 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
4174 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
4175 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
4178 {cal %0,0(0)|li %0,0}\;{s%A2i|s%A2wi} %L0,%1,%h2
4179 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
4180 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
4181 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
4182 [(set_attr "length" "8")])
4184 ;; Shift by a variable amount is too complex to be worth open-coding. We
4185 ;; just handle shifts by constants.
4186 (define_insn "ashrdi3_power"
4187 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4188 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
4189 (match_operand:SI 2 "const_int_operand" "M,i")))
4190 (clobber (match_scratch:SI 3 "=X,q"))]
4193 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
4194 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
4195 [(set_attr "length" "8")])
4197 ;; PowerPC64 DImode operations.
4199 (define_expand "adddi3"
4200 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4201 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
4202 (match_operand:DI 2 "add_operand" "")))]
4206 if (! TARGET_POWERPC64 && non_add_cint_operand (operands[2], DImode))
4210 ;; Discourage ai/addic because of carry but provide it in an alternative
4211 ;; allowing register zero as source.
4214 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
4215 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
4216 (match_operand:DI 2 "add_operand" "r,I,I,J")))]
4225 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4226 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
4227 (match_operand:DI 2 "reg_or_short_operand" "r,I"))
4229 (clobber (match_scratch:DI 3 "=r,r"))]
4234 [(set_attr "type" "compare")])
4237 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
4238 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
4239 (match_operand:DI 2 "reg_or_short_operand" "r,I"))
4241 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4242 (plus:DI (match_dup 1) (match_dup 2)))]
4247 [(set_attr "type" "compare")])
4249 ;; Split an add that we can't do in one insn into two insns, each of which
4250 ;; does one 16-bit part. This is used by combine. Note that the low-order
4251 ;; add should be last in case the result gets used in an address.
4254 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4255 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
4256 (match_operand:DI 2 "non_add_cint_operand" "")))]
4258 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
4259 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
4262 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
4263 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
4266 high+=0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
4268 operands[3] = GEN_INT (high);
4269 operands[4] = GEN_INT (low);
4272 (define_insn "one_cmpldi2"
4273 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4274 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
4279 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4280 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4282 (clobber (match_scratch:DI 2 "=r"))]
4285 [(set_attr "type" "compare")])
4288 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
4289 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4291 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4292 (not:DI (match_dup 1)))]
4295 [(set_attr "type" "compare")])
4298 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4299 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
4300 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
4307 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4308 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4309 (match_operand:DI 2 "gpc_reg_operand" "r"))
4311 (clobber (match_scratch:DI 3 "=r"))]
4314 [(set_attr "type" "compare")])
4317 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4318 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4319 (match_operand:DI 2 "gpc_reg_operand" "r"))
4321 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4322 (minus:DI (match_dup 1) (match_dup 2)))]
4325 [(set_attr "type" "compare")])
4327 (define_expand "subdi3"
4328 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4329 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
4330 (match_operand:DI 2 "reg_or_cint_operand" "")))]
4334 if (GET_CODE (operands[2]) == CONST_INT)
4336 emit_insn (gen_adddi3 (operands[0], operands[1],
4337 negate_rtx (DImode, operands[2])));
4342 (define_insn "absdi2"
4343 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4344 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
4345 (clobber (match_scratch:DI 2 "=&r,&r"))]
4347 "sradi %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0"
4348 [(set_attr "length" "12")])
4351 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4352 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
4353 (clobber (match_scratch:DI 2 "=&r,&r"))]
4354 "TARGET_POWERPC64 && reload_completed"
4355 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 31)))
4356 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
4357 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
4361 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4362 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
4363 (clobber (match_scratch:DI 2 "=&r,&r"))]
4365 "sradi %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2"
4366 [(set_attr "length" "12")])
4369 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4370 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
4371 (clobber (match_scratch:DI 2 "=&r,&r"))]
4372 "TARGET_POWERPC64 && reload_completed"
4373 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 31)))
4374 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
4375 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
4378 (define_expand "negdi2"
4379 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4380 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
4385 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4386 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
4391 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4392 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4394 (clobber (match_scratch:DI 2 "=r"))]
4397 [(set_attr "type" "compare")])
4400 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
4401 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4403 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4404 (neg:DI (match_dup 1)))]
4407 [(set_attr "type" "compare")])
4409 (define_insn "ffsdi2"
4410 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
4411 (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
4413 "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
4414 [(set_attr "length" "16")])
4416 (define_insn "muldi3"
4417 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4418 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4419 (match_operand:DI 2 "gpc_reg_operand" "r")))]
4422 [(set_attr "type" "imul")])
4424 (define_insn "smuldi3_highpart"
4425 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4427 (lshiftrt:TI (mult:TI (sign_extend:TI
4428 (match_operand:DI 1 "gpc_reg_operand" "%r"))
4430 (match_operand:DI 2 "gpc_reg_operand" "r")))
4434 [(set_attr "type" "imul")])
4436 (define_insn "umuldi3_highpart"
4437 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4439 (lshiftrt:TI (mult:TI (zero_extend:TI
4440 (match_operand:DI 1 "gpc_reg_operand" "%r"))
4442 (match_operand:DI 2 "gpc_reg_operand" "r")))
4446 [(set_attr "type" "imul")])
4448 (define_expand "divdi3"
4449 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4450 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
4451 (match_operand:DI 2 "reg_or_cint_operand" "")))]
4455 if (GET_CODE (operands[2]) == CONST_INT
4456 && exact_log2 (INTVAL (operands[2])) >= 0)
4459 operands[2] = force_reg (DImode, operands[2]);
4462 (define_expand "moddi3"
4463 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
4464 (use (match_operand:DI 1 "gpc_reg_operand" ""))
4465 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
4469 int i = exact_log2 (INTVAL (operands[2]));
4473 if (GET_CODE (operands[2]) != CONST_INT || i < 0)
4476 temp1 = gen_reg_rtx (DImode);
4477 temp2 = gen_reg_rtx (DImode);
4479 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
4480 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
4481 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
4486 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4487 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4488 (match_operand:DI 2 "const_int_operand" "N")))]
4489 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
4490 "sradi %0,%1,%p2\;addze %0,%0"
4491 [(set_attr "length" "8")])
4494 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4495 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4496 (match_operand:DI 2 "const_int_operand" "N"))
4498 (clobber (match_scratch:DI 3 "=r"))]
4499 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
4500 "sradi %3,%1,%p2\;addze. %3,%3"
4501 [(set_attr "type" "compare")
4502 (set_attr "length" "8")])
4505 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4506 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4507 (match_operand:DI 2 "const_int_operand" "N"))
4509 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4510 (div:DI (match_dup 1) (match_dup 2)))]
4511 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
4512 "sradi %0,%1,%p2\;addze. %0,%0"
4513 [(set_attr "type" "compare")
4514 (set_attr "length" "8")])
4517 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4518 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4519 (match_operand:DI 2 "gpc_reg_operand" "r")))]
4522 [(set_attr "type" "idiv")])
4524 (define_insn "udivdi3"
4525 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4526 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4527 (match_operand:DI 2 "gpc_reg_operand" "r")))]
4530 [(set_attr "type" "idiv")])
4532 (define_insn "rotldi3"
4533 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4534 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4535 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
4537 "rld%I2cl %0,%1,%H2,0")
4540 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4541 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4542 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
4544 (clobber (match_scratch:DI 3 "=r"))]
4546 "rld%I2cl. %3,%1,%H2,0"
4547 [(set_attr "type" "delayed_compare")])
4550 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4551 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4552 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
4554 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4555 (rotate:DI (match_dup 1) (match_dup 2)))]
4557 "rld%I2cl. %0,%1,%H2,0"
4558 [(set_attr "type" "delayed_compare")])
4560 (define_expand "ashldi3"
4561 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4562 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
4563 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4564 "TARGET_POWERPC64 || TARGET_POWER"
4567 if (TARGET_POWERPC64)
4569 else if (TARGET_POWER)
4571 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
4579 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4580 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4581 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4584 [(set_attr "length" "8")])
4587 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4588 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4589 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4591 (clobber (match_scratch:DI 3 "=r"))]
4594 [(set_attr "type" "delayed_compare")])
4597 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4598 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4599 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4601 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4602 (ashift:DI (match_dup 1) (match_dup 2)))]
4605 [(set_attr "type" "delayed_compare")])
4607 (define_expand "lshrdi3"
4608 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4609 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
4610 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4611 "TARGET_POWERPC64 || TARGET_POWER"
4614 if (TARGET_POWERPC64)
4616 else if (TARGET_POWER)
4618 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
4626 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4627 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4628 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4633 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4634 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4635 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4637 (clobber (match_scratch:DI 3 "=r"))]
4640 [(set_attr "type" "delayed_compare")])
4643 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4644 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4645 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4647 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4648 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
4651 [(set_attr "type" "delayed_compare")])
4653 (define_expand "ashrdi3"
4654 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4655 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
4656 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4657 "TARGET_POWERPC64 || TARGET_POWER"
4660 if (TARGET_POWERPC64)
4662 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
4664 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
4672 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4673 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4674 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4676 "srad%I2 %0,%1,%H2")
4679 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4680 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4681 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4683 (clobber (match_scratch:DI 3 "=r"))]
4685 "srad%I2. %3,%1,%H2"
4686 [(set_attr "type" "delayed_compare")])
4689 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4690 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4691 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4693 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4694 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
4696 "srad%I2. %0,%1,%H2"
4697 [(set_attr "type" "delayed_compare")])
4699 (define_insn "anddi3"
4700 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
4701 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
4702 (match_operand:DI 2 "and_operand" "?r,K,J")))
4703 (clobber (match_scratch:CC 3 "=X,x,x"))]
4711 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x")
4712 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
4713 (match_operand:DI 2 "and_operand" "r,K,J"))
4715 (clobber (match_scratch:DI 3 "=r,r,r"))]
4721 [(set_attr "type" "compare,compare,compare")])
4724 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x")
4725 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
4726 (match_operand:DI 2 "and_operand" "r,K,J"))
4728 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
4729 (and:DI (match_dup 1) (match_dup 2)))]
4735 [(set_attr "type" "compare,compare,compare")])
4737 ;; Take a AND with a constant that cannot be done in a single insn and try to
4738 ;; split it into two insns. This does not verify that the insns are valid
4739 ;; since this need not be done as combine will do it.
4742 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4743 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
4744 (match_operand:DI 2 "non_and_cint_operand" "")))]
4746 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
4747 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
4750 int maskval = INTVAL (operands[2]);
4751 int i, transitions, last_bit_value;
4752 int orig = maskval, first_c = maskval, second_c;
4754 /* We know that MASKVAL must have more than 2 bit-transitions. Start at
4755 the low-order bit and count for the third transition. When we get there,
4756 make a first mask that has everything to the left of that position
4757 a one. Then make the second mask to turn off whatever else is needed. */
4759 for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++)
4761 if (((maskval >>= 1) & 1) != last_bit_value)
4762 last_bit_value ^= 1, transitions++;
4764 if (transitions > 2)
4766 first_c |= (~0) << i;
4771 second_c = orig | ~ first_c;
4773 operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c);
4774 operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c);
4777 (define_insn "iordi3"
4778 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
4779 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
4780 (match_operand:DI 2 "logical_operand" "r,K,J")))]
4788 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4789 (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4790 (match_operand:DI 2 "gpc_reg_operand" "r"))
4792 (clobber (match_scratch:DI 3 "=r"))]
4795 [(set_attr "type" "compare")])
4798 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4799 (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4800 (match_operand:DI 2 "gpc_reg_operand" "r"))
4802 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4803 (ior:DI (match_dup 1) (match_dup 2)))]
4806 [(set_attr "type" "compare")])
4808 ;; Split an IOR that we can't do in one insn into two insns, each of which
4809 ;; does one 16-bit part. This is used by combine.
4812 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4813 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
4814 (match_operand:DI 2 "non_logical_cint_operand" "")))]
4816 [(set (match_dup 0) (ior:DI (match_dup 1) (match_dup 3)))
4817 (set (match_dup 0) (ior:DI (match_dup 0) (match_dup 4)))]
4820 operands[3] = gen_rtx (CONST_INT, VOIDmode,
4821 INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
4822 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
4825 (define_insn "xordi3"
4826 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
4827 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
4828 (match_operand:DI 2 "logical_operand" "r,K,J")))]
4836 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4837 (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4838 (match_operand:DI 2 "gpc_reg_operand" "r"))
4840 (clobber (match_scratch:DI 3 "=r"))]
4843 [(set_attr "type" "compare")])
4846 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4847 (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4848 (match_operand:DI 2 "gpc_reg_operand" "r"))
4850 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4851 (xor:DI (match_dup 1) (match_dup 2)))]
4854 [(set_attr "type" "compare")])
4856 ;; Split an XOR that we can't do in one insn into two insns, each of which
4857 ;; does one 16-bit part. This is used by combine.
4860 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4861 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
4862 (match_operand:DI 2 "non_logical_cint_operand" "")))]
4864 [(set (match_dup 0) (xor:DI (match_dup 1) (match_dup 3)))
4865 (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 4)))]
4868 operands[3] = gen_rtx (CONST_INT, VOIDmode,
4869 INTVAL (operands[2]) & 0xffff0000);
4870 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
4874 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4875 (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4876 (match_operand:DI 2 "gpc_reg_operand" "r"))))]
4881 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4882 (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4883 (match_operand:DI 2 "gpc_reg_operand" "r")))
4885 (clobber (match_scratch:DI 3 "=r"))]
4888 [(set_attr "type" "compare")])
4891 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4892 (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4893 (match_operand:DI 2 "gpc_reg_operand" "r")))
4895 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4896 (not:DI (xor:DI (match_dup 1) (match_dup 2))))]
4899 [(set_attr "type" "compare")])
4902 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4903 (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4904 (match_operand:DI 2 "gpc_reg_operand" "r")))]
4909 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4910 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4911 (match_operand:DI 2 "gpc_reg_operand" "r"))
4913 (clobber (match_scratch:DI 3 "=r"))]
4916 [(set_attr "type" "compare")])
4919 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4920 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4921 (match_operand:DI 2 "gpc_reg_operand" "r"))
4923 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4924 (and:DI (not:DI (match_dup 1)) (match_dup 2)))]
4927 [(set_attr "type" "compare")])
4930 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4931 (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4932 (match_operand:DI 2 "gpc_reg_operand" "r")))]
4937 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4938 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4939 (match_operand:DI 2 "gpc_reg_operand" "r"))
4941 (clobber (match_scratch:DI 3 "=r"))]
4944 [(set_attr "type" "compare")])
4947 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4948 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4949 (match_operand:DI 2 "gpc_reg_operand" "r"))
4951 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4952 (ior:DI (not:DI (match_dup 1)) (match_dup 2)))]
4955 [(set_attr "type" "compare")])
4958 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4959 (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
4960 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))]
4965 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4966 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
4967 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
4969 (clobber (match_scratch:DI 3 "=r"))]
4972 [(set_attr "type" "compare")])
4975 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4976 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
4977 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
4979 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4980 (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
4983 [(set_attr "type" "compare")])
4986 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4987 (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
4988 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))]
4993 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4994 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
4995 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
4997 (clobber (match_scratch:DI 3 "=r"))]
5000 [(set_attr "type" "compare")])
5003 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5004 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
5005 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
5007 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5008 (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
5011 [(set_attr "type" "compare")])
5013 ;; Now define ways of moving data around.
5015 ;; Elf specific ways of loading addresses for non-PIC code.
5016 ;; The output of this could be r0, but we limit it to base
5017 ;; registers, since almost all uses of this will need it
5018 ;; in a base register shortly.
5019 (define_insn "elf_high"
5020 [(set (match_operand:SI 0 "register_operand" "=b")
5021 (high:SI (match_operand 1 "" "")))]
5022 "TARGET_ELF && !TARGET_64BIT"
5023 "{cau|addis} %0,0,%1@ha")
5025 (define_insn "elf_low"
5026 [(set (match_operand:SI 0 "register_operand" "=r")
5027 (lo_sum:SI (match_operand:SI 1 "register_operand" "b")
5028 (match_operand 2 "" "")))]
5029 "TARGET_ELF && !TARGET_64BIT"
5030 "{cal %0,%a2@l(%1)|addi %0,%1,%2@l}")
5032 ;; Set up a register with a value from the GOT table
5034 (define_expand "movsi_got"
5035 [(set (match_operand:SI 0 "register_operand" "")
5036 (unspec [(match_operand:SI 1 "got_operand" "")
5038 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic"
5041 operands[2] = rs6000_got_register (operands[1]);
5044 (define_insn "*movsi_got_internal"
5045 [(set (match_operand:SI 0 "register_operand" "=r")
5046 (unspec [(match_operand:SI 1 "got_operand" "")
5047 (match_operand:SI 2 "register_operand" "b")] 8))]
5048 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
5049 "{l|lwz} %0,%a1@got(%2)"
5050 [(set_attr "type" "load")])
5052 ;; For SI, we special-case integers that can't be loaded in one insn. We
5053 ;; do the load 16-bits at a time. We could do this by loading from memory,
5054 ;; and this is even supposed to be faster, but it is simpler not to get
5055 ;; integers in the TOC.
5056 (define_expand "movsi"
5057 [(set (match_operand:SI 0 "general_operand" "")
5058 (match_operand:SI 1 "any_operand" ""))]
5062 if (GET_CODE (operands[0]) != REG)
5063 operands[1] = force_reg (SImode, operands[1]);
5065 /* Convert a move of a CONST_DOUBLE into a CONST_INT */
5066 if (GET_CODE (operands[1]) == CONST_DOUBLE)
5067 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
5069 /* Use default pattern for address of ELF small data */
5071 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5072 && (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
5073 && small_data_operand (operands[1], SImode))
5075 emit_insn (gen_rtx (SET, VOIDmode, operands[0], operands[1]));
5079 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5080 && flag_pic == 1 && got_operand (operands[1], SImode))
5082 emit_insn (gen_movsi_got (operands[0], operands[1]));
5086 if (TARGET_ELF && TARGET_NO_TOC && !TARGET_64BIT
5087 && CONSTANT_P (operands[1])
5088 && GET_CODE (operands[1]) != HIGH
5089 && GET_CODE (operands[1]) != CONST_INT)
5091 rtx target = (reload_completed || reload_in_progress)
5092 ? operands[0] : gen_reg_rtx (SImode);
5094 /* If this is a function address on -mcall-aixdesc or -mcall-nt,
5095 convert it to the address of the descriptor. */
5096 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
5097 && GET_CODE (operands[1]) == SYMBOL_REF
5098 && XSTR (operands[1], 0)[0] == '.')
5100 char *name = XSTR (operands[1], 0);
5102 while (*name == '.')
5104 new_ref = gen_rtx (SYMBOL_REF, Pmode, name);
5105 CONSTANT_POOL_ADDRESS_P (new_ref) = CONSTANT_POOL_ADDRESS_P (operands[1]);
5106 SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]);
5107 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
5108 operands[1] = new_ref;
5111 emit_insn (gen_elf_high (target, operands[1]));
5112 emit_insn (gen_elf_low (operands[0], target, operands[1]));
5116 if (GET_CODE (operands[1]) == CONST
5117 && DEFAULT_ABI == ABI_NT
5118 && !side_effects_p (operands[0]))
5120 rtx const_term = const0_rtx;
5121 rtx sym = eliminate_constant_term (XEXP (operands[1], 0), &const_term);
5122 if (sym && GET_CODE (const_term) == CONST_INT
5123 && (GET_CODE (sym) == SYMBOL_REF || GET_CODE (sym) == LABEL_REF))
5125 unsigned HOST_WIDE_INT value = INTVAL (const_term);
5126 int new_reg_p = (flag_expensive_optimizations
5127 && !reload_completed
5128 && !reload_in_progress);
5129 rtx tmp1 = (new_reg_p && value != 0) ? gen_reg_rtx (SImode) : operands[0];
5131 emit_insn (gen_movsi (tmp1, sym));
5132 if (INTVAL (const_term) != 0)
5134 if (value + 0x8000 < 0x10000)
5135 emit_insn (gen_addsi3 (operands[0], tmp1, GEN_INT (value)));
5139 HOST_WIDE_INT high_int = value & (~ (HOST_WIDE_INT) 0xffff);
5140 HOST_WIDE_INT low_int = value & 0xffff;
5141 rtx tmp2 = (!new_reg_p || !low_int) ? operands[0] : gen_reg_rtx (Pmode);
5143 if (low_int & 0x8000)
5144 high_int += 0x10000, low_int |= ((HOST_WIDE_INT) -1) << 16;
5146 emit_insn (gen_addsi3 (tmp2, tmp1, GEN_INT (high_int)));
5148 emit_insn (gen_addsi3 (operands[0], tmp2, GEN_INT (low_int)));
5154 fatal_insn (\"bad address\", operands[1]);
5157 if ((!TARGET_WINDOWS_NT || DEFAULT_ABI != ABI_NT)
5158 && CONSTANT_P (operands[1])
5159 && GET_CODE (operands[1]) != CONST_INT
5160 && GET_CODE (operands[1]) != HIGH
5161 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]))
5163 /* If we are to limit the number of things we put in the TOC and
5164 this is a symbol plus a constant we can add in one insn,
5165 just put the symbol in the TOC and add the constant. Don't do
5166 this if reload is in progress. */
5167 if (GET_CODE (operands[1]) == CONST
5168 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
5169 && GET_CODE (XEXP (operands[1], 0)) == PLUS
5170 && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode)
5171 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
5172 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
5173 && ! side_effects_p (operands[0]))
5175 rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0));
5176 rtx other = XEXP (XEXP (operands[1], 0), 1);
5178 emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other));
5182 operands[1] = force_const_mem (SImode, operands[1]);
5183 if (! memory_address_p (SImode, XEXP (operands[1], 0))
5184 && ! reload_in_progress)
5185 operands[1] = change_address (operands[1], SImode,
5186 XEXP (operands[1], 0));
5191 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
5192 (match_operand:SI 1 "input_operand" "r,S,T,U,m,r,I,J,n,R,*h,r,r,0"))]
5193 "gpc_reg_operand (operands[0], SImode)
5194 || gpc_reg_operand (operands[1], SImode)"
5197 {l|lwz} %0,[toc]%1(2)
5198 {l|lwz} %0,[toc]%l1(2)
5200 {l%U1%X1|lwz%U1%X1} %0,%1
5201 {st%U0%X0|stw%U0%X0} %1,%0
5210 [(set_attr "type" "*,load,load,*,load,store,*,*,*,*,*,*,mtjmpr,*")
5211 (set_attr "length" "4,4,4,4,4,4,4,4,8,4,4,4,4,4")])
5213 ;; Split a load of a large constant into the appropriate two-insn
5217 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5218 (match_operand:SI 1 "const_int_operand" ""))]
5219 "(unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
5220 && (INTVAL (operands[1]) & 0xffff) != 0"
5224 (ior:SI (match_dup 0)
5228 operands[2] = gen_rtx (CONST_INT, VOIDmode,
5229 INTVAL (operands[1]) & 0xffff0000);
5230 operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff);
5234 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
5235 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
5237 (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
5240 [(set_attr "type" "compare")])
5242 (define_expand "movhi"
5243 [(set (match_operand:HI 0 "general_operand" "")
5244 (match_operand:HI 1 "any_operand" ""))]
5248 if (GET_CODE (operands[0]) != REG)
5249 operands[1] = force_reg (HImode, operands[1]);
5251 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
5253 operands[1] = force_const_mem (HImode, operands[1]);
5254 if (! memory_address_p (HImode, XEXP (operands[1], 0))
5255 && ! reload_in_progress)
5256 operands[1] = change_address (operands[1], HImode,
5257 XEXP (operands[1], 0));
5262 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
5263 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
5264 "gpc_reg_operand (operands[0], HImode)
5265 || gpc_reg_operand (operands[1], HImode)"
5275 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
5277 (define_expand "movqi"
5278 [(set (match_operand:QI 0 "general_operand" "")
5279 (match_operand:QI 1 "any_operand" ""))]
5283 if (GET_CODE (operands[0]) != REG)
5284 operands[1] = force_reg (QImode, operands[1]);
5286 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
5288 operands[1] = force_const_mem (QImode, operands[1]);
5289 if (! memory_address_p (QImode, XEXP (operands[1], 0))
5290 && ! reload_in_progress)
5291 operands[1] = change_address (operands[1], QImode,
5292 XEXP (operands[1], 0));
5297 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
5298 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
5299 "gpc_reg_operand (operands[0], QImode)
5300 || gpc_reg_operand (operands[1], QImode)"
5310 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
5312 ;; Here is how to move condition codes around. When we store CC data in
5313 ;; an integer register or memory, we store just the high-order 4 bits.
5314 ;; This lets us not shift in the most common case of CR0.
5315 (define_expand "movcc"
5316 [(set (match_operand:CC 0 "nonimmediate_operand" "")
5317 (match_operand:CC 1 "nonimmediate_operand" ""))]
5322 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
5323 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
5324 "register_operand (operands[0], CCmode)
5325 || register_operand (operands[1], CCmode)"
5329 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
5331 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
5333 {l%U1%X1|lwz%U1%X1} %0,%1
5334 {st%U0%U1|stw%U0%U1} %1,%0"
5335 [(set_attr "type" "*,*,*,compare,*,*,load,store")
5336 (set_attr "length" "*,*,12,*,8,*,*,*")])
5338 ;; For floating-point, we normally deal with the floating-point registers
5339 ;; unless -msoft-float is used. The sole exception is that parameter passing
5340 ;; can produce floating-point values in fixed-point registers. Unless the
5341 ;; value is a simple constant or already in memory, we deal with this by
5342 ;; allocating memory and copying the value explicitly via that memory location.
5343 (define_expand "movsf"
5344 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5345 (match_operand:SF 1 "any_operand" ""))]
5349 /* If we are called from reload, we might be getting a SUBREG of a hard
5350 reg. So expand it. */
5351 if (GET_CODE (operands[0]) == SUBREG
5352 && GET_CODE (SUBREG_REG (operands[0])) == REG
5353 && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
5354 operands[0] = alter_subreg (operands[0]);
5355 if (GET_CODE (operands[1]) == SUBREG
5356 && GET_CODE (SUBREG_REG (operands[1])) == REG
5357 && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
5358 operands[1] = alter_subreg (operands[1]);
5360 if (TARGET_SOFT_FLOAT && GET_CODE (operands[0]) == MEM)
5361 operands[1] = force_reg (SFmode, operands[1]);
5363 else if (TARGET_HARD_FLOAT)
5365 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
5367 /* If this is a store to memory or another integer register do the
5368 move directly. Otherwise store to a temporary stack slot and
5369 load from there into a floating point register. */
5371 if (GET_CODE (operands[0]) == MEM
5372 || (GET_CODE (operands[0]) == REG
5373 && (REGNO (operands[0]) < 32
5374 || (reload_in_progress
5375 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))))
5377 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
5378 operand_subword (operands[1], 0, 0, SFmode));
5383 rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
5385 emit_move_insn (stack_slot, operands[1]);
5386 emit_move_insn (operands[0], stack_slot);
5391 if (GET_CODE (operands[0]) == MEM)
5393 /* If operands[1] is a register, it may have double-precision data
5394 in it, so truncate it to single precision. We need not do
5395 this for POWERPC. */
5396 if (! TARGET_POWERPC && TARGET_HARD_FLOAT
5397 && GET_CODE (operands[1]) == REG)
5400 = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
5401 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
5402 operands[1] = newreg;
5405 operands[1] = force_reg (SFmode, operands[1]);
5408 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
5410 if (GET_CODE (operands[1]) == MEM
5411 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
5412 || GET_CODE (operands[1]) == CONST_DOUBLE
5414 || (GET_CODE (operands[1]) == REG
5415 && (REGNO (operands[1]) < 32
5416 || (reload_in_progress
5417 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))))
5419 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
5420 operand_subword (operands[1], 0, 0, SFmode));
5425 rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
5427 emit_move_insn (stack_slot, operands[1]);
5428 emit_move_insn (operands[0], stack_slot);
5434 if (CONSTANT_P (operands[1]) && TARGET_HARD_FLOAT)
5436 operands[1] = force_const_mem (SFmode, operands[1]);
5437 if (! memory_address_p (SFmode, XEXP (operands[1], 0))
5438 && ! reload_in_progress)
5439 operands[1] = change_address (operands[1], SFmode,
5440 XEXP (operands[1], 0));
5445 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5446 (match_operand:SF 1 "const_double_operand" ""))]
5447 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], SFmode) <= 1 && REGNO (operands[0]) <= 31"
5448 [(set (match_dup 2) (match_dup 3))]
5454 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
5455 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5457 operands[2] = gen_rtx (SUBREG, SImode, operands[0], 0);
5458 operands[3] = GEN_INT(l);
5462 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5463 (match_operand:SF 1 "const_double_operand" ""))]
5464 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], SFmode) == 2 && REGNO (operands[0]) <= 31"
5465 [(set (match_dup 2) (match_dup 3))
5466 (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 4)))]
5472 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
5473 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5475 operands[2] = gen_rtx (SUBREG, SImode, operands[0], 0);
5476 operands[3] = GEN_INT(l & 0xffff0000);
5477 operands[4] = GEN_INT(l & 0x0000ffff);
5480 (define_insn "*movsf_hardfloat"
5481 [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m,!r,!r")
5482 (match_operand:SF 1 "input_operand" "f,m,f,G,Fn"))]
5483 "(gpc_reg_operand (operands[0], SFmode)
5484 || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT"
5491 [(set_attr "type" "fp,fpload,fpstore,*,*")
5492 (set_attr "length" "4,4,4,4,8")])
5494 (define_insn "*movsf_softfloat"
5495 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")
5496 (match_operand:SF 1 "input_operand" "r,m,r,I,J,R,G,Fn"))]
5497 "(gpc_reg_operand (operands[0], SFmode)
5498 || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT"
5501 {l%U1%X1|lwz%U1%X1} %0,%1
5502 {st%U0%X0|stw%U0%X0} %1,%0
5508 [(set_attr "type" "*,load,store,*,*,*,*,*")
5509 (set_attr "length" "4,4,4,4,4,4,4,8")])
5512 (define_expand "movdf"
5513 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5514 (match_operand:DF 1 "any_operand" ""))]
5518 if (GET_CODE (operands[0]) != REG)
5519 operands[1] = force_reg (DFmode, operands[1]);
5521 /* Stores between FPR and any non-FPR registers must go through a
5522 temporary stack slot. */
5524 if (TARGET_POWERPC64
5525 && GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
5526 && ((FP_REGNO_P (REGNO (operands[0]))
5527 && ! FP_REGNO_P (REGNO (operands[1])))
5528 || (FP_REGNO_P (REGNO (operands[1]))
5529 && ! FP_REGNO_P (REGNO (operands[0])))))
5531 rtx stack_slot = assign_stack_temp (DFmode, 8, 0);
5533 emit_move_insn (stack_slot, operands[1]);
5534 emit_move_insn (operands[0], stack_slot);
5538 if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode))
5540 operands[1] = force_const_mem (DFmode, operands[1]);
5541 if (! memory_address_p (DFmode, XEXP (operands[1], 0))
5542 && ! reload_in_progress)
5543 operands[1] = change_address (operands[1], DFmode,
5544 XEXP (operands[1], 0));
5549 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5550 (match_operand:DF 1 "const_int_operand" ""))]
5551 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) <= 1 && REGNO (operands[0]) <= 31"
5552 [(set (match_dup 2) (match_dup 4))
5553 (set (match_dup 3) (match_dup 1))]
5556 operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
5557 operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
5558 operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
5562 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5563 (match_operand:DF 1 "const_int_operand" ""))]
5564 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) >= 2 && REGNO (operands[0]) <= 31"
5565 [(set (match_dup 3) (match_dup 5))
5566 (set (match_dup 2) (match_dup 4))
5567 (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 6)))]
5570 HOST_WIDE_INT value = INTVAL (operands[1]);
5571 operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
5572 operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
5573 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
5574 operands[5] = GEN_INT (value & 0xffff0000);
5575 operands[6] = GEN_INT (value & 0x0000ffff);
5579 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5580 (match_operand:DF 1 "const_double_operand" ""))]
5581 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) <= 2 && REGNO (operands[0]) <= 31"
5582 [(set (match_dup 2) (match_dup 4))
5583 (set (match_dup 3) (match_dup 5))]
5586 operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
5587 operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
5589 #ifdef HOST_WORDS_BIG_ENDIAN
5590 operands[4] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
5591 operands[5] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
5593 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
5594 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
5599 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5600 (match_operand:DF 1 "const_double_operand" ""))]
5601 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) == 3 && REGNO (operands[0]) <= 31"
5602 [(set (match_dup 2) (match_dup 4))
5603 (set (match_dup 3) (match_dup 5))
5604 (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 6)))]
5609 rtx high_reg = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
5610 rtx low_reg = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
5612 #ifdef HOST_WORDS_BIG_ENDIAN
5613 high = CONST_DOUBLE_LOW (operands[1]);
5614 low = CONST_DOUBLE_HIGH (operands[1]);
5616 high = CONST_DOUBLE_HIGH (operands[1]);
5617 low = CONST_DOUBLE_LOW (operands[1]);
5620 if (((unsigned HOST_WIDE_INT) (low + 0x8000) < 0x10000)
5621 || (low & 0xffff) == 0)
5623 operands[2] = high_reg;
5624 operands[3] = low_reg;
5625 operands[4] = GEN_INT (high & 0xffff0000);
5626 operands[5] = GEN_INT (low);
5627 operands[6] = GEN_INT (high & 0x0000ffff);
5631 operands[2] = low_reg;
5632 operands[3] = high_reg;
5633 operands[4] = GEN_INT (low & 0xffff0000);
5634 operands[5] = GEN_INT (high);
5635 operands[6] = GEN_INT (low & 0x0000ffff);
5640 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5641 (match_operand:DF 1 "const_double_operand" ""))]
5642 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DFmode) >= 4 && REGNO (operands[0]) <= 31"
5643 [(set (match_dup 2) (match_dup 4))
5644 (set (match_dup 3) (match_dup 5))
5645 (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 6)))
5646 (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 7)))]
5649 HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
5650 HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[1]);
5652 operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
5653 operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
5654 operands[4] = GEN_INT (high & 0xffff0000);
5655 operands[5] = GEN_INT (low & 0xffff0000);
5656 operands[6] = GEN_INT (high & 0x0000ffff);
5657 operands[7] = GEN_INT (low & 0x0000ffff);
5661 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5662 (match_operand:DF 1 "easy_fp_constant" ""))]
5663 "TARGET_64BIT && reload_completed && REGNO (operands[0]) <= 31"
5664 [(set (subreg:DI (match_dup 0) 0) (subreg:DI (match_dup 1) 0))]
5667 ;; Don't have reload use general registers to load a constant. First,
5668 ;; it might not work if the output operand has is the equivalent of
5669 ;; a non-offsettable memref, but also it is less efficient than loading
5670 ;; the constant into an FP register, since it will probably be used there.
5671 ;; The "??" is a kludge until we can figure out a more reasonable way
5672 ;; of handling these non-offsettable values.
5673 (define_insn "*movdf_hardfloat32"
5674 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,!r,!r,f,f,m")
5675 (match_operand:DF 1 "input_operand" "r,o,r,G,H,F,f,m,f"))]
5676 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
5677 && (register_operand (operands[0], DFmode)
5678 || register_operand (operands[1], DFmode))"
5681 switch (which_alternative)
5684 /* We normally copy the low-numbered register first. However, if
5685 the first register operand 0 is the same as the second register of
5686 operand 1, we must copy in the opposite order. */
5687 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
5688 return \"mr %L0,%L1\;mr %0,%1\";
5690 return \"mr %0,%1\;mr %L0,%L1\";
5692 /* If the low-address word is used in the address, we must load it
5693 last. Otherwise, load it first. Note that we cannot have
5694 auto-increment in that case since the address register is known to be
5696 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
5698 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
5700 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
5702 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
5708 return \"fmr %0,%1\";
5710 return \"lfd%U1%X1 %0,%1\";
5712 return \"stfd%U0%X0 %1,%0\";
5715 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
5716 (set_attr "length" "8,8,8,8,12,16,*,*,*")])
5718 (define_insn "*movdf_softfloat32"
5719 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r,r,r")
5720 (match_operand:DF 1 "input_operand" "r,o,r,G,H,F"))]
5721 "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
5722 && (register_operand (operands[0], DFmode)
5723 || register_operand (operands[1], DFmode))"
5726 switch (which_alternative)
5729 /* We normally copy the low-numbered register first. However, if
5730 the first register operand 0 is the same as the second register of
5731 operand 1, we must copy in the opposite order. */
5732 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
5733 return \"mr %L0,%L1\;mr %0,%1\";
5735 return \"mr %0,%1\;mr %L0,%L1\";
5737 /* If the low-address word is used in the address, we must load it
5738 last. Otherwise, load it first. Note that we cannot have
5739 auto-increment in that case since the address register is known to be
5741 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
5743 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
5745 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
5747 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
5754 [(set_attr "type" "*,load,store,*,*,*")
5755 (set_attr "length" "8,8,8,8,12,16")])
5757 (define_insn "*movdf_hardfloat64"
5758 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,!r,!r,f,f,m")
5759 (match_operand:DF 1 "input_operand" "r,o,r,G,H,F,f,m,f"))]
5760 "TARGET_POWERPC64 && TARGET_HARD_FLOAT
5761 && (register_operand (operands[0], DFmode)
5762 || register_operand (operands[1], DFmode))"
5773 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
5774 (set_attr "length" "4,4,4,8,12,16,4,4,4")])
5776 (define_insn "*movdf_softfloat64"
5777 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r,r,r")
5778 (match_operand:DF 1 "input_operand" "r,o,r,G,H,F"))]
5779 "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
5780 && (register_operand (operands[0], DFmode)
5781 || register_operand (operands[1], DFmode))"
5789 [(set_attr "type" "*,load,store,*,*,*")
5790 (set_attr "length" "*,*,*,8,12,16")])
5792 ;; Next come the multi-word integer load and store and the load and store
5794 (define_expand "movdi"
5795 [(set (match_operand:DI 0 "general_operand" "")
5796 (match_operand:DI 1 "any_operand" ""))]
5800 if (GET_CODE (operands[0]) != REG)
5801 operands[1] = force_reg (DImode, operands[1]);
5804 && (GET_CODE (operands[1]) == CONST_DOUBLE
5805 || GET_CODE (operands[1]) == CONST_INT))
5810 if (GET_CODE (operands[1]) == CONST_DOUBLE)
5812 low = CONST_DOUBLE_LOW (operands[1]);
5813 high = CONST_DOUBLE_HIGH (operands[1]);
5816 #if HOST_BITS_PER_WIDE_INT == 32
5818 low = INTVAL (operands[1]);
5819 high = (low < 0) ? ~0 : 0;
5823 low = INTVAL (operands[1]) & 0xffffffff;
5824 high = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32;
5830 emit_move_insn (operands[0], GEN_INT (high));
5831 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT(32)));
5834 HOST_WIDE_INT low_low = low & 0xffff;
5835 HOST_WIDE_INT low_high = low & (~ (HOST_WIDE_INT) 0xffff);
5837 emit_insn (gen_iordi3 (operands[0], operands[0],
5838 GEN_INT (low_high)));
5840 emit_insn (gen_iordi3 (operands[0], operands[0],
5841 GEN_INT (low_low)));
5847 /* Stores between FPR and any non-FPR registers must go through a
5848 temporary stack slot. */
5850 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
5851 && ((FP_REGNO_P (REGNO (operands[0]))
5852 && ! FP_REGNO_P (REGNO (operands[1])))
5853 || (FP_REGNO_P (REGNO (operands[1]))
5854 && ! FP_REGNO_P (REGNO (operands[0])))))
5856 rtx stack_slot = assign_stack_temp (DImode, 8, 0);
5858 emit_move_insn (stack_slot, operands[1]);
5859 emit_move_insn (operands[0], stack_slot);
5864 (define_insn "*movdi_32"
5865 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
5866 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
5868 && (gpc_reg_operand (operands[0], DImode)
5869 || gpc_reg_operand (operands[1], DImode))"
5872 switch (which_alternative)
5875 /* We normally copy the low-numbered register first. However, if
5876 the first register operand 0 is the same as the second register of
5877 operand 1, we must copy in the opposite order. */
5878 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
5879 return \"mr %L0,%L1\;mr %0,%1\";
5881 return \"mr %0,%1\;mr %L0,%L1\";
5883 /* If the low-address word is used in the address, we must load it
5884 last. Otherwise, load it first. Note that we cannot have
5885 auto-increment in that case since the address register is known to be
5887 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
5889 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
5891 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
5893 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
5895 return \"fmr %0,%1\";
5897 return \"lfd%U1%X1 %0,%1\";
5899 return \"stfd%U0%X0 %1,%0\";
5908 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
5909 (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")])
5912 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5913 (match_operand:DI 1 "const_int_operand" ""))]
5914 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) <= 1"
5915 [(set (match_dup 2) (match_dup 4))
5916 (set (match_dup 3) (match_dup 1))]
5919 operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
5920 operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
5921 operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
5925 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5926 (match_operand:DI 1 "const_int_operand" ""))]
5927 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) >= 2"
5928 [(set (match_dup 3) (match_dup 5))
5929 (set (match_dup 2) (match_dup 4))
5930 (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 6)))]
5933 HOST_WIDE_INT value = INTVAL (operands[1]);
5934 operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
5935 operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
5936 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
5937 operands[5] = GEN_INT (value & 0xffff0000);
5938 operands[6] = GEN_INT (value & 0x0000ffff);
5942 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5943 (match_operand:DI 1 "const_double_operand" ""))]
5944 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) <= 2"
5945 [(set (match_dup 2) (match_dup 4))
5946 (set (match_dup 3) (match_dup 5))]
5949 operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
5950 operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
5951 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
5952 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
5956 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5957 (match_operand:DI 1 "const_double_operand" ""))]
5958 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) == 3"
5959 [(set (match_dup 2) (match_dup 4))
5960 (set (match_dup 3) (match_dup 5))
5961 (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 6)))]
5964 HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
5965 HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[1]);
5966 rtx high_reg = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
5967 rtx low_reg = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
5969 if (((unsigned HOST_WIDE_INT) (low + 0x8000) < 0x10000)
5970 || (low & 0xffff) == 0)
5972 operands[2] = high_reg;
5973 operands[3] = low_reg;
5974 operands[4] = GEN_INT (high & 0xffff0000);
5975 operands[5] = GEN_INT (low);
5976 operands[6] = GEN_INT (high & 0x0000ffff);
5980 operands[2] = low_reg;
5981 operands[3] = high_reg;
5982 operands[4] = GEN_INT (low & 0xffff0000);
5983 operands[5] = GEN_INT (high);
5984 operands[6] = GEN_INT (low & 0x0000ffff);
5989 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5990 (match_operand:DI 1 "const_double_operand" ""))]
5991 "TARGET_32BIT && reload_completed && num_insns_constant (operands[1], DImode) >= 4"
5992 [(set (match_dup 2) (match_dup 4))
5993 (set (match_dup 3) (match_dup 5))
5994 (set (match_dup 2) (ior:SI (match_dup 2) (match_dup 6)))
5995 (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 7)))]
5998 HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[1]);
5999 HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[1]);
6001 operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
6002 operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
6003 operands[4] = GEN_INT (high & 0xffff0000);
6004 operands[5] = GEN_INT (low & 0xffff0000);
6005 operands[6] = GEN_INT (high & 0x0000ffff);
6006 operands[7] = GEN_INT (low & 0x0000ffff);
6009 (define_insn "*movdi_64"
6010 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
6011 (match_operand:DI 1 "input_operand" "r,m,r,I,J,nF,R,f,m,f,*h,r,0"))]
6013 && (gpc_reg_operand (operands[0], DImode)
6014 || gpc_reg_operand (operands[1], DImode))"
6029 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
6030 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
6032 ;; Split a load of a large constant into the appropriate five-instruction
6033 ;; sequence. The expansion in movdi tries to perform the minimum number of
6034 ;; steps, but here we have to handle anything in a constant number of insns.
6037 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6038 (match_operand:DI 1 "const_double_operand" ""))]
6039 "TARGET_64BIT && num_insns_constant (operands[1], DImode) > 1"
6043 (ior:DI (match_dup 0)
6046 (ashift:DI (match_dup 0)
6049 (ior:DI (match_dup 0)
6052 (ior:DI (match_dup 0)
6059 if (GET_CODE (operands[1]) == CONST_DOUBLE)
6061 low = CONST_DOUBLE_LOW (operands[1]);
6062 high = CONST_DOUBLE_HIGH (operands[1]);
6065 #if HOST_BITS_PER_WIDE_INT == 32
6067 low = INTVAL (operands[1]);
6068 high = (low < 0) ? ~0 : 0;
6072 low = INTVAL (operands[1]) & 0xffffffff;
6073 high = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32;
6077 if ((high + 0x8000) < 0x10000
6078 && ((low & 0xffff) == 0 || (low & (~ (HOST_WIDE_INT) 0xffff)) == 0))
6081 operands[2] = GEN_INT (high & (~ (HOST_WIDE_INT) 0xffff));
6082 operands[3] = GEN_INT (high & 0xffff);
6083 operands[4] = GEN_INT (low & (~ (HOST_WIDE_INT) 0xffff));
6084 operands[5] = GEN_INT (low & 0xffff);
6088 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
6089 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
6091 (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
6094 [(set_attr "type" "compare")])
6096 ;; TImode is similar, except that we usually want to compute the address into
6097 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
6098 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
6099 (define_expand "movti"
6100 [(parallel [(set (match_operand:TI 0 "general_operand" "")
6101 (match_operand:TI 1 "general_operand" ""))
6102 (clobber (scratch:SI))])]
6103 "TARGET_STRING || TARGET_POWERPC64"
6106 if (GET_CODE (operands[0]) == MEM)
6107 operands[1] = force_reg (TImode, operands[1]);
6109 if (GET_CODE (operands[0]) == MEM
6110 && GET_CODE (XEXP (operands[0], 0)) != REG
6111 && ! reload_in_progress)
6112 operands[0] = change_address (operands[0], TImode,
6113 copy_addr_to_reg (XEXP (operands[0], 0)));
6115 if (GET_CODE (operands[1]) == MEM
6116 && GET_CODE (XEXP (operands[1], 0)) != REG
6117 && ! reload_in_progress)
6118 operands[1] = change_address (operands[1], TImode,
6119 copy_addr_to_reg (XEXP (operands[1], 0)));
6122 ;; We say that MQ is clobbered in the last alternative because the first
6123 ;; alternative would never get used otherwise since it would need a reload
6124 ;; while the 2nd alternative would not. We put memory cases first so they
6125 ;; are preferred. Otherwise, we'd try to reload the output instead of
6126 ;; giving the SCRATCH mq.
6128 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
6129 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
6130 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
6131 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
6132 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
6135 switch (which_alternative)
6141 return \"{stsi|stswi} %1,%P0,16\";
6144 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
6147 /* Normally copy registers with lowest numbered register copied first.
6148 But copy in the other order if the first register of the output
6149 is the second, third, or fourth register in the input. */
6150 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
6151 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
6152 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
6154 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
6156 /* If the address is not used in the output, we can use lsi. Otherwise,
6157 fall through to generating four loads. */
6158 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
6159 return \"{lsi|lswi} %0,%P1,16\";
6160 /* ... fall through ... */
6162 /* If the address register is the same as the register for the lowest-
6163 addressed word, load it last. Similarly for the next two words.
6164 Otherwise load lowest address to highest. */
6165 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
6167 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
6168 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
6169 REGNO (operands[0]) + 2, operands[1], 0))
6170 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
6171 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
6172 REGNO (operands[0]) + 3, operands[1], 0))
6173 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
6175 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
6178 [(set_attr "type" "store,store,*,load,load")
6179 (set_attr "length" "*,16,16,*,16")])
6182 [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
6183 (match_operand:TI 1 "reg_or_mem_operand" "r,r,m"))
6184 (clobber (match_scratch:SI 2 "=X,X,X"))]
6185 "TARGET_STRING && !TARGET_POWER && ! TARGET_POWERPC64
6186 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
6189 switch (which_alternative)
6195 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
6198 /* Normally copy registers with lowest numbered register copied first.
6199 But copy in the other order if the first register of the output
6200 is the second, third, or fourth register in the input. */
6201 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
6202 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
6203 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
6205 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
6207 /* If the address register is the same as the register for the lowest-
6208 addressed word, load it last. Similarly for the next two words.
6209 Otherwise load lowest address to highest. */
6210 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
6212 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
6213 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
6214 REGNO (operands[0]) + 2, operands[1], 0))
6215 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
6216 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
6217 REGNO (operands[0]) + 3, operands[1], 0))
6218 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
6220 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
6223 [(set_attr "type" "store,*,load")
6224 (set_attr "length" "16,16,16")])
6227 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
6228 (match_operand:TI 1 "input_operand" "r,m,r"))]
6229 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
6230 || gpc_reg_operand (operands[1], TImode))"
6233 switch (which_alternative)
6236 /* We normally copy the low-numbered register first. However, if
6237 the first register operand 0 is the same as the second register of
6238 operand 1, we must copy in the opposite order. */
6239 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
6240 return \"mr %L0,%L1\;mr %0,%1\";
6242 return \"mr %0,%1\;mr %L0,%L1\";
6244 /* If the low-address word is used in the address, we must load it
6245 last. Otherwise, load it first. Note that we cannot have
6246 auto-increment in that case since the address register is known to be
6248 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
6250 return \"ld %L0,%L1\;ld %0,%1\";
6252 return \"ld%U1 %0,%1\;ld %L0,%L1\";
6254 return \"std%U0 %1,%0\;std %L1,%L0\";
6257 [(set_attr "type" "*,load,store")
6258 (set_attr "length" "8,8,8")])
6260 (define_expand "load_multiple"
6261 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
6262 (match_operand:SI 1 "" ""))
6263 (use (match_operand:SI 2 "" ""))])]
6272 /* Support only loading a constant number of fixed-point registers from
6273 memory and only bother with this if more than two; the machine
6274 doesn't support more than eight. */
6275 if (GET_CODE (operands[2]) != CONST_INT
6276 || INTVAL (operands[2]) <= 2
6277 || INTVAL (operands[2]) > 8
6278 || GET_CODE (operands[1]) != MEM
6279 || GET_CODE (operands[0]) != REG
6280 || REGNO (operands[0]) >= 32)
6283 count = INTVAL (operands[2]);
6284 regno = REGNO (operands[0]);
6286 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
6287 from = force_reg (SImode, XEXP (operands[1], 0));
6289 for (i = 0; i < count; i++)
6290 XVECEXP (operands[3], 0, i)
6291 = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
6292 gen_rtx (MEM, SImode, plus_constant (from, i * 4)));
6296 [(match_parallel 0 "load_multiple_operation"
6297 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
6298 (mem:SI (match_operand:SI 2 "register_operand" "b")))])]
6302 /* We have to handle the case where the pseudo used to contain the address
6303 is assigned to one of the output registers. */
6305 int words = XVECLEN (operands[0], 0);
6308 if (XVECLEN (operands[0], 0) == 1)
6309 return \"{l|lwz} %1,0(%2)\";
6311 for (i = 0; i < words; i++)
6312 if (refers_to_regno_p (REGNO (operands[1]) + i,
6313 REGNO (operands[1]) + i + 1, operands[2], 0))
6317 xop[0] = operands[1];
6318 xop[1] = operands[2];
6319 xop[2] = GEN_INT (4 * (words-1));
6320 output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop);
6325 xop[0] = operands[1];
6326 xop[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
6327 xop[2] = GEN_INT (4 * (words-1));
6328 output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop);
6333 for (j = 0; j < words; j++)
6336 xop[0] = gen_rtx (REG, SImode, REGNO (operands[1]) + j);
6337 xop[1] = operands[2];
6338 xop[2] = GEN_INT (j * 4);
6339 output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop);
6341 xop[0] = operands[2];
6342 xop[1] = GEN_INT (i * 4);
6343 output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop);
6348 return \"{lsi|lswi} %1,%2,%N0\";
6350 [(set_attr "type" "load")
6351 (set_attr "length" "32")])
6354 (define_expand "store_multiple"
6355 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
6356 (match_operand:SI 1 "" ""))
6357 (clobber (scratch:SI))
6358 (use (match_operand:SI 2 "" ""))])]
6367 /* Support only storing a constant number of fixed-point registers to
6368 memory and only bother with this if more than two; the machine
6369 doesn't support more than eight. */
6370 if (GET_CODE (operands[2]) != CONST_INT
6371 || INTVAL (operands[2]) <= 2
6372 || INTVAL (operands[2]) > 8
6373 || GET_CODE (operands[0]) != MEM
6374 || GET_CODE (operands[1]) != REG
6375 || REGNO (operands[1]) >= 32)
6378 count = INTVAL (operands[2]);
6379 regno = REGNO (operands[1]);
6381 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1));
6382 to = force_reg (SImode, XEXP (operands[0], 0));
6384 XVECEXP (operands[3], 0, 0)
6385 = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]);
6386 XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode,
6387 gen_rtx (SCRATCH, SImode));
6389 for (i = 1; i < count; i++)
6390 XVECEXP (operands[3], 0, i + 1)
6391 = gen_rtx (SET, VOIDmode,
6392 gen_rtx (MEM, SImode, plus_constant (to, i * 4)),
6393 gen_rtx (REG, SImode, regno + i));
6397 [(match_parallel 0 "store_multiple_operation"
6398 [(set (match_operand:SI 1 "indirect_operand" "=Q")
6399 (match_operand:SI 2 "gpc_reg_operand" "r"))
6400 (clobber (match_scratch:SI 3 "=q"))])]
6401 "TARGET_STRING && TARGET_POWER"
6402 "{stsi|stswi} %2,%P1,%O0"
6403 [(set_attr "type" "store")])
6406 [(match_parallel 0 "store_multiple_operation"
6407 [(set (mem:SI (match_operand:SI 1 "register_operand" "b"))
6408 (match_operand:SI 2 "gpc_reg_operand" "r"))
6409 (clobber (match_scratch:SI 3 "X"))])]
6410 "TARGET_STRING && !TARGET_POWER"
6411 "{stsi|stswi} %2,%1,%O0"
6412 [(set_attr "type" "store")])
6415 ;; String/block move insn.
6416 ;; Argument 0 is the destination
6417 ;; Argument 1 is the source
6418 ;; Argument 2 is the length
6419 ;; Argument 3 is the alignment
6421 (define_expand "movstrsi"
6422 [(parallel [(set (match_operand:BLK 0 "" "")
6423 (match_operand:BLK 1 "" ""))
6424 (use (match_operand:SI 2 "" ""))
6425 (use (match_operand:SI 3 "" ""))])]
6429 if (expand_block_move (operands))
6435 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
6436 ;; register allocator doesn't have a clue about allocating 8 word registers
6437 (define_expand "movstrsi_8reg"
6438 [(parallel [(set (match_operand 0 "" "")
6439 (match_operand 1 "" ""))
6440 (use (match_operand 2 "" ""))
6441 (use (match_operand 3 "" ""))
6442 (clobber (reg:SI 5))
6443 (clobber (reg:SI 6))
6444 (clobber (reg:SI 7))
6445 (clobber (reg:SI 8))
6446 (clobber (reg:SI 9))
6447 (clobber (reg:SI 10))
6448 (clobber (reg:SI 11))
6449 (clobber (reg:SI 12))
6450 (clobber (match_scratch:SI 4 ""))])]
6455 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6456 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6457 (use (match_operand:SI 2 "immediate_operand" "i"))
6458 (use (match_operand:SI 3 "immediate_operand" "i"))
6459 (clobber (match_operand:SI 4 "register_operand" "=r"))
6460 (clobber (reg:SI 6))
6461 (clobber (reg:SI 7))
6462 (clobber (reg:SI 8))
6463 (clobber (reg:SI 9))
6464 (clobber (reg:SI 10))
6465 (clobber (reg:SI 11))
6466 (clobber (reg:SI 12))
6467 (clobber (match_scratch:SI 5 "=q"))]
6468 "TARGET_STRING && TARGET_POWER
6469 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0)
6470 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
6471 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
6472 && REGNO (operands[4]) == 5"
6473 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6474 [(set_attr "type" "load")
6475 (set_attr "length" "8")])
6478 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6479 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6480 (use (match_operand:SI 2 "immediate_operand" "i"))
6481 (use (match_operand:SI 3 "immediate_operand" "i"))
6482 (clobber (match_operand:SI 4 "register_operand" "=r"))
6483 (clobber (reg:SI 6))
6484 (clobber (reg:SI 7))
6485 (clobber (reg:SI 8))
6486 (clobber (reg:SI 9))
6487 (clobber (reg:SI 10))
6488 (clobber (reg:SI 11))
6489 (clobber (reg:SI 12))
6490 (clobber (match_scratch:SI 5 "X"))]
6491 "TARGET_STRING && !TARGET_POWER
6492 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0)
6493 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
6494 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
6495 && REGNO (operands[4]) == 5"
6496 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6497 [(set_attr "type" "load")
6498 (set_attr "length" "8")])
6500 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
6501 ;; register allocator doesn't have a clue about allocating 6 word registers
6502 (define_expand "movstrsi_6reg"
6503 [(parallel [(set (match_operand 0 "" "")
6504 (match_operand 1 "" ""))
6505 (use (match_operand 2 "" ""))
6506 (use (match_operand 3 "" ""))
6507 (clobber (reg:SI 7))
6508 (clobber (reg:SI 8))
6509 (clobber (reg:SI 9))
6510 (clobber (reg:SI 10))
6511 (clobber (reg:SI 11))
6512 (clobber (reg:SI 12))
6513 (clobber (match_scratch:SI 4 ""))])]
6518 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6519 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6520 (use (match_operand:SI 2 "immediate_operand" "i"))
6521 (use (match_operand:SI 3 "immediate_operand" "i"))
6522 (clobber (match_operand:SI 4 "register_operand" "=r"))
6523 (clobber (reg:SI 8))
6524 (clobber (reg:SI 9))
6525 (clobber (reg:SI 10))
6526 (clobber (reg:SI 11))
6527 (clobber (reg:SI 12))
6528 (clobber (match_scratch:SI 5 "=q"))]
6529 "TARGET_STRING && TARGET_POWER
6530 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
6531 && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12)
6532 && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
6533 && REGNO (operands[4]) == 7"
6534 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6535 [(set_attr "type" "load")
6536 (set_attr "length" "8")])
6539 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6540 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6541 (use (match_operand:SI 2 "immediate_operand" "i"))
6542 (use (match_operand:SI 3 "immediate_operand" "i"))
6543 (clobber (match_operand:SI 4 "register_operand" "=r"))
6544 (clobber (reg:SI 8))
6545 (clobber (reg:SI 9))
6546 (clobber (reg:SI 10))
6547 (clobber (reg:SI 11))
6548 (clobber (reg:SI 12))
6549 (clobber (match_scratch:SI 5 "X"))]
6550 "TARGET_STRING && !TARGET_POWER
6551 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
6552 && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12)
6553 && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
6554 && REGNO (operands[4]) == 7"
6555 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6556 [(set_attr "type" "load")
6557 (set_attr "length" "8")])
6559 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill problems
6561 (define_expand "movstrsi_4reg"
6562 [(parallel [(set (match_operand 0 "" "")
6563 (match_operand 1 "" ""))
6564 (use (match_operand 2 "" ""))
6565 (use (match_operand 3 "" ""))
6566 (clobber (reg:SI 9))
6567 (clobber (reg:SI 10))
6568 (clobber (reg:SI 11))
6569 (clobber (reg:SI 12))
6570 (clobber (match_scratch:SI 4 ""))])]
6575 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6576 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6577 (use (match_operand:SI 2 "immediate_operand" "i"))
6578 (use (match_operand:SI 3 "immediate_operand" "i"))
6579 (clobber (match_operand:SI 4 "register_operand" "=r"))
6580 (clobber (reg:SI 10))
6581 (clobber (reg:SI 11))
6582 (clobber (reg:SI 12))
6583 (clobber (match_scratch:SI 5 "=q"))]
6584 "TARGET_STRING && TARGET_POWER
6585 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
6586 && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12)
6587 && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
6588 && REGNO (operands[4]) == 9"
6589 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6590 [(set_attr "type" "load")
6591 (set_attr "length" "8")])
6594 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6595 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6596 (use (match_operand:SI 2 "immediate_operand" "i"))
6597 (use (match_operand:SI 3 "immediate_operand" "i"))
6598 (clobber (match_operand:SI 4 "register_operand" "=r"))
6599 (clobber (reg:SI 10))
6600 (clobber (reg:SI 11))
6601 (clobber (reg:SI 12))
6602 (clobber (match_scratch:SI 5 "X"))]
6603 "TARGET_STRING && !TARGET_POWER
6604 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
6605 && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12)
6606 && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
6607 && REGNO (operands[4]) == 9"
6608 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6609 [(set_attr "type" "load")
6610 (set_attr "length" "8")])
6612 ;; Move up to 8 bytes at a time.
6613 (define_expand "movstrsi_2reg"
6614 [(parallel [(set (match_operand 0 "" "")
6615 (match_operand 1 "" ""))
6616 (use (match_operand 2 "" ""))
6617 (use (match_operand 3 "" ""))
6618 (clobber (match_scratch:DI 4 ""))
6619 (clobber (match_scratch:SI 5 ""))])]
6620 "TARGET_STRING && !TARGET_64BIT"
6624 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6625 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6626 (use (match_operand:SI 2 "immediate_operand" "i"))
6627 (use (match_operand:SI 3 "immediate_operand" "i"))
6628 (clobber (match_scratch:DI 4 "=&r"))
6629 (clobber (match_scratch:SI 5 "=q"))]
6630 "TARGET_STRING && TARGET_POWER && !TARGET_64BIT
6631 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
6632 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6633 [(set_attr "type" "load")
6634 (set_attr "length" "8")])
6637 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6638 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6639 (use (match_operand:SI 2 "immediate_operand" "i"))
6640 (use (match_operand:SI 3 "immediate_operand" "i"))
6641 (clobber (match_scratch:DI 4 "=&r"))
6642 (clobber (match_scratch:SI 5 "X"))]
6643 "TARGET_STRING && !TARGET_POWER && !TARGET_64BIT
6644 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
6645 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6646 [(set_attr "type" "load")
6647 (set_attr "length" "8")])
6649 ;; Move up to 4 bytes at a time.
6650 (define_expand "movstrsi_1reg"
6651 [(parallel [(set (match_operand 0 "" "")
6652 (match_operand 1 "" ""))
6653 (use (match_operand 2 "" ""))
6654 (use (match_operand 3 "" ""))
6655 (clobber (match_scratch:SI 4 ""))
6656 (clobber (match_scratch:SI 5 ""))])]
6661 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6662 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6663 (use (match_operand:SI 2 "immediate_operand" "i"))
6664 (use (match_operand:SI 3 "immediate_operand" "i"))
6665 (clobber (match_scratch:SI 4 "=&r"))
6666 (clobber (match_scratch:SI 5 "=q"))]
6667 "TARGET_STRING && TARGET_POWER
6668 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
6669 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6670 [(set_attr "type" "load")
6671 (set_attr "length" "8")])
6674 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6675 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6676 (use (match_operand:SI 2 "immediate_operand" "i"))
6677 (use (match_operand:SI 3 "immediate_operand" "i"))
6678 (clobber (match_scratch:SI 4 "=&r"))
6679 (clobber (match_scratch:SI 5 "X"))]
6680 "TARGET_STRING && !TARGET_POWER
6681 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
6682 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6683 [(set_attr "type" "load")
6684 (set_attr "length" "8")])
6687 ;; Define insns that do load or store with update. Some of these we can
6688 ;; get by using pre-decrement or pre-increment, but the hardware can also
6689 ;; do cases where the increment is not the size of the object.
6691 ;; In all these cases, we use operands 0 and 1 for the register being
6692 ;; incremented because those are the operands that local-alloc will
6693 ;; tie and these are the pair most likely to be tieable (and the ones
6694 ;; that will benefit the most).
6697 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
6698 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
6699 (match_operand:DI 2 "reg_or_short_operand" "r,I"))))
6700 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
6701 (plus:DI (match_dup 1) (match_dup 2)))]
6706 [(set_attr "type" "load")])
6709 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
6711 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
6712 (match_operand:DI 2 "gpc_reg_operand" "r")))))
6713 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
6714 (plus:DI (match_dup 1) (match_dup 2)))]
6717 [(set_attr "type" "load")])
6719 (define_insn "movdi_update"
6720 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
6721 (match_operand:DI 2 "reg_or_short_operand" "r,I")))
6722 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
6723 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
6724 (plus:DI (match_dup 1) (match_dup 2)))]
6729 [(set_attr "type" "store")])
6732 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
6733 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6734 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
6735 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6736 (plus:SI (match_dup 1) (match_dup 2)))]
6739 {lux|lwzux} %3,%0,%2
6740 {lu|lwzu} %3,%2(%0)"
6741 [(set_attr "type" "load")])
6743 (define_insn "movsi_update"
6744 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6745 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
6746 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6747 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6748 (plus:SI (match_dup 1) (match_dup 2)))]
6751 {stux|stwux} %3,%0,%2
6752 {stu|stwu} %3,%2(%0)"
6753 [(set_attr "type" "store")])
6756 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
6757 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6758 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
6759 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6760 (plus:SI (match_dup 1) (match_dup 2)))]
6765 [(set_attr "type" "load")])
6768 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
6770 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6771 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
6772 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6773 (plus:SI (match_dup 1) (match_dup 2)))]
6778 [(set_attr "type" "load")])
6781 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
6783 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6784 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
6785 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6786 (plus:SI (match_dup 1) (match_dup 2)))]
6791 [(set_attr "type" "load")])
6794 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6795 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
6796 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
6797 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6798 (plus:SI (match_dup 1) (match_dup 2)))]
6803 [(set_attr "type" "store")])
6806 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
6807 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6808 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
6809 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6810 (plus:SI (match_dup 1) (match_dup 2)))]
6815 [(set_attr "type" "load")])
6818 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
6820 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6821 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
6822 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6823 (plus:SI (match_dup 1) (match_dup 2)))]
6828 [(set_attr "type" "load")])
6831 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6832 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
6833 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
6834 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6835 (plus:SI (match_dup 1) (match_dup 2)))]
6840 [(set_attr "type" "store")])
6843 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
6844 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6845 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
6846 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6847 (plus:SI (match_dup 1) (match_dup 2)))]
6852 [(set_attr "type" "fpload")])
6855 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6856 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
6857 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
6858 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6859 (plus:SI (match_dup 1) (match_dup 2)))]
6864 [(set_attr "type" "fpstore")])
6867 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
6868 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6869 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
6870 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6871 (plus:SI (match_dup 1) (match_dup 2)))]
6876 [(set_attr "type" "fpload")])
6879 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6880 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
6881 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
6882 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6883 (plus:SI (match_dup 1) (match_dup 2)))]
6888 [(set_attr "type" "fpstore")])
6890 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
6893 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6894 (match_operand:DF 1 "memory_operand" ""))
6895 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
6896 (match_operand:DF 3 "memory_operand" ""))]
6898 && TARGET_HARD_FLOAT
6899 && registers_ok_for_quad_peep (operands[0], operands[2])
6900 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
6901 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
6905 [(set (match_operand:DF 0 "memory_operand" "")
6906 (match_operand:DF 1 "gpc_reg_operand" "f"))
6907 (set (match_operand:DF 2 "memory_operand" "")
6908 (match_operand:DF 3 "gpc_reg_operand" "f"))]
6910 && TARGET_HARD_FLOAT
6911 && registers_ok_for_quad_peep (operands[1], operands[3])
6912 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
6913 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
6916 ;; Next come insns related to the calling sequence.
6918 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
6919 ;; We move the back-chain and decrement the stack pointer.
6921 (define_expand "allocate_stack"
6923 (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_short_operand" "")))]
6926 { rtx chain = gen_reg_rtx (Pmode);
6927 rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx);
6930 emit_move_insn (chain, stack_bot);
6932 /* Under Windows NT, we need to add stack probes for large/variable allocations,
6933 so do it via a call to the external function alloca, instead of doing it
6935 if (DEFAULT_ABI == ABI_NT
6936 && (GET_CODE (operands[0]) != CONST_INT || INTVAL (operands[0]) > 4096))
6938 rtx tmp = gen_reg_rtx (SImode);
6939 emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode, \"__allocate_stack\"),
6940 tmp, 0, SImode, 1, operands[0], Pmode);
6941 emit_insn (gen_set_sp (tmp));
6945 if (GET_CODE (operands[0]) != CONST_INT
6946 || INTVAL (operands[0]) < -32767
6947 || INTVAL (operands[0]) > 32768)
6949 neg_op0 = gen_reg_rtx (Pmode);
6951 emit_insn (gen_negsi2 (neg_op0, operands[0]));
6953 emit_insn (gen_negdi2 (neg_op0, operands[0]));
6956 neg_op0 = GEN_INT (- INTVAL (operands[0]));
6959 emit_insn (gen_movsi_update (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
6961 emit_insn (gen_movdi_update (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
6966 ;; Marker to indicate that the stack pointer was changed under NT in
6967 ;; ways not known to the compiler
6969 (define_insn "set_sp"
6971 (unspec [(match_operand:SI 0 "register_operand" "r")] 7))]
6974 [(set_attr "length" "0")])
6976 ;; These patterns say how to save and restore the stack pointer. We need not
6977 ;; save the stack pointer at function level since we are careful to
6978 ;; preserve the backchain. At block level, we have to restore the backchain
6979 ;; when we restore the stack pointer.
6981 ;; For nonlocal gotos, we must save both the stack pointer and its
6982 ;; backchain and restore both. Note that in the nonlocal case, the
6983 ;; save area is a memory location.
6985 (define_expand "save_stack_function"
6986 [(use (const_int 0))]
6990 (define_expand "restore_stack_function"
6991 [(use (const_int 0))]
6995 (define_expand "restore_stack_block"
6996 [(set (match_dup 2) (mem:SI (match_operand:SI 0 "register_operand" "")))
6997 (set (match_dup 0) (match_operand:SI 1 "register_operand" ""))
6998 (set (mem:SI (match_dup 0)) (match_dup 2))]
7001 { operands[2] = gen_reg_rtx (SImode); }")
7003 (define_expand "save_stack_nonlocal"
7004 [(match_operand:DI 0 "memory_operand" "")
7005 (match_operand:SI 1 "register_operand" "")]
7009 rtx temp = gen_reg_rtx (SImode);
7011 /* Copy the backchain to the first word, sp to the second. */
7012 emit_move_insn (temp, gen_rtx (MEM, SImode, operands[1]));
7013 emit_move_insn (operand_subword (operands[0], 0, 0, DImode), temp);
7014 emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]);
7018 (define_expand "restore_stack_nonlocal"
7019 [(match_operand:SI 0 "register_operand" "")
7020 (match_operand:DI 1 "memory_operand" "")]
7024 rtx temp = gen_reg_rtx (SImode);
7026 /* Restore the backchain from the first word, sp from the second. */
7027 emit_move_insn (temp, operand_subword (operands[1], 0, 0, DImode));
7028 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode));
7029 emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp);
7034 ;; A function pointer under AIX is a pointer to a data area whose first word
7035 ;; contains the actual address of the function, whose second word contains a
7036 ;; pointer to its TOC, and whose third word contains a value to place in the
7037 ;; static chain register (r11). Note that if we load the static chain, our
7038 ;; "trampoline" need not have any executable code.
7040 ;; operands[0] is a register pointing to the 3 word descriptor (aka, the function address)
7041 ;; operands[1] is the stack size to clean up
7042 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for AIX)
7043 ;; operands[3] is location to store the TOC
7044 ;; operands[4] is the TOC register
7045 ;; operands[5] is the static chain register
7047 ;; We do not break this into separate insns, so that the scheduler will not try
7048 ;; to move the load of the new TOC before any loads from the TOC.
7050 (define_insn "call_indirect_aix"
7051 [(call (mem:SI (match_operand:SI 0 "register_operand" "b"))
7052 (match_operand 1 "const_int_operand" "n"))
7053 (use (match_operand 2 "const_int_operand" "n"))
7054 (use (match_operand 3 "offsettable_addr_operand" "p"))
7055 (use (match_operand 4 "register_operand" "r"))
7056 (clobber (match_operand 5 "register_operand" "=r"))
7057 (clobber (match_scratch:SI 6 "=&r"))
7058 (clobber (match_scratch:SI 7 "=l"))]
7059 "DEFAULT_ABI == ABI_AIX
7060 && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)"
7061 "{st|stw} %4,%a3\;{l|lwz} %6,0(%0)\;{l|lwz} %4,4(%0)\;mt%7 %6\;{l|lwz} %5,8(%0)\;{brl|blrl}\;{l|lwz} %4,%a3"
7062 [(set_attr "type" "load")
7063 (set_attr "length" "28")])
7065 (define_insn "call_value_indirect_aix"
7066 [(set (match_operand 0 "register_operand" "fg")
7067 (call (mem:SI (match_operand:SI 1 "register_operand" "b"))
7068 (match_operand 2 "const_int_operand" "n")))
7069 (use (match_operand 3 "const_int_operand" "n"))
7070 (use (match_operand 4 "offsettable_addr_operand" "p"))
7071 (use (match_operand 5 "register_operand" "r"))
7072 (clobber (match_operand 6 "register_operand" "=r"))
7073 (clobber (match_scratch:SI 7 "=&r"))
7074 (clobber (match_scratch:SI 8 "=l"))]
7075 "DEFAULT_ABI == ABI_AIX
7076 && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)"
7077 "{st|stw} %5,%a4\;{l|lwz} %7,0(%1)\;{l|lwz} %5,4(%1);\;mt%8 %7\;{l|lwz} %6,8(%1)\;{brl|blrl}\;{l|lwz} %5,%a4"
7078 [(set_attr "type" "load")
7079 (set_attr "length" "28")])
7081 ;; A function pointer undef NT is a pointer to a data area whose first word
7082 ;; contains the actual address of the function, whose second word contains a
7083 ;; pointer to its TOC. The static chain is not stored under NT, which means
7084 ;; that we need a trampoline.
7086 ;; operands[0] is an SImode pseudo in which we place the address of the function.
7087 ;; operands[1] is the stack size to clean up
7088 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for NT)
7089 ;; operands[3] is location to store the TOC
7090 ;; operands[4] is the TOC register
7092 ;; We do not break this into separate insns, so that the scheduler will not try
7093 ;; to move the load of the new TOC before any loads from the TOC.
7095 (define_insn "call_indirect_nt"
7096 [(call (mem:SI (match_operand:SI 0 "register_operand" "b"))
7097 (match_operand 1 "const_int_operand" "n"))
7098 (use (match_operand 2 "const_int_operand" "n"))
7099 (use (match_operand 3 "offsettable_addr_operand" "p"))
7100 (use (match_operand 4 "register_operand" "r"))
7101 (clobber (match_scratch:SI 5 "=&r"))
7102 (clobber (match_scratch:SI 6 "=l"))]
7103 "DEFAULT_ABI == ABI_NT
7104 && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)"
7105 "{st|stw} %4,%a3\;{l|lwz} %5,0(%0)\;{l|lwz} %4,4(%0)\;mt%6 %5\;{brl|blrl}\;{l|lwz} %4,%a3"
7106 [(set_attr "type" "load")
7107 (set_attr "length" "24")])
7109 (define_insn "call_value_indirect_nt"
7110 [(set (match_operand 0 "register_operand" "fg")
7111 (call (mem:SI (match_operand:SI 1 "register_operand" "b"))
7112 (match_operand 2 "const_int_operand" "n")))
7113 (use (match_operand 3 "const_int_operand" "n"))
7114 (use (match_operand 4 "offsettable_addr_operand" "p"))
7115 (use (match_operand 5 "register_operand" "r"))
7116 (clobber (match_scratch:SI 6 "=&r"))
7117 (clobber (match_scratch:SI 7 "=l"))]
7118 "DEFAULT_ABI == ABI_NT
7119 && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)"
7120 "{st|stw} %5,%a4\;{l|lwz} %6,0(%1)\;{l|lwz} %5,4(%1)\;mt%7 %6\;{brl|blrl}\;{l|lwz} %5,%a4"
7121 [(set_attr "type" "load")
7122 (set_attr "length" "24")])
7124 ;; A function pointer under System V is just a normal pointer
7125 ;; operands[0] is the function pointer
7126 ;; operands[1] is the stack size to clean up
7127 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument which indicates how to set cr1
7129 (define_insn "call_indirect_sysv"
7130 [(call (mem:SI (match_operand:SI 0 "register_operand" "l,l"))
7131 (match_operand 1 "const_int_operand" "n,n"))
7132 (use (match_operand 2 "const_int_operand" "O,n"))
7133 (clobber (match_scratch:SI 3 "=l,l"))]
7134 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC"
7137 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
7138 output_asm_insn (\"crxor 6,6,6\", operands);
7140 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
7141 output_asm_insn (\"creqv 6,6,6\", operands);
7143 return \"{brl|blrl}\";
7145 [(set_attr "type" "jmpreg")
7146 (set_attr "length" "4,8")])
7148 (define_insn "call_value_indirect_sysv"
7149 [(set (match_operand 0 "register_operand" "=fg,fg")
7150 (call (mem:SI (match_operand:SI 1 "register_operand" "l,l"))
7151 (match_operand 2 "const_int_operand" "n,n")))
7152 (use (match_operand 3 "const_int_operand" "O,n"))
7153 (clobber (match_scratch:SI 4 "=l,l"))]
7154 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC"
7157 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
7158 output_asm_insn (\"crxor 6,6,6\", operands);
7160 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
7161 output_asm_insn (\"creqv 6,6,6\", operands);
7163 return \"{brl|blrl}\";
7165 [(set_attr "type" "jmpreg")
7166 (set_attr "length" "4,8")])
7168 ;; Now the definitions for the call and call_value insns
7169 (define_expand "call"
7170 [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" ""))
7171 (match_operand 1 "" ""))
7172 (use (match_operand 2 "" ""))
7173 (clobber (scratch:SI))])]
7177 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
7180 operands[0] = XEXP (operands[0], 0);
7182 /* Convert NT DLL imports into an indirect call. */
7183 if (GET_CODE (operands[0]) == SYMBOL_REF
7184 && (INTVAL (operands[2]) & CALL_NT_DLLIMPORT) != 0)
7186 operands[0] = rs6000_dll_import_ref (operands[0]);
7187 operands[2] = GEN_INT ((int)CALL_NORMAL);
7190 if (GET_CODE (operands[0]) != SYMBOL_REF
7191 || (INTVAL (operands[2]) & CALL_LONG) != 0)
7193 if (INTVAL (operands[2]) & CALL_LONG)
7194 operands[0] = rs6000_longcall_ref (operands[0]);
7196 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS)
7197 emit_call_insn (gen_call_indirect_sysv (force_reg (Pmode, operands[0]),
7198 operands[1], operands[2]));
7201 rtx toc_reg = gen_rtx (REG, Pmode, 2);
7202 rtx toc_addr = RS6000_SAVE_TOC;
7204 if (DEFAULT_ABI == ABI_AIX)
7206 /* AIX function pointers are really pointers to a three word area */
7207 rtx static_chain = gen_rtx (REG, Pmode, STATIC_CHAIN_REGNUM);
7208 emit_call_insn (gen_call_indirect_aix (force_reg (Pmode, operands[0]),
7209 operands[1], operands[2],
7210 toc_addr, toc_reg, static_chain));
7212 else if (DEFAULT_ABI == ABI_NT)
7214 /* NT function pointers are really pointers to a two word area */
7215 rs6000_save_toc_p = 1;
7216 emit_call_insn (gen_call_indirect_nt (force_reg (Pmode, operands[0]),
7217 operands[1], operands[2],
7218 toc_addr, toc_reg));
7227 (define_expand "call_value"
7228 [(parallel [(set (match_operand 0 "" "")
7229 (call (mem:SI (match_operand:SI 1 "address_operand" ""))
7230 (match_operand 2 "" "")))
7231 (use (match_operand 3 "" ""))
7232 (clobber (scratch:SI))])]
7236 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
7239 operands[1] = XEXP (operands[1], 0);
7241 /* Convert NT DLL imports into an indirect call. */
7242 if (GET_CODE (operands[1]) == SYMBOL_REF
7243 && (INTVAL (operands[3]) & CALL_NT_DLLIMPORT) != 0)
7245 operands[1] = rs6000_dll_import_ref (operands[1]);
7246 operands[3] = GEN_INT ((int)CALL_NORMAL);
7249 if (GET_CODE (operands[1]) != SYMBOL_REF
7250 || (INTVAL (operands[3]) & CALL_LONG) != 0)
7252 if (INTVAL (operands[2]) & CALL_LONG)
7253 operands[1] = rs6000_longcall_ref (operands[1]);
7255 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS)
7256 emit_call_insn (gen_call_value_indirect_sysv (operands[0], operands[1],
7257 operands[2], operands[3]));
7260 rtx toc_reg = gen_rtx (REG, Pmode, 2);
7261 rtx toc_addr = RS6000_SAVE_TOC;
7263 if (DEFAULT_ABI == ABI_AIX)
7265 /* AIX function pointers are really pointers to a three word area */
7266 rtx static_chain = gen_rtx (REG, Pmode, STATIC_CHAIN_REGNUM);
7267 emit_call_insn (gen_call_value_indirect_aix (operands[0],
7268 force_reg (Pmode, operands[1]),
7269 operands[2], operands[3],
7270 toc_addr, toc_reg, static_chain));
7272 else if (DEFAULT_ABI == ABI_NT)
7274 /* NT function pointers are really pointers to a two word area */
7275 rs6000_save_toc_p = 1;
7276 emit_call_insn (gen_call_value_indirect_nt (operands[0],
7277 force_reg (Pmode, operands[1]),
7278 operands[2], operands[3],
7279 toc_addr, toc_reg));
7288 ;; Call to function in current module. No TOC pointer reload needed.
7289 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
7290 ;; either the function was not prototyped, or it was prototyped as a
7291 ;; variable argument function. It is > 0 if FP registers were passed
7292 ;; and < 0 if they were not.
7295 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
7296 (match_operand 1 "" "g,g"))
7297 (use (match_operand:SI 2 "immediate_operand" "O,n"))
7298 (clobber (match_scratch:SI 3 "=l,l"))]
7299 "(INTVAL (operands[2]) & CALL_LONG) == 0"
7302 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
7303 output_asm_insn (\"crxor 6,6,6\", operands);
7305 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
7306 output_asm_insn (\"creqv 6,6,6\", operands);
7310 [(set_attr "type" "branch")
7311 (set_attr "length" "4,8")])
7313 ;; Call to function which may be in another module. Restore the TOC
7314 ;; pointer (r2) after the call unless this is System V.
7315 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
7316 ;; either the function was not prototyped, or it was prototyped as a
7317 ;; variable argument function. It is > 0 if FP registers were passed
7318 ;; and < 0 if they were not.
7321 [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s"))
7322 (match_operand 1 "" "fg,fg"))
7323 (use (match_operand:SI 2 "immediate_operand" "O,n"))
7324 (clobber (match_scratch:SI 3 "=l,l"))]
7325 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
7326 && (INTVAL (operands[2]) & CALL_LONG) == 0"
7329 /* Indirect calls should go through call_indirect */
7330 if (GET_CODE (operands[0]) == REG)
7333 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
7334 output_asm_insn (\"crxor 6,6,6\", operands);
7336 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
7337 output_asm_insn (\"creqv 6,6,6\", operands);
7339 return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\";
7341 [(set_attr "type" "branch")
7342 (set_attr "length" "8,12")])
7345 [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s"))
7346 (match_operand 1 "" "fg,fg"))
7347 (use (match_operand:SI 2 "immediate_operand" "O,n"))
7348 (clobber (match_scratch:SI 3 "=l,l"))]
7349 "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
7350 && (INTVAL (operands[2]) & CALL_LONG) == 0"
7353 /* Indirect calls should go through call_indirect */
7354 if (GET_CODE (operands[0]) == REG)
7357 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
7358 output_asm_insn (\"crxor 6,6,6\", operands);
7360 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
7361 output_asm_insn (\"creqv 6,6,6\", operands);
7365 [(set_attr "type" "branch")
7366 (set_attr "length" "4,8")])
7369 [(set (match_operand 0 "" "=fg,fg")
7370 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
7371 (match_operand 2 "" "g,g")))
7372 (use (match_operand:SI 3 "immediate_operand" "O,n"))
7373 (clobber (match_scratch:SI 4 "=l,l"))]
7374 "(INTVAL (operands[3]) & CALL_LONG) == 0"
7377 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
7378 output_asm_insn (\"crxor 6,6,6\", operands);
7380 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
7381 output_asm_insn (\"creqv 6,6,6\", operands);
7385 [(set_attr "type" "branch")
7386 (set_attr "length" "4,8")])
7389 [(set (match_operand 0 "" "=fg,fg")
7390 (call (mem:SI (match_operand:SI 1 "call_operand" "s,s"))
7391 (match_operand 2 "" "fg,fg")))
7392 (use (match_operand:SI 3 "immediate_operand" "O,n"))
7393 (clobber (match_scratch:SI 4 "=l,l"))]
7394 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
7395 && (INTVAL (operands[3]) & CALL_LONG) == 0"
7398 /* This should be handled by call_value_indirect */
7399 if (GET_CODE (operands[1]) == REG)
7402 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
7403 output_asm_insn (\"crxor 6,6,6\", operands);
7405 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
7406 output_asm_insn (\"creqv 6,6,6\", operands);
7408 return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\";
7410 [(set_attr "type" "branch")
7411 (set_attr "length" "8,12")])
7414 [(set (match_operand 0 "" "=fg,fg")
7415 (call (mem:SI (match_operand:SI 1 "call_operand" "s,s"))
7416 (match_operand 2 "" "fg,fg")))
7417 (use (match_operand:SI 3 "immediate_operand" "O,n"))
7418 (clobber (match_scratch:SI 4 "=l,l"))]
7419 "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
7420 && (INTVAL (operands[3]) & CALL_LONG) == 0"
7423 /* This should be handled by call_value_indirect */
7424 if (GET_CODE (operands[1]) == REG)
7427 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
7428 output_asm_insn (\"crxor 6,6,6\", operands);
7430 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
7431 output_asm_insn (\"creqv 6,6,6\", operands);
7435 [(set_attr "type" "branch")
7436 (set_attr "length" "4,8")])
7438 ;; Call subroutine returning any type.
7439 (define_expand "untyped_call"
7440 [(parallel [(call (match_operand 0 "" "")
7442 (match_operand 1 "" "")
7443 (match_operand 2 "" "")])]
7449 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx, const0_rtx));
7451 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7453 rtx set = XVECEXP (operands[2], 0, i);
7454 emit_move_insn (SET_DEST (set), SET_SRC (set));
7457 /* The optimizer does not know that the call sets the function value
7458 registers we stored in the result block. We avoid problems by
7459 claiming that all hard registers are used and clobbered at this
7461 emit_insn (gen_blockage ());
7466 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7467 ;; all of memory. This blocks insns from being moved across this point.
7469 (define_insn "blockage"
7470 [(unspec_volatile [(const_int 0)] 0)]
7474 ;; Synchronize instructions/data caches for V.4 trampolines
7475 ;; The extra memory_operand is to prevent the optimizer from
7476 ;; deleting insns with "no" effect.
7478 [(unspec [(match_operand 0 "memory_operand" "=m")
7479 (match_operand 1 "register_operand" "b")
7480 (match_operand 2 "register_operand" "r")] 3)]
7484 (define_insn "dcbst"
7485 [(unspec [(match_operand 0 "memory_operand" "=m")
7486 (match_operand 1 "register_operand" "b")
7487 (match_operand 2 "register_operand" "r")] 4)]
7492 [(unspec [(match_operand 0 "memory_operand" "=m")] 5)]
7496 (define_insn "isync"
7497 [(unspec [(match_operand 0 "memory_operand" "=m")] 6)]
7502 ;; V.4 specific code to initialize the PIC register
7504 (define_insn "init_v4_pic"
7505 [(set (match_operand:SI 0 "register_operand" "=l")
7506 (unspec [(const_int 0)] 7))]
7507 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS"
7508 "bl _GLOBAL_OFFSET_TABLE_-4"
7509 [(set_attr "type" "branch")])
7512 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
7513 ;; signed & unsigned, and one type of branch.
7515 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
7516 ;; insns, and branches. We store the operands of compares until we see
7518 (define_expand "cmpsi"
7520 (compare (match_operand:SI 0 "gpc_reg_operand" "")
7521 (match_operand:SI 1 "reg_or_short_operand" "")))]
7525 /* Take care of the possibility that operands[1] might be negative but
7526 this might be a logical operation. That insn doesn't exist. */
7527 if (GET_CODE (operands[1]) == CONST_INT
7528 && INTVAL (operands[1]) < 0)
7529 operands[1] = force_reg (SImode, operands[1]);
7531 rs6000_compare_op0 = operands[0];
7532 rs6000_compare_op1 = operands[1];
7533 rs6000_compare_fp_p = 0;
7537 (define_expand "cmpdi"
7539 (compare (match_operand:DI 0 "gpc_reg_operand" "")
7540 (match_operand:DI 1 "reg_or_short_operand" "")))]
7544 /* Take care of the possibility that operands[1] might be negative but
7545 this might be a logical operation. That insn doesn't exist. */
7546 if (GET_CODE (operands[1]) == CONST_INT
7547 && INTVAL (operands[1]) < 0)
7548 operands[1] = force_reg (DImode, operands[1]);
7550 rs6000_compare_op0 = operands[0];
7551 rs6000_compare_op1 = operands[1];
7552 rs6000_compare_fp_p = 0;
7556 (define_expand "cmpsf"
7557 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
7558 (match_operand:SF 1 "gpc_reg_operand" "")))]
7562 rs6000_compare_op0 = operands[0];
7563 rs6000_compare_op1 = operands[1];
7564 rs6000_compare_fp_p = 1;
7568 (define_expand "cmpdf"
7569 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
7570 (match_operand:DF 1 "gpc_reg_operand" "")))]
7574 rs6000_compare_op0 = operands[0];
7575 rs6000_compare_op1 = operands[1];
7576 rs6000_compare_fp_p = 1;
7580 (define_expand "beq"
7581 [(set (match_dup 2) (match_dup 1))
7583 (if_then_else (eq (match_dup 2)
7585 (label_ref (match_operand 0 "" ""))
7589 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7590 operands[1] = gen_rtx (COMPARE, mode,
7591 rs6000_compare_op0, rs6000_compare_op1);
7592 operands[2] = gen_reg_rtx (mode);
7595 (define_expand "bne"
7596 [(set (match_dup 2) (match_dup 1))
7598 (if_then_else (ne (match_dup 2)
7600 (label_ref (match_operand 0 "" ""))
7604 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7605 operands[1] = gen_rtx (COMPARE, mode,
7606 rs6000_compare_op0, rs6000_compare_op1);
7607 operands[2] = gen_reg_rtx (mode);
7610 (define_expand "blt"
7611 [(set (match_dup 2) (match_dup 1))
7613 (if_then_else (lt (match_dup 2)
7615 (label_ref (match_operand 0 "" ""))
7619 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7620 operands[1] = gen_rtx (COMPARE, mode,
7621 rs6000_compare_op0, rs6000_compare_op1);
7622 operands[2] = gen_reg_rtx (mode);
7625 (define_expand "bgt"
7626 [(set (match_dup 2) (match_dup 1))
7628 (if_then_else (gt (match_dup 2)
7630 (label_ref (match_operand 0 "" ""))
7634 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7635 operands[1] = gen_rtx (COMPARE, mode,
7636 rs6000_compare_op0, rs6000_compare_op1);
7637 operands[2] = gen_reg_rtx (mode);
7640 (define_expand "ble"
7641 [(set (match_dup 2) (match_dup 1))
7643 (if_then_else (le (match_dup 2)
7645 (label_ref (match_operand 0 "" ""))
7649 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7650 operands[1] = gen_rtx (COMPARE, mode,
7651 rs6000_compare_op0, rs6000_compare_op1);
7652 operands[2] = gen_reg_rtx (mode);
7655 (define_expand "bge"
7656 [(set (match_dup 2) (match_dup 1))
7658 (if_then_else (ge (match_dup 2)
7660 (label_ref (match_operand 0 "" ""))
7664 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7665 operands[1] = gen_rtx (COMPARE, mode,
7666 rs6000_compare_op0, rs6000_compare_op1);
7667 operands[2] = gen_reg_rtx (mode);
7670 (define_expand "bgtu"
7671 [(set (match_dup 2) (match_dup 1))
7673 (if_then_else (gtu (match_dup 2)
7675 (label_ref (match_operand 0 "" ""))
7679 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7680 rs6000_compare_op0, rs6000_compare_op1);
7681 operands[2] = gen_reg_rtx (CCUNSmode);
7684 (define_expand "bltu"
7685 [(set (match_dup 2) (match_dup 1))
7687 (if_then_else (ltu (match_dup 2)
7689 (label_ref (match_operand 0 "" ""))
7693 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7694 rs6000_compare_op0, rs6000_compare_op1);
7695 operands[2] = gen_reg_rtx (CCUNSmode);
7698 (define_expand "bgeu"
7699 [(set (match_dup 2) (match_dup 1))
7701 (if_then_else (geu (match_dup 2)
7703 (label_ref (match_operand 0 "" ""))
7707 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7708 rs6000_compare_op0, rs6000_compare_op1);
7709 operands[2] = gen_reg_rtx (CCUNSmode);
7712 (define_expand "bleu"
7713 [(set (match_dup 2) (match_dup 1))
7715 (if_then_else (leu (match_dup 2)
7717 (label_ref (match_operand 0 "" ""))
7721 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7722 rs6000_compare_op0, rs6000_compare_op1);
7723 operands[2] = gen_reg_rtx (CCUNSmode);
7726 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
7727 ;; For SEQ, likewise, except that comparisons with zero should be done
7728 ;; with an scc insns. However, due to the order that combine see the
7729 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
7730 ;; the cases we don't want to handle.
7731 (define_expand "seq"
7732 [(set (match_dup 2) (match_dup 1))
7733 (set (match_operand:SI 0 "gpc_reg_operand" "")
7734 (eq:SI (match_dup 2) (const_int 0)))]
7737 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7738 operands[1] = gen_rtx (COMPARE, mode,
7739 rs6000_compare_op0, rs6000_compare_op1);
7740 operands[2] = gen_reg_rtx (mode);
7743 (define_expand "sne"
7744 [(set (match_dup 2) (match_dup 1))
7745 (set (match_operand:SI 0 "gpc_reg_operand" "")
7746 (ne:SI (match_dup 2) (const_int 0)))]
7749 { if (! rs6000_compare_fp_p)
7752 operands[1] = gen_rtx (COMPARE, CCFPmode,
7753 rs6000_compare_op0, rs6000_compare_op1);
7754 operands[2] = gen_reg_rtx (CCFPmode);
7757 ;; A > 0 is best done using the portable sequence, so fail in that case.
7758 (define_expand "sgt"
7759 [(set (match_dup 2) (match_dup 1))
7760 (set (match_operand:SI 0 "gpc_reg_operand" "")
7761 (gt:SI (match_dup 2) (const_int 0)))]
7764 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7766 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
7769 operands[1] = gen_rtx (COMPARE, mode,
7770 rs6000_compare_op0, rs6000_compare_op1);
7771 operands[2] = gen_reg_rtx (mode);
7774 ;; A < 0 is best done in the portable way for A an integer.
7775 (define_expand "slt"
7776 [(set (match_dup 2) (match_dup 1))
7777 (set (match_operand:SI 0 "gpc_reg_operand" "")
7778 (lt:SI (match_dup 2) (const_int 0)))]
7781 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7783 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
7786 operands[1] = gen_rtx (COMPARE, mode,
7787 rs6000_compare_op0, rs6000_compare_op1);
7788 operands[2] = gen_reg_rtx (mode);
7791 (define_expand "sge"
7792 [(set (match_dup 2) (match_dup 1))
7793 (set (match_operand:SI 0 "gpc_reg_operand" "")
7794 (ge:SI (match_dup 2) (const_int 0)))]
7797 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7798 operands[1] = gen_rtx (COMPARE, mode,
7799 rs6000_compare_op0, rs6000_compare_op1);
7800 operands[2] = gen_reg_rtx (mode);
7803 ;; A <= 0 is best done the portable way for A an integer.
7804 (define_expand "sle"
7805 [(set (match_dup 2) (match_dup 1))
7806 (set (match_operand:SI 0 "gpc_reg_operand" "")
7807 (le:SI (match_dup 2) (const_int 0)))]
7810 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7812 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
7815 operands[1] = gen_rtx (COMPARE, mode,
7816 rs6000_compare_op0, rs6000_compare_op1);
7817 operands[2] = gen_reg_rtx (mode);
7820 (define_expand "sgtu"
7821 [(set (match_dup 2) (match_dup 1))
7822 (set (match_operand:SI 0 "gpc_reg_operand" "")
7823 (gtu:SI (match_dup 2) (const_int 0)))]
7826 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7827 rs6000_compare_op0, rs6000_compare_op1);
7828 operands[2] = gen_reg_rtx (CCUNSmode);
7831 (define_expand "sltu"
7832 [(set (match_dup 2) (match_dup 1))
7833 (set (match_operand:SI 0 "gpc_reg_operand" "")
7834 (ltu:SI (match_dup 2) (const_int 0)))]
7837 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7838 rs6000_compare_op0, rs6000_compare_op1);
7839 operands[2] = gen_reg_rtx (CCUNSmode);
7842 (define_expand "sgeu"
7843 [(set (match_dup 2) (match_dup 1))
7844 (set (match_operand:SI 0 "gpc_reg_operand" "")
7845 (geu:SI (match_dup 2) (const_int 0)))]
7848 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7849 rs6000_compare_op0, rs6000_compare_op1);
7850 operands[2] = gen_reg_rtx (CCUNSmode);
7853 (define_expand "sleu"
7854 [(set (match_dup 2) (match_dup 1))
7855 (set (match_operand:SI 0 "gpc_reg_operand" "")
7856 (leu:SI (match_dup 2) (const_int 0)))]
7859 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7860 rs6000_compare_op0, rs6000_compare_op1);
7861 operands[2] = gen_reg_rtx (CCUNSmode);
7864 ;; Here are the actual compare insns.
7866 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
7867 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
7868 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
7870 "{cmp%I2|cmpw%I2} %0,%1,%2"
7871 [(set_attr "type" "compare")])
7874 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
7875 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
7876 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
7879 [(set_attr "type" "compare")])
7881 ;; If we are comparing a register for equality with a large constant,
7882 ;; we can do this with an XOR followed by a compare. But we need a scratch
7883 ;; register for the result of the XOR.
7886 [(set (match_operand:CC 0 "cc_reg_operand" "")
7887 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7888 (match_operand:SI 2 "non_short_cint_operand" "")))
7889 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
7890 "find_single_use (operands[0], insn, 0)
7891 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
7892 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
7893 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
7894 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
7897 /* Get the constant we are comparing against, C, and see what it looks like
7898 sign-extended to 16 bits. Then see what constant could be XOR'ed
7899 with C to get the sign-extended value. */
7901 int c = INTVAL (operands[2]);
7902 int sextc = (c << 16) >> 16;
7903 int xorv = c ^ sextc;
7905 operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv);
7906 operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc);
7910 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
7911 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
7912 (match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
7914 "{cmpl%I2|cmplw%I2} %0,%1,%W2"
7915 [(set_attr "type" "compare")])
7918 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
7919 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
7920 (match_operand:DI 2 "reg_or_u_short_operand" "rI")))]
7922 "cmpld%I2 %0,%1,%W2"
7923 [(set_attr "type" "compare")])
7925 ;; The following two insns don't exist as single insns, but if we provide
7926 ;; them, we can swap an add and compare, which will enable us to overlap more
7927 ;; of the required delay between a compare and branch. We generate code for
7928 ;; them by splitting.
7931 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
7932 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
7933 (match_operand:SI 2 "short_cint_operand" "i")))
7934 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
7935 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
7938 [(set_attr "length" "8")])
7941 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
7942 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
7943 (match_operand:SI 2 "u_short_cint_operand" "i")))
7944 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
7945 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
7948 [(set_attr "length" "8")])
7951 [(set (match_operand:CC 3 "cc_reg_operand" "")
7952 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7953 (match_operand:SI 2 "short_cint_operand" "")))
7954 (set (match_operand:SI 0 "gpc_reg_operand" "")
7955 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
7957 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
7958 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
7961 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
7962 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
7963 (match_operand:SI 2 "u_short_cint_operand" "")))
7964 (set (match_operand:SI 0 "gpc_reg_operand" "")
7965 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
7967 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
7968 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
7971 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
7972 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
7973 (match_operand:SF 2 "gpc_reg_operand" "f")))]
7976 [(set_attr "type" "fpcompare")])
7979 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
7980 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
7981 (match_operand:DF 2 "gpc_reg_operand" "f")))]
7984 [(set_attr "type" "fpcompare")])
7986 ;; Now we have the scc insns. We can do some combinations because of the
7987 ;; way the machine works.
7989 ;; Note that this is probably faster if we can put an insn between the
7990 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
7991 ;; cases the insns below which don't use an intermediate CR field will
7994 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7995 (match_operator:SI 1 "scc_comparison_operator"
7996 [(match_operand 2 "cc_reg_operand" "y")
7999 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
8000 [(set_attr "length" "12")])
8003 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8004 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
8005 [(match_operand 2 "cc_reg_operand" "y")
8008 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
8009 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
8011 "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1"
8012 [(set_attr "type" "delayed_compare")
8013 (set_attr "length" "12")])
8016 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8017 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
8018 [(match_operand 2 "cc_reg_operand" "y")
8020 (match_operand:SI 3 "const_int_operand" "n")))]
8024 int is_bit = ccr_bit (operands[1], 1);
8025 int put_bit = 31 - (INTVAL (operands[3]) & 31);
8028 if (is_bit >= put_bit)
8029 count = is_bit - put_bit;
8031 count = 32 - (put_bit - is_bit);
8033 operands[4] = gen_rtx (CONST_INT, VOIDmode, count);
8034 operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
8036 return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
8038 [(set_attr "length" "12")])
8041 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8043 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
8044 [(match_operand 2 "cc_reg_operand" "y")
8046 (match_operand:SI 3 "const_int_operand" "n"))
8048 (set (match_operand:SI 4 "gpc_reg_operand" "=r")
8049 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
8054 int is_bit = ccr_bit (operands[1], 1);
8055 int put_bit = 31 - (INTVAL (operands[3]) & 31);
8058 if (is_bit >= put_bit)
8059 count = is_bit - put_bit;
8061 count = 32 - (put_bit - is_bit);
8063 operands[5] = gen_rtx (CONST_INT, VOIDmode, count);
8064 operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit);
8066 return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
8068 [(set_attr "type" "delayed_compare")
8069 (set_attr "length" "12")])
8071 ;; If we are comparing the result of two comparisons, this can be done
8072 ;; using creqv or crxor.
8075 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
8076 (compare:CCEQ (match_operator 1 "scc_comparison_operator"
8077 [(match_operand 2 "cc_reg_operand" "y")
8079 (match_operator 3 "scc_comparison_operator"
8080 [(match_operand 4 "cc_reg_operand" "y")
8082 "REGNO (operands[2]) != REGNO (operands[4])"
8085 enum rtx_code code1, code2;
8087 code1 = GET_CODE (operands[1]);
8088 code2 = GET_CODE (operands[3]);
8090 if ((code1 == EQ || code1 == LT || code1 == GT
8091 || code1 == LTU || code1 == GTU
8092 || (code1 != NE && GET_MODE (operands[2]) == CCFPmode))
8094 (code2 == EQ || code2 == LT || code2 == GT
8095 || code2 == LTU || code2 == GTU
8096 || (code2 != NE && GET_MODE (operands[4]) == CCFPmode)))
8097 return \"%C1%C3crxor %E0,%j1,%j3\";
8099 return \"%C1%C3creqv %E0,%j1,%j3\";
8101 [(set_attr "length" "12")])
8103 ;; There is a 3 cycle delay between consecutive mfcr instructions
8104 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
8107 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8108 (match_operator:SI 1 "scc_comparison_operator"
8109 [(match_operand 2 "cc_reg_operand" "y")
8111 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
8112 (match_operator:SI 4 "scc_comparison_operator"
8113 [(match_operand 5 "cc_reg_operand" "y")
8115 "REGNO (operands[2]) != REGNO (operands[5])"
8116 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
8117 [(set_attr "length" "20")])
8119 ;; There are some scc insns that can be done directly, without a compare.
8120 ;; These are faster because they don't involve the communications between
8121 ;; the FXU and branch units. In fact, we will be replacing all of the
8122 ;; integer scc insns here or in the portable methods in emit_store_flag.
8124 ;; Also support (neg (scc ..)) since that construct is used to replace
8125 ;; branches, (plus (scc ..) ..) since that construct is common and
8126 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
8127 ;; cases where it is no more expensive than (neg (scc ..)).
8129 ;; Have reload force a constant into a register for the simple insns that
8130 ;; otherwise won't accept constants. We do this because it is faster than
8131 ;; the cmp/mfcr sequence we would otherwise generate.
8134 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
8135 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
8136 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
8137 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
8140 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
8141 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
8142 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
8143 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
8144 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
8145 [(set_attr "length" "12,8,12,12,12")])
8148 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
8150 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
8151 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
8153 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
8154 (eq:SI (match_dup 1) (match_dup 2)))
8155 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
8158 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
8159 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
8160 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
8161 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
8162 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0"
8163 [(set_attr "type" "compare")
8164 (set_attr "length" "12,8,12,12,12")])
8166 ;; We have insns of the form shown by the first define_insn below. If
8167 ;; there is something inside the comparison operation, we must split it.
8169 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8170 (plus:SI (match_operator 1 "comparison_operator"
8171 [(match_operand:SI 2 "" "")
8173 "reg_or_cint_operand" "")])
8174 (match_operand:SI 4 "gpc_reg_operand" "")))
8175 (clobber (match_operand:SI 5 "register_operand" ""))]
8176 "! gpc_reg_operand (operands[2], SImode)"
8177 [(set (match_dup 5) (match_dup 2))
8178 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
8182 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
8183 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
8184 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
8185 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
8186 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
8189 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
8190 {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3
8191 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
8192 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
8193 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
8194 [(set_attr "length" "12,8,12,12,12")])
8197 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
8200 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
8201 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
8202 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
8204 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
8207 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
8208 {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3
8209 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
8210 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
8211 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
8212 [(set_attr "type" "compare")
8213 (set_attr "length" "12,8,12,12,12")])
8216 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
8219 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
8220 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
8221 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
8223 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
8224 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8225 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
8228 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
8229 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
8230 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
8231 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
8232 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
8233 [(set_attr "type" "compare")
8234 (set_attr "length" "12,8,12,12,12")])
8237 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
8238 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
8239 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
8242 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
8243 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
8244 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
8245 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
8246 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
8247 [(set_attr "length" "12,8,12,12,12")])
8249 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
8250 ;; since it nabs/sr is just as fast.
8252 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8253 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
8255 (clobber (match_scratch:SI 2 "=&r"))]
8257 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
8258 [(set_attr "length" "8")])
8260 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
8262 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8263 (plus:SI (lshiftrt:SI
8264 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
8266 (match_operand:SI 2 "gpc_reg_operand" "r")))
8267 (clobber (match_scratch:SI 3 "=&r"))]
8269 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
8270 [(set_attr "length" "8")])
8273 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8275 (plus:SI (lshiftrt:SI
8276 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
8278 (match_operand:SI 2 "gpc_reg_operand" "r"))
8280 (clobber (match_scratch:SI 3 "=&r"))]
8282 "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2"
8283 [(set_attr "type" "compare")
8284 (set_attr "length" "8")])
8287 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
8289 (plus:SI (lshiftrt:SI
8290 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
8292 (match_operand:SI 2 "gpc_reg_operand" "r"))
8294 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8295 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
8297 (clobber (match_scratch:SI 3 "=&r"))]
8299 "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2"
8300 [(set_attr "type" "compare")
8301 (set_attr "length" "8")])
8304 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8305 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8306 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
8307 (clobber (match_scratch:SI 3 "=r,X"))]
8310 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
8311 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
8312 [(set_attr "length" "12")])
8315 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x")
8317 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8318 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
8320 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8321 (le:SI (match_dup 1) (match_dup 2)))
8322 (clobber (match_scratch:SI 3 "=r,X"))]
8325 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
8326 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31"
8327 [(set_attr "type" "compare,delayed_compare")
8328 (set_attr "length" "12")])
8331 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8332 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8333 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
8334 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
8335 (clobber (match_scratch:SI 4 "=&r,&r"))]
8338 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
8339 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3"
8340 [(set_attr "length" "12")])
8343 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
8345 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8346 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
8347 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8349 (clobber (match_scratch:SI 4 "=&r,&r"))]
8352 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
8353 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3"
8354 [(set_attr "type" "compare")
8355 (set_attr "length" "12")])
8358 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
8360 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8361 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
8362 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8364 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8365 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8366 (clobber (match_scratch:SI 4 "=&r,&r"))]
8369 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
8370 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3"
8371 [(set_attr "type" "compare")
8372 (set_attr "length" "12")])
8375 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8376 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8377 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
8380 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
8381 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
8382 [(set_attr "length" "12")])
8385 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8386 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8387 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
8389 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
8390 [(set_attr "length" "12")])
8393 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
8395 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8396 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8398 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8399 (leu:SI (match_dup 1) (match_dup 2)))]
8401 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
8402 [(set_attr "type" "compare")
8403 (set_attr "length" "12")])
8406 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8407 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8408 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8409 (match_operand:SI 3 "gpc_reg_operand" "r")))
8410 (clobber (match_scratch:SI 4 "=&r"))]
8412 "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3"
8413 [(set_attr "length" "8")])
8416 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8418 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8419 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8420 (match_operand:SI 3 "gpc_reg_operand" "r"))
8422 (clobber (match_scratch:SI 4 "=&r"))]
8424 "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3"
8425 [(set_attr "type" "compare")
8426 (set_attr "length" "8")])
8429 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
8431 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8432 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8433 (match_operand:SI 3 "gpc_reg_operand" "r"))
8435 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8436 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8437 (clobber (match_scratch:SI 4 "=&r"))]
8439 "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3"
8440 [(set_attr "type" "compare")
8441 (set_attr "length" "8")])
8444 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8445 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8446 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
8448 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
8449 [(set_attr "length" "12")])
8452 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8454 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8455 (match_operand:SI 2 "reg_or_short_operand" "rI")))
8456 (match_operand:SI 3 "gpc_reg_operand" "r")))
8457 (clobber (match_scratch:SI 4 "=&r"))]
8459 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
8460 [(set_attr "length" "12")])
8463 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8466 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8467 (match_operand:SI 2 "reg_or_short_operand" "rI")))
8468 (match_operand:SI 3 "gpc_reg_operand" "r"))
8470 (clobber (match_scratch:SI 4 "=&r"))]
8472 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
8473 [(set_attr "type" "compare")
8474 (set_attr "length" "12")])
8477 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
8480 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8481 (match_operand:SI 2 "reg_or_short_operand" "rI")))
8482 (match_operand:SI 3 "gpc_reg_operand" "r"))
8484 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8485 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
8486 (clobber (match_scratch:SI 4 "=&r"))]
8488 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
8489 [(set_attr "type" "compare")
8490 (set_attr "length" "12")])
8493 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8494 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8495 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
8497 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
8498 [(set_attr "length" "12")])
8501 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
8503 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8504 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8506 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8507 (lt:SI (match_dup 1) (match_dup 2)))]
8509 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31"
8510 [(set_attr "type" "delayed_compare")
8511 (set_attr "length" "12")])
8514 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8515 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8516 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8517 (match_operand:SI 3 "gpc_reg_operand" "r")))
8518 (clobber (match_scratch:SI 4 "=&r"))]
8520 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
8521 [(set_attr "length" "12")])
8524 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8526 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8527 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8528 (match_operand:SI 3 "gpc_reg_operand" "r"))
8530 (clobber (match_scratch:SI 4 "=&r"))]
8532 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3"
8533 [(set_attr "type" "compare")
8534 (set_attr "length" "12")])
8537 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
8539 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8540 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8541 (match_operand:SI 3 "gpc_reg_operand" "r"))
8543 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8544 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8545 (clobber (match_scratch:SI 4 "=&r"))]
8547 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3"
8548 [(set_attr "type" "compare")
8549 (set_attr "length" "12")])
8552 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8553 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8554 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
8556 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
8557 [(set_attr "length" "12")])
8560 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8561 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8562 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
8565 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
8566 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
8567 [(set_attr "length" "12")])
8570 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
8572 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8573 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
8575 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8576 (ltu:SI (match_dup 1) (match_dup 2)))]
8579 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
8580 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
8581 [(set_attr "type" "compare")
8582 (set_attr "length" "12")])
8585 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
8586 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
8587 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
8588 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
8589 (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
8592 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
8593 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
8594 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
8595 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
8596 [(set_attr "length" "12")])
8599 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
8601 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8602 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
8603 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8605 (clobber (match_scratch:SI 4 "=&r,&r"))]
8608 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
8609 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3"
8610 [(set_attr "type" "compare")
8611 (set_attr "length" "12")])
8614 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
8616 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8617 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
8618 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8620 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8621 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8622 (clobber (match_scratch:SI 4 "=&r,&r"))]
8625 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
8626 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
8627 [(set_attr "type" "compare")
8628 (set_attr "length" "12")])
8631 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8632 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8633 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
8636 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
8637 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
8638 [(set_attr "length" "8")])
8641 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8642 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8643 (match_operand:SI 2 "reg_or_short_operand" "rI")))
8644 (clobber (match_scratch:SI 3 "=r"))]
8646 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
8647 [(set_attr "length" "12")])
8650 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
8652 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8653 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8655 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8656 (ge:SI (match_dup 1) (match_dup 2)))
8657 (clobber (match_scratch:SI 3 "=r"))]
8659 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3"
8660 [(set_attr "type" "compare")
8661 (set_attr "length" "12")])
8664 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8665 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8666 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8667 (match_operand:SI 3 "gpc_reg_operand" "r")))
8668 (clobber (match_scratch:SI 4 "=&r"))]
8670 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
8671 [(set_attr "length" "12")])
8674 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8676 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8677 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8678 (match_operand:SI 3 "gpc_reg_operand" "r"))
8680 (clobber (match_scratch:SI 4 "=&r"))]
8682 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
8683 [(set_attr "type" "compare")
8684 (set_attr "length" "12")])
8687 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
8689 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8690 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8691 (match_operand:SI 3 "gpc_reg_operand" "r"))
8693 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8694 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8695 (clobber (match_scratch:SI 4 "=&r"))]
8697 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
8698 [(set_attr "type" "compare")
8699 (set_attr "length" "12")])
8702 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8703 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8704 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
8706 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
8707 [(set_attr "length" "12")])
8709 ;; This is (and (neg (ge X (const_int 0))) Y).
8711 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8714 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
8716 (match_operand:SI 2 "gpc_reg_operand" "r")))
8717 (clobber (match_scratch:SI 3 "=&r"))]
8719 "{srai|srawi} %3,%1,31\;andc %0,%2,%3"
8720 [(set_attr "length" "8")])
8723 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8727 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
8729 (match_operand:SI 2 "gpc_reg_operand" "r"))
8731 (clobber (match_scratch:SI 3 "=&r"))]
8733 "{srai|srawi} %3,%1,31\;andc. %3,%2,%3"
8734 [(set_attr "type" "compare")
8735 (set_attr "length" "8")])
8738 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
8742 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
8744 (match_operand:SI 2 "gpc_reg_operand" "r"))
8746 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8747 (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
8750 (clobber (match_scratch:SI 3 "=&r"))]
8752 "{srai|srawi} %3,%1,31\;andc. %0,%2,%3"
8753 [(set_attr "type" "compare")
8754 (set_attr "length" "8")])
8757 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8758 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8759 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
8762 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
8763 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
8764 [(set_attr "length" "12")])
8767 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
8769 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8770 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
8772 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8773 (geu:SI (match_dup 1) (match_dup 2)))]
8776 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
8777 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
8778 [(set_attr "type" "compare")
8779 (set_attr "length" "12")])
8782 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8783 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8784 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
8785 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
8786 (clobber (match_scratch:SI 4 "=&r,&r"))]
8789 {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3
8790 {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3"
8791 [(set_attr "length" "8")])
8794 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
8796 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8797 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
8798 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8800 (clobber (match_scratch:SI 4 "=&r,&r"))]
8803 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
8804 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
8805 [(set_attr "type" "compare")
8806 (set_attr "length" "8")])
8809 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
8811 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8812 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
8813 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8815 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8816 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8817 (clobber (match_scratch:SI 4 "=&r,&r"))]
8820 {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
8821 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
8822 [(set_attr "type" "compare")
8823 (set_attr "length" "8")])
8826 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8827 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8828 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
8831 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
8832 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
8833 [(set_attr "length" "12")])
8836 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8838 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8839 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
8840 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
8841 (clobber (match_scratch:SI 4 "=&r,&r"))]
8844 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4
8845 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
8846 [(set_attr "length" "12")])
8849 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
8852 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8853 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
8854 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8856 (clobber (match_scratch:SI 4 "=&r,&r"))]
8859 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
8860 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
8861 [(set_attr "type" "compare")
8862 (set_attr "length" "12")])
8865 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
8868 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8869 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
8870 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8872 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8873 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
8874 (clobber (match_scratch:SI 4 "=&r,&r"))]
8877 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
8878 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
8879 [(set_attr "type" "compare")
8880 (set_attr "length" "12")])
8883 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8884 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8887 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
8888 [(set_attr "length" "12")])
8891 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
8893 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8896 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8897 (gt:SI (match_dup 1) (const_int 0)))]
8899 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31"
8900 [(set_attr "type" "delayed_compare")
8901 (set_attr "length" "12")])
8904 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8905 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8906 (match_operand:SI 2 "reg_or_short_operand" "r")))]
8908 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
8909 [(set_attr "length" "12")])
8912 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
8914 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8915 (match_operand:SI 2 "reg_or_short_operand" "r"))
8917 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8918 (gt:SI (match_dup 1) (match_dup 2)))]
8920 "doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31"
8921 [(set_attr "type" "delayed_compare")
8922 (set_attr "length" "12")])
8925 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8926 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8928 (match_operand:SI 2 "gpc_reg_operand" "r")))
8929 (clobber (match_scratch:SI 3 "=&r"))]
8931 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2"
8932 [(set_attr "length" "12")])
8935 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8937 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8939 (match_operand:SI 2 "gpc_reg_operand" "r"))
8941 (clobber (match_scratch:SI 3 "=&r"))]
8943 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2"
8944 [(set_attr "type" "compare")
8945 (set_attr "length" "12")])
8948 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
8950 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8952 (match_operand:SI 2 "gpc_reg_operand" "r"))
8954 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8955 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
8956 (clobber (match_scratch:SI 3 "=&r"))]
8958 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2"
8959 [(set_attr "type" "compare")
8960 (set_attr "length" "12")])
8963 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8964 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8965 (match_operand:SI 2 "reg_or_short_operand" "r"))
8966 (match_operand:SI 3 "gpc_reg_operand" "r")))
8967 (clobber (match_scratch:SI 4 "=&r"))]
8969 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
8970 [(set_attr "length" "12")])
8973 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8975 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8976 (match_operand:SI 2 "reg_or_short_operand" "r"))
8977 (match_operand:SI 3 "gpc_reg_operand" "r"))
8979 (clobber (match_scratch:SI 4 "=&r"))]
8981 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3"
8982 [(set_attr "type" "compare")
8983 (set_attr "length" "12")])
8986 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
8988 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8989 (match_operand:SI 2 "reg_or_short_operand" "r"))
8990 (match_operand:SI 3 "gpc_reg_operand" "r"))
8992 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8993 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8994 (clobber (match_scratch:SI 4 "=&r"))]
8996 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3"
8997 [(set_attr "type" "compare")
8998 (set_attr "length" "12")])
9001 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9002 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9005 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
9006 [(set_attr "length" "12")])
9009 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9010 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9011 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
9013 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
9014 [(set_attr "length" "12")])
9017 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9018 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9019 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
9021 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
9022 [(set_attr "length" "12")])
9025 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
9027 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9028 (match_operand:SI 2 "reg_or_short_operand" "rI"))
9030 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
9031 (gtu:SI (match_dup 1) (match_dup 2)))]
9033 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
9034 [(set_attr "type" "compare")
9035 (set_attr "length" "12")])
9038 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
9039 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
9040 (match_operand:SI 2 "reg_or_short_operand" "I,r,rI"))
9041 (match_operand:SI 3 "reg_or_short_operand" "r,r,I")))
9042 (clobber (match_scratch:SI 4 "=&r,&r,&r"))]
9045 {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
9046 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
9047 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
9048 [(set_attr "length" "8,12,12")])
9051 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
9053 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9054 (match_operand:SI 2 "reg_or_short_operand" "I,r"))
9055 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9057 (clobber (match_scratch:SI 4 "=&r,&r"))]
9060 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
9061 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
9062 [(set_attr "type" "compare")
9063 (set_attr "length" "8,12")])
9066 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
9068 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
9069 (match_operand:SI 2 "reg_or_short_operand" "I,r"))
9070 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9072 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9073 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9074 (clobber (match_scratch:SI 4 "=&r,&r"))]
9077 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
9078 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
9079 [(set_attr "type" "compare")
9080 (set_attr "length" "8,12")])
9083 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9084 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9085 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
9087 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
9088 [(set_attr "length" "8")])
9090 ;; Define both directions of branch and return. If we need a reload
9091 ;; register, we'd rather use CR0 since it is much easier to copy a
9092 ;; register CC value to there.
9096 (if_then_else (match_operator 1 "branch_comparison_operator"
9098 "cc_reg_operand" "x,?y")
9100 (label_ref (match_operand 0 "" ""))
9105 if (get_attr_length (insn) == 8)
9106 return \"%C1bc %t1,%j1,%l0\";
9108 return \"%C1bc %T1,%j1,%$+8\;b %l0\";
9111 [(set_attr "type" "branch")])
9115 (if_then_else (match_operator 0 "branch_comparison_operator"
9117 "cc_reg_operand" "x,?y")
9122 "{%C0bcr|%C0bclr} %t0,%j0"
9123 [(set_attr "type" "branch")
9124 (set_attr "length" "8")])
9128 (if_then_else (match_operator 1 "branch_comparison_operator"
9130 "cc_reg_operand" "x,?y")
9133 (label_ref (match_operand 0 "" ""))))]
9137 if (get_attr_length (insn) == 8)
9138 return \"%C1bc %T1,%j1,%l0\";
9140 return \"%C1bc %t1,%j1,%$+8\;b %l0\";
9142 [(set_attr "type" "branch")])
9146 (if_then_else (match_operator 0 "branch_comparison_operator"
9148 "cc_reg_operand" "x,?y")
9153 "{%C0bcr|%C0bclr} %T0,%j0"
9154 [(set_attr "type" "branch")
9155 (set_attr "length" "8")])
9157 ;; Unconditional branch and return.
9161 (label_ref (match_operand 0 "" "")))]
9164 [(set_attr "type" "branch")])
9166 (define_insn "return"
9170 [(set_attr "type" "jmpreg")])
9172 (define_insn "indirect_jump"
9173 [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
9178 [(set_attr "type" "jmpreg")])
9181 [(set (pc) (match_operand:DI 0 "register_operand" "c,l"))]
9186 [(set_attr "type" "jmpreg")])
9188 ;; Table jump for switch statements:
9189 (define_expand "tablejump"
9190 [(use (match_operand 0 "" ""))
9191 (use (label_ref (match_operand 1 "" "")))]
9196 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
9198 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
9202 (define_expand "tablejumpsi"
9204 (plus:SI (match_operand:SI 0 "" "")
9206 (parallel [(set (pc) (match_dup 3))
9207 (use (label_ref (match_operand 1 "" "")))])]
9210 { operands[0] = force_reg (SImode, operands[0]);
9211 operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1]));
9212 operands[3] = gen_reg_rtx (SImode);
9215 (define_expand "tablejumpdi"
9217 (plus:DI (match_operand:DI 0 "" "")
9219 (parallel [(set (pc) (match_dup 3))
9220 (use (label_ref (match_operand 1 "" "")))])]
9223 { operands[0] = force_reg (DImode, operands[0]);
9224 operands[2] = force_reg (DImode, gen_rtx (LABEL_REF, VOIDmode, operands[1]));
9225 operands[3] = gen_reg_rtx (DImode);
9230 (match_operand:SI 0 "register_operand" "c,l"))
9231 (use (label_ref (match_operand 1 "" "")))]
9236 [(set_attr "type" "jmpreg")])
9240 (match_operand:DI 0 "register_operand" "c,l"))
9241 (use (label_ref (match_operand 1 "" "")))]
9246 [(set_attr "type" "jmpreg")])
9253 ;; Define the subtract-one-and-jump insns, starting with the template
9254 ;; so loop.c knows what to generate.
9256 (define_expand "decrement_and_branch_on_count"
9257 [(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "")
9259 (label_ref (match_operand 1 "" ""))
9262 (plus:SI (match_dup 0)
9264 (clobber (match_scratch:CC 2 ""))
9265 (clobber (match_scratch:SI 3 ""))])]
9269 ;; We need to be able to do this for any operand, including MEM, or we
9270 ;; will cause reload to blow up since we don't allow output reloads on
9272 ;; In order that the length attribute is calculated correctly, the
9273 ;; label MUST be operand 0.
9277 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
9279 (label_ref (match_operand 0 "" ""))
9281 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
9282 (plus:SI (match_dup 1)
9284 (clobber (match_scratch:CC 3 "=X,&x,&x"))
9285 (clobber (match_scratch:SI 4 "=X,X,r"))]
9289 if (which_alternative != 0)
9291 else if (get_attr_length (insn) == 8)
9292 return \"{bdn|bdnz} %l0\";
9294 return \"bdz %$+8\;b %l0\";
9296 [(set_attr "type" "branch")
9297 (set_attr "length" "*,12,16")])
9301 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
9304 (label_ref (match_operand 0 "" ""))))
9305 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
9306 (plus:SI (match_dup 1)
9308 (clobber (match_scratch:CC 3 "=X,&x,&x"))
9309 (clobber (match_scratch:SI 4 "=X,X,r"))]
9313 if (which_alternative != 0)
9315 else if (get_attr_length (insn) == 8)
9318 return \"{bdn|bdnz} %$+8\;b %l0\";
9320 [(set_attr "type" "branch")
9321 (set_attr "length" "*,12,16")])
9323 ;; Similar, but we can use GE since we have a REG_NONNEG.
9326 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
9328 (label_ref (match_operand 0 "" ""))
9330 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
9331 (plus:SI (match_dup 1)
9333 (clobber (match_scratch:CC 3 "=X,&x,&X"))
9334 (clobber (match_scratch:SI 4 "=X,X,r"))]
9335 "find_reg_note (insn, REG_NONNEG, 0)"
9338 if (which_alternative != 0)
9340 else if (get_attr_length (insn) == 8)
9341 return \"{bdn|bdnz} %l0\";
9343 return \"bdz %$+8\;b %l0\";
9345 [(set_attr "type" "branch")
9346 (set_attr "length" "*,12,16")])
9350 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
9353 (label_ref (match_operand 0 "" ""))))
9354 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
9355 (plus:SI (match_dup 1)
9357 (clobber (match_scratch:CC 3 "=X,&x,&X"))
9358 (clobber (match_scratch:SI 4 "=X,X,r"))]
9359 "find_reg_note (insn, REG_NONNEG, 0)"
9362 if (which_alternative != 0)
9364 else if (get_attr_length (insn) == 8)
9367 return \"{bdn|bdnz} %$+8\;b %l0\";
9369 [(set_attr "type" "branch")
9370 (set_attr "length" "*,12,16")])
9374 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
9376 (label_ref (match_operand 0 "" ""))
9378 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
9379 (plus:SI (match_dup 1)
9381 (clobber (match_scratch:CC 3 "=X,&x,&x"))
9382 (clobber (match_scratch:SI 4 "=X,X,r"))]
9386 if (which_alternative != 0)
9388 else if (get_attr_length (insn) == 8)
9391 return \"{bdn|bdnz} %$+8\;b %l0\";
9393 [(set_attr "type" "branch")
9394 (set_attr "length" "*,12,16")])
9398 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
9401 (label_ref (match_operand 0 "" ""))))
9402 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
9403 (plus:SI (match_dup 1)
9405 (clobber (match_scratch:CC 3 "=X,&x,&x"))
9406 (clobber (match_scratch:SI 4 "=X,X,r"))]
9410 if (which_alternative != 0)
9412 else if (get_attr_length (insn) == 8)
9413 return \"{bdn|bdnz} %l0\";
9415 return \"bdz %$+8\;b %l0\";
9417 [(set_attr "type" "branch")
9418 (set_attr "length" "*,12,16")])
9422 (if_then_else (match_operator 2 "comparison_operator"
9423 [(match_operand:SI 1 "gpc_reg_operand" "")
9425 (match_operand 5 "" "")
9426 (match_operand 6 "" "")))
9427 (set (match_operand:SI 0 "gpc_reg_operand" "")
9428 (plus:SI (match_dup 1)
9430 (clobber (match_scratch:CC 3 ""))
9431 (clobber (match_scratch:SI 4 ""))]
9433 [(parallel [(set (match_dup 3)
9434 (compare:CC (plus:SI (match_dup 1)
9438 (plus:SI (match_dup 1)
9440 (set (pc) (if_then_else (match_dup 7)
9444 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
9449 (if_then_else (match_operator 2 "comparison_operator"
9450 [(match_operand:SI 1 "gpc_reg_operand" "")
9452 (match_operand 5 "" "")
9453 (match_operand 6 "" "")))
9454 (set (match_operand:SI 0 "general_operand" "")
9455 (plus:SI (match_dup 1) (const_int -1)))
9456 (clobber (match_scratch:CC 3 ""))
9457 (clobber (match_scratch:SI 4 ""))]
9458 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
9459 [(parallel [(set (match_dup 3)
9460 (compare:CC (plus:SI (match_dup 1)
9464 (plus:SI (match_dup 1)
9468 (set (pc) (if_then_else (match_dup 7)
9472 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],