1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 ;; MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
64 ;; UNSPEC_VOLATILE usage
69 (UNSPECV_EH_RR 9) ; eh_reg_restore
72 ;; Define an insn type attribute. This is used in function unit delay
74 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
75 (const_string "integer"))
78 ; '(pc)' in the following doesn't include the instruction itself; it is
79 ; calculated as if the instruction had zero size.
80 (define_attr "length" ""
81 (if_then_else (eq_attr "type" "branch")
82 (if_then_else (and (ge (minus (match_dup 0) (pc))
84 (lt (minus (match_dup 0) (pc))
90 ;; Processor type -- this attribute must exactly match the processor_type
91 ;; enumeration in rs6000.h.
93 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
94 (const (symbol_ref "rs6000_cpu_attr")))
96 (automata_option "ndfa")
109 (include "power4.md")
110 (include "power5.md")
112 (include "predicates.md")
114 (include "darwin.md")
119 ; This mode macro allows :GPR to be used to indicate the allowable size
120 ; of whole values in GPRs.
121 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
123 ; Any supported integer mode.
124 (define_mode_macro INT [QI HI SI DI TI])
126 ; Any supported integer mode that fits in one register.
127 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
129 ; SImode or DImode, even if DImode doesn't fit in GPRs.
130 (define_mode_macro SDI [SI DI])
132 ; The size of a pointer. Also, the size of the value that a record-condition
133 ; (one with a '.') will compare.
134 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
136 ; Various instructions that come in SI and DI forms.
137 (define_mode_attr larx [(SI "lwarx") (DI "ldarx")])
138 (define_mode_attr stcx [(SI "stwcx.") (DI "stdcx.")])
139 ; A generic w/d attribute, for things like cmpw/cmpd.
140 (define_mode_attr wd [(SI "w") (DI "d")])
143 ;; Start with fixed-point load and store insns. Here we put only the more
144 ;; complex forms. Basic data transfer is done later.
146 (define_expand "zero_extendqidi2"
147 [(set (match_operand:DI 0 "gpc_reg_operand" "")
148 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
153 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
154 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
159 [(set_attr "type" "load,*")])
162 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
163 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
165 (clobber (match_scratch:DI 2 "=r,r"))]
170 [(set_attr "type" "compare")
171 (set_attr "length" "4,8")])
174 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
175 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
177 (clobber (match_scratch:DI 2 ""))]
178 "TARGET_POWERPC64 && reload_completed"
180 (zero_extend:DI (match_dup 1)))
182 (compare:CC (match_dup 2)
187 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
188 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
190 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
191 (zero_extend:DI (match_dup 1)))]
196 [(set_attr "type" "compare")
197 (set_attr "length" "4,8")])
200 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
201 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
203 (set (match_operand:DI 0 "gpc_reg_operand" "")
204 (zero_extend:DI (match_dup 1)))]
205 "TARGET_POWERPC64 && reload_completed"
207 (zero_extend:DI (match_dup 1)))
209 (compare:CC (match_dup 0)
213 (define_insn "extendqidi2"
214 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
215 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
220 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
221 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
223 (clobber (match_scratch:DI 2 "=r,r"))]
228 [(set_attr "type" "compare")
229 (set_attr "length" "4,8")])
232 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
233 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
235 (clobber (match_scratch:DI 2 ""))]
236 "TARGET_POWERPC64 && reload_completed"
238 (sign_extend:DI (match_dup 1)))
240 (compare:CC (match_dup 2)
245 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
246 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
248 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
249 (sign_extend:DI (match_dup 1)))]
254 [(set_attr "type" "compare")
255 (set_attr "length" "4,8")])
258 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
259 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
261 (set (match_operand:DI 0 "gpc_reg_operand" "")
262 (sign_extend:DI (match_dup 1)))]
263 "TARGET_POWERPC64 && reload_completed"
265 (sign_extend:DI (match_dup 1)))
267 (compare:CC (match_dup 0)
271 (define_expand "zero_extendhidi2"
272 [(set (match_operand:DI 0 "gpc_reg_operand" "")
273 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
278 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
279 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
284 [(set_attr "type" "load,*")])
287 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
288 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
290 (clobber (match_scratch:DI 2 "=r,r"))]
295 [(set_attr "type" "compare")
296 (set_attr "length" "4,8")])
299 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
300 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
302 (clobber (match_scratch:DI 2 ""))]
303 "TARGET_POWERPC64 && reload_completed"
305 (zero_extend:DI (match_dup 1)))
307 (compare:CC (match_dup 2)
312 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
313 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
315 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
316 (zero_extend:DI (match_dup 1)))]
321 [(set_attr "type" "compare")
322 (set_attr "length" "4,8")])
325 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
326 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
328 (set (match_operand:DI 0 "gpc_reg_operand" "")
329 (zero_extend:DI (match_dup 1)))]
330 "TARGET_POWERPC64 && reload_completed"
332 (zero_extend:DI (match_dup 1)))
334 (compare:CC (match_dup 0)
338 (define_expand "extendhidi2"
339 [(set (match_operand:DI 0 "gpc_reg_operand" "")
340 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
345 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
346 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
351 [(set_attr "type" "load_ext,*")])
354 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
355 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
357 (clobber (match_scratch:DI 2 "=r,r"))]
362 [(set_attr "type" "compare")
363 (set_attr "length" "4,8")])
366 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
367 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
369 (clobber (match_scratch:DI 2 ""))]
370 "TARGET_POWERPC64 && reload_completed"
372 (sign_extend:DI (match_dup 1)))
374 (compare:CC (match_dup 2)
379 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
380 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
382 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
383 (sign_extend:DI (match_dup 1)))]
388 [(set_attr "type" "compare")
389 (set_attr "length" "4,8")])
392 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
393 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
395 (set (match_operand:DI 0 "gpc_reg_operand" "")
396 (sign_extend:DI (match_dup 1)))]
397 "TARGET_POWERPC64 && reload_completed"
399 (sign_extend:DI (match_dup 1)))
401 (compare:CC (match_dup 0)
405 (define_expand "zero_extendsidi2"
406 [(set (match_operand:DI 0 "gpc_reg_operand" "")
407 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
412 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
413 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
418 [(set_attr "type" "load,*")])
421 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
422 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
424 (clobber (match_scratch:DI 2 "=r,r"))]
429 [(set_attr "type" "compare")
430 (set_attr "length" "4,8")])
433 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
434 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
436 (clobber (match_scratch:DI 2 ""))]
437 "TARGET_POWERPC64 && reload_completed"
439 (zero_extend:DI (match_dup 1)))
441 (compare:CC (match_dup 2)
446 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
447 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
449 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
450 (zero_extend:DI (match_dup 1)))]
455 [(set_attr "type" "compare")
456 (set_attr "length" "4,8")])
459 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
460 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
462 (set (match_operand:DI 0 "gpc_reg_operand" "")
463 (zero_extend:DI (match_dup 1)))]
464 "TARGET_POWERPC64 && reload_completed"
466 (zero_extend:DI (match_dup 1)))
468 (compare:CC (match_dup 0)
472 (define_expand "extendsidi2"
473 [(set (match_operand:DI 0 "gpc_reg_operand" "")
474 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
479 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
480 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
485 [(set_attr "type" "load_ext,*")])
488 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
489 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
491 (clobber (match_scratch:DI 2 "=r,r"))]
496 [(set_attr "type" "compare")
497 (set_attr "length" "4,8")])
500 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
501 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
503 (clobber (match_scratch:DI 2 ""))]
504 "TARGET_POWERPC64 && reload_completed"
506 (sign_extend:DI (match_dup 1)))
508 (compare:CC (match_dup 2)
513 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
514 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
516 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
517 (sign_extend:DI (match_dup 1)))]
522 [(set_attr "type" "compare")
523 (set_attr "length" "4,8")])
526 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
527 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
529 (set (match_operand:DI 0 "gpc_reg_operand" "")
530 (sign_extend:DI (match_dup 1)))]
531 "TARGET_POWERPC64 && reload_completed"
533 (sign_extend:DI (match_dup 1)))
535 (compare:CC (match_dup 0)
539 (define_expand "zero_extendqisi2"
540 [(set (match_operand:SI 0 "gpc_reg_operand" "")
541 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
546 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
547 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
551 {rlinm|rlwinm} %0,%1,0,0xff"
552 [(set_attr "type" "load,*")])
555 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
556 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
558 (clobber (match_scratch:SI 2 "=r,r"))]
561 {andil.|andi.} %2,%1,0xff
563 [(set_attr "type" "compare")
564 (set_attr "length" "4,8")])
567 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
568 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
570 (clobber (match_scratch:SI 2 ""))]
573 (zero_extend:SI (match_dup 1)))
575 (compare:CC (match_dup 2)
580 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
581 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
583 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
584 (zero_extend:SI (match_dup 1)))]
587 {andil.|andi.} %0,%1,0xff
589 [(set_attr "type" "compare")
590 (set_attr "length" "4,8")])
593 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
594 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
596 (set (match_operand:SI 0 "gpc_reg_operand" "")
597 (zero_extend:SI (match_dup 1)))]
600 (zero_extend:SI (match_dup 1)))
602 (compare:CC (match_dup 0)
606 (define_expand "extendqisi2"
607 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
608 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
613 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
614 else if (TARGET_POWER)
615 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
617 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
621 (define_insn "extendqisi2_ppc"
622 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
623 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
628 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
629 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
631 (clobber (match_scratch:SI 2 "=r,r"))]
636 [(set_attr "type" "compare")
637 (set_attr "length" "4,8")])
640 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
641 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
643 (clobber (match_scratch:SI 2 ""))]
644 "TARGET_POWERPC && reload_completed"
646 (sign_extend:SI (match_dup 1)))
648 (compare:CC (match_dup 2)
653 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
654 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
656 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
657 (sign_extend:SI (match_dup 1)))]
662 [(set_attr "type" "compare")
663 (set_attr "length" "4,8")])
666 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
667 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
669 (set (match_operand:SI 0 "gpc_reg_operand" "")
670 (sign_extend:SI (match_dup 1)))]
671 "TARGET_POWERPC && reload_completed"
673 (sign_extend:SI (match_dup 1)))
675 (compare:CC (match_dup 0)
679 (define_expand "extendqisi2_power"
680 [(parallel [(set (match_dup 2)
681 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
683 (clobber (scratch:SI))])
684 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
685 (ashiftrt:SI (match_dup 2)
687 (clobber (scratch:SI))])]
690 { operands[1] = gen_lowpart (SImode, operands[1]);
691 operands[2] = gen_reg_rtx (SImode); }")
693 (define_expand "extendqisi2_no_power"
695 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
697 (set (match_operand:SI 0 "gpc_reg_operand" "")
698 (ashiftrt:SI (match_dup 2)
700 "! TARGET_POWER && ! TARGET_POWERPC"
702 { operands[1] = gen_lowpart (SImode, operands[1]);
703 operands[2] = gen_reg_rtx (SImode); }")
705 (define_expand "zero_extendqihi2"
706 [(set (match_operand:HI 0 "gpc_reg_operand" "")
707 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
712 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
713 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
717 {rlinm|rlwinm} %0,%1,0,0xff"
718 [(set_attr "type" "load,*")])
721 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
722 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
724 (clobber (match_scratch:HI 2 "=r,r"))]
727 {andil.|andi.} %2,%1,0xff
729 [(set_attr "type" "compare")
730 (set_attr "length" "4,8")])
733 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
734 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
736 (clobber (match_scratch:HI 2 ""))]
739 (zero_extend:HI (match_dup 1)))
741 (compare:CC (match_dup 2)
746 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
747 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
749 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
750 (zero_extend:HI (match_dup 1)))]
753 {andil.|andi.} %0,%1,0xff
755 [(set_attr "type" "compare")
756 (set_attr "length" "4,8")])
759 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
760 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
762 (set (match_operand:HI 0 "gpc_reg_operand" "")
763 (zero_extend:HI (match_dup 1)))]
766 (zero_extend:HI (match_dup 1)))
768 (compare:CC (match_dup 0)
772 (define_expand "extendqihi2"
773 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
774 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
779 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
780 else if (TARGET_POWER)
781 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
783 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
787 (define_insn "extendqihi2_ppc"
788 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
789 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
794 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
795 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
797 (clobber (match_scratch:HI 2 "=r,r"))]
802 [(set_attr "type" "compare")
803 (set_attr "length" "4,8")])
806 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
807 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
809 (clobber (match_scratch:HI 2 ""))]
810 "TARGET_POWERPC && reload_completed"
812 (sign_extend:HI (match_dup 1)))
814 (compare:CC (match_dup 2)
819 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
820 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
822 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
823 (sign_extend:HI (match_dup 1)))]
828 [(set_attr "type" "compare")
829 (set_attr "length" "4,8")])
832 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
833 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
835 (set (match_operand:HI 0 "gpc_reg_operand" "")
836 (sign_extend:HI (match_dup 1)))]
837 "TARGET_POWERPC && reload_completed"
839 (sign_extend:HI (match_dup 1)))
841 (compare:CC (match_dup 0)
845 (define_expand "extendqihi2_power"
846 [(parallel [(set (match_dup 2)
847 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
849 (clobber (scratch:SI))])
850 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
851 (ashiftrt:SI (match_dup 2)
853 (clobber (scratch:SI))])]
856 { operands[0] = gen_lowpart (SImode, operands[0]);
857 operands[1] = gen_lowpart (SImode, operands[1]);
858 operands[2] = gen_reg_rtx (SImode); }")
860 (define_expand "extendqihi2_no_power"
862 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
864 (set (match_operand:HI 0 "gpc_reg_operand" "")
865 (ashiftrt:SI (match_dup 2)
867 "! TARGET_POWER && ! TARGET_POWERPC"
869 { operands[0] = gen_lowpart (SImode, operands[0]);
870 operands[1] = gen_lowpart (SImode, operands[1]);
871 operands[2] = gen_reg_rtx (SImode); }")
873 (define_expand "zero_extendhisi2"
874 [(set (match_operand:SI 0 "gpc_reg_operand" "")
875 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
880 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
881 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
885 {rlinm|rlwinm} %0,%1,0,0xffff"
886 [(set_attr "type" "load,*")])
889 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
890 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
892 (clobber (match_scratch:SI 2 "=r,r"))]
895 {andil.|andi.} %2,%1,0xffff
897 [(set_attr "type" "compare")
898 (set_attr "length" "4,8")])
901 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
902 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
904 (clobber (match_scratch:SI 2 ""))]
907 (zero_extend:SI (match_dup 1)))
909 (compare:CC (match_dup 2)
914 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
915 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
917 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
918 (zero_extend:SI (match_dup 1)))]
921 {andil.|andi.} %0,%1,0xffff
923 [(set_attr "type" "compare")
924 (set_attr "length" "4,8")])
927 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
928 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
930 (set (match_operand:SI 0 "gpc_reg_operand" "")
931 (zero_extend:SI (match_dup 1)))]
934 (zero_extend:SI (match_dup 1)))
936 (compare:CC (match_dup 0)
940 (define_expand "extendhisi2"
941 [(set (match_operand:SI 0 "gpc_reg_operand" "")
942 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
947 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
948 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
953 [(set_attr "type" "load_ext,*")])
956 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
957 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
959 (clobber (match_scratch:SI 2 "=r,r"))]
964 [(set_attr "type" "compare")
965 (set_attr "length" "4,8")])
968 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
969 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
971 (clobber (match_scratch:SI 2 ""))]
974 (sign_extend:SI (match_dup 1)))
976 (compare:CC (match_dup 2)
981 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
982 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
984 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
985 (sign_extend:SI (match_dup 1)))]
990 [(set_attr "type" "compare")
991 (set_attr "length" "4,8")])
994 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
995 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
997 (set (match_operand:SI 0 "gpc_reg_operand" "")
998 (sign_extend:SI (match_dup 1)))]
1001 (sign_extend:SI (match_dup 1)))
1003 (compare:CC (match_dup 0)
1007 ;; Fixed-point arithmetic insns.
1009 (define_mode_attr add_op2 [(SI "reg_or_arith_cint_operand")
1010 (DI "reg_or_add_cint64_operand")])
1012 (define_expand "add<mode>3"
1013 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1014 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1015 (match_operand:SDI 2 "<add_op2>" "")))]
1019 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1021 if (non_short_cint_operand (operands[2], DImode))
1024 else if (GET_CODE (operands[2]) == CONST_INT
1025 && ! add_operand (operands[2], <MODE>mode))
1027 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1028 ? operands[0] : gen_reg_rtx (<MODE>mode));
1030 HOST_WIDE_INT val = INTVAL (operands[2]);
1031 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1032 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1034 if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L'))
1037 /* The ordering here is important for the prolog expander.
1038 When space is allocated from the stack, adding 'low' first may
1039 produce a temporary deallocation (which would be bad). */
1040 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1041 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1046 ;; Discourage ai/addic because of carry but provide it in an alternative
1047 ;; allowing register zero as source.
1048 (define_insn "*add<mode>3_internal1"
1049 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1050 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1051 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1055 {cal %0,%2(%1)|addi %0,%1,%2}
1057 {cau|addis} %0,%1,%v2"
1058 [(set_attr "length" "4,4,4,4")])
1060 (define_insn "addsi3_high"
1061 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1062 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1063 (high:SI (match_operand 2 "" ""))))]
1064 "TARGET_MACHO && !TARGET_64BIT"
1065 "{cau|addis} %0,%1,ha16(%2)"
1066 [(set_attr "length" "4")])
1068 (define_insn "*add<mode>3_internal2"
1069 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1070 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1071 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1073 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1076 {cax.|add.} %3,%1,%2
1077 {ai.|addic.} %3,%1,%2
1080 [(set_attr "type" "fast_compare,compare,compare,compare")
1081 (set_attr "length" "4,4,8,8")])
1084 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1085 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1086 (match_operand:GPR 2 "reg_or_short_operand" ""))
1088 (clobber (match_scratch:GPR 3 ""))]
1091 (plus:GPR (match_dup 1)
1094 (compare:CC (match_dup 3)
1098 (define_insn "*add<mode>3_internal3"
1099 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1100 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1101 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1103 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1104 (plus:P (match_dup 1)
1108 {cax.|add.} %0,%1,%2
1109 {ai.|addic.} %0,%1,%2
1112 [(set_attr "type" "fast_compare,compare,compare,compare")
1113 (set_attr "length" "4,4,8,8")])
1116 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1117 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1118 (match_operand:P 2 "reg_or_short_operand" ""))
1120 (set (match_operand:P 0 "gpc_reg_operand" "")
1121 (plus:P (match_dup 1) (match_dup 2)))]
1124 (plus:P (match_dup 1)
1127 (compare:CC (match_dup 0)
1131 ;; Split an add that we can't do in one insn into two insns, each of which
1132 ;; does one 16-bit part. This is used by combine. Note that the low-order
1133 ;; add should be last in case the result gets used in an address.
1136 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1137 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1138 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1140 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1141 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1144 HOST_WIDE_INT val = INTVAL (operands[2]);
1145 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1146 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1148 operands[4] = GEN_INT (low);
1149 if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L'))
1150 operands[3] = GEN_INT (rest);
1151 else if (! no_new_pseudos)
1153 operands[3] = gen_reg_rtx (DImode);
1154 emit_move_insn (operands[3], operands[2]);
1155 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1162 (define_insn "one_cmpl<mode>2"
1163 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1164 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1169 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1170 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1172 (clobber (match_scratch:P 2 "=r,r"))]
1177 [(set_attr "type" "compare")
1178 (set_attr "length" "4,8")])
1181 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1182 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1184 (clobber (match_scratch:P 2 ""))]
1187 (not:P (match_dup 1)))
1189 (compare:CC (match_dup 2)
1194 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1195 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1197 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1198 (not:P (match_dup 1)))]
1203 [(set_attr "type" "compare")
1204 (set_attr "length" "4,8")])
1207 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1208 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1210 (set (match_operand:P 0 "gpc_reg_operand" "")
1211 (not:P (match_dup 1)))]
1214 (not:P (match_dup 1)))
1216 (compare:CC (match_dup 0)
1221 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1222 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1223 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1225 "{sf%I1|subf%I1c} %0,%2,%1")
1228 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1229 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1230 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1237 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1238 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1239 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1241 (clobber (match_scratch:SI 3 "=r,r"))]
1244 {sf.|subfc.} %3,%2,%1
1246 [(set_attr "type" "compare")
1247 (set_attr "length" "4,8")])
1250 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1251 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1252 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1254 (clobber (match_scratch:P 3 "=r,r"))]
1259 [(set_attr "type" "fast_compare")
1260 (set_attr "length" "4,8")])
1263 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1264 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1265 (match_operand:P 2 "gpc_reg_operand" ""))
1267 (clobber (match_scratch:P 3 ""))]
1270 (minus:P (match_dup 1)
1273 (compare:CC (match_dup 3)
1278 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1279 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1280 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1282 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1283 (minus:SI (match_dup 1) (match_dup 2)))]
1286 {sf.|subfc.} %0,%2,%1
1288 [(set_attr "type" "compare")
1289 (set_attr "length" "4,8")])
1292 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1293 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1294 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1296 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1297 (minus:P (match_dup 1)
1303 [(set_attr "type" "fast_compare")
1304 (set_attr "length" "4,8")])
1307 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1308 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1309 (match_operand:P 2 "gpc_reg_operand" ""))
1311 (set (match_operand:P 0 "gpc_reg_operand" "")
1312 (minus:P (match_dup 1)
1316 (minus:P (match_dup 1)
1319 (compare:CC (match_dup 0)
1323 (define_mode_attr sub_op2 [(SI "reg_or_arith_cint_operand")
1324 (DI "reg_or_sub_cint64_operand")])
1326 (define_expand "sub<mode>3"
1327 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1328 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1329 (match_operand:SDI 2 "<sub_op2>" "")))]
1333 if (GET_CODE (operands[2]) == CONST_INT)
1335 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1336 negate_rtx (<MODE>mode, operands[2])));
1341 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1342 ;; instruction and some auxiliary computations. Then we just have a single
1343 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1346 (define_expand "sminsi3"
1348 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1349 (match_operand:SI 2 "reg_or_short_operand" ""))
1351 (minus:SI (match_dup 2) (match_dup 1))))
1352 (set (match_operand:SI 0 "gpc_reg_operand" "")
1353 (minus:SI (match_dup 2) (match_dup 3)))]
1354 "TARGET_POWER || TARGET_ISEL"
1359 operands[2] = force_reg (SImode, operands[2]);
1360 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1364 operands[3] = gen_reg_rtx (SImode);
1368 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1369 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1370 (match_operand:SI 2 "reg_or_short_operand" "")))
1371 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1374 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1376 (minus:SI (match_dup 2) (match_dup 1))))
1377 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1380 (define_expand "smaxsi3"
1382 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1383 (match_operand:SI 2 "reg_or_short_operand" ""))
1385 (minus:SI (match_dup 2) (match_dup 1))))
1386 (set (match_operand:SI 0 "gpc_reg_operand" "")
1387 (plus:SI (match_dup 3) (match_dup 1)))]
1388 "TARGET_POWER || TARGET_ISEL"
1393 operands[2] = force_reg (SImode, operands[2]);
1394 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1397 operands[3] = gen_reg_rtx (SImode);
1401 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1402 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1403 (match_operand:SI 2 "reg_or_short_operand" "")))
1404 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1407 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1409 (minus:SI (match_dup 2) (match_dup 1))))
1410 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1413 (define_expand "uminsi3"
1414 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1416 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1418 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1420 (minus:SI (match_dup 4) (match_dup 3))))
1421 (set (match_operand:SI 0 "gpc_reg_operand" "")
1422 (minus:SI (match_dup 2) (match_dup 3)))]
1423 "TARGET_POWER || TARGET_ISEL"
1428 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1431 operands[3] = gen_reg_rtx (SImode);
1432 operands[4] = gen_reg_rtx (SImode);
1433 operands[5] = GEN_INT (-2147483647 - 1);
1436 (define_expand "umaxsi3"
1437 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1439 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1441 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1443 (minus:SI (match_dup 4) (match_dup 3))))
1444 (set (match_operand:SI 0 "gpc_reg_operand" "")
1445 (plus:SI (match_dup 3) (match_dup 1)))]
1446 "TARGET_POWER || TARGET_ISEL"
1451 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1454 operands[3] = gen_reg_rtx (SImode);
1455 operands[4] = gen_reg_rtx (SImode);
1456 operands[5] = GEN_INT (-2147483647 - 1);
1460 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1461 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1462 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1464 (minus:SI (match_dup 2) (match_dup 1))))]
1469 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1471 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1472 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1474 (minus:SI (match_dup 2) (match_dup 1)))
1476 (clobber (match_scratch:SI 3 "=r,r"))]
1481 [(set_attr "type" "delayed_compare")
1482 (set_attr "length" "4,8")])
1485 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1487 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1488 (match_operand:SI 2 "reg_or_short_operand" ""))
1490 (minus:SI (match_dup 2) (match_dup 1)))
1492 (clobber (match_scratch:SI 3 ""))]
1493 "TARGET_POWER && reload_completed"
1495 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1497 (minus:SI (match_dup 2) (match_dup 1))))
1499 (compare:CC (match_dup 3)
1504 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1506 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1507 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1509 (minus:SI (match_dup 2) (match_dup 1)))
1511 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1512 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1514 (minus:SI (match_dup 2) (match_dup 1))))]
1519 [(set_attr "type" "delayed_compare")
1520 (set_attr "length" "4,8")])
1523 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1525 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1526 (match_operand:SI 2 "reg_or_short_operand" ""))
1528 (minus:SI (match_dup 2) (match_dup 1)))
1530 (set (match_operand:SI 0 "gpc_reg_operand" "")
1531 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1533 (minus:SI (match_dup 2) (match_dup 1))))]
1534 "TARGET_POWER && reload_completed"
1536 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1538 (minus:SI (match_dup 2) (match_dup 1))))
1540 (compare:CC (match_dup 0)
1544 ;; We don't need abs with condition code because such comparisons should
1546 (define_expand "abssi2"
1547 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1548 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1554 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1557 else if (! TARGET_POWER)
1559 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1564 (define_insn "*abssi2_power"
1565 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1566 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1570 (define_insn_and_split "abssi2_isel"
1571 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1572 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1573 (clobber (match_scratch:SI 2 "=&b"))
1574 (clobber (match_scratch:CC 3 "=y"))]
1577 "&& reload_completed"
1578 [(set (match_dup 2) (neg:SI (match_dup 1)))
1580 (compare:CC (match_dup 1)
1583 (if_then_else:SI (ge (match_dup 3)
1589 (define_insn_and_split "abssi2_nopower"
1590 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1591 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1592 (clobber (match_scratch:SI 2 "=&r,&r"))]
1593 "! TARGET_POWER && ! TARGET_ISEL"
1595 "&& reload_completed"
1596 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1597 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1598 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1601 (define_insn "*nabs_power"
1602 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1603 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1607 (define_insn_and_split "*nabs_nopower"
1608 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1609 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1610 (clobber (match_scratch:SI 2 "=&r,&r"))]
1613 "&& reload_completed"
1614 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1615 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1616 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1619 (define_expand "neg<mode>2"
1620 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1621 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1625 (define_insn "*neg<mode>2_internal"
1626 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1627 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1632 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1633 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1635 (clobber (match_scratch:P 2 "=r,r"))]
1640 [(set_attr "type" "fast_compare")
1641 (set_attr "length" "4,8")])
1644 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1645 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1647 (clobber (match_scratch:P 2 ""))]
1650 (neg:P (match_dup 1)))
1652 (compare:CC (match_dup 2)
1657 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1658 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1660 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1661 (neg:P (match_dup 1)))]
1666 [(set_attr "type" "fast_compare")
1667 (set_attr "length" "4,8")])
1670 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1671 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1673 (set (match_operand:P 0 "gpc_reg_operand" "")
1674 (neg:P (match_dup 1)))]
1677 (neg:P (match_dup 1)))
1679 (compare:CC (match_dup 0)
1683 (define_insn "clz<mode>2"
1684 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1685 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1687 "{cntlz|cntlz<wd>} %0,%1")
1689 (define_expand "ctz<mode>2"
1691 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1692 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1694 (clobber (scratch:CC))])
1695 (set (match_dup 4) (clz:GPR (match_dup 3)))
1696 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1697 (minus:GPR (match_dup 5) (match_dup 4)))]
1700 operands[2] = gen_reg_rtx (<MODE>mode);
1701 operands[3] = gen_reg_rtx (<MODE>mode);
1702 operands[4] = gen_reg_rtx (<MODE>mode);
1703 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1706 (define_expand "ffs<mode>2"
1708 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1709 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1711 (clobber (scratch:CC))])
1712 (set (match_dup 4) (clz:GPR (match_dup 3)))
1713 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1714 (minus:GPR (match_dup 5) (match_dup 4)))]
1717 operands[2] = gen_reg_rtx (<MODE>mode);
1718 operands[3] = gen_reg_rtx (<MODE>mode);
1719 operands[4] = gen_reg_rtx (<MODE>mode);
1720 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1723 (define_expand "popcount<mode>2"
1725 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1728 (mult:GPR (match_dup 2) (match_dup 4)))
1729 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1730 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
1733 operands[2] = gen_reg_rtx (<MODE>mode);
1734 operands[3] = gen_reg_rtx (<MODE>mode);
1735 operands[4] = force_reg (<MODE>mode,
1736 <MODE>mode == SImode
1737 ? GEN_INT (0x01010101)
1738 : GEN_INT ((HOST_WIDE_INT)
1739 0x01010101 << 32 | 0x01010101));
1740 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
1743 (define_insn "popcntb<mode>2"
1744 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1745 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1750 (define_expand "mulsi3"
1751 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1752 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1753 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1758 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1760 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1764 (define_insn "mulsi3_mq"
1765 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1766 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1767 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1768 (clobber (match_scratch:SI 3 "=q,q"))]
1771 {muls|mullw} %0,%1,%2
1772 {muli|mulli} %0,%1,%2"
1774 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1775 (const_string "imul3")
1776 (match_operand:SI 2 "short_cint_operand" "")
1777 (const_string "imul2")]
1778 (const_string "imul")))])
1780 (define_insn "mulsi3_no_mq"
1781 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1782 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1783 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1786 {muls|mullw} %0,%1,%2
1787 {muli|mulli} %0,%1,%2"
1789 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1790 (const_string "imul3")
1791 (match_operand:SI 2 "short_cint_operand" "")
1792 (const_string "imul2")]
1793 (const_string "imul")))])
1795 (define_insn "*mulsi3_mq_internal1"
1796 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1797 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1798 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1800 (clobber (match_scratch:SI 3 "=r,r"))
1801 (clobber (match_scratch:SI 4 "=q,q"))]
1804 {muls.|mullw.} %3,%1,%2
1806 [(set_attr "type" "imul_compare")
1807 (set_attr "length" "4,8")])
1810 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1811 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1812 (match_operand:SI 2 "gpc_reg_operand" ""))
1814 (clobber (match_scratch:SI 3 ""))
1815 (clobber (match_scratch:SI 4 ""))]
1816 "TARGET_POWER && reload_completed"
1817 [(parallel [(set (match_dup 3)
1818 (mult:SI (match_dup 1) (match_dup 2)))
1819 (clobber (match_dup 4))])
1821 (compare:CC (match_dup 3)
1825 (define_insn "*mulsi3_no_mq_internal1"
1826 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1827 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1828 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1830 (clobber (match_scratch:SI 3 "=r,r"))]
1833 {muls.|mullw.} %3,%1,%2
1835 [(set_attr "type" "imul_compare")
1836 (set_attr "length" "4,8")])
1839 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1840 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1841 (match_operand:SI 2 "gpc_reg_operand" ""))
1843 (clobber (match_scratch:SI 3 ""))]
1844 "! TARGET_POWER && reload_completed"
1846 (mult:SI (match_dup 1) (match_dup 2)))
1848 (compare:CC (match_dup 3)
1852 (define_insn "*mulsi3_mq_internal2"
1853 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1854 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1855 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1857 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1858 (mult:SI (match_dup 1) (match_dup 2)))
1859 (clobber (match_scratch:SI 4 "=q,q"))]
1862 {muls.|mullw.} %0,%1,%2
1864 [(set_attr "type" "imul_compare")
1865 (set_attr "length" "4,8")])
1868 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1869 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1870 (match_operand:SI 2 "gpc_reg_operand" ""))
1872 (set (match_operand:SI 0 "gpc_reg_operand" "")
1873 (mult:SI (match_dup 1) (match_dup 2)))
1874 (clobber (match_scratch:SI 4 ""))]
1875 "TARGET_POWER && reload_completed"
1876 [(parallel [(set (match_dup 0)
1877 (mult:SI (match_dup 1) (match_dup 2)))
1878 (clobber (match_dup 4))])
1880 (compare:CC (match_dup 0)
1884 (define_insn "*mulsi3_no_mq_internal2"
1885 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1886 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1887 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1889 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1890 (mult:SI (match_dup 1) (match_dup 2)))]
1893 {muls.|mullw.} %0,%1,%2
1895 [(set_attr "type" "imul_compare")
1896 (set_attr "length" "4,8")])
1899 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1900 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1901 (match_operand:SI 2 "gpc_reg_operand" ""))
1903 (set (match_operand:SI 0 "gpc_reg_operand" "")
1904 (mult:SI (match_dup 1) (match_dup 2)))]
1905 "! TARGET_POWER && reload_completed"
1907 (mult:SI (match_dup 1) (match_dup 2)))
1909 (compare:CC (match_dup 0)
1913 ;; Operand 1 is divided by operand 2; quotient goes to operand
1914 ;; 0 and remainder to operand 3.
1915 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1917 (define_expand "divmodsi4"
1918 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1919 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1920 (match_operand:SI 2 "gpc_reg_operand" "")))
1921 (set (match_operand:SI 3 "register_operand" "")
1922 (mod:SI (match_dup 1) (match_dup 2)))])]
1923 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1926 if (! TARGET_POWER && ! TARGET_POWERPC)
1928 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1929 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1930 emit_insn (gen_divss_call ());
1931 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1932 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1937 (define_insn "*divmodsi4_internal"
1938 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1939 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1940 (match_operand:SI 2 "gpc_reg_operand" "r")))
1941 (set (match_operand:SI 3 "register_operand" "=q")
1942 (mod:SI (match_dup 1) (match_dup 2)))]
1945 [(set_attr "type" "idiv")])
1947 (define_expand "udivsi3"
1948 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1949 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1950 (match_operand:SI 2 "gpc_reg_operand" "")))]
1951 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1954 if (! TARGET_POWER && ! TARGET_POWERPC)
1956 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1957 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1958 emit_insn (gen_quous_call ());
1959 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1962 else if (TARGET_POWER)
1964 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1969 (define_insn "udivsi3_mq"
1970 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1971 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1972 (match_operand:SI 2 "gpc_reg_operand" "r")))
1973 (clobber (match_scratch:SI 3 "=q"))]
1974 "TARGET_POWERPC && TARGET_POWER"
1976 [(set_attr "type" "idiv")])
1978 (define_insn "*udivsi3_no_mq"
1979 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1980 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1981 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1982 "TARGET_POWERPC && ! TARGET_POWER"
1984 [(set_attr "type" "idiv")])
1986 ;; For powers of two we can do srai/aze for divide and then adjust for
1987 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1988 ;; used; for PowerPC, force operands into register and do a normal divide;
1989 ;; for AIX common-mode, use quoss call on register operands.
1990 (define_expand "divsi3"
1991 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1992 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1993 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1997 if (GET_CODE (operands[2]) == CONST_INT
1998 && INTVAL (operands[2]) > 0
1999 && exact_log2 (INTVAL (operands[2])) >= 0)
2001 else if (TARGET_POWERPC)
2003 operands[2] = force_reg (SImode, operands[2]);
2006 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2010 else if (TARGET_POWER)
2014 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2015 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2016 emit_insn (gen_quoss_call ());
2017 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2022 (define_insn "divsi3_mq"
2023 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2024 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2025 (match_operand:SI 2 "gpc_reg_operand" "r")))
2026 (clobber (match_scratch:SI 3 "=q"))]
2027 "TARGET_POWERPC && TARGET_POWER"
2029 [(set_attr "type" "idiv")])
2031 (define_insn "*divsi3_no_mq"
2032 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2033 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2034 (match_operand:SI 2 "gpc_reg_operand" "r")))]
2035 "TARGET_POWERPC && ! TARGET_POWER"
2037 [(set_attr "type" "idiv")])
2039 (define_expand "modsi3"
2040 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2041 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2042 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2050 if (GET_CODE (operands[2]) != CONST_INT
2051 || INTVAL (operands[2]) <= 0
2052 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2055 temp1 = gen_reg_rtx (SImode);
2056 temp2 = gen_reg_rtx (SImode);
2058 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
2059 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
2060 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
2065 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2066 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2067 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
2069 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
2070 [(set_attr "type" "two")
2071 (set_attr "length" "8")])
2074 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2075 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2076 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2078 (clobber (match_scratch:SI 3 "=r,r"))]
2081 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
2083 [(set_attr "type" "compare")
2084 (set_attr "length" "8,12")])
2087 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2088 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2089 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2091 (clobber (match_scratch:SI 3 ""))]
2094 (div:SI (match_dup 1) (match_dup 2)))
2096 (compare:CC (match_dup 3)
2101 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2102 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2103 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2105 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2106 (div:SI (match_dup 1) (match_dup 2)))]
2109 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2111 [(set_attr "type" "compare")
2112 (set_attr "length" "8,12")])
2115 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2116 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2117 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2119 (set (match_operand:SI 0 "gpc_reg_operand" "")
2120 (div:SI (match_dup 1) (match_dup 2)))]
2123 (div:SI (match_dup 1) (match_dup 2)))
2125 (compare:CC (match_dup 0)
2130 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2133 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2135 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2136 (match_operand:SI 3 "gpc_reg_operand" "r")))
2137 (set (match_operand:SI 2 "register_operand" "=*q")
2140 (zero_extend:DI (match_dup 1)) (const_int 32))
2141 (zero_extend:DI (match_dup 4)))
2145 [(set_attr "type" "idiv")])
2147 ;; To do unsigned divide we handle the cases of the divisor looking like a
2148 ;; negative number. If it is a constant that is less than 2**31, we don't
2149 ;; have to worry about the branches. So make a few subroutines here.
2151 ;; First comes the normal case.
2152 (define_expand "udivmodsi4_normal"
2153 [(set (match_dup 4) (const_int 0))
2154 (parallel [(set (match_operand:SI 0 "" "")
2155 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2157 (zero_extend:DI (match_operand:SI 1 "" "")))
2158 (match_operand:SI 2 "" "")))
2159 (set (match_operand:SI 3 "" "")
2160 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2162 (zero_extend:DI (match_dup 1)))
2166 { operands[4] = gen_reg_rtx (SImode); }")
2168 ;; This handles the branches.
2169 (define_expand "udivmodsi4_tests"
2170 [(set (match_operand:SI 0 "" "") (const_int 0))
2171 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2172 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2173 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2174 (label_ref (match_operand:SI 4 "" "")) (pc)))
2175 (set (match_dup 0) (const_int 1))
2176 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2177 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2178 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2179 (label_ref (match_dup 4)) (pc)))]
2182 { operands[5] = gen_reg_rtx (CCUNSmode);
2183 operands[6] = gen_reg_rtx (CCmode);
2186 (define_expand "udivmodsi4"
2187 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2188 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2189 (match_operand:SI 2 "reg_or_cint_operand" "")))
2190 (set (match_operand:SI 3 "gpc_reg_operand" "")
2191 (umod:SI (match_dup 1) (match_dup 2)))])]
2199 if (! TARGET_POWERPC)
2201 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2202 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2203 emit_insn (gen_divus_call ());
2204 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2205 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2212 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2214 operands[2] = force_reg (SImode, operands[2]);
2215 label = gen_label_rtx ();
2216 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2217 operands[3], label));
2220 operands[2] = force_reg (SImode, operands[2]);
2222 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2230 ;; AIX architecture-independent common-mode multiply (DImode),
2231 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2232 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2233 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2234 ;; assumed unused if generating common-mode, so ignore.
2235 (define_insn "mulh_call"
2238 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2239 (sign_extend:DI (reg:SI 4)))
2241 (clobber (match_scratch:SI 0 "=l"))]
2242 "! TARGET_POWER && ! TARGET_POWERPC"
2244 [(set_attr "type" "imul")])
2246 (define_insn "mull_call"
2248 (mult:DI (sign_extend:DI (reg:SI 3))
2249 (sign_extend:DI (reg:SI 4))))
2250 (clobber (match_scratch:SI 0 "=l"))
2251 (clobber (reg:SI 0))]
2252 "! TARGET_POWER && ! TARGET_POWERPC"
2254 [(set_attr "type" "imul")])
2256 (define_insn "divss_call"
2258 (div:SI (reg:SI 3) (reg:SI 4)))
2260 (mod:SI (reg:SI 3) (reg:SI 4)))
2261 (clobber (match_scratch:SI 0 "=l"))
2262 (clobber (reg:SI 0))]
2263 "! TARGET_POWER && ! TARGET_POWERPC"
2265 [(set_attr "type" "idiv")])
2267 (define_insn "divus_call"
2269 (udiv:SI (reg:SI 3) (reg:SI 4)))
2271 (umod:SI (reg:SI 3) (reg:SI 4)))
2272 (clobber (match_scratch:SI 0 "=l"))
2273 (clobber (reg:SI 0))
2274 (clobber (match_scratch:CC 1 "=x"))
2275 (clobber (reg:CC 69))]
2276 "! TARGET_POWER && ! TARGET_POWERPC"
2278 [(set_attr "type" "idiv")])
2280 (define_insn "quoss_call"
2282 (div:SI (reg:SI 3) (reg:SI 4)))
2283 (clobber (match_scratch:SI 0 "=l"))]
2284 "! TARGET_POWER && ! TARGET_POWERPC"
2286 [(set_attr "type" "idiv")])
2288 (define_insn "quous_call"
2290 (udiv:SI (reg:SI 3) (reg:SI 4)))
2291 (clobber (match_scratch:SI 0 "=l"))
2292 (clobber (reg:SI 0))
2293 (clobber (match_scratch:CC 1 "=x"))
2294 (clobber (reg:CC 69))]
2295 "! TARGET_POWER && ! TARGET_POWERPC"
2297 [(set_attr "type" "idiv")])
2299 ;; Logical instructions
2300 ;; The logical instructions are mostly combined by using match_operator,
2301 ;; but the plain AND insns are somewhat different because there is no
2302 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2303 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2305 (define_insn "andsi3"
2306 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2307 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2308 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2309 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2313 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2314 {andil.|andi.} %0,%1,%b2
2315 {andiu.|andis.} %0,%1,%u2"
2316 [(set_attr "type" "*,*,compare,compare")])
2318 ;; Note to set cr's other than cr0 we do the and immediate and then
2319 ;; the test again -- this avoids a mfcr which on the higher end
2320 ;; machines causes an execution serialization
2322 (define_insn "*andsi3_internal2"
2323 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2324 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2325 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2327 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2328 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2332 {andil.|andi.} %3,%1,%b2
2333 {andiu.|andis.} %3,%1,%u2
2334 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2339 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2340 (set_attr "length" "4,4,4,4,8,8,8,8")])
2342 (define_insn "*andsi3_internal3"
2343 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2344 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2345 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2347 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2348 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2352 {andil.|andi.} %3,%1,%b2
2353 {andiu.|andis.} %3,%1,%u2
2354 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2359 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2360 (set_attr "length" "8,4,4,4,8,8,8,8")])
2363 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2364 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2365 (match_operand:SI 2 "and_operand" ""))
2367 (clobber (match_scratch:SI 3 ""))
2368 (clobber (match_scratch:CC 4 ""))]
2370 [(parallel [(set (match_dup 3)
2371 (and:SI (match_dup 1)
2373 (clobber (match_dup 4))])
2375 (compare:CC (match_dup 3)
2379 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2380 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2383 [(set (match_operand:CC 0 "cc_reg_operand" "")
2384 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2385 (match_operand:SI 2 "gpc_reg_operand" ""))
2387 (clobber (match_scratch:SI 3 ""))
2388 (clobber (match_scratch:CC 4 ""))]
2389 "TARGET_POWERPC64 && reload_completed"
2390 [(parallel [(set (match_dup 3)
2391 (and:SI (match_dup 1)
2393 (clobber (match_dup 4))])
2395 (compare:CC (match_dup 3)
2399 (define_insn "*andsi3_internal4"
2400 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2401 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2402 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2404 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2405 (and:SI (match_dup 1)
2407 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2411 {andil.|andi.} %0,%1,%b2
2412 {andiu.|andis.} %0,%1,%u2
2413 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2418 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2419 (set_attr "length" "4,4,4,4,8,8,8,8")])
2421 (define_insn "*andsi3_internal5"
2422 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2423 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2424 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2426 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2427 (and:SI (match_dup 1)
2429 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2433 {andil.|andi.} %0,%1,%b2
2434 {andiu.|andis.} %0,%1,%u2
2435 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2440 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2441 (set_attr "length" "8,4,4,4,8,8,8,8")])
2444 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2445 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2446 (match_operand:SI 2 "and_operand" ""))
2448 (set (match_operand:SI 0 "gpc_reg_operand" "")
2449 (and:SI (match_dup 1)
2451 (clobber (match_scratch:CC 4 ""))]
2453 [(parallel [(set (match_dup 0)
2454 (and:SI (match_dup 1)
2456 (clobber (match_dup 4))])
2458 (compare:CC (match_dup 0)
2463 [(set (match_operand:CC 3 "cc_reg_operand" "")
2464 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2465 (match_operand:SI 2 "gpc_reg_operand" ""))
2467 (set (match_operand:SI 0 "gpc_reg_operand" "")
2468 (and:SI (match_dup 1)
2470 (clobber (match_scratch:CC 4 ""))]
2471 "TARGET_POWERPC64 && reload_completed"
2472 [(parallel [(set (match_dup 0)
2473 (and:SI (match_dup 1)
2475 (clobber (match_dup 4))])
2477 (compare:CC (match_dup 0)
2481 ;; Handle the PowerPC64 rlwinm corner case
2483 (define_insn_and_split "*andsi3_internal6"
2484 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2485 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2486 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2491 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2494 (rotate:SI (match_dup 0) (match_dup 5)))]
2497 int mb = extract_MB (operands[2]);
2498 int me = extract_ME (operands[2]);
2499 operands[3] = GEN_INT (me + 1);
2500 operands[5] = GEN_INT (32 - (me + 1));
2501 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2503 [(set_attr "length" "8")])
2505 (define_expand "iorsi3"
2506 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2507 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2508 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2512 if (GET_CODE (operands[2]) == CONST_INT
2513 && ! logical_operand (operands[2], SImode))
2515 HOST_WIDE_INT value = INTVAL (operands[2]);
2516 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2517 ? operands[0] : gen_reg_rtx (SImode));
2519 emit_insn (gen_iorsi3 (tmp, operands[1],
2520 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2521 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2526 (define_expand "xorsi3"
2527 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2528 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2529 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2533 if (GET_CODE (operands[2]) == CONST_INT
2534 && ! logical_operand (operands[2], SImode))
2536 HOST_WIDE_INT value = INTVAL (operands[2]);
2537 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2538 ? operands[0] : gen_reg_rtx (SImode));
2540 emit_insn (gen_xorsi3 (tmp, operands[1],
2541 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2542 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2547 (define_insn "*boolsi3_internal1"
2548 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2549 (match_operator:SI 3 "boolean_or_operator"
2550 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2551 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2555 {%q3il|%q3i} %0,%1,%b2
2556 {%q3iu|%q3is} %0,%1,%u2")
2558 (define_insn "*boolsi3_internal2"
2559 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2560 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2561 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2562 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2564 (clobber (match_scratch:SI 3 "=r,r"))]
2569 [(set_attr "type" "compare")
2570 (set_attr "length" "4,8")])
2573 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2574 (compare:CC (match_operator:SI 4 "boolean_operator"
2575 [(match_operand:SI 1 "gpc_reg_operand" "")
2576 (match_operand:SI 2 "gpc_reg_operand" "")])
2578 (clobber (match_scratch:SI 3 ""))]
2579 "TARGET_32BIT && reload_completed"
2580 [(set (match_dup 3) (match_dup 4))
2582 (compare:CC (match_dup 3)
2586 (define_insn "*boolsi3_internal3"
2587 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2588 (compare:CC (match_operator:SI 4 "boolean_operator"
2589 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2590 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2592 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2598 [(set_attr "type" "compare")
2599 (set_attr "length" "4,8")])
2602 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2603 (compare:CC (match_operator:SI 4 "boolean_operator"
2604 [(match_operand:SI 1 "gpc_reg_operand" "")
2605 (match_operand:SI 2 "gpc_reg_operand" "")])
2607 (set (match_operand:SI 0 "gpc_reg_operand" "")
2609 "TARGET_32BIT && reload_completed"
2610 [(set (match_dup 0) (match_dup 4))
2612 (compare:CC (match_dup 0)
2616 ;; Split a logical operation that we can't do in one insn into two insns,
2617 ;; each of which does one 16-bit part. This is used by combine.
2620 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2621 (match_operator:SI 3 "boolean_or_operator"
2622 [(match_operand:SI 1 "gpc_reg_operand" "")
2623 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2625 [(set (match_dup 0) (match_dup 4))
2626 (set (match_dup 0) (match_dup 5))]
2630 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2631 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2633 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2634 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2638 (define_insn "*boolcsi3_internal1"
2639 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2640 (match_operator:SI 3 "boolean_operator"
2641 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2642 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2646 (define_insn "*boolcsi3_internal2"
2647 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2648 (compare:CC (match_operator:SI 4 "boolean_operator"
2649 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2650 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2652 (clobber (match_scratch:SI 3 "=r,r"))]
2657 [(set_attr "type" "compare")
2658 (set_attr "length" "4,8")])
2661 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2662 (compare:CC (match_operator:SI 4 "boolean_operator"
2663 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2664 (match_operand:SI 2 "gpc_reg_operand" "")])
2666 (clobber (match_scratch:SI 3 ""))]
2667 "TARGET_32BIT && reload_completed"
2668 [(set (match_dup 3) (match_dup 4))
2670 (compare:CC (match_dup 3)
2674 (define_insn "*boolcsi3_internal3"
2675 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2676 (compare:CC (match_operator:SI 4 "boolean_operator"
2677 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2678 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2680 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2686 [(set_attr "type" "compare")
2687 (set_attr "length" "4,8")])
2690 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2691 (compare:CC (match_operator:SI 4 "boolean_operator"
2692 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2693 (match_operand:SI 2 "gpc_reg_operand" "")])
2695 (set (match_operand:SI 0 "gpc_reg_operand" "")
2697 "TARGET_32BIT && reload_completed"
2698 [(set (match_dup 0) (match_dup 4))
2700 (compare:CC (match_dup 0)
2704 (define_insn "*boolccsi3_internal1"
2705 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2706 (match_operator:SI 3 "boolean_operator"
2707 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2708 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2712 (define_insn "*boolccsi3_internal2"
2713 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2714 (compare:CC (match_operator:SI 4 "boolean_operator"
2715 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2716 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2718 (clobber (match_scratch:SI 3 "=r,r"))]
2723 [(set_attr "type" "compare")
2724 (set_attr "length" "4,8")])
2727 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2728 (compare:CC (match_operator:SI 4 "boolean_operator"
2729 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2730 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2732 (clobber (match_scratch:SI 3 ""))]
2733 "TARGET_32BIT && reload_completed"
2734 [(set (match_dup 3) (match_dup 4))
2736 (compare:CC (match_dup 3)
2740 (define_insn "*boolccsi3_internal3"
2741 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2742 (compare:CC (match_operator:SI 4 "boolean_operator"
2743 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2744 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2746 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2752 [(set_attr "type" "compare")
2753 (set_attr "length" "4,8")])
2756 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2757 (compare:CC (match_operator:SI 4 "boolean_operator"
2758 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2759 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2761 (set (match_operand:SI 0 "gpc_reg_operand" "")
2763 "TARGET_32BIT && reload_completed"
2764 [(set (match_dup 0) (match_dup 4))
2766 (compare:CC (match_dup 0)
2770 ;; maskir insn. We need four forms because things might be in arbitrary
2771 ;; orders. Don't define forms that only set CR fields because these
2772 ;; would modify an input register.
2774 (define_insn "*maskir_internal1"
2775 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2776 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2777 (match_operand:SI 1 "gpc_reg_operand" "0"))
2778 (and:SI (match_dup 2)
2779 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2783 (define_insn "*maskir_internal2"
2784 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2785 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2786 (match_operand:SI 1 "gpc_reg_operand" "0"))
2787 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2792 (define_insn "*maskir_internal3"
2793 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2794 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2795 (match_operand:SI 3 "gpc_reg_operand" "r"))
2796 (and:SI (not:SI (match_dup 2))
2797 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2801 (define_insn "*maskir_internal4"
2802 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2803 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2804 (match_operand:SI 2 "gpc_reg_operand" "r"))
2805 (and:SI (not:SI (match_dup 2))
2806 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2810 (define_insn "*maskir_internal5"
2811 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2813 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2814 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2815 (and:SI (match_dup 2)
2816 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2818 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2819 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2820 (and:SI (match_dup 2) (match_dup 3))))]
2825 [(set_attr "type" "compare")
2826 (set_attr "length" "4,8")])
2829 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2831 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2832 (match_operand:SI 1 "gpc_reg_operand" ""))
2833 (and:SI (match_dup 2)
2834 (match_operand:SI 3 "gpc_reg_operand" "")))
2836 (set (match_operand:SI 0 "gpc_reg_operand" "")
2837 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2838 (and:SI (match_dup 2) (match_dup 3))))]
2839 "TARGET_POWER && reload_completed"
2841 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2842 (and:SI (match_dup 2) (match_dup 3))))
2844 (compare:CC (match_dup 0)
2848 (define_insn "*maskir_internal6"
2849 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2851 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2852 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2853 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2856 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2857 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2858 (and:SI (match_dup 3) (match_dup 2))))]
2863 [(set_attr "type" "compare")
2864 (set_attr "length" "4,8")])
2867 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2869 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2870 (match_operand:SI 1 "gpc_reg_operand" ""))
2871 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2874 (set (match_operand:SI 0 "gpc_reg_operand" "")
2875 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2876 (and:SI (match_dup 3) (match_dup 2))))]
2877 "TARGET_POWER && reload_completed"
2879 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2880 (and:SI (match_dup 3) (match_dup 2))))
2882 (compare:CC (match_dup 0)
2886 (define_insn "*maskir_internal7"
2887 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2889 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2890 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2891 (and:SI (not:SI (match_dup 2))
2892 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2894 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2895 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2896 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2901 [(set_attr "type" "compare")
2902 (set_attr "length" "4,8")])
2905 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2907 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2908 (match_operand:SI 3 "gpc_reg_operand" ""))
2909 (and:SI (not:SI (match_dup 2))
2910 (match_operand:SI 1 "gpc_reg_operand" "")))
2912 (set (match_operand:SI 0 "gpc_reg_operand" "")
2913 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2914 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2915 "TARGET_POWER && reload_completed"
2917 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2918 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2920 (compare:CC (match_dup 0)
2924 (define_insn "*maskir_internal8"
2925 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2927 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2928 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2929 (and:SI (not:SI (match_dup 2))
2930 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2932 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2933 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2934 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2939 [(set_attr "type" "compare")
2940 (set_attr "length" "4,8")])
2943 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2945 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2946 (match_operand:SI 2 "gpc_reg_operand" ""))
2947 (and:SI (not:SI (match_dup 2))
2948 (match_operand:SI 1 "gpc_reg_operand" "")))
2950 (set (match_operand:SI 0 "gpc_reg_operand" "")
2951 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2952 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2953 "TARGET_POWER && reload_completed"
2955 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2956 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2958 (compare:CC (match_dup 0)
2962 ;; Rotate and shift insns, in all their variants. These support shifts,
2963 ;; field inserts and extracts, and various combinations thereof.
2964 (define_expand "insv"
2965 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2966 (match_operand:SI 1 "const_int_operand" "")
2967 (match_operand:SI 2 "const_int_operand" ""))
2968 (match_operand 3 "gpc_reg_operand" ""))]
2972 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2973 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2974 compiler if the address of the structure is taken later. */
2975 if (GET_CODE (operands[0]) == SUBREG
2976 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2979 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2980 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2982 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2986 (define_insn "insvsi"
2987 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2988 (match_operand:SI 1 "const_int_operand" "i")
2989 (match_operand:SI 2 "const_int_operand" "i"))
2990 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2994 int start = INTVAL (operands[2]) & 31;
2995 int size = INTVAL (operands[1]) & 31;
2997 operands[4] = GEN_INT (32 - start - size);
2998 operands[1] = GEN_INT (start + size - 1);
2999 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3001 [(set_attr "type" "insert_word")])
3003 (define_insn "*insvsi_internal1"
3004 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3005 (match_operand:SI 1 "const_int_operand" "i")
3006 (match_operand:SI 2 "const_int_operand" "i"))
3007 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3008 (match_operand:SI 4 "const_int_operand" "i")))]
3009 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3012 int shift = INTVAL (operands[4]) & 31;
3013 int start = INTVAL (operands[2]) & 31;
3014 int size = INTVAL (operands[1]) & 31;
3016 operands[4] = GEN_INT (shift - start - size);
3017 operands[1] = GEN_INT (start + size - 1 - shift);
3018 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3020 [(set_attr "type" "insert_word")])
3022 (define_insn "*insvsi_internal2"
3023 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3024 (match_operand:SI 1 "const_int_operand" "i")
3025 (match_operand:SI 2 "const_int_operand" "i"))
3026 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3027 (match_operand:SI 4 "const_int_operand" "i")))]
3028 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3031 int shift = INTVAL (operands[4]) & 31;
3032 int start = INTVAL (operands[2]) & 31;
3033 int size = INTVAL (operands[1]) & 31;
3035 operands[4] = GEN_INT (32 - shift - start - size);
3036 operands[1] = GEN_INT (start + size - 1);
3037 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3039 [(set_attr "type" "insert_word")])
3041 (define_insn "*insvsi_internal3"
3042 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3043 (match_operand:SI 1 "const_int_operand" "i")
3044 (match_operand:SI 2 "const_int_operand" "i"))
3045 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3046 (match_operand:SI 4 "const_int_operand" "i")))]
3047 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3050 int shift = INTVAL (operands[4]) & 31;
3051 int start = INTVAL (operands[2]) & 31;
3052 int size = INTVAL (operands[1]) & 31;
3054 operands[4] = GEN_INT (32 - shift - start - size);
3055 operands[1] = GEN_INT (start + size - 1);
3056 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3058 [(set_attr "type" "insert_word")])
3060 (define_insn "*insvsi_internal4"
3061 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3062 (match_operand:SI 1 "const_int_operand" "i")
3063 (match_operand:SI 2 "const_int_operand" "i"))
3064 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3065 (match_operand:SI 4 "const_int_operand" "i")
3066 (match_operand:SI 5 "const_int_operand" "i")))]
3067 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3070 int extract_start = INTVAL (operands[5]) & 31;
3071 int extract_size = INTVAL (operands[4]) & 31;
3072 int insert_start = INTVAL (operands[2]) & 31;
3073 int insert_size = INTVAL (operands[1]) & 31;
3075 /* Align extract field with insert field */
3076 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3077 operands[1] = GEN_INT (insert_start + insert_size - 1);
3078 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3080 [(set_attr "type" "insert_word")])
3082 ;; combine patterns for rlwimi
3083 (define_insn "*insvsi_internal5"
3084 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3085 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3086 (match_operand:SI 1 "mask_operand" "i"))
3087 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3088 (match_operand:SI 2 "const_int_operand" "i"))
3089 (match_operand:SI 5 "mask_operand" "i"))))]
3090 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3093 int me = extract_ME(operands[5]);
3094 int mb = extract_MB(operands[5]);
3095 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3096 operands[2] = GEN_INT(mb);
3097 operands[1] = GEN_INT(me);
3098 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3100 [(set_attr "type" "insert_word")])
3102 (define_insn "*insvsi_internal6"
3103 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3104 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3105 (match_operand:SI 2 "const_int_operand" "i"))
3106 (match_operand:SI 5 "mask_operand" "i"))
3107 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3108 (match_operand:SI 1 "mask_operand" "i"))))]
3109 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3112 int me = extract_ME(operands[5]);
3113 int mb = extract_MB(operands[5]);
3114 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3115 operands[2] = GEN_INT(mb);
3116 operands[1] = GEN_INT(me);
3117 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3119 [(set_attr "type" "insert_word")])
3121 (define_insn "insvdi"
3122 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3123 (match_operand:SI 1 "const_int_operand" "i")
3124 (match_operand:SI 2 "const_int_operand" "i"))
3125 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3129 int start = INTVAL (operands[2]) & 63;
3130 int size = INTVAL (operands[1]) & 63;
3132 operands[1] = GEN_INT (64 - start - size);
3133 return \"rldimi %0,%3,%H1,%H2\";
3136 (define_insn "*insvdi_internal2"
3137 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3138 (match_operand:SI 1 "const_int_operand" "i")
3139 (match_operand:SI 2 "const_int_operand" "i"))
3140 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3141 (match_operand:SI 4 "const_int_operand" "i")))]
3143 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3146 int shift = INTVAL (operands[4]) & 63;
3147 int start = (INTVAL (operands[2]) & 63) - 32;
3148 int size = INTVAL (operands[1]) & 63;
3150 operands[4] = GEN_INT (64 - shift - start - size);
3151 operands[2] = GEN_INT (start);
3152 operands[1] = GEN_INT (start + size - 1);
3153 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3156 (define_insn "*insvdi_internal3"
3157 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3158 (match_operand:SI 1 "const_int_operand" "i")
3159 (match_operand:SI 2 "const_int_operand" "i"))
3160 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3161 (match_operand:SI 4 "const_int_operand" "i")))]
3163 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3166 int shift = INTVAL (operands[4]) & 63;
3167 int start = (INTVAL (operands[2]) & 63) - 32;
3168 int size = INTVAL (operands[1]) & 63;
3170 operands[4] = GEN_INT (64 - shift - start - size);
3171 operands[2] = GEN_INT (start);
3172 operands[1] = GEN_INT (start + size - 1);
3173 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3176 (define_expand "extzv"
3177 [(set (match_operand 0 "gpc_reg_operand" "")
3178 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3179 (match_operand:SI 2 "const_int_operand" "")
3180 (match_operand:SI 3 "const_int_operand" "")))]
3184 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3185 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3186 compiler if the address of the structure is taken later. */
3187 if (GET_CODE (operands[0]) == SUBREG
3188 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3191 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3192 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3194 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3198 (define_insn "extzvsi"
3199 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3200 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3201 (match_operand:SI 2 "const_int_operand" "i")
3202 (match_operand:SI 3 "const_int_operand" "i")))]
3206 int start = INTVAL (operands[3]) & 31;
3207 int size = INTVAL (operands[2]) & 31;
3209 if (start + size >= 32)
3210 operands[3] = const0_rtx;
3212 operands[3] = GEN_INT (start + size);
3213 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3216 (define_insn "*extzvsi_internal1"
3217 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3218 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3219 (match_operand:SI 2 "const_int_operand" "i,i")
3220 (match_operand:SI 3 "const_int_operand" "i,i"))
3222 (clobber (match_scratch:SI 4 "=r,r"))]
3226 int start = INTVAL (operands[3]) & 31;
3227 int size = INTVAL (operands[2]) & 31;
3229 /* Force split for non-cc0 compare. */
3230 if (which_alternative == 1)
3233 /* If the bit-field being tested fits in the upper or lower half of a
3234 word, it is possible to use andiu. or andil. to test it. This is
3235 useful because the condition register set-use delay is smaller for
3236 andi[ul]. than for rlinm. This doesn't work when the starting bit
3237 position is 0 because the LT and GT bits may be set wrong. */
3239 if ((start > 0 && start + size <= 16) || start >= 16)
3241 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3242 - (1 << (16 - (start & 15) - size))));
3244 return \"{andiu.|andis.} %4,%1,%3\";
3246 return \"{andil.|andi.} %4,%1,%3\";
3249 if (start + size >= 32)
3250 operands[3] = const0_rtx;
3252 operands[3] = GEN_INT (start + size);
3253 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3255 [(set_attr "type" "compare")
3256 (set_attr "length" "4,8")])
3259 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3260 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3261 (match_operand:SI 2 "const_int_operand" "")
3262 (match_operand:SI 3 "const_int_operand" ""))
3264 (clobber (match_scratch:SI 4 ""))]
3267 (zero_extract:SI (match_dup 1) (match_dup 2)
3270 (compare:CC (match_dup 4)
3274 (define_insn "*extzvsi_internal2"
3275 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3276 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3277 (match_operand:SI 2 "const_int_operand" "i,i")
3278 (match_operand:SI 3 "const_int_operand" "i,i"))
3280 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3281 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3285 int start = INTVAL (operands[3]) & 31;
3286 int size = INTVAL (operands[2]) & 31;
3288 /* Force split for non-cc0 compare. */
3289 if (which_alternative == 1)
3292 /* Since we are using the output value, we can't ignore any need for
3293 a shift. The bit-field must end at the LSB. */
3294 if (start >= 16 && start + size == 32)
3296 operands[3] = GEN_INT ((1 << size) - 1);
3297 return \"{andil.|andi.} %0,%1,%3\";
3300 if (start + size >= 32)
3301 operands[3] = const0_rtx;
3303 operands[3] = GEN_INT (start + size);
3304 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3306 [(set_attr "type" "compare")
3307 (set_attr "length" "4,8")])
3310 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3311 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3312 (match_operand:SI 2 "const_int_operand" "")
3313 (match_operand:SI 3 "const_int_operand" ""))
3315 (set (match_operand:SI 0 "gpc_reg_operand" "")
3316 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3319 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3321 (compare:CC (match_dup 0)
3325 (define_insn "extzvdi"
3326 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3327 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3328 (match_operand:SI 2 "const_int_operand" "i")
3329 (match_operand:SI 3 "const_int_operand" "i")))]
3333 int start = INTVAL (operands[3]) & 63;
3334 int size = INTVAL (operands[2]) & 63;
3336 if (start + size >= 64)
3337 operands[3] = const0_rtx;
3339 operands[3] = GEN_INT (start + size);
3340 operands[2] = GEN_INT (64 - size);
3341 return \"rldicl %0,%1,%3,%2\";
3344 (define_insn "*extzvdi_internal1"
3345 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3346 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3347 (match_operand:SI 2 "const_int_operand" "i")
3348 (match_operand:SI 3 "const_int_operand" "i"))
3350 (clobber (match_scratch:DI 4 "=r"))]
3354 int start = INTVAL (operands[3]) & 63;
3355 int size = INTVAL (operands[2]) & 63;
3357 if (start + size >= 64)
3358 operands[3] = const0_rtx;
3360 operands[3] = GEN_INT (start + size);
3361 operands[2] = GEN_INT (64 - size);
3362 return \"rldicl. %4,%1,%3,%2\";
3364 [(set_attr "type" "compare")])
3366 (define_insn "*extzvdi_internal2"
3367 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3368 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3369 (match_operand:SI 2 "const_int_operand" "i")
3370 (match_operand:SI 3 "const_int_operand" "i"))
3372 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3373 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3377 int start = INTVAL (operands[3]) & 63;
3378 int size = INTVAL (operands[2]) & 63;
3380 if (start + size >= 64)
3381 operands[3] = const0_rtx;
3383 operands[3] = GEN_INT (start + size);
3384 operands[2] = GEN_INT (64 - size);
3385 return \"rldicl. %0,%1,%3,%2\";
3387 [(set_attr "type" "compare")])
3389 (define_insn "rotlsi3"
3390 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3391 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3392 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3394 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3396 (define_insn "*rotlsi3_internal2"
3397 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3398 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3399 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3401 (clobber (match_scratch:SI 3 "=r,r"))]
3404 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3406 [(set_attr "type" "delayed_compare")
3407 (set_attr "length" "4,8")])
3410 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3411 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3412 (match_operand:SI 2 "reg_or_cint_operand" ""))
3414 (clobber (match_scratch:SI 3 ""))]
3417 (rotate:SI (match_dup 1) (match_dup 2)))
3419 (compare:CC (match_dup 3)
3423 (define_insn "*rotlsi3_internal3"
3424 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3425 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3426 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3428 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3429 (rotate:SI (match_dup 1) (match_dup 2)))]
3432 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3434 [(set_attr "type" "delayed_compare")
3435 (set_attr "length" "4,8")])
3438 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3439 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3440 (match_operand:SI 2 "reg_or_cint_operand" ""))
3442 (set (match_operand:SI 0 "gpc_reg_operand" "")
3443 (rotate:SI (match_dup 1) (match_dup 2)))]
3446 (rotate:SI (match_dup 1) (match_dup 2)))
3448 (compare:CC (match_dup 0)
3452 (define_insn "*rotlsi3_internal4"
3453 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3454 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3455 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3456 (match_operand:SI 3 "mask_operand" "n")))]
3458 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3460 (define_insn "*rotlsi3_internal5"
3461 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3463 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3464 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3465 (match_operand:SI 3 "mask_operand" "n,n"))
3467 (clobber (match_scratch:SI 4 "=r,r"))]
3470 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3472 [(set_attr "type" "delayed_compare")
3473 (set_attr "length" "4,8")])
3476 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3478 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3479 (match_operand:SI 2 "reg_or_cint_operand" ""))
3480 (match_operand:SI 3 "mask_operand" ""))
3482 (clobber (match_scratch:SI 4 ""))]
3485 (and:SI (rotate:SI (match_dup 1)
3489 (compare:CC (match_dup 4)
3493 (define_insn "*rotlsi3_internal6"
3494 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3496 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3497 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3498 (match_operand:SI 3 "mask_operand" "n,n"))
3500 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3501 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3504 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3506 [(set_attr "type" "delayed_compare")
3507 (set_attr "length" "4,8")])
3510 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3512 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3513 (match_operand:SI 2 "reg_or_cint_operand" ""))
3514 (match_operand:SI 3 "mask_operand" ""))
3516 (set (match_operand:SI 0 "gpc_reg_operand" "")
3517 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3520 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3522 (compare:CC (match_dup 0)
3526 (define_insn "*rotlsi3_internal7"
3527 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3530 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3531 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3533 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3535 (define_insn "*rotlsi3_internal8"
3536 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3537 (compare:CC (zero_extend:SI
3539 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3540 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3542 (clobber (match_scratch:SI 3 "=r,r"))]
3545 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3547 [(set_attr "type" "delayed_compare")
3548 (set_attr "length" "4,8")])
3551 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3552 (compare:CC (zero_extend:SI
3554 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3555 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3557 (clobber (match_scratch:SI 3 ""))]
3560 (zero_extend:SI (subreg:QI
3561 (rotate:SI (match_dup 1)
3564 (compare:CC (match_dup 3)
3568 (define_insn "*rotlsi3_internal9"
3569 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3570 (compare:CC (zero_extend:SI
3572 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3573 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3575 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3576 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3579 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3581 [(set_attr "type" "delayed_compare")
3582 (set_attr "length" "4,8")])
3585 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3586 (compare:CC (zero_extend:SI
3588 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3589 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3591 (set (match_operand:SI 0 "gpc_reg_operand" "")
3592 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3595 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3597 (compare:CC (match_dup 0)
3601 (define_insn "*rotlsi3_internal10"
3602 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3605 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3606 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3608 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3610 (define_insn "*rotlsi3_internal11"
3611 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3612 (compare:CC (zero_extend:SI
3614 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3615 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3617 (clobber (match_scratch:SI 3 "=r,r"))]
3620 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3622 [(set_attr "type" "delayed_compare")
3623 (set_attr "length" "4,8")])
3626 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3627 (compare:CC (zero_extend:SI
3629 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3630 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3632 (clobber (match_scratch:SI 3 ""))]
3635 (zero_extend:SI (subreg:HI
3636 (rotate:SI (match_dup 1)
3639 (compare:CC (match_dup 3)
3643 (define_insn "*rotlsi3_internal12"
3644 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3645 (compare:CC (zero_extend:SI
3647 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3648 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3650 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3651 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3654 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3656 [(set_attr "type" "delayed_compare")
3657 (set_attr "length" "4,8")])
3660 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3661 (compare:CC (zero_extend:SI
3663 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3664 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3666 (set (match_operand:SI 0 "gpc_reg_operand" "")
3667 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3670 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3672 (compare:CC (match_dup 0)
3676 ;; Note that we use "sle." instead of "sl." so that we can set
3677 ;; SHIFT_COUNT_TRUNCATED.
3679 (define_expand "ashlsi3"
3680 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3681 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3682 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3687 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3689 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3693 (define_insn "ashlsi3_power"
3694 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3695 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3696 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3697 (clobber (match_scratch:SI 3 "=q,X"))]
3701 {sli|slwi} %0,%1,%h2")
3703 (define_insn "ashlsi3_no_power"
3704 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3705 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3706 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3708 "{sl|slw}%I2 %0,%1,%h2")
3711 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3712 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3713 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3715 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3716 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3720 {sli.|slwi.} %3,%1,%h2
3723 [(set_attr "type" "delayed_compare")
3724 (set_attr "length" "4,4,8,8")])
3727 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3728 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3729 (match_operand:SI 2 "reg_or_cint_operand" ""))
3731 (clobber (match_scratch:SI 3 ""))
3732 (clobber (match_scratch:SI 4 ""))]
3733 "TARGET_POWER && reload_completed"
3734 [(parallel [(set (match_dup 3)
3735 (ashift:SI (match_dup 1) (match_dup 2)))
3736 (clobber (match_dup 4))])
3738 (compare:CC (match_dup 3)
3743 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3744 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3745 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3747 (clobber (match_scratch:SI 3 "=r,r"))]
3748 "! TARGET_POWER && TARGET_32BIT"
3750 {sl|slw}%I2. %3,%1,%h2
3752 [(set_attr "type" "delayed_compare")
3753 (set_attr "length" "4,8")])
3756 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3757 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3758 (match_operand:SI 2 "reg_or_cint_operand" ""))
3760 (clobber (match_scratch:SI 3 ""))]
3761 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3763 (ashift:SI (match_dup 1) (match_dup 2)))
3765 (compare:CC (match_dup 3)
3770 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3771 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3772 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3774 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3775 (ashift:SI (match_dup 1) (match_dup 2)))
3776 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3780 {sli.|slwi.} %0,%1,%h2
3783 [(set_attr "type" "delayed_compare")
3784 (set_attr "length" "4,4,8,8")])
3787 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3788 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3789 (match_operand:SI 2 "reg_or_cint_operand" ""))
3791 (set (match_operand:SI 0 "gpc_reg_operand" "")
3792 (ashift:SI (match_dup 1) (match_dup 2)))
3793 (clobber (match_scratch:SI 4 ""))]
3794 "TARGET_POWER && reload_completed"
3795 [(parallel [(set (match_dup 0)
3796 (ashift:SI (match_dup 1) (match_dup 2)))
3797 (clobber (match_dup 4))])
3799 (compare:CC (match_dup 0)
3804 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3805 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3806 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3808 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3809 (ashift:SI (match_dup 1) (match_dup 2)))]
3810 "! TARGET_POWER && TARGET_32BIT"
3812 {sl|slw}%I2. %0,%1,%h2
3814 [(set_attr "type" "delayed_compare")
3815 (set_attr "length" "4,8")])
3818 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3819 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3820 (match_operand:SI 2 "reg_or_cint_operand" ""))
3822 (set (match_operand:SI 0 "gpc_reg_operand" "")
3823 (ashift:SI (match_dup 1) (match_dup 2)))]
3824 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3826 (ashift:SI (match_dup 1) (match_dup 2)))
3828 (compare:CC (match_dup 0)
3832 (define_insn "rlwinm"
3833 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3834 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3835 (match_operand:SI 2 "const_int_operand" "i"))
3836 (match_operand:SI 3 "mask_operand" "n")))]
3837 "includes_lshift_p (operands[2], operands[3])"
3838 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3841 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3843 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3844 (match_operand:SI 2 "const_int_operand" "i,i"))
3845 (match_operand:SI 3 "mask_operand" "n,n"))
3847 (clobber (match_scratch:SI 4 "=r,r"))]
3848 "includes_lshift_p (operands[2], operands[3])"
3850 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3852 [(set_attr "type" "delayed_compare")
3853 (set_attr "length" "4,8")])
3856 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3858 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3859 (match_operand:SI 2 "const_int_operand" ""))
3860 (match_operand:SI 3 "mask_operand" ""))
3862 (clobber (match_scratch:SI 4 ""))]
3863 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3865 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3868 (compare:CC (match_dup 4)
3873 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3875 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3876 (match_operand:SI 2 "const_int_operand" "i,i"))
3877 (match_operand:SI 3 "mask_operand" "n,n"))
3879 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3880 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3881 "includes_lshift_p (operands[2], operands[3])"
3883 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3885 [(set_attr "type" "delayed_compare")
3886 (set_attr "length" "4,8")])
3889 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3891 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3892 (match_operand:SI 2 "const_int_operand" ""))
3893 (match_operand:SI 3 "mask_operand" ""))
3895 (set (match_operand:SI 0 "gpc_reg_operand" "")
3896 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3897 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3899 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3901 (compare:CC (match_dup 0)
3905 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3907 (define_expand "lshrsi3"
3908 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3909 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3910 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3915 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3917 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3921 (define_insn "lshrsi3_power"
3922 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3923 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3924 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3925 (clobber (match_scratch:SI 3 "=q,X,X"))]
3930 {s%A2i|s%A2wi} %0,%1,%h2")
3932 (define_insn "lshrsi3_no_power"
3933 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3934 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3935 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3939 {sr|srw}%I2 %0,%1,%h2")
3942 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3943 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3944 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3946 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3947 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3952 {s%A2i.|s%A2wi.} %3,%1,%h2
3956 [(set_attr "type" "delayed_compare")
3957 (set_attr "length" "4,4,4,8,8,8")])
3960 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3961 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3962 (match_operand:SI 2 "reg_or_cint_operand" ""))
3964 (clobber (match_scratch:SI 3 ""))
3965 (clobber (match_scratch:SI 4 ""))]
3966 "TARGET_POWER && reload_completed"
3967 [(parallel [(set (match_dup 3)
3968 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3969 (clobber (match_dup 4))])
3971 (compare:CC (match_dup 3)
3976 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3977 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3978 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3980 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3981 "! TARGET_POWER && TARGET_32BIT"
3984 {sr|srw}%I2. %3,%1,%h2
3987 [(set_attr "type" "delayed_compare")
3988 (set_attr "length" "4,4,8,8")])
3991 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3992 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3993 (match_operand:SI 2 "reg_or_cint_operand" ""))
3995 (clobber (match_scratch:SI 3 ""))]
3996 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3998 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4000 (compare:CC (match_dup 3)
4005 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4006 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4007 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4009 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4010 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4011 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4016 {s%A2i.|s%A2wi.} %0,%1,%h2
4020 [(set_attr "type" "delayed_compare")
4021 (set_attr "length" "4,4,4,8,8,8")])
4024 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4025 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4026 (match_operand:SI 2 "reg_or_cint_operand" ""))
4028 (set (match_operand:SI 0 "gpc_reg_operand" "")
4029 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4030 (clobber (match_scratch:SI 4 ""))]
4031 "TARGET_POWER && reload_completed"
4032 [(parallel [(set (match_dup 0)
4033 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4034 (clobber (match_dup 4))])
4036 (compare:CC (match_dup 0)
4041 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4042 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4043 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4045 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4046 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4047 "! TARGET_POWER && TARGET_32BIT"
4050 {sr|srw}%I2. %0,%1,%h2
4053 [(set_attr "type" "delayed_compare")
4054 (set_attr "length" "4,4,8,8")])
4057 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4058 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4059 (match_operand:SI 2 "reg_or_cint_operand" ""))
4061 (set (match_operand:SI 0 "gpc_reg_operand" "")
4062 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4063 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4065 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4067 (compare:CC (match_dup 0)
4072 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4073 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4074 (match_operand:SI 2 "const_int_operand" "i"))
4075 (match_operand:SI 3 "mask_operand" "n")))]
4076 "includes_rshift_p (operands[2], operands[3])"
4077 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4080 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4082 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4083 (match_operand:SI 2 "const_int_operand" "i,i"))
4084 (match_operand:SI 3 "mask_operand" "n,n"))
4086 (clobber (match_scratch:SI 4 "=r,r"))]
4087 "includes_rshift_p (operands[2], operands[3])"
4089 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4091 [(set_attr "type" "delayed_compare")
4092 (set_attr "length" "4,8")])
4095 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4097 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4098 (match_operand:SI 2 "const_int_operand" ""))
4099 (match_operand:SI 3 "mask_operand" ""))
4101 (clobber (match_scratch:SI 4 ""))]
4102 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4104 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4107 (compare:CC (match_dup 4)
4112 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4114 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4115 (match_operand:SI 2 "const_int_operand" "i,i"))
4116 (match_operand:SI 3 "mask_operand" "n,n"))
4118 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4119 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4120 "includes_rshift_p (operands[2], operands[3])"
4122 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4124 [(set_attr "type" "delayed_compare")
4125 (set_attr "length" "4,8")])
4128 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4130 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4131 (match_operand:SI 2 "const_int_operand" ""))
4132 (match_operand:SI 3 "mask_operand" ""))
4134 (set (match_operand:SI 0 "gpc_reg_operand" "")
4135 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4136 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4138 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4140 (compare:CC (match_dup 0)
4145 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4148 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4149 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4150 "includes_rshift_p (operands[2], GEN_INT (255))"
4151 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4154 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4158 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4159 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4161 (clobber (match_scratch:SI 3 "=r,r"))]
4162 "includes_rshift_p (operands[2], GEN_INT (255))"
4164 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4166 [(set_attr "type" "delayed_compare")
4167 (set_attr "length" "4,8")])
4170 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4174 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4175 (match_operand:SI 2 "const_int_operand" "")) 0))
4177 (clobber (match_scratch:SI 3 ""))]
4178 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4180 (zero_extend:SI (subreg:QI
4181 (lshiftrt:SI (match_dup 1)
4184 (compare:CC (match_dup 3)
4189 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4193 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4194 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4196 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4197 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4198 "includes_rshift_p (operands[2], GEN_INT (255))"
4200 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4202 [(set_attr "type" "delayed_compare")
4203 (set_attr "length" "4,8")])
4206 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4210 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4211 (match_operand:SI 2 "const_int_operand" "")) 0))
4213 (set (match_operand:SI 0 "gpc_reg_operand" "")
4214 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4215 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4217 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4219 (compare:CC (match_dup 0)
4224 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4227 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4228 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4229 "includes_rshift_p (operands[2], GEN_INT (65535))"
4230 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4233 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4237 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4238 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4240 (clobber (match_scratch:SI 3 "=r,r"))]
4241 "includes_rshift_p (operands[2], GEN_INT (65535))"
4243 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4245 [(set_attr "type" "delayed_compare")
4246 (set_attr "length" "4,8")])
4249 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4253 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4254 (match_operand:SI 2 "const_int_operand" "")) 0))
4256 (clobber (match_scratch:SI 3 ""))]
4257 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4259 (zero_extend:SI (subreg:HI
4260 (lshiftrt:SI (match_dup 1)
4263 (compare:CC (match_dup 3)
4268 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4272 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4273 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4275 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4276 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4277 "includes_rshift_p (operands[2], GEN_INT (65535))"
4279 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4281 [(set_attr "type" "delayed_compare")
4282 (set_attr "length" "4,8")])
4285 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4289 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4290 (match_operand:SI 2 "const_int_operand" "")) 0))
4292 (set (match_operand:SI 0 "gpc_reg_operand" "")
4293 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4294 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4296 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4298 (compare:CC (match_dup 0)
4303 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4305 (match_operand:SI 1 "gpc_reg_operand" "r"))
4306 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4312 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4314 (match_operand:SI 1 "gpc_reg_operand" "r"))
4315 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4321 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4323 (match_operand:SI 1 "gpc_reg_operand" "r"))
4324 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4330 (define_expand "ashrsi3"
4331 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4332 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4333 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4338 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4340 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4344 (define_insn "ashrsi3_power"
4345 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4346 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4347 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4348 (clobber (match_scratch:SI 3 "=q,X"))]
4352 {srai|srawi} %0,%1,%h2")
4354 (define_insn "ashrsi3_no_power"
4355 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4356 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4357 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4359 "{sra|sraw}%I2 %0,%1,%h2")
4362 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4363 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4364 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4366 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4367 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4371 {srai.|srawi.} %3,%1,%h2
4374 [(set_attr "type" "delayed_compare")
4375 (set_attr "length" "4,4,8,8")])
4378 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4379 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4380 (match_operand:SI 2 "reg_or_cint_operand" ""))
4382 (clobber (match_scratch:SI 3 ""))
4383 (clobber (match_scratch:SI 4 ""))]
4384 "TARGET_POWER && reload_completed"
4385 [(parallel [(set (match_dup 3)
4386 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4387 (clobber (match_dup 4))])
4389 (compare:CC (match_dup 3)
4394 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4395 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4396 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4398 (clobber (match_scratch:SI 3 "=r,r"))]
4401 {sra|sraw}%I2. %3,%1,%h2
4403 [(set_attr "type" "delayed_compare")
4404 (set_attr "length" "4,8")])
4407 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4408 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4409 (match_operand:SI 2 "reg_or_cint_operand" ""))
4411 (clobber (match_scratch:SI 3 ""))]
4412 "! TARGET_POWER && reload_completed"
4414 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4416 (compare:CC (match_dup 3)
4421 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4422 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4423 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4425 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4426 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4427 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4431 {srai.|srawi.} %0,%1,%h2
4434 [(set_attr "type" "delayed_compare")
4435 (set_attr "length" "4,4,8,8")])
4438 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4439 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4440 (match_operand:SI 2 "reg_or_cint_operand" ""))
4442 (set (match_operand:SI 0 "gpc_reg_operand" "")
4443 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4444 (clobber (match_scratch:SI 4 ""))]
4445 "TARGET_POWER && reload_completed"
4446 [(parallel [(set (match_dup 0)
4447 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4448 (clobber (match_dup 4))])
4450 (compare:CC (match_dup 0)
4455 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4456 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4457 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4459 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4460 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4463 {sra|sraw}%I2. %0,%1,%h2
4465 [(set_attr "type" "delayed_compare")
4466 (set_attr "length" "4,8")])
4469 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4470 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4471 (match_operand:SI 2 "reg_or_cint_operand" ""))
4473 (set (match_operand:SI 0 "gpc_reg_operand" "")
4474 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4475 "! TARGET_POWER && reload_completed"
4477 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4479 (compare:CC (match_dup 0)
4483 ;; Floating-point insns, excluding normal data motion.
4485 ;; PowerPC has a full set of single-precision floating point instructions.
4487 ;; For the POWER architecture, we pretend that we have both SFmode and
4488 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4489 ;; The only conversions we will do will be when storing to memory. In that
4490 ;; case, we will use the "frsp" instruction before storing.
4492 ;; Note that when we store into a single-precision memory location, we need to
4493 ;; use the frsp insn first. If the register being stored isn't dead, we
4494 ;; need a scratch register for the frsp. But this is difficult when the store
4495 ;; is done by reload. It is not incorrect to do the frsp on the register in
4496 ;; this case, we just lose precision that we would have otherwise gotten but
4497 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4499 (define_expand "extendsfdf2"
4500 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4501 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4502 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4505 (define_insn_and_split "*extendsfdf2_fpr"
4506 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4507 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4508 "TARGET_HARD_FLOAT && TARGET_FPRS"
4513 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4516 emit_note (NOTE_INSN_DELETED);
4519 [(set_attr "type" "fp,fp,fpload")])
4521 (define_expand "truncdfsf2"
4522 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4523 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4524 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4527 (define_insn "*truncdfsf2_fpr"
4528 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4529 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4530 "TARGET_HARD_FLOAT && TARGET_FPRS"
4532 [(set_attr "type" "fp")])
4534 (define_insn "aux_truncdfsf2"
4535 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4536 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4537 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4539 [(set_attr "type" "fp")])
4541 (define_expand "negsf2"
4542 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4543 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4547 (define_insn "*negsf2"
4548 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4549 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4550 "TARGET_HARD_FLOAT && TARGET_FPRS"
4552 [(set_attr "type" "fp")])
4554 (define_expand "abssf2"
4555 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4556 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4560 (define_insn "*abssf2"
4561 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4562 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4563 "TARGET_HARD_FLOAT && TARGET_FPRS"
4565 [(set_attr "type" "fp")])
4568 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4569 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4570 "TARGET_HARD_FLOAT && TARGET_FPRS"
4572 [(set_attr "type" "fp")])
4574 (define_expand "addsf3"
4575 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4576 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4577 (match_operand:SF 2 "gpc_reg_operand" "")))]
4582 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4583 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4584 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4585 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4587 [(set_attr "type" "fp")])
4590 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4591 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4592 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4593 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4594 "{fa|fadd} %0,%1,%2"
4595 [(set_attr "type" "fp")])
4597 (define_expand "subsf3"
4598 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4599 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4600 (match_operand:SF 2 "gpc_reg_operand" "")))]
4605 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4606 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4607 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4608 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4610 [(set_attr "type" "fp")])
4613 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4614 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4615 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4616 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4617 "{fs|fsub} %0,%1,%2"
4618 [(set_attr "type" "fp")])
4620 (define_expand "mulsf3"
4621 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4622 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4623 (match_operand:SF 2 "gpc_reg_operand" "")))]
4628 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4629 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4630 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4631 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4633 [(set_attr "type" "fp")])
4636 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4637 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4638 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4639 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4640 "{fm|fmul} %0,%1,%2"
4641 [(set_attr "type" "dmul")])
4643 (define_expand "divsf3"
4644 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4645 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4646 (match_operand:SF 2 "gpc_reg_operand" "")))]
4651 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4652 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4653 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4654 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4656 [(set_attr "type" "sdiv")])
4659 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4660 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4661 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4662 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4663 "{fd|fdiv} %0,%1,%2"
4664 [(set_attr "type" "ddiv")])
4667 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4668 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4669 (match_operand:SF 2 "gpc_reg_operand" "f"))
4670 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4671 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4672 "fmadds %0,%1,%2,%3"
4673 [(set_attr "type" "fp")])
4676 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4677 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4678 (match_operand:SF 2 "gpc_reg_operand" "f"))
4679 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4680 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4681 "{fma|fmadd} %0,%1,%2,%3"
4682 [(set_attr "type" "dmul")])
4685 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4686 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4687 (match_operand:SF 2 "gpc_reg_operand" "f"))
4688 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4689 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4690 "fmsubs %0,%1,%2,%3"
4691 [(set_attr "type" "fp")])
4694 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4695 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4696 (match_operand:SF 2 "gpc_reg_operand" "f"))
4697 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4698 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4699 "{fms|fmsub} %0,%1,%2,%3"
4700 [(set_attr "type" "dmul")])
4703 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4704 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4705 (match_operand:SF 2 "gpc_reg_operand" "f"))
4706 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4707 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4708 && HONOR_SIGNED_ZEROS (SFmode)"
4709 "fnmadds %0,%1,%2,%3"
4710 [(set_attr "type" "fp")])
4713 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4714 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4715 (match_operand:SF 2 "gpc_reg_operand" "f"))
4716 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4717 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4718 && ! HONOR_SIGNED_ZEROS (SFmode)"
4719 "fnmadds %0,%1,%2,%3"
4720 [(set_attr "type" "fp")])
4723 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4724 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4725 (match_operand:SF 2 "gpc_reg_operand" "f"))
4726 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4727 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4728 "{fnma|fnmadd} %0,%1,%2,%3"
4729 [(set_attr "type" "dmul")])
4732 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4733 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4734 (match_operand:SF 2 "gpc_reg_operand" "f"))
4735 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4736 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4737 && ! HONOR_SIGNED_ZEROS (SFmode)"
4738 "{fnma|fnmadd} %0,%1,%2,%3"
4739 [(set_attr "type" "dmul")])
4742 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4743 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4744 (match_operand:SF 2 "gpc_reg_operand" "f"))
4745 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4746 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4747 && HONOR_SIGNED_ZEROS (SFmode)"
4748 "fnmsubs %0,%1,%2,%3"
4749 [(set_attr "type" "fp")])
4752 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4753 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4754 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4755 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4756 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4757 && ! HONOR_SIGNED_ZEROS (SFmode)"
4758 "fnmsubs %0,%1,%2,%3"
4759 [(set_attr "type" "fp")])
4762 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4763 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4764 (match_operand:SF 2 "gpc_reg_operand" "f"))
4765 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4766 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4767 "{fnms|fnmsub} %0,%1,%2,%3"
4768 [(set_attr "type" "dmul")])
4771 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4772 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4773 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4774 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4775 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4776 && ! HONOR_SIGNED_ZEROS (SFmode)"
4777 "{fnms|fnmsub} %0,%1,%2,%3"
4778 [(set_attr "type" "fp")])
4780 (define_expand "sqrtsf2"
4781 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4782 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4783 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4787 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4788 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4789 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4791 [(set_attr "type" "ssqrt")])
4794 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4795 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4796 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4798 [(set_attr "type" "dsqrt")])
4800 (define_expand "copysignsf3"
4802 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
4804 (neg:SF (abs:SF (match_dup 1))))
4805 (set (match_operand:SF 0 "gpc_reg_operand" "")
4806 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
4810 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4811 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
4813 operands[3] = gen_reg_rtx (SFmode);
4814 operands[4] = gen_reg_rtx (SFmode);
4815 operands[5] = CONST0_RTX (SFmode);
4818 (define_expand "copysigndf3"
4820 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
4822 (neg:DF (abs:DF (match_dup 1))))
4823 (set (match_operand:DF 0 "gpc_reg_operand" "")
4824 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
4828 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4829 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
4831 operands[3] = gen_reg_rtx (DFmode);
4832 operands[4] = gen_reg_rtx (DFmode);
4833 operands[5] = CONST0_RTX (DFmode);
4836 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4837 ;; fsel instruction and some auxiliary computations. Then we just have a
4838 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4840 (define_expand "smaxsf3"
4841 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4842 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4843 (match_operand:SF 2 "gpc_reg_operand" ""))
4846 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4847 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4849 (define_expand "sminsf3"
4850 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4851 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4852 (match_operand:SF 2 "gpc_reg_operand" ""))
4855 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4856 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4859 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4860 (match_operator:SF 3 "min_max_operator"
4861 [(match_operand:SF 1 "gpc_reg_operand" "")
4862 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4863 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4866 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4867 operands[1], operands[2]);
4871 (define_expand "movsicc"
4872 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4873 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4874 (match_operand:SI 2 "gpc_reg_operand" "")
4875 (match_operand:SI 3 "gpc_reg_operand" "")))]
4879 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4885 ;; We use the BASE_REGS for the isel input operands because, if rA is
4886 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4887 ;; because we may switch the operands and rB may end up being rA.
4889 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4890 ;; leave out the mode in operand 4 and use one pattern, but reload can
4891 ;; change the mode underneath our feet and then gets confused trying
4892 ;; to reload the value.
4893 (define_insn "isel_signed"
4894 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4896 (match_operator 1 "comparison_operator"
4897 [(match_operand:CC 4 "cc_reg_operand" "y")
4899 (match_operand:SI 2 "gpc_reg_operand" "b")
4900 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4903 { return output_isel (operands); }"
4904 [(set_attr "length" "4")])
4906 (define_insn "isel_unsigned"
4907 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4909 (match_operator 1 "comparison_operator"
4910 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4912 (match_operand:SI 2 "gpc_reg_operand" "b")
4913 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4916 { return output_isel (operands); }"
4917 [(set_attr "length" "4")])
4919 (define_expand "movsfcc"
4920 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4921 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4922 (match_operand:SF 2 "gpc_reg_operand" "")
4923 (match_operand:SF 3 "gpc_reg_operand" "")))]
4924 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4927 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4933 (define_insn "*fselsfsf4"
4934 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4935 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4936 (match_operand:SF 4 "zero_fp_constant" "F"))
4937 (match_operand:SF 2 "gpc_reg_operand" "f")
4938 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4939 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4941 [(set_attr "type" "fp")])
4943 (define_insn "*fseldfsf4"
4944 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4945 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4946 (match_operand:DF 4 "zero_fp_constant" "F"))
4947 (match_operand:SF 2 "gpc_reg_operand" "f")
4948 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4949 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4951 [(set_attr "type" "fp")])
4953 (define_expand "negdf2"
4954 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4955 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4956 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4959 (define_insn "*negdf2_fpr"
4960 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4961 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4962 "TARGET_HARD_FLOAT && TARGET_FPRS"
4964 [(set_attr "type" "fp")])
4966 (define_expand "absdf2"
4967 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4968 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4969 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4972 (define_insn "*absdf2_fpr"
4973 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4974 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4975 "TARGET_HARD_FLOAT && TARGET_FPRS"
4977 [(set_attr "type" "fp")])
4979 (define_insn "*nabsdf2_fpr"
4980 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4981 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4982 "TARGET_HARD_FLOAT && TARGET_FPRS"
4984 [(set_attr "type" "fp")])
4986 (define_expand "adddf3"
4987 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4988 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4989 (match_operand:DF 2 "gpc_reg_operand" "")))]
4990 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4993 (define_insn "*adddf3_fpr"
4994 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4995 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4996 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4997 "TARGET_HARD_FLOAT && TARGET_FPRS"
4998 "{fa|fadd} %0,%1,%2"
4999 [(set_attr "type" "fp")])
5001 (define_expand "subdf3"
5002 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5003 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5004 (match_operand:DF 2 "gpc_reg_operand" "")))]
5005 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5008 (define_insn "*subdf3_fpr"
5009 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5010 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5011 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5012 "TARGET_HARD_FLOAT && TARGET_FPRS"
5013 "{fs|fsub} %0,%1,%2"
5014 [(set_attr "type" "fp")])
5016 (define_expand "muldf3"
5017 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5018 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5019 (match_operand:DF 2 "gpc_reg_operand" "")))]
5020 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5023 (define_insn "*muldf3_fpr"
5024 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5025 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5026 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5027 "TARGET_HARD_FLOAT && TARGET_FPRS"
5028 "{fm|fmul} %0,%1,%2"
5029 [(set_attr "type" "dmul")])
5031 (define_expand "divdf3"
5032 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5033 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5034 (match_operand:DF 2 "gpc_reg_operand" "")))]
5035 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5038 (define_insn "*divdf3_fpr"
5039 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5040 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5041 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5042 "TARGET_HARD_FLOAT && TARGET_FPRS"
5043 "{fd|fdiv} %0,%1,%2"
5044 [(set_attr "type" "ddiv")])
5047 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5048 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5049 (match_operand:DF 2 "gpc_reg_operand" "f"))
5050 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5051 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5052 "{fma|fmadd} %0,%1,%2,%3"
5053 [(set_attr "type" "dmul")])
5056 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5057 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5058 (match_operand:DF 2 "gpc_reg_operand" "f"))
5059 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5060 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5061 "{fms|fmsub} %0,%1,%2,%3"
5062 [(set_attr "type" "dmul")])
5065 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5066 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5067 (match_operand:DF 2 "gpc_reg_operand" "f"))
5068 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5069 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5070 && HONOR_SIGNED_ZEROS (DFmode)"
5071 "{fnma|fnmadd} %0,%1,%2,%3"
5072 [(set_attr "type" "dmul")])
5075 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5076 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5077 (match_operand:DF 2 "gpc_reg_operand" "f"))
5078 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5079 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5080 && ! HONOR_SIGNED_ZEROS (DFmode)"
5081 "{fnma|fnmadd} %0,%1,%2,%3"
5082 [(set_attr "type" "dmul")])
5085 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5086 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5087 (match_operand:DF 2 "gpc_reg_operand" "f"))
5088 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5089 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5090 && HONOR_SIGNED_ZEROS (DFmode)"
5091 "{fnms|fnmsub} %0,%1,%2,%3"
5092 [(set_attr "type" "dmul")])
5095 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5096 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5097 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5098 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5099 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5100 && ! HONOR_SIGNED_ZEROS (DFmode)"
5101 "{fnms|fnmsub} %0,%1,%2,%3"
5102 [(set_attr "type" "dmul")])
5104 (define_insn "sqrtdf2"
5105 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5106 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5107 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5109 [(set_attr "type" "dsqrt")])
5111 ;; The conditional move instructions allow us to perform max and min
5112 ;; operations even when
5114 (define_expand "smaxdf3"
5115 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5116 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5117 (match_operand:DF 2 "gpc_reg_operand" ""))
5120 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5121 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5123 (define_expand "smindf3"
5124 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5125 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5126 (match_operand:DF 2 "gpc_reg_operand" ""))
5129 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5130 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5133 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5134 (match_operator:DF 3 "min_max_operator"
5135 [(match_operand:DF 1 "gpc_reg_operand" "")
5136 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5137 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5140 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5141 operands[1], operands[2]);
5145 (define_expand "movdfcc"
5146 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5147 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5148 (match_operand:DF 2 "gpc_reg_operand" "")
5149 (match_operand:DF 3 "gpc_reg_operand" "")))]
5150 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5153 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5159 (define_insn "*fseldfdf4"
5160 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5161 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5162 (match_operand:DF 4 "zero_fp_constant" "F"))
5163 (match_operand:DF 2 "gpc_reg_operand" "f")
5164 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5165 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5167 [(set_attr "type" "fp")])
5169 (define_insn "*fselsfdf4"
5170 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5171 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5172 (match_operand:SF 4 "zero_fp_constant" "F"))
5173 (match_operand:DF 2 "gpc_reg_operand" "f")
5174 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5177 [(set_attr "type" "fp")])
5179 ;; Conversions to and from floating-point.
5181 (define_expand "fixuns_truncsfsi2"
5182 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5183 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5184 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5187 (define_expand "fix_truncsfsi2"
5188 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5189 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5190 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5193 ; For each of these conversions, there is a define_expand, a define_insn
5194 ; with a '#' template, and a define_split (with C code). The idea is
5195 ; to allow constant folding with the template of the define_insn,
5196 ; then to have the insns split later (between sched1 and final).
5198 (define_expand "floatsidf2"
5199 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5200 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5203 (clobber (match_dup 4))
5204 (clobber (match_dup 5))
5205 (clobber (match_dup 6))])]
5206 "TARGET_HARD_FLOAT && TARGET_FPRS"
5209 if (TARGET_E500_DOUBLE)
5211 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5214 if (TARGET_POWERPC64)
5216 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5217 rtx t1 = gen_reg_rtx (DImode);
5218 rtx t2 = gen_reg_rtx (DImode);
5219 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5223 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5224 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5225 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5226 operands[5] = gen_reg_rtx (DFmode);
5227 operands[6] = gen_reg_rtx (SImode);
5230 (define_insn_and_split "*floatsidf2_internal"
5231 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5232 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5233 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5234 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5235 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5236 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5237 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5238 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5240 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5244 rtx lowword, highword;
5245 gcc_assert (MEM_P (operands[4]));
5246 highword = adjust_address (operands[4], SImode, 0);
5247 lowword = adjust_address (operands[4], SImode, 4);
5248 if (! WORDS_BIG_ENDIAN)
5251 tmp = highword; highword = lowword; lowword = tmp;
5254 emit_insn (gen_xorsi3 (operands[6], operands[1],
5255 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5256 emit_move_insn (lowword, operands[6]);
5257 emit_move_insn (highword, operands[2]);
5258 emit_move_insn (operands[5], operands[4]);
5259 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5262 [(set_attr "length" "24")])
5264 (define_expand "floatunssisf2"
5265 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5266 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5267 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5270 (define_expand "floatunssidf2"
5271 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5272 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5275 (clobber (match_dup 4))
5276 (clobber (match_dup 5))])]
5277 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5280 if (TARGET_E500_DOUBLE)
5282 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5285 if (TARGET_POWERPC64)
5287 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5288 rtx t1 = gen_reg_rtx (DImode);
5289 rtx t2 = gen_reg_rtx (DImode);
5290 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5295 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5296 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5297 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5298 operands[5] = gen_reg_rtx (DFmode);
5301 (define_insn_and_split "*floatunssidf2_internal"
5302 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5303 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5304 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5305 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5306 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5307 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5308 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5310 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5314 rtx lowword, highword;
5315 gcc_assert (MEM_P (operands[4]));
5316 highword = adjust_address (operands[4], SImode, 0);
5317 lowword = adjust_address (operands[4], SImode, 4);
5318 if (! WORDS_BIG_ENDIAN)
5321 tmp = highword; highword = lowword; lowword = tmp;
5324 emit_move_insn (lowword, operands[1]);
5325 emit_move_insn (highword, operands[2]);
5326 emit_move_insn (operands[5], operands[4]);
5327 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5330 [(set_attr "length" "20")])
5332 (define_expand "fix_truncdfsi2"
5333 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5334 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5335 (clobber (match_dup 2))
5336 (clobber (match_dup 3))])]
5337 "(TARGET_POWER2 || TARGET_POWERPC)
5338 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5341 if (TARGET_E500_DOUBLE)
5343 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5346 operands[2] = gen_reg_rtx (DImode);
5347 if (TARGET_PPC_GFXOPT)
5349 rtx orig_dest = operands[0];
5350 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5351 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5352 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5354 if (operands[0] != orig_dest)
5355 emit_move_insn (orig_dest, operands[0]);
5358 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5361 (define_insn_and_split "*fix_truncdfsi2_internal"
5362 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5363 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5364 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5365 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5366 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5368 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5373 gcc_assert (MEM_P (operands[3]));
5374 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5376 emit_insn (gen_fctiwz (operands[2], operands[1]));
5377 emit_move_insn (operands[3], operands[2]);
5378 emit_move_insn (operands[0], lowword);
5381 [(set_attr "length" "16")])
5383 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5384 [(set (match_operand:SI 0 "memory_operand" "=Z")
5385 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5386 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5387 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5388 && TARGET_PPC_GFXOPT"
5394 emit_insn (gen_fctiwz (operands[2], operands[1]));
5395 emit_insn (gen_stfiwx (operands[0], operands[2]));
5398 [(set_attr "length" "16")])
5400 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5401 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5402 ; because the first makes it clear that operand 0 is not live
5403 ; before the instruction.
5404 (define_insn "fctiwz"
5405 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5406 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5408 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5409 "{fcirz|fctiwz} %0,%1"
5410 [(set_attr "type" "fp")])
5412 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5413 (define_insn "stfiwx"
5414 [(set (match_operand:SI 0 "memory_operand" "=Z")
5415 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
5419 [(set_attr "type" "fpstore")])
5421 (define_expand "floatsisf2"
5422 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5423 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5424 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5427 (define_insn "floatdidf2"
5428 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5429 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5430 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5432 [(set_attr "type" "fp")])
5434 (define_insn_and_split "floatsidf_ppc64"
5435 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5436 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5437 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5438 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5439 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5440 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5443 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5444 (set (match_dup 2) (match_dup 3))
5445 (set (match_dup 4) (match_dup 2))
5446 (set (match_dup 0) (float:DF (match_dup 4)))]
5449 (define_insn_and_split "floatunssidf_ppc64"
5450 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5451 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5452 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5453 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5454 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5455 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5458 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5459 (set (match_dup 2) (match_dup 3))
5460 (set (match_dup 4) (match_dup 2))
5461 (set (match_dup 0) (float:DF (match_dup 4)))]
5464 (define_insn "fix_truncdfdi2"
5465 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5466 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5467 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5469 [(set_attr "type" "fp")])
5471 (define_expand "floatdisf2"
5472 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5473 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5474 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5477 rtx val = operands[1];
5478 if (!flag_unsafe_math_optimizations)
5480 rtx label = gen_label_rtx ();
5481 val = gen_reg_rtx (DImode);
5482 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5485 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5489 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5490 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5491 ;; from double rounding.
5492 (define_insn_and_split "floatdisf2_internal1"
5493 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5494 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5495 (clobber (match_scratch:DF 2 "=f"))]
5496 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5498 "&& reload_completed"
5500 (float:DF (match_dup 1)))
5502 (float_truncate:SF (match_dup 2)))]
5505 ;; Twiddles bits to avoid double rounding.
5506 ;; Bits that might be truncated when converting to DFmode are replaced
5507 ;; by a bit that won't be lost at that stage, but is below the SFmode
5508 ;; rounding position.
5509 (define_expand "floatdisf2_internal2"
5510 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5512 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5514 (clobber (scratch:CC))])
5515 (set (match_dup 3) (plus:DI (match_dup 3)
5517 (set (match_dup 0) (plus:DI (match_dup 0)
5519 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5521 (set (match_dup 0) (ior:DI (match_dup 0)
5523 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
5525 (clobber (scratch:CC))])
5526 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5527 (label_ref (match_operand:DI 2 "" ""))
5529 (set (match_dup 0) (match_dup 1))]
5530 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5533 operands[3] = gen_reg_rtx (DImode);
5534 operands[4] = gen_reg_rtx (CCUNSmode);
5537 ;; Define the DImode operations that can be done in a small number
5538 ;; of instructions. The & constraints are to prevent the register
5539 ;; allocator from allocating registers that overlap with the inputs
5540 ;; (for example, having an input in 7,8 and an output in 6,7). We
5541 ;; also allow for the output being the same as one of the inputs.
5543 (define_insn "*adddi3_noppc64"
5544 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5545 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5546 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5547 "! TARGET_POWERPC64"
5550 if (WORDS_BIG_ENDIAN)
5551 return (GET_CODE (operands[2])) != CONST_INT
5552 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5553 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5555 return (GET_CODE (operands[2])) != CONST_INT
5556 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5557 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5559 [(set_attr "type" "two")
5560 (set_attr "length" "8")])
5562 (define_insn "*subdi3_noppc64"
5563 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5564 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5565 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5566 "! TARGET_POWERPC64"
5569 if (WORDS_BIG_ENDIAN)
5570 return (GET_CODE (operands[1]) != CONST_INT)
5571 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5572 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5574 return (GET_CODE (operands[1]) != CONST_INT)
5575 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5576 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5578 [(set_attr "type" "two")
5579 (set_attr "length" "8")])
5581 (define_insn "*negdi2_noppc64"
5582 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5583 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5584 "! TARGET_POWERPC64"
5587 return (WORDS_BIG_ENDIAN)
5588 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5589 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5591 [(set_attr "type" "two")
5592 (set_attr "length" "8")])
5594 (define_expand "mulsidi3"
5595 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5596 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5597 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5598 "! TARGET_POWERPC64"
5601 if (! TARGET_POWER && ! TARGET_POWERPC)
5603 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5604 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5605 emit_insn (gen_mull_call ());
5606 if (WORDS_BIG_ENDIAN)
5607 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5610 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5611 gen_rtx_REG (SImode, 3));
5612 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5613 gen_rtx_REG (SImode, 4));
5617 else if (TARGET_POWER)
5619 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5624 (define_insn "mulsidi3_mq"
5625 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5626 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5627 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5628 (clobber (match_scratch:SI 3 "=q"))]
5630 "mul %0,%1,%2\;mfmq %L0"
5631 [(set_attr "type" "imul")
5632 (set_attr "length" "8")])
5634 (define_insn "*mulsidi3_no_mq"
5635 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5636 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5637 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5638 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5641 return (WORDS_BIG_ENDIAN)
5642 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5643 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5645 [(set_attr "type" "imul")
5646 (set_attr "length" "8")])
5649 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5650 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5651 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5652 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5655 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5656 (sign_extend:DI (match_dup 2)))
5659 (mult:SI (match_dup 1)
5663 int endian = (WORDS_BIG_ENDIAN == 0);
5664 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5665 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5668 (define_expand "umulsidi3"
5669 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5670 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5671 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5672 "TARGET_POWERPC && ! TARGET_POWERPC64"
5677 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5682 (define_insn "umulsidi3_mq"
5683 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5684 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5685 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5686 (clobber (match_scratch:SI 3 "=q"))]
5687 "TARGET_POWERPC && TARGET_POWER"
5690 return (WORDS_BIG_ENDIAN)
5691 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5692 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5694 [(set_attr "type" "imul")
5695 (set_attr "length" "8")])
5697 (define_insn "*umulsidi3_no_mq"
5698 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5699 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5700 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5701 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5704 return (WORDS_BIG_ENDIAN)
5705 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5706 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5708 [(set_attr "type" "imul")
5709 (set_attr "length" "8")])
5712 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5713 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5714 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5715 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5718 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5719 (zero_extend:DI (match_dup 2)))
5722 (mult:SI (match_dup 1)
5726 int endian = (WORDS_BIG_ENDIAN == 0);
5727 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5728 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5731 (define_expand "smulsi3_highpart"
5732 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5734 (lshiftrt:DI (mult:DI (sign_extend:DI
5735 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5737 (match_operand:SI 2 "gpc_reg_operand" "r")))
5742 if (! TARGET_POWER && ! TARGET_POWERPC)
5744 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5745 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5746 emit_insn (gen_mulh_call ());
5747 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5750 else if (TARGET_POWER)
5752 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5757 (define_insn "smulsi3_highpart_mq"
5758 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5760 (lshiftrt:DI (mult:DI (sign_extend:DI
5761 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5763 (match_operand:SI 2 "gpc_reg_operand" "r")))
5765 (clobber (match_scratch:SI 3 "=q"))]
5768 [(set_attr "type" "imul")])
5770 (define_insn "*smulsi3_highpart_no_mq"
5771 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5773 (lshiftrt:DI (mult:DI (sign_extend:DI
5774 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5776 (match_operand:SI 2 "gpc_reg_operand" "r")))
5778 "TARGET_POWERPC && ! TARGET_POWER"
5780 [(set_attr "type" "imul")])
5782 (define_expand "umulsi3_highpart"
5783 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5785 (lshiftrt:DI (mult:DI (zero_extend:DI
5786 (match_operand:SI 1 "gpc_reg_operand" ""))
5788 (match_operand:SI 2 "gpc_reg_operand" "")))
5795 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5800 (define_insn "umulsi3_highpart_mq"
5801 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5803 (lshiftrt:DI (mult:DI (zero_extend:DI
5804 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5806 (match_operand:SI 2 "gpc_reg_operand" "r")))
5808 (clobber (match_scratch:SI 3 "=q"))]
5809 "TARGET_POWERPC && TARGET_POWER"
5811 [(set_attr "type" "imul")])
5813 (define_insn "*umulsi3_highpart_no_mq"
5814 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5816 (lshiftrt:DI (mult:DI (zero_extend:DI
5817 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5819 (match_operand:SI 2 "gpc_reg_operand" "r")))
5821 "TARGET_POWERPC && ! TARGET_POWER"
5823 [(set_attr "type" "imul")])
5825 ;; If operands 0 and 2 are in the same register, we have a problem. But
5826 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5827 ;; why we have the strange constraints below.
5828 (define_insn "ashldi3_power"
5829 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5830 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5831 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5832 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5835 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5836 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5837 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5838 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5839 [(set_attr "length" "8")])
5841 (define_insn "lshrdi3_power"
5842 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5843 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5844 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5845 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5848 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5849 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5850 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5851 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5852 [(set_attr "length" "8")])
5854 ;; Shift by a variable amount is too complex to be worth open-coding. We
5855 ;; just handle shifts by constants.
5856 (define_insn "ashrdi3_power"
5857 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5858 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5859 (match_operand:SI 2 "const_int_operand" "M,i")))
5860 (clobber (match_scratch:SI 3 "=X,q"))]
5863 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5864 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5865 [(set_attr "length" "8")])
5867 (define_insn "ashrdi3_no_power"
5868 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5869 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5870 (match_operand:SI 2 "const_int_operand" "M,i")))]
5871 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5873 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5874 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5875 [(set_attr "type" "two,three")
5876 (set_attr "length" "8,12")])
5878 (define_insn "*ashrdisi3_noppc64"
5879 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5880 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5881 (const_int 32)) 4))]
5882 "TARGET_32BIT && !TARGET_POWERPC64"
5885 if (REGNO (operands[0]) == REGNO (operands[1]))
5888 return \"mr %0,%1\";
5890 [(set_attr "length" "4")])
5893 ;; PowerPC64 DImode operations.
5895 (define_insn_and_split "absdi2"
5896 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5897 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5898 (clobber (match_scratch:DI 2 "=&r,&r"))]
5901 "&& reload_completed"
5902 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5903 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5904 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5907 (define_insn_and_split "*nabsdi2"
5908 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5909 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5910 (clobber (match_scratch:DI 2 "=&r,&r"))]
5913 "&& reload_completed"
5914 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5915 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5916 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5919 (define_insn "muldi3"
5920 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5921 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5922 (match_operand:DI 2 "gpc_reg_operand" "r")))]
5925 [(set_attr "type" "lmul")])
5927 (define_insn "*muldi3_internal1"
5928 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5929 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5930 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5932 (clobber (match_scratch:DI 3 "=r,r"))]
5937 [(set_attr "type" "lmul_compare")
5938 (set_attr "length" "4,8")])
5941 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5942 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
5943 (match_operand:DI 2 "gpc_reg_operand" ""))
5945 (clobber (match_scratch:DI 3 ""))]
5946 "TARGET_POWERPC64 && reload_completed"
5948 (mult:DI (match_dup 1) (match_dup 2)))
5950 (compare:CC (match_dup 3)
5954 (define_insn "*muldi3_internal2"
5955 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5956 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5957 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5959 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5960 (mult:DI (match_dup 1) (match_dup 2)))]
5965 [(set_attr "type" "lmul_compare")
5966 (set_attr "length" "4,8")])
5969 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5970 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
5971 (match_operand:DI 2 "gpc_reg_operand" ""))
5973 (set (match_operand:DI 0 "gpc_reg_operand" "")
5974 (mult:DI (match_dup 1) (match_dup 2)))]
5975 "TARGET_POWERPC64 && reload_completed"
5977 (mult:DI (match_dup 1) (match_dup 2)))
5979 (compare:CC (match_dup 0)
5983 (define_insn "smuldi3_highpart"
5984 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5986 (lshiftrt:TI (mult:TI (sign_extend:TI
5987 (match_operand:DI 1 "gpc_reg_operand" "%r"))
5989 (match_operand:DI 2 "gpc_reg_operand" "r")))
5993 [(set_attr "type" "lmul")])
5995 (define_insn "umuldi3_highpart"
5996 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5998 (lshiftrt:TI (mult:TI (zero_extend:TI
5999 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6001 (match_operand:DI 2 "gpc_reg_operand" "r")))
6005 [(set_attr "type" "lmul")])
6007 (define_expand "divdi3"
6008 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6009 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6010 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6014 if (GET_CODE (operands[2]) == CONST_INT
6015 && INTVAL (operands[2]) > 0
6016 && exact_log2 (INTVAL (operands[2])) >= 0)
6019 operands[2] = force_reg (DImode, operands[2]);
6022 (define_expand "moddi3"
6023 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6024 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6025 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6033 if (GET_CODE (operands[2]) != CONST_INT
6034 || INTVAL (operands[2]) <= 0
6035 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6038 temp1 = gen_reg_rtx (DImode);
6039 temp2 = gen_reg_rtx (DImode);
6041 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6042 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6043 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6048 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6049 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6050 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6052 "sradi %0,%1,%p2\;addze %0,%0"
6053 [(set_attr "type" "two")
6054 (set_attr "length" "8")])
6057 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6058 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6059 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6061 (clobber (match_scratch:DI 3 "=r,r"))]
6064 sradi %3,%1,%p2\;addze. %3,%3
6066 [(set_attr "type" "compare")
6067 (set_attr "length" "8,12")])
6070 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6071 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6072 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6074 (clobber (match_scratch:DI 3 ""))]
6075 "TARGET_POWERPC64 && reload_completed"
6077 (div:DI (match_dup 1) (match_dup 2)))
6079 (compare:CC (match_dup 3)
6084 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6085 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6086 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6088 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6089 (div:DI (match_dup 1) (match_dup 2)))]
6092 sradi %0,%1,%p2\;addze. %0,%0
6094 [(set_attr "type" "compare")
6095 (set_attr "length" "8,12")])
6098 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6099 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6100 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6102 (set (match_operand:DI 0 "gpc_reg_operand" "")
6103 (div:DI (match_dup 1) (match_dup 2)))]
6104 "TARGET_POWERPC64 && reload_completed"
6106 (div:DI (match_dup 1) (match_dup 2)))
6108 (compare:CC (match_dup 0)
6113 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6114 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6115 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6118 [(set_attr "type" "ldiv")])
6120 (define_insn "udivdi3"
6121 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6122 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6123 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6126 [(set_attr "type" "ldiv")])
6128 (define_insn "rotldi3"
6129 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6130 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6131 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6133 "rld%I2cl %0,%1,%H2,0")
6135 (define_insn "*rotldi3_internal2"
6136 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6137 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6138 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6140 (clobber (match_scratch:DI 3 "=r,r"))]
6143 rld%I2cl. %3,%1,%H2,0
6145 [(set_attr "type" "delayed_compare")
6146 (set_attr "length" "4,8")])
6149 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6150 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6151 (match_operand:DI 2 "reg_or_cint_operand" ""))
6153 (clobber (match_scratch:DI 3 ""))]
6154 "TARGET_POWERPC64 && reload_completed"
6156 (rotate:DI (match_dup 1) (match_dup 2)))
6158 (compare:CC (match_dup 3)
6162 (define_insn "*rotldi3_internal3"
6163 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6164 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6165 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6167 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6168 (rotate:DI (match_dup 1) (match_dup 2)))]
6171 rld%I2cl. %0,%1,%H2,0
6173 [(set_attr "type" "delayed_compare")
6174 (set_attr "length" "4,8")])
6177 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6178 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6179 (match_operand:DI 2 "reg_or_cint_operand" ""))
6181 (set (match_operand:DI 0 "gpc_reg_operand" "")
6182 (rotate:DI (match_dup 1) (match_dup 2)))]
6183 "TARGET_POWERPC64 && reload_completed"
6185 (rotate:DI (match_dup 1) (match_dup 2)))
6187 (compare:CC (match_dup 0)
6191 (define_insn "*rotldi3_internal4"
6192 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6193 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6194 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6195 (match_operand:DI 3 "mask64_operand" "n")))]
6197 "rld%I2c%B3 %0,%1,%H2,%S3")
6199 (define_insn "*rotldi3_internal5"
6200 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6202 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6203 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6204 (match_operand:DI 3 "mask64_operand" "n,n"))
6206 (clobber (match_scratch:DI 4 "=r,r"))]
6209 rld%I2c%B3. %4,%1,%H2,%S3
6211 [(set_attr "type" "delayed_compare")
6212 (set_attr "length" "4,8")])
6215 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6217 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6218 (match_operand:DI 2 "reg_or_cint_operand" ""))
6219 (match_operand:DI 3 "mask64_operand" ""))
6221 (clobber (match_scratch:DI 4 ""))]
6222 "TARGET_POWERPC64 && reload_completed"
6224 (and:DI (rotate:DI (match_dup 1)
6228 (compare:CC (match_dup 4)
6232 (define_insn "*rotldi3_internal6"
6233 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6235 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6236 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6237 (match_operand:DI 3 "mask64_operand" "n,n"))
6239 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6240 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6243 rld%I2c%B3. %0,%1,%H2,%S3
6245 [(set_attr "type" "delayed_compare")
6246 (set_attr "length" "4,8")])
6249 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6251 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6252 (match_operand:DI 2 "reg_or_cint_operand" ""))
6253 (match_operand:DI 3 "mask64_operand" ""))
6255 (set (match_operand:DI 0 "gpc_reg_operand" "")
6256 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6257 "TARGET_POWERPC64 && reload_completed"
6259 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6261 (compare:CC (match_dup 0)
6265 (define_insn "*rotldi3_internal7"
6266 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6269 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6270 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6272 "rld%I2cl %0,%1,%H2,56")
6274 (define_insn "*rotldi3_internal8"
6275 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6276 (compare:CC (zero_extend:DI
6278 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6279 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6281 (clobber (match_scratch:DI 3 "=r,r"))]
6284 rld%I2cl. %3,%1,%H2,56
6286 [(set_attr "type" "delayed_compare")
6287 (set_attr "length" "4,8")])
6290 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6291 (compare:CC (zero_extend:DI
6293 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6294 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6296 (clobber (match_scratch:DI 3 ""))]
6297 "TARGET_POWERPC64 && reload_completed"
6299 (zero_extend:DI (subreg:QI
6300 (rotate:DI (match_dup 1)
6303 (compare:CC (match_dup 3)
6307 (define_insn "*rotldi3_internal9"
6308 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6309 (compare:CC (zero_extend:DI
6311 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6312 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6314 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6315 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6318 rld%I2cl. %0,%1,%H2,56
6320 [(set_attr "type" "delayed_compare")
6321 (set_attr "length" "4,8")])
6324 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6325 (compare:CC (zero_extend:DI
6327 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6328 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6330 (set (match_operand:DI 0 "gpc_reg_operand" "")
6331 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6332 "TARGET_POWERPC64 && reload_completed"
6334 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6336 (compare:CC (match_dup 0)
6340 (define_insn "*rotldi3_internal10"
6341 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6344 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6345 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6347 "rld%I2cl %0,%1,%H2,48")
6349 (define_insn "*rotldi3_internal11"
6350 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6351 (compare:CC (zero_extend:DI
6353 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6354 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6356 (clobber (match_scratch:DI 3 "=r,r"))]
6359 rld%I2cl. %3,%1,%H2,48
6361 [(set_attr "type" "delayed_compare")
6362 (set_attr "length" "4,8")])
6365 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6366 (compare:CC (zero_extend:DI
6368 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6369 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6371 (clobber (match_scratch:DI 3 ""))]
6372 "TARGET_POWERPC64 && reload_completed"
6374 (zero_extend:DI (subreg:HI
6375 (rotate:DI (match_dup 1)
6378 (compare:CC (match_dup 3)
6382 (define_insn "*rotldi3_internal12"
6383 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6384 (compare:CC (zero_extend:DI
6386 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6387 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6389 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6390 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6393 rld%I2cl. %0,%1,%H2,48
6395 [(set_attr "type" "delayed_compare")
6396 (set_attr "length" "4,8")])
6399 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6400 (compare:CC (zero_extend:DI
6402 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6403 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6405 (set (match_operand:DI 0 "gpc_reg_operand" "")
6406 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6407 "TARGET_POWERPC64 && reload_completed"
6409 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6411 (compare:CC (match_dup 0)
6415 (define_insn "*rotldi3_internal13"
6416 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6419 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6420 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6422 "rld%I2cl %0,%1,%H2,32")
6424 (define_insn "*rotldi3_internal14"
6425 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6426 (compare:CC (zero_extend:DI
6428 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6429 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6431 (clobber (match_scratch:DI 3 "=r,r"))]
6434 rld%I2cl. %3,%1,%H2,32
6436 [(set_attr "type" "delayed_compare")
6437 (set_attr "length" "4,8")])
6440 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6441 (compare:CC (zero_extend:DI
6443 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6444 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6446 (clobber (match_scratch:DI 3 ""))]
6447 "TARGET_POWERPC64 && reload_completed"
6449 (zero_extend:DI (subreg:SI
6450 (rotate:DI (match_dup 1)
6453 (compare:CC (match_dup 3)
6457 (define_insn "*rotldi3_internal15"
6458 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6459 (compare:CC (zero_extend:DI
6461 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6462 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6464 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6465 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6468 rld%I2cl. %0,%1,%H2,32
6470 [(set_attr "type" "delayed_compare")
6471 (set_attr "length" "4,8")])
6474 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6475 (compare:CC (zero_extend:DI
6477 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6478 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6480 (set (match_operand:DI 0 "gpc_reg_operand" "")
6481 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6482 "TARGET_POWERPC64 && reload_completed"
6484 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6486 (compare:CC (match_dup 0)
6490 (define_expand "ashldi3"
6491 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6492 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6493 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6494 "TARGET_POWERPC64 || TARGET_POWER"
6497 if (TARGET_POWERPC64)
6499 else if (TARGET_POWER)
6501 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6508 (define_insn "*ashldi3_internal1"
6509 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6510 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6511 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6515 (define_insn "*ashldi3_internal2"
6516 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6517 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6518 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6520 (clobber (match_scratch:DI 3 "=r,r"))]
6525 [(set_attr "type" "delayed_compare")
6526 (set_attr "length" "4,8")])
6529 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6530 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6531 (match_operand:SI 2 "reg_or_cint_operand" ""))
6533 (clobber (match_scratch:DI 3 ""))]
6534 "TARGET_POWERPC64 && reload_completed"
6536 (ashift:DI (match_dup 1) (match_dup 2)))
6538 (compare:CC (match_dup 3)
6542 (define_insn "*ashldi3_internal3"
6543 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6544 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6545 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6547 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6548 (ashift:DI (match_dup 1) (match_dup 2)))]
6553 [(set_attr "type" "delayed_compare")
6554 (set_attr "length" "4,8")])
6557 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6558 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6559 (match_operand:SI 2 "reg_or_cint_operand" ""))
6561 (set (match_operand:DI 0 "gpc_reg_operand" "")
6562 (ashift:DI (match_dup 1) (match_dup 2)))]
6563 "TARGET_POWERPC64 && reload_completed"
6565 (ashift:DI (match_dup 1) (match_dup 2)))
6567 (compare:CC (match_dup 0)
6571 (define_insn "*ashldi3_internal4"
6572 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6573 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6574 (match_operand:SI 2 "const_int_operand" "i"))
6575 (match_operand:DI 3 "const_int_operand" "n")))]
6576 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6577 "rldic %0,%1,%H2,%W3")
6579 (define_insn "ashldi3_internal5"
6580 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6582 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6583 (match_operand:SI 2 "const_int_operand" "i,i"))
6584 (match_operand:DI 3 "const_int_operand" "n,n"))
6586 (clobber (match_scratch:DI 4 "=r,r"))]
6587 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6589 rldic. %4,%1,%H2,%W3
6591 [(set_attr "type" "delayed_compare")
6592 (set_attr "length" "4,8")])
6595 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6597 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6598 (match_operand:SI 2 "const_int_operand" ""))
6599 (match_operand:DI 3 "const_int_operand" ""))
6601 (clobber (match_scratch:DI 4 ""))]
6602 "TARGET_POWERPC64 && reload_completed
6603 && includes_rldic_lshift_p (operands[2], operands[3])"
6605 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6608 (compare:CC (match_dup 4)
6612 (define_insn "*ashldi3_internal6"
6613 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6615 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6616 (match_operand:SI 2 "const_int_operand" "i,i"))
6617 (match_operand:DI 3 "const_int_operand" "n,n"))
6619 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6620 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6621 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6623 rldic. %0,%1,%H2,%W3
6625 [(set_attr "type" "delayed_compare")
6626 (set_attr "length" "4,8")])
6629 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6631 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6632 (match_operand:SI 2 "const_int_operand" ""))
6633 (match_operand:DI 3 "const_int_operand" ""))
6635 (set (match_operand:DI 0 "gpc_reg_operand" "")
6636 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6637 "TARGET_POWERPC64 && reload_completed
6638 && includes_rldic_lshift_p (operands[2], operands[3])"
6640 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6643 (compare:CC (match_dup 0)
6647 (define_insn "*ashldi3_internal7"
6648 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6649 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6650 (match_operand:SI 2 "const_int_operand" "i"))
6651 (match_operand:DI 3 "mask64_operand" "n")))]
6652 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6653 "rldicr %0,%1,%H2,%S3")
6655 (define_insn "ashldi3_internal8"
6656 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6658 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6659 (match_operand:SI 2 "const_int_operand" "i,i"))
6660 (match_operand:DI 3 "mask64_operand" "n,n"))
6662 (clobber (match_scratch:DI 4 "=r,r"))]
6663 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6665 rldicr. %4,%1,%H2,%S3
6667 [(set_attr "type" "delayed_compare")
6668 (set_attr "length" "4,8")])
6671 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6673 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6674 (match_operand:SI 2 "const_int_operand" ""))
6675 (match_operand:DI 3 "mask64_operand" ""))
6677 (clobber (match_scratch:DI 4 ""))]
6678 "TARGET_POWERPC64 && reload_completed
6679 && includes_rldicr_lshift_p (operands[2], operands[3])"
6681 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6684 (compare:CC (match_dup 4)
6688 (define_insn "*ashldi3_internal9"
6689 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6691 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6692 (match_operand:SI 2 "const_int_operand" "i,i"))
6693 (match_operand:DI 3 "mask64_operand" "n,n"))
6695 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6696 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6697 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6699 rldicr. %0,%1,%H2,%S3
6701 [(set_attr "type" "delayed_compare")
6702 (set_attr "length" "4,8")])
6705 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6707 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6708 (match_operand:SI 2 "const_int_operand" ""))
6709 (match_operand:DI 3 "mask64_operand" ""))
6711 (set (match_operand:DI 0 "gpc_reg_operand" "")
6712 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6713 "TARGET_POWERPC64 && reload_completed
6714 && includes_rldicr_lshift_p (operands[2], operands[3])"
6716 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6719 (compare:CC (match_dup 0)
6723 (define_expand "lshrdi3"
6724 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6725 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6726 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6727 "TARGET_POWERPC64 || TARGET_POWER"
6730 if (TARGET_POWERPC64)
6732 else if (TARGET_POWER)
6734 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6741 (define_insn "*lshrdi3_internal1"
6742 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6743 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6744 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6748 (define_insn "*lshrdi3_internal2"
6749 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6750 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6751 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6753 (clobber (match_scratch:DI 3 "=r,r"))]
6758 [(set_attr "type" "delayed_compare")
6759 (set_attr "length" "4,8")])
6762 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6763 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6764 (match_operand:SI 2 "reg_or_cint_operand" ""))
6766 (clobber (match_scratch:DI 3 ""))]
6767 "TARGET_POWERPC64 && reload_completed"
6769 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6771 (compare:CC (match_dup 3)
6775 (define_insn "*lshrdi3_internal3"
6776 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6777 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6778 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6780 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6781 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6786 [(set_attr "type" "delayed_compare")
6787 (set_attr "length" "4,8")])
6790 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6791 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6792 (match_operand:SI 2 "reg_or_cint_operand" ""))
6794 (set (match_operand:DI 0 "gpc_reg_operand" "")
6795 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6796 "TARGET_POWERPC64 && reload_completed"
6798 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6800 (compare:CC (match_dup 0)
6804 (define_expand "ashrdi3"
6805 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6806 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6807 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6811 if (TARGET_POWERPC64)
6813 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6815 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6818 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
6819 && WORDS_BIG_ENDIAN)
6821 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6828 (define_insn "*ashrdi3_internal1"
6829 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6830 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6831 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6833 "srad%I2 %0,%1,%H2")
6835 (define_insn "*ashrdi3_internal2"
6836 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6837 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6838 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6840 (clobber (match_scratch:DI 3 "=r,r"))]
6845 [(set_attr "type" "delayed_compare")
6846 (set_attr "length" "4,8")])
6849 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6850 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6851 (match_operand:SI 2 "reg_or_cint_operand" ""))
6853 (clobber (match_scratch:DI 3 ""))]
6854 "TARGET_POWERPC64 && reload_completed"
6856 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6858 (compare:CC (match_dup 3)
6862 (define_insn "*ashrdi3_internal3"
6863 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6864 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6865 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6867 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6868 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6873 [(set_attr "type" "delayed_compare")
6874 (set_attr "length" "4,8")])
6877 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6878 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6879 (match_operand:SI 2 "reg_or_cint_operand" ""))
6881 (set (match_operand:DI 0 "gpc_reg_operand" "")
6882 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6883 "TARGET_POWERPC64 && reload_completed"
6885 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6887 (compare:CC (match_dup 0)
6891 (define_insn "anddi3"
6892 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
6893 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
6894 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
6895 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
6899 rldic%B2 %0,%1,0,%S2
6900 rlwinm %0,%1,0,%m2,%M2
6904 [(set_attr "type" "*,*,*,compare,compare,*")
6905 (set_attr "length" "4,4,4,4,4,8")])
6908 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6909 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6910 (match_operand:DI 2 "mask64_2_operand" "")))
6911 (clobber (match_scratch:CC 3 ""))]
6913 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6914 && !mask64_operand (operands[2], DImode)"
6916 (and:DI (rotate:DI (match_dup 1)
6920 (and:DI (rotate:DI (match_dup 0)
6924 build_mask64_2_operands (operands[2], &operands[4]);
6927 (define_insn "*anddi3_internal2"
6928 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
6929 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
6930 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
6932 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
6933 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
6937 rldic%B2. %3,%1,0,%S2
6946 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
6947 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
6950 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6951 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6952 (match_operand:DI 2 "and64_operand" ""))
6954 (clobber (match_scratch:DI 3 ""))
6955 (clobber (match_scratch:CC 4 ""))]
6956 "TARGET_POWERPC64 && reload_completed"
6957 [(parallel [(set (match_dup 3)
6958 (and:DI (match_dup 1)
6960 (clobber (match_dup 4))])
6962 (compare:CC (match_dup 3)
6967 [(set (match_operand:CC 0 "cc_reg_operand" "")
6968 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6969 (match_operand:DI 2 "mask64_2_operand" ""))
6971 (clobber (match_scratch:DI 3 ""))
6972 (clobber (match_scratch:CC 4 ""))]
6973 "TARGET_POWERPC64 && reload_completed
6974 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6975 && !mask64_operand (operands[2], DImode)"
6977 (and:DI (rotate:DI (match_dup 1)
6980 (parallel [(set (match_dup 0)
6981 (compare:CC (and:DI (rotate:DI (match_dup 3)
6985 (clobber (match_dup 3))])]
6988 build_mask64_2_operands (operands[2], &operands[5]);
6991 (define_insn "*anddi3_internal3"
6992 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
6993 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
6994 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
6996 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
6997 (and:DI (match_dup 1) (match_dup 2)))
6998 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7002 rldic%B2. %0,%1,0,%S2
7011 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7012 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7015 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7016 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7017 (match_operand:DI 2 "and64_operand" ""))
7019 (set (match_operand:DI 0 "gpc_reg_operand" "")
7020 (and:DI (match_dup 1) (match_dup 2)))
7021 (clobber (match_scratch:CC 4 ""))]
7022 "TARGET_POWERPC64 && reload_completed"
7023 [(parallel [(set (match_dup 0)
7024 (and:DI (match_dup 1) (match_dup 2)))
7025 (clobber (match_dup 4))])
7027 (compare:CC (match_dup 0)
7032 [(set (match_operand:CC 3 "cc_reg_operand" "")
7033 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7034 (match_operand:DI 2 "mask64_2_operand" ""))
7036 (set (match_operand:DI 0 "gpc_reg_operand" "")
7037 (and:DI (match_dup 1) (match_dup 2)))
7038 (clobber (match_scratch:CC 4 ""))]
7039 "TARGET_POWERPC64 && reload_completed
7040 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7041 && !mask64_operand (operands[2], DImode)"
7043 (and:DI (rotate:DI (match_dup 1)
7046 (parallel [(set (match_dup 3)
7047 (compare:CC (and:DI (rotate:DI (match_dup 0)
7052 (and:DI (rotate:DI (match_dup 0)
7057 build_mask64_2_operands (operands[2], &operands[5]);
7060 (define_expand "iordi3"
7061 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7062 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7063 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7067 if (non_logical_cint_operand (operands[2], DImode))
7069 HOST_WIDE_INT value;
7070 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7071 ? operands[0] : gen_reg_rtx (DImode));
7073 if (GET_CODE (operands[2]) == CONST_INT)
7075 value = INTVAL (operands[2]);
7076 emit_insn (gen_iordi3 (tmp, operands[1],
7077 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7081 value = CONST_DOUBLE_LOW (operands[2]);
7082 emit_insn (gen_iordi3 (tmp, operands[1],
7083 immed_double_const (value
7084 & (~ (HOST_WIDE_INT) 0xffff),
7088 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7093 (define_expand "xordi3"
7094 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7095 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7096 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7100 if (non_logical_cint_operand (operands[2], DImode))
7102 HOST_WIDE_INT value;
7103 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7104 ? operands[0] : gen_reg_rtx (DImode));
7106 if (GET_CODE (operands[2]) == CONST_INT)
7108 value = INTVAL (operands[2]);
7109 emit_insn (gen_xordi3 (tmp, operands[1],
7110 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7114 value = CONST_DOUBLE_LOW (operands[2]);
7115 emit_insn (gen_xordi3 (tmp, operands[1],
7116 immed_double_const (value
7117 & (~ (HOST_WIDE_INT) 0xffff),
7121 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7126 (define_insn "*booldi3_internal1"
7127 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7128 (match_operator:DI 3 "boolean_or_operator"
7129 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7130 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7137 (define_insn "*booldi3_internal2"
7138 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7139 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7140 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7141 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7143 (clobber (match_scratch:DI 3 "=r,r"))]
7148 [(set_attr "type" "compare")
7149 (set_attr "length" "4,8")])
7152 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7153 (compare:CC (match_operator:DI 4 "boolean_operator"
7154 [(match_operand:DI 1 "gpc_reg_operand" "")
7155 (match_operand:DI 2 "gpc_reg_operand" "")])
7157 (clobber (match_scratch:DI 3 ""))]
7158 "TARGET_POWERPC64 && reload_completed"
7159 [(set (match_dup 3) (match_dup 4))
7161 (compare:CC (match_dup 3)
7165 (define_insn "*booldi3_internal3"
7166 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7167 (compare:CC (match_operator:DI 4 "boolean_operator"
7168 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7169 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7171 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7177 [(set_attr "type" "compare")
7178 (set_attr "length" "4,8")])
7181 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7182 (compare:CC (match_operator:DI 4 "boolean_operator"
7183 [(match_operand:DI 1 "gpc_reg_operand" "")
7184 (match_operand:DI 2 "gpc_reg_operand" "")])
7186 (set (match_operand:DI 0 "gpc_reg_operand" "")
7188 "TARGET_POWERPC64 && reload_completed"
7189 [(set (match_dup 0) (match_dup 4))
7191 (compare:CC (match_dup 0)
7195 ;; Split a logical operation that we can't do in one insn into two insns,
7196 ;; each of which does one 16-bit part. This is used by combine.
7199 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7200 (match_operator:DI 3 "boolean_or_operator"
7201 [(match_operand:DI 1 "gpc_reg_operand" "")
7202 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7204 [(set (match_dup 0) (match_dup 4))
7205 (set (match_dup 0) (match_dup 5))]
7210 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7212 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7213 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7215 i4 = GEN_INT (value & 0xffff);
7219 i3 = GEN_INT (INTVAL (operands[2])
7220 & (~ (HOST_WIDE_INT) 0xffff));
7221 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7223 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7225 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7229 (define_insn "*boolcdi3_internal1"
7230 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7231 (match_operator:DI 3 "boolean_operator"
7232 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7233 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7237 (define_insn "*boolcdi3_internal2"
7238 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7239 (compare:CC (match_operator:DI 4 "boolean_operator"
7240 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7241 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7243 (clobber (match_scratch:DI 3 "=r,r"))]
7248 [(set_attr "type" "compare")
7249 (set_attr "length" "4,8")])
7252 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7253 (compare:CC (match_operator:DI 4 "boolean_operator"
7254 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7255 (match_operand:DI 2 "gpc_reg_operand" "")])
7257 (clobber (match_scratch:DI 3 ""))]
7258 "TARGET_POWERPC64 && reload_completed"
7259 [(set (match_dup 3) (match_dup 4))
7261 (compare:CC (match_dup 3)
7265 (define_insn "*boolcdi3_internal3"
7266 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7267 (compare:CC (match_operator:DI 4 "boolean_operator"
7268 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7269 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7271 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7277 [(set_attr "type" "compare")
7278 (set_attr "length" "4,8")])
7281 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7282 (compare:CC (match_operator:DI 4 "boolean_operator"
7283 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7284 (match_operand:DI 2 "gpc_reg_operand" "")])
7286 (set (match_operand:DI 0 "gpc_reg_operand" "")
7288 "TARGET_POWERPC64 && reload_completed"
7289 [(set (match_dup 0) (match_dup 4))
7291 (compare:CC (match_dup 0)
7295 (define_insn "*boolccdi3_internal1"
7296 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7297 (match_operator:DI 3 "boolean_operator"
7298 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7299 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7303 (define_insn "*boolccdi3_internal2"
7304 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7305 (compare:CC (match_operator:DI 4 "boolean_operator"
7306 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7307 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7309 (clobber (match_scratch:DI 3 "=r,r"))]
7314 [(set_attr "type" "compare")
7315 (set_attr "length" "4,8")])
7318 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7319 (compare:CC (match_operator:DI 4 "boolean_operator"
7320 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7321 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7323 (clobber (match_scratch:DI 3 ""))]
7324 "TARGET_POWERPC64 && reload_completed"
7325 [(set (match_dup 3) (match_dup 4))
7327 (compare:CC (match_dup 3)
7331 (define_insn "*boolccdi3_internal3"
7332 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7333 (compare:CC (match_operator:DI 4 "boolean_operator"
7334 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7335 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7337 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7343 [(set_attr "type" "compare")
7344 (set_attr "length" "4,8")])
7347 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7348 (compare:CC (match_operator:DI 4 "boolean_operator"
7349 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7350 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7352 (set (match_operand:DI 0 "gpc_reg_operand" "")
7354 "TARGET_POWERPC64 && reload_completed"
7355 [(set (match_dup 0) (match_dup 4))
7357 (compare:CC (match_dup 0)
7361 ;; Now define ways of moving data around.
7363 ;; Set up a register with a value from the GOT table
7365 (define_expand "movsi_got"
7366 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7367 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7368 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7369 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7372 if (GET_CODE (operands[1]) == CONST)
7374 rtx offset = const0_rtx;
7375 HOST_WIDE_INT value;
7377 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7378 value = INTVAL (offset);
7381 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7382 emit_insn (gen_movsi_got (tmp, operands[1]));
7383 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7388 operands[2] = rs6000_got_register (operands[1]);
7391 (define_insn "*movsi_got_internal"
7392 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7393 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7394 (match_operand:SI 2 "gpc_reg_operand" "b")]
7396 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7397 "{l|lwz} %0,%a1@got(%2)"
7398 [(set_attr "type" "load")])
7400 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7401 ;; didn't get allocated to a hard register.
7403 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7404 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7405 (match_operand:SI 2 "memory_operand" "")]
7407 "DEFAULT_ABI == ABI_V4
7409 && (reload_in_progress || reload_completed)"
7410 [(set (match_dup 0) (match_dup 2))
7411 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7415 ;; For SI, we special-case integers that can't be loaded in one insn. We
7416 ;; do the load 16-bits at a time. We could do this by loading from memory,
7417 ;; and this is even supposed to be faster, but it is simpler not to get
7418 ;; integers in the TOC.
7419 (define_expand "movsi"
7420 [(set (match_operand:SI 0 "general_operand" "")
7421 (match_operand:SI 1 "any_operand" ""))]
7423 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7425 (define_insn "movsi_low"
7426 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7427 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7428 (match_operand 2 "" ""))))]
7429 "TARGET_MACHO && ! TARGET_64BIT"
7430 "{l|lwz} %0,lo16(%2)(%1)"
7431 [(set_attr "type" "load")
7432 (set_attr "length" "4")])
7434 (define_insn "*movsi_internal1"
7435 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7436 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7437 "gpc_reg_operand (operands[0], SImode)
7438 || gpc_reg_operand (operands[1], SImode)"
7442 {l%U1%X1|lwz%U1%X1} %0,%1
7443 {st%U0%X0|stw%U0%X0} %1,%0
7453 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7454 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7456 ;; Split a load of a large constant into the appropriate two-insn
7460 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7461 (match_operand:SI 1 "const_int_operand" ""))]
7462 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7463 && (INTVAL (operands[1]) & 0xffff) != 0"
7467 (ior:SI (match_dup 0)
7470 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7472 if (tem == operands[0])
7478 (define_insn "*movsi_internal2"
7479 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7480 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r")
7482 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7485 {cmpi|cmpwi} %2,%0,0
7488 [(set_attr "type" "cmp,compare,cmp")
7489 (set_attr "length" "4,4,8")])
7492 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7493 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7495 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7496 "TARGET_32BIT && reload_completed"
7497 [(set (match_dup 0) (match_dup 1))
7499 (compare:CC (match_dup 0)
7503 (define_expand "movhi"
7504 [(set (match_operand:HI 0 "general_operand" "")
7505 (match_operand:HI 1 "any_operand" ""))]
7507 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7509 (define_insn "*movhi_internal"
7510 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7511 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7512 "gpc_reg_operand (operands[0], HImode)
7513 || gpc_reg_operand (operands[1], HImode)"
7523 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7525 (define_expand "movqi"
7526 [(set (match_operand:QI 0 "general_operand" "")
7527 (match_operand:QI 1 "any_operand" ""))]
7529 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7531 (define_insn "*movqi_internal"
7532 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7533 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7534 "gpc_reg_operand (operands[0], QImode)
7535 || gpc_reg_operand (operands[1], QImode)"
7545 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7547 ;; Here is how to move condition codes around. When we store CC data in
7548 ;; an integer register or memory, we store just the high-order 4 bits.
7549 ;; This lets us not shift in the most common case of CR0.
7550 (define_expand "movcc"
7551 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7552 (match_operand:CC 1 "nonimmediate_operand" ""))]
7556 (define_insn "*movcc_internal1"
7557 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7558 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7559 "register_operand (operands[0], CCmode)
7560 || register_operand (operands[1], CCmode)"
7564 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7566 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7571 {l%U1%X1|lwz%U1%X1} %0,%1
7572 {st%U0%U1|stw%U0%U1} %1,%0"
7574 (cond [(eq_attr "alternative" "0")
7575 (const_string "cr_logical")
7576 (eq_attr "alternative" "1,2")
7577 (const_string "mtcr")
7578 (eq_attr "alternative" "5,7")
7579 (const_string "integer")
7580 (eq_attr "alternative" "6")
7581 (const_string "mfjmpr")
7582 (eq_attr "alternative" "8")
7583 (const_string "mtjmpr")
7584 (eq_attr "alternative" "9")
7585 (const_string "load")
7586 (eq_attr "alternative" "10")
7587 (const_string "store")
7588 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7589 (const_string "mfcrf")
7591 (const_string "mfcr")))
7592 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7594 ;; For floating-point, we normally deal with the floating-point registers
7595 ;; unless -msoft-float is used. The sole exception is that parameter passing
7596 ;; can produce floating-point values in fixed-point registers. Unless the
7597 ;; value is a simple constant or already in memory, we deal with this by
7598 ;; allocating memory and copying the value explicitly via that memory location.
7599 (define_expand "movsf"
7600 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7601 (match_operand:SF 1 "any_operand" ""))]
7603 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7606 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7607 (match_operand:SF 1 "const_double_operand" ""))]
7609 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7610 || (GET_CODE (operands[0]) == SUBREG
7611 && GET_CODE (SUBREG_REG (operands[0])) == REG
7612 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7613 [(set (match_dup 2) (match_dup 3))]
7619 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7620 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7622 if (! TARGET_POWERPC64)
7623 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7625 operands[2] = gen_lowpart (SImode, operands[0]);
7627 operands[3] = gen_int_mode (l, SImode);
7630 (define_insn "*movsf_hardfloat"
7631 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
7632 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7633 "(gpc_reg_operand (operands[0], SFmode)
7634 || gpc_reg_operand (operands[1], SFmode))
7635 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7638 {l%U1%X1|lwz%U1%X1} %0,%1
7639 {st%U0%X0|stw%U0%X0} %1,%0
7649 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
7650 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7652 (define_insn "*movsf_softfloat"
7653 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7654 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7655 "(gpc_reg_operand (operands[0], SFmode)
7656 || gpc_reg_operand (operands[1], SFmode))
7657 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7663 {l%U1%X1|lwz%U1%X1} %0,%1
7664 {st%U0%X0|stw%U0%X0} %1,%0
7671 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7672 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7675 (define_expand "movdf"
7676 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7677 (match_operand:DF 1 "any_operand" ""))]
7679 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7682 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7683 (match_operand:DF 1 "const_int_operand" ""))]
7684 "! TARGET_POWERPC64 && reload_completed
7685 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7686 || (GET_CODE (operands[0]) == SUBREG
7687 && GET_CODE (SUBREG_REG (operands[0])) == REG
7688 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7689 [(set (match_dup 2) (match_dup 4))
7690 (set (match_dup 3) (match_dup 1))]
7693 int endian = (WORDS_BIG_ENDIAN == 0);
7694 HOST_WIDE_INT value = INTVAL (operands[1]);
7696 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7697 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7698 #if HOST_BITS_PER_WIDE_INT == 32
7699 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7701 operands[4] = GEN_INT (value >> 32);
7702 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7707 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7708 (match_operand:DF 1 "const_double_operand" ""))]
7709 "! TARGET_POWERPC64 && reload_completed
7710 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7711 || (GET_CODE (operands[0]) == SUBREG
7712 && GET_CODE (SUBREG_REG (operands[0])) == REG
7713 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7714 [(set (match_dup 2) (match_dup 4))
7715 (set (match_dup 3) (match_dup 5))]
7718 int endian = (WORDS_BIG_ENDIAN == 0);
7722 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7723 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7725 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7726 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7727 operands[4] = gen_int_mode (l[endian], SImode);
7728 operands[5] = gen_int_mode (l[1 - endian], SImode);
7732 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7733 (match_operand:DF 1 "easy_fp_constant" ""))]
7734 "TARGET_POWERPC64 && reload_completed
7735 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7736 || (GET_CODE (operands[0]) == SUBREG
7737 && GET_CODE (SUBREG_REG (operands[0])) == REG
7738 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7739 [(set (match_dup 2) (match_dup 3))]
7742 int endian = (WORDS_BIG_ENDIAN == 0);
7745 #if HOST_BITS_PER_WIDE_INT >= 64
7749 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7750 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7752 operands[2] = gen_lowpart (DImode, operands[0]);
7753 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7754 #if HOST_BITS_PER_WIDE_INT >= 64
7755 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7756 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7758 operands[3] = gen_int_mode (val, DImode);
7760 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
7764 ;; Don't have reload use general registers to load a constant. First,
7765 ;; it might not work if the output operand is the equivalent of
7766 ;; a non-offsettable memref, but also it is less efficient than loading
7767 ;; the constant into an FP register, since it will probably be used there.
7768 ;; The "??" is a kludge until we can figure out a more reasonable way
7769 ;; of handling these non-offsettable values.
7770 (define_insn "*movdf_hardfloat32"
7771 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
7772 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
7773 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7774 && (gpc_reg_operand (operands[0], DFmode)
7775 || gpc_reg_operand (operands[1], DFmode))"
7778 switch (which_alternative)
7783 /* We normally copy the low-numbered register first. However, if
7784 the first register operand 0 is the same as the second register
7785 of operand 1, we must copy in the opposite order. */
7786 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7787 return \"mr %L0,%L1\;mr %0,%1\";
7789 return \"mr %0,%1\;mr %L0,%L1\";
7791 if (GET_CODE (operands[1]) == MEM
7792 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
7793 reload_completed || reload_in_progress)
7794 || GET_CODE (XEXP (operands[1], 0)) == REG
7795 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
7796 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
7797 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
7799 /* If the low-address word is used in the address, we must load
7800 it last. Otherwise, load it first. Note that we cannot have
7801 auto-increment in that case since the address register is
7802 known to be dead. */
7803 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7805 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7807 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7813 addreg = find_addr_reg (XEXP (operands[1], 0));
7814 if (refers_to_regno_p (REGNO (operands[0]),
7815 REGNO (operands[0]) + 1,
7818 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7819 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7820 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7821 return \"{lx|lwzx} %0,%1\";
7825 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
7826 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7827 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7828 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7833 if (GET_CODE (operands[0]) == MEM
7834 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
7835 reload_completed || reload_in_progress)
7836 || GET_CODE (XEXP (operands[0], 0)) == REG
7837 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
7838 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
7839 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
7840 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7845 addreg = find_addr_reg (XEXP (operands[0], 0));
7846 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
7847 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7848 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
7849 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7853 return \"fmr %0,%1\";
7855 return \"lfd%U1%X1 %0,%1\";
7857 return \"stfd%U0%X0 %1,%0\";
7864 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
7865 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
7867 (define_insn "*movdf_softfloat32"
7868 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7869 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7870 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
7871 && (gpc_reg_operand (operands[0], DFmode)
7872 || gpc_reg_operand (operands[1], DFmode))"
7875 switch (which_alternative)
7880 /* We normally copy the low-numbered register first. However, if
7881 the first register operand 0 is the same as the second register of
7882 operand 1, we must copy in the opposite order. */
7883 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7884 return \"mr %L0,%L1\;mr %0,%1\";
7886 return \"mr %0,%1\;mr %L0,%L1\";
7888 /* If the low-address word is used in the address, we must load
7889 it last. Otherwise, load it first. Note that we cannot have
7890 auto-increment in that case since the address register is
7891 known to be dead. */
7892 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7894 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7896 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7898 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7905 [(set_attr "type" "two,load,store,*,*,*")
7906 (set_attr "length" "8,8,8,8,12,16")])
7908 ; ld/std require word-aligned displacements -> 'Y' constraint.
7909 ; List Y->r and r->Y before r->r for reload.
7910 (define_insn "*movdf_hardfloat64"
7911 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
7912 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
7913 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7914 && (gpc_reg_operand (operands[0], DFmode)
7915 || gpc_reg_operand (operands[1], DFmode))"
7929 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
7930 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
7932 (define_insn "*movdf_softfloat64"
7933 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
7934 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
7935 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
7936 && (gpc_reg_operand (operands[0], DFmode)
7937 || gpc_reg_operand (operands[1], DFmode))"
7948 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
7949 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
7951 (define_expand "movtf"
7952 [(set (match_operand:TF 0 "general_operand" "")
7953 (match_operand:TF 1 "any_operand" ""))]
7954 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7955 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7956 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
7958 ; It's important to list the o->f and f->o moves before f->f because
7959 ; otherwise reload, given m->f, will try to pick f->f and reload it,
7960 ; which doesn't make progress. Likewise r->Y must be before r->r.
7961 (define_insn_and_split "*movtf_internal"
7962 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
7963 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
7964 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7965 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
7966 && (gpc_reg_operand (operands[0], TFmode)
7967 || gpc_reg_operand (operands[1], TFmode))"
7969 "&& reload_completed"
7971 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
7972 [(set_attr "length" "8,8,8,20,20,16")])
7974 (define_expand "extenddftf2"
7975 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
7976 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
7977 (use (match_dup 2))])]
7978 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7979 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7981 operands[2] = CONST0_RTX (DFmode);
7984 (define_insn_and_split "*extenddftf2_internal"
7985 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
7986 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
7987 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
7988 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7989 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7991 "&& reload_completed"
7994 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
7995 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
7996 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
7998 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8003 (define_expand "extendsftf2"
8004 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8005 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8006 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8007 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8009 rtx tmp = gen_reg_rtx (DFmode);
8010 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8011 emit_insn (gen_extenddftf2 (operands[0], tmp));
8015 (define_expand "trunctfdf2"
8016 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8017 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8018 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8019 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8022 (define_insn_and_split "trunctfdf2_internal1"
8023 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8024 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8025 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
8026 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8030 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8033 emit_note (NOTE_INSN_DELETED);
8036 [(set_attr "type" "fp")])
8038 (define_insn "trunctfdf2_internal2"
8039 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8040 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8041 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
8042 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8044 [(set_attr "type" "fp")])
8046 (define_insn_and_split "trunctfsf2"
8047 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8048 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8049 (clobber (match_scratch:DF 2 "=f"))]
8050 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8051 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8053 "&& reload_completed"
8055 (float_truncate:DF (match_dup 1)))
8057 (float_truncate:SF (match_dup 2)))]
8060 (define_expand "floatsitf2"
8061 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8062 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
8063 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8064 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8066 rtx tmp = gen_reg_rtx (DFmode);
8067 expand_float (tmp, operands[1], false);
8068 emit_insn (gen_extenddftf2 (operands[0], tmp));
8072 ; fadd, but rounding towards zero.
8073 ; This is probably not the optimal code sequence.
8074 (define_insn "fix_trunc_helper"
8075 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8076 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8077 UNSPEC_FIX_TRUNC_TF))
8078 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8079 "TARGET_HARD_FLOAT && TARGET_FPRS"
8080 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8081 [(set_attr "type" "fp")
8082 (set_attr "length" "20")])
8084 (define_expand "fix_trunctfsi2"
8085 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8086 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8087 (clobber (match_dup 2))
8088 (clobber (match_dup 3))
8089 (clobber (match_dup 4))
8090 (clobber (match_dup 5))])]
8091 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8092 && (TARGET_POWER2 || TARGET_POWERPC)
8093 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8095 operands[2] = gen_reg_rtx (DFmode);
8096 operands[3] = gen_reg_rtx (DFmode);
8097 operands[4] = gen_reg_rtx (DImode);
8098 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8101 (define_insn_and_split "*fix_trunctfsi2_internal"
8102 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8103 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8104 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8105 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8106 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8107 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8108 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8109 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8111 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
8115 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8117 gcc_assert (MEM_P (operands[5]));
8118 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8120 emit_insn (gen_fctiwz (operands[4], operands[2]));
8121 emit_move_insn (operands[5], operands[4]);
8122 emit_move_insn (operands[0], lowword);
8126 (define_insn "negtf2"
8127 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8128 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8129 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8130 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8133 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8134 return \"fneg %L0,%L1\;fneg %0,%1\";
8136 return \"fneg %0,%1\;fneg %L0,%L1\";
8138 [(set_attr "type" "fp")
8139 (set_attr "length" "8")])
8141 (define_expand "abstf2"
8142 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8143 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8144 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8145 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8148 rtx label = gen_label_rtx ();
8149 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8154 (define_expand "abstf2_internal"
8155 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8156 (match_operand:TF 1 "gpc_reg_operand" "f"))
8157 (set (match_dup 3) (match_dup 5))
8158 (set (match_dup 5) (abs:DF (match_dup 5)))
8159 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8160 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8161 (label_ref (match_operand 2 "" ""))
8163 (set (match_dup 6) (neg:DF (match_dup 6)))]
8164 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8165 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8168 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8169 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8170 operands[3] = gen_reg_rtx (DFmode);
8171 operands[4] = gen_reg_rtx (CCFPmode);
8172 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8173 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8176 ;; Next come the multi-word integer load and store and the load and store
8178 (define_expand "movdi"
8179 [(set (match_operand:DI 0 "general_operand" "")
8180 (match_operand:DI 1 "any_operand" ""))]
8182 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
8184 ; List r->r after r->"o<>", otherwise reload will try to reload a
8185 ; non-offsettable address by using r->r which won't make progress.
8186 (define_insn "*movdi_internal32"
8187 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8188 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8190 && (gpc_reg_operand (operands[0], DImode)
8191 || gpc_reg_operand (operands[1], DImode))"
8200 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8203 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8204 (match_operand:DI 1 "const_int_operand" ""))]
8205 "! TARGET_POWERPC64 && reload_completed"
8206 [(set (match_dup 2) (match_dup 4))
8207 (set (match_dup 3) (match_dup 1))]
8210 HOST_WIDE_INT value = INTVAL (operands[1]);
8211 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8213 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8215 #if HOST_BITS_PER_WIDE_INT == 32
8216 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8218 operands[4] = GEN_INT (value >> 32);
8219 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8224 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8225 (match_operand:DI 1 "input_operand" ""))]
8226 "reload_completed && !TARGET_POWERPC64
8227 && gpr_or_gpr_p (operands[0], operands[1])"
8229 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8231 (define_insn "*movdi_internal64"
8232 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8233 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8235 && (gpc_reg_operand (operands[0], DImode)
8236 || gpc_reg_operand (operands[1], DImode))"
8251 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8252 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8254 ;; immediate value valid for a single instruction hiding in a const_double
8256 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8257 (match_operand:DI 1 "const_double_operand" "F"))]
8258 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8259 && GET_CODE (operands[1]) == CONST_DOUBLE
8260 && num_insns_constant (operands[1], DImode) == 1"
8263 return ((unsigned HOST_WIDE_INT)
8264 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8265 ? \"li %0,%1\" : \"lis %0,%v1\";
8268 ;; Generate all one-bits and clear left or right.
8269 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8271 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8272 (match_operand:DI 1 "mask64_operand" ""))]
8273 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8274 [(set (match_dup 0) (const_int -1))
8276 (and:DI (rotate:DI (match_dup 0)
8281 ;; Split a load of a large constant into the appropriate five-instruction
8282 ;; sequence. Handle anything in a constant number of insns.
8283 ;; When non-easy constants can go in the TOC, this should use
8284 ;; easy_fp_constant predicate.
8286 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8287 (match_operand:DI 1 "const_int_operand" ""))]
8288 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8289 [(set (match_dup 0) (match_dup 2))
8290 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8292 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8294 if (tem == operands[0])
8301 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8302 (match_operand:DI 1 "const_double_operand" ""))]
8303 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8304 [(set (match_dup 0) (match_dup 2))
8305 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8307 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8309 if (tem == operands[0])
8315 (define_insn "*movdi_internal2"
8316 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8317 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r")
8319 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8325 [(set_attr "type" "cmp,compare,cmp")
8326 (set_attr "length" "4,4,8")])
8329 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8330 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8332 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8333 "TARGET_POWERPC64 && reload_completed"
8334 [(set (match_dup 0) (match_dup 1))
8336 (compare:CC (match_dup 0)
8340 ;; TImode is similar, except that we usually want to compute the address into
8341 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8342 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8343 (define_expand "movti"
8344 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8345 (match_operand:TI 1 "general_operand" ""))
8346 (clobber (scratch:SI))])]
8348 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8350 ;; We say that MQ is clobbered in the last alternative because the first
8351 ;; alternative would never get used otherwise since it would need a reload
8352 ;; while the 2nd alternative would not. We put memory cases first so they
8353 ;; are preferred. Otherwise, we'd try to reload the output instead of
8354 ;; giving the SCRATCH mq.
8356 (define_insn "*movti_power"
8357 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8358 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8359 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8360 "TARGET_POWER && ! TARGET_POWERPC64
8361 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8364 switch (which_alternative)
8371 return \"{stsi|stswi} %1,%P0,16\";
8376 /* If the address is not used in the output, we can use lsi. Otherwise,
8377 fall through to generating four loads. */
8379 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8380 return \"{lsi|lswi} %0,%P1,16\";
8381 /* ... fall through ... */
8387 [(set_attr "type" "store,store,*,load,load,*")])
8389 (define_insn "*movti_string"
8390 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8391 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8392 "! TARGET_POWER && ! TARGET_POWERPC64
8393 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8396 switch (which_alternative)
8402 return \"{stsi|stswi} %1,%P0,16\";
8407 /* If the address is not used in the output, we can use lsi. Otherwise,
8408 fall through to generating four loads. */
8410 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8411 return \"{lsi|lswi} %0,%P1,16\";
8412 /* ... fall through ... */
8418 [(set_attr "type" "store,store,*,load,load,*")])
8420 (define_insn "*movti_ppc64"
8421 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8422 (match_operand:TI 1 "input_operand" "r,r,m"))]
8423 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8424 || gpc_reg_operand (operands[1], TImode))"
8426 [(set_attr "type" "*,load,store")])
8429 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8430 (match_operand:TI 1 "const_double_operand" ""))]
8432 [(set (match_dup 2) (match_dup 4))
8433 (set (match_dup 3) (match_dup 5))]
8436 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8438 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8440 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8442 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8443 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8445 else if (GET_CODE (operands[1]) == CONST_INT)
8447 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8448 operands[5] = operands[1];
8455 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8456 (match_operand:TI 1 "input_operand" ""))]
8458 && gpr_or_gpr_p (operands[0], operands[1])"
8460 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8462 (define_expand "load_multiple"
8463 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8464 (match_operand:SI 1 "" ""))
8465 (use (match_operand:SI 2 "" ""))])]
8466 "TARGET_STRING && !TARGET_POWERPC64"
8474 /* Support only loading a constant number of fixed-point registers from
8475 memory and only bother with this if more than two; the machine
8476 doesn't support more than eight. */
8477 if (GET_CODE (operands[2]) != CONST_INT
8478 || INTVAL (operands[2]) <= 2
8479 || INTVAL (operands[2]) > 8
8480 || GET_CODE (operands[1]) != MEM
8481 || GET_CODE (operands[0]) != REG
8482 || REGNO (operands[0]) >= 32)
8485 count = INTVAL (operands[2]);
8486 regno = REGNO (operands[0]);
8488 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8489 op1 = replace_equiv_address (operands[1],
8490 force_reg (SImode, XEXP (operands[1], 0)));
8492 for (i = 0; i < count; i++)
8493 XVECEXP (operands[3], 0, i)
8494 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8495 adjust_address_nv (op1, SImode, i * 4));
8498 (define_insn "*ldmsi8"
8499 [(match_parallel 0 "load_multiple_operation"
8500 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8501 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8502 (set (match_operand:SI 3 "gpc_reg_operand" "")
8503 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8504 (set (match_operand:SI 4 "gpc_reg_operand" "")
8505 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8506 (set (match_operand:SI 5 "gpc_reg_operand" "")
8507 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8508 (set (match_operand:SI 6 "gpc_reg_operand" "")
8509 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8510 (set (match_operand:SI 7 "gpc_reg_operand" "")
8511 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8512 (set (match_operand:SI 8 "gpc_reg_operand" "")
8513 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8514 (set (match_operand:SI 9 "gpc_reg_operand" "")
8515 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8516 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8518 { return rs6000_output_load_multiple (operands); }"
8519 [(set_attr "type" "load")
8520 (set_attr "length" "32")])
8522 (define_insn "*ldmsi7"
8523 [(match_parallel 0 "load_multiple_operation"
8524 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8525 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8526 (set (match_operand:SI 3 "gpc_reg_operand" "")
8527 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8528 (set (match_operand:SI 4 "gpc_reg_operand" "")
8529 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8530 (set (match_operand:SI 5 "gpc_reg_operand" "")
8531 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8532 (set (match_operand:SI 6 "gpc_reg_operand" "")
8533 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8534 (set (match_operand:SI 7 "gpc_reg_operand" "")
8535 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8536 (set (match_operand:SI 8 "gpc_reg_operand" "")
8537 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8538 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8540 { return rs6000_output_load_multiple (operands); }"
8541 [(set_attr "type" "load")
8542 (set_attr "length" "32")])
8544 (define_insn "*ldmsi6"
8545 [(match_parallel 0 "load_multiple_operation"
8546 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8547 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8548 (set (match_operand:SI 3 "gpc_reg_operand" "")
8549 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8550 (set (match_operand:SI 4 "gpc_reg_operand" "")
8551 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8552 (set (match_operand:SI 5 "gpc_reg_operand" "")
8553 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8554 (set (match_operand:SI 6 "gpc_reg_operand" "")
8555 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8556 (set (match_operand:SI 7 "gpc_reg_operand" "")
8557 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8558 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8560 { return rs6000_output_load_multiple (operands); }"
8561 [(set_attr "type" "load")
8562 (set_attr "length" "32")])
8564 (define_insn "*ldmsi5"
8565 [(match_parallel 0 "load_multiple_operation"
8566 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8567 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8568 (set (match_operand:SI 3 "gpc_reg_operand" "")
8569 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8570 (set (match_operand:SI 4 "gpc_reg_operand" "")
8571 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8572 (set (match_operand:SI 5 "gpc_reg_operand" "")
8573 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8574 (set (match_operand:SI 6 "gpc_reg_operand" "")
8575 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8576 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8578 { return rs6000_output_load_multiple (operands); }"
8579 [(set_attr "type" "load")
8580 (set_attr "length" "32")])
8582 (define_insn "*ldmsi4"
8583 [(match_parallel 0 "load_multiple_operation"
8584 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8585 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8586 (set (match_operand:SI 3 "gpc_reg_operand" "")
8587 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8588 (set (match_operand:SI 4 "gpc_reg_operand" "")
8589 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8590 (set (match_operand:SI 5 "gpc_reg_operand" "")
8591 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8592 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8594 { return rs6000_output_load_multiple (operands); }"
8595 [(set_attr "type" "load")
8596 (set_attr "length" "32")])
8598 (define_insn "*ldmsi3"
8599 [(match_parallel 0 "load_multiple_operation"
8600 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8601 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8602 (set (match_operand:SI 3 "gpc_reg_operand" "")
8603 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8604 (set (match_operand:SI 4 "gpc_reg_operand" "")
8605 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8606 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8608 { return rs6000_output_load_multiple (operands); }"
8609 [(set_attr "type" "load")
8610 (set_attr "length" "32")])
8612 (define_expand "store_multiple"
8613 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8614 (match_operand:SI 1 "" ""))
8615 (clobber (scratch:SI))
8616 (use (match_operand:SI 2 "" ""))])]
8617 "TARGET_STRING && !TARGET_POWERPC64"
8626 /* Support only storing a constant number of fixed-point registers to
8627 memory and only bother with this if more than two; the machine
8628 doesn't support more than eight. */
8629 if (GET_CODE (operands[2]) != CONST_INT
8630 || INTVAL (operands[2]) <= 2
8631 || INTVAL (operands[2]) > 8
8632 || GET_CODE (operands[0]) != MEM
8633 || GET_CODE (operands[1]) != REG
8634 || REGNO (operands[1]) >= 32)
8637 count = INTVAL (operands[2]);
8638 regno = REGNO (operands[1]);
8640 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8641 to = force_reg (SImode, XEXP (operands[0], 0));
8642 op0 = replace_equiv_address (operands[0], to);
8644 XVECEXP (operands[3], 0, 0)
8645 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8646 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8647 gen_rtx_SCRATCH (SImode));
8649 for (i = 1; i < count; i++)
8650 XVECEXP (operands[3], 0, i + 1)
8651 = gen_rtx_SET (VOIDmode,
8652 adjust_address_nv (op0, SImode, i * 4),
8653 gen_rtx_REG (SImode, regno + i));
8656 (define_insn "*store_multiple_power"
8657 [(match_parallel 0 "store_multiple_operation"
8658 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8659 (match_operand:SI 2 "gpc_reg_operand" "r"))
8660 (clobber (match_scratch:SI 3 "=q"))])]
8661 "TARGET_STRING && TARGET_POWER"
8662 "{stsi|stswi} %2,%P1,%O0"
8663 [(set_attr "type" "store")])
8665 (define_insn "*stmsi8"
8666 [(match_parallel 0 "store_multiple_operation"
8667 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8668 (match_operand:SI 2 "gpc_reg_operand" "r"))
8669 (clobber (match_scratch:SI 3 "X"))
8670 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8671 (match_operand:SI 4 "gpc_reg_operand" "r"))
8672 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8673 (match_operand:SI 5 "gpc_reg_operand" "r"))
8674 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8675 (match_operand:SI 6 "gpc_reg_operand" "r"))
8676 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8677 (match_operand:SI 7 "gpc_reg_operand" "r"))
8678 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8679 (match_operand:SI 8 "gpc_reg_operand" "r"))
8680 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8681 (match_operand:SI 9 "gpc_reg_operand" "r"))
8682 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8683 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8684 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8685 "{stsi|stswi} %2,%1,%O0"
8686 [(set_attr "type" "store")])
8688 (define_insn "*stmsi7"
8689 [(match_parallel 0 "store_multiple_operation"
8690 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8691 (match_operand:SI 2 "gpc_reg_operand" "r"))
8692 (clobber (match_scratch:SI 3 "X"))
8693 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8694 (match_operand:SI 4 "gpc_reg_operand" "r"))
8695 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8696 (match_operand:SI 5 "gpc_reg_operand" "r"))
8697 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8698 (match_operand:SI 6 "gpc_reg_operand" "r"))
8699 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8700 (match_operand:SI 7 "gpc_reg_operand" "r"))
8701 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8702 (match_operand:SI 8 "gpc_reg_operand" "r"))
8703 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8704 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8705 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8706 "{stsi|stswi} %2,%1,%O0"
8707 [(set_attr "type" "store")])
8709 (define_insn "*stmsi6"
8710 [(match_parallel 0 "store_multiple_operation"
8711 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8712 (match_operand:SI 2 "gpc_reg_operand" "r"))
8713 (clobber (match_scratch:SI 3 "X"))
8714 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8715 (match_operand:SI 4 "gpc_reg_operand" "r"))
8716 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8717 (match_operand:SI 5 "gpc_reg_operand" "r"))
8718 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8719 (match_operand:SI 6 "gpc_reg_operand" "r"))
8720 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8721 (match_operand:SI 7 "gpc_reg_operand" "r"))
8722 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8723 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8724 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8725 "{stsi|stswi} %2,%1,%O0"
8726 [(set_attr "type" "store")])
8728 (define_insn "*stmsi5"
8729 [(match_parallel 0 "store_multiple_operation"
8730 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8731 (match_operand:SI 2 "gpc_reg_operand" "r"))
8732 (clobber (match_scratch:SI 3 "X"))
8733 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8734 (match_operand:SI 4 "gpc_reg_operand" "r"))
8735 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8736 (match_operand:SI 5 "gpc_reg_operand" "r"))
8737 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8738 (match_operand:SI 6 "gpc_reg_operand" "r"))
8739 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8740 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8741 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8742 "{stsi|stswi} %2,%1,%O0"
8743 [(set_attr "type" "store")])
8745 (define_insn "*stmsi4"
8746 [(match_parallel 0 "store_multiple_operation"
8747 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8748 (match_operand:SI 2 "gpc_reg_operand" "r"))
8749 (clobber (match_scratch:SI 3 "X"))
8750 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8751 (match_operand:SI 4 "gpc_reg_operand" "r"))
8752 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8753 (match_operand:SI 5 "gpc_reg_operand" "r"))
8754 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8755 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
8756 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
8757 "{stsi|stswi} %2,%1,%O0"
8758 [(set_attr "type" "store")])
8760 (define_insn "*stmsi3"
8761 [(match_parallel 0 "store_multiple_operation"
8762 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8763 (match_operand:SI 2 "gpc_reg_operand" "r"))
8764 (clobber (match_scratch:SI 3 "X"))
8765 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8766 (match_operand:SI 4 "gpc_reg_operand" "r"))
8767 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8768 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
8769 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
8770 "{stsi|stswi} %2,%1,%O0"
8771 [(set_attr "type" "store")])
8773 (define_expand "clrmemsi"
8774 [(parallel [(set (match_operand:BLK 0 "" "")
8776 (use (match_operand:SI 1 "" ""))
8777 (use (match_operand:SI 2 "" ""))])]
8781 if (expand_block_clear (operands))
8787 ;; String/block move insn.
8788 ;; Argument 0 is the destination
8789 ;; Argument 1 is the source
8790 ;; Argument 2 is the length
8791 ;; Argument 3 is the alignment
8793 (define_expand "movmemsi"
8794 [(parallel [(set (match_operand:BLK 0 "" "")
8795 (match_operand:BLK 1 "" ""))
8796 (use (match_operand:SI 2 "" ""))
8797 (use (match_operand:SI 3 "" ""))])]
8801 if (expand_block_move (operands))
8807 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
8808 ;; register allocator doesn't have a clue about allocating 8 word registers.
8809 ;; rD/rS = r5 is preferred, efficient form.
8810 (define_expand "movmemsi_8reg"
8811 [(parallel [(set (match_operand 0 "" "")
8812 (match_operand 1 "" ""))
8813 (use (match_operand 2 "" ""))
8814 (use (match_operand 3 "" ""))
8815 (clobber (reg:SI 5))
8816 (clobber (reg:SI 6))
8817 (clobber (reg:SI 7))
8818 (clobber (reg:SI 8))
8819 (clobber (reg:SI 9))
8820 (clobber (reg:SI 10))
8821 (clobber (reg:SI 11))
8822 (clobber (reg:SI 12))
8823 (clobber (match_scratch:SI 4 ""))])]
8828 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8829 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8830 (use (match_operand:SI 2 "immediate_operand" "i"))
8831 (use (match_operand:SI 3 "immediate_operand" "i"))
8832 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8833 (clobber (reg:SI 6))
8834 (clobber (reg:SI 7))
8835 (clobber (reg:SI 8))
8836 (clobber (reg:SI 9))
8837 (clobber (reg:SI 10))
8838 (clobber (reg:SI 11))
8839 (clobber (reg:SI 12))
8840 (clobber (match_scratch:SI 5 "=q"))]
8841 "TARGET_STRING && TARGET_POWER
8842 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8843 || INTVAL (operands[2]) == 0)
8844 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8845 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8846 && REGNO (operands[4]) == 5"
8847 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8848 [(set_attr "type" "load")
8849 (set_attr "length" "8")])
8852 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8853 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8854 (use (match_operand:SI 2 "immediate_operand" "i"))
8855 (use (match_operand:SI 3 "immediate_operand" "i"))
8856 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8857 (clobber (reg:SI 6))
8858 (clobber (reg:SI 7))
8859 (clobber (reg:SI 8))
8860 (clobber (reg:SI 9))
8861 (clobber (reg:SI 10))
8862 (clobber (reg:SI 11))
8863 (clobber (reg:SI 12))
8864 (clobber (match_scratch:SI 5 "X"))]
8865 "TARGET_STRING && ! TARGET_POWER
8866 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8867 || INTVAL (operands[2]) == 0)
8868 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8869 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8870 && REGNO (operands[4]) == 5"
8871 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8872 [(set_attr "type" "load")
8873 (set_attr "length" "8")])
8876 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
8877 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
8878 (use (match_operand:SI 2 "immediate_operand" "i"))
8879 (use (match_operand:SI 3 "immediate_operand" "i"))
8880 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8881 (clobber (reg:SI 6))
8882 (clobber (reg:SI 7))
8883 (clobber (reg:SI 8))
8884 (clobber (reg:SI 9))
8885 (clobber (reg:SI 10))
8886 (clobber (reg:SI 11))
8887 (clobber (reg:SI 12))
8888 (clobber (match_scratch:SI 5 "X"))]
8889 "TARGET_STRING && TARGET_POWERPC64
8890 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8891 || INTVAL (operands[2]) == 0)
8892 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8893 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8894 && REGNO (operands[4]) == 5"
8895 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8896 [(set_attr "type" "load")
8897 (set_attr "length" "8")])
8899 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
8900 ;; register allocator doesn't have a clue about allocating 6 word registers.
8901 ;; rD/rS = r5 is preferred, efficient form.
8902 (define_expand "movmemsi_6reg"
8903 [(parallel [(set (match_operand 0 "" "")
8904 (match_operand 1 "" ""))
8905 (use (match_operand 2 "" ""))
8906 (use (match_operand 3 "" ""))
8907 (clobber (reg:SI 5))
8908 (clobber (reg:SI 6))
8909 (clobber (reg:SI 7))
8910 (clobber (reg:SI 8))
8911 (clobber (reg:SI 9))
8912 (clobber (reg:SI 10))
8913 (clobber (match_scratch:SI 4 ""))])]
8918 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8919 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8920 (use (match_operand:SI 2 "immediate_operand" "i"))
8921 (use (match_operand:SI 3 "immediate_operand" "i"))
8922 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8923 (clobber (reg:SI 6))
8924 (clobber (reg:SI 7))
8925 (clobber (reg:SI 8))
8926 (clobber (reg:SI 9))
8927 (clobber (reg:SI 10))
8928 (clobber (match_scratch:SI 5 "=q"))]
8929 "TARGET_STRING && TARGET_POWER
8930 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
8931 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8932 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8933 && REGNO (operands[4]) == 5"
8934 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8935 [(set_attr "type" "load")
8936 (set_attr "length" "8")])
8939 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8940 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8941 (use (match_operand:SI 2 "immediate_operand" "i"))
8942 (use (match_operand:SI 3 "immediate_operand" "i"))
8943 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8944 (clobber (reg:SI 6))
8945 (clobber (reg:SI 7))
8946 (clobber (reg:SI 8))
8947 (clobber (reg:SI 9))
8948 (clobber (reg:SI 10))
8949 (clobber (match_scratch:SI 5 "X"))]
8950 "TARGET_STRING && ! TARGET_POWER
8951 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
8952 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8953 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8954 && REGNO (operands[4]) == 5"
8955 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8956 [(set_attr "type" "load")
8957 (set_attr "length" "8")])
8960 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
8961 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
8962 (use (match_operand:SI 2 "immediate_operand" "i"))
8963 (use (match_operand:SI 3 "immediate_operand" "i"))
8964 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8965 (clobber (reg:SI 6))
8966 (clobber (reg:SI 7))
8967 (clobber (reg:SI 8))
8968 (clobber (reg:SI 9))
8969 (clobber (reg:SI 10))
8970 (clobber (match_scratch:SI 5 "X"))]
8971 "TARGET_STRING && TARGET_POWERPC64
8972 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
8973 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8974 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8975 && REGNO (operands[4]) == 5"
8976 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8977 [(set_attr "type" "load")
8978 (set_attr "length" "8")])
8980 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
8981 ;; problems with TImode.
8982 ;; rD/rS = r5 is preferred, efficient form.
8983 (define_expand "movmemsi_4reg"
8984 [(parallel [(set (match_operand 0 "" "")
8985 (match_operand 1 "" ""))
8986 (use (match_operand 2 "" ""))
8987 (use (match_operand 3 "" ""))
8988 (clobber (reg:SI 5))
8989 (clobber (reg:SI 6))
8990 (clobber (reg:SI 7))
8991 (clobber (reg:SI 8))
8992 (clobber (match_scratch:SI 4 ""))])]
8997 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8998 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8999 (use (match_operand:SI 2 "immediate_operand" "i"))
9000 (use (match_operand:SI 3 "immediate_operand" "i"))
9001 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9002 (clobber (reg:SI 6))
9003 (clobber (reg:SI 7))
9004 (clobber (reg:SI 8))
9005 (clobber (match_scratch:SI 5 "=q"))]
9006 "TARGET_STRING && TARGET_POWER
9007 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9008 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9009 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9010 && REGNO (operands[4]) == 5"
9011 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9012 [(set_attr "type" "load")
9013 (set_attr "length" "8")])
9016 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9017 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9018 (use (match_operand:SI 2 "immediate_operand" "i"))
9019 (use (match_operand:SI 3 "immediate_operand" "i"))
9020 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9021 (clobber (reg:SI 6))
9022 (clobber (reg:SI 7))
9023 (clobber (reg:SI 8))
9024 (clobber (match_scratch:SI 5 "X"))]
9025 "TARGET_STRING && ! TARGET_POWER
9026 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9027 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9028 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9029 && REGNO (operands[4]) == 5"
9030 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9031 [(set_attr "type" "load")
9032 (set_attr "length" "8")])
9035 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9036 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9037 (use (match_operand:SI 2 "immediate_operand" "i"))
9038 (use (match_operand:SI 3 "immediate_operand" "i"))
9039 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9040 (clobber (reg:SI 6))
9041 (clobber (reg:SI 7))
9042 (clobber (reg:SI 8))
9043 (clobber (match_scratch:SI 5 "X"))]
9044 "TARGET_STRING && TARGET_POWERPC64
9045 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9046 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9047 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9048 && REGNO (operands[4]) == 5"
9049 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9050 [(set_attr "type" "load")
9051 (set_attr "length" "8")])
9053 ;; Move up to 8 bytes at a time.
9054 (define_expand "movmemsi_2reg"
9055 [(parallel [(set (match_operand 0 "" "")
9056 (match_operand 1 "" ""))
9057 (use (match_operand 2 "" ""))
9058 (use (match_operand 3 "" ""))
9059 (clobber (match_scratch:DI 4 ""))
9060 (clobber (match_scratch:SI 5 ""))])]
9061 "TARGET_STRING && ! TARGET_POWERPC64"
9065 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9066 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9067 (use (match_operand:SI 2 "immediate_operand" "i"))
9068 (use (match_operand:SI 3 "immediate_operand" "i"))
9069 (clobber (match_scratch:DI 4 "=&r"))
9070 (clobber (match_scratch:SI 5 "=q"))]
9071 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9072 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9073 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9074 [(set_attr "type" "load")
9075 (set_attr "length" "8")])
9078 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9079 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9080 (use (match_operand:SI 2 "immediate_operand" "i"))
9081 (use (match_operand:SI 3 "immediate_operand" "i"))
9082 (clobber (match_scratch:DI 4 "=&r"))
9083 (clobber (match_scratch:SI 5 "X"))]
9084 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9085 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9086 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9087 [(set_attr "type" "load")
9088 (set_attr "length" "8")])
9090 ;; Move up to 4 bytes at a time.
9091 (define_expand "movmemsi_1reg"
9092 [(parallel [(set (match_operand 0 "" "")
9093 (match_operand 1 "" ""))
9094 (use (match_operand 2 "" ""))
9095 (use (match_operand 3 "" ""))
9096 (clobber (match_scratch:SI 4 ""))
9097 (clobber (match_scratch:SI 5 ""))])]
9102 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9103 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9104 (use (match_operand:SI 2 "immediate_operand" "i"))
9105 (use (match_operand:SI 3 "immediate_operand" "i"))
9106 (clobber (match_scratch:SI 4 "=&r"))
9107 (clobber (match_scratch:SI 5 "=q"))]
9108 "TARGET_STRING && TARGET_POWER
9109 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9110 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9111 [(set_attr "type" "load")
9112 (set_attr "length" "8")])
9115 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9116 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9117 (use (match_operand:SI 2 "immediate_operand" "i"))
9118 (use (match_operand:SI 3 "immediate_operand" "i"))
9119 (clobber (match_scratch:SI 4 "=&r"))
9120 (clobber (match_scratch:SI 5 "X"))]
9121 "TARGET_STRING && ! TARGET_POWER
9122 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9123 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9124 [(set_attr "type" "load")
9125 (set_attr "length" "8")])
9128 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9129 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9130 (use (match_operand:SI 2 "immediate_operand" "i"))
9131 (use (match_operand:SI 3 "immediate_operand" "i"))
9132 (clobber (match_scratch:SI 4 "=&r"))
9133 (clobber (match_scratch:SI 5 "X"))]
9134 "TARGET_STRING && TARGET_POWERPC64
9135 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9136 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9137 [(set_attr "type" "load")
9138 (set_attr "length" "8")])
9141 ;; Define insns that do load or store with update. Some of these we can
9142 ;; get by using pre-decrement or pre-increment, but the hardware can also
9143 ;; do cases where the increment is not the size of the object.
9145 ;; In all these cases, we use operands 0 and 1 for the register being
9146 ;; incremented because those are the operands that local-alloc will
9147 ;; tie and these are the pair most likely to be tieable (and the ones
9148 ;; that will benefit the most).
9150 (define_insn "*movdi_update1"
9151 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9152 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9153 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9154 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9155 (plus:DI (match_dup 1) (match_dup 2)))]
9156 "TARGET_POWERPC64 && TARGET_UPDATE"
9160 [(set_attr "type" "load_ux,load_u")])
9162 (define_insn "movdi_<mode>_update"
9163 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9164 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9165 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9166 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9167 (plus:P (match_dup 1) (match_dup 2)))]
9168 "TARGET_POWERPC64 && TARGET_UPDATE"
9172 [(set_attr "type" "store_ux,store_u")])
9174 (define_insn "*movsi_update1"
9175 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9176 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9177 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9178 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9179 (plus:SI (match_dup 1) (match_dup 2)))]
9182 {lux|lwzux} %3,%0,%2
9183 {lu|lwzu} %3,%2(%0)"
9184 [(set_attr "type" "load_ux,load_u")])
9186 (define_insn "*movsi_update2"
9187 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9189 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9190 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9191 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9192 (plus:DI (match_dup 1) (match_dup 2)))]
9195 [(set_attr "type" "load_ext_ux")])
9197 (define_insn "movsi_update"
9198 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9199 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9200 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9201 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9202 (plus:SI (match_dup 1) (match_dup 2)))]
9205 {stux|stwux} %3,%0,%2
9206 {stu|stwu} %3,%2(%0)"
9207 [(set_attr "type" "store_ux,store_u")])
9209 (define_insn "*movhi_update1"
9210 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9211 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9212 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9213 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9214 (plus:SI (match_dup 1) (match_dup 2)))]
9219 [(set_attr "type" "load_ux,load_u")])
9221 (define_insn "*movhi_update2"
9222 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9224 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9225 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9226 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9227 (plus:SI (match_dup 1) (match_dup 2)))]
9232 [(set_attr "type" "load_ux,load_u")])
9234 (define_insn "*movhi_update3"
9235 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9237 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9238 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9239 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9240 (plus:SI (match_dup 1) (match_dup 2)))]
9245 [(set_attr "type" "load_ext_ux,load_ext_u")])
9247 (define_insn "*movhi_update4"
9248 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9249 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9250 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9251 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9252 (plus:SI (match_dup 1) (match_dup 2)))]
9257 [(set_attr "type" "store_ux,store_u")])
9259 (define_insn "*movqi_update1"
9260 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9261 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9262 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9263 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9264 (plus:SI (match_dup 1) (match_dup 2)))]
9269 [(set_attr "type" "load_ux,load_u")])
9271 (define_insn "*movqi_update2"
9272 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9274 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9275 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9276 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9277 (plus:SI (match_dup 1) (match_dup 2)))]
9282 [(set_attr "type" "load_ux,load_u")])
9284 (define_insn "*movqi_update3"
9285 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9286 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9287 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9288 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9289 (plus:SI (match_dup 1) (match_dup 2)))]
9294 [(set_attr "type" "store_ux,store_u")])
9296 (define_insn "*movsf_update1"
9297 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9298 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9299 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9300 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9301 (plus:SI (match_dup 1) (match_dup 2)))]
9302 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9306 [(set_attr "type" "fpload_ux,fpload_u")])
9308 (define_insn "*movsf_update2"
9309 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9310 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9311 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9312 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9313 (plus:SI (match_dup 1) (match_dup 2)))]
9314 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9318 [(set_attr "type" "fpstore_ux,fpstore_u")])
9320 (define_insn "*movsf_update3"
9321 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9322 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9323 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9324 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9325 (plus:SI (match_dup 1) (match_dup 2)))]
9326 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9328 {lux|lwzux} %3,%0,%2
9329 {lu|lwzu} %3,%2(%0)"
9330 [(set_attr "type" "load_ux,load_u")])
9332 (define_insn "*movsf_update4"
9333 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9334 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9335 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9336 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9337 (plus:SI (match_dup 1) (match_dup 2)))]
9338 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9340 {stux|stwux} %3,%0,%2
9341 {stu|stwu} %3,%2(%0)"
9342 [(set_attr "type" "store_ux,store_u")])
9344 (define_insn "*movdf_update1"
9345 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9346 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9347 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9348 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9349 (plus:SI (match_dup 1) (match_dup 2)))]
9350 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9354 [(set_attr "type" "fpload_ux,fpload_u")])
9356 (define_insn "*movdf_update2"
9357 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9358 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9359 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9360 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9361 (plus:SI (match_dup 1) (match_dup 2)))]
9362 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9366 [(set_attr "type" "fpstore_ux,fpstore_u")])
9368 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9370 (define_insn "*lfq_power2"
9371 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
9372 (match_operand:TF 1 "memory_operand" ""))]
9374 && TARGET_HARD_FLOAT && TARGET_FPRS"
9378 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9379 (match_operand:DF 1 "memory_operand" ""))
9380 (set (match_operand:DF 2 "gpc_reg_operand" "")
9381 (match_operand:DF 3 "memory_operand" ""))]
9383 && TARGET_HARD_FLOAT && TARGET_FPRS
9384 && registers_ok_for_quad_peep (operands[0], operands[2])
9385 && mems_ok_for_quad_peep (operands[1], operands[3])"
9388 "operands[1] = widen_memory_access (operands[1], TFmode, 0);
9389 operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));")
9391 (define_insn "*stfq_power2"
9392 [(set (match_operand:TF 0 "memory_operand" "")
9393 (match_operand:TF 1 "gpc_reg_operand" "f"))]
9395 && TARGET_HARD_FLOAT && TARGET_FPRS"
9400 [(set (match_operand:DF 0 "memory_operand" "")
9401 (match_operand:DF 1 "gpc_reg_operand" ""))
9402 (set (match_operand:DF 2 "memory_operand" "")
9403 (match_operand:DF 3 "gpc_reg_operand" ""))]
9405 && TARGET_HARD_FLOAT && TARGET_FPRS
9406 && registers_ok_for_quad_peep (operands[1], operands[3])
9407 && mems_ok_for_quad_peep (operands[0], operands[2])"
9410 "operands[0] = widen_memory_access (operands[0], TFmode, 0);
9411 operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));")
9413 ;; after inserting conditional returns we can sometimes have
9414 ;; unnecessary register moves. Unfortunately we cannot have a
9415 ;; modeless peephole here, because some single SImode sets have early
9416 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9417 ;; sequences, using get_attr_length here will smash the operands
9418 ;; array. Neither is there an early_cobbler_p predicate.
9420 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9421 (match_operand:DF 1 "any_operand" ""))
9422 (set (match_operand:DF 2 "gpc_reg_operand" "")
9424 "peep2_reg_dead_p (2, operands[0])"
9425 [(set (match_dup 2) (match_dup 1))])
9428 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9429 (match_operand:SF 1 "any_operand" ""))
9430 (set (match_operand:SF 2 "gpc_reg_operand" "")
9432 "peep2_reg_dead_p (2, operands[0])"
9433 [(set (match_dup 2) (match_dup 1))])
9438 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9439 (define_insn "tls_gd_32"
9440 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9441 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9442 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9444 "HAVE_AS_TLS && !TARGET_64BIT"
9445 "addi %0,%1,%2@got@tlsgd")
9447 (define_insn "tls_gd_64"
9448 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9449 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9450 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9452 "HAVE_AS_TLS && TARGET_64BIT"
9453 "addi %0,%1,%2@got@tlsgd")
9455 (define_insn "tls_ld_32"
9456 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9457 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9459 "HAVE_AS_TLS && !TARGET_64BIT"
9460 "addi %0,%1,%&@got@tlsld")
9462 (define_insn "tls_ld_64"
9463 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9464 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9466 "HAVE_AS_TLS && TARGET_64BIT"
9467 "addi %0,%1,%&@got@tlsld")
9469 (define_insn "tls_dtprel_32"
9470 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9471 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9472 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9474 "HAVE_AS_TLS && !TARGET_64BIT"
9475 "addi %0,%1,%2@dtprel")
9477 (define_insn "tls_dtprel_64"
9478 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9479 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9480 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9482 "HAVE_AS_TLS && TARGET_64BIT"
9483 "addi %0,%1,%2@dtprel")
9485 (define_insn "tls_dtprel_ha_32"
9486 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9487 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9488 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9489 UNSPEC_TLSDTPRELHA))]
9490 "HAVE_AS_TLS && !TARGET_64BIT"
9491 "addis %0,%1,%2@dtprel@ha")
9493 (define_insn "tls_dtprel_ha_64"
9494 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9495 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9496 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9497 UNSPEC_TLSDTPRELHA))]
9498 "HAVE_AS_TLS && TARGET_64BIT"
9499 "addis %0,%1,%2@dtprel@ha")
9501 (define_insn "tls_dtprel_lo_32"
9502 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9503 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9504 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9505 UNSPEC_TLSDTPRELLO))]
9506 "HAVE_AS_TLS && !TARGET_64BIT"
9507 "addi %0,%1,%2@dtprel@l")
9509 (define_insn "tls_dtprel_lo_64"
9510 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9511 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9512 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9513 UNSPEC_TLSDTPRELLO))]
9514 "HAVE_AS_TLS && TARGET_64BIT"
9515 "addi %0,%1,%2@dtprel@l")
9517 (define_insn "tls_got_dtprel_32"
9518 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9519 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9520 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9521 UNSPEC_TLSGOTDTPREL))]
9522 "HAVE_AS_TLS && !TARGET_64BIT"
9523 "lwz %0,%2@got@dtprel(%1)")
9525 (define_insn "tls_got_dtprel_64"
9526 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9527 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9528 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9529 UNSPEC_TLSGOTDTPREL))]
9530 "HAVE_AS_TLS && TARGET_64BIT"
9531 "ld %0,%2@got@dtprel(%1)")
9533 (define_insn "tls_tprel_32"
9534 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9535 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9536 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9538 "HAVE_AS_TLS && !TARGET_64BIT"
9539 "addi %0,%1,%2@tprel")
9541 (define_insn "tls_tprel_64"
9542 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9543 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9544 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9546 "HAVE_AS_TLS && TARGET_64BIT"
9547 "addi %0,%1,%2@tprel")
9549 (define_insn "tls_tprel_ha_32"
9550 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9551 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9552 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9553 UNSPEC_TLSTPRELHA))]
9554 "HAVE_AS_TLS && !TARGET_64BIT"
9555 "addis %0,%1,%2@tprel@ha")
9557 (define_insn "tls_tprel_ha_64"
9558 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9559 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9560 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9561 UNSPEC_TLSTPRELHA))]
9562 "HAVE_AS_TLS && TARGET_64BIT"
9563 "addis %0,%1,%2@tprel@ha")
9565 (define_insn "tls_tprel_lo_32"
9566 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9567 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9568 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9569 UNSPEC_TLSTPRELLO))]
9570 "HAVE_AS_TLS && !TARGET_64BIT"
9571 "addi %0,%1,%2@tprel@l")
9573 (define_insn "tls_tprel_lo_64"
9574 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9575 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9576 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9577 UNSPEC_TLSTPRELLO))]
9578 "HAVE_AS_TLS && TARGET_64BIT"
9579 "addi %0,%1,%2@tprel@l")
9581 ;; "b" output constraint here and on tls_tls input to support linker tls
9582 ;; optimization. The linker may edit the instructions emitted by a
9583 ;; tls_got_tprel/tls_tls pair to addis,addi.
9584 (define_insn "tls_got_tprel_32"
9585 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9586 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9587 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9588 UNSPEC_TLSGOTTPREL))]
9589 "HAVE_AS_TLS && !TARGET_64BIT"
9590 "lwz %0,%2@got@tprel(%1)")
9592 (define_insn "tls_got_tprel_64"
9593 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9594 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9595 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9596 UNSPEC_TLSGOTTPREL))]
9597 "HAVE_AS_TLS && TARGET_64BIT"
9598 "ld %0,%2@got@tprel(%1)")
9600 (define_insn "tls_tls_32"
9601 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9602 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9603 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9605 "HAVE_AS_TLS && !TARGET_64BIT"
9608 (define_insn "tls_tls_64"
9609 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9610 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9611 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9613 "HAVE_AS_TLS && TARGET_64BIT"
9616 ;; Next come insns related to the calling sequence.
9618 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9619 ;; We move the back-chain and decrement the stack pointer.
9621 (define_expand "allocate_stack"
9622 [(set (match_operand 0 "gpc_reg_operand" "=r")
9623 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9625 (minus (reg 1) (match_dup 1)))]
9628 { rtx chain = gen_reg_rtx (Pmode);
9629 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9632 emit_move_insn (chain, stack_bot);
9634 /* Check stack bounds if necessary. */
9635 if (current_function_limit_stack)
9638 available = expand_binop (Pmode, sub_optab,
9639 stack_pointer_rtx, stack_limit_rtx,
9640 NULL_RTX, 1, OPTAB_WIDEN);
9641 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9644 if (GET_CODE (operands[1]) != CONST_INT
9645 || INTVAL (operands[1]) < -32767
9646 || INTVAL (operands[1]) > 32768)
9648 neg_op0 = gen_reg_rtx (Pmode);
9650 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9652 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9655 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9658 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
9659 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9663 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9664 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9665 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9668 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9672 ;; These patterns say how to save and restore the stack pointer. We need not
9673 ;; save the stack pointer at function level since we are careful to
9674 ;; preserve the backchain. At block level, we have to restore the backchain
9675 ;; when we restore the stack pointer.
9677 ;; For nonlocal gotos, we must save both the stack pointer and its
9678 ;; backchain and restore both. Note that in the nonlocal case, the
9679 ;; save area is a memory location.
9681 (define_expand "save_stack_function"
9682 [(match_operand 0 "any_operand" "")
9683 (match_operand 1 "any_operand" "")]
9687 (define_expand "restore_stack_function"
9688 [(match_operand 0 "any_operand" "")
9689 (match_operand 1 "any_operand" "")]
9693 (define_expand "restore_stack_block"
9694 [(use (match_operand 0 "register_operand" ""))
9695 (set (match_dup 2) (match_dup 3))
9696 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9697 (set (match_dup 3) (match_dup 2))]
9701 operands[2] = gen_reg_rtx (Pmode);
9702 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9705 (define_expand "save_stack_nonlocal"
9706 [(match_operand 0 "memory_operand" "")
9707 (match_operand 1 "register_operand" "")]
9711 rtx temp = gen_reg_rtx (Pmode);
9712 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9714 /* Copy the backchain to the first word, sp to the second. */
9715 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9716 emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp);
9717 emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word),
9722 (define_expand "restore_stack_nonlocal"
9723 [(match_operand 0 "register_operand" "")
9724 (match_operand 1 "memory_operand" "")]
9728 rtx temp = gen_reg_rtx (Pmode);
9729 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9731 /* Restore the backchain from the first word, sp from the second. */
9732 emit_move_insn (temp,
9733 adjust_address_nv (operands[1], Pmode, 0));
9734 emit_move_insn (operands[0],
9735 adjust_address_nv (operands[1], Pmode, units_per_word));
9736 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
9740 ;; TOC register handling.
9742 ;; Code to initialize the TOC register...
9744 (define_insn "load_toc_aix_si"
9745 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9746 (unspec:SI [(const_int 0)] UNSPEC_TOC))
9748 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
9752 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9753 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9754 operands[2] = gen_rtx_REG (Pmode, 2);
9755 return \"{l|lwz} %0,%1(%2)\";
9757 [(set_attr "type" "load")])
9759 (define_insn "load_toc_aix_di"
9760 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9761 (unspec:DI [(const_int 0)] UNSPEC_TOC))
9763 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9767 #ifdef TARGET_RELOCATABLE
9768 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9769 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9771 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9774 strcat (buf, \"@toc\");
9775 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9776 operands[2] = gen_rtx_REG (Pmode, 2);
9777 return \"ld %0,%1(%2)\";
9779 [(set_attr "type" "load")])
9781 (define_insn "load_toc_v4_pic_si"
9782 [(set (match_operand:SI 0 "register_operand" "=l")
9783 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
9784 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9785 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9786 [(set_attr "type" "branch")
9787 (set_attr "length" "4")])
9789 (define_insn "load_toc_v4_PIC_1"
9790 [(set (match_operand:SI 0 "register_operand" "=l")
9791 (match_operand:SI 1 "immediate_operand" "s"))
9792 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
9793 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
9794 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
9795 "bcl 20,31,%1\\n%1:"
9796 [(set_attr "type" "branch")
9797 (set_attr "length" "4")])
9799 (define_insn "load_toc_v4_PIC_1b"
9800 [(set (match_operand:SI 0 "register_operand" "=l")
9801 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
9803 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9804 "bcl 20,31,$+8\\n\\t.long %1-$"
9805 [(set_attr "type" "branch")
9806 (set_attr "length" "8")])
9808 (define_insn "load_toc_v4_PIC_2"
9809 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9810 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9811 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9812 (match_operand:SI 3 "immediate_operand" "s")))))]
9813 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9814 "{l|lwz} %0,%2-%3(%1)"
9815 [(set_attr "type" "load")])
9817 (define_insn "load_toc_v4_PIC_3b"
9818 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9819 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9821 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9822 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
9823 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9824 "{cau|addis} %0,%1,%2-%3@ha")
9826 (define_insn "load_toc_v4_PIC_3c"
9827 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9828 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9829 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9830 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
9831 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9832 "{cal|addi} %0,%1,%2-%3@l")
9834 ;; If the TOC is shared over a translation unit, as happens with all
9835 ;; the kinds of PIC that we support, we need to restore the TOC
9836 ;; pointer only when jumping over units of translation.
9837 ;; On Darwin, we need to reload the picbase.
9839 (define_expand "builtin_setjmp_receiver"
9840 [(use (label_ref (match_operand 0 "" "")))]
9841 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9842 || (TARGET_TOC && TARGET_MINIMAL_TOC)
9843 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9847 if (DEFAULT_ABI == ABI_DARWIN)
9849 const char *picbase = machopic_function_base_name ();
9850 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
9851 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9855 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
9856 CODE_LABEL_NUMBER (operands[0]));
9857 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
9859 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
9860 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
9864 rs6000_emit_load_toc_table (FALSE);
9868 ;; Elf specific ways of loading addresses for non-PIC code.
9869 ;; The output of this could be r0, but we make a very strong
9870 ;; preference for a base register because it will usually
9872 (define_insn "elf_high"
9873 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
9874 (high:SI (match_operand 1 "" "")))]
9875 "TARGET_ELF && ! TARGET_64BIT"
9876 "{liu|lis} %0,%1@ha")
9878 (define_insn "elf_low"
9879 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9880 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
9881 (match_operand 2 "" "")))]
9882 "TARGET_ELF && ! TARGET_64BIT"
9884 {cal|la} %0,%2@l(%1)
9885 {ai|addic} %0,%1,%K2")
9887 ;; A function pointer under AIX is a pointer to a data area whose first word
9888 ;; contains the actual address of the function, whose second word contains a
9889 ;; pointer to its TOC, and whose third word contains a value to place in the
9890 ;; static chain register (r11). Note that if we load the static chain, our
9891 ;; "trampoline" need not have any executable code.
9893 (define_expand "call_indirect_aix32"
9895 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
9896 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9899 (mem:SI (plus:SI (match_dup 0)
9902 (mem:SI (plus:SI (match_dup 0)
9904 (parallel [(call (mem:SI (match_dup 2))
9905 (match_operand 1 "" ""))
9909 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9910 (clobber (scratch:SI))])]
9913 { operands[2] = gen_reg_rtx (SImode); }")
9915 (define_expand "call_indirect_aix64"
9917 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
9918 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9921 (mem:DI (plus:DI (match_dup 0)
9924 (mem:DI (plus:DI (match_dup 0)
9926 (parallel [(call (mem:SI (match_dup 2))
9927 (match_operand 1 "" ""))
9931 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9932 (clobber (scratch:SI))])]
9935 { operands[2] = gen_reg_rtx (DImode); }")
9937 (define_expand "call_value_indirect_aix32"
9939 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
9940 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9943 (mem:SI (plus:SI (match_dup 1)
9946 (mem:SI (plus:SI (match_dup 1)
9948 (parallel [(set (match_operand 0 "" "")
9949 (call (mem:SI (match_dup 3))
9950 (match_operand 2 "" "")))
9954 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9955 (clobber (scratch:SI))])]
9958 { operands[3] = gen_reg_rtx (SImode); }")
9960 (define_expand "call_value_indirect_aix64"
9962 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
9963 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9966 (mem:DI (plus:DI (match_dup 1)
9969 (mem:DI (plus:DI (match_dup 1)
9971 (parallel [(set (match_operand 0 "" "")
9972 (call (mem:SI (match_dup 3))
9973 (match_operand 2 "" "")))
9977 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9978 (clobber (scratch:SI))])]
9981 { operands[3] = gen_reg_rtx (DImode); }")
9983 ;; Now the definitions for the call and call_value insns
9984 (define_expand "call"
9985 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
9986 (match_operand 1 "" ""))
9987 (use (match_operand 2 "" ""))
9988 (clobber (scratch:SI))])]
9993 if (MACHOPIC_INDIRECT)
9994 operands[0] = machopic_indirect_call_target (operands[0]);
9997 gcc_assert (GET_CODE (operands[0]) == MEM);
9998 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10000 operands[0] = XEXP (operands[0], 0);
10002 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10004 && GET_CODE (operands[0]) == SYMBOL_REF
10005 && !SYMBOL_REF_LOCAL_P (operands[0]))
10010 tmp = gen_rtvec (3,
10011 gen_rtx_CALL (VOIDmode,
10012 gen_rtx_MEM (SImode, operands[0]),
10014 gen_rtx_USE (VOIDmode, operands[2]),
10015 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10016 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10017 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10021 if (GET_CODE (operands[0]) != SYMBOL_REF
10022 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10023 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10025 if (INTVAL (operands[2]) & CALL_LONG)
10026 operands[0] = rs6000_longcall_ref (operands[0]);
10028 switch (DEFAULT_ABI)
10032 operands[0] = force_reg (Pmode, operands[0]);
10036 /* AIX function pointers are really pointers to a three word
10038 emit_call_insn (TARGET_32BIT
10039 ? gen_call_indirect_aix32 (force_reg (SImode,
10042 : gen_call_indirect_aix64 (force_reg (DImode,
10048 gcc_unreachable ();
10053 (define_expand "call_value"
10054 [(parallel [(set (match_operand 0 "" "")
10055 (call (mem:SI (match_operand 1 "address_operand" ""))
10056 (match_operand 2 "" "")))
10057 (use (match_operand 3 "" ""))
10058 (clobber (scratch:SI))])]
10063 if (MACHOPIC_INDIRECT)
10064 operands[1] = machopic_indirect_call_target (operands[1]);
10067 gcc_assert (GET_CODE (operands[1]) == MEM);
10068 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10070 operands[1] = XEXP (operands[1], 0);
10072 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10074 && GET_CODE (operands[1]) == SYMBOL_REF
10075 && !SYMBOL_REF_LOCAL_P (operands[1]))
10080 tmp = gen_rtvec (3,
10081 gen_rtx_SET (VOIDmode,
10083 gen_rtx_CALL (VOIDmode,
10084 gen_rtx_MEM (SImode,
10087 gen_rtx_USE (VOIDmode, operands[3]),
10088 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10089 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10090 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10094 if (GET_CODE (operands[1]) != SYMBOL_REF
10095 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10096 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10098 if (INTVAL (operands[3]) & CALL_LONG)
10099 operands[1] = rs6000_longcall_ref (operands[1]);
10101 switch (DEFAULT_ABI)
10105 operands[1] = force_reg (Pmode, operands[1]);
10109 /* AIX function pointers are really pointers to a three word
10111 emit_call_insn (TARGET_32BIT
10112 ? gen_call_value_indirect_aix32 (operands[0],
10116 : gen_call_value_indirect_aix64 (operands[0],
10123 gcc_unreachable ();
10128 ;; Call to function in current module. No TOC pointer reload needed.
10129 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10130 ;; either the function was not prototyped, or it was prototyped as a
10131 ;; variable argument function. It is > 0 if FP registers were passed
10132 ;; and < 0 if they were not.
10134 (define_insn "*call_local32"
10135 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10136 (match_operand 1 "" "g,g"))
10137 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10138 (clobber (match_scratch:SI 3 "=l,l"))]
10139 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10142 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10143 output_asm_insn (\"crxor 6,6,6\", operands);
10145 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10146 output_asm_insn (\"creqv 6,6,6\", operands);
10148 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10150 [(set_attr "type" "branch")
10151 (set_attr "length" "4,8")])
10153 (define_insn "*call_local64"
10154 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10155 (match_operand 1 "" "g,g"))
10156 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10157 (clobber (match_scratch:SI 3 "=l,l"))]
10158 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10161 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10162 output_asm_insn (\"crxor 6,6,6\", operands);
10164 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10165 output_asm_insn (\"creqv 6,6,6\", operands);
10167 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10169 [(set_attr "type" "branch")
10170 (set_attr "length" "4,8")])
10172 (define_insn "*call_value_local32"
10173 [(set (match_operand 0 "" "")
10174 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10175 (match_operand 2 "" "g,g")))
10176 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10177 (clobber (match_scratch:SI 4 "=l,l"))]
10178 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10181 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10182 output_asm_insn (\"crxor 6,6,6\", operands);
10184 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10185 output_asm_insn (\"creqv 6,6,6\", operands);
10187 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10189 [(set_attr "type" "branch")
10190 (set_attr "length" "4,8")])
10193 (define_insn "*call_value_local64"
10194 [(set (match_operand 0 "" "")
10195 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10196 (match_operand 2 "" "g,g")))
10197 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10198 (clobber (match_scratch:SI 4 "=l,l"))]
10199 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10202 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10203 output_asm_insn (\"crxor 6,6,6\", operands);
10205 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10206 output_asm_insn (\"creqv 6,6,6\", operands);
10208 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10210 [(set_attr "type" "branch")
10211 (set_attr "length" "4,8")])
10213 ;; Call to function which may be in another module. Restore the TOC
10214 ;; pointer (r2) after the call unless this is System V.
10215 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10216 ;; either the function was not prototyped, or it was prototyped as a
10217 ;; variable argument function. It is > 0 if FP registers were passed
10218 ;; and < 0 if they were not.
10220 (define_insn "*call_indirect_nonlocal_aix32"
10221 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
10222 (match_operand 1 "" "g"))
10226 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10227 (clobber (match_scratch:SI 2 "=l"))]
10228 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10229 "b%T0l\;{l|lwz} 2,20(1)"
10230 [(set_attr "type" "jmpreg")
10231 (set_attr "length" "8")])
10233 (define_insn "*call_nonlocal_aix32"
10234 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10235 (match_operand 1 "" "g"))
10236 (use (match_operand:SI 2 "immediate_operand" "O"))
10237 (clobber (match_scratch:SI 3 "=l"))]
10239 && DEFAULT_ABI == ABI_AIX
10240 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10242 [(set_attr "type" "branch")
10243 (set_attr "length" "8")])
10245 (define_insn "*call_indirect_nonlocal_aix64"
10246 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
10247 (match_operand 1 "" "g"))
10251 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10252 (clobber (match_scratch:SI 2 "=l"))]
10253 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10254 "b%T0l\;ld 2,40(1)"
10255 [(set_attr "type" "jmpreg")
10256 (set_attr "length" "8")])
10258 (define_insn "*call_nonlocal_aix64"
10259 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10260 (match_operand 1 "" "g"))
10261 (use (match_operand:SI 2 "immediate_operand" "O"))
10262 (clobber (match_scratch:SI 3 "=l"))]
10264 && DEFAULT_ABI == ABI_AIX
10265 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10267 [(set_attr "type" "branch")
10268 (set_attr "length" "8")])
10270 (define_insn "*call_value_indirect_nonlocal_aix32"
10271 [(set (match_operand 0 "" "")
10272 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
10273 (match_operand 2 "" "g")))
10277 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10278 (clobber (match_scratch:SI 3 "=l"))]
10279 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10280 "b%T1l\;{l|lwz} 2,20(1)"
10281 [(set_attr "type" "jmpreg")
10282 (set_attr "length" "8")])
10284 (define_insn "*call_value_nonlocal_aix32"
10285 [(set (match_operand 0 "" "")
10286 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10287 (match_operand 2 "" "g")))
10288 (use (match_operand:SI 3 "immediate_operand" "O"))
10289 (clobber (match_scratch:SI 4 "=l"))]
10291 && DEFAULT_ABI == ABI_AIX
10292 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10294 [(set_attr "type" "branch")
10295 (set_attr "length" "8")])
10297 (define_insn "*call_value_indirect_nonlocal_aix64"
10298 [(set (match_operand 0 "" "")
10299 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10300 (match_operand 2 "" "g")))
10304 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10305 (clobber (match_scratch:SI 3 "=l"))]
10306 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10307 "b%T1l\;ld 2,40(1)"
10308 [(set_attr "type" "jmpreg")
10309 (set_attr "length" "8")])
10311 (define_insn "*call_value_nonlocal_aix64"
10312 [(set (match_operand 0 "" "")
10313 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10314 (match_operand 2 "" "g")))
10315 (use (match_operand:SI 3 "immediate_operand" "O"))
10316 (clobber (match_scratch:SI 4 "=l"))]
10318 && DEFAULT_ABI == ABI_AIX
10319 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10321 [(set_attr "type" "branch")
10322 (set_attr "length" "8")])
10324 ;; A function pointer under System V is just a normal pointer
10325 ;; operands[0] is the function pointer
10326 ;; operands[1] is the stack size to clean up
10327 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10328 ;; which indicates how to set cr1
10330 (define_insn "*call_indirect_nonlocal_sysv"
10331 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
10332 (match_operand 1 "" "g,g"))
10333 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10334 (clobber (match_scratch:SI 3 "=l,l"))]
10335 "DEFAULT_ABI == ABI_V4
10336 || DEFAULT_ABI == ABI_DARWIN"
10338 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10339 output_asm_insn ("crxor 6,6,6", operands);
10341 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10342 output_asm_insn ("creqv 6,6,6", operands);
10346 [(set_attr "type" "jmpreg,jmpreg")
10347 (set_attr "length" "4,8")])
10349 (define_insn "*call_nonlocal_sysv"
10350 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10351 (match_operand 1 "" "g,g"))
10352 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10353 (clobber (match_scratch:SI 3 "=l,l"))]
10354 "(DEFAULT_ABI == ABI_DARWIN
10355 || (DEFAULT_ABI == ABI_V4
10356 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10358 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10359 output_asm_insn ("crxor 6,6,6", operands);
10361 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10362 output_asm_insn ("creqv 6,6,6", operands);
10365 return output_call(insn, operands, 0, 2);
10367 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10369 if (TARGET_SECURE_PLT && flag_pic == 2)
10370 /* The magic 32768 offset here and in the other sysv call insns
10371 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10372 See sysv4.h:toc_section. */
10373 return "bl %z0+32768@plt";
10375 return "bl %z0@plt";
10381 [(set_attr "type" "branch,branch")
10382 (set_attr "length" "4,8")])
10384 (define_insn "*call_value_indirect_nonlocal_sysv"
10385 [(set (match_operand 0 "" "")
10386 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
10387 (match_operand 2 "" "g,g")))
10388 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10389 (clobber (match_scratch:SI 4 "=l,l"))]
10390 "DEFAULT_ABI == ABI_V4
10391 || DEFAULT_ABI == ABI_DARWIN"
10393 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10394 output_asm_insn ("crxor 6,6,6", operands);
10396 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10397 output_asm_insn ("creqv 6,6,6", operands);
10401 [(set_attr "type" "jmpreg,jmpreg")
10402 (set_attr "length" "4,8")])
10404 (define_insn "*call_value_nonlocal_sysv"
10405 [(set (match_operand 0 "" "")
10406 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10407 (match_operand 2 "" "g,g")))
10408 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10409 (clobber (match_scratch:SI 4 "=l,l"))]
10410 "(DEFAULT_ABI == ABI_DARWIN
10411 || (DEFAULT_ABI == ABI_V4
10412 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10414 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10415 output_asm_insn ("crxor 6,6,6", operands);
10417 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10418 output_asm_insn ("creqv 6,6,6", operands);
10421 return output_call(insn, operands, 1, 3);
10423 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10425 if (TARGET_SECURE_PLT && flag_pic == 2)
10426 return "bl %z1+32768@plt";
10428 return "bl %z1@plt";
10434 [(set_attr "type" "branch,branch")
10435 (set_attr "length" "4,8")])
10437 ;; Call subroutine returning any type.
10438 (define_expand "untyped_call"
10439 [(parallel [(call (match_operand 0 "" "")
10441 (match_operand 1 "" "")
10442 (match_operand 2 "" "")])]
10448 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10450 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10452 rtx set = XVECEXP (operands[2], 0, i);
10453 emit_move_insn (SET_DEST (set), SET_SRC (set));
10456 /* The optimizer does not know that the call sets the function value
10457 registers we stored in the result block. We avoid problems by
10458 claiming that all hard registers are used and clobbered at this
10460 emit_insn (gen_blockage ());
10465 ;; sibling call patterns
10466 (define_expand "sibcall"
10467 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10468 (match_operand 1 "" ""))
10469 (use (match_operand 2 "" ""))
10470 (use (match_operand 3 "" ""))
10476 if (MACHOPIC_INDIRECT)
10477 operands[0] = machopic_indirect_call_target (operands[0]);
10480 gcc_assert (GET_CODE (operands[0]) == MEM);
10481 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10483 operands[0] = XEXP (operands[0], 0);
10484 operands[3] = gen_reg_rtx (SImode);
10488 ;; this and similar patterns must be marked as using LR, otherwise
10489 ;; dataflow will try to delete the store into it. This is true
10490 ;; even when the actual reg to jump to is in CTR, when LR was
10491 ;; saved and restored around the PIC-setting BCL.
10492 (define_insn "*sibcall_local32"
10493 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10494 (match_operand 1 "" "g,g"))
10495 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10496 (use (match_operand:SI 3 "register_operand" "l,l"))
10498 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10501 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10502 output_asm_insn (\"crxor 6,6,6\", operands);
10504 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10505 output_asm_insn (\"creqv 6,6,6\", operands);
10507 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10509 [(set_attr "type" "branch")
10510 (set_attr "length" "4,8")])
10512 (define_insn "*sibcall_local64"
10513 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10514 (match_operand 1 "" "g,g"))
10515 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10516 (use (match_operand:SI 3 "register_operand" "l,l"))
10518 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10521 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10522 output_asm_insn (\"crxor 6,6,6\", operands);
10524 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10525 output_asm_insn (\"creqv 6,6,6\", operands);
10527 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10529 [(set_attr "type" "branch")
10530 (set_attr "length" "4,8")])
10532 (define_insn "*sibcall_value_local32"
10533 [(set (match_operand 0 "" "")
10534 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10535 (match_operand 2 "" "g,g")))
10536 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10537 (use (match_operand:SI 4 "register_operand" "l,l"))
10539 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10542 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10543 output_asm_insn (\"crxor 6,6,6\", operands);
10545 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10546 output_asm_insn (\"creqv 6,6,6\", operands);
10548 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10550 [(set_attr "type" "branch")
10551 (set_attr "length" "4,8")])
10554 (define_insn "*sibcall_value_local64"
10555 [(set (match_operand 0 "" "")
10556 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10557 (match_operand 2 "" "g,g")))
10558 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10559 (use (match_operand:SI 4 "register_operand" "l,l"))
10561 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10564 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10565 output_asm_insn (\"crxor 6,6,6\", operands);
10567 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10568 output_asm_insn (\"creqv 6,6,6\", operands);
10570 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10572 [(set_attr "type" "branch")
10573 (set_attr "length" "4,8")])
10575 (define_insn "*sibcall_nonlocal_aix32"
10576 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10577 (match_operand 1 "" "g"))
10578 (use (match_operand:SI 2 "immediate_operand" "O"))
10579 (use (match_operand:SI 3 "register_operand" "l"))
10582 && DEFAULT_ABI == ABI_AIX
10583 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10585 [(set_attr "type" "branch")
10586 (set_attr "length" "4")])
10588 (define_insn "*sibcall_nonlocal_aix64"
10589 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10590 (match_operand 1 "" "g"))
10591 (use (match_operand:SI 2 "immediate_operand" "O"))
10592 (use (match_operand:SI 3 "register_operand" "l"))
10595 && DEFAULT_ABI == ABI_AIX
10596 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10598 [(set_attr "type" "branch")
10599 (set_attr "length" "4")])
10601 (define_insn "*sibcall_value_nonlocal_aix32"
10602 [(set (match_operand 0 "" "")
10603 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10604 (match_operand 2 "" "g")))
10605 (use (match_operand:SI 3 "immediate_operand" "O"))
10606 (use (match_operand:SI 4 "register_operand" "l"))
10609 && DEFAULT_ABI == ABI_AIX
10610 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10612 [(set_attr "type" "branch")
10613 (set_attr "length" "4")])
10615 (define_insn "*sibcall_value_nonlocal_aix64"
10616 [(set (match_operand 0 "" "")
10617 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10618 (match_operand 2 "" "g")))
10619 (use (match_operand:SI 3 "immediate_operand" "O"))
10620 (use (match_operand:SI 4 "register_operand" "l"))
10623 && DEFAULT_ABI == ABI_AIX
10624 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10626 [(set_attr "type" "branch")
10627 (set_attr "length" "4")])
10629 (define_insn "*sibcall_nonlocal_sysv"
10630 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10631 (match_operand 1 "" ""))
10632 (use (match_operand 2 "immediate_operand" "O,n"))
10633 (use (match_operand:SI 3 "register_operand" "l,l"))
10635 "(DEFAULT_ABI == ABI_DARWIN
10636 || DEFAULT_ABI == ABI_V4)
10637 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10640 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10641 output_asm_insn (\"crxor 6,6,6\", operands);
10643 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10644 output_asm_insn (\"creqv 6,6,6\", operands);
10646 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10648 if (TARGET_SECURE_PLT && flag_pic == 2)
10649 return \"b %z0+32768@plt\";
10651 return \"b %z0@plt\";
10656 [(set_attr "type" "branch,branch")
10657 (set_attr "length" "4,8")])
10659 (define_expand "sibcall_value"
10660 [(parallel [(set (match_operand 0 "register_operand" "")
10661 (call (mem:SI (match_operand 1 "address_operand" ""))
10662 (match_operand 2 "" "")))
10663 (use (match_operand 3 "" ""))
10664 (use (match_operand 4 "" ""))
10670 if (MACHOPIC_INDIRECT)
10671 operands[1] = machopic_indirect_call_target (operands[1]);
10674 gcc_assert (GET_CODE (operands[1]) == MEM);
10675 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10677 operands[1] = XEXP (operands[1], 0);
10678 operands[4] = gen_reg_rtx (SImode);
10682 (define_insn "*sibcall_value_nonlocal_sysv"
10683 [(set (match_operand 0 "" "")
10684 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10685 (match_operand 2 "" "")))
10686 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10687 (use (match_operand:SI 4 "register_operand" "l,l"))
10689 "(DEFAULT_ABI == ABI_DARWIN
10690 || DEFAULT_ABI == ABI_V4)
10691 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10694 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10695 output_asm_insn (\"crxor 6,6,6\", operands);
10697 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10698 output_asm_insn (\"creqv 6,6,6\", operands);
10700 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10702 if (TARGET_SECURE_PLT && flag_pic == 2)
10703 return \"b %z1+32768@plt\";
10705 return \"b %z1@plt\";
10710 [(set_attr "type" "branch,branch")
10711 (set_attr "length" "4,8")])
10713 (define_expand "sibcall_epilogue"
10714 [(use (const_int 0))]
10715 "TARGET_SCHED_PROLOG"
10718 rs6000_emit_epilogue (TRUE);
10722 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10723 ;; all of memory. This blocks insns from being moved across this point.
10725 (define_insn "blockage"
10726 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10730 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10731 ;; signed & unsigned, and one type of branch.
10733 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10734 ;; insns, and branches. We store the operands of compares until we see
10736 (define_expand "cmpsi"
10738 (compare (match_operand:SI 0 "gpc_reg_operand" "")
10739 (match_operand:SI 1 "reg_or_short_operand" "")))]
10743 /* Take care of the possibility that operands[1] might be negative but
10744 this might be a logical operation. That insn doesn't exist. */
10745 if (GET_CODE (operands[1]) == CONST_INT
10746 && INTVAL (operands[1]) < 0)
10747 operands[1] = force_reg (SImode, operands[1]);
10749 rs6000_compare_op0 = operands[0];
10750 rs6000_compare_op1 = operands[1];
10751 rs6000_compare_fp_p = 0;
10755 (define_expand "cmpdi"
10757 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10758 (match_operand:DI 1 "reg_or_short_operand" "")))]
10762 /* Take care of the possibility that operands[1] might be negative but
10763 this might be a logical operation. That insn doesn't exist. */
10764 if (GET_CODE (operands[1]) == CONST_INT
10765 && INTVAL (operands[1]) < 0)
10766 operands[1] = force_reg (DImode, operands[1]);
10768 rs6000_compare_op0 = operands[0];
10769 rs6000_compare_op1 = operands[1];
10770 rs6000_compare_fp_p = 0;
10774 (define_expand "cmpsf"
10775 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
10776 (match_operand:SF 1 "gpc_reg_operand" "")))]
10777 "TARGET_HARD_FLOAT"
10780 rs6000_compare_op0 = operands[0];
10781 rs6000_compare_op1 = operands[1];
10782 rs6000_compare_fp_p = 1;
10786 (define_expand "cmpdf"
10787 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
10788 (match_operand:DF 1 "gpc_reg_operand" "")))]
10789 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
10792 rs6000_compare_op0 = operands[0];
10793 rs6000_compare_op1 = operands[1];
10794 rs6000_compare_fp_p = 1;
10798 (define_expand "cmptf"
10799 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
10800 (match_operand:TF 1 "gpc_reg_operand" "")))]
10801 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10802 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10805 rs6000_compare_op0 = operands[0];
10806 rs6000_compare_op1 = operands[1];
10807 rs6000_compare_fp_p = 1;
10811 (define_expand "beq"
10812 [(use (match_operand 0 "" ""))]
10814 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10816 (define_expand "bne"
10817 [(use (match_operand 0 "" ""))]
10819 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10821 (define_expand "bge"
10822 [(use (match_operand 0 "" ""))]
10824 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10826 (define_expand "bgt"
10827 [(use (match_operand 0 "" ""))]
10829 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10831 (define_expand "ble"
10832 [(use (match_operand 0 "" ""))]
10834 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10836 (define_expand "blt"
10837 [(use (match_operand 0 "" ""))]
10839 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10841 (define_expand "bgeu"
10842 [(use (match_operand 0 "" ""))]
10844 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10846 (define_expand "bgtu"
10847 [(use (match_operand 0 "" ""))]
10849 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
10851 (define_expand "bleu"
10852 [(use (match_operand 0 "" ""))]
10854 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
10856 (define_expand "bltu"
10857 [(use (match_operand 0 "" ""))]
10859 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
10861 (define_expand "bunordered"
10862 [(use (match_operand 0 "" ""))]
10863 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10864 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
10866 (define_expand "bordered"
10867 [(use (match_operand 0 "" ""))]
10868 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10869 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
10871 (define_expand "buneq"
10872 [(use (match_operand 0 "" ""))]
10874 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
10876 (define_expand "bunge"
10877 [(use (match_operand 0 "" ""))]
10879 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
10881 (define_expand "bungt"
10882 [(use (match_operand 0 "" ""))]
10884 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
10886 (define_expand "bunle"
10887 [(use (match_operand 0 "" ""))]
10889 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
10891 (define_expand "bunlt"
10892 [(use (match_operand 0 "" ""))]
10894 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
10896 (define_expand "bltgt"
10897 [(use (match_operand 0 "" ""))]
10899 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
10901 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
10902 ;; For SEQ, likewise, except that comparisons with zero should be done
10903 ;; with an scc insns. However, due to the order that combine see the
10904 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
10905 ;; the cases we don't want to handle.
10906 (define_expand "seq"
10907 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10909 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
10911 (define_expand "sne"
10912 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10916 if (! rs6000_compare_fp_p)
10919 rs6000_emit_sCOND (NE, operands[0]);
10923 ;; A >= 0 is best done the portable way for A an integer.
10924 (define_expand "sge"
10925 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10929 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10932 rs6000_emit_sCOND (GE, operands[0]);
10936 ;; A > 0 is best done using the portable sequence, so fail in that case.
10937 (define_expand "sgt"
10938 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10942 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10945 rs6000_emit_sCOND (GT, operands[0]);
10949 ;; A <= 0 is best done the portable way for A an integer.
10950 (define_expand "sle"
10951 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10955 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10958 rs6000_emit_sCOND (LE, operands[0]);
10962 ;; A < 0 is best done in the portable way for A an integer.
10963 (define_expand "slt"
10964 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10968 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10971 rs6000_emit_sCOND (LT, operands[0]);
10975 (define_expand "sgeu"
10976 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10978 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
10980 (define_expand "sgtu"
10981 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10983 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
10985 (define_expand "sleu"
10986 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10988 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
10990 (define_expand "sltu"
10991 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10993 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
10995 (define_expand "sunordered"
10996 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10997 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10998 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11000 (define_expand "sordered"
11001 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11002 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11003 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11005 (define_expand "suneq"
11006 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11008 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11010 (define_expand "sunge"
11011 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11013 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11015 (define_expand "sungt"
11016 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11018 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11020 (define_expand "sunle"
11021 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11023 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11025 (define_expand "sunlt"
11026 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11028 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11030 (define_expand "sltgt"
11031 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11033 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11036 ;; Here are the actual compare insns.
11037 (define_insn "*cmpsi_internal1"
11038 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11039 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11040 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11042 "{cmp%I2|cmpw%I2} %0,%1,%2"
11043 [(set_attr "type" "cmp")])
11045 (define_insn "*cmpdi_internal1"
11046 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11047 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
11048 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11051 [(set_attr "type" "cmp")])
11053 ;; If we are comparing a register for equality with a large constant,
11054 ;; we can do this with an XOR followed by a compare. But we need a scratch
11055 ;; register for the result of the XOR.
11058 [(set (match_operand:CC 0 "cc_reg_operand" "")
11059 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11060 (match_operand:SI 2 "non_short_cint_operand" "")))
11061 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
11062 "find_single_use (operands[0], insn, 0)
11063 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
11064 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
11065 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
11066 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
11069 /* Get the constant we are comparing against, C, and see what it looks like
11070 sign-extended to 16 bits. Then see what constant could be XOR'ed
11071 with C to get the sign-extended value. */
11073 HOST_WIDE_INT c = INTVAL (operands[2]);
11074 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11075 HOST_WIDE_INT xorv = c ^ sextc;
11077 operands[4] = GEN_INT (xorv);
11078 operands[5] = GEN_INT (sextc);
11081 (define_insn "*cmpsi_internal2"
11082 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11083 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11084 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11086 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11087 [(set_attr "type" "cmp")])
11089 (define_insn "*cmpdi_internal2"
11090 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11091 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11092 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11094 "cmpld%I2 %0,%1,%b2"
11095 [(set_attr "type" "cmp")])
11097 ;; The following two insns don't exist as single insns, but if we provide
11098 ;; them, we can swap an add and compare, which will enable us to overlap more
11099 ;; of the required delay between a compare and branch. We generate code for
11100 ;; them by splitting.
11103 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11104 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11105 (match_operand:SI 2 "short_cint_operand" "i")))
11106 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11107 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11110 [(set_attr "length" "8")])
11113 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11114 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11115 (match_operand:SI 2 "u_short_cint_operand" "i")))
11116 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11117 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11120 [(set_attr "length" "8")])
11123 [(set (match_operand:CC 3 "cc_reg_operand" "")
11124 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11125 (match_operand:SI 2 "short_cint_operand" "")))
11126 (set (match_operand:SI 0 "gpc_reg_operand" "")
11127 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11129 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11130 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11133 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11134 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11135 (match_operand:SI 2 "u_short_cint_operand" "")))
11136 (set (match_operand:SI 0 "gpc_reg_operand" "")
11137 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11139 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11140 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11142 (define_insn "*cmpsf_internal1"
11143 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11144 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11145 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11146 "TARGET_HARD_FLOAT && TARGET_FPRS"
11148 [(set_attr "type" "fpcompare")])
11150 (define_insn "*cmpdf_internal1"
11151 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11152 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11153 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11154 "TARGET_HARD_FLOAT && TARGET_FPRS"
11156 [(set_attr "type" "fpcompare")])
11158 ;; Only need to compare second words if first words equal
11159 (define_insn "*cmptf_internal1"
11160 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11161 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11162 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11163 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
11164 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11165 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11166 [(set_attr "type" "fpcompare")
11167 (set_attr "length" "12")])
11169 (define_insn_and_split "*cmptf_internal2"
11170 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11171 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11172 (match_operand:TF 2 "gpc_reg_operand" "f")))
11173 (clobber (match_scratch:DF 3 "=f"))
11174 (clobber (match_scratch:DF 4 "=f"))
11175 (clobber (match_scratch:DF 5 "=f"))
11176 (clobber (match_scratch:DF 6 "=f"))
11177 (clobber (match_scratch:DF 7 "=f"))
11178 (clobber (match_scratch:DF 8 "=f"))
11179 (clobber (match_scratch:DF 9 "=f"))
11180 (clobber (match_scratch:DF 10 "=f"))]
11181 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
11182 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11184 "&& reload_completed"
11185 [(set (match_dup 3) (match_dup 13))
11186 (set (match_dup 4) (match_dup 14))
11187 (set (match_dup 9) (abs:DF (match_dup 5)))
11188 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11189 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11190 (label_ref (match_dup 11))
11192 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11193 (set (pc) (label_ref (match_dup 12)))
11195 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11196 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11197 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11198 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11201 REAL_VALUE_TYPE rv;
11202 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11203 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11205 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11206 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11207 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11208 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11209 operands[11] = gen_label_rtx ();
11210 operands[12] = gen_label_rtx ();
11212 operands[13] = force_const_mem (DFmode,
11213 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11214 operands[14] = force_const_mem (DFmode,
11215 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11219 operands[13] = gen_const_mem (DFmode,
11220 create_TOC_reference (XEXP (operands[13], 0)));
11221 operands[14] = gen_const_mem (DFmode,
11222 create_TOC_reference (XEXP (operands[14], 0)));
11223 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11224 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11228 ;; Now we have the scc insns. We can do some combinations because of the
11229 ;; way the machine works.
11231 ;; Note that this is probably faster if we can put an insn between the
11232 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11233 ;; cases the insns below which don't use an intermediate CR field will
11234 ;; be used instead.
11236 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11237 (match_operator:SI 1 "scc_comparison_operator"
11238 [(match_operand 2 "cc_reg_operand" "y")
11241 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11242 [(set (attr "type")
11243 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11244 (const_string "mfcrf")
11246 (const_string "mfcr")))
11247 (set_attr "length" "8")])
11249 ;; Same as above, but get the GT bit.
11250 (define_insn "move_from_CR_gt_bit"
11251 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11252 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11254 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
11255 [(set_attr "type" "mfcr")
11256 (set_attr "length" "8")])
11258 ;; Same as above, but get the OV/ORDERED bit.
11259 (define_insn "move_from_CR_ov_bit"
11260 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11261 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11263 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11264 [(set_attr "type" "mfcr")
11265 (set_attr "length" "8")])
11268 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11269 (match_operator:DI 1 "scc_comparison_operator"
11270 [(match_operand 2 "cc_reg_operand" "y")
11273 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11274 [(set (attr "type")
11275 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11276 (const_string "mfcrf")
11278 (const_string "mfcr")))
11279 (set_attr "length" "8")])
11282 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11283 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11284 [(match_operand 2 "cc_reg_operand" "y,y")
11287 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11288 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11291 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11293 [(set_attr "type" "delayed_compare")
11294 (set_attr "length" "8,16")])
11297 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11298 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11299 [(match_operand 2 "cc_reg_operand" "")
11302 (set (match_operand:SI 3 "gpc_reg_operand" "")
11303 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11304 "TARGET_32BIT && reload_completed"
11305 [(set (match_dup 3)
11306 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11308 (compare:CC (match_dup 3)
11313 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11314 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11315 [(match_operand 2 "cc_reg_operand" "y")
11317 (match_operand:SI 3 "const_int_operand" "n")))]
11321 int is_bit = ccr_bit (operands[1], 1);
11322 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11325 if (is_bit >= put_bit)
11326 count = is_bit - put_bit;
11328 count = 32 - (put_bit - is_bit);
11330 operands[4] = GEN_INT (count);
11331 operands[5] = GEN_INT (put_bit);
11333 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11335 [(set (attr "type")
11336 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11337 (const_string "mfcrf")
11339 (const_string "mfcr")))
11340 (set_attr "length" "8")])
11343 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11345 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11346 [(match_operand 2 "cc_reg_operand" "y,y")
11348 (match_operand:SI 3 "const_int_operand" "n,n"))
11350 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11351 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11356 int is_bit = ccr_bit (operands[1], 1);
11357 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11360 /* Force split for non-cc0 compare. */
11361 if (which_alternative == 1)
11364 if (is_bit >= put_bit)
11365 count = is_bit - put_bit;
11367 count = 32 - (put_bit - is_bit);
11369 operands[5] = GEN_INT (count);
11370 operands[6] = GEN_INT (put_bit);
11372 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11374 [(set_attr "type" "delayed_compare")
11375 (set_attr "length" "8,16")])
11378 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11380 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11381 [(match_operand 2 "cc_reg_operand" "")
11383 (match_operand:SI 3 "const_int_operand" ""))
11385 (set (match_operand:SI 4 "gpc_reg_operand" "")
11386 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11389 [(set (match_dup 4)
11390 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11393 (compare:CC (match_dup 4)
11397 ;; There is a 3 cycle delay between consecutive mfcr instructions
11398 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11401 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11402 (match_operator:SI 1 "scc_comparison_operator"
11403 [(match_operand 2 "cc_reg_operand" "y")
11405 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11406 (match_operator:SI 4 "scc_comparison_operator"
11407 [(match_operand 5 "cc_reg_operand" "y")
11409 "REGNO (operands[2]) != REGNO (operands[5])"
11410 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11411 [(set_attr "type" "mfcr")
11412 (set_attr "length" "12")])
11415 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11416 (match_operator:DI 1 "scc_comparison_operator"
11417 [(match_operand 2 "cc_reg_operand" "y")
11419 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11420 (match_operator:DI 4 "scc_comparison_operator"
11421 [(match_operand 5 "cc_reg_operand" "y")
11423 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11424 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11425 [(set_attr "type" "mfcr")
11426 (set_attr "length" "12")])
11428 ;; There are some scc insns that can be done directly, without a compare.
11429 ;; These are faster because they don't involve the communications between
11430 ;; the FXU and branch units. In fact, we will be replacing all of the
11431 ;; integer scc insns here or in the portable methods in emit_store_flag.
11433 ;; Also support (neg (scc ..)) since that construct is used to replace
11434 ;; branches, (plus (scc ..) ..) since that construct is common and
11435 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11436 ;; cases where it is no more expensive than (neg (scc ..)).
11438 ;; Have reload force a constant into a register for the simple insns that
11439 ;; otherwise won't accept constants. We do this because it is faster than
11440 ;; the cmp/mfcr sequence we would otherwise generate.
11443 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11444 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11445 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11446 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11449 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11450 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11451 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11452 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11453 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11454 [(set_attr "type" "three,two,three,three,three")
11455 (set_attr "length" "12,8,12,12,12")])
11458 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11459 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11460 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11461 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
11464 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11465 subfic %3,%1,0\;adde %0,%3,%1
11466 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11467 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11468 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11469 [(set_attr "type" "three,two,three,three,three")
11470 (set_attr "length" "12,8,12,12,12")])
11473 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11475 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11476 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11478 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11479 (eq:SI (match_dup 1) (match_dup 2)))
11480 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11483 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11484 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11485 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11486 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11487 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11493 [(set_attr "type" "compare")
11494 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11497 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11499 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11500 (match_operand:SI 2 "reg_or_cint_operand" ""))
11502 (set (match_operand:SI 0 "gpc_reg_operand" "")
11503 (eq:SI (match_dup 1) (match_dup 2)))
11504 (clobber (match_scratch:SI 3 ""))]
11505 "TARGET_32BIT && reload_completed"
11506 [(parallel [(set (match_dup 0)
11507 (eq:SI (match_dup 1) (match_dup 2)))
11508 (clobber (match_dup 3))])
11510 (compare:CC (match_dup 0)
11515 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11517 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11518 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11520 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11521 (eq:DI (match_dup 1) (match_dup 2)))
11522 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11525 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11526 subfic %3,%1,0\;adde. %0,%3,%1
11527 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11528 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
11529 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11535 [(set_attr "type" "compare")
11536 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11539 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11541 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11542 (match_operand:DI 2 "reg_or_cint_operand" ""))
11544 (set (match_operand:DI 0 "gpc_reg_operand" "")
11545 (eq:DI (match_dup 1) (match_dup 2)))
11546 (clobber (match_scratch:DI 3 ""))]
11547 "TARGET_64BIT && reload_completed"
11548 [(parallel [(set (match_dup 0)
11549 (eq:DI (match_dup 1) (match_dup 2)))
11550 (clobber (match_dup 3))])
11552 (compare:CC (match_dup 0)
11556 ;; We have insns of the form shown by the first define_insn below. If
11557 ;; there is something inside the comparison operation, we must split it.
11559 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11560 (plus:SI (match_operator 1 "comparison_operator"
11561 [(match_operand:SI 2 "" "")
11562 (match_operand:SI 3
11563 "reg_or_cint_operand" "")])
11564 (match_operand:SI 4 "gpc_reg_operand" "")))
11565 (clobber (match_operand:SI 5 "register_operand" ""))]
11566 "! gpc_reg_operand (operands[2], SImode)"
11567 [(set (match_dup 5) (match_dup 2))
11568 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11572 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11573 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11574 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
11575 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11578 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11579 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11580 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11581 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11582 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11583 [(set_attr "type" "three,two,three,three,three")
11584 (set_attr "length" "12,8,12,12,12")])
11587 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11590 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11591 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11592 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11594 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11597 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11598 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11599 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11600 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11601 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11607 [(set_attr "type" "compare")
11608 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11611 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11614 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11615 (match_operand:SI 2 "reg_or_cint_operand" ""))
11616 (match_operand:SI 3 "gpc_reg_operand" ""))
11618 (clobber (match_scratch:SI 4 ""))]
11619 "TARGET_32BIT && reload_completed"
11620 [(set (match_dup 4)
11621 (plus:SI (eq:SI (match_dup 1)
11625 (compare:CC (match_dup 4)
11630 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11633 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11634 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11635 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11637 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11638 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11641 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11642 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11643 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11644 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11645 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11651 [(set_attr "type" "compare")
11652 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11655 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11658 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11659 (match_operand:SI 2 "reg_or_cint_operand" ""))
11660 (match_operand:SI 3 "gpc_reg_operand" ""))
11662 (set (match_operand:SI 0 "gpc_reg_operand" "")
11663 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11664 "TARGET_32BIT && reload_completed"
11665 [(set (match_dup 0)
11666 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11668 (compare:CC (match_dup 0)
11673 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11674 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11675 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
11678 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11679 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11680 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11681 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11682 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11683 [(set_attr "type" "three,two,three,three,three")
11684 (set_attr "length" "12,8,12,12,12")])
11686 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11687 ;; since it nabs/sr is just as fast.
11688 (define_insn "*ne0"
11689 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11690 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11692 (clobber (match_scratch:SI 2 "=&r"))]
11693 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11694 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11695 [(set_attr "type" "two")
11696 (set_attr "length" "8")])
11699 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11700 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11702 (clobber (match_scratch:DI 2 "=&r"))]
11704 "addic %2,%1,-1\;subfe %0,%2,%1"
11705 [(set_attr "type" "two")
11706 (set_attr "length" "8")])
11708 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11710 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11711 (plus:SI (lshiftrt:SI
11712 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11714 (match_operand:SI 2 "gpc_reg_operand" "r")))
11715 (clobber (match_scratch:SI 3 "=&r"))]
11717 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11718 [(set_attr "type" "two")
11719 (set_attr "length" "8")])
11722 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11723 (plus:DI (lshiftrt:DI
11724 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11726 (match_operand:DI 2 "gpc_reg_operand" "r")))
11727 (clobber (match_scratch:DI 3 "=&r"))]
11729 "addic %3,%1,-1\;addze %0,%2"
11730 [(set_attr "type" "two")
11731 (set_attr "length" "8")])
11734 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11736 (plus:SI (lshiftrt:SI
11737 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11739 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11741 (clobber (match_scratch:SI 3 "=&r,&r"))
11742 (clobber (match_scratch:SI 4 "=X,&r"))]
11745 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11747 [(set_attr "type" "compare")
11748 (set_attr "length" "8,12")])
11751 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11753 (plus:SI (lshiftrt:SI
11754 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11756 (match_operand:SI 2 "gpc_reg_operand" ""))
11758 (clobber (match_scratch:SI 3 ""))
11759 (clobber (match_scratch:SI 4 ""))]
11760 "TARGET_32BIT && reload_completed"
11761 [(parallel [(set (match_dup 3)
11762 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11765 (clobber (match_dup 4))])
11767 (compare:CC (match_dup 3)
11772 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11774 (plus:DI (lshiftrt:DI
11775 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11777 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11779 (clobber (match_scratch:DI 3 "=&r,&r"))]
11782 addic %3,%1,-1\;addze. %3,%2
11784 [(set_attr "type" "compare")
11785 (set_attr "length" "8,12")])
11788 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11790 (plus:DI (lshiftrt:DI
11791 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11793 (match_operand:DI 2 "gpc_reg_operand" ""))
11795 (clobber (match_scratch:DI 3 ""))]
11796 "TARGET_64BIT && reload_completed"
11797 [(set (match_dup 3)
11798 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11802 (compare:CC (match_dup 3)
11807 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11809 (plus:SI (lshiftrt:SI
11810 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11812 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11814 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11815 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11817 (clobber (match_scratch:SI 3 "=&r,&r"))]
11820 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11822 [(set_attr "type" "compare")
11823 (set_attr "length" "8,12")])
11826 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11828 (plus:SI (lshiftrt:SI
11829 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11831 (match_operand:SI 2 "gpc_reg_operand" ""))
11833 (set (match_operand:SI 0 "gpc_reg_operand" "")
11834 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11836 (clobber (match_scratch:SI 3 ""))]
11837 "TARGET_32BIT && reload_completed"
11838 [(parallel [(set (match_dup 0)
11839 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11841 (clobber (match_dup 3))])
11843 (compare:CC (match_dup 0)
11848 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11850 (plus:DI (lshiftrt:DI
11851 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11853 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11855 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11856 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11858 (clobber (match_scratch:DI 3 "=&r,&r"))]
11861 addic %3,%1,-1\;addze. %0,%2
11863 [(set_attr "type" "compare")
11864 (set_attr "length" "8,12")])
11867 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11869 (plus:DI (lshiftrt:DI
11870 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11872 (match_operand:DI 2 "gpc_reg_operand" ""))
11874 (set (match_operand:DI 0 "gpc_reg_operand" "")
11875 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11877 (clobber (match_scratch:DI 3 ""))]
11878 "TARGET_64BIT && reload_completed"
11879 [(parallel [(set (match_dup 0)
11880 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11882 (clobber (match_dup 3))])
11884 (compare:CC (match_dup 0)
11889 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11890 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11891 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11892 (clobber (match_scratch:SI 3 "=r,X"))]
11895 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11896 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11897 [(set_attr "length" "12")])
11900 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11902 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11903 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11905 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11906 (le:SI (match_dup 1) (match_dup 2)))
11907 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11910 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11911 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11914 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11915 (set_attr "length" "12,12,16,16")])
11918 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11920 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11921 (match_operand:SI 2 "reg_or_short_operand" ""))
11923 (set (match_operand:SI 0 "gpc_reg_operand" "")
11924 (le:SI (match_dup 1) (match_dup 2)))
11925 (clobber (match_scratch:SI 3 ""))]
11926 "TARGET_POWER && reload_completed"
11927 [(parallel [(set (match_dup 0)
11928 (le:SI (match_dup 1) (match_dup 2)))
11929 (clobber (match_dup 3))])
11931 (compare:CC (match_dup 0)
11936 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11937 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11938 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
11939 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
11942 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11943 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
11944 [(set_attr "length" "12")])
11947 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11949 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11950 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11951 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11953 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11956 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11957 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11960 [(set_attr "type" "compare")
11961 (set_attr "length" "12,12,16,16")])
11964 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11966 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11967 (match_operand:SI 2 "reg_or_short_operand" ""))
11968 (match_operand:SI 3 "gpc_reg_operand" ""))
11970 (clobber (match_scratch:SI 4 ""))]
11971 "TARGET_POWER && reload_completed"
11972 [(set (match_dup 4)
11973 (plus:SI (le:SI (match_dup 1) (match_dup 2))
11976 (compare:CC (match_dup 4)
11981 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11983 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11984 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11985 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11987 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
11988 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11991 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11992 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
11995 [(set_attr "type" "compare")
11996 (set_attr "length" "12,12,16,16")])
11999 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12001 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12002 (match_operand:SI 2 "reg_or_short_operand" ""))
12003 (match_operand:SI 3 "gpc_reg_operand" ""))
12005 (set (match_operand:SI 0 "gpc_reg_operand" "")
12006 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12007 "TARGET_POWER && reload_completed"
12008 [(set (match_dup 0)
12009 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12011 (compare:CC (match_dup 0)
12016 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12017 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12018 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12021 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12022 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12023 [(set_attr "length" "12")])
12026 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12027 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12028 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12030 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12031 [(set_attr "type" "three")
12032 (set_attr "length" "12")])
12035 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12036 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12037 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
12039 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12040 [(set_attr "type" "three")
12041 (set_attr "length" "12")])
12044 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12046 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12047 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12049 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12050 (leu:DI (match_dup 1) (match_dup 2)))]
12053 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12055 [(set_attr "type" "compare")
12056 (set_attr "length" "12,16")])
12059 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12061 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12062 (match_operand:DI 2 "reg_or_short_operand" ""))
12064 (set (match_operand:DI 0 "gpc_reg_operand" "")
12065 (leu:DI (match_dup 1) (match_dup 2)))]
12066 "TARGET_64BIT && reload_completed"
12067 [(set (match_dup 0)
12068 (leu:DI (match_dup 1) (match_dup 2)))
12070 (compare:CC (match_dup 0)
12075 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12077 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12078 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12080 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12081 (leu:SI (match_dup 1) (match_dup 2)))]
12084 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12086 [(set_attr "type" "compare")
12087 (set_attr "length" "12,16")])
12090 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12092 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12093 (match_operand:SI 2 "reg_or_short_operand" ""))
12095 (set (match_operand:SI 0 "gpc_reg_operand" "")
12096 (leu:SI (match_dup 1) (match_dup 2)))]
12097 "TARGET_32BIT && reload_completed"
12098 [(set (match_dup 0)
12099 (leu:SI (match_dup 1) (match_dup 2)))
12101 (compare:CC (match_dup 0)
12106 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12107 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12108 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12109 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12111 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12112 [(set_attr "type" "two")
12113 (set_attr "length" "8")])
12116 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12118 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12119 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12120 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12122 (clobber (match_scratch:SI 4 "=&r,&r"))]
12125 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12127 [(set_attr "type" "compare")
12128 (set_attr "length" "8,12")])
12131 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12133 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12134 (match_operand:SI 2 "reg_or_short_operand" ""))
12135 (match_operand:SI 3 "gpc_reg_operand" ""))
12137 (clobber (match_scratch:SI 4 ""))]
12138 "TARGET_32BIT && reload_completed"
12139 [(set (match_dup 4)
12140 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12143 (compare:CC (match_dup 4)
12148 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12150 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12151 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12152 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12154 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12155 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12158 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12160 [(set_attr "type" "compare")
12161 (set_attr "length" "8,12")])
12164 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12166 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12167 (match_operand:SI 2 "reg_or_short_operand" ""))
12168 (match_operand:SI 3 "gpc_reg_operand" ""))
12170 (set (match_operand:SI 0 "gpc_reg_operand" "")
12171 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12172 "TARGET_32BIT && reload_completed"
12173 [(set (match_dup 0)
12174 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12176 (compare:CC (match_dup 0)
12181 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12182 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12183 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12185 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12186 [(set_attr "type" "three")
12187 (set_attr "length" "12")])
12190 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12192 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12193 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12194 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12196 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12197 [(set_attr "type" "three")
12198 (set_attr "length" "12")])
12201 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12204 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12205 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12206 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12208 (clobber (match_scratch:SI 4 "=&r,&r"))]
12211 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12213 [(set_attr "type" "compare")
12214 (set_attr "length" "12,16")])
12217 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12220 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12221 (match_operand:SI 2 "reg_or_short_operand" "")))
12222 (match_operand:SI 3 "gpc_reg_operand" ""))
12224 (clobber (match_scratch:SI 4 ""))]
12225 "TARGET_32BIT && reload_completed"
12226 [(set (match_dup 4)
12227 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12230 (compare:CC (match_dup 4)
12235 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12238 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12239 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12240 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12242 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12243 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12246 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12248 [(set_attr "type" "compare")
12249 (set_attr "length" "12,16")])
12252 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12255 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12256 (match_operand:SI 2 "reg_or_short_operand" "")))
12257 (match_operand:SI 3 "gpc_reg_operand" ""))
12259 (set (match_operand:SI 0 "gpc_reg_operand" "")
12260 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12261 "TARGET_32BIT && reload_completed"
12262 [(set (match_dup 0)
12263 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12266 (compare:CC (match_dup 0)
12271 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12272 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12273 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12275 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12276 [(set_attr "length" "12")])
12279 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12281 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12282 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12284 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12285 (lt:SI (match_dup 1) (match_dup 2)))]
12288 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12290 [(set_attr "type" "delayed_compare")
12291 (set_attr "length" "12,16")])
12294 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12296 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12297 (match_operand:SI 2 "reg_or_short_operand" ""))
12299 (set (match_operand:SI 0 "gpc_reg_operand" "")
12300 (lt:SI (match_dup 1) (match_dup 2)))]
12301 "TARGET_POWER && reload_completed"
12302 [(set (match_dup 0)
12303 (lt:SI (match_dup 1) (match_dup 2)))
12305 (compare:CC (match_dup 0)
12310 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12311 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12312 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12313 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12315 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12316 [(set_attr "length" "12")])
12319 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12321 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12322 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12323 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12325 (clobber (match_scratch:SI 4 "=&r,&r"))]
12328 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12330 [(set_attr "type" "compare")
12331 (set_attr "length" "12,16")])
12334 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12336 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12337 (match_operand:SI 2 "reg_or_short_operand" ""))
12338 (match_operand:SI 3 "gpc_reg_operand" ""))
12340 (clobber (match_scratch:SI 4 ""))]
12341 "TARGET_POWER && reload_completed"
12342 [(set (match_dup 4)
12343 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12346 (compare:CC (match_dup 4)
12351 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12353 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12354 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12355 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12357 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12358 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12361 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12363 [(set_attr "type" "compare")
12364 (set_attr "length" "12,16")])
12367 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12369 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12370 (match_operand:SI 2 "reg_or_short_operand" ""))
12371 (match_operand:SI 3 "gpc_reg_operand" ""))
12373 (set (match_operand:SI 0 "gpc_reg_operand" "")
12374 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12375 "TARGET_POWER && reload_completed"
12376 [(set (match_dup 0)
12377 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12379 (compare:CC (match_dup 0)
12384 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12385 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12386 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12388 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12389 [(set_attr "length" "12")])
12391 (define_insn_and_split ""
12392 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12393 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12394 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12398 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12399 (set (match_dup 0) (neg:SI (match_dup 0)))]
12402 (define_insn_and_split ""
12403 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12404 (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12405 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12409 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12410 (set (match_dup 0) (neg:DI (match_dup 0)))]
12414 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12416 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12417 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12419 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12420 (ltu:SI (match_dup 1) (match_dup 2)))]
12423 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12424 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12427 [(set_attr "type" "compare")
12428 (set_attr "length" "12,12,16,16")])
12431 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12433 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12434 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12436 (set (match_operand:SI 0 "gpc_reg_operand" "")
12437 (ltu:SI (match_dup 1) (match_dup 2)))]
12438 "TARGET_32BIT && reload_completed"
12439 [(set (match_dup 0)
12440 (ltu:SI (match_dup 1) (match_dup 2)))
12442 (compare:CC (match_dup 0)
12446 (define_insn_and_split ""
12447 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
12448 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12449 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12450 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12453 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12454 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12455 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
12458 (define_insn_and_split ""
12459 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
12460 (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12461 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
12462 (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))]
12465 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12466 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12467 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
12471 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12473 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12474 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12475 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12477 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12480 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12481 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12484 [(set_attr "type" "compare")
12485 (set_attr "length" "12,12,16,16")])
12488 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12490 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12491 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12492 (match_operand:SI 3 "gpc_reg_operand" ""))
12494 (clobber (match_scratch:SI 4 ""))]
12495 "TARGET_32BIT && reload_completed"
12496 [(set (match_dup 4)
12497 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12500 (compare:CC (match_dup 4)
12505 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12507 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12508 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12509 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12511 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12512 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12515 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12516 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12519 [(set_attr "type" "compare")
12520 (set_attr "length" "12,12,16,16")])
12523 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12525 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12526 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12527 (match_operand:SI 3 "gpc_reg_operand" ""))
12529 (set (match_operand:SI 0 "gpc_reg_operand" "")
12530 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12531 "TARGET_32BIT && reload_completed"
12532 [(set (match_dup 0)
12533 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12535 (compare:CC (match_dup 0)
12540 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12541 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12542 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12545 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12546 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12547 [(set_attr "type" "two")
12548 (set_attr "length" "8")])
12551 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12552 (neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12553 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))]
12556 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12557 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12558 [(set_attr "type" "two")
12559 (set_attr "length" "8")])
12562 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12563 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12564 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12565 (clobber (match_scratch:SI 3 "=r"))]
12567 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12568 [(set_attr "length" "12")])
12571 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12573 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12574 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12576 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12577 (ge:SI (match_dup 1) (match_dup 2)))
12578 (clobber (match_scratch:SI 3 "=r,r"))]
12581 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12583 [(set_attr "type" "compare")
12584 (set_attr "length" "12,16")])
12587 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12589 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12590 (match_operand:SI 2 "reg_or_short_operand" ""))
12592 (set (match_operand:SI 0 "gpc_reg_operand" "")
12593 (ge:SI (match_dup 1) (match_dup 2)))
12594 (clobber (match_scratch:SI 3 ""))]
12595 "TARGET_POWER && reload_completed"
12596 [(parallel [(set (match_dup 0)
12597 (ge:SI (match_dup 1) (match_dup 2)))
12598 (clobber (match_dup 3))])
12600 (compare:CC (match_dup 0)
12605 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12606 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12607 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12608 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12610 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12611 [(set_attr "length" "12")])
12614 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12616 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12617 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12618 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12620 (clobber (match_scratch:SI 4 "=&r,&r"))]
12623 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12625 [(set_attr "type" "compare")
12626 (set_attr "length" "12,16")])
12629 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12631 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12632 (match_operand:SI 2 "reg_or_short_operand" ""))
12633 (match_operand:SI 3 "gpc_reg_operand" ""))
12635 (clobber (match_scratch:SI 4 ""))]
12636 "TARGET_POWER && reload_completed"
12637 [(set (match_dup 4)
12638 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12641 (compare:CC (match_dup 4)
12646 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12648 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12649 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12650 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12652 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12653 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12656 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12658 [(set_attr "type" "compare")
12659 (set_attr "length" "12,16")])
12662 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12664 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12665 (match_operand:SI 2 "reg_or_short_operand" ""))
12666 (match_operand:SI 3 "gpc_reg_operand" ""))
12668 (set (match_operand:SI 0 "gpc_reg_operand" "")
12669 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12670 "TARGET_POWER && reload_completed"
12671 [(set (match_dup 0)
12672 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12674 (compare:CC (match_dup 0)
12679 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12680 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12681 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12683 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12684 [(set_attr "length" "12")])
12687 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12688 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12689 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12692 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12693 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12694 [(set_attr "type" "three")
12695 (set_attr "length" "12")])
12698 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12699 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12700 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12703 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12704 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12705 [(set_attr "type" "three")
12706 (set_attr "length" "12")])
12709 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12711 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12712 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12714 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12715 (geu:SI (match_dup 1) (match_dup 2)))]
12718 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12719 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12722 [(set_attr "type" "compare")
12723 (set_attr "length" "12,12,16,16")])
12726 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12728 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12729 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12731 (set (match_operand:SI 0 "gpc_reg_operand" "")
12732 (geu:SI (match_dup 1) (match_dup 2)))]
12733 "TARGET_32BIT && reload_completed"
12734 [(set (match_dup 0)
12735 (geu:SI (match_dup 1) (match_dup 2)))
12737 (compare:CC (match_dup 0)
12742 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12744 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12745 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12747 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12748 (geu:DI (match_dup 1) (match_dup 2)))]
12751 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12752 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12755 [(set_attr "type" "compare")
12756 (set_attr "length" "12,12,16,16")])
12759 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12761 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12762 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12764 (set (match_operand:DI 0 "gpc_reg_operand" "")
12765 (geu:DI (match_dup 1) (match_dup 2)))]
12766 "TARGET_64BIT && reload_completed"
12767 [(set (match_dup 0)
12768 (geu:DI (match_dup 1) (match_dup 2)))
12770 (compare:CC (match_dup 0)
12775 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12776 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12777 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12778 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12781 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12782 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12783 [(set_attr "type" "two")
12784 (set_attr "length" "8")])
12787 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12789 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12790 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12791 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12793 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12796 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12797 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12800 [(set_attr "type" "compare")
12801 (set_attr "length" "8,8,12,12")])
12804 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12806 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12807 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12808 (match_operand:SI 3 "gpc_reg_operand" ""))
12810 (clobber (match_scratch:SI 4 ""))]
12811 "TARGET_32BIT && reload_completed"
12812 [(set (match_dup 4)
12813 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12816 (compare:CC (match_dup 4)
12821 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12823 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12824 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12825 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12827 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12828 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12831 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12832 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12835 [(set_attr "type" "compare")
12836 (set_attr "length" "8,8,12,12")])
12839 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12841 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12842 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12843 (match_operand:SI 3 "gpc_reg_operand" ""))
12845 (set (match_operand:SI 0 "gpc_reg_operand" "")
12846 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12847 "TARGET_32BIT && reload_completed"
12848 [(set (match_dup 0)
12849 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12851 (compare:CC (match_dup 0)
12856 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12857 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12858 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
12861 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12862 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12863 [(set_attr "type" "three")
12864 (set_attr "length" "12")])
12867 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12869 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12870 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
12871 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12874 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12875 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12876 [(set_attr "type" "three")
12877 (set_attr "length" "12")])
12880 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12883 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12884 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12885 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12887 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12890 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12891 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12894 [(set_attr "type" "compare")
12895 (set_attr "length" "12,12,16,16")])
12898 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12901 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12902 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12903 (match_operand:SI 3 "gpc_reg_operand" ""))
12905 (clobber (match_scratch:SI 4 ""))]
12906 "TARGET_32BIT && reload_completed"
12907 [(set (match_dup 4)
12908 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12911 (compare:CC (match_dup 4)
12916 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12919 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12920 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12921 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12923 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12924 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12927 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12928 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12931 [(set_attr "type" "compare")
12932 (set_attr "length" "12,12,16,16")])
12935 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12938 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12939 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12940 (match_operand:SI 3 "gpc_reg_operand" ""))
12942 (set (match_operand:SI 0 "gpc_reg_operand" "")
12943 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12944 "TARGET_32BIT && reload_completed"
12945 [(set (match_dup 0)
12946 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12948 (compare:CC (match_dup 0)
12953 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12954 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12957 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
12958 [(set_attr "type" "three")
12959 (set_attr "length" "12")])
12962 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12963 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12966 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
12967 [(set_attr "type" "three")
12968 (set_attr "length" "12")])
12971 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12973 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12976 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12977 (gt:SI (match_dup 1) (const_int 0)))]
12980 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
12982 [(set_attr "type" "delayed_compare")
12983 (set_attr "length" "12,16")])
12986 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12988 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12991 (set (match_operand:SI 0 "gpc_reg_operand" "")
12992 (gt:SI (match_dup 1) (const_int 0)))]
12993 "TARGET_32BIT && reload_completed"
12994 [(set (match_dup 0)
12995 (gt:SI (match_dup 1) (const_int 0)))
12997 (compare:CC (match_dup 0)
13002 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13004 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13007 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13008 (gt:DI (match_dup 1) (const_int 0)))]
13011 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
13013 [(set_attr "type" "delayed_compare")
13014 (set_attr "length" "12,16")])
13017 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13019 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13022 (set (match_operand:DI 0 "gpc_reg_operand" "")
13023 (gt:DI (match_dup 1) (const_int 0)))]
13024 "TARGET_64BIT && reload_completed"
13025 [(set (match_dup 0)
13026 (gt:DI (match_dup 1) (const_int 0)))
13028 (compare:CC (match_dup 0)
13033 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13034 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13035 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13037 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13038 [(set_attr "length" "12")])
13041 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13043 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13044 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13046 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13047 (gt:SI (match_dup 1) (match_dup 2)))]
13050 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13052 [(set_attr "type" "delayed_compare")
13053 (set_attr "length" "12,16")])
13056 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13058 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13059 (match_operand:SI 2 "reg_or_short_operand" ""))
13061 (set (match_operand:SI 0 "gpc_reg_operand" "")
13062 (gt:SI (match_dup 1) (match_dup 2)))]
13063 "TARGET_POWER && reload_completed"
13064 [(set (match_dup 0)
13065 (gt:SI (match_dup 1) (match_dup 2)))
13067 (compare:CC (match_dup 0)
13072 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13073 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13075 (match_operand:SI 2 "gpc_reg_operand" "r")))]
13077 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13078 [(set_attr "type" "three")
13079 (set_attr "length" "12")])
13082 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13083 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13085 (match_operand:DI 2 "gpc_reg_operand" "r")))]
13087 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13088 [(set_attr "type" "three")
13089 (set_attr "length" "12")])
13092 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13094 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13096 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13098 (clobber (match_scratch:SI 3 "=&r,&r"))]
13101 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13103 [(set_attr "type" "compare")
13104 (set_attr "length" "12,16")])
13107 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13109 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13111 (match_operand:SI 2 "gpc_reg_operand" ""))
13113 (clobber (match_scratch:SI 3 ""))]
13114 "TARGET_32BIT && reload_completed"
13115 [(set (match_dup 3)
13116 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13119 (compare:CC (match_dup 3)
13124 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13126 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13128 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13130 (clobber (match_scratch:DI 3 "=&r,&r"))]
13133 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13135 [(set_attr "type" "compare")
13136 (set_attr "length" "12,16")])
13139 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13141 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13143 (match_operand:DI 2 "gpc_reg_operand" ""))
13145 (clobber (match_scratch:DI 3 ""))]
13146 "TARGET_64BIT && reload_completed"
13147 [(set (match_dup 3)
13148 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13151 (compare:CC (match_dup 3)
13156 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13158 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13160 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13162 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13163 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13166 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13168 [(set_attr "type" "compare")
13169 (set_attr "length" "12,16")])
13172 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13174 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13176 (match_operand:SI 2 "gpc_reg_operand" ""))
13178 (set (match_operand:SI 0 "gpc_reg_operand" "")
13179 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13180 "TARGET_32BIT && reload_completed"
13181 [(set (match_dup 0)
13182 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13184 (compare:CC (match_dup 0)
13189 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13191 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13193 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13195 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13196 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13199 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13201 [(set_attr "type" "compare")
13202 (set_attr "length" "12,16")])
13205 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13207 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13209 (match_operand:DI 2 "gpc_reg_operand" ""))
13211 (set (match_operand:DI 0 "gpc_reg_operand" "")
13212 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13213 "TARGET_64BIT && reload_completed"
13214 [(set (match_dup 0)
13215 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13217 (compare:CC (match_dup 0)
13222 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13223 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13224 (match_operand:SI 2 "reg_or_short_operand" "r"))
13225 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13227 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13228 [(set_attr "length" "12")])
13231 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13233 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13234 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13235 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13237 (clobber (match_scratch:SI 4 "=&r,&r"))]
13240 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13242 [(set_attr "type" "compare")
13243 (set_attr "length" "12,16")])
13246 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13248 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13249 (match_operand:SI 2 "reg_or_short_operand" ""))
13250 (match_operand:SI 3 "gpc_reg_operand" ""))
13252 (clobber (match_scratch:SI 4 ""))]
13253 "TARGET_POWER && reload_completed"
13254 [(set (match_dup 4)
13255 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13257 (compare:CC (match_dup 4)
13262 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13264 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13265 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13266 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13268 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13269 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13272 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13274 [(set_attr "type" "compare")
13275 (set_attr "length" "12,16")])
13278 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13280 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13281 (match_operand:SI 2 "reg_or_short_operand" ""))
13282 (match_operand:SI 3 "gpc_reg_operand" ""))
13284 (set (match_operand:SI 0 "gpc_reg_operand" "")
13285 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13286 "TARGET_POWER && reload_completed"
13287 [(set (match_dup 0)
13288 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13290 (compare:CC (match_dup 0)
13295 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13296 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13299 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13300 [(set_attr "type" "three")
13301 (set_attr "length" "12")])
13304 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13305 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13308 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13309 [(set_attr "type" "three")
13310 (set_attr "length" "12")])
13313 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13314 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13315 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13317 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13318 [(set_attr "length" "12")])
13320 (define_insn_and_split ""
13321 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13322 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13323 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13327 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13328 (set (match_dup 0) (neg:SI (match_dup 0)))]
13331 (define_insn_and_split ""
13332 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13333 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13334 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13338 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13339 (set (match_dup 0) (neg:DI (match_dup 0)))]
13343 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13345 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13346 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13348 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13349 (gtu:SI (match_dup 1) (match_dup 2)))]
13352 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13354 [(set_attr "type" "compare")
13355 (set_attr "length" "12,16")])
13358 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13360 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13361 (match_operand:SI 2 "reg_or_short_operand" ""))
13363 (set (match_operand:SI 0 "gpc_reg_operand" "")
13364 (gtu:SI (match_dup 1) (match_dup 2)))]
13365 "TARGET_32BIT && reload_completed"
13366 [(set (match_dup 0)
13367 (gtu:SI (match_dup 1) (match_dup 2)))
13369 (compare:CC (match_dup 0)
13374 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13376 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13377 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13379 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13380 (gtu:DI (match_dup 1) (match_dup 2)))]
13383 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13385 [(set_attr "type" "compare")
13386 (set_attr "length" "12,16")])
13389 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13391 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13392 (match_operand:DI 2 "reg_or_short_operand" ""))
13394 (set (match_operand:DI 0 "gpc_reg_operand" "")
13395 (gtu:DI (match_dup 1) (match_dup 2)))]
13396 "TARGET_64BIT && reload_completed"
13397 [(set (match_dup 0)
13398 (gtu:DI (match_dup 1) (match_dup 2)))
13400 (compare:CC (match_dup 0)
13404 (define_insn_and_split ""
13405 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13406 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13407 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13408 (match_operand:SI 3 "reg_or_short_operand" "rI")))]
13411 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13412 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13413 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
13416 (define_insn_and_split ""
13417 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13418 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13419 (match_operand:DI 2 "reg_or_short_operand" "rI"))
13420 (match_operand:DI 3 "reg_or_short_operand" "rI")))]
13423 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13424 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13425 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
13429 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13431 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13432 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13433 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13435 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13438 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13439 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
13442 [(set_attr "type" "compare")
13443 (set_attr "length" "8,12,12,16")])
13446 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13448 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13449 (match_operand:SI 2 "reg_or_short_operand" ""))
13450 (match_operand:SI 3 "gpc_reg_operand" ""))
13452 (clobber (match_scratch:SI 4 ""))]
13453 "TARGET_32BIT && reload_completed"
13454 [(set (match_dup 4)
13455 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13458 (compare:CC (match_dup 4)
13463 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13465 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13466 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13467 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13469 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13472 addic %4,%1,%k2\;addze. %4,%3
13473 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3
13476 [(set_attr "type" "compare")
13477 (set_attr "length" "8,12,12,16")])
13480 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13482 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13483 (match_operand:DI 2 "reg_or_short_operand" ""))
13484 (match_operand:DI 3 "gpc_reg_operand" ""))
13486 (clobber (match_scratch:DI 4 ""))]
13487 "TARGET_64BIT && reload_completed"
13488 [(set (match_dup 4)
13489 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13492 (compare:CC (match_dup 4)
13497 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13499 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13500 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13501 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13503 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13504 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13507 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13508 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
13511 [(set_attr "type" "compare")
13512 (set_attr "length" "8,12,12,16")])
13515 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13517 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13518 (match_operand:SI 2 "reg_or_short_operand" ""))
13519 (match_operand:SI 3 "gpc_reg_operand" ""))
13521 (set (match_operand:SI 0 "gpc_reg_operand" "")
13522 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13523 "TARGET_32BIT && reload_completed"
13524 [(set (match_dup 0)
13525 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13527 (compare:CC (match_dup 0)
13532 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13534 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13535 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13536 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13538 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13539 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13542 addic %0,%1,%k2\;addze. %0,%3
13543 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3
13546 [(set_attr "type" "compare")
13547 (set_attr "length" "8,12,12,16")])
13550 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13552 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13553 (match_operand:DI 2 "reg_or_short_operand" ""))
13554 (match_operand:DI 3 "gpc_reg_operand" ""))
13556 (set (match_operand:DI 0 "gpc_reg_operand" "")
13557 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13558 "TARGET_64BIT && reload_completed"
13559 [(set (match_dup 0)
13560 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13562 (compare:CC (match_dup 0)
13567 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13568 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13569 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13571 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13572 [(set_attr "type" "two")
13573 (set_attr "length" "8")])
13576 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13577 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13578 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13580 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13581 [(set_attr "type" "two")
13582 (set_attr "length" "8")])
13584 ;; Define both directions of branch and return. If we need a reload
13585 ;; register, we'd rather use CR0 since it is much easier to copy a
13586 ;; register CC value to there.
13590 (if_then_else (match_operator 1 "branch_comparison_operator"
13592 "cc_reg_operand" "y")
13594 (label_ref (match_operand 0 "" ""))
13599 return output_cbranch (operands[1], \"%l0\", 0, insn);
13601 [(set_attr "type" "branch")])
13605 (if_then_else (match_operator 0 "branch_comparison_operator"
13607 "cc_reg_operand" "y")
13614 return output_cbranch (operands[0], NULL, 0, insn);
13616 [(set_attr "type" "branch")
13617 (set_attr "length" "4")])
13621 (if_then_else (match_operator 1 "branch_comparison_operator"
13623 "cc_reg_operand" "y")
13626 (label_ref (match_operand 0 "" ""))))]
13630 return output_cbranch (operands[1], \"%l0\", 1, insn);
13632 [(set_attr "type" "branch")])
13636 (if_then_else (match_operator 0 "branch_comparison_operator"
13638 "cc_reg_operand" "y")
13645 return output_cbranch (operands[0], NULL, 1, insn);
13647 [(set_attr "type" "branch")
13648 (set_attr "length" "4")])
13650 ;; Logic on condition register values.
13652 ; This pattern matches things like
13653 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13654 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13656 ; which are generated by the branch logic.
13657 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13659 (define_insn "*cceq_ior_compare"
13660 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13661 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13662 [(match_operator:SI 2
13663 "branch_positive_comparison_operator"
13665 "cc_reg_operand" "y,y")
13667 (match_operator:SI 4
13668 "branch_positive_comparison_operator"
13670 "cc_reg_operand" "0,y")
13674 "cr%q1 %E0,%j2,%j4"
13675 [(set_attr "type" "cr_logical,delayed_cr")])
13677 ; Why is the constant -1 here, but 1 in the previous pattern?
13678 ; Because ~1 has all but the low bit set.
13680 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13681 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13682 [(not:SI (match_operator:SI 2
13683 "branch_positive_comparison_operator"
13685 "cc_reg_operand" "y,y")
13687 (match_operator:SI 4
13688 "branch_positive_comparison_operator"
13690 "cc_reg_operand" "0,y")
13694 "cr%q1 %E0,%j2,%j4"
13695 [(set_attr "type" "cr_logical,delayed_cr")])
13697 (define_insn "*cceq_rev_compare"
13698 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13699 (compare:CCEQ (match_operator:SI 1
13700 "branch_positive_comparison_operator"
13702 "cc_reg_operand" "0,y")
13706 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13707 [(set_attr "type" "cr_logical,delayed_cr")])
13709 ;; If we are comparing the result of two comparisons, this can be done
13710 ;; using creqv or crxor.
13712 (define_insn_and_split ""
13713 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13714 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13715 [(match_operand 2 "cc_reg_operand" "y")
13717 (match_operator 3 "branch_comparison_operator"
13718 [(match_operand 4 "cc_reg_operand" "y")
13723 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13727 int positive_1, positive_2;
13729 positive_1 = branch_positive_comparison_operator (operands[1],
13730 GET_MODE (operands[1]));
13731 positive_2 = branch_positive_comparison_operator (operands[3],
13732 GET_MODE (operands[3]));
13735 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13736 GET_CODE (operands[1])),
13738 operands[2], const0_rtx);
13739 else if (GET_MODE (operands[1]) != SImode)
13740 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13741 operands[2], const0_rtx);
13744 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13745 GET_CODE (operands[3])),
13747 operands[4], const0_rtx);
13748 else if (GET_MODE (operands[3]) != SImode)
13749 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13750 operands[4], const0_rtx);
13752 if (positive_1 == positive_2)
13754 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13755 operands[5] = constm1_rtx;
13759 operands[5] = const1_rtx;
13763 ;; Unconditional branch and return.
13765 (define_insn "jump"
13767 (label_ref (match_operand 0 "" "")))]
13770 [(set_attr "type" "branch")])
13772 (define_insn "return"
13776 [(set_attr "type" "jmpreg")])
13778 (define_expand "indirect_jump"
13779 [(set (pc) (match_operand 0 "register_operand" ""))]
13784 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
13786 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
13790 (define_insn "indirect_jumpsi"
13791 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
13796 [(set_attr "type" "jmpreg")])
13798 (define_insn "indirect_jumpdi"
13799 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
13804 [(set_attr "type" "jmpreg")])
13806 ;; Table jump for switch statements:
13807 (define_expand "tablejump"
13808 [(use (match_operand 0 "" ""))
13809 (use (label_ref (match_operand 1 "" "")))]
13814 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13816 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13820 (define_expand "tablejumpsi"
13821 [(set (match_dup 3)
13822 (plus:SI (match_operand:SI 0 "" "")
13824 (parallel [(set (pc) (match_dup 3))
13825 (use (label_ref (match_operand 1 "" "")))])]
13828 { operands[0] = force_reg (SImode, operands[0]);
13829 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13830 operands[3] = gen_reg_rtx (SImode);
13833 (define_expand "tablejumpdi"
13834 [(set (match_dup 4)
13835 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13837 (plus:DI (match_dup 4)
13839 (parallel [(set (pc) (match_dup 3))
13840 (use (label_ref (match_operand 1 "" "")))])]
13843 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13844 operands[3] = gen_reg_rtx (DImode);
13845 operands[4] = gen_reg_rtx (DImode);
13850 (match_operand:SI 0 "register_operand" "c,*l"))
13851 (use (label_ref (match_operand 1 "" "")))]
13856 [(set_attr "type" "jmpreg")])
13860 (match_operand:DI 0 "register_operand" "c,*l"))
13861 (use (label_ref (match_operand 1 "" "")))]
13866 [(set_attr "type" "jmpreg")])
13871 "{cror 0,0,0|nop}")
13873 ;; Define the subtract-one-and-jump insns, starting with the template
13874 ;; so loop.c knows what to generate.
13876 (define_expand "doloop_end"
13877 [(use (match_operand 0 "" "")) ; loop pseudo
13878 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13879 (use (match_operand 2 "" "")) ; max iterations
13880 (use (match_operand 3 "" "")) ; loop level
13881 (use (match_operand 4 "" ""))] ; label
13885 /* Only use this on innermost loops. */
13886 if (INTVAL (operands[3]) > 1)
13890 if (GET_MODE (operands[0]) != DImode)
13892 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13896 if (GET_MODE (operands[0]) != SImode)
13898 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13903 (define_expand "ctrsi"
13904 [(parallel [(set (pc)
13905 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
13907 (label_ref (match_operand 1 "" ""))
13910 (plus:SI (match_dup 0)
13912 (clobber (match_scratch:CC 2 ""))
13913 (clobber (match_scratch:SI 3 ""))])]
13917 (define_expand "ctrdi"
13918 [(parallel [(set (pc)
13919 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
13921 (label_ref (match_operand 1 "" ""))
13924 (plus:DI (match_dup 0)
13926 (clobber (match_scratch:CC 2 ""))
13927 (clobber (match_scratch:DI 3 ""))])]
13931 ;; We need to be able to do this for any operand, including MEM, or we
13932 ;; will cause reload to blow up since we don't allow output reloads on
13934 ;; For the length attribute to be calculated correctly, the
13935 ;; label MUST be operand 0.
13937 (define_insn "*ctrsi_internal1"
13939 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
13941 (label_ref (match_operand 0 "" ""))
13943 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13944 (plus:SI (match_dup 1)
13946 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13947 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
13951 if (which_alternative != 0)
13953 else if (get_attr_length (insn) == 4)
13954 return \"{bdn|bdnz} %l0\";
13956 return \"bdz $+8\;b %l0\";
13958 [(set_attr "type" "branch")
13959 (set_attr "length" "*,12,16,16")])
13961 (define_insn "*ctrsi_internal2"
13963 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
13966 (label_ref (match_operand 0 "" ""))))
13967 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13968 (plus:SI (match_dup 1)
13970 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13971 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
13975 if (which_alternative != 0)
13977 else if (get_attr_length (insn) == 4)
13978 return \"bdz %l0\";
13980 return \"{bdn|bdnz} $+8\;b %l0\";
13982 [(set_attr "type" "branch")
13983 (set_attr "length" "*,12,16,16")])
13985 (define_insn "*ctrdi_internal1"
13987 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
13989 (label_ref (match_operand 0 "" ""))
13991 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13992 (plus:DI (match_dup 1)
13994 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13995 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
13999 if (which_alternative != 0)
14001 else if (get_attr_length (insn) == 4)
14002 return \"{bdn|bdnz} %l0\";
14004 return \"bdz $+8\;b %l0\";
14006 [(set_attr "type" "branch")
14007 (set_attr "length" "*,12,16,16")])
14009 (define_insn "*ctrdi_internal2"
14011 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14014 (label_ref (match_operand 0 "" ""))))
14015 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14016 (plus:DI (match_dup 1)
14018 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14019 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14023 if (which_alternative != 0)
14025 else if (get_attr_length (insn) == 4)
14026 return \"bdz %l0\";
14028 return \"{bdn|bdnz} $+8\;b %l0\";
14030 [(set_attr "type" "branch")
14031 (set_attr "length" "*,12,16,16")])
14033 ;; Similar but use EQ
14035 (define_insn "*ctrsi_internal5"
14037 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14039 (label_ref (match_operand 0 "" ""))
14041 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14042 (plus:SI (match_dup 1)
14044 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14045 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14049 if (which_alternative != 0)
14051 else if (get_attr_length (insn) == 4)
14052 return \"bdz %l0\";
14054 return \"{bdn|bdnz} $+8\;b %l0\";
14056 [(set_attr "type" "branch")
14057 (set_attr "length" "*,12,16,16")])
14059 (define_insn "*ctrsi_internal6"
14061 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14064 (label_ref (match_operand 0 "" ""))))
14065 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14066 (plus:SI (match_dup 1)
14068 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14069 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14073 if (which_alternative != 0)
14075 else if (get_attr_length (insn) == 4)
14076 return \"{bdn|bdnz} %l0\";
14078 return \"bdz $+8\;b %l0\";
14080 [(set_attr "type" "branch")
14081 (set_attr "length" "*,12,16,16")])
14083 (define_insn "*ctrdi_internal5"
14085 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14087 (label_ref (match_operand 0 "" ""))
14089 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14090 (plus:DI (match_dup 1)
14092 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14093 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14097 if (which_alternative != 0)
14099 else if (get_attr_length (insn) == 4)
14100 return \"bdz %l0\";
14102 return \"{bdn|bdnz} $+8\;b %l0\";
14104 [(set_attr "type" "branch")
14105 (set_attr "length" "*,12,16,16")])
14107 (define_insn "*ctrdi_internal6"
14109 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14112 (label_ref (match_operand 0 "" ""))))
14113 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14114 (plus:DI (match_dup 1)
14116 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14117 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14121 if (which_alternative != 0)
14123 else if (get_attr_length (insn) == 4)
14124 return \"{bdn|bdnz} %l0\";
14126 return \"bdz $+8\;b %l0\";
14128 [(set_attr "type" "branch")
14129 (set_attr "length" "*,12,16,16")])
14131 ;; Now the splitters if we could not allocate the CTR register
14135 (if_then_else (match_operator 2 "comparison_operator"
14136 [(match_operand:SI 1 "gpc_reg_operand" "")
14138 (match_operand 5 "" "")
14139 (match_operand 6 "" "")))
14140 (set (match_operand:SI 0 "gpc_reg_operand" "")
14141 (plus:SI (match_dup 1)
14143 (clobber (match_scratch:CC 3 ""))
14144 (clobber (match_scratch:SI 4 ""))]
14145 "TARGET_32BIT && reload_completed"
14146 [(parallel [(set (match_dup 3)
14147 (compare:CC (plus:SI (match_dup 1)
14151 (plus:SI (match_dup 1)
14153 (set (pc) (if_then_else (match_dup 7)
14157 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14158 operands[3], const0_rtx); }")
14162 (if_then_else (match_operator 2 "comparison_operator"
14163 [(match_operand:SI 1 "gpc_reg_operand" "")
14165 (match_operand 5 "" "")
14166 (match_operand 6 "" "")))
14167 (set (match_operand:SI 0 "nonimmediate_operand" "")
14168 (plus:SI (match_dup 1) (const_int -1)))
14169 (clobber (match_scratch:CC 3 ""))
14170 (clobber (match_scratch:SI 4 ""))]
14171 "TARGET_32BIT && reload_completed
14172 && ! gpc_reg_operand (operands[0], SImode)"
14173 [(parallel [(set (match_dup 3)
14174 (compare:CC (plus:SI (match_dup 1)
14178 (plus:SI (match_dup 1)
14182 (set (pc) (if_then_else (match_dup 7)
14186 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14187 operands[3], const0_rtx); }")
14190 (if_then_else (match_operator 2 "comparison_operator"
14191 [(match_operand:DI 1 "gpc_reg_operand" "")
14193 (match_operand 5 "" "")
14194 (match_operand 6 "" "")))
14195 (set (match_operand:DI 0 "gpc_reg_operand" "")
14196 (plus:DI (match_dup 1)
14198 (clobber (match_scratch:CC 3 ""))
14199 (clobber (match_scratch:DI 4 ""))]
14200 "TARGET_64BIT && reload_completed"
14201 [(parallel [(set (match_dup 3)
14202 (compare:CC (plus:DI (match_dup 1)
14206 (plus:DI (match_dup 1)
14208 (set (pc) (if_then_else (match_dup 7)
14212 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14213 operands[3], const0_rtx); }")
14217 (if_then_else (match_operator 2 "comparison_operator"
14218 [(match_operand:DI 1 "gpc_reg_operand" "")
14220 (match_operand 5 "" "")
14221 (match_operand 6 "" "")))
14222 (set (match_operand:DI 0 "nonimmediate_operand" "")
14223 (plus:DI (match_dup 1) (const_int -1)))
14224 (clobber (match_scratch:CC 3 ""))
14225 (clobber (match_scratch:DI 4 ""))]
14226 "TARGET_64BIT && reload_completed
14227 && ! gpc_reg_operand (operands[0], DImode)"
14228 [(parallel [(set (match_dup 3)
14229 (compare:CC (plus:DI (match_dup 1)
14233 (plus:DI (match_dup 1)
14237 (set (pc) (if_then_else (match_dup 7)
14241 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14242 operands[3], const0_rtx); }")
14244 (define_insn "trap"
14245 [(trap_if (const_int 1) (const_int 0))]
14249 (define_expand "conditional_trap"
14250 [(trap_if (match_operator 0 "trap_comparison_operator"
14251 [(match_dup 2) (match_dup 3)])
14252 (match_operand 1 "const_int_operand" ""))]
14254 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14255 operands[2] = rs6000_compare_op0;
14256 operands[3] = rs6000_compare_op1;")
14259 [(trap_if (match_operator 0 "trap_comparison_operator"
14260 [(match_operand:SI 1 "register_operand" "r")
14261 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14264 "{t|tw}%V0%I2 %1,%2")
14267 [(trap_if (match_operator 0 "trap_comparison_operator"
14268 [(match_operand:DI 1 "register_operand" "r")
14269 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14274 ;; Insns related to generating the function prologue and epilogue.
14276 (define_expand "prologue"
14277 [(use (const_int 0))]
14278 "TARGET_SCHED_PROLOG"
14281 rs6000_emit_prologue ();
14285 (define_insn "*movesi_from_cr_one"
14286 [(match_parallel 0 "mfcr_operation"
14287 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14288 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14289 (match_operand 3 "immediate_operand" "n")]
14290 UNSPEC_MOVESI_FROM_CR))])]
14296 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14298 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14299 operands[4] = GEN_INT (mask);
14300 output_asm_insn (\"mfcr %1,%4\", operands);
14304 [(set_attr "type" "mfcrf")])
14306 (define_insn "movesi_from_cr"
14307 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14308 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14309 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14310 UNSPEC_MOVESI_FROM_CR))]
14313 [(set_attr "type" "mfcr")])
14315 (define_insn "*stmw"
14316 [(match_parallel 0 "stmw_operation"
14317 [(set (match_operand:SI 1 "memory_operand" "=m")
14318 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14320 "{stm|stmw} %2,%1")
14322 (define_insn "*save_fpregs_si"
14323 [(match_parallel 0 "any_parallel_operand"
14324 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14325 (use (match_operand:SI 2 "call_operand" "s"))
14326 (set (match_operand:DF 3 "memory_operand" "=m")
14327 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14330 [(set_attr "type" "branch")
14331 (set_attr "length" "4")])
14333 (define_insn "*save_fpregs_di"
14334 [(match_parallel 0 "any_parallel_operand"
14335 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14336 (use (match_operand:DI 2 "call_operand" "s"))
14337 (set (match_operand:DF 3 "memory_operand" "=m")
14338 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14341 [(set_attr "type" "branch")
14342 (set_attr "length" "4")])
14344 ; These are to explain that changes to the stack pointer should
14345 ; not be moved over stores to stack memory.
14346 (define_insn "stack_tie"
14347 [(set (match_operand:BLK 0 "memory_operand" "+m")
14348 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14351 [(set_attr "length" "0")])
14354 (define_expand "epilogue"
14355 [(use (const_int 0))]
14356 "TARGET_SCHED_PROLOG"
14359 rs6000_emit_epilogue (FALSE);
14363 ; On some processors, doing the mtcrf one CC register at a time is
14364 ; faster (like on the 604e). On others, doing them all at once is
14365 ; faster; for instance, on the 601 and 750.
14367 (define_expand "movsi_to_cr_one"
14368 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14369 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14370 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14372 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14374 (define_insn "*movsi_to_cr"
14375 [(match_parallel 0 "mtcrf_operation"
14376 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14377 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14378 (match_operand 3 "immediate_operand" "n")]
14379 UNSPEC_MOVESI_TO_CR))])]
14385 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14386 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14387 operands[4] = GEN_INT (mask);
14388 return \"mtcrf %4,%2\";
14390 [(set_attr "type" "mtcr")])
14392 (define_insn "*mtcrfsi"
14393 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14394 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14395 (match_operand 2 "immediate_operand" "n")]
14396 UNSPEC_MOVESI_TO_CR))]
14397 "GET_CODE (operands[0]) == REG
14398 && CR_REGNO_P (REGNO (operands[0]))
14399 && GET_CODE (operands[2]) == CONST_INT
14400 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14402 [(set_attr "type" "mtcr")])
14404 ; The load-multiple instructions have similar properties.
14405 ; Note that "load_multiple" is a name known to the machine-independent
14406 ; code that actually corresponds to the powerpc load-string.
14408 (define_insn "*lmw"
14409 [(match_parallel 0 "lmw_operation"
14410 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14411 (match_operand:SI 2 "memory_operand" "m"))])]
14415 (define_insn "*return_internal_si"
14417 (use (match_operand:SI 0 "register_operand" "lc"))]
14420 [(set_attr "type" "jmpreg")])
14422 (define_insn "*return_internal_di"
14424 (use (match_operand:DI 0 "register_operand" "lc"))]
14427 [(set_attr "type" "jmpreg")])
14429 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14430 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14432 (define_insn "*return_and_restore_fpregs_si"
14433 [(match_parallel 0 "any_parallel_operand"
14435 (use (match_operand:SI 1 "register_operand" "l"))
14436 (use (match_operand:SI 2 "call_operand" "s"))
14437 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14438 (match_operand:DF 4 "memory_operand" "m"))])]
14442 (define_insn "*return_and_restore_fpregs_di"
14443 [(match_parallel 0 "any_parallel_operand"
14445 (use (match_operand:DI 1 "register_operand" "l"))
14446 (use (match_operand:DI 2 "call_operand" "s"))
14447 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14448 (match_operand:DF 4 "memory_operand" "m"))])]
14452 ; This is used in compiling the unwind routines.
14453 (define_expand "eh_return"
14454 [(use (match_operand 0 "general_operand" ""))]
14459 emit_insn (gen_eh_set_lr_si (operands[0]));
14461 emit_insn (gen_eh_set_lr_di (operands[0]));
14465 ; We can't expand this before we know where the link register is stored.
14466 (define_insn "eh_set_lr_si"
14467 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
14469 (clobber (match_scratch:SI 1 "=&b"))]
14473 (define_insn "eh_set_lr_di"
14474 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
14476 (clobber (match_scratch:DI 1 "=&b"))]
14481 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14482 (clobber (match_scratch 1 ""))]
14487 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14491 (define_insn "prefetch"
14492 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
14493 (match_operand:SI 1 "const_int_operand" "n")
14494 (match_operand:SI 2 "const_int_operand" "n"))]
14498 if (GET_CODE (operands[0]) == REG)
14499 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14500 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14502 [(set_attr "type" "load")])
14504 ; Atomic instructions
14506 (define_insn "memory_barrier"
14507 [(set (mem:BLK (match_scratch 0 "X"))
14508 (unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_SYNC))]
14512 (define_insn "sync_compare_and_swap<mode>"
14513 [(set (match_operand:GPR 1 "memory_operand" "+Z")
14514 (unspec:GPR [(match_dup 1)
14515 (match_operand:GPR 2 "reg_or_short_operand" "rI")
14516 (match_operand:GPR 3 "gpc_reg_operand" "r")]
14518 (set (match_operand:GPR 0 "gpc_reg_operand" "=&r") (match_dup 1))
14519 (set (mem:BLK (match_scratch 5 "X"))
14520 (unspec:BLK [(mem:BLK (match_scratch 6 "X"))] UNSPEC_SYNC))
14521 (clobber (match_scratch:CC 4 "=&x"))]
14523 "sync\n\t<larx> %0,%y1\n\tcmp<wd>%I2 %0,%2\n\tbne- $+12\n\t<stcx> %3,%y1\n\tbne- $-16\n\tisync"
14524 [(set_attr "length" "28")])
14526 (define_expand "sync_add<mode>"
14527 [(use (match_operand:INT1 0 "memory_operand" ""))
14528 (use (match_operand:INT1 1 "add_operand" ""))]
14532 rs6000_emit_sync (PLUS, <MODE>mode, operands[0], operands[1],
14533 NULL_RTX, NULL_RTX, true);
14537 (define_expand "sync_sub<mode>"
14538 [(use (match_operand:GPR 0 "memory_operand" ""))
14539 (use (match_operand:GPR 1 "gpc_reg_operand" ""))]
14543 rs6000_emit_sync (MINUS, <MODE>mode, operands[0], operands[1],
14544 NULL_RTX, NULL_RTX, true);
14548 (define_expand "sync_ior<mode>"
14549 [(use (match_operand:INT1 0 "memory_operand" ""))
14550 (use (match_operand:INT1 1 "logical_operand" ""))]
14554 rs6000_emit_sync (IOR, <MODE>mode, operands[0], operands[1],
14555 NULL_RTX, NULL_RTX, true);
14559 (define_expand "sync_and<mode>"
14560 [(use (match_operand:INT1 0 "memory_operand" ""))
14561 (use (match_operand:INT1 1 "and_operand" ""))]
14565 rs6000_emit_sync (AND, <MODE>mode, operands[0], operands[1],
14566 NULL_RTX, NULL_RTX, true);
14570 (define_expand "sync_xor<mode>"
14571 [(use (match_operand:INT1 0 "memory_operand" ""))
14572 (use (match_operand:INT1 1 "logical_operand" ""))]
14576 rs6000_emit_sync (XOR, <MODE>mode, operands[0], operands[1],
14577 NULL_RTX, NULL_RTX, true);
14581 (define_expand "sync_nand<mode>"
14582 [(use (match_operand:INT1 0 "memory_operand" ""))
14583 (use (match_operand:INT1 1 "gpc_reg_operand" ""))]
14587 rs6000_emit_sync (AND, <MODE>mode,
14588 gen_rtx_NOT (<MODE>mode, operands[0]),
14590 NULL_RTX, NULL_RTX, true);
14594 (define_expand "sync_old_add<mode>"
14595 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14596 (use (match_operand:INT1 1 "memory_operand" ""))
14597 (use (match_operand:INT1 2 "add_operand" ""))]
14601 rs6000_emit_sync (PLUS, <MODE>mode, operands[1], operands[2],
14602 operands[0], NULL_RTX, true);
14606 (define_expand "sync_old_sub<mode>"
14607 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
14608 (use (match_operand:GPR 1 "memory_operand" ""))
14609 (use (match_operand:GPR 2 "gpc_reg_operand" ""))]
14613 rs6000_emit_sync (MINUS, <MODE>mode, operands[1], operands[2],
14614 operands[0], NULL_RTX, true);
14618 (define_expand "sync_old_ior<mode>"
14619 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14620 (use (match_operand:INT1 1 "memory_operand" ""))
14621 (use (match_operand:INT1 2 "logical_operand" ""))]
14625 rs6000_emit_sync (IOR, <MODE>mode, operands[1], operands[2],
14626 operands[0], NULL_RTX, true);
14630 (define_expand "sync_old_and<mode>"
14631 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14632 (use (match_operand:INT1 1 "memory_operand" ""))
14633 (use (match_operand:INT1 2 "and_operand" ""))]
14637 rs6000_emit_sync (AND, <MODE>mode, operands[1], operands[2],
14638 operands[0], NULL_RTX, true);
14642 (define_expand "sync_old_xor<mode>"
14643 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14644 (use (match_operand:INT1 1 "memory_operand" ""))
14645 (use (match_operand:INT1 2 "logical_operand" ""))]
14649 rs6000_emit_sync (XOR, <MODE>mode, operands[1], operands[2],
14650 operands[0], NULL_RTX, true);
14654 (define_expand "sync_old_nand<mode>"
14655 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14656 (use (match_operand:INT1 1 "memory_operand" ""))
14657 (use (match_operand:INT1 2 "gpc_reg_operand" ""))]
14661 rs6000_emit_sync (AND, <MODE>mode,
14662 gen_rtx_NOT (<MODE>mode, operands[1]),
14664 operands[0], NULL_RTX, true);
14668 (define_expand "sync_new_add<mode>"
14669 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14670 (use (match_operand:INT1 1 "memory_operand" ""))
14671 (use (match_operand:INT1 2 "add_operand" ""))]
14675 rs6000_emit_sync (PLUS, <MODE>mode, operands[1], operands[2],
14676 NULL_RTX, operands[0], true);
14680 (define_expand "sync_new_sub<mode>"
14681 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
14682 (use (match_operand:GPR 1 "memory_operand" ""))
14683 (use (match_operand:GPR 2 "gpc_reg_operand" ""))]
14687 rs6000_emit_sync (MINUS, <MODE>mode, operands[1], operands[2],
14688 NULL_RTX, operands[0], true);
14692 (define_expand "sync_new_ior<mode>"
14693 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14694 (use (match_operand:INT1 1 "memory_operand" ""))
14695 (use (match_operand:INT1 2 "logical_operand" ""))]
14699 rs6000_emit_sync (IOR, <MODE>mode, operands[1], operands[2],
14700 NULL_RTX, operands[0], true);
14704 (define_expand "sync_new_and<mode>"
14705 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14706 (use (match_operand:INT1 1 "memory_operand" ""))
14707 (use (match_operand:INT1 2 "and_operand" ""))]
14711 rs6000_emit_sync (AND, <MODE>mode, operands[1], operands[2],
14712 NULL_RTX, operands[0], true);
14716 (define_expand "sync_new_xor<mode>"
14717 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14718 (use (match_operand:INT1 1 "memory_operand" ""))
14719 (use (match_operand:INT1 2 "logical_operand" ""))]
14723 rs6000_emit_sync (XOR, <MODE>mode, operands[1], operands[2],
14724 NULL_RTX, operands[0], true);
14728 (define_expand "sync_new_nand<mode>"
14729 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14730 (use (match_operand:INT1 1 "memory_operand" ""))
14731 (use (match_operand:INT1 2 "gpc_reg_operand" ""))]
14735 rs6000_emit_sync (AND, <MODE>mode,
14736 gen_rtx_NOT (<MODE>mode, operands[1]),
14738 NULL_RTX, operands[0], true);
14742 ; the sync_*_internal patterns all have these operands:
14743 ; 0 - memory location
14745 ; 2 - value in memory after operation
14746 ; 3 - value in memory immediately before operation
14748 (define_insn "*sync_add<mode>_internal"
14749 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r,&r")
14750 (plus:GPR (match_operand:GPR 0 "memory_operand" "+Z,Z")
14751 (match_operand:GPR 1 "add_operand" "rI,L")))
14752 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b,&b") (match_dup 0))
14754 (unspec:GPR [(plus:GPR (match_dup 0) (match_dup 1))]
14756 (clobber (match_scratch:CC 4 "=&x,&x"))]
14759 <larx> %3,%y0\n\tadd%I1 %2,%3,%1\n\t<stcx> %2,%y0\n\tbne- $-12
14760 <larx> %3,%y0\n\taddis %2,%3,%v1\n\t<stcx> %2,%y0\n\tbne- $-12"
14761 [(set_attr "length" "16,16")])
14763 (define_insn "*sync_addshort_internal"
14764 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r")
14765 (ior:SI (and:SI (plus:SI (match_operand:SI 0 "memory_operand" "+Z")
14766 (match_operand:SI 1 "add_operand" "rI"))
14767 (match_operand:SI 4 "gpc_reg_operand" "r"))
14768 (and:SI (not:SI (match_dup 4)) (match_dup 0))))
14769 (set (match_operand:SI 3 "gpc_reg_operand" "=&b") (match_dup 0))
14771 (unspec:SI [(ior:SI (and:SI (plus:SI (match_dup 0) (match_dup 1))
14773 (and:SI (not:SI (match_dup 4)) (match_dup 0)))]
14775 (clobber (match_scratch:CC 5 "=&x"))
14776 (clobber (match_scratch:SI 6 "=&r"))]
14778 "lwarx %3,%y0\n\tadd%I1 %2,%3,%1\n\tandc %6,%3,%4\n\tand %2,%2,%4\n\tor %2,%2,%6\n\tstwcx. %2,%y0\n\tbne- $-24"
14779 [(set_attr "length" "28")])
14781 (define_insn "*sync_sub<mode>_internal"
14782 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
14783 (minus:GPR (match_operand:GPR 0 "memory_operand" "+Z")
14784 (match_operand:GPR 1 "gpc_reg_operand" "r")))
14785 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
14787 (unspec:GPR [(minus:GPR (match_dup 0) (match_dup 1))]
14789 (clobber (match_scratch:CC 4 "=&x"))]
14791 "<larx> %3,%y0\n\tsubf %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- $-12"
14792 [(set_attr "length" "16")])
14794 (define_insn "*sync_andsi_internal"
14795 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r,&r,&r,&r")
14796 (and:SI (match_operand:SI 0 "memory_operand" "+Z,Z,Z,Z")
14797 (match_operand:SI 1 "and_operand" "r,T,K,L")))
14798 (set (match_operand:SI 3 "gpc_reg_operand" "=&b,&b,&b,&b") (match_dup 0))
14800 (unspec:SI [(and:SI (match_dup 0) (match_dup 1))]
14802 (clobber (match_scratch:CC 4 "=&x,&x,&x,&x"))]
14805 lwarx %3,%y0\n\tand %2,%3,%1\n\tstwcx. %2,%y0\n\tbne- $-12
14806 lwarx %3,%y0\n\trlwinm %2,%3,0,%m1,%M1\n\tstwcx. %2,%y0\n\tbne- $-12
14807 lwarx %3,%y0\n\tandi. %2,%3,%b1\n\tstwcx. %2,%y0\n\tbne- $-12
14808 lwarx %3,%y0\n\tandis. %2,%3,%u1\n\tstwcx. %2,%y0\n\tbne- $-12"
14809 [(set_attr "length" "16,16,16,16")])
14811 (define_insn "*sync_anddi_internal"
14812 [(set (match_operand:DI 2 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
14813 (and:DI (match_operand:DI 0 "memory_operand" "+Z,Z,Z,Z,Z")
14814 (match_operand:DI 1 "and_operand" "r,S,T,K,J")))
14815 (set (match_operand:DI 3 "gpc_reg_operand" "=&b,&b,&b,&b,&b") (match_dup 0))
14817 (unspec:DI [(and:DI (match_dup 0) (match_dup 1))]
14819 (clobber (match_scratch:CC 4 "=&x,&x,&x,&x,&x"))]
14822 ldarx %3,%y0\n\tand %2,%3,%1\n\tstdcx. %2,%y0\n\tbne- $-12
14823 ldarx %3,%y0\n\trldic%B1 %2,%3,0,%S1\n\tstdcx. %2,%y0\n\tbne- $-12
14824 ldarx %3,%y0\n\trlwinm %2,%3,0,%m1,%M1\n\tstdcx. %2,%y0\n\tbne- $-12
14825 ldarx %3,%y0\n\tandi. %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- $-12
14826 ldarx %3,%y0\n\tandis. %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- $-12"
14827 [(set_attr "length" "16,16,16,16,16")])
14829 (define_insn "*sync_boolsi_internal"
14830 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r,&r,&r")
14831 (match_operator:SI 4 "boolean_or_operator"
14832 [(match_operand:SI 0 "memory_operand" "+Z,Z,Z")
14833 (match_operand:SI 1 "logical_operand" "r,K,L")]))
14834 (set (match_operand:SI 3 "gpc_reg_operand" "=&b,&b,&b") (match_dup 0))
14835 (set (match_dup 0) (unspec:SI [(match_dup 4)] UNSPEC_SYNC_OP))
14836 (clobber (match_scratch:CC 5 "=&x,&x,&x"))]
14839 lwarx %3,%y0\n\t%q4 %2,%3,%1\n\tstwcx. %2,%y0\n\tbne- $-12
14840 lwarx %3,%y0\n\t%q4i %2,%3,%b1\n\tstwcx. %2,%y0\n\tbne- $-12
14841 lwarx %3,%y0\n\t%q4is %2,%3,%u1\n\tstwcx. %2,%y0\n\tbne- $-12"
14842 [(set_attr "length" "16,16,16")])
14844 (define_insn "*sync_booldi_internal"
14845 [(set (match_operand:DI 2 "gpc_reg_operand" "=&r,&r,&r")
14846 (match_operator:DI 4 "boolean_or_operator"
14847 [(match_operand:DI 0 "memory_operand" "+Z,Z,Z")
14848 (match_operand:DI 1 "logical_operand" "r,K,JF")]))
14849 (set (match_operand:DI 3 "gpc_reg_operand" "=&b,&b,&b") (match_dup 0))
14850 (set (match_dup 0) (unspec:DI [(match_dup 4)] UNSPEC_SYNC_OP))
14851 (clobber (match_scratch:CC 5 "=&x,&x,&x"))]
14854 ldarx %3,%y0\n\t%q4 %2,%3,%1\n\tstdcx. %2,%y0\n\tbne- $-12
14855 ldarx %3,%y0\n\t%q4i %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- $-12
14856 ldarx %3,%y0\n\t%q4is %2,%3,%u1\n\tstdcx. %2,%y0\n\tbne- $-12"
14857 [(set_attr "length" "16,16,16")])
14859 (define_insn "*sync_boolc<mode>_internal"
14860 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
14861 (match_operator:GPR 4 "boolean_operator"
14862 [(not:GPR (match_operand:GPR 0 "memory_operand" "+Z"))
14863 (match_operand:GPR 1 "gpc_reg_operand" "r")]))
14864 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
14865 (set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP))
14866 (clobber (match_scratch:CC 5 "=&x"))]
14868 "<larx> %3,%y0\n\t%q4 %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- $-12"
14869 [(set_attr "length" "16")])
14871 ; This pattern could also take immediate values of operand 1,
14872 ; since the non-NOT version of the operator is used; but this is not
14873 ; very useful, since in practise operand 1 is a full 32-bit value.
14874 ; Likewise, operand 5 is in practise either <= 2^16 or it is a register.
14875 (define_insn "*sync_boolcshort_internal"
14876 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r")
14877 (match_operator:SI 4 "boolean_operator"
14878 [(xor:SI (match_operand:SI 0 "memory_operand" "+Z")
14879 (match_operand:SI 5 "logical_operand" "rK"))
14880 (match_operand:SI 1 "gpc_reg_operand" "r")]))
14881 (set (match_operand:SI 3 "gpc_reg_operand" "=&b") (match_dup 0))
14882 (set (match_dup 0) (unspec:SI [(match_dup 4)] UNSPEC_SYNC_OP))
14883 (clobber (match_scratch:CC 6 "=&x"))]
14885 "lwarx %3,%y0\n\txor%I2 %2,%3,%5\n\t%q4 %2,%2,%1\n\tstwcx. %2,%y0\n\tbne- $-16"
14886 [(set_attr "length" "20")])
14888 (define_insn "*sync_boolc<mode>_internal2"
14889 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
14890 (match_operator:GPR 4 "boolean_operator"
14891 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
14892 (match_operand:GPR 0 "memory_operand" "+Z")]))
14893 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
14894 (set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP))
14895 (clobber (match_scratch:CC 5 "=&x"))]
14897 "<larx> %3,%y0\n\t%q4 %2,%3,%1\n\t<stcx> %2,%y0\n\tbne- $-12"
14898 [(set_attr "length" "16")])
14900 (define_insn "*sync_boolcc<mode>_internal"
14901 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
14902 (match_operator:GPR 4 "boolean_operator"
14903 [(not:GPR (match_operand:GPR 0 "memory_operand" "+Z"))
14904 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))]))
14905 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
14906 (set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP))
14907 (clobber (match_scratch:CC 5 "=&x"))]
14909 "<larx> %3,%y0\n\t%q4 %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- $-12"
14910 [(set_attr "length" "16")])
14912 (define_insn "isync"
14913 [(set (mem:BLK (match_scratch 0 "X"))
14914 (unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_ISYNC))]
14918 (define_insn "sync_lock_test_and_set<mode>"
14919 [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r")
14920 (match_operand:GPR 1 "memory_operand" "+Z"))
14921 (set (match_dup 1) (unspec:GPR [(match_operand:GPR 2 "gpc_reg_operand" "r")]
14923 (clobber (match_scratch:CC 3 "=&x"))
14924 (set (mem:BLK (match_scratch 4 "X"))
14925 (unspec:BLK [(mem:BLK (match_scratch 5 "X"))] UNSPEC_ISYNC))]
14927 "<larx> %0,%y1\n\t<stcx> %2,%y1\n\tbne- $-8\n\tisync"
14928 [(set_attr "length" "16")])
14930 (define_expand "sync_lock_release<mode>"
14931 [(set (match_operand:INT 0 "memory_operand")
14932 (match_operand:INT 1 "any_operand"))]
14936 emit_insn (gen_lwsync ());
14937 emit_move_insn (operands[0], operands[1]);
14941 ; Some AIX assemblers don't accept lwsync, so we use a .long.
14942 (define_insn "lwsync"
14943 [(set (mem:BLK (match_scratch 0 "X"))
14944 (unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_LWSYNC))]
14946 ".long 0x7c2004ac")
14950 (include "altivec.md")