1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 ;; MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
63 ;; UNSPEC_VOLATILE usage
68 (UNSPECV_EH_RR 9) ; eh_reg_restore
71 ;; Define an insn type attribute. This is used in function unit delay
73 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
74 (const_string "integer"))
77 ; '(pc)' in the following doesn't include the instruction itself; it is
78 ; calculated as if the instruction had zero size.
79 (define_attr "length" ""
80 (if_then_else (eq_attr "type" "branch")
81 (if_then_else (and (ge (minus (match_dup 0) (pc))
83 (lt (minus (match_dup 0) (pc))
89 ;; Processor type -- this attribute must exactly match the processor_type
90 ;; enumeration in rs6000.h.
92 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
93 (const (symbol_ref "rs6000_cpu_attr")))
95 (automata_option "ndfa")
108 (include "power4.md")
109 (include "power5.md")
111 (include "predicates.md")
113 (include "darwin.md")
118 ; This mode macro allows :GPR to be used to indicate the allowable size
119 ; of whole values in GPRs.
120 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
122 ; Any supported integer mode
123 (define_mode_macro INT [QI HI SI DI TI])
125 ; Any supported integer mode that fits in one register
126 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
128 ; This mode macro allows :P to be used for patterns that operate on
129 ; pointer-sized quantities. Exactly one of the two alternatives will match.
130 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
132 ; Various instructions that come in SI and DI forms.
133 (define_mode_attr larx [(SI "lwarx") (DI "ldarx")])
134 (define_mode_attr stcx [(SI "stwcx.") (DI "stdcx.")])
135 (define_mode_attr cmp [(SI "cmpw") (DI "cmpd")])
138 ;; Start with fixed-point load and store insns. Here we put only the more
139 ;; complex forms. Basic data transfer is done later.
141 (define_expand "zero_extendqidi2"
142 [(set (match_operand:DI 0 "gpc_reg_operand" "")
143 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
148 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
149 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
154 [(set_attr "type" "load,*")])
157 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
158 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
160 (clobber (match_scratch:DI 2 "=r,r"))]
165 [(set_attr "type" "compare")
166 (set_attr "length" "4,8")])
169 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
170 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
172 (clobber (match_scratch:DI 2 ""))]
173 "TARGET_POWERPC64 && reload_completed"
175 (zero_extend:DI (match_dup 1)))
177 (compare:CC (match_dup 2)
182 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
183 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
185 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
186 (zero_extend:DI (match_dup 1)))]
191 [(set_attr "type" "compare")
192 (set_attr "length" "4,8")])
195 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
196 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
198 (set (match_operand:DI 0 "gpc_reg_operand" "")
199 (zero_extend:DI (match_dup 1)))]
200 "TARGET_POWERPC64 && reload_completed"
202 (zero_extend:DI (match_dup 1)))
204 (compare:CC (match_dup 0)
208 (define_insn "extendqidi2"
209 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
210 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
215 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
216 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
218 (clobber (match_scratch:DI 2 "=r,r"))]
223 [(set_attr "type" "compare")
224 (set_attr "length" "4,8")])
227 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
228 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
230 (clobber (match_scratch:DI 2 ""))]
231 "TARGET_POWERPC64 && reload_completed"
233 (sign_extend:DI (match_dup 1)))
235 (compare:CC (match_dup 2)
240 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
241 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
243 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
244 (sign_extend:DI (match_dup 1)))]
249 [(set_attr "type" "compare")
250 (set_attr "length" "4,8")])
253 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
254 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
256 (set (match_operand:DI 0 "gpc_reg_operand" "")
257 (sign_extend:DI (match_dup 1)))]
258 "TARGET_POWERPC64 && reload_completed"
260 (sign_extend:DI (match_dup 1)))
262 (compare:CC (match_dup 0)
266 (define_expand "zero_extendhidi2"
267 [(set (match_operand:DI 0 "gpc_reg_operand" "")
268 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
273 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
274 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
279 [(set_attr "type" "load,*")])
282 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
283 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
285 (clobber (match_scratch:DI 2 "=r,r"))]
290 [(set_attr "type" "compare")
291 (set_attr "length" "4,8")])
294 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
295 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
297 (clobber (match_scratch:DI 2 ""))]
298 "TARGET_POWERPC64 && reload_completed"
300 (zero_extend:DI (match_dup 1)))
302 (compare:CC (match_dup 2)
307 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
308 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
310 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
311 (zero_extend:DI (match_dup 1)))]
316 [(set_attr "type" "compare")
317 (set_attr "length" "4,8")])
320 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
321 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
323 (set (match_operand:DI 0 "gpc_reg_operand" "")
324 (zero_extend:DI (match_dup 1)))]
325 "TARGET_POWERPC64 && reload_completed"
327 (zero_extend:DI (match_dup 1)))
329 (compare:CC (match_dup 0)
333 (define_expand "extendhidi2"
334 [(set (match_operand:DI 0 "gpc_reg_operand" "")
335 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
340 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
341 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
346 [(set_attr "type" "load_ext,*")])
349 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
350 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
352 (clobber (match_scratch:DI 2 "=r,r"))]
357 [(set_attr "type" "compare")
358 (set_attr "length" "4,8")])
361 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
362 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
364 (clobber (match_scratch:DI 2 ""))]
365 "TARGET_POWERPC64 && reload_completed"
367 (sign_extend:DI (match_dup 1)))
369 (compare:CC (match_dup 2)
374 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
375 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
377 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
378 (sign_extend:DI (match_dup 1)))]
383 [(set_attr "type" "compare")
384 (set_attr "length" "4,8")])
387 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
388 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
390 (set (match_operand:DI 0 "gpc_reg_operand" "")
391 (sign_extend:DI (match_dup 1)))]
392 "TARGET_POWERPC64 && reload_completed"
394 (sign_extend:DI (match_dup 1)))
396 (compare:CC (match_dup 0)
400 (define_expand "zero_extendsidi2"
401 [(set (match_operand:DI 0 "gpc_reg_operand" "")
402 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
407 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
408 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
413 [(set_attr "type" "load,*")])
416 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
417 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
419 (clobber (match_scratch:DI 2 "=r,r"))]
424 [(set_attr "type" "compare")
425 (set_attr "length" "4,8")])
428 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
429 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
431 (clobber (match_scratch:DI 2 ""))]
432 "TARGET_POWERPC64 && reload_completed"
434 (zero_extend:DI (match_dup 1)))
436 (compare:CC (match_dup 2)
441 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
442 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
444 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
445 (zero_extend:DI (match_dup 1)))]
450 [(set_attr "type" "compare")
451 (set_attr "length" "4,8")])
454 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
455 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
457 (set (match_operand:DI 0 "gpc_reg_operand" "")
458 (zero_extend:DI (match_dup 1)))]
459 "TARGET_POWERPC64 && reload_completed"
461 (zero_extend:DI (match_dup 1)))
463 (compare:CC (match_dup 0)
467 (define_expand "extendsidi2"
468 [(set (match_operand:DI 0 "gpc_reg_operand" "")
469 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
474 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
475 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
480 [(set_attr "type" "load_ext,*")])
483 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
484 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
486 (clobber (match_scratch:DI 2 "=r,r"))]
491 [(set_attr "type" "compare")
492 (set_attr "length" "4,8")])
495 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
496 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
498 (clobber (match_scratch:DI 2 ""))]
499 "TARGET_POWERPC64 && reload_completed"
501 (sign_extend:DI (match_dup 1)))
503 (compare:CC (match_dup 2)
508 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
509 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
511 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
512 (sign_extend:DI (match_dup 1)))]
517 [(set_attr "type" "compare")
518 (set_attr "length" "4,8")])
521 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
522 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
524 (set (match_operand:DI 0 "gpc_reg_operand" "")
525 (sign_extend:DI (match_dup 1)))]
526 "TARGET_POWERPC64 && reload_completed"
528 (sign_extend:DI (match_dup 1)))
530 (compare:CC (match_dup 0)
534 (define_expand "zero_extendqisi2"
535 [(set (match_operand:SI 0 "gpc_reg_operand" "")
536 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
541 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
542 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
546 {rlinm|rlwinm} %0,%1,0,0xff"
547 [(set_attr "type" "load,*")])
550 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
551 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
553 (clobber (match_scratch:SI 2 "=r,r"))]
556 {andil.|andi.} %2,%1,0xff
558 [(set_attr "type" "compare")
559 (set_attr "length" "4,8")])
562 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
563 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
565 (clobber (match_scratch:SI 2 ""))]
568 (zero_extend:SI (match_dup 1)))
570 (compare:CC (match_dup 2)
575 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
576 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
578 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
579 (zero_extend:SI (match_dup 1)))]
582 {andil.|andi.} %0,%1,0xff
584 [(set_attr "type" "compare")
585 (set_attr "length" "4,8")])
588 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
589 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
591 (set (match_operand:SI 0 "gpc_reg_operand" "")
592 (zero_extend:SI (match_dup 1)))]
595 (zero_extend:SI (match_dup 1)))
597 (compare:CC (match_dup 0)
601 (define_expand "extendqisi2"
602 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
603 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
608 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
609 else if (TARGET_POWER)
610 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
612 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
616 (define_insn "extendqisi2_ppc"
617 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
618 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
623 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
624 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
626 (clobber (match_scratch:SI 2 "=r,r"))]
631 [(set_attr "type" "compare")
632 (set_attr "length" "4,8")])
635 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
636 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
638 (clobber (match_scratch:SI 2 ""))]
639 "TARGET_POWERPC && reload_completed"
641 (sign_extend:SI (match_dup 1)))
643 (compare:CC (match_dup 2)
648 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
649 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
651 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
652 (sign_extend:SI (match_dup 1)))]
657 [(set_attr "type" "compare")
658 (set_attr "length" "4,8")])
661 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
662 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
664 (set (match_operand:SI 0 "gpc_reg_operand" "")
665 (sign_extend:SI (match_dup 1)))]
666 "TARGET_POWERPC && reload_completed"
668 (sign_extend:SI (match_dup 1)))
670 (compare:CC (match_dup 0)
674 (define_expand "extendqisi2_power"
675 [(parallel [(set (match_dup 2)
676 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
678 (clobber (scratch:SI))])
679 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
680 (ashiftrt:SI (match_dup 2)
682 (clobber (scratch:SI))])]
685 { operands[1] = gen_lowpart (SImode, operands[1]);
686 operands[2] = gen_reg_rtx (SImode); }")
688 (define_expand "extendqisi2_no_power"
690 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
692 (set (match_operand:SI 0 "gpc_reg_operand" "")
693 (ashiftrt:SI (match_dup 2)
695 "! TARGET_POWER && ! TARGET_POWERPC"
697 { operands[1] = gen_lowpart (SImode, operands[1]);
698 operands[2] = gen_reg_rtx (SImode); }")
700 (define_expand "zero_extendqihi2"
701 [(set (match_operand:HI 0 "gpc_reg_operand" "")
702 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
707 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
708 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
712 {rlinm|rlwinm} %0,%1,0,0xff"
713 [(set_attr "type" "load,*")])
716 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
717 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
719 (clobber (match_scratch:HI 2 "=r,r"))]
722 {andil.|andi.} %2,%1,0xff
724 [(set_attr "type" "compare")
725 (set_attr "length" "4,8")])
728 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
729 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
731 (clobber (match_scratch:HI 2 ""))]
734 (zero_extend:HI (match_dup 1)))
736 (compare:CC (match_dup 2)
741 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
742 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
744 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
745 (zero_extend:HI (match_dup 1)))]
748 {andil.|andi.} %0,%1,0xff
750 [(set_attr "type" "compare")
751 (set_attr "length" "4,8")])
754 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
755 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
757 (set (match_operand:HI 0 "gpc_reg_operand" "")
758 (zero_extend:HI (match_dup 1)))]
761 (zero_extend:HI (match_dup 1)))
763 (compare:CC (match_dup 0)
767 (define_expand "extendqihi2"
768 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
769 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
774 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
775 else if (TARGET_POWER)
776 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
778 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
782 (define_insn "extendqihi2_ppc"
783 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
784 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
789 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
790 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
792 (clobber (match_scratch:HI 2 "=r,r"))]
797 [(set_attr "type" "compare")
798 (set_attr "length" "4,8")])
801 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
802 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
804 (clobber (match_scratch:HI 2 ""))]
805 "TARGET_POWERPC && reload_completed"
807 (sign_extend:HI (match_dup 1)))
809 (compare:CC (match_dup 2)
814 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
815 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
817 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
818 (sign_extend:HI (match_dup 1)))]
823 [(set_attr "type" "compare")
824 (set_attr "length" "4,8")])
827 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
828 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
830 (set (match_operand:HI 0 "gpc_reg_operand" "")
831 (sign_extend:HI (match_dup 1)))]
832 "TARGET_POWERPC && reload_completed"
834 (sign_extend:HI (match_dup 1)))
836 (compare:CC (match_dup 0)
840 (define_expand "extendqihi2_power"
841 [(parallel [(set (match_dup 2)
842 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
844 (clobber (scratch:SI))])
845 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
846 (ashiftrt:SI (match_dup 2)
848 (clobber (scratch:SI))])]
851 { operands[0] = gen_lowpart (SImode, operands[0]);
852 operands[1] = gen_lowpart (SImode, operands[1]);
853 operands[2] = gen_reg_rtx (SImode); }")
855 (define_expand "extendqihi2_no_power"
857 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
859 (set (match_operand:HI 0 "gpc_reg_operand" "")
860 (ashiftrt:SI (match_dup 2)
862 "! TARGET_POWER && ! TARGET_POWERPC"
864 { operands[0] = gen_lowpart (SImode, operands[0]);
865 operands[1] = gen_lowpart (SImode, operands[1]);
866 operands[2] = gen_reg_rtx (SImode); }")
868 (define_expand "zero_extendhisi2"
869 [(set (match_operand:SI 0 "gpc_reg_operand" "")
870 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
875 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
876 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
880 {rlinm|rlwinm} %0,%1,0,0xffff"
881 [(set_attr "type" "load,*")])
884 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
885 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
887 (clobber (match_scratch:SI 2 "=r,r"))]
890 {andil.|andi.} %2,%1,0xffff
892 [(set_attr "type" "compare")
893 (set_attr "length" "4,8")])
896 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
897 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
899 (clobber (match_scratch:SI 2 ""))]
902 (zero_extend:SI (match_dup 1)))
904 (compare:CC (match_dup 2)
909 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
910 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
912 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
913 (zero_extend:SI (match_dup 1)))]
916 {andil.|andi.} %0,%1,0xffff
918 [(set_attr "type" "compare")
919 (set_attr "length" "4,8")])
922 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
923 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
925 (set (match_operand:SI 0 "gpc_reg_operand" "")
926 (zero_extend:SI (match_dup 1)))]
929 (zero_extend:SI (match_dup 1)))
931 (compare:CC (match_dup 0)
935 (define_expand "extendhisi2"
936 [(set (match_operand:SI 0 "gpc_reg_operand" "")
937 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
942 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
943 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
948 [(set_attr "type" "load_ext,*")])
951 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
952 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
954 (clobber (match_scratch:SI 2 "=r,r"))]
959 [(set_attr "type" "compare")
960 (set_attr "length" "4,8")])
963 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
964 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
966 (clobber (match_scratch:SI 2 ""))]
969 (sign_extend:SI (match_dup 1)))
971 (compare:CC (match_dup 2)
976 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
977 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
979 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
980 (sign_extend:SI (match_dup 1)))]
985 [(set_attr "type" "compare")
986 (set_attr "length" "4,8")])
989 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
990 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
992 (set (match_operand:SI 0 "gpc_reg_operand" "")
993 (sign_extend:SI (match_dup 1)))]
996 (sign_extend:SI (match_dup 1)))
998 (compare:CC (match_dup 0)
1002 ;; Fixed-point arithmetic insns.
1004 ;; Discourage ai/addic because of carry but provide it in an alternative
1005 ;; allowing register zero as source.
1006 (define_expand "addsi3"
1007 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1008 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1009 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1013 if (GET_CODE (operands[2]) == CONST_INT
1014 && ! add_operand (operands[2], SImode))
1016 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1017 ? operands[0] : gen_reg_rtx (SImode));
1019 HOST_WIDE_INT val = INTVAL (operands[2]);
1020 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1021 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1023 /* The ordering here is important for the prolog expander.
1024 When space is allocated from the stack, adding 'low' first may
1025 produce a temporary deallocation (which would be bad). */
1026 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
1027 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
1032 (define_insn "*addsi3_internal1"
1033 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1034 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
1035 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1039 {cal %0,%2(%1)|addi %0,%1,%2}
1041 {cau|addis} %0,%1,%v2"
1042 [(set_attr "length" "4,4,4,4")])
1044 (define_insn "addsi3_high"
1045 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1046 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1047 (high:SI (match_operand 2 "" ""))))]
1048 "TARGET_MACHO && !TARGET_64BIT"
1049 "{cau|addis} %0,%1,ha16(%2)"
1050 [(set_attr "length" "4")])
1052 (define_insn "*addsi3_internal2"
1053 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1054 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1055 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1057 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1060 {cax.|add.} %3,%1,%2
1061 {ai.|addic.} %3,%1,%2
1064 [(set_attr "type" "fast_compare,compare,compare,compare")
1065 (set_attr "length" "4,4,8,8")])
1068 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1069 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1070 (match_operand:SI 2 "reg_or_short_operand" ""))
1072 (clobber (match_scratch:SI 3 ""))]
1073 "TARGET_32BIT && reload_completed"
1075 (plus:SI (match_dup 1)
1078 (compare:CC (match_dup 3)
1082 (define_insn "*addsi3_internal3"
1083 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1084 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1085 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1087 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1088 (plus:SI (match_dup 1)
1092 {cax.|add.} %0,%1,%2
1093 {ai.|addic.} %0,%1,%2
1096 [(set_attr "type" "fast_compare,compare,compare,compare")
1097 (set_attr "length" "4,4,8,8")])
1100 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1101 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1102 (match_operand:SI 2 "reg_or_short_operand" ""))
1104 (set (match_operand:SI 0 "gpc_reg_operand" "")
1105 (plus:SI (match_dup 1) (match_dup 2)))]
1106 "TARGET_32BIT && reload_completed"
1108 (plus:SI (match_dup 1)
1111 (compare:CC (match_dup 0)
1115 ;; Split an add that we can't do in one insn into two insns, each of which
1116 ;; does one 16-bit part. This is used by combine. Note that the low-order
1117 ;; add should be last in case the result gets used in an address.
1120 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1121 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1122 (match_operand:SI 2 "non_add_cint_operand" "")))]
1124 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1125 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1128 HOST_WIDE_INT val = INTVAL (operands[2]);
1129 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1130 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1132 operands[3] = GEN_INT (rest);
1133 operands[4] = GEN_INT (low);
1136 (define_insn "one_cmplsi2"
1137 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1138 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1143 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1144 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1146 (clobber (match_scratch:SI 2 "=r,r"))]
1151 [(set_attr "type" "compare")
1152 (set_attr "length" "4,8")])
1155 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1156 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1158 (clobber (match_scratch:SI 2 ""))]
1159 "TARGET_32BIT && reload_completed"
1161 (not:SI (match_dup 1)))
1163 (compare:CC (match_dup 2)
1168 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1169 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1171 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1172 (not:SI (match_dup 1)))]
1177 [(set_attr "type" "compare")
1178 (set_attr "length" "4,8")])
1181 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1182 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1184 (set (match_operand:SI 0 "gpc_reg_operand" "")
1185 (not:SI (match_dup 1)))]
1186 "TARGET_32BIT && reload_completed"
1188 (not:SI (match_dup 1)))
1190 (compare:CC (match_dup 0)
1195 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1196 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1197 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1199 "{sf%I1|subf%I1c} %0,%2,%1")
1202 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1203 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1204 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1211 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1212 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1213 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1215 (clobber (match_scratch:SI 3 "=r,r"))]
1218 {sf.|subfc.} %3,%2,%1
1220 [(set_attr "type" "compare")
1221 (set_attr "length" "4,8")])
1224 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1225 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1226 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1228 (clobber (match_scratch:SI 3 "=r,r"))]
1229 "TARGET_POWERPC && TARGET_32BIT"
1233 [(set_attr "type" "fast_compare")
1234 (set_attr "length" "4,8")])
1237 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1238 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1239 (match_operand:SI 2 "gpc_reg_operand" ""))
1241 (clobber (match_scratch:SI 3 ""))]
1242 "TARGET_32BIT && reload_completed"
1244 (minus:SI (match_dup 1)
1247 (compare:CC (match_dup 3)
1252 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1253 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1254 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1256 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1257 (minus:SI (match_dup 1) (match_dup 2)))]
1260 {sf.|subfc.} %0,%2,%1
1262 [(set_attr "type" "compare")
1263 (set_attr "length" "4,8")])
1266 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1267 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1268 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1270 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1271 (minus:SI (match_dup 1)
1273 "TARGET_POWERPC && TARGET_32BIT"
1277 [(set_attr "type" "fast_compare")
1278 (set_attr "length" "4,8")])
1281 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1282 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1283 (match_operand:SI 2 "gpc_reg_operand" ""))
1285 (set (match_operand:SI 0 "gpc_reg_operand" "")
1286 (minus:SI (match_dup 1)
1288 "TARGET_32BIT && reload_completed"
1290 (minus:SI (match_dup 1)
1293 (compare:CC (match_dup 0)
1297 (define_expand "subsi3"
1298 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1299 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1300 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1304 if (GET_CODE (operands[2]) == CONST_INT)
1306 emit_insn (gen_addsi3 (operands[0], operands[1],
1307 negate_rtx (SImode, operands[2])));
1312 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1313 ;; instruction and some auxiliary computations. Then we just have a single
1314 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1317 (define_expand "sminsi3"
1319 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1320 (match_operand:SI 2 "reg_or_short_operand" ""))
1322 (minus:SI (match_dup 2) (match_dup 1))))
1323 (set (match_operand:SI 0 "gpc_reg_operand" "")
1324 (minus:SI (match_dup 2) (match_dup 3)))]
1325 "TARGET_POWER || TARGET_ISEL"
1330 operands[2] = force_reg (SImode, operands[2]);
1331 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1335 operands[3] = gen_reg_rtx (SImode);
1339 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1340 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1341 (match_operand:SI 2 "reg_or_short_operand" "")))
1342 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1345 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1347 (minus:SI (match_dup 2) (match_dup 1))))
1348 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1351 (define_expand "smaxsi3"
1353 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1354 (match_operand:SI 2 "reg_or_short_operand" ""))
1356 (minus:SI (match_dup 2) (match_dup 1))))
1357 (set (match_operand:SI 0 "gpc_reg_operand" "")
1358 (plus:SI (match_dup 3) (match_dup 1)))]
1359 "TARGET_POWER || TARGET_ISEL"
1364 operands[2] = force_reg (SImode, operands[2]);
1365 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1368 operands[3] = gen_reg_rtx (SImode);
1372 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1373 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1374 (match_operand:SI 2 "reg_or_short_operand" "")))
1375 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1378 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1380 (minus:SI (match_dup 2) (match_dup 1))))
1381 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1384 (define_expand "uminsi3"
1385 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1387 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1389 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1391 (minus:SI (match_dup 4) (match_dup 3))))
1392 (set (match_operand:SI 0 "gpc_reg_operand" "")
1393 (minus:SI (match_dup 2) (match_dup 3)))]
1394 "TARGET_POWER || TARGET_ISEL"
1399 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1402 operands[3] = gen_reg_rtx (SImode);
1403 operands[4] = gen_reg_rtx (SImode);
1404 operands[5] = GEN_INT (-2147483647 - 1);
1407 (define_expand "umaxsi3"
1408 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1410 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1412 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1414 (minus:SI (match_dup 4) (match_dup 3))))
1415 (set (match_operand:SI 0 "gpc_reg_operand" "")
1416 (plus:SI (match_dup 3) (match_dup 1)))]
1417 "TARGET_POWER || TARGET_ISEL"
1422 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1425 operands[3] = gen_reg_rtx (SImode);
1426 operands[4] = gen_reg_rtx (SImode);
1427 operands[5] = GEN_INT (-2147483647 - 1);
1431 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1432 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1433 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1435 (minus:SI (match_dup 2) (match_dup 1))))]
1440 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1442 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1443 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1445 (minus:SI (match_dup 2) (match_dup 1)))
1447 (clobber (match_scratch:SI 3 "=r,r"))]
1452 [(set_attr "type" "delayed_compare")
1453 (set_attr "length" "4,8")])
1456 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1458 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1459 (match_operand:SI 2 "reg_or_short_operand" ""))
1461 (minus:SI (match_dup 2) (match_dup 1)))
1463 (clobber (match_scratch:SI 3 ""))]
1464 "TARGET_POWER && reload_completed"
1466 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1468 (minus:SI (match_dup 2) (match_dup 1))))
1470 (compare:CC (match_dup 3)
1475 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1477 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1478 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1480 (minus:SI (match_dup 2) (match_dup 1)))
1482 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1483 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1485 (minus:SI (match_dup 2) (match_dup 1))))]
1490 [(set_attr "type" "delayed_compare")
1491 (set_attr "length" "4,8")])
1494 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1496 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1497 (match_operand:SI 2 "reg_or_short_operand" ""))
1499 (minus:SI (match_dup 2) (match_dup 1)))
1501 (set (match_operand:SI 0 "gpc_reg_operand" "")
1502 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1504 (minus:SI (match_dup 2) (match_dup 1))))]
1505 "TARGET_POWER && reload_completed"
1507 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1509 (minus:SI (match_dup 2) (match_dup 1))))
1511 (compare:CC (match_dup 0)
1515 ;; We don't need abs with condition code because such comparisons should
1517 (define_expand "abssi2"
1518 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1519 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1525 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1528 else if (! TARGET_POWER)
1530 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1535 (define_insn "*abssi2_power"
1536 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1537 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1541 (define_insn_and_split "abssi2_isel"
1542 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1543 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1544 (clobber (match_scratch:SI 2 "=&b"))
1545 (clobber (match_scratch:CC 3 "=y"))]
1548 "&& reload_completed"
1549 [(set (match_dup 2) (neg:SI (match_dup 1)))
1551 (compare:CC (match_dup 1)
1554 (if_then_else:SI (ge (match_dup 3)
1560 (define_insn_and_split "abssi2_nopower"
1561 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1562 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1563 (clobber (match_scratch:SI 2 "=&r,&r"))]
1564 "! TARGET_POWER && ! TARGET_ISEL"
1566 "&& reload_completed"
1567 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1568 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1569 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1572 (define_insn "*nabs_power"
1573 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1574 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1578 (define_insn_and_split "*nabs_nopower"
1579 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1580 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1581 (clobber (match_scratch:SI 2 "=&r,&r"))]
1584 "&& reload_completed"
1585 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1586 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1587 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1590 (define_insn "negsi2"
1591 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1592 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1597 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1598 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1600 (clobber (match_scratch:SI 2 "=r,r"))]
1605 [(set_attr "type" "fast_compare")
1606 (set_attr "length" "4,8")])
1609 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1610 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1612 (clobber (match_scratch:SI 2 ""))]
1613 "TARGET_32BIT && reload_completed"
1615 (neg:SI (match_dup 1)))
1617 (compare:CC (match_dup 2)
1622 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1623 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1625 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1626 (neg:SI (match_dup 1)))]
1631 [(set_attr "type" "fast_compare")
1632 (set_attr "length" "4,8")])
1635 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1636 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1638 (set (match_operand:SI 0 "gpc_reg_operand" "")
1639 (neg:SI (match_dup 1)))]
1640 "TARGET_32BIT && reload_completed"
1642 (neg:SI (match_dup 1)))
1644 (compare:CC (match_dup 0)
1648 (define_insn "clzsi2"
1649 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1650 (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1652 "{cntlz|cntlzw} %0,%1")
1654 (define_expand "ctzsi2"
1656 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1657 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1659 (clobber (scratch:CC))])
1660 (set (match_dup 4) (clz:SI (match_dup 3)))
1661 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1662 (minus:SI (const_int 31) (match_dup 4)))]
1665 operands[2] = gen_reg_rtx (SImode);
1666 operands[3] = gen_reg_rtx (SImode);
1667 operands[4] = gen_reg_rtx (SImode);
1670 (define_expand "ffssi2"
1672 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1673 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1675 (clobber (scratch:CC))])
1676 (set (match_dup 4) (clz:SI (match_dup 3)))
1677 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1678 (minus:SI (const_int 32) (match_dup 4)))]
1681 operands[2] = gen_reg_rtx (SImode);
1682 operands[3] = gen_reg_rtx (SImode);
1683 operands[4] = gen_reg_rtx (SImode);
1686 (define_expand "mulsi3"
1687 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1688 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1689 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1694 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1696 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1700 (define_insn "mulsi3_mq"
1701 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1702 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1703 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1704 (clobber (match_scratch:SI 3 "=q,q"))]
1707 {muls|mullw} %0,%1,%2
1708 {muli|mulli} %0,%1,%2"
1710 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1711 (const_string "imul3")
1712 (match_operand:SI 2 "short_cint_operand" "")
1713 (const_string "imul2")]
1714 (const_string "imul")))])
1716 (define_insn "mulsi3_no_mq"
1717 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1718 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1719 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1722 {muls|mullw} %0,%1,%2
1723 {muli|mulli} %0,%1,%2"
1725 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1726 (const_string "imul3")
1727 (match_operand:SI 2 "short_cint_operand" "")
1728 (const_string "imul2")]
1729 (const_string "imul")))])
1731 (define_insn "*mulsi3_mq_internal1"
1732 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1733 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1734 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1736 (clobber (match_scratch:SI 3 "=r,r"))
1737 (clobber (match_scratch:SI 4 "=q,q"))]
1740 {muls.|mullw.} %3,%1,%2
1742 [(set_attr "type" "imul_compare")
1743 (set_attr "length" "4,8")])
1746 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1747 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1748 (match_operand:SI 2 "gpc_reg_operand" ""))
1750 (clobber (match_scratch:SI 3 ""))
1751 (clobber (match_scratch:SI 4 ""))]
1752 "TARGET_POWER && reload_completed"
1753 [(parallel [(set (match_dup 3)
1754 (mult:SI (match_dup 1) (match_dup 2)))
1755 (clobber (match_dup 4))])
1757 (compare:CC (match_dup 3)
1761 (define_insn "*mulsi3_no_mq_internal1"
1762 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1763 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1764 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1766 (clobber (match_scratch:SI 3 "=r,r"))]
1769 {muls.|mullw.} %3,%1,%2
1771 [(set_attr "type" "imul_compare")
1772 (set_attr "length" "4,8")])
1775 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1776 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1777 (match_operand:SI 2 "gpc_reg_operand" ""))
1779 (clobber (match_scratch:SI 3 ""))]
1780 "! TARGET_POWER && reload_completed"
1782 (mult:SI (match_dup 1) (match_dup 2)))
1784 (compare:CC (match_dup 3)
1788 (define_insn "*mulsi3_mq_internal2"
1789 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1790 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1791 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1793 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1794 (mult:SI (match_dup 1) (match_dup 2)))
1795 (clobber (match_scratch:SI 4 "=q,q"))]
1798 {muls.|mullw.} %0,%1,%2
1800 [(set_attr "type" "imul_compare")
1801 (set_attr "length" "4,8")])
1804 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1805 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1806 (match_operand:SI 2 "gpc_reg_operand" ""))
1808 (set (match_operand:SI 0 "gpc_reg_operand" "")
1809 (mult:SI (match_dup 1) (match_dup 2)))
1810 (clobber (match_scratch:SI 4 ""))]
1811 "TARGET_POWER && reload_completed"
1812 [(parallel [(set (match_dup 0)
1813 (mult:SI (match_dup 1) (match_dup 2)))
1814 (clobber (match_dup 4))])
1816 (compare:CC (match_dup 0)
1820 (define_insn "*mulsi3_no_mq_internal2"
1821 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1822 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1823 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1825 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1826 (mult:SI (match_dup 1) (match_dup 2)))]
1829 {muls.|mullw.} %0,%1,%2
1831 [(set_attr "type" "imul_compare")
1832 (set_attr "length" "4,8")])
1835 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1836 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1837 (match_operand:SI 2 "gpc_reg_operand" ""))
1839 (set (match_operand:SI 0 "gpc_reg_operand" "")
1840 (mult:SI (match_dup 1) (match_dup 2)))]
1841 "! TARGET_POWER && reload_completed"
1843 (mult:SI (match_dup 1) (match_dup 2)))
1845 (compare:CC (match_dup 0)
1849 ;; Operand 1 is divided by operand 2; quotient goes to operand
1850 ;; 0 and remainder to operand 3.
1851 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1853 (define_expand "divmodsi4"
1854 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1855 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1856 (match_operand:SI 2 "gpc_reg_operand" "")))
1857 (set (match_operand:SI 3 "register_operand" "")
1858 (mod:SI (match_dup 1) (match_dup 2)))])]
1859 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1862 if (! TARGET_POWER && ! TARGET_POWERPC)
1864 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1865 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1866 emit_insn (gen_divss_call ());
1867 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1868 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1873 (define_insn "*divmodsi4_internal"
1874 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1875 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1876 (match_operand:SI 2 "gpc_reg_operand" "r")))
1877 (set (match_operand:SI 3 "register_operand" "=q")
1878 (mod:SI (match_dup 1) (match_dup 2)))]
1881 [(set_attr "type" "idiv")])
1883 (define_expand "udivsi3"
1884 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1885 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1886 (match_operand:SI 2 "gpc_reg_operand" "")))]
1887 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1890 if (! TARGET_POWER && ! TARGET_POWERPC)
1892 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1893 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1894 emit_insn (gen_quous_call ());
1895 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1898 else if (TARGET_POWER)
1900 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1905 (define_insn "udivsi3_mq"
1906 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1907 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1908 (match_operand:SI 2 "gpc_reg_operand" "r")))
1909 (clobber (match_scratch:SI 3 "=q"))]
1910 "TARGET_POWERPC && TARGET_POWER"
1912 [(set_attr "type" "idiv")])
1914 (define_insn "*udivsi3_no_mq"
1915 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1916 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1917 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1918 "TARGET_POWERPC && ! TARGET_POWER"
1920 [(set_attr "type" "idiv")])
1922 ;; For powers of two we can do srai/aze for divide and then adjust for
1923 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1924 ;; used; for PowerPC, force operands into register and do a normal divide;
1925 ;; for AIX common-mode, use quoss call on register operands.
1926 (define_expand "divsi3"
1927 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1928 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1929 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1933 if (GET_CODE (operands[2]) == CONST_INT
1934 && INTVAL (operands[2]) > 0
1935 && exact_log2 (INTVAL (operands[2])) >= 0)
1937 else if (TARGET_POWERPC)
1939 operands[2] = force_reg (SImode, operands[2]);
1942 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1946 else if (TARGET_POWER)
1950 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1951 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1952 emit_insn (gen_quoss_call ());
1953 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1958 (define_insn "divsi3_mq"
1959 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1960 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1961 (match_operand:SI 2 "gpc_reg_operand" "r")))
1962 (clobber (match_scratch:SI 3 "=q"))]
1963 "TARGET_POWERPC && TARGET_POWER"
1965 [(set_attr "type" "idiv")])
1967 (define_insn "*divsi3_no_mq"
1968 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1969 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1970 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1971 "TARGET_POWERPC && ! TARGET_POWER"
1973 [(set_attr "type" "idiv")])
1975 (define_expand "modsi3"
1976 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1977 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1978 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1986 if (GET_CODE (operands[2]) != CONST_INT
1987 || INTVAL (operands[2]) <= 0
1988 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
1991 temp1 = gen_reg_rtx (SImode);
1992 temp2 = gen_reg_rtx (SImode);
1994 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1995 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1996 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
2001 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2002 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2003 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
2005 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
2006 [(set_attr "type" "two")
2007 (set_attr "length" "8")])
2010 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2011 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2012 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2014 (clobber (match_scratch:SI 3 "=r,r"))]
2017 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
2019 [(set_attr "type" "compare")
2020 (set_attr "length" "8,12")])
2023 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2024 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2025 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2027 (clobber (match_scratch:SI 3 ""))]
2030 (div:SI (match_dup 1) (match_dup 2)))
2032 (compare:CC (match_dup 3)
2037 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2038 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2039 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2041 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2042 (div:SI (match_dup 1) (match_dup 2)))]
2045 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2047 [(set_attr "type" "compare")
2048 (set_attr "length" "8,12")])
2051 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2052 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2053 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2055 (set (match_operand:SI 0 "gpc_reg_operand" "")
2056 (div:SI (match_dup 1) (match_dup 2)))]
2059 (div:SI (match_dup 1) (match_dup 2)))
2061 (compare:CC (match_dup 0)
2066 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2069 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2071 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2072 (match_operand:SI 3 "gpc_reg_operand" "r")))
2073 (set (match_operand:SI 2 "register_operand" "=*q")
2076 (zero_extend:DI (match_dup 1)) (const_int 32))
2077 (zero_extend:DI (match_dup 4)))
2081 [(set_attr "type" "idiv")])
2083 ;; To do unsigned divide we handle the cases of the divisor looking like a
2084 ;; negative number. If it is a constant that is less than 2**31, we don't
2085 ;; have to worry about the branches. So make a few subroutines here.
2087 ;; First comes the normal case.
2088 (define_expand "udivmodsi4_normal"
2089 [(set (match_dup 4) (const_int 0))
2090 (parallel [(set (match_operand:SI 0 "" "")
2091 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2093 (zero_extend:DI (match_operand:SI 1 "" "")))
2094 (match_operand:SI 2 "" "")))
2095 (set (match_operand:SI 3 "" "")
2096 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2098 (zero_extend:DI (match_dup 1)))
2102 { operands[4] = gen_reg_rtx (SImode); }")
2104 ;; This handles the branches.
2105 (define_expand "udivmodsi4_tests"
2106 [(set (match_operand:SI 0 "" "") (const_int 0))
2107 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2108 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2109 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2110 (label_ref (match_operand:SI 4 "" "")) (pc)))
2111 (set (match_dup 0) (const_int 1))
2112 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2113 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2114 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2115 (label_ref (match_dup 4)) (pc)))]
2118 { operands[5] = gen_reg_rtx (CCUNSmode);
2119 operands[6] = gen_reg_rtx (CCmode);
2122 (define_expand "udivmodsi4"
2123 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2124 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2125 (match_operand:SI 2 "reg_or_cint_operand" "")))
2126 (set (match_operand:SI 3 "gpc_reg_operand" "")
2127 (umod:SI (match_dup 1) (match_dup 2)))])]
2135 if (! TARGET_POWERPC)
2137 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2138 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2139 emit_insn (gen_divus_call ());
2140 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2141 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2148 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2150 operands[2] = force_reg (SImode, operands[2]);
2151 label = gen_label_rtx ();
2152 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2153 operands[3], label));
2156 operands[2] = force_reg (SImode, operands[2]);
2158 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2166 ;; AIX architecture-independent common-mode multiply (DImode),
2167 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2168 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2169 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2170 ;; assumed unused if generating common-mode, so ignore.
2171 (define_insn "mulh_call"
2174 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2175 (sign_extend:DI (reg:SI 4)))
2177 (clobber (match_scratch:SI 0 "=l"))]
2178 "! TARGET_POWER && ! TARGET_POWERPC"
2180 [(set_attr "type" "imul")])
2182 (define_insn "mull_call"
2184 (mult:DI (sign_extend:DI (reg:SI 3))
2185 (sign_extend:DI (reg:SI 4))))
2186 (clobber (match_scratch:SI 0 "=l"))
2187 (clobber (reg:SI 0))]
2188 "! TARGET_POWER && ! TARGET_POWERPC"
2190 [(set_attr "type" "imul")])
2192 (define_insn "divss_call"
2194 (div:SI (reg:SI 3) (reg:SI 4)))
2196 (mod:SI (reg:SI 3) (reg:SI 4)))
2197 (clobber (match_scratch:SI 0 "=l"))
2198 (clobber (reg:SI 0))]
2199 "! TARGET_POWER && ! TARGET_POWERPC"
2201 [(set_attr "type" "idiv")])
2203 (define_insn "divus_call"
2205 (udiv:SI (reg:SI 3) (reg:SI 4)))
2207 (umod:SI (reg:SI 3) (reg:SI 4)))
2208 (clobber (match_scratch:SI 0 "=l"))
2209 (clobber (reg:SI 0))
2210 (clobber (match_scratch:CC 1 "=x"))
2211 (clobber (reg:CC 69))]
2212 "! TARGET_POWER && ! TARGET_POWERPC"
2214 [(set_attr "type" "idiv")])
2216 (define_insn "quoss_call"
2218 (div:SI (reg:SI 3) (reg:SI 4)))
2219 (clobber (match_scratch:SI 0 "=l"))]
2220 "! TARGET_POWER && ! TARGET_POWERPC"
2222 [(set_attr "type" "idiv")])
2224 (define_insn "quous_call"
2226 (udiv:SI (reg:SI 3) (reg:SI 4)))
2227 (clobber (match_scratch:SI 0 "=l"))
2228 (clobber (reg:SI 0))
2229 (clobber (match_scratch:CC 1 "=x"))
2230 (clobber (reg:CC 69))]
2231 "! TARGET_POWER && ! TARGET_POWERPC"
2233 [(set_attr "type" "idiv")])
2235 ;; Logical instructions
2236 ;; The logical instructions are mostly combined by using match_operator,
2237 ;; but the plain AND insns are somewhat different because there is no
2238 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2239 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2241 (define_insn "andsi3"
2242 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2243 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2244 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2245 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2249 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2250 {andil.|andi.} %0,%1,%b2
2251 {andiu.|andis.} %0,%1,%u2"
2252 [(set_attr "type" "*,*,compare,compare")])
2254 ;; Note to set cr's other than cr0 we do the and immediate and then
2255 ;; the test again -- this avoids a mfcr which on the higher end
2256 ;; machines causes an execution serialization
2258 (define_insn "*andsi3_internal2"
2259 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2260 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2261 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2263 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2264 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2268 {andil.|andi.} %3,%1,%b2
2269 {andiu.|andis.} %3,%1,%u2
2270 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2275 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2276 (set_attr "length" "4,4,4,4,8,8,8,8")])
2278 (define_insn "*andsi3_internal3"
2279 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2280 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2281 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2283 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2284 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2288 {andil.|andi.} %3,%1,%b2
2289 {andiu.|andis.} %3,%1,%u2
2290 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2295 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2296 (set_attr "length" "8,4,4,4,8,8,8,8")])
2299 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2300 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2301 (match_operand:SI 2 "and_operand" ""))
2303 (clobber (match_scratch:SI 3 ""))
2304 (clobber (match_scratch:CC 4 ""))]
2306 [(parallel [(set (match_dup 3)
2307 (and:SI (match_dup 1)
2309 (clobber (match_dup 4))])
2311 (compare:CC (match_dup 3)
2315 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2316 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2319 [(set (match_operand:CC 0 "cc_reg_operand" "")
2320 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2321 (match_operand:SI 2 "gpc_reg_operand" ""))
2323 (clobber (match_scratch:SI 3 ""))
2324 (clobber (match_scratch:CC 4 ""))]
2325 "TARGET_POWERPC64 && reload_completed"
2326 [(parallel [(set (match_dup 3)
2327 (and:SI (match_dup 1)
2329 (clobber (match_dup 4))])
2331 (compare:CC (match_dup 3)
2335 (define_insn "*andsi3_internal4"
2336 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2337 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2338 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2340 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2341 (and:SI (match_dup 1)
2343 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2347 {andil.|andi.} %0,%1,%b2
2348 {andiu.|andis.} %0,%1,%u2
2349 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2354 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2355 (set_attr "length" "4,4,4,4,8,8,8,8")])
2357 (define_insn "*andsi3_internal5"
2358 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2359 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2360 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2362 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2363 (and:SI (match_dup 1)
2365 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2369 {andil.|andi.} %0,%1,%b2
2370 {andiu.|andis.} %0,%1,%u2
2371 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2376 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2377 (set_attr "length" "8,4,4,4,8,8,8,8")])
2380 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2381 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2382 (match_operand:SI 2 "and_operand" ""))
2384 (set (match_operand:SI 0 "gpc_reg_operand" "")
2385 (and:SI (match_dup 1)
2387 (clobber (match_scratch:CC 4 ""))]
2389 [(parallel [(set (match_dup 0)
2390 (and:SI (match_dup 1)
2392 (clobber (match_dup 4))])
2394 (compare:CC (match_dup 0)
2399 [(set (match_operand:CC 3 "cc_reg_operand" "")
2400 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2401 (match_operand:SI 2 "gpc_reg_operand" ""))
2403 (set (match_operand:SI 0 "gpc_reg_operand" "")
2404 (and:SI (match_dup 1)
2406 (clobber (match_scratch:CC 4 ""))]
2407 "TARGET_POWERPC64 && reload_completed"
2408 [(parallel [(set (match_dup 0)
2409 (and:SI (match_dup 1)
2411 (clobber (match_dup 4))])
2413 (compare:CC (match_dup 0)
2417 ;; Handle the PowerPC64 rlwinm corner case
2419 (define_insn_and_split "*andsi3_internal6"
2420 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2421 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2422 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2427 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2430 (rotate:SI (match_dup 0) (match_dup 5)))]
2433 int mb = extract_MB (operands[2]);
2434 int me = extract_ME (operands[2]);
2435 operands[3] = GEN_INT (me + 1);
2436 operands[5] = GEN_INT (32 - (me + 1));
2437 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2439 [(set_attr "length" "8")])
2441 (define_expand "iorsi3"
2442 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2443 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2444 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2448 if (GET_CODE (operands[2]) == CONST_INT
2449 && ! logical_operand (operands[2], SImode))
2451 HOST_WIDE_INT value = INTVAL (operands[2]);
2452 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2453 ? operands[0] : gen_reg_rtx (SImode));
2455 emit_insn (gen_iorsi3 (tmp, operands[1],
2456 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2457 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2462 (define_expand "xorsi3"
2463 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2464 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2465 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2469 if (GET_CODE (operands[2]) == CONST_INT
2470 && ! logical_operand (operands[2], SImode))
2472 HOST_WIDE_INT value = INTVAL (operands[2]);
2473 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2474 ? operands[0] : gen_reg_rtx (SImode));
2476 emit_insn (gen_xorsi3 (tmp, operands[1],
2477 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2478 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2483 (define_insn "*boolsi3_internal1"
2484 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2485 (match_operator:SI 3 "boolean_or_operator"
2486 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2487 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2491 {%q3il|%q3i} %0,%1,%b2
2492 {%q3iu|%q3is} %0,%1,%u2")
2494 (define_insn "*boolsi3_internal2"
2495 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2496 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2497 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2498 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2500 (clobber (match_scratch:SI 3 "=r,r"))]
2505 [(set_attr "type" "compare")
2506 (set_attr "length" "4,8")])
2509 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2510 (compare:CC (match_operator:SI 4 "boolean_operator"
2511 [(match_operand:SI 1 "gpc_reg_operand" "")
2512 (match_operand:SI 2 "gpc_reg_operand" "")])
2514 (clobber (match_scratch:SI 3 ""))]
2515 "TARGET_32BIT && reload_completed"
2516 [(set (match_dup 3) (match_dup 4))
2518 (compare:CC (match_dup 3)
2522 (define_insn "*boolsi3_internal3"
2523 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2524 (compare:CC (match_operator:SI 4 "boolean_operator"
2525 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2526 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2528 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2534 [(set_attr "type" "compare")
2535 (set_attr "length" "4,8")])
2538 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2539 (compare:CC (match_operator:SI 4 "boolean_operator"
2540 [(match_operand:SI 1 "gpc_reg_operand" "")
2541 (match_operand:SI 2 "gpc_reg_operand" "")])
2543 (set (match_operand:SI 0 "gpc_reg_operand" "")
2545 "TARGET_32BIT && reload_completed"
2546 [(set (match_dup 0) (match_dup 4))
2548 (compare:CC (match_dup 0)
2552 ;; Split a logical operation that we can't do in one insn into two insns,
2553 ;; each of which does one 16-bit part. This is used by combine.
2556 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2557 (match_operator:SI 3 "boolean_or_operator"
2558 [(match_operand:SI 1 "gpc_reg_operand" "")
2559 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2561 [(set (match_dup 0) (match_dup 4))
2562 (set (match_dup 0) (match_dup 5))]
2566 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2567 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2569 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2570 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2574 (define_insn "*boolcsi3_internal1"
2575 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2576 (match_operator:SI 3 "boolean_operator"
2577 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2578 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2582 (define_insn "*boolcsi3_internal2"
2583 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2584 (compare:CC (match_operator:SI 4 "boolean_operator"
2585 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2586 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2588 (clobber (match_scratch:SI 3 "=r,r"))]
2593 [(set_attr "type" "compare")
2594 (set_attr "length" "4,8")])
2597 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2598 (compare:CC (match_operator:SI 4 "boolean_operator"
2599 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2600 (match_operand:SI 2 "gpc_reg_operand" "")])
2602 (clobber (match_scratch:SI 3 ""))]
2603 "TARGET_32BIT && reload_completed"
2604 [(set (match_dup 3) (match_dup 4))
2606 (compare:CC (match_dup 3)
2610 (define_insn "*boolcsi3_internal3"
2611 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2612 (compare:CC (match_operator:SI 4 "boolean_operator"
2613 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2614 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2616 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2622 [(set_attr "type" "compare")
2623 (set_attr "length" "4,8")])
2626 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2627 (compare:CC (match_operator:SI 4 "boolean_operator"
2628 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2629 (match_operand:SI 2 "gpc_reg_operand" "")])
2631 (set (match_operand:SI 0 "gpc_reg_operand" "")
2633 "TARGET_32BIT && reload_completed"
2634 [(set (match_dup 0) (match_dup 4))
2636 (compare:CC (match_dup 0)
2640 (define_insn "*boolccsi3_internal1"
2641 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2642 (match_operator:SI 3 "boolean_operator"
2643 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2644 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2648 (define_insn "*boolccsi3_internal2"
2649 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2650 (compare:CC (match_operator:SI 4 "boolean_operator"
2651 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2652 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2654 (clobber (match_scratch:SI 3 "=r,r"))]
2659 [(set_attr "type" "compare")
2660 (set_attr "length" "4,8")])
2663 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2664 (compare:CC (match_operator:SI 4 "boolean_operator"
2665 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2666 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2668 (clobber (match_scratch:SI 3 ""))]
2669 "TARGET_32BIT && reload_completed"
2670 [(set (match_dup 3) (match_dup 4))
2672 (compare:CC (match_dup 3)
2676 (define_insn "*boolccsi3_internal3"
2677 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2678 (compare:CC (match_operator:SI 4 "boolean_operator"
2679 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2680 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2682 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2688 [(set_attr "type" "compare")
2689 (set_attr "length" "4,8")])
2692 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2693 (compare:CC (match_operator:SI 4 "boolean_operator"
2694 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2695 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2697 (set (match_operand:SI 0 "gpc_reg_operand" "")
2699 "TARGET_32BIT && reload_completed"
2700 [(set (match_dup 0) (match_dup 4))
2702 (compare:CC (match_dup 0)
2706 ;; maskir insn. We need four forms because things might be in arbitrary
2707 ;; orders. Don't define forms that only set CR fields because these
2708 ;; would modify an input register.
2710 (define_insn "*maskir_internal1"
2711 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2712 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2713 (match_operand:SI 1 "gpc_reg_operand" "0"))
2714 (and:SI (match_dup 2)
2715 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2719 (define_insn "*maskir_internal2"
2720 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2721 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2722 (match_operand:SI 1 "gpc_reg_operand" "0"))
2723 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2728 (define_insn "*maskir_internal3"
2729 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2730 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2731 (match_operand:SI 3 "gpc_reg_operand" "r"))
2732 (and:SI (not:SI (match_dup 2))
2733 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2737 (define_insn "*maskir_internal4"
2738 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2739 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2740 (match_operand:SI 2 "gpc_reg_operand" "r"))
2741 (and:SI (not:SI (match_dup 2))
2742 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2746 (define_insn "*maskir_internal5"
2747 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2749 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2750 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2751 (and:SI (match_dup 2)
2752 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2754 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2755 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2756 (and:SI (match_dup 2) (match_dup 3))))]
2761 [(set_attr "type" "compare")
2762 (set_attr "length" "4,8")])
2765 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2767 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2768 (match_operand:SI 1 "gpc_reg_operand" ""))
2769 (and:SI (match_dup 2)
2770 (match_operand:SI 3 "gpc_reg_operand" "")))
2772 (set (match_operand:SI 0 "gpc_reg_operand" "")
2773 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2774 (and:SI (match_dup 2) (match_dup 3))))]
2775 "TARGET_POWER && reload_completed"
2777 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2778 (and:SI (match_dup 2) (match_dup 3))))
2780 (compare:CC (match_dup 0)
2784 (define_insn "*maskir_internal6"
2785 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2787 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2788 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2789 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2792 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2793 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2794 (and:SI (match_dup 3) (match_dup 2))))]
2799 [(set_attr "type" "compare")
2800 (set_attr "length" "4,8")])
2803 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2805 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2806 (match_operand:SI 1 "gpc_reg_operand" ""))
2807 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2810 (set (match_operand:SI 0 "gpc_reg_operand" "")
2811 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2812 (and:SI (match_dup 3) (match_dup 2))))]
2813 "TARGET_POWER && reload_completed"
2815 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2816 (and:SI (match_dup 3) (match_dup 2))))
2818 (compare:CC (match_dup 0)
2822 (define_insn "*maskir_internal7"
2823 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2825 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2826 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2827 (and:SI (not:SI (match_dup 2))
2828 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2830 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2831 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2832 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2837 [(set_attr "type" "compare")
2838 (set_attr "length" "4,8")])
2841 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2843 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2844 (match_operand:SI 3 "gpc_reg_operand" ""))
2845 (and:SI (not:SI (match_dup 2))
2846 (match_operand:SI 1 "gpc_reg_operand" "")))
2848 (set (match_operand:SI 0 "gpc_reg_operand" "")
2849 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2850 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2851 "TARGET_POWER && reload_completed"
2853 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2854 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2856 (compare:CC (match_dup 0)
2860 (define_insn "*maskir_internal8"
2861 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2863 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2864 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2865 (and:SI (not:SI (match_dup 2))
2866 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2868 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2869 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2870 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2875 [(set_attr "type" "compare")
2876 (set_attr "length" "4,8")])
2879 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2881 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2882 (match_operand:SI 2 "gpc_reg_operand" ""))
2883 (and:SI (not:SI (match_dup 2))
2884 (match_operand:SI 1 "gpc_reg_operand" "")))
2886 (set (match_operand:SI 0 "gpc_reg_operand" "")
2887 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2888 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2889 "TARGET_POWER && reload_completed"
2891 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2892 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2894 (compare:CC (match_dup 0)
2898 ;; Rotate and shift insns, in all their variants. These support shifts,
2899 ;; field inserts and extracts, and various combinations thereof.
2900 (define_expand "insv"
2901 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2902 (match_operand:SI 1 "const_int_operand" "")
2903 (match_operand:SI 2 "const_int_operand" ""))
2904 (match_operand 3 "gpc_reg_operand" ""))]
2908 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2909 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2910 compiler if the address of the structure is taken later. */
2911 if (GET_CODE (operands[0]) == SUBREG
2912 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2915 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2916 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2918 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2922 (define_insn "insvsi"
2923 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2924 (match_operand:SI 1 "const_int_operand" "i")
2925 (match_operand:SI 2 "const_int_operand" "i"))
2926 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2930 int start = INTVAL (operands[2]) & 31;
2931 int size = INTVAL (operands[1]) & 31;
2933 operands[4] = GEN_INT (32 - start - size);
2934 operands[1] = GEN_INT (start + size - 1);
2935 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2937 [(set_attr "type" "insert_word")])
2939 (define_insn "*insvsi_internal1"
2940 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2941 (match_operand:SI 1 "const_int_operand" "i")
2942 (match_operand:SI 2 "const_int_operand" "i"))
2943 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2944 (match_operand:SI 4 "const_int_operand" "i")))]
2945 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2948 int shift = INTVAL (operands[4]) & 31;
2949 int start = INTVAL (operands[2]) & 31;
2950 int size = INTVAL (operands[1]) & 31;
2952 operands[4] = GEN_INT (shift - start - size);
2953 operands[1] = GEN_INT (start + size - 1);
2954 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2956 [(set_attr "type" "insert_word")])
2958 (define_insn "*insvsi_internal2"
2959 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2960 (match_operand:SI 1 "const_int_operand" "i")
2961 (match_operand:SI 2 "const_int_operand" "i"))
2962 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2963 (match_operand:SI 4 "const_int_operand" "i")))]
2964 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2967 int shift = INTVAL (operands[4]) & 31;
2968 int start = INTVAL (operands[2]) & 31;
2969 int size = INTVAL (operands[1]) & 31;
2971 operands[4] = GEN_INT (32 - shift - start - size);
2972 operands[1] = GEN_INT (start + size - 1);
2973 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2975 [(set_attr "type" "insert_word")])
2977 (define_insn "*insvsi_internal3"
2978 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2979 (match_operand:SI 1 "const_int_operand" "i")
2980 (match_operand:SI 2 "const_int_operand" "i"))
2981 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2982 (match_operand:SI 4 "const_int_operand" "i")))]
2983 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2986 int shift = INTVAL (operands[4]) & 31;
2987 int start = INTVAL (operands[2]) & 31;
2988 int size = INTVAL (operands[1]) & 31;
2990 operands[4] = GEN_INT (32 - shift - start - size);
2991 operands[1] = GEN_INT (start + size - 1);
2992 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2994 [(set_attr "type" "insert_word")])
2996 (define_insn "*insvsi_internal4"
2997 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2998 (match_operand:SI 1 "const_int_operand" "i")
2999 (match_operand:SI 2 "const_int_operand" "i"))
3000 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3001 (match_operand:SI 4 "const_int_operand" "i")
3002 (match_operand:SI 5 "const_int_operand" "i")))]
3003 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3006 int extract_start = INTVAL (operands[5]) & 31;
3007 int extract_size = INTVAL (operands[4]) & 31;
3008 int insert_start = INTVAL (operands[2]) & 31;
3009 int insert_size = INTVAL (operands[1]) & 31;
3011 /* Align extract field with insert field */
3012 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3013 operands[1] = GEN_INT (insert_start + insert_size - 1);
3014 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3016 [(set_attr "type" "insert_word")])
3018 ;; combine patterns for rlwimi
3019 (define_insn "*insvsi_internal5"
3020 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3021 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3022 (match_operand:SI 1 "mask_operand" "i"))
3023 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3024 (match_operand:SI 2 "const_int_operand" "i"))
3025 (match_operand:SI 5 "mask_operand" "i"))))]
3026 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3029 int me = extract_ME(operands[5]);
3030 int mb = extract_MB(operands[5]);
3031 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3032 operands[2] = GEN_INT(mb);
3033 operands[1] = GEN_INT(me);
3034 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3036 [(set_attr "type" "insert_word")])
3038 (define_insn "*insvsi_internal6"
3039 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3040 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3041 (match_operand:SI 2 "const_int_operand" "i"))
3042 (match_operand:SI 5 "mask_operand" "i"))
3043 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3044 (match_operand:SI 1 "mask_operand" "i"))))]
3045 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3048 int me = extract_ME(operands[5]);
3049 int mb = extract_MB(operands[5]);
3050 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3051 operands[2] = GEN_INT(mb);
3052 operands[1] = GEN_INT(me);
3053 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3055 [(set_attr "type" "insert_word")])
3057 (define_insn "insvdi"
3058 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3059 (match_operand:SI 1 "const_int_operand" "i")
3060 (match_operand:SI 2 "const_int_operand" "i"))
3061 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3065 int start = INTVAL (operands[2]) & 63;
3066 int size = INTVAL (operands[1]) & 63;
3068 operands[1] = GEN_INT (64 - start - size);
3069 return \"rldimi %0,%3,%H1,%H2\";
3072 (define_insn "*insvdi_internal2"
3073 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3074 (match_operand:SI 1 "const_int_operand" "i")
3075 (match_operand:SI 2 "const_int_operand" "i"))
3076 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3077 (match_operand:SI 4 "const_int_operand" "i")))]
3079 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3082 int shift = INTVAL (operands[4]) & 63;
3083 int start = (INTVAL (operands[2]) & 63) - 32;
3084 int size = INTVAL (operands[1]) & 63;
3086 operands[4] = GEN_INT (64 - shift - start - size);
3087 operands[2] = GEN_INT (start);
3088 operands[1] = GEN_INT (start + size - 1);
3089 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3092 (define_insn "*insvdi_internal3"
3093 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3094 (match_operand:SI 1 "const_int_operand" "i")
3095 (match_operand:SI 2 "const_int_operand" "i"))
3096 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3097 (match_operand:SI 4 "const_int_operand" "i")))]
3099 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3102 int shift = INTVAL (operands[4]) & 63;
3103 int start = (INTVAL (operands[2]) & 63) - 32;
3104 int size = INTVAL (operands[1]) & 63;
3106 operands[4] = GEN_INT (64 - shift - start - size);
3107 operands[2] = GEN_INT (start);
3108 operands[1] = GEN_INT (start + size - 1);
3109 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3112 (define_expand "extzv"
3113 [(set (match_operand 0 "gpc_reg_operand" "")
3114 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3115 (match_operand:SI 2 "const_int_operand" "")
3116 (match_operand:SI 3 "const_int_operand" "")))]
3120 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3121 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3122 compiler if the address of the structure is taken later. */
3123 if (GET_CODE (operands[0]) == SUBREG
3124 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3127 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3128 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3130 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3134 (define_insn "extzvsi"
3135 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3136 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3137 (match_operand:SI 2 "const_int_operand" "i")
3138 (match_operand:SI 3 "const_int_operand" "i")))]
3142 int start = INTVAL (operands[3]) & 31;
3143 int size = INTVAL (operands[2]) & 31;
3145 if (start + size >= 32)
3146 operands[3] = const0_rtx;
3148 operands[3] = GEN_INT (start + size);
3149 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3152 (define_insn "*extzvsi_internal1"
3153 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3154 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3155 (match_operand:SI 2 "const_int_operand" "i,i")
3156 (match_operand:SI 3 "const_int_operand" "i,i"))
3158 (clobber (match_scratch:SI 4 "=r,r"))]
3162 int start = INTVAL (operands[3]) & 31;
3163 int size = INTVAL (operands[2]) & 31;
3165 /* Force split for non-cc0 compare. */
3166 if (which_alternative == 1)
3169 /* If the bit-field being tested fits in the upper or lower half of a
3170 word, it is possible to use andiu. or andil. to test it. This is
3171 useful because the condition register set-use delay is smaller for
3172 andi[ul]. than for rlinm. This doesn't work when the starting bit
3173 position is 0 because the LT and GT bits may be set wrong. */
3175 if ((start > 0 && start + size <= 16) || start >= 16)
3177 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3178 - (1 << (16 - (start & 15) - size))));
3180 return \"{andiu.|andis.} %4,%1,%3\";
3182 return \"{andil.|andi.} %4,%1,%3\";
3185 if (start + size >= 32)
3186 operands[3] = const0_rtx;
3188 operands[3] = GEN_INT (start + size);
3189 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3191 [(set_attr "type" "compare")
3192 (set_attr "length" "4,8")])
3195 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3196 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3197 (match_operand:SI 2 "const_int_operand" "")
3198 (match_operand:SI 3 "const_int_operand" ""))
3200 (clobber (match_scratch:SI 4 ""))]
3203 (zero_extract:SI (match_dup 1) (match_dup 2)
3206 (compare:CC (match_dup 4)
3210 (define_insn "*extzvsi_internal2"
3211 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3212 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3213 (match_operand:SI 2 "const_int_operand" "i,i")
3214 (match_operand:SI 3 "const_int_operand" "i,i"))
3216 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3217 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3221 int start = INTVAL (operands[3]) & 31;
3222 int size = INTVAL (operands[2]) & 31;
3224 /* Force split for non-cc0 compare. */
3225 if (which_alternative == 1)
3228 /* Since we are using the output value, we can't ignore any need for
3229 a shift. The bit-field must end at the LSB. */
3230 if (start >= 16 && start + size == 32)
3232 operands[3] = GEN_INT ((1 << size) - 1);
3233 return \"{andil.|andi.} %0,%1,%3\";
3236 if (start + size >= 32)
3237 operands[3] = const0_rtx;
3239 operands[3] = GEN_INT (start + size);
3240 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3242 [(set_attr "type" "compare")
3243 (set_attr "length" "4,8")])
3246 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3247 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3248 (match_operand:SI 2 "const_int_operand" "")
3249 (match_operand:SI 3 "const_int_operand" ""))
3251 (set (match_operand:SI 0 "gpc_reg_operand" "")
3252 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3255 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3257 (compare:CC (match_dup 0)
3261 (define_insn "extzvdi"
3262 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3263 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3264 (match_operand:SI 2 "const_int_operand" "i")
3265 (match_operand:SI 3 "const_int_operand" "i")))]
3269 int start = INTVAL (operands[3]) & 63;
3270 int size = INTVAL (operands[2]) & 63;
3272 if (start + size >= 64)
3273 operands[3] = const0_rtx;
3275 operands[3] = GEN_INT (start + size);
3276 operands[2] = GEN_INT (64 - size);
3277 return \"rldicl %0,%1,%3,%2\";
3280 (define_insn "*extzvdi_internal1"
3281 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3282 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3283 (match_operand:SI 2 "const_int_operand" "i")
3284 (match_operand:SI 3 "const_int_operand" "i"))
3286 (clobber (match_scratch:DI 4 "=r"))]
3290 int start = INTVAL (operands[3]) & 63;
3291 int size = INTVAL (operands[2]) & 63;
3293 if (start + size >= 64)
3294 operands[3] = const0_rtx;
3296 operands[3] = GEN_INT (start + size);
3297 operands[2] = GEN_INT (64 - size);
3298 return \"rldicl. %4,%1,%3,%2\";
3300 [(set_attr "type" "compare")])
3302 (define_insn "*extzvdi_internal2"
3303 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3304 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3305 (match_operand:SI 2 "const_int_operand" "i")
3306 (match_operand:SI 3 "const_int_operand" "i"))
3308 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3309 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3313 int start = INTVAL (operands[3]) & 63;
3314 int size = INTVAL (operands[2]) & 63;
3316 if (start + size >= 64)
3317 operands[3] = const0_rtx;
3319 operands[3] = GEN_INT (start + size);
3320 operands[2] = GEN_INT (64 - size);
3321 return \"rldicl. %0,%1,%3,%2\";
3323 [(set_attr "type" "compare")])
3325 (define_insn "rotlsi3"
3326 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3327 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3328 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3330 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3332 (define_insn "*rotlsi3_internal2"
3333 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3334 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3335 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3337 (clobber (match_scratch:SI 3 "=r,r"))]
3340 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3342 [(set_attr "type" "delayed_compare")
3343 (set_attr "length" "4,8")])
3346 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3347 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3348 (match_operand:SI 2 "reg_or_cint_operand" ""))
3350 (clobber (match_scratch:SI 3 ""))]
3353 (rotate:SI (match_dup 1) (match_dup 2)))
3355 (compare:CC (match_dup 3)
3359 (define_insn "*rotlsi3_internal3"
3360 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3361 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3362 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3364 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3365 (rotate:SI (match_dup 1) (match_dup 2)))]
3368 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3370 [(set_attr "type" "delayed_compare")
3371 (set_attr "length" "4,8")])
3374 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3375 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3376 (match_operand:SI 2 "reg_or_cint_operand" ""))
3378 (set (match_operand:SI 0 "gpc_reg_operand" "")
3379 (rotate:SI (match_dup 1) (match_dup 2)))]
3382 (rotate:SI (match_dup 1) (match_dup 2)))
3384 (compare:CC (match_dup 0)
3388 (define_insn "*rotlsi3_internal4"
3389 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3390 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3391 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3392 (match_operand:SI 3 "mask_operand" "n")))]
3394 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3396 (define_insn "*rotlsi3_internal5"
3397 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3399 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3400 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3401 (match_operand:SI 3 "mask_operand" "n,n"))
3403 (clobber (match_scratch:SI 4 "=r,r"))]
3406 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3408 [(set_attr "type" "delayed_compare")
3409 (set_attr "length" "4,8")])
3412 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3414 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3415 (match_operand:SI 2 "reg_or_cint_operand" ""))
3416 (match_operand:SI 3 "mask_operand" ""))
3418 (clobber (match_scratch:SI 4 ""))]
3421 (and:SI (rotate:SI (match_dup 1)
3425 (compare:CC (match_dup 4)
3429 (define_insn "*rotlsi3_internal6"
3430 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3432 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3433 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3434 (match_operand:SI 3 "mask_operand" "n,n"))
3436 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3437 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3440 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3442 [(set_attr "type" "delayed_compare")
3443 (set_attr "length" "4,8")])
3446 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3448 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3449 (match_operand:SI 2 "reg_or_cint_operand" ""))
3450 (match_operand:SI 3 "mask_operand" ""))
3452 (set (match_operand:SI 0 "gpc_reg_operand" "")
3453 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3456 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3458 (compare:CC (match_dup 0)
3462 (define_insn "*rotlsi3_internal7"
3463 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3466 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3467 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3469 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3471 (define_insn "*rotlsi3_internal8"
3472 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3473 (compare:CC (zero_extend:SI
3475 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3476 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3478 (clobber (match_scratch:SI 3 "=r,r"))]
3481 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3483 [(set_attr "type" "delayed_compare")
3484 (set_attr "length" "4,8")])
3487 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3488 (compare:CC (zero_extend:SI
3490 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3491 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3493 (clobber (match_scratch:SI 3 ""))]
3496 (zero_extend:SI (subreg:QI
3497 (rotate:SI (match_dup 1)
3500 (compare:CC (match_dup 3)
3504 (define_insn "*rotlsi3_internal9"
3505 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3506 (compare:CC (zero_extend:SI
3508 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3509 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3511 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3512 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3515 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3517 [(set_attr "type" "delayed_compare")
3518 (set_attr "length" "4,8")])
3521 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3522 (compare:CC (zero_extend:SI
3524 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3525 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3527 (set (match_operand:SI 0 "gpc_reg_operand" "")
3528 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3531 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3533 (compare:CC (match_dup 0)
3537 (define_insn "*rotlsi3_internal10"
3538 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3541 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3542 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3544 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3546 (define_insn "*rotlsi3_internal11"
3547 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3548 (compare:CC (zero_extend:SI
3550 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3551 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3553 (clobber (match_scratch:SI 3 "=r,r"))]
3556 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3558 [(set_attr "type" "delayed_compare")
3559 (set_attr "length" "4,8")])
3562 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3563 (compare:CC (zero_extend:SI
3565 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3566 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3568 (clobber (match_scratch:SI 3 ""))]
3571 (zero_extend:SI (subreg:HI
3572 (rotate:SI (match_dup 1)
3575 (compare:CC (match_dup 3)
3579 (define_insn "*rotlsi3_internal12"
3580 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3581 (compare:CC (zero_extend:SI
3583 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3584 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3586 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3587 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3590 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3592 [(set_attr "type" "delayed_compare")
3593 (set_attr "length" "4,8")])
3596 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3597 (compare:CC (zero_extend:SI
3599 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3600 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3602 (set (match_operand:SI 0 "gpc_reg_operand" "")
3603 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3606 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3608 (compare:CC (match_dup 0)
3612 ;; Note that we use "sle." instead of "sl." so that we can set
3613 ;; SHIFT_COUNT_TRUNCATED.
3615 (define_expand "ashlsi3"
3616 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3617 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3618 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3623 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3625 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3629 (define_insn "ashlsi3_power"
3630 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3631 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3632 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3633 (clobber (match_scratch:SI 3 "=q,X"))]
3637 {sli|slwi} %0,%1,%h2")
3639 (define_insn "ashlsi3_no_power"
3640 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3641 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3642 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3644 "{sl|slw}%I2 %0,%1,%h2")
3647 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3648 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3649 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3651 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3652 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3656 {sli.|slwi.} %3,%1,%h2
3659 [(set_attr "type" "delayed_compare")
3660 (set_attr "length" "4,4,8,8")])
3663 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3664 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3665 (match_operand:SI 2 "reg_or_cint_operand" ""))
3667 (clobber (match_scratch:SI 3 ""))
3668 (clobber (match_scratch:SI 4 ""))]
3669 "TARGET_POWER && reload_completed"
3670 [(parallel [(set (match_dup 3)
3671 (ashift:SI (match_dup 1) (match_dup 2)))
3672 (clobber (match_dup 4))])
3674 (compare:CC (match_dup 3)
3679 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3680 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3681 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3683 (clobber (match_scratch:SI 3 "=r,r"))]
3684 "! TARGET_POWER && TARGET_32BIT"
3686 {sl|slw}%I2. %3,%1,%h2
3688 [(set_attr "type" "delayed_compare")
3689 (set_attr "length" "4,8")])
3692 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3693 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3694 (match_operand:SI 2 "reg_or_cint_operand" ""))
3696 (clobber (match_scratch:SI 3 ""))]
3697 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3699 (ashift:SI (match_dup 1) (match_dup 2)))
3701 (compare:CC (match_dup 3)
3706 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3707 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3708 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3710 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3711 (ashift:SI (match_dup 1) (match_dup 2)))
3712 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3716 {sli.|slwi.} %0,%1,%h2
3719 [(set_attr "type" "delayed_compare")
3720 (set_attr "length" "4,4,8,8")])
3723 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3724 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3725 (match_operand:SI 2 "reg_or_cint_operand" ""))
3727 (set (match_operand:SI 0 "gpc_reg_operand" "")
3728 (ashift:SI (match_dup 1) (match_dup 2)))
3729 (clobber (match_scratch:SI 4 ""))]
3730 "TARGET_POWER && reload_completed"
3731 [(parallel [(set (match_dup 0)
3732 (ashift:SI (match_dup 1) (match_dup 2)))
3733 (clobber (match_dup 4))])
3735 (compare:CC (match_dup 0)
3740 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3741 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3742 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3744 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3745 (ashift:SI (match_dup 1) (match_dup 2)))]
3746 "! TARGET_POWER && TARGET_32BIT"
3748 {sl|slw}%I2. %0,%1,%h2
3750 [(set_attr "type" "delayed_compare")
3751 (set_attr "length" "4,8")])
3754 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3755 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3756 (match_operand:SI 2 "reg_or_cint_operand" ""))
3758 (set (match_operand:SI 0 "gpc_reg_operand" "")
3759 (ashift:SI (match_dup 1) (match_dup 2)))]
3760 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3762 (ashift:SI (match_dup 1) (match_dup 2)))
3764 (compare:CC (match_dup 0)
3768 (define_insn "rlwinm"
3769 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3770 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3771 (match_operand:SI 2 "const_int_operand" "i"))
3772 (match_operand:SI 3 "mask_operand" "n")))]
3773 "includes_lshift_p (operands[2], operands[3])"
3774 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3777 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3779 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3780 (match_operand:SI 2 "const_int_operand" "i,i"))
3781 (match_operand:SI 3 "mask_operand" "n,n"))
3783 (clobber (match_scratch:SI 4 "=r,r"))]
3784 "includes_lshift_p (operands[2], operands[3])"
3786 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3788 [(set_attr "type" "delayed_compare")
3789 (set_attr "length" "4,8")])
3792 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3794 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3795 (match_operand:SI 2 "const_int_operand" ""))
3796 (match_operand:SI 3 "mask_operand" ""))
3798 (clobber (match_scratch:SI 4 ""))]
3799 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3801 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3804 (compare:CC (match_dup 4)
3809 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3811 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3812 (match_operand:SI 2 "const_int_operand" "i,i"))
3813 (match_operand:SI 3 "mask_operand" "n,n"))
3815 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3816 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3817 "includes_lshift_p (operands[2], operands[3])"
3819 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3821 [(set_attr "type" "delayed_compare")
3822 (set_attr "length" "4,8")])
3825 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3827 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3828 (match_operand:SI 2 "const_int_operand" ""))
3829 (match_operand:SI 3 "mask_operand" ""))
3831 (set (match_operand:SI 0 "gpc_reg_operand" "")
3832 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3833 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3835 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3837 (compare:CC (match_dup 0)
3841 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3843 (define_expand "lshrsi3"
3844 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3845 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3846 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3851 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3853 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3857 (define_insn "lshrsi3_power"
3858 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3859 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3860 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3861 (clobber (match_scratch:SI 3 "=q,X,X"))]
3866 {s%A2i|s%A2wi} %0,%1,%h2")
3868 (define_insn "lshrsi3_no_power"
3869 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3870 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3871 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3875 {sr|srw}%I2 %0,%1,%h2")
3878 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3879 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3880 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3882 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3883 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3888 {s%A2i.|s%A2wi.} %3,%1,%h2
3892 [(set_attr "type" "delayed_compare")
3893 (set_attr "length" "4,4,4,8,8,8")])
3896 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3897 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3898 (match_operand:SI 2 "reg_or_cint_operand" ""))
3900 (clobber (match_scratch:SI 3 ""))
3901 (clobber (match_scratch:SI 4 ""))]
3902 "TARGET_POWER && reload_completed"
3903 [(parallel [(set (match_dup 3)
3904 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3905 (clobber (match_dup 4))])
3907 (compare:CC (match_dup 3)
3912 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3913 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3914 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3916 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3917 "! TARGET_POWER && TARGET_32BIT"
3920 {sr|srw}%I2. %3,%1,%h2
3923 [(set_attr "type" "delayed_compare")
3924 (set_attr "length" "4,4,8,8")])
3927 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3928 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3929 (match_operand:SI 2 "reg_or_cint_operand" ""))
3931 (clobber (match_scratch:SI 3 ""))]
3932 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3934 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3936 (compare:CC (match_dup 3)
3941 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3942 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3943 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3945 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
3946 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3947 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3952 {s%A2i.|s%A2wi.} %0,%1,%h2
3956 [(set_attr "type" "delayed_compare")
3957 (set_attr "length" "4,4,4,8,8,8")])
3960 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3961 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3962 (match_operand:SI 2 "reg_or_cint_operand" ""))
3964 (set (match_operand:SI 0 "gpc_reg_operand" "")
3965 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3966 (clobber (match_scratch:SI 4 ""))]
3967 "TARGET_POWER && reload_completed"
3968 [(parallel [(set (match_dup 0)
3969 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3970 (clobber (match_dup 4))])
3972 (compare:CC (match_dup 0)
3977 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3978 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3979 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3981 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3982 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3983 "! TARGET_POWER && TARGET_32BIT"
3986 {sr|srw}%I2. %0,%1,%h2
3989 [(set_attr "type" "delayed_compare")
3990 (set_attr "length" "4,4,8,8")])
3993 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3994 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3995 (match_operand:SI 2 "reg_or_cint_operand" ""))
3997 (set (match_operand:SI 0 "gpc_reg_operand" "")
3998 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3999 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4001 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4003 (compare:CC (match_dup 0)
4008 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4009 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4010 (match_operand:SI 2 "const_int_operand" "i"))
4011 (match_operand:SI 3 "mask_operand" "n")))]
4012 "includes_rshift_p (operands[2], operands[3])"
4013 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4016 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4018 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4019 (match_operand:SI 2 "const_int_operand" "i,i"))
4020 (match_operand:SI 3 "mask_operand" "n,n"))
4022 (clobber (match_scratch:SI 4 "=r,r"))]
4023 "includes_rshift_p (operands[2], operands[3])"
4025 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4027 [(set_attr "type" "delayed_compare")
4028 (set_attr "length" "4,8")])
4031 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4033 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4034 (match_operand:SI 2 "const_int_operand" ""))
4035 (match_operand:SI 3 "mask_operand" ""))
4037 (clobber (match_scratch:SI 4 ""))]
4038 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4040 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4043 (compare:CC (match_dup 4)
4048 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4050 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4051 (match_operand:SI 2 "const_int_operand" "i,i"))
4052 (match_operand:SI 3 "mask_operand" "n,n"))
4054 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4055 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4056 "includes_rshift_p (operands[2], operands[3])"
4058 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4060 [(set_attr "type" "delayed_compare")
4061 (set_attr "length" "4,8")])
4064 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4066 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4067 (match_operand:SI 2 "const_int_operand" ""))
4068 (match_operand:SI 3 "mask_operand" ""))
4070 (set (match_operand:SI 0 "gpc_reg_operand" "")
4071 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4072 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4074 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4076 (compare:CC (match_dup 0)
4081 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4084 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4085 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4086 "includes_rshift_p (operands[2], GEN_INT (255))"
4087 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4090 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4094 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4095 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4097 (clobber (match_scratch:SI 3 "=r,r"))]
4098 "includes_rshift_p (operands[2], GEN_INT (255))"
4100 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4102 [(set_attr "type" "delayed_compare")
4103 (set_attr "length" "4,8")])
4106 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4110 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4111 (match_operand:SI 2 "const_int_operand" "")) 0))
4113 (clobber (match_scratch:SI 3 ""))]
4114 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4116 (zero_extend:SI (subreg:QI
4117 (lshiftrt:SI (match_dup 1)
4120 (compare:CC (match_dup 3)
4125 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4129 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4130 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4132 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4133 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4134 "includes_rshift_p (operands[2], GEN_INT (255))"
4136 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4138 [(set_attr "type" "delayed_compare")
4139 (set_attr "length" "4,8")])
4142 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4146 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4147 (match_operand:SI 2 "const_int_operand" "")) 0))
4149 (set (match_operand:SI 0 "gpc_reg_operand" "")
4150 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4151 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4153 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4155 (compare:CC (match_dup 0)
4160 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4163 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4164 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4165 "includes_rshift_p (operands[2], GEN_INT (65535))"
4166 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4169 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4173 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4174 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4176 (clobber (match_scratch:SI 3 "=r,r"))]
4177 "includes_rshift_p (operands[2], GEN_INT (65535))"
4179 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4181 [(set_attr "type" "delayed_compare")
4182 (set_attr "length" "4,8")])
4185 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4189 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4190 (match_operand:SI 2 "const_int_operand" "")) 0))
4192 (clobber (match_scratch:SI 3 ""))]
4193 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4195 (zero_extend:SI (subreg:HI
4196 (lshiftrt:SI (match_dup 1)
4199 (compare:CC (match_dup 3)
4204 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4208 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4209 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4211 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4212 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4213 "includes_rshift_p (operands[2], GEN_INT (65535))"
4215 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4217 [(set_attr "type" "delayed_compare")
4218 (set_attr "length" "4,8")])
4221 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4225 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4226 (match_operand:SI 2 "const_int_operand" "")) 0))
4228 (set (match_operand:SI 0 "gpc_reg_operand" "")
4229 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4230 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4232 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4234 (compare:CC (match_dup 0)
4239 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4241 (match_operand:SI 1 "gpc_reg_operand" "r"))
4242 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4248 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4250 (match_operand:SI 1 "gpc_reg_operand" "r"))
4251 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4257 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4259 (match_operand:SI 1 "gpc_reg_operand" "r"))
4260 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4266 (define_expand "ashrsi3"
4267 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4268 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4269 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4274 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4276 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4280 (define_insn "ashrsi3_power"
4281 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4282 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4283 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4284 (clobber (match_scratch:SI 3 "=q,X"))]
4288 {srai|srawi} %0,%1,%h2")
4290 (define_insn "ashrsi3_no_power"
4291 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4292 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4293 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4295 "{sra|sraw}%I2 %0,%1,%h2")
4298 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4299 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4300 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4302 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4303 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4307 {srai.|srawi.} %3,%1,%h2
4310 [(set_attr "type" "delayed_compare")
4311 (set_attr "length" "4,4,8,8")])
4314 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4315 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4316 (match_operand:SI 2 "reg_or_cint_operand" ""))
4318 (clobber (match_scratch:SI 3 ""))
4319 (clobber (match_scratch:SI 4 ""))]
4320 "TARGET_POWER && reload_completed"
4321 [(parallel [(set (match_dup 3)
4322 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4323 (clobber (match_dup 4))])
4325 (compare:CC (match_dup 3)
4330 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4331 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4332 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4334 (clobber (match_scratch:SI 3 "=r,r"))]
4337 {sra|sraw}%I2. %3,%1,%h2
4339 [(set_attr "type" "delayed_compare")
4340 (set_attr "length" "4,8")])
4343 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4344 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4345 (match_operand:SI 2 "reg_or_cint_operand" ""))
4347 (clobber (match_scratch:SI 3 ""))]
4348 "! TARGET_POWER && reload_completed"
4350 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4352 (compare:CC (match_dup 3)
4357 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4358 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4359 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4361 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4362 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4363 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4367 {srai.|srawi.} %0,%1,%h2
4370 [(set_attr "type" "delayed_compare")
4371 (set_attr "length" "4,4,8,8")])
4374 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4375 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4376 (match_operand:SI 2 "reg_or_cint_operand" ""))
4378 (set (match_operand:SI 0 "gpc_reg_operand" "")
4379 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4380 (clobber (match_scratch:SI 4 ""))]
4381 "TARGET_POWER && reload_completed"
4382 [(parallel [(set (match_dup 0)
4383 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4384 (clobber (match_dup 4))])
4386 (compare:CC (match_dup 0)
4391 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4392 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4393 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4395 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4396 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4399 {sra|sraw}%I2. %0,%1,%h2
4401 [(set_attr "type" "delayed_compare")
4402 (set_attr "length" "4,8")])
4405 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4406 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4407 (match_operand:SI 2 "reg_or_cint_operand" ""))
4409 (set (match_operand:SI 0 "gpc_reg_operand" "")
4410 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4411 "! TARGET_POWER && reload_completed"
4413 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4415 (compare:CC (match_dup 0)
4419 ;; Floating-point insns, excluding normal data motion.
4421 ;; PowerPC has a full set of single-precision floating point instructions.
4423 ;; For the POWER architecture, we pretend that we have both SFmode and
4424 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4425 ;; The only conversions we will do will be when storing to memory. In that
4426 ;; case, we will use the "frsp" instruction before storing.
4428 ;; Note that when we store into a single-precision memory location, we need to
4429 ;; use the frsp insn first. If the register being stored isn't dead, we
4430 ;; need a scratch register for the frsp. But this is difficult when the store
4431 ;; is done by reload. It is not incorrect to do the frsp on the register in
4432 ;; this case, we just lose precision that we would have otherwise gotten but
4433 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4435 (define_expand "extendsfdf2"
4436 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4437 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4438 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4441 (define_insn_and_split "*extendsfdf2_fpr"
4442 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4443 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4444 "TARGET_HARD_FLOAT && TARGET_FPRS"
4449 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4452 emit_note (NOTE_INSN_DELETED);
4455 [(set_attr "type" "fp,fp,fpload")])
4457 (define_expand "truncdfsf2"
4458 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4459 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4460 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4463 (define_insn "*truncdfsf2_fpr"
4464 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4465 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4466 "TARGET_HARD_FLOAT && TARGET_FPRS"
4468 [(set_attr "type" "fp")])
4470 (define_insn "aux_truncdfsf2"
4471 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4472 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4473 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4475 [(set_attr "type" "fp")])
4477 (define_expand "negsf2"
4478 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4479 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4483 (define_insn "*negsf2"
4484 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4485 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4486 "TARGET_HARD_FLOAT && TARGET_FPRS"
4488 [(set_attr "type" "fp")])
4490 (define_expand "abssf2"
4491 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4492 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4496 (define_insn "*abssf2"
4497 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4498 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4499 "TARGET_HARD_FLOAT && TARGET_FPRS"
4501 [(set_attr "type" "fp")])
4504 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4505 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4506 "TARGET_HARD_FLOAT && TARGET_FPRS"
4508 [(set_attr "type" "fp")])
4510 (define_expand "addsf3"
4511 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4512 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4513 (match_operand:SF 2 "gpc_reg_operand" "")))]
4518 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4519 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4520 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4521 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4523 [(set_attr "type" "fp")])
4526 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4527 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4528 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4529 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4530 "{fa|fadd} %0,%1,%2"
4531 [(set_attr "type" "fp")])
4533 (define_expand "subsf3"
4534 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4535 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4536 (match_operand:SF 2 "gpc_reg_operand" "")))]
4541 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4542 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4543 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4544 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4546 [(set_attr "type" "fp")])
4549 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4550 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4551 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4552 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4553 "{fs|fsub} %0,%1,%2"
4554 [(set_attr "type" "fp")])
4556 (define_expand "mulsf3"
4557 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4558 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4559 (match_operand:SF 2 "gpc_reg_operand" "")))]
4564 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4565 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4566 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4567 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4569 [(set_attr "type" "fp")])
4572 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4573 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4574 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4575 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4576 "{fm|fmul} %0,%1,%2"
4577 [(set_attr "type" "dmul")])
4579 (define_expand "divsf3"
4580 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4581 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4582 (match_operand:SF 2 "gpc_reg_operand" "")))]
4587 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4588 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4589 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4590 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4592 [(set_attr "type" "sdiv")])
4595 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4596 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4597 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4598 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4599 "{fd|fdiv} %0,%1,%2"
4600 [(set_attr "type" "ddiv")])
4603 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4604 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4605 (match_operand:SF 2 "gpc_reg_operand" "f"))
4606 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4607 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4608 "fmadds %0,%1,%2,%3"
4609 [(set_attr "type" "fp")])
4612 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4613 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4614 (match_operand:SF 2 "gpc_reg_operand" "f"))
4615 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4616 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4617 "{fma|fmadd} %0,%1,%2,%3"
4618 [(set_attr "type" "dmul")])
4621 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4622 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4623 (match_operand:SF 2 "gpc_reg_operand" "f"))
4624 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4625 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4626 "fmsubs %0,%1,%2,%3"
4627 [(set_attr "type" "fp")])
4630 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4631 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4632 (match_operand:SF 2 "gpc_reg_operand" "f"))
4633 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4634 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4635 "{fms|fmsub} %0,%1,%2,%3"
4636 [(set_attr "type" "dmul")])
4639 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4640 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4641 (match_operand:SF 2 "gpc_reg_operand" "f"))
4642 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4643 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4644 && HONOR_SIGNED_ZEROS (SFmode)"
4645 "fnmadds %0,%1,%2,%3"
4646 [(set_attr "type" "fp")])
4649 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4650 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4651 (match_operand:SF 2 "gpc_reg_operand" "f"))
4652 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4653 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4654 && ! HONOR_SIGNED_ZEROS (SFmode)"
4655 "fnmadds %0,%1,%2,%3"
4656 [(set_attr "type" "fp")])
4659 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4660 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4661 (match_operand:SF 2 "gpc_reg_operand" "f"))
4662 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4663 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4664 "{fnma|fnmadd} %0,%1,%2,%3"
4665 [(set_attr "type" "dmul")])
4668 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4669 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4670 (match_operand:SF 2 "gpc_reg_operand" "f"))
4671 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4672 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4673 && ! HONOR_SIGNED_ZEROS (SFmode)"
4674 "{fnma|fnmadd} %0,%1,%2,%3"
4675 [(set_attr "type" "dmul")])
4678 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4679 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4680 (match_operand:SF 2 "gpc_reg_operand" "f"))
4681 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4682 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4683 && HONOR_SIGNED_ZEROS (SFmode)"
4684 "fnmsubs %0,%1,%2,%3"
4685 [(set_attr "type" "fp")])
4688 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4689 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4690 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4691 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4692 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4693 && ! HONOR_SIGNED_ZEROS (SFmode)"
4694 "fnmsubs %0,%1,%2,%3"
4695 [(set_attr "type" "fp")])
4698 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4699 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4700 (match_operand:SF 2 "gpc_reg_operand" "f"))
4701 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4702 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4703 "{fnms|fnmsub} %0,%1,%2,%3"
4704 [(set_attr "type" "dmul")])
4707 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4708 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4709 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4710 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4711 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4712 && ! HONOR_SIGNED_ZEROS (SFmode)"
4713 "{fnms|fnmsub} %0,%1,%2,%3"
4714 [(set_attr "type" "fp")])
4716 (define_expand "sqrtsf2"
4717 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4718 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4719 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4723 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4724 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4725 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4727 [(set_attr "type" "ssqrt")])
4730 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4731 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4732 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4734 [(set_attr "type" "dsqrt")])
4736 (define_expand "copysignsf3"
4738 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
4740 (neg:SF (abs:SF (match_dup 1))))
4741 (set (match_operand:SF 0 "gpc_reg_operand" "")
4742 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
4746 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4747 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
4749 operands[3] = gen_reg_rtx (SFmode);
4750 operands[4] = gen_reg_rtx (SFmode);
4751 operands[5] = CONST0_RTX (SFmode);
4754 (define_expand "copysigndf3"
4756 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
4758 (neg:DF (abs:DF (match_dup 1))))
4759 (set (match_operand:DF 0 "gpc_reg_operand" "")
4760 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
4764 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4765 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
4767 operands[3] = gen_reg_rtx (DFmode);
4768 operands[4] = gen_reg_rtx (DFmode);
4769 operands[5] = CONST0_RTX (DFmode);
4772 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4773 ;; fsel instruction and some auxiliary computations. Then we just have a
4774 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4776 (define_expand "smaxsf3"
4777 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4778 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4779 (match_operand:SF 2 "gpc_reg_operand" ""))
4782 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4783 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4785 (define_expand "sminsf3"
4786 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4787 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4788 (match_operand:SF 2 "gpc_reg_operand" ""))
4791 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4792 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4795 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4796 (match_operator:SF 3 "min_max_operator"
4797 [(match_operand:SF 1 "gpc_reg_operand" "")
4798 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4799 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4802 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4803 operands[1], operands[2]);
4807 (define_expand "movsicc"
4808 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4809 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4810 (match_operand:SI 2 "gpc_reg_operand" "")
4811 (match_operand:SI 3 "gpc_reg_operand" "")))]
4815 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4821 ;; We use the BASE_REGS for the isel input operands because, if rA is
4822 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4823 ;; because we may switch the operands and rB may end up being rA.
4825 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4826 ;; leave out the mode in operand 4 and use one pattern, but reload can
4827 ;; change the mode underneath our feet and then gets confused trying
4828 ;; to reload the value.
4829 (define_insn "isel_signed"
4830 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4832 (match_operator 1 "comparison_operator"
4833 [(match_operand:CC 4 "cc_reg_operand" "y")
4835 (match_operand:SI 2 "gpc_reg_operand" "b")
4836 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4839 { return output_isel (operands); }"
4840 [(set_attr "length" "4")])
4842 (define_insn "isel_unsigned"
4843 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4845 (match_operator 1 "comparison_operator"
4846 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4848 (match_operand:SI 2 "gpc_reg_operand" "b")
4849 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4852 { return output_isel (operands); }"
4853 [(set_attr "length" "4")])
4855 (define_expand "movsfcc"
4856 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4857 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4858 (match_operand:SF 2 "gpc_reg_operand" "")
4859 (match_operand:SF 3 "gpc_reg_operand" "")))]
4860 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4863 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4869 (define_insn "*fselsfsf4"
4870 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4871 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4872 (match_operand:SF 4 "zero_fp_constant" "F"))
4873 (match_operand:SF 2 "gpc_reg_operand" "f")
4874 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4875 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4877 [(set_attr "type" "fp")])
4879 (define_insn "*fseldfsf4"
4880 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4881 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4882 (match_operand:DF 4 "zero_fp_constant" "F"))
4883 (match_operand:SF 2 "gpc_reg_operand" "f")
4884 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4885 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4887 [(set_attr "type" "fp")])
4889 (define_expand "negdf2"
4890 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4891 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4892 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4895 (define_insn "*negdf2_fpr"
4896 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4897 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4898 "TARGET_HARD_FLOAT && TARGET_FPRS"
4900 [(set_attr "type" "fp")])
4902 (define_expand "absdf2"
4903 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4904 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4905 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4908 (define_insn "*absdf2_fpr"
4909 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4910 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4911 "TARGET_HARD_FLOAT && TARGET_FPRS"
4913 [(set_attr "type" "fp")])
4915 (define_insn "*nabsdf2_fpr"
4916 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4917 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4918 "TARGET_HARD_FLOAT && TARGET_FPRS"
4920 [(set_attr "type" "fp")])
4922 (define_expand "adddf3"
4923 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4924 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4925 (match_operand:DF 2 "gpc_reg_operand" "")))]
4926 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4929 (define_insn "*adddf3_fpr"
4930 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4931 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4932 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4933 "TARGET_HARD_FLOAT && TARGET_FPRS"
4934 "{fa|fadd} %0,%1,%2"
4935 [(set_attr "type" "fp")])
4937 (define_expand "subdf3"
4938 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4939 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4940 (match_operand:DF 2 "gpc_reg_operand" "")))]
4941 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4944 (define_insn "*subdf3_fpr"
4945 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4946 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4947 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4948 "TARGET_HARD_FLOAT && TARGET_FPRS"
4949 "{fs|fsub} %0,%1,%2"
4950 [(set_attr "type" "fp")])
4952 (define_expand "muldf3"
4953 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4954 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
4955 (match_operand:DF 2 "gpc_reg_operand" "")))]
4956 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4959 (define_insn "*muldf3_fpr"
4960 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4961 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4962 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4963 "TARGET_HARD_FLOAT && TARGET_FPRS"
4964 "{fm|fmul} %0,%1,%2"
4965 [(set_attr "type" "dmul")])
4967 (define_expand "divdf3"
4968 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4969 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
4970 (match_operand:DF 2 "gpc_reg_operand" "")))]
4971 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4974 (define_insn "*divdf3_fpr"
4975 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4976 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4977 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4978 "TARGET_HARD_FLOAT && TARGET_FPRS"
4979 "{fd|fdiv} %0,%1,%2"
4980 [(set_attr "type" "ddiv")])
4983 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4984 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4985 (match_operand:DF 2 "gpc_reg_operand" "f"))
4986 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4987 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4988 "{fma|fmadd} %0,%1,%2,%3"
4989 [(set_attr "type" "dmul")])
4992 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4993 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4994 (match_operand:DF 2 "gpc_reg_operand" "f"))
4995 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4996 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4997 "{fms|fmsub} %0,%1,%2,%3"
4998 [(set_attr "type" "dmul")])
5001 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5002 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5003 (match_operand:DF 2 "gpc_reg_operand" "f"))
5004 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5005 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5006 && HONOR_SIGNED_ZEROS (DFmode)"
5007 "{fnma|fnmadd} %0,%1,%2,%3"
5008 [(set_attr "type" "dmul")])
5011 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5012 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5013 (match_operand:DF 2 "gpc_reg_operand" "f"))
5014 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5015 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5016 && ! HONOR_SIGNED_ZEROS (DFmode)"
5017 "{fnma|fnmadd} %0,%1,%2,%3"
5018 [(set_attr "type" "dmul")])
5021 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5022 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5023 (match_operand:DF 2 "gpc_reg_operand" "f"))
5024 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5025 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5026 && HONOR_SIGNED_ZEROS (DFmode)"
5027 "{fnms|fnmsub} %0,%1,%2,%3"
5028 [(set_attr "type" "dmul")])
5031 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5032 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5033 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5034 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5035 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5036 && ! HONOR_SIGNED_ZEROS (DFmode)"
5037 "{fnms|fnmsub} %0,%1,%2,%3"
5038 [(set_attr "type" "dmul")])
5040 (define_insn "sqrtdf2"
5041 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5042 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5043 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5045 [(set_attr "type" "dsqrt")])
5047 ;; The conditional move instructions allow us to perform max and min
5048 ;; operations even when
5050 (define_expand "smaxdf3"
5051 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5052 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5053 (match_operand:DF 2 "gpc_reg_operand" ""))
5056 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5057 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5059 (define_expand "smindf3"
5060 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5061 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5062 (match_operand:DF 2 "gpc_reg_operand" ""))
5065 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5066 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5069 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5070 (match_operator:DF 3 "min_max_operator"
5071 [(match_operand:DF 1 "gpc_reg_operand" "")
5072 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5073 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5076 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5077 operands[1], operands[2]);
5081 (define_expand "movdfcc"
5082 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5083 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5084 (match_operand:DF 2 "gpc_reg_operand" "")
5085 (match_operand:DF 3 "gpc_reg_operand" "")))]
5086 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5089 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5095 (define_insn "*fseldfdf4"
5096 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5097 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5098 (match_operand:DF 4 "zero_fp_constant" "F"))
5099 (match_operand:DF 2 "gpc_reg_operand" "f")
5100 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5101 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5103 [(set_attr "type" "fp")])
5105 (define_insn "*fselsfdf4"
5106 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5107 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5108 (match_operand:SF 4 "zero_fp_constant" "F"))
5109 (match_operand:DF 2 "gpc_reg_operand" "f")
5110 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5113 [(set_attr "type" "fp")])
5115 ;; Conversions to and from floating-point.
5117 (define_expand "fixuns_truncsfsi2"
5118 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5119 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5120 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5123 (define_expand "fix_truncsfsi2"
5124 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5125 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5126 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5129 ; For each of these conversions, there is a define_expand, a define_insn
5130 ; with a '#' template, and a define_split (with C code). The idea is
5131 ; to allow constant folding with the template of the define_insn,
5132 ; then to have the insns split later (between sched1 and final).
5134 (define_expand "floatsidf2"
5135 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5136 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5139 (clobber (match_dup 4))
5140 (clobber (match_dup 5))
5141 (clobber (match_dup 6))])]
5142 "TARGET_HARD_FLOAT && TARGET_FPRS"
5145 if (TARGET_E500_DOUBLE)
5147 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5150 if (TARGET_POWERPC64)
5152 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5153 rtx t1 = gen_reg_rtx (DImode);
5154 rtx t2 = gen_reg_rtx (DImode);
5155 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5159 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5160 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5161 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5162 operands[5] = gen_reg_rtx (DFmode);
5163 operands[6] = gen_reg_rtx (SImode);
5166 (define_insn "*floatsidf2_internal"
5167 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5168 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5169 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5170 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5171 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5172 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5173 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5174 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5176 [(set_attr "length" "24")])
5179 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5180 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5181 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5182 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5183 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5184 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5185 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5186 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5187 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5188 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5189 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5190 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5191 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5192 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5193 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5196 rtx lowword, highword;
5197 if (GET_CODE (operands[4]) != MEM)
5199 highword = XEXP (operands[4], 0);
5200 lowword = plus_constant (highword, 4);
5201 if (! WORDS_BIG_ENDIAN)
5204 tmp = highword; highword = lowword; lowword = tmp;
5207 emit_insn (gen_xorsi3 (operands[6], operands[1],
5208 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5209 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5210 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5211 emit_move_insn (operands[5], operands[4]);
5212 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5216 (define_expand "floatunssisf2"
5217 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5218 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5219 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5222 (define_expand "floatunssidf2"
5223 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5224 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5227 (clobber (match_dup 4))
5228 (clobber (match_dup 5))])]
5229 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5232 if (TARGET_E500_DOUBLE)
5234 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5237 if (TARGET_POWERPC64)
5239 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5240 rtx t1 = gen_reg_rtx (DImode);
5241 rtx t2 = gen_reg_rtx (DImode);
5242 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5247 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5248 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5249 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5250 operands[5] = gen_reg_rtx (DFmode);
5253 (define_insn "*floatunssidf2_internal"
5254 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5255 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5256 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5257 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5258 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5259 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5260 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5262 [(set_attr "length" "20")])
5265 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5266 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5267 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5268 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5269 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5270 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5271 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5272 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5273 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5274 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5275 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5276 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5277 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5280 rtx lowword, highword;
5281 if (GET_CODE (operands[4]) != MEM)
5283 highword = XEXP (operands[4], 0);
5284 lowword = plus_constant (highword, 4);
5285 if (! WORDS_BIG_ENDIAN)
5288 tmp = highword; highword = lowword; lowword = tmp;
5291 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5292 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5293 emit_move_insn (operands[5], operands[4]);
5294 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5298 ; In the TARGET_PPC_GFXOPT case, this could and probably should
5299 ; take a memory destination; but actually making this work is hard.
5300 (define_expand "fix_truncdfsi2"
5301 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5302 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5303 (clobber (match_dup 2))
5304 (clobber (match_dup 3))])]
5305 "(TARGET_POWER2 || TARGET_POWERPC)
5306 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5309 if (TARGET_E500_DOUBLE)
5311 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5314 operands[2] = gen_reg_rtx (DImode);
5315 if (TARGET_PPC_GFXOPT)
5317 rtx orig_dest = operands[0];
5318 if (GET_CODE (orig_dest) != MEM)
5319 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5320 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5322 if (operands[0] != orig_dest)
5323 emit_move_insn (orig_dest, operands[0]);
5326 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5329 (define_insn_and_split "*fix_truncdfsi2_internal"
5330 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5331 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5332 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5333 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5334 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5341 if (GET_CODE (operands[3]) != MEM)
5343 lowword = XEXP (operands[3], 0);
5344 if (WORDS_BIG_ENDIAN)
5345 lowword = plus_constant (lowword, 4);
5347 emit_insn (gen_fctiwz (operands[2], operands[1]));
5348 emit_move_insn (operands[3], operands[2]);
5349 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5352 [(set_attr "length" "16")])
5354 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5355 [(set (match_operand:SI 0 "memory_operand" "=Z")
5356 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5357 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5358 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5359 && TARGET_PPC_GFXOPT"
5365 emit_insn (gen_fctiwz (operands[2], operands[1]));
5366 emit_insn (gen_stfiwx (operands[0], operands[2]));
5369 [(set_attr "length" "16")])
5371 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5372 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5373 ; because the first makes it clear that operand 0 is not live
5374 ; before the instruction.
5375 (define_insn "fctiwz"
5376 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5377 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5379 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5380 "{fcirz|fctiwz} %0,%1"
5381 [(set_attr "type" "fp")])
5383 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5384 (define_insn "stfiwx"
5385 [(set (match_operand:SI 0 "memory_operand" "=Z")
5386 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
5390 [(set_attr "type" "fpstore")])
5392 (define_expand "floatsisf2"
5393 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5394 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5395 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5398 (define_insn "floatdidf2"
5399 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5400 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5401 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5403 [(set_attr "type" "fp")])
5405 (define_insn_and_split "floatsidf_ppc64"
5406 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5407 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5408 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5409 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5410 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5411 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5414 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5415 (set (match_dup 2) (match_dup 3))
5416 (set (match_dup 4) (match_dup 2))
5417 (set (match_dup 0) (float:DF (match_dup 4)))]
5420 (define_insn_and_split "floatunssidf_ppc64"
5421 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5422 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5423 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5424 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5425 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5426 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5429 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5430 (set (match_dup 2) (match_dup 3))
5431 (set (match_dup 4) (match_dup 2))
5432 (set (match_dup 0) (float:DF (match_dup 4)))]
5435 (define_insn "fix_truncdfdi2"
5436 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5437 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5438 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5440 [(set_attr "type" "fp")])
5442 (define_expand "floatdisf2"
5443 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5444 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5445 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5448 rtx val = operands[1];
5449 if (!flag_unsafe_math_optimizations)
5451 rtx label = gen_label_rtx ();
5452 val = gen_reg_rtx (DImode);
5453 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5456 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5460 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5461 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5462 ;; from double rounding.
5463 (define_insn_and_split "floatdisf2_internal1"
5464 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5465 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5466 (clobber (match_scratch:DF 2 "=f"))]
5467 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5469 "&& reload_completed"
5471 (float:DF (match_dup 1)))
5473 (float_truncate:SF (match_dup 2)))]
5476 ;; Twiddles bits to avoid double rounding.
5477 ;; Bits that might be truncated when converting to DFmode are replaced
5478 ;; by a bit that won't be lost at that stage, but is below the SFmode
5479 ;; rounding position.
5480 (define_expand "floatdisf2_internal2"
5481 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5483 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5485 (clobber (scratch:CC))])
5486 (set (match_dup 3) (plus:DI (match_dup 3)
5488 (set (match_dup 0) (plus:DI (match_dup 0)
5490 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5492 (set (match_dup 0) (ior:DI (match_dup 0)
5494 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
5496 (clobber (scratch:CC))])
5497 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5498 (label_ref (match_operand:DI 2 "" ""))
5500 (set (match_dup 0) (match_dup 1))]
5501 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5504 operands[3] = gen_reg_rtx (DImode);
5505 operands[4] = gen_reg_rtx (CCUNSmode);
5508 ;; Define the DImode operations that can be done in a small number
5509 ;; of instructions. The & constraints are to prevent the register
5510 ;; allocator from allocating registers that overlap with the inputs
5511 ;; (for example, having an input in 7,8 and an output in 6,7). We
5512 ;; also allow for the output being the same as one of the inputs.
5514 (define_insn "*adddi3_noppc64"
5515 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5516 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5517 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5518 "! TARGET_POWERPC64"
5521 if (WORDS_BIG_ENDIAN)
5522 return (GET_CODE (operands[2])) != CONST_INT
5523 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5524 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5526 return (GET_CODE (operands[2])) != CONST_INT
5527 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5528 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5530 [(set_attr "type" "two")
5531 (set_attr "length" "8")])
5533 (define_insn "*subdi3_noppc64"
5534 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5535 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5536 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5537 "! TARGET_POWERPC64"
5540 if (WORDS_BIG_ENDIAN)
5541 return (GET_CODE (operands[1]) != CONST_INT)
5542 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5543 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5545 return (GET_CODE (operands[1]) != CONST_INT)
5546 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5547 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5549 [(set_attr "type" "two")
5550 (set_attr "length" "8")])
5552 (define_insn "*negdi2_noppc64"
5553 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5554 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5555 "! TARGET_POWERPC64"
5558 return (WORDS_BIG_ENDIAN)
5559 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5560 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5562 [(set_attr "type" "two")
5563 (set_attr "length" "8")])
5565 (define_expand "mulsidi3"
5566 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5567 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5568 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5569 "! TARGET_POWERPC64"
5572 if (! TARGET_POWER && ! TARGET_POWERPC)
5574 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5575 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5576 emit_insn (gen_mull_call ());
5577 if (WORDS_BIG_ENDIAN)
5578 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5581 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5582 gen_rtx_REG (SImode, 3));
5583 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5584 gen_rtx_REG (SImode, 4));
5588 else if (TARGET_POWER)
5590 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5595 (define_insn "mulsidi3_mq"
5596 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5597 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5598 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5599 (clobber (match_scratch:SI 3 "=q"))]
5601 "mul %0,%1,%2\;mfmq %L0"
5602 [(set_attr "type" "imul")
5603 (set_attr "length" "8")])
5605 (define_insn "*mulsidi3_no_mq"
5606 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5607 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5608 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5609 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5612 return (WORDS_BIG_ENDIAN)
5613 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5614 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5616 [(set_attr "type" "imul")
5617 (set_attr "length" "8")])
5620 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5621 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5622 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5623 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5626 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5627 (sign_extend:DI (match_dup 2)))
5630 (mult:SI (match_dup 1)
5634 int endian = (WORDS_BIG_ENDIAN == 0);
5635 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5636 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5639 (define_expand "umulsidi3"
5640 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5641 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5642 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5643 "TARGET_POWERPC && ! TARGET_POWERPC64"
5648 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5653 (define_insn "umulsidi3_mq"
5654 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5655 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5656 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5657 (clobber (match_scratch:SI 3 "=q"))]
5658 "TARGET_POWERPC && TARGET_POWER"
5661 return (WORDS_BIG_ENDIAN)
5662 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5663 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5665 [(set_attr "type" "imul")
5666 (set_attr "length" "8")])
5668 (define_insn "*umulsidi3_no_mq"
5669 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5670 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5671 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5672 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5675 return (WORDS_BIG_ENDIAN)
5676 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5677 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5679 [(set_attr "type" "imul")
5680 (set_attr "length" "8")])
5683 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5684 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5685 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5686 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5689 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5690 (zero_extend:DI (match_dup 2)))
5693 (mult:SI (match_dup 1)
5697 int endian = (WORDS_BIG_ENDIAN == 0);
5698 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5699 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5702 (define_expand "smulsi3_highpart"
5703 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5705 (lshiftrt:DI (mult:DI (sign_extend:DI
5706 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5708 (match_operand:SI 2 "gpc_reg_operand" "r")))
5713 if (! TARGET_POWER && ! TARGET_POWERPC)
5715 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5716 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5717 emit_insn (gen_mulh_call ());
5718 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5721 else if (TARGET_POWER)
5723 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5728 (define_insn "smulsi3_highpart_mq"
5729 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5731 (lshiftrt:DI (mult:DI (sign_extend:DI
5732 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5734 (match_operand:SI 2 "gpc_reg_operand" "r")))
5736 (clobber (match_scratch:SI 3 "=q"))]
5739 [(set_attr "type" "imul")])
5741 (define_insn "*smulsi3_highpart_no_mq"
5742 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5744 (lshiftrt:DI (mult:DI (sign_extend:DI
5745 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5747 (match_operand:SI 2 "gpc_reg_operand" "r")))
5749 "TARGET_POWERPC && ! TARGET_POWER"
5751 [(set_attr "type" "imul")])
5753 (define_expand "umulsi3_highpart"
5754 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5756 (lshiftrt:DI (mult:DI (zero_extend:DI
5757 (match_operand:SI 1 "gpc_reg_operand" ""))
5759 (match_operand:SI 2 "gpc_reg_operand" "")))
5766 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5771 (define_insn "umulsi3_highpart_mq"
5772 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5774 (lshiftrt:DI (mult:DI (zero_extend:DI
5775 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5777 (match_operand:SI 2 "gpc_reg_operand" "r")))
5779 (clobber (match_scratch:SI 3 "=q"))]
5780 "TARGET_POWERPC && TARGET_POWER"
5782 [(set_attr "type" "imul")])
5784 (define_insn "*umulsi3_highpart_no_mq"
5785 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5787 (lshiftrt:DI (mult:DI (zero_extend:DI
5788 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5790 (match_operand:SI 2 "gpc_reg_operand" "r")))
5792 "TARGET_POWERPC && ! TARGET_POWER"
5794 [(set_attr "type" "imul")])
5796 ;; If operands 0 and 2 are in the same register, we have a problem. But
5797 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5798 ;; why we have the strange constraints below.
5799 (define_insn "ashldi3_power"
5800 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5801 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5802 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5803 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5806 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5807 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5808 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5809 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5810 [(set_attr "length" "8")])
5812 (define_insn "lshrdi3_power"
5813 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5814 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5815 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5816 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5819 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5820 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5821 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5822 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5823 [(set_attr "length" "8")])
5825 ;; Shift by a variable amount is too complex to be worth open-coding. We
5826 ;; just handle shifts by constants.
5827 (define_insn "ashrdi3_power"
5828 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5829 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5830 (match_operand:SI 2 "const_int_operand" "M,i")))
5831 (clobber (match_scratch:SI 3 "=X,q"))]
5834 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5835 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5836 [(set_attr "length" "8")])
5838 (define_insn "ashrdi3_no_power"
5839 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5840 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5841 (match_operand:SI 2 "const_int_operand" "M,i")))]
5842 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5844 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5845 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5846 [(set_attr "type" "two,three")
5847 (set_attr "length" "8,12")])
5849 (define_insn "*ashrdisi3_noppc64"
5850 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5851 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5852 (const_int 32)) 4))]
5853 "TARGET_32BIT && !TARGET_POWERPC64"
5856 if (REGNO (operands[0]) == REGNO (operands[1]))
5859 return \"mr %0,%1\";
5861 [(set_attr "length" "4")])
5864 ;; PowerPC64 DImode operations.
5866 (define_expand "adddi3"
5867 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5868 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5869 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
5873 if (! TARGET_POWERPC64)
5875 if (non_short_cint_operand (operands[2], DImode))
5879 if (GET_CODE (operands[2]) == CONST_INT
5880 && ! add_operand (operands[2], DImode))
5882 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5883 ? operands[0] : gen_reg_rtx (DImode));
5885 HOST_WIDE_INT val = INTVAL (operands[2]);
5886 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5887 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5889 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5892 /* The ordering here is important for the prolog expander.
5893 When space is allocated from the stack, adding 'low' first may
5894 produce a temporary deallocation (which would be bad). */
5895 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
5896 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5901 ;; Discourage ai/addic because of carry but provide it in an alternative
5902 ;; allowing register zero as source.
5904 (define_insn "*adddi3_internal1"
5905 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5906 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
5907 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
5915 (define_insn "*adddi3_internal2"
5916 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5917 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5918 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5920 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5927 [(set_attr "type" "fast_compare,compare,compare,compare")
5928 (set_attr "length" "4,4,8,8")])
5931 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5932 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5933 (match_operand:DI 2 "reg_or_short_operand" ""))
5935 (clobber (match_scratch:DI 3 ""))]
5936 "TARGET_POWERPC64 && reload_completed"
5938 (plus:DI (match_dup 1) (match_dup 2)))
5940 (compare:CC (match_dup 3)
5944 (define_insn "*adddi3_internal3"
5945 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5946 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5947 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5949 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5950 (plus:DI (match_dup 1) (match_dup 2)))]
5957 [(set_attr "type" "fast_compare,compare,compare,compare")
5958 (set_attr "length" "4,4,8,8")])
5961 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5962 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5963 (match_operand:DI 2 "reg_or_short_operand" ""))
5965 (set (match_operand:DI 0 "gpc_reg_operand" "")
5966 (plus:DI (match_dup 1) (match_dup 2)))]
5967 "TARGET_POWERPC64 && reload_completed"
5969 (plus:DI (match_dup 1) (match_dup 2)))
5971 (compare:CC (match_dup 0)
5975 ;; Split an add that we can't do in one insn into two insns, each of which
5976 ;; does one 16-bit part. This is used by combine. Note that the low-order
5977 ;; add should be last in case the result gets used in an address.
5980 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5981 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5982 (match_operand:DI 2 "non_add_cint_operand" "")))]
5984 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5985 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5988 HOST_WIDE_INT val = INTVAL (operands[2]);
5989 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5990 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5992 operands[4] = GEN_INT (low);
5993 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5994 operands[3] = GEN_INT (rest);
5995 else if (! no_new_pseudos)
5997 operands[3] = gen_reg_rtx (DImode);
5998 emit_move_insn (operands[3], operands[2]);
5999 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
6006 (define_insn "one_cmpldi2"
6007 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6008 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6013 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6014 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6016 (clobber (match_scratch:DI 2 "=r,r"))]
6021 [(set_attr "type" "compare")
6022 (set_attr "length" "4,8")])
6025 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6026 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6028 (clobber (match_scratch:DI 2 ""))]
6029 "TARGET_POWERPC64 && reload_completed"
6031 (not:DI (match_dup 1)))
6033 (compare:CC (match_dup 2)
6038 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6039 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6041 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6042 (not:DI (match_dup 1)))]
6047 [(set_attr "type" "compare")
6048 (set_attr "length" "4,8")])
6051 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6052 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6054 (set (match_operand:DI 0 "gpc_reg_operand" "")
6055 (not:DI (match_dup 1)))]
6056 "TARGET_POWERPC64 && reload_completed"
6058 (not:DI (match_dup 1)))
6060 (compare:CC (match_dup 0)
6065 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6066 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
6067 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
6074 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6075 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6076 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6078 (clobber (match_scratch:DI 3 "=r,r"))]
6083 [(set_attr "type" "fast_compare")
6084 (set_attr "length" "4,8")])
6087 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6088 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6089 (match_operand:DI 2 "gpc_reg_operand" ""))
6091 (clobber (match_scratch:DI 3 ""))]
6092 "TARGET_POWERPC64 && reload_completed"
6094 (minus:DI (match_dup 1) (match_dup 2)))
6096 (compare:CC (match_dup 3)
6101 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6102 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6103 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6105 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6106 (minus:DI (match_dup 1) (match_dup 2)))]
6111 [(set_attr "type" "fast_compare")
6112 (set_attr "length" "4,8")])
6115 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6116 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6117 (match_operand:DI 2 "gpc_reg_operand" ""))
6119 (set (match_operand:DI 0 "gpc_reg_operand" "")
6120 (minus:DI (match_dup 1) (match_dup 2)))]
6121 "TARGET_POWERPC64 && reload_completed"
6123 (minus:DI (match_dup 1) (match_dup 2)))
6125 (compare:CC (match_dup 0)
6129 (define_expand "subdi3"
6130 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6131 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
6132 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
6136 if (GET_CODE (operands[2]) == CONST_INT)
6138 emit_insn (gen_adddi3 (operands[0], operands[1],
6139 negate_rtx (DImode, operands[2])));
6144 (define_insn_and_split "absdi2"
6145 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6146 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6147 (clobber (match_scratch:DI 2 "=&r,&r"))]
6150 "&& reload_completed"
6151 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6152 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6153 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6156 (define_insn_and_split "*nabsdi2"
6157 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6158 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6159 (clobber (match_scratch:DI 2 "=&r,&r"))]
6162 "&& reload_completed"
6163 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6164 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6165 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6168 (define_expand "negdi2"
6169 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6170 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
6175 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6176 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6181 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6182 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6184 (clobber (match_scratch:DI 2 "=r,r"))]
6189 [(set_attr "type" "fast_compare")
6190 (set_attr "length" "4,8")])
6193 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6194 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6196 (clobber (match_scratch:DI 2 ""))]
6197 "TARGET_POWERPC64 && reload_completed"
6199 (neg:DI (match_dup 1)))
6201 (compare:CC (match_dup 2)
6206 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6207 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6209 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6210 (neg:DI (match_dup 1)))]
6215 [(set_attr "type" "fast_compare")
6216 (set_attr "length" "4,8")])
6219 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6220 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6222 (set (match_operand:DI 0 "gpc_reg_operand" "")
6223 (neg:DI (match_dup 1)))]
6224 "TARGET_POWERPC64 && reload_completed"
6226 (neg:DI (match_dup 1)))
6228 (compare:CC (match_dup 0)
6232 (define_insn "clzdi2"
6233 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6234 (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6238 (define_expand "ctzdi2"
6240 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6241 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6243 (clobber (scratch:CC))])
6244 (set (match_dup 4) (clz:DI (match_dup 3)))
6245 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6246 (minus:DI (const_int 63) (match_dup 4)))]
6249 operands[2] = gen_reg_rtx (DImode);
6250 operands[3] = gen_reg_rtx (DImode);
6251 operands[4] = gen_reg_rtx (DImode);
6254 (define_expand "ffsdi2"
6256 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6257 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6259 (clobber (scratch:CC))])
6260 (set (match_dup 4) (clz:DI (match_dup 3)))
6261 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6262 (minus:DI (const_int 64) (match_dup 4)))]
6265 operands[2] = gen_reg_rtx (DImode);
6266 operands[3] = gen_reg_rtx (DImode);
6267 operands[4] = gen_reg_rtx (DImode);
6270 (define_insn "muldi3"
6271 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6272 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6273 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6276 [(set_attr "type" "lmul")])
6278 (define_insn "*muldi3_internal1"
6279 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6280 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6281 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6283 (clobber (match_scratch:DI 3 "=r,r"))]
6288 [(set_attr "type" "lmul_compare")
6289 (set_attr "length" "4,8")])
6292 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6293 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6294 (match_operand:DI 2 "gpc_reg_operand" ""))
6296 (clobber (match_scratch:DI 3 ""))]
6297 "TARGET_POWERPC64 && reload_completed"
6299 (mult:DI (match_dup 1) (match_dup 2)))
6301 (compare:CC (match_dup 3)
6305 (define_insn "*muldi3_internal2"
6306 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6307 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6308 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6310 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6311 (mult:DI (match_dup 1) (match_dup 2)))]
6316 [(set_attr "type" "lmul_compare")
6317 (set_attr "length" "4,8")])
6320 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6321 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6322 (match_operand:DI 2 "gpc_reg_operand" ""))
6324 (set (match_operand:DI 0 "gpc_reg_operand" "")
6325 (mult:DI (match_dup 1) (match_dup 2)))]
6326 "TARGET_POWERPC64 && reload_completed"
6328 (mult:DI (match_dup 1) (match_dup 2)))
6330 (compare:CC (match_dup 0)
6334 (define_insn "smuldi3_highpart"
6335 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6337 (lshiftrt:TI (mult:TI (sign_extend:TI
6338 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6340 (match_operand:DI 2 "gpc_reg_operand" "r")))
6344 [(set_attr "type" "lmul")])
6346 (define_insn "umuldi3_highpart"
6347 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6349 (lshiftrt:TI (mult:TI (zero_extend:TI
6350 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6352 (match_operand:DI 2 "gpc_reg_operand" "r")))
6356 [(set_attr "type" "lmul")])
6358 (define_expand "divdi3"
6359 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6360 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6361 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6365 if (GET_CODE (operands[2]) == CONST_INT
6366 && INTVAL (operands[2]) > 0
6367 && exact_log2 (INTVAL (operands[2])) >= 0)
6370 operands[2] = force_reg (DImode, operands[2]);
6373 (define_expand "moddi3"
6374 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6375 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6376 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6384 if (GET_CODE (operands[2]) != CONST_INT
6385 || INTVAL (operands[2]) <= 0
6386 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6389 temp1 = gen_reg_rtx (DImode);
6390 temp2 = gen_reg_rtx (DImode);
6392 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6393 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6394 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6399 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6400 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6401 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6403 "sradi %0,%1,%p2\;addze %0,%0"
6404 [(set_attr "type" "two")
6405 (set_attr "length" "8")])
6408 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6409 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6410 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6412 (clobber (match_scratch:DI 3 "=r,r"))]
6415 sradi %3,%1,%p2\;addze. %3,%3
6417 [(set_attr "type" "compare")
6418 (set_attr "length" "8,12")])
6421 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6422 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6423 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6425 (clobber (match_scratch:DI 3 ""))]
6426 "TARGET_POWERPC64 && reload_completed"
6428 (div:DI (match_dup 1) (match_dup 2)))
6430 (compare:CC (match_dup 3)
6435 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6436 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6437 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6439 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6440 (div:DI (match_dup 1) (match_dup 2)))]
6443 sradi %0,%1,%p2\;addze. %0,%0
6445 [(set_attr "type" "compare")
6446 (set_attr "length" "8,12")])
6449 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6450 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6451 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6453 (set (match_operand:DI 0 "gpc_reg_operand" "")
6454 (div:DI (match_dup 1) (match_dup 2)))]
6455 "TARGET_POWERPC64 && reload_completed"
6457 (div:DI (match_dup 1) (match_dup 2)))
6459 (compare:CC (match_dup 0)
6464 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6465 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6466 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6469 [(set_attr "type" "ldiv")])
6471 (define_insn "udivdi3"
6472 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6473 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6474 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6477 [(set_attr "type" "ldiv")])
6479 (define_insn "rotldi3"
6480 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6481 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6482 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6484 "rld%I2cl %0,%1,%H2,0")
6486 (define_insn "*rotldi3_internal2"
6487 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6488 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6489 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6491 (clobber (match_scratch:DI 3 "=r,r"))]
6494 rld%I2cl. %3,%1,%H2,0
6496 [(set_attr "type" "delayed_compare")
6497 (set_attr "length" "4,8")])
6500 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6501 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6502 (match_operand:DI 2 "reg_or_cint_operand" ""))
6504 (clobber (match_scratch:DI 3 ""))]
6505 "TARGET_POWERPC64 && reload_completed"
6507 (rotate:DI (match_dup 1) (match_dup 2)))
6509 (compare:CC (match_dup 3)
6513 (define_insn "*rotldi3_internal3"
6514 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6515 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6516 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6518 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6519 (rotate:DI (match_dup 1) (match_dup 2)))]
6522 rld%I2cl. %0,%1,%H2,0
6524 [(set_attr "type" "delayed_compare")
6525 (set_attr "length" "4,8")])
6528 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6529 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6530 (match_operand:DI 2 "reg_or_cint_operand" ""))
6532 (set (match_operand:DI 0 "gpc_reg_operand" "")
6533 (rotate:DI (match_dup 1) (match_dup 2)))]
6534 "TARGET_POWERPC64 && reload_completed"
6536 (rotate:DI (match_dup 1) (match_dup 2)))
6538 (compare:CC (match_dup 0)
6542 (define_insn "*rotldi3_internal4"
6543 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6544 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6545 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6546 (match_operand:DI 3 "mask64_operand" "n")))]
6548 "rld%I2c%B3 %0,%1,%H2,%S3")
6550 (define_insn "*rotldi3_internal5"
6551 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6553 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6554 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6555 (match_operand:DI 3 "mask64_operand" "n,n"))
6557 (clobber (match_scratch:DI 4 "=r,r"))]
6560 rld%I2c%B3. %4,%1,%H2,%S3
6562 [(set_attr "type" "delayed_compare")
6563 (set_attr "length" "4,8")])
6566 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6568 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6569 (match_operand:DI 2 "reg_or_cint_operand" ""))
6570 (match_operand:DI 3 "mask64_operand" ""))
6572 (clobber (match_scratch:DI 4 ""))]
6573 "TARGET_POWERPC64 && reload_completed"
6575 (and:DI (rotate:DI (match_dup 1)
6579 (compare:CC (match_dup 4)
6583 (define_insn "*rotldi3_internal6"
6584 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6586 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6587 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6588 (match_operand:DI 3 "mask64_operand" "n,n"))
6590 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6591 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6594 rld%I2c%B3. %0,%1,%H2,%S3
6596 [(set_attr "type" "delayed_compare")
6597 (set_attr "length" "4,8")])
6600 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6602 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6603 (match_operand:DI 2 "reg_or_cint_operand" ""))
6604 (match_operand:DI 3 "mask64_operand" ""))
6606 (set (match_operand:DI 0 "gpc_reg_operand" "")
6607 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6608 "TARGET_POWERPC64 && reload_completed"
6610 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6612 (compare:CC (match_dup 0)
6616 (define_insn "*rotldi3_internal7"
6617 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6620 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6621 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6623 "rld%I2cl %0,%1,%H2,56")
6625 (define_insn "*rotldi3_internal8"
6626 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6627 (compare:CC (zero_extend:DI
6629 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6630 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6632 (clobber (match_scratch:DI 3 "=r,r"))]
6635 rld%I2cl. %3,%1,%H2,56
6637 [(set_attr "type" "delayed_compare")
6638 (set_attr "length" "4,8")])
6641 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6642 (compare:CC (zero_extend:DI
6644 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6645 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6647 (clobber (match_scratch:DI 3 ""))]
6648 "TARGET_POWERPC64 && reload_completed"
6650 (zero_extend:DI (subreg:QI
6651 (rotate:DI (match_dup 1)
6654 (compare:CC (match_dup 3)
6658 (define_insn "*rotldi3_internal9"
6659 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6660 (compare:CC (zero_extend:DI
6662 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6663 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6665 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6666 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6669 rld%I2cl. %0,%1,%H2,56
6671 [(set_attr "type" "delayed_compare")
6672 (set_attr "length" "4,8")])
6675 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6676 (compare:CC (zero_extend:DI
6678 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6679 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6681 (set (match_operand:DI 0 "gpc_reg_operand" "")
6682 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6683 "TARGET_POWERPC64 && reload_completed"
6685 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6687 (compare:CC (match_dup 0)
6691 (define_insn "*rotldi3_internal10"
6692 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6695 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6696 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6698 "rld%I2cl %0,%1,%H2,48")
6700 (define_insn "*rotldi3_internal11"
6701 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6702 (compare:CC (zero_extend:DI
6704 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6705 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6707 (clobber (match_scratch:DI 3 "=r,r"))]
6710 rld%I2cl. %3,%1,%H2,48
6712 [(set_attr "type" "delayed_compare")
6713 (set_attr "length" "4,8")])
6716 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6717 (compare:CC (zero_extend:DI
6719 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6720 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6722 (clobber (match_scratch:DI 3 ""))]
6723 "TARGET_POWERPC64 && reload_completed"
6725 (zero_extend:DI (subreg:HI
6726 (rotate:DI (match_dup 1)
6729 (compare:CC (match_dup 3)
6733 (define_insn "*rotldi3_internal12"
6734 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6735 (compare:CC (zero_extend:DI
6737 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6738 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6740 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6741 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6744 rld%I2cl. %0,%1,%H2,48
6746 [(set_attr "type" "delayed_compare")
6747 (set_attr "length" "4,8")])
6750 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6751 (compare:CC (zero_extend:DI
6753 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6754 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6756 (set (match_operand:DI 0 "gpc_reg_operand" "")
6757 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6758 "TARGET_POWERPC64 && reload_completed"
6760 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6762 (compare:CC (match_dup 0)
6766 (define_insn "*rotldi3_internal13"
6767 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6770 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6771 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6773 "rld%I2cl %0,%1,%H2,32")
6775 (define_insn "*rotldi3_internal14"
6776 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6777 (compare:CC (zero_extend:DI
6779 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6780 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6782 (clobber (match_scratch:DI 3 "=r,r"))]
6785 rld%I2cl. %3,%1,%H2,32
6787 [(set_attr "type" "delayed_compare")
6788 (set_attr "length" "4,8")])
6791 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6792 (compare:CC (zero_extend:DI
6794 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6795 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6797 (clobber (match_scratch:DI 3 ""))]
6798 "TARGET_POWERPC64 && reload_completed"
6800 (zero_extend:DI (subreg:SI
6801 (rotate:DI (match_dup 1)
6804 (compare:CC (match_dup 3)
6808 (define_insn "*rotldi3_internal15"
6809 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6810 (compare:CC (zero_extend:DI
6812 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6813 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6815 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6816 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6819 rld%I2cl. %0,%1,%H2,32
6821 [(set_attr "type" "delayed_compare")
6822 (set_attr "length" "4,8")])
6825 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6826 (compare:CC (zero_extend:DI
6828 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6829 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6831 (set (match_operand:DI 0 "gpc_reg_operand" "")
6832 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6833 "TARGET_POWERPC64 && reload_completed"
6835 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6837 (compare:CC (match_dup 0)
6841 (define_expand "ashldi3"
6842 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6843 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6844 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6845 "TARGET_POWERPC64 || TARGET_POWER"
6848 if (TARGET_POWERPC64)
6850 else if (TARGET_POWER)
6852 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6859 (define_insn "*ashldi3_internal1"
6860 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6861 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6862 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6866 (define_insn "*ashldi3_internal2"
6867 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6868 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6869 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6871 (clobber (match_scratch:DI 3 "=r,r"))]
6876 [(set_attr "type" "delayed_compare")
6877 (set_attr "length" "4,8")])
6880 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6881 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6882 (match_operand:SI 2 "reg_or_cint_operand" ""))
6884 (clobber (match_scratch:DI 3 ""))]
6885 "TARGET_POWERPC64 && reload_completed"
6887 (ashift:DI (match_dup 1) (match_dup 2)))
6889 (compare:CC (match_dup 3)
6893 (define_insn "*ashldi3_internal3"
6894 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6895 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6896 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6898 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6899 (ashift:DI (match_dup 1) (match_dup 2)))]
6904 [(set_attr "type" "delayed_compare")
6905 (set_attr "length" "4,8")])
6908 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6909 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6910 (match_operand:SI 2 "reg_or_cint_operand" ""))
6912 (set (match_operand:DI 0 "gpc_reg_operand" "")
6913 (ashift:DI (match_dup 1) (match_dup 2)))]
6914 "TARGET_POWERPC64 && reload_completed"
6916 (ashift:DI (match_dup 1) (match_dup 2)))
6918 (compare:CC (match_dup 0)
6922 (define_insn "*ashldi3_internal4"
6923 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6924 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6925 (match_operand:SI 2 "const_int_operand" "i"))
6926 (match_operand:DI 3 "const_int_operand" "n")))]
6927 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6928 "rldic %0,%1,%H2,%W3")
6930 (define_insn "ashldi3_internal5"
6931 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6933 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6934 (match_operand:SI 2 "const_int_operand" "i,i"))
6935 (match_operand:DI 3 "const_int_operand" "n,n"))
6937 (clobber (match_scratch:DI 4 "=r,r"))]
6938 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6940 rldic. %4,%1,%H2,%W3
6942 [(set_attr "type" "delayed_compare")
6943 (set_attr "length" "4,8")])
6946 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6948 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6949 (match_operand:SI 2 "const_int_operand" ""))
6950 (match_operand:DI 3 "const_int_operand" ""))
6952 (clobber (match_scratch:DI 4 ""))]
6953 "TARGET_POWERPC64 && reload_completed
6954 && includes_rldic_lshift_p (operands[2], operands[3])"
6956 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6959 (compare:CC (match_dup 4)
6963 (define_insn "*ashldi3_internal6"
6964 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6966 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6967 (match_operand:SI 2 "const_int_operand" "i,i"))
6968 (match_operand:DI 3 "const_int_operand" "n,n"))
6970 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6971 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6972 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6974 rldic. %0,%1,%H2,%W3
6976 [(set_attr "type" "delayed_compare")
6977 (set_attr "length" "4,8")])
6980 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6982 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6983 (match_operand:SI 2 "const_int_operand" ""))
6984 (match_operand:DI 3 "const_int_operand" ""))
6986 (set (match_operand:DI 0 "gpc_reg_operand" "")
6987 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6988 "TARGET_POWERPC64 && reload_completed
6989 && includes_rldic_lshift_p (operands[2], operands[3])"
6991 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6994 (compare:CC (match_dup 0)
6998 (define_insn "*ashldi3_internal7"
6999 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7000 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7001 (match_operand:SI 2 "const_int_operand" "i"))
7002 (match_operand:DI 3 "mask64_operand" "n")))]
7003 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7004 "rldicr %0,%1,%H2,%S3")
7006 (define_insn "ashldi3_internal8"
7007 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7009 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7010 (match_operand:SI 2 "const_int_operand" "i,i"))
7011 (match_operand:DI 3 "mask64_operand" "n,n"))
7013 (clobber (match_scratch:DI 4 "=r,r"))]
7014 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7016 rldicr. %4,%1,%H2,%S3
7018 [(set_attr "type" "delayed_compare")
7019 (set_attr "length" "4,8")])
7022 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7024 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7025 (match_operand:SI 2 "const_int_operand" ""))
7026 (match_operand:DI 3 "mask64_operand" ""))
7028 (clobber (match_scratch:DI 4 ""))]
7029 "TARGET_POWERPC64 && reload_completed
7030 && includes_rldicr_lshift_p (operands[2], operands[3])"
7032 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7035 (compare:CC (match_dup 4)
7039 (define_insn "*ashldi3_internal9"
7040 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7042 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7043 (match_operand:SI 2 "const_int_operand" "i,i"))
7044 (match_operand:DI 3 "mask64_operand" "n,n"))
7046 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7047 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7048 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7050 rldicr. %0,%1,%H2,%S3
7052 [(set_attr "type" "delayed_compare")
7053 (set_attr "length" "4,8")])
7056 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7058 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7059 (match_operand:SI 2 "const_int_operand" ""))
7060 (match_operand:DI 3 "mask64_operand" ""))
7062 (set (match_operand:DI 0 "gpc_reg_operand" "")
7063 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7064 "TARGET_POWERPC64 && reload_completed
7065 && includes_rldicr_lshift_p (operands[2], operands[3])"
7067 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7070 (compare:CC (match_dup 0)
7074 (define_expand "lshrdi3"
7075 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7076 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7077 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7078 "TARGET_POWERPC64 || TARGET_POWER"
7081 if (TARGET_POWERPC64)
7083 else if (TARGET_POWER)
7085 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7092 (define_insn "*lshrdi3_internal1"
7093 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7094 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7095 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7099 (define_insn "*lshrdi3_internal2"
7100 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7101 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7102 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7104 (clobber (match_scratch:DI 3 "=r,r"))]
7109 [(set_attr "type" "delayed_compare")
7110 (set_attr "length" "4,8")])
7113 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7114 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7115 (match_operand:SI 2 "reg_or_cint_operand" ""))
7117 (clobber (match_scratch:DI 3 ""))]
7118 "TARGET_POWERPC64 && reload_completed"
7120 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7122 (compare:CC (match_dup 3)
7126 (define_insn "*lshrdi3_internal3"
7127 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7128 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7129 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7131 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7132 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7137 [(set_attr "type" "delayed_compare")
7138 (set_attr "length" "4,8")])
7141 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7142 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7143 (match_operand:SI 2 "reg_or_cint_operand" ""))
7145 (set (match_operand:DI 0 "gpc_reg_operand" "")
7146 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7147 "TARGET_POWERPC64 && reload_completed"
7149 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7151 (compare:CC (match_dup 0)
7155 (define_expand "ashrdi3"
7156 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7157 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7158 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7162 if (TARGET_POWERPC64)
7164 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7166 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7169 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7170 && WORDS_BIG_ENDIAN)
7172 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7179 (define_insn "*ashrdi3_internal1"
7180 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7181 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7182 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7184 "srad%I2 %0,%1,%H2")
7186 (define_insn "*ashrdi3_internal2"
7187 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7188 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7189 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7191 (clobber (match_scratch:DI 3 "=r,r"))]
7196 [(set_attr "type" "delayed_compare")
7197 (set_attr "length" "4,8")])
7200 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7201 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7202 (match_operand:SI 2 "reg_or_cint_operand" ""))
7204 (clobber (match_scratch:DI 3 ""))]
7205 "TARGET_POWERPC64 && reload_completed"
7207 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7209 (compare:CC (match_dup 3)
7213 (define_insn "*ashrdi3_internal3"
7214 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7215 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7216 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7218 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7219 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7224 [(set_attr "type" "delayed_compare")
7225 (set_attr "length" "4,8")])
7228 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7229 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7230 (match_operand:SI 2 "reg_or_cint_operand" ""))
7232 (set (match_operand:DI 0 "gpc_reg_operand" "")
7233 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7234 "TARGET_POWERPC64 && reload_completed"
7236 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7238 (compare:CC (match_dup 0)
7242 (define_insn "anddi3"
7243 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7244 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7245 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7246 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7250 rldic%B2 %0,%1,0,%S2
7251 rlwinm %0,%1,0,%m2,%M2
7255 [(set_attr "type" "*,*,*,compare,compare,*")
7256 (set_attr "length" "4,4,4,4,4,8")])
7259 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7260 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7261 (match_operand:DI 2 "mask64_2_operand" "")))
7262 (clobber (match_scratch:CC 3 ""))]
7264 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7265 && !mask64_operand (operands[2], DImode)"
7267 (and:DI (rotate:DI (match_dup 1)
7271 (and:DI (rotate:DI (match_dup 0)
7275 build_mask64_2_operands (operands[2], &operands[4]);
7278 (define_insn "*anddi3_internal2"
7279 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7280 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7281 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7283 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
7284 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7288 rldic%B2. %3,%1,0,%S2
7297 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7298 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7301 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7302 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7303 (match_operand:DI 2 "and64_operand" ""))
7305 (clobber (match_scratch:DI 3 ""))
7306 (clobber (match_scratch:CC 4 ""))]
7307 "TARGET_POWERPC64 && reload_completed"
7308 [(parallel [(set (match_dup 3)
7309 (and:DI (match_dup 1)
7311 (clobber (match_dup 4))])
7313 (compare:CC (match_dup 3)
7318 [(set (match_operand:CC 0 "cc_reg_operand" "")
7319 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7320 (match_operand:DI 2 "mask64_2_operand" ""))
7322 (clobber (match_scratch:DI 3 ""))
7323 (clobber (match_scratch:CC 4 ""))]
7324 "TARGET_POWERPC64 && reload_completed
7325 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7326 && !mask64_operand (operands[2], DImode)"
7328 (and:DI (rotate:DI (match_dup 1)
7331 (parallel [(set (match_dup 0)
7332 (compare:CC (and:DI (rotate:DI (match_dup 3)
7336 (clobber (match_dup 3))])]
7339 build_mask64_2_operands (operands[2], &operands[5]);
7342 (define_insn "*anddi3_internal3"
7343 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7344 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7345 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7347 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
7348 (and:DI (match_dup 1) (match_dup 2)))
7349 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7353 rldic%B2. %0,%1,0,%S2
7362 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7363 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7366 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7367 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7368 (match_operand:DI 2 "and64_operand" ""))
7370 (set (match_operand:DI 0 "gpc_reg_operand" "")
7371 (and:DI (match_dup 1) (match_dup 2)))
7372 (clobber (match_scratch:CC 4 ""))]
7373 "TARGET_POWERPC64 && reload_completed"
7374 [(parallel [(set (match_dup 0)
7375 (and:DI (match_dup 1) (match_dup 2)))
7376 (clobber (match_dup 4))])
7378 (compare:CC (match_dup 0)
7383 [(set (match_operand:CC 3 "cc_reg_operand" "")
7384 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7385 (match_operand:DI 2 "mask64_2_operand" ""))
7387 (set (match_operand:DI 0 "gpc_reg_operand" "")
7388 (and:DI (match_dup 1) (match_dup 2)))
7389 (clobber (match_scratch:CC 4 ""))]
7390 "TARGET_POWERPC64 && reload_completed
7391 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7392 && !mask64_operand (operands[2], DImode)"
7394 (and:DI (rotate:DI (match_dup 1)
7397 (parallel [(set (match_dup 3)
7398 (compare:CC (and:DI (rotate:DI (match_dup 0)
7403 (and:DI (rotate:DI (match_dup 0)
7408 build_mask64_2_operands (operands[2], &operands[5]);
7411 (define_expand "iordi3"
7412 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7413 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7414 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7418 if (non_logical_cint_operand (operands[2], DImode))
7420 HOST_WIDE_INT value;
7421 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7422 ? operands[0] : gen_reg_rtx (DImode));
7424 if (GET_CODE (operands[2]) == CONST_INT)
7426 value = INTVAL (operands[2]);
7427 emit_insn (gen_iordi3 (tmp, operands[1],
7428 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7432 value = CONST_DOUBLE_LOW (operands[2]);
7433 emit_insn (gen_iordi3 (tmp, operands[1],
7434 immed_double_const (value
7435 & (~ (HOST_WIDE_INT) 0xffff),
7439 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7444 (define_expand "xordi3"
7445 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7446 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7447 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7451 if (non_logical_cint_operand (operands[2], DImode))
7453 HOST_WIDE_INT value;
7454 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7455 ? operands[0] : gen_reg_rtx (DImode));
7457 if (GET_CODE (operands[2]) == CONST_INT)
7459 value = INTVAL (operands[2]);
7460 emit_insn (gen_xordi3 (tmp, operands[1],
7461 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7465 value = CONST_DOUBLE_LOW (operands[2]);
7466 emit_insn (gen_xordi3 (tmp, operands[1],
7467 immed_double_const (value
7468 & (~ (HOST_WIDE_INT) 0xffff),
7472 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7477 (define_insn "*booldi3_internal1"
7478 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7479 (match_operator:DI 3 "boolean_or_operator"
7480 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7481 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7488 (define_insn "*booldi3_internal2"
7489 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7490 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7491 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7492 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7494 (clobber (match_scratch:DI 3 "=r,r"))]
7499 [(set_attr "type" "compare")
7500 (set_attr "length" "4,8")])
7503 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7504 (compare:CC (match_operator:DI 4 "boolean_operator"
7505 [(match_operand:DI 1 "gpc_reg_operand" "")
7506 (match_operand:DI 2 "gpc_reg_operand" "")])
7508 (clobber (match_scratch:DI 3 ""))]
7509 "TARGET_POWERPC64 && reload_completed"
7510 [(set (match_dup 3) (match_dup 4))
7512 (compare:CC (match_dup 3)
7516 (define_insn "*booldi3_internal3"
7517 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7518 (compare:CC (match_operator:DI 4 "boolean_operator"
7519 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7520 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7522 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7528 [(set_attr "type" "compare")
7529 (set_attr "length" "4,8")])
7532 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7533 (compare:CC (match_operator:DI 4 "boolean_operator"
7534 [(match_operand:DI 1 "gpc_reg_operand" "")
7535 (match_operand:DI 2 "gpc_reg_operand" "")])
7537 (set (match_operand:DI 0 "gpc_reg_operand" "")
7539 "TARGET_POWERPC64 && reload_completed"
7540 [(set (match_dup 0) (match_dup 4))
7542 (compare:CC (match_dup 0)
7546 ;; Split a logical operation that we can't do in one insn into two insns,
7547 ;; each of which does one 16-bit part. This is used by combine.
7550 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7551 (match_operator:DI 3 "boolean_or_operator"
7552 [(match_operand:DI 1 "gpc_reg_operand" "")
7553 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7555 [(set (match_dup 0) (match_dup 4))
7556 (set (match_dup 0) (match_dup 5))]
7561 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7563 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7564 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7566 i4 = GEN_INT (value & 0xffff);
7570 i3 = GEN_INT (INTVAL (operands[2])
7571 & (~ (HOST_WIDE_INT) 0xffff));
7572 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7574 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7576 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7580 (define_insn "*boolcdi3_internal1"
7581 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7582 (match_operator:DI 3 "boolean_operator"
7583 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7584 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7588 (define_insn "*boolcdi3_internal2"
7589 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7590 (compare:CC (match_operator:DI 4 "boolean_operator"
7591 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7592 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7594 (clobber (match_scratch:DI 3 "=r,r"))]
7599 [(set_attr "type" "compare")
7600 (set_attr "length" "4,8")])
7603 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7604 (compare:CC (match_operator:DI 4 "boolean_operator"
7605 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7606 (match_operand:DI 2 "gpc_reg_operand" "")])
7608 (clobber (match_scratch:DI 3 ""))]
7609 "TARGET_POWERPC64 && reload_completed"
7610 [(set (match_dup 3) (match_dup 4))
7612 (compare:CC (match_dup 3)
7616 (define_insn "*boolcdi3_internal3"
7617 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7618 (compare:CC (match_operator:DI 4 "boolean_operator"
7619 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7620 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7622 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7628 [(set_attr "type" "compare")
7629 (set_attr "length" "4,8")])
7632 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7633 (compare:CC (match_operator:DI 4 "boolean_operator"
7634 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7635 (match_operand:DI 2 "gpc_reg_operand" "")])
7637 (set (match_operand:DI 0 "gpc_reg_operand" "")
7639 "TARGET_POWERPC64 && reload_completed"
7640 [(set (match_dup 0) (match_dup 4))
7642 (compare:CC (match_dup 0)
7646 (define_insn "*boolccdi3_internal1"
7647 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7648 (match_operator:DI 3 "boolean_operator"
7649 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7650 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7654 (define_insn "*boolccdi3_internal2"
7655 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7656 (compare:CC (match_operator:DI 4 "boolean_operator"
7657 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7658 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7660 (clobber (match_scratch:DI 3 "=r,r"))]
7665 [(set_attr "type" "compare")
7666 (set_attr "length" "4,8")])
7669 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7670 (compare:CC (match_operator:DI 4 "boolean_operator"
7671 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7672 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7674 (clobber (match_scratch:DI 3 ""))]
7675 "TARGET_POWERPC64 && reload_completed"
7676 [(set (match_dup 3) (match_dup 4))
7678 (compare:CC (match_dup 3)
7682 (define_insn "*boolccdi3_internal3"
7683 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7684 (compare:CC (match_operator:DI 4 "boolean_operator"
7685 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7686 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7688 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7694 [(set_attr "type" "compare")
7695 (set_attr "length" "4,8")])
7698 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7699 (compare:CC (match_operator:DI 4 "boolean_operator"
7700 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7701 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7703 (set (match_operand:DI 0 "gpc_reg_operand" "")
7705 "TARGET_POWERPC64 && reload_completed"
7706 [(set (match_dup 0) (match_dup 4))
7708 (compare:CC (match_dup 0)
7712 ;; Now define ways of moving data around.
7714 ;; Elf specific ways of loading addresses for non-PIC code.
7715 ;; The output of this could be r0, but we make a very strong
7716 ;; preference for a base register because it will usually
7718 (define_insn "elf_high"
7719 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7720 (high:SI (match_operand 1 "" "")))]
7721 "TARGET_ELF && ! TARGET_64BIT"
7722 "{liu|lis} %0,%1@ha")
7724 (define_insn "elf_low"
7725 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7726 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7727 (match_operand 2 "" "")))]
7728 "TARGET_ELF && ! TARGET_64BIT"
7730 {cal|la} %0,%2@l(%1)
7731 {ai|addic} %0,%1,%K2")
7734 ;; Set up a register with a value from the GOT table
7736 (define_expand "movsi_got"
7737 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7738 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7739 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7740 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7743 if (GET_CODE (operands[1]) == CONST)
7745 rtx offset = const0_rtx;
7746 HOST_WIDE_INT value;
7748 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7749 value = INTVAL (offset);
7752 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7753 emit_insn (gen_movsi_got (tmp, operands[1]));
7754 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7759 operands[2] = rs6000_got_register (operands[1]);
7762 (define_insn "*movsi_got_internal"
7763 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7764 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7765 (match_operand:SI 2 "gpc_reg_operand" "b")]
7767 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7768 "{l|lwz} %0,%a1@got(%2)"
7769 [(set_attr "type" "load")])
7771 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7772 ;; didn't get allocated to a hard register.
7774 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7775 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7776 (match_operand:SI 2 "memory_operand" "")]
7778 "DEFAULT_ABI == ABI_V4
7780 && (reload_in_progress || reload_completed)"
7781 [(set (match_dup 0) (match_dup 2))
7782 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7786 ;; For SI, we special-case integers that can't be loaded in one insn. We
7787 ;; do the load 16-bits at a time. We could do this by loading from memory,
7788 ;; and this is even supposed to be faster, but it is simpler not to get
7789 ;; integers in the TOC.
7790 (define_expand "movsi"
7791 [(set (match_operand:SI 0 "general_operand" "")
7792 (match_operand:SI 1 "any_operand" ""))]
7794 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7796 (define_insn "movsi_low"
7797 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7798 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7799 (match_operand 2 "" ""))))]
7800 "TARGET_MACHO && ! TARGET_64BIT"
7801 "{l|lwz} %0,lo16(%2)(%1)"
7802 [(set_attr "type" "load")
7803 (set_attr "length" "4")])
7805 (define_insn "*movsi_internal1"
7806 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7807 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7808 "gpc_reg_operand (operands[0], SImode)
7809 || gpc_reg_operand (operands[1], SImode)"
7813 {l%U1%X1|lwz%U1%X1} %0,%1
7814 {st%U0%X0|stw%U0%X0} %1,%0
7824 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7825 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7827 ;; Split a load of a large constant into the appropriate two-insn
7831 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7832 (match_operand:SI 1 "const_int_operand" ""))]
7833 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7834 && (INTVAL (operands[1]) & 0xffff) != 0"
7838 (ior:SI (match_dup 0)
7841 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7843 if (tem == operands[0])
7849 (define_insn "*movsi_internal2"
7850 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7851 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r")
7853 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7856 {cmpi|cmpwi} %2,%0,0
7859 [(set_attr "type" "cmp,compare,cmp")
7860 (set_attr "length" "4,4,8")])
7863 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7864 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7866 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7867 "TARGET_32BIT && reload_completed"
7868 [(set (match_dup 0) (match_dup 1))
7870 (compare:CC (match_dup 0)
7874 (define_expand "movhi"
7875 [(set (match_operand:HI 0 "general_operand" "")
7876 (match_operand:HI 1 "any_operand" ""))]
7878 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7880 (define_insn "*movhi_internal"
7881 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7882 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7883 "gpc_reg_operand (operands[0], HImode)
7884 || gpc_reg_operand (operands[1], HImode)"
7894 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7896 (define_expand "movqi"
7897 [(set (match_operand:QI 0 "general_operand" "")
7898 (match_operand:QI 1 "any_operand" ""))]
7900 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7902 (define_insn "*movqi_internal"
7903 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7904 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7905 "gpc_reg_operand (operands[0], QImode)
7906 || gpc_reg_operand (operands[1], QImode)"
7916 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7918 ;; Here is how to move condition codes around. When we store CC data in
7919 ;; an integer register or memory, we store just the high-order 4 bits.
7920 ;; This lets us not shift in the most common case of CR0.
7921 (define_expand "movcc"
7922 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7923 (match_operand:CC 1 "nonimmediate_operand" ""))]
7927 (define_insn "*movcc_internal1"
7928 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7929 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7930 "register_operand (operands[0], CCmode)
7931 || register_operand (operands[1], CCmode)"
7935 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7937 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7942 {l%U1%X1|lwz%U1%X1} %0,%1
7943 {st%U0%U1|stw%U0%U1} %1,%0"
7945 (cond [(eq_attr "alternative" "0")
7946 (const_string "cr_logical")
7947 (eq_attr "alternative" "1,2")
7948 (const_string "mtcr")
7949 (eq_attr "alternative" "5,7")
7950 (const_string "integer")
7951 (eq_attr "alternative" "6")
7952 (const_string "mfjmpr")
7953 (eq_attr "alternative" "8")
7954 (const_string "mtjmpr")
7955 (eq_attr "alternative" "9")
7956 (const_string "load")
7957 (eq_attr "alternative" "10")
7958 (const_string "store")
7959 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7960 (const_string "mfcrf")
7962 (const_string "mfcr")))
7963 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7965 ;; For floating-point, we normally deal with the floating-point registers
7966 ;; unless -msoft-float is used. The sole exception is that parameter passing
7967 ;; can produce floating-point values in fixed-point registers. Unless the
7968 ;; value is a simple constant or already in memory, we deal with this by
7969 ;; allocating memory and copying the value explicitly via that memory location.
7970 (define_expand "movsf"
7971 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7972 (match_operand:SF 1 "any_operand" ""))]
7974 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7977 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7978 (match_operand:SF 1 "const_double_operand" ""))]
7980 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7981 || (GET_CODE (operands[0]) == SUBREG
7982 && GET_CODE (SUBREG_REG (operands[0])) == REG
7983 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7984 [(set (match_dup 2) (match_dup 3))]
7990 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7991 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7993 if (! TARGET_POWERPC64)
7994 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7996 operands[2] = gen_lowpart (SImode, operands[0]);
7998 operands[3] = gen_int_mode (l, SImode);
8001 (define_insn "*movsf_hardfloat"
8002 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
8003 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8004 "(gpc_reg_operand (operands[0], SFmode)
8005 || gpc_reg_operand (operands[1], SFmode))
8006 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
8009 {l%U1%X1|lwz%U1%X1} %0,%1
8010 {st%U0%X0|stw%U0%X0} %1,%0
8020 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
8021 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8023 (define_insn "*movsf_softfloat"
8024 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8025 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8026 "(gpc_reg_operand (operands[0], SFmode)
8027 || gpc_reg_operand (operands[1], SFmode))
8028 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8034 {l%U1%X1|lwz%U1%X1} %0,%1
8035 {st%U0%X0|stw%U0%X0} %1,%0
8042 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
8043 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8046 (define_expand "movdf"
8047 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8048 (match_operand:DF 1 "any_operand" ""))]
8050 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8053 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8054 (match_operand:DF 1 "const_int_operand" ""))]
8055 "! TARGET_POWERPC64 && reload_completed
8056 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8057 || (GET_CODE (operands[0]) == SUBREG
8058 && GET_CODE (SUBREG_REG (operands[0])) == REG
8059 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8060 [(set (match_dup 2) (match_dup 4))
8061 (set (match_dup 3) (match_dup 1))]
8064 int endian = (WORDS_BIG_ENDIAN == 0);
8065 HOST_WIDE_INT value = INTVAL (operands[1]);
8067 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8068 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8069 #if HOST_BITS_PER_WIDE_INT == 32
8070 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8072 operands[4] = GEN_INT (value >> 32);
8073 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8078 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8079 (match_operand:DF 1 "const_double_operand" ""))]
8080 "! TARGET_POWERPC64 && reload_completed
8081 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8082 || (GET_CODE (operands[0]) == SUBREG
8083 && GET_CODE (SUBREG_REG (operands[0])) == REG
8084 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8085 [(set (match_dup 2) (match_dup 4))
8086 (set (match_dup 3) (match_dup 5))]
8089 int endian = (WORDS_BIG_ENDIAN == 0);
8093 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8094 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8096 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8097 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8098 operands[4] = gen_int_mode (l[endian], SImode);
8099 operands[5] = gen_int_mode (l[1 - endian], SImode);
8103 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8104 (match_operand:DF 1 "easy_fp_constant" ""))]
8105 "TARGET_POWERPC64 && reload_completed
8106 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8107 || (GET_CODE (operands[0]) == SUBREG
8108 && GET_CODE (SUBREG_REG (operands[0])) == REG
8109 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8110 [(set (match_dup 2) (match_dup 3))]
8113 int endian = (WORDS_BIG_ENDIAN == 0);
8116 #if HOST_BITS_PER_WIDE_INT >= 64
8120 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8121 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8123 operands[2] = gen_lowpart (DImode, operands[0]);
8124 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8125 #if HOST_BITS_PER_WIDE_INT >= 64
8126 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8127 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8129 operands[3] = gen_int_mode (val, DImode);
8131 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8135 ;; Don't have reload use general registers to load a constant. First,
8136 ;; it might not work if the output operand is the equivalent of
8137 ;; a non-offsettable memref, but also it is less efficient than loading
8138 ;; the constant into an FP register, since it will probably be used there.
8139 ;; The "??" is a kludge until we can figure out a more reasonable way
8140 ;; of handling these non-offsettable values.
8141 (define_insn "*movdf_hardfloat32"
8142 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8143 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8144 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8145 && (gpc_reg_operand (operands[0], DFmode)
8146 || gpc_reg_operand (operands[1], DFmode))"
8149 switch (which_alternative)
8154 /* We normally copy the low-numbered register first. However, if
8155 the first register operand 0 is the same as the second register
8156 of operand 1, we must copy in the opposite order. */
8157 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8158 return \"mr %L0,%L1\;mr %0,%1\";
8160 return \"mr %0,%1\;mr %L0,%L1\";
8162 if (GET_CODE (operands[1]) == MEM
8163 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
8164 reload_completed || reload_in_progress)
8165 || GET_CODE (XEXP (operands[1], 0)) == REG
8166 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8167 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8168 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
8170 /* If the low-address word is used in the address, we must load
8171 it last. Otherwise, load it first. Note that we cannot have
8172 auto-increment in that case since the address register is
8173 known to be dead. */
8174 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8176 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8178 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8184 addreg = find_addr_reg (XEXP (operands[1], 0));
8185 if (refers_to_regno_p (REGNO (operands[0]),
8186 REGNO (operands[0]) + 1,
8189 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8190 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8191 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8192 return \"{lx|lwzx} %0,%1\";
8196 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8197 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8198 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8199 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8204 if (GET_CODE (operands[0]) == MEM
8205 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
8206 reload_completed || reload_in_progress)
8207 || GET_CODE (XEXP (operands[0], 0)) == REG
8208 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8209 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8210 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
8211 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8216 addreg = find_addr_reg (XEXP (operands[0], 0));
8217 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8218 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8219 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8220 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8224 return \"fmr %0,%1\";
8226 return \"lfd%U1%X1 %0,%1\";
8228 return \"stfd%U0%X0 %1,%0\";
8235 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8236 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8238 (define_insn "*movdf_softfloat32"
8239 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8240 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8241 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8242 && (gpc_reg_operand (operands[0], DFmode)
8243 || gpc_reg_operand (operands[1], DFmode))"
8246 switch (which_alternative)
8251 /* We normally copy the low-numbered register first. However, if
8252 the first register operand 0 is the same as the second register of
8253 operand 1, we must copy in the opposite order. */
8254 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8255 return \"mr %L0,%L1\;mr %0,%1\";
8257 return \"mr %0,%1\;mr %L0,%L1\";
8259 /* If the low-address word is used in the address, we must load
8260 it last. Otherwise, load it first. Note that we cannot have
8261 auto-increment in that case since the address register is
8262 known to be dead. */
8263 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8265 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8267 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8269 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8276 [(set_attr "type" "two,load,store,*,*,*")
8277 (set_attr "length" "8,8,8,8,12,16")])
8279 ; ld/std require word-aligned displacements -> 'Y' constraint.
8280 ; List Y->r and r->Y before r->r for reload.
8281 (define_insn "*movdf_hardfloat64"
8282 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
8283 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8284 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8285 && (gpc_reg_operand (operands[0], DFmode)
8286 || gpc_reg_operand (operands[1], DFmode))"
8300 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
8301 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8303 (define_insn "*movdf_softfloat64"
8304 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8305 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8306 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8307 && (gpc_reg_operand (operands[0], DFmode)
8308 || gpc_reg_operand (operands[1], DFmode))"
8319 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
8320 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8322 (define_expand "movtf"
8323 [(set (match_operand:TF 0 "general_operand" "")
8324 (match_operand:TF 1 "any_operand" ""))]
8325 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8326 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8327 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8329 ; It's important to list the o->f and f->o moves before f->f because
8330 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8331 ; which doesn't make progress. Likewise r->Y must be before r->r.
8332 (define_insn_and_split "*movtf_internal"
8333 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8334 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8335 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8336 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8337 && (gpc_reg_operand (operands[0], TFmode)
8338 || gpc_reg_operand (operands[1], TFmode))"
8340 "&& reload_completed"
8342 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8343 [(set_attr "length" "8,8,8,20,20,16")])
8345 (define_expand "extenddftf2"
8346 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8347 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8348 (use (match_dup 2))])]
8349 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8350 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8352 operands[2] = CONST0_RTX (DFmode);
8355 (define_insn_and_split "*extenddftf2_internal"
8356 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8357 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8358 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8359 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8360 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8362 "&& reload_completed"
8365 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8366 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8367 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8369 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8374 (define_expand "extendsftf2"
8375 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8376 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8377 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8378 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8380 rtx tmp = gen_reg_rtx (DFmode);
8381 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8382 emit_insn (gen_extenddftf2 (operands[0], tmp));
8386 (define_expand "trunctfdf2"
8387 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8388 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8389 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8390 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8393 (define_insn_and_split "trunctfdf2_internal1"
8394 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8395 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8396 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
8397 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8401 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8404 emit_note (NOTE_INSN_DELETED);
8407 [(set_attr "type" "fp")])
8409 (define_insn "trunctfdf2_internal2"
8410 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8411 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8412 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
8413 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8415 [(set_attr "type" "fp")])
8417 (define_insn_and_split "trunctfsf2"
8418 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8419 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8420 (clobber (match_scratch:DF 2 "=f"))]
8421 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8422 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8424 "&& reload_completed"
8426 (float_truncate:DF (match_dup 1)))
8428 (float_truncate:SF (match_dup 2)))]
8431 (define_expand "floatsitf2"
8432 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8433 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
8434 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8435 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8437 rtx tmp = gen_reg_rtx (DFmode);
8438 expand_float (tmp, operands[1], false);
8439 emit_insn (gen_extenddftf2 (operands[0], tmp));
8443 ; fadd, but rounding towards zero.
8444 ; This is probably not the optimal code sequence.
8445 (define_insn "fix_trunc_helper"
8446 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8447 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8448 UNSPEC_FIX_TRUNC_TF))
8449 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8450 "TARGET_HARD_FLOAT && TARGET_FPRS"
8451 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8452 [(set_attr "type" "fp")
8453 (set_attr "length" "20")])
8455 (define_expand "fix_trunctfsi2"
8456 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8457 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8458 (clobber (match_dup 2))
8459 (clobber (match_dup 3))
8460 (clobber (match_dup 4))
8461 (clobber (match_dup 5))])]
8462 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8463 && (TARGET_POWER2 || TARGET_POWERPC)
8464 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8466 operands[2] = gen_reg_rtx (DFmode);
8467 operands[3] = gen_reg_rtx (DFmode);
8468 operands[4] = gen_reg_rtx (DImode);
8469 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8472 (define_insn_and_split "*fix_trunctfsi2_internal"
8473 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8474 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8475 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8476 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8477 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8478 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8479 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8480 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8482 "&& reload_completed"
8486 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8488 if (GET_CODE (operands[5]) != MEM)
8490 lowword = XEXP (operands[5], 0);
8491 if (WORDS_BIG_ENDIAN)
8492 lowword = plus_constant (lowword, 4);
8494 emit_insn (gen_fctiwz (operands[4], operands[2]));
8495 emit_move_insn (operands[5], operands[4]);
8496 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
8500 (define_insn "negtf2"
8501 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8502 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8503 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8504 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8507 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8508 return \"fneg %L0,%L1\;fneg %0,%1\";
8510 return \"fneg %0,%1\;fneg %L0,%L1\";
8512 [(set_attr "type" "fp")
8513 (set_attr "length" "8")])
8515 (define_expand "abstf2"
8516 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8517 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8518 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8519 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8522 rtx label = gen_label_rtx ();
8523 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8528 (define_expand "abstf2_internal"
8529 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8530 (match_operand:TF 1 "gpc_reg_operand" "f"))
8531 (set (match_dup 3) (match_dup 5))
8532 (set (match_dup 5) (abs:DF (match_dup 5)))
8533 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8534 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8535 (label_ref (match_operand 2 "" ""))
8537 (set (match_dup 6) (neg:DF (match_dup 6)))]
8538 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8539 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8542 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8543 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8544 operands[3] = gen_reg_rtx (DFmode);
8545 operands[4] = gen_reg_rtx (CCFPmode);
8546 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8547 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8550 ;; Next come the multi-word integer load and store and the load and store
8552 (define_expand "movdi"
8553 [(set (match_operand:DI 0 "general_operand" "")
8554 (match_operand:DI 1 "any_operand" ""))]
8556 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
8558 ; List r->r after r->"o<>", otherwise reload will try to reload a
8559 ; non-offsettable address by using r->r which won't make progress.
8560 (define_insn "*movdi_internal32"
8561 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8562 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8564 && (gpc_reg_operand (operands[0], DImode)
8565 || gpc_reg_operand (operands[1], DImode))"
8574 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8577 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8578 (match_operand:DI 1 "const_int_operand" ""))]
8579 "! TARGET_POWERPC64 && reload_completed"
8580 [(set (match_dup 2) (match_dup 4))
8581 (set (match_dup 3) (match_dup 1))]
8584 HOST_WIDE_INT value = INTVAL (operands[1]);
8585 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8587 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8589 #if HOST_BITS_PER_WIDE_INT == 32
8590 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8592 operands[4] = GEN_INT (value >> 32);
8593 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8598 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8599 (match_operand:DI 1 "input_operand" ""))]
8600 "reload_completed && !TARGET_POWERPC64
8601 && gpr_or_gpr_p (operands[0], operands[1])"
8603 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8605 (define_insn "*movdi_internal64"
8606 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8607 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8609 && (gpc_reg_operand (operands[0], DImode)
8610 || gpc_reg_operand (operands[1], DImode))"
8625 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8626 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8628 ;; immediate value valid for a single instruction hiding in a const_double
8630 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8631 (match_operand:DI 1 "const_double_operand" "F"))]
8632 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8633 && GET_CODE (operands[1]) == CONST_DOUBLE
8634 && num_insns_constant (operands[1], DImode) == 1"
8637 return ((unsigned HOST_WIDE_INT)
8638 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8639 ? \"li %0,%1\" : \"lis %0,%v1\";
8642 ;; Generate all one-bits and clear left or right.
8643 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8645 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8646 (match_operand:DI 1 "mask64_operand" ""))]
8647 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8648 [(set (match_dup 0) (const_int -1))
8650 (and:DI (rotate:DI (match_dup 0)
8655 ;; Split a load of a large constant into the appropriate five-instruction
8656 ;; sequence. Handle anything in a constant number of insns.
8657 ;; When non-easy constants can go in the TOC, this should use
8658 ;; easy_fp_constant predicate.
8660 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8661 (match_operand:DI 1 "const_int_operand" ""))]
8662 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8663 [(set (match_dup 0) (match_dup 2))
8664 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8666 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8668 if (tem == operands[0])
8675 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8676 (match_operand:DI 1 "const_double_operand" ""))]
8677 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8678 [(set (match_dup 0) (match_dup 2))
8679 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8681 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8683 if (tem == operands[0])
8689 (define_insn "*movdi_internal2"
8690 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8691 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r")
8693 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8699 [(set_attr "type" "cmp,compare,cmp")
8700 (set_attr "length" "4,4,8")])
8703 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8704 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8706 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8707 "TARGET_POWERPC64 && reload_completed"
8708 [(set (match_dup 0) (match_dup 1))
8710 (compare:CC (match_dup 0)
8714 ;; TImode is similar, except that we usually want to compute the address into
8715 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8716 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8717 (define_expand "movti"
8718 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8719 (match_operand:TI 1 "general_operand" ""))
8720 (clobber (scratch:SI))])]
8722 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8724 ;; We say that MQ is clobbered in the last alternative because the first
8725 ;; alternative would never get used otherwise since it would need a reload
8726 ;; while the 2nd alternative would not. We put memory cases first so they
8727 ;; are preferred. Otherwise, we'd try to reload the output instead of
8728 ;; giving the SCRATCH mq.
8730 (define_insn "*movti_power"
8731 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8732 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8733 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8734 "TARGET_POWER && ! TARGET_POWERPC64
8735 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8738 switch (which_alternative)
8745 return \"{stsi|stswi} %1,%P0,16\";
8750 /* If the address is not used in the output, we can use lsi. Otherwise,
8751 fall through to generating four loads. */
8753 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8754 return \"{lsi|lswi} %0,%P1,16\";
8755 /* ... fall through ... */
8761 [(set_attr "type" "store,store,*,load,load,*")])
8763 (define_insn "*movti_string"
8764 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8765 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8766 "! TARGET_POWER && ! TARGET_POWERPC64
8767 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8770 switch (which_alternative)
8776 return \"{stsi|stswi} %1,%P0,16\";
8781 /* If the address is not used in the output, we can use lsi. Otherwise,
8782 fall through to generating four loads. */
8784 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8785 return \"{lsi|lswi} %0,%P1,16\";
8786 /* ... fall through ... */
8792 [(set_attr "type" "store,store,*,load,load,*")])
8794 (define_insn "*movti_ppc64"
8795 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8796 (match_operand:TI 1 "input_operand" "r,r,m"))]
8797 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8798 || gpc_reg_operand (operands[1], TImode))"
8800 [(set_attr "type" "*,load,store")])
8803 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8804 (match_operand:TI 1 "const_double_operand" ""))]
8806 [(set (match_dup 2) (match_dup 4))
8807 (set (match_dup 3) (match_dup 5))]
8810 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8812 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8814 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8816 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8817 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8819 else if (GET_CODE (operands[1]) == CONST_INT)
8821 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8822 operands[5] = operands[1];
8829 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8830 (match_operand:TI 1 "input_operand" ""))]
8832 && gpr_or_gpr_p (operands[0], operands[1])"
8834 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8836 (define_expand "load_multiple"
8837 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8838 (match_operand:SI 1 "" ""))
8839 (use (match_operand:SI 2 "" ""))])]
8840 "TARGET_STRING && !TARGET_POWERPC64"
8848 /* Support only loading a constant number of fixed-point registers from
8849 memory and only bother with this if more than two; the machine
8850 doesn't support more than eight. */
8851 if (GET_CODE (operands[2]) != CONST_INT
8852 || INTVAL (operands[2]) <= 2
8853 || INTVAL (operands[2]) > 8
8854 || GET_CODE (operands[1]) != MEM
8855 || GET_CODE (operands[0]) != REG
8856 || REGNO (operands[0]) >= 32)
8859 count = INTVAL (operands[2]);
8860 regno = REGNO (operands[0]);
8862 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8863 op1 = replace_equiv_address (operands[1],
8864 force_reg (SImode, XEXP (operands[1], 0)));
8866 for (i = 0; i < count; i++)
8867 XVECEXP (operands[3], 0, i)
8868 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8869 adjust_address_nv (op1, SImode, i * 4));
8872 (define_insn "*ldmsi8"
8873 [(match_parallel 0 "load_multiple_operation"
8874 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8875 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8876 (set (match_operand:SI 3 "gpc_reg_operand" "")
8877 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8878 (set (match_operand:SI 4 "gpc_reg_operand" "")
8879 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8880 (set (match_operand:SI 5 "gpc_reg_operand" "")
8881 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8882 (set (match_operand:SI 6 "gpc_reg_operand" "")
8883 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8884 (set (match_operand:SI 7 "gpc_reg_operand" "")
8885 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8886 (set (match_operand:SI 8 "gpc_reg_operand" "")
8887 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8888 (set (match_operand:SI 9 "gpc_reg_operand" "")
8889 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8890 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8892 { return rs6000_output_load_multiple (operands); }"
8893 [(set_attr "type" "load")
8894 (set_attr "length" "32")])
8896 (define_insn "*ldmsi7"
8897 [(match_parallel 0 "load_multiple_operation"
8898 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8899 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8900 (set (match_operand:SI 3 "gpc_reg_operand" "")
8901 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8902 (set (match_operand:SI 4 "gpc_reg_operand" "")
8903 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8904 (set (match_operand:SI 5 "gpc_reg_operand" "")
8905 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8906 (set (match_operand:SI 6 "gpc_reg_operand" "")
8907 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8908 (set (match_operand:SI 7 "gpc_reg_operand" "")
8909 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8910 (set (match_operand:SI 8 "gpc_reg_operand" "")
8911 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8912 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8914 { return rs6000_output_load_multiple (operands); }"
8915 [(set_attr "type" "load")
8916 (set_attr "length" "32")])
8918 (define_insn "*ldmsi6"
8919 [(match_parallel 0 "load_multiple_operation"
8920 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8921 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8922 (set (match_operand:SI 3 "gpc_reg_operand" "")
8923 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8924 (set (match_operand:SI 4 "gpc_reg_operand" "")
8925 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8926 (set (match_operand:SI 5 "gpc_reg_operand" "")
8927 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8928 (set (match_operand:SI 6 "gpc_reg_operand" "")
8929 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8930 (set (match_operand:SI 7 "gpc_reg_operand" "")
8931 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8932 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8934 { return rs6000_output_load_multiple (operands); }"
8935 [(set_attr "type" "load")
8936 (set_attr "length" "32")])
8938 (define_insn "*ldmsi5"
8939 [(match_parallel 0 "load_multiple_operation"
8940 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8941 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8942 (set (match_operand:SI 3 "gpc_reg_operand" "")
8943 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8944 (set (match_operand:SI 4 "gpc_reg_operand" "")
8945 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8946 (set (match_operand:SI 5 "gpc_reg_operand" "")
8947 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8948 (set (match_operand:SI 6 "gpc_reg_operand" "")
8949 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8950 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8952 { return rs6000_output_load_multiple (operands); }"
8953 [(set_attr "type" "load")
8954 (set_attr "length" "32")])
8956 (define_insn "*ldmsi4"
8957 [(match_parallel 0 "load_multiple_operation"
8958 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8959 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8960 (set (match_operand:SI 3 "gpc_reg_operand" "")
8961 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8962 (set (match_operand:SI 4 "gpc_reg_operand" "")
8963 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8964 (set (match_operand:SI 5 "gpc_reg_operand" "")
8965 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8966 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8968 { return rs6000_output_load_multiple (operands); }"
8969 [(set_attr "type" "load")
8970 (set_attr "length" "32")])
8972 (define_insn "*ldmsi3"
8973 [(match_parallel 0 "load_multiple_operation"
8974 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8975 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8976 (set (match_operand:SI 3 "gpc_reg_operand" "")
8977 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8978 (set (match_operand:SI 4 "gpc_reg_operand" "")
8979 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8980 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8982 { return rs6000_output_load_multiple (operands); }"
8983 [(set_attr "type" "load")
8984 (set_attr "length" "32")])
8986 (define_expand "store_multiple"
8987 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8988 (match_operand:SI 1 "" ""))
8989 (clobber (scratch:SI))
8990 (use (match_operand:SI 2 "" ""))])]
8991 "TARGET_STRING && !TARGET_POWERPC64"
9000 /* Support only storing a constant number of fixed-point registers to
9001 memory and only bother with this if more than two; the machine
9002 doesn't support more than eight. */
9003 if (GET_CODE (operands[2]) != CONST_INT
9004 || INTVAL (operands[2]) <= 2
9005 || INTVAL (operands[2]) > 8
9006 || GET_CODE (operands[0]) != MEM
9007 || GET_CODE (operands[1]) != REG
9008 || REGNO (operands[1]) >= 32)
9011 count = INTVAL (operands[2]);
9012 regno = REGNO (operands[1]);
9014 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9015 to = force_reg (SImode, XEXP (operands[0], 0));
9016 op0 = replace_equiv_address (operands[0], to);
9018 XVECEXP (operands[3], 0, 0)
9019 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9020 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9021 gen_rtx_SCRATCH (SImode));
9023 for (i = 1; i < count; i++)
9024 XVECEXP (operands[3], 0, i + 1)
9025 = gen_rtx_SET (VOIDmode,
9026 adjust_address_nv (op0, SImode, i * 4),
9027 gen_rtx_REG (SImode, regno + i));
9030 (define_insn "*store_multiple_power"
9031 [(match_parallel 0 "store_multiple_operation"
9032 [(set (match_operand:SI 1 "indirect_operand" "=Q")
9033 (match_operand:SI 2 "gpc_reg_operand" "r"))
9034 (clobber (match_scratch:SI 3 "=q"))])]
9035 "TARGET_STRING && TARGET_POWER"
9036 "{stsi|stswi} %2,%P1,%O0"
9037 [(set_attr "type" "store")])
9039 (define_insn "*stmsi8"
9040 [(match_parallel 0 "store_multiple_operation"
9041 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9042 (match_operand:SI 2 "gpc_reg_operand" "r"))
9043 (clobber (match_scratch:SI 3 "X"))
9044 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9045 (match_operand:SI 4 "gpc_reg_operand" "r"))
9046 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9047 (match_operand:SI 5 "gpc_reg_operand" "r"))
9048 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9049 (match_operand:SI 6 "gpc_reg_operand" "r"))
9050 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9051 (match_operand:SI 7 "gpc_reg_operand" "r"))
9052 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9053 (match_operand:SI 8 "gpc_reg_operand" "r"))
9054 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9055 (match_operand:SI 9 "gpc_reg_operand" "r"))
9056 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9057 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9058 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9059 "{stsi|stswi} %2,%1,%O0"
9060 [(set_attr "type" "store")])
9062 (define_insn "*stmsi7"
9063 [(match_parallel 0 "store_multiple_operation"
9064 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9065 (match_operand:SI 2 "gpc_reg_operand" "r"))
9066 (clobber (match_scratch:SI 3 "X"))
9067 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9068 (match_operand:SI 4 "gpc_reg_operand" "r"))
9069 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9070 (match_operand:SI 5 "gpc_reg_operand" "r"))
9071 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9072 (match_operand:SI 6 "gpc_reg_operand" "r"))
9073 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9074 (match_operand:SI 7 "gpc_reg_operand" "r"))
9075 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9076 (match_operand:SI 8 "gpc_reg_operand" "r"))
9077 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9078 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9079 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9080 "{stsi|stswi} %2,%1,%O0"
9081 [(set_attr "type" "store")])
9083 (define_insn "*stmsi6"
9084 [(match_parallel 0 "store_multiple_operation"
9085 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9086 (match_operand:SI 2 "gpc_reg_operand" "r"))
9087 (clobber (match_scratch:SI 3 "X"))
9088 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9089 (match_operand:SI 4 "gpc_reg_operand" "r"))
9090 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9091 (match_operand:SI 5 "gpc_reg_operand" "r"))
9092 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9093 (match_operand:SI 6 "gpc_reg_operand" "r"))
9094 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9095 (match_operand:SI 7 "gpc_reg_operand" "r"))
9096 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9097 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9098 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9099 "{stsi|stswi} %2,%1,%O0"
9100 [(set_attr "type" "store")])
9102 (define_insn "*stmsi5"
9103 [(match_parallel 0 "store_multiple_operation"
9104 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9105 (match_operand:SI 2 "gpc_reg_operand" "r"))
9106 (clobber (match_scratch:SI 3 "X"))
9107 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9108 (match_operand:SI 4 "gpc_reg_operand" "r"))
9109 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9110 (match_operand:SI 5 "gpc_reg_operand" "r"))
9111 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9112 (match_operand:SI 6 "gpc_reg_operand" "r"))
9113 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9114 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9115 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9116 "{stsi|stswi} %2,%1,%O0"
9117 [(set_attr "type" "store")])
9119 (define_insn "*stmsi4"
9120 [(match_parallel 0 "store_multiple_operation"
9121 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9122 (match_operand:SI 2 "gpc_reg_operand" "r"))
9123 (clobber (match_scratch:SI 3 "X"))
9124 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9125 (match_operand:SI 4 "gpc_reg_operand" "r"))
9126 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9127 (match_operand:SI 5 "gpc_reg_operand" "r"))
9128 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9129 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9130 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9131 "{stsi|stswi} %2,%1,%O0"
9132 [(set_attr "type" "store")])
9134 (define_insn "*stmsi3"
9135 [(match_parallel 0 "store_multiple_operation"
9136 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9137 (match_operand:SI 2 "gpc_reg_operand" "r"))
9138 (clobber (match_scratch:SI 3 "X"))
9139 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9140 (match_operand:SI 4 "gpc_reg_operand" "r"))
9141 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9142 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9143 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9144 "{stsi|stswi} %2,%1,%O0"
9145 [(set_attr "type" "store")])
9147 (define_expand "clrmemsi"
9148 [(parallel [(set (match_operand:BLK 0 "" "")
9150 (use (match_operand:SI 1 "" ""))
9151 (use (match_operand:SI 2 "" ""))])]
9155 if (expand_block_clear (operands))
9161 ;; String/block move insn.
9162 ;; Argument 0 is the destination
9163 ;; Argument 1 is the source
9164 ;; Argument 2 is the length
9165 ;; Argument 3 is the alignment
9167 (define_expand "movmemsi"
9168 [(parallel [(set (match_operand:BLK 0 "" "")
9169 (match_operand:BLK 1 "" ""))
9170 (use (match_operand:SI 2 "" ""))
9171 (use (match_operand:SI 3 "" ""))])]
9175 if (expand_block_move (operands))
9181 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9182 ;; register allocator doesn't have a clue about allocating 8 word registers.
9183 ;; rD/rS = r5 is preferred, efficient form.
9184 (define_expand "movmemsi_8reg"
9185 [(parallel [(set (match_operand 0 "" "")
9186 (match_operand 1 "" ""))
9187 (use (match_operand 2 "" ""))
9188 (use (match_operand 3 "" ""))
9189 (clobber (reg:SI 5))
9190 (clobber (reg:SI 6))
9191 (clobber (reg:SI 7))
9192 (clobber (reg:SI 8))
9193 (clobber (reg:SI 9))
9194 (clobber (reg:SI 10))
9195 (clobber (reg:SI 11))
9196 (clobber (reg:SI 12))
9197 (clobber (match_scratch:SI 4 ""))])]
9202 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9203 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9204 (use (match_operand:SI 2 "immediate_operand" "i"))
9205 (use (match_operand:SI 3 "immediate_operand" "i"))
9206 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9207 (clobber (reg:SI 6))
9208 (clobber (reg:SI 7))
9209 (clobber (reg:SI 8))
9210 (clobber (reg:SI 9))
9211 (clobber (reg:SI 10))
9212 (clobber (reg:SI 11))
9213 (clobber (reg:SI 12))
9214 (clobber (match_scratch:SI 5 "=q"))]
9215 "TARGET_STRING && TARGET_POWER
9216 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9217 || INTVAL (operands[2]) == 0)
9218 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9219 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9220 && REGNO (operands[4]) == 5"
9221 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9222 [(set_attr "type" "load")
9223 (set_attr "length" "8")])
9226 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9227 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9228 (use (match_operand:SI 2 "immediate_operand" "i"))
9229 (use (match_operand:SI 3 "immediate_operand" "i"))
9230 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9231 (clobber (reg:SI 6))
9232 (clobber (reg:SI 7))
9233 (clobber (reg:SI 8))
9234 (clobber (reg:SI 9))
9235 (clobber (reg:SI 10))
9236 (clobber (reg:SI 11))
9237 (clobber (reg:SI 12))
9238 (clobber (match_scratch:SI 5 "X"))]
9239 "TARGET_STRING && ! TARGET_POWER
9240 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9241 || INTVAL (operands[2]) == 0)
9242 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9243 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9244 && REGNO (operands[4]) == 5"
9245 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9246 [(set_attr "type" "load")
9247 (set_attr "length" "8")])
9250 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9251 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9252 (use (match_operand:SI 2 "immediate_operand" "i"))
9253 (use (match_operand:SI 3 "immediate_operand" "i"))
9254 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9255 (clobber (reg:SI 6))
9256 (clobber (reg:SI 7))
9257 (clobber (reg:SI 8))
9258 (clobber (reg:SI 9))
9259 (clobber (reg:SI 10))
9260 (clobber (reg:SI 11))
9261 (clobber (reg:SI 12))
9262 (clobber (match_scratch:SI 5 "X"))]
9263 "TARGET_STRING && TARGET_POWERPC64
9264 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9265 || INTVAL (operands[2]) == 0)
9266 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9267 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9268 && REGNO (operands[4]) == 5"
9269 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9270 [(set_attr "type" "load")
9271 (set_attr "length" "8")])
9273 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9274 ;; register allocator doesn't have a clue about allocating 6 word registers.
9275 ;; rD/rS = r5 is preferred, efficient form.
9276 (define_expand "movmemsi_6reg"
9277 [(parallel [(set (match_operand 0 "" "")
9278 (match_operand 1 "" ""))
9279 (use (match_operand 2 "" ""))
9280 (use (match_operand 3 "" ""))
9281 (clobber (reg:SI 5))
9282 (clobber (reg:SI 6))
9283 (clobber (reg:SI 7))
9284 (clobber (reg:SI 8))
9285 (clobber (reg:SI 9))
9286 (clobber (reg:SI 10))
9287 (clobber (match_scratch:SI 4 ""))])]
9292 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9293 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9294 (use (match_operand:SI 2 "immediate_operand" "i"))
9295 (use (match_operand:SI 3 "immediate_operand" "i"))
9296 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9297 (clobber (reg:SI 6))
9298 (clobber (reg:SI 7))
9299 (clobber (reg:SI 8))
9300 (clobber (reg:SI 9))
9301 (clobber (reg:SI 10))
9302 (clobber (match_scratch:SI 5 "=q"))]
9303 "TARGET_STRING && TARGET_POWER
9304 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9305 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9306 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9307 && REGNO (operands[4]) == 5"
9308 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9309 [(set_attr "type" "load")
9310 (set_attr "length" "8")])
9313 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9314 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9315 (use (match_operand:SI 2 "immediate_operand" "i"))
9316 (use (match_operand:SI 3 "immediate_operand" "i"))
9317 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9318 (clobber (reg:SI 6))
9319 (clobber (reg:SI 7))
9320 (clobber (reg:SI 8))
9321 (clobber (reg:SI 9))
9322 (clobber (reg:SI 10))
9323 (clobber (match_scratch:SI 5 "X"))]
9324 "TARGET_STRING && ! TARGET_POWER
9325 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9326 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9327 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9328 && REGNO (operands[4]) == 5"
9329 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9330 [(set_attr "type" "load")
9331 (set_attr "length" "8")])
9334 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9335 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9336 (use (match_operand:SI 2 "immediate_operand" "i"))
9337 (use (match_operand:SI 3 "immediate_operand" "i"))
9338 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9339 (clobber (reg:SI 6))
9340 (clobber (reg:SI 7))
9341 (clobber (reg:SI 8))
9342 (clobber (reg:SI 9))
9343 (clobber (reg:SI 10))
9344 (clobber (match_scratch:SI 5 "X"))]
9345 "TARGET_STRING && TARGET_POWERPC64
9346 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9347 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9348 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9349 && REGNO (operands[4]) == 5"
9350 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9351 [(set_attr "type" "load")
9352 (set_attr "length" "8")])
9354 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9355 ;; problems with TImode.
9356 ;; rD/rS = r5 is preferred, efficient form.
9357 (define_expand "movmemsi_4reg"
9358 [(parallel [(set (match_operand 0 "" "")
9359 (match_operand 1 "" ""))
9360 (use (match_operand 2 "" ""))
9361 (use (match_operand 3 "" ""))
9362 (clobber (reg:SI 5))
9363 (clobber (reg:SI 6))
9364 (clobber (reg:SI 7))
9365 (clobber (reg:SI 8))
9366 (clobber (match_scratch:SI 4 ""))])]
9371 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9372 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9373 (use (match_operand:SI 2 "immediate_operand" "i"))
9374 (use (match_operand:SI 3 "immediate_operand" "i"))
9375 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9376 (clobber (reg:SI 6))
9377 (clobber (reg:SI 7))
9378 (clobber (reg:SI 8))
9379 (clobber (match_scratch:SI 5 "=q"))]
9380 "TARGET_STRING && TARGET_POWER
9381 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9382 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9383 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9384 && REGNO (operands[4]) == 5"
9385 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9386 [(set_attr "type" "load")
9387 (set_attr "length" "8")])
9390 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9391 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9392 (use (match_operand:SI 2 "immediate_operand" "i"))
9393 (use (match_operand:SI 3 "immediate_operand" "i"))
9394 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9395 (clobber (reg:SI 6))
9396 (clobber (reg:SI 7))
9397 (clobber (reg:SI 8))
9398 (clobber (match_scratch:SI 5 "X"))]
9399 "TARGET_STRING && ! TARGET_POWER
9400 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9401 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9402 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9403 && REGNO (operands[4]) == 5"
9404 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9405 [(set_attr "type" "load")
9406 (set_attr "length" "8")])
9409 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9410 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9411 (use (match_operand:SI 2 "immediate_operand" "i"))
9412 (use (match_operand:SI 3 "immediate_operand" "i"))
9413 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9414 (clobber (reg:SI 6))
9415 (clobber (reg:SI 7))
9416 (clobber (reg:SI 8))
9417 (clobber (match_scratch:SI 5 "X"))]
9418 "TARGET_STRING && TARGET_POWERPC64
9419 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9420 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9421 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9422 && REGNO (operands[4]) == 5"
9423 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9424 [(set_attr "type" "load")
9425 (set_attr "length" "8")])
9427 ;; Move up to 8 bytes at a time.
9428 (define_expand "movmemsi_2reg"
9429 [(parallel [(set (match_operand 0 "" "")
9430 (match_operand 1 "" ""))
9431 (use (match_operand 2 "" ""))
9432 (use (match_operand 3 "" ""))
9433 (clobber (match_scratch:DI 4 ""))
9434 (clobber (match_scratch:SI 5 ""))])]
9435 "TARGET_STRING && ! TARGET_POWERPC64"
9439 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9440 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9441 (use (match_operand:SI 2 "immediate_operand" "i"))
9442 (use (match_operand:SI 3 "immediate_operand" "i"))
9443 (clobber (match_scratch:DI 4 "=&r"))
9444 (clobber (match_scratch:SI 5 "=q"))]
9445 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9446 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9447 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9448 [(set_attr "type" "load")
9449 (set_attr "length" "8")])
9452 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9453 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9454 (use (match_operand:SI 2 "immediate_operand" "i"))
9455 (use (match_operand:SI 3 "immediate_operand" "i"))
9456 (clobber (match_scratch:DI 4 "=&r"))
9457 (clobber (match_scratch:SI 5 "X"))]
9458 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9459 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9460 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9461 [(set_attr "type" "load")
9462 (set_attr "length" "8")])
9464 ;; Move up to 4 bytes at a time.
9465 (define_expand "movmemsi_1reg"
9466 [(parallel [(set (match_operand 0 "" "")
9467 (match_operand 1 "" ""))
9468 (use (match_operand 2 "" ""))
9469 (use (match_operand 3 "" ""))
9470 (clobber (match_scratch:SI 4 ""))
9471 (clobber (match_scratch:SI 5 ""))])]
9476 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9477 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9478 (use (match_operand:SI 2 "immediate_operand" "i"))
9479 (use (match_operand:SI 3 "immediate_operand" "i"))
9480 (clobber (match_scratch:SI 4 "=&r"))
9481 (clobber (match_scratch:SI 5 "=q"))]
9482 "TARGET_STRING && TARGET_POWER
9483 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9484 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9485 [(set_attr "type" "load")
9486 (set_attr "length" "8")])
9489 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9490 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9491 (use (match_operand:SI 2 "immediate_operand" "i"))
9492 (use (match_operand:SI 3 "immediate_operand" "i"))
9493 (clobber (match_scratch:SI 4 "=&r"))
9494 (clobber (match_scratch:SI 5 "X"))]
9495 "TARGET_STRING && ! TARGET_POWER
9496 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9497 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9498 [(set_attr "type" "load")
9499 (set_attr "length" "8")])
9502 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9503 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9504 (use (match_operand:SI 2 "immediate_operand" "i"))
9505 (use (match_operand:SI 3 "immediate_operand" "i"))
9506 (clobber (match_scratch:SI 4 "=&r"))
9507 (clobber (match_scratch:SI 5 "X"))]
9508 "TARGET_STRING && TARGET_POWERPC64
9509 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9510 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9511 [(set_attr "type" "load")
9512 (set_attr "length" "8")])
9515 ;; Define insns that do load or store with update. Some of these we can
9516 ;; get by using pre-decrement or pre-increment, but the hardware can also
9517 ;; do cases where the increment is not the size of the object.
9519 ;; In all these cases, we use operands 0 and 1 for the register being
9520 ;; incremented because those are the operands that local-alloc will
9521 ;; tie and these are the pair most likely to be tieable (and the ones
9522 ;; that will benefit the most).
9524 (define_insn "*movdi_update1"
9525 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9526 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9527 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9528 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9529 (plus:DI (match_dup 1) (match_dup 2)))]
9530 "TARGET_POWERPC64 && TARGET_UPDATE"
9534 [(set_attr "type" "load_ux,load_u")])
9536 (define_insn "movdi_<mode>_update"
9537 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9538 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9539 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9540 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9541 (plus:P (match_dup 1) (match_dup 2)))]
9542 "TARGET_POWERPC64 && TARGET_UPDATE"
9546 [(set_attr "type" "store_ux,store_u")])
9548 (define_insn "*movsi_update1"
9549 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9550 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9551 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9552 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9553 (plus:SI (match_dup 1) (match_dup 2)))]
9556 {lux|lwzux} %3,%0,%2
9557 {lu|lwzu} %3,%2(%0)"
9558 [(set_attr "type" "load_ux,load_u")])
9560 (define_insn "*movsi_update2"
9561 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9563 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9564 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9565 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9566 (plus:DI (match_dup 1) (match_dup 2)))]
9569 [(set_attr "type" "load_ext_ux")])
9571 (define_insn "movsi_update"
9572 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9573 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9574 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9575 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9576 (plus:SI (match_dup 1) (match_dup 2)))]
9579 {stux|stwux} %3,%0,%2
9580 {stu|stwu} %3,%2(%0)"
9581 [(set_attr "type" "store_ux,store_u")])
9583 (define_insn "*movhi_update1"
9584 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9585 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9586 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9587 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9588 (plus:SI (match_dup 1) (match_dup 2)))]
9593 [(set_attr "type" "load_ux,load_u")])
9595 (define_insn "*movhi_update2"
9596 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9598 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9599 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9600 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9601 (plus:SI (match_dup 1) (match_dup 2)))]
9606 [(set_attr "type" "load_ux,load_u")])
9608 (define_insn "*movhi_update3"
9609 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9611 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9612 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9613 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9614 (plus:SI (match_dup 1) (match_dup 2)))]
9619 [(set_attr "type" "load_ext_ux,load_ext_u")])
9621 (define_insn "*movhi_update4"
9622 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9623 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9624 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9625 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9626 (plus:SI (match_dup 1) (match_dup 2)))]
9631 [(set_attr "type" "store_ux,store_u")])
9633 (define_insn "*movqi_update1"
9634 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9635 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9636 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9637 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9638 (plus:SI (match_dup 1) (match_dup 2)))]
9643 [(set_attr "type" "load_ux,load_u")])
9645 (define_insn "*movqi_update2"
9646 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9648 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9649 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9650 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9651 (plus:SI (match_dup 1) (match_dup 2)))]
9656 [(set_attr "type" "load_ux,load_u")])
9658 (define_insn "*movqi_update3"
9659 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9660 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9661 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9662 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9663 (plus:SI (match_dup 1) (match_dup 2)))]
9668 [(set_attr "type" "store_ux,store_u")])
9670 (define_insn "*movsf_update1"
9671 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9672 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9673 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9674 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9675 (plus:SI (match_dup 1) (match_dup 2)))]
9676 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9680 [(set_attr "type" "fpload_ux,fpload_u")])
9682 (define_insn "*movsf_update2"
9683 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9684 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9685 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9686 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9687 (plus:SI (match_dup 1) (match_dup 2)))]
9688 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9692 [(set_attr "type" "fpstore_ux,fpstore_u")])
9694 (define_insn "*movsf_update3"
9695 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9696 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9697 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9698 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9699 (plus:SI (match_dup 1) (match_dup 2)))]
9700 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9702 {lux|lwzux} %3,%0,%2
9703 {lu|lwzu} %3,%2(%0)"
9704 [(set_attr "type" "load_ux,load_u")])
9706 (define_insn "*movsf_update4"
9707 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9708 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9709 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9710 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9711 (plus:SI (match_dup 1) (match_dup 2)))]
9712 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9714 {stux|stwux} %3,%0,%2
9715 {stu|stwu} %3,%2(%0)"
9716 [(set_attr "type" "store_ux,store_u")])
9718 (define_insn "*movdf_update1"
9719 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9720 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9721 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9722 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9723 (plus:SI (match_dup 1) (match_dup 2)))]
9724 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9728 [(set_attr "type" "fpload_ux,fpload_u")])
9730 (define_insn "*movdf_update2"
9731 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9732 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9733 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9734 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9735 (plus:SI (match_dup 1) (match_dup 2)))]
9736 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9740 [(set_attr "type" "fpstore_ux,fpstore_u")])
9742 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9744 (define_insn "*lfq_power2"
9745 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
9746 (match_operand:TF 1 "memory_operand" ""))]
9748 && TARGET_HARD_FLOAT && TARGET_FPRS"
9752 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9753 (match_operand:DF 1 "memory_operand" ""))
9754 (set (match_operand:DF 2 "gpc_reg_operand" "")
9755 (match_operand:DF 3 "memory_operand" ""))]
9757 && TARGET_HARD_FLOAT && TARGET_FPRS
9758 && registers_ok_for_quad_peep (operands[0], operands[2])
9759 && mems_ok_for_quad_peep (operands[1], operands[3])"
9762 "operands[1] = widen_memory_access (operands[1], TFmode, 0);
9763 operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));")
9765 (define_insn "*stfq_power2"
9766 [(set (match_operand:TF 0 "memory_operand" "")
9767 (match_operand:TF 1 "gpc_reg_operand" "f"))]
9769 && TARGET_HARD_FLOAT && TARGET_FPRS"
9774 [(set (match_operand:DF 0 "memory_operand" "")
9775 (match_operand:DF 1 "gpc_reg_operand" ""))
9776 (set (match_operand:DF 2 "memory_operand" "")
9777 (match_operand:DF 3 "gpc_reg_operand" ""))]
9779 && TARGET_HARD_FLOAT && TARGET_FPRS
9780 && registers_ok_for_quad_peep (operands[1], operands[3])
9781 && mems_ok_for_quad_peep (operands[0], operands[2])"
9784 "operands[0] = widen_memory_access (operands[0], TFmode, 0);
9785 operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));")
9787 ;; after inserting conditional returns we can sometimes have
9788 ;; unnecessary register moves. Unfortunately we cannot have a
9789 ;; modeless peephole here, because some single SImode sets have early
9790 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9791 ;; sequences, using get_attr_length here will smash the operands
9792 ;; array. Neither is there an early_cobbler_p predicate.
9794 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9795 (match_operand:DF 1 "any_operand" ""))
9796 (set (match_operand:DF 2 "gpc_reg_operand" "")
9798 "peep2_reg_dead_p (2, operands[0])"
9799 [(set (match_dup 2) (match_dup 1))])
9802 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9803 (match_operand:SF 1 "any_operand" ""))
9804 (set (match_operand:SF 2 "gpc_reg_operand" "")
9806 "peep2_reg_dead_p (2, operands[0])"
9807 [(set (match_dup 2) (match_dup 1))])
9812 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9813 (define_insn "tls_gd_32"
9814 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9815 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9816 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9818 "HAVE_AS_TLS && !TARGET_64BIT"
9819 "addi %0,%1,%2@got@tlsgd")
9821 (define_insn "tls_gd_64"
9822 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9823 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9824 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9826 "HAVE_AS_TLS && TARGET_64BIT"
9827 "addi %0,%1,%2@got@tlsgd")
9829 (define_insn "tls_ld_32"
9830 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9831 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9833 "HAVE_AS_TLS && !TARGET_64BIT"
9834 "addi %0,%1,%&@got@tlsld")
9836 (define_insn "tls_ld_64"
9837 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9838 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9840 "HAVE_AS_TLS && TARGET_64BIT"
9841 "addi %0,%1,%&@got@tlsld")
9843 (define_insn "tls_dtprel_32"
9844 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9845 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9846 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9848 "HAVE_AS_TLS && !TARGET_64BIT"
9849 "addi %0,%1,%2@dtprel")
9851 (define_insn "tls_dtprel_64"
9852 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9853 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9854 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9856 "HAVE_AS_TLS && TARGET_64BIT"
9857 "addi %0,%1,%2@dtprel")
9859 (define_insn "tls_dtprel_ha_32"
9860 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9861 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9862 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9863 UNSPEC_TLSDTPRELHA))]
9864 "HAVE_AS_TLS && !TARGET_64BIT"
9865 "addis %0,%1,%2@dtprel@ha")
9867 (define_insn "tls_dtprel_ha_64"
9868 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9869 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9870 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9871 UNSPEC_TLSDTPRELHA))]
9872 "HAVE_AS_TLS && TARGET_64BIT"
9873 "addis %0,%1,%2@dtprel@ha")
9875 (define_insn "tls_dtprel_lo_32"
9876 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9877 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9878 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9879 UNSPEC_TLSDTPRELLO))]
9880 "HAVE_AS_TLS && !TARGET_64BIT"
9881 "addi %0,%1,%2@dtprel@l")
9883 (define_insn "tls_dtprel_lo_64"
9884 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9885 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9886 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9887 UNSPEC_TLSDTPRELLO))]
9888 "HAVE_AS_TLS && TARGET_64BIT"
9889 "addi %0,%1,%2@dtprel@l")
9891 (define_insn "tls_got_dtprel_32"
9892 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9893 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9894 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9895 UNSPEC_TLSGOTDTPREL))]
9896 "HAVE_AS_TLS && !TARGET_64BIT"
9897 "lwz %0,%2@got@dtprel(%1)")
9899 (define_insn "tls_got_dtprel_64"
9900 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9901 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9902 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9903 UNSPEC_TLSGOTDTPREL))]
9904 "HAVE_AS_TLS && TARGET_64BIT"
9905 "ld %0,%2@got@dtprel(%1)")
9907 (define_insn "tls_tprel_32"
9908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9909 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9910 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9912 "HAVE_AS_TLS && !TARGET_64BIT"
9913 "addi %0,%1,%2@tprel")
9915 (define_insn "tls_tprel_64"
9916 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9917 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9918 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9920 "HAVE_AS_TLS && TARGET_64BIT"
9921 "addi %0,%1,%2@tprel")
9923 (define_insn "tls_tprel_ha_32"
9924 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9925 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9926 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9927 UNSPEC_TLSTPRELHA))]
9928 "HAVE_AS_TLS && !TARGET_64BIT"
9929 "addis %0,%1,%2@tprel@ha")
9931 (define_insn "tls_tprel_ha_64"
9932 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9933 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9934 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9935 UNSPEC_TLSTPRELHA))]
9936 "HAVE_AS_TLS && TARGET_64BIT"
9937 "addis %0,%1,%2@tprel@ha")
9939 (define_insn "tls_tprel_lo_32"
9940 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9941 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9942 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9943 UNSPEC_TLSTPRELLO))]
9944 "HAVE_AS_TLS && !TARGET_64BIT"
9945 "addi %0,%1,%2@tprel@l")
9947 (define_insn "tls_tprel_lo_64"
9948 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9949 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9950 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9951 UNSPEC_TLSTPRELLO))]
9952 "HAVE_AS_TLS && TARGET_64BIT"
9953 "addi %0,%1,%2@tprel@l")
9955 ;; "b" output constraint here and on tls_tls input to support linker tls
9956 ;; optimization. The linker may edit the instructions emitted by a
9957 ;; tls_got_tprel/tls_tls pair to addis,addi.
9958 (define_insn "tls_got_tprel_32"
9959 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9960 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9961 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9962 UNSPEC_TLSGOTTPREL))]
9963 "HAVE_AS_TLS && !TARGET_64BIT"
9964 "lwz %0,%2@got@tprel(%1)")
9966 (define_insn "tls_got_tprel_64"
9967 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9968 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9969 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9970 UNSPEC_TLSGOTTPREL))]
9971 "HAVE_AS_TLS && TARGET_64BIT"
9972 "ld %0,%2@got@tprel(%1)")
9974 (define_insn "tls_tls_32"
9975 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9976 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9977 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9979 "HAVE_AS_TLS && !TARGET_64BIT"
9982 (define_insn "tls_tls_64"
9983 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9984 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9985 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9987 "HAVE_AS_TLS && TARGET_64BIT"
9990 ;; Next come insns related to the calling sequence.
9992 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9993 ;; We move the back-chain and decrement the stack pointer.
9995 (define_expand "allocate_stack"
9996 [(set (match_operand 0 "gpc_reg_operand" "=r")
9997 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9999 (minus (reg 1) (match_dup 1)))]
10002 { rtx chain = gen_reg_rtx (Pmode);
10003 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10006 emit_move_insn (chain, stack_bot);
10008 /* Check stack bounds if necessary. */
10009 if (current_function_limit_stack)
10012 available = expand_binop (Pmode, sub_optab,
10013 stack_pointer_rtx, stack_limit_rtx,
10014 NULL_RTX, 1, OPTAB_WIDEN);
10015 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10018 if (GET_CODE (operands[1]) != CONST_INT
10019 || INTVAL (operands[1]) < -32767
10020 || INTVAL (operands[1]) > 32768)
10022 neg_op0 = gen_reg_rtx (Pmode);
10024 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10026 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10029 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10032 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
10033 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
10037 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10038 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10039 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
10042 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10046 ;; These patterns say how to save and restore the stack pointer. We need not
10047 ;; save the stack pointer at function level since we are careful to
10048 ;; preserve the backchain. At block level, we have to restore the backchain
10049 ;; when we restore the stack pointer.
10051 ;; For nonlocal gotos, we must save both the stack pointer and its
10052 ;; backchain and restore both. Note that in the nonlocal case, the
10053 ;; save area is a memory location.
10055 (define_expand "save_stack_function"
10056 [(match_operand 0 "any_operand" "")
10057 (match_operand 1 "any_operand" "")]
10061 (define_expand "restore_stack_function"
10062 [(match_operand 0 "any_operand" "")
10063 (match_operand 1 "any_operand" "")]
10067 (define_expand "restore_stack_block"
10068 [(use (match_operand 0 "register_operand" ""))
10069 (set (match_dup 2) (match_dup 3))
10070 (set (match_dup 0) (match_operand 1 "register_operand" ""))
10071 (set (match_dup 3) (match_dup 2))]
10075 operands[2] = gen_reg_rtx (Pmode);
10076 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
10079 (define_expand "save_stack_nonlocal"
10080 [(match_operand 0 "memory_operand" "")
10081 (match_operand 1 "register_operand" "")]
10085 rtx temp = gen_reg_rtx (Pmode);
10086 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10088 /* Copy the backchain to the first word, sp to the second. */
10089 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
10090 emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp);
10091 emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word),
10096 (define_expand "restore_stack_nonlocal"
10097 [(match_operand 0 "register_operand" "")
10098 (match_operand 1 "memory_operand" "")]
10102 rtx temp = gen_reg_rtx (Pmode);
10103 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10105 /* Restore the backchain from the first word, sp from the second. */
10106 emit_move_insn (temp,
10107 adjust_address_nv (operands[1], Pmode, 0));
10108 emit_move_insn (operands[0],
10109 adjust_address_nv (operands[1], Pmode, units_per_word));
10110 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
10114 ;; TOC register handling.
10116 ;; Code to initialize the TOC register...
10118 (define_insn "load_toc_aix_si"
10119 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10120 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10121 (use (reg:SI 2))])]
10122 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10126 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10127 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10128 operands[2] = gen_rtx_REG (Pmode, 2);
10129 return \"{l|lwz} %0,%1(%2)\";
10131 [(set_attr "type" "load")])
10133 (define_insn "load_toc_aix_di"
10134 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10135 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10136 (use (reg:DI 2))])]
10137 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10141 #ifdef TARGET_RELOCATABLE
10142 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10143 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10145 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10148 strcat (buf, \"@toc\");
10149 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10150 operands[2] = gen_rtx_REG (Pmode, 2);
10151 return \"ld %0,%1(%2)\";
10153 [(set_attr "type" "load")])
10155 (define_insn "load_toc_v4_pic_si"
10156 [(set (match_operand:SI 0 "register_operand" "=l")
10157 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10158 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10159 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10160 [(set_attr "type" "branch")
10161 (set_attr "length" "4")])
10163 (define_insn "load_toc_v4_PIC_1"
10164 [(set (match_operand:SI 0 "register_operand" "=l")
10165 (match_operand:SI 1 "immediate_operand" "s"))
10166 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
10167 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10168 "bcl 20,31,%1\\n%1:"
10169 [(set_attr "type" "branch")
10170 (set_attr "length" "4")])
10172 (define_insn "load_toc_v4_PIC_1b"
10173 [(set (match_operand:SI 0 "register_operand" "=l")
10174 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
10176 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10177 "bcl 20,31,$+8\\n\\t.long %1-$"
10178 [(set_attr "type" "branch")
10179 (set_attr "length" "8")])
10181 (define_insn "load_toc_v4_PIC_2"
10182 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10183 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10184 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10185 (match_operand:SI 3 "immediate_operand" "s")))))]
10186 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10187 "{l|lwz} %0,%2-%3(%1)"
10188 [(set_attr "type" "load")])
10191 ;; If the TOC is shared over a translation unit, as happens with all
10192 ;; the kinds of PIC that we support, we need to restore the TOC
10193 ;; pointer only when jumping over units of translation.
10194 ;; On Darwin, we need to reload the picbase.
10196 (define_expand "builtin_setjmp_receiver"
10197 [(use (label_ref (match_operand 0 "" "")))]
10198 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10199 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10200 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10204 if (DEFAULT_ABI == ABI_DARWIN)
10206 const char *picbase = machopic_function_base_name ();
10207 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10208 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10212 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10213 CODE_LABEL_NUMBER (operands[0]));
10214 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10216 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10217 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10221 rs6000_emit_load_toc_table (FALSE);
10225 ;; A function pointer under AIX is a pointer to a data area whose first word
10226 ;; contains the actual address of the function, whose second word contains a
10227 ;; pointer to its TOC, and whose third word contains a value to place in the
10228 ;; static chain register (r11). Note that if we load the static chain, our
10229 ;; "trampoline" need not have any executable code.
10231 (define_expand "call_indirect_aix32"
10232 [(set (match_dup 2)
10233 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10234 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10237 (mem:SI (plus:SI (match_dup 0)
10240 (mem:SI (plus:SI (match_dup 0)
10242 (parallel [(call (mem:SI (match_dup 2))
10243 (match_operand 1 "" ""))
10247 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10248 (clobber (scratch:SI))])]
10251 { operands[2] = gen_reg_rtx (SImode); }")
10253 (define_expand "call_indirect_aix64"
10254 [(set (match_dup 2)
10255 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10256 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10259 (mem:DI (plus:DI (match_dup 0)
10262 (mem:DI (plus:DI (match_dup 0)
10264 (parallel [(call (mem:SI (match_dup 2))
10265 (match_operand 1 "" ""))
10269 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10270 (clobber (scratch:SI))])]
10273 { operands[2] = gen_reg_rtx (DImode); }")
10275 (define_expand "call_value_indirect_aix32"
10276 [(set (match_dup 3)
10277 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10278 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10281 (mem:SI (plus:SI (match_dup 1)
10284 (mem:SI (plus:SI (match_dup 1)
10286 (parallel [(set (match_operand 0 "" "")
10287 (call (mem:SI (match_dup 3))
10288 (match_operand 2 "" "")))
10292 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10293 (clobber (scratch:SI))])]
10296 { operands[3] = gen_reg_rtx (SImode); }")
10298 (define_expand "call_value_indirect_aix64"
10299 [(set (match_dup 3)
10300 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10301 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10304 (mem:DI (plus:DI (match_dup 1)
10307 (mem:DI (plus:DI (match_dup 1)
10309 (parallel [(set (match_operand 0 "" "")
10310 (call (mem:SI (match_dup 3))
10311 (match_operand 2 "" "")))
10315 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10316 (clobber (scratch:SI))])]
10319 { operands[3] = gen_reg_rtx (DImode); }")
10321 ;; Now the definitions for the call and call_value insns
10322 (define_expand "call"
10323 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10324 (match_operand 1 "" ""))
10325 (use (match_operand 2 "" ""))
10326 (clobber (scratch:SI))])]
10331 if (MACHOPIC_INDIRECT)
10332 operands[0] = machopic_indirect_call_target (operands[0]);
10335 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10338 operands[0] = XEXP (operands[0], 0);
10340 if (GET_CODE (operands[0]) != SYMBOL_REF
10341 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10342 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10344 if (INTVAL (operands[2]) & CALL_LONG)
10345 operands[0] = rs6000_longcall_ref (operands[0]);
10347 if (DEFAULT_ABI == ABI_V4
10348 || DEFAULT_ABI == ABI_DARWIN)
10349 operands[0] = force_reg (Pmode, operands[0]);
10351 else if (DEFAULT_ABI == ABI_AIX)
10353 /* AIX function pointers are really pointers to a three word
10355 emit_call_insn (TARGET_32BIT
10356 ? gen_call_indirect_aix32 (force_reg (SImode,
10359 : gen_call_indirect_aix64 (force_reg (DImode,
10369 (define_expand "call_value"
10370 [(parallel [(set (match_operand 0 "" "")
10371 (call (mem:SI (match_operand 1 "address_operand" ""))
10372 (match_operand 2 "" "")))
10373 (use (match_operand 3 "" ""))
10374 (clobber (scratch:SI))])]
10379 if (MACHOPIC_INDIRECT)
10380 operands[1] = machopic_indirect_call_target (operands[1]);
10383 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10386 operands[1] = XEXP (operands[1], 0);
10388 if (GET_CODE (operands[1]) != SYMBOL_REF
10389 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10390 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10392 if (INTVAL (operands[3]) & CALL_LONG)
10393 operands[1] = rs6000_longcall_ref (operands[1]);
10395 if (DEFAULT_ABI == ABI_V4
10396 || DEFAULT_ABI == ABI_DARWIN)
10397 operands[1] = force_reg (Pmode, operands[1]);
10399 else if (DEFAULT_ABI == ABI_AIX)
10401 /* AIX function pointers are really pointers to a three word
10403 emit_call_insn (TARGET_32BIT
10404 ? gen_call_value_indirect_aix32 (operands[0],
10408 : gen_call_value_indirect_aix64 (operands[0],
10419 ;; Call to function in current module. No TOC pointer reload needed.
10420 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10421 ;; either the function was not prototyped, or it was prototyped as a
10422 ;; variable argument function. It is > 0 if FP registers were passed
10423 ;; and < 0 if they were not.
10425 (define_insn "*call_local32"
10426 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10427 (match_operand 1 "" "g,g"))
10428 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10429 (clobber (match_scratch:SI 3 "=l,l"))]
10430 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10433 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10434 output_asm_insn (\"crxor 6,6,6\", operands);
10436 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10437 output_asm_insn (\"creqv 6,6,6\", operands);
10439 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10441 [(set_attr "type" "branch")
10442 (set_attr "length" "4,8")])
10444 (define_insn "*call_local64"
10445 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10446 (match_operand 1 "" "g,g"))
10447 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10448 (clobber (match_scratch:SI 3 "=l,l"))]
10449 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10452 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10453 output_asm_insn (\"crxor 6,6,6\", operands);
10455 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10456 output_asm_insn (\"creqv 6,6,6\", operands);
10458 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10460 [(set_attr "type" "branch")
10461 (set_attr "length" "4,8")])
10463 (define_insn "*call_value_local32"
10464 [(set (match_operand 0 "" "")
10465 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10466 (match_operand 2 "" "g,g")))
10467 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10468 (clobber (match_scratch:SI 4 "=l,l"))]
10469 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10472 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10473 output_asm_insn (\"crxor 6,6,6\", operands);
10475 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10476 output_asm_insn (\"creqv 6,6,6\", operands);
10478 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10480 [(set_attr "type" "branch")
10481 (set_attr "length" "4,8")])
10484 (define_insn "*call_value_local64"
10485 [(set (match_operand 0 "" "")
10486 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10487 (match_operand 2 "" "g,g")))
10488 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10489 (clobber (match_scratch:SI 4 "=l,l"))]
10490 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10493 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10494 output_asm_insn (\"crxor 6,6,6\", operands);
10496 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10497 output_asm_insn (\"creqv 6,6,6\", operands);
10499 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10501 [(set_attr "type" "branch")
10502 (set_attr "length" "4,8")])
10504 ;; Call to function which may be in another module. Restore the TOC
10505 ;; pointer (r2) after the call unless this is System V.
10506 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10507 ;; either the function was not prototyped, or it was prototyped as a
10508 ;; variable argument function. It is > 0 if FP registers were passed
10509 ;; and < 0 if they were not.
10511 (define_insn "*call_indirect_nonlocal_aix32"
10512 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
10513 (match_operand 1 "" "g"))
10517 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10518 (clobber (match_scratch:SI 2 "=l"))]
10519 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10520 "b%T0l\;{l|lwz} 2,20(1)"
10521 [(set_attr "type" "jmpreg")
10522 (set_attr "length" "8")])
10524 (define_insn "*call_nonlocal_aix32"
10525 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10526 (match_operand 1 "" "g"))
10527 (use (match_operand:SI 2 "immediate_operand" "O"))
10528 (clobber (match_scratch:SI 3 "=l"))]
10530 && DEFAULT_ABI == ABI_AIX
10531 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10533 [(set_attr "type" "branch")
10534 (set_attr "length" "8")])
10536 (define_insn "*call_indirect_nonlocal_aix64"
10537 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
10538 (match_operand 1 "" "g"))
10542 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10543 (clobber (match_scratch:SI 2 "=l"))]
10544 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10545 "b%T0l\;ld 2,40(1)"
10546 [(set_attr "type" "jmpreg")
10547 (set_attr "length" "8")])
10549 (define_insn "*call_nonlocal_aix64"
10550 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10551 (match_operand 1 "" "g"))
10552 (use (match_operand:SI 2 "immediate_operand" "O"))
10553 (clobber (match_scratch:SI 3 "=l"))]
10555 && DEFAULT_ABI == ABI_AIX
10556 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10558 [(set_attr "type" "branch")
10559 (set_attr "length" "8")])
10561 (define_insn "*call_value_indirect_nonlocal_aix32"
10562 [(set (match_operand 0 "" "")
10563 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
10564 (match_operand 2 "" "g")))
10568 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10569 (clobber (match_scratch:SI 3 "=l"))]
10570 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10571 "b%T1l\;{l|lwz} 2,20(1)"
10572 [(set_attr "type" "jmpreg")
10573 (set_attr "length" "8")])
10575 (define_insn "*call_value_nonlocal_aix32"
10576 [(set (match_operand 0 "" "")
10577 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10578 (match_operand 2 "" "g")))
10579 (use (match_operand:SI 3 "immediate_operand" "O"))
10580 (clobber (match_scratch:SI 4 "=l"))]
10582 && DEFAULT_ABI == ABI_AIX
10583 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10585 [(set_attr "type" "branch")
10586 (set_attr "length" "8")])
10588 (define_insn "*call_value_indirect_nonlocal_aix64"
10589 [(set (match_operand 0 "" "")
10590 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10591 (match_operand 2 "" "g")))
10595 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10596 (clobber (match_scratch:SI 3 "=l"))]
10597 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10598 "b%T1l\;ld 2,40(1)"
10599 [(set_attr "type" "jmpreg")
10600 (set_attr "length" "8")])
10602 (define_insn "*call_value_nonlocal_aix64"
10603 [(set (match_operand 0 "" "")
10604 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10605 (match_operand 2 "" "g")))
10606 (use (match_operand:SI 3 "immediate_operand" "O"))
10607 (clobber (match_scratch:SI 4 "=l"))]
10609 && DEFAULT_ABI == ABI_AIX
10610 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10612 [(set_attr "type" "branch")
10613 (set_attr "length" "8")])
10615 ;; A function pointer under System V is just a normal pointer
10616 ;; operands[0] is the function pointer
10617 ;; operands[1] is the stack size to clean up
10618 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10619 ;; which indicates how to set cr1
10621 (define_insn "*call_indirect_nonlocal_sysv"
10622 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
10623 (match_operand 1 "" "g,g"))
10624 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10625 (clobber (match_scratch:SI 3 "=l,l"))]
10626 "DEFAULT_ABI == ABI_V4
10627 || DEFAULT_ABI == ABI_DARWIN"
10629 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10630 output_asm_insn ("crxor 6,6,6", operands);
10632 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10633 output_asm_insn ("creqv 6,6,6", operands);
10637 [(set_attr "type" "jmpreg,jmpreg")
10638 (set_attr "length" "4,8")])
10640 (define_insn "*call_nonlocal_sysv"
10641 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10642 (match_operand 1 "" "g,g"))
10643 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10644 (clobber (match_scratch:SI 3 "=l,l"))]
10645 "(DEFAULT_ABI == ABI_DARWIN
10646 || (DEFAULT_ABI == ABI_V4
10647 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10649 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10650 output_asm_insn ("crxor 6,6,6", operands);
10652 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10653 output_asm_insn ("creqv 6,6,6", operands);
10656 return output_call(insn, operands, 0, 2);
10658 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";
10661 [(set_attr "type" "branch,branch")
10662 (set_attr "length" "4,8")])
10664 (define_insn "*call_value_indirect_nonlocal_sysv"
10665 [(set (match_operand 0 "" "")
10666 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
10667 (match_operand 2 "" "g,g")))
10668 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10669 (clobber (match_scratch:SI 4 "=l,l"))]
10670 "DEFAULT_ABI == ABI_V4
10671 || DEFAULT_ABI == ABI_DARWIN"
10673 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10674 output_asm_insn ("crxor 6,6,6", operands);
10676 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10677 output_asm_insn ("creqv 6,6,6", operands);
10681 [(set_attr "type" "jmpreg,jmpreg")
10682 (set_attr "length" "4,8")])
10684 (define_insn "*call_value_nonlocal_sysv"
10685 [(set (match_operand 0 "" "")
10686 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10687 (match_operand 2 "" "g,g")))
10688 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10689 (clobber (match_scratch:SI 4 "=l,l"))]
10690 "(DEFAULT_ABI == ABI_DARWIN
10691 || (DEFAULT_ABI == ABI_V4
10692 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10694 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10695 output_asm_insn ("crxor 6,6,6", operands);
10697 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10698 output_asm_insn ("creqv 6,6,6", operands);
10701 return output_call(insn, operands, 1, 3);
10703 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";
10706 [(set_attr "type" "branch,branch")
10707 (set_attr "length" "4,8")])
10709 ;; Call subroutine returning any type.
10710 (define_expand "untyped_call"
10711 [(parallel [(call (match_operand 0 "" "")
10713 (match_operand 1 "" "")
10714 (match_operand 2 "" "")])]
10720 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10722 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10724 rtx set = XVECEXP (operands[2], 0, i);
10725 emit_move_insn (SET_DEST (set), SET_SRC (set));
10728 /* The optimizer does not know that the call sets the function value
10729 registers we stored in the result block. We avoid problems by
10730 claiming that all hard registers are used and clobbered at this
10732 emit_insn (gen_blockage ());
10737 ;; sibling call patterns
10738 (define_expand "sibcall"
10739 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10740 (match_operand 1 "" ""))
10741 (use (match_operand 2 "" ""))
10742 (use (match_operand 3 "" ""))
10748 if (MACHOPIC_INDIRECT)
10749 operands[0] = machopic_indirect_call_target (operands[0]);
10752 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10755 operands[0] = XEXP (operands[0], 0);
10756 operands[3] = gen_reg_rtx (SImode);
10760 ;; this and similar patterns must be marked as using LR, otherwise
10761 ;; dataflow will try to delete the store into it. This is true
10762 ;; even when the actual reg to jump to is in CTR, when LR was
10763 ;; saved and restored around the PIC-setting BCL.
10764 (define_insn "*sibcall_local32"
10765 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10766 (match_operand 1 "" "g,g"))
10767 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10768 (use (match_operand:SI 3 "register_operand" "l,l"))
10770 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10773 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10774 output_asm_insn (\"crxor 6,6,6\", operands);
10776 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10777 output_asm_insn (\"creqv 6,6,6\", operands);
10779 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10781 [(set_attr "type" "branch")
10782 (set_attr "length" "4,8")])
10784 (define_insn "*sibcall_local64"
10785 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10786 (match_operand 1 "" "g,g"))
10787 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10788 (use (match_operand:SI 3 "register_operand" "l,l"))
10790 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10793 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10794 output_asm_insn (\"crxor 6,6,6\", operands);
10796 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10797 output_asm_insn (\"creqv 6,6,6\", operands);
10799 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10801 [(set_attr "type" "branch")
10802 (set_attr "length" "4,8")])
10804 (define_insn "*sibcall_value_local32"
10805 [(set (match_operand 0 "" "")
10806 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10807 (match_operand 2 "" "g,g")))
10808 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10809 (use (match_operand:SI 4 "register_operand" "l,l"))
10811 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10814 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10815 output_asm_insn (\"crxor 6,6,6\", operands);
10817 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10818 output_asm_insn (\"creqv 6,6,6\", operands);
10820 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10822 [(set_attr "type" "branch")
10823 (set_attr "length" "4,8")])
10826 (define_insn "*sibcall_value_local64"
10827 [(set (match_operand 0 "" "")
10828 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10829 (match_operand 2 "" "g,g")))
10830 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10831 (use (match_operand:SI 4 "register_operand" "l,l"))
10833 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10836 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10837 output_asm_insn (\"crxor 6,6,6\", operands);
10839 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10840 output_asm_insn (\"creqv 6,6,6\", operands);
10842 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10844 [(set_attr "type" "branch")
10845 (set_attr "length" "4,8")])
10847 (define_insn "*sibcall_nonlocal_aix32"
10848 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10849 (match_operand 1 "" "g"))
10850 (use (match_operand:SI 2 "immediate_operand" "O"))
10851 (use (match_operand:SI 3 "register_operand" "l"))
10854 && DEFAULT_ABI == ABI_AIX
10855 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10857 [(set_attr "type" "branch")
10858 (set_attr "length" "4")])
10860 (define_insn "*sibcall_nonlocal_aix64"
10861 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10862 (match_operand 1 "" "g"))
10863 (use (match_operand:SI 2 "immediate_operand" "O"))
10864 (use (match_operand:SI 3 "register_operand" "l"))
10867 && DEFAULT_ABI == ABI_AIX
10868 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10870 [(set_attr "type" "branch")
10871 (set_attr "length" "4")])
10873 (define_insn "*sibcall_value_nonlocal_aix32"
10874 [(set (match_operand 0 "" "")
10875 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10876 (match_operand 2 "" "g")))
10877 (use (match_operand:SI 3 "immediate_operand" "O"))
10878 (use (match_operand:SI 4 "register_operand" "l"))
10881 && DEFAULT_ABI == ABI_AIX
10882 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10884 [(set_attr "type" "branch")
10885 (set_attr "length" "4")])
10887 (define_insn "*sibcall_value_nonlocal_aix64"
10888 [(set (match_operand 0 "" "")
10889 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10890 (match_operand 2 "" "g")))
10891 (use (match_operand:SI 3 "immediate_operand" "O"))
10892 (use (match_operand:SI 4 "register_operand" "l"))
10895 && DEFAULT_ABI == ABI_AIX
10896 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10898 [(set_attr "type" "branch")
10899 (set_attr "length" "4")])
10901 (define_insn "*sibcall_nonlocal_sysv"
10902 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10903 (match_operand 1 "" ""))
10904 (use (match_operand 2 "immediate_operand" "O,n"))
10905 (use (match_operand:SI 3 "register_operand" "l,l"))
10907 "(DEFAULT_ABI == ABI_DARWIN
10908 || DEFAULT_ABI == ABI_V4)
10909 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10912 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10913 output_asm_insn (\"crxor 6,6,6\", operands);
10915 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10916 output_asm_insn (\"creqv 6,6,6\", operands);
10918 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";
10920 [(set_attr "type" "branch,branch")
10921 (set_attr "length" "4,8")])
10923 (define_expand "sibcall_value"
10924 [(parallel [(set (match_operand 0 "register_operand" "")
10925 (call (mem:SI (match_operand 1 "address_operand" ""))
10926 (match_operand 2 "" "")))
10927 (use (match_operand 3 "" ""))
10928 (use (match_operand 4 "" ""))
10934 if (MACHOPIC_INDIRECT)
10935 operands[1] = machopic_indirect_call_target (operands[1]);
10938 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10941 operands[1] = XEXP (operands[1], 0);
10942 operands[4] = gen_reg_rtx (SImode);
10946 (define_insn "*sibcall_value_nonlocal_sysv"
10947 [(set (match_operand 0 "" "")
10948 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10949 (match_operand 2 "" "")))
10950 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10951 (use (match_operand:SI 4 "register_operand" "l,l"))
10953 "(DEFAULT_ABI == ABI_DARWIN
10954 || DEFAULT_ABI == ABI_V4)
10955 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10958 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10959 output_asm_insn (\"crxor 6,6,6\", operands);
10961 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10962 output_asm_insn (\"creqv 6,6,6\", operands);
10964 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";
10966 [(set_attr "type" "branch,branch")
10967 (set_attr "length" "4,8")])
10969 (define_expand "sibcall_epilogue"
10970 [(use (const_int 0))]
10971 "TARGET_SCHED_PROLOG"
10974 rs6000_emit_epilogue (TRUE);
10978 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10979 ;; all of memory. This blocks insns from being moved across this point.
10981 (define_insn "blockage"
10982 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10986 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10987 ;; signed & unsigned, and one type of branch.
10989 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10990 ;; insns, and branches. We store the operands of compares until we see
10992 (define_expand "cmpsi"
10994 (compare (match_operand:SI 0 "gpc_reg_operand" "")
10995 (match_operand:SI 1 "reg_or_short_operand" "")))]
10999 /* Take care of the possibility that operands[1] might be negative but
11000 this might be a logical operation. That insn doesn't exist. */
11001 if (GET_CODE (operands[1]) == CONST_INT
11002 && INTVAL (operands[1]) < 0)
11003 operands[1] = force_reg (SImode, operands[1]);
11005 rs6000_compare_op0 = operands[0];
11006 rs6000_compare_op1 = operands[1];
11007 rs6000_compare_fp_p = 0;
11011 (define_expand "cmpdi"
11013 (compare (match_operand:DI 0 "gpc_reg_operand" "")
11014 (match_operand:DI 1 "reg_or_short_operand" "")))]
11018 /* Take care of the possibility that operands[1] might be negative but
11019 this might be a logical operation. That insn doesn't exist. */
11020 if (GET_CODE (operands[1]) == CONST_INT
11021 && INTVAL (operands[1]) < 0)
11022 operands[1] = force_reg (DImode, operands[1]);
11024 rs6000_compare_op0 = operands[0];
11025 rs6000_compare_op1 = operands[1];
11026 rs6000_compare_fp_p = 0;
11030 (define_expand "cmpsf"
11031 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
11032 (match_operand:SF 1 "gpc_reg_operand" "")))]
11033 "TARGET_HARD_FLOAT"
11036 rs6000_compare_op0 = operands[0];
11037 rs6000_compare_op1 = operands[1];
11038 rs6000_compare_fp_p = 1;
11042 (define_expand "cmpdf"
11043 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
11044 (match_operand:DF 1 "gpc_reg_operand" "")))]
11045 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
11048 rs6000_compare_op0 = operands[0];
11049 rs6000_compare_op1 = operands[1];
11050 rs6000_compare_fp_p = 1;
11054 (define_expand "cmptf"
11055 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
11056 (match_operand:TF 1 "gpc_reg_operand" "")))]
11057 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
11058 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11061 rs6000_compare_op0 = operands[0];
11062 rs6000_compare_op1 = operands[1];
11063 rs6000_compare_fp_p = 1;
11067 (define_expand "beq"
11068 [(use (match_operand 0 "" ""))]
11070 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11072 (define_expand "bne"
11073 [(use (match_operand 0 "" ""))]
11075 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11077 (define_expand "bge"
11078 [(use (match_operand 0 "" ""))]
11080 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11082 (define_expand "bgt"
11083 [(use (match_operand 0 "" ""))]
11085 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11087 (define_expand "ble"
11088 [(use (match_operand 0 "" ""))]
11090 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11092 (define_expand "blt"
11093 [(use (match_operand 0 "" ""))]
11095 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11097 (define_expand "bgeu"
11098 [(use (match_operand 0 "" ""))]
11100 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11102 (define_expand "bgtu"
11103 [(use (match_operand 0 "" ""))]
11105 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11107 (define_expand "bleu"
11108 [(use (match_operand 0 "" ""))]
11110 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11112 (define_expand "bltu"
11113 [(use (match_operand 0 "" ""))]
11115 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11117 (define_expand "bunordered"
11118 [(use (match_operand 0 "" ""))]
11119 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11120 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11122 (define_expand "bordered"
11123 [(use (match_operand 0 "" ""))]
11124 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11125 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11127 (define_expand "buneq"
11128 [(use (match_operand 0 "" ""))]
11130 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11132 (define_expand "bunge"
11133 [(use (match_operand 0 "" ""))]
11135 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11137 (define_expand "bungt"
11138 [(use (match_operand 0 "" ""))]
11140 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11142 (define_expand "bunle"
11143 [(use (match_operand 0 "" ""))]
11145 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11147 (define_expand "bunlt"
11148 [(use (match_operand 0 "" ""))]
11150 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11152 (define_expand "bltgt"
11153 [(use (match_operand 0 "" ""))]
11155 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11157 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11158 ;; For SEQ, likewise, except that comparisons with zero should be done
11159 ;; with an scc insns. However, due to the order that combine see the
11160 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11161 ;; the cases we don't want to handle.
11162 (define_expand "seq"
11163 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11165 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11167 (define_expand "sne"
11168 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11172 if (! rs6000_compare_fp_p)
11175 rs6000_emit_sCOND (NE, operands[0]);
11179 ;; A >= 0 is best done the portable way for A an integer.
11180 (define_expand "sge"
11181 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11185 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11188 rs6000_emit_sCOND (GE, operands[0]);
11192 ;; A > 0 is best done using the portable sequence, so fail in that case.
11193 (define_expand "sgt"
11194 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11198 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11201 rs6000_emit_sCOND (GT, operands[0]);
11205 ;; A <= 0 is best done the portable way for A an integer.
11206 (define_expand "sle"
11207 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11211 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11214 rs6000_emit_sCOND (LE, operands[0]);
11218 ;; A < 0 is best done in the portable way for A an integer.
11219 (define_expand "slt"
11220 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11224 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11227 rs6000_emit_sCOND (LT, operands[0]);
11231 (define_expand "sgeu"
11232 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11234 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11236 (define_expand "sgtu"
11237 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11239 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11241 (define_expand "sleu"
11242 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11244 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11246 (define_expand "sltu"
11247 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11249 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11251 (define_expand "sunordered"
11252 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11253 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11254 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11256 (define_expand "sordered"
11257 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11258 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11259 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11261 (define_expand "suneq"
11262 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11264 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11266 (define_expand "sunge"
11267 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11269 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11271 (define_expand "sungt"
11272 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11274 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11276 (define_expand "sunle"
11277 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11279 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11281 (define_expand "sunlt"
11282 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11284 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11286 (define_expand "sltgt"
11287 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11289 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11292 ;; Here are the actual compare insns.
11293 (define_insn "*cmpsi_internal1"
11294 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11295 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11296 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11298 "{cmp%I2|cmpw%I2} %0,%1,%2"
11299 [(set_attr "type" "cmp")])
11301 (define_insn "*cmpdi_internal1"
11302 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11303 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
11304 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11307 [(set_attr "type" "cmp")])
11309 ;; If we are comparing a register for equality with a large constant,
11310 ;; we can do this with an XOR followed by a compare. But we need a scratch
11311 ;; register for the result of the XOR.
11314 [(set (match_operand:CC 0 "cc_reg_operand" "")
11315 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11316 (match_operand:SI 2 "non_short_cint_operand" "")))
11317 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
11318 "find_single_use (operands[0], insn, 0)
11319 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
11320 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
11321 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
11322 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
11325 /* Get the constant we are comparing against, C, and see what it looks like
11326 sign-extended to 16 bits. Then see what constant could be XOR'ed
11327 with C to get the sign-extended value. */
11329 HOST_WIDE_INT c = INTVAL (operands[2]);
11330 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11331 HOST_WIDE_INT xorv = c ^ sextc;
11333 operands[4] = GEN_INT (xorv);
11334 operands[5] = GEN_INT (sextc);
11337 (define_insn "*cmpsi_internal2"
11338 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11339 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11340 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11342 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11343 [(set_attr "type" "cmp")])
11345 (define_insn "*cmpdi_internal2"
11346 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11347 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11348 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11350 "cmpld%I2 %0,%1,%b2"
11351 [(set_attr "type" "cmp")])
11353 ;; The following two insns don't exist as single insns, but if we provide
11354 ;; them, we can swap an add and compare, which will enable us to overlap more
11355 ;; of the required delay between a compare and branch. We generate code for
11356 ;; them by splitting.
11359 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11360 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11361 (match_operand:SI 2 "short_cint_operand" "i")))
11362 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11363 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11366 [(set_attr "length" "8")])
11369 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11370 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11371 (match_operand:SI 2 "u_short_cint_operand" "i")))
11372 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11373 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11376 [(set_attr "length" "8")])
11379 [(set (match_operand:CC 3 "cc_reg_operand" "")
11380 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11381 (match_operand:SI 2 "short_cint_operand" "")))
11382 (set (match_operand:SI 0 "gpc_reg_operand" "")
11383 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11385 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11386 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11389 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11390 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11391 (match_operand:SI 2 "u_short_cint_operand" "")))
11392 (set (match_operand:SI 0 "gpc_reg_operand" "")
11393 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11395 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11396 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11398 (define_insn "*cmpsf_internal1"
11399 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11400 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11401 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11402 "TARGET_HARD_FLOAT && TARGET_FPRS"
11404 [(set_attr "type" "fpcompare")])
11406 (define_insn "*cmpdf_internal1"
11407 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11408 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11409 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11410 "TARGET_HARD_FLOAT && TARGET_FPRS"
11412 [(set_attr "type" "fpcompare")])
11414 ;; Only need to compare second words if first words equal
11415 (define_insn "*cmptf_internal1"
11416 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11417 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11418 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11419 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
11420 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11421 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11422 [(set_attr "type" "fpcompare")
11423 (set_attr "length" "12")])
11425 (define_insn_and_split "*cmptf_internal2"
11426 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11427 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11428 (match_operand:TF 2 "gpc_reg_operand" "f")))
11429 (clobber (match_scratch:DF 3 "=f"))
11430 (clobber (match_scratch:DF 4 "=f"))
11431 (clobber (match_scratch:DF 5 "=f"))
11432 (clobber (match_scratch:DF 6 "=f"))
11433 (clobber (match_scratch:DF 7 "=f"))
11434 (clobber (match_scratch:DF 8 "=f"))
11435 (clobber (match_scratch:DF 9 "=f"))
11436 (clobber (match_scratch:DF 10 "=f"))]
11437 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
11438 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11440 "&& reload_completed"
11441 [(set (match_dup 3) (match_dup 13))
11442 (set (match_dup 4) (match_dup 14))
11443 (set (match_dup 9) (abs:DF (match_dup 5)))
11444 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11445 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11446 (label_ref (match_dup 11))
11448 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11449 (set (pc) (label_ref (match_dup 12)))
11451 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11452 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11453 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11454 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11457 REAL_VALUE_TYPE rv;
11458 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11459 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11461 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11462 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11463 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11464 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11465 operands[11] = gen_label_rtx ();
11466 operands[12] = gen_label_rtx ();
11468 operands[13] = force_const_mem (DFmode,
11469 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11470 operands[14] = force_const_mem (DFmode,
11471 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11475 operands[13] = gen_const_mem (DFmode,
11476 create_TOC_reference (XEXP (operands[13], 0)));
11477 operands[14] = gen_const_mem (DFmode,
11478 create_TOC_reference (XEXP (operands[14], 0)));
11479 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11480 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11484 ;; Now we have the scc insns. We can do some combinations because of the
11485 ;; way the machine works.
11487 ;; Note that this is probably faster if we can put an insn between the
11488 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11489 ;; cases the insns below which don't use an intermediate CR field will
11490 ;; be used instead.
11492 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11493 (match_operator:SI 1 "scc_comparison_operator"
11494 [(match_operand 2 "cc_reg_operand" "y")
11497 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11498 [(set (attr "type")
11499 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11500 (const_string "mfcrf")
11502 (const_string "mfcr")))
11503 (set_attr "length" "8")])
11505 ;; Same as above, but get the GT bit.
11506 (define_insn "move_from_CR_gt_bit"
11507 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11508 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11510 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
11511 [(set_attr "type" "mfcr")
11512 (set_attr "length" "8")])
11514 ;; Same as above, but get the OV/ORDERED bit.
11515 (define_insn "move_from_CR_ov_bit"
11516 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11517 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11519 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11520 [(set_attr "type" "mfcr")
11521 (set_attr "length" "8")])
11524 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11525 (match_operator:DI 1 "scc_comparison_operator"
11526 [(match_operand 2 "cc_reg_operand" "y")
11529 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11530 [(set (attr "type")
11531 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11532 (const_string "mfcrf")
11534 (const_string "mfcr")))
11535 (set_attr "length" "8")])
11538 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11539 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11540 [(match_operand 2 "cc_reg_operand" "y,y")
11543 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11544 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11547 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11549 [(set_attr "type" "delayed_compare")
11550 (set_attr "length" "8,16")])
11553 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11554 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11555 [(match_operand 2 "cc_reg_operand" "")
11558 (set (match_operand:SI 3 "gpc_reg_operand" "")
11559 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11560 "TARGET_32BIT && reload_completed"
11561 [(set (match_dup 3)
11562 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11564 (compare:CC (match_dup 3)
11569 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11570 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11571 [(match_operand 2 "cc_reg_operand" "y")
11573 (match_operand:SI 3 "const_int_operand" "n")))]
11577 int is_bit = ccr_bit (operands[1], 1);
11578 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11581 if (is_bit >= put_bit)
11582 count = is_bit - put_bit;
11584 count = 32 - (put_bit - is_bit);
11586 operands[4] = GEN_INT (count);
11587 operands[5] = GEN_INT (put_bit);
11589 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11591 [(set (attr "type")
11592 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11593 (const_string "mfcrf")
11595 (const_string "mfcr")))
11596 (set_attr "length" "8")])
11599 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11601 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11602 [(match_operand 2 "cc_reg_operand" "y,y")
11604 (match_operand:SI 3 "const_int_operand" "n,n"))
11606 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11607 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11612 int is_bit = ccr_bit (operands[1], 1);
11613 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11616 /* Force split for non-cc0 compare. */
11617 if (which_alternative == 1)
11620 if (is_bit >= put_bit)
11621 count = is_bit - put_bit;
11623 count = 32 - (put_bit - is_bit);
11625 operands[5] = GEN_INT (count);
11626 operands[6] = GEN_INT (put_bit);
11628 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11630 [(set_attr "type" "delayed_compare")
11631 (set_attr "length" "8,16")])
11634 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11636 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11637 [(match_operand 2 "cc_reg_operand" "")
11639 (match_operand:SI 3 "const_int_operand" ""))
11641 (set (match_operand:SI 4 "gpc_reg_operand" "")
11642 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11645 [(set (match_dup 4)
11646 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11649 (compare:CC (match_dup 4)
11653 ;; There is a 3 cycle delay between consecutive mfcr instructions
11654 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11657 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11658 (match_operator:SI 1 "scc_comparison_operator"
11659 [(match_operand 2 "cc_reg_operand" "y")
11661 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11662 (match_operator:SI 4 "scc_comparison_operator"
11663 [(match_operand 5 "cc_reg_operand" "y")
11665 "REGNO (operands[2]) != REGNO (operands[5])"
11666 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11667 [(set_attr "type" "mfcr")
11668 (set_attr "length" "12")])
11671 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11672 (match_operator:DI 1 "scc_comparison_operator"
11673 [(match_operand 2 "cc_reg_operand" "y")
11675 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11676 (match_operator:DI 4 "scc_comparison_operator"
11677 [(match_operand 5 "cc_reg_operand" "y")
11679 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11680 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11681 [(set_attr "type" "mfcr")
11682 (set_attr "length" "12")])
11684 ;; There are some scc insns that can be done directly, without a compare.
11685 ;; These are faster because they don't involve the communications between
11686 ;; the FXU and branch units. In fact, we will be replacing all of the
11687 ;; integer scc insns here or in the portable methods in emit_store_flag.
11689 ;; Also support (neg (scc ..)) since that construct is used to replace
11690 ;; branches, (plus (scc ..) ..) since that construct is common and
11691 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11692 ;; cases where it is no more expensive than (neg (scc ..)).
11694 ;; Have reload force a constant into a register for the simple insns that
11695 ;; otherwise won't accept constants. We do this because it is faster than
11696 ;; the cmp/mfcr sequence we would otherwise generate.
11699 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11700 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11701 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11702 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11705 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11706 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11707 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11708 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11709 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11710 [(set_attr "type" "three,two,three,three,three")
11711 (set_attr "length" "12,8,12,12,12")])
11714 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11715 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11716 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11717 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
11720 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11721 subfic %3,%1,0\;adde %0,%3,%1
11722 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11723 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11724 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11725 [(set_attr "type" "three,two,three,three,three")
11726 (set_attr "length" "12,8,12,12,12")])
11729 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11731 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11732 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11734 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11735 (eq:SI (match_dup 1) (match_dup 2)))
11736 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11739 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11740 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11741 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11742 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11743 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11749 [(set_attr "type" "compare")
11750 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11753 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11755 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11756 (match_operand:SI 2 "reg_or_cint_operand" ""))
11758 (set (match_operand:SI 0 "gpc_reg_operand" "")
11759 (eq:SI (match_dup 1) (match_dup 2)))
11760 (clobber (match_scratch:SI 3 ""))]
11761 "TARGET_32BIT && reload_completed"
11762 [(parallel [(set (match_dup 0)
11763 (eq:SI (match_dup 1) (match_dup 2)))
11764 (clobber (match_dup 3))])
11766 (compare:CC (match_dup 0)
11771 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11773 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11774 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11776 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11777 (eq:DI (match_dup 1) (match_dup 2)))
11778 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11781 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11782 subfic %3,%1,0\;adde. %0,%3,%1
11783 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11784 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
11785 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11791 [(set_attr "type" "compare")
11792 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11795 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11797 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11798 (match_operand:DI 2 "reg_or_cint_operand" ""))
11800 (set (match_operand:DI 0 "gpc_reg_operand" "")
11801 (eq:DI (match_dup 1) (match_dup 2)))
11802 (clobber (match_scratch:DI 3 ""))]
11803 "TARGET_64BIT && reload_completed"
11804 [(parallel [(set (match_dup 0)
11805 (eq:DI (match_dup 1) (match_dup 2)))
11806 (clobber (match_dup 3))])
11808 (compare:CC (match_dup 0)
11812 ;; We have insns of the form shown by the first define_insn below. If
11813 ;; there is something inside the comparison operation, we must split it.
11815 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11816 (plus:SI (match_operator 1 "comparison_operator"
11817 [(match_operand:SI 2 "" "")
11818 (match_operand:SI 3
11819 "reg_or_cint_operand" "")])
11820 (match_operand:SI 4 "gpc_reg_operand" "")))
11821 (clobber (match_operand:SI 5 "register_operand" ""))]
11822 "! gpc_reg_operand (operands[2], SImode)"
11823 [(set (match_dup 5) (match_dup 2))
11824 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11828 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11829 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11830 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
11831 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11834 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11835 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11836 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11837 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11838 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11839 [(set_attr "type" "three,two,three,three,three")
11840 (set_attr "length" "12,8,12,12,12")])
11843 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11846 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11847 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11848 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11850 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11853 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11854 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11855 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11856 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11857 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11863 [(set_attr "type" "compare")
11864 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11867 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11870 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11871 (match_operand:SI 2 "reg_or_cint_operand" ""))
11872 (match_operand:SI 3 "gpc_reg_operand" ""))
11874 (clobber (match_scratch:SI 4 ""))]
11875 "TARGET_32BIT && reload_completed"
11876 [(set (match_dup 4)
11877 (plus:SI (eq:SI (match_dup 1)
11881 (compare:CC (match_dup 4)
11886 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11889 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11890 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11891 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11893 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11894 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11897 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11898 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11899 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11900 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11901 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11907 [(set_attr "type" "compare")
11908 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11911 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11914 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11915 (match_operand:SI 2 "reg_or_cint_operand" ""))
11916 (match_operand:SI 3 "gpc_reg_operand" ""))
11918 (set (match_operand:SI 0 "gpc_reg_operand" "")
11919 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11920 "TARGET_32BIT && reload_completed"
11921 [(set (match_dup 0)
11922 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11924 (compare:CC (match_dup 0)
11929 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11930 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11931 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
11934 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11935 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11936 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11937 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11938 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11939 [(set_attr "type" "three,two,three,three,three")
11940 (set_attr "length" "12,8,12,12,12")])
11942 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11943 ;; since it nabs/sr is just as fast.
11944 (define_insn "*ne0"
11945 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11946 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11948 (clobber (match_scratch:SI 2 "=&r"))]
11949 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11950 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11951 [(set_attr "type" "two")
11952 (set_attr "length" "8")])
11955 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11956 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11958 (clobber (match_scratch:DI 2 "=&r"))]
11960 "addic %2,%1,-1\;subfe %0,%2,%1"
11961 [(set_attr "type" "two")
11962 (set_attr "length" "8")])
11964 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11966 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11967 (plus:SI (lshiftrt:SI
11968 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11970 (match_operand:SI 2 "gpc_reg_operand" "r")))
11971 (clobber (match_scratch:SI 3 "=&r"))]
11973 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11974 [(set_attr "type" "two")
11975 (set_attr "length" "8")])
11978 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11979 (plus:DI (lshiftrt:DI
11980 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11982 (match_operand:DI 2 "gpc_reg_operand" "r")))
11983 (clobber (match_scratch:DI 3 "=&r"))]
11985 "addic %3,%1,-1\;addze %0,%2"
11986 [(set_attr "type" "two")
11987 (set_attr "length" "8")])
11990 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11992 (plus:SI (lshiftrt:SI
11993 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11995 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11997 (clobber (match_scratch:SI 3 "=&r,&r"))
11998 (clobber (match_scratch:SI 4 "=X,&r"))]
12001 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12003 [(set_attr "type" "compare")
12004 (set_attr "length" "8,12")])
12007 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12009 (plus:SI (lshiftrt:SI
12010 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12012 (match_operand:SI 2 "gpc_reg_operand" ""))
12014 (clobber (match_scratch:SI 3 ""))
12015 (clobber (match_scratch:SI 4 ""))]
12016 "TARGET_32BIT && reload_completed"
12017 [(parallel [(set (match_dup 3)
12018 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12021 (clobber (match_dup 4))])
12023 (compare:CC (match_dup 3)
12028 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12030 (plus:DI (lshiftrt:DI
12031 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12033 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12035 (clobber (match_scratch:DI 3 "=&r,&r"))]
12038 addic %3,%1,-1\;addze. %3,%2
12040 [(set_attr "type" "compare")
12041 (set_attr "length" "8,12")])
12044 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12046 (plus:DI (lshiftrt:DI
12047 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12049 (match_operand:DI 2 "gpc_reg_operand" ""))
12051 (clobber (match_scratch:DI 3 ""))]
12052 "TARGET_64BIT && reload_completed"
12053 [(set (match_dup 3)
12054 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12058 (compare:CC (match_dup 3)
12063 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12065 (plus:SI (lshiftrt:SI
12066 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12068 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12070 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12071 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12073 (clobber (match_scratch:SI 3 "=&r,&r"))]
12076 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12078 [(set_attr "type" "compare")
12079 (set_attr "length" "8,12")])
12082 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12084 (plus:SI (lshiftrt:SI
12085 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12087 (match_operand:SI 2 "gpc_reg_operand" ""))
12089 (set (match_operand:SI 0 "gpc_reg_operand" "")
12090 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12092 (clobber (match_scratch:SI 3 ""))]
12093 "TARGET_32BIT && reload_completed"
12094 [(parallel [(set (match_dup 0)
12095 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12097 (clobber (match_dup 3))])
12099 (compare:CC (match_dup 0)
12104 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12106 (plus:DI (lshiftrt:DI
12107 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12109 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12111 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12112 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12114 (clobber (match_scratch:DI 3 "=&r,&r"))]
12117 addic %3,%1,-1\;addze. %0,%2
12119 [(set_attr "type" "compare")
12120 (set_attr "length" "8,12")])
12123 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12125 (plus:DI (lshiftrt:DI
12126 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12128 (match_operand:DI 2 "gpc_reg_operand" ""))
12130 (set (match_operand:DI 0 "gpc_reg_operand" "")
12131 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12133 (clobber (match_scratch:DI 3 ""))]
12134 "TARGET_64BIT && reload_completed"
12135 [(parallel [(set (match_dup 0)
12136 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12138 (clobber (match_dup 3))])
12140 (compare:CC (match_dup 0)
12145 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12146 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12147 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12148 (clobber (match_scratch:SI 3 "=r,X"))]
12151 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12152 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12153 [(set_attr "length" "12")])
12156 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12158 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12159 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12161 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12162 (le:SI (match_dup 1) (match_dup 2)))
12163 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12166 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12167 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12170 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12171 (set_attr "length" "12,12,16,16")])
12174 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12176 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12177 (match_operand:SI 2 "reg_or_short_operand" ""))
12179 (set (match_operand:SI 0 "gpc_reg_operand" "")
12180 (le:SI (match_dup 1) (match_dup 2)))
12181 (clobber (match_scratch:SI 3 ""))]
12182 "TARGET_POWER && reload_completed"
12183 [(parallel [(set (match_dup 0)
12184 (le:SI (match_dup 1) (match_dup 2)))
12185 (clobber (match_dup 3))])
12187 (compare:CC (match_dup 0)
12192 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12193 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12194 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12195 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12198 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12199 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12200 [(set_attr "length" "12")])
12203 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12205 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12206 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12207 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12209 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12212 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12213 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12216 [(set_attr "type" "compare")
12217 (set_attr "length" "12,12,16,16")])
12220 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12222 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12223 (match_operand:SI 2 "reg_or_short_operand" ""))
12224 (match_operand:SI 3 "gpc_reg_operand" ""))
12226 (clobber (match_scratch:SI 4 ""))]
12227 "TARGET_POWER && reload_completed"
12228 [(set (match_dup 4)
12229 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12232 (compare:CC (match_dup 4)
12237 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12239 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12240 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12241 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12243 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12244 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12247 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12248 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12251 [(set_attr "type" "compare")
12252 (set_attr "length" "12,12,16,16")])
12255 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12257 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12258 (match_operand:SI 2 "reg_or_short_operand" ""))
12259 (match_operand:SI 3 "gpc_reg_operand" ""))
12261 (set (match_operand:SI 0 "gpc_reg_operand" "")
12262 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12263 "TARGET_POWER && reload_completed"
12264 [(set (match_dup 0)
12265 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12267 (compare:CC (match_dup 0)
12272 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12273 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12274 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12277 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12278 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12279 [(set_attr "length" "12")])
12282 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12283 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12284 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12286 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12287 [(set_attr "type" "three")
12288 (set_attr "length" "12")])
12291 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12292 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12293 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
12295 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12296 [(set_attr "type" "three")
12297 (set_attr "length" "12")])
12300 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12302 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12303 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12305 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12306 (leu:DI (match_dup 1) (match_dup 2)))]
12309 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12311 [(set_attr "type" "compare")
12312 (set_attr "length" "12,16")])
12315 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12317 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12318 (match_operand:DI 2 "reg_or_short_operand" ""))
12320 (set (match_operand:DI 0 "gpc_reg_operand" "")
12321 (leu:DI (match_dup 1) (match_dup 2)))]
12322 "TARGET_64BIT && reload_completed"
12323 [(set (match_dup 0)
12324 (leu:DI (match_dup 1) (match_dup 2)))
12326 (compare:CC (match_dup 0)
12331 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12333 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12334 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12336 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12337 (leu:SI (match_dup 1) (match_dup 2)))]
12340 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12342 [(set_attr "type" "compare")
12343 (set_attr "length" "12,16")])
12346 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12348 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12349 (match_operand:SI 2 "reg_or_short_operand" ""))
12351 (set (match_operand:SI 0 "gpc_reg_operand" "")
12352 (leu:SI (match_dup 1) (match_dup 2)))]
12353 "TARGET_32BIT && reload_completed"
12354 [(set (match_dup 0)
12355 (leu:SI (match_dup 1) (match_dup 2)))
12357 (compare:CC (match_dup 0)
12362 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12363 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12364 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12365 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12367 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12368 [(set_attr "type" "two")
12369 (set_attr "length" "8")])
12372 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12374 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12375 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12376 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12378 (clobber (match_scratch:SI 4 "=&r,&r"))]
12381 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12383 [(set_attr "type" "compare")
12384 (set_attr "length" "8,12")])
12387 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12389 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12390 (match_operand:SI 2 "reg_or_short_operand" ""))
12391 (match_operand:SI 3 "gpc_reg_operand" ""))
12393 (clobber (match_scratch:SI 4 ""))]
12394 "TARGET_32BIT && reload_completed"
12395 [(set (match_dup 4)
12396 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12399 (compare:CC (match_dup 4)
12404 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12406 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12407 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12408 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12410 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12411 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12414 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12416 [(set_attr "type" "compare")
12417 (set_attr "length" "8,12")])
12420 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12422 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12423 (match_operand:SI 2 "reg_or_short_operand" ""))
12424 (match_operand:SI 3 "gpc_reg_operand" ""))
12426 (set (match_operand:SI 0 "gpc_reg_operand" "")
12427 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12428 "TARGET_32BIT && reload_completed"
12429 [(set (match_dup 0)
12430 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12432 (compare:CC (match_dup 0)
12437 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12438 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12439 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12441 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12442 [(set_attr "type" "three")
12443 (set_attr "length" "12")])
12446 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12448 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12449 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12450 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12452 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12453 [(set_attr "type" "three")
12454 (set_attr "length" "12")])
12457 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12460 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12461 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12462 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12464 (clobber (match_scratch:SI 4 "=&r,&r"))]
12467 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12469 [(set_attr "type" "compare")
12470 (set_attr "length" "12,16")])
12473 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12476 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12477 (match_operand:SI 2 "reg_or_short_operand" "")))
12478 (match_operand:SI 3 "gpc_reg_operand" ""))
12480 (clobber (match_scratch:SI 4 ""))]
12481 "TARGET_32BIT && reload_completed"
12482 [(set (match_dup 4)
12483 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12486 (compare:CC (match_dup 4)
12491 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12494 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12495 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12496 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12498 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12499 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12502 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12504 [(set_attr "type" "compare")
12505 (set_attr "length" "12,16")])
12508 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12511 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12512 (match_operand:SI 2 "reg_or_short_operand" "")))
12513 (match_operand:SI 3 "gpc_reg_operand" ""))
12515 (set (match_operand:SI 0 "gpc_reg_operand" "")
12516 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12517 "TARGET_32BIT && reload_completed"
12518 [(set (match_dup 0)
12519 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12522 (compare:CC (match_dup 0)
12527 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12528 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12529 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12531 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12532 [(set_attr "length" "12")])
12535 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12537 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12538 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12540 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12541 (lt:SI (match_dup 1) (match_dup 2)))]
12544 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12546 [(set_attr "type" "delayed_compare")
12547 (set_attr "length" "12,16")])
12550 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12552 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12553 (match_operand:SI 2 "reg_or_short_operand" ""))
12555 (set (match_operand:SI 0 "gpc_reg_operand" "")
12556 (lt:SI (match_dup 1) (match_dup 2)))]
12557 "TARGET_POWER && reload_completed"
12558 [(set (match_dup 0)
12559 (lt:SI (match_dup 1) (match_dup 2)))
12561 (compare:CC (match_dup 0)
12566 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12567 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12568 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12569 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12571 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12572 [(set_attr "length" "12")])
12575 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12577 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12578 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12579 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12581 (clobber (match_scratch:SI 4 "=&r,&r"))]
12584 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12586 [(set_attr "type" "compare")
12587 (set_attr "length" "12,16")])
12590 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12592 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12593 (match_operand:SI 2 "reg_or_short_operand" ""))
12594 (match_operand:SI 3 "gpc_reg_operand" ""))
12596 (clobber (match_scratch:SI 4 ""))]
12597 "TARGET_POWER && reload_completed"
12598 [(set (match_dup 4)
12599 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12602 (compare:CC (match_dup 4)
12607 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12609 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12610 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12611 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12613 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12614 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12617 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12619 [(set_attr "type" "compare")
12620 (set_attr "length" "12,16")])
12623 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12625 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12626 (match_operand:SI 2 "reg_or_short_operand" ""))
12627 (match_operand:SI 3 "gpc_reg_operand" ""))
12629 (set (match_operand:SI 0 "gpc_reg_operand" "")
12630 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12631 "TARGET_POWER && reload_completed"
12632 [(set (match_dup 0)
12633 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12635 (compare:CC (match_dup 0)
12640 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12641 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12642 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12644 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12645 [(set_attr "length" "12")])
12647 (define_insn_and_split ""
12648 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12649 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12650 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12654 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12655 (set (match_dup 0) (neg:SI (match_dup 0)))]
12658 (define_insn_and_split ""
12659 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12660 (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12661 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12665 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12666 (set (match_dup 0) (neg:DI (match_dup 0)))]
12670 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12672 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12673 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12675 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12676 (ltu:SI (match_dup 1) (match_dup 2)))]
12679 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12680 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12683 [(set_attr "type" "compare")
12684 (set_attr "length" "12,12,16,16")])
12687 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12689 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12690 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12692 (set (match_operand:SI 0 "gpc_reg_operand" "")
12693 (ltu:SI (match_dup 1) (match_dup 2)))]
12694 "TARGET_32BIT && reload_completed"
12695 [(set (match_dup 0)
12696 (ltu:SI (match_dup 1) (match_dup 2)))
12698 (compare:CC (match_dup 0)
12702 (define_insn_and_split ""
12703 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
12704 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12705 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12706 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12709 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12710 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12711 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
12714 (define_insn_and_split ""
12715 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
12716 (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12717 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
12718 (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))]
12721 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12722 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12723 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
12727 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12729 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12730 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12731 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12733 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12736 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12737 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12740 [(set_attr "type" "compare")
12741 (set_attr "length" "12,12,16,16")])
12744 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12746 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12747 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12748 (match_operand:SI 3 "gpc_reg_operand" ""))
12750 (clobber (match_scratch:SI 4 ""))]
12751 "TARGET_32BIT && reload_completed"
12752 [(set (match_dup 4)
12753 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12756 (compare:CC (match_dup 4)
12761 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12763 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12764 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12765 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12767 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12768 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12771 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12772 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12775 [(set_attr "type" "compare")
12776 (set_attr "length" "12,12,16,16")])
12779 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12781 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12782 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12783 (match_operand:SI 3 "gpc_reg_operand" ""))
12785 (set (match_operand:SI 0 "gpc_reg_operand" "")
12786 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12787 "TARGET_32BIT && reload_completed"
12788 [(set (match_dup 0)
12789 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12791 (compare:CC (match_dup 0)
12796 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12797 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12798 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12801 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12802 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12803 [(set_attr "type" "two")
12804 (set_attr "length" "8")])
12807 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12808 (neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12809 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))]
12812 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12813 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12814 [(set_attr "type" "two")
12815 (set_attr "length" "8")])
12818 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12819 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12820 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12821 (clobber (match_scratch:SI 3 "=r"))]
12823 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12824 [(set_attr "length" "12")])
12827 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12829 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12830 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12832 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12833 (ge:SI (match_dup 1) (match_dup 2)))
12834 (clobber (match_scratch:SI 3 "=r,r"))]
12837 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12839 [(set_attr "type" "compare")
12840 (set_attr "length" "12,16")])
12843 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12845 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12846 (match_operand:SI 2 "reg_or_short_operand" ""))
12848 (set (match_operand:SI 0 "gpc_reg_operand" "")
12849 (ge:SI (match_dup 1) (match_dup 2)))
12850 (clobber (match_scratch:SI 3 ""))]
12851 "TARGET_POWER && reload_completed"
12852 [(parallel [(set (match_dup 0)
12853 (ge:SI (match_dup 1) (match_dup 2)))
12854 (clobber (match_dup 3))])
12856 (compare:CC (match_dup 0)
12861 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12862 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12863 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12864 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12866 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12867 [(set_attr "length" "12")])
12870 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12872 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12873 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12874 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12876 (clobber (match_scratch:SI 4 "=&r,&r"))]
12879 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12881 [(set_attr "type" "compare")
12882 (set_attr "length" "12,16")])
12885 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12887 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12888 (match_operand:SI 2 "reg_or_short_operand" ""))
12889 (match_operand:SI 3 "gpc_reg_operand" ""))
12891 (clobber (match_scratch:SI 4 ""))]
12892 "TARGET_POWER && reload_completed"
12893 [(set (match_dup 4)
12894 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12897 (compare:CC (match_dup 4)
12902 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12904 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12905 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12906 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12908 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12909 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12912 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12914 [(set_attr "type" "compare")
12915 (set_attr "length" "12,16")])
12918 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12920 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12921 (match_operand:SI 2 "reg_or_short_operand" ""))
12922 (match_operand:SI 3 "gpc_reg_operand" ""))
12924 (set (match_operand:SI 0 "gpc_reg_operand" "")
12925 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12926 "TARGET_POWER && reload_completed"
12927 [(set (match_dup 0)
12928 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12930 (compare:CC (match_dup 0)
12935 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12936 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12937 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12939 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12940 [(set_attr "length" "12")])
12943 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12944 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12945 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12948 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12949 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12950 [(set_attr "type" "three")
12951 (set_attr "length" "12")])
12954 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12955 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12956 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12959 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12960 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12961 [(set_attr "type" "three")
12962 (set_attr "length" "12")])
12965 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12967 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12968 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12970 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12971 (geu:SI (match_dup 1) (match_dup 2)))]
12974 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12975 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12978 [(set_attr "type" "compare")
12979 (set_attr "length" "12,12,16,16")])
12982 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12984 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12985 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12987 (set (match_operand:SI 0 "gpc_reg_operand" "")
12988 (geu:SI (match_dup 1) (match_dup 2)))]
12989 "TARGET_32BIT && reload_completed"
12990 [(set (match_dup 0)
12991 (geu:SI (match_dup 1) (match_dup 2)))
12993 (compare:CC (match_dup 0)
12998 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13000 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13001 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13003 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
13004 (geu:DI (match_dup 1) (match_dup 2)))]
13007 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
13008 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
13011 [(set_attr "type" "compare")
13012 (set_attr "length" "12,12,16,16")])
13015 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13017 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13018 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
13020 (set (match_operand:DI 0 "gpc_reg_operand" "")
13021 (geu:DI (match_dup 1) (match_dup 2)))]
13022 "TARGET_64BIT && reload_completed"
13023 [(set (match_dup 0)
13024 (geu:DI (match_dup 1) (match_dup 2)))
13026 (compare:CC (match_dup 0)
13031 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13032 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13033 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
13034 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13037 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13038 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13039 [(set_attr "type" "two")
13040 (set_attr "length" "8")])
13043 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13045 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13046 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13047 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13049 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13052 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13053 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13056 [(set_attr "type" "compare")
13057 (set_attr "length" "8,8,12,12")])
13060 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13062 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13063 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13064 (match_operand:SI 3 "gpc_reg_operand" ""))
13066 (clobber (match_scratch:SI 4 ""))]
13067 "TARGET_32BIT && reload_completed"
13068 [(set (match_dup 4)
13069 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13072 (compare:CC (match_dup 4)
13077 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13079 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13080 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13081 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13083 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13084 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13087 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13088 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13091 [(set_attr "type" "compare")
13092 (set_attr "length" "8,8,12,12")])
13095 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13097 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13098 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13099 (match_operand:SI 3 "gpc_reg_operand" ""))
13101 (set (match_operand:SI 0 "gpc_reg_operand" "")
13102 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13103 "TARGET_32BIT && reload_completed"
13104 [(set (match_dup 0)
13105 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13107 (compare:CC (match_dup 0)
13112 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13113 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13114 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
13117 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13118 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13119 [(set_attr "type" "three")
13120 (set_attr "length" "12")])
13123 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13125 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13126 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
13127 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13130 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13131 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13132 [(set_attr "type" "three")
13133 (set_attr "length" "12")])
13136 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13139 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13140 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13141 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13143 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13146 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13147 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13150 [(set_attr "type" "compare")
13151 (set_attr "length" "12,12,16,16")])
13154 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13157 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13158 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13159 (match_operand:SI 3 "gpc_reg_operand" ""))
13161 (clobber (match_scratch:SI 4 ""))]
13162 "TARGET_32BIT && reload_completed"
13163 [(set (match_dup 4)
13164 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13167 (compare:CC (match_dup 4)
13172 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13175 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13176 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13177 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13179 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13180 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13183 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13184 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13187 [(set_attr "type" "compare")
13188 (set_attr "length" "12,12,16,16")])
13191 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13194 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13195 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13196 (match_operand:SI 3 "gpc_reg_operand" ""))
13198 (set (match_operand:SI 0 "gpc_reg_operand" "")
13199 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13200 "TARGET_32BIT && reload_completed"
13201 [(set (match_dup 0)
13202 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13204 (compare:CC (match_dup 0)
13209 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13210 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13213 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
13214 [(set_attr "type" "three")
13215 (set_attr "length" "12")])
13218 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13219 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13222 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
13223 [(set_attr "type" "three")
13224 (set_attr "length" "12")])
13227 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13229 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13232 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13233 (gt:SI (match_dup 1) (const_int 0)))]
13236 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
13238 [(set_attr "type" "delayed_compare")
13239 (set_attr "length" "12,16")])
13242 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13244 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13247 (set (match_operand:SI 0 "gpc_reg_operand" "")
13248 (gt:SI (match_dup 1) (const_int 0)))]
13249 "TARGET_32BIT && reload_completed"
13250 [(set (match_dup 0)
13251 (gt:SI (match_dup 1) (const_int 0)))
13253 (compare:CC (match_dup 0)
13258 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13260 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13263 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13264 (gt:DI (match_dup 1) (const_int 0)))]
13267 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
13269 [(set_attr "type" "delayed_compare")
13270 (set_attr "length" "12,16")])
13273 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13275 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13278 (set (match_operand:DI 0 "gpc_reg_operand" "")
13279 (gt:DI (match_dup 1) (const_int 0)))]
13280 "TARGET_64BIT && reload_completed"
13281 [(set (match_dup 0)
13282 (gt:DI (match_dup 1) (const_int 0)))
13284 (compare:CC (match_dup 0)
13289 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13290 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13291 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13293 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13294 [(set_attr "length" "12")])
13297 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13299 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13300 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13302 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13303 (gt:SI (match_dup 1) (match_dup 2)))]
13306 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13308 [(set_attr "type" "delayed_compare")
13309 (set_attr "length" "12,16")])
13312 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13314 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13315 (match_operand:SI 2 "reg_or_short_operand" ""))
13317 (set (match_operand:SI 0 "gpc_reg_operand" "")
13318 (gt:SI (match_dup 1) (match_dup 2)))]
13319 "TARGET_POWER && reload_completed"
13320 [(set (match_dup 0)
13321 (gt:SI (match_dup 1) (match_dup 2)))
13323 (compare:CC (match_dup 0)
13328 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13329 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13331 (match_operand:SI 2 "gpc_reg_operand" "r")))]
13333 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13334 [(set_attr "type" "three")
13335 (set_attr "length" "12")])
13338 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13339 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13341 (match_operand:DI 2 "gpc_reg_operand" "r")))]
13343 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13344 [(set_attr "type" "three")
13345 (set_attr "length" "12")])
13348 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13350 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13352 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13354 (clobber (match_scratch:SI 3 "=&r,&r"))]
13357 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13359 [(set_attr "type" "compare")
13360 (set_attr "length" "12,16")])
13363 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13365 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13367 (match_operand:SI 2 "gpc_reg_operand" ""))
13369 (clobber (match_scratch:SI 3 ""))]
13370 "TARGET_32BIT && reload_completed"
13371 [(set (match_dup 3)
13372 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13375 (compare:CC (match_dup 3)
13380 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13382 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13384 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13386 (clobber (match_scratch:DI 3 "=&r,&r"))]
13389 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13391 [(set_attr "type" "compare")
13392 (set_attr "length" "12,16")])
13395 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13397 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13399 (match_operand:DI 2 "gpc_reg_operand" ""))
13401 (clobber (match_scratch:DI 3 ""))]
13402 "TARGET_64BIT && reload_completed"
13403 [(set (match_dup 3)
13404 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13407 (compare:CC (match_dup 3)
13412 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13414 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13416 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13418 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13419 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13422 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13424 [(set_attr "type" "compare")
13425 (set_attr "length" "12,16")])
13428 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13430 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13432 (match_operand:SI 2 "gpc_reg_operand" ""))
13434 (set (match_operand:SI 0 "gpc_reg_operand" "")
13435 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13436 "TARGET_32BIT && reload_completed"
13437 [(set (match_dup 0)
13438 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13440 (compare:CC (match_dup 0)
13445 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13447 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13449 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13451 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13452 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13455 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13457 [(set_attr "type" "compare")
13458 (set_attr "length" "12,16")])
13461 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13463 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13465 (match_operand:DI 2 "gpc_reg_operand" ""))
13467 (set (match_operand:DI 0 "gpc_reg_operand" "")
13468 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13469 "TARGET_64BIT && reload_completed"
13470 [(set (match_dup 0)
13471 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13473 (compare:CC (match_dup 0)
13478 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13479 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13480 (match_operand:SI 2 "reg_or_short_operand" "r"))
13481 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13483 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13484 [(set_attr "length" "12")])
13487 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13489 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13490 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13491 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13493 (clobber (match_scratch:SI 4 "=&r,&r"))]
13496 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13498 [(set_attr "type" "compare")
13499 (set_attr "length" "12,16")])
13502 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13504 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13505 (match_operand:SI 2 "reg_or_short_operand" ""))
13506 (match_operand:SI 3 "gpc_reg_operand" ""))
13508 (clobber (match_scratch:SI 4 ""))]
13509 "TARGET_POWER && reload_completed"
13510 [(set (match_dup 4)
13511 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13513 (compare:CC (match_dup 4)
13518 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13520 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13521 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13522 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13524 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13525 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13528 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13530 [(set_attr "type" "compare")
13531 (set_attr "length" "12,16")])
13534 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13536 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13537 (match_operand:SI 2 "reg_or_short_operand" ""))
13538 (match_operand:SI 3 "gpc_reg_operand" ""))
13540 (set (match_operand:SI 0 "gpc_reg_operand" "")
13541 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13542 "TARGET_POWER && reload_completed"
13543 [(set (match_dup 0)
13544 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13546 (compare:CC (match_dup 0)
13551 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13552 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13555 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13556 [(set_attr "type" "three")
13557 (set_attr "length" "12")])
13560 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13561 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13564 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13565 [(set_attr "type" "three")
13566 (set_attr "length" "12")])
13569 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13570 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13571 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13573 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13574 [(set_attr "length" "12")])
13576 (define_insn_and_split ""
13577 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13578 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13579 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13583 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13584 (set (match_dup 0) (neg:SI (match_dup 0)))]
13587 (define_insn_and_split ""
13588 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13589 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13590 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13594 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13595 (set (match_dup 0) (neg:DI (match_dup 0)))]
13599 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13601 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13602 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13604 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13605 (gtu:SI (match_dup 1) (match_dup 2)))]
13608 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13610 [(set_attr "type" "compare")
13611 (set_attr "length" "12,16")])
13614 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13616 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13617 (match_operand:SI 2 "reg_or_short_operand" ""))
13619 (set (match_operand:SI 0 "gpc_reg_operand" "")
13620 (gtu:SI (match_dup 1) (match_dup 2)))]
13621 "TARGET_32BIT && reload_completed"
13622 [(set (match_dup 0)
13623 (gtu:SI (match_dup 1) (match_dup 2)))
13625 (compare:CC (match_dup 0)
13630 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13632 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13633 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13635 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13636 (gtu:DI (match_dup 1) (match_dup 2)))]
13639 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13641 [(set_attr "type" "compare")
13642 (set_attr "length" "12,16")])
13645 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13647 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13648 (match_operand:DI 2 "reg_or_short_operand" ""))
13650 (set (match_operand:DI 0 "gpc_reg_operand" "")
13651 (gtu:DI (match_dup 1) (match_dup 2)))]
13652 "TARGET_64BIT && reload_completed"
13653 [(set (match_dup 0)
13654 (gtu:DI (match_dup 1) (match_dup 2)))
13656 (compare:CC (match_dup 0)
13660 (define_insn_and_split ""
13661 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13662 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13663 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13664 (match_operand:SI 3 "reg_or_short_operand" "rI")))]
13667 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13668 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13669 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
13672 (define_insn_and_split ""
13673 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13674 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13675 (match_operand:DI 2 "reg_or_short_operand" "rI"))
13676 (match_operand:DI 3 "reg_or_short_operand" "rI")))]
13679 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13680 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13681 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
13685 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13687 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13688 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13689 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13691 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13694 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13695 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
13698 [(set_attr "type" "compare")
13699 (set_attr "length" "8,12,12,16")])
13702 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13704 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13705 (match_operand:SI 2 "reg_or_short_operand" ""))
13706 (match_operand:SI 3 "gpc_reg_operand" ""))
13708 (clobber (match_scratch:SI 4 ""))]
13709 "TARGET_32BIT && reload_completed"
13710 [(set (match_dup 4)
13711 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13714 (compare:CC (match_dup 4)
13719 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13721 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13722 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13723 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13725 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13728 addic %4,%1,%k2\;addze. %4,%3
13729 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3
13732 [(set_attr "type" "compare")
13733 (set_attr "length" "8,12,12,16")])
13736 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13738 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13739 (match_operand:DI 2 "reg_or_short_operand" ""))
13740 (match_operand:DI 3 "gpc_reg_operand" ""))
13742 (clobber (match_scratch:DI 4 ""))]
13743 "TARGET_64BIT && reload_completed"
13744 [(set (match_dup 4)
13745 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13748 (compare:CC (match_dup 4)
13753 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13755 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13756 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13757 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13759 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13760 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13763 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13764 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
13767 [(set_attr "type" "compare")
13768 (set_attr "length" "8,12,12,16")])
13771 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13773 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13774 (match_operand:SI 2 "reg_or_short_operand" ""))
13775 (match_operand:SI 3 "gpc_reg_operand" ""))
13777 (set (match_operand:SI 0 "gpc_reg_operand" "")
13778 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13779 "TARGET_32BIT && reload_completed"
13780 [(set (match_dup 0)
13781 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13783 (compare:CC (match_dup 0)
13788 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13790 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13791 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13792 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13794 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13795 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13798 addic %0,%1,%k2\;addze. %0,%3
13799 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3
13802 [(set_attr "type" "compare")
13803 (set_attr "length" "8,12,12,16")])
13806 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13808 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13809 (match_operand:DI 2 "reg_or_short_operand" ""))
13810 (match_operand:DI 3 "gpc_reg_operand" ""))
13812 (set (match_operand:DI 0 "gpc_reg_operand" "")
13813 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13814 "TARGET_64BIT && reload_completed"
13815 [(set (match_dup 0)
13816 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13818 (compare:CC (match_dup 0)
13823 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13824 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13825 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13827 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13828 [(set_attr "type" "two")
13829 (set_attr "length" "8")])
13832 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13833 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13834 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13836 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13837 [(set_attr "type" "two")
13838 (set_attr "length" "8")])
13840 ;; Define both directions of branch and return. If we need a reload
13841 ;; register, we'd rather use CR0 since it is much easier to copy a
13842 ;; register CC value to there.
13846 (if_then_else (match_operator 1 "branch_comparison_operator"
13848 "cc_reg_operand" "y")
13850 (label_ref (match_operand 0 "" ""))
13855 return output_cbranch (operands[1], \"%l0\", 0, insn);
13857 [(set_attr "type" "branch")])
13861 (if_then_else (match_operator 0 "branch_comparison_operator"
13863 "cc_reg_operand" "y")
13870 return output_cbranch (operands[0], NULL, 0, insn);
13872 [(set_attr "type" "branch")
13873 (set_attr "length" "4")])
13877 (if_then_else (match_operator 1 "branch_comparison_operator"
13879 "cc_reg_operand" "y")
13882 (label_ref (match_operand 0 "" ""))))]
13886 return output_cbranch (operands[1], \"%l0\", 1, insn);
13888 [(set_attr "type" "branch")])
13892 (if_then_else (match_operator 0 "branch_comparison_operator"
13894 "cc_reg_operand" "y")
13901 return output_cbranch (operands[0], NULL, 1, insn);
13903 [(set_attr "type" "branch")
13904 (set_attr "length" "4")])
13906 ;; Logic on condition register values.
13908 ; This pattern matches things like
13909 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13910 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13912 ; which are generated by the branch logic.
13913 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13915 (define_insn "*cceq_ior_compare"
13916 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13917 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13918 [(match_operator:SI 2
13919 "branch_positive_comparison_operator"
13921 "cc_reg_operand" "y,y")
13923 (match_operator:SI 4
13924 "branch_positive_comparison_operator"
13926 "cc_reg_operand" "0,y")
13930 "cr%q1 %E0,%j2,%j4"
13931 [(set_attr "type" "cr_logical,delayed_cr")])
13933 ; Why is the constant -1 here, but 1 in the previous pattern?
13934 ; Because ~1 has all but the low bit set.
13936 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13937 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13938 [(not:SI (match_operator:SI 2
13939 "branch_positive_comparison_operator"
13941 "cc_reg_operand" "y,y")
13943 (match_operator:SI 4
13944 "branch_positive_comparison_operator"
13946 "cc_reg_operand" "0,y")
13950 "cr%q1 %E0,%j2,%j4"
13951 [(set_attr "type" "cr_logical,delayed_cr")])
13953 (define_insn "*cceq_rev_compare"
13954 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13955 (compare:CCEQ (match_operator:SI 1
13956 "branch_positive_comparison_operator"
13958 "cc_reg_operand" "0,y")
13962 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13963 [(set_attr "type" "cr_logical,delayed_cr")])
13965 ;; If we are comparing the result of two comparisons, this can be done
13966 ;; using creqv or crxor.
13968 (define_insn_and_split ""
13969 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13970 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13971 [(match_operand 2 "cc_reg_operand" "y")
13973 (match_operator 3 "branch_comparison_operator"
13974 [(match_operand 4 "cc_reg_operand" "y")
13979 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13983 int positive_1, positive_2;
13985 positive_1 = branch_positive_comparison_operator (operands[1],
13986 GET_MODE (operands[1]));
13987 positive_2 = branch_positive_comparison_operator (operands[3],
13988 GET_MODE (operands[3]));
13991 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13992 GET_CODE (operands[1])),
13994 operands[2], const0_rtx);
13995 else if (GET_MODE (operands[1]) != SImode)
13996 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13997 operands[2], const0_rtx);
14000 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14001 GET_CODE (operands[3])),
14003 operands[4], const0_rtx);
14004 else if (GET_MODE (operands[3]) != SImode)
14005 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14006 operands[4], const0_rtx);
14008 if (positive_1 == positive_2)
14010 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14011 operands[5] = constm1_rtx;
14015 operands[5] = const1_rtx;
14019 ;; Unconditional branch and return.
14021 (define_insn "jump"
14023 (label_ref (match_operand 0 "" "")))]
14026 [(set_attr "type" "branch")])
14028 (define_insn "return"
14032 [(set_attr "type" "jmpreg")])
14034 (define_expand "indirect_jump"
14035 [(set (pc) (match_operand 0 "register_operand" ""))]
14040 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
14042 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
14046 (define_insn "indirect_jumpsi"
14047 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
14052 [(set_attr "type" "jmpreg")])
14054 (define_insn "indirect_jumpdi"
14055 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
14060 [(set_attr "type" "jmpreg")])
14062 ;; Table jump for switch statements:
14063 (define_expand "tablejump"
14064 [(use (match_operand 0 "" ""))
14065 (use (label_ref (match_operand 1 "" "")))]
14070 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14072 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14076 (define_expand "tablejumpsi"
14077 [(set (match_dup 3)
14078 (plus:SI (match_operand:SI 0 "" "")
14080 (parallel [(set (pc) (match_dup 3))
14081 (use (label_ref (match_operand 1 "" "")))])]
14084 { operands[0] = force_reg (SImode, operands[0]);
14085 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14086 operands[3] = gen_reg_rtx (SImode);
14089 (define_expand "tablejumpdi"
14090 [(set (match_dup 4)
14091 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
14093 (plus:DI (match_dup 4)
14095 (parallel [(set (pc) (match_dup 3))
14096 (use (label_ref (match_operand 1 "" "")))])]
14099 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14100 operands[3] = gen_reg_rtx (DImode);
14101 operands[4] = gen_reg_rtx (DImode);
14106 (match_operand:SI 0 "register_operand" "c,*l"))
14107 (use (label_ref (match_operand 1 "" "")))]
14112 [(set_attr "type" "jmpreg")])
14116 (match_operand:DI 0 "register_operand" "c,*l"))
14117 (use (label_ref (match_operand 1 "" "")))]
14122 [(set_attr "type" "jmpreg")])
14127 "{cror 0,0,0|nop}")
14129 ;; Define the subtract-one-and-jump insns, starting with the template
14130 ;; so loop.c knows what to generate.
14132 (define_expand "doloop_end"
14133 [(use (match_operand 0 "" "")) ; loop pseudo
14134 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14135 (use (match_operand 2 "" "")) ; max iterations
14136 (use (match_operand 3 "" "")) ; loop level
14137 (use (match_operand 4 "" ""))] ; label
14141 /* Only use this on innermost loops. */
14142 if (INTVAL (operands[3]) > 1)
14146 if (GET_MODE (operands[0]) != DImode)
14148 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14152 if (GET_MODE (operands[0]) != SImode)
14154 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14159 (define_expand "ctrsi"
14160 [(parallel [(set (pc)
14161 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
14163 (label_ref (match_operand 1 "" ""))
14166 (plus:SI (match_dup 0)
14168 (clobber (match_scratch:CC 2 ""))
14169 (clobber (match_scratch:SI 3 ""))])]
14173 (define_expand "ctrdi"
14174 [(parallel [(set (pc)
14175 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
14177 (label_ref (match_operand 1 "" ""))
14180 (plus:DI (match_dup 0)
14182 (clobber (match_scratch:CC 2 ""))
14183 (clobber (match_scratch:DI 3 ""))])]
14187 ;; We need to be able to do this for any operand, including MEM, or we
14188 ;; will cause reload to blow up since we don't allow output reloads on
14190 ;; For the length attribute to be calculated correctly, the
14191 ;; label MUST be operand 0.
14193 (define_insn "*ctrsi_internal1"
14195 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14197 (label_ref (match_operand 0 "" ""))
14199 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14200 (plus:SI (match_dup 1)
14202 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14203 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14207 if (which_alternative != 0)
14209 else if (get_attr_length (insn) == 4)
14210 return \"{bdn|bdnz} %l0\";
14212 return \"bdz $+8\;b %l0\";
14214 [(set_attr "type" "branch")
14215 (set_attr "length" "*,12,16,16")])
14217 (define_insn "*ctrsi_internal2"
14219 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14222 (label_ref (match_operand 0 "" ""))))
14223 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14224 (plus:SI (match_dup 1)
14226 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14227 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14231 if (which_alternative != 0)
14233 else if (get_attr_length (insn) == 4)
14234 return \"bdz %l0\";
14236 return \"{bdn|bdnz} $+8\;b %l0\";
14238 [(set_attr "type" "branch")
14239 (set_attr "length" "*,12,16,16")])
14241 (define_insn "*ctrdi_internal1"
14243 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14245 (label_ref (match_operand 0 "" ""))
14247 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14248 (plus:DI (match_dup 1)
14250 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14251 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14255 if (which_alternative != 0)
14257 else if (get_attr_length (insn) == 4)
14258 return \"{bdn|bdnz} %l0\";
14260 return \"bdz $+8\;b %l0\";
14262 [(set_attr "type" "branch")
14263 (set_attr "length" "*,12,16,16")])
14265 (define_insn "*ctrdi_internal2"
14267 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14270 (label_ref (match_operand 0 "" ""))))
14271 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14272 (plus:DI (match_dup 1)
14274 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14275 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14279 if (which_alternative != 0)
14281 else if (get_attr_length (insn) == 4)
14282 return \"bdz %l0\";
14284 return \"{bdn|bdnz} $+8\;b %l0\";
14286 [(set_attr "type" "branch")
14287 (set_attr "length" "*,12,16,16")])
14289 ;; Similar but use EQ
14291 (define_insn "*ctrsi_internal5"
14293 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14295 (label_ref (match_operand 0 "" ""))
14297 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14298 (plus:SI (match_dup 1)
14300 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14301 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14305 if (which_alternative != 0)
14307 else if (get_attr_length (insn) == 4)
14308 return \"bdz %l0\";
14310 return \"{bdn|bdnz} $+8\;b %l0\";
14312 [(set_attr "type" "branch")
14313 (set_attr "length" "*,12,16,16")])
14315 (define_insn "*ctrsi_internal6"
14317 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14320 (label_ref (match_operand 0 "" ""))))
14321 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14322 (plus:SI (match_dup 1)
14324 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14325 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14329 if (which_alternative != 0)
14331 else if (get_attr_length (insn) == 4)
14332 return \"{bdn|bdnz} %l0\";
14334 return \"bdz $+8\;b %l0\";
14336 [(set_attr "type" "branch")
14337 (set_attr "length" "*,12,16,16")])
14339 (define_insn "*ctrdi_internal5"
14341 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14343 (label_ref (match_operand 0 "" ""))
14345 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14346 (plus:DI (match_dup 1)
14348 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14349 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14353 if (which_alternative != 0)
14355 else if (get_attr_length (insn) == 4)
14356 return \"bdz %l0\";
14358 return \"{bdn|bdnz} $+8\;b %l0\";
14360 [(set_attr "type" "branch")
14361 (set_attr "length" "*,12,16,16")])
14363 (define_insn "*ctrdi_internal6"
14365 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14368 (label_ref (match_operand 0 "" ""))))
14369 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14370 (plus:DI (match_dup 1)
14372 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14373 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14377 if (which_alternative != 0)
14379 else if (get_attr_length (insn) == 4)
14380 return \"{bdn|bdnz} %l0\";
14382 return \"bdz $+8\;b %l0\";
14384 [(set_attr "type" "branch")
14385 (set_attr "length" "*,12,16,16")])
14387 ;; Now the splitters if we could not allocate the CTR register
14391 (if_then_else (match_operator 2 "comparison_operator"
14392 [(match_operand:SI 1 "gpc_reg_operand" "")
14394 (match_operand 5 "" "")
14395 (match_operand 6 "" "")))
14396 (set (match_operand:SI 0 "gpc_reg_operand" "")
14397 (plus:SI (match_dup 1)
14399 (clobber (match_scratch:CC 3 ""))
14400 (clobber (match_scratch:SI 4 ""))]
14401 "TARGET_32BIT && reload_completed"
14402 [(parallel [(set (match_dup 3)
14403 (compare:CC (plus:SI (match_dup 1)
14407 (plus:SI (match_dup 1)
14409 (set (pc) (if_then_else (match_dup 7)
14413 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14414 operands[3], const0_rtx); }")
14418 (if_then_else (match_operator 2 "comparison_operator"
14419 [(match_operand:SI 1 "gpc_reg_operand" "")
14421 (match_operand 5 "" "")
14422 (match_operand 6 "" "")))
14423 (set (match_operand:SI 0 "nonimmediate_operand" "")
14424 (plus:SI (match_dup 1) (const_int -1)))
14425 (clobber (match_scratch:CC 3 ""))
14426 (clobber (match_scratch:SI 4 ""))]
14427 "TARGET_32BIT && reload_completed
14428 && ! gpc_reg_operand (operands[0], SImode)"
14429 [(parallel [(set (match_dup 3)
14430 (compare:CC (plus:SI (match_dup 1)
14434 (plus:SI (match_dup 1)
14438 (set (pc) (if_then_else (match_dup 7)
14442 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14443 operands[3], const0_rtx); }")
14446 (if_then_else (match_operator 2 "comparison_operator"
14447 [(match_operand:DI 1 "gpc_reg_operand" "")
14449 (match_operand 5 "" "")
14450 (match_operand 6 "" "")))
14451 (set (match_operand:DI 0 "gpc_reg_operand" "")
14452 (plus:DI (match_dup 1)
14454 (clobber (match_scratch:CC 3 ""))
14455 (clobber (match_scratch:DI 4 ""))]
14456 "TARGET_64BIT && reload_completed"
14457 [(parallel [(set (match_dup 3)
14458 (compare:CC (plus:DI (match_dup 1)
14462 (plus:DI (match_dup 1)
14464 (set (pc) (if_then_else (match_dup 7)
14468 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14469 operands[3], const0_rtx); }")
14473 (if_then_else (match_operator 2 "comparison_operator"
14474 [(match_operand:DI 1 "gpc_reg_operand" "")
14476 (match_operand 5 "" "")
14477 (match_operand 6 "" "")))
14478 (set (match_operand:DI 0 "nonimmediate_operand" "")
14479 (plus:DI (match_dup 1) (const_int -1)))
14480 (clobber (match_scratch:CC 3 ""))
14481 (clobber (match_scratch:DI 4 ""))]
14482 "TARGET_64BIT && reload_completed
14483 && ! gpc_reg_operand (operands[0], DImode)"
14484 [(parallel [(set (match_dup 3)
14485 (compare:CC (plus:DI (match_dup 1)
14489 (plus:DI (match_dup 1)
14493 (set (pc) (if_then_else (match_dup 7)
14497 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14498 operands[3], const0_rtx); }")
14500 (define_insn "trap"
14501 [(trap_if (const_int 1) (const_int 0))]
14505 (define_expand "conditional_trap"
14506 [(trap_if (match_operator 0 "trap_comparison_operator"
14507 [(match_dup 2) (match_dup 3)])
14508 (match_operand 1 "const_int_operand" ""))]
14510 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14511 operands[2] = rs6000_compare_op0;
14512 operands[3] = rs6000_compare_op1;")
14515 [(trap_if (match_operator 0 "trap_comparison_operator"
14516 [(match_operand:SI 1 "register_operand" "r")
14517 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14520 "{t|tw}%V0%I2 %1,%2")
14523 [(trap_if (match_operator 0 "trap_comparison_operator"
14524 [(match_operand:DI 1 "register_operand" "r")
14525 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14530 ;; Insns related to generating the function prologue and epilogue.
14532 (define_expand "prologue"
14533 [(use (const_int 0))]
14534 "TARGET_SCHED_PROLOG"
14537 rs6000_emit_prologue ();
14541 (define_insn "*movesi_from_cr_one"
14542 [(match_parallel 0 "mfcr_operation"
14543 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14544 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14545 (match_operand 3 "immediate_operand" "n")]
14546 UNSPEC_MOVESI_FROM_CR))])]
14552 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14554 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14555 operands[4] = GEN_INT (mask);
14556 output_asm_insn (\"mfcr %1,%4\", operands);
14560 [(set_attr "type" "mfcrf")])
14562 (define_insn "movesi_from_cr"
14563 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14564 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14565 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14566 UNSPEC_MOVESI_FROM_CR))]
14569 [(set_attr "type" "mfcr")])
14571 (define_insn "*stmw"
14572 [(match_parallel 0 "stmw_operation"
14573 [(set (match_operand:SI 1 "memory_operand" "=m")
14574 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14576 "{stm|stmw} %2,%1")
14578 (define_insn "*save_fpregs_si"
14579 [(match_parallel 0 "any_parallel_operand"
14580 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14581 (use (match_operand:SI 2 "call_operand" "s"))
14582 (set (match_operand:DF 3 "memory_operand" "=m")
14583 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14586 [(set_attr "type" "branch")
14587 (set_attr "length" "4")])
14589 (define_insn "*save_fpregs_di"
14590 [(match_parallel 0 "any_parallel_operand"
14591 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14592 (use (match_operand:DI 2 "call_operand" "s"))
14593 (set (match_operand:DF 3 "memory_operand" "=m")
14594 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14597 [(set_attr "type" "branch")
14598 (set_attr "length" "4")])
14600 ; These are to explain that changes to the stack pointer should
14601 ; not be moved over stores to stack memory.
14602 (define_insn "stack_tie"
14603 [(set (match_operand:BLK 0 "memory_operand" "+m")
14604 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14607 [(set_attr "length" "0")])
14610 (define_expand "epilogue"
14611 [(use (const_int 0))]
14612 "TARGET_SCHED_PROLOG"
14615 rs6000_emit_epilogue (FALSE);
14619 ; On some processors, doing the mtcrf one CC register at a time is
14620 ; faster (like on the 604e). On others, doing them all at once is
14621 ; faster; for instance, on the 601 and 750.
14623 (define_expand "movsi_to_cr_one"
14624 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14625 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14626 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14628 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14630 (define_insn "*movsi_to_cr"
14631 [(match_parallel 0 "mtcrf_operation"
14632 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14633 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14634 (match_operand 3 "immediate_operand" "n")]
14635 UNSPEC_MOVESI_TO_CR))])]
14641 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14642 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14643 operands[4] = GEN_INT (mask);
14644 return \"mtcrf %4,%2\";
14646 [(set_attr "type" "mtcr")])
14648 (define_insn "*mtcrfsi"
14649 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14650 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14651 (match_operand 2 "immediate_operand" "n")]
14652 UNSPEC_MOVESI_TO_CR))]
14653 "GET_CODE (operands[0]) == REG
14654 && CR_REGNO_P (REGNO (operands[0]))
14655 && GET_CODE (operands[2]) == CONST_INT
14656 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14658 [(set_attr "type" "mtcr")])
14660 ; The load-multiple instructions have similar properties.
14661 ; Note that "load_multiple" is a name known to the machine-independent
14662 ; code that actually corresponds to the powerpc load-string.
14664 (define_insn "*lmw"
14665 [(match_parallel 0 "lmw_operation"
14666 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14667 (match_operand:SI 2 "memory_operand" "m"))])]
14671 (define_insn "*return_internal_si"
14673 (use (match_operand:SI 0 "register_operand" "lc"))]
14676 [(set_attr "type" "jmpreg")])
14678 (define_insn "*return_internal_di"
14680 (use (match_operand:DI 0 "register_operand" "lc"))]
14683 [(set_attr "type" "jmpreg")])
14685 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14686 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14688 (define_insn "*return_and_restore_fpregs_si"
14689 [(match_parallel 0 "any_parallel_operand"
14691 (use (match_operand:SI 1 "register_operand" "l"))
14692 (use (match_operand:SI 2 "call_operand" "s"))
14693 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14694 (match_operand:DF 4 "memory_operand" "m"))])]
14698 (define_insn "*return_and_restore_fpregs_di"
14699 [(match_parallel 0 "any_parallel_operand"
14701 (use (match_operand:DI 1 "register_operand" "l"))
14702 (use (match_operand:DI 2 "call_operand" "s"))
14703 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14704 (match_operand:DF 4 "memory_operand" "m"))])]
14708 ; This is used in compiling the unwind routines.
14709 (define_expand "eh_return"
14710 [(use (match_operand 0 "general_operand" ""))]
14715 emit_insn (gen_eh_set_lr_si (operands[0]));
14717 emit_insn (gen_eh_set_lr_di (operands[0]));
14721 ; We can't expand this before we know where the link register is stored.
14722 (define_insn "eh_set_lr_si"
14723 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
14725 (clobber (match_scratch:SI 1 "=&b"))]
14729 (define_insn "eh_set_lr_di"
14730 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
14732 (clobber (match_scratch:DI 1 "=&b"))]
14737 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14738 (clobber (match_scratch 1 ""))]
14743 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14747 (define_insn "prefetch"
14748 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
14749 (match_operand:SI 1 "const_int_operand" "n")
14750 (match_operand:SI 2 "const_int_operand" "n"))]
14754 if (GET_CODE (operands[0]) == REG)
14755 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14756 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14758 [(set_attr "type" "load")])
14760 ; Atomic instructions
14762 (define_insn "memory_barrier"
14763 [(set (mem:BLK (match_scratch 0 "X"))
14764 (unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_SYNC))]
14768 (define_insn "sync_compare_and_swap<mode>"
14769 [(set (match_operand:GPR 1 "memory_operand" "+Z")
14770 (unspec:GPR [(match_dup 1)
14771 (match_operand:GPR 2 "reg_or_short_operand" "rI")
14772 (match_operand:GPR 3 "gpc_reg_operand" "r")]
14774 (set (match_operand:GPR 0 "gpc_reg_operand" "=&r") (match_dup 1))
14775 (set (mem:BLK (match_scratch 5 "X"))
14776 (unspec:BLK [(mem:BLK (match_scratch 6 "X"))] UNSPEC_SYNC))
14777 (clobber (match_scratch:CC 4 "=&x"))]
14779 "sync\n0:\t<larx> %0,%y1\n\t<cmp>%I2 %0,%2\n\tbne- 1f\n\t<stcx> %3,%y1\n\tbne- 0b\n\t1:\tisync"
14780 [(set_attr "length" "28")])
14782 (define_expand "sync_add<mode>"
14783 [(use (match_operand:INT1 0 "memory_operand" ""))
14784 (use (match_operand:INT1 1 "add_operand" ""))]
14788 rs6000_emit_sync (PLUS, <MODE>mode, operands[0], operands[1],
14789 NULL_RTX, NULL_RTX, true);
14793 (define_expand "sync_sub<mode>"
14794 [(use (match_operand:GPR 0 "memory_operand" ""))
14795 (use (match_operand:GPR 1 "gpc_reg_operand" ""))]
14799 rs6000_emit_sync (MINUS, <MODE>mode, operands[0], operands[1],
14800 NULL_RTX, NULL_RTX, true);
14804 (define_expand "sync_ior<mode>"
14805 [(use (match_operand:INT1 0 "memory_operand" ""))
14806 (use (match_operand:INT1 1 "logical_operand" ""))]
14810 rs6000_emit_sync (IOR, <MODE>mode, operands[0], operands[1],
14811 NULL_RTX, NULL_RTX, true);
14815 (define_expand "sync_and<mode>"
14816 [(use (match_operand:INT1 0 "memory_operand" ""))
14817 (use (match_operand:INT1 1 "and_operand" ""))]
14821 rs6000_emit_sync (AND, <MODE>mode, operands[0], operands[1],
14822 NULL_RTX, NULL_RTX, true);
14826 (define_expand "sync_xor<mode>"
14827 [(use (match_operand:INT1 0 "memory_operand" ""))
14828 (use (match_operand:INT1 1 "logical_operand" ""))]
14832 rs6000_emit_sync (XOR, <MODE>mode, operands[0], operands[1],
14833 NULL_RTX, NULL_RTX, true);
14837 (define_expand "sync_nand<mode>"
14838 [(use (match_operand:INT1 0 "memory_operand" ""))
14839 (use (match_operand:INT1 1 "gpc_reg_operand" ""))]
14843 rs6000_emit_sync (AND, <MODE>mode,
14844 gen_rtx_NOT (<MODE>mode, operands[0]),
14846 NULL_RTX, NULL_RTX, true);
14850 (define_expand "sync_old_add<mode>"
14851 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14852 (use (match_operand:INT1 1 "memory_operand" ""))
14853 (use (match_operand:INT1 2 "add_operand" ""))]
14857 rs6000_emit_sync (PLUS, <MODE>mode, operands[1], operands[2],
14858 operands[0], NULL_RTX, true);
14862 (define_expand "sync_old_sub<mode>"
14863 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
14864 (use (match_operand:GPR 1 "memory_operand" ""))
14865 (use (match_operand:GPR 2 "gpc_reg_operand" ""))]
14869 rs6000_emit_sync (MINUS, <MODE>mode, operands[1], operands[2],
14870 operands[0], NULL_RTX, true);
14874 (define_expand "sync_old_ior<mode>"
14875 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14876 (use (match_operand:INT1 1 "memory_operand" ""))
14877 (use (match_operand:INT1 2 "logical_operand" ""))]
14881 rs6000_emit_sync (IOR, <MODE>mode, operands[1], operands[2],
14882 operands[0], NULL_RTX, true);
14886 (define_expand "sync_old_and<mode>"
14887 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14888 (use (match_operand:INT1 1 "memory_operand" ""))
14889 (use (match_operand:INT1 2 "and_operand" ""))]
14893 rs6000_emit_sync (AND, <MODE>mode, operands[1], operands[2],
14894 operands[0], NULL_RTX, true);
14898 (define_expand "sync_old_xor<mode>"
14899 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14900 (use (match_operand:INT1 1 "memory_operand" ""))
14901 (use (match_operand:INT1 2 "logical_operand" ""))]
14905 rs6000_emit_sync (XOR, <MODE>mode, operands[1], operands[2],
14906 operands[0], NULL_RTX, true);
14910 (define_expand "sync_old_nand<mode>"
14911 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14912 (use (match_operand:INT1 1 "memory_operand" ""))
14913 (use (match_operand:INT1 2 "gpc_reg_operand" ""))]
14917 rs6000_emit_sync (AND, <MODE>mode,
14918 gen_rtx_NOT (<MODE>mode, operands[1]),
14920 operands[0], NULL_RTX, true);
14924 (define_expand "sync_new_add<mode>"
14925 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14926 (use (match_operand:INT1 1 "memory_operand" ""))
14927 (use (match_operand:INT1 2 "add_operand" ""))]
14931 rs6000_emit_sync (PLUS, <MODE>mode, operands[1], operands[2],
14932 NULL_RTX, operands[0], true);
14936 (define_expand "sync_new_sub<mode>"
14937 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
14938 (use (match_operand:GPR 1 "memory_operand" ""))
14939 (use (match_operand:GPR 2 "gpc_reg_operand" ""))]
14943 rs6000_emit_sync (MINUS, <MODE>mode, operands[1], operands[2],
14944 NULL_RTX, operands[0], true);
14948 (define_expand "sync_new_ior<mode>"
14949 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14950 (use (match_operand:INT1 1 "memory_operand" ""))
14951 (use (match_operand:INT1 2 "logical_operand" ""))]
14955 rs6000_emit_sync (IOR, <MODE>mode, operands[1], operands[2],
14956 NULL_RTX, operands[0], true);
14960 (define_expand "sync_new_and<mode>"
14961 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14962 (use (match_operand:INT1 1 "memory_operand" ""))
14963 (use (match_operand:INT1 2 "and_operand" ""))]
14967 rs6000_emit_sync (AND, <MODE>mode, operands[1], operands[2],
14968 NULL_RTX, operands[0], true);
14972 (define_expand "sync_new_xor<mode>"
14973 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14974 (use (match_operand:INT1 1 "memory_operand" ""))
14975 (use (match_operand:INT1 2 "logical_operand" ""))]
14979 rs6000_emit_sync (XOR, <MODE>mode, operands[1], operands[2],
14980 NULL_RTX, operands[0], true);
14984 (define_expand "sync_new_nand<mode>"
14985 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14986 (use (match_operand:INT1 1 "memory_operand" ""))
14987 (use (match_operand:INT1 2 "gpc_reg_operand" ""))]
14991 rs6000_emit_sync (AND, <MODE>mode,
14992 gen_rtx_NOT (<MODE>mode, operands[1]),
14994 NULL_RTX, operands[0], true);
14998 ; the sync_*_internal patterns all have these operands:
14999 ; 0 - memory location
15001 ; 2 - value in memory after operation
15002 ; 3 - value in memory immediately before operation
15004 (define_insn "*sync_add<mode>_internal"
15005 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r,&r")
15006 (plus:GPR (match_operand:GPR 0 "memory_operand" "+Z,Z")
15007 (match_operand:GPR 1 "add_operand" "rI,L")))
15008 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b,&b") (match_dup 0))
15010 (unspec:GPR [(plus:GPR (match_dup 0) (match_dup 1))]
15012 (clobber (match_scratch:CC 4 "=&x,&x"))]
15015 0:\t<larx> %3,%y0\n\tadd%I1 %2,%3,%1\n\t<stcx> %2,%y0\n\tbne- 0b
15016 0:\t<larx> %3,%y0\n\taddis %2,%3,%v1\n\t<stcx> %2,%y0\n\tbne- 0b"
15017 [(set_attr "length" "16,16")])
15019 (define_insn "*sync_addshort_internal"
15020 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r")
15021 (ior:SI (and:SI (plus:SI (match_operand:SI 0 "memory_operand" "+Z")
15022 (match_operand:SI 1 "add_operand" "rI"))
15023 (match_operand:SI 4 "gpc_reg_operand" "r"))
15024 (and:SI (not:SI (match_dup 4)) (match_dup 0))))
15025 (set (match_operand:SI 3 "gpc_reg_operand" "=&b") (match_dup 0))
15027 (unspec:SI [(ior:SI (and:SI (plus:SI (match_dup 0) (match_dup 1))
15029 (and:SI (not:SI (match_dup 4)) (match_dup 0)))]
15031 (clobber (match_scratch:CC 5 "=&x"))
15032 (clobber (match_scratch:SI 6 "=&r"))]
15034 "0:\tlwarx %3,%y0\n\tadd%I1 %2,%3,%1\n\tandc %6,%3,%4\n\tand %2,%2,%4\n\tor %2,%2,%6\n\tstwcx. %2,%y0\n\tbne- 0b"
15035 [(set_attr "length" "28")])
15037 (define_insn "*sync_sub<mode>_internal"
15038 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
15039 (minus:GPR (match_operand:GPR 0 "memory_operand" "+Z")
15040 (match_operand:GPR 1 "gpc_reg_operand" "r")))
15041 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
15043 (unspec:GPR [(minus:GPR (match_dup 0) (match_dup 1))]
15045 (clobber (match_scratch:CC 4 "=&x"))]
15047 "0:\t<larx> %3,%y0\n\tsubf %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- 0b"
15048 [(set_attr "length" "16")])
15050 (define_insn "*sync_andsi_internal"
15051 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r,&r,&r,&r")
15052 (and:SI (match_operand:SI 0 "memory_operand" "+Z,Z,Z,Z")
15053 (match_operand:SI 1 "and_operand" "r,T,K,L")))
15054 (set (match_operand:SI 3 "gpc_reg_operand" "=&b,&b,&b,&b") (match_dup 0))
15056 (unspec:SI [(and:SI (match_dup 0) (match_dup 1))]
15058 (clobber (match_scratch:CC 4 "=&x,&x,&x,&x"))]
15061 0:\tlwarx %3,%y0\n\tand %2,%3,%1\n\tstwcx. %2,%y0\n\tbne- 0b
15062 0:\tlwarx %3,%y0\n\trlwinm %2,%3,0,%m1,%M1\n\tstwcx. %2,%y0\n\tbne- 0b
15063 0:\tlwarx %3,%y0\n\tandi. %2,%3,%b1\n\tstwcx. %2,%y0\n\tbne- 0b
15064 0:\tlwarx %3,%y0\n\tandis. %2,%3,%u1\n\tstwcx. %2,%y0\n\tbne- 0b"
15065 [(set_attr "length" "16,16,16,16")])
15067 (define_insn "*sync_anddi_internal"
15068 [(set (match_operand:DI 2 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
15069 (and:DI (match_operand:DI 0 "memory_operand" "+Z,Z,Z,Z,Z")
15070 (match_operand:DI 1 "and_operand" "r,S,T,K,J")))
15071 (set (match_operand:DI 3 "gpc_reg_operand" "=&b,&b,&b,&b,&b") (match_dup 0))
15073 (unspec:DI [(and:DI (match_dup 0) (match_dup 1))]
15075 (clobber (match_scratch:CC 4 "=&x,&x,&x,&x,&x"))]
15078 0:\tldarx %3,%y0\n\tand %2,%3,%1\n\tstdcx. %2,%y0\n\tbne- 0b
15079 0:\tldarx %3,%y0\n\trldic%B1 %2,%3,0,%S1\n\tstdcx. %2,%y0\n\tbne- 0b
15080 0:\tldarx %3,%y0\n\trlwinm %2,%3,0,%m1,%M1\n\tstdcx. %2,%y0\n\tbne- 0b
15081 0:\tldarx %3,%y0\n\tandi. %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- 0b
15082 0:\tldarx %3,%y0\n\tandis. %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- 0b"
15083 [(set_attr "length" "16,16,16,16,16")])
15085 (define_insn "*sync_boolsi_internal"
15086 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r,&r,&r")
15087 (match_operator:SI 4 "boolean_or_operator"
15088 [(match_operand:SI 0 "memory_operand" "+Z,Z,Z")
15089 (match_operand:SI 1 "logical_operand" "r,K,L")]))
15090 (set (match_operand:SI 3 "gpc_reg_operand" "=&b,&b,&b") (match_dup 0))
15091 (set (match_dup 0) (unspec:SI [(match_dup 4)] UNSPEC_SYNC_OP))
15092 (clobber (match_scratch:CC 5 "=&x,&x,&x"))]
15095 0:\tlwarx %3,%y0\n\t%q4 %2,%3,%1\n\tstwcx. %2,%y0\n\tbne- 0b
15096 0:\tlwarx %3,%y0\n\t%q4i %2,%3,%b1\n\tstwcx. %2,%y0\n\tbne- 0b
15097 0:\tlwarx %3,%y0\n\t%q4is %2,%3,%u1\n\tstwcx. %2,%y0\n\tbne- 0b"
15098 [(set_attr "length" "16,16,16")])
15100 (define_insn "*sync_booldi_internal"
15101 [(set (match_operand:DI 2 "gpc_reg_operand" "=&r,&r,&r")
15102 (match_operator:DI 4 "boolean_or_operator"
15103 [(match_operand:DI 0 "memory_operand" "+Z,Z,Z")
15104 (match_operand:DI 1 "logical_operand" "r,K,JF")]))
15105 (set (match_operand:DI 3 "gpc_reg_operand" "=&b,&b,&b") (match_dup 0))
15106 (set (match_dup 0) (unspec:DI [(match_dup 4)] UNSPEC_SYNC_OP))
15107 (clobber (match_scratch:CC 5 "=&x,&x,&x"))]
15110 0:\tldarx %3,%y0\n\t%q4 %2,%3,%1\n\tstdcx. %2,%y0\n\tbne- 0b
15111 0:\tldarx %3,%y0\n\t%q4i %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- 0b
15112 0:\tldarx %3,%y0\n\t%q4is %2,%3,%u1\n\tstdcx. %2,%y0\n\tbne- 0b"
15113 [(set_attr "length" "16,16,16")])
15115 (define_insn "*sync_boolc<mode>_internal"
15116 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
15117 (match_operator:GPR 4 "boolean_operator"
15118 [(not:GPR (match_operand:GPR 0 "memory_operand" "+Z"))
15119 (match_operand:GPR 1 "gpc_reg_operand" "r")]))
15120 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
15121 (set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP))
15122 (clobber (match_scratch:CC 5 "=&x"))]
15124 "0:\t<larx> %3,%y0\n\t%q4 %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- 0b"
15125 [(set_attr "length" "16")])
15127 (define_insn "*sync_boolc<mode>_internal2"
15128 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
15129 (match_operator:GPR 4 "boolean_operator"
15130 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
15131 (match_operand:GPR 0 "memory_operand" "+Z")]))
15132 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
15133 (set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP))
15134 (clobber (match_scratch:CC 5 "=&x"))]
15136 "0:\t<larx> %3,%y0\n\t%q4 %2,%3,%1\n\t<stcx> %2,%y0\n\tbne- 0b"
15137 [(set_attr "length" "16")])
15139 (define_insn "*sync_boolcc<mode>_internal"
15140 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
15141 (match_operator:GPR 4 "boolean_operator"
15142 [(not:GPR (match_operand:GPR 0 "memory_operand" "+Z"))
15143 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))]))
15144 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
15145 (set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP))
15146 (clobber (match_scratch:CC 5 "=&x"))]
15148 "0:\t<larx> %3,%y0\n\t%q4 %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- 0b"
15149 [(set_attr "length" "16")])
15151 (define_insn "isync"
15152 [(set (mem:BLK (match_scratch 0 "X"))
15153 (unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_ISYNC))]
15157 (define_insn "sync_lock_test_and_set<mode>"
15158 [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r")
15159 (match_operand:GPR 1 "memory_operand" "+Z"))
15160 (set (match_dup 1) (unspec:GPR [(match_operand:GPR 2 "gpc_reg_operand" "r")]
15162 (clobber (match_scratch:CC 3 "=&x"))
15163 (set (mem:BLK (match_scratch 4 "X"))
15164 (unspec:BLK [(mem:BLK (match_scratch 5 "X"))] UNSPEC_ISYNC))]
15166 "0:\t<larx> %0,%y1\n\t<stcx> %2,%y1\n\tbne- 0b\n\tisync"
15167 [(set_attr "length" "16")])
15169 (define_expand "sync_lock_release<mode>"
15170 [(use (match_operand:INT 0 "memory_operand"))]
15174 emit_insn (gen_lwsync ());
15175 emit_move_insn (operands[0], CONST0_RTX (<MODE>mode));
15179 (define_insn "lwsync"
15180 [(set (mem:BLK (match_scratch 0 "X"))
15181 (unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_LWSYNC))]
15187 (include "altivec.md")