1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 2, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the
21 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 ;; MA 02110-1301, USA.
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
31 [(UNSPEC_FRSP 0) ; frsp for POWER machines
32 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
33 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
34 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
36 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
42 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
43 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
46 (UNSPEC_MOVESI_FROM_CR 19)
47 (UNSPEC_MOVESI_TO_CR 20)
49 (UNSPEC_TLSDTPRELHA 22)
50 (UNSPEC_TLSDTPRELLO 23)
51 (UNSPEC_TLSGOTDTPREL 24)
53 (UNSPEC_TLSTPRELHA 26)
54 (UNSPEC_TLSTPRELLO 27)
55 (UNSPEC_TLSGOTTPREL 28)
57 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
58 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
74 (UNSPEC_DLMZB_STRLEN 47)
78 ;; UNSPEC_VOLATILE usage
83 (UNSPECV_LL 1) ; load-locked
84 (UNSPECV_SC 2) ; store-conditional
85 (UNSPECV_EH_RR 9) ; eh_reg_restore
88 ;; Define an insn type attribute. This is used in function unit delay
90 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c"
91 (const_string "integer"))
94 ; '(pc)' in the following doesn't include the instruction itself; it is
95 ; calculated as if the instruction had zero size.
96 (define_attr "length" ""
97 (if_then_else (eq_attr "type" "branch")
98 (if_then_else (and (ge (minus (match_dup 0) (pc))
100 (lt (minus (match_dup 0) (pc))
106 ;; Processor type -- this attribute must exactly match the processor_type
107 ;; enumeration in rs6000.h.
109 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
110 (const (symbol_ref "rs6000_cpu_attr")))
112 (automata_option "ndfa")
125 (include "power4.md")
126 (include "power5.md")
128 (include "predicates.md")
129 (include "constraints.md")
131 (include "darwin.md")
136 ; This mode macro allows :GPR to be used to indicate the allowable size
137 ; of whole values in GPRs.
138 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
140 ; Any supported integer mode.
141 (define_mode_macro INT [QI HI SI DI TI])
143 ; Any supported integer mode that fits in one register.
144 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
146 ; extend modes for DImode
147 (define_mode_macro QHSI [QI HI SI])
149 ; SImode or DImode, even if DImode doesn't fit in GPRs.
150 (define_mode_macro SDI [SI DI])
152 ; The size of a pointer. Also, the size of the value that a record-condition
153 ; (one with a '.') will compare.
154 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
156 ; Any hardware-supported floating-point mode
157 (define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
158 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
159 (TF "!TARGET_IEEEQUAD
160 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")])
162 ; Various instructions that come in SI and DI forms.
163 ; A generic w/d attribute, for things like cmpw/cmpd.
164 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
167 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
170 ;; Start with fixed-point load and store insns. Here we put only the more
171 ;; complex forms. Basic data transfer is done later.
173 (define_expand "zero_extend<mode>di2"
174 [(set (match_operand:DI 0 "gpc_reg_operand" "")
175 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
179 (define_insn "*zero_extend<mode>di2_internal1"
180 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
181 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
185 rldicl %0,%1,0,<dbits>"
186 [(set_attr "type" "load,*")])
188 (define_insn "*zero_extend<mode>di2_internal2"
189 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
190 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
192 (clobber (match_scratch:DI 2 "=r,r"))]
195 rldicl. %2,%1,0,<dbits>
197 [(set_attr "type" "compare")
198 (set_attr "length" "4,8")])
201 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
202 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
204 (clobber (match_scratch:DI 2 ""))]
205 "TARGET_POWERPC64 && reload_completed"
207 (zero_extend:DI (match_dup 1)))
209 (compare:CC (match_dup 2)
213 (define_insn "*zero_extend<mode>di2_internal3"
214 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
215 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
217 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
218 (zero_extend:DI (match_dup 1)))]
221 rldicl. %0,%1,0,<dbits>
223 [(set_attr "type" "compare")
224 (set_attr "length" "4,8")])
227 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
228 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
230 (set (match_operand:DI 0 "gpc_reg_operand" "")
231 (zero_extend:DI (match_dup 1)))]
232 "TARGET_POWERPC64 && reload_completed"
234 (zero_extend:DI (match_dup 1)))
236 (compare:CC (match_dup 0)
240 (define_insn "extendqidi2"
241 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
242 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
247 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
248 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
250 (clobber (match_scratch:DI 2 "=r,r"))]
255 [(set_attr "type" "compare")
256 (set_attr "length" "4,8")])
259 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
260 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
262 (clobber (match_scratch:DI 2 ""))]
263 "TARGET_POWERPC64 && reload_completed"
265 (sign_extend:DI (match_dup 1)))
267 (compare:CC (match_dup 2)
272 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
273 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
275 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
276 (sign_extend:DI (match_dup 1)))]
281 [(set_attr "type" "compare")
282 (set_attr "length" "4,8")])
285 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
286 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
288 (set (match_operand:DI 0 "gpc_reg_operand" "")
289 (sign_extend:DI (match_dup 1)))]
290 "TARGET_POWERPC64 && reload_completed"
292 (sign_extend:DI (match_dup 1)))
294 (compare:CC (match_dup 0)
298 (define_expand "extendhidi2"
299 [(set (match_operand:DI 0 "gpc_reg_operand" "")
300 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
305 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
306 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
311 [(set_attr "type" "load_ext,*")])
314 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
315 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
317 (clobber (match_scratch:DI 2 "=r,r"))]
322 [(set_attr "type" "compare")
323 (set_attr "length" "4,8")])
326 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
327 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
329 (clobber (match_scratch:DI 2 ""))]
330 "TARGET_POWERPC64 && reload_completed"
332 (sign_extend:DI (match_dup 1)))
334 (compare:CC (match_dup 2)
339 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
340 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
342 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
343 (sign_extend:DI (match_dup 1)))]
348 [(set_attr "type" "compare")
349 (set_attr "length" "4,8")])
352 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
353 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
355 (set (match_operand:DI 0 "gpc_reg_operand" "")
356 (sign_extend:DI (match_dup 1)))]
357 "TARGET_POWERPC64 && reload_completed"
359 (sign_extend:DI (match_dup 1)))
361 (compare:CC (match_dup 0)
365 (define_expand "extendsidi2"
366 [(set (match_operand:DI 0 "gpc_reg_operand" "")
367 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
372 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
373 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
378 [(set_attr "type" "load_ext,*")])
381 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
382 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
384 (clobber (match_scratch:DI 2 "=r,r"))]
389 [(set_attr "type" "compare")
390 (set_attr "length" "4,8")])
393 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
394 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
396 (clobber (match_scratch:DI 2 ""))]
397 "TARGET_POWERPC64 && reload_completed"
399 (sign_extend:DI (match_dup 1)))
401 (compare:CC (match_dup 2)
406 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
407 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
409 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
410 (sign_extend:DI (match_dup 1)))]
415 [(set_attr "type" "compare")
416 (set_attr "length" "4,8")])
419 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
420 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
422 (set (match_operand:DI 0 "gpc_reg_operand" "")
423 (sign_extend:DI (match_dup 1)))]
424 "TARGET_POWERPC64 && reload_completed"
426 (sign_extend:DI (match_dup 1)))
428 (compare:CC (match_dup 0)
432 (define_expand "zero_extendqisi2"
433 [(set (match_operand:SI 0 "gpc_reg_operand" "")
434 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
439 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
440 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
444 {rlinm|rlwinm} %0,%1,0,0xff"
445 [(set_attr "type" "load,*")])
448 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
449 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
451 (clobber (match_scratch:SI 2 "=r,r"))]
454 {andil.|andi.} %2,%1,0xff
456 [(set_attr "type" "compare")
457 (set_attr "length" "4,8")])
460 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
461 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
463 (clobber (match_scratch:SI 2 ""))]
466 (zero_extend:SI (match_dup 1)))
468 (compare:CC (match_dup 2)
473 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
474 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
476 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
477 (zero_extend:SI (match_dup 1)))]
480 {andil.|andi.} %0,%1,0xff
482 [(set_attr "type" "compare")
483 (set_attr "length" "4,8")])
486 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
487 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
489 (set (match_operand:SI 0 "gpc_reg_operand" "")
490 (zero_extend:SI (match_dup 1)))]
493 (zero_extend:SI (match_dup 1)))
495 (compare:CC (match_dup 0)
499 (define_expand "extendqisi2"
500 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
501 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
506 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
507 else if (TARGET_POWER)
508 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
510 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
514 (define_insn "extendqisi2_ppc"
515 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
516 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
521 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
522 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
524 (clobber (match_scratch:SI 2 "=r,r"))]
529 [(set_attr "type" "compare")
530 (set_attr "length" "4,8")])
533 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
534 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
536 (clobber (match_scratch:SI 2 ""))]
537 "TARGET_POWERPC && reload_completed"
539 (sign_extend:SI (match_dup 1)))
541 (compare:CC (match_dup 2)
546 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
547 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
549 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
550 (sign_extend:SI (match_dup 1)))]
555 [(set_attr "type" "compare")
556 (set_attr "length" "4,8")])
559 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
560 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
562 (set (match_operand:SI 0 "gpc_reg_operand" "")
563 (sign_extend:SI (match_dup 1)))]
564 "TARGET_POWERPC && reload_completed"
566 (sign_extend:SI (match_dup 1)))
568 (compare:CC (match_dup 0)
572 (define_expand "extendqisi2_power"
573 [(parallel [(set (match_dup 2)
574 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
576 (clobber (scratch:SI))])
577 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
578 (ashiftrt:SI (match_dup 2)
580 (clobber (scratch:SI))])]
583 { operands[1] = gen_lowpart (SImode, operands[1]);
584 operands[2] = gen_reg_rtx (SImode); }")
586 (define_expand "extendqisi2_no_power"
588 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
590 (set (match_operand:SI 0 "gpc_reg_operand" "")
591 (ashiftrt:SI (match_dup 2)
593 "! TARGET_POWER && ! TARGET_POWERPC"
595 { operands[1] = gen_lowpart (SImode, operands[1]);
596 operands[2] = gen_reg_rtx (SImode); }")
598 (define_expand "zero_extendqihi2"
599 [(set (match_operand:HI 0 "gpc_reg_operand" "")
600 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
605 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
606 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
610 {rlinm|rlwinm} %0,%1,0,0xff"
611 [(set_attr "type" "load,*")])
614 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
615 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
617 (clobber (match_scratch:HI 2 "=r,r"))]
620 {andil.|andi.} %2,%1,0xff
622 [(set_attr "type" "compare")
623 (set_attr "length" "4,8")])
626 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
627 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
629 (clobber (match_scratch:HI 2 ""))]
632 (zero_extend:HI (match_dup 1)))
634 (compare:CC (match_dup 2)
639 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
640 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
642 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
643 (zero_extend:HI (match_dup 1)))]
646 {andil.|andi.} %0,%1,0xff
648 [(set_attr "type" "compare")
649 (set_attr "length" "4,8")])
652 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
653 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
655 (set (match_operand:HI 0 "gpc_reg_operand" "")
656 (zero_extend:HI (match_dup 1)))]
659 (zero_extend:HI (match_dup 1)))
661 (compare:CC (match_dup 0)
665 (define_expand "extendqihi2"
666 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
667 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
672 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
673 else if (TARGET_POWER)
674 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
676 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
680 (define_insn "extendqihi2_ppc"
681 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
682 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
687 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
688 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
690 (clobber (match_scratch:HI 2 "=r,r"))]
695 [(set_attr "type" "compare")
696 (set_attr "length" "4,8")])
699 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
700 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
702 (clobber (match_scratch:HI 2 ""))]
703 "TARGET_POWERPC && reload_completed"
705 (sign_extend:HI (match_dup 1)))
707 (compare:CC (match_dup 2)
712 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
713 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
715 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
716 (sign_extend:HI (match_dup 1)))]
721 [(set_attr "type" "compare")
722 (set_attr "length" "4,8")])
725 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
726 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
728 (set (match_operand:HI 0 "gpc_reg_operand" "")
729 (sign_extend:HI (match_dup 1)))]
730 "TARGET_POWERPC && reload_completed"
732 (sign_extend:HI (match_dup 1)))
734 (compare:CC (match_dup 0)
738 (define_expand "extendqihi2_power"
739 [(parallel [(set (match_dup 2)
740 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
742 (clobber (scratch:SI))])
743 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
744 (ashiftrt:SI (match_dup 2)
746 (clobber (scratch:SI))])]
749 { operands[0] = gen_lowpart (SImode, operands[0]);
750 operands[1] = gen_lowpart (SImode, operands[1]);
751 operands[2] = gen_reg_rtx (SImode); }")
753 (define_expand "extendqihi2_no_power"
755 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
757 (set (match_operand:HI 0 "gpc_reg_operand" "")
758 (ashiftrt:SI (match_dup 2)
760 "! TARGET_POWER && ! TARGET_POWERPC"
762 { operands[0] = gen_lowpart (SImode, operands[0]);
763 operands[1] = gen_lowpart (SImode, operands[1]);
764 operands[2] = gen_reg_rtx (SImode); }")
766 (define_expand "zero_extendhisi2"
767 [(set (match_operand:SI 0 "gpc_reg_operand" "")
768 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
773 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
774 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
778 {rlinm|rlwinm} %0,%1,0,0xffff"
779 [(set_attr "type" "load,*")])
782 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
783 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
785 (clobber (match_scratch:SI 2 "=r,r"))]
788 {andil.|andi.} %2,%1,0xffff
790 [(set_attr "type" "compare")
791 (set_attr "length" "4,8")])
794 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
795 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
797 (clobber (match_scratch:SI 2 ""))]
800 (zero_extend:SI (match_dup 1)))
802 (compare:CC (match_dup 2)
807 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
808 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
810 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
811 (zero_extend:SI (match_dup 1)))]
814 {andil.|andi.} %0,%1,0xffff
816 [(set_attr "type" "compare")
817 (set_attr "length" "4,8")])
820 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
821 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
823 (set (match_operand:SI 0 "gpc_reg_operand" "")
824 (zero_extend:SI (match_dup 1)))]
827 (zero_extend:SI (match_dup 1)))
829 (compare:CC (match_dup 0)
833 (define_expand "extendhisi2"
834 [(set (match_operand:SI 0 "gpc_reg_operand" "")
835 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
840 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
841 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
846 [(set_attr "type" "load_ext,*")])
849 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
850 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
852 (clobber (match_scratch:SI 2 "=r,r"))]
857 [(set_attr "type" "compare")
858 (set_attr "length" "4,8")])
861 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
862 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
864 (clobber (match_scratch:SI 2 ""))]
867 (sign_extend:SI (match_dup 1)))
869 (compare:CC (match_dup 2)
874 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
875 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
877 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
878 (sign_extend:SI (match_dup 1)))]
883 [(set_attr "type" "compare")
884 (set_attr "length" "4,8")])
886 ;; IBM 405 and 440 half-word multiplication operations.
888 (define_insn "*macchwc"
889 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
890 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
891 (match_operand:SI 2 "gpc_reg_operand" "r")
894 (match_operand:HI 1 "gpc_reg_operand" "r")))
895 (match_operand:SI 4 "gpc_reg_operand" "0"))
897 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
898 (plus:SI (mult:SI (ashiftrt:SI
906 [(set_attr "type" "imul3")])
908 (define_insn "*macchw"
909 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
910 (plus:SI (mult:SI (ashiftrt:SI
911 (match_operand:SI 2 "gpc_reg_operand" "r")
914 (match_operand:HI 1 "gpc_reg_operand" "r")))
915 (match_operand:SI 3 "gpc_reg_operand" "0")))]
918 [(set_attr "type" "imul3")])
920 (define_insn "*macchwuc"
921 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
922 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
923 (match_operand:SI 2 "gpc_reg_operand" "r")
926 (match_operand:HI 1 "gpc_reg_operand" "r")))
927 (match_operand:SI 4 "gpc_reg_operand" "0"))
929 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
930 (plus:SI (mult:SI (lshiftrt:SI
937 "macchwu. %0, %1, %2"
938 [(set_attr "type" "imul3")])
940 (define_insn "*macchwu"
941 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
942 (plus:SI (mult:SI (lshiftrt:SI
943 (match_operand:SI 2 "gpc_reg_operand" "r")
946 (match_operand:HI 1 "gpc_reg_operand" "r")))
947 (match_operand:SI 3 "gpc_reg_operand" "0")))]
950 [(set_attr "type" "imul3")])
952 (define_insn "*machhwc"
953 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
954 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
955 (match_operand:SI 1 "gpc_reg_operand" "%r")
958 (match_operand:SI 2 "gpc_reg_operand" "r")
960 (match_operand:SI 4 "gpc_reg_operand" "0"))
962 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
963 (plus:SI (mult:SI (ashiftrt:SI
972 [(set_attr "type" "imul3")])
974 (define_insn "*machhw"
975 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
976 (plus:SI (mult:SI (ashiftrt:SI
977 (match_operand:SI 1 "gpc_reg_operand" "%r")
980 (match_operand:SI 2 "gpc_reg_operand" "r")
982 (match_operand:SI 3 "gpc_reg_operand" "0")))]
985 [(set_attr "type" "imul3")])
987 (define_insn "*machhwuc"
988 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
989 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
990 (match_operand:SI 1 "gpc_reg_operand" "%r")
993 (match_operand:SI 2 "gpc_reg_operand" "r")
995 (match_operand:SI 4 "gpc_reg_operand" "0"))
997 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
998 (plus:SI (mult:SI (lshiftrt:SI
1006 "machhwu. %0, %1, %2"
1007 [(set_attr "type" "imul3")])
1009 (define_insn "*machhwu"
1010 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1011 (plus:SI (mult:SI (lshiftrt:SI
1012 (match_operand:SI 1 "gpc_reg_operand" "%r")
1015 (match_operand:SI 2 "gpc_reg_operand" "r")
1017 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1019 "machhwu %0, %1, %2"
1020 [(set_attr "type" "imul3")])
1022 (define_insn "*maclhwc"
1023 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1024 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1025 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1027 (match_operand:HI 2 "gpc_reg_operand" "r")))
1028 (match_operand:SI 4 "gpc_reg_operand" "0"))
1030 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1031 (plus:SI (mult:SI (sign_extend:SI
1037 "maclhw. %0, %1, %2"
1038 [(set_attr "type" "imul3")])
1040 (define_insn "*maclhw"
1041 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1042 (plus:SI (mult:SI (sign_extend:SI
1043 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1045 (match_operand:HI 2 "gpc_reg_operand" "r")))
1046 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1049 [(set_attr "type" "imul3")])
1051 (define_insn "*maclhwuc"
1052 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1053 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1054 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1056 (match_operand:HI 2 "gpc_reg_operand" "r")))
1057 (match_operand:SI 4 "gpc_reg_operand" "0"))
1059 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1060 (plus:SI (mult:SI (zero_extend:SI
1066 "maclhwu. %0, %1, %2"
1067 [(set_attr "type" "imul3")])
1069 (define_insn "*maclhwu"
1070 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1071 (plus:SI (mult:SI (zero_extend:SI
1072 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1074 (match_operand:HI 2 "gpc_reg_operand" "r")))
1075 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1077 "maclhwu %0, %1, %2"
1078 [(set_attr "type" "imul3")])
1080 (define_insn "*nmacchwc"
1081 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1082 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1083 (mult:SI (ashiftrt:SI
1084 (match_operand:SI 2 "gpc_reg_operand" "r")
1087 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1089 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1090 (minus:SI (match_dup 4)
1091 (mult:SI (ashiftrt:SI
1097 "nmacchw. %0, %1, %2"
1098 [(set_attr "type" "imul3")])
1100 (define_insn "*nmacchw"
1101 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1102 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1103 (mult:SI (ashiftrt:SI
1104 (match_operand:SI 2 "gpc_reg_operand" "r")
1107 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1109 "nmacchw %0, %1, %2"
1110 [(set_attr "type" "imul3")])
1112 (define_insn "*nmachhwc"
1113 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1114 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1115 (mult:SI (ashiftrt:SI
1116 (match_operand:SI 1 "gpc_reg_operand" "%r")
1119 (match_operand:SI 2 "gpc_reg_operand" "r")
1122 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1123 (minus:SI (match_dup 4)
1124 (mult:SI (ashiftrt:SI
1131 "nmachhw. %0, %1, %2"
1132 [(set_attr "type" "imul3")])
1134 (define_insn "*nmachhw"
1135 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1136 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1137 (mult:SI (ashiftrt:SI
1138 (match_operand:SI 1 "gpc_reg_operand" "%r")
1141 (match_operand:SI 2 "gpc_reg_operand" "r")
1144 "nmachhw %0, %1, %2"
1145 [(set_attr "type" "imul3")])
1147 (define_insn "*nmaclhwc"
1148 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1149 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1150 (mult:SI (sign_extend:SI
1151 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1153 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1155 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1156 (minus:SI (match_dup 4)
1157 (mult:SI (sign_extend:SI
1162 "nmaclhw. %0, %1, %2"
1163 [(set_attr "type" "imul3")])
1165 (define_insn "*nmaclhw"
1166 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1167 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1168 (mult:SI (sign_extend:SI
1169 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1171 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1173 "nmaclhw %0, %1, %2"
1174 [(set_attr "type" "imul3")])
1176 (define_insn "*mulchwc"
1177 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1178 (compare:CC (mult:SI (ashiftrt:SI
1179 (match_operand:SI 2 "gpc_reg_operand" "r")
1182 (match_operand:HI 1 "gpc_reg_operand" "r")))
1184 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1185 (mult:SI (ashiftrt:SI
1191 "mulchw. %0, %1, %2"
1192 [(set_attr "type" "imul3")])
1194 (define_insn "*mulchw"
1195 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1196 (mult:SI (ashiftrt:SI
1197 (match_operand:SI 2 "gpc_reg_operand" "r")
1200 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1203 [(set_attr "type" "imul3")])
1205 (define_insn "*mulchwuc"
1206 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1207 (compare:CC (mult:SI (lshiftrt:SI
1208 (match_operand:SI 2 "gpc_reg_operand" "r")
1211 (match_operand:HI 1 "gpc_reg_operand" "r")))
1213 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1214 (mult:SI (lshiftrt:SI
1220 "mulchwu. %0, %1, %2"
1221 [(set_attr "type" "imul3")])
1223 (define_insn "*mulchwu"
1224 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1225 (mult:SI (lshiftrt:SI
1226 (match_operand:SI 2 "gpc_reg_operand" "r")
1229 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1231 "mulchwu %0, %1, %2"
1232 [(set_attr "type" "imul3")])
1234 (define_insn "*mulhhwc"
1235 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1236 (compare:CC (mult:SI (ashiftrt:SI
1237 (match_operand:SI 1 "gpc_reg_operand" "%r")
1240 (match_operand:SI 2 "gpc_reg_operand" "r")
1243 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1244 (mult:SI (ashiftrt:SI
1251 "mulhhw. %0, %1, %2"
1252 [(set_attr "type" "imul3")])
1254 (define_insn "*mulhhw"
1255 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1256 (mult:SI (ashiftrt:SI
1257 (match_operand:SI 1 "gpc_reg_operand" "%r")
1260 (match_operand:SI 2 "gpc_reg_operand" "r")
1264 [(set_attr "type" "imul3")])
1266 (define_insn "*mulhhwuc"
1267 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1268 (compare:CC (mult:SI (lshiftrt:SI
1269 (match_operand:SI 1 "gpc_reg_operand" "%r")
1272 (match_operand:SI 2 "gpc_reg_operand" "r")
1275 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1276 (mult:SI (lshiftrt:SI
1283 "mulhhwu. %0, %1, %2"
1284 [(set_attr "type" "imul3")])
1286 (define_insn "*mulhhwu"
1287 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1288 (mult:SI (lshiftrt:SI
1289 (match_operand:SI 1 "gpc_reg_operand" "%r")
1292 (match_operand:SI 2 "gpc_reg_operand" "r")
1295 "mulhhwu %0, %1, %2"
1296 [(set_attr "type" "imul3")])
1298 (define_insn "*mullhwc"
1299 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1300 (compare:CC (mult:SI (sign_extend:SI
1301 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1303 (match_operand:HI 2 "gpc_reg_operand" "r")))
1305 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1306 (mult:SI (sign_extend:SI
1311 "mullhw. %0, %1, %2"
1312 [(set_attr "type" "imul3")])
1314 (define_insn "*mullhw"
1315 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1316 (mult:SI (sign_extend:SI
1317 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1319 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1322 [(set_attr "type" "imul3")])
1324 (define_insn "*mullhwuc"
1325 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1326 (compare:CC (mult:SI (zero_extend:SI
1327 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1329 (match_operand:HI 2 "gpc_reg_operand" "r")))
1331 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1332 (mult:SI (zero_extend:SI
1337 "mullhwu. %0, %1, %2"
1338 [(set_attr "type" "imul3")])
1340 (define_insn "*mullhwu"
1341 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1342 (mult:SI (zero_extend:SI
1343 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1345 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1347 "mullhwu %0, %1, %2"
1348 [(set_attr "type" "imul3")])
1350 ;; IBM 405 and 440 string-search dlmzb instruction support.
1351 (define_insn "dlmzb"
1352 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1353 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1354 (match_operand:SI 2 "gpc_reg_operand" "r")]
1356 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1357 (unspec:SI [(match_dup 1)
1361 "dlmzb. %0, %1, %2")
1363 (define_expand "strlensi"
1364 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1365 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1366 (match_operand:QI 2 "const_int_operand" "")
1367 (match_operand 3 "const_int_operand" "")]
1368 UNSPEC_DLMZB_STRLEN))
1369 (clobber (match_scratch:CC 4 "=x"))]
1370 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1372 rtx result = operands[0];
1373 rtx src = operands[1];
1374 rtx search_char = operands[2];
1375 rtx align = operands[3];
1376 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1377 rtx loop_label, end_label, mem, cr0, cond;
1378 if (search_char != const0_rtx
1379 || GET_CODE (align) != CONST_INT
1380 || INTVAL (align) < 8)
1382 word1 = gen_reg_rtx (SImode);
1383 word2 = gen_reg_rtx (SImode);
1384 scratch_dlmzb = gen_reg_rtx (SImode);
1385 scratch_string = gen_reg_rtx (Pmode);
1386 loop_label = gen_label_rtx ();
1387 end_label = gen_label_rtx ();
1388 addr = force_reg (Pmode, XEXP (src, 0));
1389 emit_move_insn (scratch_string, addr);
1390 emit_label (loop_label);
1391 mem = change_address (src, SImode, scratch_string);
1392 emit_move_insn (word1, mem);
1393 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1394 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1395 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1396 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1397 emit_jump_insn (gen_rtx_SET (VOIDmode,
1399 gen_rtx_IF_THEN_ELSE (VOIDmode,
1405 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1406 emit_jump_insn (gen_rtx_SET (VOIDmode,
1408 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1410 emit_label (end_label);
1411 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1412 emit_insn (gen_subsi3 (result, scratch_string, addr));
1413 emit_insn (gen_subsi3 (result, result, const1_rtx));
1418 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1419 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1421 (set (match_operand:SI 0 "gpc_reg_operand" "")
1422 (sign_extend:SI (match_dup 1)))]
1425 (sign_extend:SI (match_dup 1)))
1427 (compare:CC (match_dup 0)
1431 ;; Fixed-point arithmetic insns.
1433 (define_expand "add<mode>3"
1434 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1435 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1436 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1439 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1441 if (non_short_cint_operand (operands[2], DImode))
1444 else if (GET_CODE (operands[2]) == CONST_INT
1445 && ! add_operand (operands[2], <MODE>mode))
1447 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1448 ? operands[0] : gen_reg_rtx (<MODE>mode));
1450 HOST_WIDE_INT val = INTVAL (operands[2]);
1451 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1452 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1454 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1457 /* The ordering here is important for the prolog expander.
1458 When space is allocated from the stack, adding 'low' first may
1459 produce a temporary deallocation (which would be bad). */
1460 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1461 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1466 ;; Discourage ai/addic because of carry but provide it in an alternative
1467 ;; allowing register zero as source.
1468 (define_insn "*add<mode>3_internal1"
1469 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1470 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1471 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1475 {cal %0,%2(%1)|addi %0,%1,%2}
1477 {cau|addis} %0,%1,%v2"
1478 [(set_attr "length" "4,4,4,4")])
1480 (define_insn "addsi3_high"
1481 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1482 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1483 (high:SI (match_operand 2 "" ""))))]
1484 "TARGET_MACHO && !TARGET_64BIT"
1485 "{cau|addis} %0,%1,ha16(%2)"
1486 [(set_attr "length" "4")])
1488 (define_insn "*add<mode>3_internal2"
1489 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1490 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1491 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1493 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1496 {cax.|add.} %3,%1,%2
1497 {ai.|addic.} %3,%1,%2
1500 [(set_attr "type" "fast_compare,compare,compare,compare")
1501 (set_attr "length" "4,4,8,8")])
1504 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1505 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1506 (match_operand:GPR 2 "reg_or_short_operand" ""))
1508 (clobber (match_scratch:GPR 3 ""))]
1511 (plus:GPR (match_dup 1)
1514 (compare:CC (match_dup 3)
1518 (define_insn "*add<mode>3_internal3"
1519 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1520 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1521 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1523 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1524 (plus:P (match_dup 1)
1528 {cax.|add.} %0,%1,%2
1529 {ai.|addic.} %0,%1,%2
1532 [(set_attr "type" "fast_compare,compare,compare,compare")
1533 (set_attr "length" "4,4,8,8")])
1536 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1537 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1538 (match_operand:P 2 "reg_or_short_operand" ""))
1540 (set (match_operand:P 0 "gpc_reg_operand" "")
1541 (plus:P (match_dup 1) (match_dup 2)))]
1544 (plus:P (match_dup 1)
1547 (compare:CC (match_dup 0)
1551 ;; Split an add that we can't do in one insn into two insns, each of which
1552 ;; does one 16-bit part. This is used by combine. Note that the low-order
1553 ;; add should be last in case the result gets used in an address.
1556 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1557 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1558 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1560 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1561 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1563 HOST_WIDE_INT val = INTVAL (operands[2]);
1564 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1565 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1567 operands[4] = GEN_INT (low);
1568 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1569 operands[3] = GEN_INT (rest);
1570 else if (! no_new_pseudos)
1572 operands[3] = gen_reg_rtx (DImode);
1573 emit_move_insn (operands[3], operands[2]);
1574 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1581 (define_insn "one_cmpl<mode>2"
1582 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1583 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1588 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1589 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1591 (clobber (match_scratch:P 2 "=r,r"))]
1596 [(set_attr "type" "compare")
1597 (set_attr "length" "4,8")])
1600 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1601 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1603 (clobber (match_scratch:P 2 ""))]
1606 (not:P (match_dup 1)))
1608 (compare:CC (match_dup 2)
1613 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1614 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1616 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1617 (not:P (match_dup 1)))]
1622 [(set_attr "type" "compare")
1623 (set_attr "length" "4,8")])
1626 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1627 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1629 (set (match_operand:P 0 "gpc_reg_operand" "")
1630 (not:P (match_dup 1)))]
1633 (not:P (match_dup 1)))
1635 (compare:CC (match_dup 0)
1640 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1641 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1642 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1644 "{sf%I1|subf%I1c} %0,%2,%1")
1647 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1648 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1649 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1656 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1657 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1658 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1660 (clobber (match_scratch:SI 3 "=r,r"))]
1663 {sf.|subfc.} %3,%2,%1
1665 [(set_attr "type" "compare")
1666 (set_attr "length" "4,8")])
1669 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1670 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1671 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1673 (clobber (match_scratch:P 3 "=r,r"))]
1678 [(set_attr "type" "fast_compare")
1679 (set_attr "length" "4,8")])
1682 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1683 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1684 (match_operand:P 2 "gpc_reg_operand" ""))
1686 (clobber (match_scratch:P 3 ""))]
1689 (minus:P (match_dup 1)
1692 (compare:CC (match_dup 3)
1697 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1698 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1699 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1701 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1702 (minus:SI (match_dup 1) (match_dup 2)))]
1705 {sf.|subfc.} %0,%2,%1
1707 [(set_attr "type" "compare")
1708 (set_attr "length" "4,8")])
1711 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1712 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1713 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1715 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1716 (minus:P (match_dup 1)
1722 [(set_attr "type" "fast_compare")
1723 (set_attr "length" "4,8")])
1726 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1727 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1728 (match_operand:P 2 "gpc_reg_operand" ""))
1730 (set (match_operand:P 0 "gpc_reg_operand" "")
1731 (minus:P (match_dup 1)
1735 (minus:P (match_dup 1)
1738 (compare:CC (match_dup 0)
1742 (define_expand "sub<mode>3"
1743 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1744 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1745 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1749 if (GET_CODE (operands[2]) == CONST_INT)
1751 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1752 negate_rtx (<MODE>mode, operands[2])));
1757 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1758 ;; instruction and some auxiliary computations. Then we just have a single
1759 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1762 (define_expand "sminsi3"
1764 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1765 (match_operand:SI 2 "reg_or_short_operand" ""))
1767 (minus:SI (match_dup 2) (match_dup 1))))
1768 (set (match_operand:SI 0 "gpc_reg_operand" "")
1769 (minus:SI (match_dup 2) (match_dup 3)))]
1770 "TARGET_POWER || TARGET_ISEL"
1775 operands[2] = force_reg (SImode, operands[2]);
1776 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1780 operands[3] = gen_reg_rtx (SImode);
1784 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1785 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1786 (match_operand:SI 2 "reg_or_short_operand" "")))
1787 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1790 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1792 (minus:SI (match_dup 2) (match_dup 1))))
1793 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1796 (define_expand "smaxsi3"
1798 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1799 (match_operand:SI 2 "reg_or_short_operand" ""))
1801 (minus:SI (match_dup 2) (match_dup 1))))
1802 (set (match_operand:SI 0 "gpc_reg_operand" "")
1803 (plus:SI (match_dup 3) (match_dup 1)))]
1804 "TARGET_POWER || TARGET_ISEL"
1809 operands[2] = force_reg (SImode, operands[2]);
1810 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1813 operands[3] = gen_reg_rtx (SImode);
1817 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1818 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1819 (match_operand:SI 2 "reg_or_short_operand" "")))
1820 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1823 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1825 (minus:SI (match_dup 2) (match_dup 1))))
1826 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1829 (define_expand "uminsi3"
1830 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1832 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1834 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1836 (minus:SI (match_dup 4) (match_dup 3))))
1837 (set (match_operand:SI 0 "gpc_reg_operand" "")
1838 (minus:SI (match_dup 2) (match_dup 3)))]
1839 "TARGET_POWER || TARGET_ISEL"
1844 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1847 operands[3] = gen_reg_rtx (SImode);
1848 operands[4] = gen_reg_rtx (SImode);
1849 operands[5] = GEN_INT (-2147483647 - 1);
1852 (define_expand "umaxsi3"
1853 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1855 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1857 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1859 (minus:SI (match_dup 4) (match_dup 3))))
1860 (set (match_operand:SI 0 "gpc_reg_operand" "")
1861 (plus:SI (match_dup 3) (match_dup 1)))]
1862 "TARGET_POWER || TARGET_ISEL"
1867 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1870 operands[3] = gen_reg_rtx (SImode);
1871 operands[4] = gen_reg_rtx (SImode);
1872 operands[5] = GEN_INT (-2147483647 - 1);
1876 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1877 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1878 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1880 (minus:SI (match_dup 2) (match_dup 1))))]
1885 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1887 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1888 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1890 (minus:SI (match_dup 2) (match_dup 1)))
1892 (clobber (match_scratch:SI 3 "=r,r"))]
1897 [(set_attr "type" "delayed_compare")
1898 (set_attr "length" "4,8")])
1901 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1903 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1904 (match_operand:SI 2 "reg_or_short_operand" ""))
1906 (minus:SI (match_dup 2) (match_dup 1)))
1908 (clobber (match_scratch:SI 3 ""))]
1909 "TARGET_POWER && reload_completed"
1911 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1913 (minus:SI (match_dup 2) (match_dup 1))))
1915 (compare:CC (match_dup 3)
1920 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1922 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1923 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1925 (minus:SI (match_dup 2) (match_dup 1)))
1927 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1928 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1930 (minus:SI (match_dup 2) (match_dup 1))))]
1935 [(set_attr "type" "delayed_compare")
1936 (set_attr "length" "4,8")])
1939 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1941 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1942 (match_operand:SI 2 "reg_or_short_operand" ""))
1944 (minus:SI (match_dup 2) (match_dup 1)))
1946 (set (match_operand:SI 0 "gpc_reg_operand" "")
1947 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1949 (minus:SI (match_dup 2) (match_dup 1))))]
1950 "TARGET_POWER && reload_completed"
1952 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1954 (minus:SI (match_dup 2) (match_dup 1))))
1956 (compare:CC (match_dup 0)
1960 ;; We don't need abs with condition code because such comparisons should
1962 (define_expand "abssi2"
1963 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1964 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1970 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1973 else if (! TARGET_POWER)
1975 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1980 (define_insn "*abssi2_power"
1981 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1982 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1986 (define_insn_and_split "abssi2_isel"
1987 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1988 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1989 (clobber (match_scratch:SI 2 "=&b"))
1990 (clobber (match_scratch:CC 3 "=y"))]
1993 "&& reload_completed"
1994 [(set (match_dup 2) (neg:SI (match_dup 1)))
1996 (compare:CC (match_dup 1)
1999 (if_then_else:SI (ge (match_dup 3)
2005 (define_insn_and_split "abssi2_nopower"
2006 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2007 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2008 (clobber (match_scratch:SI 2 "=&r,&r"))]
2009 "! TARGET_POWER && ! TARGET_ISEL"
2011 "&& reload_completed"
2012 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2013 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2014 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2017 (define_insn "*nabs_power"
2018 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2019 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2023 (define_insn_and_split "*nabs_nopower"
2024 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2025 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2026 (clobber (match_scratch:SI 2 "=&r,&r"))]
2029 "&& reload_completed"
2030 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2031 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2032 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2035 (define_expand "neg<mode>2"
2036 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2037 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2041 (define_insn "*neg<mode>2_internal"
2042 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2043 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2048 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2049 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2051 (clobber (match_scratch:P 2 "=r,r"))]
2056 [(set_attr "type" "fast_compare")
2057 (set_attr "length" "4,8")])
2060 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2061 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2063 (clobber (match_scratch:P 2 ""))]
2066 (neg:P (match_dup 1)))
2068 (compare:CC (match_dup 2)
2073 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2074 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2076 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2077 (neg:P (match_dup 1)))]
2082 [(set_attr "type" "fast_compare")
2083 (set_attr "length" "4,8")])
2086 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2087 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2089 (set (match_operand:P 0 "gpc_reg_operand" "")
2090 (neg:P (match_dup 1)))]
2093 (neg:P (match_dup 1)))
2095 (compare:CC (match_dup 0)
2099 (define_insn "clz<mode>2"
2100 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2101 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2103 "{cntlz|cntlz<wd>} %0,%1")
2105 (define_expand "ctz<mode>2"
2107 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
2108 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2110 (clobber (scratch:CC))])
2111 (set (match_dup 4) (clz:GPR (match_dup 3)))
2112 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2113 (minus:GPR (match_dup 5) (match_dup 4)))]
2116 operands[2] = gen_reg_rtx (<MODE>mode);
2117 operands[3] = gen_reg_rtx (<MODE>mode);
2118 operands[4] = gen_reg_rtx (<MODE>mode);
2119 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2122 (define_expand "ffs<mode>2"
2124 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
2125 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2127 (clobber (scratch:CC))])
2128 (set (match_dup 4) (clz:GPR (match_dup 3)))
2129 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2130 (minus:GPR (match_dup 5) (match_dup 4)))]
2133 operands[2] = gen_reg_rtx (<MODE>mode);
2134 operands[3] = gen_reg_rtx (<MODE>mode);
2135 operands[4] = gen_reg_rtx (<MODE>mode);
2136 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2139 (define_expand "popcount<mode>2"
2141 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2144 (mult:GPR (match_dup 2) (match_dup 4)))
2145 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2146 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
2149 operands[2] = gen_reg_rtx (<MODE>mode);
2150 operands[3] = gen_reg_rtx (<MODE>mode);
2151 operands[4] = force_reg (<MODE>mode,
2152 <MODE>mode == SImode
2153 ? GEN_INT (0x01010101)
2154 : GEN_INT ((HOST_WIDE_INT)
2155 0x01010101 << 32 | 0x01010101));
2156 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
2159 (define_insn "popcntb<mode>2"
2160 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2161 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2166 (define_expand "mulsi3"
2167 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2168 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2169 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2174 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2176 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2180 (define_insn "mulsi3_mq"
2181 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2182 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2183 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2184 (clobber (match_scratch:SI 3 "=q,q"))]
2187 {muls|mullw} %0,%1,%2
2188 {muli|mulli} %0,%1,%2"
2190 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2191 (const_string "imul3")
2192 (match_operand:SI 2 "short_cint_operand" "")
2193 (const_string "imul2")]
2194 (const_string "imul")))])
2196 (define_insn "mulsi3_no_mq"
2197 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2198 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2199 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2202 {muls|mullw} %0,%1,%2
2203 {muli|mulli} %0,%1,%2"
2205 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2206 (const_string "imul3")
2207 (match_operand:SI 2 "short_cint_operand" "")
2208 (const_string "imul2")]
2209 (const_string "imul")))])
2211 (define_insn "*mulsi3_mq_internal1"
2212 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2213 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2214 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2216 (clobber (match_scratch:SI 3 "=r,r"))
2217 (clobber (match_scratch:SI 4 "=q,q"))]
2220 {muls.|mullw.} %3,%1,%2
2222 [(set_attr "type" "imul_compare")
2223 (set_attr "length" "4,8")])
2226 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2227 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2228 (match_operand:SI 2 "gpc_reg_operand" ""))
2230 (clobber (match_scratch:SI 3 ""))
2231 (clobber (match_scratch:SI 4 ""))]
2232 "TARGET_POWER && reload_completed"
2233 [(parallel [(set (match_dup 3)
2234 (mult:SI (match_dup 1) (match_dup 2)))
2235 (clobber (match_dup 4))])
2237 (compare:CC (match_dup 3)
2241 (define_insn "*mulsi3_no_mq_internal1"
2242 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2243 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2244 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2246 (clobber (match_scratch:SI 3 "=r,r"))]
2249 {muls.|mullw.} %3,%1,%2
2251 [(set_attr "type" "imul_compare")
2252 (set_attr "length" "4,8")])
2255 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2256 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2257 (match_operand:SI 2 "gpc_reg_operand" ""))
2259 (clobber (match_scratch:SI 3 ""))]
2260 "! TARGET_POWER && reload_completed"
2262 (mult:SI (match_dup 1) (match_dup 2)))
2264 (compare:CC (match_dup 3)
2268 (define_insn "*mulsi3_mq_internal2"
2269 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2270 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2271 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2273 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2274 (mult:SI (match_dup 1) (match_dup 2)))
2275 (clobber (match_scratch:SI 4 "=q,q"))]
2278 {muls.|mullw.} %0,%1,%2
2280 [(set_attr "type" "imul_compare")
2281 (set_attr "length" "4,8")])
2284 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2285 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2286 (match_operand:SI 2 "gpc_reg_operand" ""))
2288 (set (match_operand:SI 0 "gpc_reg_operand" "")
2289 (mult:SI (match_dup 1) (match_dup 2)))
2290 (clobber (match_scratch:SI 4 ""))]
2291 "TARGET_POWER && reload_completed"
2292 [(parallel [(set (match_dup 0)
2293 (mult:SI (match_dup 1) (match_dup 2)))
2294 (clobber (match_dup 4))])
2296 (compare:CC (match_dup 0)
2300 (define_insn "*mulsi3_no_mq_internal2"
2301 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2302 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2303 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2305 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2306 (mult:SI (match_dup 1) (match_dup 2)))]
2309 {muls.|mullw.} %0,%1,%2
2311 [(set_attr "type" "imul_compare")
2312 (set_attr "length" "4,8")])
2315 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2316 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2317 (match_operand:SI 2 "gpc_reg_operand" ""))
2319 (set (match_operand:SI 0 "gpc_reg_operand" "")
2320 (mult:SI (match_dup 1) (match_dup 2)))]
2321 "! TARGET_POWER && reload_completed"
2323 (mult:SI (match_dup 1) (match_dup 2)))
2325 (compare:CC (match_dup 0)
2329 ;; Operand 1 is divided by operand 2; quotient goes to operand
2330 ;; 0 and remainder to operand 3.
2331 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2333 (define_expand "divmodsi4"
2334 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2335 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2336 (match_operand:SI 2 "gpc_reg_operand" "")))
2337 (set (match_operand:SI 3 "register_operand" "")
2338 (mod:SI (match_dup 1) (match_dup 2)))])]
2339 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2342 if (! TARGET_POWER && ! TARGET_POWERPC)
2344 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2345 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2346 emit_insn (gen_divss_call ());
2347 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2348 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2353 (define_insn "*divmodsi4_internal"
2354 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2355 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2356 (match_operand:SI 2 "gpc_reg_operand" "r")))
2357 (set (match_operand:SI 3 "register_operand" "=q")
2358 (mod:SI (match_dup 1) (match_dup 2)))]
2361 [(set_attr "type" "idiv")])
2363 (define_expand "udiv<mode>3"
2364 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2365 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2366 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2367 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2370 if (! TARGET_POWER && ! TARGET_POWERPC)
2372 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2373 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2374 emit_insn (gen_quous_call ());
2375 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2378 else if (TARGET_POWER)
2380 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2385 (define_insn "udivsi3_mq"
2386 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2387 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2388 (match_operand:SI 2 "gpc_reg_operand" "r")))
2389 (clobber (match_scratch:SI 3 "=q"))]
2390 "TARGET_POWERPC && TARGET_POWER"
2392 [(set_attr "type" "idiv")])
2394 (define_insn "*udivsi3_no_mq"
2395 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2396 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2397 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2398 "TARGET_POWERPC && ! TARGET_POWER"
2400 [(set_attr "type" "idiv")])
2402 ;; For powers of two we can do srai/aze for divide and then adjust for
2403 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2404 ;; used; for PowerPC, force operands into register and do a normal divide;
2405 ;; for AIX common-mode, use quoss call on register operands.
2406 (define_expand "div<mode>3"
2407 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2408 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2409 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2413 if (GET_CODE (operands[2]) == CONST_INT
2414 && INTVAL (operands[2]) > 0
2415 && exact_log2 (INTVAL (operands[2])) >= 0)
2417 else if (TARGET_POWERPC)
2419 operands[2] = force_reg (SImode, operands[2]);
2422 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2426 else if (TARGET_POWER)
2430 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2431 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2432 emit_insn (gen_quoss_call ());
2433 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2438 (define_insn "divsi3_mq"
2439 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2440 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2441 (match_operand:SI 2 "gpc_reg_operand" "r")))
2442 (clobber (match_scratch:SI 3 "=q"))]
2443 "TARGET_POWERPC && TARGET_POWER"
2445 [(set_attr "type" "idiv")])
2447 (define_insn "*div<mode>3_no_mq"
2448 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2449 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2450 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2451 "TARGET_POWERPC && ! TARGET_POWER"
2453 [(set_attr "type" "idiv")])
2455 (define_expand "mod<mode>3"
2456 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2457 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2458 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2466 if (GET_CODE (operands[2]) != CONST_INT
2467 || INTVAL (operands[2]) <= 0
2468 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2471 temp1 = gen_reg_rtx (<MODE>mode);
2472 temp2 = gen_reg_rtx (<MODE>mode);
2474 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2475 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2476 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2481 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2482 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2483 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2485 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2486 [(set_attr "type" "two")
2487 (set_attr "length" "8")])
2490 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2491 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2492 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2494 (clobber (match_scratch:P 3 "=r,r"))]
2497 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2499 [(set_attr "type" "compare")
2500 (set_attr "length" "8,12")])
2503 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2504 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2505 (match_operand:GPR 2 "exact_log2_cint_operand"
2508 (clobber (match_scratch:GPR 3 ""))]
2511 (div:<MODE> (match_dup 1) (match_dup 2)))
2513 (compare:CC (match_dup 3)
2518 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2519 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2520 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2522 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2523 (div:P (match_dup 1) (match_dup 2)))]
2526 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2528 [(set_attr "type" "compare")
2529 (set_attr "length" "8,12")])
2532 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2533 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2534 (match_operand:GPR 2 "exact_log2_cint_operand"
2537 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2538 (div:GPR (match_dup 1) (match_dup 2)))]
2541 (div:<MODE> (match_dup 1) (match_dup 2)))
2543 (compare:CC (match_dup 0)
2548 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2551 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2553 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2554 (match_operand:SI 3 "gpc_reg_operand" "r")))
2555 (set (match_operand:SI 2 "register_operand" "=*q")
2558 (zero_extend:DI (match_dup 1)) (const_int 32))
2559 (zero_extend:DI (match_dup 4)))
2563 [(set_attr "type" "idiv")])
2565 ;; To do unsigned divide we handle the cases of the divisor looking like a
2566 ;; negative number. If it is a constant that is less than 2**31, we don't
2567 ;; have to worry about the branches. So make a few subroutines here.
2569 ;; First comes the normal case.
2570 (define_expand "udivmodsi4_normal"
2571 [(set (match_dup 4) (const_int 0))
2572 (parallel [(set (match_operand:SI 0 "" "")
2573 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2575 (zero_extend:DI (match_operand:SI 1 "" "")))
2576 (match_operand:SI 2 "" "")))
2577 (set (match_operand:SI 3 "" "")
2578 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2580 (zero_extend:DI (match_dup 1)))
2584 { operands[4] = gen_reg_rtx (SImode); }")
2586 ;; This handles the branches.
2587 (define_expand "udivmodsi4_tests"
2588 [(set (match_operand:SI 0 "" "") (const_int 0))
2589 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2590 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2591 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2592 (label_ref (match_operand:SI 4 "" "")) (pc)))
2593 (set (match_dup 0) (const_int 1))
2594 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2595 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2596 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2597 (label_ref (match_dup 4)) (pc)))]
2600 { operands[5] = gen_reg_rtx (CCUNSmode);
2601 operands[6] = gen_reg_rtx (CCmode);
2604 (define_expand "udivmodsi4"
2605 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2606 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2607 (match_operand:SI 2 "reg_or_cint_operand" "")))
2608 (set (match_operand:SI 3 "gpc_reg_operand" "")
2609 (umod:SI (match_dup 1) (match_dup 2)))])]
2617 if (! TARGET_POWERPC)
2619 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2620 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2621 emit_insn (gen_divus_call ());
2622 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2623 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2630 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2632 operands[2] = force_reg (SImode, operands[2]);
2633 label = gen_label_rtx ();
2634 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2635 operands[3], label));
2638 operands[2] = force_reg (SImode, operands[2]);
2640 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2648 ;; AIX architecture-independent common-mode multiply (DImode),
2649 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2650 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2651 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2652 ;; assumed unused if generating common-mode, so ignore.
2653 (define_insn "mulh_call"
2656 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2657 (sign_extend:DI (reg:SI 4)))
2659 (clobber (match_scratch:SI 0 "=l"))]
2660 "! TARGET_POWER && ! TARGET_POWERPC"
2662 [(set_attr "type" "imul")])
2664 (define_insn "mull_call"
2666 (mult:DI (sign_extend:DI (reg:SI 3))
2667 (sign_extend:DI (reg:SI 4))))
2668 (clobber (match_scratch:SI 0 "=l"))
2669 (clobber (reg:SI 0))]
2670 "! TARGET_POWER && ! TARGET_POWERPC"
2672 [(set_attr "type" "imul")])
2674 (define_insn "divss_call"
2676 (div:SI (reg:SI 3) (reg:SI 4)))
2678 (mod:SI (reg:SI 3) (reg:SI 4)))
2679 (clobber (match_scratch:SI 0 "=l"))
2680 (clobber (reg:SI 0))]
2681 "! TARGET_POWER && ! TARGET_POWERPC"
2683 [(set_attr "type" "idiv")])
2685 (define_insn "divus_call"
2687 (udiv:SI (reg:SI 3) (reg:SI 4)))
2689 (umod:SI (reg:SI 3) (reg:SI 4)))
2690 (clobber (match_scratch:SI 0 "=l"))
2691 (clobber (reg:SI 0))
2692 (clobber (match_scratch:CC 1 "=x"))
2693 (clobber (reg:CC 69))]
2694 "! TARGET_POWER && ! TARGET_POWERPC"
2696 [(set_attr "type" "idiv")])
2698 (define_insn "quoss_call"
2700 (div:SI (reg:SI 3) (reg:SI 4)))
2701 (clobber (match_scratch:SI 0 "=l"))]
2702 "! TARGET_POWER && ! TARGET_POWERPC"
2704 [(set_attr "type" "idiv")])
2706 (define_insn "quous_call"
2708 (udiv:SI (reg:SI 3) (reg:SI 4)))
2709 (clobber (match_scratch:SI 0 "=l"))
2710 (clobber (reg:SI 0))
2711 (clobber (match_scratch:CC 1 "=x"))
2712 (clobber (reg:CC 69))]
2713 "! TARGET_POWER && ! TARGET_POWERPC"
2715 [(set_attr "type" "idiv")])
2717 ;; Logical instructions
2718 ;; The logical instructions are mostly combined by using match_operator,
2719 ;; but the plain AND insns are somewhat different because there is no
2720 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2721 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2723 (define_insn "andsi3"
2724 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2725 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2726 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2727 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2731 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2732 {andil.|andi.} %0,%1,%b2
2733 {andiu.|andis.} %0,%1,%u2"
2734 [(set_attr "type" "*,*,compare,compare")])
2736 ;; Note to set cr's other than cr0 we do the and immediate and then
2737 ;; the test again -- this avoids a mfcr which on the higher end
2738 ;; machines causes an execution serialization
2740 (define_insn "*andsi3_internal2"
2741 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2742 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2743 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2745 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2746 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2750 {andil.|andi.} %3,%1,%b2
2751 {andiu.|andis.} %3,%1,%u2
2752 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2757 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2758 (set_attr "length" "4,4,4,4,8,8,8,8")])
2760 (define_insn "*andsi3_internal3"
2761 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2762 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2763 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2765 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2766 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2770 {andil.|andi.} %3,%1,%b2
2771 {andiu.|andis.} %3,%1,%u2
2772 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2777 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2778 (set_attr "length" "8,4,4,4,8,8,8,8")])
2781 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2782 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2783 (match_operand:GPR 2 "and_operand" ""))
2785 (clobber (match_scratch:GPR 3 ""))
2786 (clobber (match_scratch:CC 4 ""))]
2788 [(parallel [(set (match_dup 3)
2789 (and:<MODE> (match_dup 1)
2791 (clobber (match_dup 4))])
2793 (compare:CC (match_dup 3)
2797 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2798 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2801 [(set (match_operand:CC 0 "cc_reg_operand" "")
2802 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2803 (match_operand:SI 2 "gpc_reg_operand" ""))
2805 (clobber (match_scratch:SI 3 ""))
2806 (clobber (match_scratch:CC 4 ""))]
2807 "TARGET_POWERPC64 && reload_completed"
2808 [(parallel [(set (match_dup 3)
2809 (and:SI (match_dup 1)
2811 (clobber (match_dup 4))])
2813 (compare:CC (match_dup 3)
2817 (define_insn "*andsi3_internal4"
2818 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2819 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2820 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2822 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2823 (and:SI (match_dup 1)
2825 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2829 {andil.|andi.} %0,%1,%b2
2830 {andiu.|andis.} %0,%1,%u2
2831 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2836 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2837 (set_attr "length" "4,4,4,4,8,8,8,8")])
2839 (define_insn "*andsi3_internal5"
2840 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2841 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2842 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2844 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2845 (and:SI (match_dup 1)
2847 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2851 {andil.|andi.} %0,%1,%b2
2852 {andiu.|andis.} %0,%1,%u2
2853 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2858 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2859 (set_attr "length" "8,4,4,4,8,8,8,8")])
2862 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2863 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2864 (match_operand:SI 2 "and_operand" ""))
2866 (set (match_operand:SI 0 "gpc_reg_operand" "")
2867 (and:SI (match_dup 1)
2869 (clobber (match_scratch:CC 4 ""))]
2871 [(parallel [(set (match_dup 0)
2872 (and:SI (match_dup 1)
2874 (clobber (match_dup 4))])
2876 (compare:CC (match_dup 0)
2881 [(set (match_operand:CC 3 "cc_reg_operand" "")
2882 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2883 (match_operand:SI 2 "gpc_reg_operand" ""))
2885 (set (match_operand:SI 0 "gpc_reg_operand" "")
2886 (and:SI (match_dup 1)
2888 (clobber (match_scratch:CC 4 ""))]
2889 "TARGET_POWERPC64 && reload_completed"
2890 [(parallel [(set (match_dup 0)
2891 (and:SI (match_dup 1)
2893 (clobber (match_dup 4))])
2895 (compare:CC (match_dup 0)
2899 ;; Handle the PowerPC64 rlwinm corner case
2901 (define_insn_and_split "*andsi3_internal6"
2902 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2903 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2904 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2909 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2912 (rotate:SI (match_dup 0) (match_dup 5)))]
2915 int mb = extract_MB (operands[2]);
2916 int me = extract_ME (operands[2]);
2917 operands[3] = GEN_INT (me + 1);
2918 operands[5] = GEN_INT (32 - (me + 1));
2919 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2921 [(set_attr "length" "8")])
2923 (define_expand "iorsi3"
2924 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2925 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2926 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2930 if (GET_CODE (operands[2]) == CONST_INT
2931 && ! logical_operand (operands[2], SImode))
2933 HOST_WIDE_INT value = INTVAL (operands[2]);
2934 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2935 ? operands[0] : gen_reg_rtx (SImode));
2937 emit_insn (gen_iorsi3 (tmp, operands[1],
2938 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2939 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2944 (define_expand "xorsi3"
2945 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2946 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2947 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2951 if (GET_CODE (operands[2]) == CONST_INT
2952 && ! logical_operand (operands[2], SImode))
2954 HOST_WIDE_INT value = INTVAL (operands[2]);
2955 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2956 ? operands[0] : gen_reg_rtx (SImode));
2958 emit_insn (gen_xorsi3 (tmp, operands[1],
2959 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2960 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2965 (define_insn "*boolsi3_internal1"
2966 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2967 (match_operator:SI 3 "boolean_or_operator"
2968 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2969 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2973 {%q3il|%q3i} %0,%1,%b2
2974 {%q3iu|%q3is} %0,%1,%u2")
2976 (define_insn "*boolsi3_internal2"
2977 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2978 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2979 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2980 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2982 (clobber (match_scratch:SI 3 "=r,r"))]
2987 [(set_attr "type" "compare")
2988 (set_attr "length" "4,8")])
2991 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2992 (compare:CC (match_operator:SI 4 "boolean_operator"
2993 [(match_operand:SI 1 "gpc_reg_operand" "")
2994 (match_operand:SI 2 "gpc_reg_operand" "")])
2996 (clobber (match_scratch:SI 3 ""))]
2997 "TARGET_32BIT && reload_completed"
2998 [(set (match_dup 3) (match_dup 4))
3000 (compare:CC (match_dup 3)
3004 (define_insn "*boolsi3_internal3"
3005 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3006 (compare:CC (match_operator:SI 4 "boolean_operator"
3007 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3008 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3010 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3016 [(set_attr "type" "compare")
3017 (set_attr "length" "4,8")])
3020 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3021 (compare:CC (match_operator:SI 4 "boolean_operator"
3022 [(match_operand:SI 1 "gpc_reg_operand" "")
3023 (match_operand:SI 2 "gpc_reg_operand" "")])
3025 (set (match_operand:SI 0 "gpc_reg_operand" "")
3027 "TARGET_32BIT && reload_completed"
3028 [(set (match_dup 0) (match_dup 4))
3030 (compare:CC (match_dup 0)
3034 ;; Split a logical operation that we can't do in one insn into two insns,
3035 ;; each of which does one 16-bit part. This is used by combine.
3038 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3039 (match_operator:SI 3 "boolean_or_operator"
3040 [(match_operand:SI 1 "gpc_reg_operand" "")
3041 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3043 [(set (match_dup 0) (match_dup 4))
3044 (set (match_dup 0) (match_dup 5))]
3048 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3049 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3051 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3052 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3056 (define_insn "*boolcsi3_internal1"
3057 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3058 (match_operator:SI 3 "boolean_operator"
3059 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3060 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3064 (define_insn "*boolcsi3_internal2"
3065 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3066 (compare:CC (match_operator:SI 4 "boolean_operator"
3067 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3068 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3070 (clobber (match_scratch:SI 3 "=r,r"))]
3075 [(set_attr "type" "compare")
3076 (set_attr "length" "4,8")])
3079 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3080 (compare:CC (match_operator:SI 4 "boolean_operator"
3081 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3082 (match_operand:SI 2 "gpc_reg_operand" "")])
3084 (clobber (match_scratch:SI 3 ""))]
3085 "TARGET_32BIT && reload_completed"
3086 [(set (match_dup 3) (match_dup 4))
3088 (compare:CC (match_dup 3)
3092 (define_insn "*boolcsi3_internal3"
3093 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3094 (compare:CC (match_operator:SI 4 "boolean_operator"
3095 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3096 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3098 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3104 [(set_attr "type" "compare")
3105 (set_attr "length" "4,8")])
3108 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3109 (compare:CC (match_operator:SI 4 "boolean_operator"
3110 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3111 (match_operand:SI 2 "gpc_reg_operand" "")])
3113 (set (match_operand:SI 0 "gpc_reg_operand" "")
3115 "TARGET_32BIT && reload_completed"
3116 [(set (match_dup 0) (match_dup 4))
3118 (compare:CC (match_dup 0)
3122 (define_insn "*boolccsi3_internal1"
3123 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3124 (match_operator:SI 3 "boolean_operator"
3125 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3126 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3130 (define_insn "*boolccsi3_internal2"
3131 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3132 (compare:CC (match_operator:SI 4 "boolean_operator"
3133 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3134 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3136 (clobber (match_scratch:SI 3 "=r,r"))]
3141 [(set_attr "type" "compare")
3142 (set_attr "length" "4,8")])
3145 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3146 (compare:CC (match_operator:SI 4 "boolean_operator"
3147 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3148 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3150 (clobber (match_scratch:SI 3 ""))]
3151 "TARGET_32BIT && reload_completed"
3152 [(set (match_dup 3) (match_dup 4))
3154 (compare:CC (match_dup 3)
3158 (define_insn "*boolccsi3_internal3"
3159 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3160 (compare:CC (match_operator:SI 4 "boolean_operator"
3161 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3162 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3164 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3170 [(set_attr "type" "compare")
3171 (set_attr "length" "4,8")])
3174 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3175 (compare:CC (match_operator:SI 4 "boolean_operator"
3176 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3177 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3179 (set (match_operand:SI 0 "gpc_reg_operand" "")
3181 "TARGET_32BIT && reload_completed"
3182 [(set (match_dup 0) (match_dup 4))
3184 (compare:CC (match_dup 0)
3188 ;; maskir insn. We need four forms because things might be in arbitrary
3189 ;; orders. Don't define forms that only set CR fields because these
3190 ;; would modify an input register.
3192 (define_insn "*maskir_internal1"
3193 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3194 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3195 (match_operand:SI 1 "gpc_reg_operand" "0"))
3196 (and:SI (match_dup 2)
3197 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3201 (define_insn "*maskir_internal2"
3202 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3203 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3204 (match_operand:SI 1 "gpc_reg_operand" "0"))
3205 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3210 (define_insn "*maskir_internal3"
3211 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3212 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3213 (match_operand:SI 3 "gpc_reg_operand" "r"))
3214 (and:SI (not:SI (match_dup 2))
3215 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3219 (define_insn "*maskir_internal4"
3220 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3221 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3222 (match_operand:SI 2 "gpc_reg_operand" "r"))
3223 (and:SI (not:SI (match_dup 2))
3224 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3228 (define_insn "*maskir_internal5"
3229 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3231 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3232 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3233 (and:SI (match_dup 2)
3234 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3236 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3237 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3238 (and:SI (match_dup 2) (match_dup 3))))]
3243 [(set_attr "type" "compare")
3244 (set_attr "length" "4,8")])
3247 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3249 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3250 (match_operand:SI 1 "gpc_reg_operand" ""))
3251 (and:SI (match_dup 2)
3252 (match_operand:SI 3 "gpc_reg_operand" "")))
3254 (set (match_operand:SI 0 "gpc_reg_operand" "")
3255 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3256 (and:SI (match_dup 2) (match_dup 3))))]
3257 "TARGET_POWER && reload_completed"
3259 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3260 (and:SI (match_dup 2) (match_dup 3))))
3262 (compare:CC (match_dup 0)
3266 (define_insn "*maskir_internal6"
3267 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3269 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3270 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3271 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3274 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3275 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3276 (and:SI (match_dup 3) (match_dup 2))))]
3281 [(set_attr "type" "compare")
3282 (set_attr "length" "4,8")])
3285 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3287 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3288 (match_operand:SI 1 "gpc_reg_operand" ""))
3289 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3292 (set (match_operand:SI 0 "gpc_reg_operand" "")
3293 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3294 (and:SI (match_dup 3) (match_dup 2))))]
3295 "TARGET_POWER && reload_completed"
3297 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3298 (and:SI (match_dup 3) (match_dup 2))))
3300 (compare:CC (match_dup 0)
3304 (define_insn "*maskir_internal7"
3305 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3307 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3308 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3309 (and:SI (not:SI (match_dup 2))
3310 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3312 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3313 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3314 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3319 [(set_attr "type" "compare")
3320 (set_attr "length" "4,8")])
3323 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3325 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3326 (match_operand:SI 3 "gpc_reg_operand" ""))
3327 (and:SI (not:SI (match_dup 2))
3328 (match_operand:SI 1 "gpc_reg_operand" "")))
3330 (set (match_operand:SI 0 "gpc_reg_operand" "")
3331 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3332 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3333 "TARGET_POWER && reload_completed"
3335 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3336 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3338 (compare:CC (match_dup 0)
3342 (define_insn "*maskir_internal8"
3343 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3345 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3346 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3347 (and:SI (not:SI (match_dup 2))
3348 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3350 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3351 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3352 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3357 [(set_attr "type" "compare")
3358 (set_attr "length" "4,8")])
3361 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3363 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3364 (match_operand:SI 2 "gpc_reg_operand" ""))
3365 (and:SI (not:SI (match_dup 2))
3366 (match_operand:SI 1 "gpc_reg_operand" "")))
3368 (set (match_operand:SI 0 "gpc_reg_operand" "")
3369 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3370 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3371 "TARGET_POWER && reload_completed"
3373 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3374 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3376 (compare:CC (match_dup 0)
3380 ;; Rotate and shift insns, in all their variants. These support shifts,
3381 ;; field inserts and extracts, and various combinations thereof.
3382 (define_expand "insv"
3383 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3384 (match_operand:SI 1 "const_int_operand" "")
3385 (match_operand:SI 2 "const_int_operand" ""))
3386 (match_operand 3 "gpc_reg_operand" ""))]
3390 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3391 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3392 compiler if the address of the structure is taken later. */
3393 if (GET_CODE (operands[0]) == SUBREG
3394 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3397 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3398 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3400 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3404 (define_insn "insvsi"
3405 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3406 (match_operand:SI 1 "const_int_operand" "i")
3407 (match_operand:SI 2 "const_int_operand" "i"))
3408 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3412 int start = INTVAL (operands[2]) & 31;
3413 int size = INTVAL (operands[1]) & 31;
3415 operands[4] = GEN_INT (32 - start - size);
3416 operands[1] = GEN_INT (start + size - 1);
3417 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3419 [(set_attr "type" "insert_word")])
3421 (define_insn "*insvsi_internal1"
3422 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3423 (match_operand:SI 1 "const_int_operand" "i")
3424 (match_operand:SI 2 "const_int_operand" "i"))
3425 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3426 (match_operand:SI 4 "const_int_operand" "i")))]
3427 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3430 int shift = INTVAL (operands[4]) & 31;
3431 int start = INTVAL (operands[2]) & 31;
3432 int size = INTVAL (operands[1]) & 31;
3434 operands[4] = GEN_INT (shift - start - size);
3435 operands[1] = GEN_INT (start + size - 1);
3436 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3438 [(set_attr "type" "insert_word")])
3440 (define_insn "*insvsi_internal2"
3441 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3442 (match_operand:SI 1 "const_int_operand" "i")
3443 (match_operand:SI 2 "const_int_operand" "i"))
3444 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3445 (match_operand:SI 4 "const_int_operand" "i")))]
3446 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3449 int shift = INTVAL (operands[4]) & 31;
3450 int start = INTVAL (operands[2]) & 31;
3451 int size = INTVAL (operands[1]) & 31;
3453 operands[4] = GEN_INT (32 - shift - start - size);
3454 operands[1] = GEN_INT (start + size - 1);
3455 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3457 [(set_attr "type" "insert_word")])
3459 (define_insn "*insvsi_internal3"
3460 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3461 (match_operand:SI 1 "const_int_operand" "i")
3462 (match_operand:SI 2 "const_int_operand" "i"))
3463 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3464 (match_operand:SI 4 "const_int_operand" "i")))]
3465 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3468 int shift = INTVAL (operands[4]) & 31;
3469 int start = INTVAL (operands[2]) & 31;
3470 int size = INTVAL (operands[1]) & 31;
3472 operands[4] = GEN_INT (32 - shift - start - size);
3473 operands[1] = GEN_INT (start + size - 1);
3474 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3476 [(set_attr "type" "insert_word")])
3478 (define_insn "*insvsi_internal4"
3479 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3480 (match_operand:SI 1 "const_int_operand" "i")
3481 (match_operand:SI 2 "const_int_operand" "i"))
3482 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3483 (match_operand:SI 4 "const_int_operand" "i")
3484 (match_operand:SI 5 "const_int_operand" "i")))]
3485 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3488 int extract_start = INTVAL (operands[5]) & 31;
3489 int extract_size = INTVAL (operands[4]) & 31;
3490 int insert_start = INTVAL (operands[2]) & 31;
3491 int insert_size = INTVAL (operands[1]) & 31;
3493 /* Align extract field with insert field */
3494 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3495 operands[1] = GEN_INT (insert_start + insert_size - 1);
3496 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3498 [(set_attr "type" "insert_word")])
3500 ;; combine patterns for rlwimi
3501 (define_insn "*insvsi_internal5"
3502 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3503 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3504 (match_operand:SI 1 "mask_operand" "i"))
3505 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3506 (match_operand:SI 2 "const_int_operand" "i"))
3507 (match_operand:SI 5 "mask_operand" "i"))))]
3508 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3511 int me = extract_ME(operands[5]);
3512 int mb = extract_MB(operands[5]);
3513 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3514 operands[2] = GEN_INT(mb);
3515 operands[1] = GEN_INT(me);
3516 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3518 [(set_attr "type" "insert_word")])
3520 (define_insn "*insvsi_internal6"
3521 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3522 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3523 (match_operand:SI 2 "const_int_operand" "i"))
3524 (match_operand:SI 5 "mask_operand" "i"))
3525 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3526 (match_operand:SI 1 "mask_operand" "i"))))]
3527 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3530 int me = extract_ME(operands[5]);
3531 int mb = extract_MB(operands[5]);
3532 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3533 operands[2] = GEN_INT(mb);
3534 operands[1] = GEN_INT(me);
3535 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3537 [(set_attr "type" "insert_word")])
3539 (define_insn "insvdi"
3540 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3541 (match_operand:SI 1 "const_int_operand" "i")
3542 (match_operand:SI 2 "const_int_operand" "i"))
3543 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3547 int start = INTVAL (operands[2]) & 63;
3548 int size = INTVAL (operands[1]) & 63;
3550 operands[1] = GEN_INT (64 - start - size);
3551 return \"rldimi %0,%3,%H1,%H2\";
3554 (define_insn "*insvdi_internal2"
3555 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3556 (match_operand:SI 1 "const_int_operand" "i")
3557 (match_operand:SI 2 "const_int_operand" "i"))
3558 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3559 (match_operand:SI 4 "const_int_operand" "i")))]
3561 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3564 int shift = INTVAL (operands[4]) & 63;
3565 int start = (INTVAL (operands[2]) & 63) - 32;
3566 int size = INTVAL (operands[1]) & 63;
3568 operands[4] = GEN_INT (64 - shift - start - size);
3569 operands[2] = GEN_INT (start);
3570 operands[1] = GEN_INT (start + size - 1);
3571 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3574 (define_insn "*insvdi_internal3"
3575 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3576 (match_operand:SI 1 "const_int_operand" "i")
3577 (match_operand:SI 2 "const_int_operand" "i"))
3578 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3579 (match_operand:SI 4 "const_int_operand" "i")))]
3581 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3584 int shift = INTVAL (operands[4]) & 63;
3585 int start = (INTVAL (operands[2]) & 63) - 32;
3586 int size = INTVAL (operands[1]) & 63;
3588 operands[4] = GEN_INT (64 - shift - start - size);
3589 operands[2] = GEN_INT (start);
3590 operands[1] = GEN_INT (start + size - 1);
3591 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3594 (define_expand "extzv"
3595 [(set (match_operand 0 "gpc_reg_operand" "")
3596 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3597 (match_operand:SI 2 "const_int_operand" "")
3598 (match_operand:SI 3 "const_int_operand" "")))]
3602 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3603 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3604 compiler if the address of the structure is taken later. */
3605 if (GET_CODE (operands[0]) == SUBREG
3606 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3609 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3610 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3612 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3616 (define_insn "extzvsi"
3617 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3618 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3619 (match_operand:SI 2 "const_int_operand" "i")
3620 (match_operand:SI 3 "const_int_operand" "i")))]
3624 int start = INTVAL (operands[3]) & 31;
3625 int size = INTVAL (operands[2]) & 31;
3627 if (start + size >= 32)
3628 operands[3] = const0_rtx;
3630 operands[3] = GEN_INT (start + size);
3631 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3634 (define_insn "*extzvsi_internal1"
3635 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3636 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3637 (match_operand:SI 2 "const_int_operand" "i,i")
3638 (match_operand:SI 3 "const_int_operand" "i,i"))
3640 (clobber (match_scratch:SI 4 "=r,r"))]
3644 int start = INTVAL (operands[3]) & 31;
3645 int size = INTVAL (operands[2]) & 31;
3647 /* Force split for non-cc0 compare. */
3648 if (which_alternative == 1)
3651 /* If the bit-field being tested fits in the upper or lower half of a
3652 word, it is possible to use andiu. or andil. to test it. This is
3653 useful because the condition register set-use delay is smaller for
3654 andi[ul]. than for rlinm. This doesn't work when the starting bit
3655 position is 0 because the LT and GT bits may be set wrong. */
3657 if ((start > 0 && start + size <= 16) || start >= 16)
3659 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3660 - (1 << (16 - (start & 15) - size))));
3662 return \"{andiu.|andis.} %4,%1,%3\";
3664 return \"{andil.|andi.} %4,%1,%3\";
3667 if (start + size >= 32)
3668 operands[3] = const0_rtx;
3670 operands[3] = GEN_INT (start + size);
3671 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3673 [(set_attr "type" "compare")
3674 (set_attr "length" "4,8")])
3677 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3678 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3679 (match_operand:SI 2 "const_int_operand" "")
3680 (match_operand:SI 3 "const_int_operand" ""))
3682 (clobber (match_scratch:SI 4 ""))]
3685 (zero_extract:SI (match_dup 1) (match_dup 2)
3688 (compare:CC (match_dup 4)
3692 (define_insn "*extzvsi_internal2"
3693 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3694 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3695 (match_operand:SI 2 "const_int_operand" "i,i")
3696 (match_operand:SI 3 "const_int_operand" "i,i"))
3698 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3699 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3703 int start = INTVAL (operands[3]) & 31;
3704 int size = INTVAL (operands[2]) & 31;
3706 /* Force split for non-cc0 compare. */
3707 if (which_alternative == 1)
3710 /* Since we are using the output value, we can't ignore any need for
3711 a shift. The bit-field must end at the LSB. */
3712 if (start >= 16 && start + size == 32)
3714 operands[3] = GEN_INT ((1 << size) - 1);
3715 return \"{andil.|andi.} %0,%1,%3\";
3718 if (start + size >= 32)
3719 operands[3] = const0_rtx;
3721 operands[3] = GEN_INT (start + size);
3722 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3724 [(set_attr "type" "compare")
3725 (set_attr "length" "4,8")])
3728 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3729 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3730 (match_operand:SI 2 "const_int_operand" "")
3731 (match_operand:SI 3 "const_int_operand" ""))
3733 (set (match_operand:SI 0 "gpc_reg_operand" "")
3734 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3737 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3739 (compare:CC (match_dup 0)
3743 (define_insn "extzvdi"
3744 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3745 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3746 (match_operand:SI 2 "const_int_operand" "i")
3747 (match_operand:SI 3 "const_int_operand" "i")))]
3751 int start = INTVAL (operands[3]) & 63;
3752 int size = INTVAL (operands[2]) & 63;
3754 if (start + size >= 64)
3755 operands[3] = const0_rtx;
3757 operands[3] = GEN_INT (start + size);
3758 operands[2] = GEN_INT (64 - size);
3759 return \"rldicl %0,%1,%3,%2\";
3762 (define_insn "*extzvdi_internal1"
3763 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3764 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3765 (match_operand:SI 2 "const_int_operand" "i")
3766 (match_operand:SI 3 "const_int_operand" "i"))
3768 (clobber (match_scratch:DI 4 "=r"))]
3772 int start = INTVAL (operands[3]) & 63;
3773 int size = INTVAL (operands[2]) & 63;
3775 if (start + size >= 64)
3776 operands[3] = const0_rtx;
3778 operands[3] = GEN_INT (start + size);
3779 operands[2] = GEN_INT (64 - size);
3780 return \"rldicl. %4,%1,%3,%2\";
3782 [(set_attr "type" "compare")])
3784 (define_insn "*extzvdi_internal2"
3785 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3786 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3787 (match_operand:SI 2 "const_int_operand" "i")
3788 (match_operand:SI 3 "const_int_operand" "i"))
3790 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3791 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3795 int start = INTVAL (operands[3]) & 63;
3796 int size = INTVAL (operands[2]) & 63;
3798 if (start + size >= 64)
3799 operands[3] = const0_rtx;
3801 operands[3] = GEN_INT (start + size);
3802 operands[2] = GEN_INT (64 - size);
3803 return \"rldicl. %0,%1,%3,%2\";
3805 [(set_attr "type" "compare")])
3807 (define_insn "rotlsi3"
3808 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3809 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3810 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3812 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3814 (define_insn "*rotlsi3_internal2"
3815 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3816 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3817 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3819 (clobber (match_scratch:SI 3 "=r,r"))]
3822 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3824 [(set_attr "type" "delayed_compare")
3825 (set_attr "length" "4,8")])
3828 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3829 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3830 (match_operand:SI 2 "reg_or_cint_operand" ""))
3832 (clobber (match_scratch:SI 3 ""))]
3835 (rotate:SI (match_dup 1) (match_dup 2)))
3837 (compare:CC (match_dup 3)
3841 (define_insn "*rotlsi3_internal3"
3842 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3843 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3844 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3846 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3847 (rotate:SI (match_dup 1) (match_dup 2)))]
3850 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3852 [(set_attr "type" "delayed_compare")
3853 (set_attr "length" "4,8")])
3856 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3857 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3858 (match_operand:SI 2 "reg_or_cint_operand" ""))
3860 (set (match_operand:SI 0 "gpc_reg_operand" "")
3861 (rotate:SI (match_dup 1) (match_dup 2)))]
3864 (rotate:SI (match_dup 1) (match_dup 2)))
3866 (compare:CC (match_dup 0)
3870 (define_insn "*rotlsi3_internal4"
3871 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3872 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3873 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3874 (match_operand:SI 3 "mask_operand" "n")))]
3876 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3878 (define_insn "*rotlsi3_internal5"
3879 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3881 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3882 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3883 (match_operand:SI 3 "mask_operand" "n,n"))
3885 (clobber (match_scratch:SI 4 "=r,r"))]
3888 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3890 [(set_attr "type" "delayed_compare")
3891 (set_attr "length" "4,8")])
3894 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3896 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3897 (match_operand:SI 2 "reg_or_cint_operand" ""))
3898 (match_operand:SI 3 "mask_operand" ""))
3900 (clobber (match_scratch:SI 4 ""))]
3903 (and:SI (rotate:SI (match_dup 1)
3907 (compare:CC (match_dup 4)
3911 (define_insn "*rotlsi3_internal6"
3912 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3914 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3915 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3916 (match_operand:SI 3 "mask_operand" "n,n"))
3918 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3919 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3922 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3924 [(set_attr "type" "delayed_compare")
3925 (set_attr "length" "4,8")])
3928 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3930 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3931 (match_operand:SI 2 "reg_or_cint_operand" ""))
3932 (match_operand:SI 3 "mask_operand" ""))
3934 (set (match_operand:SI 0 "gpc_reg_operand" "")
3935 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3938 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3940 (compare:CC (match_dup 0)
3944 (define_insn "*rotlsi3_internal7"
3945 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3948 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3949 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3951 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3953 (define_insn "*rotlsi3_internal8"
3954 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3955 (compare:CC (zero_extend:SI
3957 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3958 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3960 (clobber (match_scratch:SI 3 "=r,r"))]
3963 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3965 [(set_attr "type" "delayed_compare")
3966 (set_attr "length" "4,8")])
3969 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3970 (compare:CC (zero_extend:SI
3972 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3973 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3975 (clobber (match_scratch:SI 3 ""))]
3978 (zero_extend:SI (subreg:QI
3979 (rotate:SI (match_dup 1)
3982 (compare:CC (match_dup 3)
3986 (define_insn "*rotlsi3_internal9"
3987 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3988 (compare:CC (zero_extend:SI
3990 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3991 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3993 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3994 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3997 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3999 [(set_attr "type" "delayed_compare")
4000 (set_attr "length" "4,8")])
4003 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4004 (compare:CC (zero_extend:SI
4006 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4007 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4009 (set (match_operand:SI 0 "gpc_reg_operand" "")
4010 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4013 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4015 (compare:CC (match_dup 0)
4019 (define_insn "*rotlsi3_internal10"
4020 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4023 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4024 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4026 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
4028 (define_insn "*rotlsi3_internal11"
4029 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4030 (compare:CC (zero_extend:SI
4032 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4033 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
4035 (clobber (match_scratch:SI 3 "=r,r"))]
4038 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
4040 [(set_attr "type" "delayed_compare")
4041 (set_attr "length" "4,8")])
4044 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4045 (compare:CC (zero_extend:SI
4047 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4048 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4050 (clobber (match_scratch:SI 3 ""))]
4053 (zero_extend:SI (subreg:HI
4054 (rotate:SI (match_dup 1)
4057 (compare:CC (match_dup 3)
4061 (define_insn "*rotlsi3_internal12"
4062 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4063 (compare:CC (zero_extend:SI
4065 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4066 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
4068 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4069 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4072 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
4074 [(set_attr "type" "delayed_compare")
4075 (set_attr "length" "4,8")])
4078 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4079 (compare:CC (zero_extend:SI
4081 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4082 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4084 (set (match_operand:SI 0 "gpc_reg_operand" "")
4085 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4088 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4090 (compare:CC (match_dup 0)
4094 ;; Note that we use "sle." instead of "sl." so that we can set
4095 ;; SHIFT_COUNT_TRUNCATED.
4097 (define_expand "ashlsi3"
4098 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4099 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4100 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4105 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4107 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4111 (define_insn "ashlsi3_power"
4112 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4113 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4114 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4115 (clobber (match_scratch:SI 3 "=q,X"))]
4119 {sli|slwi} %0,%1,%h2")
4121 (define_insn "ashlsi3_no_power"
4122 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4123 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4124 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4126 "{sl|slw}%I2 %0,%1,%h2")
4129 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4130 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4131 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4133 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4134 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4138 {sli.|slwi.} %3,%1,%h2
4141 [(set_attr "type" "delayed_compare")
4142 (set_attr "length" "4,4,8,8")])
4145 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4146 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4147 (match_operand:SI 2 "reg_or_cint_operand" ""))
4149 (clobber (match_scratch:SI 3 ""))
4150 (clobber (match_scratch:SI 4 ""))]
4151 "TARGET_POWER && reload_completed"
4152 [(parallel [(set (match_dup 3)
4153 (ashift:SI (match_dup 1) (match_dup 2)))
4154 (clobber (match_dup 4))])
4156 (compare:CC (match_dup 3)
4161 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4162 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4163 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4165 (clobber (match_scratch:SI 3 "=r,r"))]
4166 "! TARGET_POWER && TARGET_32BIT"
4168 {sl|slw}%I2. %3,%1,%h2
4170 [(set_attr "type" "delayed_compare")
4171 (set_attr "length" "4,8")])
4174 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4175 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4176 (match_operand:SI 2 "reg_or_cint_operand" ""))
4178 (clobber (match_scratch:SI 3 ""))]
4179 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4181 (ashift:SI (match_dup 1) (match_dup 2)))
4183 (compare:CC (match_dup 3)
4188 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4189 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4190 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4192 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4193 (ashift:SI (match_dup 1) (match_dup 2)))
4194 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4198 {sli.|slwi.} %0,%1,%h2
4201 [(set_attr "type" "delayed_compare")
4202 (set_attr "length" "4,4,8,8")])
4205 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4206 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4207 (match_operand:SI 2 "reg_or_cint_operand" ""))
4209 (set (match_operand:SI 0 "gpc_reg_operand" "")
4210 (ashift:SI (match_dup 1) (match_dup 2)))
4211 (clobber (match_scratch:SI 4 ""))]
4212 "TARGET_POWER && reload_completed"
4213 [(parallel [(set (match_dup 0)
4214 (ashift:SI (match_dup 1) (match_dup 2)))
4215 (clobber (match_dup 4))])
4217 (compare:CC (match_dup 0)
4222 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4223 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4224 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4226 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4227 (ashift:SI (match_dup 1) (match_dup 2)))]
4228 "! TARGET_POWER && TARGET_32BIT"
4230 {sl|slw}%I2. %0,%1,%h2
4232 [(set_attr "type" "delayed_compare")
4233 (set_attr "length" "4,8")])
4236 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4237 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4238 (match_operand:SI 2 "reg_or_cint_operand" ""))
4240 (set (match_operand:SI 0 "gpc_reg_operand" "")
4241 (ashift:SI (match_dup 1) (match_dup 2)))]
4242 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4244 (ashift:SI (match_dup 1) (match_dup 2)))
4246 (compare:CC (match_dup 0)
4250 (define_insn "rlwinm"
4251 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4252 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4253 (match_operand:SI 2 "const_int_operand" "i"))
4254 (match_operand:SI 3 "mask_operand" "n")))]
4255 "includes_lshift_p (operands[2], operands[3])"
4256 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4259 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4261 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4262 (match_operand:SI 2 "const_int_operand" "i,i"))
4263 (match_operand:SI 3 "mask_operand" "n,n"))
4265 (clobber (match_scratch:SI 4 "=r,r"))]
4266 "includes_lshift_p (operands[2], operands[3])"
4268 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4270 [(set_attr "type" "delayed_compare")
4271 (set_attr "length" "4,8")])
4274 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4276 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4277 (match_operand:SI 2 "const_int_operand" ""))
4278 (match_operand:SI 3 "mask_operand" ""))
4280 (clobber (match_scratch:SI 4 ""))]
4281 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4283 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4286 (compare:CC (match_dup 4)
4291 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4293 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4294 (match_operand:SI 2 "const_int_operand" "i,i"))
4295 (match_operand:SI 3 "mask_operand" "n,n"))
4297 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4298 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4299 "includes_lshift_p (operands[2], operands[3])"
4301 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4303 [(set_attr "type" "delayed_compare")
4304 (set_attr "length" "4,8")])
4307 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4309 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4310 (match_operand:SI 2 "const_int_operand" ""))
4311 (match_operand:SI 3 "mask_operand" ""))
4313 (set (match_operand:SI 0 "gpc_reg_operand" "")
4314 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4315 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4317 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4319 (compare:CC (match_dup 0)
4323 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4325 (define_expand "lshrsi3"
4326 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4327 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4328 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4333 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4335 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4339 (define_insn "lshrsi3_power"
4340 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4341 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4342 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4343 (clobber (match_scratch:SI 3 "=q,X,X"))]
4348 {s%A2i|s%A2wi} %0,%1,%h2")
4350 (define_insn "lshrsi3_no_power"
4351 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4352 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4353 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
4357 {sr|srw}%I2 %0,%1,%h2")
4360 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4361 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4362 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4364 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4365 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4370 {s%A2i.|s%A2wi.} %3,%1,%h2
4374 [(set_attr "type" "delayed_compare")
4375 (set_attr "length" "4,4,4,8,8,8")])
4378 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4379 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4380 (match_operand:SI 2 "reg_or_cint_operand" ""))
4382 (clobber (match_scratch:SI 3 ""))
4383 (clobber (match_scratch:SI 4 ""))]
4384 "TARGET_POWER && reload_completed"
4385 [(parallel [(set (match_dup 3)
4386 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4387 (clobber (match_dup 4))])
4389 (compare:CC (match_dup 3)
4394 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4395 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4396 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4398 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
4399 "! TARGET_POWER && TARGET_32BIT"
4402 {sr|srw}%I2. %3,%1,%h2
4405 [(set_attr "type" "delayed_compare")
4406 (set_attr "length" "4,4,8,8")])
4409 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4410 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4411 (match_operand:SI 2 "reg_or_cint_operand" ""))
4413 (clobber (match_scratch:SI 3 ""))]
4414 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4416 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4418 (compare:CC (match_dup 3)
4423 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4424 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4425 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4427 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4428 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4429 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4434 {s%A2i.|s%A2wi.} %0,%1,%h2
4438 [(set_attr "type" "delayed_compare")
4439 (set_attr "length" "4,4,4,8,8,8")])
4442 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4443 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4444 (match_operand:SI 2 "reg_or_cint_operand" ""))
4446 (set (match_operand:SI 0 "gpc_reg_operand" "")
4447 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4448 (clobber (match_scratch:SI 4 ""))]
4449 "TARGET_POWER && reload_completed"
4450 [(parallel [(set (match_dup 0)
4451 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4452 (clobber (match_dup 4))])
4454 (compare:CC (match_dup 0)
4459 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4460 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4461 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4463 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4464 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4465 "! TARGET_POWER && TARGET_32BIT"
4468 {sr|srw}%I2. %0,%1,%h2
4471 [(set_attr "type" "delayed_compare")
4472 (set_attr "length" "4,4,8,8")])
4475 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4476 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4477 (match_operand:SI 2 "reg_or_cint_operand" ""))
4479 (set (match_operand:SI 0 "gpc_reg_operand" "")
4480 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4481 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4483 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4485 (compare:CC (match_dup 0)
4490 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4491 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4492 (match_operand:SI 2 "const_int_operand" "i"))
4493 (match_operand:SI 3 "mask_operand" "n")))]
4494 "includes_rshift_p (operands[2], operands[3])"
4495 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4498 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4500 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4501 (match_operand:SI 2 "const_int_operand" "i,i"))
4502 (match_operand:SI 3 "mask_operand" "n,n"))
4504 (clobber (match_scratch:SI 4 "=r,r"))]
4505 "includes_rshift_p (operands[2], operands[3])"
4507 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4509 [(set_attr "type" "delayed_compare")
4510 (set_attr "length" "4,8")])
4513 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4515 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4516 (match_operand:SI 2 "const_int_operand" ""))
4517 (match_operand:SI 3 "mask_operand" ""))
4519 (clobber (match_scratch:SI 4 ""))]
4520 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4522 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4525 (compare:CC (match_dup 4)
4530 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4532 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4533 (match_operand:SI 2 "const_int_operand" "i,i"))
4534 (match_operand:SI 3 "mask_operand" "n,n"))
4536 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4537 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4538 "includes_rshift_p (operands[2], operands[3])"
4540 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4542 [(set_attr "type" "delayed_compare")
4543 (set_attr "length" "4,8")])
4546 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4548 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4549 (match_operand:SI 2 "const_int_operand" ""))
4550 (match_operand:SI 3 "mask_operand" ""))
4552 (set (match_operand:SI 0 "gpc_reg_operand" "")
4553 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4554 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4556 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4558 (compare:CC (match_dup 0)
4563 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4566 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4567 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4568 "includes_rshift_p (operands[2], GEN_INT (255))"
4569 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4572 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4576 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4577 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4579 (clobber (match_scratch:SI 3 "=r,r"))]
4580 "includes_rshift_p (operands[2], GEN_INT (255))"
4582 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4584 [(set_attr "type" "delayed_compare")
4585 (set_attr "length" "4,8")])
4588 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4592 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4593 (match_operand:SI 2 "const_int_operand" "")) 0))
4595 (clobber (match_scratch:SI 3 ""))]
4596 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4598 (zero_extend:SI (subreg:QI
4599 (lshiftrt:SI (match_dup 1)
4602 (compare:CC (match_dup 3)
4607 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4611 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4612 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4614 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4615 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4616 "includes_rshift_p (operands[2], GEN_INT (255))"
4618 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4620 [(set_attr "type" "delayed_compare")
4621 (set_attr "length" "4,8")])
4624 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4628 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4629 (match_operand:SI 2 "const_int_operand" "")) 0))
4631 (set (match_operand:SI 0 "gpc_reg_operand" "")
4632 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4633 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4635 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4637 (compare:CC (match_dup 0)
4642 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4645 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4646 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4647 "includes_rshift_p (operands[2], GEN_INT (65535))"
4648 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4651 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4655 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4656 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4658 (clobber (match_scratch:SI 3 "=r,r"))]
4659 "includes_rshift_p (operands[2], GEN_INT (65535))"
4661 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4663 [(set_attr "type" "delayed_compare")
4664 (set_attr "length" "4,8")])
4667 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4671 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4672 (match_operand:SI 2 "const_int_operand" "")) 0))
4674 (clobber (match_scratch:SI 3 ""))]
4675 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4677 (zero_extend:SI (subreg:HI
4678 (lshiftrt:SI (match_dup 1)
4681 (compare:CC (match_dup 3)
4686 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4690 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4691 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4693 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4694 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4695 "includes_rshift_p (operands[2], GEN_INT (65535))"
4697 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4699 [(set_attr "type" "delayed_compare")
4700 (set_attr "length" "4,8")])
4703 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4707 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4708 (match_operand:SI 2 "const_int_operand" "")) 0))
4710 (set (match_operand:SI 0 "gpc_reg_operand" "")
4711 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4712 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4714 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4716 (compare:CC (match_dup 0)
4721 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4723 (match_operand:SI 1 "gpc_reg_operand" "r"))
4724 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4730 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4732 (match_operand:SI 1 "gpc_reg_operand" "r"))
4733 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4739 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4741 (match_operand:SI 1 "gpc_reg_operand" "r"))
4742 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4748 (define_expand "ashrsi3"
4749 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4750 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4751 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4756 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4758 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4762 (define_insn "ashrsi3_power"
4763 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4764 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4765 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4766 (clobber (match_scratch:SI 3 "=q,X"))]
4770 {srai|srawi} %0,%1,%h2")
4772 (define_insn "ashrsi3_no_power"
4773 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4774 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4775 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4777 "{sra|sraw}%I2 %0,%1,%h2")
4780 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4781 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4782 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4784 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4785 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4789 {srai.|srawi.} %3,%1,%h2
4792 [(set_attr "type" "delayed_compare")
4793 (set_attr "length" "4,4,8,8")])
4796 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4797 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4798 (match_operand:SI 2 "reg_or_cint_operand" ""))
4800 (clobber (match_scratch:SI 3 ""))
4801 (clobber (match_scratch:SI 4 ""))]
4802 "TARGET_POWER && reload_completed"
4803 [(parallel [(set (match_dup 3)
4804 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4805 (clobber (match_dup 4))])
4807 (compare:CC (match_dup 3)
4812 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4813 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4814 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4816 (clobber (match_scratch:SI 3 "=r,r"))]
4819 {sra|sraw}%I2. %3,%1,%h2
4821 [(set_attr "type" "delayed_compare")
4822 (set_attr "length" "4,8")])
4825 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4826 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4827 (match_operand:SI 2 "reg_or_cint_operand" ""))
4829 (clobber (match_scratch:SI 3 ""))]
4830 "! TARGET_POWER && reload_completed"
4832 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4834 (compare:CC (match_dup 3)
4839 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4840 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4841 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4843 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4844 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4845 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4849 {srai.|srawi.} %0,%1,%h2
4852 [(set_attr "type" "delayed_compare")
4853 (set_attr "length" "4,4,8,8")])
4856 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4857 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4858 (match_operand:SI 2 "reg_or_cint_operand" ""))
4860 (set (match_operand:SI 0 "gpc_reg_operand" "")
4861 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4862 (clobber (match_scratch:SI 4 ""))]
4863 "TARGET_POWER && reload_completed"
4864 [(parallel [(set (match_dup 0)
4865 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4866 (clobber (match_dup 4))])
4868 (compare:CC (match_dup 0)
4873 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4874 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4875 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4877 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4878 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4881 {sra|sraw}%I2. %0,%1,%h2
4883 [(set_attr "type" "delayed_compare")
4884 (set_attr "length" "4,8")])
4887 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4888 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4889 (match_operand:SI 2 "reg_or_cint_operand" ""))
4891 (set (match_operand:SI 0 "gpc_reg_operand" "")
4892 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4893 "! TARGET_POWER && reload_completed"
4895 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4897 (compare:CC (match_dup 0)
4901 ;; Floating-point insns, excluding normal data motion.
4903 ;; PowerPC has a full set of single-precision floating point instructions.
4905 ;; For the POWER architecture, we pretend that we have both SFmode and
4906 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4907 ;; The only conversions we will do will be when storing to memory. In that
4908 ;; case, we will use the "frsp" instruction before storing.
4910 ;; Note that when we store into a single-precision memory location, we need to
4911 ;; use the frsp insn first. If the register being stored isn't dead, we
4912 ;; need a scratch register for the frsp. But this is difficult when the store
4913 ;; is done by reload. It is not incorrect to do the frsp on the register in
4914 ;; this case, we just lose precision that we would have otherwise gotten but
4915 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4917 (define_expand "extendsfdf2"
4918 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4919 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4920 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4923 (define_insn_and_split "*extendsfdf2_fpr"
4924 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4925 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4926 "TARGET_HARD_FLOAT && TARGET_FPRS"
4931 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4934 emit_note (NOTE_INSN_DELETED);
4937 [(set_attr "type" "fp,fp,fpload")])
4939 (define_expand "truncdfsf2"
4940 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4941 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4942 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4945 (define_insn "*truncdfsf2_fpr"
4946 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4947 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4948 "TARGET_HARD_FLOAT && TARGET_FPRS"
4950 [(set_attr "type" "fp")])
4952 (define_insn "aux_truncdfsf2"
4953 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4954 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4955 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4957 [(set_attr "type" "fp")])
4959 (define_expand "negsf2"
4960 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4961 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4965 (define_insn "*negsf2"
4966 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4967 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4968 "TARGET_HARD_FLOAT && TARGET_FPRS"
4970 [(set_attr "type" "fp")])
4972 (define_expand "abssf2"
4973 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4974 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4978 (define_insn "*abssf2"
4979 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4980 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4981 "TARGET_HARD_FLOAT && TARGET_FPRS"
4983 [(set_attr "type" "fp")])
4986 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4987 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4988 "TARGET_HARD_FLOAT && TARGET_FPRS"
4990 [(set_attr "type" "fp")])
4992 (define_expand "addsf3"
4993 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4994 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4995 (match_operand:SF 2 "gpc_reg_operand" "")))]
5000 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5001 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5002 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5003 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5005 [(set_attr "type" "fp")])
5008 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5009 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5010 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5011 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5012 "{fa|fadd} %0,%1,%2"
5013 [(set_attr "type" "fp")])
5015 (define_expand "subsf3"
5016 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5017 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5018 (match_operand:SF 2 "gpc_reg_operand" "")))]
5023 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5024 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5025 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5026 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5028 [(set_attr "type" "fp")])
5031 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5032 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5033 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5034 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5035 "{fs|fsub} %0,%1,%2"
5036 [(set_attr "type" "fp")])
5038 (define_expand "mulsf3"
5039 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5040 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5041 (match_operand:SF 2 "gpc_reg_operand" "")))]
5046 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5047 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5048 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5049 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5051 [(set_attr "type" "fp")])
5054 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5055 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5056 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5057 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5058 "{fm|fmul} %0,%1,%2"
5059 [(set_attr "type" "dmul")])
5062 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5063 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5064 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5066 [(set_attr "type" "fp")])
5068 (define_expand "divsf3"
5069 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5070 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5071 (match_operand:SF 2 "gpc_reg_operand" "")))]
5074 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
5075 && flag_finite_math_only && !flag_trapping_math)
5077 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5083 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5084 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5085 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5086 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5088 [(set_attr "type" "sdiv")])
5091 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5092 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5093 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5094 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5095 "{fd|fdiv} %0,%1,%2"
5096 [(set_attr "type" "ddiv")])
5099 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5100 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5101 (match_operand:SF 2 "gpc_reg_operand" "f"))
5102 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5103 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5104 "fmadds %0,%1,%2,%3"
5105 [(set_attr "type" "fp")])
5108 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5109 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5110 (match_operand:SF 2 "gpc_reg_operand" "f"))
5111 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5112 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5113 "{fma|fmadd} %0,%1,%2,%3"
5114 [(set_attr "type" "dmul")])
5117 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5118 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5119 (match_operand:SF 2 "gpc_reg_operand" "f"))
5120 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5121 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5122 "fmsubs %0,%1,%2,%3"
5123 [(set_attr "type" "fp")])
5126 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5127 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5128 (match_operand:SF 2 "gpc_reg_operand" "f"))
5129 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5130 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5131 "{fms|fmsub} %0,%1,%2,%3"
5132 [(set_attr "type" "dmul")])
5135 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5136 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5137 (match_operand:SF 2 "gpc_reg_operand" "f"))
5138 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5139 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5140 && HONOR_SIGNED_ZEROS (SFmode)"
5141 "fnmadds %0,%1,%2,%3"
5142 [(set_attr "type" "fp")])
5145 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5146 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5147 (match_operand:SF 2 "gpc_reg_operand" "f"))
5148 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5149 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5150 && ! HONOR_SIGNED_ZEROS (SFmode)"
5151 "fnmadds %0,%1,%2,%3"
5152 [(set_attr "type" "fp")])
5155 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5156 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5157 (match_operand:SF 2 "gpc_reg_operand" "f"))
5158 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5159 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5160 "{fnma|fnmadd} %0,%1,%2,%3"
5161 [(set_attr "type" "dmul")])
5164 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5165 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5166 (match_operand:SF 2 "gpc_reg_operand" "f"))
5167 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5168 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5169 && ! HONOR_SIGNED_ZEROS (SFmode)"
5170 "{fnma|fnmadd} %0,%1,%2,%3"
5171 [(set_attr "type" "dmul")])
5174 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5175 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5176 (match_operand:SF 2 "gpc_reg_operand" "f"))
5177 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5178 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5179 && HONOR_SIGNED_ZEROS (SFmode)"
5180 "fnmsubs %0,%1,%2,%3"
5181 [(set_attr "type" "fp")])
5184 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5185 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5186 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5187 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5188 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5189 && ! HONOR_SIGNED_ZEROS (SFmode)"
5190 "fnmsubs %0,%1,%2,%3"
5191 [(set_attr "type" "fp")])
5194 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5195 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5196 (match_operand:SF 2 "gpc_reg_operand" "f"))
5197 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5198 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5199 "{fnms|fnmsub} %0,%1,%2,%3"
5200 [(set_attr "type" "dmul")])
5203 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5204 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5205 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5206 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5207 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5208 && ! HONOR_SIGNED_ZEROS (SFmode)"
5209 "{fnms|fnmsub} %0,%1,%2,%3"
5210 [(set_attr "type" "dmul")])
5212 (define_expand "sqrtsf2"
5213 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5214 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5215 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5219 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5220 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5221 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5223 [(set_attr "type" "ssqrt")])
5226 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5227 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5228 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
5230 [(set_attr "type" "dsqrt")])
5232 (define_expand "copysignsf3"
5234 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5236 (neg:SF (abs:SF (match_dup 1))))
5237 (set (match_operand:SF 0 "gpc_reg_operand" "")
5238 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5242 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5243 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5245 operands[3] = gen_reg_rtx (SFmode);
5246 operands[4] = gen_reg_rtx (SFmode);
5247 operands[5] = CONST0_RTX (SFmode);
5250 (define_expand "copysigndf3"
5252 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5254 (neg:DF (abs:DF (match_dup 1))))
5255 (set (match_operand:DF 0 "gpc_reg_operand" "")
5256 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5260 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5261 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5263 operands[3] = gen_reg_rtx (DFmode);
5264 operands[4] = gen_reg_rtx (DFmode);
5265 operands[5] = CONST0_RTX (DFmode);
5268 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5269 ;; fsel instruction and some auxiliary computations. Then we just have a
5270 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5272 (define_expand "smaxsf3"
5273 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5274 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5275 (match_operand:SF 2 "gpc_reg_operand" ""))
5278 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5279 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5281 (define_expand "sminsf3"
5282 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5283 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5284 (match_operand:SF 2 "gpc_reg_operand" ""))
5287 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5288 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5291 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5292 (match_operator:SF 3 "min_max_operator"
5293 [(match_operand:SF 1 "gpc_reg_operand" "")
5294 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5295 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5298 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5299 operands[1], operands[2]);
5303 (define_expand "movsicc"
5304 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5305 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5306 (match_operand:SI 2 "gpc_reg_operand" "")
5307 (match_operand:SI 3 "gpc_reg_operand" "")))]
5311 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5317 ;; We use the BASE_REGS for the isel input operands because, if rA is
5318 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5319 ;; because we may switch the operands and rB may end up being rA.
5321 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5322 ;; leave out the mode in operand 4 and use one pattern, but reload can
5323 ;; change the mode underneath our feet and then gets confused trying
5324 ;; to reload the value.
5325 (define_insn "isel_signed"
5326 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5328 (match_operator 1 "comparison_operator"
5329 [(match_operand:CC 4 "cc_reg_operand" "y")
5331 (match_operand:SI 2 "gpc_reg_operand" "b")
5332 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5335 { return output_isel (operands); }"
5336 [(set_attr "length" "4")])
5338 (define_insn "isel_unsigned"
5339 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5341 (match_operator 1 "comparison_operator"
5342 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5344 (match_operand:SI 2 "gpc_reg_operand" "b")
5345 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5348 { return output_isel (operands); }"
5349 [(set_attr "length" "4")])
5351 (define_expand "movsfcc"
5352 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5353 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5354 (match_operand:SF 2 "gpc_reg_operand" "")
5355 (match_operand:SF 3 "gpc_reg_operand" "")))]
5356 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5359 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5365 (define_insn "*fselsfsf4"
5366 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5367 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5368 (match_operand:SF 4 "zero_fp_constant" "F"))
5369 (match_operand:SF 2 "gpc_reg_operand" "f")
5370 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5371 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5373 [(set_attr "type" "fp")])
5375 (define_insn "*fseldfsf4"
5376 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5377 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5378 (match_operand:DF 4 "zero_fp_constant" "F"))
5379 (match_operand:SF 2 "gpc_reg_operand" "f")
5380 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5381 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5383 [(set_attr "type" "fp")])
5385 (define_expand "negdf2"
5386 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5387 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5388 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5391 (define_insn "*negdf2_fpr"
5392 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5393 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5394 "TARGET_HARD_FLOAT && TARGET_FPRS"
5396 [(set_attr "type" "fp")])
5398 (define_expand "absdf2"
5399 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5400 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5401 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5404 (define_insn "*absdf2_fpr"
5405 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5406 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5407 "TARGET_HARD_FLOAT && TARGET_FPRS"
5409 [(set_attr "type" "fp")])
5411 (define_insn "*nabsdf2_fpr"
5412 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5413 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5414 "TARGET_HARD_FLOAT && TARGET_FPRS"
5416 [(set_attr "type" "fp")])
5418 (define_expand "adddf3"
5419 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5420 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5421 (match_operand:DF 2 "gpc_reg_operand" "")))]
5422 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5425 (define_insn "*adddf3_fpr"
5426 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5427 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5428 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5429 "TARGET_HARD_FLOAT && TARGET_FPRS"
5430 "{fa|fadd} %0,%1,%2"
5431 [(set_attr "type" "fp")])
5433 (define_expand "subdf3"
5434 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5435 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5436 (match_operand:DF 2 "gpc_reg_operand" "")))]
5437 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5440 (define_insn "*subdf3_fpr"
5441 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5442 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5443 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5444 "TARGET_HARD_FLOAT && TARGET_FPRS"
5445 "{fs|fsub} %0,%1,%2"
5446 [(set_attr "type" "fp")])
5448 (define_expand "muldf3"
5449 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5450 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5451 (match_operand:DF 2 "gpc_reg_operand" "")))]
5452 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5455 (define_insn "*muldf3_fpr"
5456 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5457 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5458 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5459 "TARGET_HARD_FLOAT && TARGET_FPRS"
5460 "{fm|fmul} %0,%1,%2"
5461 [(set_attr "type" "dmul")])
5464 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5465 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5466 "TARGET_POPCNTB && flag_finite_math_only"
5468 [(set_attr "type" "fp")])
5470 (define_expand "divdf3"
5471 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5472 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5473 (match_operand:DF 2 "gpc_reg_operand" "")))]
5474 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5476 if (swdiv && !optimize_size && TARGET_POPCNTB
5477 && flag_finite_math_only && !flag_trapping_math)
5479 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5484 (define_insn "*divdf3_fpr"
5485 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5486 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5487 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5488 "TARGET_HARD_FLOAT && TARGET_FPRS"
5489 "{fd|fdiv} %0,%1,%2"
5490 [(set_attr "type" "ddiv")])
5493 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5494 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5495 (match_operand:DF 2 "gpc_reg_operand" "f"))
5496 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5497 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5498 "{fma|fmadd} %0,%1,%2,%3"
5499 [(set_attr "type" "dmul")])
5502 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5503 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5504 (match_operand:DF 2 "gpc_reg_operand" "f"))
5505 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5506 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5507 "{fms|fmsub} %0,%1,%2,%3"
5508 [(set_attr "type" "dmul")])
5511 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5512 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5513 (match_operand:DF 2 "gpc_reg_operand" "f"))
5514 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5515 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5516 && HONOR_SIGNED_ZEROS (DFmode)"
5517 "{fnma|fnmadd} %0,%1,%2,%3"
5518 [(set_attr "type" "dmul")])
5521 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5522 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5523 (match_operand:DF 2 "gpc_reg_operand" "f"))
5524 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5525 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5526 && ! HONOR_SIGNED_ZEROS (DFmode)"
5527 "{fnma|fnmadd} %0,%1,%2,%3"
5528 [(set_attr "type" "dmul")])
5531 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5532 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5533 (match_operand:DF 2 "gpc_reg_operand" "f"))
5534 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5535 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5536 && HONOR_SIGNED_ZEROS (DFmode)"
5537 "{fnms|fnmsub} %0,%1,%2,%3"
5538 [(set_attr "type" "dmul")])
5541 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5542 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5543 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5544 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5545 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5546 && ! HONOR_SIGNED_ZEROS (DFmode)"
5547 "{fnms|fnmsub} %0,%1,%2,%3"
5548 [(set_attr "type" "dmul")])
5550 (define_insn "sqrtdf2"
5551 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5552 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5553 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5555 [(set_attr "type" "dsqrt")])
5557 ;; The conditional move instructions allow us to perform max and min
5558 ;; operations even when
5560 (define_expand "smaxdf3"
5561 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5562 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5563 (match_operand:DF 2 "gpc_reg_operand" ""))
5566 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5567 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5569 (define_expand "smindf3"
5570 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5571 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5572 (match_operand:DF 2 "gpc_reg_operand" ""))
5575 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5576 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5579 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5580 (match_operator:DF 3 "min_max_operator"
5581 [(match_operand:DF 1 "gpc_reg_operand" "")
5582 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5583 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5586 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5587 operands[1], operands[2]);
5591 (define_expand "movdfcc"
5592 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5593 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5594 (match_operand:DF 2 "gpc_reg_operand" "")
5595 (match_operand:DF 3 "gpc_reg_operand" "")))]
5596 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5599 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5605 (define_insn "*fseldfdf4"
5606 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5607 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5608 (match_operand:DF 4 "zero_fp_constant" "F"))
5609 (match_operand:DF 2 "gpc_reg_operand" "f")
5610 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5611 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5613 [(set_attr "type" "fp")])
5615 (define_insn "*fselsfdf4"
5616 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5617 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5618 (match_operand:SF 4 "zero_fp_constant" "F"))
5619 (match_operand:DF 2 "gpc_reg_operand" "f")
5620 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5623 [(set_attr "type" "fp")])
5625 ;; Conversions to and from floating-point.
5627 (define_expand "fixuns_truncsfsi2"
5628 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5629 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5630 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5633 (define_expand "fix_truncsfsi2"
5634 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5635 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5636 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5639 ; For each of these conversions, there is a define_expand, a define_insn
5640 ; with a '#' template, and a define_split (with C code). The idea is
5641 ; to allow constant folding with the template of the define_insn,
5642 ; then to have the insns split later (between sched1 and final).
5644 (define_expand "floatsidf2"
5645 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5646 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5649 (clobber (match_dup 4))
5650 (clobber (match_dup 5))
5651 (clobber (match_dup 6))])]
5652 "TARGET_HARD_FLOAT && TARGET_FPRS"
5655 if (TARGET_E500_DOUBLE)
5657 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5660 if (TARGET_POWERPC64)
5662 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5663 rtx t1 = gen_reg_rtx (DImode);
5664 rtx t2 = gen_reg_rtx (DImode);
5665 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5669 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5670 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5671 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5672 operands[5] = gen_reg_rtx (DFmode);
5673 operands[6] = gen_reg_rtx (SImode);
5676 (define_insn_and_split "*floatsidf2_internal"
5677 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5678 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5679 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5680 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5681 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5682 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5683 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5684 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5686 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5690 rtx lowword, highword;
5691 gcc_assert (MEM_P (operands[4]));
5692 highword = adjust_address (operands[4], SImode, 0);
5693 lowword = adjust_address (operands[4], SImode, 4);
5694 if (! WORDS_BIG_ENDIAN)
5697 tmp = highword; highword = lowword; lowword = tmp;
5700 emit_insn (gen_xorsi3 (operands[6], operands[1],
5701 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5702 emit_move_insn (lowword, operands[6]);
5703 emit_move_insn (highword, operands[2]);
5704 emit_move_insn (operands[5], operands[4]);
5705 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5708 [(set_attr "length" "24")])
5710 (define_expand "floatunssisf2"
5711 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5712 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5713 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5716 (define_expand "floatunssidf2"
5717 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5718 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5721 (clobber (match_dup 4))
5722 (clobber (match_dup 5))])]
5723 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5726 if (TARGET_E500_DOUBLE)
5728 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5731 if (TARGET_POWERPC64)
5733 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5734 rtx t1 = gen_reg_rtx (DImode);
5735 rtx t2 = gen_reg_rtx (DImode);
5736 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5741 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5742 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5743 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5744 operands[5] = gen_reg_rtx (DFmode);
5747 (define_insn_and_split "*floatunssidf2_internal"
5748 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5749 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5750 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5751 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5752 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5753 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5754 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5756 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5760 rtx lowword, highword;
5761 gcc_assert (MEM_P (operands[4]));
5762 highword = adjust_address (operands[4], SImode, 0);
5763 lowword = adjust_address (operands[4], SImode, 4);
5764 if (! WORDS_BIG_ENDIAN)
5767 tmp = highword; highword = lowword; lowword = tmp;
5770 emit_move_insn (lowword, operands[1]);
5771 emit_move_insn (highword, operands[2]);
5772 emit_move_insn (operands[5], operands[4]);
5773 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5776 [(set_attr "length" "20")])
5778 (define_expand "fix_truncdfsi2"
5779 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5780 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5781 (clobber (match_dup 2))
5782 (clobber (match_dup 3))])]
5783 "(TARGET_POWER2 || TARGET_POWERPC)
5784 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5787 if (TARGET_E500_DOUBLE)
5789 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5792 operands[2] = gen_reg_rtx (DImode);
5793 if (TARGET_PPC_GFXOPT)
5795 rtx orig_dest = operands[0];
5796 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5797 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5798 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5800 if (operands[0] != orig_dest)
5801 emit_move_insn (orig_dest, operands[0]);
5804 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5807 (define_insn_and_split "*fix_truncdfsi2_internal"
5808 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5809 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5810 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5811 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5812 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5814 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5819 gcc_assert (MEM_P (operands[3]));
5820 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5822 emit_insn (gen_fctiwz (operands[2], operands[1]));
5823 emit_move_insn (operands[3], operands[2]);
5824 emit_move_insn (operands[0], lowword);
5827 [(set_attr "length" "16")])
5829 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5830 [(set (match_operand:SI 0 "memory_operand" "=Z")
5831 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5832 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5833 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5834 && TARGET_PPC_GFXOPT"
5840 emit_insn (gen_fctiwz (operands[2], operands[1]));
5841 emit_insn (gen_stfiwx (operands[0], operands[2]));
5844 [(set_attr "length" "16")])
5846 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5847 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5848 ; because the first makes it clear that operand 0 is not live
5849 ; before the instruction.
5850 (define_insn "fctiwz"
5851 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5852 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5854 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5855 "{fcirz|fctiwz} %0,%1"
5856 [(set_attr "type" "fp")])
5858 (define_insn "btruncdf2"
5859 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5860 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5861 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5863 [(set_attr "type" "fp")])
5865 (define_insn "btruncsf2"
5866 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5867 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5868 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5870 [(set_attr "type" "fp")])
5872 (define_insn "ceildf2"
5873 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5874 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5875 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5877 [(set_attr "type" "fp")])
5879 (define_insn "ceilsf2"
5880 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5881 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5882 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5884 [(set_attr "type" "fp")])
5886 (define_insn "floordf2"
5887 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5888 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
5889 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5891 [(set_attr "type" "fp")])
5893 (define_insn "floorsf2"
5894 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5895 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
5896 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5898 [(set_attr "type" "fp")])
5900 (define_insn "rounddf2"
5901 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5902 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
5903 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5905 [(set_attr "type" "fp")])
5907 (define_insn "roundsf2"
5908 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5909 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
5910 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5912 [(set_attr "type" "fp")])
5914 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5915 (define_insn "stfiwx"
5916 [(set (match_operand:SI 0 "memory_operand" "=Z")
5917 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
5921 [(set_attr "type" "fpstore")])
5923 (define_expand "floatsisf2"
5924 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5925 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5926 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5929 (define_insn "floatdidf2"
5930 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5931 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5932 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5934 [(set_attr "type" "fp")])
5936 (define_insn_and_split "floatsidf_ppc64"
5937 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5938 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5939 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5940 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5941 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5942 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5945 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5946 (set (match_dup 2) (match_dup 3))
5947 (set (match_dup 4) (match_dup 2))
5948 (set (match_dup 0) (float:DF (match_dup 4)))]
5951 (define_insn_and_split "floatunssidf_ppc64"
5952 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5953 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5954 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5955 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5956 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5957 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5960 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5961 (set (match_dup 2) (match_dup 3))
5962 (set (match_dup 4) (match_dup 2))
5963 (set (match_dup 0) (float:DF (match_dup 4)))]
5966 (define_insn "fix_truncdfdi2"
5967 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5968 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5969 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5971 [(set_attr "type" "fp")])
5973 (define_expand "floatdisf2"
5974 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5975 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5976 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5979 rtx val = operands[1];
5980 if (!flag_unsafe_math_optimizations)
5982 rtx label = gen_label_rtx ();
5983 val = gen_reg_rtx (DImode);
5984 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5987 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5991 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5992 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5993 ;; from double rounding.
5994 (define_insn_and_split "floatdisf2_internal1"
5995 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5996 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5997 (clobber (match_scratch:DF 2 "=f"))]
5998 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6000 "&& reload_completed"
6002 (float:DF (match_dup 1)))
6004 (float_truncate:SF (match_dup 2)))]
6007 ;; Twiddles bits to avoid double rounding.
6008 ;; Bits that might be truncated when converting to DFmode are replaced
6009 ;; by a bit that won't be lost at that stage, but is below the SFmode
6010 ;; rounding position.
6011 (define_expand "floatdisf2_internal2"
6012 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6014 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6016 (clobber (scratch:CC))])
6017 (set (match_dup 3) (plus:DI (match_dup 3)
6019 (set (match_dup 0) (plus:DI (match_dup 0)
6021 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6023 (set (match_dup 0) (ior:DI (match_dup 0)
6025 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6027 (clobber (scratch:CC))])
6028 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6029 (label_ref (match_operand:DI 2 "" ""))
6031 (set (match_dup 0) (match_dup 1))]
6032 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6035 operands[3] = gen_reg_rtx (DImode);
6036 operands[4] = gen_reg_rtx (CCUNSmode);
6039 ;; Define the DImode operations that can be done in a small number
6040 ;; of instructions. The & constraints are to prevent the register
6041 ;; allocator from allocating registers that overlap with the inputs
6042 ;; (for example, having an input in 7,8 and an output in 6,7). We
6043 ;; also allow for the output being the same as one of the inputs.
6045 (define_insn "*adddi3_noppc64"
6046 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6047 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6048 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6049 "! TARGET_POWERPC64"
6052 if (WORDS_BIG_ENDIAN)
6053 return (GET_CODE (operands[2])) != CONST_INT
6054 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6055 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6057 return (GET_CODE (operands[2])) != CONST_INT
6058 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6059 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6061 [(set_attr "type" "two")
6062 (set_attr "length" "8")])
6064 (define_insn "*subdi3_noppc64"
6065 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6066 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6067 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6068 "! TARGET_POWERPC64"
6071 if (WORDS_BIG_ENDIAN)
6072 return (GET_CODE (operands[1]) != CONST_INT)
6073 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6074 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6076 return (GET_CODE (operands[1]) != CONST_INT)
6077 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6078 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6080 [(set_attr "type" "two")
6081 (set_attr "length" "8")])
6083 (define_insn "*negdi2_noppc64"
6084 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6085 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6086 "! TARGET_POWERPC64"
6089 return (WORDS_BIG_ENDIAN)
6090 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6091 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6093 [(set_attr "type" "two")
6094 (set_attr "length" "8")])
6096 (define_expand "mulsidi3"
6097 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6098 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6099 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6100 "! TARGET_POWERPC64"
6103 if (! TARGET_POWER && ! TARGET_POWERPC)
6105 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6106 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6107 emit_insn (gen_mull_call ());
6108 if (WORDS_BIG_ENDIAN)
6109 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6112 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6113 gen_rtx_REG (SImode, 3));
6114 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6115 gen_rtx_REG (SImode, 4));
6119 else if (TARGET_POWER)
6121 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6126 (define_insn "mulsidi3_mq"
6127 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6128 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6129 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6130 (clobber (match_scratch:SI 3 "=q"))]
6132 "mul %0,%1,%2\;mfmq %L0"
6133 [(set_attr "type" "imul")
6134 (set_attr "length" "8")])
6136 (define_insn "*mulsidi3_no_mq"
6137 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6138 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6139 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6140 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6143 return (WORDS_BIG_ENDIAN)
6144 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6145 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6147 [(set_attr "type" "imul")
6148 (set_attr "length" "8")])
6151 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6152 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6153 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6154 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6157 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6158 (sign_extend:DI (match_dup 2)))
6161 (mult:SI (match_dup 1)
6165 int endian = (WORDS_BIG_ENDIAN == 0);
6166 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6167 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6170 (define_expand "umulsidi3"
6171 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6172 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6173 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6174 "TARGET_POWERPC && ! TARGET_POWERPC64"
6179 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6184 (define_insn "umulsidi3_mq"
6185 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6186 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6187 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6188 (clobber (match_scratch:SI 3 "=q"))]
6189 "TARGET_POWERPC && TARGET_POWER"
6192 return (WORDS_BIG_ENDIAN)
6193 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6194 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6196 [(set_attr "type" "imul")
6197 (set_attr "length" "8")])
6199 (define_insn "*umulsidi3_no_mq"
6200 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6201 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6202 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6203 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6206 return (WORDS_BIG_ENDIAN)
6207 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6208 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6210 [(set_attr "type" "imul")
6211 (set_attr "length" "8")])
6214 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6215 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6216 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6217 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6220 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6221 (zero_extend:DI (match_dup 2)))
6224 (mult:SI (match_dup 1)
6228 int endian = (WORDS_BIG_ENDIAN == 0);
6229 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6230 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6233 (define_expand "smulsi3_highpart"
6234 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6236 (lshiftrt:DI (mult:DI (sign_extend:DI
6237 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6239 (match_operand:SI 2 "gpc_reg_operand" "r")))
6244 if (! TARGET_POWER && ! TARGET_POWERPC)
6246 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6247 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6248 emit_insn (gen_mulh_call ());
6249 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6252 else if (TARGET_POWER)
6254 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6259 (define_insn "smulsi3_highpart_mq"
6260 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6262 (lshiftrt:DI (mult:DI (sign_extend:DI
6263 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6265 (match_operand:SI 2 "gpc_reg_operand" "r")))
6267 (clobber (match_scratch:SI 3 "=q"))]
6270 [(set_attr "type" "imul")])
6272 (define_insn "*smulsi3_highpart_no_mq"
6273 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6275 (lshiftrt:DI (mult:DI (sign_extend:DI
6276 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6278 (match_operand:SI 2 "gpc_reg_operand" "r")))
6280 "TARGET_POWERPC && ! TARGET_POWER"
6282 [(set_attr "type" "imul")])
6284 (define_expand "umulsi3_highpart"
6285 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6287 (lshiftrt:DI (mult:DI (zero_extend:DI
6288 (match_operand:SI 1 "gpc_reg_operand" ""))
6290 (match_operand:SI 2 "gpc_reg_operand" "")))
6297 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6302 (define_insn "umulsi3_highpart_mq"
6303 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6305 (lshiftrt:DI (mult:DI (zero_extend:DI
6306 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6308 (match_operand:SI 2 "gpc_reg_operand" "r")))
6310 (clobber (match_scratch:SI 3 "=q"))]
6311 "TARGET_POWERPC && TARGET_POWER"
6313 [(set_attr "type" "imul")])
6315 (define_insn "*umulsi3_highpart_no_mq"
6316 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6318 (lshiftrt:DI (mult:DI (zero_extend:DI
6319 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6321 (match_operand:SI 2 "gpc_reg_operand" "r")))
6323 "TARGET_POWERPC && ! TARGET_POWER"
6325 [(set_attr "type" "imul")])
6327 ;; If operands 0 and 2 are in the same register, we have a problem. But
6328 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6329 ;; why we have the strange constraints below.
6330 (define_insn "ashldi3_power"
6331 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6332 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6333 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6334 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6337 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6338 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6339 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6340 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6341 [(set_attr "length" "8")])
6343 (define_insn "lshrdi3_power"
6344 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6345 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6346 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6347 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6350 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6351 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6352 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6353 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6354 [(set_attr "length" "8")])
6356 ;; Shift by a variable amount is too complex to be worth open-coding. We
6357 ;; just handle shifts by constants.
6358 (define_insn "ashrdi3_power"
6359 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6360 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6361 (match_operand:SI 2 "const_int_operand" "M,i")))
6362 (clobber (match_scratch:SI 3 "=X,q"))]
6365 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6366 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6367 [(set_attr "length" "8")])
6369 (define_insn "ashrdi3_no_power"
6370 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6371 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6372 (match_operand:SI 2 "const_int_operand" "M,i")))]
6373 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6375 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6376 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6377 [(set_attr "type" "two,three")
6378 (set_attr "length" "8,12")])
6380 (define_insn "*ashrdisi3_noppc64"
6381 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6382 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6383 (const_int 32)) 4))]
6384 "TARGET_32BIT && !TARGET_POWERPC64"
6387 if (REGNO (operands[0]) == REGNO (operands[1]))
6390 return \"mr %0,%1\";
6392 [(set_attr "length" "4")])
6395 ;; PowerPC64 DImode operations.
6397 (define_insn_and_split "absdi2"
6398 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6399 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6400 (clobber (match_scratch:DI 2 "=&r,&r"))]
6403 "&& reload_completed"
6404 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6405 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6406 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6409 (define_insn_and_split "*nabsdi2"
6410 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6411 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6412 (clobber (match_scratch:DI 2 "=&r,&r"))]
6415 "&& reload_completed"
6416 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6417 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6418 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6421 (define_insn "muldi3"
6422 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6423 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6424 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6430 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6431 (const_string "imul3")
6432 (match_operand:SI 2 "short_cint_operand" "")
6433 (const_string "imul2")]
6434 (const_string "lmul")))])
6436 (define_insn "*muldi3_internal1"
6437 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6438 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6439 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6441 (clobber (match_scratch:DI 3 "=r,r"))]
6446 [(set_attr "type" "lmul_compare")
6447 (set_attr "length" "4,8")])
6450 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6451 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6452 (match_operand:DI 2 "gpc_reg_operand" ""))
6454 (clobber (match_scratch:DI 3 ""))]
6455 "TARGET_POWERPC64 && reload_completed"
6457 (mult:DI (match_dup 1) (match_dup 2)))
6459 (compare:CC (match_dup 3)
6463 (define_insn "*muldi3_internal2"
6464 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6465 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6466 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6468 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6469 (mult:DI (match_dup 1) (match_dup 2)))]
6474 [(set_attr "type" "lmul_compare")
6475 (set_attr "length" "4,8")])
6478 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6479 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6480 (match_operand:DI 2 "gpc_reg_operand" ""))
6482 (set (match_operand:DI 0 "gpc_reg_operand" "")
6483 (mult:DI (match_dup 1) (match_dup 2)))]
6484 "TARGET_POWERPC64 && reload_completed"
6486 (mult:DI (match_dup 1) (match_dup 2)))
6488 (compare:CC (match_dup 0)
6492 (define_insn "smuldi3_highpart"
6493 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6495 (lshiftrt:TI (mult:TI (sign_extend:TI
6496 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6498 (match_operand:DI 2 "gpc_reg_operand" "r")))
6502 [(set_attr "type" "lmul")])
6504 (define_insn "umuldi3_highpart"
6505 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6507 (lshiftrt:TI (mult:TI (zero_extend:TI
6508 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6510 (match_operand:DI 2 "gpc_reg_operand" "r")))
6514 [(set_attr "type" "lmul")])
6516 (define_insn "rotldi3"
6517 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6518 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6519 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6521 "rld%I2cl %0,%1,%H2,0")
6523 (define_insn "*rotldi3_internal2"
6524 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6525 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6526 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6528 (clobber (match_scratch:DI 3 "=r,r"))]
6531 rld%I2cl. %3,%1,%H2,0
6533 [(set_attr "type" "delayed_compare")
6534 (set_attr "length" "4,8")])
6537 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6538 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6539 (match_operand:DI 2 "reg_or_cint_operand" ""))
6541 (clobber (match_scratch:DI 3 ""))]
6542 "TARGET_POWERPC64 && reload_completed"
6544 (rotate:DI (match_dup 1) (match_dup 2)))
6546 (compare:CC (match_dup 3)
6550 (define_insn "*rotldi3_internal3"
6551 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6552 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6553 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6555 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6556 (rotate:DI (match_dup 1) (match_dup 2)))]
6559 rld%I2cl. %0,%1,%H2,0
6561 [(set_attr "type" "delayed_compare")
6562 (set_attr "length" "4,8")])
6565 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6566 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6567 (match_operand:DI 2 "reg_or_cint_operand" ""))
6569 (set (match_operand:DI 0 "gpc_reg_operand" "")
6570 (rotate:DI (match_dup 1) (match_dup 2)))]
6571 "TARGET_POWERPC64 && reload_completed"
6573 (rotate:DI (match_dup 1) (match_dup 2)))
6575 (compare:CC (match_dup 0)
6579 (define_insn "*rotldi3_internal4"
6580 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6581 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6582 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6583 (match_operand:DI 3 "mask64_operand" "n")))]
6585 "rld%I2c%B3 %0,%1,%H2,%S3")
6587 (define_insn "*rotldi3_internal5"
6588 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6590 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6591 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6592 (match_operand:DI 3 "mask64_operand" "n,n"))
6594 (clobber (match_scratch:DI 4 "=r,r"))]
6597 rld%I2c%B3. %4,%1,%H2,%S3
6599 [(set_attr "type" "delayed_compare")
6600 (set_attr "length" "4,8")])
6603 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6605 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6606 (match_operand:DI 2 "reg_or_cint_operand" ""))
6607 (match_operand:DI 3 "mask64_operand" ""))
6609 (clobber (match_scratch:DI 4 ""))]
6610 "TARGET_POWERPC64 && reload_completed"
6612 (and:DI (rotate:DI (match_dup 1)
6616 (compare:CC (match_dup 4)
6620 (define_insn "*rotldi3_internal6"
6621 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6623 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6624 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6625 (match_operand:DI 3 "mask64_operand" "n,n"))
6627 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6628 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6631 rld%I2c%B3. %0,%1,%H2,%S3
6633 [(set_attr "type" "delayed_compare")
6634 (set_attr "length" "4,8")])
6637 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6639 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6640 (match_operand:DI 2 "reg_or_cint_operand" ""))
6641 (match_operand:DI 3 "mask64_operand" ""))
6643 (set (match_operand:DI 0 "gpc_reg_operand" "")
6644 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6645 "TARGET_POWERPC64 && reload_completed"
6647 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6649 (compare:CC (match_dup 0)
6653 (define_insn "*rotldi3_internal7"
6654 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6657 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6658 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6660 "rld%I2cl %0,%1,%H2,56")
6662 (define_insn "*rotldi3_internal8"
6663 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6664 (compare:CC (zero_extend:DI
6666 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6667 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6669 (clobber (match_scratch:DI 3 "=r,r"))]
6672 rld%I2cl. %3,%1,%H2,56
6674 [(set_attr "type" "delayed_compare")
6675 (set_attr "length" "4,8")])
6678 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6679 (compare:CC (zero_extend:DI
6681 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6682 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6684 (clobber (match_scratch:DI 3 ""))]
6685 "TARGET_POWERPC64 && reload_completed"
6687 (zero_extend:DI (subreg:QI
6688 (rotate:DI (match_dup 1)
6691 (compare:CC (match_dup 3)
6695 (define_insn "*rotldi3_internal9"
6696 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6697 (compare:CC (zero_extend:DI
6699 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6700 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6702 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6703 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6706 rld%I2cl. %0,%1,%H2,56
6708 [(set_attr "type" "delayed_compare")
6709 (set_attr "length" "4,8")])
6712 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6713 (compare:CC (zero_extend:DI
6715 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6716 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6718 (set (match_operand:DI 0 "gpc_reg_operand" "")
6719 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6720 "TARGET_POWERPC64 && reload_completed"
6722 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6724 (compare:CC (match_dup 0)
6728 (define_insn "*rotldi3_internal10"
6729 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6732 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6733 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6735 "rld%I2cl %0,%1,%H2,48")
6737 (define_insn "*rotldi3_internal11"
6738 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6739 (compare:CC (zero_extend:DI
6741 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6742 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6744 (clobber (match_scratch:DI 3 "=r,r"))]
6747 rld%I2cl. %3,%1,%H2,48
6749 [(set_attr "type" "delayed_compare")
6750 (set_attr "length" "4,8")])
6753 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6754 (compare:CC (zero_extend:DI
6756 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6757 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6759 (clobber (match_scratch:DI 3 ""))]
6760 "TARGET_POWERPC64 && reload_completed"
6762 (zero_extend:DI (subreg:HI
6763 (rotate:DI (match_dup 1)
6766 (compare:CC (match_dup 3)
6770 (define_insn "*rotldi3_internal12"
6771 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6772 (compare:CC (zero_extend:DI
6774 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6775 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6777 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6778 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6781 rld%I2cl. %0,%1,%H2,48
6783 [(set_attr "type" "delayed_compare")
6784 (set_attr "length" "4,8")])
6787 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6788 (compare:CC (zero_extend:DI
6790 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6791 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6793 (set (match_operand:DI 0 "gpc_reg_operand" "")
6794 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6795 "TARGET_POWERPC64 && reload_completed"
6797 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6799 (compare:CC (match_dup 0)
6803 (define_insn "*rotldi3_internal13"
6804 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6807 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6808 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6810 "rld%I2cl %0,%1,%H2,32")
6812 (define_insn "*rotldi3_internal14"
6813 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6814 (compare:CC (zero_extend:DI
6816 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6817 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6819 (clobber (match_scratch:DI 3 "=r,r"))]
6822 rld%I2cl. %3,%1,%H2,32
6824 [(set_attr "type" "delayed_compare")
6825 (set_attr "length" "4,8")])
6828 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6829 (compare:CC (zero_extend:DI
6831 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6832 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6834 (clobber (match_scratch:DI 3 ""))]
6835 "TARGET_POWERPC64 && reload_completed"
6837 (zero_extend:DI (subreg:SI
6838 (rotate:DI (match_dup 1)
6841 (compare:CC (match_dup 3)
6845 (define_insn "*rotldi3_internal15"
6846 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6847 (compare:CC (zero_extend:DI
6849 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6850 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6852 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6853 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6856 rld%I2cl. %0,%1,%H2,32
6858 [(set_attr "type" "delayed_compare")
6859 (set_attr "length" "4,8")])
6862 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6863 (compare:CC (zero_extend:DI
6865 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6866 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6868 (set (match_operand:DI 0 "gpc_reg_operand" "")
6869 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6870 "TARGET_POWERPC64 && reload_completed"
6872 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6874 (compare:CC (match_dup 0)
6878 (define_expand "ashldi3"
6879 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6880 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6881 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6882 "TARGET_POWERPC64 || TARGET_POWER"
6885 if (TARGET_POWERPC64)
6887 else if (TARGET_POWER)
6889 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6896 (define_insn "*ashldi3_internal1"
6897 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6898 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6899 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6903 (define_insn "*ashldi3_internal2"
6904 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6905 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6906 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6908 (clobber (match_scratch:DI 3 "=r,r"))]
6913 [(set_attr "type" "delayed_compare")
6914 (set_attr "length" "4,8")])
6917 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6918 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6919 (match_operand:SI 2 "reg_or_cint_operand" ""))
6921 (clobber (match_scratch:DI 3 ""))]
6922 "TARGET_POWERPC64 && reload_completed"
6924 (ashift:DI (match_dup 1) (match_dup 2)))
6926 (compare:CC (match_dup 3)
6930 (define_insn "*ashldi3_internal3"
6931 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6932 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6933 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6935 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6936 (ashift:DI (match_dup 1) (match_dup 2)))]
6941 [(set_attr "type" "delayed_compare")
6942 (set_attr "length" "4,8")])
6945 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6946 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6947 (match_operand:SI 2 "reg_or_cint_operand" ""))
6949 (set (match_operand:DI 0 "gpc_reg_operand" "")
6950 (ashift:DI (match_dup 1) (match_dup 2)))]
6951 "TARGET_POWERPC64 && reload_completed"
6953 (ashift:DI (match_dup 1) (match_dup 2)))
6955 (compare:CC (match_dup 0)
6959 (define_insn "*ashldi3_internal4"
6960 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6961 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6962 (match_operand:SI 2 "const_int_operand" "i"))
6963 (match_operand:DI 3 "const_int_operand" "n")))]
6964 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6965 "rldic %0,%1,%H2,%W3")
6967 (define_insn "ashldi3_internal5"
6968 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6970 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6971 (match_operand:SI 2 "const_int_operand" "i,i"))
6972 (match_operand:DI 3 "const_int_operand" "n,n"))
6974 (clobber (match_scratch:DI 4 "=r,r"))]
6975 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6977 rldic. %4,%1,%H2,%W3
6979 [(set_attr "type" "compare")
6980 (set_attr "length" "4,8")])
6983 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6985 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6986 (match_operand:SI 2 "const_int_operand" ""))
6987 (match_operand:DI 3 "const_int_operand" ""))
6989 (clobber (match_scratch:DI 4 ""))]
6990 "TARGET_POWERPC64 && reload_completed
6991 && includes_rldic_lshift_p (operands[2], operands[3])"
6993 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6996 (compare:CC (match_dup 4)
7000 (define_insn "*ashldi3_internal6"
7001 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7003 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7004 (match_operand:SI 2 "const_int_operand" "i,i"))
7005 (match_operand:DI 3 "const_int_operand" "n,n"))
7007 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7008 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7009 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7011 rldic. %0,%1,%H2,%W3
7013 [(set_attr "type" "compare")
7014 (set_attr "length" "4,8")])
7017 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7019 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7020 (match_operand:SI 2 "const_int_operand" ""))
7021 (match_operand:DI 3 "const_int_operand" ""))
7023 (set (match_operand:DI 0 "gpc_reg_operand" "")
7024 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7025 "TARGET_POWERPC64 && reload_completed
7026 && includes_rldic_lshift_p (operands[2], operands[3])"
7028 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7031 (compare:CC (match_dup 0)
7035 (define_insn "*ashldi3_internal7"
7036 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7037 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7038 (match_operand:SI 2 "const_int_operand" "i"))
7039 (match_operand:DI 3 "mask64_operand" "n")))]
7040 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7041 "rldicr %0,%1,%H2,%S3")
7043 (define_insn "ashldi3_internal8"
7044 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7046 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7047 (match_operand:SI 2 "const_int_operand" "i,i"))
7048 (match_operand:DI 3 "mask64_operand" "n,n"))
7050 (clobber (match_scratch:DI 4 "=r,r"))]
7051 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7053 rldicr. %4,%1,%H2,%S3
7055 [(set_attr "type" "compare")
7056 (set_attr "length" "4,8")])
7059 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7061 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7062 (match_operand:SI 2 "const_int_operand" ""))
7063 (match_operand:DI 3 "mask64_operand" ""))
7065 (clobber (match_scratch:DI 4 ""))]
7066 "TARGET_POWERPC64 && reload_completed
7067 && includes_rldicr_lshift_p (operands[2], operands[3])"
7069 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7072 (compare:CC (match_dup 4)
7076 (define_insn "*ashldi3_internal9"
7077 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7079 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7080 (match_operand:SI 2 "const_int_operand" "i,i"))
7081 (match_operand:DI 3 "mask64_operand" "n,n"))
7083 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7084 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7085 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7087 rldicr. %0,%1,%H2,%S3
7089 [(set_attr "type" "compare")
7090 (set_attr "length" "4,8")])
7093 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7095 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7096 (match_operand:SI 2 "const_int_operand" ""))
7097 (match_operand:DI 3 "mask64_operand" ""))
7099 (set (match_operand:DI 0 "gpc_reg_operand" "")
7100 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7101 "TARGET_POWERPC64 && reload_completed
7102 && includes_rldicr_lshift_p (operands[2], operands[3])"
7104 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7107 (compare:CC (match_dup 0)
7111 (define_expand "lshrdi3"
7112 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7113 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7114 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7115 "TARGET_POWERPC64 || TARGET_POWER"
7118 if (TARGET_POWERPC64)
7120 else if (TARGET_POWER)
7122 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7129 (define_insn "*lshrdi3_internal1"
7130 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7131 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7132 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7136 (define_insn "*lshrdi3_internal2"
7137 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7138 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7139 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7141 (clobber (match_scratch:DI 3 "=r,r"))]
7146 [(set_attr "type" "delayed_compare")
7147 (set_attr "length" "4,8")])
7150 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7151 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7152 (match_operand:SI 2 "reg_or_cint_operand" ""))
7154 (clobber (match_scratch:DI 3 ""))]
7155 "TARGET_POWERPC64 && reload_completed"
7157 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7159 (compare:CC (match_dup 3)
7163 (define_insn "*lshrdi3_internal3"
7164 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7165 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7166 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7168 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7169 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7174 [(set_attr "type" "delayed_compare")
7175 (set_attr "length" "4,8")])
7178 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7179 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7180 (match_operand:SI 2 "reg_or_cint_operand" ""))
7182 (set (match_operand:DI 0 "gpc_reg_operand" "")
7183 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7184 "TARGET_POWERPC64 && reload_completed"
7186 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7188 (compare:CC (match_dup 0)
7192 (define_expand "ashrdi3"
7193 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7194 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7195 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7199 if (TARGET_POWERPC64)
7201 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7203 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7206 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7207 && WORDS_BIG_ENDIAN)
7209 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7216 (define_insn "*ashrdi3_internal1"
7217 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7218 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7219 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7221 "srad%I2 %0,%1,%H2")
7223 (define_insn "*ashrdi3_internal2"
7224 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7225 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7226 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7228 (clobber (match_scratch:DI 3 "=r,r"))]
7233 [(set_attr "type" "delayed_compare")
7234 (set_attr "length" "4,8")])
7237 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7238 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7239 (match_operand:SI 2 "reg_or_cint_operand" ""))
7241 (clobber (match_scratch:DI 3 ""))]
7242 "TARGET_POWERPC64 && reload_completed"
7244 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7246 (compare:CC (match_dup 3)
7250 (define_insn "*ashrdi3_internal3"
7251 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7252 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7253 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7255 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7256 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7261 [(set_attr "type" "delayed_compare")
7262 (set_attr "length" "4,8")])
7265 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7266 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7267 (match_operand:SI 2 "reg_or_cint_operand" ""))
7269 (set (match_operand:DI 0 "gpc_reg_operand" "")
7270 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7271 "TARGET_POWERPC64 && reload_completed"
7273 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7275 (compare:CC (match_dup 0)
7279 (define_insn "anddi3"
7280 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7281 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7282 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7283 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7287 rldic%B2 %0,%1,0,%S2
7288 rlwinm %0,%1,0,%m2,%M2
7292 [(set_attr "type" "*,*,*,compare,compare,*")
7293 (set_attr "length" "4,4,4,4,4,8")])
7296 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7297 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7298 (match_operand:DI 2 "mask64_2_operand" "")))
7299 (clobber (match_scratch:CC 3 ""))]
7301 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7302 && !mask_operand (operands[2], DImode)
7303 && !mask64_operand (operands[2], DImode)"
7305 (and:DI (rotate:DI (match_dup 1)
7309 (and:DI (rotate:DI (match_dup 0)
7313 build_mask64_2_operands (operands[2], &operands[4]);
7316 (define_insn "*anddi3_internal2"
7317 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7318 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7319 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7321 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7322 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7326 rldic%B2. %3,%1,0,%S2
7327 rlwinm. %3,%1,0,%m2,%M2
7337 [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7338 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7341 [(set (match_operand:CC 0 "cc_reg_operand" "")
7342 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7343 (match_operand:DI 2 "mask64_2_operand" ""))
7345 (clobber (match_scratch:DI 3 ""))
7346 (clobber (match_scratch:CC 4 ""))]
7347 "TARGET_64BIT && reload_completed
7348 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7349 && !mask_operand (operands[2], DImode)
7350 && !mask64_operand (operands[2], DImode)"
7352 (and:DI (rotate:DI (match_dup 1)
7355 (parallel [(set (match_dup 0)
7356 (compare:CC (and:DI (rotate:DI (match_dup 3)
7360 (clobber (match_dup 3))])]
7363 build_mask64_2_operands (operands[2], &operands[5]);
7366 (define_insn "*anddi3_internal3"
7367 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7368 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7369 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7371 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7372 (and:DI (match_dup 1) (match_dup 2)))
7373 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7377 rldic%B2. %0,%1,0,%S2
7378 rlwinm. %0,%1,0,%m2,%M2
7388 [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7389 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7392 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7393 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7394 (match_operand:DI 2 "and64_2_operand" ""))
7396 (set (match_operand:DI 0 "gpc_reg_operand" "")
7397 (and:DI (match_dup 1) (match_dup 2)))
7398 (clobber (match_scratch:CC 4 ""))]
7399 "TARGET_64BIT && reload_completed"
7400 [(parallel [(set (match_dup 0)
7401 (and:DI (match_dup 1) (match_dup 2)))
7402 (clobber (match_dup 4))])
7404 (compare:CC (match_dup 0)
7409 [(set (match_operand:CC 3 "cc_reg_operand" "")
7410 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7411 (match_operand:DI 2 "mask64_2_operand" ""))
7413 (set (match_operand:DI 0 "gpc_reg_operand" "")
7414 (and:DI (match_dup 1) (match_dup 2)))
7415 (clobber (match_scratch:CC 4 ""))]
7416 "TARGET_64BIT && reload_completed
7417 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7418 && !mask_operand (operands[2], DImode)
7419 && !mask64_operand (operands[2], DImode)"
7421 (and:DI (rotate:DI (match_dup 1)
7424 (parallel [(set (match_dup 3)
7425 (compare:CC (and:DI (rotate:DI (match_dup 0)
7430 (and:DI (rotate:DI (match_dup 0)
7435 build_mask64_2_operands (operands[2], &operands[5]);
7438 (define_expand "iordi3"
7439 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7440 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7441 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7445 if (non_logical_cint_operand (operands[2], DImode))
7447 HOST_WIDE_INT value;
7448 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7449 ? operands[0] : gen_reg_rtx (DImode));
7451 if (GET_CODE (operands[2]) == CONST_INT)
7453 value = INTVAL (operands[2]);
7454 emit_insn (gen_iordi3 (tmp, operands[1],
7455 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7459 value = CONST_DOUBLE_LOW (operands[2]);
7460 emit_insn (gen_iordi3 (tmp, operands[1],
7461 immed_double_const (value
7462 & (~ (HOST_WIDE_INT) 0xffff),
7466 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7471 (define_expand "xordi3"
7472 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7473 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7474 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7478 if (non_logical_cint_operand (operands[2], DImode))
7480 HOST_WIDE_INT value;
7481 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7482 ? operands[0] : gen_reg_rtx (DImode));
7484 if (GET_CODE (operands[2]) == CONST_INT)
7486 value = INTVAL (operands[2]);
7487 emit_insn (gen_xordi3 (tmp, operands[1],
7488 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7492 value = CONST_DOUBLE_LOW (operands[2]);
7493 emit_insn (gen_xordi3 (tmp, operands[1],
7494 immed_double_const (value
7495 & (~ (HOST_WIDE_INT) 0xffff),
7499 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7504 (define_insn "*booldi3_internal1"
7505 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7506 (match_operator:DI 3 "boolean_or_operator"
7507 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7508 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7515 (define_insn "*booldi3_internal2"
7516 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7517 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7518 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7519 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7521 (clobber (match_scratch:DI 3 "=r,r"))]
7526 [(set_attr "type" "compare")
7527 (set_attr "length" "4,8")])
7530 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7531 (compare:CC (match_operator:DI 4 "boolean_operator"
7532 [(match_operand:DI 1 "gpc_reg_operand" "")
7533 (match_operand:DI 2 "gpc_reg_operand" "")])
7535 (clobber (match_scratch:DI 3 ""))]
7536 "TARGET_POWERPC64 && reload_completed"
7537 [(set (match_dup 3) (match_dup 4))
7539 (compare:CC (match_dup 3)
7543 (define_insn "*booldi3_internal3"
7544 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7545 (compare:CC (match_operator:DI 4 "boolean_operator"
7546 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7547 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7549 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7555 [(set_attr "type" "compare")
7556 (set_attr "length" "4,8")])
7559 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7560 (compare:CC (match_operator:DI 4 "boolean_operator"
7561 [(match_operand:DI 1 "gpc_reg_operand" "")
7562 (match_operand:DI 2 "gpc_reg_operand" "")])
7564 (set (match_operand:DI 0 "gpc_reg_operand" "")
7566 "TARGET_POWERPC64 && reload_completed"
7567 [(set (match_dup 0) (match_dup 4))
7569 (compare:CC (match_dup 0)
7573 ;; Split a logical operation that we can't do in one insn into two insns,
7574 ;; each of which does one 16-bit part. This is used by combine.
7577 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7578 (match_operator:DI 3 "boolean_or_operator"
7579 [(match_operand:DI 1 "gpc_reg_operand" "")
7580 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7582 [(set (match_dup 0) (match_dup 4))
7583 (set (match_dup 0) (match_dup 5))]
7588 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7590 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7591 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7593 i4 = GEN_INT (value & 0xffff);
7597 i3 = GEN_INT (INTVAL (operands[2])
7598 & (~ (HOST_WIDE_INT) 0xffff));
7599 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7601 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7603 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7607 (define_insn "*boolcdi3_internal1"
7608 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7609 (match_operator:DI 3 "boolean_operator"
7610 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7611 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7615 (define_insn "*boolcdi3_internal2"
7616 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7617 (compare:CC (match_operator:DI 4 "boolean_operator"
7618 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7619 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7621 (clobber (match_scratch:DI 3 "=r,r"))]
7626 [(set_attr "type" "compare")
7627 (set_attr "length" "4,8")])
7630 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7631 (compare:CC (match_operator:DI 4 "boolean_operator"
7632 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7633 (match_operand:DI 2 "gpc_reg_operand" "")])
7635 (clobber (match_scratch:DI 3 ""))]
7636 "TARGET_POWERPC64 && reload_completed"
7637 [(set (match_dup 3) (match_dup 4))
7639 (compare:CC (match_dup 3)
7643 (define_insn "*boolcdi3_internal3"
7644 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7645 (compare:CC (match_operator:DI 4 "boolean_operator"
7646 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7647 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7649 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7655 [(set_attr "type" "compare")
7656 (set_attr "length" "4,8")])
7659 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7660 (compare:CC (match_operator:DI 4 "boolean_operator"
7661 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7662 (match_operand:DI 2 "gpc_reg_operand" "")])
7664 (set (match_operand:DI 0 "gpc_reg_operand" "")
7666 "TARGET_POWERPC64 && reload_completed"
7667 [(set (match_dup 0) (match_dup 4))
7669 (compare:CC (match_dup 0)
7673 (define_insn "*boolccdi3_internal1"
7674 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7675 (match_operator:DI 3 "boolean_operator"
7676 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7677 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7681 (define_insn "*boolccdi3_internal2"
7682 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7683 (compare:CC (match_operator:DI 4 "boolean_operator"
7684 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7685 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7687 (clobber (match_scratch:DI 3 "=r,r"))]
7692 [(set_attr "type" "compare")
7693 (set_attr "length" "4,8")])
7696 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7697 (compare:CC (match_operator:DI 4 "boolean_operator"
7698 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7699 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7701 (clobber (match_scratch:DI 3 ""))]
7702 "TARGET_POWERPC64 && reload_completed"
7703 [(set (match_dup 3) (match_dup 4))
7705 (compare:CC (match_dup 3)
7709 (define_insn "*boolccdi3_internal3"
7710 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7711 (compare:CC (match_operator:DI 4 "boolean_operator"
7712 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7713 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7715 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7721 [(set_attr "type" "compare")
7722 (set_attr "length" "4,8")])
7725 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7726 (compare:CC (match_operator:DI 4 "boolean_operator"
7727 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7728 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7730 (set (match_operand:DI 0 "gpc_reg_operand" "")
7732 "TARGET_POWERPC64 && reload_completed"
7733 [(set (match_dup 0) (match_dup 4))
7735 (compare:CC (match_dup 0)
7739 ;; Now define ways of moving data around.
7741 ;; Set up a register with a value from the GOT table
7743 (define_expand "movsi_got"
7744 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7745 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7746 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7747 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7750 if (GET_CODE (operands[1]) == CONST)
7752 rtx offset = const0_rtx;
7753 HOST_WIDE_INT value;
7755 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7756 value = INTVAL (offset);
7759 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7760 emit_insn (gen_movsi_got (tmp, operands[1]));
7761 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7766 operands[2] = rs6000_got_register (operands[1]);
7769 (define_insn "*movsi_got_internal"
7770 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7771 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7772 (match_operand:SI 2 "gpc_reg_operand" "b")]
7774 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7775 "{l|lwz} %0,%a1@got(%2)"
7776 [(set_attr "type" "load")])
7778 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7779 ;; didn't get allocated to a hard register.
7781 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7782 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7783 (match_operand:SI 2 "memory_operand" "")]
7785 "DEFAULT_ABI == ABI_V4
7787 && (reload_in_progress || reload_completed)"
7788 [(set (match_dup 0) (match_dup 2))
7789 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7793 ;; For SI, we special-case integers that can't be loaded in one insn. We
7794 ;; do the load 16-bits at a time. We could do this by loading from memory,
7795 ;; and this is even supposed to be faster, but it is simpler not to get
7796 ;; integers in the TOC.
7797 (define_insn "movsi_low"
7798 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7799 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7800 (match_operand 2 "" ""))))]
7801 "TARGET_MACHO && ! TARGET_64BIT"
7802 "{l|lwz} %0,lo16(%2)(%1)"
7803 [(set_attr "type" "load")
7804 (set_attr "length" "4")])
7806 (define_insn "*movsi_internal1"
7807 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7808 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7809 "gpc_reg_operand (operands[0], SImode)
7810 || gpc_reg_operand (operands[1], SImode)"
7814 {l%U1%X1|lwz%U1%X1} %0,%1
7815 {st%U0%X0|stw%U0%X0} %1,%0
7825 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7826 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7828 ;; Split a load of a large constant into the appropriate two-insn
7832 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7833 (match_operand:SI 1 "const_int_operand" ""))]
7834 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7835 && (INTVAL (operands[1]) & 0xffff) != 0"
7839 (ior:SI (match_dup 0)
7842 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7844 if (tem == operands[0])
7850 (define_insn "*mov<mode>_internal2"
7851 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7852 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7854 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7857 {cmpi|cmp<wd>i} %2,%0,0
7860 [(set_attr "type" "cmp,compare,cmp")
7861 (set_attr "length" "4,4,8")])
7864 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7865 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7867 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7869 [(set (match_dup 0) (match_dup 1))
7871 (compare:CC (match_dup 0)
7875 (define_insn "*movhi_internal"
7876 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7877 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7878 "gpc_reg_operand (operands[0], HImode)
7879 || gpc_reg_operand (operands[1], HImode)"
7889 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7891 (define_expand "mov<mode>"
7892 [(set (match_operand:INT 0 "general_operand" "")
7893 (match_operand:INT 1 "any_operand" ""))]
7895 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7897 (define_insn "*movqi_internal"
7898 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7899 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7900 "gpc_reg_operand (operands[0], QImode)
7901 || gpc_reg_operand (operands[1], QImode)"
7911 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7913 ;; Here is how to move condition codes around. When we store CC data in
7914 ;; an integer register or memory, we store just the high-order 4 bits.
7915 ;; This lets us not shift in the most common case of CR0.
7916 (define_expand "movcc"
7917 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7918 (match_operand:CC 1 "nonimmediate_operand" ""))]
7922 (define_insn "*movcc_internal1"
7923 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
7924 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
7925 "register_operand (operands[0], CCmode)
7926 || register_operand (operands[1], CCmode)"
7930 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7933 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7939 {l%U1%X1|lwz%U1%X1} %0,%1
7940 {st%U0%U1|stw%U0%U1} %1,%0"
7942 (cond [(eq_attr "alternative" "0,3")
7943 (const_string "cr_logical")
7944 (eq_attr "alternative" "1,2")
7945 (const_string "mtcr")
7946 (eq_attr "alternative" "6,7,9")
7947 (const_string "integer")
7948 (eq_attr "alternative" "8")
7949 (const_string "mfjmpr")
7950 (eq_attr "alternative" "10")
7951 (const_string "mtjmpr")
7952 (eq_attr "alternative" "11")
7953 (const_string "load")
7954 (eq_attr "alternative" "12")
7955 (const_string "store")
7956 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7957 (const_string "mfcrf")
7959 (const_string "mfcr")))
7960 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
7962 ;; For floating-point, we normally deal with the floating-point registers
7963 ;; unless -msoft-float is used. The sole exception is that parameter passing
7964 ;; can produce floating-point values in fixed-point registers. Unless the
7965 ;; value is a simple constant or already in memory, we deal with this by
7966 ;; allocating memory and copying the value explicitly via that memory location.
7967 (define_expand "movsf"
7968 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7969 (match_operand:SF 1 "any_operand" ""))]
7971 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7974 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7975 (match_operand:SF 1 "const_double_operand" ""))]
7977 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7978 || (GET_CODE (operands[0]) == SUBREG
7979 && GET_CODE (SUBREG_REG (operands[0])) == REG
7980 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7981 [(set (match_dup 2) (match_dup 3))]
7987 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7988 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7990 if (! TARGET_POWERPC64)
7991 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7993 operands[2] = gen_lowpart (SImode, operands[0]);
7995 operands[3] = gen_int_mode (l, SImode);
7998 (define_insn "*movsf_hardfloat"
7999 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8000 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8001 "(gpc_reg_operand (operands[0], SFmode)
8002 || gpc_reg_operand (operands[1], SFmode))
8003 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
8006 {l%U1%X1|lwz%U1%X1} %0,%1
8007 {st%U0%X0|stw%U0%X0} %1,%0
8017 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8018 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8020 (define_insn "*movsf_softfloat"
8021 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8022 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8023 "(gpc_reg_operand (operands[0], SFmode)
8024 || gpc_reg_operand (operands[1], SFmode))
8025 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8031 {l%U1%X1|lwz%U1%X1} %0,%1
8032 {st%U0%X0|stw%U0%X0} %1,%0
8039 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8040 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8043 (define_expand "movdf"
8044 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8045 (match_operand:DF 1 "any_operand" ""))]
8047 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8050 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8051 (match_operand:DF 1 "const_int_operand" ""))]
8052 "! TARGET_POWERPC64 && reload_completed
8053 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8054 || (GET_CODE (operands[0]) == SUBREG
8055 && GET_CODE (SUBREG_REG (operands[0])) == REG
8056 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8057 [(set (match_dup 2) (match_dup 4))
8058 (set (match_dup 3) (match_dup 1))]
8061 int endian = (WORDS_BIG_ENDIAN == 0);
8062 HOST_WIDE_INT value = INTVAL (operands[1]);
8064 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8065 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8066 #if HOST_BITS_PER_WIDE_INT == 32
8067 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8069 operands[4] = GEN_INT (value >> 32);
8070 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8075 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8076 (match_operand:DF 1 "const_double_operand" ""))]
8077 "! TARGET_POWERPC64 && reload_completed
8078 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8079 || (GET_CODE (operands[0]) == SUBREG
8080 && GET_CODE (SUBREG_REG (operands[0])) == REG
8081 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8082 [(set (match_dup 2) (match_dup 4))
8083 (set (match_dup 3) (match_dup 5))]
8086 int endian = (WORDS_BIG_ENDIAN == 0);
8090 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8091 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8093 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8094 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8095 operands[4] = gen_int_mode (l[endian], SImode);
8096 operands[5] = gen_int_mode (l[1 - endian], SImode);
8100 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8101 (match_operand:DF 1 "const_double_operand" ""))]
8102 "TARGET_POWERPC64 && reload_completed
8103 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8104 || (GET_CODE (operands[0]) == SUBREG
8105 && GET_CODE (SUBREG_REG (operands[0])) == REG
8106 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8107 [(set (match_dup 2) (match_dup 3))]
8110 int endian = (WORDS_BIG_ENDIAN == 0);
8113 #if HOST_BITS_PER_WIDE_INT >= 64
8117 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8118 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8120 operands[2] = gen_lowpart (DImode, operands[0]);
8121 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8122 #if HOST_BITS_PER_WIDE_INT >= 64
8123 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8124 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8126 operands[3] = gen_int_mode (val, DImode);
8128 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8132 ;; Don't have reload use general registers to load a constant. First,
8133 ;; it might not work if the output operand is the equivalent of
8134 ;; a non-offsettable memref, but also it is less efficient than loading
8135 ;; the constant into an FP register, since it will probably be used there.
8136 ;; The "??" is a kludge until we can figure out a more reasonable way
8137 ;; of handling these non-offsettable values.
8138 (define_insn "*movdf_hardfloat32"
8139 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8140 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8141 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8142 && (gpc_reg_operand (operands[0], DFmode)
8143 || gpc_reg_operand (operands[1], DFmode))"
8146 switch (which_alternative)
8151 /* We normally copy the low-numbered register first. However, if
8152 the first register operand 0 is the same as the second register
8153 of operand 1, we must copy in the opposite order. */
8154 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8155 return \"mr %L0,%L1\;mr %0,%1\";
8157 return \"mr %0,%1\;mr %L0,%L1\";
8159 if (rs6000_offsettable_memref_p (operands[1])
8160 || (GET_CODE (operands[1]) == MEM
8161 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8162 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8163 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
8165 /* If the low-address word is used in the address, we must load
8166 it last. Otherwise, load it first. Note that we cannot have
8167 auto-increment in that case since the address register is
8168 known to be dead. */
8169 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8171 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8173 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8179 addreg = find_addr_reg (XEXP (operands[1], 0));
8180 if (refers_to_regno_p (REGNO (operands[0]),
8181 REGNO (operands[0]) + 1,
8184 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8185 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8186 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8187 return \"{lx|lwzx} %0,%1\";
8191 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8192 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8193 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8194 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8199 if (rs6000_offsettable_memref_p (operands[0])
8200 || (GET_CODE (operands[0]) == MEM
8201 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8202 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8203 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
8204 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8209 addreg = find_addr_reg (XEXP (operands[0], 0));
8210 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8211 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8212 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8213 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8217 return \"fmr %0,%1\";
8219 return \"lfd%U1%X1 %0,%1\";
8221 return \"stfd%U0%X0 %1,%0\";
8228 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8229 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8231 (define_insn "*movdf_softfloat32"
8232 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8233 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8234 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8235 && (gpc_reg_operand (operands[0], DFmode)
8236 || gpc_reg_operand (operands[1], DFmode))"
8239 switch (which_alternative)
8244 /* We normally copy the low-numbered register first. However, if
8245 the first register operand 0 is the same as the second register of
8246 operand 1, we must copy in the opposite order. */
8247 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8248 return \"mr %L0,%L1\;mr %0,%1\";
8250 return \"mr %0,%1\;mr %L0,%L1\";
8252 /* If the low-address word is used in the address, we must load
8253 it last. Otherwise, load it first. Note that we cannot have
8254 auto-increment in that case since the address register is
8255 known to be dead. */
8256 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8258 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8260 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8262 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8269 [(set_attr "type" "two,load,store,*,*,*")
8270 (set_attr "length" "8,8,8,8,12,16")])
8272 ; ld/std require word-aligned displacements -> 'Y' constraint.
8273 ; List Y->r and r->Y before r->r for reload.
8274 (define_insn "*movdf_hardfloat64"
8275 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8276 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8277 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8278 && (gpc_reg_operand (operands[0], DFmode)
8279 || gpc_reg_operand (operands[1], DFmode))"
8293 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8294 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8296 (define_insn "*movdf_softfloat64"
8297 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8298 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8299 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8300 && (gpc_reg_operand (operands[0], DFmode)
8301 || gpc_reg_operand (operands[1], DFmode))"
8312 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8313 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8315 (define_expand "movtf"
8316 [(set (match_operand:TF 0 "general_operand" "")
8317 (match_operand:TF 1 "any_operand" ""))]
8319 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8320 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8322 ; It's important to list the o->f and f->o moves before f->f because
8323 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8324 ; which doesn't make progress. Likewise r->Y must be before r->r.
8325 (define_insn_and_split "*movtf_internal"
8326 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8327 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8329 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8330 && (gpc_reg_operand (operands[0], TFmode)
8331 || gpc_reg_operand (operands[1], TFmode))"
8333 "&& reload_completed"
8335 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8336 [(set_attr "length" "8,8,8,20,20,16")])
8338 (define_expand "extenddftf2"
8339 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8340 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8341 (use (match_dup 2))])]
8343 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8345 operands[2] = CONST0_RTX (DFmode);
8346 /* Generate GOT reference early for SVR4 PIC. */
8347 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8348 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8351 (define_insn_and_split "*extenddftf2_internal"
8352 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8353 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8354 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8356 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8358 "&& reload_completed"
8361 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8362 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8363 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8365 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8370 (define_expand "extendsftf2"
8371 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8372 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8374 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8376 rtx tmp = gen_reg_rtx (DFmode);
8377 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8378 emit_insn (gen_extenddftf2 (operands[0], tmp));
8382 (define_expand "trunctfdf2"
8383 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8384 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8386 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8389 (define_insn_and_split "trunctfdf2_internal1"
8390 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8391 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8392 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8393 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8397 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8400 emit_note (NOTE_INSN_DELETED);
8403 [(set_attr "type" "fp")])
8405 (define_insn "trunctfdf2_internal2"
8406 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8407 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8408 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8409 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8411 [(set_attr "type" "fp")])
8413 (define_insn_and_split "trunctfsf2"
8414 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8415 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8416 (clobber (match_scratch:DF 2 "=f"))]
8418 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8420 "&& reload_completed"
8422 (float_truncate:DF (match_dup 1)))
8424 (float_truncate:SF (match_dup 2)))]
8427 (define_expand "floatsitf2"
8428 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8429 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8431 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8433 rtx tmp = gen_reg_rtx (DFmode);
8434 expand_float (tmp, operands[1], false);
8435 emit_insn (gen_extenddftf2 (operands[0], tmp));
8439 ; fadd, but rounding towards zero.
8440 ; This is probably not the optimal code sequence.
8441 (define_insn "fix_trunc_helper"
8442 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8443 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8444 UNSPEC_FIX_TRUNC_TF))
8445 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8446 "TARGET_HARD_FLOAT && TARGET_FPRS"
8447 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8448 [(set_attr "type" "fp")
8449 (set_attr "length" "20")])
8451 (define_expand "fix_trunctfsi2"
8452 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8453 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8454 (clobber (match_dup 2))
8455 (clobber (match_dup 3))
8456 (clobber (match_dup 4))
8457 (clobber (match_dup 5))])]
8459 && (TARGET_POWER2 || TARGET_POWERPC)
8460 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8462 operands[2] = gen_reg_rtx (DFmode);
8463 operands[3] = gen_reg_rtx (DFmode);
8464 operands[4] = gen_reg_rtx (DImode);
8465 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8468 (define_insn_and_split "*fix_trunctfsi2_internal"
8469 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8470 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8471 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8472 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8473 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8474 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8476 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8478 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
8482 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8484 gcc_assert (MEM_P (operands[5]));
8485 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8487 emit_insn (gen_fctiwz (operands[4], operands[2]));
8488 emit_move_insn (operands[5], operands[4]);
8489 emit_move_insn (operands[0], lowword);
8493 (define_insn "negtf2"
8494 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8495 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8497 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8500 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8501 return \"fneg %L0,%L1\;fneg %0,%1\";
8503 return \"fneg %0,%1\;fneg %L0,%L1\";
8505 [(set_attr "type" "fp")
8506 (set_attr "length" "8")])
8508 (define_expand "abstf2"
8509 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8510 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8512 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8515 rtx label = gen_label_rtx ();
8516 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8521 (define_expand "abstf2_internal"
8522 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8523 (match_operand:TF 1 "gpc_reg_operand" "f"))
8524 (set (match_dup 3) (match_dup 5))
8525 (set (match_dup 5) (abs:DF (match_dup 5)))
8526 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8527 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8528 (label_ref (match_operand 2 "" ""))
8530 (set (match_dup 6) (neg:DF (match_dup 6)))]
8532 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8535 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8536 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8537 operands[3] = gen_reg_rtx (DFmode);
8538 operands[4] = gen_reg_rtx (CCFPmode);
8539 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8540 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8543 ;; Next come the multi-word integer load and store and the load and store
8546 ; List r->r after r->"o<>", otherwise reload will try to reload a
8547 ; non-offsettable address by using r->r which won't make progress.
8548 (define_insn "*movdi_internal32"
8549 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8550 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8552 && (gpc_reg_operand (operands[0], DImode)
8553 || gpc_reg_operand (operands[1], DImode))"
8562 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8565 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8566 (match_operand:DI 1 "const_int_operand" ""))]
8567 "! TARGET_POWERPC64 && reload_completed"
8568 [(set (match_dup 2) (match_dup 4))
8569 (set (match_dup 3) (match_dup 1))]
8572 HOST_WIDE_INT value = INTVAL (operands[1]);
8573 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8575 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8577 #if HOST_BITS_PER_WIDE_INT == 32
8578 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8580 operands[4] = GEN_INT (value >> 32);
8581 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8586 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8587 (match_operand:DI 1 "input_operand" ""))]
8588 "reload_completed && !TARGET_POWERPC64
8589 && gpr_or_gpr_p (operands[0], operands[1])"
8591 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8593 (define_insn "*movdi_internal64"
8594 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8595 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8597 && (gpc_reg_operand (operands[0], DImode)
8598 || gpc_reg_operand (operands[1], DImode))"
8613 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8614 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8616 ;; immediate value valid for a single instruction hiding in a const_double
8618 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8619 (match_operand:DI 1 "const_double_operand" "F"))]
8620 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8621 && GET_CODE (operands[1]) == CONST_DOUBLE
8622 && num_insns_constant (operands[1], DImode) == 1"
8625 return ((unsigned HOST_WIDE_INT)
8626 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8627 ? \"li %0,%1\" : \"lis %0,%v1\";
8630 ;; Generate all one-bits and clear left or right.
8631 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8633 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8634 (match_operand:DI 1 "mask64_operand" ""))]
8635 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8636 [(set (match_dup 0) (const_int -1))
8638 (and:DI (rotate:DI (match_dup 0)
8643 ;; Split a load of a large constant into the appropriate five-instruction
8644 ;; sequence. Handle anything in a constant number of insns.
8645 ;; When non-easy constants can go in the TOC, this should use
8646 ;; easy_fp_constant predicate.
8648 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8649 (match_operand:DI 1 "const_int_operand" ""))]
8650 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8651 [(set (match_dup 0) (match_dup 2))
8652 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8654 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8656 if (tem == operands[0])
8663 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8664 (match_operand:DI 1 "const_double_operand" ""))]
8665 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8666 [(set (match_dup 0) (match_dup 2))
8667 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8669 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8671 if (tem == operands[0])
8677 ;; TImode is similar, except that we usually want to compute the address into
8678 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8679 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8681 ;; We say that MQ is clobbered in the last alternative because the first
8682 ;; alternative would never get used otherwise since it would need a reload
8683 ;; while the 2nd alternative would not. We put memory cases first so they
8684 ;; are preferred. Otherwise, we'd try to reload the output instead of
8685 ;; giving the SCRATCH mq.
8687 (define_insn "*movti_power"
8688 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8689 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8690 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8691 "TARGET_POWER && ! TARGET_POWERPC64
8692 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8695 switch (which_alternative)
8702 return \"{stsi|stswi} %1,%P0,16\";
8707 /* If the address is not used in the output, we can use lsi. Otherwise,
8708 fall through to generating four loads. */
8710 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8711 return \"{lsi|lswi} %0,%P1,16\";
8712 /* ... fall through ... */
8718 [(set_attr "type" "store,store,*,load,load,*")])
8720 (define_insn "*movti_string"
8721 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8722 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8723 "! TARGET_POWER && ! TARGET_POWERPC64
8724 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8727 switch (which_alternative)
8733 return \"{stsi|stswi} %1,%P0,16\";
8738 /* If the address is not used in the output, we can use lsi. Otherwise,
8739 fall through to generating four loads. */
8741 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8742 return \"{lsi|lswi} %0,%P1,16\";
8743 /* ... fall through ... */
8749 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
8751 (define_insn "*movti_ppc64"
8752 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8753 (match_operand:TI 1 "input_operand" "r,r,m"))]
8754 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8755 || gpc_reg_operand (operands[1], TImode))"
8757 [(set_attr "type" "*,load,store")])
8760 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8761 (match_operand:TI 1 "const_double_operand" ""))]
8763 [(set (match_dup 2) (match_dup 4))
8764 (set (match_dup 3) (match_dup 5))]
8767 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8769 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8771 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8773 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8774 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8776 else if (GET_CODE (operands[1]) == CONST_INT)
8778 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8779 operands[5] = operands[1];
8786 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8787 (match_operand:TI 1 "input_operand" ""))]
8789 && gpr_or_gpr_p (operands[0], operands[1])"
8791 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8793 (define_expand "load_multiple"
8794 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8795 (match_operand:SI 1 "" ""))
8796 (use (match_operand:SI 2 "" ""))])]
8797 "TARGET_STRING && !TARGET_POWERPC64"
8805 /* Support only loading a constant number of fixed-point registers from
8806 memory and only bother with this if more than two; the machine
8807 doesn't support more than eight. */
8808 if (GET_CODE (operands[2]) != CONST_INT
8809 || INTVAL (operands[2]) <= 2
8810 || INTVAL (operands[2]) > 8
8811 || GET_CODE (operands[1]) != MEM
8812 || GET_CODE (operands[0]) != REG
8813 || REGNO (operands[0]) >= 32)
8816 count = INTVAL (operands[2]);
8817 regno = REGNO (operands[0]);
8819 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8820 op1 = replace_equiv_address (operands[1],
8821 force_reg (SImode, XEXP (operands[1], 0)));
8823 for (i = 0; i < count; i++)
8824 XVECEXP (operands[3], 0, i)
8825 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8826 adjust_address_nv (op1, SImode, i * 4));
8829 (define_insn "*ldmsi8"
8830 [(match_parallel 0 "load_multiple_operation"
8831 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8832 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8833 (set (match_operand:SI 3 "gpc_reg_operand" "")
8834 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8835 (set (match_operand:SI 4 "gpc_reg_operand" "")
8836 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8837 (set (match_operand:SI 5 "gpc_reg_operand" "")
8838 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8839 (set (match_operand:SI 6 "gpc_reg_operand" "")
8840 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8841 (set (match_operand:SI 7 "gpc_reg_operand" "")
8842 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8843 (set (match_operand:SI 8 "gpc_reg_operand" "")
8844 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8845 (set (match_operand:SI 9 "gpc_reg_operand" "")
8846 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8847 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8849 { return rs6000_output_load_multiple (operands); }"
8850 [(set_attr "type" "load_ux")
8851 (set_attr "length" "32")])
8853 (define_insn "*ldmsi7"
8854 [(match_parallel 0 "load_multiple_operation"
8855 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8856 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8857 (set (match_operand:SI 3 "gpc_reg_operand" "")
8858 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8859 (set (match_operand:SI 4 "gpc_reg_operand" "")
8860 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8861 (set (match_operand:SI 5 "gpc_reg_operand" "")
8862 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8863 (set (match_operand:SI 6 "gpc_reg_operand" "")
8864 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8865 (set (match_operand:SI 7 "gpc_reg_operand" "")
8866 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8867 (set (match_operand:SI 8 "gpc_reg_operand" "")
8868 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8869 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8871 { return rs6000_output_load_multiple (operands); }"
8872 [(set_attr "type" "load_ux")
8873 (set_attr "length" "32")])
8875 (define_insn "*ldmsi6"
8876 [(match_parallel 0 "load_multiple_operation"
8877 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8878 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8879 (set (match_operand:SI 3 "gpc_reg_operand" "")
8880 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8881 (set (match_operand:SI 4 "gpc_reg_operand" "")
8882 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8883 (set (match_operand:SI 5 "gpc_reg_operand" "")
8884 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8885 (set (match_operand:SI 6 "gpc_reg_operand" "")
8886 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8887 (set (match_operand:SI 7 "gpc_reg_operand" "")
8888 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8889 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8891 { return rs6000_output_load_multiple (operands); }"
8892 [(set_attr "type" "load_ux")
8893 (set_attr "length" "32")])
8895 (define_insn "*ldmsi5"
8896 [(match_parallel 0 "load_multiple_operation"
8897 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8898 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8899 (set (match_operand:SI 3 "gpc_reg_operand" "")
8900 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8901 (set (match_operand:SI 4 "gpc_reg_operand" "")
8902 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8903 (set (match_operand:SI 5 "gpc_reg_operand" "")
8904 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8905 (set (match_operand:SI 6 "gpc_reg_operand" "")
8906 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8907 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8909 { return rs6000_output_load_multiple (operands); }"
8910 [(set_attr "type" "load_ux")
8911 (set_attr "length" "32")])
8913 (define_insn "*ldmsi4"
8914 [(match_parallel 0 "load_multiple_operation"
8915 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8916 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8917 (set (match_operand:SI 3 "gpc_reg_operand" "")
8918 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8919 (set (match_operand:SI 4 "gpc_reg_operand" "")
8920 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8921 (set (match_operand:SI 5 "gpc_reg_operand" "")
8922 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8923 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8925 { return rs6000_output_load_multiple (operands); }"
8926 [(set_attr "type" "load_ux")
8927 (set_attr "length" "32")])
8929 (define_insn "*ldmsi3"
8930 [(match_parallel 0 "load_multiple_operation"
8931 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8932 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8933 (set (match_operand:SI 3 "gpc_reg_operand" "")
8934 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8935 (set (match_operand:SI 4 "gpc_reg_operand" "")
8936 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8937 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8939 { return rs6000_output_load_multiple (operands); }"
8940 [(set_attr "type" "load_ux")
8941 (set_attr "length" "32")])
8943 (define_expand "store_multiple"
8944 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8945 (match_operand:SI 1 "" ""))
8946 (clobber (scratch:SI))
8947 (use (match_operand:SI 2 "" ""))])]
8948 "TARGET_STRING && !TARGET_POWERPC64"
8957 /* Support only storing a constant number of fixed-point registers to
8958 memory and only bother with this if more than two; the machine
8959 doesn't support more than eight. */
8960 if (GET_CODE (operands[2]) != CONST_INT
8961 || INTVAL (operands[2]) <= 2
8962 || INTVAL (operands[2]) > 8
8963 || GET_CODE (operands[0]) != MEM
8964 || GET_CODE (operands[1]) != REG
8965 || REGNO (operands[1]) >= 32)
8968 count = INTVAL (operands[2]);
8969 regno = REGNO (operands[1]);
8971 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8972 to = force_reg (SImode, XEXP (operands[0], 0));
8973 op0 = replace_equiv_address (operands[0], to);
8975 XVECEXP (operands[3], 0, 0)
8976 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8977 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8978 gen_rtx_SCRATCH (SImode));
8980 for (i = 1; i < count; i++)
8981 XVECEXP (operands[3], 0, i + 1)
8982 = gen_rtx_SET (VOIDmode,
8983 adjust_address_nv (op0, SImode, i * 4),
8984 gen_rtx_REG (SImode, regno + i));
8987 (define_insn "*stmsi8"
8988 [(match_parallel 0 "store_multiple_operation"
8989 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8990 (match_operand:SI 2 "gpc_reg_operand" "r"))
8991 (clobber (match_scratch:SI 3 "=X"))
8992 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8993 (match_operand:SI 4 "gpc_reg_operand" "r"))
8994 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8995 (match_operand:SI 5 "gpc_reg_operand" "r"))
8996 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8997 (match_operand:SI 6 "gpc_reg_operand" "r"))
8998 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8999 (match_operand:SI 7 "gpc_reg_operand" "r"))
9000 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9001 (match_operand:SI 8 "gpc_reg_operand" "r"))
9002 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9003 (match_operand:SI 9 "gpc_reg_operand" "r"))
9004 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9005 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9006 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9007 "{stsi|stswi} %2,%1,%O0"
9008 [(set_attr "type" "store_ux")])
9010 (define_insn "*stmsi7"
9011 [(match_parallel 0 "store_multiple_operation"
9012 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9013 (match_operand:SI 2 "gpc_reg_operand" "r"))
9014 (clobber (match_scratch:SI 3 "=X"))
9015 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9016 (match_operand:SI 4 "gpc_reg_operand" "r"))
9017 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9018 (match_operand:SI 5 "gpc_reg_operand" "r"))
9019 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9020 (match_operand:SI 6 "gpc_reg_operand" "r"))
9021 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9022 (match_operand:SI 7 "gpc_reg_operand" "r"))
9023 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9024 (match_operand:SI 8 "gpc_reg_operand" "r"))
9025 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9026 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9027 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9028 "{stsi|stswi} %2,%1,%O0"
9029 [(set_attr "type" "store_ux")])
9031 (define_insn "*stmsi6"
9032 [(match_parallel 0 "store_multiple_operation"
9033 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9034 (match_operand:SI 2 "gpc_reg_operand" "r"))
9035 (clobber (match_scratch:SI 3 "=X"))
9036 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9037 (match_operand:SI 4 "gpc_reg_operand" "r"))
9038 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9039 (match_operand:SI 5 "gpc_reg_operand" "r"))
9040 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9041 (match_operand:SI 6 "gpc_reg_operand" "r"))
9042 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9043 (match_operand:SI 7 "gpc_reg_operand" "r"))
9044 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9045 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9046 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9047 "{stsi|stswi} %2,%1,%O0"
9048 [(set_attr "type" "store_ux")])
9050 (define_insn "*stmsi5"
9051 [(match_parallel 0 "store_multiple_operation"
9052 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9053 (match_operand:SI 2 "gpc_reg_operand" "r"))
9054 (clobber (match_scratch:SI 3 "=X"))
9055 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9056 (match_operand:SI 4 "gpc_reg_operand" "r"))
9057 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9058 (match_operand:SI 5 "gpc_reg_operand" "r"))
9059 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9060 (match_operand:SI 6 "gpc_reg_operand" "r"))
9061 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9062 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9063 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9064 "{stsi|stswi} %2,%1,%O0"
9065 [(set_attr "type" "store_ux")])
9067 (define_insn "*stmsi4"
9068 [(match_parallel 0 "store_multiple_operation"
9069 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9070 (match_operand:SI 2 "gpc_reg_operand" "r"))
9071 (clobber (match_scratch:SI 3 "=X"))
9072 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9073 (match_operand:SI 4 "gpc_reg_operand" "r"))
9074 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9075 (match_operand:SI 5 "gpc_reg_operand" "r"))
9076 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9077 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9078 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9079 "{stsi|stswi} %2,%1,%O0"
9080 [(set_attr "type" "store_ux")])
9082 (define_insn "*stmsi3"
9083 [(match_parallel 0 "store_multiple_operation"
9084 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9085 (match_operand:SI 2 "gpc_reg_operand" "r"))
9086 (clobber (match_scratch:SI 3 "=X"))
9087 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9088 (match_operand:SI 4 "gpc_reg_operand" "r"))
9089 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9090 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9091 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9092 "{stsi|stswi} %2,%1,%O0"
9093 [(set_attr "type" "store_ux")])
9095 (define_insn "*stmsi8_power"
9096 [(match_parallel 0 "store_multiple_operation"
9097 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9098 (match_operand:SI 2 "gpc_reg_operand" "r"))
9099 (clobber (match_scratch:SI 3 "=q"))
9100 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9101 (match_operand:SI 4 "gpc_reg_operand" "r"))
9102 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9103 (match_operand:SI 5 "gpc_reg_operand" "r"))
9104 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9105 (match_operand:SI 6 "gpc_reg_operand" "r"))
9106 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9107 (match_operand:SI 7 "gpc_reg_operand" "r"))
9108 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9109 (match_operand:SI 8 "gpc_reg_operand" "r"))
9110 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9111 (match_operand:SI 9 "gpc_reg_operand" "r"))
9112 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9113 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9114 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9115 "{stsi|stswi} %2,%1,%O0"
9116 [(set_attr "type" "store_ux")])
9118 (define_insn "*stmsi7_power"
9119 [(match_parallel 0 "store_multiple_operation"
9120 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9121 (match_operand:SI 2 "gpc_reg_operand" "r"))
9122 (clobber (match_scratch:SI 3 "=q"))
9123 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9124 (match_operand:SI 4 "gpc_reg_operand" "r"))
9125 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9126 (match_operand:SI 5 "gpc_reg_operand" "r"))
9127 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9128 (match_operand:SI 6 "gpc_reg_operand" "r"))
9129 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9130 (match_operand:SI 7 "gpc_reg_operand" "r"))
9131 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9132 (match_operand:SI 8 "gpc_reg_operand" "r"))
9133 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9134 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9135 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9136 "{stsi|stswi} %2,%1,%O0"
9137 [(set_attr "type" "store_ux")])
9139 (define_insn "*stmsi6_power"
9140 [(match_parallel 0 "store_multiple_operation"
9141 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9142 (match_operand:SI 2 "gpc_reg_operand" "r"))
9143 (clobber (match_scratch:SI 3 "=q"))
9144 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9145 (match_operand:SI 4 "gpc_reg_operand" "r"))
9146 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9147 (match_operand:SI 5 "gpc_reg_operand" "r"))
9148 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9149 (match_operand:SI 6 "gpc_reg_operand" "r"))
9150 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9151 (match_operand:SI 7 "gpc_reg_operand" "r"))
9152 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9153 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9154 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9155 "{stsi|stswi} %2,%1,%O0"
9156 [(set_attr "type" "store_ux")])
9158 (define_insn "*stmsi5_power"
9159 [(match_parallel 0 "store_multiple_operation"
9160 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9161 (match_operand:SI 2 "gpc_reg_operand" "r"))
9162 (clobber (match_scratch:SI 3 "=q"))
9163 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9164 (match_operand:SI 4 "gpc_reg_operand" "r"))
9165 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9166 (match_operand:SI 5 "gpc_reg_operand" "r"))
9167 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9168 (match_operand:SI 6 "gpc_reg_operand" "r"))
9169 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9170 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9171 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9172 "{stsi|stswi} %2,%1,%O0"
9173 [(set_attr "type" "store_ux")])
9175 (define_insn "*stmsi4_power"
9176 [(match_parallel 0 "store_multiple_operation"
9177 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9178 (match_operand:SI 2 "gpc_reg_operand" "r"))
9179 (clobber (match_scratch:SI 3 "=q"))
9180 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9181 (match_operand:SI 4 "gpc_reg_operand" "r"))
9182 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9183 (match_operand:SI 5 "gpc_reg_operand" "r"))
9184 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9185 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9186 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9187 "{stsi|stswi} %2,%1,%O0"
9188 [(set_attr "type" "store_ux")])
9190 (define_insn "*stmsi3_power"
9191 [(match_parallel 0 "store_multiple_operation"
9192 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9193 (match_operand:SI 2 "gpc_reg_operand" "r"))
9194 (clobber (match_scratch:SI 3 "=q"))
9195 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9196 (match_operand:SI 4 "gpc_reg_operand" "r"))
9197 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9198 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9199 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9200 "{stsi|stswi} %2,%1,%O0"
9201 [(set_attr "type" "store_ux")])
9203 (define_expand "setmemsi"
9204 [(parallel [(set (match_operand:BLK 0 "" "")
9205 (match_operand 2 "const_int_operand" ""))
9206 (use (match_operand:SI 1 "" ""))
9207 (use (match_operand:SI 3 "" ""))])]
9211 /* If value to set is not zero, use the library routine. */
9212 if (operands[2] != const0_rtx)
9215 if (expand_block_clear (operands))
9221 ;; String/block move insn.
9222 ;; Argument 0 is the destination
9223 ;; Argument 1 is the source
9224 ;; Argument 2 is the length
9225 ;; Argument 3 is the alignment
9227 (define_expand "movmemsi"
9228 [(parallel [(set (match_operand:BLK 0 "" "")
9229 (match_operand:BLK 1 "" ""))
9230 (use (match_operand:SI 2 "" ""))
9231 (use (match_operand:SI 3 "" ""))])]
9235 if (expand_block_move (operands))
9241 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9242 ;; register allocator doesn't have a clue about allocating 8 word registers.
9243 ;; rD/rS = r5 is preferred, efficient form.
9244 (define_expand "movmemsi_8reg"
9245 [(parallel [(set (match_operand 0 "" "")
9246 (match_operand 1 "" ""))
9247 (use (match_operand 2 "" ""))
9248 (use (match_operand 3 "" ""))
9249 (clobber (reg:SI 5))
9250 (clobber (reg:SI 6))
9251 (clobber (reg:SI 7))
9252 (clobber (reg:SI 8))
9253 (clobber (reg:SI 9))
9254 (clobber (reg:SI 10))
9255 (clobber (reg:SI 11))
9256 (clobber (reg:SI 12))
9257 (clobber (match_scratch:SI 4 ""))])]
9262 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9263 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9264 (use (match_operand:SI 2 "immediate_operand" "i"))
9265 (use (match_operand:SI 3 "immediate_operand" "i"))
9266 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9267 (clobber (reg:SI 6))
9268 (clobber (reg:SI 7))
9269 (clobber (reg:SI 8))
9270 (clobber (reg:SI 9))
9271 (clobber (reg:SI 10))
9272 (clobber (reg:SI 11))
9273 (clobber (reg:SI 12))
9274 (clobber (match_scratch:SI 5 "=q"))]
9275 "TARGET_STRING && TARGET_POWER
9276 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9277 || INTVAL (operands[2]) == 0)
9278 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9279 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9280 && REGNO (operands[4]) == 5"
9281 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9282 [(set_attr "type" "store_ux")
9283 (set_attr "length" "8")])
9286 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9287 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9288 (use (match_operand:SI 2 "immediate_operand" "i"))
9289 (use (match_operand:SI 3 "immediate_operand" "i"))
9290 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9291 (clobber (reg:SI 6))
9292 (clobber (reg:SI 7))
9293 (clobber (reg:SI 8))
9294 (clobber (reg:SI 9))
9295 (clobber (reg:SI 10))
9296 (clobber (reg:SI 11))
9297 (clobber (reg:SI 12))
9298 (clobber (match_scratch:SI 5 "=X"))]
9299 "TARGET_STRING && ! TARGET_POWER
9300 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9301 || INTVAL (operands[2]) == 0)
9302 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9303 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9304 && REGNO (operands[4]) == 5"
9305 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9306 [(set_attr "type" "store_ux")
9307 (set_attr "length" "8")])
9309 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9310 ;; register allocator doesn't have a clue about allocating 6 word registers.
9311 ;; rD/rS = r5 is preferred, efficient form.
9312 (define_expand "movmemsi_6reg"
9313 [(parallel [(set (match_operand 0 "" "")
9314 (match_operand 1 "" ""))
9315 (use (match_operand 2 "" ""))
9316 (use (match_operand 3 "" ""))
9317 (clobber (reg:SI 5))
9318 (clobber (reg:SI 6))
9319 (clobber (reg:SI 7))
9320 (clobber (reg:SI 8))
9321 (clobber (reg:SI 9))
9322 (clobber (reg:SI 10))
9323 (clobber (match_scratch:SI 4 ""))])]
9328 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9329 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9330 (use (match_operand:SI 2 "immediate_operand" "i"))
9331 (use (match_operand:SI 3 "immediate_operand" "i"))
9332 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9333 (clobber (reg:SI 6))
9334 (clobber (reg:SI 7))
9335 (clobber (reg:SI 8))
9336 (clobber (reg:SI 9))
9337 (clobber (reg:SI 10))
9338 (clobber (match_scratch:SI 5 "=q"))]
9339 "TARGET_STRING && TARGET_POWER
9340 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9341 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9342 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9343 && REGNO (operands[4]) == 5"
9344 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9345 [(set_attr "type" "store_ux")
9346 (set_attr "length" "8")])
9349 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9350 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9351 (use (match_operand:SI 2 "immediate_operand" "i"))
9352 (use (match_operand:SI 3 "immediate_operand" "i"))
9353 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9354 (clobber (reg:SI 6))
9355 (clobber (reg:SI 7))
9356 (clobber (reg:SI 8))
9357 (clobber (reg:SI 9))
9358 (clobber (reg:SI 10))
9359 (clobber (match_scratch:SI 5 "=X"))]
9360 "TARGET_STRING && ! TARGET_POWER
9361 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9362 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9363 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9364 && REGNO (operands[4]) == 5"
9365 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9366 [(set_attr "type" "store_ux")
9367 (set_attr "length" "8")])
9369 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9370 ;; problems with TImode.
9371 ;; rD/rS = r5 is preferred, efficient form.
9372 (define_expand "movmemsi_4reg"
9373 [(parallel [(set (match_operand 0 "" "")
9374 (match_operand 1 "" ""))
9375 (use (match_operand 2 "" ""))
9376 (use (match_operand 3 "" ""))
9377 (clobber (reg:SI 5))
9378 (clobber (reg:SI 6))
9379 (clobber (reg:SI 7))
9380 (clobber (reg:SI 8))
9381 (clobber (match_scratch:SI 4 ""))])]
9386 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9387 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9388 (use (match_operand:SI 2 "immediate_operand" "i"))
9389 (use (match_operand:SI 3 "immediate_operand" "i"))
9390 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9391 (clobber (reg:SI 6))
9392 (clobber (reg:SI 7))
9393 (clobber (reg:SI 8))
9394 (clobber (match_scratch:SI 5 "=q"))]
9395 "TARGET_STRING && TARGET_POWER
9396 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9397 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9398 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9399 && REGNO (operands[4]) == 5"
9400 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9401 [(set_attr "type" "store_ux")
9402 (set_attr "length" "8")])
9405 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9406 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9407 (use (match_operand:SI 2 "immediate_operand" "i"))
9408 (use (match_operand:SI 3 "immediate_operand" "i"))
9409 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9410 (clobber (reg:SI 6))
9411 (clobber (reg:SI 7))
9412 (clobber (reg:SI 8))
9413 (clobber (match_scratch:SI 5 "=X"))]
9414 "TARGET_STRING && ! TARGET_POWER
9415 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9416 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9417 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9418 && REGNO (operands[4]) == 5"
9419 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9420 [(set_attr "type" "store_ux")
9421 (set_attr "length" "8")])
9423 ;; Move up to 8 bytes at a time.
9424 (define_expand "movmemsi_2reg"
9425 [(parallel [(set (match_operand 0 "" "")
9426 (match_operand 1 "" ""))
9427 (use (match_operand 2 "" ""))
9428 (use (match_operand 3 "" ""))
9429 (clobber (match_scratch:DI 4 ""))
9430 (clobber (match_scratch:SI 5 ""))])]
9431 "TARGET_STRING && ! TARGET_POWERPC64"
9435 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9436 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9437 (use (match_operand:SI 2 "immediate_operand" "i"))
9438 (use (match_operand:SI 3 "immediate_operand" "i"))
9439 (clobber (match_scratch:DI 4 "=&r"))
9440 (clobber (match_scratch:SI 5 "=q"))]
9441 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9442 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9443 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9444 [(set_attr "type" "store_ux")
9445 (set_attr "length" "8")])
9448 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9449 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9450 (use (match_operand:SI 2 "immediate_operand" "i"))
9451 (use (match_operand:SI 3 "immediate_operand" "i"))
9452 (clobber (match_scratch:DI 4 "=&r"))
9453 (clobber (match_scratch:SI 5 "=X"))]
9454 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9455 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9456 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9457 [(set_attr "type" "store_ux")
9458 (set_attr "length" "8")])
9460 ;; Move up to 4 bytes at a time.
9461 (define_expand "movmemsi_1reg"
9462 [(parallel [(set (match_operand 0 "" "")
9463 (match_operand 1 "" ""))
9464 (use (match_operand 2 "" ""))
9465 (use (match_operand 3 "" ""))
9466 (clobber (match_scratch:SI 4 ""))
9467 (clobber (match_scratch:SI 5 ""))])]
9472 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9473 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9474 (use (match_operand:SI 2 "immediate_operand" "i"))
9475 (use (match_operand:SI 3 "immediate_operand" "i"))
9476 (clobber (match_scratch:SI 4 "=&r"))
9477 (clobber (match_scratch:SI 5 "=q"))]
9478 "TARGET_STRING && TARGET_POWER
9479 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9480 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9481 [(set_attr "type" "store_ux")
9482 (set_attr "length" "8")])
9485 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9486 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9487 (use (match_operand:SI 2 "immediate_operand" "i"))
9488 (use (match_operand:SI 3 "immediate_operand" "i"))
9489 (clobber (match_scratch:SI 4 "=&r"))
9490 (clobber (match_scratch:SI 5 "=X"))]
9491 "TARGET_STRING && ! TARGET_POWER
9492 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9493 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9494 [(set_attr "type" "store_ux")
9495 (set_attr "length" "8")])
9497 ;; Define insns that do load or store with update. Some of these we can
9498 ;; get by using pre-decrement or pre-increment, but the hardware can also
9499 ;; do cases where the increment is not the size of the object.
9501 ;; In all these cases, we use operands 0 and 1 for the register being
9502 ;; incremented because those are the operands that local-alloc will
9503 ;; tie and these are the pair most likely to be tieable (and the ones
9504 ;; that will benefit the most).
9506 (define_insn "*movdi_update1"
9507 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9508 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9509 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9510 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9511 (plus:DI (match_dup 1) (match_dup 2)))]
9512 "TARGET_POWERPC64 && TARGET_UPDATE"
9516 [(set_attr "type" "load_ux,load_u")])
9518 (define_insn "movdi_<mode>_update"
9519 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9520 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9521 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9522 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9523 (plus:P (match_dup 1) (match_dup 2)))]
9524 "TARGET_POWERPC64 && TARGET_UPDATE"
9528 [(set_attr "type" "store_ux,store_u")])
9530 (define_insn "*movsi_update1"
9531 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9532 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9533 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9534 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9535 (plus:SI (match_dup 1) (match_dup 2)))]
9538 {lux|lwzux} %3,%0,%2
9539 {lu|lwzu} %3,%2(%0)"
9540 [(set_attr "type" "load_ux,load_u")])
9542 (define_insn "*movsi_update2"
9543 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9545 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9546 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9547 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9548 (plus:DI (match_dup 1) (match_dup 2)))]
9551 [(set_attr "type" "load_ext_ux")])
9553 (define_insn "movsi_update"
9554 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9555 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9556 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9557 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9558 (plus:SI (match_dup 1) (match_dup 2)))]
9561 {stux|stwux} %3,%0,%2
9562 {stu|stwu} %3,%2(%0)"
9563 [(set_attr "type" "store_ux,store_u")])
9565 (define_insn "*movhi_update1"
9566 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9567 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9568 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9569 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9570 (plus:SI (match_dup 1) (match_dup 2)))]
9575 [(set_attr "type" "load_ux,load_u")])
9577 (define_insn "*movhi_update2"
9578 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9580 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9581 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9582 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9583 (plus:SI (match_dup 1) (match_dup 2)))]
9588 [(set_attr "type" "load_ux,load_u")])
9590 (define_insn "*movhi_update3"
9591 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9593 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9594 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9595 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9596 (plus:SI (match_dup 1) (match_dup 2)))]
9601 [(set_attr "type" "load_ext_ux,load_ext_u")])
9603 (define_insn "*movhi_update4"
9604 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9605 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9606 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9607 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9608 (plus:SI (match_dup 1) (match_dup 2)))]
9613 [(set_attr "type" "store_ux,store_u")])
9615 (define_insn "*movqi_update1"
9616 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9617 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9618 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9619 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9620 (plus:SI (match_dup 1) (match_dup 2)))]
9625 [(set_attr "type" "load_ux,load_u")])
9627 (define_insn "*movqi_update2"
9628 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9630 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9631 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9632 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9633 (plus:SI (match_dup 1) (match_dup 2)))]
9638 [(set_attr "type" "load_ux,load_u")])
9640 (define_insn "*movqi_update3"
9641 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9642 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9643 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9644 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9645 (plus:SI (match_dup 1) (match_dup 2)))]
9650 [(set_attr "type" "store_ux,store_u")])
9652 (define_insn "*movsf_update1"
9653 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9654 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9655 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9656 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9657 (plus:SI (match_dup 1) (match_dup 2)))]
9658 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9662 [(set_attr "type" "fpload_ux,fpload_u")])
9664 (define_insn "*movsf_update2"
9665 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9666 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9667 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9668 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9669 (plus:SI (match_dup 1) (match_dup 2)))]
9670 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9674 [(set_attr "type" "fpstore_ux,fpstore_u")])
9676 (define_insn "*movsf_update3"
9677 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9678 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9679 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9680 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9681 (plus:SI (match_dup 1) (match_dup 2)))]
9682 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9684 {lux|lwzux} %3,%0,%2
9685 {lu|lwzu} %3,%2(%0)"
9686 [(set_attr "type" "load_ux,load_u")])
9688 (define_insn "*movsf_update4"
9689 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9690 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9691 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9692 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9693 (plus:SI (match_dup 1) (match_dup 2)))]
9694 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9696 {stux|stwux} %3,%0,%2
9697 {stu|stwu} %3,%2(%0)"
9698 [(set_attr "type" "store_ux,store_u")])
9700 (define_insn "*movdf_update1"
9701 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9702 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9703 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9704 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9705 (plus:SI (match_dup 1) (match_dup 2)))]
9706 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9710 [(set_attr "type" "fpload_ux,fpload_u")])
9712 (define_insn "*movdf_update2"
9713 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9714 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9715 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9716 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9717 (plus:SI (match_dup 1) (match_dup 2)))]
9718 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9722 [(set_attr "type" "fpstore_ux,fpstore_u")])
9724 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9726 (define_insn "*lfq_power2"
9727 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
9728 (match_operand:V2DF 1 "memory_operand" ""))]
9730 && TARGET_HARD_FLOAT && TARGET_FPRS"
9734 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9735 (match_operand:DF 1 "memory_operand" ""))
9736 (set (match_operand:DF 2 "gpc_reg_operand" "")
9737 (match_operand:DF 3 "memory_operand" ""))]
9739 && TARGET_HARD_FLOAT && TARGET_FPRS
9740 && registers_ok_for_quad_peep (operands[0], operands[2])
9741 && mems_ok_for_quad_peep (operands[1], operands[3])"
9744 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
9745 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
9747 (define_insn "*stfq_power2"
9748 [(set (match_operand:V2DF 0 "memory_operand" "")
9749 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
9751 && TARGET_HARD_FLOAT && TARGET_FPRS"
9756 [(set (match_operand:DF 0 "memory_operand" "")
9757 (match_operand:DF 1 "gpc_reg_operand" ""))
9758 (set (match_operand:DF 2 "memory_operand" "")
9759 (match_operand:DF 3 "gpc_reg_operand" ""))]
9761 && TARGET_HARD_FLOAT && TARGET_FPRS
9762 && registers_ok_for_quad_peep (operands[1], operands[3])
9763 && mems_ok_for_quad_peep (operands[0], operands[2])"
9766 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
9767 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
9769 ;; After inserting conditional returns we can sometimes have
9770 ;; unnecessary register moves. Unfortunately we cannot have a
9771 ;; modeless peephole here, because some single SImode sets have early
9772 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9773 ;; sequences, using get_attr_length here will smash the operands
9774 ;; array. Neither is there an early_cobbler_p predicate.
9775 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
9777 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9778 (match_operand:DF 1 "any_operand" ""))
9779 (set (match_operand:DF 2 "gpc_reg_operand" "")
9781 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
9782 && peep2_reg_dead_p (2, operands[0])"
9783 [(set (match_dup 2) (match_dup 1))])
9786 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9787 (match_operand:SF 1 "any_operand" ""))
9788 (set (match_operand:SF 2 "gpc_reg_operand" "")
9790 "peep2_reg_dead_p (2, operands[0])"
9791 [(set (match_dup 2) (match_dup 1))])
9796 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9797 (define_insn "tls_gd_32"
9798 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9799 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9800 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9802 "HAVE_AS_TLS && !TARGET_64BIT"
9803 "addi %0,%1,%2@got@tlsgd")
9805 (define_insn "tls_gd_64"
9806 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9807 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9808 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9810 "HAVE_AS_TLS && TARGET_64BIT"
9811 "addi %0,%1,%2@got@tlsgd")
9813 (define_insn "tls_ld_32"
9814 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9815 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9817 "HAVE_AS_TLS && !TARGET_64BIT"
9818 "addi %0,%1,%&@got@tlsld")
9820 (define_insn "tls_ld_64"
9821 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9822 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9824 "HAVE_AS_TLS && TARGET_64BIT"
9825 "addi %0,%1,%&@got@tlsld")
9827 (define_insn "tls_dtprel_32"
9828 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9829 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9830 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9832 "HAVE_AS_TLS && !TARGET_64BIT"
9833 "addi %0,%1,%2@dtprel")
9835 (define_insn "tls_dtprel_64"
9836 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9837 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9838 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9840 "HAVE_AS_TLS && TARGET_64BIT"
9841 "addi %0,%1,%2@dtprel")
9843 (define_insn "tls_dtprel_ha_32"
9844 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9845 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9846 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9847 UNSPEC_TLSDTPRELHA))]
9848 "HAVE_AS_TLS && !TARGET_64BIT"
9849 "addis %0,%1,%2@dtprel@ha")
9851 (define_insn "tls_dtprel_ha_64"
9852 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9853 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9854 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9855 UNSPEC_TLSDTPRELHA))]
9856 "HAVE_AS_TLS && TARGET_64BIT"
9857 "addis %0,%1,%2@dtprel@ha")
9859 (define_insn "tls_dtprel_lo_32"
9860 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9861 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9862 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9863 UNSPEC_TLSDTPRELLO))]
9864 "HAVE_AS_TLS && !TARGET_64BIT"
9865 "addi %0,%1,%2@dtprel@l")
9867 (define_insn "tls_dtprel_lo_64"
9868 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9869 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9870 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9871 UNSPEC_TLSDTPRELLO))]
9872 "HAVE_AS_TLS && TARGET_64BIT"
9873 "addi %0,%1,%2@dtprel@l")
9875 (define_insn "tls_got_dtprel_32"
9876 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9877 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9878 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9879 UNSPEC_TLSGOTDTPREL))]
9880 "HAVE_AS_TLS && !TARGET_64BIT"
9881 "lwz %0,%2@got@dtprel(%1)")
9883 (define_insn "tls_got_dtprel_64"
9884 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9885 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9886 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9887 UNSPEC_TLSGOTDTPREL))]
9888 "HAVE_AS_TLS && TARGET_64BIT"
9889 "ld %0,%2@got@dtprel(%1)")
9891 (define_insn "tls_tprel_32"
9892 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9893 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9894 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9896 "HAVE_AS_TLS && !TARGET_64BIT"
9897 "addi %0,%1,%2@tprel")
9899 (define_insn "tls_tprel_64"
9900 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9901 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9902 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9904 "HAVE_AS_TLS && TARGET_64BIT"
9905 "addi %0,%1,%2@tprel")
9907 (define_insn "tls_tprel_ha_32"
9908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9909 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9910 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9911 UNSPEC_TLSTPRELHA))]
9912 "HAVE_AS_TLS && !TARGET_64BIT"
9913 "addis %0,%1,%2@tprel@ha")
9915 (define_insn "tls_tprel_ha_64"
9916 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9917 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9918 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9919 UNSPEC_TLSTPRELHA))]
9920 "HAVE_AS_TLS && TARGET_64BIT"
9921 "addis %0,%1,%2@tprel@ha")
9923 (define_insn "tls_tprel_lo_32"
9924 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9925 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9926 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9927 UNSPEC_TLSTPRELLO))]
9928 "HAVE_AS_TLS && !TARGET_64BIT"
9929 "addi %0,%1,%2@tprel@l")
9931 (define_insn "tls_tprel_lo_64"
9932 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9933 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9934 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9935 UNSPEC_TLSTPRELLO))]
9936 "HAVE_AS_TLS && TARGET_64BIT"
9937 "addi %0,%1,%2@tprel@l")
9939 ;; "b" output constraint here and on tls_tls input to support linker tls
9940 ;; optimization. The linker may edit the instructions emitted by a
9941 ;; tls_got_tprel/tls_tls pair to addis,addi.
9942 (define_insn "tls_got_tprel_32"
9943 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9944 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9945 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9946 UNSPEC_TLSGOTTPREL))]
9947 "HAVE_AS_TLS && !TARGET_64BIT"
9948 "lwz %0,%2@got@tprel(%1)")
9950 (define_insn "tls_got_tprel_64"
9951 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9952 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9953 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9954 UNSPEC_TLSGOTTPREL))]
9955 "HAVE_AS_TLS && TARGET_64BIT"
9956 "ld %0,%2@got@tprel(%1)")
9958 (define_insn "tls_tls_32"
9959 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9960 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9961 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9963 "HAVE_AS_TLS && !TARGET_64BIT"
9966 (define_insn "tls_tls_64"
9967 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9968 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9969 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9971 "HAVE_AS_TLS && TARGET_64BIT"
9974 ;; Next come insns related to the calling sequence.
9976 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9977 ;; We move the back-chain and decrement the stack pointer.
9979 (define_expand "allocate_stack"
9980 [(set (match_operand 0 "gpc_reg_operand" "=r")
9981 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9983 (minus (reg 1) (match_dup 1)))]
9986 { rtx chain = gen_reg_rtx (Pmode);
9987 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9990 emit_move_insn (chain, stack_bot);
9992 /* Check stack bounds if necessary. */
9993 if (current_function_limit_stack)
9996 available = expand_binop (Pmode, sub_optab,
9997 stack_pointer_rtx, stack_limit_rtx,
9998 NULL_RTX, 1, OPTAB_WIDEN);
9999 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10002 if (GET_CODE (operands[1]) != CONST_INT
10003 || INTVAL (operands[1]) < -32767
10004 || INTVAL (operands[1]) > 32768)
10006 neg_op0 = gen_reg_rtx (Pmode);
10008 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10010 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10013 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10016 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
10017 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
10021 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10022 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10023 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
10026 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10030 ;; These patterns say how to save and restore the stack pointer. We need not
10031 ;; save the stack pointer at function level since we are careful to
10032 ;; preserve the backchain. At block level, we have to restore the backchain
10033 ;; when we restore the stack pointer.
10035 ;; For nonlocal gotos, we must save both the stack pointer and its
10036 ;; backchain and restore both. Note that in the nonlocal case, the
10037 ;; save area is a memory location.
10039 (define_expand "save_stack_function"
10040 [(match_operand 0 "any_operand" "")
10041 (match_operand 1 "any_operand" "")]
10045 (define_expand "restore_stack_function"
10046 [(match_operand 0 "any_operand" "")
10047 (match_operand 1 "any_operand" "")]
10051 ;; Adjust stack pointer (op0) to a new value (op1).
10052 ;; First copy old stack backchain to new location, and ensure that the
10053 ;; scheduler won't reorder the sp assignment before the backchain write.
10054 (define_expand "restore_stack_block"
10055 [(set (match_dup 2) (match_dup 3))
10056 (set (match_dup 4) (match_dup 2))
10057 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10058 (set (match_operand 0 "register_operand" "")
10059 (match_operand 1 "register_operand" ""))]
10063 operands[2] = gen_reg_rtx (Pmode);
10064 operands[3] = gen_frame_mem (Pmode, operands[0]);
10065 operands[4] = gen_frame_mem (Pmode, operands[1]);
10066 operands[5] = gen_frame_mem (BLKmode, operands[0]);
10069 (define_expand "save_stack_nonlocal"
10070 [(set (match_dup 3) (match_dup 4))
10071 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10072 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10076 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10078 /* Copy the backchain to the first word, sp to the second. */
10079 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10080 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10081 operands[3] = gen_reg_rtx (Pmode);
10082 operands[4] = gen_frame_mem (Pmode, operands[1]);
10085 (define_expand "restore_stack_nonlocal"
10086 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10087 (set (match_dup 3) (match_dup 4))
10088 (set (match_dup 5) (match_dup 2))
10089 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10090 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10094 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10096 /* Restore the backchain from the first word, sp from the second. */
10097 operands[2] = gen_reg_rtx (Pmode);
10098 operands[3] = gen_reg_rtx (Pmode);
10099 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10100 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10101 operands[5] = gen_frame_mem (Pmode, operands[3]);
10102 operands[6] = gen_frame_mem (BLKmode, operands[0]);
10105 ;; TOC register handling.
10107 ;; Code to initialize the TOC register...
10109 (define_insn "load_toc_aix_si"
10110 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10111 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10112 (use (reg:SI 2))])]
10113 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10117 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10118 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10119 operands[2] = gen_rtx_REG (Pmode, 2);
10120 return \"{l|lwz} %0,%1(%2)\";
10122 [(set_attr "type" "load")])
10124 (define_insn "load_toc_aix_di"
10125 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10126 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10127 (use (reg:DI 2))])]
10128 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10132 #ifdef TARGET_RELOCATABLE
10133 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10134 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10136 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10139 strcat (buf, \"@toc\");
10140 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10141 operands[2] = gen_rtx_REG (Pmode, 2);
10142 return \"ld %0,%1(%2)\";
10144 [(set_attr "type" "load")])
10146 (define_insn "load_toc_v4_pic_si"
10147 [(set (match_operand:SI 0 "register_operand" "=l")
10148 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10149 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10150 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10151 [(set_attr "type" "branch")
10152 (set_attr "length" "4")])
10154 (define_insn "load_toc_v4_PIC_1"
10155 [(set (match_operand:SI 0 "register_operand" "=l")
10156 (match_operand:SI 1 "immediate_operand" "s"))
10157 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
10158 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10159 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10160 "bcl 20,31,%1\\n%1:"
10161 [(set_attr "type" "branch")
10162 (set_attr "length" "4")])
10164 (define_insn "load_toc_v4_PIC_1b"
10165 [(set (match_operand:SI 0 "register_operand" "=l")
10166 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
10168 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10169 "bcl 20,31,$+8\\n\\t.long %1-$"
10170 [(set_attr "type" "branch")
10171 (set_attr "length" "8")])
10173 (define_insn "load_toc_v4_PIC_2"
10174 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10175 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10176 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10177 (match_operand:SI 3 "immediate_operand" "s")))))]
10178 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10179 "{l|lwz} %0,%2-%3(%1)"
10180 [(set_attr "type" "load")])
10182 (define_insn "load_toc_v4_PIC_3b"
10183 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10184 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10186 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10187 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10188 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10189 "{cau|addis} %0,%1,%2-%3@ha")
10191 (define_insn "load_toc_v4_PIC_3c"
10192 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10193 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10194 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10195 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10196 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10197 "{cal|addi} %0,%1,%2-%3@l")
10199 ;; If the TOC is shared over a translation unit, as happens with all
10200 ;; the kinds of PIC that we support, we need to restore the TOC
10201 ;; pointer only when jumping over units of translation.
10202 ;; On Darwin, we need to reload the picbase.
10204 (define_expand "builtin_setjmp_receiver"
10205 [(use (label_ref (match_operand 0 "" "")))]
10206 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10207 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10208 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10212 if (DEFAULT_ABI == ABI_DARWIN)
10214 const char *picbase = machopic_function_base_name ();
10215 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10216 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10220 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10221 CODE_LABEL_NUMBER (operands[0]));
10222 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10224 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10225 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10229 rs6000_emit_load_toc_table (FALSE);
10233 ;; Elf specific ways of loading addresses for non-PIC code.
10234 ;; The output of this could be r0, but we make a very strong
10235 ;; preference for a base register because it will usually
10236 ;; be needed there.
10237 (define_insn "elf_high"
10238 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10239 (high:SI (match_operand 1 "" "")))]
10240 "TARGET_ELF && ! TARGET_64BIT"
10241 "{liu|lis} %0,%1@ha")
10243 (define_insn "elf_low"
10244 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10245 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10246 (match_operand 2 "" "")))]
10247 "TARGET_ELF && ! TARGET_64BIT"
10249 {cal|la} %0,%2@l(%1)
10250 {ai|addic} %0,%1,%K2")
10252 ;; A function pointer under AIX is a pointer to a data area whose first word
10253 ;; contains the actual address of the function, whose second word contains a
10254 ;; pointer to its TOC, and whose third word contains a value to place in the
10255 ;; static chain register (r11). Note that if we load the static chain, our
10256 ;; "trampoline" need not have any executable code.
10258 (define_expand "call_indirect_aix32"
10259 [(set (match_dup 2)
10260 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10261 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10264 (mem:SI (plus:SI (match_dup 0)
10267 (mem:SI (plus:SI (match_dup 0)
10269 (parallel [(call (mem:SI (match_dup 2))
10270 (match_operand 1 "" ""))
10274 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10275 (clobber (scratch:SI))])]
10278 { operands[2] = gen_reg_rtx (SImode); }")
10280 (define_expand "call_indirect_aix64"
10281 [(set (match_dup 2)
10282 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10283 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10286 (mem:DI (plus:DI (match_dup 0)
10289 (mem:DI (plus:DI (match_dup 0)
10291 (parallel [(call (mem:SI (match_dup 2))
10292 (match_operand 1 "" ""))
10296 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10297 (clobber (scratch:SI))])]
10300 { operands[2] = gen_reg_rtx (DImode); }")
10302 (define_expand "call_value_indirect_aix32"
10303 [(set (match_dup 3)
10304 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10305 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10308 (mem:SI (plus:SI (match_dup 1)
10311 (mem:SI (plus:SI (match_dup 1)
10313 (parallel [(set (match_operand 0 "" "")
10314 (call (mem:SI (match_dup 3))
10315 (match_operand 2 "" "")))
10319 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10320 (clobber (scratch:SI))])]
10323 { operands[3] = gen_reg_rtx (SImode); }")
10325 (define_expand "call_value_indirect_aix64"
10326 [(set (match_dup 3)
10327 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10328 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10331 (mem:DI (plus:DI (match_dup 1)
10334 (mem:DI (plus:DI (match_dup 1)
10336 (parallel [(set (match_operand 0 "" "")
10337 (call (mem:SI (match_dup 3))
10338 (match_operand 2 "" "")))
10342 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10343 (clobber (scratch:SI))])]
10346 { operands[3] = gen_reg_rtx (DImode); }")
10348 ;; Now the definitions for the call and call_value insns
10349 (define_expand "call"
10350 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10351 (match_operand 1 "" ""))
10352 (use (match_operand 2 "" ""))
10353 (clobber (scratch:SI))])]
10358 if (MACHOPIC_INDIRECT)
10359 operands[0] = machopic_indirect_call_target (operands[0]);
10362 gcc_assert (GET_CODE (operands[0]) == MEM);
10363 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10365 operands[0] = XEXP (operands[0], 0);
10367 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10369 && GET_CODE (operands[0]) == SYMBOL_REF
10370 && !SYMBOL_REF_LOCAL_P (operands[0]))
10375 tmp = gen_rtvec (3,
10376 gen_rtx_CALL (VOIDmode,
10377 gen_rtx_MEM (SImode, operands[0]),
10379 gen_rtx_USE (VOIDmode, operands[2]),
10380 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10381 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10382 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10386 if (GET_CODE (operands[0]) != SYMBOL_REF
10387 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10388 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10390 if (INTVAL (operands[2]) & CALL_LONG)
10391 operands[0] = rs6000_longcall_ref (operands[0]);
10393 switch (DEFAULT_ABI)
10397 operands[0] = force_reg (Pmode, operands[0]);
10401 /* AIX function pointers are really pointers to a three word
10403 emit_call_insn (TARGET_32BIT
10404 ? gen_call_indirect_aix32 (force_reg (SImode,
10407 : gen_call_indirect_aix64 (force_reg (DImode,
10413 gcc_unreachable ();
10418 (define_expand "call_value"
10419 [(parallel [(set (match_operand 0 "" "")
10420 (call (mem:SI (match_operand 1 "address_operand" ""))
10421 (match_operand 2 "" "")))
10422 (use (match_operand 3 "" ""))
10423 (clobber (scratch:SI))])]
10428 if (MACHOPIC_INDIRECT)
10429 operands[1] = machopic_indirect_call_target (operands[1]);
10432 gcc_assert (GET_CODE (operands[1]) == MEM);
10433 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10435 operands[1] = XEXP (operands[1], 0);
10437 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10439 && GET_CODE (operands[1]) == SYMBOL_REF
10440 && !SYMBOL_REF_LOCAL_P (operands[1]))
10445 tmp = gen_rtvec (3,
10446 gen_rtx_SET (VOIDmode,
10448 gen_rtx_CALL (VOIDmode,
10449 gen_rtx_MEM (SImode,
10452 gen_rtx_USE (VOIDmode, operands[3]),
10453 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10454 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10455 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10459 if (GET_CODE (operands[1]) != SYMBOL_REF
10460 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10461 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10463 if (INTVAL (operands[3]) & CALL_LONG)
10464 operands[1] = rs6000_longcall_ref (operands[1]);
10466 switch (DEFAULT_ABI)
10470 operands[1] = force_reg (Pmode, operands[1]);
10474 /* AIX function pointers are really pointers to a three word
10476 emit_call_insn (TARGET_32BIT
10477 ? gen_call_value_indirect_aix32 (operands[0],
10481 : gen_call_value_indirect_aix64 (operands[0],
10488 gcc_unreachable ();
10493 ;; Call to function in current module. No TOC pointer reload needed.
10494 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10495 ;; either the function was not prototyped, or it was prototyped as a
10496 ;; variable argument function. It is > 0 if FP registers were passed
10497 ;; and < 0 if they were not.
10499 (define_insn "*call_local32"
10500 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10501 (match_operand 1 "" "g,g"))
10502 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10503 (clobber (match_scratch:SI 3 "=l,l"))]
10504 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10507 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10508 output_asm_insn (\"crxor 6,6,6\", operands);
10510 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10511 output_asm_insn (\"creqv 6,6,6\", operands);
10513 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10515 [(set_attr "type" "branch")
10516 (set_attr "length" "4,8")])
10518 (define_insn "*call_local64"
10519 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10520 (match_operand 1 "" "g,g"))
10521 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10522 (clobber (match_scratch:SI 3 "=l,l"))]
10523 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10526 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10527 output_asm_insn (\"crxor 6,6,6\", operands);
10529 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10530 output_asm_insn (\"creqv 6,6,6\", operands);
10532 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10534 [(set_attr "type" "branch")
10535 (set_attr "length" "4,8")])
10537 (define_insn "*call_value_local32"
10538 [(set (match_operand 0 "" "")
10539 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10540 (match_operand 2 "" "g,g")))
10541 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10542 (clobber (match_scratch:SI 4 "=l,l"))]
10543 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10546 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10547 output_asm_insn (\"crxor 6,6,6\", operands);
10549 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10550 output_asm_insn (\"creqv 6,6,6\", operands);
10552 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10554 [(set_attr "type" "branch")
10555 (set_attr "length" "4,8")])
10558 (define_insn "*call_value_local64"
10559 [(set (match_operand 0 "" "")
10560 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10561 (match_operand 2 "" "g,g")))
10562 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10563 (clobber (match_scratch:SI 4 "=l,l"))]
10564 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10567 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10568 output_asm_insn (\"crxor 6,6,6\", operands);
10570 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10571 output_asm_insn (\"creqv 6,6,6\", operands);
10573 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10575 [(set_attr "type" "branch")
10576 (set_attr "length" "4,8")])
10578 ;; Call to function which may be in another module. Restore the TOC
10579 ;; pointer (r2) after the call unless this is System V.
10580 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10581 ;; either the function was not prototyped, or it was prototyped as a
10582 ;; variable argument function. It is > 0 if FP registers were passed
10583 ;; and < 0 if they were not.
10585 (define_insn "*call_indirect_nonlocal_aix32"
10586 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10587 (match_operand 1 "" "g,g"))
10591 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10592 (clobber (match_scratch:SI 2 "=l,l"))]
10593 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10594 "b%T0l\;{l|lwz} 2,20(1)"
10595 [(set_attr "type" "jmpreg")
10596 (set_attr "length" "8")])
10598 (define_insn "*call_nonlocal_aix32"
10599 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10600 (match_operand 1 "" "g"))
10601 (use (match_operand:SI 2 "immediate_operand" "O"))
10602 (clobber (match_scratch:SI 3 "=l"))]
10604 && DEFAULT_ABI == ABI_AIX
10605 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10607 [(set_attr "type" "branch")
10608 (set_attr "length" "8")])
10610 (define_insn "*call_indirect_nonlocal_aix64"
10611 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10612 (match_operand 1 "" "g,g"))
10616 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10617 (clobber (match_scratch:SI 2 "=l,l"))]
10618 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10619 "b%T0l\;ld 2,40(1)"
10620 [(set_attr "type" "jmpreg")
10621 (set_attr "length" "8")])
10623 (define_insn "*call_nonlocal_aix64"
10624 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10625 (match_operand 1 "" "g"))
10626 (use (match_operand:SI 2 "immediate_operand" "O"))
10627 (clobber (match_scratch:SI 3 "=l"))]
10629 && DEFAULT_ABI == ABI_AIX
10630 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10632 [(set_attr "type" "branch")
10633 (set_attr "length" "8")])
10635 (define_insn "*call_value_indirect_nonlocal_aix32"
10636 [(set (match_operand 0 "" "")
10637 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10638 (match_operand 2 "" "g,g")))
10642 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10643 (clobber (match_scratch:SI 3 "=l,l"))]
10644 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10645 "b%T1l\;{l|lwz} 2,20(1)"
10646 [(set_attr "type" "jmpreg")
10647 (set_attr "length" "8")])
10649 (define_insn "*call_value_nonlocal_aix32"
10650 [(set (match_operand 0 "" "")
10651 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10652 (match_operand 2 "" "g")))
10653 (use (match_operand:SI 3 "immediate_operand" "O"))
10654 (clobber (match_scratch:SI 4 "=l"))]
10656 && DEFAULT_ABI == ABI_AIX
10657 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10659 [(set_attr "type" "branch")
10660 (set_attr "length" "8")])
10662 (define_insn "*call_value_indirect_nonlocal_aix64"
10663 [(set (match_operand 0 "" "")
10664 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
10665 (match_operand 2 "" "g,g")))
10669 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10670 (clobber (match_scratch:SI 3 "=l,l"))]
10671 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10672 "b%T1l\;ld 2,40(1)"
10673 [(set_attr "type" "jmpreg")
10674 (set_attr "length" "8")])
10676 (define_insn "*call_value_nonlocal_aix64"
10677 [(set (match_operand 0 "" "")
10678 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10679 (match_operand 2 "" "g")))
10680 (use (match_operand:SI 3 "immediate_operand" "O"))
10681 (clobber (match_scratch:SI 4 "=l"))]
10683 && DEFAULT_ABI == ABI_AIX
10684 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10686 [(set_attr "type" "branch")
10687 (set_attr "length" "8")])
10689 ;; A function pointer under System V is just a normal pointer
10690 ;; operands[0] is the function pointer
10691 ;; operands[1] is the stack size to clean up
10692 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10693 ;; which indicates how to set cr1
10695 (define_insn "*call_indirect_nonlocal_sysv<mode>"
10696 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
10697 (match_operand 1 "" "g,g,g,g"))
10698 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10699 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
10700 "DEFAULT_ABI == ABI_V4
10701 || DEFAULT_ABI == ABI_DARWIN"
10703 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10704 output_asm_insn ("crxor 6,6,6", operands);
10706 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10707 output_asm_insn ("creqv 6,6,6", operands);
10711 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10712 (set_attr "length" "4,4,8,8")])
10714 (define_insn "*call_nonlocal_sysv<mode>"
10715 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10716 (match_operand 1 "" "g,g"))
10717 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10718 (clobber (match_scratch:SI 3 "=l,l"))]
10719 "(DEFAULT_ABI == ABI_DARWIN
10720 || (DEFAULT_ABI == ABI_V4
10721 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10723 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10724 output_asm_insn ("crxor 6,6,6", operands);
10726 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10727 output_asm_insn ("creqv 6,6,6", operands);
10730 return output_call(insn, operands, 0, 2);
10732 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10734 if (TARGET_SECURE_PLT && flag_pic == 2)
10735 /* The magic 32768 offset here and in the other sysv call insns
10736 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10737 See sysv4.h:toc_section. */
10738 return "bl %z0+32768@plt";
10740 return "bl %z0@plt";
10746 [(set_attr "type" "branch,branch")
10747 (set_attr "length" "4,8")])
10749 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
10750 [(set (match_operand 0 "" "")
10751 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
10752 (match_operand 2 "" "g,g,g,g")))
10753 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10754 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
10755 "DEFAULT_ABI == ABI_V4
10756 || DEFAULT_ABI == ABI_DARWIN"
10758 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10759 output_asm_insn ("crxor 6,6,6", operands);
10761 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10762 output_asm_insn ("creqv 6,6,6", operands);
10766 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10767 (set_attr "length" "4,4,8,8")])
10769 (define_insn "*call_value_nonlocal_sysv<mode>"
10770 [(set (match_operand 0 "" "")
10771 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
10772 (match_operand 2 "" "g,g")))
10773 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10774 (clobber (match_scratch:SI 4 "=l,l"))]
10775 "(DEFAULT_ABI == ABI_DARWIN
10776 || (DEFAULT_ABI == ABI_V4
10777 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10779 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10780 output_asm_insn ("crxor 6,6,6", operands);
10782 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10783 output_asm_insn ("creqv 6,6,6", operands);
10786 return output_call(insn, operands, 1, 3);
10788 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10790 if (TARGET_SECURE_PLT && flag_pic == 2)
10791 return "bl %z1+32768@plt";
10793 return "bl %z1@plt";
10799 [(set_attr "type" "branch,branch")
10800 (set_attr "length" "4,8")])
10802 ;; Call subroutine returning any type.
10803 (define_expand "untyped_call"
10804 [(parallel [(call (match_operand 0 "" "")
10806 (match_operand 1 "" "")
10807 (match_operand 2 "" "")])]
10813 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10815 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10817 rtx set = XVECEXP (operands[2], 0, i);
10818 emit_move_insn (SET_DEST (set), SET_SRC (set));
10821 /* The optimizer does not know that the call sets the function value
10822 registers we stored in the result block. We avoid problems by
10823 claiming that all hard registers are used and clobbered at this
10825 emit_insn (gen_blockage ());
10830 ;; sibling call patterns
10831 (define_expand "sibcall"
10832 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10833 (match_operand 1 "" ""))
10834 (use (match_operand 2 "" ""))
10835 (use (match_operand 3 "" ""))
10841 if (MACHOPIC_INDIRECT)
10842 operands[0] = machopic_indirect_call_target (operands[0]);
10845 gcc_assert (GET_CODE (operands[0]) == MEM);
10846 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10848 operands[0] = XEXP (operands[0], 0);
10849 operands[3] = gen_reg_rtx (SImode);
10853 ;; this and similar patterns must be marked as using LR, otherwise
10854 ;; dataflow will try to delete the store into it. This is true
10855 ;; even when the actual reg to jump to is in CTR, when LR was
10856 ;; saved and restored around the PIC-setting BCL.
10857 (define_insn "*sibcall_local32"
10858 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10859 (match_operand 1 "" "g,g"))
10860 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10861 (use (match_operand:SI 3 "register_operand" "l,l"))
10863 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10866 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10867 output_asm_insn (\"crxor 6,6,6\", operands);
10869 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10870 output_asm_insn (\"creqv 6,6,6\", operands);
10872 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10874 [(set_attr "type" "branch")
10875 (set_attr "length" "4,8")])
10877 (define_insn "*sibcall_local64"
10878 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10879 (match_operand 1 "" "g,g"))
10880 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10881 (use (match_operand:SI 3 "register_operand" "l,l"))
10883 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10886 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10887 output_asm_insn (\"crxor 6,6,6\", operands);
10889 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10890 output_asm_insn (\"creqv 6,6,6\", operands);
10892 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10894 [(set_attr "type" "branch")
10895 (set_attr "length" "4,8")])
10897 (define_insn "*sibcall_value_local32"
10898 [(set (match_operand 0 "" "")
10899 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10900 (match_operand 2 "" "g,g")))
10901 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10902 (use (match_operand:SI 4 "register_operand" "l,l"))
10904 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10907 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10908 output_asm_insn (\"crxor 6,6,6\", operands);
10910 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10911 output_asm_insn (\"creqv 6,6,6\", operands);
10913 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10915 [(set_attr "type" "branch")
10916 (set_attr "length" "4,8")])
10919 (define_insn "*sibcall_value_local64"
10920 [(set (match_operand 0 "" "")
10921 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10922 (match_operand 2 "" "g,g")))
10923 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10924 (use (match_operand:SI 4 "register_operand" "l,l"))
10926 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10929 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10930 output_asm_insn (\"crxor 6,6,6\", operands);
10932 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10933 output_asm_insn (\"creqv 6,6,6\", operands);
10935 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10937 [(set_attr "type" "branch")
10938 (set_attr "length" "4,8")])
10940 (define_insn "*sibcall_nonlocal_aix32"
10941 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10942 (match_operand 1 "" "g"))
10943 (use (match_operand:SI 2 "immediate_operand" "O"))
10944 (use (match_operand:SI 3 "register_operand" "l"))
10947 && DEFAULT_ABI == ABI_AIX
10948 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10950 [(set_attr "type" "branch")
10951 (set_attr "length" "4")])
10953 (define_insn "*sibcall_nonlocal_aix64"
10954 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10955 (match_operand 1 "" "g"))
10956 (use (match_operand:SI 2 "immediate_operand" "O"))
10957 (use (match_operand:SI 3 "register_operand" "l"))
10960 && DEFAULT_ABI == ABI_AIX
10961 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10963 [(set_attr "type" "branch")
10964 (set_attr "length" "4")])
10966 (define_insn "*sibcall_value_nonlocal_aix32"
10967 [(set (match_operand 0 "" "")
10968 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10969 (match_operand 2 "" "g")))
10970 (use (match_operand:SI 3 "immediate_operand" "O"))
10971 (use (match_operand:SI 4 "register_operand" "l"))
10974 && DEFAULT_ABI == ABI_AIX
10975 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10977 [(set_attr "type" "branch")
10978 (set_attr "length" "4")])
10980 (define_insn "*sibcall_value_nonlocal_aix64"
10981 [(set (match_operand 0 "" "")
10982 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10983 (match_operand 2 "" "g")))
10984 (use (match_operand:SI 3 "immediate_operand" "O"))
10985 (use (match_operand:SI 4 "register_operand" "l"))
10988 && DEFAULT_ABI == ABI_AIX
10989 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10991 [(set_attr "type" "branch")
10992 (set_attr "length" "4")])
10994 (define_insn "*sibcall_nonlocal_sysv<mode>"
10995 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10996 (match_operand 1 "" ""))
10997 (use (match_operand 2 "immediate_operand" "O,n"))
10998 (use (match_operand:SI 3 "register_operand" "l,l"))
11000 "(DEFAULT_ABI == ABI_DARWIN
11001 || DEFAULT_ABI == ABI_V4)
11002 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11005 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11006 output_asm_insn (\"crxor 6,6,6\", operands);
11008 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11009 output_asm_insn (\"creqv 6,6,6\", operands);
11011 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11013 if (TARGET_SECURE_PLT && flag_pic == 2)
11014 return \"b %z0+32768@plt\";
11016 return \"b %z0@plt\";
11021 [(set_attr "type" "branch,branch")
11022 (set_attr "length" "4,8")])
11024 (define_expand "sibcall_value"
11025 [(parallel [(set (match_operand 0 "register_operand" "")
11026 (call (mem:SI (match_operand 1 "address_operand" ""))
11027 (match_operand 2 "" "")))
11028 (use (match_operand 3 "" ""))
11029 (use (match_operand 4 "" ""))
11035 if (MACHOPIC_INDIRECT)
11036 operands[1] = machopic_indirect_call_target (operands[1]);
11039 gcc_assert (GET_CODE (operands[1]) == MEM);
11040 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11042 operands[1] = XEXP (operands[1], 0);
11043 operands[4] = gen_reg_rtx (SImode);
11047 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11048 [(set (match_operand 0 "" "")
11049 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11050 (match_operand 2 "" "")))
11051 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11052 (use (match_operand:SI 4 "register_operand" "l,l"))
11054 "(DEFAULT_ABI == ABI_DARWIN
11055 || DEFAULT_ABI == ABI_V4)
11056 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11059 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11060 output_asm_insn (\"crxor 6,6,6\", operands);
11062 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11063 output_asm_insn (\"creqv 6,6,6\", operands);
11065 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11067 if (TARGET_SECURE_PLT && flag_pic == 2)
11068 return \"b %z1+32768@plt\";
11070 return \"b %z1@plt\";
11075 [(set_attr "type" "branch,branch")
11076 (set_attr "length" "4,8")])
11078 (define_expand "sibcall_epilogue"
11079 [(use (const_int 0))]
11080 "TARGET_SCHED_PROLOG"
11083 rs6000_emit_epilogue (TRUE);
11087 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11088 ;; all of memory. This blocks insns from being moved across this point.
11090 (define_insn "blockage"
11091 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11095 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11096 ;; signed & unsigned, and one type of branch.
11098 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11099 ;; insns, and branches. We store the operands of compares until we see
11101 (define_expand "cmp<mode>"
11103 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11104 (match_operand:GPR 1 "reg_or_short_operand" "")))]
11108 /* Take care of the possibility that operands[1] might be negative but
11109 this might be a logical operation. That insn doesn't exist. */
11110 if (GET_CODE (operands[1]) == CONST_INT
11111 && INTVAL (operands[1]) < 0)
11112 operands[1] = force_reg (<MODE>mode, operands[1]);
11114 rs6000_compare_op0 = operands[0];
11115 rs6000_compare_op1 = operands[1];
11116 rs6000_compare_fp_p = 0;
11120 (define_expand "cmp<mode>"
11121 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11122 (match_operand:FP 1 "gpc_reg_operand" "")))]
11126 rs6000_compare_op0 = operands[0];
11127 rs6000_compare_op1 = operands[1];
11128 rs6000_compare_fp_p = 1;
11132 (define_expand "beq"
11133 [(use (match_operand 0 "" ""))]
11135 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11137 (define_expand "bne"
11138 [(use (match_operand 0 "" ""))]
11140 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11142 (define_expand "bge"
11143 [(use (match_operand 0 "" ""))]
11145 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11147 (define_expand "bgt"
11148 [(use (match_operand 0 "" ""))]
11150 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11152 (define_expand "ble"
11153 [(use (match_operand 0 "" ""))]
11155 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11157 (define_expand "blt"
11158 [(use (match_operand 0 "" ""))]
11160 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11162 (define_expand "bgeu"
11163 [(use (match_operand 0 "" ""))]
11165 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11167 (define_expand "bgtu"
11168 [(use (match_operand 0 "" ""))]
11170 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11172 (define_expand "bleu"
11173 [(use (match_operand 0 "" ""))]
11175 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11177 (define_expand "bltu"
11178 [(use (match_operand 0 "" ""))]
11180 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11182 (define_expand "bunordered"
11183 [(use (match_operand 0 "" ""))]
11184 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11185 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11187 (define_expand "bordered"
11188 [(use (match_operand 0 "" ""))]
11189 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11190 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11192 (define_expand "buneq"
11193 [(use (match_operand 0 "" ""))]
11195 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11197 (define_expand "bunge"
11198 [(use (match_operand 0 "" ""))]
11200 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11202 (define_expand "bungt"
11203 [(use (match_operand 0 "" ""))]
11205 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11207 (define_expand "bunle"
11208 [(use (match_operand 0 "" ""))]
11210 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11212 (define_expand "bunlt"
11213 [(use (match_operand 0 "" ""))]
11215 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11217 (define_expand "bltgt"
11218 [(use (match_operand 0 "" ""))]
11220 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11222 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11223 ;; For SEQ, likewise, except that comparisons with zero should be done
11224 ;; with an scc insns. However, due to the order that combine see the
11225 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11226 ;; the cases we don't want to handle.
11227 (define_expand "seq"
11228 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11230 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11232 (define_expand "sne"
11233 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11237 if (! rs6000_compare_fp_p)
11240 rs6000_emit_sCOND (NE, operands[0]);
11244 ;; A >= 0 is best done the portable way for A an integer.
11245 (define_expand "sge"
11246 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11250 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11253 rs6000_emit_sCOND (GE, operands[0]);
11257 ;; A > 0 is best done using the portable sequence, so fail in that case.
11258 (define_expand "sgt"
11259 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11263 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11266 rs6000_emit_sCOND (GT, operands[0]);
11270 ;; A <= 0 is best done the portable way for A an integer.
11271 (define_expand "sle"
11272 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11276 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11279 rs6000_emit_sCOND (LE, operands[0]);
11283 ;; A < 0 is best done in the portable way for A an integer.
11284 (define_expand "slt"
11285 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11289 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11292 rs6000_emit_sCOND (LT, operands[0]);
11296 (define_expand "sgeu"
11297 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11299 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11301 (define_expand "sgtu"
11302 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11304 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11306 (define_expand "sleu"
11307 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11309 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11311 (define_expand "sltu"
11312 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11314 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11316 (define_expand "sunordered"
11317 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11318 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11319 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11321 (define_expand "sordered"
11322 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11323 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11324 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11326 (define_expand "suneq"
11327 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11329 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11331 (define_expand "sunge"
11332 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11334 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11336 (define_expand "sungt"
11337 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11339 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11341 (define_expand "sunle"
11342 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11344 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11346 (define_expand "sunlt"
11347 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11349 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11351 (define_expand "sltgt"
11352 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11354 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11356 (define_expand "stack_protect_set"
11357 [(match_operand 0 "memory_operand" "")
11358 (match_operand 1 "memory_operand" "")]
11361 #ifdef TARGET_THREAD_SSP_OFFSET
11362 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11363 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11364 operands[1] = gen_rtx_MEM (Pmode, addr);
11367 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11369 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11373 (define_insn "stack_protect_setsi"
11374 [(set (match_operand:SI 0 "memory_operand" "=m")
11375 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11376 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11378 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11379 [(set_attr "type" "three")
11380 (set_attr "length" "12")])
11382 (define_insn "stack_protect_setdi"
11383 [(set (match_operand:DI 0 "memory_operand" "=m")
11384 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11385 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11387 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11388 [(set_attr "type" "three")
11389 (set_attr "length" "12")])
11391 (define_expand "stack_protect_test"
11392 [(match_operand 0 "memory_operand" "")
11393 (match_operand 1 "memory_operand" "")
11394 (match_operand 2 "" "")]
11397 #ifdef TARGET_THREAD_SSP_OFFSET
11398 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11399 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11400 operands[1] = gen_rtx_MEM (Pmode, addr);
11402 rs6000_compare_op0 = operands[0];
11403 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11405 rs6000_compare_fp_p = 0;
11406 emit_jump_insn (gen_beq (operands[2]));
11410 (define_insn "stack_protect_testsi"
11411 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11412 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11413 (match_operand:SI 2 "memory_operand" "m,m")]
11415 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11416 (clobber (match_scratch:SI 3 "=&r,&r"))]
11419 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11420 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11421 [(set_attr "length" "16,20")])
11423 (define_insn "stack_protect_testdi"
11424 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11425 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11426 (match_operand:DI 2 "memory_operand" "m,m")]
11428 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11429 (clobber (match_scratch:DI 3 "=&r,&r"))]
11432 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11433 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11434 [(set_attr "length" "16,20")])
11437 ;; Here are the actual compare insns.
11438 (define_insn "*cmp<mode>_internal1"
11439 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11440 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11441 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11443 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
11444 [(set_attr "type" "cmp")])
11446 ;; If we are comparing a register for equality with a large constant,
11447 ;; we can do this with an XOR followed by a compare. But this is profitable
11448 ;; only if the large constant is only used for the comparison (and in this
11449 ;; case we already have a register to reuse as scratch).
11451 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11452 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11455 [(set (match_operand:SI 0 "register_operand")
11456 (match_operand:SI 1 "logical_const_operand" ""))
11457 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11459 (match_operand:SI 2 "logical_const_operand" "")]))
11460 (set (match_operand:CC 4 "cc_reg_operand" "")
11461 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11464 (if_then_else (match_operator 6 "equality_operator"
11465 [(match_dup 4) (const_int 0)])
11466 (match_operand 7 "" "")
11467 (match_operand 8 "" "")))]
11468 "peep2_reg_dead_p (3, operands[0])
11469 && peep2_reg_dead_p (4, operands[4])"
11470 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11471 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11472 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11475 /* Get the constant we are comparing against, and see what it looks like
11476 when sign-extended from 16 to 32 bits. Then see what constant we could
11477 XOR with SEXTC to get the sign-extended value. */
11478 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11480 operands[1], operands[2]);
11481 HOST_WIDE_INT c = INTVAL (cnst);
11482 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11483 HOST_WIDE_INT xorv = c ^ sextc;
11485 operands[9] = GEN_INT (xorv);
11486 operands[10] = GEN_INT (sextc);
11489 (define_insn "*cmpsi_internal2"
11490 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11491 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11492 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11494 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11495 [(set_attr "type" "cmp")])
11497 (define_insn "*cmpdi_internal2"
11498 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11499 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11500 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11502 "cmpld%I2 %0,%1,%b2"
11503 [(set_attr "type" "cmp")])
11505 ;; The following two insns don't exist as single insns, but if we provide
11506 ;; them, we can swap an add and compare, which will enable us to overlap more
11507 ;; of the required delay between a compare and branch. We generate code for
11508 ;; them by splitting.
11511 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11512 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11513 (match_operand:SI 2 "short_cint_operand" "i")))
11514 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11515 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11518 [(set_attr "length" "8")])
11521 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11522 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11523 (match_operand:SI 2 "u_short_cint_operand" "i")))
11524 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11525 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11528 [(set_attr "length" "8")])
11531 [(set (match_operand:CC 3 "cc_reg_operand" "")
11532 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11533 (match_operand:SI 2 "short_cint_operand" "")))
11534 (set (match_operand:SI 0 "gpc_reg_operand" "")
11535 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11537 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11538 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11541 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11542 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11543 (match_operand:SI 2 "u_short_cint_operand" "")))
11544 (set (match_operand:SI 0 "gpc_reg_operand" "")
11545 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11547 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11548 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11550 (define_insn "*cmpsf_internal1"
11551 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11552 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11553 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11554 "TARGET_HARD_FLOAT && TARGET_FPRS"
11556 [(set_attr "type" "fpcompare")])
11558 (define_insn "*cmpdf_internal1"
11559 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11560 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11561 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11562 "TARGET_HARD_FLOAT && TARGET_FPRS"
11564 [(set_attr "type" "fpcompare")])
11566 ;; Only need to compare second words if first words equal
11567 (define_insn "*cmptf_internal1"
11568 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11569 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11570 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11571 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11572 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11573 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11574 [(set_attr "type" "fpcompare")
11575 (set_attr "length" "12")])
11577 (define_insn_and_split "*cmptf_internal2"
11578 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11579 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11580 (match_operand:TF 2 "gpc_reg_operand" "f")))
11581 (clobber (match_scratch:DF 3 "=f"))
11582 (clobber (match_scratch:DF 4 "=f"))
11583 (clobber (match_scratch:DF 5 "=f"))
11584 (clobber (match_scratch:DF 6 "=f"))
11585 (clobber (match_scratch:DF 7 "=f"))
11586 (clobber (match_scratch:DF 8 "=f"))
11587 (clobber (match_scratch:DF 9 "=f"))
11588 (clobber (match_scratch:DF 10 "=f"))]
11589 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11590 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11592 "&& reload_completed"
11593 [(set (match_dup 3) (match_dup 13))
11594 (set (match_dup 4) (match_dup 14))
11595 (set (match_dup 9) (abs:DF (match_dup 5)))
11596 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11597 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11598 (label_ref (match_dup 11))
11600 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11601 (set (pc) (label_ref (match_dup 12)))
11603 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11604 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11605 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11606 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11609 REAL_VALUE_TYPE rv;
11610 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11611 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11613 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11614 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11615 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11616 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11617 operands[11] = gen_label_rtx ();
11618 operands[12] = gen_label_rtx ();
11620 operands[13] = force_const_mem (DFmode,
11621 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11622 operands[14] = force_const_mem (DFmode,
11623 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11627 operands[13] = gen_const_mem (DFmode,
11628 create_TOC_reference (XEXP (operands[13], 0)));
11629 operands[14] = gen_const_mem (DFmode,
11630 create_TOC_reference (XEXP (operands[14], 0)));
11631 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11632 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11636 ;; Now we have the scc insns. We can do some combinations because of the
11637 ;; way the machine works.
11639 ;; Note that this is probably faster if we can put an insn between the
11640 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11641 ;; cases the insns below which don't use an intermediate CR field will
11642 ;; be used instead.
11644 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11645 (match_operator:SI 1 "scc_comparison_operator"
11646 [(match_operand 2 "cc_reg_operand" "y")
11649 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11650 [(set (attr "type")
11651 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11652 (const_string "mfcrf")
11654 (const_string "mfcr")))
11655 (set_attr "length" "8")])
11657 ;; Same as above, but get the GT bit.
11658 (define_insn "move_from_CR_gt_bit"
11659 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11660 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11662 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
11663 [(set_attr "type" "mfcr")
11664 (set_attr "length" "8")])
11666 ;; Same as above, but get the OV/ORDERED bit.
11667 (define_insn "move_from_CR_ov_bit"
11668 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11669 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11671 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11672 [(set_attr "type" "mfcr")
11673 (set_attr "length" "8")])
11676 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11677 (match_operator:DI 1 "scc_comparison_operator"
11678 [(match_operand 2 "cc_reg_operand" "y")
11681 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11682 [(set (attr "type")
11683 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11684 (const_string "mfcrf")
11686 (const_string "mfcr")))
11687 (set_attr "length" "8")])
11690 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11691 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11692 [(match_operand 2 "cc_reg_operand" "y,y")
11695 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11696 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11699 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11701 [(set_attr "type" "delayed_compare")
11702 (set_attr "length" "8,16")])
11705 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11706 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11707 [(match_operand 2 "cc_reg_operand" "")
11710 (set (match_operand:SI 3 "gpc_reg_operand" "")
11711 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11712 "TARGET_32BIT && reload_completed"
11713 [(set (match_dup 3)
11714 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11716 (compare:CC (match_dup 3)
11721 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11722 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11723 [(match_operand 2 "cc_reg_operand" "y")
11725 (match_operand:SI 3 "const_int_operand" "n")))]
11729 int is_bit = ccr_bit (operands[1], 1);
11730 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11733 if (is_bit >= put_bit)
11734 count = is_bit - put_bit;
11736 count = 32 - (put_bit - is_bit);
11738 operands[4] = GEN_INT (count);
11739 operands[5] = GEN_INT (put_bit);
11741 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11743 [(set (attr "type")
11744 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11745 (const_string "mfcrf")
11747 (const_string "mfcr")))
11748 (set_attr "length" "8")])
11751 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11753 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11754 [(match_operand 2 "cc_reg_operand" "y,y")
11756 (match_operand:SI 3 "const_int_operand" "n,n"))
11758 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11759 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11764 int is_bit = ccr_bit (operands[1], 1);
11765 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11768 /* Force split for non-cc0 compare. */
11769 if (which_alternative == 1)
11772 if (is_bit >= put_bit)
11773 count = is_bit - put_bit;
11775 count = 32 - (put_bit - is_bit);
11777 operands[5] = GEN_INT (count);
11778 operands[6] = GEN_INT (put_bit);
11780 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11782 [(set_attr "type" "delayed_compare")
11783 (set_attr "length" "8,16")])
11786 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11788 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11789 [(match_operand 2 "cc_reg_operand" "")
11791 (match_operand:SI 3 "const_int_operand" ""))
11793 (set (match_operand:SI 4 "gpc_reg_operand" "")
11794 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11797 [(set (match_dup 4)
11798 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11801 (compare:CC (match_dup 4)
11805 ;; There is a 3 cycle delay between consecutive mfcr instructions
11806 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11809 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11810 (match_operator:SI 1 "scc_comparison_operator"
11811 [(match_operand 2 "cc_reg_operand" "y")
11813 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11814 (match_operator:SI 4 "scc_comparison_operator"
11815 [(match_operand 5 "cc_reg_operand" "y")
11817 "REGNO (operands[2]) != REGNO (operands[5])"
11818 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11819 [(set_attr "type" "mfcr")
11820 (set_attr "length" "12")])
11823 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11824 (match_operator:DI 1 "scc_comparison_operator"
11825 [(match_operand 2 "cc_reg_operand" "y")
11827 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11828 (match_operator:DI 4 "scc_comparison_operator"
11829 [(match_operand 5 "cc_reg_operand" "y")
11831 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11832 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11833 [(set_attr "type" "mfcr")
11834 (set_attr "length" "12")])
11836 ;; There are some scc insns that can be done directly, without a compare.
11837 ;; These are faster because they don't involve the communications between
11838 ;; the FXU and branch units. In fact, we will be replacing all of the
11839 ;; integer scc insns here or in the portable methods in emit_store_flag.
11841 ;; Also support (neg (scc ..)) since that construct is used to replace
11842 ;; branches, (plus (scc ..) ..) since that construct is common and
11843 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11844 ;; cases where it is no more expensive than (neg (scc ..)).
11846 ;; Have reload force a constant into a register for the simple insns that
11847 ;; otherwise won't accept constants. We do this because it is faster than
11848 ;; the cmp/mfcr sequence we would otherwise generate.
11850 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11853 (define_insn_and_split "*eq<mode>"
11854 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11855 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11856 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
11860 [(set (match_dup 0)
11861 (clz:GPR (match_dup 3)))
11863 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
11865 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11867 /* Use output operand as intermediate. */
11868 operands[3] = operands[0];
11870 if (logical_operand (operands[2], <MODE>mode))
11871 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11872 gen_rtx_XOR (<MODE>mode,
11873 operands[1], operands[2])));
11875 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11876 gen_rtx_PLUS (<MODE>mode, operands[1],
11877 negate_rtx (<MODE>mode,
11881 operands[3] = operands[1];
11883 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11886 (define_insn_and_split "*eq<mode>_compare"
11887 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11889 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
11890 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
11892 (set (match_operand:P 0 "gpc_reg_operand" "=r")
11893 (eq:P (match_dup 1) (match_dup 2)))]
11894 "!TARGET_POWER && optimize_size"
11896 "!TARGET_POWER && optimize_size"
11897 [(set (match_dup 0)
11898 (clz:P (match_dup 4)))
11899 (parallel [(set (match_dup 3)
11900 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
11903 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
11905 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11907 /* Use output operand as intermediate. */
11908 operands[4] = operands[0];
11910 if (logical_operand (operands[2], <MODE>mode))
11911 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11912 gen_rtx_XOR (<MODE>mode,
11913 operands[1], operands[2])));
11915 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11916 gen_rtx_PLUS (<MODE>mode, operands[1],
11917 negate_rtx (<MODE>mode,
11921 operands[4] = operands[1];
11923 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11926 (define_insn "*eqsi_power"
11927 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11928 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11929 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11930 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11933 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11934 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11935 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11936 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11937 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11938 [(set_attr "type" "three,two,three,three,three")
11939 (set_attr "length" "12,8,12,12,12")])
11941 ;; We have insns of the form shown by the first define_insn below. If
11942 ;; there is something inside the comparison operation, we must split it.
11944 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11945 (plus:SI (match_operator 1 "comparison_operator"
11946 [(match_operand:SI 2 "" "")
11947 (match_operand:SI 3
11948 "reg_or_cint_operand" "")])
11949 (match_operand:SI 4 "gpc_reg_operand" "")))
11950 (clobber (match_operand:SI 5 "register_operand" ""))]
11951 "! gpc_reg_operand (operands[2], SImode)"
11952 [(set (match_dup 5) (match_dup 2))
11953 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11956 (define_insn "*plus_eqsi"
11957 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11958 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11959 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
11960 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11963 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11964 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11965 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11966 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11967 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11968 [(set_attr "type" "three,two,three,three,three")
11969 (set_attr "length" "12,8,12,12,12")])
11971 (define_insn "*compare_plus_eqsi"
11972 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11975 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11976 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11977 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11979 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11980 "TARGET_32BIT && optimize_size"
11982 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11983 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11984 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11985 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11986 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11992 [(set_attr "type" "compare")
11993 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11996 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11999 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12000 (match_operand:SI 2 "scc_eq_operand" ""))
12001 (match_operand:SI 3 "gpc_reg_operand" ""))
12003 (clobber (match_scratch:SI 4 ""))]
12004 "TARGET_32BIT && optimize_size && reload_completed"
12005 [(set (match_dup 4)
12006 (plus:SI (eq:SI (match_dup 1)
12010 (compare:CC (match_dup 4)
12014 (define_insn "*plus_eqsi_compare"
12015 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12018 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12019 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12020 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12022 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12023 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12024 "TARGET_32BIT && optimize_size"
12026 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12027 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12028 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12029 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12030 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12036 [(set_attr "type" "compare")
12037 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12040 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12043 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12044 (match_operand:SI 2 "scc_eq_operand" ""))
12045 (match_operand:SI 3 "gpc_reg_operand" ""))
12047 (set (match_operand:SI 0 "gpc_reg_operand" "")
12048 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12049 "TARGET_32BIT && optimize_size && reload_completed"
12050 [(set (match_dup 0)
12051 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12053 (compare:CC (match_dup 0)
12057 (define_insn "*neg_eq0<mode>"
12058 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12059 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12062 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12063 [(set_attr "type" "two")
12064 (set_attr "length" "8")])
12066 (define_insn_and_split "*neg_eq<mode>"
12067 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12068 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12069 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12073 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12075 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12077 /* Use output operand as intermediate. */
12078 operands[3] = operands[0];
12080 if (logical_operand (operands[2], <MODE>mode))
12081 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12082 gen_rtx_XOR (<MODE>mode,
12083 operands[1], operands[2])));
12085 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12086 gen_rtx_PLUS (<MODE>mode, operands[1],
12087 negate_rtx (<MODE>mode,
12091 operands[3] = operands[1];
12094 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12095 ;; since it nabs/sr is just as fast.
12096 (define_insn "*ne0si"
12097 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12098 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12100 (clobber (match_scratch:SI 2 "=&r"))]
12101 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12102 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12103 [(set_attr "type" "two")
12104 (set_attr "length" "8")])
12106 (define_insn "*ne0di"
12107 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12108 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12110 (clobber (match_scratch:DI 2 "=&r"))]
12112 "addic %2,%1,-1\;subfe %0,%2,%1"
12113 [(set_attr "type" "two")
12114 (set_attr "length" "8")])
12116 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12117 (define_insn "*plus_ne0si"
12118 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12119 (plus:SI (lshiftrt:SI
12120 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12122 (match_operand:SI 2 "gpc_reg_operand" "r")))
12123 (clobber (match_scratch:SI 3 "=&r"))]
12125 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12126 [(set_attr "type" "two")
12127 (set_attr "length" "8")])
12129 (define_insn "*plus_ne0di"
12130 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12131 (plus:DI (lshiftrt:DI
12132 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12134 (match_operand:DI 2 "gpc_reg_operand" "r")))
12135 (clobber (match_scratch:DI 3 "=&r"))]
12137 "addic %3,%1,-1\;addze %0,%2"
12138 [(set_attr "type" "two")
12139 (set_attr "length" "8")])
12141 (define_insn "*compare_plus_ne0si"
12142 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12144 (plus:SI (lshiftrt:SI
12145 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12147 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12149 (clobber (match_scratch:SI 3 "=&r,&r"))
12150 (clobber (match_scratch:SI 4 "=X,&r"))]
12153 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12155 [(set_attr "type" "compare")
12156 (set_attr "length" "8,12")])
12159 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12161 (plus:SI (lshiftrt:SI
12162 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12164 (match_operand:SI 2 "gpc_reg_operand" ""))
12166 (clobber (match_scratch:SI 3 ""))
12167 (clobber (match_scratch:SI 4 ""))]
12168 "TARGET_32BIT && reload_completed"
12169 [(parallel [(set (match_dup 3)
12170 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12173 (clobber (match_dup 4))])
12175 (compare:CC (match_dup 3)
12179 (define_insn "*compare_plus_ne0di"
12180 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12182 (plus:DI (lshiftrt:DI
12183 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12185 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12187 (clobber (match_scratch:DI 3 "=&r,&r"))]
12190 addic %3,%1,-1\;addze. %3,%2
12192 [(set_attr "type" "compare")
12193 (set_attr "length" "8,12")])
12196 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12198 (plus:DI (lshiftrt:DI
12199 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12201 (match_operand:DI 2 "gpc_reg_operand" ""))
12203 (clobber (match_scratch:DI 3 ""))]
12204 "TARGET_64BIT && reload_completed"
12205 [(set (match_dup 3)
12206 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12210 (compare:CC (match_dup 3)
12214 (define_insn "*plus_ne0si_compare"
12215 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12217 (plus:SI (lshiftrt:SI
12218 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12220 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12222 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12223 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12225 (clobber (match_scratch:SI 3 "=&r,&r"))]
12228 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12230 [(set_attr "type" "compare")
12231 (set_attr "length" "8,12")])
12234 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12236 (plus:SI (lshiftrt:SI
12237 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12239 (match_operand:SI 2 "gpc_reg_operand" ""))
12241 (set (match_operand:SI 0 "gpc_reg_operand" "")
12242 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12244 (clobber (match_scratch:SI 3 ""))]
12245 "TARGET_32BIT && reload_completed"
12246 [(parallel [(set (match_dup 0)
12247 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12249 (clobber (match_dup 3))])
12251 (compare:CC (match_dup 0)
12255 (define_insn "*plus_ne0di_compare"
12256 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12258 (plus:DI (lshiftrt:DI
12259 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12261 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12263 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12264 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12266 (clobber (match_scratch:DI 3 "=&r,&r"))]
12269 addic %3,%1,-1\;addze. %0,%2
12271 [(set_attr "type" "compare")
12272 (set_attr "length" "8,12")])
12275 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12277 (plus:DI (lshiftrt:DI
12278 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12280 (match_operand:DI 2 "gpc_reg_operand" ""))
12282 (set (match_operand:DI 0 "gpc_reg_operand" "")
12283 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12285 (clobber (match_scratch:DI 3 ""))]
12286 "TARGET_64BIT && reload_completed"
12287 [(parallel [(set (match_dup 0)
12288 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12290 (clobber (match_dup 3))])
12292 (compare:CC (match_dup 0)
12297 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12298 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12299 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12300 (clobber (match_scratch:SI 3 "=r,X"))]
12303 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12304 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12305 [(set_attr "length" "12")])
12308 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12310 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12311 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12313 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12314 (le:SI (match_dup 1) (match_dup 2)))
12315 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12318 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12319 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12322 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12323 (set_attr "length" "12,12,16,16")])
12326 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12328 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12329 (match_operand:SI 2 "reg_or_short_operand" ""))
12331 (set (match_operand:SI 0 "gpc_reg_operand" "")
12332 (le:SI (match_dup 1) (match_dup 2)))
12333 (clobber (match_scratch:SI 3 ""))]
12334 "TARGET_POWER && reload_completed"
12335 [(parallel [(set (match_dup 0)
12336 (le:SI (match_dup 1) (match_dup 2)))
12337 (clobber (match_dup 3))])
12339 (compare:CC (match_dup 0)
12344 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12345 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12346 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12347 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12350 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12351 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12352 [(set_attr "length" "12")])
12355 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12357 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12358 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12359 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12361 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12364 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12365 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12368 [(set_attr "type" "compare")
12369 (set_attr "length" "12,12,16,16")])
12372 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12374 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12375 (match_operand:SI 2 "reg_or_short_operand" ""))
12376 (match_operand:SI 3 "gpc_reg_operand" ""))
12378 (clobber (match_scratch:SI 4 ""))]
12379 "TARGET_POWER && reload_completed"
12380 [(set (match_dup 4)
12381 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12384 (compare:CC (match_dup 4)
12389 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12391 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12392 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12393 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12395 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12396 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12399 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12400 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12403 [(set_attr "type" "compare")
12404 (set_attr "length" "12,12,16,16")])
12407 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12409 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12410 (match_operand:SI 2 "reg_or_short_operand" ""))
12411 (match_operand:SI 3 "gpc_reg_operand" ""))
12413 (set (match_operand:SI 0 "gpc_reg_operand" "")
12414 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12415 "TARGET_POWER && reload_completed"
12416 [(set (match_dup 0)
12417 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12419 (compare:CC (match_dup 0)
12424 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12425 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12426 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12429 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12430 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12431 [(set_attr "length" "12")])
12433 (define_insn "*leu<mode>"
12434 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12435 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12436 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12438 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12439 [(set_attr "type" "three")
12440 (set_attr "length" "12")])
12442 (define_insn "*leu<mode>_compare"
12443 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12445 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12446 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12448 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12449 (leu:P (match_dup 1) (match_dup 2)))]
12452 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12454 [(set_attr "type" "compare")
12455 (set_attr "length" "12,16")])
12458 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12460 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12461 (match_operand:P 2 "reg_or_short_operand" ""))
12463 (set (match_operand:P 0 "gpc_reg_operand" "")
12464 (leu:P (match_dup 1) (match_dup 2)))]
12466 [(set (match_dup 0)
12467 (leu:P (match_dup 1) (match_dup 2)))
12469 (compare:CC (match_dup 0)
12473 (define_insn "*plus_leu<mode>"
12474 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12475 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12476 (match_operand:P 2 "reg_or_short_operand" "rI"))
12477 (match_operand:P 3 "gpc_reg_operand" "r")))]
12479 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12480 [(set_attr "type" "two")
12481 (set_attr "length" "8")])
12484 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12486 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12487 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12488 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12490 (clobber (match_scratch:SI 4 "=&r,&r"))]
12493 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12495 [(set_attr "type" "compare")
12496 (set_attr "length" "8,12")])
12499 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12501 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12502 (match_operand:SI 2 "reg_or_short_operand" ""))
12503 (match_operand:SI 3 "gpc_reg_operand" ""))
12505 (clobber (match_scratch:SI 4 ""))]
12506 "TARGET_32BIT && reload_completed"
12507 [(set (match_dup 4)
12508 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12511 (compare:CC (match_dup 4)
12516 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12518 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12519 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12520 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12522 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12523 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12526 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12528 [(set_attr "type" "compare")
12529 (set_attr "length" "8,12")])
12532 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12534 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12535 (match_operand:SI 2 "reg_or_short_operand" ""))
12536 (match_operand:SI 3 "gpc_reg_operand" ""))
12538 (set (match_operand:SI 0 "gpc_reg_operand" "")
12539 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12540 "TARGET_32BIT && reload_completed"
12541 [(set (match_dup 0)
12542 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12544 (compare:CC (match_dup 0)
12548 (define_insn "*neg_leu<mode>"
12549 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12550 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12551 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12553 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12554 [(set_attr "type" "three")
12555 (set_attr "length" "12")])
12557 (define_insn "*and_neg_leu<mode>"
12558 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12560 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12561 (match_operand:P 2 "reg_or_short_operand" "rI")))
12562 (match_operand:P 3 "gpc_reg_operand" "r")))]
12564 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12565 [(set_attr "type" "three")
12566 (set_attr "length" "12")])
12569 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12572 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12573 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12574 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12576 (clobber (match_scratch:SI 4 "=&r,&r"))]
12579 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12581 [(set_attr "type" "compare")
12582 (set_attr "length" "12,16")])
12585 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12588 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12589 (match_operand:SI 2 "reg_or_short_operand" "")))
12590 (match_operand:SI 3 "gpc_reg_operand" ""))
12592 (clobber (match_scratch:SI 4 ""))]
12593 "TARGET_32BIT && reload_completed"
12594 [(set (match_dup 4)
12595 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12598 (compare:CC (match_dup 4)
12603 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12606 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12607 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12608 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12610 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12611 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12614 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12616 [(set_attr "type" "compare")
12617 (set_attr "length" "12,16")])
12620 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12623 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12624 (match_operand:SI 2 "reg_or_short_operand" "")))
12625 (match_operand:SI 3 "gpc_reg_operand" ""))
12627 (set (match_operand:SI 0 "gpc_reg_operand" "")
12628 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12629 "TARGET_32BIT && reload_completed"
12630 [(set (match_dup 0)
12631 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12634 (compare:CC (match_dup 0)
12639 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12640 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12641 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12643 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12644 [(set_attr "length" "12")])
12647 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12649 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12650 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12652 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12653 (lt:SI (match_dup 1) (match_dup 2)))]
12656 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12658 [(set_attr "type" "delayed_compare")
12659 (set_attr "length" "12,16")])
12662 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12664 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12665 (match_operand:SI 2 "reg_or_short_operand" ""))
12667 (set (match_operand:SI 0 "gpc_reg_operand" "")
12668 (lt:SI (match_dup 1) (match_dup 2)))]
12669 "TARGET_POWER && reload_completed"
12670 [(set (match_dup 0)
12671 (lt:SI (match_dup 1) (match_dup 2)))
12673 (compare:CC (match_dup 0)
12678 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12679 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12680 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12681 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12683 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12684 [(set_attr "length" "12")])
12687 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12689 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12690 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12691 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12693 (clobber (match_scratch:SI 4 "=&r,&r"))]
12696 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12698 [(set_attr "type" "compare")
12699 (set_attr "length" "12,16")])
12702 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12704 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12705 (match_operand:SI 2 "reg_or_short_operand" ""))
12706 (match_operand:SI 3 "gpc_reg_operand" ""))
12708 (clobber (match_scratch:SI 4 ""))]
12709 "TARGET_POWER && reload_completed"
12710 [(set (match_dup 4)
12711 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12714 (compare:CC (match_dup 4)
12719 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12721 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12722 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12723 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12725 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12726 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12729 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12731 [(set_attr "type" "compare")
12732 (set_attr "length" "12,16")])
12735 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12737 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12738 (match_operand:SI 2 "reg_or_short_operand" ""))
12739 (match_operand:SI 3 "gpc_reg_operand" ""))
12741 (set (match_operand:SI 0 "gpc_reg_operand" "")
12742 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12743 "TARGET_POWER && reload_completed"
12744 [(set (match_dup 0)
12745 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12747 (compare:CC (match_dup 0)
12752 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12753 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12754 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12756 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12757 [(set_attr "length" "12")])
12759 (define_insn_and_split "*ltu<mode>"
12760 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12761 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12762 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12766 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12767 (set (match_dup 0) (neg:P (match_dup 0)))]
12770 (define_insn_and_split "*ltu<mode>_compare"
12771 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12773 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12774 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12776 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12777 (ltu:P (match_dup 1) (match_dup 2)))]
12781 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12782 (parallel [(set (match_dup 3)
12783 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12784 (set (match_dup 0) (neg:P (match_dup 0)))])]
12787 (define_insn_and_split "*plus_ltu<mode>"
12788 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12789 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12790 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12791 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12794 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12795 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12796 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12799 (define_insn_and_split "*plus_ltu<mode>_compare"
12800 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12802 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12803 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12804 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12806 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12807 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12810 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12811 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12812 (parallel [(set (match_dup 4)
12813 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12815 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12818 (define_insn "*neg_ltu<mode>"
12819 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12820 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12821 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12824 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12825 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12826 [(set_attr "type" "two")
12827 (set_attr "length" "8")])
12830 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12831 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12832 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12833 (clobber (match_scratch:SI 3 "=r"))]
12835 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12836 [(set_attr "length" "12")])
12839 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12841 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12842 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12844 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12845 (ge:SI (match_dup 1) (match_dup 2)))
12846 (clobber (match_scratch:SI 3 "=r,r"))]
12849 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12851 [(set_attr "type" "compare")
12852 (set_attr "length" "12,16")])
12855 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12857 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12858 (match_operand:SI 2 "reg_or_short_operand" ""))
12860 (set (match_operand:SI 0 "gpc_reg_operand" "")
12861 (ge:SI (match_dup 1) (match_dup 2)))
12862 (clobber (match_scratch:SI 3 ""))]
12863 "TARGET_POWER && reload_completed"
12864 [(parallel [(set (match_dup 0)
12865 (ge:SI (match_dup 1) (match_dup 2)))
12866 (clobber (match_dup 3))])
12868 (compare:CC (match_dup 0)
12873 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12874 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12875 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12876 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12878 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12879 [(set_attr "length" "12")])
12882 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12884 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12885 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12886 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12888 (clobber (match_scratch:SI 4 "=&r,&r"))]
12891 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12893 [(set_attr "type" "compare")
12894 (set_attr "length" "12,16")])
12897 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12899 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12900 (match_operand:SI 2 "reg_or_short_operand" ""))
12901 (match_operand:SI 3 "gpc_reg_operand" ""))
12903 (clobber (match_scratch:SI 4 ""))]
12904 "TARGET_POWER && reload_completed"
12905 [(set (match_dup 4)
12906 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12909 (compare:CC (match_dup 4)
12914 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12916 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12917 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12918 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12920 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12921 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12924 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12926 [(set_attr "type" "compare")
12927 (set_attr "length" "12,16")])
12930 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12932 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12933 (match_operand:SI 2 "reg_or_short_operand" ""))
12934 (match_operand:SI 3 "gpc_reg_operand" ""))
12936 (set (match_operand:SI 0 "gpc_reg_operand" "")
12937 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12938 "TARGET_POWER && reload_completed"
12939 [(set (match_dup 0)
12940 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12942 (compare:CC (match_dup 0)
12947 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12948 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12949 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12951 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12952 [(set_attr "length" "12")])
12954 (define_insn "*geu<mode>"
12955 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12956 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12957 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12960 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12961 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12962 [(set_attr "type" "three")
12963 (set_attr "length" "12")])
12965 (define_insn "*geu<mode>_compare"
12966 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12968 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12969 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12971 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12972 (geu:P (match_dup 1) (match_dup 2)))]
12975 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12976 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12979 [(set_attr "type" "compare")
12980 (set_attr "length" "12,12,16,16")])
12983 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12985 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12986 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12988 (set (match_operand:P 0 "gpc_reg_operand" "")
12989 (geu:P (match_dup 1) (match_dup 2)))]
12991 [(set (match_dup 0)
12992 (geu:P (match_dup 1) (match_dup 2)))
12994 (compare:CC (match_dup 0)
12998 (define_insn "*plus_geu<mode>"
12999 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13000 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13001 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13002 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13005 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13006 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13007 [(set_attr "type" "two")
13008 (set_attr "length" "8")])
13011 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13013 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13014 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13015 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13017 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13020 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13021 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13024 [(set_attr "type" "compare")
13025 (set_attr "length" "8,8,12,12")])
13028 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13030 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13031 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13032 (match_operand:SI 3 "gpc_reg_operand" ""))
13034 (clobber (match_scratch:SI 4 ""))]
13035 "TARGET_32BIT && reload_completed"
13036 [(set (match_dup 4)
13037 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13040 (compare:CC (match_dup 4)
13045 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13047 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13048 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13049 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13051 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13052 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13055 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13056 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13059 [(set_attr "type" "compare")
13060 (set_attr "length" "8,8,12,12")])
13063 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13065 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13066 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13067 (match_operand:SI 3 "gpc_reg_operand" ""))
13069 (set (match_operand:SI 0 "gpc_reg_operand" "")
13070 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13071 "TARGET_32BIT && reload_completed"
13072 [(set (match_dup 0)
13073 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13075 (compare:CC (match_dup 0)
13079 (define_insn "*neg_geu<mode>"
13080 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13081 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13082 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13085 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13086 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13087 [(set_attr "type" "three")
13088 (set_attr "length" "12")])
13090 (define_insn "*and_neg_geu<mode>"
13091 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13093 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13094 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13095 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13098 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13099 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13100 [(set_attr "type" "three")
13101 (set_attr "length" "12")])
13104 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13107 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13108 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13109 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13111 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13114 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13115 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13118 [(set_attr "type" "compare")
13119 (set_attr "length" "12,12,16,16")])
13122 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13125 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13126 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13127 (match_operand:SI 3 "gpc_reg_operand" ""))
13129 (clobber (match_scratch:SI 4 ""))]
13130 "TARGET_32BIT && reload_completed"
13131 [(set (match_dup 4)
13132 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13135 (compare:CC (match_dup 4)
13140 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13143 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13144 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13145 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13147 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13148 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13151 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13152 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13155 [(set_attr "type" "compare")
13156 (set_attr "length" "12,12,16,16")])
13159 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13162 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13163 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13164 (match_operand:SI 3 "gpc_reg_operand" ""))
13166 (set (match_operand:SI 0 "gpc_reg_operand" "")
13167 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13168 "TARGET_32BIT && reload_completed"
13169 [(set (match_dup 0)
13170 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13172 (compare:CC (match_dup 0)
13177 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13178 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13179 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13181 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13182 [(set_attr "length" "12")])
13185 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13187 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13188 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13190 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13191 (gt:SI (match_dup 1) (match_dup 2)))]
13194 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13196 [(set_attr "type" "delayed_compare")
13197 (set_attr "length" "12,16")])
13200 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13202 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13203 (match_operand:SI 2 "reg_or_short_operand" ""))
13205 (set (match_operand:SI 0 "gpc_reg_operand" "")
13206 (gt:SI (match_dup 1) (match_dup 2)))]
13207 "TARGET_POWER && reload_completed"
13208 [(set (match_dup 0)
13209 (gt:SI (match_dup 1) (match_dup 2)))
13211 (compare:CC (match_dup 0)
13215 (define_insn "*plus_gt0<mode>"
13216 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13217 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13219 (match_operand:P 2 "gpc_reg_operand" "r")))]
13221 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13222 [(set_attr "type" "three")
13223 (set_attr "length" "12")])
13226 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13228 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13230 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13232 (clobber (match_scratch:SI 3 "=&r,&r"))]
13235 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13237 [(set_attr "type" "compare")
13238 (set_attr "length" "12,16")])
13241 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13243 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13245 (match_operand:SI 2 "gpc_reg_operand" ""))
13247 (clobber (match_scratch:SI 3 ""))]
13248 "TARGET_32BIT && reload_completed"
13249 [(set (match_dup 3)
13250 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13253 (compare:CC (match_dup 3)
13258 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13260 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13262 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13264 (clobber (match_scratch:DI 3 "=&r,&r"))]
13267 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13269 [(set_attr "type" "compare")
13270 (set_attr "length" "12,16")])
13273 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13275 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13277 (match_operand:DI 2 "gpc_reg_operand" ""))
13279 (clobber (match_scratch:DI 3 ""))]
13280 "TARGET_64BIT && reload_completed"
13281 [(set (match_dup 3)
13282 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13285 (compare:CC (match_dup 3)
13290 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13292 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13294 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13296 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13297 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13300 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13302 [(set_attr "type" "compare")
13303 (set_attr "length" "12,16")])
13306 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13308 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13310 (match_operand:SI 2 "gpc_reg_operand" ""))
13312 (set (match_operand:SI 0 "gpc_reg_operand" "")
13313 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13314 "TARGET_32BIT && reload_completed"
13315 [(set (match_dup 0)
13316 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13318 (compare:CC (match_dup 0)
13323 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13325 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13327 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13329 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13330 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13333 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13335 [(set_attr "type" "compare")
13336 (set_attr "length" "12,16")])
13339 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13341 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13343 (match_operand:DI 2 "gpc_reg_operand" ""))
13345 (set (match_operand:DI 0 "gpc_reg_operand" "")
13346 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13347 "TARGET_64BIT && reload_completed"
13348 [(set (match_dup 0)
13349 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13351 (compare:CC (match_dup 0)
13356 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13357 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13358 (match_operand:SI 2 "reg_or_short_operand" "r"))
13359 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13361 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13362 [(set_attr "length" "12")])
13365 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13367 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13368 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13369 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13371 (clobber (match_scratch:SI 4 "=&r,&r"))]
13374 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13376 [(set_attr "type" "compare")
13377 (set_attr "length" "12,16")])
13380 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13382 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13383 (match_operand:SI 2 "reg_or_short_operand" ""))
13384 (match_operand:SI 3 "gpc_reg_operand" ""))
13386 (clobber (match_scratch:SI 4 ""))]
13387 "TARGET_POWER && reload_completed"
13388 [(set (match_dup 4)
13389 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13391 (compare:CC (match_dup 4)
13396 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13398 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13399 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13400 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13402 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13403 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13406 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13408 [(set_attr "type" "compare")
13409 (set_attr "length" "12,16")])
13412 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13414 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13415 (match_operand:SI 2 "reg_or_short_operand" ""))
13416 (match_operand:SI 3 "gpc_reg_operand" ""))
13418 (set (match_operand:SI 0 "gpc_reg_operand" "")
13419 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13420 "TARGET_POWER && reload_completed"
13421 [(set (match_dup 0)
13422 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13424 (compare:CC (match_dup 0)
13429 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13430 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13431 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13433 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13434 [(set_attr "length" "12")])
13436 (define_insn_and_split "*gtu<mode>"
13437 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13438 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13439 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13443 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13444 (set (match_dup 0) (neg:P (match_dup 0)))]
13447 (define_insn_and_split "*gtu<mode>_compare"
13448 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13450 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13451 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13453 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13454 (gtu:P (match_dup 1) (match_dup 2)))]
13458 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13459 (parallel [(set (match_dup 3)
13460 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13461 (set (match_dup 0) (neg:P (match_dup 0)))])]
13464 (define_insn_and_split "*plus_gtu<mode>"
13465 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13466 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13467 (match_operand:P 2 "reg_or_short_operand" "rI"))
13468 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13471 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13472 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13473 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13476 (define_insn_and_split "*plus_gtu<mode>_compare"
13477 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13479 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13480 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13481 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13483 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13484 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13487 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13488 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13489 (parallel [(set (match_dup 4)
13490 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13492 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13495 (define_insn "*neg_gtu<mode>"
13496 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13497 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13498 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13500 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13501 [(set_attr "type" "two")
13502 (set_attr "length" "8")])
13505 ;; Define both directions of branch and return. If we need a reload
13506 ;; register, we'd rather use CR0 since it is much easier to copy a
13507 ;; register CC value to there.
13511 (if_then_else (match_operator 1 "branch_comparison_operator"
13513 "cc_reg_operand" "y")
13515 (label_ref (match_operand 0 "" ""))
13520 return output_cbranch (operands[1], \"%l0\", 0, insn);
13522 [(set_attr "type" "branch")])
13526 (if_then_else (match_operator 0 "branch_comparison_operator"
13528 "cc_reg_operand" "y")
13535 return output_cbranch (operands[0], NULL, 0, insn);
13537 [(set_attr "type" "jmpreg")
13538 (set_attr "length" "4")])
13542 (if_then_else (match_operator 1 "branch_comparison_operator"
13544 "cc_reg_operand" "y")
13547 (label_ref (match_operand 0 "" ""))))]
13551 return output_cbranch (operands[1], \"%l0\", 1, insn);
13553 [(set_attr "type" "branch")])
13557 (if_then_else (match_operator 0 "branch_comparison_operator"
13559 "cc_reg_operand" "y")
13566 return output_cbranch (operands[0], NULL, 1, insn);
13568 [(set_attr "type" "jmpreg")
13569 (set_attr "length" "4")])
13571 ;; Logic on condition register values.
13573 ; This pattern matches things like
13574 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13575 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13577 ; which are generated by the branch logic.
13578 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13580 (define_insn "*cceq_ior_compare"
13581 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13582 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13583 [(match_operator:SI 2
13584 "branch_positive_comparison_operator"
13586 "cc_reg_operand" "y,y")
13588 (match_operator:SI 4
13589 "branch_positive_comparison_operator"
13591 "cc_reg_operand" "0,y")
13595 "cr%q1 %E0,%j2,%j4"
13596 [(set_attr "type" "cr_logical,delayed_cr")])
13598 ; Why is the constant -1 here, but 1 in the previous pattern?
13599 ; Because ~1 has all but the low bit set.
13601 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13602 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13603 [(not:SI (match_operator:SI 2
13604 "branch_positive_comparison_operator"
13606 "cc_reg_operand" "y,y")
13608 (match_operator:SI 4
13609 "branch_positive_comparison_operator"
13611 "cc_reg_operand" "0,y")
13615 "cr%q1 %E0,%j2,%j4"
13616 [(set_attr "type" "cr_logical,delayed_cr")])
13618 (define_insn "*cceq_rev_compare"
13619 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13620 (compare:CCEQ (match_operator:SI 1
13621 "branch_positive_comparison_operator"
13623 "cc_reg_operand" "0,y")
13627 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13628 [(set_attr "type" "cr_logical,delayed_cr")])
13630 ;; If we are comparing the result of two comparisons, this can be done
13631 ;; using creqv or crxor.
13633 (define_insn_and_split ""
13634 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13635 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13636 [(match_operand 2 "cc_reg_operand" "y")
13638 (match_operator 3 "branch_comparison_operator"
13639 [(match_operand 4 "cc_reg_operand" "y")
13644 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13648 int positive_1, positive_2;
13650 positive_1 = branch_positive_comparison_operator (operands[1],
13651 GET_MODE (operands[1]));
13652 positive_2 = branch_positive_comparison_operator (operands[3],
13653 GET_MODE (operands[3]));
13656 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13657 GET_CODE (operands[1])),
13659 operands[2], const0_rtx);
13660 else if (GET_MODE (operands[1]) != SImode)
13661 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13662 operands[2], const0_rtx);
13665 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13666 GET_CODE (operands[3])),
13668 operands[4], const0_rtx);
13669 else if (GET_MODE (operands[3]) != SImode)
13670 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13671 operands[4], const0_rtx);
13673 if (positive_1 == positive_2)
13675 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13676 operands[5] = constm1_rtx;
13680 operands[5] = const1_rtx;
13684 ;; Unconditional branch and return.
13686 (define_insn "jump"
13688 (label_ref (match_operand 0 "" "")))]
13691 [(set_attr "type" "branch")])
13693 (define_insn "return"
13697 [(set_attr "type" "jmpreg")])
13699 (define_expand "indirect_jump"
13700 [(set (pc) (match_operand 0 "register_operand" ""))])
13702 (define_insn "*indirect_jump<mode>"
13703 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13708 [(set_attr "type" "jmpreg")])
13710 ;; Table jump for switch statements:
13711 (define_expand "tablejump"
13712 [(use (match_operand 0 "" ""))
13713 (use (label_ref (match_operand 1 "" "")))]
13718 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13720 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13724 (define_expand "tablejumpsi"
13725 [(set (match_dup 3)
13726 (plus:SI (match_operand:SI 0 "" "")
13728 (parallel [(set (pc) (match_dup 3))
13729 (use (label_ref (match_operand 1 "" "")))])]
13732 { operands[0] = force_reg (SImode, operands[0]);
13733 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13734 operands[3] = gen_reg_rtx (SImode);
13737 (define_expand "tablejumpdi"
13738 [(set (match_dup 4)
13739 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13741 (plus:DI (match_dup 4)
13743 (parallel [(set (pc) (match_dup 3))
13744 (use (label_ref (match_operand 1 "" "")))])]
13747 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13748 operands[3] = gen_reg_rtx (DImode);
13749 operands[4] = gen_reg_rtx (DImode);
13752 (define_insn "*tablejump<mode>_internal1"
13754 (match_operand:P 0 "register_operand" "c,*l"))
13755 (use (label_ref (match_operand 1 "" "")))]
13760 [(set_attr "type" "jmpreg")])
13765 "{cror 0,0,0|nop}")
13767 ;; Define the subtract-one-and-jump insns, starting with the template
13768 ;; so loop.c knows what to generate.
13770 (define_expand "doloop_end"
13771 [(use (match_operand 0 "" "")) ; loop pseudo
13772 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13773 (use (match_operand 2 "" "")) ; max iterations
13774 (use (match_operand 3 "" "")) ; loop level
13775 (use (match_operand 4 "" ""))] ; label
13779 /* Only use this on innermost loops. */
13780 if (INTVAL (operands[3]) > 1)
13784 if (GET_MODE (operands[0]) != DImode)
13786 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13790 if (GET_MODE (operands[0]) != SImode)
13792 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13797 (define_expand "ctr<mode>"
13798 [(parallel [(set (pc)
13799 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13801 (label_ref (match_operand 1 "" ""))
13804 (plus:P (match_dup 0)
13806 (clobber (match_scratch:CC 2 ""))
13807 (clobber (match_scratch:P 3 ""))])]
13811 ;; We need to be able to do this for any operand, including MEM, or we
13812 ;; will cause reload to blow up since we don't allow output reloads on
13814 ;; For the length attribute to be calculated correctly, the
13815 ;; label MUST be operand 0.
13817 (define_insn "*ctr<mode>_internal1"
13819 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13821 (label_ref (match_operand 0 "" ""))
13823 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13824 (plus:P (match_dup 1)
13826 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13827 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13831 if (which_alternative != 0)
13833 else if (get_attr_length (insn) == 4)
13834 return \"{bdn|bdnz} %l0\";
13836 return \"bdz $+8\;b %l0\";
13838 [(set_attr "type" "branch")
13839 (set_attr "length" "*,12,16,16")])
13841 (define_insn "*ctr<mode>_internal2"
13843 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13846 (label_ref (match_operand 0 "" ""))))
13847 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13848 (plus:P (match_dup 1)
13850 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13851 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13855 if (which_alternative != 0)
13857 else if (get_attr_length (insn) == 4)
13858 return \"bdz %l0\";
13860 return \"{bdn|bdnz} $+8\;b %l0\";
13862 [(set_attr "type" "branch")
13863 (set_attr "length" "*,12,16,16")])
13865 ;; Similar but use EQ
13867 (define_insn "*ctr<mode>_internal5"
13869 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13871 (label_ref (match_operand 0 "" ""))
13873 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13874 (plus:P (match_dup 1)
13876 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13877 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13881 if (which_alternative != 0)
13883 else if (get_attr_length (insn) == 4)
13884 return \"bdz %l0\";
13886 return \"{bdn|bdnz} $+8\;b %l0\";
13888 [(set_attr "type" "branch")
13889 (set_attr "length" "*,12,16,16")])
13891 (define_insn "*ctr<mode>_internal6"
13893 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13896 (label_ref (match_operand 0 "" ""))))
13897 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13898 (plus:P (match_dup 1)
13900 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13901 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13905 if (which_alternative != 0)
13907 else if (get_attr_length (insn) == 4)
13908 return \"{bdn|bdnz} %l0\";
13910 return \"bdz $+8\;b %l0\";
13912 [(set_attr "type" "branch")
13913 (set_attr "length" "*,12,16,16")])
13915 ;; Now the splitters if we could not allocate the CTR register
13919 (if_then_else (match_operator 2 "comparison_operator"
13920 [(match_operand:P 1 "gpc_reg_operand" "")
13922 (match_operand 5 "" "")
13923 (match_operand 6 "" "")))
13924 (set (match_operand:P 0 "gpc_reg_operand" "")
13925 (plus:P (match_dup 1) (const_int -1)))
13926 (clobber (match_scratch:CC 3 ""))
13927 (clobber (match_scratch:P 4 ""))]
13929 [(parallel [(set (match_dup 3)
13930 (compare:CC (plus:P (match_dup 1)
13934 (plus:P (match_dup 1)
13936 (set (pc) (if_then_else (match_dup 7)
13940 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13941 operands[3], const0_rtx); }")
13945 (if_then_else (match_operator 2 "comparison_operator"
13946 [(match_operand:P 1 "gpc_reg_operand" "")
13948 (match_operand 5 "" "")
13949 (match_operand 6 "" "")))
13950 (set (match_operand:P 0 "nonimmediate_operand" "")
13951 (plus:P (match_dup 1) (const_int -1)))
13952 (clobber (match_scratch:CC 3 ""))
13953 (clobber (match_scratch:P 4 ""))]
13954 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13955 [(parallel [(set (match_dup 3)
13956 (compare:CC (plus:P (match_dup 1)
13960 (plus:P (match_dup 1)
13964 (set (pc) (if_then_else (match_dup 7)
13968 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13969 operands[3], const0_rtx); }")
13971 (define_insn "trap"
13972 [(trap_if (const_int 1) (const_int 0))]
13976 (define_expand "conditional_trap"
13977 [(trap_if (match_operator 0 "trap_comparison_operator"
13978 [(match_dup 2) (match_dup 3)])
13979 (match_operand 1 "const_int_operand" ""))]
13981 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
13982 operands[2] = rs6000_compare_op0;
13983 operands[3] = rs6000_compare_op1;")
13986 [(trap_if (match_operator 0 "trap_comparison_operator"
13987 [(match_operand:GPR 1 "register_operand" "r")
13988 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13991 "{t|t<wd>}%V0%I2 %1,%2")
13993 ;; Insns related to generating the function prologue and epilogue.
13995 (define_expand "prologue"
13996 [(use (const_int 0))]
13997 "TARGET_SCHED_PROLOG"
14000 rs6000_emit_prologue ();
14004 (define_insn "*movesi_from_cr_one"
14005 [(match_parallel 0 "mfcr_operation"
14006 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14007 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14008 (match_operand 3 "immediate_operand" "n")]
14009 UNSPEC_MOVESI_FROM_CR))])]
14015 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14017 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14018 operands[4] = GEN_INT (mask);
14019 output_asm_insn (\"mfcr %1,%4\", operands);
14023 [(set_attr "type" "mfcrf")])
14025 (define_insn "movesi_from_cr"
14026 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14027 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14028 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14029 UNSPEC_MOVESI_FROM_CR))]
14032 [(set_attr "type" "mfcr")])
14034 (define_insn "*stmw"
14035 [(match_parallel 0 "stmw_operation"
14036 [(set (match_operand:SI 1 "memory_operand" "=m")
14037 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14040 [(set_attr "type" "store_ux")])
14042 (define_insn "*save_fpregs_<mode>"
14043 [(match_parallel 0 "any_parallel_operand"
14044 [(clobber (match_operand:P 1 "register_operand" "=l"))
14045 (use (match_operand:P 2 "call_operand" "s"))
14046 (set (match_operand:DF 3 "memory_operand" "=m")
14047 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14050 [(set_attr "type" "branch")
14051 (set_attr "length" "4")])
14053 ; These are to explain that changes to the stack pointer should
14054 ; not be moved over stores to stack memory.
14055 (define_insn "stack_tie"
14056 [(set (match_operand:BLK 0 "memory_operand" "+m")
14057 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14060 [(set_attr "length" "0")])
14063 (define_expand "epilogue"
14064 [(use (const_int 0))]
14065 "TARGET_SCHED_PROLOG"
14068 rs6000_emit_epilogue (FALSE);
14072 ; On some processors, doing the mtcrf one CC register at a time is
14073 ; faster (like on the 604e). On others, doing them all at once is
14074 ; faster; for instance, on the 601 and 750.
14076 (define_expand "movsi_to_cr_one"
14077 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14078 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14079 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14081 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14083 (define_insn "*movsi_to_cr"
14084 [(match_parallel 0 "mtcrf_operation"
14085 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14086 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14087 (match_operand 3 "immediate_operand" "n")]
14088 UNSPEC_MOVESI_TO_CR))])]
14094 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14095 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14096 operands[4] = GEN_INT (mask);
14097 return \"mtcrf %4,%2\";
14099 [(set_attr "type" "mtcr")])
14101 (define_insn "*mtcrfsi"
14102 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14103 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14104 (match_operand 2 "immediate_operand" "n")]
14105 UNSPEC_MOVESI_TO_CR))]
14106 "GET_CODE (operands[0]) == REG
14107 && CR_REGNO_P (REGNO (operands[0]))
14108 && GET_CODE (operands[2]) == CONST_INT
14109 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14111 [(set_attr "type" "mtcr")])
14113 ; The load-multiple instructions have similar properties.
14114 ; Note that "load_multiple" is a name known to the machine-independent
14115 ; code that actually corresponds to the PowerPC load-string.
14117 (define_insn "*lmw"
14118 [(match_parallel 0 "lmw_operation"
14119 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14120 (match_operand:SI 2 "memory_operand" "m"))])]
14123 [(set_attr "type" "load_ux")])
14125 (define_insn "*return_internal_<mode>"
14127 (use (match_operand:P 0 "register_operand" "lc"))]
14130 [(set_attr "type" "jmpreg")])
14132 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14133 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14135 (define_insn "*return_and_restore_fpregs_<mode>"
14136 [(match_parallel 0 "any_parallel_operand"
14138 (use (match_operand:P 1 "register_operand" "l"))
14139 (use (match_operand:P 2 "call_operand" "s"))
14140 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14141 (match_operand:DF 4 "memory_operand" "m"))])]
14145 ; This is used in compiling the unwind routines.
14146 (define_expand "eh_return"
14147 [(use (match_operand 0 "general_operand" ""))]
14152 emit_insn (gen_eh_set_lr_si (operands[0]));
14154 emit_insn (gen_eh_set_lr_di (operands[0]));
14158 ; We can't expand this before we know where the link register is stored.
14159 (define_insn "eh_set_lr_<mode>"
14160 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14162 (clobber (match_scratch:P 1 "=&b"))]
14167 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14168 (clobber (match_scratch 1 ""))]
14173 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14177 (define_insn "prefetch"
14178 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14179 (match_operand:SI 1 "const_int_operand" "n")
14180 (match_operand:SI 2 "const_int_operand" "n"))]
14184 if (GET_CODE (operands[0]) == REG)
14185 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14186 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14188 [(set_attr "type" "load")])
14191 (include "sync.md")
14192 (include "altivec.md")