1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 ;; MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
65 ;; UNSPEC_VOLATILE usage
70 (UNSPECV_EH_RR 9) ; eh_reg_restore
73 ;; Define an insn type attribute. This is used in function unit delay
75 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
76 (const_string "integer"))
79 ; '(pc)' in the following doesn't include the instruction itself; it is
80 ; calculated as if the instruction had zero size.
81 (define_attr "length" ""
82 (if_then_else (eq_attr "type" "branch")
83 (if_then_else (and (ge (minus (match_dup 0) (pc))
85 (lt (minus (match_dup 0) (pc))
91 ;; Processor type -- this attribute must exactly match the processor_type
92 ;; enumeration in rs6000.h.
94 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
95 (const (symbol_ref "rs6000_cpu_attr")))
97 (automata_option "ndfa")
110 (include "power4.md")
111 (include "power5.md")
113 (include "predicates.md")
115 (include "darwin.md")
120 ; This mode macro allows :GPR to be used to indicate the allowable size
121 ; of whole values in GPRs.
122 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
124 ; Any supported integer mode.
125 (define_mode_macro INT [QI HI SI DI TI])
127 ; Any supported integer mode that fits in one register.
128 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
130 ; SImode or DImode, even if DImode doesn't fit in GPRs.
131 (define_mode_macro SDI [SI DI])
133 ; The size of a pointer. Also, the size of the value that a record-condition
134 ; (one with a '.') will compare.
135 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
137 ; Various instructions that come in SI and DI forms.
138 (define_mode_attr larx [(SI "lwarx") (DI "ldarx")])
139 (define_mode_attr stcx [(SI "stwcx.") (DI "stdcx.")])
140 ; A generic w/d attribute, for things like cmpw/cmpd.
141 (define_mode_attr wd [(SI "w") (DI "d")])
144 ;; Start with fixed-point load and store insns. Here we put only the more
145 ;; complex forms. Basic data transfer is done later.
147 (define_expand "zero_extendqidi2"
148 [(set (match_operand:DI 0 "gpc_reg_operand" "")
149 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
154 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
155 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
160 [(set_attr "type" "load,*")])
163 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
164 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
166 (clobber (match_scratch:DI 2 "=r,r"))]
171 [(set_attr "type" "compare")
172 (set_attr "length" "4,8")])
175 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
176 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
178 (clobber (match_scratch:DI 2 ""))]
179 "TARGET_POWERPC64 && reload_completed"
181 (zero_extend:DI (match_dup 1)))
183 (compare:CC (match_dup 2)
188 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
189 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
191 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
192 (zero_extend:DI (match_dup 1)))]
197 [(set_attr "type" "compare")
198 (set_attr "length" "4,8")])
201 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
202 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
204 (set (match_operand:DI 0 "gpc_reg_operand" "")
205 (zero_extend:DI (match_dup 1)))]
206 "TARGET_POWERPC64 && reload_completed"
208 (zero_extend:DI (match_dup 1)))
210 (compare:CC (match_dup 0)
214 (define_insn "extendqidi2"
215 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
216 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
221 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
222 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
224 (clobber (match_scratch:DI 2 "=r,r"))]
229 [(set_attr "type" "compare")
230 (set_attr "length" "4,8")])
233 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
234 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
236 (clobber (match_scratch:DI 2 ""))]
237 "TARGET_POWERPC64 && reload_completed"
239 (sign_extend:DI (match_dup 1)))
241 (compare:CC (match_dup 2)
246 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
247 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
249 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
250 (sign_extend:DI (match_dup 1)))]
255 [(set_attr "type" "compare")
256 (set_attr "length" "4,8")])
259 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
260 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
262 (set (match_operand:DI 0 "gpc_reg_operand" "")
263 (sign_extend:DI (match_dup 1)))]
264 "TARGET_POWERPC64 && reload_completed"
266 (sign_extend:DI (match_dup 1)))
268 (compare:CC (match_dup 0)
272 (define_expand "zero_extendhidi2"
273 [(set (match_operand:DI 0 "gpc_reg_operand" "")
274 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
279 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
280 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
285 [(set_attr "type" "load,*")])
288 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
289 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
291 (clobber (match_scratch:DI 2 "=r,r"))]
296 [(set_attr "type" "compare")
297 (set_attr "length" "4,8")])
300 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
301 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
303 (clobber (match_scratch:DI 2 ""))]
304 "TARGET_POWERPC64 && reload_completed"
306 (zero_extend:DI (match_dup 1)))
308 (compare:CC (match_dup 2)
313 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
314 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
316 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
317 (zero_extend:DI (match_dup 1)))]
322 [(set_attr "type" "compare")
323 (set_attr "length" "4,8")])
326 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
327 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
329 (set (match_operand:DI 0 "gpc_reg_operand" "")
330 (zero_extend:DI (match_dup 1)))]
331 "TARGET_POWERPC64 && reload_completed"
333 (zero_extend:DI (match_dup 1)))
335 (compare:CC (match_dup 0)
339 (define_expand "extendhidi2"
340 [(set (match_operand:DI 0 "gpc_reg_operand" "")
341 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
346 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
347 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
352 [(set_attr "type" "load_ext,*")])
355 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
356 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
358 (clobber (match_scratch:DI 2 "=r,r"))]
363 [(set_attr "type" "compare")
364 (set_attr "length" "4,8")])
367 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
368 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
370 (clobber (match_scratch:DI 2 ""))]
371 "TARGET_POWERPC64 && reload_completed"
373 (sign_extend:DI (match_dup 1)))
375 (compare:CC (match_dup 2)
380 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
381 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
383 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
384 (sign_extend:DI (match_dup 1)))]
389 [(set_attr "type" "compare")
390 (set_attr "length" "4,8")])
393 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
394 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
396 (set (match_operand:DI 0 "gpc_reg_operand" "")
397 (sign_extend:DI (match_dup 1)))]
398 "TARGET_POWERPC64 && reload_completed"
400 (sign_extend:DI (match_dup 1)))
402 (compare:CC (match_dup 0)
406 (define_expand "zero_extendsidi2"
407 [(set (match_operand:DI 0 "gpc_reg_operand" "")
408 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
413 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
414 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
419 [(set_attr "type" "load,*")])
422 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
423 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
425 (clobber (match_scratch:DI 2 "=r,r"))]
430 [(set_attr "type" "compare")
431 (set_attr "length" "4,8")])
434 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
435 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
437 (clobber (match_scratch:DI 2 ""))]
438 "TARGET_POWERPC64 && reload_completed"
440 (zero_extend:DI (match_dup 1)))
442 (compare:CC (match_dup 2)
447 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
448 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
450 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
451 (zero_extend:DI (match_dup 1)))]
456 [(set_attr "type" "compare")
457 (set_attr "length" "4,8")])
460 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
461 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
463 (set (match_operand:DI 0 "gpc_reg_operand" "")
464 (zero_extend:DI (match_dup 1)))]
465 "TARGET_POWERPC64 && reload_completed"
467 (zero_extend:DI (match_dup 1)))
469 (compare:CC (match_dup 0)
473 (define_expand "extendsidi2"
474 [(set (match_operand:DI 0 "gpc_reg_operand" "")
475 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
480 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
481 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
486 [(set_attr "type" "load_ext,*")])
489 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
490 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
492 (clobber (match_scratch:DI 2 "=r,r"))]
497 [(set_attr "type" "compare")
498 (set_attr "length" "4,8")])
501 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
502 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
504 (clobber (match_scratch:DI 2 ""))]
505 "TARGET_POWERPC64 && reload_completed"
507 (sign_extend:DI (match_dup 1)))
509 (compare:CC (match_dup 2)
514 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
515 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
517 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
518 (sign_extend:DI (match_dup 1)))]
523 [(set_attr "type" "compare")
524 (set_attr "length" "4,8")])
527 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
528 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
530 (set (match_operand:DI 0 "gpc_reg_operand" "")
531 (sign_extend:DI (match_dup 1)))]
532 "TARGET_POWERPC64 && reload_completed"
534 (sign_extend:DI (match_dup 1)))
536 (compare:CC (match_dup 0)
540 (define_expand "zero_extendqisi2"
541 [(set (match_operand:SI 0 "gpc_reg_operand" "")
542 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
547 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
548 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
552 {rlinm|rlwinm} %0,%1,0,0xff"
553 [(set_attr "type" "load,*")])
556 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
557 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
559 (clobber (match_scratch:SI 2 "=r,r"))]
562 {andil.|andi.} %2,%1,0xff
564 [(set_attr "type" "compare")
565 (set_attr "length" "4,8")])
568 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
569 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
571 (clobber (match_scratch:SI 2 ""))]
574 (zero_extend:SI (match_dup 1)))
576 (compare:CC (match_dup 2)
581 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
582 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
584 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
585 (zero_extend:SI (match_dup 1)))]
588 {andil.|andi.} %0,%1,0xff
590 [(set_attr "type" "compare")
591 (set_attr "length" "4,8")])
594 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
595 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
597 (set (match_operand:SI 0 "gpc_reg_operand" "")
598 (zero_extend:SI (match_dup 1)))]
601 (zero_extend:SI (match_dup 1)))
603 (compare:CC (match_dup 0)
607 (define_expand "extendqisi2"
608 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
609 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
614 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
615 else if (TARGET_POWER)
616 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
618 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
622 (define_insn "extendqisi2_ppc"
623 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
624 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
629 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
630 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
632 (clobber (match_scratch:SI 2 "=r,r"))]
637 [(set_attr "type" "compare")
638 (set_attr "length" "4,8")])
641 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
642 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
644 (clobber (match_scratch:SI 2 ""))]
645 "TARGET_POWERPC && reload_completed"
647 (sign_extend:SI (match_dup 1)))
649 (compare:CC (match_dup 2)
654 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
655 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
657 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
658 (sign_extend:SI (match_dup 1)))]
663 [(set_attr "type" "compare")
664 (set_attr "length" "4,8")])
667 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
668 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
670 (set (match_operand:SI 0 "gpc_reg_operand" "")
671 (sign_extend:SI (match_dup 1)))]
672 "TARGET_POWERPC && reload_completed"
674 (sign_extend:SI (match_dup 1)))
676 (compare:CC (match_dup 0)
680 (define_expand "extendqisi2_power"
681 [(parallel [(set (match_dup 2)
682 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
684 (clobber (scratch:SI))])
685 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
686 (ashiftrt:SI (match_dup 2)
688 (clobber (scratch:SI))])]
691 { operands[1] = gen_lowpart (SImode, operands[1]);
692 operands[2] = gen_reg_rtx (SImode); }")
694 (define_expand "extendqisi2_no_power"
696 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
698 (set (match_operand:SI 0 "gpc_reg_operand" "")
699 (ashiftrt:SI (match_dup 2)
701 "! TARGET_POWER && ! TARGET_POWERPC"
703 { operands[1] = gen_lowpart (SImode, operands[1]);
704 operands[2] = gen_reg_rtx (SImode); }")
706 (define_expand "zero_extendqihi2"
707 [(set (match_operand:HI 0 "gpc_reg_operand" "")
708 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
713 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
714 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
718 {rlinm|rlwinm} %0,%1,0,0xff"
719 [(set_attr "type" "load,*")])
722 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
723 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
725 (clobber (match_scratch:HI 2 "=r,r"))]
728 {andil.|andi.} %2,%1,0xff
730 [(set_attr "type" "compare")
731 (set_attr "length" "4,8")])
734 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
735 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
737 (clobber (match_scratch:HI 2 ""))]
740 (zero_extend:HI (match_dup 1)))
742 (compare:CC (match_dup 2)
747 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
748 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
750 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
751 (zero_extend:HI (match_dup 1)))]
754 {andil.|andi.} %0,%1,0xff
756 [(set_attr "type" "compare")
757 (set_attr "length" "4,8")])
760 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
761 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
763 (set (match_operand:HI 0 "gpc_reg_operand" "")
764 (zero_extend:HI (match_dup 1)))]
767 (zero_extend:HI (match_dup 1)))
769 (compare:CC (match_dup 0)
773 (define_expand "extendqihi2"
774 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
775 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
780 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
781 else if (TARGET_POWER)
782 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
784 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
788 (define_insn "extendqihi2_ppc"
789 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
790 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
795 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
796 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
798 (clobber (match_scratch:HI 2 "=r,r"))]
803 [(set_attr "type" "compare")
804 (set_attr "length" "4,8")])
807 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
808 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
810 (clobber (match_scratch:HI 2 ""))]
811 "TARGET_POWERPC && reload_completed"
813 (sign_extend:HI (match_dup 1)))
815 (compare:CC (match_dup 2)
820 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
821 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
823 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
824 (sign_extend:HI (match_dup 1)))]
829 [(set_attr "type" "compare")
830 (set_attr "length" "4,8")])
833 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
834 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
836 (set (match_operand:HI 0 "gpc_reg_operand" "")
837 (sign_extend:HI (match_dup 1)))]
838 "TARGET_POWERPC && reload_completed"
840 (sign_extend:HI (match_dup 1)))
842 (compare:CC (match_dup 0)
846 (define_expand "extendqihi2_power"
847 [(parallel [(set (match_dup 2)
848 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
850 (clobber (scratch:SI))])
851 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
852 (ashiftrt:SI (match_dup 2)
854 (clobber (scratch:SI))])]
857 { operands[0] = gen_lowpart (SImode, operands[0]);
858 operands[1] = gen_lowpart (SImode, operands[1]);
859 operands[2] = gen_reg_rtx (SImode); }")
861 (define_expand "extendqihi2_no_power"
863 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
865 (set (match_operand:HI 0 "gpc_reg_operand" "")
866 (ashiftrt:SI (match_dup 2)
868 "! TARGET_POWER && ! TARGET_POWERPC"
870 { operands[0] = gen_lowpart (SImode, operands[0]);
871 operands[1] = gen_lowpart (SImode, operands[1]);
872 operands[2] = gen_reg_rtx (SImode); }")
874 (define_expand "zero_extendhisi2"
875 [(set (match_operand:SI 0 "gpc_reg_operand" "")
876 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
881 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
882 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
886 {rlinm|rlwinm} %0,%1,0,0xffff"
887 [(set_attr "type" "load,*")])
890 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
891 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
893 (clobber (match_scratch:SI 2 "=r,r"))]
896 {andil.|andi.} %2,%1,0xffff
898 [(set_attr "type" "compare")
899 (set_attr "length" "4,8")])
902 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
903 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
905 (clobber (match_scratch:SI 2 ""))]
908 (zero_extend:SI (match_dup 1)))
910 (compare:CC (match_dup 2)
915 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
916 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
918 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
919 (zero_extend:SI (match_dup 1)))]
922 {andil.|andi.} %0,%1,0xffff
924 [(set_attr "type" "compare")
925 (set_attr "length" "4,8")])
928 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
929 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
931 (set (match_operand:SI 0 "gpc_reg_operand" "")
932 (zero_extend:SI (match_dup 1)))]
935 (zero_extend:SI (match_dup 1)))
937 (compare:CC (match_dup 0)
941 (define_expand "extendhisi2"
942 [(set (match_operand:SI 0 "gpc_reg_operand" "")
943 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
948 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
949 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
954 [(set_attr "type" "load_ext,*")])
957 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
958 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
960 (clobber (match_scratch:SI 2 "=r,r"))]
965 [(set_attr "type" "compare")
966 (set_attr "length" "4,8")])
969 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
970 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
972 (clobber (match_scratch:SI 2 ""))]
975 (sign_extend:SI (match_dup 1)))
977 (compare:CC (match_dup 2)
982 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
983 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
985 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
986 (sign_extend:SI (match_dup 1)))]
991 [(set_attr "type" "compare")
992 (set_attr "length" "4,8")])
995 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
996 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
998 (set (match_operand:SI 0 "gpc_reg_operand" "")
999 (sign_extend:SI (match_dup 1)))]
1002 (sign_extend:SI (match_dup 1)))
1004 (compare:CC (match_dup 0)
1008 ;; Fixed-point arithmetic insns.
1010 (define_mode_attr add_op2 [(SI "reg_or_arith_cint_operand")
1011 (DI "reg_or_add_cint64_operand")])
1013 (define_expand "add<mode>3"
1014 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1015 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1016 (match_operand:SDI 2 "<add_op2>" "")))]
1020 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1022 if (non_short_cint_operand (operands[2], DImode))
1025 else if (GET_CODE (operands[2]) == CONST_INT
1026 && ! add_operand (operands[2], <MODE>mode))
1028 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1029 ? operands[0] : gen_reg_rtx (<MODE>mode));
1031 HOST_WIDE_INT val = INTVAL (operands[2]);
1032 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1033 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1035 if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L'))
1038 /* The ordering here is important for the prolog expander.
1039 When space is allocated from the stack, adding 'low' first may
1040 produce a temporary deallocation (which would be bad). */
1041 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1042 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1047 ;; Discourage ai/addic because of carry but provide it in an alternative
1048 ;; allowing register zero as source.
1049 (define_insn "*add<mode>3_internal1"
1050 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1051 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1052 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1056 {cal %0,%2(%1)|addi %0,%1,%2}
1058 {cau|addis} %0,%1,%v2"
1059 [(set_attr "length" "4,4,4,4")])
1061 (define_insn "addsi3_high"
1062 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1063 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1064 (high:SI (match_operand 2 "" ""))))]
1065 "TARGET_MACHO && !TARGET_64BIT"
1066 "{cau|addis} %0,%1,ha16(%2)"
1067 [(set_attr "length" "4")])
1069 (define_insn "*add<mode>3_internal2"
1070 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1071 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1072 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1074 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1077 {cax.|add.} %3,%1,%2
1078 {ai.|addic.} %3,%1,%2
1081 [(set_attr "type" "fast_compare,compare,compare,compare")
1082 (set_attr "length" "4,4,8,8")])
1085 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1086 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1087 (match_operand:GPR 2 "reg_or_short_operand" ""))
1089 (clobber (match_scratch:GPR 3 ""))]
1092 (plus:GPR (match_dup 1)
1095 (compare:CC (match_dup 3)
1099 (define_insn "*add<mode>3_internal3"
1100 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1101 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1102 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1104 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1105 (plus:P (match_dup 1)
1109 {cax.|add.} %0,%1,%2
1110 {ai.|addic.} %0,%1,%2
1113 [(set_attr "type" "fast_compare,compare,compare,compare")
1114 (set_attr "length" "4,4,8,8")])
1117 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1118 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1119 (match_operand:P 2 "reg_or_short_operand" ""))
1121 (set (match_operand:P 0 "gpc_reg_operand" "")
1122 (plus:P (match_dup 1) (match_dup 2)))]
1125 (plus:P (match_dup 1)
1128 (compare:CC (match_dup 0)
1132 ;; Split an add that we can't do in one insn into two insns, each of which
1133 ;; does one 16-bit part. This is used by combine. Note that the low-order
1134 ;; add should be last in case the result gets used in an address.
1137 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1138 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1139 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1141 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1142 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1145 HOST_WIDE_INT val = INTVAL (operands[2]);
1146 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1147 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1149 operands[4] = GEN_INT (low);
1150 if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L'))
1151 operands[3] = GEN_INT (rest);
1152 else if (! no_new_pseudos)
1154 operands[3] = gen_reg_rtx (DImode);
1155 emit_move_insn (operands[3], operands[2]);
1156 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1163 (define_insn "one_cmpl<mode>2"
1164 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1165 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1170 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1171 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1173 (clobber (match_scratch:P 2 "=r,r"))]
1178 [(set_attr "type" "compare")
1179 (set_attr "length" "4,8")])
1182 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1183 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1185 (clobber (match_scratch:P 2 ""))]
1188 (not:P (match_dup 1)))
1190 (compare:CC (match_dup 2)
1195 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1196 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1198 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1199 (not:P (match_dup 1)))]
1204 [(set_attr "type" "compare")
1205 (set_attr "length" "4,8")])
1208 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1209 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1211 (set (match_operand:P 0 "gpc_reg_operand" "")
1212 (not:P (match_dup 1)))]
1215 (not:P (match_dup 1)))
1217 (compare:CC (match_dup 0)
1222 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1223 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1224 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1226 "{sf%I1|subf%I1c} %0,%2,%1")
1229 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1230 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1231 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1238 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1239 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1240 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1242 (clobber (match_scratch:SI 3 "=r,r"))]
1245 {sf.|subfc.} %3,%2,%1
1247 [(set_attr "type" "compare")
1248 (set_attr "length" "4,8")])
1251 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1252 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1253 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1255 (clobber (match_scratch:P 3 "=r,r"))]
1260 [(set_attr "type" "fast_compare")
1261 (set_attr "length" "4,8")])
1264 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1265 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1266 (match_operand:P 2 "gpc_reg_operand" ""))
1268 (clobber (match_scratch:P 3 ""))]
1271 (minus:P (match_dup 1)
1274 (compare:CC (match_dup 3)
1279 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1280 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1281 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1283 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1284 (minus:SI (match_dup 1) (match_dup 2)))]
1287 {sf.|subfc.} %0,%2,%1
1289 [(set_attr "type" "compare")
1290 (set_attr "length" "4,8")])
1293 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1294 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1295 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1297 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1298 (minus:P (match_dup 1)
1304 [(set_attr "type" "fast_compare")
1305 (set_attr "length" "4,8")])
1308 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1309 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1310 (match_operand:P 2 "gpc_reg_operand" ""))
1312 (set (match_operand:P 0 "gpc_reg_operand" "")
1313 (minus:P (match_dup 1)
1317 (minus:P (match_dup 1)
1320 (compare:CC (match_dup 0)
1324 (define_mode_attr sub_op2 [(SI "reg_or_arith_cint_operand")
1325 (DI "reg_or_sub_cint64_operand")])
1327 (define_expand "sub<mode>3"
1328 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1329 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1330 (match_operand:SDI 2 "<sub_op2>" "")))]
1334 if (GET_CODE (operands[2]) == CONST_INT)
1336 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1337 negate_rtx (<MODE>mode, operands[2])));
1342 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1343 ;; instruction and some auxiliary computations. Then we just have a single
1344 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1347 (define_expand "sminsi3"
1349 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1350 (match_operand:SI 2 "reg_or_short_operand" ""))
1352 (minus:SI (match_dup 2) (match_dup 1))))
1353 (set (match_operand:SI 0 "gpc_reg_operand" "")
1354 (minus:SI (match_dup 2) (match_dup 3)))]
1355 "TARGET_POWER || TARGET_ISEL"
1360 operands[2] = force_reg (SImode, operands[2]);
1361 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1365 operands[3] = gen_reg_rtx (SImode);
1369 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1370 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1371 (match_operand:SI 2 "reg_or_short_operand" "")))
1372 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1375 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1377 (minus:SI (match_dup 2) (match_dup 1))))
1378 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1381 (define_expand "smaxsi3"
1383 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1384 (match_operand:SI 2 "reg_or_short_operand" ""))
1386 (minus:SI (match_dup 2) (match_dup 1))))
1387 (set (match_operand:SI 0 "gpc_reg_operand" "")
1388 (plus:SI (match_dup 3) (match_dup 1)))]
1389 "TARGET_POWER || TARGET_ISEL"
1394 operands[2] = force_reg (SImode, operands[2]);
1395 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1398 operands[3] = gen_reg_rtx (SImode);
1402 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1403 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1404 (match_operand:SI 2 "reg_or_short_operand" "")))
1405 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1408 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1410 (minus:SI (match_dup 2) (match_dup 1))))
1411 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1414 (define_expand "uminsi3"
1415 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1417 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1419 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1421 (minus:SI (match_dup 4) (match_dup 3))))
1422 (set (match_operand:SI 0 "gpc_reg_operand" "")
1423 (minus:SI (match_dup 2) (match_dup 3)))]
1424 "TARGET_POWER || TARGET_ISEL"
1429 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1432 operands[3] = gen_reg_rtx (SImode);
1433 operands[4] = gen_reg_rtx (SImode);
1434 operands[5] = GEN_INT (-2147483647 - 1);
1437 (define_expand "umaxsi3"
1438 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1440 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1442 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1444 (minus:SI (match_dup 4) (match_dup 3))))
1445 (set (match_operand:SI 0 "gpc_reg_operand" "")
1446 (plus:SI (match_dup 3) (match_dup 1)))]
1447 "TARGET_POWER || TARGET_ISEL"
1452 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1455 operands[3] = gen_reg_rtx (SImode);
1456 operands[4] = gen_reg_rtx (SImode);
1457 operands[5] = GEN_INT (-2147483647 - 1);
1461 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1462 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1463 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1465 (minus:SI (match_dup 2) (match_dup 1))))]
1470 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1472 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1473 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1475 (minus:SI (match_dup 2) (match_dup 1)))
1477 (clobber (match_scratch:SI 3 "=r,r"))]
1482 [(set_attr "type" "delayed_compare")
1483 (set_attr "length" "4,8")])
1486 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1488 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1489 (match_operand:SI 2 "reg_or_short_operand" ""))
1491 (minus:SI (match_dup 2) (match_dup 1)))
1493 (clobber (match_scratch:SI 3 ""))]
1494 "TARGET_POWER && reload_completed"
1496 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1498 (minus:SI (match_dup 2) (match_dup 1))))
1500 (compare:CC (match_dup 3)
1505 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1507 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1508 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1510 (minus:SI (match_dup 2) (match_dup 1)))
1512 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1513 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1515 (minus:SI (match_dup 2) (match_dup 1))))]
1520 [(set_attr "type" "delayed_compare")
1521 (set_attr "length" "4,8")])
1524 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1526 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1527 (match_operand:SI 2 "reg_or_short_operand" ""))
1529 (minus:SI (match_dup 2) (match_dup 1)))
1531 (set (match_operand:SI 0 "gpc_reg_operand" "")
1532 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1534 (minus:SI (match_dup 2) (match_dup 1))))]
1535 "TARGET_POWER && reload_completed"
1537 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1539 (minus:SI (match_dup 2) (match_dup 1))))
1541 (compare:CC (match_dup 0)
1545 ;; We don't need abs with condition code because such comparisons should
1547 (define_expand "abssi2"
1548 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1549 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1555 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1558 else if (! TARGET_POWER)
1560 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1565 (define_insn "*abssi2_power"
1566 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1567 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1571 (define_insn_and_split "abssi2_isel"
1572 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1573 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1574 (clobber (match_scratch:SI 2 "=&b"))
1575 (clobber (match_scratch:CC 3 "=y"))]
1578 "&& reload_completed"
1579 [(set (match_dup 2) (neg:SI (match_dup 1)))
1581 (compare:CC (match_dup 1)
1584 (if_then_else:SI (ge (match_dup 3)
1590 (define_insn_and_split "abssi2_nopower"
1591 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1592 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1593 (clobber (match_scratch:SI 2 "=&r,&r"))]
1594 "! TARGET_POWER && ! TARGET_ISEL"
1596 "&& reload_completed"
1597 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1598 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1599 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1602 (define_insn "*nabs_power"
1603 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1604 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1608 (define_insn_and_split "*nabs_nopower"
1609 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1610 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1611 (clobber (match_scratch:SI 2 "=&r,&r"))]
1614 "&& reload_completed"
1615 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1616 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1617 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1620 (define_expand "neg<mode>2"
1621 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1622 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1626 (define_insn "*neg<mode>2_internal"
1627 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1628 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1633 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1634 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1636 (clobber (match_scratch:P 2 "=r,r"))]
1641 [(set_attr "type" "fast_compare")
1642 (set_attr "length" "4,8")])
1645 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1646 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1648 (clobber (match_scratch:P 2 ""))]
1651 (neg:P (match_dup 1)))
1653 (compare:CC (match_dup 2)
1658 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1659 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1661 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1662 (neg:P (match_dup 1)))]
1667 [(set_attr "type" "fast_compare")
1668 (set_attr "length" "4,8")])
1671 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1672 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1674 (set (match_operand:P 0 "gpc_reg_operand" "")
1675 (neg:P (match_dup 1)))]
1678 (neg:P (match_dup 1)))
1680 (compare:CC (match_dup 0)
1684 (define_insn "clz<mode>2"
1685 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1686 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1688 "{cntlz|cntlz<wd>} %0,%1")
1690 (define_expand "ctz<mode>2"
1692 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1693 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1695 (clobber (scratch:CC))])
1696 (set (match_dup 4) (clz:GPR (match_dup 3)))
1697 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1698 (minus:GPR (match_dup 5) (match_dup 4)))]
1701 operands[2] = gen_reg_rtx (<MODE>mode);
1702 operands[3] = gen_reg_rtx (<MODE>mode);
1703 operands[4] = gen_reg_rtx (<MODE>mode);
1704 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1707 (define_expand "ffs<mode>2"
1709 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
1710 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1712 (clobber (scratch:CC))])
1713 (set (match_dup 4) (clz:GPR (match_dup 3)))
1714 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1715 (minus:GPR (match_dup 5) (match_dup 4)))]
1718 operands[2] = gen_reg_rtx (<MODE>mode);
1719 operands[3] = gen_reg_rtx (<MODE>mode);
1720 operands[4] = gen_reg_rtx (<MODE>mode);
1721 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1724 (define_expand "popcount<mode>2"
1726 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1729 (mult:GPR (match_dup 2) (match_dup 4)))
1730 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1731 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
1734 operands[2] = gen_reg_rtx (<MODE>mode);
1735 operands[3] = gen_reg_rtx (<MODE>mode);
1736 operands[4] = force_reg (<MODE>mode,
1737 <MODE>mode == SImode
1738 ? GEN_INT (0x01010101)
1739 : GEN_INT ((HOST_WIDE_INT)
1740 0x01010101 << 32 | 0x01010101));
1741 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
1744 (define_insn "popcntb<mode>2"
1745 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1746 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1751 (define_expand "mulsi3"
1752 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1753 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1754 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1759 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1761 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1765 (define_insn "mulsi3_mq"
1766 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1767 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1768 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1769 (clobber (match_scratch:SI 3 "=q,q"))]
1772 {muls|mullw} %0,%1,%2
1773 {muli|mulli} %0,%1,%2"
1775 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1776 (const_string "imul3")
1777 (match_operand:SI 2 "short_cint_operand" "")
1778 (const_string "imul2")]
1779 (const_string "imul")))])
1781 (define_insn "mulsi3_no_mq"
1782 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1783 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1784 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1787 {muls|mullw} %0,%1,%2
1788 {muli|mulli} %0,%1,%2"
1790 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1791 (const_string "imul3")
1792 (match_operand:SI 2 "short_cint_operand" "")
1793 (const_string "imul2")]
1794 (const_string "imul")))])
1796 (define_insn "*mulsi3_mq_internal1"
1797 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1798 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1799 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1801 (clobber (match_scratch:SI 3 "=r,r"))
1802 (clobber (match_scratch:SI 4 "=q,q"))]
1805 {muls.|mullw.} %3,%1,%2
1807 [(set_attr "type" "imul_compare")
1808 (set_attr "length" "4,8")])
1811 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1812 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1813 (match_operand:SI 2 "gpc_reg_operand" ""))
1815 (clobber (match_scratch:SI 3 ""))
1816 (clobber (match_scratch:SI 4 ""))]
1817 "TARGET_POWER && reload_completed"
1818 [(parallel [(set (match_dup 3)
1819 (mult:SI (match_dup 1) (match_dup 2)))
1820 (clobber (match_dup 4))])
1822 (compare:CC (match_dup 3)
1826 (define_insn "*mulsi3_no_mq_internal1"
1827 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1828 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1829 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1831 (clobber (match_scratch:SI 3 "=r,r"))]
1834 {muls.|mullw.} %3,%1,%2
1836 [(set_attr "type" "imul_compare")
1837 (set_attr "length" "4,8")])
1840 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1841 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1842 (match_operand:SI 2 "gpc_reg_operand" ""))
1844 (clobber (match_scratch:SI 3 ""))]
1845 "! TARGET_POWER && reload_completed"
1847 (mult:SI (match_dup 1) (match_dup 2)))
1849 (compare:CC (match_dup 3)
1853 (define_insn "*mulsi3_mq_internal2"
1854 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1855 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1856 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1858 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1859 (mult:SI (match_dup 1) (match_dup 2)))
1860 (clobber (match_scratch:SI 4 "=q,q"))]
1863 {muls.|mullw.} %0,%1,%2
1865 [(set_attr "type" "imul_compare")
1866 (set_attr "length" "4,8")])
1869 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1870 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1871 (match_operand:SI 2 "gpc_reg_operand" ""))
1873 (set (match_operand:SI 0 "gpc_reg_operand" "")
1874 (mult:SI (match_dup 1) (match_dup 2)))
1875 (clobber (match_scratch:SI 4 ""))]
1876 "TARGET_POWER && reload_completed"
1877 [(parallel [(set (match_dup 0)
1878 (mult:SI (match_dup 1) (match_dup 2)))
1879 (clobber (match_dup 4))])
1881 (compare:CC (match_dup 0)
1885 (define_insn "*mulsi3_no_mq_internal2"
1886 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1887 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1888 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1890 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1891 (mult:SI (match_dup 1) (match_dup 2)))]
1894 {muls.|mullw.} %0,%1,%2
1896 [(set_attr "type" "imul_compare")
1897 (set_attr "length" "4,8")])
1900 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1901 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1902 (match_operand:SI 2 "gpc_reg_operand" ""))
1904 (set (match_operand:SI 0 "gpc_reg_operand" "")
1905 (mult:SI (match_dup 1) (match_dup 2)))]
1906 "! TARGET_POWER && reload_completed"
1908 (mult:SI (match_dup 1) (match_dup 2)))
1910 (compare:CC (match_dup 0)
1914 ;; Operand 1 is divided by operand 2; quotient goes to operand
1915 ;; 0 and remainder to operand 3.
1916 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1918 (define_expand "divmodsi4"
1919 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1920 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1921 (match_operand:SI 2 "gpc_reg_operand" "")))
1922 (set (match_operand:SI 3 "register_operand" "")
1923 (mod:SI (match_dup 1) (match_dup 2)))])]
1924 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1927 if (! TARGET_POWER && ! TARGET_POWERPC)
1929 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1930 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1931 emit_insn (gen_divss_call ());
1932 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1933 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1938 (define_insn "*divmodsi4_internal"
1939 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1940 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1941 (match_operand:SI 2 "gpc_reg_operand" "r")))
1942 (set (match_operand:SI 3 "register_operand" "=q")
1943 (mod:SI (match_dup 1) (match_dup 2)))]
1946 [(set_attr "type" "idiv")])
1948 (define_expand "udivsi3"
1949 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1950 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1951 (match_operand:SI 2 "gpc_reg_operand" "")))]
1952 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1955 if (! TARGET_POWER && ! TARGET_POWERPC)
1957 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1958 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1959 emit_insn (gen_quous_call ());
1960 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1963 else if (TARGET_POWER)
1965 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1970 (define_insn "udivsi3_mq"
1971 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1972 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1973 (match_operand:SI 2 "gpc_reg_operand" "r")))
1974 (clobber (match_scratch:SI 3 "=q"))]
1975 "TARGET_POWERPC && TARGET_POWER"
1977 [(set_attr "type" "idiv")])
1979 (define_insn "*udivsi3_no_mq"
1980 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1981 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1982 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1983 "TARGET_POWERPC && ! TARGET_POWER"
1985 [(set_attr "type" "idiv")])
1987 ;; For powers of two we can do srai/aze for divide and then adjust for
1988 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1989 ;; used; for PowerPC, force operands into register and do a normal divide;
1990 ;; for AIX common-mode, use quoss call on register operands.
1991 (define_expand "divsi3"
1992 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1993 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1994 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1998 if (GET_CODE (operands[2]) == CONST_INT
1999 && INTVAL (operands[2]) > 0
2000 && exact_log2 (INTVAL (operands[2])) >= 0)
2002 else if (TARGET_POWERPC)
2004 operands[2] = force_reg (SImode, operands[2]);
2007 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2011 else if (TARGET_POWER)
2015 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2016 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2017 emit_insn (gen_quoss_call ());
2018 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2023 (define_insn "divsi3_mq"
2024 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2025 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2026 (match_operand:SI 2 "gpc_reg_operand" "r")))
2027 (clobber (match_scratch:SI 3 "=q"))]
2028 "TARGET_POWERPC && TARGET_POWER"
2030 [(set_attr "type" "idiv")])
2032 (define_insn "*divsi3_no_mq"
2033 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2034 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2035 (match_operand:SI 2 "gpc_reg_operand" "r")))]
2036 "TARGET_POWERPC && ! TARGET_POWER"
2038 [(set_attr "type" "idiv")])
2040 (define_expand "modsi3"
2041 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2042 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2043 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2051 if (GET_CODE (operands[2]) != CONST_INT
2052 || INTVAL (operands[2]) <= 0
2053 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2056 temp1 = gen_reg_rtx (SImode);
2057 temp2 = gen_reg_rtx (SImode);
2059 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
2060 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
2061 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
2066 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2067 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2068 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
2070 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
2071 [(set_attr "type" "two")
2072 (set_attr "length" "8")])
2075 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2076 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2077 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2079 (clobber (match_scratch:SI 3 "=r,r"))]
2082 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
2084 [(set_attr "type" "compare")
2085 (set_attr "length" "8,12")])
2088 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2089 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2090 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2092 (clobber (match_scratch:SI 3 ""))]
2095 (div:SI (match_dup 1) (match_dup 2)))
2097 (compare:CC (match_dup 3)
2102 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2103 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2104 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2106 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2107 (div:SI (match_dup 1) (match_dup 2)))]
2110 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2112 [(set_attr "type" "compare")
2113 (set_attr "length" "8,12")])
2116 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2117 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2118 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2120 (set (match_operand:SI 0 "gpc_reg_operand" "")
2121 (div:SI (match_dup 1) (match_dup 2)))]
2124 (div:SI (match_dup 1) (match_dup 2)))
2126 (compare:CC (match_dup 0)
2131 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2134 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2136 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2137 (match_operand:SI 3 "gpc_reg_operand" "r")))
2138 (set (match_operand:SI 2 "register_operand" "=*q")
2141 (zero_extend:DI (match_dup 1)) (const_int 32))
2142 (zero_extend:DI (match_dup 4)))
2146 [(set_attr "type" "idiv")])
2148 ;; To do unsigned divide we handle the cases of the divisor looking like a
2149 ;; negative number. If it is a constant that is less than 2**31, we don't
2150 ;; have to worry about the branches. So make a few subroutines here.
2152 ;; First comes the normal case.
2153 (define_expand "udivmodsi4_normal"
2154 [(set (match_dup 4) (const_int 0))
2155 (parallel [(set (match_operand:SI 0 "" "")
2156 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2158 (zero_extend:DI (match_operand:SI 1 "" "")))
2159 (match_operand:SI 2 "" "")))
2160 (set (match_operand:SI 3 "" "")
2161 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2163 (zero_extend:DI (match_dup 1)))
2167 { operands[4] = gen_reg_rtx (SImode); }")
2169 ;; This handles the branches.
2170 (define_expand "udivmodsi4_tests"
2171 [(set (match_operand:SI 0 "" "") (const_int 0))
2172 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2173 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2174 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2175 (label_ref (match_operand:SI 4 "" "")) (pc)))
2176 (set (match_dup 0) (const_int 1))
2177 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2178 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2179 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2180 (label_ref (match_dup 4)) (pc)))]
2183 { operands[5] = gen_reg_rtx (CCUNSmode);
2184 operands[6] = gen_reg_rtx (CCmode);
2187 (define_expand "udivmodsi4"
2188 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2189 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2190 (match_operand:SI 2 "reg_or_cint_operand" "")))
2191 (set (match_operand:SI 3 "gpc_reg_operand" "")
2192 (umod:SI (match_dup 1) (match_dup 2)))])]
2200 if (! TARGET_POWERPC)
2202 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2203 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2204 emit_insn (gen_divus_call ());
2205 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2206 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2213 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2215 operands[2] = force_reg (SImode, operands[2]);
2216 label = gen_label_rtx ();
2217 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2218 operands[3], label));
2221 operands[2] = force_reg (SImode, operands[2]);
2223 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2231 ;; AIX architecture-independent common-mode multiply (DImode),
2232 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2233 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2234 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2235 ;; assumed unused if generating common-mode, so ignore.
2236 (define_insn "mulh_call"
2239 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2240 (sign_extend:DI (reg:SI 4)))
2242 (clobber (match_scratch:SI 0 "=l"))]
2243 "! TARGET_POWER && ! TARGET_POWERPC"
2245 [(set_attr "type" "imul")])
2247 (define_insn "mull_call"
2249 (mult:DI (sign_extend:DI (reg:SI 3))
2250 (sign_extend:DI (reg:SI 4))))
2251 (clobber (match_scratch:SI 0 "=l"))
2252 (clobber (reg:SI 0))]
2253 "! TARGET_POWER && ! TARGET_POWERPC"
2255 [(set_attr "type" "imul")])
2257 (define_insn "divss_call"
2259 (div:SI (reg:SI 3) (reg:SI 4)))
2261 (mod:SI (reg:SI 3) (reg:SI 4)))
2262 (clobber (match_scratch:SI 0 "=l"))
2263 (clobber (reg:SI 0))]
2264 "! TARGET_POWER && ! TARGET_POWERPC"
2266 [(set_attr "type" "idiv")])
2268 (define_insn "divus_call"
2270 (udiv:SI (reg:SI 3) (reg:SI 4)))
2272 (umod:SI (reg:SI 3) (reg:SI 4)))
2273 (clobber (match_scratch:SI 0 "=l"))
2274 (clobber (reg:SI 0))
2275 (clobber (match_scratch:CC 1 "=x"))
2276 (clobber (reg:CC 69))]
2277 "! TARGET_POWER && ! TARGET_POWERPC"
2279 [(set_attr "type" "idiv")])
2281 (define_insn "quoss_call"
2283 (div:SI (reg:SI 3) (reg:SI 4)))
2284 (clobber (match_scratch:SI 0 "=l"))]
2285 "! TARGET_POWER && ! TARGET_POWERPC"
2287 [(set_attr "type" "idiv")])
2289 (define_insn "quous_call"
2291 (udiv:SI (reg:SI 3) (reg:SI 4)))
2292 (clobber (match_scratch:SI 0 "=l"))
2293 (clobber (reg:SI 0))
2294 (clobber (match_scratch:CC 1 "=x"))
2295 (clobber (reg:CC 69))]
2296 "! TARGET_POWER && ! TARGET_POWERPC"
2298 [(set_attr "type" "idiv")])
2300 ;; Logical instructions
2301 ;; The logical instructions are mostly combined by using match_operator,
2302 ;; but the plain AND insns are somewhat different because there is no
2303 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2304 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2306 (define_insn "andsi3"
2307 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2308 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2309 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2310 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2314 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2315 {andil.|andi.} %0,%1,%b2
2316 {andiu.|andis.} %0,%1,%u2"
2317 [(set_attr "type" "*,*,compare,compare")])
2319 ;; Note to set cr's other than cr0 we do the and immediate and then
2320 ;; the test again -- this avoids a mfcr which on the higher end
2321 ;; machines causes an execution serialization
2323 (define_insn "*andsi3_internal2"
2324 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2325 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2326 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2328 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2329 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2333 {andil.|andi.} %3,%1,%b2
2334 {andiu.|andis.} %3,%1,%u2
2335 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2340 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2341 (set_attr "length" "4,4,4,4,8,8,8,8")])
2343 (define_insn "*andsi3_internal3"
2344 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2345 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2346 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2348 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2349 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2353 {andil.|andi.} %3,%1,%b2
2354 {andiu.|andis.} %3,%1,%u2
2355 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2360 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2361 (set_attr "length" "8,4,4,4,8,8,8,8")])
2364 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2365 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2366 (match_operand:SI 2 "and_operand" ""))
2368 (clobber (match_scratch:SI 3 ""))
2369 (clobber (match_scratch:CC 4 ""))]
2371 [(parallel [(set (match_dup 3)
2372 (and:SI (match_dup 1)
2374 (clobber (match_dup 4))])
2376 (compare:CC (match_dup 3)
2380 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2381 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2384 [(set (match_operand:CC 0 "cc_reg_operand" "")
2385 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2386 (match_operand:SI 2 "gpc_reg_operand" ""))
2388 (clobber (match_scratch:SI 3 ""))
2389 (clobber (match_scratch:CC 4 ""))]
2390 "TARGET_POWERPC64 && reload_completed"
2391 [(parallel [(set (match_dup 3)
2392 (and:SI (match_dup 1)
2394 (clobber (match_dup 4))])
2396 (compare:CC (match_dup 3)
2400 (define_insn "*andsi3_internal4"
2401 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2402 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2403 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2405 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2406 (and:SI (match_dup 1)
2408 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2412 {andil.|andi.} %0,%1,%b2
2413 {andiu.|andis.} %0,%1,%u2
2414 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2419 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2420 (set_attr "length" "4,4,4,4,8,8,8,8")])
2422 (define_insn "*andsi3_internal5"
2423 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2424 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2425 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2427 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2428 (and:SI (match_dup 1)
2430 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2434 {andil.|andi.} %0,%1,%b2
2435 {andiu.|andis.} %0,%1,%u2
2436 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2441 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2442 (set_attr "length" "8,4,4,4,8,8,8,8")])
2445 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2446 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2447 (match_operand:SI 2 "and_operand" ""))
2449 (set (match_operand:SI 0 "gpc_reg_operand" "")
2450 (and:SI (match_dup 1)
2452 (clobber (match_scratch:CC 4 ""))]
2454 [(parallel [(set (match_dup 0)
2455 (and:SI (match_dup 1)
2457 (clobber (match_dup 4))])
2459 (compare:CC (match_dup 0)
2464 [(set (match_operand:CC 3 "cc_reg_operand" "")
2465 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2466 (match_operand:SI 2 "gpc_reg_operand" ""))
2468 (set (match_operand:SI 0 "gpc_reg_operand" "")
2469 (and:SI (match_dup 1)
2471 (clobber (match_scratch:CC 4 ""))]
2472 "TARGET_POWERPC64 && reload_completed"
2473 [(parallel [(set (match_dup 0)
2474 (and:SI (match_dup 1)
2476 (clobber (match_dup 4))])
2478 (compare:CC (match_dup 0)
2482 ;; Handle the PowerPC64 rlwinm corner case
2484 (define_insn_and_split "*andsi3_internal6"
2485 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2486 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2487 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2492 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2495 (rotate:SI (match_dup 0) (match_dup 5)))]
2498 int mb = extract_MB (operands[2]);
2499 int me = extract_ME (operands[2]);
2500 operands[3] = GEN_INT (me + 1);
2501 operands[5] = GEN_INT (32 - (me + 1));
2502 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2504 [(set_attr "length" "8")])
2506 (define_expand "iorsi3"
2507 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2508 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2509 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2513 if (GET_CODE (operands[2]) == CONST_INT
2514 && ! logical_operand (operands[2], SImode))
2516 HOST_WIDE_INT value = INTVAL (operands[2]);
2517 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2518 ? operands[0] : gen_reg_rtx (SImode));
2520 emit_insn (gen_iorsi3 (tmp, operands[1],
2521 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2522 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2527 (define_expand "xorsi3"
2528 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2529 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2530 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2534 if (GET_CODE (operands[2]) == CONST_INT
2535 && ! logical_operand (operands[2], SImode))
2537 HOST_WIDE_INT value = INTVAL (operands[2]);
2538 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2539 ? operands[0] : gen_reg_rtx (SImode));
2541 emit_insn (gen_xorsi3 (tmp, operands[1],
2542 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2543 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2548 (define_insn "*boolsi3_internal1"
2549 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2550 (match_operator:SI 3 "boolean_or_operator"
2551 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2552 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2556 {%q3il|%q3i} %0,%1,%b2
2557 {%q3iu|%q3is} %0,%1,%u2")
2559 (define_insn "*boolsi3_internal2"
2560 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2561 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2562 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2563 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2565 (clobber (match_scratch:SI 3 "=r,r"))]
2570 [(set_attr "type" "compare")
2571 (set_attr "length" "4,8")])
2574 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2575 (compare:CC (match_operator:SI 4 "boolean_operator"
2576 [(match_operand:SI 1 "gpc_reg_operand" "")
2577 (match_operand:SI 2 "gpc_reg_operand" "")])
2579 (clobber (match_scratch:SI 3 ""))]
2580 "TARGET_32BIT && reload_completed"
2581 [(set (match_dup 3) (match_dup 4))
2583 (compare:CC (match_dup 3)
2587 (define_insn "*boolsi3_internal3"
2588 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2589 (compare:CC (match_operator:SI 4 "boolean_operator"
2590 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2591 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2593 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2599 [(set_attr "type" "compare")
2600 (set_attr "length" "4,8")])
2603 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2604 (compare:CC (match_operator:SI 4 "boolean_operator"
2605 [(match_operand:SI 1 "gpc_reg_operand" "")
2606 (match_operand:SI 2 "gpc_reg_operand" "")])
2608 (set (match_operand:SI 0 "gpc_reg_operand" "")
2610 "TARGET_32BIT && reload_completed"
2611 [(set (match_dup 0) (match_dup 4))
2613 (compare:CC (match_dup 0)
2617 ;; Split a logical operation that we can't do in one insn into two insns,
2618 ;; each of which does one 16-bit part. This is used by combine.
2621 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2622 (match_operator:SI 3 "boolean_or_operator"
2623 [(match_operand:SI 1 "gpc_reg_operand" "")
2624 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2626 [(set (match_dup 0) (match_dup 4))
2627 (set (match_dup 0) (match_dup 5))]
2631 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2632 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2634 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2635 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2639 (define_insn "*boolcsi3_internal1"
2640 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2641 (match_operator:SI 3 "boolean_operator"
2642 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2643 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2647 (define_insn "*boolcsi3_internal2"
2648 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2649 (compare:CC (match_operator:SI 4 "boolean_operator"
2650 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2651 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2653 (clobber (match_scratch:SI 3 "=r,r"))]
2658 [(set_attr "type" "compare")
2659 (set_attr "length" "4,8")])
2662 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2663 (compare:CC (match_operator:SI 4 "boolean_operator"
2664 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2665 (match_operand:SI 2 "gpc_reg_operand" "")])
2667 (clobber (match_scratch:SI 3 ""))]
2668 "TARGET_32BIT && reload_completed"
2669 [(set (match_dup 3) (match_dup 4))
2671 (compare:CC (match_dup 3)
2675 (define_insn "*boolcsi3_internal3"
2676 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2677 (compare:CC (match_operator:SI 4 "boolean_operator"
2678 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2679 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2681 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2687 [(set_attr "type" "compare")
2688 (set_attr "length" "4,8")])
2691 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2692 (compare:CC (match_operator:SI 4 "boolean_operator"
2693 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2694 (match_operand:SI 2 "gpc_reg_operand" "")])
2696 (set (match_operand:SI 0 "gpc_reg_operand" "")
2698 "TARGET_32BIT && reload_completed"
2699 [(set (match_dup 0) (match_dup 4))
2701 (compare:CC (match_dup 0)
2705 (define_insn "*boolccsi3_internal1"
2706 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2707 (match_operator:SI 3 "boolean_operator"
2708 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2709 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2713 (define_insn "*boolccsi3_internal2"
2714 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2715 (compare:CC (match_operator:SI 4 "boolean_operator"
2716 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2717 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2719 (clobber (match_scratch:SI 3 "=r,r"))]
2724 [(set_attr "type" "compare")
2725 (set_attr "length" "4,8")])
2728 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2729 (compare:CC (match_operator:SI 4 "boolean_operator"
2730 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2731 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2733 (clobber (match_scratch:SI 3 ""))]
2734 "TARGET_32BIT && reload_completed"
2735 [(set (match_dup 3) (match_dup 4))
2737 (compare:CC (match_dup 3)
2741 (define_insn "*boolccsi3_internal3"
2742 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2743 (compare:CC (match_operator:SI 4 "boolean_operator"
2744 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2745 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2747 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2753 [(set_attr "type" "compare")
2754 (set_attr "length" "4,8")])
2757 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2758 (compare:CC (match_operator:SI 4 "boolean_operator"
2759 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2760 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2762 (set (match_operand:SI 0 "gpc_reg_operand" "")
2764 "TARGET_32BIT && reload_completed"
2765 [(set (match_dup 0) (match_dup 4))
2767 (compare:CC (match_dup 0)
2771 ;; maskir insn. We need four forms because things might be in arbitrary
2772 ;; orders. Don't define forms that only set CR fields because these
2773 ;; would modify an input register.
2775 (define_insn "*maskir_internal1"
2776 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2777 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2778 (match_operand:SI 1 "gpc_reg_operand" "0"))
2779 (and:SI (match_dup 2)
2780 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2784 (define_insn "*maskir_internal2"
2785 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2786 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2787 (match_operand:SI 1 "gpc_reg_operand" "0"))
2788 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2793 (define_insn "*maskir_internal3"
2794 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2795 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2796 (match_operand:SI 3 "gpc_reg_operand" "r"))
2797 (and:SI (not:SI (match_dup 2))
2798 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2802 (define_insn "*maskir_internal4"
2803 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2804 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2805 (match_operand:SI 2 "gpc_reg_operand" "r"))
2806 (and:SI (not:SI (match_dup 2))
2807 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2811 (define_insn "*maskir_internal5"
2812 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2814 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2815 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2816 (and:SI (match_dup 2)
2817 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2819 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2820 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2821 (and:SI (match_dup 2) (match_dup 3))))]
2826 [(set_attr "type" "compare")
2827 (set_attr "length" "4,8")])
2830 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2832 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2833 (match_operand:SI 1 "gpc_reg_operand" ""))
2834 (and:SI (match_dup 2)
2835 (match_operand:SI 3 "gpc_reg_operand" "")))
2837 (set (match_operand:SI 0 "gpc_reg_operand" "")
2838 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2839 (and:SI (match_dup 2) (match_dup 3))))]
2840 "TARGET_POWER && reload_completed"
2842 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2843 (and:SI (match_dup 2) (match_dup 3))))
2845 (compare:CC (match_dup 0)
2849 (define_insn "*maskir_internal6"
2850 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2852 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2853 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2854 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2857 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2858 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2859 (and:SI (match_dup 3) (match_dup 2))))]
2864 [(set_attr "type" "compare")
2865 (set_attr "length" "4,8")])
2868 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2870 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2871 (match_operand:SI 1 "gpc_reg_operand" ""))
2872 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2875 (set (match_operand:SI 0 "gpc_reg_operand" "")
2876 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2877 (and:SI (match_dup 3) (match_dup 2))))]
2878 "TARGET_POWER && reload_completed"
2880 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2881 (and:SI (match_dup 3) (match_dup 2))))
2883 (compare:CC (match_dup 0)
2887 (define_insn "*maskir_internal7"
2888 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2890 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2891 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2892 (and:SI (not:SI (match_dup 2))
2893 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2895 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2896 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2897 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2902 [(set_attr "type" "compare")
2903 (set_attr "length" "4,8")])
2906 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2908 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2909 (match_operand:SI 3 "gpc_reg_operand" ""))
2910 (and:SI (not:SI (match_dup 2))
2911 (match_operand:SI 1 "gpc_reg_operand" "")))
2913 (set (match_operand:SI 0 "gpc_reg_operand" "")
2914 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2915 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2916 "TARGET_POWER && reload_completed"
2918 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2919 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2921 (compare:CC (match_dup 0)
2925 (define_insn "*maskir_internal8"
2926 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2928 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2929 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2930 (and:SI (not:SI (match_dup 2))
2931 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2933 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2934 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2935 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2940 [(set_attr "type" "compare")
2941 (set_attr "length" "4,8")])
2944 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2946 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2947 (match_operand:SI 2 "gpc_reg_operand" ""))
2948 (and:SI (not:SI (match_dup 2))
2949 (match_operand:SI 1 "gpc_reg_operand" "")))
2951 (set (match_operand:SI 0 "gpc_reg_operand" "")
2952 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2953 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2954 "TARGET_POWER && reload_completed"
2956 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2957 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2959 (compare:CC (match_dup 0)
2963 ;; Rotate and shift insns, in all their variants. These support shifts,
2964 ;; field inserts and extracts, and various combinations thereof.
2965 (define_expand "insv"
2966 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2967 (match_operand:SI 1 "const_int_operand" "")
2968 (match_operand:SI 2 "const_int_operand" ""))
2969 (match_operand 3 "gpc_reg_operand" ""))]
2973 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2974 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2975 compiler if the address of the structure is taken later. */
2976 if (GET_CODE (operands[0]) == SUBREG
2977 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2980 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2981 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2983 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2987 (define_insn "insvsi"
2988 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2989 (match_operand:SI 1 "const_int_operand" "i")
2990 (match_operand:SI 2 "const_int_operand" "i"))
2991 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2995 int start = INTVAL (operands[2]) & 31;
2996 int size = INTVAL (operands[1]) & 31;
2998 operands[4] = GEN_INT (32 - start - size);
2999 operands[1] = GEN_INT (start + size - 1);
3000 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3002 [(set_attr "type" "insert_word")])
3004 (define_insn "*insvsi_internal1"
3005 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3006 (match_operand:SI 1 "const_int_operand" "i")
3007 (match_operand:SI 2 "const_int_operand" "i"))
3008 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3009 (match_operand:SI 4 "const_int_operand" "i")))]
3010 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3013 int shift = INTVAL (operands[4]) & 31;
3014 int start = INTVAL (operands[2]) & 31;
3015 int size = INTVAL (operands[1]) & 31;
3017 operands[4] = GEN_INT (shift - start - size);
3018 operands[1] = GEN_INT (start + size - 1);
3019 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3021 [(set_attr "type" "insert_word")])
3023 (define_insn "*insvsi_internal2"
3024 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3025 (match_operand:SI 1 "const_int_operand" "i")
3026 (match_operand:SI 2 "const_int_operand" "i"))
3027 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3028 (match_operand:SI 4 "const_int_operand" "i")))]
3029 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3032 int shift = INTVAL (operands[4]) & 31;
3033 int start = INTVAL (operands[2]) & 31;
3034 int size = INTVAL (operands[1]) & 31;
3036 operands[4] = GEN_INT (32 - shift - start - size);
3037 operands[1] = GEN_INT (start + size - 1);
3038 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3040 [(set_attr "type" "insert_word")])
3042 (define_insn "*insvsi_internal3"
3043 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3044 (match_operand:SI 1 "const_int_operand" "i")
3045 (match_operand:SI 2 "const_int_operand" "i"))
3046 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3047 (match_operand:SI 4 "const_int_operand" "i")))]
3048 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3051 int shift = INTVAL (operands[4]) & 31;
3052 int start = INTVAL (operands[2]) & 31;
3053 int size = INTVAL (operands[1]) & 31;
3055 operands[4] = GEN_INT (32 - shift - start - size);
3056 operands[1] = GEN_INT (start + size - 1);
3057 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3059 [(set_attr "type" "insert_word")])
3061 (define_insn "*insvsi_internal4"
3062 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3063 (match_operand:SI 1 "const_int_operand" "i")
3064 (match_operand:SI 2 "const_int_operand" "i"))
3065 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3066 (match_operand:SI 4 "const_int_operand" "i")
3067 (match_operand:SI 5 "const_int_operand" "i")))]
3068 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3071 int extract_start = INTVAL (operands[5]) & 31;
3072 int extract_size = INTVAL (operands[4]) & 31;
3073 int insert_start = INTVAL (operands[2]) & 31;
3074 int insert_size = INTVAL (operands[1]) & 31;
3076 /* Align extract field with insert field */
3077 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3078 operands[1] = GEN_INT (insert_start + insert_size - 1);
3079 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3081 [(set_attr "type" "insert_word")])
3083 ;; combine patterns for rlwimi
3084 (define_insn "*insvsi_internal5"
3085 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3086 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3087 (match_operand:SI 1 "mask_operand" "i"))
3088 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3089 (match_operand:SI 2 "const_int_operand" "i"))
3090 (match_operand:SI 5 "mask_operand" "i"))))]
3091 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3094 int me = extract_ME(operands[5]);
3095 int mb = extract_MB(operands[5]);
3096 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3097 operands[2] = GEN_INT(mb);
3098 operands[1] = GEN_INT(me);
3099 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3101 [(set_attr "type" "insert_word")])
3103 (define_insn "*insvsi_internal6"
3104 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3105 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3106 (match_operand:SI 2 "const_int_operand" "i"))
3107 (match_operand:SI 5 "mask_operand" "i"))
3108 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3109 (match_operand:SI 1 "mask_operand" "i"))))]
3110 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3113 int me = extract_ME(operands[5]);
3114 int mb = extract_MB(operands[5]);
3115 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3116 operands[2] = GEN_INT(mb);
3117 operands[1] = GEN_INT(me);
3118 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3120 [(set_attr "type" "insert_word")])
3122 (define_insn "insvdi"
3123 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3124 (match_operand:SI 1 "const_int_operand" "i")
3125 (match_operand:SI 2 "const_int_operand" "i"))
3126 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3130 int start = INTVAL (operands[2]) & 63;
3131 int size = INTVAL (operands[1]) & 63;
3133 operands[1] = GEN_INT (64 - start - size);
3134 return \"rldimi %0,%3,%H1,%H2\";
3137 (define_insn "*insvdi_internal2"
3138 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3139 (match_operand:SI 1 "const_int_operand" "i")
3140 (match_operand:SI 2 "const_int_operand" "i"))
3141 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3142 (match_operand:SI 4 "const_int_operand" "i")))]
3144 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3147 int shift = INTVAL (operands[4]) & 63;
3148 int start = (INTVAL (operands[2]) & 63) - 32;
3149 int size = INTVAL (operands[1]) & 63;
3151 operands[4] = GEN_INT (64 - shift - start - size);
3152 operands[2] = GEN_INT (start);
3153 operands[1] = GEN_INT (start + size - 1);
3154 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3157 (define_insn "*insvdi_internal3"
3158 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3159 (match_operand:SI 1 "const_int_operand" "i")
3160 (match_operand:SI 2 "const_int_operand" "i"))
3161 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3162 (match_operand:SI 4 "const_int_operand" "i")))]
3164 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3167 int shift = INTVAL (operands[4]) & 63;
3168 int start = (INTVAL (operands[2]) & 63) - 32;
3169 int size = INTVAL (operands[1]) & 63;
3171 operands[4] = GEN_INT (64 - shift - start - size);
3172 operands[2] = GEN_INT (start);
3173 operands[1] = GEN_INT (start + size - 1);
3174 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3177 (define_expand "extzv"
3178 [(set (match_operand 0 "gpc_reg_operand" "")
3179 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3180 (match_operand:SI 2 "const_int_operand" "")
3181 (match_operand:SI 3 "const_int_operand" "")))]
3185 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3186 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3187 compiler if the address of the structure is taken later. */
3188 if (GET_CODE (operands[0]) == SUBREG
3189 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3192 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3193 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3195 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3199 (define_insn "extzvsi"
3200 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3201 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3202 (match_operand:SI 2 "const_int_operand" "i")
3203 (match_operand:SI 3 "const_int_operand" "i")))]
3207 int start = INTVAL (operands[3]) & 31;
3208 int size = INTVAL (operands[2]) & 31;
3210 if (start + size >= 32)
3211 operands[3] = const0_rtx;
3213 operands[3] = GEN_INT (start + size);
3214 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3217 (define_insn "*extzvsi_internal1"
3218 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3219 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3220 (match_operand:SI 2 "const_int_operand" "i,i")
3221 (match_operand:SI 3 "const_int_operand" "i,i"))
3223 (clobber (match_scratch:SI 4 "=r,r"))]
3227 int start = INTVAL (operands[3]) & 31;
3228 int size = INTVAL (operands[2]) & 31;
3230 /* Force split for non-cc0 compare. */
3231 if (which_alternative == 1)
3234 /* If the bit-field being tested fits in the upper or lower half of a
3235 word, it is possible to use andiu. or andil. to test it. This is
3236 useful because the condition register set-use delay is smaller for
3237 andi[ul]. than for rlinm. This doesn't work when the starting bit
3238 position is 0 because the LT and GT bits may be set wrong. */
3240 if ((start > 0 && start + size <= 16) || start >= 16)
3242 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3243 - (1 << (16 - (start & 15) - size))));
3245 return \"{andiu.|andis.} %4,%1,%3\";
3247 return \"{andil.|andi.} %4,%1,%3\";
3250 if (start + size >= 32)
3251 operands[3] = const0_rtx;
3253 operands[3] = GEN_INT (start + size);
3254 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3256 [(set_attr "type" "compare")
3257 (set_attr "length" "4,8")])
3260 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3261 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3262 (match_operand:SI 2 "const_int_operand" "")
3263 (match_operand:SI 3 "const_int_operand" ""))
3265 (clobber (match_scratch:SI 4 ""))]
3268 (zero_extract:SI (match_dup 1) (match_dup 2)
3271 (compare:CC (match_dup 4)
3275 (define_insn "*extzvsi_internal2"
3276 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3277 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3278 (match_operand:SI 2 "const_int_operand" "i,i")
3279 (match_operand:SI 3 "const_int_operand" "i,i"))
3281 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3282 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3286 int start = INTVAL (operands[3]) & 31;
3287 int size = INTVAL (operands[2]) & 31;
3289 /* Force split for non-cc0 compare. */
3290 if (which_alternative == 1)
3293 /* Since we are using the output value, we can't ignore any need for
3294 a shift. The bit-field must end at the LSB. */
3295 if (start >= 16 && start + size == 32)
3297 operands[3] = GEN_INT ((1 << size) - 1);
3298 return \"{andil.|andi.} %0,%1,%3\";
3301 if (start + size >= 32)
3302 operands[3] = const0_rtx;
3304 operands[3] = GEN_INT (start + size);
3305 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3307 [(set_attr "type" "compare")
3308 (set_attr "length" "4,8")])
3311 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3312 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3313 (match_operand:SI 2 "const_int_operand" "")
3314 (match_operand:SI 3 "const_int_operand" ""))
3316 (set (match_operand:SI 0 "gpc_reg_operand" "")
3317 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3320 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3322 (compare:CC (match_dup 0)
3326 (define_insn "extzvdi"
3327 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3328 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3329 (match_operand:SI 2 "const_int_operand" "i")
3330 (match_operand:SI 3 "const_int_operand" "i")))]
3334 int start = INTVAL (operands[3]) & 63;
3335 int size = INTVAL (operands[2]) & 63;
3337 if (start + size >= 64)
3338 operands[3] = const0_rtx;
3340 operands[3] = GEN_INT (start + size);
3341 operands[2] = GEN_INT (64 - size);
3342 return \"rldicl %0,%1,%3,%2\";
3345 (define_insn "*extzvdi_internal1"
3346 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3347 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3348 (match_operand:SI 2 "const_int_operand" "i")
3349 (match_operand:SI 3 "const_int_operand" "i"))
3351 (clobber (match_scratch:DI 4 "=r"))]
3355 int start = INTVAL (operands[3]) & 63;
3356 int size = INTVAL (operands[2]) & 63;
3358 if (start + size >= 64)
3359 operands[3] = const0_rtx;
3361 operands[3] = GEN_INT (start + size);
3362 operands[2] = GEN_INT (64 - size);
3363 return \"rldicl. %4,%1,%3,%2\";
3365 [(set_attr "type" "compare")])
3367 (define_insn "*extzvdi_internal2"
3368 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3369 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3370 (match_operand:SI 2 "const_int_operand" "i")
3371 (match_operand:SI 3 "const_int_operand" "i"))
3373 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3374 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3378 int start = INTVAL (operands[3]) & 63;
3379 int size = INTVAL (operands[2]) & 63;
3381 if (start + size >= 64)
3382 operands[3] = const0_rtx;
3384 operands[3] = GEN_INT (start + size);
3385 operands[2] = GEN_INT (64 - size);
3386 return \"rldicl. %0,%1,%3,%2\";
3388 [(set_attr "type" "compare")])
3390 (define_insn "rotlsi3"
3391 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3392 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3393 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3395 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3397 (define_insn "*rotlsi3_internal2"
3398 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3399 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3400 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3402 (clobber (match_scratch:SI 3 "=r,r"))]
3405 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3407 [(set_attr "type" "delayed_compare")
3408 (set_attr "length" "4,8")])
3411 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3412 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3413 (match_operand:SI 2 "reg_or_cint_operand" ""))
3415 (clobber (match_scratch:SI 3 ""))]
3418 (rotate:SI (match_dup 1) (match_dup 2)))
3420 (compare:CC (match_dup 3)
3424 (define_insn "*rotlsi3_internal3"
3425 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3426 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3427 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3429 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3430 (rotate:SI (match_dup 1) (match_dup 2)))]
3433 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3435 [(set_attr "type" "delayed_compare")
3436 (set_attr "length" "4,8")])
3439 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3440 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3441 (match_operand:SI 2 "reg_or_cint_operand" ""))
3443 (set (match_operand:SI 0 "gpc_reg_operand" "")
3444 (rotate:SI (match_dup 1) (match_dup 2)))]
3447 (rotate:SI (match_dup 1) (match_dup 2)))
3449 (compare:CC (match_dup 0)
3453 (define_insn "*rotlsi3_internal4"
3454 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3455 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3456 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3457 (match_operand:SI 3 "mask_operand" "n")))]
3459 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3461 (define_insn "*rotlsi3_internal5"
3462 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3464 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3465 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3466 (match_operand:SI 3 "mask_operand" "n,n"))
3468 (clobber (match_scratch:SI 4 "=r,r"))]
3471 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3473 [(set_attr "type" "delayed_compare")
3474 (set_attr "length" "4,8")])
3477 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3479 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3480 (match_operand:SI 2 "reg_or_cint_operand" ""))
3481 (match_operand:SI 3 "mask_operand" ""))
3483 (clobber (match_scratch:SI 4 ""))]
3486 (and:SI (rotate:SI (match_dup 1)
3490 (compare:CC (match_dup 4)
3494 (define_insn "*rotlsi3_internal6"
3495 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3497 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3498 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3499 (match_operand:SI 3 "mask_operand" "n,n"))
3501 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3502 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3505 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3507 [(set_attr "type" "delayed_compare")
3508 (set_attr "length" "4,8")])
3511 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3513 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3514 (match_operand:SI 2 "reg_or_cint_operand" ""))
3515 (match_operand:SI 3 "mask_operand" ""))
3517 (set (match_operand:SI 0 "gpc_reg_operand" "")
3518 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3521 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3523 (compare:CC (match_dup 0)
3527 (define_insn "*rotlsi3_internal7"
3528 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3531 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3532 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3534 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3536 (define_insn "*rotlsi3_internal8"
3537 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3538 (compare:CC (zero_extend:SI
3540 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3541 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3543 (clobber (match_scratch:SI 3 "=r,r"))]
3546 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3548 [(set_attr "type" "delayed_compare")
3549 (set_attr "length" "4,8")])
3552 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3553 (compare:CC (zero_extend:SI
3555 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3556 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3558 (clobber (match_scratch:SI 3 ""))]
3561 (zero_extend:SI (subreg:QI
3562 (rotate:SI (match_dup 1)
3565 (compare:CC (match_dup 3)
3569 (define_insn "*rotlsi3_internal9"
3570 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3571 (compare:CC (zero_extend:SI
3573 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3574 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3576 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3577 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3580 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3582 [(set_attr "type" "delayed_compare")
3583 (set_attr "length" "4,8")])
3586 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3587 (compare:CC (zero_extend:SI
3589 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3590 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3592 (set (match_operand:SI 0 "gpc_reg_operand" "")
3593 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3596 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3598 (compare:CC (match_dup 0)
3602 (define_insn "*rotlsi3_internal10"
3603 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3606 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3607 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3609 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3611 (define_insn "*rotlsi3_internal11"
3612 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3613 (compare:CC (zero_extend:SI
3615 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3616 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3618 (clobber (match_scratch:SI 3 "=r,r"))]
3621 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3623 [(set_attr "type" "delayed_compare")
3624 (set_attr "length" "4,8")])
3627 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3628 (compare:CC (zero_extend:SI
3630 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3631 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3633 (clobber (match_scratch:SI 3 ""))]
3636 (zero_extend:SI (subreg:HI
3637 (rotate:SI (match_dup 1)
3640 (compare:CC (match_dup 3)
3644 (define_insn "*rotlsi3_internal12"
3645 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3646 (compare:CC (zero_extend:SI
3648 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3649 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3651 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3652 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3655 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3657 [(set_attr "type" "delayed_compare")
3658 (set_attr "length" "4,8")])
3661 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3662 (compare:CC (zero_extend:SI
3664 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3665 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3667 (set (match_operand:SI 0 "gpc_reg_operand" "")
3668 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3671 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3673 (compare:CC (match_dup 0)
3677 ;; Note that we use "sle." instead of "sl." so that we can set
3678 ;; SHIFT_COUNT_TRUNCATED.
3680 (define_expand "ashlsi3"
3681 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3682 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3683 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3688 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3690 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3694 (define_insn "ashlsi3_power"
3695 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3696 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3697 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3698 (clobber (match_scratch:SI 3 "=q,X"))]
3702 {sli|slwi} %0,%1,%h2")
3704 (define_insn "ashlsi3_no_power"
3705 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3706 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3707 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3709 "{sl|slw}%I2 %0,%1,%h2")
3712 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3713 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3714 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3716 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3717 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3721 {sli.|slwi.} %3,%1,%h2
3724 [(set_attr "type" "delayed_compare")
3725 (set_attr "length" "4,4,8,8")])
3728 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3729 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3730 (match_operand:SI 2 "reg_or_cint_operand" ""))
3732 (clobber (match_scratch:SI 3 ""))
3733 (clobber (match_scratch:SI 4 ""))]
3734 "TARGET_POWER && reload_completed"
3735 [(parallel [(set (match_dup 3)
3736 (ashift:SI (match_dup 1) (match_dup 2)))
3737 (clobber (match_dup 4))])
3739 (compare:CC (match_dup 3)
3744 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3745 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3746 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3748 (clobber (match_scratch:SI 3 "=r,r"))]
3749 "! TARGET_POWER && TARGET_32BIT"
3751 {sl|slw}%I2. %3,%1,%h2
3753 [(set_attr "type" "delayed_compare")
3754 (set_attr "length" "4,8")])
3757 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3758 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3759 (match_operand:SI 2 "reg_or_cint_operand" ""))
3761 (clobber (match_scratch:SI 3 ""))]
3762 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3764 (ashift:SI (match_dup 1) (match_dup 2)))
3766 (compare:CC (match_dup 3)
3771 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3772 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3773 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3775 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3776 (ashift:SI (match_dup 1) (match_dup 2)))
3777 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3781 {sli.|slwi.} %0,%1,%h2
3784 [(set_attr "type" "delayed_compare")
3785 (set_attr "length" "4,4,8,8")])
3788 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3789 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3790 (match_operand:SI 2 "reg_or_cint_operand" ""))
3792 (set (match_operand:SI 0 "gpc_reg_operand" "")
3793 (ashift:SI (match_dup 1) (match_dup 2)))
3794 (clobber (match_scratch:SI 4 ""))]
3795 "TARGET_POWER && reload_completed"
3796 [(parallel [(set (match_dup 0)
3797 (ashift:SI (match_dup 1) (match_dup 2)))
3798 (clobber (match_dup 4))])
3800 (compare:CC (match_dup 0)
3805 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3806 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3807 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3809 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3810 (ashift:SI (match_dup 1) (match_dup 2)))]
3811 "! TARGET_POWER && TARGET_32BIT"
3813 {sl|slw}%I2. %0,%1,%h2
3815 [(set_attr "type" "delayed_compare")
3816 (set_attr "length" "4,8")])
3819 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3820 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3821 (match_operand:SI 2 "reg_or_cint_operand" ""))
3823 (set (match_operand:SI 0 "gpc_reg_operand" "")
3824 (ashift:SI (match_dup 1) (match_dup 2)))]
3825 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3827 (ashift:SI (match_dup 1) (match_dup 2)))
3829 (compare:CC (match_dup 0)
3833 (define_insn "rlwinm"
3834 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3835 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3836 (match_operand:SI 2 "const_int_operand" "i"))
3837 (match_operand:SI 3 "mask_operand" "n")))]
3838 "includes_lshift_p (operands[2], operands[3])"
3839 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3842 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3844 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3845 (match_operand:SI 2 "const_int_operand" "i,i"))
3846 (match_operand:SI 3 "mask_operand" "n,n"))
3848 (clobber (match_scratch:SI 4 "=r,r"))]
3849 "includes_lshift_p (operands[2], operands[3])"
3851 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3853 [(set_attr "type" "delayed_compare")
3854 (set_attr "length" "4,8")])
3857 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3859 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3860 (match_operand:SI 2 "const_int_operand" ""))
3861 (match_operand:SI 3 "mask_operand" ""))
3863 (clobber (match_scratch:SI 4 ""))]
3864 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3866 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3869 (compare:CC (match_dup 4)
3874 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3876 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3877 (match_operand:SI 2 "const_int_operand" "i,i"))
3878 (match_operand:SI 3 "mask_operand" "n,n"))
3880 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3881 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3882 "includes_lshift_p (operands[2], operands[3])"
3884 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3886 [(set_attr "type" "delayed_compare")
3887 (set_attr "length" "4,8")])
3890 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3892 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3893 (match_operand:SI 2 "const_int_operand" ""))
3894 (match_operand:SI 3 "mask_operand" ""))
3896 (set (match_operand:SI 0 "gpc_reg_operand" "")
3897 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3898 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3900 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3902 (compare:CC (match_dup 0)
3906 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3908 (define_expand "lshrsi3"
3909 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3910 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3911 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3916 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3918 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3922 (define_insn "lshrsi3_power"
3923 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3924 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3925 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3926 (clobber (match_scratch:SI 3 "=q,X,X"))]
3931 {s%A2i|s%A2wi} %0,%1,%h2")
3933 (define_insn "lshrsi3_no_power"
3934 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3935 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3936 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3940 {sr|srw}%I2 %0,%1,%h2")
3943 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3944 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3945 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3947 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3948 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3953 {s%A2i.|s%A2wi.} %3,%1,%h2
3957 [(set_attr "type" "delayed_compare")
3958 (set_attr "length" "4,4,4,8,8,8")])
3961 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3962 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3963 (match_operand:SI 2 "reg_or_cint_operand" ""))
3965 (clobber (match_scratch:SI 3 ""))
3966 (clobber (match_scratch:SI 4 ""))]
3967 "TARGET_POWER && reload_completed"
3968 [(parallel [(set (match_dup 3)
3969 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3970 (clobber (match_dup 4))])
3972 (compare:CC (match_dup 3)
3977 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3978 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3979 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3981 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3982 "! TARGET_POWER && TARGET_32BIT"
3985 {sr|srw}%I2. %3,%1,%h2
3988 [(set_attr "type" "delayed_compare")
3989 (set_attr "length" "4,4,8,8")])
3992 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3993 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3994 (match_operand:SI 2 "reg_or_cint_operand" ""))
3996 (clobber (match_scratch:SI 3 ""))]
3997 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3999 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4001 (compare:CC (match_dup 3)
4006 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4007 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4008 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4010 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4011 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4012 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4017 {s%A2i.|s%A2wi.} %0,%1,%h2
4021 [(set_attr "type" "delayed_compare")
4022 (set_attr "length" "4,4,4,8,8,8")])
4025 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4026 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4027 (match_operand:SI 2 "reg_or_cint_operand" ""))
4029 (set (match_operand:SI 0 "gpc_reg_operand" "")
4030 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4031 (clobber (match_scratch:SI 4 ""))]
4032 "TARGET_POWER && reload_completed"
4033 [(parallel [(set (match_dup 0)
4034 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4035 (clobber (match_dup 4))])
4037 (compare:CC (match_dup 0)
4042 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4043 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4044 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4046 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4047 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4048 "! TARGET_POWER && TARGET_32BIT"
4051 {sr|srw}%I2. %0,%1,%h2
4054 [(set_attr "type" "delayed_compare")
4055 (set_attr "length" "4,4,8,8")])
4058 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4059 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4060 (match_operand:SI 2 "reg_or_cint_operand" ""))
4062 (set (match_operand:SI 0 "gpc_reg_operand" "")
4063 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4064 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4066 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4068 (compare:CC (match_dup 0)
4073 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4074 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4075 (match_operand:SI 2 "const_int_operand" "i"))
4076 (match_operand:SI 3 "mask_operand" "n")))]
4077 "includes_rshift_p (operands[2], operands[3])"
4078 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4081 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4083 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4084 (match_operand:SI 2 "const_int_operand" "i,i"))
4085 (match_operand:SI 3 "mask_operand" "n,n"))
4087 (clobber (match_scratch:SI 4 "=r,r"))]
4088 "includes_rshift_p (operands[2], operands[3])"
4090 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4092 [(set_attr "type" "delayed_compare")
4093 (set_attr "length" "4,8")])
4096 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4098 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4099 (match_operand:SI 2 "const_int_operand" ""))
4100 (match_operand:SI 3 "mask_operand" ""))
4102 (clobber (match_scratch:SI 4 ""))]
4103 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4105 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4108 (compare:CC (match_dup 4)
4113 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4115 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4116 (match_operand:SI 2 "const_int_operand" "i,i"))
4117 (match_operand:SI 3 "mask_operand" "n,n"))
4119 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4120 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4121 "includes_rshift_p (operands[2], operands[3])"
4123 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4125 [(set_attr "type" "delayed_compare")
4126 (set_attr "length" "4,8")])
4129 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4131 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4132 (match_operand:SI 2 "const_int_operand" ""))
4133 (match_operand:SI 3 "mask_operand" ""))
4135 (set (match_operand:SI 0 "gpc_reg_operand" "")
4136 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4137 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4139 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4141 (compare:CC (match_dup 0)
4146 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4149 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4150 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4151 "includes_rshift_p (operands[2], GEN_INT (255))"
4152 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4155 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4159 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4160 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4162 (clobber (match_scratch:SI 3 "=r,r"))]
4163 "includes_rshift_p (operands[2], GEN_INT (255))"
4165 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4167 [(set_attr "type" "delayed_compare")
4168 (set_attr "length" "4,8")])
4171 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4175 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4176 (match_operand:SI 2 "const_int_operand" "")) 0))
4178 (clobber (match_scratch:SI 3 ""))]
4179 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4181 (zero_extend:SI (subreg:QI
4182 (lshiftrt:SI (match_dup 1)
4185 (compare:CC (match_dup 3)
4190 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4194 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4195 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4197 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4198 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4199 "includes_rshift_p (operands[2], GEN_INT (255))"
4201 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4203 [(set_attr "type" "delayed_compare")
4204 (set_attr "length" "4,8")])
4207 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4211 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4212 (match_operand:SI 2 "const_int_operand" "")) 0))
4214 (set (match_operand:SI 0 "gpc_reg_operand" "")
4215 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4216 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4218 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4220 (compare:CC (match_dup 0)
4225 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4228 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4229 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4230 "includes_rshift_p (operands[2], GEN_INT (65535))"
4231 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4234 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4238 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4239 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4241 (clobber (match_scratch:SI 3 "=r,r"))]
4242 "includes_rshift_p (operands[2], GEN_INT (65535))"
4244 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4246 [(set_attr "type" "delayed_compare")
4247 (set_attr "length" "4,8")])
4250 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4254 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4255 (match_operand:SI 2 "const_int_operand" "")) 0))
4257 (clobber (match_scratch:SI 3 ""))]
4258 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4260 (zero_extend:SI (subreg:HI
4261 (lshiftrt:SI (match_dup 1)
4264 (compare:CC (match_dup 3)
4269 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4273 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4274 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4276 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4277 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4278 "includes_rshift_p (operands[2], GEN_INT (65535))"
4280 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4282 [(set_attr "type" "delayed_compare")
4283 (set_attr "length" "4,8")])
4286 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4290 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4291 (match_operand:SI 2 "const_int_operand" "")) 0))
4293 (set (match_operand:SI 0 "gpc_reg_operand" "")
4294 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4295 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4297 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4299 (compare:CC (match_dup 0)
4304 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4306 (match_operand:SI 1 "gpc_reg_operand" "r"))
4307 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4313 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4315 (match_operand:SI 1 "gpc_reg_operand" "r"))
4316 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4322 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4324 (match_operand:SI 1 "gpc_reg_operand" "r"))
4325 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4331 (define_expand "ashrsi3"
4332 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4333 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4334 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4339 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4341 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4345 (define_insn "ashrsi3_power"
4346 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4347 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4348 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4349 (clobber (match_scratch:SI 3 "=q,X"))]
4353 {srai|srawi} %0,%1,%h2")
4355 (define_insn "ashrsi3_no_power"
4356 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4357 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4358 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4360 "{sra|sraw}%I2 %0,%1,%h2")
4363 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4364 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4365 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4367 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4368 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4372 {srai.|srawi.} %3,%1,%h2
4375 [(set_attr "type" "delayed_compare")
4376 (set_attr "length" "4,4,8,8")])
4379 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4380 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4381 (match_operand:SI 2 "reg_or_cint_operand" ""))
4383 (clobber (match_scratch:SI 3 ""))
4384 (clobber (match_scratch:SI 4 ""))]
4385 "TARGET_POWER && reload_completed"
4386 [(parallel [(set (match_dup 3)
4387 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4388 (clobber (match_dup 4))])
4390 (compare:CC (match_dup 3)
4395 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4396 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4397 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4399 (clobber (match_scratch:SI 3 "=r,r"))]
4402 {sra|sraw}%I2. %3,%1,%h2
4404 [(set_attr "type" "delayed_compare")
4405 (set_attr "length" "4,8")])
4408 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4409 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4410 (match_operand:SI 2 "reg_or_cint_operand" ""))
4412 (clobber (match_scratch:SI 3 ""))]
4413 "! TARGET_POWER && reload_completed"
4415 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4417 (compare:CC (match_dup 3)
4422 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4423 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4424 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4426 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4427 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4428 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4432 {srai.|srawi.} %0,%1,%h2
4435 [(set_attr "type" "delayed_compare")
4436 (set_attr "length" "4,4,8,8")])
4439 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4440 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4441 (match_operand:SI 2 "reg_or_cint_operand" ""))
4443 (set (match_operand:SI 0 "gpc_reg_operand" "")
4444 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4445 (clobber (match_scratch:SI 4 ""))]
4446 "TARGET_POWER && reload_completed"
4447 [(parallel [(set (match_dup 0)
4448 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4449 (clobber (match_dup 4))])
4451 (compare:CC (match_dup 0)
4456 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4457 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4458 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4460 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4461 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4464 {sra|sraw}%I2. %0,%1,%h2
4466 [(set_attr "type" "delayed_compare")
4467 (set_attr "length" "4,8")])
4470 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4471 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4472 (match_operand:SI 2 "reg_or_cint_operand" ""))
4474 (set (match_operand:SI 0 "gpc_reg_operand" "")
4475 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4476 "! TARGET_POWER && reload_completed"
4478 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4480 (compare:CC (match_dup 0)
4484 ;; Floating-point insns, excluding normal data motion.
4486 ;; PowerPC has a full set of single-precision floating point instructions.
4488 ;; For the POWER architecture, we pretend that we have both SFmode and
4489 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4490 ;; The only conversions we will do will be when storing to memory. In that
4491 ;; case, we will use the "frsp" instruction before storing.
4493 ;; Note that when we store into a single-precision memory location, we need to
4494 ;; use the frsp insn first. If the register being stored isn't dead, we
4495 ;; need a scratch register for the frsp. But this is difficult when the store
4496 ;; is done by reload. It is not incorrect to do the frsp on the register in
4497 ;; this case, we just lose precision that we would have otherwise gotten but
4498 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4500 (define_expand "extendsfdf2"
4501 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4502 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4503 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4506 (define_insn_and_split "*extendsfdf2_fpr"
4507 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4508 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4509 "TARGET_HARD_FLOAT && TARGET_FPRS"
4514 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4517 emit_note (NOTE_INSN_DELETED);
4520 [(set_attr "type" "fp,fp,fpload")])
4522 (define_expand "truncdfsf2"
4523 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4524 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4525 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4528 (define_insn "*truncdfsf2_fpr"
4529 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4530 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4531 "TARGET_HARD_FLOAT && TARGET_FPRS"
4533 [(set_attr "type" "fp")])
4535 (define_insn "aux_truncdfsf2"
4536 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4537 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4538 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4540 [(set_attr "type" "fp")])
4542 (define_expand "negsf2"
4543 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4544 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4548 (define_insn "*negsf2"
4549 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4550 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4551 "TARGET_HARD_FLOAT && TARGET_FPRS"
4553 [(set_attr "type" "fp")])
4555 (define_expand "abssf2"
4556 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4557 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4561 (define_insn "*abssf2"
4562 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4563 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4564 "TARGET_HARD_FLOAT && TARGET_FPRS"
4566 [(set_attr "type" "fp")])
4569 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4570 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4571 "TARGET_HARD_FLOAT && TARGET_FPRS"
4573 [(set_attr "type" "fp")])
4575 (define_expand "addsf3"
4576 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4577 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4578 (match_operand:SF 2 "gpc_reg_operand" "")))]
4583 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4584 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4585 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4586 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4588 [(set_attr "type" "fp")])
4591 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4592 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4593 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4594 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4595 "{fa|fadd} %0,%1,%2"
4596 [(set_attr "type" "fp")])
4598 (define_expand "subsf3"
4599 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4600 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4601 (match_operand:SF 2 "gpc_reg_operand" "")))]
4606 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4607 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4608 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4609 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4611 [(set_attr "type" "fp")])
4614 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4615 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4616 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4617 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4618 "{fs|fsub} %0,%1,%2"
4619 [(set_attr "type" "fp")])
4621 (define_expand "mulsf3"
4622 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4623 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4624 (match_operand:SF 2 "gpc_reg_operand" "")))]
4629 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4630 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4631 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4632 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4634 [(set_attr "type" "fp")])
4637 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4638 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4639 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4640 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4641 "{fm|fmul} %0,%1,%2"
4642 [(set_attr "type" "dmul")])
4645 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4646 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4647 "TARGET_PPC_GFXOPT && flag_finite_math_only"
4649 [(set_attr "type" "fp")])
4651 (define_expand "divsf3"
4652 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4653 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4654 (match_operand:SF 2 "gpc_reg_operand" "")))]
4657 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
4658 && flag_finite_math_only && !flag_trapping_math)
4660 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
4666 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4667 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4668 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4669 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4671 [(set_attr "type" "sdiv")])
4674 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4675 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4676 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4677 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4678 "{fd|fdiv} %0,%1,%2"
4679 [(set_attr "type" "ddiv")])
4682 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4683 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4684 (match_operand:SF 2 "gpc_reg_operand" "f"))
4685 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4686 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4687 "fmadds %0,%1,%2,%3"
4688 [(set_attr "type" "fp")])
4691 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4692 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4693 (match_operand:SF 2 "gpc_reg_operand" "f"))
4694 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4695 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4696 "{fma|fmadd} %0,%1,%2,%3"
4697 [(set_attr "type" "dmul")])
4700 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4701 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4702 (match_operand:SF 2 "gpc_reg_operand" "f"))
4703 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4704 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4705 "fmsubs %0,%1,%2,%3"
4706 [(set_attr "type" "fp")])
4709 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4710 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4711 (match_operand:SF 2 "gpc_reg_operand" "f"))
4712 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4713 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4714 "{fms|fmsub} %0,%1,%2,%3"
4715 [(set_attr "type" "dmul")])
4718 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4719 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4720 (match_operand:SF 2 "gpc_reg_operand" "f"))
4721 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4722 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4723 && HONOR_SIGNED_ZEROS (SFmode)"
4724 "fnmadds %0,%1,%2,%3"
4725 [(set_attr "type" "fp")])
4728 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4729 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4730 (match_operand:SF 2 "gpc_reg_operand" "f"))
4731 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4732 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4733 && ! HONOR_SIGNED_ZEROS (SFmode)"
4734 "fnmadds %0,%1,%2,%3"
4735 [(set_attr "type" "fp")])
4738 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4739 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4740 (match_operand:SF 2 "gpc_reg_operand" "f"))
4741 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4742 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4743 "{fnma|fnmadd} %0,%1,%2,%3"
4744 [(set_attr "type" "dmul")])
4747 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4748 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4749 (match_operand:SF 2 "gpc_reg_operand" "f"))
4750 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4751 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4752 && ! HONOR_SIGNED_ZEROS (SFmode)"
4753 "{fnma|fnmadd} %0,%1,%2,%3"
4754 [(set_attr "type" "dmul")])
4757 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4758 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4759 (match_operand:SF 2 "gpc_reg_operand" "f"))
4760 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4761 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4762 && HONOR_SIGNED_ZEROS (SFmode)"
4763 "fnmsubs %0,%1,%2,%3"
4764 [(set_attr "type" "fp")])
4767 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4768 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4769 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4770 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4771 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4772 && ! HONOR_SIGNED_ZEROS (SFmode)"
4773 "fnmsubs %0,%1,%2,%3"
4774 [(set_attr "type" "fp")])
4777 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4778 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4779 (match_operand:SF 2 "gpc_reg_operand" "f"))
4780 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4781 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4782 "{fnms|fnmsub} %0,%1,%2,%3"
4783 [(set_attr "type" "dmul")])
4786 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4787 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4788 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4789 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4790 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4791 && ! HONOR_SIGNED_ZEROS (SFmode)"
4792 "{fnms|fnmsub} %0,%1,%2,%3"
4793 [(set_attr "type" "fp")])
4795 (define_expand "sqrtsf2"
4796 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4797 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4798 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4802 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4803 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4804 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4806 [(set_attr "type" "ssqrt")])
4809 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4810 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4811 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4813 [(set_attr "type" "dsqrt")])
4815 (define_expand "copysignsf3"
4817 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
4819 (neg:SF (abs:SF (match_dup 1))))
4820 (set (match_operand:SF 0 "gpc_reg_operand" "")
4821 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
4825 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4826 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
4828 operands[3] = gen_reg_rtx (SFmode);
4829 operands[4] = gen_reg_rtx (SFmode);
4830 operands[5] = CONST0_RTX (SFmode);
4833 (define_expand "copysigndf3"
4835 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
4837 (neg:DF (abs:DF (match_dup 1))))
4838 (set (match_operand:DF 0 "gpc_reg_operand" "")
4839 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
4843 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4844 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
4846 operands[3] = gen_reg_rtx (DFmode);
4847 operands[4] = gen_reg_rtx (DFmode);
4848 operands[5] = CONST0_RTX (DFmode);
4851 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4852 ;; fsel instruction and some auxiliary computations. Then we just have a
4853 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4855 (define_expand "smaxsf3"
4856 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4857 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4858 (match_operand:SF 2 "gpc_reg_operand" ""))
4861 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4862 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4864 (define_expand "sminsf3"
4865 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4866 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4867 (match_operand:SF 2 "gpc_reg_operand" ""))
4870 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4871 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4874 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4875 (match_operator:SF 3 "min_max_operator"
4876 [(match_operand:SF 1 "gpc_reg_operand" "")
4877 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4878 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
4881 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4882 operands[1], operands[2]);
4886 (define_expand "movsicc"
4887 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4888 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4889 (match_operand:SI 2 "gpc_reg_operand" "")
4890 (match_operand:SI 3 "gpc_reg_operand" "")))]
4894 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4900 ;; We use the BASE_REGS for the isel input operands because, if rA is
4901 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4902 ;; because we may switch the operands and rB may end up being rA.
4904 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4905 ;; leave out the mode in operand 4 and use one pattern, but reload can
4906 ;; change the mode underneath our feet and then gets confused trying
4907 ;; to reload the value.
4908 (define_insn "isel_signed"
4909 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4911 (match_operator 1 "comparison_operator"
4912 [(match_operand:CC 4 "cc_reg_operand" "y")
4914 (match_operand:SI 2 "gpc_reg_operand" "b")
4915 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4918 { return output_isel (operands); }"
4919 [(set_attr "length" "4")])
4921 (define_insn "isel_unsigned"
4922 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4924 (match_operator 1 "comparison_operator"
4925 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4927 (match_operand:SI 2 "gpc_reg_operand" "b")
4928 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4931 { return output_isel (operands); }"
4932 [(set_attr "length" "4")])
4934 (define_expand "movsfcc"
4935 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4936 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4937 (match_operand:SF 2 "gpc_reg_operand" "")
4938 (match_operand:SF 3 "gpc_reg_operand" "")))]
4939 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4942 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4948 (define_insn "*fselsfsf4"
4949 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4950 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4951 (match_operand:SF 4 "zero_fp_constant" "F"))
4952 (match_operand:SF 2 "gpc_reg_operand" "f")
4953 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4954 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4956 [(set_attr "type" "fp")])
4958 (define_insn "*fseldfsf4"
4959 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4960 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4961 (match_operand:DF 4 "zero_fp_constant" "F"))
4962 (match_operand:SF 2 "gpc_reg_operand" "f")
4963 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4964 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4966 [(set_attr "type" "fp")])
4968 (define_expand "negdf2"
4969 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4970 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4971 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4974 (define_insn "*negdf2_fpr"
4975 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4976 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4977 "TARGET_HARD_FLOAT && TARGET_FPRS"
4979 [(set_attr "type" "fp")])
4981 (define_expand "absdf2"
4982 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4983 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4984 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4987 (define_insn "*absdf2_fpr"
4988 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4989 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4990 "TARGET_HARD_FLOAT && TARGET_FPRS"
4992 [(set_attr "type" "fp")])
4994 (define_insn "*nabsdf2_fpr"
4995 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4996 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4997 "TARGET_HARD_FLOAT && TARGET_FPRS"
4999 [(set_attr "type" "fp")])
5001 (define_expand "adddf3"
5002 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5003 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5004 (match_operand:DF 2 "gpc_reg_operand" "")))]
5005 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5008 (define_insn "*adddf3_fpr"
5009 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5010 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5011 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5012 "TARGET_HARD_FLOAT && TARGET_FPRS"
5013 "{fa|fadd} %0,%1,%2"
5014 [(set_attr "type" "fp")])
5016 (define_expand "subdf3"
5017 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5018 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5019 (match_operand:DF 2 "gpc_reg_operand" "")))]
5020 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5023 (define_insn "*subdf3_fpr"
5024 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5025 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5026 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5027 "TARGET_HARD_FLOAT && TARGET_FPRS"
5028 "{fs|fsub} %0,%1,%2"
5029 [(set_attr "type" "fp")])
5031 (define_expand "muldf3"
5032 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5033 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5034 (match_operand:DF 2 "gpc_reg_operand" "")))]
5035 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5038 (define_insn "*muldf3_fpr"
5039 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5040 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5041 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5042 "TARGET_HARD_FLOAT && TARGET_FPRS"
5043 "{fm|fmul} %0,%1,%2"
5044 [(set_attr "type" "dmul")])
5047 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5048 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5049 "TARGET_POPCNTB && flag_finite_math_only"
5051 [(set_attr "type" "fp")])
5053 (define_expand "divdf3"
5054 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5055 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5056 (match_operand:DF 2 "gpc_reg_operand" "")))]
5057 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5059 if (swdiv && !optimize_size && TARGET_POPCNTB
5060 && flag_finite_math_only && !flag_trapping_math)
5062 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5067 (define_insn "*divdf3_fpr"
5068 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5069 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5070 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5071 "TARGET_HARD_FLOAT && TARGET_FPRS"
5072 "{fd|fdiv} %0,%1,%2"
5073 [(set_attr "type" "ddiv")])
5076 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5077 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5078 (match_operand:DF 2 "gpc_reg_operand" "f"))
5079 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5080 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5081 "{fma|fmadd} %0,%1,%2,%3"
5082 [(set_attr "type" "dmul")])
5085 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5086 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5087 (match_operand:DF 2 "gpc_reg_operand" "f"))
5088 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5089 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5090 "{fms|fmsub} %0,%1,%2,%3"
5091 [(set_attr "type" "dmul")])
5094 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5095 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5096 (match_operand:DF 2 "gpc_reg_operand" "f"))
5097 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5098 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5099 && HONOR_SIGNED_ZEROS (DFmode)"
5100 "{fnma|fnmadd} %0,%1,%2,%3"
5101 [(set_attr "type" "dmul")])
5104 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5105 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5106 (match_operand:DF 2 "gpc_reg_operand" "f"))
5107 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5108 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5109 && ! HONOR_SIGNED_ZEROS (DFmode)"
5110 "{fnma|fnmadd} %0,%1,%2,%3"
5111 [(set_attr "type" "dmul")])
5114 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5115 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5116 (match_operand:DF 2 "gpc_reg_operand" "f"))
5117 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5118 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5119 && HONOR_SIGNED_ZEROS (DFmode)"
5120 "{fnms|fnmsub} %0,%1,%2,%3"
5121 [(set_attr "type" "dmul")])
5124 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5125 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5126 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5127 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5128 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5129 && ! HONOR_SIGNED_ZEROS (DFmode)"
5130 "{fnms|fnmsub} %0,%1,%2,%3"
5131 [(set_attr "type" "dmul")])
5133 (define_insn "sqrtdf2"
5134 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5135 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5136 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5138 [(set_attr "type" "dsqrt")])
5140 ;; The conditional move instructions allow us to perform max and min
5141 ;; operations even when
5143 (define_expand "smaxdf3"
5144 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5145 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5146 (match_operand:DF 2 "gpc_reg_operand" ""))
5149 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5150 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5152 (define_expand "smindf3"
5153 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5154 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5155 (match_operand:DF 2 "gpc_reg_operand" ""))
5158 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5159 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5162 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5163 (match_operator:DF 3 "min_max_operator"
5164 [(match_operand:DF 1 "gpc_reg_operand" "")
5165 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5166 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5169 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5170 operands[1], operands[2]);
5174 (define_expand "movdfcc"
5175 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5176 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5177 (match_operand:DF 2 "gpc_reg_operand" "")
5178 (match_operand:DF 3 "gpc_reg_operand" "")))]
5179 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5182 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5188 (define_insn "*fseldfdf4"
5189 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5190 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5191 (match_operand:DF 4 "zero_fp_constant" "F"))
5192 (match_operand:DF 2 "gpc_reg_operand" "f")
5193 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5194 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5196 [(set_attr "type" "fp")])
5198 (define_insn "*fselsfdf4"
5199 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5200 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5201 (match_operand:SF 4 "zero_fp_constant" "F"))
5202 (match_operand:DF 2 "gpc_reg_operand" "f")
5203 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5206 [(set_attr "type" "fp")])
5208 ;; Conversions to and from floating-point.
5210 (define_expand "fixuns_truncsfsi2"
5211 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5212 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5213 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5216 (define_expand "fix_truncsfsi2"
5217 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5218 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5219 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5222 ; For each of these conversions, there is a define_expand, a define_insn
5223 ; with a '#' template, and a define_split (with C code). The idea is
5224 ; to allow constant folding with the template of the define_insn,
5225 ; then to have the insns split later (between sched1 and final).
5227 (define_expand "floatsidf2"
5228 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5229 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5232 (clobber (match_dup 4))
5233 (clobber (match_dup 5))
5234 (clobber (match_dup 6))])]
5235 "TARGET_HARD_FLOAT && TARGET_FPRS"
5238 if (TARGET_E500_DOUBLE)
5240 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5243 if (TARGET_POWERPC64)
5245 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5246 rtx t1 = gen_reg_rtx (DImode);
5247 rtx t2 = gen_reg_rtx (DImode);
5248 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5252 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5253 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5254 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5255 operands[5] = gen_reg_rtx (DFmode);
5256 operands[6] = gen_reg_rtx (SImode);
5259 (define_insn_and_split "*floatsidf2_internal"
5260 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5261 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5262 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5263 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5264 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5265 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5266 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5267 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5269 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5273 rtx lowword, highword;
5274 gcc_assert (MEM_P (operands[4]));
5275 highword = adjust_address (operands[4], SImode, 0);
5276 lowword = adjust_address (operands[4], SImode, 4);
5277 if (! WORDS_BIG_ENDIAN)
5280 tmp = highword; highword = lowword; lowword = tmp;
5283 emit_insn (gen_xorsi3 (operands[6], operands[1],
5284 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5285 emit_move_insn (lowword, operands[6]);
5286 emit_move_insn (highword, operands[2]);
5287 emit_move_insn (operands[5], operands[4]);
5288 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5291 [(set_attr "length" "24")])
5293 (define_expand "floatunssisf2"
5294 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5295 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5296 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5299 (define_expand "floatunssidf2"
5300 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5301 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5304 (clobber (match_dup 4))
5305 (clobber (match_dup 5))])]
5306 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5309 if (TARGET_E500_DOUBLE)
5311 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5314 if (TARGET_POWERPC64)
5316 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5317 rtx t1 = gen_reg_rtx (DImode);
5318 rtx t2 = gen_reg_rtx (DImode);
5319 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5324 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5325 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5326 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5327 operands[5] = gen_reg_rtx (DFmode);
5330 (define_insn_and_split "*floatunssidf2_internal"
5331 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5332 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5333 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5334 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5335 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5336 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5337 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5339 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5343 rtx lowword, highword;
5344 gcc_assert (MEM_P (operands[4]));
5345 highword = adjust_address (operands[4], SImode, 0);
5346 lowword = adjust_address (operands[4], SImode, 4);
5347 if (! WORDS_BIG_ENDIAN)
5350 tmp = highword; highword = lowword; lowword = tmp;
5353 emit_move_insn (lowword, operands[1]);
5354 emit_move_insn (highword, operands[2]);
5355 emit_move_insn (operands[5], operands[4]);
5356 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5359 [(set_attr "length" "20")])
5361 (define_expand "fix_truncdfsi2"
5362 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5363 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5364 (clobber (match_dup 2))
5365 (clobber (match_dup 3))])]
5366 "(TARGET_POWER2 || TARGET_POWERPC)
5367 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5370 if (TARGET_E500_DOUBLE)
5372 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5375 operands[2] = gen_reg_rtx (DImode);
5376 if (TARGET_PPC_GFXOPT)
5378 rtx orig_dest = operands[0];
5379 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5380 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5381 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5383 if (operands[0] != orig_dest)
5384 emit_move_insn (orig_dest, operands[0]);
5387 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5390 (define_insn_and_split "*fix_truncdfsi2_internal"
5391 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5392 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5393 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5394 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5395 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5397 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5402 gcc_assert (MEM_P (operands[3]));
5403 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5405 emit_insn (gen_fctiwz (operands[2], operands[1]));
5406 emit_move_insn (operands[3], operands[2]);
5407 emit_move_insn (operands[0], lowword);
5410 [(set_attr "length" "16")])
5412 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5413 [(set (match_operand:SI 0 "memory_operand" "=Z")
5414 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5415 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5416 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5417 && TARGET_PPC_GFXOPT"
5423 emit_insn (gen_fctiwz (operands[2], operands[1]));
5424 emit_insn (gen_stfiwx (operands[0], operands[2]));
5427 [(set_attr "length" "16")])
5429 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5430 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5431 ; because the first makes it clear that operand 0 is not live
5432 ; before the instruction.
5433 (define_insn "fctiwz"
5434 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5435 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5437 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5438 "{fcirz|fctiwz} %0,%1"
5439 [(set_attr "type" "fp")])
5441 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5442 (define_insn "stfiwx"
5443 [(set (match_operand:SI 0 "memory_operand" "=Z")
5444 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
5448 [(set_attr "type" "fpstore")])
5450 (define_expand "floatsisf2"
5451 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5452 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5453 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5456 (define_insn "floatdidf2"
5457 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5458 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5459 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5461 [(set_attr "type" "fp")])
5463 (define_insn_and_split "floatsidf_ppc64"
5464 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5465 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5466 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5467 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5468 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5469 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5472 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5473 (set (match_dup 2) (match_dup 3))
5474 (set (match_dup 4) (match_dup 2))
5475 (set (match_dup 0) (float:DF (match_dup 4)))]
5478 (define_insn_and_split "floatunssidf_ppc64"
5479 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5480 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5481 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5482 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5483 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5484 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5487 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5488 (set (match_dup 2) (match_dup 3))
5489 (set (match_dup 4) (match_dup 2))
5490 (set (match_dup 0) (float:DF (match_dup 4)))]
5493 (define_insn "fix_truncdfdi2"
5494 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5495 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5496 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5498 [(set_attr "type" "fp")])
5500 (define_expand "floatdisf2"
5501 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5502 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5503 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5506 rtx val = operands[1];
5507 if (!flag_unsafe_math_optimizations)
5509 rtx label = gen_label_rtx ();
5510 val = gen_reg_rtx (DImode);
5511 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5514 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5518 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5519 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5520 ;; from double rounding.
5521 (define_insn_and_split "floatdisf2_internal1"
5522 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5523 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5524 (clobber (match_scratch:DF 2 "=f"))]
5525 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5527 "&& reload_completed"
5529 (float:DF (match_dup 1)))
5531 (float_truncate:SF (match_dup 2)))]
5534 ;; Twiddles bits to avoid double rounding.
5535 ;; Bits that might be truncated when converting to DFmode are replaced
5536 ;; by a bit that won't be lost at that stage, but is below the SFmode
5537 ;; rounding position.
5538 (define_expand "floatdisf2_internal2"
5539 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5541 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5543 (clobber (scratch:CC))])
5544 (set (match_dup 3) (plus:DI (match_dup 3)
5546 (set (match_dup 0) (plus:DI (match_dup 0)
5548 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5550 (set (match_dup 0) (ior:DI (match_dup 0)
5552 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
5554 (clobber (scratch:CC))])
5555 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5556 (label_ref (match_operand:DI 2 "" ""))
5558 (set (match_dup 0) (match_dup 1))]
5559 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5562 operands[3] = gen_reg_rtx (DImode);
5563 operands[4] = gen_reg_rtx (CCUNSmode);
5566 ;; Define the DImode operations that can be done in a small number
5567 ;; of instructions. The & constraints are to prevent the register
5568 ;; allocator from allocating registers that overlap with the inputs
5569 ;; (for example, having an input in 7,8 and an output in 6,7). We
5570 ;; also allow for the output being the same as one of the inputs.
5572 (define_insn "*adddi3_noppc64"
5573 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5574 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5575 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5576 "! TARGET_POWERPC64"
5579 if (WORDS_BIG_ENDIAN)
5580 return (GET_CODE (operands[2])) != CONST_INT
5581 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5582 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5584 return (GET_CODE (operands[2])) != CONST_INT
5585 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5586 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5588 [(set_attr "type" "two")
5589 (set_attr "length" "8")])
5591 (define_insn "*subdi3_noppc64"
5592 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5593 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5594 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5595 "! TARGET_POWERPC64"
5598 if (WORDS_BIG_ENDIAN)
5599 return (GET_CODE (operands[1]) != CONST_INT)
5600 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5601 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5603 return (GET_CODE (operands[1]) != CONST_INT)
5604 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5605 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5607 [(set_attr "type" "two")
5608 (set_attr "length" "8")])
5610 (define_insn "*negdi2_noppc64"
5611 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5612 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5613 "! TARGET_POWERPC64"
5616 return (WORDS_BIG_ENDIAN)
5617 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5618 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5620 [(set_attr "type" "two")
5621 (set_attr "length" "8")])
5623 (define_expand "mulsidi3"
5624 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5625 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5626 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5627 "! TARGET_POWERPC64"
5630 if (! TARGET_POWER && ! TARGET_POWERPC)
5632 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5633 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5634 emit_insn (gen_mull_call ());
5635 if (WORDS_BIG_ENDIAN)
5636 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5639 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5640 gen_rtx_REG (SImode, 3));
5641 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5642 gen_rtx_REG (SImode, 4));
5646 else if (TARGET_POWER)
5648 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5653 (define_insn "mulsidi3_mq"
5654 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5655 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5656 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5657 (clobber (match_scratch:SI 3 "=q"))]
5659 "mul %0,%1,%2\;mfmq %L0"
5660 [(set_attr "type" "imul")
5661 (set_attr "length" "8")])
5663 (define_insn "*mulsidi3_no_mq"
5664 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5665 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5666 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5667 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5670 return (WORDS_BIG_ENDIAN)
5671 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5672 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5674 [(set_attr "type" "imul")
5675 (set_attr "length" "8")])
5678 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5679 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5680 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5681 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5684 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5685 (sign_extend:DI (match_dup 2)))
5688 (mult:SI (match_dup 1)
5692 int endian = (WORDS_BIG_ENDIAN == 0);
5693 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5694 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5697 (define_expand "umulsidi3"
5698 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5699 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5700 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5701 "TARGET_POWERPC && ! TARGET_POWERPC64"
5706 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5711 (define_insn "umulsidi3_mq"
5712 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5713 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5714 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5715 (clobber (match_scratch:SI 3 "=q"))]
5716 "TARGET_POWERPC && TARGET_POWER"
5719 return (WORDS_BIG_ENDIAN)
5720 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5721 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5723 [(set_attr "type" "imul")
5724 (set_attr "length" "8")])
5726 (define_insn "*umulsidi3_no_mq"
5727 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5728 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5729 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5730 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5733 return (WORDS_BIG_ENDIAN)
5734 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5735 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5737 [(set_attr "type" "imul")
5738 (set_attr "length" "8")])
5741 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5742 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5743 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5744 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5747 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5748 (zero_extend:DI (match_dup 2)))
5751 (mult:SI (match_dup 1)
5755 int endian = (WORDS_BIG_ENDIAN == 0);
5756 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5757 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5760 (define_expand "smulsi3_highpart"
5761 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5763 (lshiftrt:DI (mult:DI (sign_extend:DI
5764 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5766 (match_operand:SI 2 "gpc_reg_operand" "r")))
5771 if (! TARGET_POWER && ! TARGET_POWERPC)
5773 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5774 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5775 emit_insn (gen_mulh_call ());
5776 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5779 else if (TARGET_POWER)
5781 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5786 (define_insn "smulsi3_highpart_mq"
5787 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5789 (lshiftrt:DI (mult:DI (sign_extend:DI
5790 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5792 (match_operand:SI 2 "gpc_reg_operand" "r")))
5794 (clobber (match_scratch:SI 3 "=q"))]
5797 [(set_attr "type" "imul")])
5799 (define_insn "*smulsi3_highpart_no_mq"
5800 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5802 (lshiftrt:DI (mult:DI (sign_extend:DI
5803 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5805 (match_operand:SI 2 "gpc_reg_operand" "r")))
5807 "TARGET_POWERPC && ! TARGET_POWER"
5809 [(set_attr "type" "imul")])
5811 (define_expand "umulsi3_highpart"
5812 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5814 (lshiftrt:DI (mult:DI (zero_extend:DI
5815 (match_operand:SI 1 "gpc_reg_operand" ""))
5817 (match_operand:SI 2 "gpc_reg_operand" "")))
5824 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5829 (define_insn "umulsi3_highpart_mq"
5830 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5832 (lshiftrt:DI (mult:DI (zero_extend:DI
5833 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5835 (match_operand:SI 2 "gpc_reg_operand" "r")))
5837 (clobber (match_scratch:SI 3 "=q"))]
5838 "TARGET_POWERPC && TARGET_POWER"
5840 [(set_attr "type" "imul")])
5842 (define_insn "*umulsi3_highpart_no_mq"
5843 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5845 (lshiftrt:DI (mult:DI (zero_extend:DI
5846 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5848 (match_operand:SI 2 "gpc_reg_operand" "r")))
5850 "TARGET_POWERPC && ! TARGET_POWER"
5852 [(set_attr "type" "imul")])
5854 ;; If operands 0 and 2 are in the same register, we have a problem. But
5855 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5856 ;; why we have the strange constraints below.
5857 (define_insn "ashldi3_power"
5858 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5859 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5860 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5861 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5864 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5865 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5866 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5867 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5868 [(set_attr "length" "8")])
5870 (define_insn "lshrdi3_power"
5871 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5872 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5873 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5874 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5877 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5878 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5879 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5880 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5881 [(set_attr "length" "8")])
5883 ;; Shift by a variable amount is too complex to be worth open-coding. We
5884 ;; just handle shifts by constants.
5885 (define_insn "ashrdi3_power"
5886 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5887 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5888 (match_operand:SI 2 "const_int_operand" "M,i")))
5889 (clobber (match_scratch:SI 3 "=X,q"))]
5892 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5893 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5894 [(set_attr "length" "8")])
5896 (define_insn "ashrdi3_no_power"
5897 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5898 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5899 (match_operand:SI 2 "const_int_operand" "M,i")))]
5900 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5902 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5903 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5904 [(set_attr "type" "two,three")
5905 (set_attr "length" "8,12")])
5907 (define_insn "*ashrdisi3_noppc64"
5908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5909 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5910 (const_int 32)) 4))]
5911 "TARGET_32BIT && !TARGET_POWERPC64"
5914 if (REGNO (operands[0]) == REGNO (operands[1]))
5917 return \"mr %0,%1\";
5919 [(set_attr "length" "4")])
5922 ;; PowerPC64 DImode operations.
5924 (define_insn_and_split "absdi2"
5925 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5926 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5927 (clobber (match_scratch:DI 2 "=&r,&r"))]
5930 "&& reload_completed"
5931 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5932 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5933 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5936 (define_insn_and_split "*nabsdi2"
5937 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5938 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5939 (clobber (match_scratch:DI 2 "=&r,&r"))]
5942 "&& reload_completed"
5943 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5944 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5945 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5948 (define_insn "muldi3"
5949 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5950 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
5951 (match_operand:DI 2 "gpc_reg_operand" "r")))]
5954 [(set_attr "type" "lmul")])
5956 (define_insn "*muldi3_internal1"
5957 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5958 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5959 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5961 (clobber (match_scratch:DI 3 "=r,r"))]
5966 [(set_attr "type" "lmul_compare")
5967 (set_attr "length" "4,8")])
5970 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5971 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
5972 (match_operand:DI 2 "gpc_reg_operand" ""))
5974 (clobber (match_scratch:DI 3 ""))]
5975 "TARGET_POWERPC64 && reload_completed"
5977 (mult:DI (match_dup 1) (match_dup 2)))
5979 (compare:CC (match_dup 3)
5983 (define_insn "*muldi3_internal2"
5984 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5985 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
5986 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5988 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5989 (mult:DI (match_dup 1) (match_dup 2)))]
5994 [(set_attr "type" "lmul_compare")
5995 (set_attr "length" "4,8")])
5998 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5999 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6000 (match_operand:DI 2 "gpc_reg_operand" ""))
6002 (set (match_operand:DI 0 "gpc_reg_operand" "")
6003 (mult:DI (match_dup 1) (match_dup 2)))]
6004 "TARGET_POWERPC64 && reload_completed"
6006 (mult:DI (match_dup 1) (match_dup 2)))
6008 (compare:CC (match_dup 0)
6012 (define_insn "smuldi3_highpart"
6013 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6015 (lshiftrt:TI (mult:TI (sign_extend:TI
6016 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6018 (match_operand:DI 2 "gpc_reg_operand" "r")))
6022 [(set_attr "type" "lmul")])
6024 (define_insn "umuldi3_highpart"
6025 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6027 (lshiftrt:TI (mult:TI (zero_extend:TI
6028 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6030 (match_operand:DI 2 "gpc_reg_operand" "r")))
6034 [(set_attr "type" "lmul")])
6036 (define_expand "divdi3"
6037 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6038 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6039 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6043 if (GET_CODE (operands[2]) == CONST_INT
6044 && INTVAL (operands[2]) > 0
6045 && exact_log2 (INTVAL (operands[2])) >= 0)
6048 operands[2] = force_reg (DImode, operands[2]);
6051 (define_expand "moddi3"
6052 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6053 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6054 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6062 if (GET_CODE (operands[2]) != CONST_INT
6063 || INTVAL (operands[2]) <= 0
6064 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6067 temp1 = gen_reg_rtx (DImode);
6068 temp2 = gen_reg_rtx (DImode);
6070 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6071 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6072 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6077 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6078 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6079 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6081 "sradi %0,%1,%p2\;addze %0,%0"
6082 [(set_attr "type" "two")
6083 (set_attr "length" "8")])
6086 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6087 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6088 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6090 (clobber (match_scratch:DI 3 "=r,r"))]
6093 sradi %3,%1,%p2\;addze. %3,%3
6095 [(set_attr "type" "compare")
6096 (set_attr "length" "8,12")])
6099 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6100 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6101 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6103 (clobber (match_scratch:DI 3 ""))]
6104 "TARGET_POWERPC64 && reload_completed"
6106 (div:DI (match_dup 1) (match_dup 2)))
6108 (compare:CC (match_dup 3)
6113 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6114 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6115 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6117 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6118 (div:DI (match_dup 1) (match_dup 2)))]
6121 sradi %0,%1,%p2\;addze. %0,%0
6123 [(set_attr "type" "compare")
6124 (set_attr "length" "8,12")])
6127 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6128 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6129 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6131 (set (match_operand:DI 0 "gpc_reg_operand" "")
6132 (div:DI (match_dup 1) (match_dup 2)))]
6133 "TARGET_POWERPC64 && reload_completed"
6135 (div:DI (match_dup 1) (match_dup 2)))
6137 (compare:CC (match_dup 0)
6142 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6143 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6144 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6147 [(set_attr "type" "ldiv")])
6149 (define_insn "udivdi3"
6150 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6151 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6152 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6155 [(set_attr "type" "ldiv")])
6157 (define_insn "rotldi3"
6158 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6159 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6160 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6162 "rld%I2cl %0,%1,%H2,0")
6164 (define_insn "*rotldi3_internal2"
6165 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6166 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6167 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6169 (clobber (match_scratch:DI 3 "=r,r"))]
6172 rld%I2cl. %3,%1,%H2,0
6174 [(set_attr "type" "delayed_compare")
6175 (set_attr "length" "4,8")])
6178 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6179 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6180 (match_operand:DI 2 "reg_or_cint_operand" ""))
6182 (clobber (match_scratch:DI 3 ""))]
6183 "TARGET_POWERPC64 && reload_completed"
6185 (rotate:DI (match_dup 1) (match_dup 2)))
6187 (compare:CC (match_dup 3)
6191 (define_insn "*rotldi3_internal3"
6192 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6193 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6194 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6196 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6197 (rotate:DI (match_dup 1) (match_dup 2)))]
6200 rld%I2cl. %0,%1,%H2,0
6202 [(set_attr "type" "delayed_compare")
6203 (set_attr "length" "4,8")])
6206 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6207 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6208 (match_operand:DI 2 "reg_or_cint_operand" ""))
6210 (set (match_operand:DI 0 "gpc_reg_operand" "")
6211 (rotate:DI (match_dup 1) (match_dup 2)))]
6212 "TARGET_POWERPC64 && reload_completed"
6214 (rotate:DI (match_dup 1) (match_dup 2)))
6216 (compare:CC (match_dup 0)
6220 (define_insn "*rotldi3_internal4"
6221 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6222 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6223 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6224 (match_operand:DI 3 "mask64_operand" "n")))]
6226 "rld%I2c%B3 %0,%1,%H2,%S3")
6228 (define_insn "*rotldi3_internal5"
6229 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6231 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6232 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6233 (match_operand:DI 3 "mask64_operand" "n,n"))
6235 (clobber (match_scratch:DI 4 "=r,r"))]
6238 rld%I2c%B3. %4,%1,%H2,%S3
6240 [(set_attr "type" "delayed_compare")
6241 (set_attr "length" "4,8")])
6244 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6246 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6247 (match_operand:DI 2 "reg_or_cint_operand" ""))
6248 (match_operand:DI 3 "mask64_operand" ""))
6250 (clobber (match_scratch:DI 4 ""))]
6251 "TARGET_POWERPC64 && reload_completed"
6253 (and:DI (rotate:DI (match_dup 1)
6257 (compare:CC (match_dup 4)
6261 (define_insn "*rotldi3_internal6"
6262 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6264 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6265 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6266 (match_operand:DI 3 "mask64_operand" "n,n"))
6268 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6269 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6272 rld%I2c%B3. %0,%1,%H2,%S3
6274 [(set_attr "type" "delayed_compare")
6275 (set_attr "length" "4,8")])
6278 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6280 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6281 (match_operand:DI 2 "reg_or_cint_operand" ""))
6282 (match_operand:DI 3 "mask64_operand" ""))
6284 (set (match_operand:DI 0 "gpc_reg_operand" "")
6285 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6286 "TARGET_POWERPC64 && reload_completed"
6288 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6290 (compare:CC (match_dup 0)
6294 (define_insn "*rotldi3_internal7"
6295 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6298 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6299 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6301 "rld%I2cl %0,%1,%H2,56")
6303 (define_insn "*rotldi3_internal8"
6304 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6305 (compare:CC (zero_extend:DI
6307 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6308 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6310 (clobber (match_scratch:DI 3 "=r,r"))]
6313 rld%I2cl. %3,%1,%H2,56
6315 [(set_attr "type" "delayed_compare")
6316 (set_attr "length" "4,8")])
6319 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6320 (compare:CC (zero_extend:DI
6322 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6323 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6325 (clobber (match_scratch:DI 3 ""))]
6326 "TARGET_POWERPC64 && reload_completed"
6328 (zero_extend:DI (subreg:QI
6329 (rotate:DI (match_dup 1)
6332 (compare:CC (match_dup 3)
6336 (define_insn "*rotldi3_internal9"
6337 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6338 (compare:CC (zero_extend:DI
6340 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6341 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6343 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6344 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6347 rld%I2cl. %0,%1,%H2,56
6349 [(set_attr "type" "delayed_compare")
6350 (set_attr "length" "4,8")])
6353 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6354 (compare:CC (zero_extend:DI
6356 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6357 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6359 (set (match_operand:DI 0 "gpc_reg_operand" "")
6360 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6361 "TARGET_POWERPC64 && reload_completed"
6363 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6365 (compare:CC (match_dup 0)
6369 (define_insn "*rotldi3_internal10"
6370 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6373 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6374 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6376 "rld%I2cl %0,%1,%H2,48")
6378 (define_insn "*rotldi3_internal11"
6379 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6380 (compare:CC (zero_extend:DI
6382 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6383 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6385 (clobber (match_scratch:DI 3 "=r,r"))]
6388 rld%I2cl. %3,%1,%H2,48
6390 [(set_attr "type" "delayed_compare")
6391 (set_attr "length" "4,8")])
6394 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6395 (compare:CC (zero_extend:DI
6397 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6398 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6400 (clobber (match_scratch:DI 3 ""))]
6401 "TARGET_POWERPC64 && reload_completed"
6403 (zero_extend:DI (subreg:HI
6404 (rotate:DI (match_dup 1)
6407 (compare:CC (match_dup 3)
6411 (define_insn "*rotldi3_internal12"
6412 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6413 (compare:CC (zero_extend:DI
6415 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6416 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6418 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6419 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6422 rld%I2cl. %0,%1,%H2,48
6424 [(set_attr "type" "delayed_compare")
6425 (set_attr "length" "4,8")])
6428 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6429 (compare:CC (zero_extend:DI
6431 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6432 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6434 (set (match_operand:DI 0 "gpc_reg_operand" "")
6435 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6436 "TARGET_POWERPC64 && reload_completed"
6438 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6440 (compare:CC (match_dup 0)
6444 (define_insn "*rotldi3_internal13"
6445 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6448 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6449 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6451 "rld%I2cl %0,%1,%H2,32")
6453 (define_insn "*rotldi3_internal14"
6454 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6455 (compare:CC (zero_extend:DI
6457 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6458 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6460 (clobber (match_scratch:DI 3 "=r,r"))]
6463 rld%I2cl. %3,%1,%H2,32
6465 [(set_attr "type" "delayed_compare")
6466 (set_attr "length" "4,8")])
6469 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6470 (compare:CC (zero_extend:DI
6472 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6473 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6475 (clobber (match_scratch:DI 3 ""))]
6476 "TARGET_POWERPC64 && reload_completed"
6478 (zero_extend:DI (subreg:SI
6479 (rotate:DI (match_dup 1)
6482 (compare:CC (match_dup 3)
6486 (define_insn "*rotldi3_internal15"
6487 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6488 (compare:CC (zero_extend:DI
6490 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6491 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6493 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6494 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6497 rld%I2cl. %0,%1,%H2,32
6499 [(set_attr "type" "delayed_compare")
6500 (set_attr "length" "4,8")])
6503 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6504 (compare:CC (zero_extend:DI
6506 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6507 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6509 (set (match_operand:DI 0 "gpc_reg_operand" "")
6510 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6511 "TARGET_POWERPC64 && reload_completed"
6513 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6515 (compare:CC (match_dup 0)
6519 (define_expand "ashldi3"
6520 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6521 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6522 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6523 "TARGET_POWERPC64 || TARGET_POWER"
6526 if (TARGET_POWERPC64)
6528 else if (TARGET_POWER)
6530 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6537 (define_insn "*ashldi3_internal1"
6538 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6539 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6540 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6544 (define_insn "*ashldi3_internal2"
6545 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6546 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6547 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6549 (clobber (match_scratch:DI 3 "=r,r"))]
6554 [(set_attr "type" "delayed_compare")
6555 (set_attr "length" "4,8")])
6558 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6559 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6560 (match_operand:SI 2 "reg_or_cint_operand" ""))
6562 (clobber (match_scratch:DI 3 ""))]
6563 "TARGET_POWERPC64 && reload_completed"
6565 (ashift:DI (match_dup 1) (match_dup 2)))
6567 (compare:CC (match_dup 3)
6571 (define_insn "*ashldi3_internal3"
6572 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6573 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6574 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6576 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6577 (ashift:DI (match_dup 1) (match_dup 2)))]
6582 [(set_attr "type" "delayed_compare")
6583 (set_attr "length" "4,8")])
6586 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6587 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6588 (match_operand:SI 2 "reg_or_cint_operand" ""))
6590 (set (match_operand:DI 0 "gpc_reg_operand" "")
6591 (ashift:DI (match_dup 1) (match_dup 2)))]
6592 "TARGET_POWERPC64 && reload_completed"
6594 (ashift:DI (match_dup 1) (match_dup 2)))
6596 (compare:CC (match_dup 0)
6600 (define_insn "*ashldi3_internal4"
6601 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6602 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6603 (match_operand:SI 2 "const_int_operand" "i"))
6604 (match_operand:DI 3 "const_int_operand" "n")))]
6605 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6606 "rldic %0,%1,%H2,%W3")
6608 (define_insn "ashldi3_internal5"
6609 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6611 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6612 (match_operand:SI 2 "const_int_operand" "i,i"))
6613 (match_operand:DI 3 "const_int_operand" "n,n"))
6615 (clobber (match_scratch:DI 4 "=r,r"))]
6616 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6618 rldic. %4,%1,%H2,%W3
6620 [(set_attr "type" "delayed_compare")
6621 (set_attr "length" "4,8")])
6624 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6626 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6627 (match_operand:SI 2 "const_int_operand" ""))
6628 (match_operand:DI 3 "const_int_operand" ""))
6630 (clobber (match_scratch:DI 4 ""))]
6631 "TARGET_POWERPC64 && reload_completed
6632 && includes_rldic_lshift_p (operands[2], operands[3])"
6634 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6637 (compare:CC (match_dup 4)
6641 (define_insn "*ashldi3_internal6"
6642 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6644 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6645 (match_operand:SI 2 "const_int_operand" "i,i"))
6646 (match_operand:DI 3 "const_int_operand" "n,n"))
6648 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6649 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6650 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6652 rldic. %0,%1,%H2,%W3
6654 [(set_attr "type" "delayed_compare")
6655 (set_attr "length" "4,8")])
6658 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6660 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6661 (match_operand:SI 2 "const_int_operand" ""))
6662 (match_operand:DI 3 "const_int_operand" ""))
6664 (set (match_operand:DI 0 "gpc_reg_operand" "")
6665 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6666 "TARGET_POWERPC64 && reload_completed
6667 && includes_rldic_lshift_p (operands[2], operands[3])"
6669 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6672 (compare:CC (match_dup 0)
6676 (define_insn "*ashldi3_internal7"
6677 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6678 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6679 (match_operand:SI 2 "const_int_operand" "i"))
6680 (match_operand:DI 3 "mask64_operand" "n")))]
6681 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6682 "rldicr %0,%1,%H2,%S3")
6684 (define_insn "ashldi3_internal8"
6685 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6687 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6688 (match_operand:SI 2 "const_int_operand" "i,i"))
6689 (match_operand:DI 3 "mask64_operand" "n,n"))
6691 (clobber (match_scratch:DI 4 "=r,r"))]
6692 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6694 rldicr. %4,%1,%H2,%S3
6696 [(set_attr "type" "delayed_compare")
6697 (set_attr "length" "4,8")])
6700 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6702 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6703 (match_operand:SI 2 "const_int_operand" ""))
6704 (match_operand:DI 3 "mask64_operand" ""))
6706 (clobber (match_scratch:DI 4 ""))]
6707 "TARGET_POWERPC64 && reload_completed
6708 && includes_rldicr_lshift_p (operands[2], operands[3])"
6710 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6713 (compare:CC (match_dup 4)
6717 (define_insn "*ashldi3_internal9"
6718 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6720 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6721 (match_operand:SI 2 "const_int_operand" "i,i"))
6722 (match_operand:DI 3 "mask64_operand" "n,n"))
6724 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6725 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6726 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6728 rldicr. %0,%1,%H2,%S3
6730 [(set_attr "type" "delayed_compare")
6731 (set_attr "length" "4,8")])
6734 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6736 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6737 (match_operand:SI 2 "const_int_operand" ""))
6738 (match_operand:DI 3 "mask64_operand" ""))
6740 (set (match_operand:DI 0 "gpc_reg_operand" "")
6741 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6742 "TARGET_POWERPC64 && reload_completed
6743 && includes_rldicr_lshift_p (operands[2], operands[3])"
6745 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6748 (compare:CC (match_dup 0)
6752 (define_expand "lshrdi3"
6753 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6754 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6755 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6756 "TARGET_POWERPC64 || TARGET_POWER"
6759 if (TARGET_POWERPC64)
6761 else if (TARGET_POWER)
6763 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6770 (define_insn "*lshrdi3_internal1"
6771 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6772 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6773 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6777 (define_insn "*lshrdi3_internal2"
6778 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6779 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6780 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6782 (clobber (match_scratch:DI 3 "=r,r"))]
6787 [(set_attr "type" "delayed_compare")
6788 (set_attr "length" "4,8")])
6791 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6792 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6793 (match_operand:SI 2 "reg_or_cint_operand" ""))
6795 (clobber (match_scratch:DI 3 ""))]
6796 "TARGET_POWERPC64 && reload_completed"
6798 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6800 (compare:CC (match_dup 3)
6804 (define_insn "*lshrdi3_internal3"
6805 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6806 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6807 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6809 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6810 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6815 [(set_attr "type" "delayed_compare")
6816 (set_attr "length" "4,8")])
6819 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6820 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6821 (match_operand:SI 2 "reg_or_cint_operand" ""))
6823 (set (match_operand:DI 0 "gpc_reg_operand" "")
6824 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6825 "TARGET_POWERPC64 && reload_completed"
6827 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6829 (compare:CC (match_dup 0)
6833 (define_expand "ashrdi3"
6834 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6835 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6836 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6840 if (TARGET_POWERPC64)
6842 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6844 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6847 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
6848 && WORDS_BIG_ENDIAN)
6850 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6857 (define_insn "*ashrdi3_internal1"
6858 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6859 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6860 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6862 "srad%I2 %0,%1,%H2")
6864 (define_insn "*ashrdi3_internal2"
6865 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6866 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6867 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6869 (clobber (match_scratch:DI 3 "=r,r"))]
6874 [(set_attr "type" "delayed_compare")
6875 (set_attr "length" "4,8")])
6878 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6879 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6880 (match_operand:SI 2 "reg_or_cint_operand" ""))
6882 (clobber (match_scratch:DI 3 ""))]
6883 "TARGET_POWERPC64 && reload_completed"
6885 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6887 (compare:CC (match_dup 3)
6891 (define_insn "*ashrdi3_internal3"
6892 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6893 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6894 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6896 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6897 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6902 [(set_attr "type" "delayed_compare")
6903 (set_attr "length" "4,8")])
6906 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6907 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6908 (match_operand:SI 2 "reg_or_cint_operand" ""))
6910 (set (match_operand:DI 0 "gpc_reg_operand" "")
6911 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6912 "TARGET_POWERPC64 && reload_completed"
6914 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6916 (compare:CC (match_dup 0)
6920 (define_insn "anddi3"
6921 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
6922 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
6923 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
6924 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
6928 rldic%B2 %0,%1,0,%S2
6929 rlwinm %0,%1,0,%m2,%M2
6933 [(set_attr "type" "*,*,*,compare,compare,*")
6934 (set_attr "length" "4,4,4,4,4,8")])
6937 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6938 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6939 (match_operand:DI 2 "mask64_2_operand" "")))
6940 (clobber (match_scratch:CC 3 ""))]
6942 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6943 && !mask64_operand (operands[2], DImode)"
6945 (and:DI (rotate:DI (match_dup 1)
6949 (and:DI (rotate:DI (match_dup 0)
6953 build_mask64_2_operands (operands[2], &operands[4]);
6956 (define_insn "*anddi3_internal2"
6957 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
6958 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
6959 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
6961 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
6962 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
6966 rldic%B2. %3,%1,0,%S2
6975 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
6976 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
6979 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6980 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6981 (match_operand:DI 2 "and64_operand" ""))
6983 (clobber (match_scratch:DI 3 ""))
6984 (clobber (match_scratch:CC 4 ""))]
6985 "TARGET_POWERPC64 && reload_completed"
6986 [(parallel [(set (match_dup 3)
6987 (and:DI (match_dup 1)
6989 (clobber (match_dup 4))])
6991 (compare:CC (match_dup 3)
6996 [(set (match_operand:CC 0 "cc_reg_operand" "")
6997 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6998 (match_operand:DI 2 "mask64_2_operand" ""))
7000 (clobber (match_scratch:DI 3 ""))
7001 (clobber (match_scratch:CC 4 ""))]
7002 "TARGET_POWERPC64 && reload_completed
7003 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7004 && !mask64_operand (operands[2], DImode)"
7006 (and:DI (rotate:DI (match_dup 1)
7009 (parallel [(set (match_dup 0)
7010 (compare:CC (and:DI (rotate:DI (match_dup 3)
7014 (clobber (match_dup 3))])]
7017 build_mask64_2_operands (operands[2], &operands[5]);
7020 (define_insn "*anddi3_internal3"
7021 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7022 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7023 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7025 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
7026 (and:DI (match_dup 1) (match_dup 2)))
7027 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7031 rldic%B2. %0,%1,0,%S2
7040 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7041 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7044 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7045 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7046 (match_operand:DI 2 "and64_operand" ""))
7048 (set (match_operand:DI 0 "gpc_reg_operand" "")
7049 (and:DI (match_dup 1) (match_dup 2)))
7050 (clobber (match_scratch:CC 4 ""))]
7051 "TARGET_POWERPC64 && reload_completed"
7052 [(parallel [(set (match_dup 0)
7053 (and:DI (match_dup 1) (match_dup 2)))
7054 (clobber (match_dup 4))])
7056 (compare:CC (match_dup 0)
7061 [(set (match_operand:CC 3 "cc_reg_operand" "")
7062 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7063 (match_operand:DI 2 "mask64_2_operand" ""))
7065 (set (match_operand:DI 0 "gpc_reg_operand" "")
7066 (and:DI (match_dup 1) (match_dup 2)))
7067 (clobber (match_scratch:CC 4 ""))]
7068 "TARGET_POWERPC64 && reload_completed
7069 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7070 && !mask64_operand (operands[2], DImode)"
7072 (and:DI (rotate:DI (match_dup 1)
7075 (parallel [(set (match_dup 3)
7076 (compare:CC (and:DI (rotate:DI (match_dup 0)
7081 (and:DI (rotate:DI (match_dup 0)
7086 build_mask64_2_operands (operands[2], &operands[5]);
7089 (define_expand "iordi3"
7090 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7091 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7092 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7096 if (non_logical_cint_operand (operands[2], DImode))
7098 HOST_WIDE_INT value;
7099 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7100 ? operands[0] : gen_reg_rtx (DImode));
7102 if (GET_CODE (operands[2]) == CONST_INT)
7104 value = INTVAL (operands[2]);
7105 emit_insn (gen_iordi3 (tmp, operands[1],
7106 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7110 value = CONST_DOUBLE_LOW (operands[2]);
7111 emit_insn (gen_iordi3 (tmp, operands[1],
7112 immed_double_const (value
7113 & (~ (HOST_WIDE_INT) 0xffff),
7117 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7122 (define_expand "xordi3"
7123 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7124 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7125 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7129 if (non_logical_cint_operand (operands[2], DImode))
7131 HOST_WIDE_INT value;
7132 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7133 ? operands[0] : gen_reg_rtx (DImode));
7135 if (GET_CODE (operands[2]) == CONST_INT)
7137 value = INTVAL (operands[2]);
7138 emit_insn (gen_xordi3 (tmp, operands[1],
7139 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7143 value = CONST_DOUBLE_LOW (operands[2]);
7144 emit_insn (gen_xordi3 (tmp, operands[1],
7145 immed_double_const (value
7146 & (~ (HOST_WIDE_INT) 0xffff),
7150 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7155 (define_insn "*booldi3_internal1"
7156 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7157 (match_operator:DI 3 "boolean_or_operator"
7158 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7159 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7166 (define_insn "*booldi3_internal2"
7167 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7168 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7169 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7170 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7172 (clobber (match_scratch:DI 3 "=r,r"))]
7177 [(set_attr "type" "compare")
7178 (set_attr "length" "4,8")])
7181 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7182 (compare:CC (match_operator:DI 4 "boolean_operator"
7183 [(match_operand:DI 1 "gpc_reg_operand" "")
7184 (match_operand:DI 2 "gpc_reg_operand" "")])
7186 (clobber (match_scratch:DI 3 ""))]
7187 "TARGET_POWERPC64 && reload_completed"
7188 [(set (match_dup 3) (match_dup 4))
7190 (compare:CC (match_dup 3)
7194 (define_insn "*booldi3_internal3"
7195 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7196 (compare:CC (match_operator:DI 4 "boolean_operator"
7197 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7198 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7200 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7206 [(set_attr "type" "compare")
7207 (set_attr "length" "4,8")])
7210 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7211 (compare:CC (match_operator:DI 4 "boolean_operator"
7212 [(match_operand:DI 1 "gpc_reg_operand" "")
7213 (match_operand:DI 2 "gpc_reg_operand" "")])
7215 (set (match_operand:DI 0 "gpc_reg_operand" "")
7217 "TARGET_POWERPC64 && reload_completed"
7218 [(set (match_dup 0) (match_dup 4))
7220 (compare:CC (match_dup 0)
7224 ;; Split a logical operation that we can't do in one insn into two insns,
7225 ;; each of which does one 16-bit part. This is used by combine.
7228 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7229 (match_operator:DI 3 "boolean_or_operator"
7230 [(match_operand:DI 1 "gpc_reg_operand" "")
7231 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7233 [(set (match_dup 0) (match_dup 4))
7234 (set (match_dup 0) (match_dup 5))]
7239 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7241 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7242 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7244 i4 = GEN_INT (value & 0xffff);
7248 i3 = GEN_INT (INTVAL (operands[2])
7249 & (~ (HOST_WIDE_INT) 0xffff));
7250 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7252 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7254 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7258 (define_insn "*boolcdi3_internal1"
7259 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7260 (match_operator:DI 3 "boolean_operator"
7261 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7262 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7266 (define_insn "*boolcdi3_internal2"
7267 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7268 (compare:CC (match_operator:DI 4 "boolean_operator"
7269 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7270 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7272 (clobber (match_scratch:DI 3 "=r,r"))]
7277 [(set_attr "type" "compare")
7278 (set_attr "length" "4,8")])
7281 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7282 (compare:CC (match_operator:DI 4 "boolean_operator"
7283 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7284 (match_operand:DI 2 "gpc_reg_operand" "")])
7286 (clobber (match_scratch:DI 3 ""))]
7287 "TARGET_POWERPC64 && reload_completed"
7288 [(set (match_dup 3) (match_dup 4))
7290 (compare:CC (match_dup 3)
7294 (define_insn "*boolcdi3_internal3"
7295 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7296 (compare:CC (match_operator:DI 4 "boolean_operator"
7297 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7298 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7300 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7306 [(set_attr "type" "compare")
7307 (set_attr "length" "4,8")])
7310 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7311 (compare:CC (match_operator:DI 4 "boolean_operator"
7312 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7313 (match_operand:DI 2 "gpc_reg_operand" "")])
7315 (set (match_operand:DI 0 "gpc_reg_operand" "")
7317 "TARGET_POWERPC64 && reload_completed"
7318 [(set (match_dup 0) (match_dup 4))
7320 (compare:CC (match_dup 0)
7324 (define_insn "*boolccdi3_internal1"
7325 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7326 (match_operator:DI 3 "boolean_operator"
7327 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7328 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7332 (define_insn "*boolccdi3_internal2"
7333 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7334 (compare:CC (match_operator:DI 4 "boolean_operator"
7335 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7336 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7338 (clobber (match_scratch:DI 3 "=r,r"))]
7343 [(set_attr "type" "compare")
7344 (set_attr "length" "4,8")])
7347 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7348 (compare:CC (match_operator:DI 4 "boolean_operator"
7349 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7350 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7352 (clobber (match_scratch:DI 3 ""))]
7353 "TARGET_POWERPC64 && reload_completed"
7354 [(set (match_dup 3) (match_dup 4))
7356 (compare:CC (match_dup 3)
7360 (define_insn "*boolccdi3_internal3"
7361 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7362 (compare:CC (match_operator:DI 4 "boolean_operator"
7363 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7364 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7366 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7372 [(set_attr "type" "compare")
7373 (set_attr "length" "4,8")])
7376 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7377 (compare:CC (match_operator:DI 4 "boolean_operator"
7378 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7379 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7381 (set (match_operand:DI 0 "gpc_reg_operand" "")
7383 "TARGET_POWERPC64 && reload_completed"
7384 [(set (match_dup 0) (match_dup 4))
7386 (compare:CC (match_dup 0)
7390 ;; Now define ways of moving data around.
7392 ;; Set up a register with a value from the GOT table
7394 (define_expand "movsi_got"
7395 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7396 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7397 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7398 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7401 if (GET_CODE (operands[1]) == CONST)
7403 rtx offset = const0_rtx;
7404 HOST_WIDE_INT value;
7406 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7407 value = INTVAL (offset);
7410 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7411 emit_insn (gen_movsi_got (tmp, operands[1]));
7412 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7417 operands[2] = rs6000_got_register (operands[1]);
7420 (define_insn "*movsi_got_internal"
7421 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7422 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7423 (match_operand:SI 2 "gpc_reg_operand" "b")]
7425 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7426 "{l|lwz} %0,%a1@got(%2)"
7427 [(set_attr "type" "load")])
7429 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7430 ;; didn't get allocated to a hard register.
7432 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7433 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7434 (match_operand:SI 2 "memory_operand" "")]
7436 "DEFAULT_ABI == ABI_V4
7438 && (reload_in_progress || reload_completed)"
7439 [(set (match_dup 0) (match_dup 2))
7440 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7444 ;; For SI, we special-case integers that can't be loaded in one insn. We
7445 ;; do the load 16-bits at a time. We could do this by loading from memory,
7446 ;; and this is even supposed to be faster, but it is simpler not to get
7447 ;; integers in the TOC.
7448 (define_expand "movsi"
7449 [(set (match_operand:SI 0 "general_operand" "")
7450 (match_operand:SI 1 "any_operand" ""))]
7452 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7454 (define_insn "movsi_low"
7455 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7456 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7457 (match_operand 2 "" ""))))]
7458 "TARGET_MACHO && ! TARGET_64BIT"
7459 "{l|lwz} %0,lo16(%2)(%1)"
7460 [(set_attr "type" "load")
7461 (set_attr "length" "4")])
7463 (define_insn "*movsi_internal1"
7464 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7465 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7466 "gpc_reg_operand (operands[0], SImode)
7467 || gpc_reg_operand (operands[1], SImode)"
7471 {l%U1%X1|lwz%U1%X1} %0,%1
7472 {st%U0%X0|stw%U0%X0} %1,%0
7482 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7483 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7485 ;; Split a load of a large constant into the appropriate two-insn
7489 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7490 (match_operand:SI 1 "const_int_operand" ""))]
7491 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7492 && (INTVAL (operands[1]) & 0xffff) != 0"
7496 (ior:SI (match_dup 0)
7499 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7501 if (tem == operands[0])
7507 (define_insn "*movsi_internal2"
7508 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7509 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r")
7511 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7514 {cmpi|cmpwi} %2,%0,0
7517 [(set_attr "type" "cmp,compare,cmp")
7518 (set_attr "length" "4,4,8")])
7521 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7522 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7524 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7525 "TARGET_32BIT && reload_completed"
7526 [(set (match_dup 0) (match_dup 1))
7528 (compare:CC (match_dup 0)
7532 (define_expand "movhi"
7533 [(set (match_operand:HI 0 "general_operand" "")
7534 (match_operand:HI 1 "any_operand" ""))]
7536 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7538 (define_insn "*movhi_internal"
7539 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7540 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7541 "gpc_reg_operand (operands[0], HImode)
7542 || gpc_reg_operand (operands[1], HImode)"
7552 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7554 (define_expand "movqi"
7555 [(set (match_operand:QI 0 "general_operand" "")
7556 (match_operand:QI 1 "any_operand" ""))]
7558 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7560 (define_insn "*movqi_internal"
7561 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7562 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7563 "gpc_reg_operand (operands[0], QImode)
7564 || gpc_reg_operand (operands[1], QImode)"
7574 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7576 ;; Here is how to move condition codes around. When we store CC data in
7577 ;; an integer register or memory, we store just the high-order 4 bits.
7578 ;; This lets us not shift in the most common case of CR0.
7579 (define_expand "movcc"
7580 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7581 (match_operand:CC 1 "nonimmediate_operand" ""))]
7585 (define_insn "*movcc_internal1"
7586 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7587 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7588 "register_operand (operands[0], CCmode)
7589 || register_operand (operands[1], CCmode)"
7593 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7595 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7600 {l%U1%X1|lwz%U1%X1} %0,%1
7601 {st%U0%U1|stw%U0%U1} %1,%0"
7603 (cond [(eq_attr "alternative" "0")
7604 (const_string "cr_logical")
7605 (eq_attr "alternative" "1,2")
7606 (const_string "mtcr")
7607 (eq_attr "alternative" "5,7")
7608 (const_string "integer")
7609 (eq_attr "alternative" "6")
7610 (const_string "mfjmpr")
7611 (eq_attr "alternative" "8")
7612 (const_string "mtjmpr")
7613 (eq_attr "alternative" "9")
7614 (const_string "load")
7615 (eq_attr "alternative" "10")
7616 (const_string "store")
7617 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7618 (const_string "mfcrf")
7620 (const_string "mfcr")))
7621 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7623 ;; For floating-point, we normally deal with the floating-point registers
7624 ;; unless -msoft-float is used. The sole exception is that parameter passing
7625 ;; can produce floating-point values in fixed-point registers. Unless the
7626 ;; value is a simple constant or already in memory, we deal with this by
7627 ;; allocating memory and copying the value explicitly via that memory location.
7628 (define_expand "movsf"
7629 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7630 (match_operand:SF 1 "any_operand" ""))]
7632 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7635 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7636 (match_operand:SF 1 "const_double_operand" ""))]
7638 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7639 || (GET_CODE (operands[0]) == SUBREG
7640 && GET_CODE (SUBREG_REG (operands[0])) == REG
7641 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7642 [(set (match_dup 2) (match_dup 3))]
7648 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7649 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7651 if (! TARGET_POWERPC64)
7652 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7654 operands[2] = gen_lowpart (SImode, operands[0]);
7656 operands[3] = gen_int_mode (l, SImode);
7659 (define_insn "*movsf_hardfloat"
7660 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
7661 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7662 "(gpc_reg_operand (operands[0], SFmode)
7663 || gpc_reg_operand (operands[1], SFmode))
7664 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7667 {l%U1%X1|lwz%U1%X1} %0,%1
7668 {st%U0%X0|stw%U0%X0} %1,%0
7678 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
7679 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7681 (define_insn "*movsf_softfloat"
7682 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7683 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7684 "(gpc_reg_operand (operands[0], SFmode)
7685 || gpc_reg_operand (operands[1], SFmode))
7686 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7692 {l%U1%X1|lwz%U1%X1} %0,%1
7693 {st%U0%X0|stw%U0%X0} %1,%0
7700 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7701 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7704 (define_expand "movdf"
7705 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7706 (match_operand:DF 1 "any_operand" ""))]
7708 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7711 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7712 (match_operand:DF 1 "const_int_operand" ""))]
7713 "! TARGET_POWERPC64 && reload_completed
7714 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7715 || (GET_CODE (operands[0]) == SUBREG
7716 && GET_CODE (SUBREG_REG (operands[0])) == REG
7717 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7718 [(set (match_dup 2) (match_dup 4))
7719 (set (match_dup 3) (match_dup 1))]
7722 int endian = (WORDS_BIG_ENDIAN == 0);
7723 HOST_WIDE_INT value = INTVAL (operands[1]);
7725 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7726 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7727 #if HOST_BITS_PER_WIDE_INT == 32
7728 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7730 operands[4] = GEN_INT (value >> 32);
7731 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7736 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7737 (match_operand:DF 1 "const_double_operand" ""))]
7738 "! TARGET_POWERPC64 && reload_completed
7739 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7740 || (GET_CODE (operands[0]) == SUBREG
7741 && GET_CODE (SUBREG_REG (operands[0])) == REG
7742 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7743 [(set (match_dup 2) (match_dup 4))
7744 (set (match_dup 3) (match_dup 5))]
7747 int endian = (WORDS_BIG_ENDIAN == 0);
7751 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7752 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7754 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7755 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7756 operands[4] = gen_int_mode (l[endian], SImode);
7757 operands[5] = gen_int_mode (l[1 - endian], SImode);
7761 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7762 (match_operand:DF 1 "easy_fp_constant" ""))]
7763 "TARGET_POWERPC64 && reload_completed
7764 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7765 || (GET_CODE (operands[0]) == SUBREG
7766 && GET_CODE (SUBREG_REG (operands[0])) == REG
7767 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7768 [(set (match_dup 2) (match_dup 3))]
7771 int endian = (WORDS_BIG_ENDIAN == 0);
7774 #if HOST_BITS_PER_WIDE_INT >= 64
7778 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7779 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7781 operands[2] = gen_lowpart (DImode, operands[0]);
7782 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7783 #if HOST_BITS_PER_WIDE_INT >= 64
7784 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7785 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7787 operands[3] = gen_int_mode (val, DImode);
7789 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
7793 ;; Don't have reload use general registers to load a constant. First,
7794 ;; it might not work if the output operand is the equivalent of
7795 ;; a non-offsettable memref, but also it is less efficient than loading
7796 ;; the constant into an FP register, since it will probably be used there.
7797 ;; The "??" is a kludge until we can figure out a more reasonable way
7798 ;; of handling these non-offsettable values.
7799 (define_insn "*movdf_hardfloat32"
7800 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
7801 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
7802 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7803 && (gpc_reg_operand (operands[0], DFmode)
7804 || gpc_reg_operand (operands[1], DFmode))"
7807 switch (which_alternative)
7812 /* We normally copy the low-numbered register first. However, if
7813 the first register operand 0 is the same as the second register
7814 of operand 1, we must copy in the opposite order. */
7815 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7816 return \"mr %L0,%L1\;mr %0,%1\";
7818 return \"mr %0,%1\;mr %L0,%L1\";
7820 if (GET_CODE (operands[1]) == MEM
7821 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0),
7822 reload_completed || reload_in_progress)
7823 || GET_CODE (XEXP (operands[1], 0)) == REG
7824 || GET_CODE (XEXP (operands[1], 0)) == LO_SUM
7825 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
7826 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
7828 /* If the low-address word is used in the address, we must load
7829 it last. Otherwise, load it first. Note that we cannot have
7830 auto-increment in that case since the address register is
7831 known to be dead. */
7832 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7834 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7836 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7842 addreg = find_addr_reg (XEXP (operands[1], 0));
7843 if (refers_to_regno_p (REGNO (operands[0]),
7844 REGNO (operands[0]) + 1,
7847 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7848 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7849 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7850 return \"{lx|lwzx} %0,%1\";
7854 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
7855 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7856 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7857 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7862 if (GET_CODE (operands[0]) == MEM
7863 && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0),
7864 reload_completed || reload_in_progress)
7865 || GET_CODE (XEXP (operands[0], 0)) == REG
7866 || GET_CODE (XEXP (operands[0], 0)) == LO_SUM
7867 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
7868 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))
7869 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7874 addreg = find_addr_reg (XEXP (operands[0], 0));
7875 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
7876 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7877 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
7878 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7882 return \"fmr %0,%1\";
7884 return \"lfd%U1%X1 %0,%1\";
7886 return \"stfd%U0%X0 %1,%0\";
7893 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
7894 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
7896 (define_insn "*movdf_softfloat32"
7897 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7898 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7899 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
7900 && (gpc_reg_operand (operands[0], DFmode)
7901 || gpc_reg_operand (operands[1], DFmode))"
7904 switch (which_alternative)
7909 /* We normally copy the low-numbered register first. However, if
7910 the first register operand 0 is the same as the second register of
7911 operand 1, we must copy in the opposite order. */
7912 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7913 return \"mr %L0,%L1\;mr %0,%1\";
7915 return \"mr %0,%1\;mr %L0,%L1\";
7917 /* If the low-address word is used in the address, we must load
7918 it last. Otherwise, load it first. Note that we cannot have
7919 auto-increment in that case since the address register is
7920 known to be dead. */
7921 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7923 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7925 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7927 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7934 [(set_attr "type" "two,load,store,*,*,*")
7935 (set_attr "length" "8,8,8,8,12,16")])
7937 ; ld/std require word-aligned displacements -> 'Y' constraint.
7938 ; List Y->r and r->Y before r->r for reload.
7939 (define_insn "*movdf_hardfloat64"
7940 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
7941 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
7942 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7943 && (gpc_reg_operand (operands[0], DFmode)
7944 || gpc_reg_operand (operands[1], DFmode))"
7958 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
7959 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
7961 (define_insn "*movdf_softfloat64"
7962 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
7963 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
7964 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
7965 && (gpc_reg_operand (operands[0], DFmode)
7966 || gpc_reg_operand (operands[1], DFmode))"
7977 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
7978 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
7980 (define_expand "movtf"
7981 [(set (match_operand:TF 0 "general_operand" "")
7982 (match_operand:TF 1 "any_operand" ""))]
7983 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7984 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7985 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
7987 ; It's important to list the o->f and f->o moves before f->f because
7988 ; otherwise reload, given m->f, will try to pick f->f and reload it,
7989 ; which doesn't make progress. Likewise r->Y must be before r->r.
7990 (define_insn_and_split "*movtf_internal"
7991 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
7992 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
7993 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
7994 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
7995 && (gpc_reg_operand (operands[0], TFmode)
7996 || gpc_reg_operand (operands[1], TFmode))"
7998 "&& reload_completed"
8000 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8001 [(set_attr "length" "8,8,8,20,20,16")])
8003 (define_expand "extenddftf2"
8004 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8005 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8006 (use (match_dup 2))])]
8007 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8008 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8010 operands[2] = CONST0_RTX (DFmode);
8013 (define_insn_and_split "*extenddftf2_internal"
8014 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8015 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8016 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8017 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8018 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8020 "&& reload_completed"
8023 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8024 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8025 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8027 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8032 (define_expand "extendsftf2"
8033 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8034 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8035 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8036 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8038 rtx tmp = gen_reg_rtx (DFmode);
8039 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8040 emit_insn (gen_extenddftf2 (operands[0], tmp));
8044 (define_expand "trunctfdf2"
8045 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8046 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8047 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8048 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8051 (define_insn_and_split "trunctfdf2_internal1"
8052 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8053 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8054 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
8055 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8059 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8062 emit_note (NOTE_INSN_DELETED);
8065 [(set_attr "type" "fp")])
8067 (define_insn "trunctfdf2_internal2"
8068 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8069 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8070 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
8071 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8073 [(set_attr "type" "fp")])
8075 (define_insn_and_split "trunctfsf2"
8076 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8077 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8078 (clobber (match_scratch:DF 2 "=f"))]
8079 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8080 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8082 "&& reload_completed"
8084 (float_truncate:DF (match_dup 1)))
8086 (float_truncate:SF (match_dup 2)))]
8089 (define_expand "floatsitf2"
8090 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8091 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
8092 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8093 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8095 rtx tmp = gen_reg_rtx (DFmode);
8096 expand_float (tmp, operands[1], false);
8097 emit_insn (gen_extenddftf2 (operands[0], tmp));
8101 ; fadd, but rounding towards zero.
8102 ; This is probably not the optimal code sequence.
8103 (define_insn "fix_trunc_helper"
8104 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8105 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8106 UNSPEC_FIX_TRUNC_TF))
8107 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8108 "TARGET_HARD_FLOAT && TARGET_FPRS"
8109 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8110 [(set_attr "type" "fp")
8111 (set_attr "length" "20")])
8113 (define_expand "fix_trunctfsi2"
8114 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8115 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8116 (clobber (match_dup 2))
8117 (clobber (match_dup 3))
8118 (clobber (match_dup 4))
8119 (clobber (match_dup 5))])]
8120 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8121 && (TARGET_POWER2 || TARGET_POWERPC)
8122 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8124 operands[2] = gen_reg_rtx (DFmode);
8125 operands[3] = gen_reg_rtx (DFmode);
8126 operands[4] = gen_reg_rtx (DImode);
8127 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8130 (define_insn_and_split "*fix_trunctfsi2_internal"
8131 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8132 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8133 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8134 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8135 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8136 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8137 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8138 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8140 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
8144 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8146 gcc_assert (MEM_P (operands[5]));
8147 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8149 emit_insn (gen_fctiwz (operands[4], operands[2]));
8150 emit_move_insn (operands[5], operands[4]);
8151 emit_move_insn (operands[0], lowword);
8155 (define_insn "negtf2"
8156 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8157 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8158 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8159 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8162 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8163 return \"fneg %L0,%L1\;fneg %0,%1\";
8165 return \"fneg %0,%1\;fneg %L0,%L1\";
8167 [(set_attr "type" "fp")
8168 (set_attr "length" "8")])
8170 (define_expand "abstf2"
8171 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8172 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8173 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8174 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8177 rtx label = gen_label_rtx ();
8178 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8183 (define_expand "abstf2_internal"
8184 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8185 (match_operand:TF 1 "gpc_reg_operand" "f"))
8186 (set (match_dup 3) (match_dup 5))
8187 (set (match_dup 5) (abs:DF (match_dup 5)))
8188 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8189 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8190 (label_ref (match_operand 2 "" ""))
8192 (set (match_dup 6) (neg:DF (match_dup 6)))]
8193 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8194 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8197 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8198 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8199 operands[3] = gen_reg_rtx (DFmode);
8200 operands[4] = gen_reg_rtx (CCFPmode);
8201 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8202 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8205 ;; Next come the multi-word integer load and store and the load and store
8207 (define_expand "movdi"
8208 [(set (match_operand:DI 0 "general_operand" "")
8209 (match_operand:DI 1 "any_operand" ""))]
8211 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
8213 ; List r->r after r->"o<>", otherwise reload will try to reload a
8214 ; non-offsettable address by using r->r which won't make progress.
8215 (define_insn "*movdi_internal32"
8216 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8217 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8219 && (gpc_reg_operand (operands[0], DImode)
8220 || gpc_reg_operand (operands[1], DImode))"
8229 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8232 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8233 (match_operand:DI 1 "const_int_operand" ""))]
8234 "! TARGET_POWERPC64 && reload_completed"
8235 [(set (match_dup 2) (match_dup 4))
8236 (set (match_dup 3) (match_dup 1))]
8239 HOST_WIDE_INT value = INTVAL (operands[1]);
8240 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8242 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8244 #if HOST_BITS_PER_WIDE_INT == 32
8245 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8247 operands[4] = GEN_INT (value >> 32);
8248 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8253 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8254 (match_operand:DI 1 "input_operand" ""))]
8255 "reload_completed && !TARGET_POWERPC64
8256 && gpr_or_gpr_p (operands[0], operands[1])"
8258 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8260 (define_insn "*movdi_internal64"
8261 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8262 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8264 && (gpc_reg_operand (operands[0], DImode)
8265 || gpc_reg_operand (operands[1], DImode))"
8280 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8281 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8283 ;; immediate value valid for a single instruction hiding in a const_double
8285 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8286 (match_operand:DI 1 "const_double_operand" "F"))]
8287 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8288 && GET_CODE (operands[1]) == CONST_DOUBLE
8289 && num_insns_constant (operands[1], DImode) == 1"
8292 return ((unsigned HOST_WIDE_INT)
8293 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8294 ? \"li %0,%1\" : \"lis %0,%v1\";
8297 ;; Generate all one-bits and clear left or right.
8298 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8300 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8301 (match_operand:DI 1 "mask64_operand" ""))]
8302 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8303 [(set (match_dup 0) (const_int -1))
8305 (and:DI (rotate:DI (match_dup 0)
8310 ;; Split a load of a large constant into the appropriate five-instruction
8311 ;; sequence. Handle anything in a constant number of insns.
8312 ;; When non-easy constants can go in the TOC, this should use
8313 ;; easy_fp_constant predicate.
8315 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8316 (match_operand:DI 1 "const_int_operand" ""))]
8317 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8318 [(set (match_dup 0) (match_dup 2))
8319 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8321 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8323 if (tem == operands[0])
8330 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8331 (match_operand:DI 1 "const_double_operand" ""))]
8332 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8333 [(set (match_dup 0) (match_dup 2))
8334 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8336 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8338 if (tem == operands[0])
8344 (define_insn "*movdi_internal2"
8345 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8346 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r")
8348 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8354 [(set_attr "type" "cmp,compare,cmp")
8355 (set_attr "length" "4,4,8")])
8358 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8359 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8361 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8362 "TARGET_POWERPC64 && reload_completed"
8363 [(set (match_dup 0) (match_dup 1))
8365 (compare:CC (match_dup 0)
8369 ;; TImode is similar, except that we usually want to compute the address into
8370 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8371 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8372 (define_expand "movti"
8373 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8374 (match_operand:TI 1 "general_operand" ""))
8375 (clobber (scratch:SI))])]
8377 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8379 ;; We say that MQ is clobbered in the last alternative because the first
8380 ;; alternative would never get used otherwise since it would need a reload
8381 ;; while the 2nd alternative would not. We put memory cases first so they
8382 ;; are preferred. Otherwise, we'd try to reload the output instead of
8383 ;; giving the SCRATCH mq.
8385 (define_insn "*movti_power"
8386 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8387 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8388 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8389 "TARGET_POWER && ! TARGET_POWERPC64
8390 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8393 switch (which_alternative)
8400 return \"{stsi|stswi} %1,%P0,16\";
8405 /* If the address is not used in the output, we can use lsi. Otherwise,
8406 fall through to generating four loads. */
8408 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8409 return \"{lsi|lswi} %0,%P1,16\";
8410 /* ... fall through ... */
8416 [(set_attr "type" "store,store,*,load,load,*")])
8418 (define_insn "*movti_string"
8419 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8420 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8421 "! TARGET_POWER && ! TARGET_POWERPC64
8422 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8425 switch (which_alternative)
8431 return \"{stsi|stswi} %1,%P0,16\";
8436 /* If the address is not used in the output, we can use lsi. Otherwise,
8437 fall through to generating four loads. */
8439 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8440 return \"{lsi|lswi} %0,%P1,16\";
8441 /* ... fall through ... */
8447 [(set_attr "type" "store,store,*,load,load,*")])
8449 (define_insn "*movti_ppc64"
8450 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8451 (match_operand:TI 1 "input_operand" "r,r,m"))]
8452 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8453 || gpc_reg_operand (operands[1], TImode))"
8455 [(set_attr "type" "*,load,store")])
8458 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8459 (match_operand:TI 1 "const_double_operand" ""))]
8461 [(set (match_dup 2) (match_dup 4))
8462 (set (match_dup 3) (match_dup 5))]
8465 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8467 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8469 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8471 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8472 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8474 else if (GET_CODE (operands[1]) == CONST_INT)
8476 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8477 operands[5] = operands[1];
8484 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8485 (match_operand:TI 1 "input_operand" ""))]
8487 && gpr_or_gpr_p (operands[0], operands[1])"
8489 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8491 (define_expand "load_multiple"
8492 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8493 (match_operand:SI 1 "" ""))
8494 (use (match_operand:SI 2 "" ""))])]
8495 "TARGET_STRING && !TARGET_POWERPC64"
8503 /* Support only loading a constant number of fixed-point registers from
8504 memory and only bother with this if more than two; the machine
8505 doesn't support more than eight. */
8506 if (GET_CODE (operands[2]) != CONST_INT
8507 || INTVAL (operands[2]) <= 2
8508 || INTVAL (operands[2]) > 8
8509 || GET_CODE (operands[1]) != MEM
8510 || GET_CODE (operands[0]) != REG
8511 || REGNO (operands[0]) >= 32)
8514 count = INTVAL (operands[2]);
8515 regno = REGNO (operands[0]);
8517 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8518 op1 = replace_equiv_address (operands[1],
8519 force_reg (SImode, XEXP (operands[1], 0)));
8521 for (i = 0; i < count; i++)
8522 XVECEXP (operands[3], 0, i)
8523 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8524 adjust_address_nv (op1, SImode, i * 4));
8527 (define_insn "*ldmsi8"
8528 [(match_parallel 0 "load_multiple_operation"
8529 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8530 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8531 (set (match_operand:SI 3 "gpc_reg_operand" "")
8532 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8533 (set (match_operand:SI 4 "gpc_reg_operand" "")
8534 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8535 (set (match_operand:SI 5 "gpc_reg_operand" "")
8536 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8537 (set (match_operand:SI 6 "gpc_reg_operand" "")
8538 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8539 (set (match_operand:SI 7 "gpc_reg_operand" "")
8540 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8541 (set (match_operand:SI 8 "gpc_reg_operand" "")
8542 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8543 (set (match_operand:SI 9 "gpc_reg_operand" "")
8544 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8545 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8547 { return rs6000_output_load_multiple (operands); }"
8548 [(set_attr "type" "load")
8549 (set_attr "length" "32")])
8551 (define_insn "*ldmsi7"
8552 [(match_parallel 0 "load_multiple_operation"
8553 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8554 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8555 (set (match_operand:SI 3 "gpc_reg_operand" "")
8556 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8557 (set (match_operand:SI 4 "gpc_reg_operand" "")
8558 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8559 (set (match_operand:SI 5 "gpc_reg_operand" "")
8560 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8561 (set (match_operand:SI 6 "gpc_reg_operand" "")
8562 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8563 (set (match_operand:SI 7 "gpc_reg_operand" "")
8564 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8565 (set (match_operand:SI 8 "gpc_reg_operand" "")
8566 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8567 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8569 { return rs6000_output_load_multiple (operands); }"
8570 [(set_attr "type" "load")
8571 (set_attr "length" "32")])
8573 (define_insn "*ldmsi6"
8574 [(match_parallel 0 "load_multiple_operation"
8575 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8576 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8577 (set (match_operand:SI 3 "gpc_reg_operand" "")
8578 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8579 (set (match_operand:SI 4 "gpc_reg_operand" "")
8580 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8581 (set (match_operand:SI 5 "gpc_reg_operand" "")
8582 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8583 (set (match_operand:SI 6 "gpc_reg_operand" "")
8584 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8585 (set (match_operand:SI 7 "gpc_reg_operand" "")
8586 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8587 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8589 { return rs6000_output_load_multiple (operands); }"
8590 [(set_attr "type" "load")
8591 (set_attr "length" "32")])
8593 (define_insn "*ldmsi5"
8594 [(match_parallel 0 "load_multiple_operation"
8595 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8596 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8597 (set (match_operand:SI 3 "gpc_reg_operand" "")
8598 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8599 (set (match_operand:SI 4 "gpc_reg_operand" "")
8600 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8601 (set (match_operand:SI 5 "gpc_reg_operand" "")
8602 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8603 (set (match_operand:SI 6 "gpc_reg_operand" "")
8604 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8605 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8607 { return rs6000_output_load_multiple (operands); }"
8608 [(set_attr "type" "load")
8609 (set_attr "length" "32")])
8611 (define_insn "*ldmsi4"
8612 [(match_parallel 0 "load_multiple_operation"
8613 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8614 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8615 (set (match_operand:SI 3 "gpc_reg_operand" "")
8616 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8617 (set (match_operand:SI 4 "gpc_reg_operand" "")
8618 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8619 (set (match_operand:SI 5 "gpc_reg_operand" "")
8620 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8621 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8623 { return rs6000_output_load_multiple (operands); }"
8624 [(set_attr "type" "load")
8625 (set_attr "length" "32")])
8627 (define_insn "*ldmsi3"
8628 [(match_parallel 0 "load_multiple_operation"
8629 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8630 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8631 (set (match_operand:SI 3 "gpc_reg_operand" "")
8632 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8633 (set (match_operand:SI 4 "gpc_reg_operand" "")
8634 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8635 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8637 { return rs6000_output_load_multiple (operands); }"
8638 [(set_attr "type" "load")
8639 (set_attr "length" "32")])
8641 (define_expand "store_multiple"
8642 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8643 (match_operand:SI 1 "" ""))
8644 (clobber (scratch:SI))
8645 (use (match_operand:SI 2 "" ""))])]
8646 "TARGET_STRING && !TARGET_POWERPC64"
8655 /* Support only storing a constant number of fixed-point registers to
8656 memory and only bother with this if more than two; the machine
8657 doesn't support more than eight. */
8658 if (GET_CODE (operands[2]) != CONST_INT
8659 || INTVAL (operands[2]) <= 2
8660 || INTVAL (operands[2]) > 8
8661 || GET_CODE (operands[0]) != MEM
8662 || GET_CODE (operands[1]) != REG
8663 || REGNO (operands[1]) >= 32)
8666 count = INTVAL (operands[2]);
8667 regno = REGNO (operands[1]);
8669 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8670 to = force_reg (SImode, XEXP (operands[0], 0));
8671 op0 = replace_equiv_address (operands[0], to);
8673 XVECEXP (operands[3], 0, 0)
8674 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8675 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8676 gen_rtx_SCRATCH (SImode));
8678 for (i = 1; i < count; i++)
8679 XVECEXP (operands[3], 0, i + 1)
8680 = gen_rtx_SET (VOIDmode,
8681 adjust_address_nv (op0, SImode, i * 4),
8682 gen_rtx_REG (SImode, regno + i));
8685 (define_insn "*store_multiple_power"
8686 [(match_parallel 0 "store_multiple_operation"
8687 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8688 (match_operand:SI 2 "gpc_reg_operand" "r"))
8689 (clobber (match_scratch:SI 3 "=q"))])]
8690 "TARGET_STRING && TARGET_POWER"
8691 "{stsi|stswi} %2,%P1,%O0"
8692 [(set_attr "type" "store")])
8694 (define_insn "*stmsi8"
8695 [(match_parallel 0 "store_multiple_operation"
8696 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8697 (match_operand:SI 2 "gpc_reg_operand" "r"))
8698 (clobber (match_scratch:SI 3 "X"))
8699 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8700 (match_operand:SI 4 "gpc_reg_operand" "r"))
8701 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8702 (match_operand:SI 5 "gpc_reg_operand" "r"))
8703 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8704 (match_operand:SI 6 "gpc_reg_operand" "r"))
8705 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8706 (match_operand:SI 7 "gpc_reg_operand" "r"))
8707 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8708 (match_operand:SI 8 "gpc_reg_operand" "r"))
8709 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8710 (match_operand:SI 9 "gpc_reg_operand" "r"))
8711 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8712 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8713 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8714 "{stsi|stswi} %2,%1,%O0"
8715 [(set_attr "type" "store")])
8717 (define_insn "*stmsi7"
8718 [(match_parallel 0 "store_multiple_operation"
8719 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8720 (match_operand:SI 2 "gpc_reg_operand" "r"))
8721 (clobber (match_scratch:SI 3 "X"))
8722 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8723 (match_operand:SI 4 "gpc_reg_operand" "r"))
8724 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8725 (match_operand:SI 5 "gpc_reg_operand" "r"))
8726 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8727 (match_operand:SI 6 "gpc_reg_operand" "r"))
8728 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8729 (match_operand:SI 7 "gpc_reg_operand" "r"))
8730 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8731 (match_operand:SI 8 "gpc_reg_operand" "r"))
8732 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8733 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8734 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8735 "{stsi|stswi} %2,%1,%O0"
8736 [(set_attr "type" "store")])
8738 (define_insn "*stmsi6"
8739 [(match_parallel 0 "store_multiple_operation"
8740 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8741 (match_operand:SI 2 "gpc_reg_operand" "r"))
8742 (clobber (match_scratch:SI 3 "X"))
8743 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8744 (match_operand:SI 4 "gpc_reg_operand" "r"))
8745 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8746 (match_operand:SI 5 "gpc_reg_operand" "r"))
8747 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8748 (match_operand:SI 6 "gpc_reg_operand" "r"))
8749 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8750 (match_operand:SI 7 "gpc_reg_operand" "r"))
8751 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8752 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8753 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8754 "{stsi|stswi} %2,%1,%O0"
8755 [(set_attr "type" "store")])
8757 (define_insn "*stmsi5"
8758 [(match_parallel 0 "store_multiple_operation"
8759 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8760 (match_operand:SI 2 "gpc_reg_operand" "r"))
8761 (clobber (match_scratch:SI 3 "X"))
8762 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8763 (match_operand:SI 4 "gpc_reg_operand" "r"))
8764 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8765 (match_operand:SI 5 "gpc_reg_operand" "r"))
8766 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8767 (match_operand:SI 6 "gpc_reg_operand" "r"))
8768 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8769 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8770 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8771 "{stsi|stswi} %2,%1,%O0"
8772 [(set_attr "type" "store")])
8774 (define_insn "*stmsi4"
8775 [(match_parallel 0 "store_multiple_operation"
8776 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8777 (match_operand:SI 2 "gpc_reg_operand" "r"))
8778 (clobber (match_scratch:SI 3 "X"))
8779 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8780 (match_operand:SI 4 "gpc_reg_operand" "r"))
8781 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8782 (match_operand:SI 5 "gpc_reg_operand" "r"))
8783 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8784 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
8785 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
8786 "{stsi|stswi} %2,%1,%O0"
8787 [(set_attr "type" "store")])
8789 (define_insn "*stmsi3"
8790 [(match_parallel 0 "store_multiple_operation"
8791 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8792 (match_operand:SI 2 "gpc_reg_operand" "r"))
8793 (clobber (match_scratch:SI 3 "X"))
8794 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8795 (match_operand:SI 4 "gpc_reg_operand" "r"))
8796 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8797 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
8798 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
8799 "{stsi|stswi} %2,%1,%O0"
8800 [(set_attr "type" "store")])
8802 (define_expand "clrmemsi"
8803 [(parallel [(set (match_operand:BLK 0 "" "")
8805 (use (match_operand:SI 1 "" ""))
8806 (use (match_operand:SI 2 "" ""))])]
8810 if (expand_block_clear (operands))
8816 ;; String/block move insn.
8817 ;; Argument 0 is the destination
8818 ;; Argument 1 is the source
8819 ;; Argument 2 is the length
8820 ;; Argument 3 is the alignment
8822 (define_expand "movmemsi"
8823 [(parallel [(set (match_operand:BLK 0 "" "")
8824 (match_operand:BLK 1 "" ""))
8825 (use (match_operand:SI 2 "" ""))
8826 (use (match_operand:SI 3 "" ""))])]
8830 if (expand_block_move (operands))
8836 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
8837 ;; register allocator doesn't have a clue about allocating 8 word registers.
8838 ;; rD/rS = r5 is preferred, efficient form.
8839 (define_expand "movmemsi_8reg"
8840 [(parallel [(set (match_operand 0 "" "")
8841 (match_operand 1 "" ""))
8842 (use (match_operand 2 "" ""))
8843 (use (match_operand 3 "" ""))
8844 (clobber (reg:SI 5))
8845 (clobber (reg:SI 6))
8846 (clobber (reg:SI 7))
8847 (clobber (reg:SI 8))
8848 (clobber (reg:SI 9))
8849 (clobber (reg:SI 10))
8850 (clobber (reg:SI 11))
8851 (clobber (reg:SI 12))
8852 (clobber (match_scratch:SI 4 ""))])]
8857 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8858 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8859 (use (match_operand:SI 2 "immediate_operand" "i"))
8860 (use (match_operand:SI 3 "immediate_operand" "i"))
8861 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8862 (clobber (reg:SI 6))
8863 (clobber (reg:SI 7))
8864 (clobber (reg:SI 8))
8865 (clobber (reg:SI 9))
8866 (clobber (reg:SI 10))
8867 (clobber (reg:SI 11))
8868 (clobber (reg:SI 12))
8869 (clobber (match_scratch:SI 5 "=q"))]
8870 "TARGET_STRING && TARGET_POWER
8871 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8872 || INTVAL (operands[2]) == 0)
8873 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8874 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8875 && REGNO (operands[4]) == 5"
8876 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8877 [(set_attr "type" "load")
8878 (set_attr "length" "8")])
8881 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8882 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8883 (use (match_operand:SI 2 "immediate_operand" "i"))
8884 (use (match_operand:SI 3 "immediate_operand" "i"))
8885 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8886 (clobber (reg:SI 6))
8887 (clobber (reg:SI 7))
8888 (clobber (reg:SI 8))
8889 (clobber (reg:SI 9))
8890 (clobber (reg:SI 10))
8891 (clobber (reg:SI 11))
8892 (clobber (reg:SI 12))
8893 (clobber (match_scratch:SI 5 "X"))]
8894 "TARGET_STRING && ! TARGET_POWER
8895 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8896 || INTVAL (operands[2]) == 0)
8897 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8898 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8899 && REGNO (operands[4]) == 5"
8900 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8901 [(set_attr "type" "load")
8902 (set_attr "length" "8")])
8905 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
8906 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
8907 (use (match_operand:SI 2 "immediate_operand" "i"))
8908 (use (match_operand:SI 3 "immediate_operand" "i"))
8909 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8910 (clobber (reg:SI 6))
8911 (clobber (reg:SI 7))
8912 (clobber (reg:SI 8))
8913 (clobber (reg:SI 9))
8914 (clobber (reg:SI 10))
8915 (clobber (reg:SI 11))
8916 (clobber (reg:SI 12))
8917 (clobber (match_scratch:SI 5 "X"))]
8918 "TARGET_STRING && TARGET_POWERPC64
8919 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8920 || INTVAL (operands[2]) == 0)
8921 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8922 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8923 && REGNO (operands[4]) == 5"
8924 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8925 [(set_attr "type" "load")
8926 (set_attr "length" "8")])
8928 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
8929 ;; register allocator doesn't have a clue about allocating 6 word registers.
8930 ;; rD/rS = r5 is preferred, efficient form.
8931 (define_expand "movmemsi_6reg"
8932 [(parallel [(set (match_operand 0 "" "")
8933 (match_operand 1 "" ""))
8934 (use (match_operand 2 "" ""))
8935 (use (match_operand 3 "" ""))
8936 (clobber (reg:SI 5))
8937 (clobber (reg:SI 6))
8938 (clobber (reg:SI 7))
8939 (clobber (reg:SI 8))
8940 (clobber (reg:SI 9))
8941 (clobber (reg:SI 10))
8942 (clobber (match_scratch:SI 4 ""))])]
8947 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8948 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8949 (use (match_operand:SI 2 "immediate_operand" "i"))
8950 (use (match_operand:SI 3 "immediate_operand" "i"))
8951 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8952 (clobber (reg:SI 6))
8953 (clobber (reg:SI 7))
8954 (clobber (reg:SI 8))
8955 (clobber (reg:SI 9))
8956 (clobber (reg:SI 10))
8957 (clobber (match_scratch:SI 5 "=q"))]
8958 "TARGET_STRING && TARGET_POWER
8959 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
8960 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8961 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8962 && REGNO (operands[4]) == 5"
8963 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8964 [(set_attr "type" "load")
8965 (set_attr "length" "8")])
8968 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8969 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8970 (use (match_operand:SI 2 "immediate_operand" "i"))
8971 (use (match_operand:SI 3 "immediate_operand" "i"))
8972 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8973 (clobber (reg:SI 6))
8974 (clobber (reg:SI 7))
8975 (clobber (reg:SI 8))
8976 (clobber (reg:SI 9))
8977 (clobber (reg:SI 10))
8978 (clobber (match_scratch:SI 5 "X"))]
8979 "TARGET_STRING && ! TARGET_POWER
8980 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
8981 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8982 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8983 && REGNO (operands[4]) == 5"
8984 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8985 [(set_attr "type" "load")
8986 (set_attr "length" "8")])
8989 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
8990 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
8991 (use (match_operand:SI 2 "immediate_operand" "i"))
8992 (use (match_operand:SI 3 "immediate_operand" "i"))
8993 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8994 (clobber (reg:SI 6))
8995 (clobber (reg:SI 7))
8996 (clobber (reg:SI 8))
8997 (clobber (reg:SI 9))
8998 (clobber (reg:SI 10))
8999 (clobber (match_scratch:SI 5 "X"))]
9000 "TARGET_STRING && TARGET_POWERPC64
9001 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9002 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9003 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9004 && REGNO (operands[4]) == 5"
9005 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9006 [(set_attr "type" "load")
9007 (set_attr "length" "8")])
9009 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9010 ;; problems with TImode.
9011 ;; rD/rS = r5 is preferred, efficient form.
9012 (define_expand "movmemsi_4reg"
9013 [(parallel [(set (match_operand 0 "" "")
9014 (match_operand 1 "" ""))
9015 (use (match_operand 2 "" ""))
9016 (use (match_operand 3 "" ""))
9017 (clobber (reg:SI 5))
9018 (clobber (reg:SI 6))
9019 (clobber (reg:SI 7))
9020 (clobber (reg:SI 8))
9021 (clobber (match_scratch:SI 4 ""))])]
9026 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9027 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9028 (use (match_operand:SI 2 "immediate_operand" "i"))
9029 (use (match_operand:SI 3 "immediate_operand" "i"))
9030 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9031 (clobber (reg:SI 6))
9032 (clobber (reg:SI 7))
9033 (clobber (reg:SI 8))
9034 (clobber (match_scratch:SI 5 "=q"))]
9035 "TARGET_STRING && TARGET_POWER
9036 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9037 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9038 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9039 && REGNO (operands[4]) == 5"
9040 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9041 [(set_attr "type" "load")
9042 (set_attr "length" "8")])
9045 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9046 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9047 (use (match_operand:SI 2 "immediate_operand" "i"))
9048 (use (match_operand:SI 3 "immediate_operand" "i"))
9049 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9050 (clobber (reg:SI 6))
9051 (clobber (reg:SI 7))
9052 (clobber (reg:SI 8))
9053 (clobber (match_scratch:SI 5 "X"))]
9054 "TARGET_STRING && ! TARGET_POWER
9055 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9056 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9057 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9058 && REGNO (operands[4]) == 5"
9059 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9060 [(set_attr "type" "load")
9061 (set_attr "length" "8")])
9064 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9065 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9066 (use (match_operand:SI 2 "immediate_operand" "i"))
9067 (use (match_operand:SI 3 "immediate_operand" "i"))
9068 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9069 (clobber (reg:SI 6))
9070 (clobber (reg:SI 7))
9071 (clobber (reg:SI 8))
9072 (clobber (match_scratch:SI 5 "X"))]
9073 "TARGET_STRING && TARGET_POWERPC64
9074 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9075 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9076 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9077 && REGNO (operands[4]) == 5"
9078 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9079 [(set_attr "type" "load")
9080 (set_attr "length" "8")])
9082 ;; Move up to 8 bytes at a time.
9083 (define_expand "movmemsi_2reg"
9084 [(parallel [(set (match_operand 0 "" "")
9085 (match_operand 1 "" ""))
9086 (use (match_operand 2 "" ""))
9087 (use (match_operand 3 "" ""))
9088 (clobber (match_scratch:DI 4 ""))
9089 (clobber (match_scratch:SI 5 ""))])]
9090 "TARGET_STRING && ! TARGET_POWERPC64"
9094 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9095 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9096 (use (match_operand:SI 2 "immediate_operand" "i"))
9097 (use (match_operand:SI 3 "immediate_operand" "i"))
9098 (clobber (match_scratch:DI 4 "=&r"))
9099 (clobber (match_scratch:SI 5 "=q"))]
9100 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9101 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9102 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9103 [(set_attr "type" "load")
9104 (set_attr "length" "8")])
9107 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9108 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9109 (use (match_operand:SI 2 "immediate_operand" "i"))
9110 (use (match_operand:SI 3 "immediate_operand" "i"))
9111 (clobber (match_scratch:DI 4 "=&r"))
9112 (clobber (match_scratch:SI 5 "X"))]
9113 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9114 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9115 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9116 [(set_attr "type" "load")
9117 (set_attr "length" "8")])
9119 ;; Move up to 4 bytes at a time.
9120 (define_expand "movmemsi_1reg"
9121 [(parallel [(set (match_operand 0 "" "")
9122 (match_operand 1 "" ""))
9123 (use (match_operand 2 "" ""))
9124 (use (match_operand 3 "" ""))
9125 (clobber (match_scratch:SI 4 ""))
9126 (clobber (match_scratch:SI 5 ""))])]
9131 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9132 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9133 (use (match_operand:SI 2 "immediate_operand" "i"))
9134 (use (match_operand:SI 3 "immediate_operand" "i"))
9135 (clobber (match_scratch:SI 4 "=&r"))
9136 (clobber (match_scratch:SI 5 "=q"))]
9137 "TARGET_STRING && TARGET_POWER
9138 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9139 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9140 [(set_attr "type" "load")
9141 (set_attr "length" "8")])
9144 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9145 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9146 (use (match_operand:SI 2 "immediate_operand" "i"))
9147 (use (match_operand:SI 3 "immediate_operand" "i"))
9148 (clobber (match_scratch:SI 4 "=&r"))
9149 (clobber (match_scratch:SI 5 "X"))]
9150 "TARGET_STRING && ! TARGET_POWER
9151 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9152 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9153 [(set_attr "type" "load")
9154 (set_attr "length" "8")])
9157 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9158 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9159 (use (match_operand:SI 2 "immediate_operand" "i"))
9160 (use (match_operand:SI 3 "immediate_operand" "i"))
9161 (clobber (match_scratch:SI 4 "=&r"))
9162 (clobber (match_scratch:SI 5 "X"))]
9163 "TARGET_STRING && TARGET_POWERPC64
9164 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9165 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9166 [(set_attr "type" "load")
9167 (set_attr "length" "8")])
9170 ;; Define insns that do load or store with update. Some of these we can
9171 ;; get by using pre-decrement or pre-increment, but the hardware can also
9172 ;; do cases where the increment is not the size of the object.
9174 ;; In all these cases, we use operands 0 and 1 for the register being
9175 ;; incremented because those are the operands that local-alloc will
9176 ;; tie and these are the pair most likely to be tieable (and the ones
9177 ;; that will benefit the most).
9179 (define_insn "*movdi_update1"
9180 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9181 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9182 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9183 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9184 (plus:DI (match_dup 1) (match_dup 2)))]
9185 "TARGET_POWERPC64 && TARGET_UPDATE"
9189 [(set_attr "type" "load_ux,load_u")])
9191 (define_insn "movdi_<mode>_update"
9192 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9193 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9194 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9195 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9196 (plus:P (match_dup 1) (match_dup 2)))]
9197 "TARGET_POWERPC64 && TARGET_UPDATE"
9201 [(set_attr "type" "store_ux,store_u")])
9203 (define_insn "*movsi_update1"
9204 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9205 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9206 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9207 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9208 (plus:SI (match_dup 1) (match_dup 2)))]
9211 {lux|lwzux} %3,%0,%2
9212 {lu|lwzu} %3,%2(%0)"
9213 [(set_attr "type" "load_ux,load_u")])
9215 (define_insn "*movsi_update2"
9216 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9218 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9219 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9220 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9221 (plus:DI (match_dup 1) (match_dup 2)))]
9224 [(set_attr "type" "load_ext_ux")])
9226 (define_insn "movsi_update"
9227 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9228 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9229 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9230 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9231 (plus:SI (match_dup 1) (match_dup 2)))]
9234 {stux|stwux} %3,%0,%2
9235 {stu|stwu} %3,%2(%0)"
9236 [(set_attr "type" "store_ux,store_u")])
9238 (define_insn "*movhi_update1"
9239 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9240 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9241 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9242 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9243 (plus:SI (match_dup 1) (match_dup 2)))]
9248 [(set_attr "type" "load_ux,load_u")])
9250 (define_insn "*movhi_update2"
9251 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9253 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9254 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9255 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9256 (plus:SI (match_dup 1) (match_dup 2)))]
9261 [(set_attr "type" "load_ux,load_u")])
9263 (define_insn "*movhi_update3"
9264 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9266 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9267 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9268 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9269 (plus:SI (match_dup 1) (match_dup 2)))]
9274 [(set_attr "type" "load_ext_ux,load_ext_u")])
9276 (define_insn "*movhi_update4"
9277 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9278 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9279 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9280 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9281 (plus:SI (match_dup 1) (match_dup 2)))]
9286 [(set_attr "type" "store_ux,store_u")])
9288 (define_insn "*movqi_update1"
9289 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9290 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9291 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9292 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9293 (plus:SI (match_dup 1) (match_dup 2)))]
9298 [(set_attr "type" "load_ux,load_u")])
9300 (define_insn "*movqi_update2"
9301 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9303 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9304 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9305 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9306 (plus:SI (match_dup 1) (match_dup 2)))]
9311 [(set_attr "type" "load_ux,load_u")])
9313 (define_insn "*movqi_update3"
9314 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9315 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9316 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9317 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9318 (plus:SI (match_dup 1) (match_dup 2)))]
9323 [(set_attr "type" "store_ux,store_u")])
9325 (define_insn "*movsf_update1"
9326 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9327 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9328 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9329 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9330 (plus:SI (match_dup 1) (match_dup 2)))]
9331 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9335 [(set_attr "type" "fpload_ux,fpload_u")])
9337 (define_insn "*movsf_update2"
9338 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9339 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9340 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9341 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9342 (plus:SI (match_dup 1) (match_dup 2)))]
9343 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9347 [(set_attr "type" "fpstore_ux,fpstore_u")])
9349 (define_insn "*movsf_update3"
9350 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9351 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9352 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9353 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9354 (plus:SI (match_dup 1) (match_dup 2)))]
9355 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9357 {lux|lwzux} %3,%0,%2
9358 {lu|lwzu} %3,%2(%0)"
9359 [(set_attr "type" "load_ux,load_u")])
9361 (define_insn "*movsf_update4"
9362 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9363 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9364 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9365 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9366 (plus:SI (match_dup 1) (match_dup 2)))]
9367 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9369 {stux|stwux} %3,%0,%2
9370 {stu|stwu} %3,%2(%0)"
9371 [(set_attr "type" "store_ux,store_u")])
9373 (define_insn "*movdf_update1"
9374 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9375 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9376 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9377 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9378 (plus:SI (match_dup 1) (match_dup 2)))]
9379 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9383 [(set_attr "type" "fpload_ux,fpload_u")])
9385 (define_insn "*movdf_update2"
9386 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9387 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9388 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9389 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9390 (plus:SI (match_dup 1) (match_dup 2)))]
9391 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9395 [(set_attr "type" "fpstore_ux,fpstore_u")])
9397 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9399 (define_insn "*lfq_power2"
9400 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
9401 (match_operand:TF 1 "memory_operand" ""))]
9403 && TARGET_HARD_FLOAT && TARGET_FPRS"
9407 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9408 (match_operand:DF 1 "memory_operand" ""))
9409 (set (match_operand:DF 2 "gpc_reg_operand" "")
9410 (match_operand:DF 3 "memory_operand" ""))]
9412 && TARGET_HARD_FLOAT && TARGET_FPRS
9413 && registers_ok_for_quad_peep (operands[0], operands[2])
9414 && mems_ok_for_quad_peep (operands[1], operands[3])"
9417 "operands[1] = widen_memory_access (operands[1], TFmode, 0);
9418 operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));")
9420 (define_insn "*stfq_power2"
9421 [(set (match_operand:TF 0 "memory_operand" "")
9422 (match_operand:TF 1 "gpc_reg_operand" "f"))]
9424 && TARGET_HARD_FLOAT && TARGET_FPRS"
9429 [(set (match_operand:DF 0 "memory_operand" "")
9430 (match_operand:DF 1 "gpc_reg_operand" ""))
9431 (set (match_operand:DF 2 "memory_operand" "")
9432 (match_operand:DF 3 "gpc_reg_operand" ""))]
9434 && TARGET_HARD_FLOAT && TARGET_FPRS
9435 && registers_ok_for_quad_peep (operands[1], operands[3])
9436 && mems_ok_for_quad_peep (operands[0], operands[2])"
9439 "operands[0] = widen_memory_access (operands[0], TFmode, 0);
9440 operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));")
9442 ;; after inserting conditional returns we can sometimes have
9443 ;; unnecessary register moves. Unfortunately we cannot have a
9444 ;; modeless peephole here, because some single SImode sets have early
9445 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9446 ;; sequences, using get_attr_length here will smash the operands
9447 ;; array. Neither is there an early_cobbler_p predicate.
9449 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9450 (match_operand:DF 1 "any_operand" ""))
9451 (set (match_operand:DF 2 "gpc_reg_operand" "")
9453 "peep2_reg_dead_p (2, operands[0])"
9454 [(set (match_dup 2) (match_dup 1))])
9457 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9458 (match_operand:SF 1 "any_operand" ""))
9459 (set (match_operand:SF 2 "gpc_reg_operand" "")
9461 "peep2_reg_dead_p (2, operands[0])"
9462 [(set (match_dup 2) (match_dup 1))])
9467 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9468 (define_insn "tls_gd_32"
9469 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9470 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9471 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9473 "HAVE_AS_TLS && !TARGET_64BIT"
9474 "addi %0,%1,%2@got@tlsgd")
9476 (define_insn "tls_gd_64"
9477 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9478 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9479 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9481 "HAVE_AS_TLS && TARGET_64BIT"
9482 "addi %0,%1,%2@got@tlsgd")
9484 (define_insn "tls_ld_32"
9485 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9486 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9488 "HAVE_AS_TLS && !TARGET_64BIT"
9489 "addi %0,%1,%&@got@tlsld")
9491 (define_insn "tls_ld_64"
9492 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9493 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9495 "HAVE_AS_TLS && TARGET_64BIT"
9496 "addi %0,%1,%&@got@tlsld")
9498 (define_insn "tls_dtprel_32"
9499 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9500 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9501 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9503 "HAVE_AS_TLS && !TARGET_64BIT"
9504 "addi %0,%1,%2@dtprel")
9506 (define_insn "tls_dtprel_64"
9507 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9508 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9509 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9511 "HAVE_AS_TLS && TARGET_64BIT"
9512 "addi %0,%1,%2@dtprel")
9514 (define_insn "tls_dtprel_ha_32"
9515 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9516 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9517 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9518 UNSPEC_TLSDTPRELHA))]
9519 "HAVE_AS_TLS && !TARGET_64BIT"
9520 "addis %0,%1,%2@dtprel@ha")
9522 (define_insn "tls_dtprel_ha_64"
9523 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9524 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9525 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9526 UNSPEC_TLSDTPRELHA))]
9527 "HAVE_AS_TLS && TARGET_64BIT"
9528 "addis %0,%1,%2@dtprel@ha")
9530 (define_insn "tls_dtprel_lo_32"
9531 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9532 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9533 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9534 UNSPEC_TLSDTPRELLO))]
9535 "HAVE_AS_TLS && !TARGET_64BIT"
9536 "addi %0,%1,%2@dtprel@l")
9538 (define_insn "tls_dtprel_lo_64"
9539 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9540 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9541 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9542 UNSPEC_TLSDTPRELLO))]
9543 "HAVE_AS_TLS && TARGET_64BIT"
9544 "addi %0,%1,%2@dtprel@l")
9546 (define_insn "tls_got_dtprel_32"
9547 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9548 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9549 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9550 UNSPEC_TLSGOTDTPREL))]
9551 "HAVE_AS_TLS && !TARGET_64BIT"
9552 "lwz %0,%2@got@dtprel(%1)")
9554 (define_insn "tls_got_dtprel_64"
9555 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9556 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9557 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9558 UNSPEC_TLSGOTDTPREL))]
9559 "HAVE_AS_TLS && TARGET_64BIT"
9560 "ld %0,%2@got@dtprel(%1)")
9562 (define_insn "tls_tprel_32"
9563 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9564 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9565 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9567 "HAVE_AS_TLS && !TARGET_64BIT"
9568 "addi %0,%1,%2@tprel")
9570 (define_insn "tls_tprel_64"
9571 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9572 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9573 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9575 "HAVE_AS_TLS && TARGET_64BIT"
9576 "addi %0,%1,%2@tprel")
9578 (define_insn "tls_tprel_ha_32"
9579 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9580 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9581 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9582 UNSPEC_TLSTPRELHA))]
9583 "HAVE_AS_TLS && !TARGET_64BIT"
9584 "addis %0,%1,%2@tprel@ha")
9586 (define_insn "tls_tprel_ha_64"
9587 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9588 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9589 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9590 UNSPEC_TLSTPRELHA))]
9591 "HAVE_AS_TLS && TARGET_64BIT"
9592 "addis %0,%1,%2@tprel@ha")
9594 (define_insn "tls_tprel_lo_32"
9595 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9596 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9597 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9598 UNSPEC_TLSTPRELLO))]
9599 "HAVE_AS_TLS && !TARGET_64BIT"
9600 "addi %0,%1,%2@tprel@l")
9602 (define_insn "tls_tprel_lo_64"
9603 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9604 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9605 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9606 UNSPEC_TLSTPRELLO))]
9607 "HAVE_AS_TLS && TARGET_64BIT"
9608 "addi %0,%1,%2@tprel@l")
9610 ;; "b" output constraint here and on tls_tls input to support linker tls
9611 ;; optimization. The linker may edit the instructions emitted by a
9612 ;; tls_got_tprel/tls_tls pair to addis,addi.
9613 (define_insn "tls_got_tprel_32"
9614 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9615 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9616 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9617 UNSPEC_TLSGOTTPREL))]
9618 "HAVE_AS_TLS && !TARGET_64BIT"
9619 "lwz %0,%2@got@tprel(%1)")
9621 (define_insn "tls_got_tprel_64"
9622 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9623 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9624 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9625 UNSPEC_TLSGOTTPREL))]
9626 "HAVE_AS_TLS && TARGET_64BIT"
9627 "ld %0,%2@got@tprel(%1)")
9629 (define_insn "tls_tls_32"
9630 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9631 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9632 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9634 "HAVE_AS_TLS && !TARGET_64BIT"
9637 (define_insn "tls_tls_64"
9638 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9639 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9640 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9642 "HAVE_AS_TLS && TARGET_64BIT"
9645 ;; Next come insns related to the calling sequence.
9647 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9648 ;; We move the back-chain and decrement the stack pointer.
9650 (define_expand "allocate_stack"
9651 [(set (match_operand 0 "gpc_reg_operand" "=r")
9652 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9654 (minus (reg 1) (match_dup 1)))]
9657 { rtx chain = gen_reg_rtx (Pmode);
9658 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9661 emit_move_insn (chain, stack_bot);
9663 /* Check stack bounds if necessary. */
9664 if (current_function_limit_stack)
9667 available = expand_binop (Pmode, sub_optab,
9668 stack_pointer_rtx, stack_limit_rtx,
9669 NULL_RTX, 1, OPTAB_WIDEN);
9670 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9673 if (GET_CODE (operands[1]) != CONST_INT
9674 || INTVAL (operands[1]) < -32767
9675 || INTVAL (operands[1]) > 32768)
9677 neg_op0 = gen_reg_rtx (Pmode);
9679 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9681 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9684 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9687 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
9688 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9692 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9693 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9694 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9697 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9701 ;; These patterns say how to save and restore the stack pointer. We need not
9702 ;; save the stack pointer at function level since we are careful to
9703 ;; preserve the backchain. At block level, we have to restore the backchain
9704 ;; when we restore the stack pointer.
9706 ;; For nonlocal gotos, we must save both the stack pointer and its
9707 ;; backchain and restore both. Note that in the nonlocal case, the
9708 ;; save area is a memory location.
9710 (define_expand "save_stack_function"
9711 [(match_operand 0 "any_operand" "")
9712 (match_operand 1 "any_operand" "")]
9716 (define_expand "restore_stack_function"
9717 [(match_operand 0 "any_operand" "")
9718 (match_operand 1 "any_operand" "")]
9722 (define_expand "restore_stack_block"
9723 [(use (match_operand 0 "register_operand" ""))
9724 (set (match_dup 2) (match_dup 3))
9725 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9726 (set (match_dup 3) (match_dup 2))]
9730 operands[2] = gen_reg_rtx (Pmode);
9731 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9734 (define_expand "save_stack_nonlocal"
9735 [(match_operand 0 "memory_operand" "")
9736 (match_operand 1 "register_operand" "")]
9740 rtx temp = gen_reg_rtx (Pmode);
9741 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9743 /* Copy the backchain to the first word, sp to the second. */
9744 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9745 emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp);
9746 emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word),
9751 (define_expand "restore_stack_nonlocal"
9752 [(match_operand 0 "register_operand" "")
9753 (match_operand 1 "memory_operand" "")]
9757 rtx temp = gen_reg_rtx (Pmode);
9758 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9760 /* Restore the backchain from the first word, sp from the second. */
9761 emit_move_insn (temp,
9762 adjust_address_nv (operands[1], Pmode, 0));
9763 emit_move_insn (operands[0],
9764 adjust_address_nv (operands[1], Pmode, units_per_word));
9765 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
9769 ;; TOC register handling.
9771 ;; Code to initialize the TOC register...
9773 (define_insn "load_toc_aix_si"
9774 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9775 (unspec:SI [(const_int 0)] UNSPEC_TOC))
9777 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
9781 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9782 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9783 operands[2] = gen_rtx_REG (Pmode, 2);
9784 return \"{l|lwz} %0,%1(%2)\";
9786 [(set_attr "type" "load")])
9788 (define_insn "load_toc_aix_di"
9789 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9790 (unspec:DI [(const_int 0)] UNSPEC_TOC))
9792 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9796 #ifdef TARGET_RELOCATABLE
9797 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9798 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9800 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9803 strcat (buf, \"@toc\");
9804 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9805 operands[2] = gen_rtx_REG (Pmode, 2);
9806 return \"ld %0,%1(%2)\";
9808 [(set_attr "type" "load")])
9810 (define_insn "load_toc_v4_pic_si"
9811 [(set (match_operand:SI 0 "register_operand" "=l")
9812 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
9813 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9814 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9815 [(set_attr "type" "branch")
9816 (set_attr "length" "4")])
9818 (define_insn "load_toc_v4_PIC_1"
9819 [(set (match_operand:SI 0 "register_operand" "=l")
9820 (match_operand:SI 1 "immediate_operand" "s"))
9821 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
9822 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
9823 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
9824 "bcl 20,31,%1\\n%1:"
9825 [(set_attr "type" "branch")
9826 (set_attr "length" "4")])
9828 (define_insn "load_toc_v4_PIC_1b"
9829 [(set (match_operand:SI 0 "register_operand" "=l")
9830 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
9832 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9833 "bcl 20,31,$+8\\n\\t.long %1-$"
9834 [(set_attr "type" "branch")
9835 (set_attr "length" "8")])
9837 (define_insn "load_toc_v4_PIC_2"
9838 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9839 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9840 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9841 (match_operand:SI 3 "immediate_operand" "s")))))]
9842 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9843 "{l|lwz} %0,%2-%3(%1)"
9844 [(set_attr "type" "load")])
9846 (define_insn "load_toc_v4_PIC_3b"
9847 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9848 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9850 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9851 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
9852 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9853 "{cau|addis} %0,%1,%2-%3@ha")
9855 (define_insn "load_toc_v4_PIC_3c"
9856 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9857 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9858 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9859 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
9860 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
9861 "{cal|addi} %0,%1,%2-%3@l")
9863 ;; If the TOC is shared over a translation unit, as happens with all
9864 ;; the kinds of PIC that we support, we need to restore the TOC
9865 ;; pointer only when jumping over units of translation.
9866 ;; On Darwin, we need to reload the picbase.
9868 (define_expand "builtin_setjmp_receiver"
9869 [(use (label_ref (match_operand 0 "" "")))]
9870 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9871 || (TARGET_TOC && TARGET_MINIMAL_TOC)
9872 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9876 if (DEFAULT_ABI == ABI_DARWIN)
9878 const char *picbase = machopic_function_base_name ();
9879 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
9880 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9884 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
9885 CODE_LABEL_NUMBER (operands[0]));
9886 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
9888 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
9889 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
9893 rs6000_emit_load_toc_table (FALSE);
9897 ;; Elf specific ways of loading addresses for non-PIC code.
9898 ;; The output of this could be r0, but we make a very strong
9899 ;; preference for a base register because it will usually
9901 (define_insn "elf_high"
9902 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
9903 (high:SI (match_operand 1 "" "")))]
9904 "TARGET_ELF && ! TARGET_64BIT"
9905 "{liu|lis} %0,%1@ha")
9907 (define_insn "elf_low"
9908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
9909 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
9910 (match_operand 2 "" "")))]
9911 "TARGET_ELF && ! TARGET_64BIT"
9913 {cal|la} %0,%2@l(%1)
9914 {ai|addic} %0,%1,%K2")
9916 ;; A function pointer under AIX is a pointer to a data area whose first word
9917 ;; contains the actual address of the function, whose second word contains a
9918 ;; pointer to its TOC, and whose third word contains a value to place in the
9919 ;; static chain register (r11). Note that if we load the static chain, our
9920 ;; "trampoline" need not have any executable code.
9922 (define_expand "call_indirect_aix32"
9924 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
9925 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9928 (mem:SI (plus:SI (match_dup 0)
9931 (mem:SI (plus:SI (match_dup 0)
9933 (parallel [(call (mem:SI (match_dup 2))
9934 (match_operand 1 "" ""))
9938 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9939 (clobber (scratch:SI))])]
9942 { operands[2] = gen_reg_rtx (SImode); }")
9944 (define_expand "call_indirect_aix64"
9946 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
9947 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9950 (mem:DI (plus:DI (match_dup 0)
9953 (mem:DI (plus:DI (match_dup 0)
9955 (parallel [(call (mem:SI (match_dup 2))
9956 (match_operand 1 "" ""))
9960 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9961 (clobber (scratch:SI))])]
9964 { operands[2] = gen_reg_rtx (DImode); }")
9966 (define_expand "call_value_indirect_aix32"
9968 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
9969 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9972 (mem:SI (plus:SI (match_dup 1)
9975 (mem:SI (plus:SI (match_dup 1)
9977 (parallel [(set (match_operand 0 "" "")
9978 (call (mem:SI (match_dup 3))
9979 (match_operand 2 "" "")))
9983 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9984 (clobber (scratch:SI))])]
9987 { operands[3] = gen_reg_rtx (SImode); }")
9989 (define_expand "call_value_indirect_aix64"
9991 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
9992 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9995 (mem:DI (plus:DI (match_dup 1)
9998 (mem:DI (plus:DI (match_dup 1)
10000 (parallel [(set (match_operand 0 "" "")
10001 (call (mem:SI (match_dup 3))
10002 (match_operand 2 "" "")))
10006 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10007 (clobber (scratch:SI))])]
10010 { operands[3] = gen_reg_rtx (DImode); }")
10012 ;; Now the definitions for the call and call_value insns
10013 (define_expand "call"
10014 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10015 (match_operand 1 "" ""))
10016 (use (match_operand 2 "" ""))
10017 (clobber (scratch:SI))])]
10022 if (MACHOPIC_INDIRECT)
10023 operands[0] = machopic_indirect_call_target (operands[0]);
10026 gcc_assert (GET_CODE (operands[0]) == MEM);
10027 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10029 operands[0] = XEXP (operands[0], 0);
10031 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10033 && GET_CODE (operands[0]) == SYMBOL_REF
10034 && !SYMBOL_REF_LOCAL_P (operands[0]))
10039 tmp = gen_rtvec (3,
10040 gen_rtx_CALL (VOIDmode,
10041 gen_rtx_MEM (SImode, operands[0]),
10043 gen_rtx_USE (VOIDmode, operands[2]),
10044 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10045 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10046 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10050 if (GET_CODE (operands[0]) != SYMBOL_REF
10051 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10052 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10054 if (INTVAL (operands[2]) & CALL_LONG)
10055 operands[0] = rs6000_longcall_ref (operands[0]);
10057 switch (DEFAULT_ABI)
10061 operands[0] = force_reg (Pmode, operands[0]);
10065 /* AIX function pointers are really pointers to a three word
10067 emit_call_insn (TARGET_32BIT
10068 ? gen_call_indirect_aix32 (force_reg (SImode,
10071 : gen_call_indirect_aix64 (force_reg (DImode,
10077 gcc_unreachable ();
10082 (define_expand "call_value"
10083 [(parallel [(set (match_operand 0 "" "")
10084 (call (mem:SI (match_operand 1 "address_operand" ""))
10085 (match_operand 2 "" "")))
10086 (use (match_operand 3 "" ""))
10087 (clobber (scratch:SI))])]
10092 if (MACHOPIC_INDIRECT)
10093 operands[1] = machopic_indirect_call_target (operands[1]);
10096 gcc_assert (GET_CODE (operands[1]) == MEM);
10097 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10099 operands[1] = XEXP (operands[1], 0);
10101 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10103 && GET_CODE (operands[1]) == SYMBOL_REF
10104 && !SYMBOL_REF_LOCAL_P (operands[1]))
10109 tmp = gen_rtvec (3,
10110 gen_rtx_SET (VOIDmode,
10112 gen_rtx_CALL (VOIDmode,
10113 gen_rtx_MEM (SImode,
10116 gen_rtx_USE (VOIDmode, operands[3]),
10117 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10118 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10119 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10123 if (GET_CODE (operands[1]) != SYMBOL_REF
10124 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10125 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10127 if (INTVAL (operands[3]) & CALL_LONG)
10128 operands[1] = rs6000_longcall_ref (operands[1]);
10130 switch (DEFAULT_ABI)
10134 operands[1] = force_reg (Pmode, operands[1]);
10138 /* AIX function pointers are really pointers to a three word
10140 emit_call_insn (TARGET_32BIT
10141 ? gen_call_value_indirect_aix32 (operands[0],
10145 : gen_call_value_indirect_aix64 (operands[0],
10152 gcc_unreachable ();
10157 ;; Call to function in current module. No TOC pointer reload needed.
10158 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10159 ;; either the function was not prototyped, or it was prototyped as a
10160 ;; variable argument function. It is > 0 if FP registers were passed
10161 ;; and < 0 if they were not.
10163 (define_insn "*call_local32"
10164 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10165 (match_operand 1 "" "g,g"))
10166 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10167 (clobber (match_scratch:SI 3 "=l,l"))]
10168 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10171 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10172 output_asm_insn (\"crxor 6,6,6\", operands);
10174 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10175 output_asm_insn (\"creqv 6,6,6\", operands);
10177 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10179 [(set_attr "type" "branch")
10180 (set_attr "length" "4,8")])
10182 (define_insn "*call_local64"
10183 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10184 (match_operand 1 "" "g,g"))
10185 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10186 (clobber (match_scratch:SI 3 "=l,l"))]
10187 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10190 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10191 output_asm_insn (\"crxor 6,6,6\", operands);
10193 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10194 output_asm_insn (\"creqv 6,6,6\", operands);
10196 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10198 [(set_attr "type" "branch")
10199 (set_attr "length" "4,8")])
10201 (define_insn "*call_value_local32"
10202 [(set (match_operand 0 "" "")
10203 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10204 (match_operand 2 "" "g,g")))
10205 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10206 (clobber (match_scratch:SI 4 "=l,l"))]
10207 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10210 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10211 output_asm_insn (\"crxor 6,6,6\", operands);
10213 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10214 output_asm_insn (\"creqv 6,6,6\", operands);
10216 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10218 [(set_attr "type" "branch")
10219 (set_attr "length" "4,8")])
10222 (define_insn "*call_value_local64"
10223 [(set (match_operand 0 "" "")
10224 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10225 (match_operand 2 "" "g,g")))
10226 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10227 (clobber (match_scratch:SI 4 "=l,l"))]
10228 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10231 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10232 output_asm_insn (\"crxor 6,6,6\", operands);
10234 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10235 output_asm_insn (\"creqv 6,6,6\", operands);
10237 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10239 [(set_attr "type" "branch")
10240 (set_attr "length" "4,8")])
10242 ;; Call to function which may be in another module. Restore the TOC
10243 ;; pointer (r2) after the call unless this is System V.
10244 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10245 ;; either the function was not prototyped, or it was prototyped as a
10246 ;; variable argument function. It is > 0 if FP registers were passed
10247 ;; and < 0 if they were not.
10249 (define_insn "*call_indirect_nonlocal_aix32"
10250 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10251 (match_operand 1 "" "g,g"))
10255 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10256 (clobber (match_scratch:SI 2 "=l,l"))]
10257 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10258 "b%T0l\;{l|lwz} 2,20(1)"
10259 [(set_attr "type" "jmpreg")
10260 (set_attr "length" "8")])
10262 (define_insn "*call_nonlocal_aix32"
10263 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10264 (match_operand 1 "" "g"))
10265 (use (match_operand:SI 2 "immediate_operand" "O"))
10266 (clobber (match_scratch:SI 3 "=l"))]
10268 && DEFAULT_ABI == ABI_AIX
10269 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10271 [(set_attr "type" "branch")
10272 (set_attr "length" "8")])
10274 (define_insn "*call_indirect_nonlocal_aix64"
10275 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10276 (match_operand 1 "" "g,g"))
10280 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10281 (clobber (match_scratch:SI 2 "=l,l"))]
10282 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10283 "b%T0l\;ld 2,40(1)"
10284 [(set_attr "type" "jmpreg")
10285 (set_attr "length" "8")])
10287 (define_insn "*call_nonlocal_aix64"
10288 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10289 (match_operand 1 "" "g"))
10290 (use (match_operand:SI 2 "immediate_operand" "O"))
10291 (clobber (match_scratch:SI 3 "=l"))]
10293 && DEFAULT_ABI == ABI_AIX
10294 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10296 [(set_attr "type" "branch")
10297 (set_attr "length" "8")])
10299 (define_insn "*call_value_indirect_nonlocal_aix32"
10300 [(set (match_operand 0 "" "")
10301 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10302 (match_operand 2 "" "g,g")))
10306 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10307 (clobber (match_scratch:SI 3 "=l,l"))]
10308 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10309 "b%T1l\;{l|lwz} 2,20(1)"
10310 [(set_attr "type" "jmpreg")
10311 (set_attr "length" "8")])
10313 (define_insn "*call_value_nonlocal_aix32"
10314 [(set (match_operand 0 "" "")
10315 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10316 (match_operand 2 "" "g")))
10317 (use (match_operand:SI 3 "immediate_operand" "O"))
10318 (clobber (match_scratch:SI 4 "=l"))]
10320 && DEFAULT_ABI == ABI_AIX
10321 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10323 [(set_attr "type" "branch")
10324 (set_attr "length" "8")])
10326 (define_insn "*call_value_indirect_nonlocal_aix64"
10327 [(set (match_operand 0 "" "")
10328 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
10329 (match_operand 2 "" "g,g")))
10333 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10334 (clobber (match_scratch:SI 3 "=l,l"))]
10335 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10336 "b%T1l\;ld 2,40(1)"
10337 [(set_attr "type" "jmpreg")
10338 (set_attr "length" "8")])
10340 (define_insn "*call_value_nonlocal_aix64"
10341 [(set (match_operand 0 "" "")
10342 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10343 (match_operand 2 "" "g")))
10344 (use (match_operand:SI 3 "immediate_operand" "O"))
10345 (clobber (match_scratch:SI 4 "=l"))]
10347 && DEFAULT_ABI == ABI_AIX
10348 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10350 [(set_attr "type" "branch")
10351 (set_attr "length" "8")])
10353 ;; A function pointer under System V is just a normal pointer
10354 ;; operands[0] is the function pointer
10355 ;; operands[1] is the stack size to clean up
10356 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10357 ;; which indicates how to set cr1
10359 (define_insn "*call_indirect_nonlocal_sysv"
10360 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l,c,*l"))
10361 (match_operand 1 "" "g,g,g,g"))
10362 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10363 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
10364 "DEFAULT_ABI == ABI_V4
10365 || DEFAULT_ABI == ABI_DARWIN"
10367 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10368 output_asm_insn ("crxor 6,6,6", operands);
10370 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10371 output_asm_insn ("creqv 6,6,6", operands);
10375 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10376 (set_attr "length" "4,4,8,8")])
10378 (define_insn "*call_nonlocal_sysv"
10379 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10380 (match_operand 1 "" "g,g"))
10381 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10382 (clobber (match_scratch:SI 3 "=l,l"))]
10383 "(DEFAULT_ABI == ABI_DARWIN
10384 || (DEFAULT_ABI == ABI_V4
10385 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10387 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10388 output_asm_insn ("crxor 6,6,6", operands);
10390 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10391 output_asm_insn ("creqv 6,6,6", operands);
10394 return output_call(insn, operands, 0, 2);
10396 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10398 if (TARGET_SECURE_PLT && flag_pic == 2)
10399 /* The magic 32768 offset here and in the other sysv call insns
10400 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10401 See sysv4.h:toc_section. */
10402 return "bl %z0+32768@plt";
10404 return "bl %z0@plt";
10410 [(set_attr "type" "branch,branch")
10411 (set_attr "length" "4,8")])
10413 (define_insn "*call_value_indirect_nonlocal_sysv"
10414 [(set (match_operand 0 "" "")
10415 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l,c,*l"))
10416 (match_operand 2 "" "g,g,g,g")))
10417 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10418 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
10419 "DEFAULT_ABI == ABI_V4
10420 || DEFAULT_ABI == ABI_DARWIN"
10422 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10423 output_asm_insn ("crxor 6,6,6", operands);
10425 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10426 output_asm_insn ("creqv 6,6,6", operands);
10430 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10431 (set_attr "length" "4,4,8,8")])
10433 (define_insn "*call_value_nonlocal_sysv"
10434 [(set (match_operand 0 "" "")
10435 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10436 (match_operand 2 "" "g,g")))
10437 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10438 (clobber (match_scratch:SI 4 "=l,l"))]
10439 "(DEFAULT_ABI == ABI_DARWIN
10440 || (DEFAULT_ABI == ABI_V4
10441 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10443 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10444 output_asm_insn ("crxor 6,6,6", operands);
10446 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10447 output_asm_insn ("creqv 6,6,6", operands);
10450 return output_call(insn, operands, 1, 3);
10452 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10454 if (TARGET_SECURE_PLT && flag_pic == 2)
10455 return "bl %z1+32768@plt";
10457 return "bl %z1@plt";
10463 [(set_attr "type" "branch,branch")
10464 (set_attr "length" "4,8")])
10466 ;; Call subroutine returning any type.
10467 (define_expand "untyped_call"
10468 [(parallel [(call (match_operand 0 "" "")
10470 (match_operand 1 "" "")
10471 (match_operand 2 "" "")])]
10477 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10479 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10481 rtx set = XVECEXP (operands[2], 0, i);
10482 emit_move_insn (SET_DEST (set), SET_SRC (set));
10485 /* The optimizer does not know that the call sets the function value
10486 registers we stored in the result block. We avoid problems by
10487 claiming that all hard registers are used and clobbered at this
10489 emit_insn (gen_blockage ());
10494 ;; sibling call patterns
10495 (define_expand "sibcall"
10496 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10497 (match_operand 1 "" ""))
10498 (use (match_operand 2 "" ""))
10499 (use (match_operand 3 "" ""))
10505 if (MACHOPIC_INDIRECT)
10506 operands[0] = machopic_indirect_call_target (operands[0]);
10509 gcc_assert (GET_CODE (operands[0]) == MEM);
10510 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10512 operands[0] = XEXP (operands[0], 0);
10513 operands[3] = gen_reg_rtx (SImode);
10517 ;; this and similar patterns must be marked as using LR, otherwise
10518 ;; dataflow will try to delete the store into it. This is true
10519 ;; even when the actual reg to jump to is in CTR, when LR was
10520 ;; saved and restored around the PIC-setting BCL.
10521 (define_insn "*sibcall_local32"
10522 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10523 (match_operand 1 "" "g,g"))
10524 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10525 (use (match_operand:SI 3 "register_operand" "l,l"))
10527 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10530 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10531 output_asm_insn (\"crxor 6,6,6\", operands);
10533 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10534 output_asm_insn (\"creqv 6,6,6\", operands);
10536 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10538 [(set_attr "type" "branch")
10539 (set_attr "length" "4,8")])
10541 (define_insn "*sibcall_local64"
10542 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10543 (match_operand 1 "" "g,g"))
10544 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10545 (use (match_operand:SI 3 "register_operand" "l,l"))
10547 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10550 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10551 output_asm_insn (\"crxor 6,6,6\", operands);
10553 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10554 output_asm_insn (\"creqv 6,6,6\", operands);
10556 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10558 [(set_attr "type" "branch")
10559 (set_attr "length" "4,8")])
10561 (define_insn "*sibcall_value_local32"
10562 [(set (match_operand 0 "" "")
10563 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10564 (match_operand 2 "" "g,g")))
10565 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10566 (use (match_operand:SI 4 "register_operand" "l,l"))
10568 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10571 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10572 output_asm_insn (\"crxor 6,6,6\", operands);
10574 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10575 output_asm_insn (\"creqv 6,6,6\", operands);
10577 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10579 [(set_attr "type" "branch")
10580 (set_attr "length" "4,8")])
10583 (define_insn "*sibcall_value_local64"
10584 [(set (match_operand 0 "" "")
10585 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10586 (match_operand 2 "" "g,g")))
10587 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10588 (use (match_operand:SI 4 "register_operand" "l,l"))
10590 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10593 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10594 output_asm_insn (\"crxor 6,6,6\", operands);
10596 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10597 output_asm_insn (\"creqv 6,6,6\", operands);
10599 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10601 [(set_attr "type" "branch")
10602 (set_attr "length" "4,8")])
10604 (define_insn "*sibcall_nonlocal_aix32"
10605 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10606 (match_operand 1 "" "g"))
10607 (use (match_operand:SI 2 "immediate_operand" "O"))
10608 (use (match_operand:SI 3 "register_operand" "l"))
10611 && DEFAULT_ABI == ABI_AIX
10612 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10614 [(set_attr "type" "branch")
10615 (set_attr "length" "4")])
10617 (define_insn "*sibcall_nonlocal_aix64"
10618 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10619 (match_operand 1 "" "g"))
10620 (use (match_operand:SI 2 "immediate_operand" "O"))
10621 (use (match_operand:SI 3 "register_operand" "l"))
10624 && DEFAULT_ABI == ABI_AIX
10625 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10627 [(set_attr "type" "branch")
10628 (set_attr "length" "4")])
10630 (define_insn "*sibcall_value_nonlocal_aix32"
10631 [(set (match_operand 0 "" "")
10632 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10633 (match_operand 2 "" "g")))
10634 (use (match_operand:SI 3 "immediate_operand" "O"))
10635 (use (match_operand:SI 4 "register_operand" "l"))
10638 && DEFAULT_ABI == ABI_AIX
10639 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10641 [(set_attr "type" "branch")
10642 (set_attr "length" "4")])
10644 (define_insn "*sibcall_value_nonlocal_aix64"
10645 [(set (match_operand 0 "" "")
10646 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10647 (match_operand 2 "" "g")))
10648 (use (match_operand:SI 3 "immediate_operand" "O"))
10649 (use (match_operand:SI 4 "register_operand" "l"))
10652 && DEFAULT_ABI == ABI_AIX
10653 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10655 [(set_attr "type" "branch")
10656 (set_attr "length" "4")])
10658 (define_insn "*sibcall_nonlocal_sysv"
10659 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10660 (match_operand 1 "" ""))
10661 (use (match_operand 2 "immediate_operand" "O,n"))
10662 (use (match_operand:SI 3 "register_operand" "l,l"))
10664 "(DEFAULT_ABI == ABI_DARWIN
10665 || DEFAULT_ABI == ABI_V4)
10666 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10669 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10670 output_asm_insn (\"crxor 6,6,6\", operands);
10672 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10673 output_asm_insn (\"creqv 6,6,6\", operands);
10675 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10677 if (TARGET_SECURE_PLT && flag_pic == 2)
10678 return \"b %z0+32768@plt\";
10680 return \"b %z0@plt\";
10685 [(set_attr "type" "branch,branch")
10686 (set_attr "length" "4,8")])
10688 (define_expand "sibcall_value"
10689 [(parallel [(set (match_operand 0 "register_operand" "")
10690 (call (mem:SI (match_operand 1 "address_operand" ""))
10691 (match_operand 2 "" "")))
10692 (use (match_operand 3 "" ""))
10693 (use (match_operand 4 "" ""))
10699 if (MACHOPIC_INDIRECT)
10700 operands[1] = machopic_indirect_call_target (operands[1]);
10703 gcc_assert (GET_CODE (operands[1]) == MEM);
10704 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10706 operands[1] = XEXP (operands[1], 0);
10707 operands[4] = gen_reg_rtx (SImode);
10711 (define_insn "*sibcall_value_nonlocal_sysv"
10712 [(set (match_operand 0 "" "")
10713 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10714 (match_operand 2 "" "")))
10715 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10716 (use (match_operand:SI 4 "register_operand" "l,l"))
10718 "(DEFAULT_ABI == ABI_DARWIN
10719 || DEFAULT_ABI == ABI_V4)
10720 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10723 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10724 output_asm_insn (\"crxor 6,6,6\", operands);
10726 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10727 output_asm_insn (\"creqv 6,6,6\", operands);
10729 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10731 if (TARGET_SECURE_PLT && flag_pic == 2)
10732 return \"b %z1+32768@plt\";
10734 return \"b %z1@plt\";
10739 [(set_attr "type" "branch,branch")
10740 (set_attr "length" "4,8")])
10742 (define_expand "sibcall_epilogue"
10743 [(use (const_int 0))]
10744 "TARGET_SCHED_PROLOG"
10747 rs6000_emit_epilogue (TRUE);
10751 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10752 ;; all of memory. This blocks insns from being moved across this point.
10754 (define_insn "blockage"
10755 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10759 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10760 ;; signed & unsigned, and one type of branch.
10762 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10763 ;; insns, and branches. We store the operands of compares until we see
10765 (define_expand "cmpsi"
10767 (compare (match_operand:SI 0 "gpc_reg_operand" "")
10768 (match_operand:SI 1 "reg_or_short_operand" "")))]
10772 /* Take care of the possibility that operands[1] might be negative but
10773 this might be a logical operation. That insn doesn't exist. */
10774 if (GET_CODE (operands[1]) == CONST_INT
10775 && INTVAL (operands[1]) < 0)
10776 operands[1] = force_reg (SImode, operands[1]);
10778 rs6000_compare_op0 = operands[0];
10779 rs6000_compare_op1 = operands[1];
10780 rs6000_compare_fp_p = 0;
10784 (define_expand "cmpdi"
10786 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10787 (match_operand:DI 1 "reg_or_short_operand" "")))]
10791 /* Take care of the possibility that operands[1] might be negative but
10792 this might be a logical operation. That insn doesn't exist. */
10793 if (GET_CODE (operands[1]) == CONST_INT
10794 && INTVAL (operands[1]) < 0)
10795 operands[1] = force_reg (DImode, operands[1]);
10797 rs6000_compare_op0 = operands[0];
10798 rs6000_compare_op1 = operands[1];
10799 rs6000_compare_fp_p = 0;
10803 (define_expand "cmpsf"
10804 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
10805 (match_operand:SF 1 "gpc_reg_operand" "")))]
10806 "TARGET_HARD_FLOAT"
10809 rs6000_compare_op0 = operands[0];
10810 rs6000_compare_op1 = operands[1];
10811 rs6000_compare_fp_p = 1;
10815 (define_expand "cmpdf"
10816 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
10817 (match_operand:DF 1 "gpc_reg_operand" "")))]
10818 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
10821 rs6000_compare_op0 = operands[0];
10822 rs6000_compare_op1 = operands[1];
10823 rs6000_compare_fp_p = 1;
10827 (define_expand "cmptf"
10828 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
10829 (match_operand:TF 1 "gpc_reg_operand" "")))]
10830 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10831 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10834 rs6000_compare_op0 = operands[0];
10835 rs6000_compare_op1 = operands[1];
10836 rs6000_compare_fp_p = 1;
10840 (define_expand "beq"
10841 [(use (match_operand 0 "" ""))]
10843 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10845 (define_expand "bne"
10846 [(use (match_operand 0 "" ""))]
10848 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10850 (define_expand "bge"
10851 [(use (match_operand 0 "" ""))]
10853 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10855 (define_expand "bgt"
10856 [(use (match_operand 0 "" ""))]
10858 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10860 (define_expand "ble"
10861 [(use (match_operand 0 "" ""))]
10863 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10865 (define_expand "blt"
10866 [(use (match_operand 0 "" ""))]
10868 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10870 (define_expand "bgeu"
10871 [(use (match_operand 0 "" ""))]
10873 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10875 (define_expand "bgtu"
10876 [(use (match_operand 0 "" ""))]
10878 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
10880 (define_expand "bleu"
10881 [(use (match_operand 0 "" ""))]
10883 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
10885 (define_expand "bltu"
10886 [(use (match_operand 0 "" ""))]
10888 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
10890 (define_expand "bunordered"
10891 [(use (match_operand 0 "" ""))]
10892 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10893 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
10895 (define_expand "bordered"
10896 [(use (match_operand 0 "" ""))]
10897 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
10898 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
10900 (define_expand "buneq"
10901 [(use (match_operand 0 "" ""))]
10903 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
10905 (define_expand "bunge"
10906 [(use (match_operand 0 "" ""))]
10908 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
10910 (define_expand "bungt"
10911 [(use (match_operand 0 "" ""))]
10913 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
10915 (define_expand "bunle"
10916 [(use (match_operand 0 "" ""))]
10918 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
10920 (define_expand "bunlt"
10921 [(use (match_operand 0 "" ""))]
10923 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
10925 (define_expand "bltgt"
10926 [(use (match_operand 0 "" ""))]
10928 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
10930 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
10931 ;; For SEQ, likewise, except that comparisons with zero should be done
10932 ;; with an scc insns. However, due to the order that combine see the
10933 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
10934 ;; the cases we don't want to handle.
10935 (define_expand "seq"
10936 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10938 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
10940 (define_expand "sne"
10941 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10945 if (! rs6000_compare_fp_p)
10948 rs6000_emit_sCOND (NE, operands[0]);
10952 ;; A >= 0 is best done the portable way for A an integer.
10953 (define_expand "sge"
10954 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10958 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10961 rs6000_emit_sCOND (GE, operands[0]);
10965 ;; A > 0 is best done using the portable sequence, so fail in that case.
10966 (define_expand "sgt"
10967 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10971 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10974 rs6000_emit_sCOND (GT, operands[0]);
10978 ;; A <= 0 is best done the portable way for A an integer.
10979 (define_expand "sle"
10980 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10984 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
10987 rs6000_emit_sCOND (LE, operands[0]);
10991 ;; A < 0 is best done in the portable way for A an integer.
10992 (define_expand "slt"
10993 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10997 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11000 rs6000_emit_sCOND (LT, operands[0]);
11004 (define_expand "sgeu"
11005 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11007 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11009 (define_expand "sgtu"
11010 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11012 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11014 (define_expand "sleu"
11015 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11017 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11019 (define_expand "sltu"
11020 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11022 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11024 (define_expand "sunordered"
11025 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11026 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11027 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11029 (define_expand "sordered"
11030 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11031 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11032 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11034 (define_expand "suneq"
11035 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11037 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11039 (define_expand "sunge"
11040 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11042 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11044 (define_expand "sungt"
11045 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11047 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11049 (define_expand "sunle"
11050 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11052 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11054 (define_expand "sunlt"
11055 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11057 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11059 (define_expand "sltgt"
11060 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11062 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11065 ;; Here are the actual compare insns.
11066 (define_insn "*cmpsi_internal1"
11067 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11068 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11069 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11071 "{cmp%I2|cmpw%I2} %0,%1,%2"
11072 [(set_attr "type" "cmp")])
11074 (define_insn "*cmpdi_internal1"
11075 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11076 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
11077 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11080 [(set_attr "type" "cmp")])
11082 ;; If we are comparing a register for equality with a large constant,
11083 ;; we can do this with an XOR followed by a compare. But we need a scratch
11084 ;; register for the result of the XOR.
11087 [(set (match_operand:CC 0 "cc_reg_operand" "")
11088 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11089 (match_operand:SI 2 "non_short_cint_operand" "")))
11090 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
11091 "find_single_use (operands[0], insn, 0)
11092 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
11093 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
11094 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
11095 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
11098 /* Get the constant we are comparing against, C, and see what it looks like
11099 sign-extended to 16 bits. Then see what constant could be XOR'ed
11100 with C to get the sign-extended value. */
11102 HOST_WIDE_INT c = INTVAL (operands[2]);
11103 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11104 HOST_WIDE_INT xorv = c ^ sextc;
11106 operands[4] = GEN_INT (xorv);
11107 operands[5] = GEN_INT (sextc);
11110 (define_insn "*cmpsi_internal2"
11111 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11112 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11113 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11115 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11116 [(set_attr "type" "cmp")])
11118 (define_insn "*cmpdi_internal2"
11119 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11120 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11121 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11123 "cmpld%I2 %0,%1,%b2"
11124 [(set_attr "type" "cmp")])
11126 ;; The following two insns don't exist as single insns, but if we provide
11127 ;; them, we can swap an add and compare, which will enable us to overlap more
11128 ;; of the required delay between a compare and branch. We generate code for
11129 ;; them by splitting.
11132 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11133 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11134 (match_operand:SI 2 "short_cint_operand" "i")))
11135 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11136 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11139 [(set_attr "length" "8")])
11142 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11143 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11144 (match_operand:SI 2 "u_short_cint_operand" "i")))
11145 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11146 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11149 [(set_attr "length" "8")])
11152 [(set (match_operand:CC 3 "cc_reg_operand" "")
11153 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11154 (match_operand:SI 2 "short_cint_operand" "")))
11155 (set (match_operand:SI 0 "gpc_reg_operand" "")
11156 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11158 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11159 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11162 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11163 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11164 (match_operand:SI 2 "u_short_cint_operand" "")))
11165 (set (match_operand:SI 0 "gpc_reg_operand" "")
11166 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11168 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11169 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11171 (define_insn "*cmpsf_internal1"
11172 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11173 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11174 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11175 "TARGET_HARD_FLOAT && TARGET_FPRS"
11177 [(set_attr "type" "fpcompare")])
11179 (define_insn "*cmpdf_internal1"
11180 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11181 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11182 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11183 "TARGET_HARD_FLOAT && TARGET_FPRS"
11185 [(set_attr "type" "fpcompare")])
11187 ;; Only need to compare second words if first words equal
11188 (define_insn "*cmptf_internal1"
11189 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11190 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11191 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11192 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
11193 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11194 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11195 [(set_attr "type" "fpcompare")
11196 (set_attr "length" "12")])
11198 (define_insn_and_split "*cmptf_internal2"
11199 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11200 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11201 (match_operand:TF 2 "gpc_reg_operand" "f")))
11202 (clobber (match_scratch:DF 3 "=f"))
11203 (clobber (match_scratch:DF 4 "=f"))
11204 (clobber (match_scratch:DF 5 "=f"))
11205 (clobber (match_scratch:DF 6 "=f"))
11206 (clobber (match_scratch:DF 7 "=f"))
11207 (clobber (match_scratch:DF 8 "=f"))
11208 (clobber (match_scratch:DF 9 "=f"))
11209 (clobber (match_scratch:DF 10 "=f"))]
11210 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
11211 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11213 "&& reload_completed"
11214 [(set (match_dup 3) (match_dup 13))
11215 (set (match_dup 4) (match_dup 14))
11216 (set (match_dup 9) (abs:DF (match_dup 5)))
11217 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11218 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11219 (label_ref (match_dup 11))
11221 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11222 (set (pc) (label_ref (match_dup 12)))
11224 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11225 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11226 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11227 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11230 REAL_VALUE_TYPE rv;
11231 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11232 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11234 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11235 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11236 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11237 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11238 operands[11] = gen_label_rtx ();
11239 operands[12] = gen_label_rtx ();
11241 operands[13] = force_const_mem (DFmode,
11242 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11243 operands[14] = force_const_mem (DFmode,
11244 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11248 operands[13] = gen_const_mem (DFmode,
11249 create_TOC_reference (XEXP (operands[13], 0)));
11250 operands[14] = gen_const_mem (DFmode,
11251 create_TOC_reference (XEXP (operands[14], 0)));
11252 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11253 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11257 ;; Now we have the scc insns. We can do some combinations because of the
11258 ;; way the machine works.
11260 ;; Note that this is probably faster if we can put an insn between the
11261 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11262 ;; cases the insns below which don't use an intermediate CR field will
11263 ;; be used instead.
11265 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11266 (match_operator:SI 1 "scc_comparison_operator"
11267 [(match_operand 2 "cc_reg_operand" "y")
11270 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11271 [(set (attr "type")
11272 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11273 (const_string "mfcrf")
11275 (const_string "mfcr")))
11276 (set_attr "length" "8")])
11278 ;; Same as above, but get the GT bit.
11279 (define_insn "move_from_CR_gt_bit"
11280 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11281 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11283 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
11284 [(set_attr "type" "mfcr")
11285 (set_attr "length" "8")])
11287 ;; Same as above, but get the OV/ORDERED bit.
11288 (define_insn "move_from_CR_ov_bit"
11289 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11290 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11292 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11293 [(set_attr "type" "mfcr")
11294 (set_attr "length" "8")])
11297 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11298 (match_operator:DI 1 "scc_comparison_operator"
11299 [(match_operand 2 "cc_reg_operand" "y")
11302 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11303 [(set (attr "type")
11304 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11305 (const_string "mfcrf")
11307 (const_string "mfcr")))
11308 (set_attr "length" "8")])
11311 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11312 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11313 [(match_operand 2 "cc_reg_operand" "y,y")
11316 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11317 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11320 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11322 [(set_attr "type" "delayed_compare")
11323 (set_attr "length" "8,16")])
11326 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11327 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11328 [(match_operand 2 "cc_reg_operand" "")
11331 (set (match_operand:SI 3 "gpc_reg_operand" "")
11332 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11333 "TARGET_32BIT && reload_completed"
11334 [(set (match_dup 3)
11335 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11337 (compare:CC (match_dup 3)
11342 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11343 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11344 [(match_operand 2 "cc_reg_operand" "y")
11346 (match_operand:SI 3 "const_int_operand" "n")))]
11350 int is_bit = ccr_bit (operands[1], 1);
11351 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11354 if (is_bit >= put_bit)
11355 count = is_bit - put_bit;
11357 count = 32 - (put_bit - is_bit);
11359 operands[4] = GEN_INT (count);
11360 operands[5] = GEN_INT (put_bit);
11362 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11364 [(set (attr "type")
11365 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11366 (const_string "mfcrf")
11368 (const_string "mfcr")))
11369 (set_attr "length" "8")])
11372 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11374 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11375 [(match_operand 2 "cc_reg_operand" "y,y")
11377 (match_operand:SI 3 "const_int_operand" "n,n"))
11379 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11380 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11385 int is_bit = ccr_bit (operands[1], 1);
11386 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11389 /* Force split for non-cc0 compare. */
11390 if (which_alternative == 1)
11393 if (is_bit >= put_bit)
11394 count = is_bit - put_bit;
11396 count = 32 - (put_bit - is_bit);
11398 operands[5] = GEN_INT (count);
11399 operands[6] = GEN_INT (put_bit);
11401 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11403 [(set_attr "type" "delayed_compare")
11404 (set_attr "length" "8,16")])
11407 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11409 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11410 [(match_operand 2 "cc_reg_operand" "")
11412 (match_operand:SI 3 "const_int_operand" ""))
11414 (set (match_operand:SI 4 "gpc_reg_operand" "")
11415 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11418 [(set (match_dup 4)
11419 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11422 (compare:CC (match_dup 4)
11426 ;; There is a 3 cycle delay between consecutive mfcr instructions
11427 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11430 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11431 (match_operator:SI 1 "scc_comparison_operator"
11432 [(match_operand 2 "cc_reg_operand" "y")
11434 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11435 (match_operator:SI 4 "scc_comparison_operator"
11436 [(match_operand 5 "cc_reg_operand" "y")
11438 "REGNO (operands[2]) != REGNO (operands[5])"
11439 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11440 [(set_attr "type" "mfcr")
11441 (set_attr "length" "12")])
11444 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11445 (match_operator:DI 1 "scc_comparison_operator"
11446 [(match_operand 2 "cc_reg_operand" "y")
11448 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11449 (match_operator:DI 4 "scc_comparison_operator"
11450 [(match_operand 5 "cc_reg_operand" "y")
11452 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11453 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11454 [(set_attr "type" "mfcr")
11455 (set_attr "length" "12")])
11457 ;; There are some scc insns that can be done directly, without a compare.
11458 ;; These are faster because they don't involve the communications between
11459 ;; the FXU and branch units. In fact, we will be replacing all of the
11460 ;; integer scc insns here or in the portable methods in emit_store_flag.
11462 ;; Also support (neg (scc ..)) since that construct is used to replace
11463 ;; branches, (plus (scc ..) ..) since that construct is common and
11464 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11465 ;; cases where it is no more expensive than (neg (scc ..)).
11467 ;; Have reload force a constant into a register for the simple insns that
11468 ;; otherwise won't accept constants. We do this because it is faster than
11469 ;; the cmp/mfcr sequence we would otherwise generate.
11471 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11474 (define_insn_and_split "*eq<mode>"
11475 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11476 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11477 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))
11478 (clobber (match_scratch:GPR 3 "=r"))
11479 (clobber (match_scratch:GPR 4 "=r"))]
11483 [(set (match_dup 3)
11484 (clz:GPR (match_dup 4)))
11486 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
11488 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11490 if (logical_operand (operands[2], <MODE>mode))
11491 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11492 gen_rtx_XOR (<MODE>mode,
11493 operands[1], operands[2])));
11495 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11496 gen_rtx_PLUS (<MODE>mode, operands[1],
11497 negate_rtx (<MODE>mode,
11501 operands[4] = operands[1];
11503 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11506 (define_insn_and_split "*eq<mode>_compare"
11507 [(set (match_operand:CC 5 "cc_reg_operand" "=y")
11509 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "=r")
11510 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>"))
11512 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11513 (eq:GPR (match_dup 1) (match_dup 2)))
11514 (clobber (match_scratch:GPR 3 "=r"))
11515 (clobber (match_scratch:GPR 4 "=r"))]
11519 [(set (match_dup 3)
11520 (clz:GPR (match_dup 4)))
11521 (parallel [(set (match_dup 5)
11522 (compare:CC (lshiftrt:GPR (match_dup 3) (match_dup 6))
11525 (lshiftrt:GPR (match_dup 3) (match_dup 6)))])]
11527 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11529 if (logical_operand (operands[2], <MODE>mode))
11530 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11531 gen_rtx_XOR (<MODE>mode,
11532 operands[1], operands[2])));
11534 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11535 gen_rtx_PLUS (<MODE>mode, operands[1],
11536 negate_rtx (<MODE>mode,
11540 operands[4] = operands[1];
11542 operands[6] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11545 ;; We have insns of the form shown by the first define_insn below. If
11546 ;; there is something inside the comparison operation, we must split it.
11548 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11549 (plus:SI (match_operator 1 "comparison_operator"
11550 [(match_operand:SI 2 "" "")
11551 (match_operand:SI 3
11552 "reg_or_cint_operand" "")])
11553 (match_operand:SI 4 "gpc_reg_operand" "")))
11554 (clobber (match_operand:SI 5 "register_operand" ""))]
11555 "! gpc_reg_operand (operands[2], SImode)"
11556 [(set (match_dup 5) (match_dup 2))
11557 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11561 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11562 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11563 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
11564 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11567 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11568 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11569 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11570 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11571 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11572 [(set_attr "type" "three,two,three,three,three")
11573 (set_attr "length" "12,8,12,12,12")])
11576 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11579 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11580 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11581 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11583 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11586 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11587 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11588 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11589 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11590 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11596 [(set_attr "type" "compare")
11597 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11600 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11603 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11604 (match_operand:SI 2 "reg_or_cint_operand" ""))
11605 (match_operand:SI 3 "gpc_reg_operand" ""))
11607 (clobber (match_scratch:SI 4 ""))]
11608 "TARGET_32BIT && reload_completed"
11609 [(set (match_dup 4)
11610 (plus:SI (eq:SI (match_dup 1)
11614 (compare:CC (match_dup 4)
11619 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11622 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11623 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11624 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11626 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11627 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11630 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11631 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11632 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11633 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11634 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11640 [(set_attr "type" "compare")
11641 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11644 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11647 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11648 (match_operand:SI 2 "reg_or_cint_operand" ""))
11649 (match_operand:SI 3 "gpc_reg_operand" ""))
11651 (set (match_operand:SI 0 "gpc_reg_operand" "")
11652 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11653 "TARGET_32BIT && reload_completed"
11654 [(set (match_dup 0)
11655 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11657 (compare:CC (match_dup 0)
11662 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11663 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11664 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
11667 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11668 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11669 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11670 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11671 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11672 [(set_attr "type" "three,two,three,three,three")
11673 (set_attr "length" "12,8,12,12,12")])
11675 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11676 ;; since it nabs/sr is just as fast.
11677 (define_insn "*ne0"
11678 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11679 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11681 (clobber (match_scratch:SI 2 "=&r"))]
11682 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11683 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11684 [(set_attr "type" "two")
11685 (set_attr "length" "8")])
11688 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11689 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11691 (clobber (match_scratch:DI 2 "=&r"))]
11693 "addic %2,%1,-1\;subfe %0,%2,%1"
11694 [(set_attr "type" "two")
11695 (set_attr "length" "8")])
11697 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11699 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11700 (plus:SI (lshiftrt:SI
11701 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11703 (match_operand:SI 2 "gpc_reg_operand" "r")))
11704 (clobber (match_scratch:SI 3 "=&r"))]
11706 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11707 [(set_attr "type" "two")
11708 (set_attr "length" "8")])
11711 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11712 (plus:DI (lshiftrt:DI
11713 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11715 (match_operand:DI 2 "gpc_reg_operand" "r")))
11716 (clobber (match_scratch:DI 3 "=&r"))]
11718 "addic %3,%1,-1\;addze %0,%2"
11719 [(set_attr "type" "two")
11720 (set_attr "length" "8")])
11723 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11725 (plus:SI (lshiftrt:SI
11726 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11728 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11730 (clobber (match_scratch:SI 3 "=&r,&r"))
11731 (clobber (match_scratch:SI 4 "=X,&r"))]
11734 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11736 [(set_attr "type" "compare")
11737 (set_attr "length" "8,12")])
11740 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11742 (plus:SI (lshiftrt:SI
11743 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11745 (match_operand:SI 2 "gpc_reg_operand" ""))
11747 (clobber (match_scratch:SI 3 ""))
11748 (clobber (match_scratch:SI 4 ""))]
11749 "TARGET_32BIT && reload_completed"
11750 [(parallel [(set (match_dup 3)
11751 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11754 (clobber (match_dup 4))])
11756 (compare:CC (match_dup 3)
11761 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11763 (plus:DI (lshiftrt:DI
11764 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11766 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11768 (clobber (match_scratch:DI 3 "=&r,&r"))]
11771 addic %3,%1,-1\;addze. %3,%2
11773 [(set_attr "type" "compare")
11774 (set_attr "length" "8,12")])
11777 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11779 (plus:DI (lshiftrt:DI
11780 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11782 (match_operand:DI 2 "gpc_reg_operand" ""))
11784 (clobber (match_scratch:DI 3 ""))]
11785 "TARGET_64BIT && reload_completed"
11786 [(set (match_dup 3)
11787 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11791 (compare:CC (match_dup 3)
11796 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11798 (plus:SI (lshiftrt:SI
11799 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11801 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11803 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11804 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11806 (clobber (match_scratch:SI 3 "=&r,&r"))]
11809 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11811 [(set_attr "type" "compare")
11812 (set_attr "length" "8,12")])
11815 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11817 (plus:SI (lshiftrt:SI
11818 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11820 (match_operand:SI 2 "gpc_reg_operand" ""))
11822 (set (match_operand:SI 0 "gpc_reg_operand" "")
11823 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11825 (clobber (match_scratch:SI 3 ""))]
11826 "TARGET_32BIT && reload_completed"
11827 [(parallel [(set (match_dup 0)
11828 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11830 (clobber (match_dup 3))])
11832 (compare:CC (match_dup 0)
11837 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11839 (plus:DI (lshiftrt:DI
11840 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11842 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11844 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11845 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11847 (clobber (match_scratch:DI 3 "=&r,&r"))]
11850 addic %3,%1,-1\;addze. %0,%2
11852 [(set_attr "type" "compare")
11853 (set_attr "length" "8,12")])
11856 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11858 (plus:DI (lshiftrt:DI
11859 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11861 (match_operand:DI 2 "gpc_reg_operand" ""))
11863 (set (match_operand:DI 0 "gpc_reg_operand" "")
11864 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11866 (clobber (match_scratch:DI 3 ""))]
11867 "TARGET_64BIT && reload_completed"
11868 [(parallel [(set (match_dup 0)
11869 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11871 (clobber (match_dup 3))])
11873 (compare:CC (match_dup 0)
11878 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11879 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11880 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11881 (clobber (match_scratch:SI 3 "=r,X"))]
11884 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11885 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11886 [(set_attr "length" "12")])
11889 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11891 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11892 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11894 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11895 (le:SI (match_dup 1) (match_dup 2)))
11896 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11899 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11900 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11903 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11904 (set_attr "length" "12,12,16,16")])
11907 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11909 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11910 (match_operand:SI 2 "reg_or_short_operand" ""))
11912 (set (match_operand:SI 0 "gpc_reg_operand" "")
11913 (le:SI (match_dup 1) (match_dup 2)))
11914 (clobber (match_scratch:SI 3 ""))]
11915 "TARGET_POWER && reload_completed"
11916 [(parallel [(set (match_dup 0)
11917 (le:SI (match_dup 1) (match_dup 2)))
11918 (clobber (match_dup 3))])
11920 (compare:CC (match_dup 0)
11925 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11926 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11927 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
11928 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
11931 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11932 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
11933 [(set_attr "length" "12")])
11936 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11938 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11939 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11940 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11942 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11945 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11946 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11949 [(set_attr "type" "compare")
11950 (set_attr "length" "12,12,16,16")])
11953 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11955 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11956 (match_operand:SI 2 "reg_or_short_operand" ""))
11957 (match_operand:SI 3 "gpc_reg_operand" ""))
11959 (clobber (match_scratch:SI 4 ""))]
11960 "TARGET_POWER && reload_completed"
11961 [(set (match_dup 4)
11962 (plus:SI (le:SI (match_dup 1) (match_dup 2))
11965 (compare:CC (match_dup 4)
11970 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11972 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11973 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11974 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11976 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
11977 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11980 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11981 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
11984 [(set_attr "type" "compare")
11985 (set_attr "length" "12,12,16,16")])
11988 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11990 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11991 (match_operand:SI 2 "reg_or_short_operand" ""))
11992 (match_operand:SI 3 "gpc_reg_operand" ""))
11994 (set (match_operand:SI 0 "gpc_reg_operand" "")
11995 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11996 "TARGET_POWER && reload_completed"
11997 [(set (match_dup 0)
11998 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12000 (compare:CC (match_dup 0)
12005 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12006 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12007 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12010 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12011 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12012 [(set_attr "length" "12")])
12015 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12016 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12017 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12019 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12020 [(set_attr "type" "three")
12021 (set_attr "length" "12")])
12024 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12025 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12026 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
12028 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12029 [(set_attr "type" "three")
12030 (set_attr "length" "12")])
12033 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12035 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12036 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12038 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12039 (leu:DI (match_dup 1) (match_dup 2)))]
12042 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12044 [(set_attr "type" "compare")
12045 (set_attr "length" "12,16")])
12048 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12050 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12051 (match_operand:DI 2 "reg_or_short_operand" ""))
12053 (set (match_operand:DI 0 "gpc_reg_operand" "")
12054 (leu:DI (match_dup 1) (match_dup 2)))]
12055 "TARGET_64BIT && reload_completed"
12056 [(set (match_dup 0)
12057 (leu:DI (match_dup 1) (match_dup 2)))
12059 (compare:CC (match_dup 0)
12064 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12066 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12067 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12069 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12070 (leu:SI (match_dup 1) (match_dup 2)))]
12073 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12075 [(set_attr "type" "compare")
12076 (set_attr "length" "12,16")])
12079 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12081 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12082 (match_operand:SI 2 "reg_or_short_operand" ""))
12084 (set (match_operand:SI 0 "gpc_reg_operand" "")
12085 (leu:SI (match_dup 1) (match_dup 2)))]
12086 "TARGET_32BIT && reload_completed"
12087 [(set (match_dup 0)
12088 (leu:SI (match_dup 1) (match_dup 2)))
12090 (compare:CC (match_dup 0)
12095 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12096 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12097 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12098 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12100 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12101 [(set_attr "type" "two")
12102 (set_attr "length" "8")])
12105 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12107 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12108 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12109 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12111 (clobber (match_scratch:SI 4 "=&r,&r"))]
12114 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12116 [(set_attr "type" "compare")
12117 (set_attr "length" "8,12")])
12120 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12122 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12123 (match_operand:SI 2 "reg_or_short_operand" ""))
12124 (match_operand:SI 3 "gpc_reg_operand" ""))
12126 (clobber (match_scratch:SI 4 ""))]
12127 "TARGET_32BIT && reload_completed"
12128 [(set (match_dup 4)
12129 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12132 (compare:CC (match_dup 4)
12137 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12139 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12140 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12141 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12143 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12144 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12147 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12149 [(set_attr "type" "compare")
12150 (set_attr "length" "8,12")])
12153 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12155 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12156 (match_operand:SI 2 "reg_or_short_operand" ""))
12157 (match_operand:SI 3 "gpc_reg_operand" ""))
12159 (set (match_operand:SI 0 "gpc_reg_operand" "")
12160 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12161 "TARGET_32BIT && reload_completed"
12162 [(set (match_dup 0)
12163 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12165 (compare:CC (match_dup 0)
12170 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12171 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12172 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12174 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12175 [(set_attr "type" "three")
12176 (set_attr "length" "12")])
12179 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12181 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12182 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12183 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12185 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12186 [(set_attr "type" "three")
12187 (set_attr "length" "12")])
12190 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12193 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12194 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12195 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12197 (clobber (match_scratch:SI 4 "=&r,&r"))]
12200 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12202 [(set_attr "type" "compare")
12203 (set_attr "length" "12,16")])
12206 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12209 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12210 (match_operand:SI 2 "reg_or_short_operand" "")))
12211 (match_operand:SI 3 "gpc_reg_operand" ""))
12213 (clobber (match_scratch:SI 4 ""))]
12214 "TARGET_32BIT && reload_completed"
12215 [(set (match_dup 4)
12216 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12219 (compare:CC (match_dup 4)
12224 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12227 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12228 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12229 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12231 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12232 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12235 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12237 [(set_attr "type" "compare")
12238 (set_attr "length" "12,16")])
12241 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12244 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12245 (match_operand:SI 2 "reg_or_short_operand" "")))
12246 (match_operand:SI 3 "gpc_reg_operand" ""))
12248 (set (match_operand:SI 0 "gpc_reg_operand" "")
12249 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12250 "TARGET_32BIT && reload_completed"
12251 [(set (match_dup 0)
12252 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12255 (compare:CC (match_dup 0)
12260 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12261 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12262 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12264 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12265 [(set_attr "length" "12")])
12268 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12270 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12271 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12273 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12274 (lt:SI (match_dup 1) (match_dup 2)))]
12277 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12279 [(set_attr "type" "delayed_compare")
12280 (set_attr "length" "12,16")])
12283 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12285 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12286 (match_operand:SI 2 "reg_or_short_operand" ""))
12288 (set (match_operand:SI 0 "gpc_reg_operand" "")
12289 (lt:SI (match_dup 1) (match_dup 2)))]
12290 "TARGET_POWER && reload_completed"
12291 [(set (match_dup 0)
12292 (lt:SI (match_dup 1) (match_dup 2)))
12294 (compare:CC (match_dup 0)
12299 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12300 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12301 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12302 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12304 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12305 [(set_attr "length" "12")])
12308 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12310 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12311 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12312 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12314 (clobber (match_scratch:SI 4 "=&r,&r"))]
12317 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12319 [(set_attr "type" "compare")
12320 (set_attr "length" "12,16")])
12323 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12325 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12326 (match_operand:SI 2 "reg_or_short_operand" ""))
12327 (match_operand:SI 3 "gpc_reg_operand" ""))
12329 (clobber (match_scratch:SI 4 ""))]
12330 "TARGET_POWER && reload_completed"
12331 [(set (match_dup 4)
12332 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12335 (compare:CC (match_dup 4)
12340 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12342 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12343 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12344 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12346 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12347 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12350 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12352 [(set_attr "type" "compare")
12353 (set_attr "length" "12,16")])
12356 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12358 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12359 (match_operand:SI 2 "reg_or_short_operand" ""))
12360 (match_operand:SI 3 "gpc_reg_operand" ""))
12362 (set (match_operand:SI 0 "gpc_reg_operand" "")
12363 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12364 "TARGET_POWER && reload_completed"
12365 [(set (match_dup 0)
12366 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12368 (compare:CC (match_dup 0)
12373 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12374 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12375 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12377 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12378 [(set_attr "length" "12")])
12380 (define_insn_and_split ""
12381 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12382 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12383 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12387 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12388 (set (match_dup 0) (neg:SI (match_dup 0)))]
12391 (define_insn_and_split ""
12392 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12393 (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12394 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12398 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12399 (set (match_dup 0) (neg:DI (match_dup 0)))]
12403 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12405 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12406 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12408 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12409 (ltu:SI (match_dup 1) (match_dup 2)))]
12412 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12413 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12416 [(set_attr "type" "compare")
12417 (set_attr "length" "12,12,16,16")])
12420 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12422 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12423 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12425 (set (match_operand:SI 0 "gpc_reg_operand" "")
12426 (ltu:SI (match_dup 1) (match_dup 2)))]
12427 "TARGET_32BIT && reload_completed"
12428 [(set (match_dup 0)
12429 (ltu:SI (match_dup 1) (match_dup 2)))
12431 (compare:CC (match_dup 0)
12435 (define_insn_and_split ""
12436 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
12437 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12438 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12439 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12442 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12443 [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
12444 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
12447 (define_insn_and_split ""
12448 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
12449 (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12450 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
12451 (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))]
12454 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12455 [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
12456 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
12460 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12462 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12463 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12464 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12466 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12469 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12470 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
12473 [(set_attr "type" "compare")
12474 (set_attr "length" "12,12,16,16")])
12477 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12479 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12480 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12481 (match_operand:SI 3 "gpc_reg_operand" ""))
12483 (clobber (match_scratch:SI 4 ""))]
12484 "TARGET_32BIT && reload_completed"
12485 [(set (match_dup 4)
12486 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12489 (compare:CC (match_dup 4)
12494 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12496 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12497 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12498 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12500 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12501 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12504 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12505 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
12508 [(set_attr "type" "compare")
12509 (set_attr "length" "12,12,16,16")])
12512 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12514 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12515 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12516 (match_operand:SI 3 "gpc_reg_operand" ""))
12518 (set (match_operand:SI 0 "gpc_reg_operand" "")
12519 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12520 "TARGET_32BIT && reload_completed"
12521 [(set (match_dup 0)
12522 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12524 (compare:CC (match_dup 0)
12529 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12530 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12531 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12534 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12535 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12536 [(set_attr "type" "two")
12537 (set_attr "length" "8")])
12540 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12541 (neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12542 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))]
12545 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12546 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12547 [(set_attr "type" "two")
12548 (set_attr "length" "8")])
12551 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12552 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12553 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12554 (clobber (match_scratch:SI 3 "=r"))]
12556 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12557 [(set_attr "length" "12")])
12560 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12562 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12563 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12565 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12566 (ge:SI (match_dup 1) (match_dup 2)))
12567 (clobber (match_scratch:SI 3 "=r,r"))]
12570 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12572 [(set_attr "type" "compare")
12573 (set_attr "length" "12,16")])
12576 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12578 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12579 (match_operand:SI 2 "reg_or_short_operand" ""))
12581 (set (match_operand:SI 0 "gpc_reg_operand" "")
12582 (ge:SI (match_dup 1) (match_dup 2)))
12583 (clobber (match_scratch:SI 3 ""))]
12584 "TARGET_POWER && reload_completed"
12585 [(parallel [(set (match_dup 0)
12586 (ge:SI (match_dup 1) (match_dup 2)))
12587 (clobber (match_dup 3))])
12589 (compare:CC (match_dup 0)
12594 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12595 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12596 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12597 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12599 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12600 [(set_attr "length" "12")])
12603 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12605 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12606 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12607 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12609 (clobber (match_scratch:SI 4 "=&r,&r"))]
12612 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12614 [(set_attr "type" "compare")
12615 (set_attr "length" "12,16")])
12618 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12620 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12621 (match_operand:SI 2 "reg_or_short_operand" ""))
12622 (match_operand:SI 3 "gpc_reg_operand" ""))
12624 (clobber (match_scratch:SI 4 ""))]
12625 "TARGET_POWER && reload_completed"
12626 [(set (match_dup 4)
12627 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12630 (compare:CC (match_dup 4)
12635 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12637 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12638 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12639 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12641 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12642 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12645 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12647 [(set_attr "type" "compare")
12648 (set_attr "length" "12,16")])
12651 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12653 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12654 (match_operand:SI 2 "reg_or_short_operand" ""))
12655 (match_operand:SI 3 "gpc_reg_operand" ""))
12657 (set (match_operand:SI 0 "gpc_reg_operand" "")
12658 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12659 "TARGET_POWER && reload_completed"
12660 [(set (match_dup 0)
12661 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12663 (compare:CC (match_dup 0)
12668 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12669 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12670 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12672 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12673 [(set_attr "length" "12")])
12676 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12677 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12678 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12681 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12682 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12683 [(set_attr "type" "three")
12684 (set_attr "length" "12")])
12687 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12688 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12689 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12692 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12693 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12694 [(set_attr "type" "three")
12695 (set_attr "length" "12")])
12698 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12700 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12701 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12703 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12704 (geu:SI (match_dup 1) (match_dup 2)))]
12707 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12708 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12711 [(set_attr "type" "compare")
12712 (set_attr "length" "12,12,16,16")])
12715 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12717 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12718 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12720 (set (match_operand:SI 0 "gpc_reg_operand" "")
12721 (geu:SI (match_dup 1) (match_dup 2)))]
12722 "TARGET_32BIT && reload_completed"
12723 [(set (match_dup 0)
12724 (geu:SI (match_dup 1) (match_dup 2)))
12726 (compare:CC (match_dup 0)
12731 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12733 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12734 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12736 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12737 (geu:DI (match_dup 1) (match_dup 2)))]
12740 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12741 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12744 [(set_attr "type" "compare")
12745 (set_attr "length" "12,12,16,16")])
12748 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12750 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12751 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12753 (set (match_operand:DI 0 "gpc_reg_operand" "")
12754 (geu:DI (match_dup 1) (match_dup 2)))]
12755 "TARGET_64BIT && reload_completed"
12756 [(set (match_dup 0)
12757 (geu:DI (match_dup 1) (match_dup 2)))
12759 (compare:CC (match_dup 0)
12764 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12765 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12766 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12767 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12770 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12771 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12772 [(set_attr "type" "two")
12773 (set_attr "length" "8")])
12776 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12778 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12779 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12780 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12782 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12785 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12786 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12789 [(set_attr "type" "compare")
12790 (set_attr "length" "8,8,12,12")])
12793 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12795 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12796 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12797 (match_operand:SI 3 "gpc_reg_operand" ""))
12799 (clobber (match_scratch:SI 4 ""))]
12800 "TARGET_32BIT && reload_completed"
12801 [(set (match_dup 4)
12802 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12805 (compare:CC (match_dup 4)
12810 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12812 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12813 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12814 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12816 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12817 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12820 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12821 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12824 [(set_attr "type" "compare")
12825 (set_attr "length" "8,8,12,12")])
12828 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12830 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12831 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12832 (match_operand:SI 3 "gpc_reg_operand" ""))
12834 (set (match_operand:SI 0 "gpc_reg_operand" "")
12835 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12836 "TARGET_32BIT && reload_completed"
12837 [(set (match_dup 0)
12838 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12840 (compare:CC (match_dup 0)
12845 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12846 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12847 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
12850 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12851 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12852 [(set_attr "type" "three")
12853 (set_attr "length" "12")])
12856 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12858 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12859 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
12860 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12863 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12864 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12865 [(set_attr "type" "three")
12866 (set_attr "length" "12")])
12869 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12872 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12873 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12874 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12876 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12879 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12880 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12883 [(set_attr "type" "compare")
12884 (set_attr "length" "12,12,16,16")])
12887 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12890 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12891 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12892 (match_operand:SI 3 "gpc_reg_operand" ""))
12894 (clobber (match_scratch:SI 4 ""))]
12895 "TARGET_32BIT && reload_completed"
12896 [(set (match_dup 4)
12897 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12900 (compare:CC (match_dup 4)
12905 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12908 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12909 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12910 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12912 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12913 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12916 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12917 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12920 [(set_attr "type" "compare")
12921 (set_attr "length" "12,12,16,16")])
12924 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12927 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12928 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12929 (match_operand:SI 3 "gpc_reg_operand" ""))
12931 (set (match_operand:SI 0 "gpc_reg_operand" "")
12932 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12933 "TARGET_32BIT && reload_completed"
12934 [(set (match_dup 0)
12935 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12937 (compare:CC (match_dup 0)
12942 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12943 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12946 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
12947 [(set_attr "type" "three")
12948 (set_attr "length" "12")])
12951 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12952 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12955 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
12956 [(set_attr "type" "three")
12957 (set_attr "length" "12")])
12960 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12962 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12965 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12966 (gt:SI (match_dup 1) (const_int 0)))]
12969 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
12971 [(set_attr "type" "delayed_compare")
12972 (set_attr "length" "12,16")])
12975 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12977 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12980 (set (match_operand:SI 0 "gpc_reg_operand" "")
12981 (gt:SI (match_dup 1) (const_int 0)))]
12982 "TARGET_32BIT && reload_completed"
12983 [(set (match_dup 0)
12984 (gt:SI (match_dup 1) (const_int 0)))
12986 (compare:CC (match_dup 0)
12991 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12993 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12996 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12997 (gt:DI (match_dup 1) (const_int 0)))]
13000 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
13002 [(set_attr "type" "delayed_compare")
13003 (set_attr "length" "12,16")])
13006 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13008 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13011 (set (match_operand:DI 0 "gpc_reg_operand" "")
13012 (gt:DI (match_dup 1) (const_int 0)))]
13013 "TARGET_64BIT && reload_completed"
13014 [(set (match_dup 0)
13015 (gt:DI (match_dup 1) (const_int 0)))
13017 (compare:CC (match_dup 0)
13022 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13023 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13024 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13026 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13027 [(set_attr "length" "12")])
13030 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13032 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13033 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13035 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13036 (gt:SI (match_dup 1) (match_dup 2)))]
13039 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13041 [(set_attr "type" "delayed_compare")
13042 (set_attr "length" "12,16")])
13045 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13047 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13048 (match_operand:SI 2 "reg_or_short_operand" ""))
13050 (set (match_operand:SI 0 "gpc_reg_operand" "")
13051 (gt:SI (match_dup 1) (match_dup 2)))]
13052 "TARGET_POWER && reload_completed"
13053 [(set (match_dup 0)
13054 (gt:SI (match_dup 1) (match_dup 2)))
13056 (compare:CC (match_dup 0)
13061 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13062 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13064 (match_operand:SI 2 "gpc_reg_operand" "r")))]
13066 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13067 [(set_attr "type" "three")
13068 (set_attr "length" "12")])
13071 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13072 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13074 (match_operand:DI 2 "gpc_reg_operand" "r")))]
13076 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13077 [(set_attr "type" "three")
13078 (set_attr "length" "12")])
13081 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13083 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13085 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13087 (clobber (match_scratch:SI 3 "=&r,&r"))]
13090 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13092 [(set_attr "type" "compare")
13093 (set_attr "length" "12,16")])
13096 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13098 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13100 (match_operand:SI 2 "gpc_reg_operand" ""))
13102 (clobber (match_scratch:SI 3 ""))]
13103 "TARGET_32BIT && reload_completed"
13104 [(set (match_dup 3)
13105 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13108 (compare:CC (match_dup 3)
13113 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13115 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13117 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13119 (clobber (match_scratch:DI 3 "=&r,&r"))]
13122 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13124 [(set_attr "type" "compare")
13125 (set_attr "length" "12,16")])
13128 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13130 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13132 (match_operand:DI 2 "gpc_reg_operand" ""))
13134 (clobber (match_scratch:DI 3 ""))]
13135 "TARGET_64BIT && reload_completed"
13136 [(set (match_dup 3)
13137 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13140 (compare:CC (match_dup 3)
13145 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13147 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13149 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13151 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13152 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13155 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13157 [(set_attr "type" "compare")
13158 (set_attr "length" "12,16")])
13161 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13163 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13165 (match_operand:SI 2 "gpc_reg_operand" ""))
13167 (set (match_operand:SI 0 "gpc_reg_operand" "")
13168 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13169 "TARGET_32BIT && reload_completed"
13170 [(set (match_dup 0)
13171 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13173 (compare:CC (match_dup 0)
13178 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13180 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13182 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13184 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13185 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13188 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13190 [(set_attr "type" "compare")
13191 (set_attr "length" "12,16")])
13194 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13196 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13198 (match_operand:DI 2 "gpc_reg_operand" ""))
13200 (set (match_operand:DI 0 "gpc_reg_operand" "")
13201 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13202 "TARGET_64BIT && reload_completed"
13203 [(set (match_dup 0)
13204 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13206 (compare:CC (match_dup 0)
13211 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13212 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13213 (match_operand:SI 2 "reg_or_short_operand" "r"))
13214 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13216 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13217 [(set_attr "length" "12")])
13220 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13222 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13223 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13224 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13226 (clobber (match_scratch:SI 4 "=&r,&r"))]
13229 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13231 [(set_attr "type" "compare")
13232 (set_attr "length" "12,16")])
13235 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13237 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13238 (match_operand:SI 2 "reg_or_short_operand" ""))
13239 (match_operand:SI 3 "gpc_reg_operand" ""))
13241 (clobber (match_scratch:SI 4 ""))]
13242 "TARGET_POWER && reload_completed"
13243 [(set (match_dup 4)
13244 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13246 (compare:CC (match_dup 4)
13251 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13253 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13254 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13255 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13257 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13258 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13261 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13263 [(set_attr "type" "compare")
13264 (set_attr "length" "12,16")])
13267 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13269 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13270 (match_operand:SI 2 "reg_or_short_operand" ""))
13271 (match_operand:SI 3 "gpc_reg_operand" ""))
13273 (set (match_operand:SI 0 "gpc_reg_operand" "")
13274 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13275 "TARGET_POWER && reload_completed"
13276 [(set (match_dup 0)
13277 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13279 (compare:CC (match_dup 0)
13284 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13285 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13288 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13289 [(set_attr "type" "three")
13290 (set_attr "length" "12")])
13293 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13294 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13297 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13298 [(set_attr "type" "three")
13299 (set_attr "length" "12")])
13302 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13303 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13304 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13306 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13307 [(set_attr "length" "12")])
13309 (define_insn_and_split ""
13310 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13311 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13312 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13316 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13317 (set (match_dup 0) (neg:SI (match_dup 0)))]
13320 (define_insn_and_split ""
13321 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13322 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13323 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13327 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13328 (set (match_dup 0) (neg:DI (match_dup 0)))]
13332 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13334 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13335 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13337 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13338 (gtu:SI (match_dup 1) (match_dup 2)))]
13341 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13343 [(set_attr "type" "compare")
13344 (set_attr "length" "12,16")])
13347 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13349 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13350 (match_operand:SI 2 "reg_or_short_operand" ""))
13352 (set (match_operand:SI 0 "gpc_reg_operand" "")
13353 (gtu:SI (match_dup 1) (match_dup 2)))]
13354 "TARGET_32BIT && reload_completed"
13355 [(set (match_dup 0)
13356 (gtu:SI (match_dup 1) (match_dup 2)))
13358 (compare:CC (match_dup 0)
13363 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13365 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13366 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13368 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13369 (gtu:DI (match_dup 1) (match_dup 2)))]
13372 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13374 [(set_attr "type" "compare")
13375 (set_attr "length" "12,16")])
13378 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13380 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13381 (match_operand:DI 2 "reg_or_short_operand" ""))
13383 (set (match_operand:DI 0 "gpc_reg_operand" "")
13384 (gtu:DI (match_dup 1) (match_dup 2)))]
13385 "TARGET_64BIT && reload_completed"
13386 [(set (match_dup 0)
13387 (gtu:DI (match_dup 1) (match_dup 2)))
13389 (compare:CC (match_dup 0)
13393 (define_insn_and_split ""
13394 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13395 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13396 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13397 (match_operand:SI 3 "reg_or_short_operand" "rI")))]
13400 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13401 [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
13402 (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
13405 (define_insn_and_split ""
13406 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13407 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13408 (match_operand:DI 2 "reg_or_short_operand" "rI"))
13409 (match_operand:DI 3 "reg_or_short_operand" "rI")))]
13412 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13413 [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
13414 (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
13418 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13420 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13421 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13422 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13424 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13427 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13428 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
13431 [(set_attr "type" "compare")
13432 (set_attr "length" "8,12,12,16")])
13435 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13437 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13438 (match_operand:SI 2 "reg_or_short_operand" ""))
13439 (match_operand:SI 3 "gpc_reg_operand" ""))
13441 (clobber (match_scratch:SI 4 ""))]
13442 "TARGET_32BIT && reload_completed"
13443 [(set (match_dup 4)
13444 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13447 (compare:CC (match_dup 4)
13452 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13454 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13455 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13456 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13458 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13461 addic %4,%1,%k2\;addze. %4,%3
13462 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3
13465 [(set_attr "type" "compare")
13466 (set_attr "length" "8,12,12,16")])
13469 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13471 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13472 (match_operand:DI 2 "reg_or_short_operand" ""))
13473 (match_operand:DI 3 "gpc_reg_operand" ""))
13475 (clobber (match_scratch:DI 4 ""))]
13476 "TARGET_64BIT && reload_completed"
13477 [(set (match_dup 4)
13478 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13481 (compare:CC (match_dup 4)
13486 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13488 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13489 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13490 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13492 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13493 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13496 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13497 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
13500 [(set_attr "type" "compare")
13501 (set_attr "length" "8,12,12,16")])
13504 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13506 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13507 (match_operand:SI 2 "reg_or_short_operand" ""))
13508 (match_operand:SI 3 "gpc_reg_operand" ""))
13510 (set (match_operand:SI 0 "gpc_reg_operand" "")
13511 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13512 "TARGET_32BIT && reload_completed"
13513 [(set (match_dup 0)
13514 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13516 (compare:CC (match_dup 0)
13521 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13523 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13524 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13525 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13527 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13528 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13531 addic %0,%1,%k2\;addze. %0,%3
13532 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3
13535 [(set_attr "type" "compare")
13536 (set_attr "length" "8,12,12,16")])
13539 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13541 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13542 (match_operand:DI 2 "reg_or_short_operand" ""))
13543 (match_operand:DI 3 "gpc_reg_operand" ""))
13545 (set (match_operand:DI 0 "gpc_reg_operand" "")
13546 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13547 "TARGET_64BIT && reload_completed"
13548 [(set (match_dup 0)
13549 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13551 (compare:CC (match_dup 0)
13556 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13557 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13558 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13560 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13561 [(set_attr "type" "two")
13562 (set_attr "length" "8")])
13565 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13566 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13567 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13569 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13570 [(set_attr "type" "two")
13571 (set_attr "length" "8")])
13573 ;; Define both directions of branch and return. If we need a reload
13574 ;; register, we'd rather use CR0 since it is much easier to copy a
13575 ;; register CC value to there.
13579 (if_then_else (match_operator 1 "branch_comparison_operator"
13581 "cc_reg_operand" "y")
13583 (label_ref (match_operand 0 "" ""))
13588 return output_cbranch (operands[1], \"%l0\", 0, insn);
13590 [(set_attr "type" "branch")])
13594 (if_then_else (match_operator 0 "branch_comparison_operator"
13596 "cc_reg_operand" "y")
13603 return output_cbranch (operands[0], NULL, 0, insn);
13605 [(set_attr "type" "branch")
13606 (set_attr "length" "4")])
13610 (if_then_else (match_operator 1 "branch_comparison_operator"
13612 "cc_reg_operand" "y")
13615 (label_ref (match_operand 0 "" ""))))]
13619 return output_cbranch (operands[1], \"%l0\", 1, insn);
13621 [(set_attr "type" "branch")])
13625 (if_then_else (match_operator 0 "branch_comparison_operator"
13627 "cc_reg_operand" "y")
13634 return output_cbranch (operands[0], NULL, 1, insn);
13636 [(set_attr "type" "branch")
13637 (set_attr "length" "4")])
13639 ;; Logic on condition register values.
13641 ; This pattern matches things like
13642 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13643 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13645 ; which are generated by the branch logic.
13646 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13648 (define_insn "*cceq_ior_compare"
13649 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13650 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13651 [(match_operator:SI 2
13652 "branch_positive_comparison_operator"
13654 "cc_reg_operand" "y,y")
13656 (match_operator:SI 4
13657 "branch_positive_comparison_operator"
13659 "cc_reg_operand" "0,y")
13663 "cr%q1 %E0,%j2,%j4"
13664 [(set_attr "type" "cr_logical,delayed_cr")])
13666 ; Why is the constant -1 here, but 1 in the previous pattern?
13667 ; Because ~1 has all but the low bit set.
13669 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13670 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13671 [(not:SI (match_operator:SI 2
13672 "branch_positive_comparison_operator"
13674 "cc_reg_operand" "y,y")
13676 (match_operator:SI 4
13677 "branch_positive_comparison_operator"
13679 "cc_reg_operand" "0,y")
13683 "cr%q1 %E0,%j2,%j4"
13684 [(set_attr "type" "cr_logical,delayed_cr")])
13686 (define_insn "*cceq_rev_compare"
13687 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13688 (compare:CCEQ (match_operator:SI 1
13689 "branch_positive_comparison_operator"
13691 "cc_reg_operand" "0,y")
13695 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13696 [(set_attr "type" "cr_logical,delayed_cr")])
13698 ;; If we are comparing the result of two comparisons, this can be done
13699 ;; using creqv or crxor.
13701 (define_insn_and_split ""
13702 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13703 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13704 [(match_operand 2 "cc_reg_operand" "y")
13706 (match_operator 3 "branch_comparison_operator"
13707 [(match_operand 4 "cc_reg_operand" "y")
13712 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13716 int positive_1, positive_2;
13718 positive_1 = branch_positive_comparison_operator (operands[1],
13719 GET_MODE (operands[1]));
13720 positive_2 = branch_positive_comparison_operator (operands[3],
13721 GET_MODE (operands[3]));
13724 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13725 GET_CODE (operands[1])),
13727 operands[2], const0_rtx);
13728 else if (GET_MODE (operands[1]) != SImode)
13729 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13730 operands[2], const0_rtx);
13733 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13734 GET_CODE (operands[3])),
13736 operands[4], const0_rtx);
13737 else if (GET_MODE (operands[3]) != SImode)
13738 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13739 operands[4], const0_rtx);
13741 if (positive_1 == positive_2)
13743 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13744 operands[5] = constm1_rtx;
13748 operands[5] = const1_rtx;
13752 ;; Unconditional branch and return.
13754 (define_insn "jump"
13756 (label_ref (match_operand 0 "" "")))]
13759 [(set_attr "type" "branch")])
13761 (define_insn "return"
13765 [(set_attr "type" "jmpreg")])
13767 (define_expand "indirect_jump"
13768 [(set (pc) (match_operand 0 "register_operand" ""))]
13773 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
13775 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
13779 (define_insn "indirect_jumpsi"
13780 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
13785 [(set_attr "type" "jmpreg")])
13787 (define_insn "indirect_jumpdi"
13788 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
13793 [(set_attr "type" "jmpreg")])
13795 ;; Table jump for switch statements:
13796 (define_expand "tablejump"
13797 [(use (match_operand 0 "" ""))
13798 (use (label_ref (match_operand 1 "" "")))]
13803 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13805 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13809 (define_expand "tablejumpsi"
13810 [(set (match_dup 3)
13811 (plus:SI (match_operand:SI 0 "" "")
13813 (parallel [(set (pc) (match_dup 3))
13814 (use (label_ref (match_operand 1 "" "")))])]
13817 { operands[0] = force_reg (SImode, operands[0]);
13818 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13819 operands[3] = gen_reg_rtx (SImode);
13822 (define_expand "tablejumpdi"
13823 [(set (match_dup 4)
13824 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13826 (plus:DI (match_dup 4)
13828 (parallel [(set (pc) (match_dup 3))
13829 (use (label_ref (match_operand 1 "" "")))])]
13832 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13833 operands[3] = gen_reg_rtx (DImode);
13834 operands[4] = gen_reg_rtx (DImode);
13839 (match_operand:SI 0 "register_operand" "c,*l"))
13840 (use (label_ref (match_operand 1 "" "")))]
13845 [(set_attr "type" "jmpreg")])
13849 (match_operand:DI 0 "register_operand" "c,*l"))
13850 (use (label_ref (match_operand 1 "" "")))]
13855 [(set_attr "type" "jmpreg")])
13860 "{cror 0,0,0|nop}")
13862 ;; Define the subtract-one-and-jump insns, starting with the template
13863 ;; so loop.c knows what to generate.
13865 (define_expand "doloop_end"
13866 [(use (match_operand 0 "" "")) ; loop pseudo
13867 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13868 (use (match_operand 2 "" "")) ; max iterations
13869 (use (match_operand 3 "" "")) ; loop level
13870 (use (match_operand 4 "" ""))] ; label
13874 /* Only use this on innermost loops. */
13875 if (INTVAL (operands[3]) > 1)
13879 if (GET_MODE (operands[0]) != DImode)
13881 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13885 if (GET_MODE (operands[0]) != SImode)
13887 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13892 (define_expand "ctrsi"
13893 [(parallel [(set (pc)
13894 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
13896 (label_ref (match_operand 1 "" ""))
13899 (plus:SI (match_dup 0)
13901 (clobber (match_scratch:CC 2 ""))
13902 (clobber (match_scratch:SI 3 ""))])]
13906 (define_expand "ctrdi"
13907 [(parallel [(set (pc)
13908 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
13910 (label_ref (match_operand 1 "" ""))
13913 (plus:DI (match_dup 0)
13915 (clobber (match_scratch:CC 2 ""))
13916 (clobber (match_scratch:DI 3 ""))])]
13920 ;; We need to be able to do this for any operand, including MEM, or we
13921 ;; will cause reload to blow up since we don't allow output reloads on
13923 ;; For the length attribute to be calculated correctly, the
13924 ;; label MUST be operand 0.
13926 (define_insn "*ctrsi_internal1"
13928 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
13930 (label_ref (match_operand 0 "" ""))
13932 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13933 (plus:SI (match_dup 1)
13935 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13936 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
13940 if (which_alternative != 0)
13942 else if (get_attr_length (insn) == 4)
13943 return \"{bdn|bdnz} %l0\";
13945 return \"bdz $+8\;b %l0\";
13947 [(set_attr "type" "branch")
13948 (set_attr "length" "*,12,16,16")])
13950 (define_insn "*ctrsi_internal2"
13952 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
13955 (label_ref (match_operand 0 "" ""))))
13956 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13957 (plus:SI (match_dup 1)
13959 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13960 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
13964 if (which_alternative != 0)
13966 else if (get_attr_length (insn) == 4)
13967 return \"bdz %l0\";
13969 return \"{bdn|bdnz} $+8\;b %l0\";
13971 [(set_attr "type" "branch")
13972 (set_attr "length" "*,12,16,16")])
13974 (define_insn "*ctrdi_internal1"
13976 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
13978 (label_ref (match_operand 0 "" ""))
13980 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13981 (plus:DI (match_dup 1)
13983 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13984 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
13988 if (which_alternative != 0)
13990 else if (get_attr_length (insn) == 4)
13991 return \"{bdn|bdnz} %l0\";
13993 return \"bdz $+8\;b %l0\";
13995 [(set_attr "type" "branch")
13996 (set_attr "length" "*,12,16,16")])
13998 (define_insn "*ctrdi_internal2"
14000 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14003 (label_ref (match_operand 0 "" ""))))
14004 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14005 (plus:DI (match_dup 1)
14007 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14008 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14012 if (which_alternative != 0)
14014 else if (get_attr_length (insn) == 4)
14015 return \"bdz %l0\";
14017 return \"{bdn|bdnz} $+8\;b %l0\";
14019 [(set_attr "type" "branch")
14020 (set_attr "length" "*,12,16,16")])
14022 ;; Similar but use EQ
14024 (define_insn "*ctrsi_internal5"
14026 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14028 (label_ref (match_operand 0 "" ""))
14030 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14031 (plus:SI (match_dup 1)
14033 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14034 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14038 if (which_alternative != 0)
14040 else if (get_attr_length (insn) == 4)
14041 return \"bdz %l0\";
14043 return \"{bdn|bdnz} $+8\;b %l0\";
14045 [(set_attr "type" "branch")
14046 (set_attr "length" "*,12,16,16")])
14048 (define_insn "*ctrsi_internal6"
14050 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14053 (label_ref (match_operand 0 "" ""))))
14054 (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14055 (plus:SI (match_dup 1)
14057 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14058 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14062 if (which_alternative != 0)
14064 else if (get_attr_length (insn) == 4)
14065 return \"{bdn|bdnz} %l0\";
14067 return \"bdz $+8\;b %l0\";
14069 [(set_attr "type" "branch")
14070 (set_attr "length" "*,12,16,16")])
14072 (define_insn "*ctrdi_internal5"
14074 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14076 (label_ref (match_operand 0 "" ""))
14078 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14079 (plus:DI (match_dup 1)
14081 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14082 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14086 if (which_alternative != 0)
14088 else if (get_attr_length (insn) == 4)
14089 return \"bdz %l0\";
14091 return \"{bdn|bdnz} $+8\;b %l0\";
14093 [(set_attr "type" "branch")
14094 (set_attr "length" "*,12,16,16")])
14096 (define_insn "*ctrdi_internal6"
14098 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14101 (label_ref (match_operand 0 "" ""))))
14102 (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14103 (plus:DI (match_dup 1)
14105 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14106 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14110 if (which_alternative != 0)
14112 else if (get_attr_length (insn) == 4)
14113 return \"{bdn|bdnz} %l0\";
14115 return \"bdz $+8\;b %l0\";
14117 [(set_attr "type" "branch")
14118 (set_attr "length" "*,12,16,16")])
14120 ;; Now the splitters if we could not allocate the CTR register
14124 (if_then_else (match_operator 2 "comparison_operator"
14125 [(match_operand:SI 1 "gpc_reg_operand" "")
14127 (match_operand 5 "" "")
14128 (match_operand 6 "" "")))
14129 (set (match_operand:SI 0 "gpc_reg_operand" "")
14130 (plus:SI (match_dup 1)
14132 (clobber (match_scratch:CC 3 ""))
14133 (clobber (match_scratch:SI 4 ""))]
14134 "TARGET_32BIT && reload_completed"
14135 [(parallel [(set (match_dup 3)
14136 (compare:CC (plus:SI (match_dup 1)
14140 (plus:SI (match_dup 1)
14142 (set (pc) (if_then_else (match_dup 7)
14146 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14147 operands[3], const0_rtx); }")
14151 (if_then_else (match_operator 2 "comparison_operator"
14152 [(match_operand:SI 1 "gpc_reg_operand" "")
14154 (match_operand 5 "" "")
14155 (match_operand 6 "" "")))
14156 (set (match_operand:SI 0 "nonimmediate_operand" "")
14157 (plus:SI (match_dup 1) (const_int -1)))
14158 (clobber (match_scratch:CC 3 ""))
14159 (clobber (match_scratch:SI 4 ""))]
14160 "TARGET_32BIT && reload_completed
14161 && ! gpc_reg_operand (operands[0], SImode)"
14162 [(parallel [(set (match_dup 3)
14163 (compare:CC (plus:SI (match_dup 1)
14167 (plus:SI (match_dup 1)
14171 (set (pc) (if_then_else (match_dup 7)
14175 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14176 operands[3], const0_rtx); }")
14179 (if_then_else (match_operator 2 "comparison_operator"
14180 [(match_operand:DI 1 "gpc_reg_operand" "")
14182 (match_operand 5 "" "")
14183 (match_operand 6 "" "")))
14184 (set (match_operand:DI 0 "gpc_reg_operand" "")
14185 (plus:DI (match_dup 1)
14187 (clobber (match_scratch:CC 3 ""))
14188 (clobber (match_scratch:DI 4 ""))]
14189 "TARGET_64BIT && reload_completed"
14190 [(parallel [(set (match_dup 3)
14191 (compare:CC (plus:DI (match_dup 1)
14195 (plus:DI (match_dup 1)
14197 (set (pc) (if_then_else (match_dup 7)
14201 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14202 operands[3], const0_rtx); }")
14206 (if_then_else (match_operator 2 "comparison_operator"
14207 [(match_operand:DI 1 "gpc_reg_operand" "")
14209 (match_operand 5 "" "")
14210 (match_operand 6 "" "")))
14211 (set (match_operand:DI 0 "nonimmediate_operand" "")
14212 (plus:DI (match_dup 1) (const_int -1)))
14213 (clobber (match_scratch:CC 3 ""))
14214 (clobber (match_scratch:DI 4 ""))]
14215 "TARGET_64BIT && reload_completed
14216 && ! gpc_reg_operand (operands[0], DImode)"
14217 [(parallel [(set (match_dup 3)
14218 (compare:CC (plus:DI (match_dup 1)
14222 (plus:DI (match_dup 1)
14226 (set (pc) (if_then_else (match_dup 7)
14230 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14231 operands[3], const0_rtx); }")
14233 (define_insn "trap"
14234 [(trap_if (const_int 1) (const_int 0))]
14238 (define_expand "conditional_trap"
14239 [(trap_if (match_operator 0 "trap_comparison_operator"
14240 [(match_dup 2) (match_dup 3)])
14241 (match_operand 1 "const_int_operand" ""))]
14243 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14244 operands[2] = rs6000_compare_op0;
14245 operands[3] = rs6000_compare_op1;")
14248 [(trap_if (match_operator 0 "trap_comparison_operator"
14249 [(match_operand:SI 1 "register_operand" "r")
14250 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14253 "{t|tw}%V0%I2 %1,%2")
14256 [(trap_if (match_operator 0 "trap_comparison_operator"
14257 [(match_operand:DI 1 "register_operand" "r")
14258 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14263 ;; Insns related to generating the function prologue and epilogue.
14265 (define_expand "prologue"
14266 [(use (const_int 0))]
14267 "TARGET_SCHED_PROLOG"
14270 rs6000_emit_prologue ();
14274 (define_insn "*movesi_from_cr_one"
14275 [(match_parallel 0 "mfcr_operation"
14276 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14277 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14278 (match_operand 3 "immediate_operand" "n")]
14279 UNSPEC_MOVESI_FROM_CR))])]
14285 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14287 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14288 operands[4] = GEN_INT (mask);
14289 output_asm_insn (\"mfcr %1,%4\", operands);
14293 [(set_attr "type" "mfcrf")])
14295 (define_insn "movesi_from_cr"
14296 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14297 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14298 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14299 UNSPEC_MOVESI_FROM_CR))]
14302 [(set_attr "type" "mfcr")])
14304 (define_insn "*stmw"
14305 [(match_parallel 0 "stmw_operation"
14306 [(set (match_operand:SI 1 "memory_operand" "=m")
14307 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14309 "{stm|stmw} %2,%1")
14311 (define_insn "*save_fpregs_si"
14312 [(match_parallel 0 "any_parallel_operand"
14313 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14314 (use (match_operand:SI 2 "call_operand" "s"))
14315 (set (match_operand:DF 3 "memory_operand" "=m")
14316 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14319 [(set_attr "type" "branch")
14320 (set_attr "length" "4")])
14322 (define_insn "*save_fpregs_di"
14323 [(match_parallel 0 "any_parallel_operand"
14324 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14325 (use (match_operand:DI 2 "call_operand" "s"))
14326 (set (match_operand:DF 3 "memory_operand" "=m")
14327 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14330 [(set_attr "type" "branch")
14331 (set_attr "length" "4")])
14333 ; These are to explain that changes to the stack pointer should
14334 ; not be moved over stores to stack memory.
14335 (define_insn "stack_tie"
14336 [(set (match_operand:BLK 0 "memory_operand" "+m")
14337 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14340 [(set_attr "length" "0")])
14343 (define_expand "epilogue"
14344 [(use (const_int 0))]
14345 "TARGET_SCHED_PROLOG"
14348 rs6000_emit_epilogue (FALSE);
14352 ; On some processors, doing the mtcrf one CC register at a time is
14353 ; faster (like on the 604e). On others, doing them all at once is
14354 ; faster; for instance, on the 601 and 750.
14356 (define_expand "movsi_to_cr_one"
14357 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14358 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14359 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14361 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14363 (define_insn "*movsi_to_cr"
14364 [(match_parallel 0 "mtcrf_operation"
14365 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14366 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14367 (match_operand 3 "immediate_operand" "n")]
14368 UNSPEC_MOVESI_TO_CR))])]
14374 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14375 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14376 operands[4] = GEN_INT (mask);
14377 return \"mtcrf %4,%2\";
14379 [(set_attr "type" "mtcr")])
14381 (define_insn "*mtcrfsi"
14382 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14383 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14384 (match_operand 2 "immediate_operand" "n")]
14385 UNSPEC_MOVESI_TO_CR))]
14386 "GET_CODE (operands[0]) == REG
14387 && CR_REGNO_P (REGNO (operands[0]))
14388 && GET_CODE (operands[2]) == CONST_INT
14389 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14391 [(set_attr "type" "mtcr")])
14393 ; The load-multiple instructions have similar properties.
14394 ; Note that "load_multiple" is a name known to the machine-independent
14395 ; code that actually corresponds to the powerpc load-string.
14397 (define_insn "*lmw"
14398 [(match_parallel 0 "lmw_operation"
14399 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14400 (match_operand:SI 2 "memory_operand" "m"))])]
14404 (define_insn "*return_internal_si"
14406 (use (match_operand:SI 0 "register_operand" "lc"))]
14409 [(set_attr "type" "jmpreg")])
14411 (define_insn "*return_internal_di"
14413 (use (match_operand:DI 0 "register_operand" "lc"))]
14416 [(set_attr "type" "jmpreg")])
14418 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14419 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14421 (define_insn "*return_and_restore_fpregs_si"
14422 [(match_parallel 0 "any_parallel_operand"
14424 (use (match_operand:SI 1 "register_operand" "l"))
14425 (use (match_operand:SI 2 "call_operand" "s"))
14426 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14427 (match_operand:DF 4 "memory_operand" "m"))])]
14431 (define_insn "*return_and_restore_fpregs_di"
14432 [(match_parallel 0 "any_parallel_operand"
14434 (use (match_operand:DI 1 "register_operand" "l"))
14435 (use (match_operand:DI 2 "call_operand" "s"))
14436 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14437 (match_operand:DF 4 "memory_operand" "m"))])]
14441 ; This is used in compiling the unwind routines.
14442 (define_expand "eh_return"
14443 [(use (match_operand 0 "general_operand" ""))]
14448 emit_insn (gen_eh_set_lr_si (operands[0]));
14450 emit_insn (gen_eh_set_lr_di (operands[0]));
14454 ; We can't expand this before we know where the link register is stored.
14455 (define_insn "eh_set_lr_si"
14456 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
14458 (clobber (match_scratch:SI 1 "=&b"))]
14462 (define_insn "eh_set_lr_di"
14463 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
14465 (clobber (match_scratch:DI 1 "=&b"))]
14470 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14471 (clobber (match_scratch 1 ""))]
14476 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14480 (define_insn "prefetch"
14481 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
14482 (match_operand:SI 1 "const_int_operand" "n")
14483 (match_operand:SI 2 "const_int_operand" "n"))]
14487 if (GET_CODE (operands[0]) == REG)
14488 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14489 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14491 [(set_attr "type" "load")])
14493 ; Atomic instructions
14495 (define_insn "memory_barrier"
14496 [(set (mem:BLK (match_scratch 0 "X"))
14497 (unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_SYNC))]
14501 (define_insn "sync_compare_and_swap<mode>"
14502 [(set (match_operand:GPR 1 "memory_operand" "+Z")
14503 (unspec:GPR [(match_dup 1)
14504 (match_operand:GPR 2 "reg_or_short_operand" "rI")
14505 (match_operand:GPR 3 "gpc_reg_operand" "r")]
14507 (set (match_operand:GPR 0 "gpc_reg_operand" "=&r") (match_dup 1))
14508 (set (mem:BLK (match_scratch 5 "X"))
14509 (unspec:BLK [(mem:BLK (match_scratch 6 "X"))] UNSPEC_SYNC))
14510 (clobber (match_scratch:CC 4 "=&x"))]
14512 "sync\n\t<larx> %0,%y1\n\tcmp<wd>%I2 %0,%2\n\tbne- $+12\n\t<stcx> %3,%y1\n\tbne- $-16\n\tisync"
14513 [(set_attr "length" "28")])
14515 (define_expand "sync_add<mode>"
14516 [(use (match_operand:INT1 0 "memory_operand" ""))
14517 (use (match_operand:INT1 1 "add_operand" ""))]
14521 rs6000_emit_sync (PLUS, <MODE>mode, operands[0], operands[1],
14522 NULL_RTX, NULL_RTX, true);
14526 (define_expand "sync_sub<mode>"
14527 [(use (match_operand:GPR 0 "memory_operand" ""))
14528 (use (match_operand:GPR 1 "gpc_reg_operand" ""))]
14532 rs6000_emit_sync (MINUS, <MODE>mode, operands[0], operands[1],
14533 NULL_RTX, NULL_RTX, true);
14537 (define_expand "sync_ior<mode>"
14538 [(use (match_operand:INT1 0 "memory_operand" ""))
14539 (use (match_operand:INT1 1 "logical_operand" ""))]
14543 rs6000_emit_sync (IOR, <MODE>mode, operands[0], operands[1],
14544 NULL_RTX, NULL_RTX, true);
14548 (define_expand "sync_and<mode>"
14549 [(use (match_operand:INT1 0 "memory_operand" ""))
14550 (use (match_operand:INT1 1 "and_operand" ""))]
14554 rs6000_emit_sync (AND, <MODE>mode, operands[0], operands[1],
14555 NULL_RTX, NULL_RTX, true);
14559 (define_expand "sync_xor<mode>"
14560 [(use (match_operand:INT1 0 "memory_operand" ""))
14561 (use (match_operand:INT1 1 "logical_operand" ""))]
14565 rs6000_emit_sync (XOR, <MODE>mode, operands[0], operands[1],
14566 NULL_RTX, NULL_RTX, true);
14570 (define_expand "sync_nand<mode>"
14571 [(use (match_operand:INT1 0 "memory_operand" ""))
14572 (use (match_operand:INT1 1 "gpc_reg_operand" ""))]
14576 rs6000_emit_sync (AND, <MODE>mode,
14577 gen_rtx_NOT (<MODE>mode, operands[0]),
14579 NULL_RTX, NULL_RTX, true);
14583 (define_expand "sync_old_add<mode>"
14584 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14585 (use (match_operand:INT1 1 "memory_operand" ""))
14586 (use (match_operand:INT1 2 "add_operand" ""))]
14590 rs6000_emit_sync (PLUS, <MODE>mode, operands[1], operands[2],
14591 operands[0], NULL_RTX, true);
14595 (define_expand "sync_old_sub<mode>"
14596 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
14597 (use (match_operand:GPR 1 "memory_operand" ""))
14598 (use (match_operand:GPR 2 "gpc_reg_operand" ""))]
14602 rs6000_emit_sync (MINUS, <MODE>mode, operands[1], operands[2],
14603 operands[0], NULL_RTX, true);
14607 (define_expand "sync_old_ior<mode>"
14608 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14609 (use (match_operand:INT1 1 "memory_operand" ""))
14610 (use (match_operand:INT1 2 "logical_operand" ""))]
14614 rs6000_emit_sync (IOR, <MODE>mode, operands[1], operands[2],
14615 operands[0], NULL_RTX, true);
14619 (define_expand "sync_old_and<mode>"
14620 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14621 (use (match_operand:INT1 1 "memory_operand" ""))
14622 (use (match_operand:INT1 2 "and_operand" ""))]
14626 rs6000_emit_sync (AND, <MODE>mode, operands[1], operands[2],
14627 operands[0], NULL_RTX, true);
14631 (define_expand "sync_old_xor<mode>"
14632 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14633 (use (match_operand:INT1 1 "memory_operand" ""))
14634 (use (match_operand:INT1 2 "logical_operand" ""))]
14638 rs6000_emit_sync (XOR, <MODE>mode, operands[1], operands[2],
14639 operands[0], NULL_RTX, true);
14643 (define_expand "sync_old_nand<mode>"
14644 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14645 (use (match_operand:INT1 1 "memory_operand" ""))
14646 (use (match_operand:INT1 2 "gpc_reg_operand" ""))]
14650 rs6000_emit_sync (AND, <MODE>mode,
14651 gen_rtx_NOT (<MODE>mode, operands[1]),
14653 operands[0], NULL_RTX, true);
14657 (define_expand "sync_new_add<mode>"
14658 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14659 (use (match_operand:INT1 1 "memory_operand" ""))
14660 (use (match_operand:INT1 2 "add_operand" ""))]
14664 rs6000_emit_sync (PLUS, <MODE>mode, operands[1], operands[2],
14665 NULL_RTX, operands[0], true);
14669 (define_expand "sync_new_sub<mode>"
14670 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
14671 (use (match_operand:GPR 1 "memory_operand" ""))
14672 (use (match_operand:GPR 2 "gpc_reg_operand" ""))]
14676 rs6000_emit_sync (MINUS, <MODE>mode, operands[1], operands[2],
14677 NULL_RTX, operands[0], true);
14681 (define_expand "sync_new_ior<mode>"
14682 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14683 (use (match_operand:INT1 1 "memory_operand" ""))
14684 (use (match_operand:INT1 2 "logical_operand" ""))]
14688 rs6000_emit_sync (IOR, <MODE>mode, operands[1], operands[2],
14689 NULL_RTX, operands[0], true);
14693 (define_expand "sync_new_and<mode>"
14694 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14695 (use (match_operand:INT1 1 "memory_operand" ""))
14696 (use (match_operand:INT1 2 "and_operand" ""))]
14700 rs6000_emit_sync (AND, <MODE>mode, operands[1], operands[2],
14701 NULL_RTX, operands[0], true);
14705 (define_expand "sync_new_xor<mode>"
14706 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14707 (use (match_operand:INT1 1 "memory_operand" ""))
14708 (use (match_operand:INT1 2 "logical_operand" ""))]
14712 rs6000_emit_sync (XOR, <MODE>mode, operands[1], operands[2],
14713 NULL_RTX, operands[0], true);
14717 (define_expand "sync_new_nand<mode>"
14718 [(use (match_operand:INT1 0 "gpc_reg_operand" ""))
14719 (use (match_operand:INT1 1 "memory_operand" ""))
14720 (use (match_operand:INT1 2 "gpc_reg_operand" ""))]
14724 rs6000_emit_sync (AND, <MODE>mode,
14725 gen_rtx_NOT (<MODE>mode, operands[1]),
14727 NULL_RTX, operands[0], true);
14731 ; the sync_*_internal patterns all have these operands:
14732 ; 0 - memory location
14734 ; 2 - value in memory after operation
14735 ; 3 - value in memory immediately before operation
14737 (define_insn "*sync_add<mode>_internal"
14738 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r,&r")
14739 (plus:GPR (match_operand:GPR 0 "memory_operand" "+Z,Z")
14740 (match_operand:GPR 1 "add_operand" "rI,L")))
14741 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b,&b") (match_dup 0))
14743 (unspec:GPR [(plus:GPR (match_dup 0) (match_dup 1))]
14745 (clobber (match_scratch:CC 4 "=&x,&x"))]
14748 <larx> %3,%y0\n\tadd%I1 %2,%3,%1\n\t<stcx> %2,%y0\n\tbne- $-12
14749 <larx> %3,%y0\n\taddis %2,%3,%v1\n\t<stcx> %2,%y0\n\tbne- $-12"
14750 [(set_attr "length" "16,16")])
14752 (define_insn "*sync_addshort_internal"
14753 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r")
14754 (ior:SI (and:SI (plus:SI (match_operand:SI 0 "memory_operand" "+Z")
14755 (match_operand:SI 1 "add_operand" "rI"))
14756 (match_operand:SI 4 "gpc_reg_operand" "r"))
14757 (and:SI (not:SI (match_dup 4)) (match_dup 0))))
14758 (set (match_operand:SI 3 "gpc_reg_operand" "=&b") (match_dup 0))
14760 (unspec:SI [(ior:SI (and:SI (plus:SI (match_dup 0) (match_dup 1))
14762 (and:SI (not:SI (match_dup 4)) (match_dup 0)))]
14764 (clobber (match_scratch:CC 5 "=&x"))
14765 (clobber (match_scratch:SI 6 "=&r"))]
14767 "lwarx %3,%y0\n\tadd%I1 %2,%3,%1\n\tandc %6,%3,%4\n\tand %2,%2,%4\n\tor %2,%2,%6\n\tstwcx. %2,%y0\n\tbne- $-24"
14768 [(set_attr "length" "28")])
14770 (define_insn "*sync_sub<mode>_internal"
14771 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
14772 (minus:GPR (match_operand:GPR 0 "memory_operand" "+Z")
14773 (match_operand:GPR 1 "gpc_reg_operand" "r")))
14774 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
14776 (unspec:GPR [(minus:GPR (match_dup 0) (match_dup 1))]
14778 (clobber (match_scratch:CC 4 "=&x"))]
14780 "<larx> %3,%y0\n\tsubf %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- $-12"
14781 [(set_attr "length" "16")])
14783 (define_insn "*sync_andsi_internal"
14784 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r,&r,&r,&r")
14785 (and:SI (match_operand:SI 0 "memory_operand" "+Z,Z,Z,Z")
14786 (match_operand:SI 1 "and_operand" "r,T,K,L")))
14787 (set (match_operand:SI 3 "gpc_reg_operand" "=&b,&b,&b,&b") (match_dup 0))
14789 (unspec:SI [(and:SI (match_dup 0) (match_dup 1))]
14791 (clobber (match_scratch:CC 4 "=&x,&x,&x,&x"))]
14794 lwarx %3,%y0\n\tand %2,%3,%1\n\tstwcx. %2,%y0\n\tbne- $-12
14795 lwarx %3,%y0\n\trlwinm %2,%3,0,%m1,%M1\n\tstwcx. %2,%y0\n\tbne- $-12
14796 lwarx %3,%y0\n\tandi. %2,%3,%b1\n\tstwcx. %2,%y0\n\tbne- $-12
14797 lwarx %3,%y0\n\tandis. %2,%3,%u1\n\tstwcx. %2,%y0\n\tbne- $-12"
14798 [(set_attr "length" "16,16,16,16")])
14800 (define_insn "*sync_anddi_internal"
14801 [(set (match_operand:DI 2 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
14802 (and:DI (match_operand:DI 0 "memory_operand" "+Z,Z,Z,Z,Z")
14803 (match_operand:DI 1 "and_operand" "r,S,T,K,J")))
14804 (set (match_operand:DI 3 "gpc_reg_operand" "=&b,&b,&b,&b,&b") (match_dup 0))
14806 (unspec:DI [(and:DI (match_dup 0) (match_dup 1))]
14808 (clobber (match_scratch:CC 4 "=&x,&x,&x,&x,&x"))]
14811 ldarx %3,%y0\n\tand %2,%3,%1\n\tstdcx. %2,%y0\n\tbne- $-12
14812 ldarx %3,%y0\n\trldic%B1 %2,%3,0,%S1\n\tstdcx. %2,%y0\n\tbne- $-12
14813 ldarx %3,%y0\n\trlwinm %2,%3,0,%m1,%M1\n\tstdcx. %2,%y0\n\tbne- $-12
14814 ldarx %3,%y0\n\tandi. %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- $-12
14815 ldarx %3,%y0\n\tandis. %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- $-12"
14816 [(set_attr "length" "16,16,16,16,16")])
14818 (define_insn "*sync_boolsi_internal"
14819 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r,&r,&r")
14820 (match_operator:SI 4 "boolean_or_operator"
14821 [(match_operand:SI 0 "memory_operand" "+Z,Z,Z")
14822 (match_operand:SI 1 "logical_operand" "r,K,L")]))
14823 (set (match_operand:SI 3 "gpc_reg_operand" "=&b,&b,&b") (match_dup 0))
14824 (set (match_dup 0) (unspec:SI [(match_dup 4)] UNSPEC_SYNC_OP))
14825 (clobber (match_scratch:CC 5 "=&x,&x,&x"))]
14828 lwarx %3,%y0\n\t%q4 %2,%3,%1\n\tstwcx. %2,%y0\n\tbne- $-12
14829 lwarx %3,%y0\n\t%q4i %2,%3,%b1\n\tstwcx. %2,%y0\n\tbne- $-12
14830 lwarx %3,%y0\n\t%q4is %2,%3,%u1\n\tstwcx. %2,%y0\n\tbne- $-12"
14831 [(set_attr "length" "16,16,16")])
14833 (define_insn "*sync_booldi_internal"
14834 [(set (match_operand:DI 2 "gpc_reg_operand" "=&r,&r,&r")
14835 (match_operator:DI 4 "boolean_or_operator"
14836 [(match_operand:DI 0 "memory_operand" "+Z,Z,Z")
14837 (match_operand:DI 1 "logical_operand" "r,K,JF")]))
14838 (set (match_operand:DI 3 "gpc_reg_operand" "=&b,&b,&b") (match_dup 0))
14839 (set (match_dup 0) (unspec:DI [(match_dup 4)] UNSPEC_SYNC_OP))
14840 (clobber (match_scratch:CC 5 "=&x,&x,&x"))]
14843 ldarx %3,%y0\n\t%q4 %2,%3,%1\n\tstdcx. %2,%y0\n\tbne- $-12
14844 ldarx %3,%y0\n\t%q4i %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- $-12
14845 ldarx %3,%y0\n\t%q4is %2,%3,%u1\n\tstdcx. %2,%y0\n\tbne- $-12"
14846 [(set_attr "length" "16,16,16")])
14848 (define_insn "*sync_boolc<mode>_internal"
14849 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
14850 (match_operator:GPR 4 "boolean_operator"
14851 [(not:GPR (match_operand:GPR 0 "memory_operand" "+Z"))
14852 (match_operand:GPR 1 "gpc_reg_operand" "r")]))
14853 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
14854 (set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP))
14855 (clobber (match_scratch:CC 5 "=&x"))]
14857 "<larx> %3,%y0\n\t%q4 %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- $-12"
14858 [(set_attr "length" "16")])
14860 ; This pattern could also take immediate values of operand 1,
14861 ; since the non-NOT version of the operator is used; but this is not
14862 ; very useful, since in practice operand 1 is a full 32-bit value.
14863 ; Likewise, operand 5 is in practice either <= 2^16 or it is a register.
14864 (define_insn "*sync_boolcshort_internal"
14865 [(set (match_operand:SI 2 "gpc_reg_operand" "=&r")
14866 (match_operator:SI 4 "boolean_operator"
14867 [(xor:SI (match_operand:SI 0 "memory_operand" "+Z")
14868 (match_operand:SI 5 "logical_operand" "rK"))
14869 (match_operand:SI 1 "gpc_reg_operand" "r")]))
14870 (set (match_operand:SI 3 "gpc_reg_operand" "=&b") (match_dup 0))
14871 (set (match_dup 0) (unspec:SI [(match_dup 4)] UNSPEC_SYNC_OP))
14872 (clobber (match_scratch:CC 6 "=&x"))]
14874 "lwarx %3,%y0\n\txor%I2 %2,%3,%5\n\t%q4 %2,%2,%1\n\tstwcx. %2,%y0\n\tbne- $-16"
14875 [(set_attr "length" "20")])
14877 (define_insn "*sync_boolc<mode>_internal2"
14878 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
14879 (match_operator:GPR 4 "boolean_operator"
14880 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
14881 (match_operand:GPR 0 "memory_operand" "+Z")]))
14882 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
14883 (set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP))
14884 (clobber (match_scratch:CC 5 "=&x"))]
14886 "<larx> %3,%y0\n\t%q4 %2,%3,%1\n\t<stcx> %2,%y0\n\tbne- $-12"
14887 [(set_attr "length" "16")])
14889 (define_insn "*sync_boolcc<mode>_internal"
14890 [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r")
14891 (match_operator:GPR 4 "boolean_operator"
14892 [(not:GPR (match_operand:GPR 0 "memory_operand" "+Z"))
14893 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))]))
14894 (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0))
14895 (set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP))
14896 (clobber (match_scratch:CC 5 "=&x"))]
14898 "<larx> %3,%y0\n\t%q4 %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- $-12"
14899 [(set_attr "length" "16")])
14901 (define_insn "isync"
14902 [(set (mem:BLK (match_scratch 0 "X"))
14903 (unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_ISYNC))]
14907 (define_insn "sync_lock_test_and_set<mode>"
14908 [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r")
14909 (match_operand:GPR 1 "memory_operand" "+Z"))
14910 (set (match_dup 1) (unspec:GPR [(match_operand:GPR 2 "gpc_reg_operand" "r")]
14912 (clobber (match_scratch:CC 3 "=&x"))
14913 (set (mem:BLK (match_scratch 4 "X"))
14914 (unspec:BLK [(mem:BLK (match_scratch 5 "X"))] UNSPEC_ISYNC))]
14916 "<larx> %0,%y1\n\t<stcx> %2,%y1\n\tbne- $-8\n\tisync"
14917 [(set_attr "length" "16")])
14919 (define_expand "sync_lock_release<mode>"
14920 [(set (match_operand:INT 0 "memory_operand")
14921 (match_operand:INT 1 "any_operand"))]
14925 emit_insn (gen_lwsync ());
14926 emit_move_insn (operands[0], operands[1]);
14930 ; Some AIX assemblers don't accept lwsync, so we use a .long.
14931 (define_insn "lwsync"
14932 [(set (mem:BLK (match_scratch 0 "X"))
14933 (unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_LWSYNC))]
14935 ".long 0x7c2004ac")
14939 (include "altivec.md")