1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
23 /* Note that some other tm.h files include this one and then override
24 many of the definitions. */
26 /* Definitions for the object file format. These are set at
29 #define OBJECT_XCOFF 1
32 #define OBJECT_MACHO 4
34 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
35 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
36 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
37 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
43 /* Default string to use for cpu if not specified. */
44 #ifndef TARGET_CPU_DEFAULT
45 #define TARGET_CPU_DEFAULT ((char *)0)
48 /* Common ASM definitions used by ASM_SPEC among the various targets
49 for handling -mcpu=xxx switches. */
50 #define ASM_CPU_SPEC \
52 %{mpower: %{!mpower2: -mpwr}} \
55 %{mno-power: %{!mpowerpc*: -mcom}} \
56 %{!mno-power: %{!mpower2: %(asm_default)}}} \
57 %{mcpu=common: -mcom} \
58 %{mcpu=power: -mpwr} \
59 %{mcpu=power2: -mpwrx} \
60 %{mcpu=power3: -m604} \
61 %{mcpu=power4: -mpower4} \
62 %{mcpu=powerpc: -mppc} \
64 %{mcpu=rios1: -mpwr} \
65 %{mcpu=rios2: -mpwrx} \
71 %{mcpu=405fp: -m405} \
73 %{mcpu=440fp: -m440} \
79 %{mcpu=ec603e: -mppc} \
94 %{mcpu=970: -mpower4} \
95 %{mcpu=G5: -mpower4} \
96 %{mcpu=8540: -me500} \
97 %{maltivec: -maltivec}"
99 #define CPP_DEFAULT_SPEC ""
101 #define ASM_DEFAULT_SPEC ""
103 /* This macro defines names of additional specifications to put in the specs
104 that can be used in various specifications like CC1_SPEC. Its definition
105 is an initializer with a subgrouping for each command option.
107 Each subgrouping contains a string constant, that defines the
108 specification name, and a string constant that used by the GCC driver
111 Do not define this macro if it does not need to do anything. */
113 #define SUBTARGET_EXTRA_SPECS
115 #define EXTRA_SPECS \
116 { "cpp_default", CPP_DEFAULT_SPEC }, \
117 { "asm_cpu", ASM_CPU_SPEC }, \
118 { "asm_default", ASM_DEFAULT_SPEC }, \
119 SUBTARGET_EXTRA_SPECS
121 /* Architecture type. */
123 extern int target_flags;
125 /* Use POWER architecture instructions and MQ register. */
126 #define MASK_POWER 0x00000001
128 /* Use POWER2 extensions to POWER architecture. */
129 #define MASK_POWER2 0x00000002
131 /* Use PowerPC architecture instructions. */
132 #define MASK_POWERPC 0x00000004
134 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */
135 #define MASK_PPC_GPOPT 0x00000008
137 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */
138 #define MASK_PPC_GFXOPT 0x00000010
140 /* Use PowerPC-64 architecture instructions. */
141 #define MASK_POWERPC64 0x00000020
143 /* Use revised mnemonic names defined for PowerPC architecture. */
144 #define MASK_NEW_MNEMONICS 0x00000040
146 /* Disable placing fp constants in the TOC; can be turned on when the
148 #define MASK_NO_FP_IN_TOC 0x00000080
150 /* Disable placing symbol+offset constants in the TOC; can be turned on when
151 the TOC overflows. */
152 #define MASK_NO_SUM_IN_TOC 0x00000100
154 /* Output only one TOC entry per module. Normally linking fails if
155 there are more than 16K unique variables/constants in an executable. With
156 this option, linking fails only if there are more than 16K modules, or
157 if there are more than 16K unique variables/constant in a single module.
159 This is at the cost of having 2 extra loads and one extra store per
160 function, and one less allocable register. */
161 #define MASK_MINIMAL_TOC 0x00000200
163 /* Nonzero for the 64 bit ABIs: longs and pointers are 64 bits. The
164 chip is running in "64-bit mode", in which CR0 is set in dot
165 operations based on all 64 bits of the register, bdnz works on 64-bit
166 ctr, lr is 64 bits, and so on. Requires MASK_POWERPC64. */
167 #define MASK_64BIT 0x00000400
169 /* Disable use of FPRs. */
170 #define MASK_SOFT_FLOAT 0x00000800
172 /* Enable load/store multiple, even on PowerPC */
173 #define MASK_MULTIPLE 0x00001000
175 /* Use string instructions for block moves */
176 #define MASK_STRING 0x00002000
178 /* Disable update form of load/store */
179 #define MASK_NO_UPDATE 0x00004000
181 /* Disable fused multiply/add operations */
182 #define MASK_NO_FUSED_MADD 0x00008000
184 /* Nonzero if we need to schedule the prolog and epilog. */
185 #define MASK_SCHED_PROLOG 0x00010000
187 /* Use AltiVec instructions. */
188 #define MASK_ALTIVEC 0x00020000
190 /* Return small structures in memory (as the AIX ABI requires). */
191 #define MASK_AIX_STRUCT_RET 0x00040000
193 /* Use single field mfcr instruction. */
194 #define MASK_MFCRF 0x00080000
196 /* The only remaining free bits are 0x00600000. linux64.h uses
197 0x00100000, and sysv4.h uses 0x00800000 -> 0x40000000.
198 0x80000000 is not available because target_flags is signed. */
200 #define TARGET_POWER (target_flags & MASK_POWER)
201 #define TARGET_POWER2 (target_flags & MASK_POWER2)
202 #define TARGET_POWERPC (target_flags & MASK_POWERPC)
203 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
204 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
205 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
206 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
207 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
208 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
209 #define TARGET_64BIT (target_flags & MASK_64BIT)
210 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
211 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
212 #define TARGET_STRING (target_flags & MASK_STRING)
213 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
214 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
215 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
216 #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
217 #define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET)
219 /* Define TARGET_MFCRF if the target assembler supports the optional
220 field operand for mfcr and the target processor supports the
224 #define TARGET_MFCRF (target_flags & MASK_MFCRF)
226 #define TARGET_MFCRF 0
230 #define TARGET_32BIT (! TARGET_64BIT)
231 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
232 #define TARGET_UPDATE (! TARGET_NO_UPDATE)
233 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
235 /* Emit a dtp-relative reference to a TLS variable. */
238 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
239 rs6000_output_dwarf_dtprel (FILE, SIZE, X)
243 #define HAVE_AS_TLS 0
247 /* For libgcc2 we make sure this is a compile time constant */
248 #if defined (__64BIT__) || defined (__powerpc64__)
249 #define TARGET_POWERPC64 1
251 #define TARGET_POWERPC64 0
254 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
257 #define TARGET_XL_CALL 0
259 /* Run-time compilation parameters selecting different hardware subsets.
261 Macro to define tables used to set the flags.
262 This is a list in braces of pairs in braces,
263 each pair being { "NAME", VALUE }
264 where VALUE is the bits to set or minus the bits to clear.
265 An empty string NAME is used to identify the default VALUE. */
267 #define TARGET_SWITCHES \
268 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
269 N_("Use POWER instruction set")}, \
270 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
272 N_("Use POWER2 instruction set")}, \
273 {"no-power2", - MASK_POWER2, \
274 N_("Do not use POWER2 instruction set")}, \
275 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
277 N_("Do not use POWER instruction set")}, \
278 {"powerpc", MASK_POWERPC, \
279 N_("Use PowerPC instruction set")}, \
280 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
281 | MASK_PPC_GFXOPT | MASK_POWERPC64), \
282 N_("Do not use PowerPC instruction set")}, \
283 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
284 N_("Use PowerPC General Purpose group optional instructions")},\
285 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
286 N_("Do not use PowerPC General Purpose group optional instructions")},\
287 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
288 N_("Use PowerPC Graphics group optional instructions")},\
289 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
290 N_("Do not use PowerPC Graphics group optional instructions")},\
291 {"powerpc64", MASK_POWERPC64, \
292 N_("Use PowerPC-64 instruction set")}, \
293 {"no-powerpc64", - MASK_POWERPC64, \
294 N_("Do not use PowerPC-64 instruction set")}, \
295 {"altivec", MASK_ALTIVEC , \
296 N_("Use AltiVec instructions")}, \
297 {"no-altivec", - MASK_ALTIVEC , \
298 N_("Do not use AltiVec instructions")}, \
299 {"new-mnemonics", MASK_NEW_MNEMONICS, \
300 N_("Use new mnemonics for PowerPC architecture")},\
301 {"old-mnemonics", -MASK_NEW_MNEMONICS, \
302 N_("Use old mnemonics for PowerPC architecture")},\
303 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
304 | MASK_MINIMAL_TOC), \
305 N_("Put everything in the regular TOC")}, \
306 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
307 N_("Place floating point constants in TOC")}, \
308 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
309 N_("Do not place floating point constants in TOC")},\
310 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
311 N_("Place symbol+offset constants in TOC")}, \
312 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
313 N_("Do not place symbol+offset constants in TOC")},\
314 {"minimal-toc", MASK_MINIMAL_TOC, \
315 "Use only one TOC entry per procedure"}, \
316 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
318 {"no-minimal-toc", - MASK_MINIMAL_TOC, \
319 N_("Place variable addresses in the regular TOC")},\
320 {"hard-float", - MASK_SOFT_FLOAT, \
321 N_("Use hardware floating point")}, \
322 {"soft-float", MASK_SOFT_FLOAT, \
323 N_("Do not use hardware floating point")}, \
324 {"multiple", MASK_MULTIPLE, \
325 N_("Generate load/store multiple instructions")}, \
326 {"no-multiple", - MASK_MULTIPLE, \
327 N_("Do not generate load/store multiple instructions")},\
328 {"string", MASK_STRING, \
329 N_("Generate string instructions for block moves")},\
330 {"no-string", - MASK_STRING, \
331 N_("Do not generate string instructions for block moves")},\
332 {"update", - MASK_NO_UPDATE, \
333 N_("Generate load/store with update instructions")},\
334 {"no-update", MASK_NO_UPDATE, \
335 N_("Do not generate load/store with update instructions")},\
336 {"fused-madd", - MASK_NO_FUSED_MADD, \
337 N_("Generate fused multiply/add instructions")},\
338 {"no-fused-madd", MASK_NO_FUSED_MADD, \
339 N_("Do not generate fused multiply/add instructions")},\
340 {"sched-prolog", MASK_SCHED_PROLOG, \
342 {"no-sched-prolog", -MASK_SCHED_PROLOG, \
343 N_("Do not schedule the start and end of the procedure")},\
344 {"sched-epilog", MASK_SCHED_PROLOG, \
346 {"no-sched-epilog", -MASK_SCHED_PROLOG, \
348 {"aix-struct-return", MASK_AIX_STRUCT_RET, \
349 N_("Return all structures in memory (AIX default)")},\
350 {"svr4-struct-return", - MASK_AIX_STRUCT_RET, \
351 N_("Return small structures in registers (SVR4 default)")},\
352 {"no-aix-struct-return", - MASK_AIX_STRUCT_RET, \
354 {"no-svr4-struct-return", MASK_AIX_STRUCT_RET, \
356 {"mfcrf", MASK_MFCRF, \
357 N_("Generate single field mfcr instruction")}, \
358 {"no-mfcrf", - MASK_MFCRF, \
359 N_("Do not generate single field mfcr instruction")},\
361 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
364 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
366 /* This is meant to be redefined in the host dependent files */
367 #define SUBTARGET_SWITCHES
369 /* Processor type. Order must match cpu attribute in MD file. */
392 extern enum processor_type rs6000_cpu;
394 /* Recast the processor type to the cpu attribute. */
395 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
397 /* Define generic processor types based upon current deployment. */
398 #define PROCESSOR_COMMON PROCESSOR_PPC601
399 #define PROCESSOR_POWER PROCESSOR_RIOS1
400 #define PROCESSOR_POWERPC PROCESSOR_PPC604
401 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
403 /* Define the default processor. This is overridden by other tm.h files. */
404 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
405 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
407 /* Specify the dialect of assembler to use. New mnemonics is dialect one
408 and the old mnemonics are dialect zero. */
409 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
411 /* Types of costly dependences. */
412 enum rs6000_dependence_cost
414 max_dep_latency = 1000,
417 true_store_to_load_dep_costly,
418 store_to_load_dep_costly
421 /* Types of nop insertion schemes in sched target hook sched_finish. */
422 enum rs6000_nop_insertion
424 sched_finish_regroup_exact = 1000,
425 sched_finish_pad_groups,
429 /* Dispatch group termination caused by an insn. */
430 enum group_termination
436 /* This is meant to be overridden in target specific files. */
437 #define SUBTARGET_OPTIONS
439 #define TARGET_OPTIONS \
441 {"cpu=", &rs6000_select[1].string, \
442 N_("Use features of and schedule code for given CPU"), 0}, \
443 {"tune=", &rs6000_select[2].string, \
444 N_("Schedule code for given CPU"), 0}, \
445 {"debug=", &rs6000_debug_name, N_("Enable debug output"), 0}, \
446 {"traceback=", &rs6000_traceback_name, \
447 N_("Select full, part, or no traceback table"), 0}, \
448 {"abi=", &rs6000_abi_string, N_("Specify ABI to use"), 0}, \
449 {"long-double-", &rs6000_long_double_size_string, \
450 N_("Specify size of long double (64 or 128 bits)"), 0}, \
451 {"isel=", &rs6000_isel_string, \
452 N_("Specify yes/no if isel instructions should be generated"), 0}, \
453 {"spe=", &rs6000_spe_string, \
454 N_("Specify yes/no if SPE SIMD instructions should be generated"), 0},\
455 {"float-gprs=", &rs6000_float_gprs_string, \
456 N_("Specify yes/no if using floating point in the GPRs"), 0}, \
457 {"vrsave=", &rs6000_altivec_vrsave_string, \
458 N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec"), 0}, \
459 {"longcall", &rs6000_longcall_switch, \
460 N_("Avoid all range limits on call instructions"), 0}, \
461 {"no-longcall", &rs6000_longcall_switch, "", 0}, \
462 {"warn-altivec-long", &rs6000_warn_altivec_long_switch, \
463 N_("Warn about deprecated 'vector long ...' AltiVec type usage"), 0}, \
464 {"no-warn-altivec-long", &rs6000_warn_altivec_long_switch, "", 0}, \
465 {"sched-costly-dep=", &rs6000_sched_costly_dep_str, \
466 N_("Determine which dependences between insns are considered costly"), 0}, \
467 {"insert-sched-nops=", &rs6000_sched_insert_nops_str, \
468 N_("Specify which post scheduling nop insertion scheme to apply"), 0}, \
469 {"align-", &rs6000_alignment_string, \
470 N_("Specify alignment of structure fields default/natural"), 0}, \
471 {"prioritize-restricted-insns=", &rs6000_sched_restricted_insns_priority_str, \
472 N_("Specify scheduling priority for dispatch slot restricted insns"), 0}, \
476 /* Support for a compile-time default CPU, et cetera. The rules are:
477 --with-cpu is ignored if -mcpu is specified.
478 --with-tune is ignored if -mtune is specified.
479 --with-float is ignored if -mhard-float or -msoft-float are
481 #define OPTION_DEFAULT_SPECS \
482 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
483 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
484 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
486 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
487 struct rs6000_cpu_select
495 extern struct rs6000_cpu_select rs6000_select[];
498 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
499 extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,eabi,aix,altivec} */
500 extern int rs6000_debug_stack; /* debug stack applications */
501 extern int rs6000_debug_arg; /* debug argument handling */
503 #define TARGET_DEBUG_STACK rs6000_debug_stack
504 #define TARGET_DEBUG_ARG rs6000_debug_arg
506 extern const char *rs6000_traceback_name; /* Type of traceback table. */
508 /* These are separate from target_flags because we've run out of bits
510 extern const char *rs6000_long_double_size_string;
511 extern int rs6000_long_double_type_size;
512 extern int rs6000_altivec_abi;
513 extern int rs6000_spe_abi;
514 extern int rs6000_isel;
515 extern int rs6000_spe;
516 extern int rs6000_float_gprs;
517 extern const char *rs6000_float_gprs_string;
518 extern const char *rs6000_isel_string;
519 extern const char *rs6000_spe_string;
520 extern const char *rs6000_altivec_vrsave_string;
521 extern int rs6000_altivec_vrsave;
522 extern const char *rs6000_longcall_switch;
523 extern int rs6000_default_long_calls;
524 extern const char* rs6000_alignment_string;
525 extern int rs6000_alignment_flags;
526 extern const char *rs6000_sched_restricted_insns_priority_str;
527 extern int rs6000_sched_restricted_insns_priority;
528 extern const char *rs6000_sched_costly_dep_str;
529 extern enum rs6000_dependence_cost rs6000_sched_costly_dep;
530 extern const char *rs6000_sched_insert_nops_str;
531 extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
533 extern int rs6000_warn_altivec_long;
534 extern const char *rs6000_warn_altivec_long_switch;
536 /* Alignment options for fields in structures for sub-targets following
538 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
539 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
541 Override the macro definitions when compiling libobjc to avoid undefined
542 reference to rs6000_alignment_flags due to library's use of GCC alignment
543 macros which use the macros below. */
545 #ifndef IN_TARGET_LIBS
546 #define MASK_ALIGN_POWER 0x00000000
547 #define MASK_ALIGN_NATURAL 0x00000001
548 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
550 #define TARGET_ALIGN_NATURAL 0
553 /* Set a default value for DEFAULT_SCHED_COSTLY_DEP used by target hook
554 is_costly_dependence. */
555 #define DEFAULT_SCHED_COSTLY_DEP \
556 (rs6000_cpu == PROCESSOR_POWER4 ? store_to_load_dep_costly : no_dep_costly)
558 /* Define if the target has restricted dispatch slot instructions. */
559 #define DEFAULT_RESTRICTED_INSNS_PRIORITY (rs6000_cpu == PROCESSOR_POWER4 ? 1 : 0)
561 /* Set a default value for post scheduling nop insertion scheme
562 (used by taget hook sched_finish). */
563 #define DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME \
564 (rs6000_cpu == PROCESSOR_POWER4 ? sched_finish_regroup_exact : sched_finish_none)
566 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
567 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
568 #define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave
570 #define TARGET_SPE_ABI 0
572 #define TARGET_E500 0
573 #define TARGET_ISEL 0
574 #define TARGET_FPRS 1
576 /* Sometimes certain combinations of command options do not make sense
577 on a particular target machine. You can define a macro
578 `OVERRIDE_OPTIONS' to take account of this. This macro, if
579 defined, is executed once just after all the command options have
582 Do not use this macro to turn on various extra optimizations for
583 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
585 On the RS/6000 this is used to define the target cpu type. */
587 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
589 /* Define this to change the optimizations performed by default. */
590 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
592 /* Show we can debug even without a frame pointer. */
593 #define CAN_DEBUG_WITHOUT_FP
596 #define REGISTER_TARGET_PRAGMAS() do { \
597 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
600 /* Target #defines. */
601 #define TARGET_CPU_CPP_BUILTINS() \
602 rs6000_cpu_cpp_builtins (pfile)
604 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
605 we're compiling for. Some configurations may need to override it. */
606 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
609 if (BYTES_BIG_ENDIAN) \
611 builtin_define ("__BIG_ENDIAN__"); \
612 builtin_define ("_BIG_ENDIAN"); \
613 builtin_assert ("machine=bigendian"); \
617 builtin_define ("__LITTLE_ENDIAN__"); \
618 builtin_define ("_LITTLE_ENDIAN"); \
619 builtin_assert ("machine=littleendian"); \
624 /* Target machine storage layout. */
626 /* Define this macro if it is advisable to hold scalars in registers
627 in a wider mode than that declared by the program. In such cases,
628 the value is constrained to be within the bounds of the declared
629 type, but kept valid in the wider mode. The signedness of the
630 extension may differ from that of the type. */
632 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
633 if (GET_MODE_CLASS (MODE) == MODE_INT \
634 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
635 (MODE) = TARGET_32BIT ? SImode : DImode;
637 /* Define this if most significant bit is lowest numbered
638 in instructions that operate on numbered bit-fields. */
639 /* That is true on RS/6000. */
640 #define BITS_BIG_ENDIAN 1
642 /* Define this if most significant byte of a word is the lowest numbered. */
643 /* That is true on RS/6000. */
644 #define BYTES_BIG_ENDIAN 1
646 /* Define this if most significant word of a multiword number is lowest
649 For RS/6000 we can decide arbitrarily since there are no machine
650 instructions for them. Might as well be consistent with bits and bytes. */
651 #define WORDS_BIG_ENDIAN 1
653 #define MAX_BITS_PER_WORD 64
655 /* Width of a word, in units (bytes). */
656 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
658 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
660 #define MIN_UNITS_PER_WORD 4
662 #define UNITS_PER_FP_WORD 8
663 #define UNITS_PER_ALTIVEC_WORD 16
664 #define UNITS_PER_SPE_WORD 8
666 /* Type used for ptrdiff_t, as a string used in a declaration. */
667 #define PTRDIFF_TYPE "int"
669 /* Type used for size_t, as a string used in a declaration. */
670 #define SIZE_TYPE "long unsigned int"
672 /* Type used for wchar_t, as a string used in a declaration. */
673 #define WCHAR_TYPE "short unsigned int"
675 /* Width of wchar_t in bits. */
676 #define WCHAR_TYPE_SIZE 16
678 /* A C expression for the size in bits of the type `short' on the
679 target machine. If you don't define this, the default is half a
680 word. (If this would be less than one storage unit, it is
681 rounded up to one unit.) */
682 #define SHORT_TYPE_SIZE 16
684 /* A C expression for the size in bits of the type `int' on the
685 target machine. If you don't define this, the default is one
687 #define INT_TYPE_SIZE 32
689 /* A C expression for the size in bits of the type `long' on the
690 target machine. If you don't define this, the default is one
692 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
694 /* A C expression for the size in bits of the type `long long' on the
695 target machine. If you don't define this, the default is two
697 #define LONG_LONG_TYPE_SIZE 64
699 /* A C expression for the size in bits of the type `float' on the
700 target machine. If you don't define this, the default is one
702 #define FLOAT_TYPE_SIZE 32
704 /* A C expression for the size in bits of the type `double' on the
705 target machine. If you don't define this, the default is two
707 #define DOUBLE_TYPE_SIZE 64
709 /* A C expression for the size in bits of the type `long double' on
710 the target machine. If you don't define this, the default is two
712 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
714 /* Define this to set long double type size to use in libgcc2.c, which can
715 not depend on target_flags. */
716 #ifdef __LONG_DOUBLE_128__
717 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
719 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
722 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
723 #define WIDEST_HARDWARE_FP_SIZE 64
725 /* Width in bits of a pointer.
726 See also the macro `Pmode' defined below. */
727 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
729 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
730 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
732 /* Boundary (in *bits*) on which stack pointer should be aligned. */
733 #define STACK_BOUNDARY ((TARGET_32BIT && !TARGET_ALTIVEC_ABI) ? 64 : 128)
735 /* Allocation boundary (in *bits*) for the code of a function. */
736 #define FUNCTION_BOUNDARY 32
738 /* No data type wants to be aligned rounder than this. */
739 #define BIGGEST_ALIGNMENT 128
741 /* A C expression to compute the alignment for a variables in the
742 local store. TYPE is the data type, and ALIGN is the alignment
743 that the object would ordinarily have. */
744 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
745 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
746 (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN)
748 /* Alignment of field after `int : 0' in a structure. */
749 #define EMPTY_FIELD_BOUNDARY 32
751 /* Every structure's size must be a multiple of this. */
752 #define STRUCTURE_SIZE_BOUNDARY 8
754 /* Return 1 if a structure or array containing FIELD should be
755 accessed using `BLKMODE'.
757 For the SPE, simd types are V2SI, and gcc can be tempted to put the
758 entire thing in a DI and use subregs to access the internals.
759 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
760 back-end. Because a single GPR can hold a V2SI, but not a DI, the
761 best thing to do is set structs to BLKmode and avoid Severe Tire
763 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
764 (TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE)
766 /* A bit-field declared as `int' forces `int' alignment for the struct. */
767 #define PCC_BITFIELD_TYPE_MATTERS 1
769 /* Make strings word-aligned so strcpy from constants will be faster.
770 Make vector constants quadword aligned. */
771 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
772 (TREE_CODE (EXP) == STRING_CST \
773 && (ALIGN) < BITS_PER_WORD \
777 /* Make arrays of chars word-aligned for the same reasons.
778 Align vectors to 128 bits. */
779 #define DATA_ALIGNMENT(TYPE, ALIGN) \
780 (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \
781 : TREE_CODE (TYPE) == ARRAY_TYPE \
782 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
783 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
785 /* Nonzero if move instructions will actually fail to work
786 when given unaligned data. */
787 #define STRICT_ALIGNMENT 0
789 /* Define this macro to be the value 1 if unaligned accesses have a cost
790 many times greater than aligned accesses, for example if they are
791 emulated in a trap handler. */
792 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
794 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
795 || (MODE) == DImode) \
798 /* Standard register usage. */
800 /* Number of actual hardware registers.
801 The hardware registers are assigned numbers for the compiler
802 from 0 to just below FIRST_PSEUDO_REGISTER.
803 All registers that the compiler knows about must be given numbers,
804 even those that are not normally considered general registers.
806 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
807 an MQ register, a count register, a link register, and 8 condition
808 register fields, which we view here as separate registers. AltiVec
809 adds 32 vector registers and a VRsave register.
811 In addition, the difference between the frame and argument pointers is
812 a function of the number of registers saved, so we need to have a
813 register for AP that will later be eliminated in favor of SP or FP.
814 This is a normal register, but it is fixed.
816 We also create a pseudo register for float/int conversions, that will
817 really represent the memory location used. It is represented here as
818 a register, in order to work around problems in allocating stack storage
819 in inline functions. */
821 #define FIRST_PSEUDO_REGISTER 113
823 /* This must be included for pre gcc 3.0 glibc compatibility. */
824 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
826 /* Add 32 dwarf columns for synthetic SPE registers. */
827 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 32)
829 /* The SPE has an additional 32 synthetic registers, with DWARF debug
830 info numbering for these registers starting at 1200. While eh_frame
831 register numbering need not be the same as the debug info numbering,
832 we choose to number these regs for eh_frame at 1200 too. This allows
833 future versions of the rs6000 backend to add hard registers and
834 continue to use the gcc hard register numbering for eh_frame. If the
835 extra SPE registers in eh_frame were numbered starting from the
836 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
837 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
838 avoid invalidating older SPE eh_frame info.
840 We must map them here to avoid huge unwinder tables mostly consisting
842 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
843 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER) : (r))
845 /* Use gcc hard register numbering for eh_frame. */
846 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
848 /* 1 for registers that have pervasive standard uses
849 and are not available for the register allocator.
851 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
852 as a local register; for all other OS's r2 is the TOC pointer.
854 cr5 is not supposed to be used.
856 On System V implementations, r13 is fixed and not available for use. */
858 #define FIXED_REGISTERS \
859 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
860 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
861 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
862 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
863 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
864 /* AltiVec registers. */ \
865 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
866 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
871 /* 1 for registers not available across function calls.
872 These must include the FIXED_REGISTERS and also any
873 registers that can be used without being saved.
874 The latter must include the registers where values are returned
875 and the register where structure-value addresses are passed.
876 Aside from that, you can include as many other registers as you like. */
878 #define CALL_USED_REGISTERS \
879 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
880 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
881 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
882 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
883 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
884 /* AltiVec registers. */ \
885 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
886 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
891 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
892 the entire set of `FIXED_REGISTERS' be included.
893 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
894 This macro is optional. If not specified, it defaults to the value
895 of `CALL_USED_REGISTERS'. */
897 #define CALL_REALLY_USED_REGISTERS \
898 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
899 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
900 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
901 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
902 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
903 /* AltiVec registers. */ \
904 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
905 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
916 #define MAX_CR_REGNO 75
918 #define FIRST_ALTIVEC_REGNO 77
919 #define LAST_ALTIVEC_REGNO 108
920 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
921 #define VRSAVE_REGNO 109
922 #define VSCR_REGNO 110
923 #define SPE_ACC_REGNO 111
924 #define SPEFSCR_REGNO 112
926 /* List the order in which to allocate registers. Each register must be
927 listed once, even those in FIXED_REGISTERS.
929 We allocate in the following order:
930 fp0 (not saved or used for anything)
931 fp13 - fp2 (not saved; incoming fp arg registers)
932 fp1 (not saved; return value)
933 fp31 - fp14 (saved; order given to save least number)
934 cr7, cr6 (not saved or special)
935 cr1 (not saved, but used for FP operations)
936 cr0 (not saved, but used for arithmetic operations)
937 cr4, cr3, cr2 (saved)
938 r0 (not saved; cannot be base reg)
939 r9 (not saved; best for TImode)
940 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
941 r3 (not saved; return value register)
942 r31 - r13 (saved; order given to save least number)
943 r12 (not saved; if used for DImode or DFmode would use r13)
944 mq (not saved; best to use it if we can)
945 ctr (not saved; when we have the choice ctr is better)
947 cr5, r1, r2, ap, xer, vrsave, vscr (fixed)
948 spe_acc, spefscr (fixed)
951 v0 - v1 (not saved or used for anything)
952 v13 - v3 (not saved; incoming vector arg registers)
953 v2 (not saved; incoming vector arg reg; return value)
954 v19 - v14 (not saved or used for anything)
955 v31 - v20 (saved; order given to save least number)
959 #define MAYBE_R2_AVAILABLE
960 #define MAYBE_R2_FIXED 2,
962 #define MAYBE_R2_AVAILABLE 2,
963 #define MAYBE_R2_FIXED
966 #define REG_ALLOC_ORDER \
968 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
970 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
971 50, 49, 48, 47, 46, \
972 75, 74, 69, 68, 72, 71, 70, \
973 0, MAYBE_R2_AVAILABLE \
974 9, 11, 10, 8, 7, 6, 5, 4, \
976 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
977 18, 17, 16, 15, 14, 13, 12, \
979 73, 1, MAYBE_R2_FIXED 67, 76, \
980 /* AltiVec registers. */ \
982 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
984 96, 95, 94, 93, 92, 91, \
985 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \
990 /* True if register is floating-point. */
991 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
993 /* True if register is a condition register. */
994 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
996 /* True if register is a condition register, but not cr0. */
997 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
999 /* True if register is an integer register. */
1000 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
1002 /* SPE SIMD registers are just the GPRs. */
1003 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
1005 /* True if register is the XER register. */
1006 #define XER_REGNO_P(N) ((N) == XER_REGNO)
1008 /* True if register is an AltiVec register. */
1009 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1011 /* Return number of consecutive hard regs needed starting at reg REGNO
1012 to hold something of mode MODE.
1013 This is ordinarily the length in words of a value of mode MODE
1014 but can be less for certain modes in special long registers.
1016 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1017 scalar instructions. The upper 32 bits are only available to the
1020 POWER and PowerPC GPRs hold 32 bits worth;
1021 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1023 #define HARD_REGNO_NREGS(REGNO, MODE) \
1024 (FP_REGNO_P (REGNO) \
1025 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1026 : (SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE)) \
1027 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD) \
1028 : ALTIVEC_REGNO_P (REGNO) \
1029 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \
1030 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1032 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1033 ((TARGET_32BIT && TARGET_POWERPC64 \
1034 && (MODE == DImode || MODE == DFmode) \
1035 && INT_REGNO_P (REGNO)) ? 1 : 0)
1037 #define ALTIVEC_VECTOR_MODE(MODE) \
1038 ((MODE) == V16QImode \
1039 || (MODE) == V8HImode \
1040 || (MODE) == V4SFmode \
1041 || (MODE) == V4SImode)
1043 #define SPE_VECTOR_MODE(MODE) \
1044 ((MODE) == V4HImode \
1045 || (MODE) == V2SFmode \
1046 || (MODE) == V1DImode \
1047 || (MODE) == V2SImode)
1049 /* Define this macro to be nonzero if the port is prepared to handle
1050 insns involving vector mode MODE. At the very least, it must have
1051 move patterns for this mode. */
1053 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1054 ((TARGET_SPE && SPE_VECTOR_MODE (MODE)) \
1055 || (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE)))
1057 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1058 For POWER and PowerPC, the GPRs can hold any mode, but values bigger
1059 than one register cannot go past R31. The float
1060 registers only can hold floating modes and DImode, and CR register only
1061 can hold CC modes. We cannot put TImode anywhere except general
1062 register and it must be able to fit within the register set. */
1064 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1065 (INT_REGNO_P (REGNO) ? \
1066 INT_REGNO_P (REGNO + HARD_REGNO_NREGS (REGNO, MODE) - 1) \
1067 : FP_REGNO_P (REGNO) ? \
1068 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1069 || (GET_MODE_CLASS (MODE) == MODE_INT \
1070 && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \
1071 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE) \
1072 : SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE) ? 1 \
1073 : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \
1074 : XER_REGNO_P (REGNO) ? (MODE) == PSImode \
1075 : GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
1077 /* Value is 1 if it is a good idea to tie two pseudo registers
1078 when one has mode MODE1 and one has mode MODE2.
1079 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1080 for any hard reg, then this must be 0 for correct output. */
1081 #define MODES_TIEABLE_P(MODE1, MODE2) \
1082 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
1083 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
1084 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
1085 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
1086 : GET_MODE_CLASS (MODE1) == MODE_CC \
1087 ? GET_MODE_CLASS (MODE2) == MODE_CC \
1088 : GET_MODE_CLASS (MODE2) == MODE_CC \
1089 ? GET_MODE_CLASS (MODE1) == MODE_CC \
1090 : SPE_VECTOR_MODE (MODE1) \
1091 ? SPE_VECTOR_MODE (MODE2) \
1092 : SPE_VECTOR_MODE (MODE2) \
1093 ? SPE_VECTOR_MODE (MODE1) \
1094 : ALTIVEC_VECTOR_MODE (MODE1) \
1095 ? ALTIVEC_VECTOR_MODE (MODE2) \
1096 : ALTIVEC_VECTOR_MODE (MODE2) \
1097 ? ALTIVEC_VECTOR_MODE (MODE1) \
1100 /* Post-reload, we can't use any new AltiVec registers, as we already
1101 emitted the vrsave mask. */
1103 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1104 (! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST])
1106 /* A C expression returning the cost of moving data from a register of class
1107 CLASS1 to one of CLASS2. */
1109 #define REGISTER_MOVE_COST rs6000_register_move_cost
1111 /* A C expressions returning the cost of moving data of MODE from a register to
1114 #define MEMORY_MOVE_COST rs6000_memory_move_cost
1116 /* Specify the cost of a branch insn; roughly the number of extra insns that
1117 should be added to avoid a branch.
1119 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1120 unscheduled conditional branch. */
1122 #define BRANCH_COST 3
1124 /* Override BRANCH_COST heuristic which empirically produces worse
1125 performance for fold_range_test(). */
1127 #define RANGE_TEST_NON_SHORT_CIRCUIT 0
1129 /* A fixed register used at prologue and epilogue generation to fix
1130 addressing modes. The SPE needs heavy addressing fixes at the last
1131 minute, and it's best to save a register for it.
1133 AltiVec also needs fixes, but we've gotten around using r11, which
1134 is actually wrong because when use_backchain_to_restore_sp is true,
1135 we end up clobbering r11.
1137 The AltiVec case needs to be fixed. Dunno if we should break ABI
1138 compatibility and reserve a register for it as well.. */
1140 #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11)
1142 /* Define this macro to change register usage conditional on target flags.
1143 Set MQ register fixed (already call_used) if not POWER architecture
1144 (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated.
1145 64-bit AIX reserves GPR13 for thread-private data.
1146 Conditionally disable FPRs. */
1148 #define CONDITIONAL_REGISTER_USAGE \
1151 if (! TARGET_POWER) \
1152 fixed_regs[64] = 1; \
1154 fixed_regs[13] = call_used_regs[13] \
1155 = call_really_used_regs[13] = 1; \
1156 if (TARGET_SOFT_FLOAT || !TARGET_FPRS) \
1157 for (i = 32; i < 64; i++) \
1158 fixed_regs[i] = call_used_regs[i] \
1159 = call_really_used_regs[i] = 1; \
1160 if (DEFAULT_ABI == ABI_V4 \
1161 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \
1163 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1164 if (DEFAULT_ABI == ABI_V4 \
1165 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \
1167 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1168 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1169 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1170 if (DEFAULT_ABI == ABI_DARWIN \
1171 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
1172 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1173 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1174 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1175 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1176 if (TARGET_ALTIVEC) \
1177 global_regs[VSCR_REGNO] = 1; \
1180 global_regs[SPEFSCR_REGNO] = 1; \
1181 fixed_regs[FIXED_SCRATCH] \
1182 = call_used_regs[FIXED_SCRATCH] \
1183 = call_really_used_regs[FIXED_SCRATCH] = 1; \
1185 if (! TARGET_ALTIVEC) \
1187 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \
1188 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; \
1189 call_really_used_regs[VRSAVE_REGNO] = 1; \
1191 if (TARGET_ALTIVEC_ABI) \
1192 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) \
1193 call_used_regs[i] = call_really_used_regs[i] = 1; \
1196 /* Specify the registers used for certain standard purposes.
1197 The values of these macros are register numbers. */
1199 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1200 /* #define PC_REGNUM */
1202 /* Register to use for pushing function arguments. */
1203 #define STACK_POINTER_REGNUM 1
1205 /* Base register for access to local variables of the function. */
1206 #define FRAME_POINTER_REGNUM 31
1208 /* Value should be nonzero if functions must have frame pointers.
1209 Zero means the frame pointer need not be set up (and parms
1210 may be accessed via the stack pointer) in functions that seem suitable.
1211 This is computed in `reload', in reload1.c. */
1212 #define FRAME_POINTER_REQUIRED 0
1214 /* Base register for access to arguments of the function. */
1215 #define ARG_POINTER_REGNUM 67
1217 /* Place to put static chain when calling a function that requires it. */
1218 #define STATIC_CHAIN_REGNUM 11
1220 /* Link register number. */
1221 #define LINK_REGISTER_REGNUM 65
1223 /* Count register number. */
1224 #define COUNT_REGISTER_REGNUM 66
1226 /* Define the classes of registers for register constraints in the
1227 machine description. Also define ranges of constants.
1229 One of the classes must always be named ALL_REGS and include all hard regs.
1230 If there is more than one class, another class must be named NO_REGS
1231 and contain no registers.
1233 The name GENERAL_REGS must be the name of a class (or an alias for
1234 another name such as ALL_REGS). This is the class of registers
1235 that is allowed by "g" or "r" in a register constraint.
1236 Also, registers outside this class are allocated only when
1237 instructions express preferences for them.
1239 The classes must be numbered in nondecreasing order; that is,
1240 a larger-numbered class must never be contained completely
1241 in a smaller-numbered class.
1243 For any two classes, it is very desirable that there be another
1244 class that represents their union. */
1246 /* The RS/6000 has three types of registers, fixed-point, floating-point,
1247 and condition registers, plus three special registers, MQ, CTR, and the
1248 link register. AltiVec adds a vector register class.
1250 However, r0 is special in that it cannot be used as a base register.
1251 So make a class for registers valid as base registers.
1253 Also, cr0 is the only condition code register that can be used in
1254 arithmetic insns, so make a separate class for it. */
1282 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1284 /* Give names of register classes as strings for dump file. */
1286 #define REG_CLASS_NAMES \
1297 "NON_SPECIAL_REGS", \
1301 "LINK_OR_CTR_REGS", \
1303 "SPEC_OR_GEN_REGS", \
1311 /* Define which registers fit in which classes.
1312 This is an initializer for a vector of HARD_REG_SET
1313 of length N_REG_CLASSES. */
1315 #define REG_CLASS_CONTENTS \
1317 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1318 { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \
1319 { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \
1320 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1321 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1322 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1323 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1324 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1325 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1326 { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
1327 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1328 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1329 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1330 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1331 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1332 { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
1333 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1334 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1335 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1336 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1337 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \
1340 /* The same information, inverted:
1341 Return the class number of the smallest class containing
1342 reg number REGNO. This could be a conditional expression
1343 or could index an array. */
1345 #define REGNO_REG_CLASS(REGNO) \
1346 ((REGNO) == 0 ? GENERAL_REGS \
1347 : (REGNO) < 32 ? BASE_REGS \
1348 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1349 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1350 : (REGNO) == CR0_REGNO ? CR0_REGS \
1351 : CR_REGNO_P (REGNO) ? CR_REGS \
1352 : (REGNO) == MQ_REGNO ? MQ_REGS \
1353 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1354 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1355 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1356 : (REGNO) == XER_REGNO ? XER_REGS \
1357 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1358 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1359 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
1360 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
1363 /* The class value for index registers, and the one for base regs. */
1364 #define INDEX_REG_CLASS GENERAL_REGS
1365 #define BASE_REG_CLASS BASE_REGS
1367 /* Get reg_class from a letter such as appears in the machine description. */
1369 #define REG_CLASS_FROM_LETTER(C) \
1370 ((C) == 'f' ? FLOAT_REGS \
1371 : (C) == 'b' ? BASE_REGS \
1372 : (C) == 'h' ? SPECIAL_REGS \
1373 : (C) == 'q' ? MQ_REGS \
1374 : (C) == 'c' ? CTR_REGS \
1375 : (C) == 'l' ? LINK_REGS \
1376 : (C) == 'v' ? ALTIVEC_REGS \
1377 : (C) == 'x' ? CR0_REGS \
1378 : (C) == 'y' ? CR_REGS \
1379 : (C) == 'z' ? XER_REGS \
1382 /* The letters I, J, K, L, M, N, and P in a register constraint string
1383 can be used to stand for particular ranges of immediate operands.
1384 This macro defines what the ranges are.
1385 C is the letter, and VALUE is a constant value.
1386 Return 1 if VALUE is in the range specified by C.
1388 `I' is a signed 16-bit constant
1389 `J' is a constant with only the high-order 16 bits nonzero
1390 `K' is a constant with only the low-order 16 bits nonzero
1391 `L' is a signed 16-bit constant shifted left 16 bits
1392 `M' is a constant that is greater than 31
1393 `N' is a positive constant that is an exact power of two
1394 `O' is the constant zero
1395 `P' is a constant whose negation is a signed 16-bit constant */
1397 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1398 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1399 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1400 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1401 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1402 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1403 : (C) == 'M' ? (VALUE) > 31 \
1404 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1405 : (C) == 'O' ? (VALUE) == 0 \
1406 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1409 /* Similar, but for floating constants, and defining letters G and H.
1410 Here VALUE is the CONST_DOUBLE rtx itself.
1412 We flag for special constants when we can copy the constant into
1413 a general register in two insns for DF/DI and one insn for SF.
1415 'H' is used for DI/DF constants that take 3 insns. */
1417 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1418 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1419 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1420 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1423 /* Optional extra constraints for this machine.
1425 'Q' means that is a memory operand that is just an offset from a reg.
1426 'R' is for AIX TOC entries.
1427 'S' is a constant that can be placed into a 64-bit mask operand
1428 'T' is a constant that can be placed into a 32-bit mask operand
1429 'U' is for V.4 small data references.
1430 'W' is a vector constant that can be easily generated (no mem refs).
1431 'Y' is a indexed or word-aligned displacement memory operand.
1432 't' is for AND masks that can be performed by two rldic{l,r} insns. */
1434 #define EXTRA_CONSTRAINT(OP, C) \
1435 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1436 : (C) == 'R' ? legitimate_constant_pool_address_p (OP) \
1437 : (C) == 'S' ? mask64_operand (OP, DImode) \
1438 : (C) == 'T' ? mask_operand (OP, SImode) \
1439 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
1440 && small_data_operand (OP, GET_MODE (OP))) \
1441 : (C) == 't' ? (mask64_2_operand (OP, DImode) \
1442 && (fixed_regs[CR0_REGNO] \
1443 || !logical_operand (OP, DImode)) \
1444 && !mask64_operand (OP, DImode)) \
1445 : (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP))) \
1446 : (C) == 'Y' ? (word_offset_memref_operand (OP, GET_MODE (OP))) \
1449 /* Define which constraints are memory constraints. Tell reload
1450 that any memory address can be reloaded by copying the
1451 memory address into a base register if required. */
1453 #define EXTRA_MEMORY_CONSTRAINT(C, STR) \
1454 ((C) == 'Q' || (C) == 'Y')
1456 /* Given an rtx X being reloaded into a reg required to be
1457 in class CLASS, return the class of reg to actually use.
1458 In general this is just CLASS; but on some machines
1459 in some cases it is preferable to use a more restrictive class.
1461 On the RS/6000, we have to return NO_REGS when we want to reload a
1462 floating-point CONST_DOUBLE to force it to be copied to memory.
1464 We also don't want to reload integer values into floating-point
1465 registers if we can at all help it. In fact, this can
1466 cause reload to abort, if it tries to generate a reload of CTR
1467 into a FP register and discovers it doesn't have the memory location
1470 ??? Would it be a good idea to have reload do the converse, that is
1471 try to reload floating modes into FP registers if possible?
1474 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1475 (((GET_CODE (X) == CONST_DOUBLE \
1476 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1478 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1479 && (CLASS) == NON_SPECIAL_REGS) \
1483 /* Return the register class of a scratch register needed to copy IN into
1484 or out of a register in CLASS in MODE. If it can be done directly,
1485 NO_REGS is returned. */
1487 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1488 secondary_reload_class (CLASS, MODE, IN)
1490 /* If we are copying between FP or AltiVec registers and anything
1491 else, we need a memory location. */
1493 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1494 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1495 || (CLASS2) == FLOAT_REGS \
1496 || (CLASS1) == ALTIVEC_REGS \
1497 || (CLASS2) == ALTIVEC_REGS))
1499 /* Return the maximum number of consecutive registers
1500 needed to represent mode MODE in a register of class CLASS.
1502 On RS/6000, this is the size of MODE in words,
1503 except in the FP regs, where a single reg is enough for two words. */
1504 #define CLASS_MAX_NREGS(CLASS, MODE) \
1505 (((CLASS) == FLOAT_REGS) \
1506 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1507 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1510 /* Return a class of registers that cannot change FROM mode to TO mode. */
1512 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1513 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) \
1514 && GET_MODE_SIZE (FROM) >= 8 && GET_MODE_SIZE (TO) >= 8) \
1516 : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1517 ? reg_classes_intersect_p (FLOAT_REGS, CLASS) \
1518 : (TARGET_SPE && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1) \
1519 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
1522 /* Stack layout; function entry, exit and calling. */
1524 /* Enumeration to give which calling sequence to use. */
1527 ABI_AIX, /* IBM's AIX */
1528 ABI_V4, /* System V.4/eabi */
1529 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1532 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1534 /* Define this if pushing a word on the stack
1535 makes the stack pointer a smaller address. */
1536 #define STACK_GROWS_DOWNWARD
1538 /* Define this if the nominal address of the stack frame
1539 is at the high-address end of the local variables;
1540 that is, each additional local variable allocated
1541 goes at a more negative offset in the frame.
1543 On the RS/6000, we grow upwards, from the area after the outgoing
1545 /* #define FRAME_GROWS_DOWNWARD */
1547 /* Size of the outgoing register save area */
1548 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1549 || DEFAULT_ABI == ABI_DARWIN) \
1550 ? (TARGET_64BIT ? 64 : 32) \
1553 /* Size of the fixed area on the stack */
1554 #define RS6000_SAVE_AREA \
1555 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1556 << (TARGET_64BIT ? 1 : 0))
1558 /* MEM representing address to save the TOC register */
1559 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1560 plus_constant (stack_pointer_rtx, \
1561 (TARGET_32BIT ? 20 : 40)))
1563 /* Size of the V.4 varargs area if needed */
1564 #define RS6000_VARARGS_AREA 0
1566 /* Align an address */
1567 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1569 /* Size of V.4 varargs area in bytes */
1570 #define RS6000_VARARGS_SIZE \
1571 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
1573 /* Offset within stack frame to start allocating local variables at.
1574 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1575 first local allocated. Otherwise, it is the offset to the BEGINNING
1576 of the first local allocated.
1578 On the RS/6000, the frame pointer is the same as the stack pointer,
1579 except for dynamic allocations. So we start after the fixed area and
1580 outgoing parameter area. */
1582 #define STARTING_FRAME_OFFSET \
1583 (RS6000_ALIGN (current_function_outgoing_args_size, \
1584 TARGET_ALTIVEC ? 16 : 8) \
1585 + RS6000_VARARGS_AREA \
1588 /* Offset from the stack pointer register to an item dynamically
1589 allocated on the stack, e.g., by `alloca'.
1591 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1592 length of the outgoing arguments. The default is correct for most
1593 machines. See `function.c' for details. */
1594 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1595 (RS6000_ALIGN (current_function_outgoing_args_size, \
1596 TARGET_ALTIVEC ? 16 : 8) \
1597 + (STACK_POINTER_OFFSET))
1599 /* If we generate an insn to push BYTES bytes,
1600 this says how many the stack pointer really advances by.
1601 On RS/6000, don't define this because there are no push insns. */
1602 /* #define PUSH_ROUNDING(BYTES) */
1604 /* Offset of first parameter from the argument pointer register value.
1605 On the RS/6000, we define the argument pointer to the start of the fixed
1607 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1609 /* Offset from the argument pointer register value to the top of
1610 stack. This is different from FIRST_PARM_OFFSET because of the
1611 register save area. */
1612 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1614 /* Define this if stack space is still allocated for a parameter passed
1615 in a register. The value is the number of bytes allocated to this
1617 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1619 /* Define this if the above stack space is to be considered part of the
1620 space allocated by the caller. */
1621 #define OUTGOING_REG_PARM_STACK_SPACE
1623 /* This is the difference between the logical top of stack and the actual sp.
1625 For the RS/6000, sp points past the fixed area. */
1626 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1628 /* Define this if the maximum size of all the outgoing args is to be
1629 accumulated and pushed during the prologue. The amount can be
1630 found in the variable current_function_outgoing_args_size. */
1631 #define ACCUMULATE_OUTGOING_ARGS 1
1633 /* Value is the number of bytes of arguments automatically
1634 popped when returning from a subroutine call.
1635 FUNDECL is the declaration node of the function (as a tree),
1636 FUNTYPE is the data type of the function (as a tree),
1637 or for a library call it is an identifier node for the subroutine name.
1638 SIZE is the number of bytes of arguments passed on the stack. */
1640 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1642 /* Define how to find the value returned by a function.
1643 VALTYPE is the data type of the value (as a tree).
1644 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1645 otherwise, FUNC is 0. */
1647 #define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC))
1649 /* Define how to find the value returned by a library function
1650 assuming the value has mode MODE. */
1652 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1654 /* DRAFT_V4_STRUCT_RET defaults off. */
1655 #define DRAFT_V4_STRUCT_RET 0
1657 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1658 #define DEFAULT_PCC_STRUCT_RETURN 0
1660 /* Mode of stack savearea.
1661 FUNCTION is VOIDmode because calling convention maintains SP.
1662 BLOCK needs Pmode for SP.
1663 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1664 #define STACK_SAVEAREA_MODE(LEVEL) \
1665 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1666 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1668 /* Minimum and maximum general purpose registers used to hold arguments. */
1669 #define GP_ARG_MIN_REG 3
1670 #define GP_ARG_MAX_REG 10
1671 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1673 /* Minimum and maximum floating point registers used to hold arguments. */
1674 #define FP_ARG_MIN_REG 33
1675 #define FP_ARG_AIX_MAX_REG 45
1676 #define FP_ARG_V4_MAX_REG 40
1677 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1678 || DEFAULT_ABI == ABI_DARWIN) \
1679 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1680 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1682 /* Minimum and maximum AltiVec registers used to hold arguments. */
1683 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1684 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1685 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1687 /* Return registers */
1688 #define GP_ARG_RETURN GP_ARG_MIN_REG
1689 #define FP_ARG_RETURN FP_ARG_MIN_REG
1690 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1692 /* Flags for the call/call_value rtl operations set up by function_arg */
1693 #define CALL_NORMAL 0x00000000 /* no special processing */
1694 /* Bits in 0x00000001 are unused. */
1695 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1696 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1697 #define CALL_LONG 0x00000008 /* always call indirect */
1698 #define CALL_LIBCALL 0x00000010 /* libcall */
1700 /* 1 if N is a possible register number for a function value
1701 as seen by the caller.
1703 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1704 #define FUNCTION_VALUE_REGNO_P(N) \
1705 ((N) == GP_ARG_RETURN \
1706 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT) \
1707 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC))
1709 /* 1 if N is a possible register number for function argument passing.
1710 On RS/6000, these are r3-r10 and fp1-fp13.
1711 On AltiVec, v2 - v13 are used for passing vectors. */
1712 #define FUNCTION_ARG_REGNO_P(N) \
1713 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1714 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1715 && TARGET_ALTIVEC) \
1716 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1717 && TARGET_HARD_FLOAT))
1719 /* A C structure for machine-specific, per-function data.
1720 This is added to the cfun structure. */
1721 typedef struct machine_function GTY(())
1723 /* Whether a System V.4 varargs area was created. */
1725 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
1726 int ra_needs_full_frame;
1727 /* Some local-dynamic symbol. */
1728 const char *some_ld_name;
1729 /* Whether the instruction chain has been scanned already. */
1730 int insn_chain_scanned_p;
1731 /* Flags if __builtin_return_address (0) was used. */
1735 /* Define a data type for recording info about an argument list
1736 during the scan of that argument list. This data type should
1737 hold all necessary information about the function itself
1738 and about the args processed so far, enough to enable macros
1739 such as FUNCTION_ARG to determine where the next arg should go.
1741 On the RS/6000, this is a structure. The first element is the number of
1742 total argument words, the second is used to store the next
1743 floating-point register number, and the third says how many more args we
1744 have prototype types for.
1746 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1747 the next available GP register, `fregno' is the next available FP
1748 register, and `words' is the number of words used on the stack.
1750 The varargs/stdarg support requires that this structure's size
1751 be a multiple of sizeof(int). */
1753 typedef struct rs6000_args
1755 int words; /* # words used for passing GP registers */
1756 int fregno; /* next available FP register */
1757 int vregno; /* next available AltiVec register */
1758 int nargs_prototype; /* # args left in the current prototype */
1759 int prototype; /* Whether a prototype was defined */
1760 int stdarg; /* Whether function is a stdarg function. */
1761 int call_cookie; /* Do special things for this call */
1762 int sysv_gregno; /* next available GP register */
1765 /* Define intermediate macro to compute the size (in registers) of an argument
1768 #define UNITS_PER_ARG (TARGET_32BIT ? 4 : 8)
1770 #define RS6000_ARG_SIZE(MODE, TYPE) \
1771 ((MODE) != BLKmode \
1772 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_ARG - 1)) / UNITS_PER_ARG \
1773 : (int_size_in_bytes (TYPE) + (UNITS_PER_ARG - 1)) / UNITS_PER_ARG)
1775 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1776 for a call to a function whose data type is FNTYPE.
1777 For a library call, FNTYPE is 0. */
1779 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1780 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
1782 /* Similar, but when scanning the definition of a procedure. We always
1783 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1785 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1786 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
1788 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1790 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1791 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
1793 /* Update the data in CUM to advance over an argument
1794 of mode MODE and data type TYPE.
1795 (TYPE is null for libcalls where that information may not be available.) */
1797 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1798 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1800 /* Determine where to put an argument to a function.
1801 Value is zero to push the argument on the stack,
1802 or a hard register in which to store the argument.
1804 MODE is the argument's machine mode.
1805 TYPE is the data type of the argument (as a tree).
1806 This is null for libcalls where that information may
1808 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1809 the preceding args and about the function being called.
1810 NAMED is nonzero if this argument is a named parameter
1811 (otherwise it is an extra parameter matching an ellipsis).
1813 On RS/6000 the first eight words of non-FP are normally in registers
1814 and the rest are pushed. The first 13 FP args are in registers.
1816 If this is floating-point and no prototype is specified, we use
1817 both an FP and integer register (or possibly FP reg and stack). Library
1818 functions (when TYPE is zero) always have the proper types for args,
1819 so we can pass the FP value just in one register. emit_library_function
1820 doesn't support EXPR_LIST anyway. */
1822 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1823 function_arg (&CUM, MODE, TYPE, NAMED)
1825 /* For an arg passed partly in registers and partly in memory,
1826 this is the number of registers used.
1827 For args passed entirely in registers or entirely in memory, zero. */
1829 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1830 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1832 /* A C expression that indicates when an argument must be passed by
1833 reference. If nonzero for an argument, a copy of that argument is
1834 made in memory and a pointer to the argument is passed instead of
1835 the argument itself. The pointer is passed in whatever way is
1836 appropriate for passing a pointer to that type. */
1838 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1839 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
1841 /* If defined, a C expression which determines whether, and in which
1842 direction, to pad out an argument with extra space. The value
1843 should be of type `enum direction': either `upward' to pad above
1844 the argument, `downward' to pad below, or `none' to inhibit
1847 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1849 /* If defined, a C expression that gives the alignment boundary, in bits,
1850 of an argument with the specified mode and type. If it is not defined,
1851 PARM_BOUNDARY is used for all arguments. */
1853 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1854 function_arg_boundary (MODE, TYPE)
1856 /* Implement `va_start' for varargs and stdarg. */
1857 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1858 rs6000_va_start (valist, nextarg)
1860 /* Implement `va_arg'. */
1861 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1862 rs6000_va_arg (valist, type)
1864 #define PAD_VARARGS_DOWN \
1865 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1867 /* Output assembler code to FILE to increment profiler label # LABELNO
1868 for profiling a function entry. */
1870 #define FUNCTION_PROFILER(FILE, LABELNO) \
1871 output_function_profiler ((FILE), (LABELNO));
1873 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1874 the stack pointer does not matter. No definition is equivalent to
1877 On the RS/6000, this is nonzero because we can restore the stack from
1878 its backpointer, which we maintain. */
1879 #define EXIT_IGNORE_STACK 1
1881 /* Define this macro as a C expression that is nonzero for registers
1882 that are used by the epilogue or the return' pattern. The stack
1883 and frame pointer registers are already be assumed to be used as
1886 #define EPILOGUE_USES(REGNO) \
1887 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1888 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1889 || (current_function_calls_eh_return \
1894 /* TRAMPOLINE_TEMPLATE deleted */
1896 /* Length in units of the trampoline for entering a nested function. */
1898 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1900 /* Emit RTL insns to initialize the variable parts of a trampoline.
1901 FNADDR is an RTX for the address of the function's pure code.
1902 CXT is an RTX for the static chain value for the function. */
1904 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1905 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1907 /* Definitions for __builtin_return_address and __builtin_frame_address.
1908 __builtin_return_address (0) should give link register (65), enable
1910 /* This should be uncommented, so that the link register is used, but
1911 currently this would result in unmatched insns and spilling fixed
1912 registers so we'll leave it for another day. When these problems are
1913 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1915 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1917 /* Number of bytes into the frame return addresses can be found. See
1918 rs6000_stack_info in rs6000.c for more information on how the different
1919 abi's store the return address. */
1920 #define RETURN_ADDRESS_OFFSET \
1921 ((DEFAULT_ABI == ABI_AIX \
1922 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
1923 (DEFAULT_ABI == ABI_V4) ? 4 : \
1924 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1926 /* The current return address is in link register (65). The return address
1927 of anything farther back is accessed normally at an offset of 8 from the
1929 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1930 (rs6000_return_addr (COUNT, FRAME))
1933 /* Definitions for register eliminations.
1935 We have two registers that can be eliminated on the RS/6000. First, the
1936 frame pointer register can often be eliminated in favor of the stack
1937 pointer register. Secondly, the argument pointer register can always be
1938 eliminated; it is replaced with either the stack or frame pointer.
1940 In addition, we use the elimination mechanism to see if r30 is needed
1941 Initially we assume that it isn't. If it is, we spill it. This is done
1942 by making it an eliminable register. We replace it with itself so that
1943 if it isn't needed, then existing uses won't be modified. */
1945 /* This is an array of structures. Each structure initializes one pair
1946 of eliminable registers. The "from" register number is given first,
1947 followed by "to". Eliminations of the same "from" register are listed
1948 in order of preference. */
1949 #define ELIMINABLE_REGS \
1950 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1951 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1952 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1953 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1955 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1956 Frame pointer elimination is automatically handled.
1958 For the RS/6000, if frame pointer elimination is being done, we would like
1959 to convert ap into fp, not sp.
1961 We need r30 if -mminimal-toc was specified, and there are constant pool
1964 #define CAN_ELIMINATE(FROM, TO) \
1965 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1966 ? ! frame_pointer_needed \
1967 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1968 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1971 /* Define the offset between two registers, one to be eliminated, and the other
1972 its replacement, at the start of a routine. */
1973 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1974 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1976 /* Addressing modes, and classification of registers for them. */
1978 #define HAVE_PRE_DECREMENT 1
1979 #define HAVE_PRE_INCREMENT 1
1981 /* Macros to check register numbers against specific register classes. */
1983 /* These assume that REGNO is a hard or pseudo reg number.
1984 They give nonzero only if REGNO is a hard reg of the suitable class
1985 or a pseudo reg currently allocated to a suitable hard reg.
1986 Since they use reg_renumber, they are safe only once reg_renumber
1987 has been allocated, which happens in local-alloc.c. */
1989 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1990 ((REGNO) < FIRST_PSEUDO_REGISTER \
1991 ? (REGNO) <= 31 || (REGNO) == 67 \
1992 : (reg_renumber[REGNO] >= 0 \
1993 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1995 #define REGNO_OK_FOR_BASE_P(REGNO) \
1996 ((REGNO) < FIRST_PSEUDO_REGISTER \
1997 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1998 : (reg_renumber[REGNO] > 0 \
1999 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
2001 /* Maximum number of registers that can appear in a valid memory address. */
2003 #define MAX_REGS_PER_ADDRESS 2
2005 /* Recognize any constant value that is a valid address. */
2007 #define CONSTANT_ADDRESS_P(X) \
2008 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2009 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
2010 || GET_CODE (X) == HIGH)
2012 /* Nonzero if the constant value X is a legitimate general operand.
2013 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2015 On the RS/6000, all integer constants are acceptable, most won't be valid
2016 for particular insns, though. Only easy FP constants are
2019 #define LEGITIMATE_CONSTANT_P(X) \
2020 (((GET_CODE (X) != CONST_DOUBLE \
2021 && GET_CODE (X) != CONST_VECTOR) \
2022 || GET_MODE (X) == VOIDmode \
2023 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
2024 || easy_fp_constant (X, GET_MODE (X)) \
2025 || easy_vector_constant (X, GET_MODE (X))) \
2026 && !rs6000_tls_referenced_p (X))
2028 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2029 and check its validity for a certain class.
2030 We have two alternate definitions for each of them.
2031 The usual definition accepts all pseudo regs; the other rejects
2032 them unless they have been allocated suitable hard regs.
2033 The symbol REG_OK_STRICT causes the latter definition to be used.
2035 Most source files want to accept pseudo regs in the hope that
2036 they will get allocated to the class that the insn wants them to be in.
2037 Source files for reload pass need to be strict.
2038 After reload, it makes no difference, since pseudo regs have
2039 been eliminated by then. */
2041 #ifdef REG_OK_STRICT
2042 # define REG_OK_STRICT_FLAG 1
2044 # define REG_OK_STRICT_FLAG 0
2047 /* Nonzero if X is a hard reg that can be used as an index
2048 or if it is a pseudo reg in the non-strict case. */
2049 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
2051 && (REGNO (X) <= 31 \
2052 || REGNO (X) == ARG_POINTER_REGNUM \
2053 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
2054 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
2056 /* Nonzero if X is a hard reg that can be used as a base reg
2057 or if it is a pseudo reg in the non-strict case. */
2058 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
2059 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
2061 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
2062 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
2064 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2065 that is a valid memory address for an instruction.
2066 The MODE argument is the machine mode for the MEM expression
2067 that wants to use this address.
2069 On the RS/6000, there are four valid address: a SYMBOL_REF that
2070 refers to a constant pool entry of an address (or the sum of it
2071 plus a constant), a short (16-bit signed) constant plus a register,
2072 the sum of two registers, or a register indirect, possibly with an
2073 auto-increment. For DFmode and DImode with a constant plus register,
2074 we must ensure that both words are addressable or PowerPC64 with offset
2077 For modes spanning multiple registers (DFmode in 32-bit GPRs,
2078 32-bit DImode, TImode), indexed addressing cannot be used because
2079 adjacent memory cells are accessed by adding word-sized offsets
2080 during assembly output. */
2082 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2083 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
2087 /* Try machine-dependent ways of modifying an illegitimate address
2088 to be legitimate. If we find one, return the new, valid address.
2089 This macro is used in only one place: `memory_address' in explow.c.
2091 OLDX is the address as it was before break_out_memory_refs was called.
2092 In some cases it is useful to look at this to decide what needs to be done.
2094 MODE and WIN are passed so that this macro can use
2095 GO_IF_LEGITIMATE_ADDRESS.
2097 It is always safe for this macro to do nothing. It exists to recognize
2098 opportunities to optimize the output.
2100 On RS/6000, first check for the sum of a register with a constant
2101 integer that is out of range. If so, generate code to add the
2102 constant with the low-order 16 bits masked to the register and force
2103 this result into another register (this can be done with `cau').
2104 Then generate an address of REG+(CONST&0xffff), allowing for the
2105 possibility of bit 16 being a one.
2107 Then check for the sum of a register and something not constant, try to
2108 load the other things into a register and return the sum. */
2110 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2111 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
2112 if (result != NULL_RTX) \
2119 /* Try a machine-dependent way of reloading an illegitimate address
2120 operand. If we find one, push the reload and jump to WIN. This
2121 macro is used in only one place: `find_reloads_address' in reload.c.
2123 Implemented on rs6000 by rs6000_legitimize_reload_address.
2124 Note that (X) is evaluated twice; this is safe in current usage. */
2126 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2129 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
2130 (int)(TYPE), (IND_LEVELS), &win); \
2135 /* Go to LABEL if ADDR (a legitimate address expression)
2136 has an effect that depends on the machine mode it is used for. */
2138 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2140 if (rs6000_mode_dependent_address (ADDR)) \
2144 /* The register number of the register used to address a table of
2145 static data addresses in memory. In some cases this register is
2146 defined by a processor's "application binary interface" (ABI).
2147 When this macro is defined, RTL is generated for this register
2148 once, as with the stack pointer and frame pointer registers. If
2149 this macro is not defined, it is up to the machine-dependent files
2150 to allocate such a register (if necessary). */
2152 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
2153 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
2155 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
2157 /* Define this macro if the register defined by
2158 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
2159 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
2161 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
2163 /* By generating position-independent code, when two different
2164 programs (A and B) share a common library (libC.a), the text of
2165 the library can be shared whether or not the library is linked at
2166 the same address for both programs. In some of these
2167 environments, position-independent code requires not only the use
2168 of different addressing modes, but also special code to enable the
2169 use of these addressing modes.
2171 The `FINALIZE_PIC' macro serves as a hook to emit these special
2172 codes once the function is being compiled into assembly code, but
2173 not before. (It is not done before, because in the case of
2174 compiling an inline function, it would lead to multiple PIC
2175 prologues being included in functions which used inline functions
2176 and were compiled to assembly language.) */
2178 /* #define FINALIZE_PIC */
2180 /* A C expression that is nonzero if X is a legitimate immediate
2181 operand on the target machine when generating position independent
2182 code. You can assume that X satisfies `CONSTANT_P', so you need
2183 not check this. You can also assume FLAG_PIC is true, so you need
2184 not check it either. You need not define this macro if all
2185 constants (including `SYMBOL_REF') can be immediate operands when
2186 generating position independent code. */
2188 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2190 /* Define this if some processing needs to be done immediately before
2191 emitting code for an insn. */
2193 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
2195 /* Specify the machine mode that this machine uses
2196 for the index in the tablejump instruction. */
2197 #define CASE_VECTOR_MODE SImode
2199 /* Define as C expression which evaluates to nonzero if the tablejump
2200 instruction expects the table to contain offsets from the address of the
2202 Do not define this if the table should contain absolute addresses. */
2203 #define CASE_VECTOR_PC_RELATIVE 1
2205 /* Define this as 1 if `char' should by default be signed; else as 0. */
2206 #define DEFAULT_SIGNED_CHAR 0
2208 /* This flag, if defined, says the same insns that convert to a signed fixnum
2209 also convert validly to an unsigned one. */
2211 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
2213 /* Max number of bytes we can move from memory to memory
2214 in one reasonably fast instruction. */
2215 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2216 #define MAX_MOVE_MAX 8
2218 /* Nonzero if access to memory by bytes is no faster than for words.
2219 Also nonzero if doing byte operations (specifically shifts) in registers
2221 #define SLOW_BYTE_ACCESS 1
2223 /* Define if operations between registers always perform the operation
2224 on the full register even if a narrower mode is specified. */
2225 #define WORD_REGISTER_OPERATIONS
2227 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2228 will either zero-extend or sign-extend. The value of this macro should
2229 be the code that says which one of the two operations is implicitly
2230 done, NIL if none. */
2231 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2233 /* Define if loading short immediate values into registers sign extends. */
2234 #define SHORT_IMMEDIATES_SIGN_EXTEND
2236 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2237 is done just by pretending it is already truncated. */
2238 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2240 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
2241 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2242 ((VALUE) = ((MODE) == SImode ? 32 : 64))
2244 /* The CTZ patterns return -1 for input of zero. */
2245 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1)
2247 /* Specify the machine mode that pointers have.
2248 After generation of rtl, the compiler makes no further distinction
2249 between pointers and any other objects of this machine mode. */
2250 #define Pmode (TARGET_32BIT ? SImode : DImode)
2252 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
2253 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
2255 /* Mode of a function address in a call instruction (for indexing purposes).
2256 Doesn't matter on RS/6000. */
2257 #define FUNCTION_MODE SImode
2259 /* Define this if addresses of constant functions
2260 shouldn't be put through pseudo regs where they can be cse'd.
2261 Desirable on machines where ordinary constants are expensive
2262 but a CALL with constant address is cheap. */
2263 #define NO_FUNCTION_CSE
2265 /* Define this to be nonzero if shift instructions ignore all but the low-order
2268 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2269 have been dropped from the PowerPC architecture. */
2271 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2273 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2274 should be adjusted to reflect any required changes. This macro is used when
2275 there is some systematic length adjustment required that would be difficult
2276 to express in the length attribute. */
2278 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2280 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2281 COMPARE, return the mode to be used for the comparison. For
2282 floating-point, CCFPmode should be used. CCUNSmode should be used
2283 for unsigned comparisons. CCEQmode should be used when we are
2284 doing an inequality comparison on the result of a
2285 comparison. CCmode should be used in all other cases. */
2287 #define SELECT_CC_MODE(OP,X,Y) \
2288 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2289 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2290 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
2291 ? CCEQmode : CCmode))
2293 /* Can the condition code MODE be safely reversed? This is safe in
2294 all cases on this port, because at present it doesn't use the
2295 trapping FP comparisons (fcmpo). */
2296 #define REVERSIBLE_CC_MODE(MODE) 1
2298 /* Given a condition code and a mode, return the inverse condition. */
2299 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
2301 /* Define the information needed to generate branch and scc insns. This is
2302 stored from the compare operation. */
2304 extern GTY(()) rtx rs6000_compare_op0;
2305 extern GTY(()) rtx rs6000_compare_op1;
2306 extern int rs6000_compare_fp_p;
2308 /* Control the assembler format that we output. */
2310 /* A C string constant describing how to begin a comment in the target
2311 assembler language. The compiler assumes that the comment will end at
2312 the end of the line. */
2313 #define ASM_COMMENT_START " #"
2315 /* Implicit library calls should use memcpy, not bcopy, etc. */
2317 #define TARGET_MEM_FUNCTIONS
2319 /* Flag to say the TOC is initialized */
2320 extern int toc_initialized;
2322 /* Macro to output a special constant pool entry. Go to WIN if we output
2323 it. Otherwise, it is written the usual way.
2325 On the RS/6000, toc entries are handled this way. */
2327 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2328 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2330 output_toc (FILE, X, LABELNO, MODE); \
2335 #ifdef HAVE_GAS_WEAK
2336 #define RS6000_WEAK 1
2338 #define RS6000_WEAK 0
2342 /* Used in lieu of ASM_WEAKEN_LABEL. */
2343 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2346 fputs ("\t.weak\t", (FILE)); \
2347 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2348 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2349 && DEFAULT_ABI == ABI_AIX) \
2352 fputs ("[DS]", (FILE)); \
2353 fputs ("\n\t.weak\t.", (FILE)); \
2354 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2356 fputc ('\n', (FILE)); \
2359 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2360 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2361 && DEFAULT_ABI == ABI_AIX) \
2363 fputs ("\t.set\t.", (FILE)); \
2364 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2365 fputs (",.", (FILE)); \
2366 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2367 fputc ('\n', (FILE)); \
2374 /* This implements the `alias' attribute. */
2375 #undef ASM_OUTPUT_DEF_FROM_DECLS
2376 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2379 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2380 const char *name = IDENTIFIER_POINTER (TARGET); \
2381 if (TREE_CODE (DECL) == FUNCTION_DECL \
2382 && DEFAULT_ABI == ABI_AIX) \
2384 if (TREE_PUBLIC (DECL)) \
2386 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2388 fputs ("\t.globl\t.", FILE); \
2389 RS6000_OUTPUT_BASENAME (FILE, alias); \
2390 putc ('\n', FILE); \
2393 else if (TARGET_XCOFF) \
2395 fputs ("\t.lglobl\t.", FILE); \
2396 RS6000_OUTPUT_BASENAME (FILE, alias); \
2397 putc ('\n', FILE); \
2399 fputs ("\t.set\t.", FILE); \
2400 RS6000_OUTPUT_BASENAME (FILE, alias); \
2401 fputs (",.", FILE); \
2402 RS6000_OUTPUT_BASENAME (FILE, name); \
2403 fputc ('\n', FILE); \
2405 ASM_OUTPUT_DEF (FILE, alias, name); \
2409 #define TARGET_ASM_FILE_START rs6000_file_start
2411 /* Output to assembler file text saying following lines
2412 may contain character constants, extra white space, comments, etc. */
2414 #define ASM_APP_ON ""
2416 /* Output to assembler file text saying following lines
2417 no longer contain unusual constructs. */
2419 #define ASM_APP_OFF ""
2421 /* How to refer to registers in assembler output.
2422 This sequence is indexed by compiler's hard-register-number (see above). */
2424 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2426 #define REGISTER_NAMES \
2428 &rs6000_reg_names[ 0][0], /* r0 */ \
2429 &rs6000_reg_names[ 1][0], /* r1 */ \
2430 &rs6000_reg_names[ 2][0], /* r2 */ \
2431 &rs6000_reg_names[ 3][0], /* r3 */ \
2432 &rs6000_reg_names[ 4][0], /* r4 */ \
2433 &rs6000_reg_names[ 5][0], /* r5 */ \
2434 &rs6000_reg_names[ 6][0], /* r6 */ \
2435 &rs6000_reg_names[ 7][0], /* r7 */ \
2436 &rs6000_reg_names[ 8][0], /* r8 */ \
2437 &rs6000_reg_names[ 9][0], /* r9 */ \
2438 &rs6000_reg_names[10][0], /* r10 */ \
2439 &rs6000_reg_names[11][0], /* r11 */ \
2440 &rs6000_reg_names[12][0], /* r12 */ \
2441 &rs6000_reg_names[13][0], /* r13 */ \
2442 &rs6000_reg_names[14][0], /* r14 */ \
2443 &rs6000_reg_names[15][0], /* r15 */ \
2444 &rs6000_reg_names[16][0], /* r16 */ \
2445 &rs6000_reg_names[17][0], /* r17 */ \
2446 &rs6000_reg_names[18][0], /* r18 */ \
2447 &rs6000_reg_names[19][0], /* r19 */ \
2448 &rs6000_reg_names[20][0], /* r20 */ \
2449 &rs6000_reg_names[21][0], /* r21 */ \
2450 &rs6000_reg_names[22][0], /* r22 */ \
2451 &rs6000_reg_names[23][0], /* r23 */ \
2452 &rs6000_reg_names[24][0], /* r24 */ \
2453 &rs6000_reg_names[25][0], /* r25 */ \
2454 &rs6000_reg_names[26][0], /* r26 */ \
2455 &rs6000_reg_names[27][0], /* r27 */ \
2456 &rs6000_reg_names[28][0], /* r28 */ \
2457 &rs6000_reg_names[29][0], /* r29 */ \
2458 &rs6000_reg_names[30][0], /* r30 */ \
2459 &rs6000_reg_names[31][0], /* r31 */ \
2461 &rs6000_reg_names[32][0], /* fr0 */ \
2462 &rs6000_reg_names[33][0], /* fr1 */ \
2463 &rs6000_reg_names[34][0], /* fr2 */ \
2464 &rs6000_reg_names[35][0], /* fr3 */ \
2465 &rs6000_reg_names[36][0], /* fr4 */ \
2466 &rs6000_reg_names[37][0], /* fr5 */ \
2467 &rs6000_reg_names[38][0], /* fr6 */ \
2468 &rs6000_reg_names[39][0], /* fr7 */ \
2469 &rs6000_reg_names[40][0], /* fr8 */ \
2470 &rs6000_reg_names[41][0], /* fr9 */ \
2471 &rs6000_reg_names[42][0], /* fr10 */ \
2472 &rs6000_reg_names[43][0], /* fr11 */ \
2473 &rs6000_reg_names[44][0], /* fr12 */ \
2474 &rs6000_reg_names[45][0], /* fr13 */ \
2475 &rs6000_reg_names[46][0], /* fr14 */ \
2476 &rs6000_reg_names[47][0], /* fr15 */ \
2477 &rs6000_reg_names[48][0], /* fr16 */ \
2478 &rs6000_reg_names[49][0], /* fr17 */ \
2479 &rs6000_reg_names[50][0], /* fr18 */ \
2480 &rs6000_reg_names[51][0], /* fr19 */ \
2481 &rs6000_reg_names[52][0], /* fr20 */ \
2482 &rs6000_reg_names[53][0], /* fr21 */ \
2483 &rs6000_reg_names[54][0], /* fr22 */ \
2484 &rs6000_reg_names[55][0], /* fr23 */ \
2485 &rs6000_reg_names[56][0], /* fr24 */ \
2486 &rs6000_reg_names[57][0], /* fr25 */ \
2487 &rs6000_reg_names[58][0], /* fr26 */ \
2488 &rs6000_reg_names[59][0], /* fr27 */ \
2489 &rs6000_reg_names[60][0], /* fr28 */ \
2490 &rs6000_reg_names[61][0], /* fr29 */ \
2491 &rs6000_reg_names[62][0], /* fr30 */ \
2492 &rs6000_reg_names[63][0], /* fr31 */ \
2494 &rs6000_reg_names[64][0], /* mq */ \
2495 &rs6000_reg_names[65][0], /* lr */ \
2496 &rs6000_reg_names[66][0], /* ctr */ \
2497 &rs6000_reg_names[67][0], /* ap */ \
2499 &rs6000_reg_names[68][0], /* cr0 */ \
2500 &rs6000_reg_names[69][0], /* cr1 */ \
2501 &rs6000_reg_names[70][0], /* cr2 */ \
2502 &rs6000_reg_names[71][0], /* cr3 */ \
2503 &rs6000_reg_names[72][0], /* cr4 */ \
2504 &rs6000_reg_names[73][0], /* cr5 */ \
2505 &rs6000_reg_names[74][0], /* cr6 */ \
2506 &rs6000_reg_names[75][0], /* cr7 */ \
2508 &rs6000_reg_names[76][0], /* xer */ \
2510 &rs6000_reg_names[77][0], /* v0 */ \
2511 &rs6000_reg_names[78][0], /* v1 */ \
2512 &rs6000_reg_names[79][0], /* v2 */ \
2513 &rs6000_reg_names[80][0], /* v3 */ \
2514 &rs6000_reg_names[81][0], /* v4 */ \
2515 &rs6000_reg_names[82][0], /* v5 */ \
2516 &rs6000_reg_names[83][0], /* v6 */ \
2517 &rs6000_reg_names[84][0], /* v7 */ \
2518 &rs6000_reg_names[85][0], /* v8 */ \
2519 &rs6000_reg_names[86][0], /* v9 */ \
2520 &rs6000_reg_names[87][0], /* v10 */ \
2521 &rs6000_reg_names[88][0], /* v11 */ \
2522 &rs6000_reg_names[89][0], /* v12 */ \
2523 &rs6000_reg_names[90][0], /* v13 */ \
2524 &rs6000_reg_names[91][0], /* v14 */ \
2525 &rs6000_reg_names[92][0], /* v15 */ \
2526 &rs6000_reg_names[93][0], /* v16 */ \
2527 &rs6000_reg_names[94][0], /* v17 */ \
2528 &rs6000_reg_names[95][0], /* v18 */ \
2529 &rs6000_reg_names[96][0], /* v19 */ \
2530 &rs6000_reg_names[97][0], /* v20 */ \
2531 &rs6000_reg_names[98][0], /* v21 */ \
2532 &rs6000_reg_names[99][0], /* v22 */ \
2533 &rs6000_reg_names[100][0], /* v23 */ \
2534 &rs6000_reg_names[101][0], /* v24 */ \
2535 &rs6000_reg_names[102][0], /* v25 */ \
2536 &rs6000_reg_names[103][0], /* v26 */ \
2537 &rs6000_reg_names[104][0], /* v27 */ \
2538 &rs6000_reg_names[105][0], /* v28 */ \
2539 &rs6000_reg_names[106][0], /* v29 */ \
2540 &rs6000_reg_names[107][0], /* v30 */ \
2541 &rs6000_reg_names[108][0], /* v31 */ \
2542 &rs6000_reg_names[109][0], /* vrsave */ \
2543 &rs6000_reg_names[110][0], /* vscr */ \
2544 &rs6000_reg_names[111][0], /* spe_acc */ \
2545 &rs6000_reg_names[112][0], /* spefscr */ \
2548 /* Table of additional register names to use in user input. */
2550 #define ADDITIONAL_REGISTER_NAMES \
2551 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2552 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2553 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2554 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2555 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2556 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2557 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2558 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2559 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2560 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2561 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2562 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2563 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2564 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2565 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2566 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2567 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2568 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2569 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2570 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2571 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2572 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2573 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2574 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2575 {"vrsave", 109}, {"vscr", 110}, \
2576 {"spe_acc", 111}, {"spefscr", 112}, \
2577 /* no additional names for: mq, lr, ctr, ap */ \
2578 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2579 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2580 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2582 /* Text to write out after a CALL that may be replaced by glue code by
2583 the loader. This depends on the AIX version. */
2584 #define RS6000_CALL_GLUE "cror 31,31,31"
2586 /* This is how to output an element of a case-vector that is relative. */
2588 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2589 do { char buf[100]; \
2590 fputs ("\t.long ", FILE); \
2591 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2592 assemble_name (FILE, buf); \
2594 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2595 assemble_name (FILE, buf); \
2596 putc ('\n', FILE); \
2599 /* This is how to output an assembler line
2600 that says to advance the location counter
2601 to a multiple of 2**LOG bytes. */
2603 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2605 fprintf (FILE, "\t.align %d\n", (LOG))
2607 /* Pick up the return address upon entry to a procedure. Used for
2608 dwarf2 unwind information. This also enables the table driven
2611 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2612 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2614 /* Describe how we implement __builtin_eh_return. */
2615 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2616 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2618 /* Print operand X (an rtx) in assembler syntax to file FILE.
2619 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2620 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2622 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2624 /* Define which CODE values are valid. */
2626 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2627 ((CODE) == '.' || (CODE) == '&')
2629 /* Print a memory address as an operand to reference that memory location. */
2631 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2633 /* Define the codes that are matched by predicates in rs6000.c. */
2635 #define PREDICATE_CODES \
2636 {"any_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2637 LABEL_REF, SUBREG, REG, MEM, PARALLEL}}, \
2638 {"zero_constant", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2639 LABEL_REF, SUBREG, REG, MEM}}, \
2640 {"short_cint_operand", {CONST_INT}}, \
2641 {"u_short_cint_operand", {CONST_INT}}, \
2642 {"non_short_cint_operand", {CONST_INT}}, \
2643 {"exact_log2_cint_operand", {CONST_INT}}, \
2644 {"gpc_reg_operand", {SUBREG, REG}}, \
2645 {"cc_reg_operand", {SUBREG, REG}}, \
2646 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
2647 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
2648 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
2649 {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \
2650 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
2651 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2652 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
2653 {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2654 {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2655 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2656 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2657 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
2658 {"easy_fp_constant", {CONST_DOUBLE}}, \
2659 {"easy_vector_constant", {CONST_VECTOR}}, \
2660 {"easy_vector_constant_add_self", {CONST_VECTOR}}, \
2661 {"zero_fp_constant", {CONST_DOUBLE}}, \
2662 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
2663 {"lwa_operand", {SUBREG, MEM, REG}}, \
2664 {"volatile_mem_operand", {MEM}}, \
2665 {"offsettable_mem_operand", {MEM}}, \
2666 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
2667 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2668 {"non_add_cint_operand", {CONST_INT}}, \
2669 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2670 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2671 {"and64_2_operand", {SUBREG, REG, CONST_INT}}, \
2672 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2673 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
2674 {"mask_operand", {CONST_INT}}, \
2675 {"mask_operand_wrap", {CONST_INT}}, \
2676 {"mask64_operand", {CONST_INT}}, \
2677 {"mask64_2_operand", {CONST_INT}}, \
2678 {"count_register_operand", {REG}}, \
2679 {"xer_operand", {REG}}, \
2680 {"symbol_ref_operand", {SYMBOL_REF}}, \
2681 {"rs6000_tls_symbol_ref", {SYMBOL_REF}}, \
2682 {"call_operand", {SYMBOL_REF, REG}}, \
2683 {"current_file_function_operand", {SYMBOL_REF}}, \
2684 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \
2685 CONST_DOUBLE, SYMBOL_REF}}, \
2686 {"load_multiple_operation", {PARALLEL}}, \
2687 {"store_multiple_operation", {PARALLEL}}, \
2688 {"vrsave_operation", {PARALLEL}}, \
2689 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
2690 GT, LEU, LTU, GEU, GTU, \
2691 UNORDERED, ORDERED, \
2693 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \
2695 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
2696 GT, LEU, LTU, GEU, GTU, \
2697 UNORDERED, ORDERED, \
2699 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
2700 GT, LEU, LTU, GEU, GTU}}, \
2701 {"boolean_operator", {AND, IOR, XOR}}, \
2702 {"boolean_or_operator", {IOR, XOR}}, \
2703 {"altivec_register_operand", {REG}}, \
2704 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
2706 /* uncomment for disabling the corresponding default options */
2707 /* #define MACHINE_no_sched_interblock */
2708 /* #define MACHINE_no_sched_speculative */
2709 /* #define MACHINE_no_sched_speculative_load */
2711 /* General flags. */
2712 extern int flag_pic;
2713 extern int optimize;
2714 extern int flag_expensive_optimizations;
2715 extern int frame_pointer_needed;
2717 enum rs6000_builtins
2719 /* AltiVec builtins. */
2720 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2721 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2722 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2723 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2724 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2725 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2726 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2727 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2728 ALTIVEC_BUILTIN_VADDUBM,
2729 ALTIVEC_BUILTIN_VADDUHM,
2730 ALTIVEC_BUILTIN_VADDUWM,
2731 ALTIVEC_BUILTIN_VADDFP,
2732 ALTIVEC_BUILTIN_VADDCUW,
2733 ALTIVEC_BUILTIN_VADDUBS,
2734 ALTIVEC_BUILTIN_VADDSBS,
2735 ALTIVEC_BUILTIN_VADDUHS,
2736 ALTIVEC_BUILTIN_VADDSHS,
2737 ALTIVEC_BUILTIN_VADDUWS,
2738 ALTIVEC_BUILTIN_VADDSWS,
2739 ALTIVEC_BUILTIN_VAND,
2740 ALTIVEC_BUILTIN_VANDC,
2741 ALTIVEC_BUILTIN_VAVGUB,
2742 ALTIVEC_BUILTIN_VAVGSB,
2743 ALTIVEC_BUILTIN_VAVGUH,
2744 ALTIVEC_BUILTIN_VAVGSH,
2745 ALTIVEC_BUILTIN_VAVGUW,
2746 ALTIVEC_BUILTIN_VAVGSW,
2747 ALTIVEC_BUILTIN_VCFUX,
2748 ALTIVEC_BUILTIN_VCFSX,
2749 ALTIVEC_BUILTIN_VCTSXS,
2750 ALTIVEC_BUILTIN_VCTUXS,
2751 ALTIVEC_BUILTIN_VCMPBFP,
2752 ALTIVEC_BUILTIN_VCMPEQUB,
2753 ALTIVEC_BUILTIN_VCMPEQUH,
2754 ALTIVEC_BUILTIN_VCMPEQUW,
2755 ALTIVEC_BUILTIN_VCMPEQFP,
2756 ALTIVEC_BUILTIN_VCMPGEFP,
2757 ALTIVEC_BUILTIN_VCMPGTUB,
2758 ALTIVEC_BUILTIN_VCMPGTSB,
2759 ALTIVEC_BUILTIN_VCMPGTUH,
2760 ALTIVEC_BUILTIN_VCMPGTSH,
2761 ALTIVEC_BUILTIN_VCMPGTUW,
2762 ALTIVEC_BUILTIN_VCMPGTSW,
2763 ALTIVEC_BUILTIN_VCMPGTFP,
2764 ALTIVEC_BUILTIN_VEXPTEFP,
2765 ALTIVEC_BUILTIN_VLOGEFP,
2766 ALTIVEC_BUILTIN_VMADDFP,
2767 ALTIVEC_BUILTIN_VMAXUB,
2768 ALTIVEC_BUILTIN_VMAXSB,
2769 ALTIVEC_BUILTIN_VMAXUH,
2770 ALTIVEC_BUILTIN_VMAXSH,
2771 ALTIVEC_BUILTIN_VMAXUW,
2772 ALTIVEC_BUILTIN_VMAXSW,
2773 ALTIVEC_BUILTIN_VMAXFP,
2774 ALTIVEC_BUILTIN_VMHADDSHS,
2775 ALTIVEC_BUILTIN_VMHRADDSHS,
2776 ALTIVEC_BUILTIN_VMLADDUHM,
2777 ALTIVEC_BUILTIN_VMRGHB,
2778 ALTIVEC_BUILTIN_VMRGHH,
2779 ALTIVEC_BUILTIN_VMRGHW,
2780 ALTIVEC_BUILTIN_VMRGLB,
2781 ALTIVEC_BUILTIN_VMRGLH,
2782 ALTIVEC_BUILTIN_VMRGLW,
2783 ALTIVEC_BUILTIN_VMSUMUBM,
2784 ALTIVEC_BUILTIN_VMSUMMBM,
2785 ALTIVEC_BUILTIN_VMSUMUHM,
2786 ALTIVEC_BUILTIN_VMSUMSHM,
2787 ALTIVEC_BUILTIN_VMSUMUHS,
2788 ALTIVEC_BUILTIN_VMSUMSHS,
2789 ALTIVEC_BUILTIN_VMINUB,
2790 ALTIVEC_BUILTIN_VMINSB,
2791 ALTIVEC_BUILTIN_VMINUH,
2792 ALTIVEC_BUILTIN_VMINSH,
2793 ALTIVEC_BUILTIN_VMINUW,
2794 ALTIVEC_BUILTIN_VMINSW,
2795 ALTIVEC_BUILTIN_VMINFP,
2796 ALTIVEC_BUILTIN_VMULEUB,
2797 ALTIVEC_BUILTIN_VMULESB,
2798 ALTIVEC_BUILTIN_VMULEUH,
2799 ALTIVEC_BUILTIN_VMULESH,
2800 ALTIVEC_BUILTIN_VMULOUB,
2801 ALTIVEC_BUILTIN_VMULOSB,
2802 ALTIVEC_BUILTIN_VMULOUH,
2803 ALTIVEC_BUILTIN_VMULOSH,
2804 ALTIVEC_BUILTIN_VNMSUBFP,
2805 ALTIVEC_BUILTIN_VNOR,
2806 ALTIVEC_BUILTIN_VOR,
2807 ALTIVEC_BUILTIN_VSEL_4SI,
2808 ALTIVEC_BUILTIN_VSEL_4SF,
2809 ALTIVEC_BUILTIN_VSEL_8HI,
2810 ALTIVEC_BUILTIN_VSEL_16QI,
2811 ALTIVEC_BUILTIN_VPERM_4SI,
2812 ALTIVEC_BUILTIN_VPERM_4SF,
2813 ALTIVEC_BUILTIN_VPERM_8HI,
2814 ALTIVEC_BUILTIN_VPERM_16QI,
2815 ALTIVEC_BUILTIN_VPKUHUM,
2816 ALTIVEC_BUILTIN_VPKUWUM,
2817 ALTIVEC_BUILTIN_VPKPX,
2818 ALTIVEC_BUILTIN_VPKUHSS,
2819 ALTIVEC_BUILTIN_VPKSHSS,
2820 ALTIVEC_BUILTIN_VPKUWSS,
2821 ALTIVEC_BUILTIN_VPKSWSS,
2822 ALTIVEC_BUILTIN_VPKUHUS,
2823 ALTIVEC_BUILTIN_VPKSHUS,
2824 ALTIVEC_BUILTIN_VPKUWUS,
2825 ALTIVEC_BUILTIN_VPKSWUS,
2826 ALTIVEC_BUILTIN_VREFP,
2827 ALTIVEC_BUILTIN_VRFIM,
2828 ALTIVEC_BUILTIN_VRFIN,
2829 ALTIVEC_BUILTIN_VRFIP,
2830 ALTIVEC_BUILTIN_VRFIZ,
2831 ALTIVEC_BUILTIN_VRLB,
2832 ALTIVEC_BUILTIN_VRLH,
2833 ALTIVEC_BUILTIN_VRLW,
2834 ALTIVEC_BUILTIN_VRSQRTEFP,
2835 ALTIVEC_BUILTIN_VSLB,
2836 ALTIVEC_BUILTIN_VSLH,
2837 ALTIVEC_BUILTIN_VSLW,
2838 ALTIVEC_BUILTIN_VSL,
2839 ALTIVEC_BUILTIN_VSLO,
2840 ALTIVEC_BUILTIN_VSPLTB,
2841 ALTIVEC_BUILTIN_VSPLTH,
2842 ALTIVEC_BUILTIN_VSPLTW,
2843 ALTIVEC_BUILTIN_VSPLTISB,
2844 ALTIVEC_BUILTIN_VSPLTISH,
2845 ALTIVEC_BUILTIN_VSPLTISW,
2846 ALTIVEC_BUILTIN_VSRB,
2847 ALTIVEC_BUILTIN_VSRH,
2848 ALTIVEC_BUILTIN_VSRW,
2849 ALTIVEC_BUILTIN_VSRAB,
2850 ALTIVEC_BUILTIN_VSRAH,
2851 ALTIVEC_BUILTIN_VSRAW,
2852 ALTIVEC_BUILTIN_VSR,
2853 ALTIVEC_BUILTIN_VSRO,
2854 ALTIVEC_BUILTIN_VSUBUBM,
2855 ALTIVEC_BUILTIN_VSUBUHM,
2856 ALTIVEC_BUILTIN_VSUBUWM,
2857 ALTIVEC_BUILTIN_VSUBFP,
2858 ALTIVEC_BUILTIN_VSUBCUW,
2859 ALTIVEC_BUILTIN_VSUBUBS,
2860 ALTIVEC_BUILTIN_VSUBSBS,
2861 ALTIVEC_BUILTIN_VSUBUHS,
2862 ALTIVEC_BUILTIN_VSUBSHS,
2863 ALTIVEC_BUILTIN_VSUBUWS,
2864 ALTIVEC_BUILTIN_VSUBSWS,
2865 ALTIVEC_BUILTIN_VSUM4UBS,
2866 ALTIVEC_BUILTIN_VSUM4SBS,
2867 ALTIVEC_BUILTIN_VSUM4SHS,
2868 ALTIVEC_BUILTIN_VSUM2SWS,
2869 ALTIVEC_BUILTIN_VSUMSWS,
2870 ALTIVEC_BUILTIN_VXOR,
2871 ALTIVEC_BUILTIN_VSLDOI_16QI,
2872 ALTIVEC_BUILTIN_VSLDOI_8HI,
2873 ALTIVEC_BUILTIN_VSLDOI_4SI,
2874 ALTIVEC_BUILTIN_VSLDOI_4SF,
2875 ALTIVEC_BUILTIN_VUPKHSB,
2876 ALTIVEC_BUILTIN_VUPKHPX,
2877 ALTIVEC_BUILTIN_VUPKHSH,
2878 ALTIVEC_BUILTIN_VUPKLSB,
2879 ALTIVEC_BUILTIN_VUPKLPX,
2880 ALTIVEC_BUILTIN_VUPKLSH,
2881 ALTIVEC_BUILTIN_MTVSCR,
2882 ALTIVEC_BUILTIN_MFVSCR,
2883 ALTIVEC_BUILTIN_DSSALL,
2884 ALTIVEC_BUILTIN_DSS,
2885 ALTIVEC_BUILTIN_LVSL,
2886 ALTIVEC_BUILTIN_LVSR,
2887 ALTIVEC_BUILTIN_DSTT,
2888 ALTIVEC_BUILTIN_DSTST,
2889 ALTIVEC_BUILTIN_DSTSTT,
2890 ALTIVEC_BUILTIN_DST,
2891 ALTIVEC_BUILTIN_LVEBX,
2892 ALTIVEC_BUILTIN_LVEHX,
2893 ALTIVEC_BUILTIN_LVEWX,
2894 ALTIVEC_BUILTIN_LVXL,
2895 ALTIVEC_BUILTIN_LVX,
2896 ALTIVEC_BUILTIN_STVX,
2897 ALTIVEC_BUILTIN_STVEBX,
2898 ALTIVEC_BUILTIN_STVEHX,
2899 ALTIVEC_BUILTIN_STVEWX,
2900 ALTIVEC_BUILTIN_STVXL,
2901 ALTIVEC_BUILTIN_VCMPBFP_P,
2902 ALTIVEC_BUILTIN_VCMPEQFP_P,
2903 ALTIVEC_BUILTIN_VCMPEQUB_P,
2904 ALTIVEC_BUILTIN_VCMPEQUH_P,
2905 ALTIVEC_BUILTIN_VCMPEQUW_P,
2906 ALTIVEC_BUILTIN_VCMPGEFP_P,
2907 ALTIVEC_BUILTIN_VCMPGTFP_P,
2908 ALTIVEC_BUILTIN_VCMPGTSB_P,
2909 ALTIVEC_BUILTIN_VCMPGTSH_P,
2910 ALTIVEC_BUILTIN_VCMPGTSW_P,
2911 ALTIVEC_BUILTIN_VCMPGTUB_P,
2912 ALTIVEC_BUILTIN_VCMPGTUH_P,
2913 ALTIVEC_BUILTIN_VCMPGTUW_P,
2914 ALTIVEC_BUILTIN_ABSS_V4SI,
2915 ALTIVEC_BUILTIN_ABSS_V8HI,
2916 ALTIVEC_BUILTIN_ABSS_V16QI,
2917 ALTIVEC_BUILTIN_ABS_V4SI,
2918 ALTIVEC_BUILTIN_ABS_V4SF,
2919 ALTIVEC_BUILTIN_ABS_V8HI,
2920 ALTIVEC_BUILTIN_ABS_V16QI,
2921 ALTIVEC_BUILTIN_COMPILETIME_ERROR,
2927 SPE_BUILTIN_EVDIVWS,
2928 SPE_BUILTIN_EVDIVWU,
2930 SPE_BUILTIN_EVFSADD,
2931 SPE_BUILTIN_EVFSDIV,
2932 SPE_BUILTIN_EVFSMUL,
2933 SPE_BUILTIN_EVFSSUB,
2937 SPE_BUILTIN_EVLHHESPLATX,
2938 SPE_BUILTIN_EVLHHOSSPLATX,
2939 SPE_BUILTIN_EVLHHOUSPLATX,
2940 SPE_BUILTIN_EVLWHEX,
2941 SPE_BUILTIN_EVLWHOSX,
2942 SPE_BUILTIN_EVLWHOUX,
2943 SPE_BUILTIN_EVLWHSPLATX,
2944 SPE_BUILTIN_EVLWWSPLATX,
2945 SPE_BUILTIN_EVMERGEHI,
2946 SPE_BUILTIN_EVMERGEHILO,
2947 SPE_BUILTIN_EVMERGELO,
2948 SPE_BUILTIN_EVMERGELOHI,
2949 SPE_BUILTIN_EVMHEGSMFAA,
2950 SPE_BUILTIN_EVMHEGSMFAN,
2951 SPE_BUILTIN_EVMHEGSMIAA,
2952 SPE_BUILTIN_EVMHEGSMIAN,
2953 SPE_BUILTIN_EVMHEGUMIAA,
2954 SPE_BUILTIN_EVMHEGUMIAN,
2955 SPE_BUILTIN_EVMHESMF,
2956 SPE_BUILTIN_EVMHESMFA,
2957 SPE_BUILTIN_EVMHESMFAAW,
2958 SPE_BUILTIN_EVMHESMFANW,
2959 SPE_BUILTIN_EVMHESMI,
2960 SPE_BUILTIN_EVMHESMIA,
2961 SPE_BUILTIN_EVMHESMIAAW,
2962 SPE_BUILTIN_EVMHESMIANW,
2963 SPE_BUILTIN_EVMHESSF,
2964 SPE_BUILTIN_EVMHESSFA,
2965 SPE_BUILTIN_EVMHESSFAAW,
2966 SPE_BUILTIN_EVMHESSFANW,
2967 SPE_BUILTIN_EVMHESSIAAW,
2968 SPE_BUILTIN_EVMHESSIANW,
2969 SPE_BUILTIN_EVMHEUMI,
2970 SPE_BUILTIN_EVMHEUMIA,
2971 SPE_BUILTIN_EVMHEUMIAAW,
2972 SPE_BUILTIN_EVMHEUMIANW,
2973 SPE_BUILTIN_EVMHEUSIAAW,
2974 SPE_BUILTIN_EVMHEUSIANW,
2975 SPE_BUILTIN_EVMHOGSMFAA,
2976 SPE_BUILTIN_EVMHOGSMFAN,
2977 SPE_BUILTIN_EVMHOGSMIAA,
2978 SPE_BUILTIN_EVMHOGSMIAN,
2979 SPE_BUILTIN_EVMHOGUMIAA,
2980 SPE_BUILTIN_EVMHOGUMIAN,
2981 SPE_BUILTIN_EVMHOSMF,
2982 SPE_BUILTIN_EVMHOSMFA,
2983 SPE_BUILTIN_EVMHOSMFAAW,
2984 SPE_BUILTIN_EVMHOSMFANW,
2985 SPE_BUILTIN_EVMHOSMI,
2986 SPE_BUILTIN_EVMHOSMIA,
2987 SPE_BUILTIN_EVMHOSMIAAW,
2988 SPE_BUILTIN_EVMHOSMIANW,
2989 SPE_BUILTIN_EVMHOSSF,
2990 SPE_BUILTIN_EVMHOSSFA,
2991 SPE_BUILTIN_EVMHOSSFAAW,
2992 SPE_BUILTIN_EVMHOSSFANW,
2993 SPE_BUILTIN_EVMHOSSIAAW,
2994 SPE_BUILTIN_EVMHOSSIANW,
2995 SPE_BUILTIN_EVMHOUMI,
2996 SPE_BUILTIN_EVMHOUMIA,
2997 SPE_BUILTIN_EVMHOUMIAAW,
2998 SPE_BUILTIN_EVMHOUMIANW,
2999 SPE_BUILTIN_EVMHOUSIAAW,
3000 SPE_BUILTIN_EVMHOUSIANW,
3001 SPE_BUILTIN_EVMWHSMF,
3002 SPE_BUILTIN_EVMWHSMFA,
3003 SPE_BUILTIN_EVMWHSMI,
3004 SPE_BUILTIN_EVMWHSMIA,
3005 SPE_BUILTIN_EVMWHSSF,
3006 SPE_BUILTIN_EVMWHSSFA,
3007 SPE_BUILTIN_EVMWHUMI,
3008 SPE_BUILTIN_EVMWHUMIA,
3009 SPE_BUILTIN_EVMWLSMIAAW,
3010 SPE_BUILTIN_EVMWLSMIANW,
3011 SPE_BUILTIN_EVMWLSSIAAW,
3012 SPE_BUILTIN_EVMWLSSIANW,
3013 SPE_BUILTIN_EVMWLUMI,
3014 SPE_BUILTIN_EVMWLUMIA,
3015 SPE_BUILTIN_EVMWLUMIAAW,
3016 SPE_BUILTIN_EVMWLUMIANW,
3017 SPE_BUILTIN_EVMWLUSIAAW,
3018 SPE_BUILTIN_EVMWLUSIANW,
3019 SPE_BUILTIN_EVMWSMF,
3020 SPE_BUILTIN_EVMWSMFA,
3021 SPE_BUILTIN_EVMWSMFAA,
3022 SPE_BUILTIN_EVMWSMFAN,
3023 SPE_BUILTIN_EVMWSMI,
3024 SPE_BUILTIN_EVMWSMIA,
3025 SPE_BUILTIN_EVMWSMIAA,
3026 SPE_BUILTIN_EVMWSMIAN,
3027 SPE_BUILTIN_EVMWHSSFAA,
3028 SPE_BUILTIN_EVMWSSF,
3029 SPE_BUILTIN_EVMWSSFA,
3030 SPE_BUILTIN_EVMWSSFAA,
3031 SPE_BUILTIN_EVMWSSFAN,
3032 SPE_BUILTIN_EVMWUMI,
3033 SPE_BUILTIN_EVMWUMIA,
3034 SPE_BUILTIN_EVMWUMIAA,
3035 SPE_BUILTIN_EVMWUMIAN,
3044 SPE_BUILTIN_EVSTDDX,
3045 SPE_BUILTIN_EVSTDHX,
3046 SPE_BUILTIN_EVSTDWX,
3047 SPE_BUILTIN_EVSTWHEX,
3048 SPE_BUILTIN_EVSTWHOX,
3049 SPE_BUILTIN_EVSTWWEX,
3050 SPE_BUILTIN_EVSTWWOX,
3051 SPE_BUILTIN_EVSUBFW,
3054 SPE_BUILTIN_EVADDSMIAAW,
3055 SPE_BUILTIN_EVADDSSIAAW,
3056 SPE_BUILTIN_EVADDUMIAAW,
3057 SPE_BUILTIN_EVADDUSIAAW,
3058 SPE_BUILTIN_EVCNTLSW,
3059 SPE_BUILTIN_EVCNTLZW,
3060 SPE_BUILTIN_EVEXTSB,
3061 SPE_BUILTIN_EVEXTSH,
3062 SPE_BUILTIN_EVFSABS,
3063 SPE_BUILTIN_EVFSCFSF,
3064 SPE_BUILTIN_EVFSCFSI,
3065 SPE_BUILTIN_EVFSCFUF,
3066 SPE_BUILTIN_EVFSCFUI,
3067 SPE_BUILTIN_EVFSCTSF,
3068 SPE_BUILTIN_EVFSCTSI,
3069 SPE_BUILTIN_EVFSCTSIZ,
3070 SPE_BUILTIN_EVFSCTUF,
3071 SPE_BUILTIN_EVFSCTUI,
3072 SPE_BUILTIN_EVFSCTUIZ,
3073 SPE_BUILTIN_EVFSNABS,
3074 SPE_BUILTIN_EVFSNEG,
3078 SPE_BUILTIN_EVSUBFSMIAAW,
3079 SPE_BUILTIN_EVSUBFSSIAAW,
3080 SPE_BUILTIN_EVSUBFUMIAAW,
3081 SPE_BUILTIN_EVSUBFUSIAAW,
3082 SPE_BUILTIN_EVADDIW,
3086 SPE_BUILTIN_EVLHHESPLAT,
3087 SPE_BUILTIN_EVLHHOSSPLAT,
3088 SPE_BUILTIN_EVLHHOUSPLAT,
3090 SPE_BUILTIN_EVLWHOS,
3091 SPE_BUILTIN_EVLWHOU,
3092 SPE_BUILTIN_EVLWHSPLAT,
3093 SPE_BUILTIN_EVLWWSPLAT,
3096 SPE_BUILTIN_EVSRWIS,
3097 SPE_BUILTIN_EVSRWIU,
3101 SPE_BUILTIN_EVSTWHE,
3102 SPE_BUILTIN_EVSTWHO,
3103 SPE_BUILTIN_EVSTWWE,
3104 SPE_BUILTIN_EVSTWWO,
3105 SPE_BUILTIN_EVSUBIFW,
3108 SPE_BUILTIN_EVCMPEQ,
3109 SPE_BUILTIN_EVCMPGTS,
3110 SPE_BUILTIN_EVCMPGTU,
3111 SPE_BUILTIN_EVCMPLTS,
3112 SPE_BUILTIN_EVCMPLTU,
3113 SPE_BUILTIN_EVFSCMPEQ,
3114 SPE_BUILTIN_EVFSCMPGT,
3115 SPE_BUILTIN_EVFSCMPLT,
3116 SPE_BUILTIN_EVFSTSTEQ,
3117 SPE_BUILTIN_EVFSTSTGT,
3118 SPE_BUILTIN_EVFSTSTLT,
3120 /* EVSEL compares. */
3121 SPE_BUILTIN_EVSEL_CMPEQ,
3122 SPE_BUILTIN_EVSEL_CMPGTS,
3123 SPE_BUILTIN_EVSEL_CMPGTU,
3124 SPE_BUILTIN_EVSEL_CMPLTS,
3125 SPE_BUILTIN_EVSEL_CMPLTU,
3126 SPE_BUILTIN_EVSEL_FSCMPEQ,
3127 SPE_BUILTIN_EVSEL_FSCMPGT,
3128 SPE_BUILTIN_EVSEL_FSCMPLT,
3129 SPE_BUILTIN_EVSEL_FSTSTEQ,
3130 SPE_BUILTIN_EVSEL_FSTSTGT,
3131 SPE_BUILTIN_EVSEL_FSTSTLT,
3133 SPE_BUILTIN_EVSPLATFI,
3134 SPE_BUILTIN_EVSPLATI,
3135 SPE_BUILTIN_EVMWHSSMAA,
3136 SPE_BUILTIN_EVMWHSMFAA,
3137 SPE_BUILTIN_EVMWHSMIAA,
3138 SPE_BUILTIN_EVMWHUSIAA,
3139 SPE_BUILTIN_EVMWHUMIAA,
3140 SPE_BUILTIN_EVMWHSSFAN,
3141 SPE_BUILTIN_EVMWHSSIAN,
3142 SPE_BUILTIN_EVMWHSMFAN,
3143 SPE_BUILTIN_EVMWHSMIAN,
3144 SPE_BUILTIN_EVMWHUSIAN,
3145 SPE_BUILTIN_EVMWHUMIAN,
3146 SPE_BUILTIN_EVMWHGSSFAA,
3147 SPE_BUILTIN_EVMWHGSMFAA,
3148 SPE_BUILTIN_EVMWHGSMIAA,
3149 SPE_BUILTIN_EVMWHGUMIAA,
3150 SPE_BUILTIN_EVMWHGSSFAN,
3151 SPE_BUILTIN_EVMWHGSMFAN,
3152 SPE_BUILTIN_EVMWHGSMIAN,
3153 SPE_BUILTIN_EVMWHGUMIAN,
3154 SPE_BUILTIN_MTSPEFSCR,
3155 SPE_BUILTIN_MFSPEFSCR,
OSDN Git Service
