1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
23 /* Note that some other tm.h files include this one and then override
24 many of the definitions. */
26 /* Definitions for the object file format. These are set at
29 #define OBJECT_XCOFF 1
32 #define OBJECT_MACHO 4
34 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
35 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
36 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
37 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
43 /* Control whether function entry points use a "dot" symbol when
47 /* Default string to use for cpu if not specified. */
48 #ifndef TARGET_CPU_DEFAULT
49 #define TARGET_CPU_DEFAULT ((char *)0)
52 /* Common ASM definitions used by ASM_SPEC among the various targets
53 for handling -mcpu=xxx switches. */
54 #define ASM_CPU_SPEC \
56 %{mpower: %{!mpower2: -mpwr}} \
58 %{mpowerpc64*: -mppc64} \
59 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
60 %{mno-power: %{!mpowerpc*: -mcom}} \
61 %{!mno-power: %{!mpower*: %(asm_default)}}} \
62 %{mcpu=common: -mcom} \
63 %{mcpu=power: -mpwr} \
64 %{mcpu=power2: -mpwrx} \
65 %{mcpu=power3: -mppc64} \
66 %{mcpu=power4: -mpower4} \
67 %{mcpu=power5: -mpower4} \
68 %{mcpu=powerpc: -mppc} \
70 %{mcpu=rios1: -mpwr} \
71 %{mcpu=rios2: -mpwrx} \
74 %{mcpu=rs64a: -mppc64} \
78 %{mcpu=405fp: -m405} \
80 %{mcpu=440fp: -m440} \
86 %{mcpu=ec603e: -mppc} \
89 %{mcpu=620: -mppc64} \
90 %{mcpu=630: -mppc64} \
94 %{mcpu=7400: -mppc -maltivec} \
95 %{mcpu=7450: -mppc -maltivec} \
96 %{mcpu=G4: -mppc -maltivec} \
101 %{mcpu=970: -mpower4 -maltivec} \
102 %{mcpu=G5: -mpower4 -maltivec} \
103 %{mcpu=8540: -me500} \
104 %{maltivec: -maltivec} \
107 #define CPP_DEFAULT_SPEC ""
109 #define ASM_DEFAULT_SPEC ""
111 /* This macro defines names of additional specifications to put in the specs
112 that can be used in various specifications like CC1_SPEC. Its definition
113 is an initializer with a subgrouping for each command option.
115 Each subgrouping contains a string constant, that defines the
116 specification name, and a string constant that used by the GCC driver
119 Do not define this macro if it does not need to do anything. */
121 #define SUBTARGET_EXTRA_SPECS
123 #define EXTRA_SPECS \
124 { "cpp_default", CPP_DEFAULT_SPEC }, \
125 { "asm_cpu", ASM_CPU_SPEC }, \
126 { "asm_default", ASM_DEFAULT_SPEC }, \
127 SUBTARGET_EXTRA_SPECS
129 /* Architecture type. */
131 extern int target_flags;
133 /* Use POWER architecture instructions and MQ register. */
134 #define MASK_POWER 0x00000001
136 /* Use POWER2 extensions to POWER architecture. */
137 #define MASK_POWER2 0x00000002
139 /* Use PowerPC architecture instructions. */
140 #define MASK_POWERPC 0x00000004
142 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */
143 #define MASK_PPC_GPOPT 0x00000008
145 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */
146 #define MASK_PPC_GFXOPT 0x00000010
148 /* Use PowerPC-64 architecture instructions. */
149 #define MASK_POWERPC64 0x00000020
151 /* Use revised mnemonic names defined for PowerPC architecture. */
152 #define MASK_NEW_MNEMONICS 0x00000040
154 /* Disable placing fp constants in the TOC; can be turned on when the
156 #define MASK_NO_FP_IN_TOC 0x00000080
158 /* Disable placing symbol+offset constants in the TOC; can be turned on when
159 the TOC overflows. */
160 #define MASK_NO_SUM_IN_TOC 0x00000100
162 /* Output only one TOC entry per module. Normally linking fails if
163 there are more than 16K unique variables/constants in an executable. With
164 this option, linking fails only if there are more than 16K modules, or
165 if there are more than 16K unique variables/constant in a single module.
167 This is at the cost of having 2 extra loads and one extra store per
168 function, and one less allocable register. */
169 #define MASK_MINIMAL_TOC 0x00000200
171 /* Nonzero for the 64 bit ABIs: longs and pointers are 64 bits. The
172 chip is running in "64-bit mode", in which CR0 is set in dot
173 operations based on all 64 bits of the register, bdnz works on 64-bit
174 ctr, lr is 64 bits, and so on. Requires MASK_POWERPC64. */
175 #define MASK_64BIT 0x00000400
177 /* Disable use of FPRs. */
178 #define MASK_SOFT_FLOAT 0x00000800
180 /* Enable load/store multiple, even on PowerPC */
181 #define MASK_MULTIPLE 0x00001000
183 /* Use string instructions for block moves */
184 #define MASK_STRING 0x00002000
186 /* Disable update form of load/store */
187 #define MASK_NO_UPDATE 0x00004000
189 /* Disable fused multiply/add operations */
190 #define MASK_NO_FUSED_MADD 0x00008000
192 /* Nonzero if we need to schedule the prolog and epilog. */
193 #define MASK_SCHED_PROLOG 0x00010000
195 /* Use AltiVec instructions. */
196 #define MASK_ALTIVEC 0x00020000
198 /* Return small structures in memory (as the AIX ABI requires). */
199 #define MASK_AIX_STRUCT_RET 0x00040000
201 /* Use single field mfcr instruction. */
202 #define MASK_MFCRF 0x00080000
204 /* The only remaining free bits are 0x00600000. linux64.h uses
205 0x00100000, and sysv4.h uses 0x00800000 -> 0x40000000.
206 0x80000000 is not available because target_flags is signed. */
208 #define TARGET_POWER (target_flags & MASK_POWER)
209 #define TARGET_POWER2 (target_flags & MASK_POWER2)
210 #define TARGET_POWERPC (target_flags & MASK_POWERPC)
211 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
212 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
213 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
214 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
215 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
216 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
217 #define TARGET_64BIT (target_flags & MASK_64BIT)
218 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
219 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
220 #define TARGET_STRING (target_flags & MASK_STRING)
221 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
222 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
223 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
224 #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
225 #define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET)
227 /* Define TARGET_MFCRF if the target assembler supports the optional
228 field operand for mfcr and the target processor supports the
232 #define TARGET_MFCRF (target_flags & MASK_MFCRF)
234 #define TARGET_MFCRF 0
238 #define TARGET_32BIT (! TARGET_64BIT)
239 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
240 #define TARGET_UPDATE (! TARGET_NO_UPDATE)
241 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
243 /* Emit a dtp-relative reference to a TLS variable. */
246 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
247 rs6000_output_dwarf_dtprel (FILE, SIZE, X)
251 #define HAVE_AS_TLS 0
255 /* For libgcc2 we make sure this is a compile time constant */
256 #if defined (__64BIT__) || defined (__powerpc64__)
257 #define TARGET_POWERPC64 1
259 #define TARGET_POWERPC64 0
262 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
265 #define TARGET_XL_CALL 0
267 /* Run-time compilation parameters selecting different hardware subsets.
269 Macro to define tables used to set the flags.
270 This is a list in braces of pairs in braces,
271 each pair being { "NAME", VALUE }
272 where VALUE is the bits to set or minus the bits to clear.
273 An empty string NAME is used to identify the default VALUE. */
275 #define TARGET_SWITCHES \
276 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
277 N_("Use POWER instruction set")}, \
278 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
280 N_("Use POWER2 instruction set")}, \
281 {"no-power2", - MASK_POWER2, \
282 N_("Do not use POWER2 instruction set")}, \
283 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
285 N_("Do not use POWER instruction set")}, \
286 {"powerpc", MASK_POWERPC, \
287 N_("Use PowerPC instruction set")}, \
288 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
289 | MASK_PPC_GFXOPT | MASK_POWERPC64), \
290 N_("Do not use PowerPC instruction set")}, \
291 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
292 N_("Use PowerPC General Purpose group optional instructions")},\
293 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
294 N_("Do not use PowerPC General Purpose group optional instructions")},\
295 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
296 N_("Use PowerPC Graphics group optional instructions")},\
297 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
298 N_("Do not use PowerPC Graphics group optional instructions")},\
299 {"powerpc64", MASK_POWERPC64, \
300 N_("Use PowerPC-64 instruction set")}, \
301 {"no-powerpc64", - MASK_POWERPC64, \
302 N_("Do not use PowerPC-64 instruction set")}, \
303 {"altivec", MASK_ALTIVEC , \
304 N_("Use AltiVec instructions")}, \
305 {"no-altivec", - MASK_ALTIVEC , \
306 N_("Do not use AltiVec instructions")}, \
307 {"new-mnemonics", MASK_NEW_MNEMONICS, \
308 N_("Use new mnemonics for PowerPC architecture")},\
309 {"old-mnemonics", -MASK_NEW_MNEMONICS, \
310 N_("Use old mnemonics for PowerPC architecture")},\
311 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
312 | MASK_MINIMAL_TOC), \
313 N_("Put everything in the regular TOC")}, \
314 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
315 N_("Place floating point constants in TOC")}, \
316 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
317 N_("Do not place floating point constants in TOC")},\
318 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
319 N_("Place symbol+offset constants in TOC")}, \
320 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
321 N_("Do not place symbol+offset constants in TOC")},\
322 {"minimal-toc", MASK_MINIMAL_TOC, \
323 "Use only one TOC entry per procedure"}, \
324 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
326 {"no-minimal-toc", - MASK_MINIMAL_TOC, \
327 N_("Place variable addresses in the regular TOC")},\
328 {"hard-float", - MASK_SOFT_FLOAT, \
329 N_("Use hardware floating point")}, \
330 {"soft-float", MASK_SOFT_FLOAT, \
331 N_("Do not use hardware floating point")}, \
332 {"multiple", MASK_MULTIPLE, \
333 N_("Generate load/store multiple instructions")}, \
334 {"no-multiple", - MASK_MULTIPLE, \
335 N_("Do not generate load/store multiple instructions")},\
336 {"string", MASK_STRING, \
337 N_("Generate string instructions for block moves")},\
338 {"no-string", - MASK_STRING, \
339 N_("Do not generate string instructions for block moves")},\
340 {"update", - MASK_NO_UPDATE, \
341 N_("Generate load/store with update instructions")},\
342 {"no-update", MASK_NO_UPDATE, \
343 N_("Do not generate load/store with update instructions")},\
344 {"fused-madd", - MASK_NO_FUSED_MADD, \
345 N_("Generate fused multiply/add instructions")},\
346 {"no-fused-madd", MASK_NO_FUSED_MADD, \
347 N_("Do not generate fused multiply/add instructions")},\
348 {"sched-prolog", MASK_SCHED_PROLOG, \
350 {"no-sched-prolog", -MASK_SCHED_PROLOG, \
351 N_("Do not schedule the start and end of the procedure")},\
352 {"sched-epilog", MASK_SCHED_PROLOG, \
354 {"no-sched-epilog", -MASK_SCHED_PROLOG, \
356 {"aix-struct-return", MASK_AIX_STRUCT_RET, \
357 N_("Return all structures in memory (AIX default)")},\
358 {"svr4-struct-return", - MASK_AIX_STRUCT_RET, \
359 N_("Return small structures in registers (SVR4 default)")},\
360 {"no-aix-struct-return", - MASK_AIX_STRUCT_RET, \
362 {"no-svr4-struct-return", MASK_AIX_STRUCT_RET, \
364 {"mfcrf", MASK_MFCRF, \
365 N_("Generate single field mfcr instruction")}, \
366 {"no-mfcrf", - MASK_MFCRF, \
367 N_("Do not generate single field mfcr instruction")},\
369 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
372 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
374 /* This is meant to be redefined in the host dependent files */
375 #define SUBTARGET_SWITCHES
377 /* Processor type. Order must match cpu attribute in MD file. */
401 extern enum processor_type rs6000_cpu;
403 /* Recast the processor type to the cpu attribute. */
404 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
406 /* Define generic processor types based upon current deployment. */
407 #define PROCESSOR_COMMON PROCESSOR_PPC601
408 #define PROCESSOR_POWER PROCESSOR_RIOS1
409 #define PROCESSOR_POWERPC PROCESSOR_PPC604
410 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
412 /* Define the default processor. This is overridden by other tm.h files. */
413 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
414 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
416 /* Specify the dialect of assembler to use. New mnemonics is dialect one
417 and the old mnemonics are dialect zero. */
418 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
420 /* Types of costly dependences. */
421 enum rs6000_dependence_cost
423 max_dep_latency = 1000,
426 true_store_to_load_dep_costly,
427 store_to_load_dep_costly
430 /* Types of nop insertion schemes in sched target hook sched_finish. */
431 enum rs6000_nop_insertion
433 sched_finish_regroup_exact = 1000,
434 sched_finish_pad_groups,
438 /* Dispatch group termination caused by an insn. */
439 enum group_termination
445 /* This is meant to be overridden in target specific files. */
446 #define SUBTARGET_OPTIONS
448 #define TARGET_OPTIONS \
450 {"cpu=", &rs6000_select[1].string, \
451 N_("Use features of and schedule code for given CPU"), 0}, \
452 {"tune=", &rs6000_select[2].string, \
453 N_("Schedule code for given CPU"), 0}, \
454 {"debug=", &rs6000_debug_name, N_("Enable debug output"), 0}, \
455 {"traceback=", &rs6000_traceback_name, \
456 N_("Select full, part, or no traceback table"), 0}, \
457 {"abi=", &rs6000_abi_string, N_("Specify ABI to use"), 0}, \
458 {"long-double-", &rs6000_long_double_size_string, \
459 N_("Specify size of long double (64 or 128 bits)"), 0}, \
460 {"isel=", &rs6000_isel_string, \
461 N_("Specify yes/no if isel instructions should be generated"), 0}, \
462 {"spe=", &rs6000_spe_string, \
463 N_("Specify yes/no if SPE SIMD instructions should be generated"), 0},\
464 {"float-gprs=", &rs6000_float_gprs_string, \
465 N_("Specify yes/no if using floating point in the GPRs"), 0}, \
466 {"vrsave=", &rs6000_altivec_vrsave_string, \
467 N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec"), 0}, \
468 {"longcall", &rs6000_longcall_switch, \
469 N_("Avoid all range limits on call instructions"), 0}, \
470 {"no-longcall", &rs6000_longcall_switch, "", 0}, \
471 {"warn-altivec-long", &rs6000_warn_altivec_long_switch, \
472 N_("Warn about deprecated 'vector long ...' AltiVec type usage"), 0}, \
473 {"no-warn-altivec-long", &rs6000_warn_altivec_long_switch, "", 0}, \
474 {"sched-costly-dep=", &rs6000_sched_costly_dep_str, \
475 N_("Determine which dependences between insns are considered costly"), 0}, \
476 {"insert-sched-nops=", &rs6000_sched_insert_nops_str, \
477 N_("Specify which post scheduling nop insertion scheme to apply"), 0}, \
478 {"align-", &rs6000_alignment_string, \
479 N_("Specify alignment of structure fields default/natural"), 0}, \
480 {"prioritize-restricted-insns=", &rs6000_sched_restricted_insns_priority_str, \
481 N_("Specify scheduling priority for dispatch slot restricted insns"), 0}, \
485 /* Support for a compile-time default CPU, et cetera. The rules are:
486 --with-cpu is ignored if -mcpu is specified.
487 --with-tune is ignored if -mtune is specified.
488 --with-float is ignored if -mhard-float or -msoft-float are
490 #define OPTION_DEFAULT_SPECS \
491 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
492 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
493 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
495 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
496 struct rs6000_cpu_select
504 extern struct rs6000_cpu_select rs6000_select[];
507 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
508 extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,eabi,aix,altivec} */
509 extern int rs6000_debug_stack; /* debug stack applications */
510 extern int rs6000_debug_arg; /* debug argument handling */
512 #define TARGET_DEBUG_STACK rs6000_debug_stack
513 #define TARGET_DEBUG_ARG rs6000_debug_arg
515 extern const char *rs6000_traceback_name; /* Type of traceback table. */
517 /* These are separate from target_flags because we've run out of bits
519 extern const char *rs6000_long_double_size_string;
520 extern int rs6000_long_double_type_size;
521 extern int rs6000_altivec_abi;
522 extern int rs6000_spe_abi;
523 extern int rs6000_isel;
524 extern int rs6000_spe;
525 extern int rs6000_float_gprs;
526 extern const char *rs6000_float_gprs_string;
527 extern const char *rs6000_isel_string;
528 extern const char *rs6000_spe_string;
529 extern const char *rs6000_altivec_vrsave_string;
530 extern int rs6000_altivec_vrsave;
531 extern const char *rs6000_longcall_switch;
532 extern int rs6000_default_long_calls;
533 extern const char* rs6000_alignment_string;
534 extern int rs6000_alignment_flags;
535 extern const char *rs6000_sched_restricted_insns_priority_str;
536 extern int rs6000_sched_restricted_insns_priority;
537 extern const char *rs6000_sched_costly_dep_str;
538 extern enum rs6000_dependence_cost rs6000_sched_costly_dep;
539 extern const char *rs6000_sched_insert_nops_str;
540 extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
542 extern int rs6000_warn_altivec_long;
543 extern const char *rs6000_warn_altivec_long_switch;
545 /* Alignment options for fields in structures for sub-targets following
547 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
548 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
550 Override the macro definitions when compiling libobjc to avoid undefined
551 reference to rs6000_alignment_flags due to library's use of GCC alignment
552 macros which use the macros below. */
554 #ifndef IN_TARGET_LIBS
555 #define MASK_ALIGN_POWER 0x00000000
556 #define MASK_ALIGN_NATURAL 0x00000001
557 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
559 #define TARGET_ALIGN_NATURAL 0
562 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
563 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
564 #define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave
566 #define TARGET_SPE_ABI 0
568 #define TARGET_E500 0
569 #define TARGET_ISEL 0
570 #define TARGET_FPRS 1
572 /* Sometimes certain combinations of command options do not make sense
573 on a particular target machine. You can define a macro
574 `OVERRIDE_OPTIONS' to take account of this. This macro, if
575 defined, is executed once just after all the command options have
578 Do not use this macro to turn on various extra optimizations for
579 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
581 On the RS/6000 this is used to define the target cpu type. */
583 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
585 /* Define this to change the optimizations performed by default. */
586 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
588 /* Show we can debug even without a frame pointer. */
589 #define CAN_DEBUG_WITHOUT_FP
592 #define REGISTER_TARGET_PRAGMAS() do { \
593 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
596 /* Target #defines. */
597 #define TARGET_CPU_CPP_BUILTINS() \
598 rs6000_cpu_cpp_builtins (pfile)
600 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
601 we're compiling for. Some configurations may need to override it. */
602 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
605 if (BYTES_BIG_ENDIAN) \
607 builtin_define ("__BIG_ENDIAN__"); \
608 builtin_define ("_BIG_ENDIAN"); \
609 builtin_assert ("machine=bigendian"); \
613 builtin_define ("__LITTLE_ENDIAN__"); \
614 builtin_define ("_LITTLE_ENDIAN"); \
615 builtin_assert ("machine=littleendian"); \
620 /* Target machine storage layout. */
622 /* Define this macro if it is advisable to hold scalars in registers
623 in a wider mode than that declared by the program. In such cases,
624 the value is constrained to be within the bounds of the declared
625 type, but kept valid in the wider mode. The signedness of the
626 extension may differ from that of the type. */
628 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
629 if (GET_MODE_CLASS (MODE) == MODE_INT \
630 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
631 (MODE) = TARGET_32BIT ? SImode : DImode;
633 /* Define this if most significant bit is lowest numbered
634 in instructions that operate on numbered bit-fields. */
635 /* That is true on RS/6000. */
636 #define BITS_BIG_ENDIAN 1
638 /* Define this if most significant byte of a word is the lowest numbered. */
639 /* That is true on RS/6000. */
640 #define BYTES_BIG_ENDIAN 1
642 /* Define this if most significant word of a multiword number is lowest
645 For RS/6000 we can decide arbitrarily since there are no machine
646 instructions for them. Might as well be consistent with bits and bytes. */
647 #define WORDS_BIG_ENDIAN 1
649 #define MAX_BITS_PER_WORD 64
651 /* Width of a word, in units (bytes). */
652 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
654 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
656 #define MIN_UNITS_PER_WORD 4
658 #define UNITS_PER_FP_WORD 8
659 #define UNITS_PER_ALTIVEC_WORD 16
660 #define UNITS_PER_SPE_WORD 8
662 /* Type used for ptrdiff_t, as a string used in a declaration. */
663 #define PTRDIFF_TYPE "int"
665 /* Type used for size_t, as a string used in a declaration. */
666 #define SIZE_TYPE "long unsigned int"
668 /* Type used for wchar_t, as a string used in a declaration. */
669 #define WCHAR_TYPE "short unsigned int"
671 /* Width of wchar_t in bits. */
672 #define WCHAR_TYPE_SIZE 16
674 /* A C expression for the size in bits of the type `short' on the
675 target machine. If you don't define this, the default is half a
676 word. (If this would be less than one storage unit, it is
677 rounded up to one unit.) */
678 #define SHORT_TYPE_SIZE 16
680 /* A C expression for the size in bits of the type `int' on the
681 target machine. If you don't define this, the default is one
683 #define INT_TYPE_SIZE 32
685 /* A C expression for the size in bits of the type `long' on the
686 target machine. If you don't define this, the default is one
688 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
690 /* A C expression for the size in bits of the type `long long' on the
691 target machine. If you don't define this, the default is two
693 #define LONG_LONG_TYPE_SIZE 64
695 /* A C expression for the size in bits of the type `float' on the
696 target machine. If you don't define this, the default is one
698 #define FLOAT_TYPE_SIZE 32
700 /* A C expression for the size in bits of the type `double' on the
701 target machine. If you don't define this, the default is two
703 #define DOUBLE_TYPE_SIZE 64
705 /* A C expression for the size in bits of the type `long double' on
706 the target machine. If you don't define this, the default is two
708 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
710 /* Define this to set long double type size to use in libgcc2.c, which can
711 not depend on target_flags. */
712 #ifdef __LONG_DOUBLE_128__
713 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
715 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
718 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
719 #define WIDEST_HARDWARE_FP_SIZE 64
721 /* Width in bits of a pointer.
722 See also the macro `Pmode' defined below. */
723 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
725 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
726 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
728 /* Boundary (in *bits*) on which stack pointer should be aligned. */
729 #define STACK_BOUNDARY \
730 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI) ? 64 : 128)
732 /* Allocation boundary (in *bits*) for the code of a function. */
733 #define FUNCTION_BOUNDARY 32
735 /* No data type wants to be aligned rounder than this. */
736 #define BIGGEST_ALIGNMENT 128
738 /* A C expression to compute the alignment for a variables in the
739 local store. TYPE is the data type, and ALIGN is the alignment
740 that the object would ordinarily have. */
741 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
742 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
743 (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN)
745 /* Alignment of field after `int : 0' in a structure. */
746 #define EMPTY_FIELD_BOUNDARY 32
748 /* Every structure's size must be a multiple of this. */
749 #define STRUCTURE_SIZE_BOUNDARY 8
751 /* Return 1 if a structure or array containing FIELD should be
752 accessed using `BLKMODE'.
754 For the SPE, simd types are V2SI, and gcc can be tempted to put the
755 entire thing in a DI and use subregs to access the internals.
756 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
757 back-end. Because a single GPR can hold a V2SI, but not a DI, the
758 best thing to do is set structs to BLKmode and avoid Severe Tire
760 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
761 (TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE)
763 /* A bit-field declared as `int' forces `int' alignment for the struct. */
764 #define PCC_BITFIELD_TYPE_MATTERS 1
766 /* Make strings word-aligned so strcpy from constants will be faster.
767 Make vector constants quadword aligned. */
768 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
769 (TREE_CODE (EXP) == STRING_CST \
770 && (ALIGN) < BITS_PER_WORD \
774 /* Make arrays of chars word-aligned for the same reasons.
775 Align vectors to 128 bits. */
776 #define DATA_ALIGNMENT(TYPE, ALIGN) \
777 (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \
778 : TREE_CODE (TYPE) == ARRAY_TYPE \
779 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
780 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
782 /* Nonzero if move instructions will actually fail to work
783 when given unaligned data. */
784 #define STRICT_ALIGNMENT 0
786 /* Define this macro to be the value 1 if unaligned accesses have a cost
787 many times greater than aligned accesses, for example if they are
788 emulated in a trap handler. */
789 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
791 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
792 || (MODE) == DImode) \
795 /* Standard register usage. */
797 /* Number of actual hardware registers.
798 The hardware registers are assigned numbers for the compiler
799 from 0 to just below FIRST_PSEUDO_REGISTER.
800 All registers that the compiler knows about must be given numbers,
801 even those that are not normally considered general registers.
803 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
804 an MQ register, a count register, a link register, and 8 condition
805 register fields, which we view here as separate registers. AltiVec
806 adds 32 vector registers and a VRsave register.
808 In addition, the difference between the frame and argument pointers is
809 a function of the number of registers saved, so we need to have a
810 register for AP that will later be eliminated in favor of SP or FP.
811 This is a normal register, but it is fixed.
813 We also create a pseudo register for float/int conversions, that will
814 really represent the memory location used. It is represented here as
815 a register, in order to work around problems in allocating stack storage
816 in inline functions. */
818 #define FIRST_PSEUDO_REGISTER 113
820 /* This must be included for pre gcc 3.0 glibc compatibility. */
821 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
823 /* Add 32 dwarf columns for synthetic SPE registers. */
824 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 32)
826 /* The SPE has an additional 32 synthetic registers, with DWARF debug
827 info numbering for these registers starting at 1200. While eh_frame
828 register numbering need not be the same as the debug info numbering,
829 we choose to number these regs for eh_frame at 1200 too. This allows
830 future versions of the rs6000 backend to add hard registers and
831 continue to use the gcc hard register numbering for eh_frame. If the
832 extra SPE registers in eh_frame were numbered starting from the
833 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
834 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
835 avoid invalidating older SPE eh_frame info.
837 We must map them here to avoid huge unwinder tables mostly consisting
839 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
840 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER) : (r))
842 /* Use gcc hard register numbering for eh_frame. */
843 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
845 /* 1 for registers that have pervasive standard uses
846 and are not available for the register allocator.
848 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
849 as a local register; for all other OS's r2 is the TOC pointer.
851 cr5 is not supposed to be used.
853 On System V implementations, r13 is fixed and not available for use. */
855 #define FIXED_REGISTERS \
856 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
857 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
858 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
859 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
860 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
861 /* AltiVec registers. */ \
862 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
863 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
868 /* 1 for registers not available across function calls.
869 These must include the FIXED_REGISTERS and also any
870 registers that can be used without being saved.
871 The latter must include the registers where values are returned
872 and the register where structure-value addresses are passed.
873 Aside from that, you can include as many other registers as you like. */
875 #define CALL_USED_REGISTERS \
876 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
877 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
878 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
879 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
880 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
881 /* AltiVec registers. */ \
882 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
883 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
888 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
889 the entire set of `FIXED_REGISTERS' be included.
890 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
891 This macro is optional. If not specified, it defaults to the value
892 of `CALL_USED_REGISTERS'. */
894 #define CALL_REALLY_USED_REGISTERS \
895 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
896 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
897 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
898 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
899 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
900 /* AltiVec registers. */ \
901 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
902 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
913 #define MAX_CR_REGNO 75
915 #define FIRST_ALTIVEC_REGNO 77
916 #define LAST_ALTIVEC_REGNO 108
917 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
918 #define VRSAVE_REGNO 109
919 #define VSCR_REGNO 110
920 #define SPE_ACC_REGNO 111
921 #define SPEFSCR_REGNO 112
923 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
924 #define FIRST_SAVED_FP_REGNO (14+32)
925 #define FIRST_SAVED_GP_REGNO 13
927 /* List the order in which to allocate registers. Each register must be
928 listed once, even those in FIXED_REGISTERS.
930 We allocate in the following order:
931 fp0 (not saved or used for anything)
932 fp13 - fp2 (not saved; incoming fp arg registers)
933 fp1 (not saved; return value)
934 fp31 - fp14 (saved; order given to save least number)
935 cr7, cr6 (not saved or special)
936 cr1 (not saved, but used for FP operations)
937 cr0 (not saved, but used for arithmetic operations)
938 cr4, cr3, cr2 (saved)
939 r0 (not saved; cannot be base reg)
940 r9 (not saved; best for TImode)
941 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
942 r3 (not saved; return value register)
943 r31 - r13 (saved; order given to save least number)
944 r12 (not saved; if used for DImode or DFmode would use r13)
945 mq (not saved; best to use it if we can)
946 ctr (not saved; when we have the choice ctr is better)
948 cr5, r1, r2, ap, xer, vrsave, vscr (fixed)
949 spe_acc, spefscr (fixed)
952 v0 - v1 (not saved or used for anything)
953 v13 - v3 (not saved; incoming vector arg registers)
954 v2 (not saved; incoming vector arg reg; return value)
955 v19 - v14 (not saved or used for anything)
956 v31 - v20 (saved; order given to save least number)
960 #define MAYBE_R2_AVAILABLE
961 #define MAYBE_R2_FIXED 2,
963 #define MAYBE_R2_AVAILABLE 2,
964 #define MAYBE_R2_FIXED
967 #define REG_ALLOC_ORDER \
969 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
971 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
972 50, 49, 48, 47, 46, \
973 75, 74, 69, 68, 72, 71, 70, \
974 0, MAYBE_R2_AVAILABLE \
975 9, 11, 10, 8, 7, 6, 5, 4, \
977 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
978 18, 17, 16, 15, 14, 13, 12, \
980 73, 1, MAYBE_R2_FIXED 67, 76, \
981 /* AltiVec registers. */ \
983 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
985 96, 95, 94, 93, 92, 91, \
986 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \
991 /* True if register is floating-point. */
992 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
994 /* True if register is a condition register. */
995 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
997 /* True if register is a condition register, but not cr0. */
998 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
1000 /* True if register is an integer register. */
1001 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
1003 /* SPE SIMD registers are just the GPRs. */
1004 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
1006 /* True if register is the XER register. */
1007 #define XER_REGNO_P(N) ((N) == XER_REGNO)
1009 /* True if register is an AltiVec register. */
1010 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1012 /* Return number of consecutive hard regs needed starting at reg REGNO
1013 to hold something of mode MODE. */
1015 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs ((REGNO), (MODE))
1017 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1018 ((TARGET_32BIT && TARGET_POWERPC64 \
1019 && (GET_MODE_SIZE (MODE) > 4) \
1020 && INT_REGNO_P (REGNO)) ? 1 : 0)
1022 #define ALTIVEC_VECTOR_MODE(MODE) \
1023 ((MODE) == V16QImode \
1024 || (MODE) == V8HImode \
1025 || (MODE) == V4SFmode \
1026 || (MODE) == V4SImode)
1028 #define SPE_VECTOR_MODE(MODE) \
1029 ((MODE) == V4HImode \
1030 || (MODE) == V2SFmode \
1031 || (MODE) == V1DImode \
1032 || (MODE) == V2SImode)
1034 #define UNITS_PER_SIMD_WORD \
1035 (TARGET_ALTIVEC ? 16 : (TARGET_SPE ? 8 : 0) )
1037 /* Value is TRUE if hard register REGNO can hold a value of
1038 machine-mode MODE. */
1039 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1040 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
1042 /* Value is 1 if it is a good idea to tie two pseudo registers
1043 when one has mode MODE1 and one has mode MODE2.
1044 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1045 for any hard reg, then this must be 0 for correct output. */
1046 #define MODES_TIEABLE_P(MODE1, MODE2) \
1047 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
1048 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
1049 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
1050 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
1051 : GET_MODE_CLASS (MODE1) == MODE_CC \
1052 ? GET_MODE_CLASS (MODE2) == MODE_CC \
1053 : GET_MODE_CLASS (MODE2) == MODE_CC \
1054 ? GET_MODE_CLASS (MODE1) == MODE_CC \
1055 : SPE_VECTOR_MODE (MODE1) \
1056 ? SPE_VECTOR_MODE (MODE2) \
1057 : SPE_VECTOR_MODE (MODE2) \
1058 ? SPE_VECTOR_MODE (MODE1) \
1059 : ALTIVEC_VECTOR_MODE (MODE1) \
1060 ? ALTIVEC_VECTOR_MODE (MODE2) \
1061 : ALTIVEC_VECTOR_MODE (MODE2) \
1062 ? ALTIVEC_VECTOR_MODE (MODE1) \
1065 /* Post-reload, we can't use any new AltiVec registers, as we already
1066 emitted the vrsave mask. */
1068 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1069 (! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST])
1071 /* A C expression returning the cost of moving data from a register of class
1072 CLASS1 to one of CLASS2. */
1074 #define REGISTER_MOVE_COST rs6000_register_move_cost
1076 /* A C expressions returning the cost of moving data of MODE from a register to
1079 #define MEMORY_MOVE_COST rs6000_memory_move_cost
1081 /* Specify the cost of a branch insn; roughly the number of extra insns that
1082 should be added to avoid a branch.
1084 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1085 unscheduled conditional branch. */
1087 #define BRANCH_COST 3
1089 /* Override BRANCH_COST heuristic which empirically produces worse
1090 performance for fold_range_test(). */
1092 #define RANGE_TEST_NON_SHORT_CIRCUIT 0
1094 /* A fixed register used at prologue and epilogue generation to fix
1095 addressing modes. The SPE needs heavy addressing fixes at the last
1096 minute, and it's best to save a register for it.
1098 AltiVec also needs fixes, but we've gotten around using r11, which
1099 is actually wrong because when use_backchain_to_restore_sp is true,
1100 we end up clobbering r11.
1102 The AltiVec case needs to be fixed. Dunno if we should break ABI
1103 compatibility and reserve a register for it as well.. */
1105 #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11)
1107 /* Define this macro to change register usage conditional on target
1110 #define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
1112 /* Specify the registers used for certain standard purposes.
1113 The values of these macros are register numbers. */
1115 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1116 /* #define PC_REGNUM */
1118 /* Register to use for pushing function arguments. */
1119 #define STACK_POINTER_REGNUM 1
1121 /* Base register for access to local variables of the function. */
1122 #define FRAME_POINTER_REGNUM 31
1124 /* Value should be nonzero if functions must have frame pointers.
1125 Zero means the frame pointer need not be set up (and parms
1126 may be accessed via the stack pointer) in functions that seem suitable.
1127 This is computed in `reload', in reload1.c. */
1128 #define FRAME_POINTER_REQUIRED 0
1130 /* Base register for access to arguments of the function. */
1131 #define ARG_POINTER_REGNUM 67
1133 /* Place to put static chain when calling a function that requires it. */
1134 #define STATIC_CHAIN_REGNUM 11
1136 /* Link register number. */
1137 #define LINK_REGISTER_REGNUM 65
1139 /* Count register number. */
1140 #define COUNT_REGISTER_REGNUM 66
1142 /* Define the classes of registers for register constraints in the
1143 machine description. Also define ranges of constants.
1145 One of the classes must always be named ALL_REGS and include all hard regs.
1146 If there is more than one class, another class must be named NO_REGS
1147 and contain no registers.
1149 The name GENERAL_REGS must be the name of a class (or an alias for
1150 another name such as ALL_REGS). This is the class of registers
1151 that is allowed by "g" or "r" in a register constraint.
1152 Also, registers outside this class are allocated only when
1153 instructions express preferences for them.
1155 The classes must be numbered in nondecreasing order; that is,
1156 a larger-numbered class must never be contained completely
1157 in a smaller-numbered class.
1159 For any two classes, it is very desirable that there be another
1160 class that represents their union. */
1162 /* The RS/6000 has three types of registers, fixed-point, floating-point,
1163 and condition registers, plus three special registers, MQ, CTR, and the
1164 link register. AltiVec adds a vector register class.
1166 However, r0 is special in that it cannot be used as a base register.
1167 So make a class for registers valid as base registers.
1169 Also, cr0 is the only condition code register that can be used in
1170 arithmetic insns, so make a separate class for it. */
1198 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1200 /* Give names of register classes as strings for dump file. */
1202 #define REG_CLASS_NAMES \
1213 "NON_SPECIAL_REGS", \
1217 "LINK_OR_CTR_REGS", \
1219 "SPEC_OR_GEN_REGS", \
1227 /* Define which registers fit in which classes.
1228 This is an initializer for a vector of HARD_REG_SET
1229 of length N_REG_CLASSES. */
1231 #define REG_CLASS_CONTENTS \
1233 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1234 { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \
1235 { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \
1236 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1237 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1238 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1239 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1240 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1241 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1242 { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
1243 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1244 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1245 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1246 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1247 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1248 { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
1249 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1250 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1251 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1252 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1253 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \
1256 /* The same information, inverted:
1257 Return the class number of the smallest class containing
1258 reg number REGNO. This could be a conditional expression
1259 or could index an array. */
1261 #define REGNO_REG_CLASS(REGNO) \
1262 ((REGNO) == 0 ? GENERAL_REGS \
1263 : (REGNO) < 32 ? BASE_REGS \
1264 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1265 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1266 : (REGNO) == CR0_REGNO ? CR0_REGS \
1267 : CR_REGNO_P (REGNO) ? CR_REGS \
1268 : (REGNO) == MQ_REGNO ? MQ_REGS \
1269 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1270 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1271 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1272 : (REGNO) == XER_REGNO ? XER_REGS \
1273 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1274 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1275 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
1276 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
1279 /* The class value for index registers, and the one for base regs. */
1280 #define INDEX_REG_CLASS GENERAL_REGS
1281 #define BASE_REG_CLASS BASE_REGS
1283 /* Get reg_class from a letter such as appears in the machine description. */
1285 #define REG_CLASS_FROM_LETTER(C) \
1286 ((C) == 'f' ? FLOAT_REGS \
1287 : (C) == 'b' ? BASE_REGS \
1288 : (C) == 'h' ? SPECIAL_REGS \
1289 : (C) == 'q' ? MQ_REGS \
1290 : (C) == 'c' ? CTR_REGS \
1291 : (C) == 'l' ? LINK_REGS \
1292 : (C) == 'v' ? ALTIVEC_REGS \
1293 : (C) == 'x' ? CR0_REGS \
1294 : (C) == 'y' ? CR_REGS \
1295 : (C) == 'z' ? XER_REGS \
1298 /* The letters I, J, K, L, M, N, and P in a register constraint string
1299 can be used to stand for particular ranges of immediate operands.
1300 This macro defines what the ranges are.
1301 C is the letter, and VALUE is a constant value.
1302 Return 1 if VALUE is in the range specified by C.
1304 `I' is a signed 16-bit constant
1305 `J' is a constant with only the high-order 16 bits nonzero
1306 `K' is a constant with only the low-order 16 bits nonzero
1307 `L' is a signed 16-bit constant shifted left 16 bits
1308 `M' is a constant that is greater than 31
1309 `N' is a positive constant that is an exact power of two
1310 `O' is the constant zero
1311 `P' is a constant whose negation is a signed 16-bit constant */
1313 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1314 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1315 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1316 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1317 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1318 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1319 : (C) == 'M' ? (VALUE) > 31 \
1320 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1321 : (C) == 'O' ? (VALUE) == 0 \
1322 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1325 /* Similar, but for floating constants, and defining letters G and H.
1326 Here VALUE is the CONST_DOUBLE rtx itself.
1328 We flag for special constants when we can copy the constant into
1329 a general register in two insns for DF/DI and one insn for SF.
1331 'H' is used for DI/DF constants that take 3 insns. */
1333 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1334 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1335 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1336 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1339 /* Optional extra constraints for this machine.
1341 'Q' means that is a memory operand that is just an offset from a reg.
1342 'R' is for AIX TOC entries.
1343 'S' is a constant that can be placed into a 64-bit mask operand
1344 'T' is a constant that can be placed into a 32-bit mask operand
1345 'U' is for V.4 small data references.
1346 'W' is a vector constant that can be easily generated (no mem refs).
1347 'Y' is a indexed or word-aligned displacement memory operand.
1348 't' is for AND masks that can be performed by two rldic{l,r} insns. */
1350 #define EXTRA_CONSTRAINT(OP, C) \
1351 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1352 : (C) == 'R' ? legitimate_constant_pool_address_p (OP) \
1353 : (C) == 'S' ? mask64_operand (OP, DImode) \
1354 : (C) == 'T' ? mask_operand (OP, SImode) \
1355 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
1356 && small_data_operand (OP, GET_MODE (OP))) \
1357 : (C) == 't' ? (mask64_2_operand (OP, DImode) \
1358 && (fixed_regs[CR0_REGNO] \
1359 || !logical_operand (OP, DImode)) \
1360 && !mask64_operand (OP, DImode)) \
1361 : (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP))) \
1362 : (C) == 'Y' ? (word_offset_memref_operand (OP, GET_MODE (OP))) \
1365 /* Define which constraints are memory constraints. Tell reload
1366 that any memory address can be reloaded by copying the
1367 memory address into a base register if required. */
1369 #define EXTRA_MEMORY_CONSTRAINT(C, STR) \
1370 ((C) == 'Q' || (C) == 'Y')
1372 /* Given an rtx X being reloaded into a reg required to be
1373 in class CLASS, return the class of reg to actually use.
1374 In general this is just CLASS; but on some machines
1375 in some cases it is preferable to use a more restrictive class.
1377 On the RS/6000, we have to return NO_REGS when we want to reload a
1378 floating-point CONST_DOUBLE to force it to be copied to memory.
1380 We also don't want to reload integer values into floating-point
1381 registers if we can at all help it. In fact, this can
1382 cause reload to abort, if it tries to generate a reload of CTR
1383 into a FP register and discovers it doesn't have the memory location
1386 ??? Would it be a good idea to have reload do the converse, that is
1387 try to reload floating modes into FP registers if possible?
1390 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1391 (((GET_CODE (X) == CONST_DOUBLE \
1392 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1394 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1395 && (CLASS) == NON_SPECIAL_REGS) \
1399 /* Return the register class of a scratch register needed to copy IN into
1400 or out of a register in CLASS in MODE. If it can be done directly,
1401 NO_REGS is returned. */
1403 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1404 secondary_reload_class (CLASS, MODE, IN)
1406 /* If we are copying between FP or AltiVec registers and anything
1407 else, we need a memory location. */
1409 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1410 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1411 || (CLASS2) == FLOAT_REGS \
1412 || (CLASS1) == ALTIVEC_REGS \
1413 || (CLASS2) == ALTIVEC_REGS))
1415 /* Return the maximum number of consecutive registers
1416 needed to represent mode MODE in a register of class CLASS.
1418 On RS/6000, this is the size of MODE in words,
1419 except in the FP regs, where a single reg is enough for two words. */
1420 #define CLASS_MAX_NREGS(CLASS, MODE) \
1421 (((CLASS) == FLOAT_REGS) \
1422 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1423 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1426 /* Return a class of registers that cannot change FROM mode to TO mode. */
1428 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1429 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) \
1430 && GET_MODE_SIZE (FROM) >= 8 && GET_MODE_SIZE (TO) >= 8) \
1432 : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1433 ? reg_classes_intersect_p (FLOAT_REGS, CLASS) \
1434 : (TARGET_SPE && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1) \
1435 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
1438 /* Stack layout; function entry, exit and calling. */
1440 /* Enumeration to give which calling sequence to use. */
1443 ABI_AIX, /* IBM's AIX */
1444 ABI_V4, /* System V.4/eabi */
1445 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1448 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1450 /* Define this if pushing a word on the stack
1451 makes the stack pointer a smaller address. */
1452 #define STACK_GROWS_DOWNWARD
1454 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1455 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1457 /* Define this if the nominal address of the stack frame
1458 is at the high-address end of the local variables;
1459 that is, each additional local variable allocated
1460 goes at a more negative offset in the frame.
1462 On the RS/6000, we grow upwards, from the area after the outgoing
1464 /* #define FRAME_GROWS_DOWNWARD */
1466 /* Size of the outgoing register save area */
1467 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1468 || DEFAULT_ABI == ABI_DARWIN) \
1469 ? (TARGET_64BIT ? 64 : 32) \
1472 /* Size of the fixed area on the stack */
1473 #define RS6000_SAVE_AREA \
1474 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1475 << (TARGET_64BIT ? 1 : 0))
1477 /* MEM representing address to save the TOC register */
1478 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1479 plus_constant (stack_pointer_rtx, \
1480 (TARGET_32BIT ? 20 : 40)))
1482 /* Size of the V.4 varargs area if needed */
1483 #define RS6000_VARARGS_AREA 0
1485 /* Align an address */
1486 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1488 /* Size of V.4 varargs area in bytes */
1489 #define RS6000_VARARGS_SIZE \
1490 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
1492 /* Offset within stack frame to start allocating local variables at.
1493 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1494 first local allocated. Otherwise, it is the offset to the BEGINNING
1495 of the first local allocated.
1497 On the RS/6000, the frame pointer is the same as the stack pointer,
1498 except for dynamic allocations. So we start after the fixed area and
1499 outgoing parameter area. */
1501 #define STARTING_FRAME_OFFSET \
1502 (RS6000_ALIGN (current_function_outgoing_args_size, \
1503 TARGET_ALTIVEC ? 16 : 8) \
1504 + RS6000_VARARGS_AREA \
1507 /* Offset from the stack pointer register to an item dynamically
1508 allocated on the stack, e.g., by `alloca'.
1510 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1511 length of the outgoing arguments. The default is correct for most
1512 machines. See `function.c' for details. */
1513 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1514 (RS6000_ALIGN (current_function_outgoing_args_size, \
1515 TARGET_ALTIVEC ? 16 : 8) \
1516 + (STACK_POINTER_OFFSET))
1518 /* If we generate an insn to push BYTES bytes,
1519 this says how many the stack pointer really advances by.
1520 On RS/6000, don't define this because there are no push insns. */
1521 /* #define PUSH_ROUNDING(BYTES) */
1523 /* Offset of first parameter from the argument pointer register value.
1524 On the RS/6000, we define the argument pointer to the start of the fixed
1526 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1528 /* Offset from the argument pointer register value to the top of
1529 stack. This is different from FIRST_PARM_OFFSET because of the
1530 register save area. */
1531 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1533 /* Define this if stack space is still allocated for a parameter passed
1534 in a register. The value is the number of bytes allocated to this
1536 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1538 /* Define this if the above stack space is to be considered part of the
1539 space allocated by the caller. */
1540 #define OUTGOING_REG_PARM_STACK_SPACE
1542 /* This is the difference between the logical top of stack and the actual sp.
1544 For the RS/6000, sp points past the fixed area. */
1545 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1547 /* Define this if the maximum size of all the outgoing args is to be
1548 accumulated and pushed during the prologue. The amount can be
1549 found in the variable current_function_outgoing_args_size. */
1550 #define ACCUMULATE_OUTGOING_ARGS 1
1552 /* Value is the number of bytes of arguments automatically
1553 popped when returning from a subroutine call.
1554 FUNDECL is the declaration node of the function (as a tree),
1555 FUNTYPE is the data type of the function (as a tree),
1556 or for a library call it is an identifier node for the subroutine name.
1557 SIZE is the number of bytes of arguments passed on the stack. */
1559 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1561 /* Define how to find the value returned by a function.
1562 VALTYPE is the data type of the value (as a tree).
1563 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1564 otherwise, FUNC is 0. */
1566 #define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC))
1568 /* Define how to find the value returned by a library function
1569 assuming the value has mode MODE. */
1571 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1573 /* DRAFT_V4_STRUCT_RET defaults off. */
1574 #define DRAFT_V4_STRUCT_RET 0
1576 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1577 #define DEFAULT_PCC_STRUCT_RETURN 0
1579 /* Mode of stack savearea.
1580 FUNCTION is VOIDmode because calling convention maintains SP.
1581 BLOCK needs Pmode for SP.
1582 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1583 #define STACK_SAVEAREA_MODE(LEVEL) \
1584 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1585 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1587 /* Minimum and maximum general purpose registers used to hold arguments. */
1588 #define GP_ARG_MIN_REG 3
1589 #define GP_ARG_MAX_REG 10
1590 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1592 /* Minimum and maximum floating point registers used to hold arguments. */
1593 #define FP_ARG_MIN_REG 33
1594 #define FP_ARG_AIX_MAX_REG 45
1595 #define FP_ARG_V4_MAX_REG 40
1596 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1597 || DEFAULT_ABI == ABI_DARWIN) \
1598 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1599 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1601 /* Minimum and maximum AltiVec registers used to hold arguments. */
1602 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1603 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1604 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1606 /* Return registers */
1607 #define GP_ARG_RETURN GP_ARG_MIN_REG
1608 #define FP_ARG_RETURN FP_ARG_MIN_REG
1609 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1611 /* Flags for the call/call_value rtl operations set up by function_arg */
1612 #define CALL_NORMAL 0x00000000 /* no special processing */
1613 /* Bits in 0x00000001 are unused. */
1614 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1615 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1616 #define CALL_LONG 0x00000008 /* always call indirect */
1617 #define CALL_LIBCALL 0x00000010 /* libcall */
1619 /* 1 if N is a possible register number for a function value
1620 as seen by the caller.
1622 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1623 #define FUNCTION_VALUE_REGNO_P(N) \
1624 ((N) == GP_ARG_RETURN \
1625 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT) \
1626 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1628 /* 1 if N is a possible register number for function argument passing.
1629 On RS/6000, these are r3-r10 and fp1-fp13.
1630 On AltiVec, v2 - v13 are used for passing vectors. */
1631 #define FUNCTION_ARG_REGNO_P(N) \
1632 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1633 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1634 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1635 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1636 && TARGET_HARD_FLOAT))
1638 /* A C structure for machine-specific, per-function data.
1639 This is added to the cfun structure. */
1640 typedef struct machine_function GTY(())
1642 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
1643 int ra_needs_full_frame;
1644 /* Some local-dynamic symbol. */
1645 const char *some_ld_name;
1646 /* Whether the instruction chain has been scanned already. */
1647 int insn_chain_scanned_p;
1648 /* Flags if __builtin_return_address (0) was used. */
1652 /* Define a data type for recording info about an argument list
1653 during the scan of that argument list. This data type should
1654 hold all necessary information about the function itself
1655 and about the args processed so far, enough to enable macros
1656 such as FUNCTION_ARG to determine where the next arg should go.
1658 On the RS/6000, this is a structure. The first element is the number of
1659 total argument words, the second is used to store the next
1660 floating-point register number, and the third says how many more args we
1661 have prototype types for.
1663 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1664 the next available GP register, `fregno' is the next available FP
1665 register, and `words' is the number of words used on the stack.
1667 The varargs/stdarg support requires that this structure's size
1668 be a multiple of sizeof(int). */
1670 typedef struct rs6000_args
1672 int words; /* # words used for passing GP registers */
1673 int fregno; /* next available FP register */
1674 int vregno; /* next available AltiVec register */
1675 int nargs_prototype; /* # args left in the current prototype */
1676 int prototype; /* Whether a prototype was defined */
1677 int stdarg; /* Whether function is a stdarg function. */
1678 int call_cookie; /* Do special things for this call */
1679 int sysv_gregno; /* next available GP register */
1682 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1683 for a call to a function whose data type is FNTYPE.
1684 For a library call, FNTYPE is 0. */
1686 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1687 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
1689 /* Similar, but when scanning the definition of a procedure. We always
1690 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1692 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1693 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
1695 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1697 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1698 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
1700 /* Update the data in CUM to advance over an argument
1701 of mode MODE and data type TYPE.
1702 (TYPE is null for libcalls where that information may not be available.) */
1704 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1705 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1707 /* Determine where to put an argument to a function.
1708 Value is zero to push the argument on the stack,
1709 or a hard register in which to store the argument.
1711 MODE is the argument's machine mode.
1712 TYPE is the data type of the argument (as a tree).
1713 This is null for libcalls where that information may
1715 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1716 the preceding args and about the function being called.
1717 NAMED is nonzero if this argument is a named parameter
1718 (otherwise it is an extra parameter matching an ellipsis).
1720 On RS/6000 the first eight words of non-FP are normally in registers
1721 and the rest are pushed. The first 13 FP args are in registers.
1723 If this is floating-point and no prototype is specified, we use
1724 both an FP and integer register (or possibly FP reg and stack). Library
1725 functions (when TYPE is zero) always have the proper types for args,
1726 so we can pass the FP value just in one register. emit_library_function
1727 doesn't support EXPR_LIST anyway. */
1729 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1730 function_arg (&CUM, MODE, TYPE, NAMED)
1732 /* For an arg passed partly in registers and partly in memory,
1733 this is the number of registers used.
1734 For args passed entirely in registers or entirely in memory, zero. */
1736 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1737 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1739 /* If defined, a C expression which determines whether, and in which
1740 direction, to pad out an argument with extra space. The value
1741 should be of type `enum direction': either `upward' to pad above
1742 the argument, `downward' to pad below, or `none' to inhibit
1745 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1747 /* If defined, a C expression that gives the alignment boundary, in bits,
1748 of an argument with the specified mode and type. If it is not defined,
1749 PARM_BOUNDARY is used for all arguments. */
1751 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1752 function_arg_boundary (MODE, TYPE)
1754 /* Implement `va_start' for varargs and stdarg. */
1755 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1756 rs6000_va_start (valist, nextarg)
1758 #define PAD_VARARGS_DOWN \
1759 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1761 /* Output assembler code to FILE to increment profiler label # LABELNO
1762 for profiling a function entry. */
1764 #define FUNCTION_PROFILER(FILE, LABELNO) \
1765 output_function_profiler ((FILE), (LABELNO));
1767 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1768 the stack pointer does not matter. No definition is equivalent to
1771 On the RS/6000, this is nonzero because we can restore the stack from
1772 its backpointer, which we maintain. */
1773 #define EXIT_IGNORE_STACK 1
1775 /* Define this macro as a C expression that is nonzero for registers
1776 that are used by the epilogue or the return' pattern. The stack
1777 and frame pointer registers are already be assumed to be used as
1780 #define EPILOGUE_USES(REGNO) \
1781 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1782 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1783 || (current_function_calls_eh_return \
1788 /* TRAMPOLINE_TEMPLATE deleted */
1790 /* Length in units of the trampoline for entering a nested function. */
1792 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1794 /* Emit RTL insns to initialize the variable parts of a trampoline.
1795 FNADDR is an RTX for the address of the function's pure code.
1796 CXT is an RTX for the static chain value for the function. */
1798 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1799 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1801 /* Definitions for __builtin_return_address and __builtin_frame_address.
1802 __builtin_return_address (0) should give link register (65), enable
1804 /* This should be uncommented, so that the link register is used, but
1805 currently this would result in unmatched insns and spilling fixed
1806 registers so we'll leave it for another day. When these problems are
1807 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1809 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1811 /* Number of bytes into the frame return addresses can be found. See
1812 rs6000_stack_info in rs6000.c for more information on how the different
1813 abi's store the return address. */
1814 #define RETURN_ADDRESS_OFFSET \
1815 ((DEFAULT_ABI == ABI_AIX \
1816 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
1817 (DEFAULT_ABI == ABI_V4) ? 4 : \
1818 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1820 /* The current return address is in link register (65). The return address
1821 of anything farther back is accessed normally at an offset of 8 from the
1823 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1824 (rs6000_return_addr (COUNT, FRAME))
1827 /* Definitions for register eliminations.
1829 We have two registers that can be eliminated on the RS/6000. First, the
1830 frame pointer register can often be eliminated in favor of the stack
1831 pointer register. Secondly, the argument pointer register can always be
1832 eliminated; it is replaced with either the stack or frame pointer.
1834 In addition, we use the elimination mechanism to see if r30 is needed
1835 Initially we assume that it isn't. If it is, we spill it. This is done
1836 by making it an eliminable register. We replace it with itself so that
1837 if it isn't needed, then existing uses won't be modified. */
1839 /* This is an array of structures. Each structure initializes one pair
1840 of eliminable registers. The "from" register number is given first,
1841 followed by "to". Eliminations of the same "from" register are listed
1842 in order of preference. */
1843 #define ELIMINABLE_REGS \
1844 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1845 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1846 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1847 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1849 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1850 Frame pointer elimination is automatically handled.
1852 For the RS/6000, if frame pointer elimination is being done, we would like
1853 to convert ap into fp, not sp.
1855 We need r30 if -mminimal-toc was specified, and there are constant pool
1858 #define CAN_ELIMINATE(FROM, TO) \
1859 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1860 ? ! frame_pointer_needed \
1861 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1862 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1865 /* Define the offset between two registers, one to be eliminated, and the other
1866 its replacement, at the start of a routine. */
1867 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1868 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1870 /* Addressing modes, and classification of registers for them. */
1872 #define HAVE_PRE_DECREMENT 1
1873 #define HAVE_PRE_INCREMENT 1
1875 /* Macros to check register numbers against specific register classes. */
1877 /* These assume that REGNO is a hard or pseudo reg number.
1878 They give nonzero only if REGNO is a hard reg of the suitable class
1879 or a pseudo reg currently allocated to a suitable hard reg.
1880 Since they use reg_renumber, they are safe only once reg_renumber
1881 has been allocated, which happens in local-alloc.c. */
1883 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1884 ((REGNO) < FIRST_PSEUDO_REGISTER \
1885 ? (REGNO) <= 31 || (REGNO) == 67 \
1886 : (reg_renumber[REGNO] >= 0 \
1887 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1889 #define REGNO_OK_FOR_BASE_P(REGNO) \
1890 ((REGNO) < FIRST_PSEUDO_REGISTER \
1891 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1892 : (reg_renumber[REGNO] > 0 \
1893 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1895 /* Maximum number of registers that can appear in a valid memory address. */
1897 #define MAX_REGS_PER_ADDRESS 2
1899 /* Recognize any constant value that is a valid address. */
1901 #define CONSTANT_ADDRESS_P(X) \
1902 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1903 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1904 || GET_CODE (X) == HIGH)
1906 /* Nonzero if the constant value X is a legitimate general operand.
1907 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1909 On the RS/6000, all integer constants are acceptable, most won't be valid
1910 for particular insns, though. Only easy FP constants are
1913 #define LEGITIMATE_CONSTANT_P(X) \
1914 (((GET_CODE (X) != CONST_DOUBLE \
1915 && GET_CODE (X) != CONST_VECTOR) \
1916 || GET_MODE (X) == VOIDmode \
1917 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1918 || easy_fp_constant (X, GET_MODE (X)) \
1919 || easy_vector_constant (X, GET_MODE (X))) \
1920 && !rs6000_tls_referenced_p (X))
1922 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1923 and check its validity for a certain class.
1924 We have two alternate definitions for each of them.
1925 The usual definition accepts all pseudo regs; the other rejects
1926 them unless they have been allocated suitable hard regs.
1927 The symbol REG_OK_STRICT causes the latter definition to be used.
1929 Most source files want to accept pseudo regs in the hope that
1930 they will get allocated to the class that the insn wants them to be in.
1931 Source files for reload pass need to be strict.
1932 After reload, it makes no difference, since pseudo regs have
1933 been eliminated by then. */
1935 #ifdef REG_OK_STRICT
1936 # define REG_OK_STRICT_FLAG 1
1938 # define REG_OK_STRICT_FLAG 0
1941 /* Nonzero if X is a hard reg that can be used as an index
1942 or if it is a pseudo reg in the non-strict case. */
1943 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1945 && (REGNO (X) <= 31 \
1946 || REGNO (X) == ARG_POINTER_REGNUM \
1947 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
1948 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
1950 /* Nonzero if X is a hard reg that can be used as a base reg
1951 or if it is a pseudo reg in the non-strict case. */
1952 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1953 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
1955 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
1956 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
1958 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1959 that is a valid memory address for an instruction.
1960 The MODE argument is the machine mode for the MEM expression
1961 that wants to use this address.
1963 On the RS/6000, there are four valid address: a SYMBOL_REF that
1964 refers to a constant pool entry of an address (or the sum of it
1965 plus a constant), a short (16-bit signed) constant plus a register,
1966 the sum of two registers, or a register indirect, possibly with an
1967 auto-increment. For DFmode and DImode with a constant plus register,
1968 we must ensure that both words are addressable or PowerPC64 with offset
1971 For modes spanning multiple registers (DFmode in 32-bit GPRs,
1972 32-bit DImode, TImode), indexed addressing cannot be used because
1973 adjacent memory cells are accessed by adding word-sized offsets
1974 during assembly output. */
1976 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1977 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
1981 /* Try machine-dependent ways of modifying an illegitimate address
1982 to be legitimate. If we find one, return the new, valid address.
1983 This macro is used in only one place: `memory_address' in explow.c.
1985 OLDX is the address as it was before break_out_memory_refs was called.
1986 In some cases it is useful to look at this to decide what needs to be done.
1988 MODE and WIN are passed so that this macro can use
1989 GO_IF_LEGITIMATE_ADDRESS.
1991 It is always safe for this macro to do nothing. It exists to recognize
1992 opportunities to optimize the output.
1994 On RS/6000, first check for the sum of a register with a constant
1995 integer that is out of range. If so, generate code to add the
1996 constant with the low-order 16 bits masked to the register and force
1997 this result into another register (this can be done with `cau').
1998 Then generate an address of REG+(CONST&0xffff), allowing for the
1999 possibility of bit 16 being a one.
2001 Then check for the sum of a register and something not constant, try to
2002 load the other things into a register and return the sum. */
2004 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2005 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
2006 if (result != NULL_RTX) \
2013 /* Try a machine-dependent way of reloading an illegitimate address
2014 operand. If we find one, push the reload and jump to WIN. This
2015 macro is used in only one place: `find_reloads_address' in reload.c.
2017 Implemented on rs6000 by rs6000_legitimize_reload_address.
2018 Note that (X) is evaluated twice; this is safe in current usage. */
2020 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2023 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
2024 (int)(TYPE), (IND_LEVELS), &win); \
2029 /* Go to LABEL if ADDR (a legitimate address expression)
2030 has an effect that depends on the machine mode it is used for. */
2032 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2034 if (rs6000_mode_dependent_address (ADDR)) \
2038 /* The register number of the register used to address a table of
2039 static data addresses in memory. In some cases this register is
2040 defined by a processor's "application binary interface" (ABI).
2041 When this macro is defined, RTL is generated for this register
2042 once, as with the stack pointer and frame pointer registers. If
2043 this macro is not defined, it is up to the machine-dependent files
2044 to allocate such a register (if necessary). */
2046 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
2047 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
2049 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
2051 /* Define this macro if the register defined by
2052 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
2053 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
2055 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
2057 /* By generating position-independent code, when two different
2058 programs (A and B) share a common library (libC.a), the text of
2059 the library can be shared whether or not the library is linked at
2060 the same address for both programs. In some of these
2061 environments, position-independent code requires not only the use
2062 of different addressing modes, but also special code to enable the
2063 use of these addressing modes.
2065 The `FINALIZE_PIC' macro serves as a hook to emit these special
2066 codes once the function is being compiled into assembly code, but
2067 not before. (It is not done before, because in the case of
2068 compiling an inline function, it would lead to multiple PIC
2069 prologues being included in functions which used inline functions
2070 and were compiled to assembly language.) */
2072 /* #define FINALIZE_PIC */
2074 /* A C expression that is nonzero if X is a legitimate immediate
2075 operand on the target machine when generating position independent
2076 code. You can assume that X satisfies `CONSTANT_P', so you need
2077 not check this. You can also assume FLAG_PIC is true, so you need
2078 not check it either. You need not define this macro if all
2079 constants (including `SYMBOL_REF') can be immediate operands when
2080 generating position independent code. */
2082 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2084 /* Define this if some processing needs to be done immediately before
2085 emitting code for an insn. */
2087 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
2089 /* Specify the machine mode that this machine uses
2090 for the index in the tablejump instruction. */
2091 #define CASE_VECTOR_MODE SImode
2093 /* Define as C expression which evaluates to nonzero if the tablejump
2094 instruction expects the table to contain offsets from the address of the
2096 Do not define this if the table should contain absolute addresses. */
2097 #define CASE_VECTOR_PC_RELATIVE 1
2099 /* Define this as 1 if `char' should by default be signed; else as 0. */
2100 #define DEFAULT_SIGNED_CHAR 0
2102 /* This flag, if defined, says the same insns that convert to a signed fixnum
2103 also convert validly to an unsigned one. */
2105 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
2107 /* An integer expression for the size in bits of the largest integer machine
2108 mode that should actually be used. */
2110 /* Allow pairs of registers to be used, which is the intent of the default. */
2111 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
2113 /* Max number of bytes we can move from memory to memory
2114 in one reasonably fast instruction. */
2115 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2116 #define MAX_MOVE_MAX 8
2118 /* Nonzero if access to memory by bytes is no faster than for words.
2119 Also nonzero if doing byte operations (specifically shifts) in registers
2121 #define SLOW_BYTE_ACCESS 1
2123 /* Define if operations between registers always perform the operation
2124 on the full register even if a narrower mode is specified. */
2125 #define WORD_REGISTER_OPERATIONS
2127 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2128 will either zero-extend or sign-extend. The value of this macro should
2129 be the code that says which one of the two operations is implicitly
2130 done, UNKNOWN if none. */
2131 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2133 /* Define if loading short immediate values into registers sign extends. */
2134 #define SHORT_IMMEDIATES_SIGN_EXTEND
2136 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2137 is done just by pretending it is already truncated. */
2138 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2140 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
2141 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2142 ((VALUE) = ((MODE) == SImode ? 32 : 64))
2144 /* The CTZ patterns return -1 for input of zero. */
2145 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1)
2147 /* Specify the machine mode that pointers have.
2148 After generation of rtl, the compiler makes no further distinction
2149 between pointers and any other objects of this machine mode. */
2150 #define Pmode (TARGET_32BIT ? SImode : DImode)
2152 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
2153 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
2155 /* Mode of a function address in a call instruction (for indexing purposes).
2156 Doesn't matter on RS/6000. */
2157 #define FUNCTION_MODE SImode
2159 /* Define this if addresses of constant functions
2160 shouldn't be put through pseudo regs where they can be cse'd.
2161 Desirable on machines where ordinary constants are expensive
2162 but a CALL with constant address is cheap. */
2163 #define NO_FUNCTION_CSE
2165 /* Define this to be nonzero if shift instructions ignore all but the low-order
2168 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2169 have been dropped from the PowerPC architecture. */
2171 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2173 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2174 should be adjusted to reflect any required changes. This macro is used when
2175 there is some systematic length adjustment required that would be difficult
2176 to express in the length attribute. */
2178 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2180 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2181 COMPARE, return the mode to be used for the comparison. For
2182 floating-point, CCFPmode should be used. CCUNSmode should be used
2183 for unsigned comparisons. CCEQmode should be used when we are
2184 doing an inequality comparison on the result of a
2185 comparison. CCmode should be used in all other cases. */
2187 #define SELECT_CC_MODE(OP,X,Y) \
2188 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2189 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2190 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
2191 ? CCEQmode : CCmode))
2193 /* Can the condition code MODE be safely reversed? This is safe in
2194 all cases on this port, because at present it doesn't use the
2195 trapping FP comparisons (fcmpo). */
2196 #define REVERSIBLE_CC_MODE(MODE) 1
2198 /* Given a condition code and a mode, return the inverse condition. */
2199 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
2201 /* Define the information needed to generate branch and scc insns. This is
2202 stored from the compare operation. */
2204 extern GTY(()) rtx rs6000_compare_op0;
2205 extern GTY(()) rtx rs6000_compare_op1;
2206 extern int rs6000_compare_fp_p;
2208 /* Control the assembler format that we output. */
2210 /* A C string constant describing how to begin a comment in the target
2211 assembler language. The compiler assumes that the comment will end at
2212 the end of the line. */
2213 #define ASM_COMMENT_START " #"
2215 /* Flag to say the TOC is initialized */
2216 extern int toc_initialized;
2218 /* Macro to output a special constant pool entry. Go to WIN if we output
2219 it. Otherwise, it is written the usual way.
2221 On the RS/6000, toc entries are handled this way. */
2223 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2224 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2226 output_toc (FILE, X, LABELNO, MODE); \
2231 #ifdef HAVE_GAS_WEAK
2232 #define RS6000_WEAK 1
2234 #define RS6000_WEAK 0
2238 /* Used in lieu of ASM_WEAKEN_LABEL. */
2239 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2242 fputs ("\t.weak\t", (FILE)); \
2243 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2244 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2245 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2248 fputs ("[DS]", (FILE)); \
2249 fputs ("\n\t.weak\t.", (FILE)); \
2250 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2252 fputc ('\n', (FILE)); \
2255 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2256 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2257 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2259 fputs ("\t.set\t.", (FILE)); \
2260 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2261 fputs (",.", (FILE)); \
2262 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2263 fputc ('\n', (FILE)); \
2270 /* This implements the `alias' attribute. */
2271 #undef ASM_OUTPUT_DEF_FROM_DECLS
2272 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2275 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2276 const char *name = IDENTIFIER_POINTER (TARGET); \
2277 if (TREE_CODE (DECL) == FUNCTION_DECL \
2278 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2280 if (TREE_PUBLIC (DECL)) \
2282 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2284 fputs ("\t.globl\t.", FILE); \
2285 RS6000_OUTPUT_BASENAME (FILE, alias); \
2286 putc ('\n', FILE); \
2289 else if (TARGET_XCOFF) \
2291 fputs ("\t.lglobl\t.", FILE); \
2292 RS6000_OUTPUT_BASENAME (FILE, alias); \
2293 putc ('\n', FILE); \
2295 fputs ("\t.set\t.", FILE); \
2296 RS6000_OUTPUT_BASENAME (FILE, alias); \
2297 fputs (",.", FILE); \
2298 RS6000_OUTPUT_BASENAME (FILE, name); \
2299 fputc ('\n', FILE); \
2301 ASM_OUTPUT_DEF (FILE, alias, name); \
2305 #define TARGET_ASM_FILE_START rs6000_file_start
2307 /* Output to assembler file text saying following lines
2308 may contain character constants, extra white space, comments, etc. */
2310 #define ASM_APP_ON ""
2312 /* Output to assembler file text saying following lines
2313 no longer contain unusual constructs. */
2315 #define ASM_APP_OFF ""
2317 /* How to refer to registers in assembler output.
2318 This sequence is indexed by compiler's hard-register-number (see above). */
2320 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2322 #define REGISTER_NAMES \
2324 &rs6000_reg_names[ 0][0], /* r0 */ \
2325 &rs6000_reg_names[ 1][0], /* r1 */ \
2326 &rs6000_reg_names[ 2][0], /* r2 */ \
2327 &rs6000_reg_names[ 3][0], /* r3 */ \
2328 &rs6000_reg_names[ 4][0], /* r4 */ \
2329 &rs6000_reg_names[ 5][0], /* r5 */ \
2330 &rs6000_reg_names[ 6][0], /* r6 */ \
2331 &rs6000_reg_names[ 7][0], /* r7 */ \
2332 &rs6000_reg_names[ 8][0], /* r8 */ \
2333 &rs6000_reg_names[ 9][0], /* r9 */ \
2334 &rs6000_reg_names[10][0], /* r10 */ \
2335 &rs6000_reg_names[11][0], /* r11 */ \
2336 &rs6000_reg_names[12][0], /* r12 */ \
2337 &rs6000_reg_names[13][0], /* r13 */ \
2338 &rs6000_reg_names[14][0], /* r14 */ \
2339 &rs6000_reg_names[15][0], /* r15 */ \
2340 &rs6000_reg_names[16][0], /* r16 */ \
2341 &rs6000_reg_names[17][0], /* r17 */ \
2342 &rs6000_reg_names[18][0], /* r18 */ \
2343 &rs6000_reg_names[19][0], /* r19 */ \
2344 &rs6000_reg_names[20][0], /* r20 */ \
2345 &rs6000_reg_names[21][0], /* r21 */ \
2346 &rs6000_reg_names[22][0], /* r22 */ \
2347 &rs6000_reg_names[23][0], /* r23 */ \
2348 &rs6000_reg_names[24][0], /* r24 */ \
2349 &rs6000_reg_names[25][0], /* r25 */ \
2350 &rs6000_reg_names[26][0], /* r26 */ \
2351 &rs6000_reg_names[27][0], /* r27 */ \
2352 &rs6000_reg_names[28][0], /* r28 */ \
2353 &rs6000_reg_names[29][0], /* r29 */ \
2354 &rs6000_reg_names[30][0], /* r30 */ \
2355 &rs6000_reg_names[31][0], /* r31 */ \
2357 &rs6000_reg_names[32][0], /* fr0 */ \
2358 &rs6000_reg_names[33][0], /* fr1 */ \
2359 &rs6000_reg_names[34][0], /* fr2 */ \
2360 &rs6000_reg_names[35][0], /* fr3 */ \
2361 &rs6000_reg_names[36][0], /* fr4 */ \
2362 &rs6000_reg_names[37][0], /* fr5 */ \
2363 &rs6000_reg_names[38][0], /* fr6 */ \
2364 &rs6000_reg_names[39][0], /* fr7 */ \
2365 &rs6000_reg_names[40][0], /* fr8 */ \
2366 &rs6000_reg_names[41][0], /* fr9 */ \
2367 &rs6000_reg_names[42][0], /* fr10 */ \
2368 &rs6000_reg_names[43][0], /* fr11 */ \
2369 &rs6000_reg_names[44][0], /* fr12 */ \
2370 &rs6000_reg_names[45][0], /* fr13 */ \
2371 &rs6000_reg_names[46][0], /* fr14 */ \
2372 &rs6000_reg_names[47][0], /* fr15 */ \
2373 &rs6000_reg_names[48][0], /* fr16 */ \
2374 &rs6000_reg_names[49][0], /* fr17 */ \
2375 &rs6000_reg_names[50][0], /* fr18 */ \
2376 &rs6000_reg_names[51][0], /* fr19 */ \
2377 &rs6000_reg_names[52][0], /* fr20 */ \
2378 &rs6000_reg_names[53][0], /* fr21 */ \
2379 &rs6000_reg_names[54][0], /* fr22 */ \
2380 &rs6000_reg_names[55][0], /* fr23 */ \
2381 &rs6000_reg_names[56][0], /* fr24 */ \
2382 &rs6000_reg_names[57][0], /* fr25 */ \
2383 &rs6000_reg_names[58][0], /* fr26 */ \
2384 &rs6000_reg_names[59][0], /* fr27 */ \
2385 &rs6000_reg_names[60][0], /* fr28 */ \
2386 &rs6000_reg_names[61][0], /* fr29 */ \
2387 &rs6000_reg_names[62][0], /* fr30 */ \
2388 &rs6000_reg_names[63][0], /* fr31 */ \
2390 &rs6000_reg_names[64][0], /* mq */ \
2391 &rs6000_reg_names[65][0], /* lr */ \
2392 &rs6000_reg_names[66][0], /* ctr */ \
2393 &rs6000_reg_names[67][0], /* ap */ \
2395 &rs6000_reg_names[68][0], /* cr0 */ \
2396 &rs6000_reg_names[69][0], /* cr1 */ \
2397 &rs6000_reg_names[70][0], /* cr2 */ \
2398 &rs6000_reg_names[71][0], /* cr3 */ \
2399 &rs6000_reg_names[72][0], /* cr4 */ \
2400 &rs6000_reg_names[73][0], /* cr5 */ \
2401 &rs6000_reg_names[74][0], /* cr6 */ \
2402 &rs6000_reg_names[75][0], /* cr7 */ \
2404 &rs6000_reg_names[76][0], /* xer */ \
2406 &rs6000_reg_names[77][0], /* v0 */ \
2407 &rs6000_reg_names[78][0], /* v1 */ \
2408 &rs6000_reg_names[79][0], /* v2 */ \
2409 &rs6000_reg_names[80][0], /* v3 */ \
2410 &rs6000_reg_names[81][0], /* v4 */ \
2411 &rs6000_reg_names[82][0], /* v5 */ \
2412 &rs6000_reg_names[83][0], /* v6 */ \
2413 &rs6000_reg_names[84][0], /* v7 */ \
2414 &rs6000_reg_names[85][0], /* v8 */ \
2415 &rs6000_reg_names[86][0], /* v9 */ \
2416 &rs6000_reg_names[87][0], /* v10 */ \
2417 &rs6000_reg_names[88][0], /* v11 */ \
2418 &rs6000_reg_names[89][0], /* v12 */ \
2419 &rs6000_reg_names[90][0], /* v13 */ \
2420 &rs6000_reg_names[91][0], /* v14 */ \
2421 &rs6000_reg_names[92][0], /* v15 */ \
2422 &rs6000_reg_names[93][0], /* v16 */ \
2423 &rs6000_reg_names[94][0], /* v17 */ \
2424 &rs6000_reg_names[95][0], /* v18 */ \
2425 &rs6000_reg_names[96][0], /* v19 */ \
2426 &rs6000_reg_names[97][0], /* v20 */ \
2427 &rs6000_reg_names[98][0], /* v21 */ \
2428 &rs6000_reg_names[99][0], /* v22 */ \
2429 &rs6000_reg_names[100][0], /* v23 */ \
2430 &rs6000_reg_names[101][0], /* v24 */ \
2431 &rs6000_reg_names[102][0], /* v25 */ \
2432 &rs6000_reg_names[103][0], /* v26 */ \
2433 &rs6000_reg_names[104][0], /* v27 */ \
2434 &rs6000_reg_names[105][0], /* v28 */ \
2435 &rs6000_reg_names[106][0], /* v29 */ \
2436 &rs6000_reg_names[107][0], /* v30 */ \
2437 &rs6000_reg_names[108][0], /* v31 */ \
2438 &rs6000_reg_names[109][0], /* vrsave */ \
2439 &rs6000_reg_names[110][0], /* vscr */ \
2440 &rs6000_reg_names[111][0], /* spe_acc */ \
2441 &rs6000_reg_names[112][0], /* spefscr */ \
2444 /* Table of additional register names to use in user input. */
2446 #define ADDITIONAL_REGISTER_NAMES \
2447 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2448 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2449 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2450 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2451 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2452 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2453 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2454 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2455 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2456 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2457 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2458 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2459 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2460 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2461 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2462 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2463 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2464 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2465 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2466 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2467 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2468 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2469 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2470 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2471 {"vrsave", 109}, {"vscr", 110}, \
2472 {"spe_acc", 111}, {"spefscr", 112}, \
2473 /* no additional names for: mq, lr, ctr, ap */ \
2474 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2475 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2476 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2478 /* Text to write out after a CALL that may be replaced by glue code by
2479 the loader. This depends on the AIX version. */
2480 #define RS6000_CALL_GLUE "cror 31,31,31"
2482 /* This is how to output an element of a case-vector that is relative. */
2484 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2485 do { char buf[100]; \
2486 fputs ("\t.long ", FILE); \
2487 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2488 assemble_name (FILE, buf); \
2490 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2491 assemble_name (FILE, buf); \
2492 putc ('\n', FILE); \
2495 /* This is how to output an assembler line
2496 that says to advance the location counter
2497 to a multiple of 2**LOG bytes. */
2499 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2501 fprintf (FILE, "\t.align %d\n", (LOG))
2503 /* Pick up the return address upon entry to a procedure. Used for
2504 dwarf2 unwind information. This also enables the table driven
2507 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2508 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2510 /* Describe how we implement __builtin_eh_return. */
2511 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2512 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2514 /* Print operand X (an rtx) in assembler syntax to file FILE.
2515 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2516 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2518 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2520 /* Define which CODE values are valid. */
2522 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2523 ((CODE) == '.' || (CODE) == '&')
2525 /* Print a memory address as an operand to reference that memory location. */
2527 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2529 /* Define the codes that are matched by predicates in rs6000.c. */
2531 #define PREDICATE_CODES \
2532 {"any_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2533 LABEL_REF, SUBREG, REG, MEM}}, \
2534 {"any_parallel_operand", {PARALLEL}}, \
2535 {"zero_constant", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2536 LABEL_REF, SUBREG, REG, MEM}}, \
2537 {"short_cint_operand", {CONST_INT}}, \
2538 {"u_short_cint_operand", {CONST_INT}}, \
2539 {"non_short_cint_operand", {CONST_INT}}, \
2540 {"exact_log2_cint_operand", {CONST_INT}}, \
2541 {"gpc_reg_operand", {SUBREG, REG}}, \
2542 {"cc_reg_operand", {SUBREG, REG}}, \
2543 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
2544 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
2545 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
2546 {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \
2547 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
2548 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2549 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
2550 {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2551 {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2552 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2553 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2554 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
2555 {"easy_fp_constant", {CONST_DOUBLE}}, \
2556 {"easy_vector_constant", {CONST_VECTOR}}, \
2557 {"easy_vector_constant_add_self", {CONST_VECTOR}}, \
2558 {"zero_fp_constant", {CONST_DOUBLE}}, \
2559 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
2560 {"lwa_operand", {SUBREG, MEM, REG}}, \
2561 {"volatile_mem_operand", {MEM}}, \
2562 {"offsettable_mem_operand", {MEM}}, \
2563 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
2564 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2565 {"non_add_cint_operand", {CONST_INT}}, \
2566 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2567 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2568 {"and64_2_operand", {SUBREG, REG, CONST_INT}}, \
2569 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2570 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
2571 {"mask_operand", {CONST_INT}}, \
2572 {"mask_operand_wrap", {CONST_INT}}, \
2573 {"mask64_operand", {CONST_INT}}, \
2574 {"mask64_2_operand", {CONST_INT}}, \
2575 {"count_register_operand", {REG}}, \
2576 {"xer_operand", {REG}}, \
2577 {"symbol_ref_operand", {SYMBOL_REF}}, \
2578 {"rs6000_tls_symbol_ref", {SYMBOL_REF}}, \
2579 {"call_operand", {SYMBOL_REF, REG}}, \
2580 {"current_file_function_operand", {SYMBOL_REF}}, \
2581 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \
2582 CONST_DOUBLE, SYMBOL_REF}}, \
2583 {"load_multiple_operation", {PARALLEL}}, \
2584 {"store_multiple_operation", {PARALLEL}}, \
2585 {"lmw_operation", {PARALLEL}}, \
2586 {"stmw_operation", {PARALLEL}}, \
2587 {"vrsave_operation", {PARALLEL}}, \
2588 {"save_world_operation", {PARALLEL}}, \
2589 {"restore_world_operation", {PARALLEL}}, \
2590 {"mfcr_operation", {PARALLEL}}, \
2591 {"mtcrf_operation", {PARALLEL}}, \
2592 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
2593 GT, LEU, LTU, GEU, GTU, \
2594 UNORDERED, ORDERED, \
2596 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \
2598 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
2599 GT, LEU, LTU, GEU, GTU, \
2600 UNORDERED, ORDERED, \
2602 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
2603 GT, LEU, LTU, GEU, GTU}}, \
2604 {"boolean_operator", {AND, IOR, XOR}}, \
2605 {"boolean_or_operator", {IOR, XOR}}, \
2606 {"altivec_register_operand", {REG}}, \
2607 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
2609 /* uncomment for disabling the corresponding default options */
2610 /* #define MACHINE_no_sched_interblock */
2611 /* #define MACHINE_no_sched_speculative */
2612 /* #define MACHINE_no_sched_speculative_load */
2614 /* General flags. */
2615 extern int flag_pic;
2616 extern int optimize;
2617 extern int flag_expensive_optimizations;
2618 extern int frame_pointer_needed;
2620 enum rs6000_builtins
2622 /* AltiVec builtins. */
2623 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2624 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2625 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2626 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2627 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2628 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2629 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2630 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2631 ALTIVEC_BUILTIN_VADDUBM,
2632 ALTIVEC_BUILTIN_VADDUHM,
2633 ALTIVEC_BUILTIN_VADDUWM,
2634 ALTIVEC_BUILTIN_VADDFP,
2635 ALTIVEC_BUILTIN_VADDCUW,
2636 ALTIVEC_BUILTIN_VADDUBS,
2637 ALTIVEC_BUILTIN_VADDSBS,
2638 ALTIVEC_BUILTIN_VADDUHS,
2639 ALTIVEC_BUILTIN_VADDSHS,
2640 ALTIVEC_BUILTIN_VADDUWS,
2641 ALTIVEC_BUILTIN_VADDSWS,
2642 ALTIVEC_BUILTIN_VAND,
2643 ALTIVEC_BUILTIN_VANDC,
2644 ALTIVEC_BUILTIN_VAVGUB,
2645 ALTIVEC_BUILTIN_VAVGSB,
2646 ALTIVEC_BUILTIN_VAVGUH,
2647 ALTIVEC_BUILTIN_VAVGSH,
2648 ALTIVEC_BUILTIN_VAVGUW,
2649 ALTIVEC_BUILTIN_VAVGSW,
2650 ALTIVEC_BUILTIN_VCFUX,
2651 ALTIVEC_BUILTIN_VCFSX,
2652 ALTIVEC_BUILTIN_VCTSXS,
2653 ALTIVEC_BUILTIN_VCTUXS,
2654 ALTIVEC_BUILTIN_VCMPBFP,
2655 ALTIVEC_BUILTIN_VCMPEQUB,
2656 ALTIVEC_BUILTIN_VCMPEQUH,
2657 ALTIVEC_BUILTIN_VCMPEQUW,
2658 ALTIVEC_BUILTIN_VCMPEQFP,
2659 ALTIVEC_BUILTIN_VCMPGEFP,
2660 ALTIVEC_BUILTIN_VCMPGTUB,
2661 ALTIVEC_BUILTIN_VCMPGTSB,
2662 ALTIVEC_BUILTIN_VCMPGTUH,
2663 ALTIVEC_BUILTIN_VCMPGTSH,
2664 ALTIVEC_BUILTIN_VCMPGTUW,
2665 ALTIVEC_BUILTIN_VCMPGTSW,
2666 ALTIVEC_BUILTIN_VCMPGTFP,
2667 ALTIVEC_BUILTIN_VEXPTEFP,
2668 ALTIVEC_BUILTIN_VLOGEFP,
2669 ALTIVEC_BUILTIN_VMADDFP,
2670 ALTIVEC_BUILTIN_VMAXUB,
2671 ALTIVEC_BUILTIN_VMAXSB,
2672 ALTIVEC_BUILTIN_VMAXUH,
2673 ALTIVEC_BUILTIN_VMAXSH,
2674 ALTIVEC_BUILTIN_VMAXUW,
2675 ALTIVEC_BUILTIN_VMAXSW,
2676 ALTIVEC_BUILTIN_VMAXFP,
2677 ALTIVEC_BUILTIN_VMHADDSHS,
2678 ALTIVEC_BUILTIN_VMHRADDSHS,
2679 ALTIVEC_BUILTIN_VMLADDUHM,
2680 ALTIVEC_BUILTIN_VMRGHB,
2681 ALTIVEC_BUILTIN_VMRGHH,
2682 ALTIVEC_BUILTIN_VMRGHW,
2683 ALTIVEC_BUILTIN_VMRGLB,
2684 ALTIVEC_BUILTIN_VMRGLH,
2685 ALTIVEC_BUILTIN_VMRGLW,
2686 ALTIVEC_BUILTIN_VMSUMUBM,
2687 ALTIVEC_BUILTIN_VMSUMMBM,
2688 ALTIVEC_BUILTIN_VMSUMUHM,
2689 ALTIVEC_BUILTIN_VMSUMSHM,
2690 ALTIVEC_BUILTIN_VMSUMUHS,
2691 ALTIVEC_BUILTIN_VMSUMSHS,
2692 ALTIVEC_BUILTIN_VMINUB,
2693 ALTIVEC_BUILTIN_VMINSB,
2694 ALTIVEC_BUILTIN_VMINUH,
2695 ALTIVEC_BUILTIN_VMINSH,
2696 ALTIVEC_BUILTIN_VMINUW,
2697 ALTIVEC_BUILTIN_VMINSW,
2698 ALTIVEC_BUILTIN_VMINFP,
2699 ALTIVEC_BUILTIN_VMULEUB,
2700 ALTIVEC_BUILTIN_VMULESB,
2701 ALTIVEC_BUILTIN_VMULEUH,
2702 ALTIVEC_BUILTIN_VMULESH,
2703 ALTIVEC_BUILTIN_VMULOUB,
2704 ALTIVEC_BUILTIN_VMULOSB,
2705 ALTIVEC_BUILTIN_VMULOUH,
2706 ALTIVEC_BUILTIN_VMULOSH,
2707 ALTIVEC_BUILTIN_VNMSUBFP,
2708 ALTIVEC_BUILTIN_VNOR,
2709 ALTIVEC_BUILTIN_VOR,
2710 ALTIVEC_BUILTIN_VSEL_4SI,
2711 ALTIVEC_BUILTIN_VSEL_4SF,
2712 ALTIVEC_BUILTIN_VSEL_8HI,
2713 ALTIVEC_BUILTIN_VSEL_16QI,
2714 ALTIVEC_BUILTIN_VPERM_4SI,
2715 ALTIVEC_BUILTIN_VPERM_4SF,
2716 ALTIVEC_BUILTIN_VPERM_8HI,
2717 ALTIVEC_BUILTIN_VPERM_16QI,
2718 ALTIVEC_BUILTIN_VPKUHUM,
2719 ALTIVEC_BUILTIN_VPKUWUM,
2720 ALTIVEC_BUILTIN_VPKPX,
2721 ALTIVEC_BUILTIN_VPKUHSS,
2722 ALTIVEC_BUILTIN_VPKSHSS,
2723 ALTIVEC_BUILTIN_VPKUWSS,
2724 ALTIVEC_BUILTIN_VPKSWSS,
2725 ALTIVEC_BUILTIN_VPKUHUS,
2726 ALTIVEC_BUILTIN_VPKSHUS,
2727 ALTIVEC_BUILTIN_VPKUWUS,
2728 ALTIVEC_BUILTIN_VPKSWUS,
2729 ALTIVEC_BUILTIN_VREFP,
2730 ALTIVEC_BUILTIN_VRFIM,
2731 ALTIVEC_BUILTIN_VRFIN,
2732 ALTIVEC_BUILTIN_VRFIP,
2733 ALTIVEC_BUILTIN_VRFIZ,
2734 ALTIVEC_BUILTIN_VRLB,
2735 ALTIVEC_BUILTIN_VRLH,
2736 ALTIVEC_BUILTIN_VRLW,
2737 ALTIVEC_BUILTIN_VRSQRTEFP,
2738 ALTIVEC_BUILTIN_VSLB,
2739 ALTIVEC_BUILTIN_VSLH,
2740 ALTIVEC_BUILTIN_VSLW,
2741 ALTIVEC_BUILTIN_VSL,
2742 ALTIVEC_BUILTIN_VSLO,
2743 ALTIVEC_BUILTIN_VSPLTB,
2744 ALTIVEC_BUILTIN_VSPLTH,
2745 ALTIVEC_BUILTIN_VSPLTW,
2746 ALTIVEC_BUILTIN_VSPLTISB,
2747 ALTIVEC_BUILTIN_VSPLTISH,
2748 ALTIVEC_BUILTIN_VSPLTISW,
2749 ALTIVEC_BUILTIN_VSRB,
2750 ALTIVEC_BUILTIN_VSRH,
2751 ALTIVEC_BUILTIN_VSRW,
2752 ALTIVEC_BUILTIN_VSRAB,
2753 ALTIVEC_BUILTIN_VSRAH,
2754 ALTIVEC_BUILTIN_VSRAW,
2755 ALTIVEC_BUILTIN_VSR,
2756 ALTIVEC_BUILTIN_VSRO,
2757 ALTIVEC_BUILTIN_VSUBUBM,
2758 ALTIVEC_BUILTIN_VSUBUHM,
2759 ALTIVEC_BUILTIN_VSUBUWM,
2760 ALTIVEC_BUILTIN_VSUBFP,
2761 ALTIVEC_BUILTIN_VSUBCUW,
2762 ALTIVEC_BUILTIN_VSUBUBS,
2763 ALTIVEC_BUILTIN_VSUBSBS,
2764 ALTIVEC_BUILTIN_VSUBUHS,
2765 ALTIVEC_BUILTIN_VSUBSHS,
2766 ALTIVEC_BUILTIN_VSUBUWS,
2767 ALTIVEC_BUILTIN_VSUBSWS,
2768 ALTIVEC_BUILTIN_VSUM4UBS,
2769 ALTIVEC_BUILTIN_VSUM4SBS,
2770 ALTIVEC_BUILTIN_VSUM4SHS,
2771 ALTIVEC_BUILTIN_VSUM2SWS,
2772 ALTIVEC_BUILTIN_VSUMSWS,
2773 ALTIVEC_BUILTIN_VXOR,
2774 ALTIVEC_BUILTIN_VSLDOI_16QI,
2775 ALTIVEC_BUILTIN_VSLDOI_8HI,
2776 ALTIVEC_BUILTIN_VSLDOI_4SI,
2777 ALTIVEC_BUILTIN_VSLDOI_4SF,
2778 ALTIVEC_BUILTIN_VUPKHSB,
2779 ALTIVEC_BUILTIN_VUPKHPX,
2780 ALTIVEC_BUILTIN_VUPKHSH,
2781 ALTIVEC_BUILTIN_VUPKLSB,
2782 ALTIVEC_BUILTIN_VUPKLPX,
2783 ALTIVEC_BUILTIN_VUPKLSH,
2784 ALTIVEC_BUILTIN_MTVSCR,
2785 ALTIVEC_BUILTIN_MFVSCR,
2786 ALTIVEC_BUILTIN_DSSALL,
2787 ALTIVEC_BUILTIN_DSS,
2788 ALTIVEC_BUILTIN_LVSL,
2789 ALTIVEC_BUILTIN_LVSR,
2790 ALTIVEC_BUILTIN_DSTT,
2791 ALTIVEC_BUILTIN_DSTST,
2792 ALTIVEC_BUILTIN_DSTSTT,
2793 ALTIVEC_BUILTIN_DST,
2794 ALTIVEC_BUILTIN_LVEBX,
2795 ALTIVEC_BUILTIN_LVEHX,
2796 ALTIVEC_BUILTIN_LVEWX,
2797 ALTIVEC_BUILTIN_LVXL,
2798 ALTIVEC_BUILTIN_LVX,
2799 ALTIVEC_BUILTIN_STVX,
2800 ALTIVEC_BUILTIN_STVEBX,
2801 ALTIVEC_BUILTIN_STVEHX,
2802 ALTIVEC_BUILTIN_STVEWX,
2803 ALTIVEC_BUILTIN_STVXL,
2804 ALTIVEC_BUILTIN_VCMPBFP_P,
2805 ALTIVEC_BUILTIN_VCMPEQFP_P,
2806 ALTIVEC_BUILTIN_VCMPEQUB_P,
2807 ALTIVEC_BUILTIN_VCMPEQUH_P,
2808 ALTIVEC_BUILTIN_VCMPEQUW_P,
2809 ALTIVEC_BUILTIN_VCMPGEFP_P,
2810 ALTIVEC_BUILTIN_VCMPGTFP_P,
2811 ALTIVEC_BUILTIN_VCMPGTSB_P,
2812 ALTIVEC_BUILTIN_VCMPGTSH_P,
2813 ALTIVEC_BUILTIN_VCMPGTSW_P,
2814 ALTIVEC_BUILTIN_VCMPGTUB_P,
2815 ALTIVEC_BUILTIN_VCMPGTUH_P,
2816 ALTIVEC_BUILTIN_VCMPGTUW_P,
2817 ALTIVEC_BUILTIN_ABSS_V4SI,
2818 ALTIVEC_BUILTIN_ABSS_V8HI,
2819 ALTIVEC_BUILTIN_ABSS_V16QI,
2820 ALTIVEC_BUILTIN_ABS_V4SI,
2821 ALTIVEC_BUILTIN_ABS_V4SF,
2822 ALTIVEC_BUILTIN_ABS_V8HI,
2823 ALTIVEC_BUILTIN_ABS_V16QI,
2824 ALTIVEC_BUILTIN_COMPILETIME_ERROR,
2825 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
2826 ALTIVEC_BUILTIN_MASK_FOR_STORE,
2832 SPE_BUILTIN_EVDIVWS,
2833 SPE_BUILTIN_EVDIVWU,
2835 SPE_BUILTIN_EVFSADD,
2836 SPE_BUILTIN_EVFSDIV,
2837 SPE_BUILTIN_EVFSMUL,
2838 SPE_BUILTIN_EVFSSUB,
2842 SPE_BUILTIN_EVLHHESPLATX,
2843 SPE_BUILTIN_EVLHHOSSPLATX,
2844 SPE_BUILTIN_EVLHHOUSPLATX,
2845 SPE_BUILTIN_EVLWHEX,
2846 SPE_BUILTIN_EVLWHOSX,
2847 SPE_BUILTIN_EVLWHOUX,
2848 SPE_BUILTIN_EVLWHSPLATX,
2849 SPE_BUILTIN_EVLWWSPLATX,
2850 SPE_BUILTIN_EVMERGEHI,
2851 SPE_BUILTIN_EVMERGEHILO,
2852 SPE_BUILTIN_EVMERGELO,
2853 SPE_BUILTIN_EVMERGELOHI,
2854 SPE_BUILTIN_EVMHEGSMFAA,
2855 SPE_BUILTIN_EVMHEGSMFAN,
2856 SPE_BUILTIN_EVMHEGSMIAA,
2857 SPE_BUILTIN_EVMHEGSMIAN,
2858 SPE_BUILTIN_EVMHEGUMIAA,
2859 SPE_BUILTIN_EVMHEGUMIAN,
2860 SPE_BUILTIN_EVMHESMF,
2861 SPE_BUILTIN_EVMHESMFA,
2862 SPE_BUILTIN_EVMHESMFAAW,
2863 SPE_BUILTIN_EVMHESMFANW,
2864 SPE_BUILTIN_EVMHESMI,
2865 SPE_BUILTIN_EVMHESMIA,
2866 SPE_BUILTIN_EVMHESMIAAW,
2867 SPE_BUILTIN_EVMHESMIANW,
2868 SPE_BUILTIN_EVMHESSF,
2869 SPE_BUILTIN_EVMHESSFA,
2870 SPE_BUILTIN_EVMHESSFAAW,
2871 SPE_BUILTIN_EVMHESSFANW,
2872 SPE_BUILTIN_EVMHESSIAAW,
2873 SPE_BUILTIN_EVMHESSIANW,
2874 SPE_BUILTIN_EVMHEUMI,
2875 SPE_BUILTIN_EVMHEUMIA,
2876 SPE_BUILTIN_EVMHEUMIAAW,
2877 SPE_BUILTIN_EVMHEUMIANW,
2878 SPE_BUILTIN_EVMHEUSIAAW,
2879 SPE_BUILTIN_EVMHEUSIANW,
2880 SPE_BUILTIN_EVMHOGSMFAA,
2881 SPE_BUILTIN_EVMHOGSMFAN,
2882 SPE_BUILTIN_EVMHOGSMIAA,
2883 SPE_BUILTIN_EVMHOGSMIAN,
2884 SPE_BUILTIN_EVMHOGUMIAA,
2885 SPE_BUILTIN_EVMHOGUMIAN,
2886 SPE_BUILTIN_EVMHOSMF,
2887 SPE_BUILTIN_EVMHOSMFA,
2888 SPE_BUILTIN_EVMHOSMFAAW,
2889 SPE_BUILTIN_EVMHOSMFANW,
2890 SPE_BUILTIN_EVMHOSMI,
2891 SPE_BUILTIN_EVMHOSMIA,
2892 SPE_BUILTIN_EVMHOSMIAAW,
2893 SPE_BUILTIN_EVMHOSMIANW,
2894 SPE_BUILTIN_EVMHOSSF,
2895 SPE_BUILTIN_EVMHOSSFA,
2896 SPE_BUILTIN_EVMHOSSFAAW,
2897 SPE_BUILTIN_EVMHOSSFANW,
2898 SPE_BUILTIN_EVMHOSSIAAW,
2899 SPE_BUILTIN_EVMHOSSIANW,
2900 SPE_BUILTIN_EVMHOUMI,
2901 SPE_BUILTIN_EVMHOUMIA,
2902 SPE_BUILTIN_EVMHOUMIAAW,
2903 SPE_BUILTIN_EVMHOUMIANW,
2904 SPE_BUILTIN_EVMHOUSIAAW,
2905 SPE_BUILTIN_EVMHOUSIANW,
2906 SPE_BUILTIN_EVMWHSMF,
2907 SPE_BUILTIN_EVMWHSMFA,
2908 SPE_BUILTIN_EVMWHSMI,
2909 SPE_BUILTIN_EVMWHSMIA,
2910 SPE_BUILTIN_EVMWHSSF,
2911 SPE_BUILTIN_EVMWHSSFA,
2912 SPE_BUILTIN_EVMWHUMI,
2913 SPE_BUILTIN_EVMWHUMIA,
2914 SPE_BUILTIN_EVMWLSMIAAW,
2915 SPE_BUILTIN_EVMWLSMIANW,
2916 SPE_BUILTIN_EVMWLSSIAAW,
2917 SPE_BUILTIN_EVMWLSSIANW,
2918 SPE_BUILTIN_EVMWLUMI,
2919 SPE_BUILTIN_EVMWLUMIA,
2920 SPE_BUILTIN_EVMWLUMIAAW,
2921 SPE_BUILTIN_EVMWLUMIANW,
2922 SPE_BUILTIN_EVMWLUSIAAW,
2923 SPE_BUILTIN_EVMWLUSIANW,
2924 SPE_BUILTIN_EVMWSMF,
2925 SPE_BUILTIN_EVMWSMFA,
2926 SPE_BUILTIN_EVMWSMFAA,
2927 SPE_BUILTIN_EVMWSMFAN,
2928 SPE_BUILTIN_EVMWSMI,
2929 SPE_BUILTIN_EVMWSMIA,
2930 SPE_BUILTIN_EVMWSMIAA,
2931 SPE_BUILTIN_EVMWSMIAN,
2932 SPE_BUILTIN_EVMWHSSFAA,
2933 SPE_BUILTIN_EVMWSSF,
2934 SPE_BUILTIN_EVMWSSFA,
2935 SPE_BUILTIN_EVMWSSFAA,
2936 SPE_BUILTIN_EVMWSSFAN,
2937 SPE_BUILTIN_EVMWUMI,
2938 SPE_BUILTIN_EVMWUMIA,
2939 SPE_BUILTIN_EVMWUMIAA,
2940 SPE_BUILTIN_EVMWUMIAN,
2949 SPE_BUILTIN_EVSTDDX,
2950 SPE_BUILTIN_EVSTDHX,
2951 SPE_BUILTIN_EVSTDWX,
2952 SPE_BUILTIN_EVSTWHEX,
2953 SPE_BUILTIN_EVSTWHOX,
2954 SPE_BUILTIN_EVSTWWEX,
2955 SPE_BUILTIN_EVSTWWOX,
2956 SPE_BUILTIN_EVSUBFW,
2959 SPE_BUILTIN_EVADDSMIAAW,
2960 SPE_BUILTIN_EVADDSSIAAW,
2961 SPE_BUILTIN_EVADDUMIAAW,
2962 SPE_BUILTIN_EVADDUSIAAW,
2963 SPE_BUILTIN_EVCNTLSW,
2964 SPE_BUILTIN_EVCNTLZW,
2965 SPE_BUILTIN_EVEXTSB,
2966 SPE_BUILTIN_EVEXTSH,
2967 SPE_BUILTIN_EVFSABS,
2968 SPE_BUILTIN_EVFSCFSF,
2969 SPE_BUILTIN_EVFSCFSI,
2970 SPE_BUILTIN_EVFSCFUF,
2971 SPE_BUILTIN_EVFSCFUI,
2972 SPE_BUILTIN_EVFSCTSF,
2973 SPE_BUILTIN_EVFSCTSI,
2974 SPE_BUILTIN_EVFSCTSIZ,
2975 SPE_BUILTIN_EVFSCTUF,
2976 SPE_BUILTIN_EVFSCTUI,
2977 SPE_BUILTIN_EVFSCTUIZ,
2978 SPE_BUILTIN_EVFSNABS,
2979 SPE_BUILTIN_EVFSNEG,
2983 SPE_BUILTIN_EVSUBFSMIAAW,
2984 SPE_BUILTIN_EVSUBFSSIAAW,
2985 SPE_BUILTIN_EVSUBFUMIAAW,
2986 SPE_BUILTIN_EVSUBFUSIAAW,
2987 SPE_BUILTIN_EVADDIW,
2991 SPE_BUILTIN_EVLHHESPLAT,
2992 SPE_BUILTIN_EVLHHOSSPLAT,
2993 SPE_BUILTIN_EVLHHOUSPLAT,
2995 SPE_BUILTIN_EVLWHOS,
2996 SPE_BUILTIN_EVLWHOU,
2997 SPE_BUILTIN_EVLWHSPLAT,
2998 SPE_BUILTIN_EVLWWSPLAT,
3001 SPE_BUILTIN_EVSRWIS,
3002 SPE_BUILTIN_EVSRWIU,
3006 SPE_BUILTIN_EVSTWHE,
3007 SPE_BUILTIN_EVSTWHO,
3008 SPE_BUILTIN_EVSTWWE,
3009 SPE_BUILTIN_EVSTWWO,
3010 SPE_BUILTIN_EVSUBIFW,
3013 SPE_BUILTIN_EVCMPEQ,
3014 SPE_BUILTIN_EVCMPGTS,
3015 SPE_BUILTIN_EVCMPGTU,
3016 SPE_BUILTIN_EVCMPLTS,
3017 SPE_BUILTIN_EVCMPLTU,
3018 SPE_BUILTIN_EVFSCMPEQ,
3019 SPE_BUILTIN_EVFSCMPGT,
3020 SPE_BUILTIN_EVFSCMPLT,
3021 SPE_BUILTIN_EVFSTSTEQ,
3022 SPE_BUILTIN_EVFSTSTGT,
3023 SPE_BUILTIN_EVFSTSTLT,
3025 /* EVSEL compares. */
3026 SPE_BUILTIN_EVSEL_CMPEQ,
3027 SPE_BUILTIN_EVSEL_CMPGTS,
3028 SPE_BUILTIN_EVSEL_CMPGTU,
3029 SPE_BUILTIN_EVSEL_CMPLTS,
3030 SPE_BUILTIN_EVSEL_CMPLTU,
3031 SPE_BUILTIN_EVSEL_FSCMPEQ,
3032 SPE_BUILTIN_EVSEL_FSCMPGT,
3033 SPE_BUILTIN_EVSEL_FSCMPLT,
3034 SPE_BUILTIN_EVSEL_FSTSTEQ,
3035 SPE_BUILTIN_EVSEL_FSTSTGT,
3036 SPE_BUILTIN_EVSEL_FSTSTLT,
3038 SPE_BUILTIN_EVSPLATFI,
3039 SPE_BUILTIN_EVSPLATI,
3040 SPE_BUILTIN_EVMWHSSMAA,
3041 SPE_BUILTIN_EVMWHSMFAA,
3042 SPE_BUILTIN_EVMWHSMIAA,
3043 SPE_BUILTIN_EVMWHUSIAA,
3044 SPE_BUILTIN_EVMWHUMIAA,
3045 SPE_BUILTIN_EVMWHSSFAN,
3046 SPE_BUILTIN_EVMWHSSIAN,
3047 SPE_BUILTIN_EVMWHSMFAN,
3048 SPE_BUILTIN_EVMWHSMIAN,
3049 SPE_BUILTIN_EVMWHUSIAN,
3050 SPE_BUILTIN_EVMWHUMIAN,
3051 SPE_BUILTIN_EVMWHGSSFAA,
3052 SPE_BUILTIN_EVMWHGSMFAA,
3053 SPE_BUILTIN_EVMWHGSMIAA,
3054 SPE_BUILTIN_EVMWHGUMIAA,
3055 SPE_BUILTIN_EVMWHGSSFAN,
3056 SPE_BUILTIN_EVMWHGSMFAN,
3057 SPE_BUILTIN_EVMWHGSMIAN,
3058 SPE_BUILTIN_EVMWHGUMIAN,
3059 SPE_BUILTIN_MTSPEFSCR,
3060 SPE_BUILTIN_MFSPEFSCR,
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