1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
23 /* Note that some other tm.h files include this one and then override
24 many of the definitions. */
26 /* Definitions for the object file format. These are set at
29 #define OBJECT_XCOFF 1
32 #define OBJECT_MACHO 4
34 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
35 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
36 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
37 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
43 /* Default string to use for cpu if not specified. */
44 #ifndef TARGET_CPU_DEFAULT
45 #define TARGET_CPU_DEFAULT ((char *)0)
48 /* Common ASM definitions used by ASM_SPEC among the various targets
49 for handling -mcpu=xxx switches. */
50 #define ASM_CPU_SPEC \
52 %{mpower: %{!mpower2: -mpwr}} \
55 %{mno-power: %{!mpowerpc*: -mcom}} \
56 %{!mno-power: %{!mpower2: %(asm_default)}}} \
57 %{mcpu=common: -mcom} \
58 %{mcpu=power: -mpwr} \
59 %{mcpu=power2: -mpwrx} \
60 %{mcpu=power3: -m604} \
61 %{mcpu=power4: -mpower4} \
62 %{mcpu=powerpc: -mppc} \
64 %{mcpu=rios1: -mpwr} \
65 %{mcpu=rios2: -mpwrx} \
71 %{mcpu=405fp: -m405} \
73 %{mcpu=440fp: -m440} \
79 %{mcpu=ec603e: -mppc} \
94 %{mcpu=970: -mpower4} \
95 %{mcpu=G5: -mpower4} \
96 %{mcpu=8540: -me500} \
97 %{maltivec: -maltivec}"
99 #define CPP_DEFAULT_SPEC ""
101 #define ASM_DEFAULT_SPEC ""
103 /* This macro defines names of additional specifications to put in the specs
104 that can be used in various specifications like CC1_SPEC. Its definition
105 is an initializer with a subgrouping for each command option.
107 Each subgrouping contains a string constant, that defines the
108 specification name, and a string constant that used by the GCC driver
111 Do not define this macro if it does not need to do anything. */
113 #define SUBTARGET_EXTRA_SPECS
115 #define EXTRA_SPECS \
116 { "cpp_default", CPP_DEFAULT_SPEC }, \
117 { "asm_cpu", ASM_CPU_SPEC }, \
118 { "asm_default", ASM_DEFAULT_SPEC }, \
119 SUBTARGET_EXTRA_SPECS
121 /* Architecture type. */
123 extern int target_flags;
125 /* Use POWER architecture instructions and MQ register. */
126 #define MASK_POWER 0x00000001
128 /* Use POWER2 extensions to POWER architecture. */
129 #define MASK_POWER2 0x00000002
131 /* Use PowerPC architecture instructions. */
132 #define MASK_POWERPC 0x00000004
134 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */
135 #define MASK_PPC_GPOPT 0x00000008
137 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */
138 #define MASK_PPC_GFXOPT 0x00000010
140 /* Use PowerPC-64 architecture instructions. */
141 #define MASK_POWERPC64 0x00000020
143 /* Use revised mnemonic names defined for PowerPC architecture. */
144 #define MASK_NEW_MNEMONICS 0x00000040
146 /* Disable placing fp constants in the TOC; can be turned on when the
148 #define MASK_NO_FP_IN_TOC 0x00000080
150 /* Disable placing symbol+offset constants in the TOC; can be turned on when
151 the TOC overflows. */
152 #define MASK_NO_SUM_IN_TOC 0x00000100
154 /* Output only one TOC entry per module. Normally linking fails if
155 there are more than 16K unique variables/constants in an executable. With
156 this option, linking fails only if there are more than 16K modules, or
157 if there are more than 16K unique variables/constant in a single module.
159 This is at the cost of having 2 extra loads and one extra store per
160 function, and one less allocable register. */
161 #define MASK_MINIMAL_TOC 0x00000200
163 /* Nonzero for the 64bit model: longs and pointers are 64 bits. */
164 #define MASK_64BIT 0x00000400
166 /* Disable use of FPRs. */
167 #define MASK_SOFT_FLOAT 0x00000800
169 /* Enable load/store multiple, even on PowerPC */
170 #define MASK_MULTIPLE 0x00001000
172 /* Use string instructions for block moves */
173 #define MASK_STRING 0x00002000
175 /* Disable update form of load/store */
176 #define MASK_NO_UPDATE 0x00004000
178 /* Disable fused multiply/add operations */
179 #define MASK_NO_FUSED_MADD 0x00008000
181 /* Nonzero if we need to schedule the prolog and epilog. */
182 #define MASK_SCHED_PROLOG 0x00010000
184 /* Use AltiVec instructions. */
185 #define MASK_ALTIVEC 0x00020000
187 /* Return small structures in memory (as the AIX ABI requires). */
188 #define MASK_AIX_STRUCT_RET 0x00040000
190 /* Use single field mfcr instruction. */
191 #define MASK_MFCRF 0x00080000
193 /* The only remaining free bits are 0x00700000. sysv4.h uses
194 0x00800000 -> 0x40000000, and 0x80000000 is not available
195 because target_flags is signed. */
197 #define TARGET_POWER (target_flags & MASK_POWER)
198 #define TARGET_POWER2 (target_flags & MASK_POWER2)
199 #define TARGET_POWERPC (target_flags & MASK_POWERPC)
200 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
201 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
202 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
203 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
204 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
205 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
206 #define TARGET_64BIT (target_flags & MASK_64BIT)
207 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
208 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
209 #define TARGET_STRING (target_flags & MASK_STRING)
210 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
211 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
212 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
213 #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
214 #define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET)
216 /* Define TARGET_MFCRF if the target assembler supports the optional
217 field operand for mfcr and the target processor supports the
221 #define TARGET_MFCRF (target_flags & MASK_MFCRF)
223 #define TARGET_MFCRF 0
227 #define TARGET_32BIT (! TARGET_64BIT)
228 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
229 #define TARGET_UPDATE (! TARGET_NO_UPDATE)
230 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
233 #define HAVE_AS_TLS 0
237 /* For libgcc2 we make sure this is a compile time constant */
238 #if defined (__64BIT__) || defined (__powerpc64__)
239 #define TARGET_POWERPC64 1
241 #define TARGET_POWERPC64 0
244 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
247 #define TARGET_XL_CALL 0
249 /* Run-time compilation parameters selecting different hardware subsets.
251 Macro to define tables used to set the flags.
252 This is a list in braces of pairs in braces,
253 each pair being { "NAME", VALUE }
254 where VALUE is the bits to set or minus the bits to clear.
255 An empty string NAME is used to identify the default VALUE. */
257 #define TARGET_SWITCHES \
258 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
259 N_("Use POWER instruction set")}, \
260 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
262 N_("Use POWER2 instruction set")}, \
263 {"no-power2", - MASK_POWER2, \
264 N_("Do not use POWER2 instruction set")}, \
265 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
267 N_("Do not use POWER instruction set")}, \
268 {"powerpc", MASK_POWERPC, \
269 N_("Use PowerPC instruction set")}, \
270 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
271 | MASK_PPC_GFXOPT | MASK_POWERPC64), \
272 N_("Do not use PowerPC instruction set")}, \
273 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
274 N_("Use PowerPC General Purpose group optional instructions")},\
275 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
276 N_("Do not use PowerPC General Purpose group optional instructions")},\
277 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
278 N_("Use PowerPC Graphics group optional instructions")},\
279 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
280 N_("Do not use PowerPC Graphics group optional instructions")},\
281 {"powerpc64", MASK_POWERPC64, \
282 N_("Use PowerPC-64 instruction set")}, \
283 {"no-powerpc64", - MASK_POWERPC64, \
284 N_("Do not use PowerPC-64 instruction set")}, \
285 {"altivec", MASK_ALTIVEC , \
286 N_("Use AltiVec instructions")}, \
287 {"no-altivec", - MASK_ALTIVEC , \
288 N_("Do not use AltiVec instructions")}, \
289 {"new-mnemonics", MASK_NEW_MNEMONICS, \
290 N_("Use new mnemonics for PowerPC architecture")},\
291 {"old-mnemonics", -MASK_NEW_MNEMONICS, \
292 N_("Use old mnemonics for PowerPC architecture")},\
293 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
294 | MASK_MINIMAL_TOC), \
295 N_("Put everything in the regular TOC")}, \
296 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
297 N_("Place floating point constants in TOC")}, \
298 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
299 N_("Do not place floating point constants in TOC")},\
300 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
301 N_("Place symbol+offset constants in TOC")}, \
302 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
303 N_("Do not place symbol+offset constants in TOC")},\
304 {"minimal-toc", MASK_MINIMAL_TOC, \
305 "Use only one TOC entry per procedure"}, \
306 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
308 {"no-minimal-toc", - MASK_MINIMAL_TOC, \
309 N_("Place variable addresses in the regular TOC")},\
310 {"hard-float", - MASK_SOFT_FLOAT, \
311 N_("Use hardware floating point")}, \
312 {"soft-float", MASK_SOFT_FLOAT, \
313 N_("Do not use hardware floating point")}, \
314 {"multiple", MASK_MULTIPLE, \
315 N_("Generate load/store multiple instructions")}, \
316 {"no-multiple", - MASK_MULTIPLE, \
317 N_("Do not generate load/store multiple instructions")},\
318 {"string", MASK_STRING, \
319 N_("Generate string instructions for block moves")},\
320 {"no-string", - MASK_STRING, \
321 N_("Do not generate string instructions for block moves")},\
322 {"update", - MASK_NO_UPDATE, \
323 N_("Generate load/store with update instructions")},\
324 {"no-update", MASK_NO_UPDATE, \
325 N_("Do not generate load/store with update instructions")},\
326 {"fused-madd", - MASK_NO_FUSED_MADD, \
327 N_("Generate fused multiply/add instructions")},\
328 {"no-fused-madd", MASK_NO_FUSED_MADD, \
329 N_("Do not generate fused multiply/add instructions")},\
330 {"sched-prolog", MASK_SCHED_PROLOG, \
332 {"no-sched-prolog", -MASK_SCHED_PROLOG, \
333 N_("Do not schedule the start and end of the procedure")},\
334 {"sched-epilog", MASK_SCHED_PROLOG, \
336 {"no-sched-epilog", -MASK_SCHED_PROLOG, \
338 {"aix-struct-return", MASK_AIX_STRUCT_RET, \
339 N_("Return all structures in memory (AIX default)")},\
340 {"svr4-struct-return", - MASK_AIX_STRUCT_RET, \
341 N_("Return small structures in registers (SVR4 default)")},\
342 {"no-aix-struct-return", - MASK_AIX_STRUCT_RET, \
344 {"no-svr4-struct-return", MASK_AIX_STRUCT_RET, \
346 {"mfcrf", MASK_MFCRF, \
347 N_("Generate single field mfcr instruction")}, \
348 {"no-mfcrf", - MASK_MFCRF, \
349 N_("Do not generate single field mfcr instruction")},\
351 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
354 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
356 /* This is meant to be redefined in the host dependent files */
357 #define SUBTARGET_SWITCHES
359 /* Processor type. Order must match cpu attribute in MD file. */
382 extern enum processor_type rs6000_cpu;
384 /* Recast the processor type to the cpu attribute. */
385 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
387 /* Define generic processor types based upon current deployment. */
388 #define PROCESSOR_COMMON PROCESSOR_PPC601
389 #define PROCESSOR_POWER PROCESSOR_RIOS1
390 #define PROCESSOR_POWERPC PROCESSOR_PPC604
391 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
393 /* Define the default processor. This is overridden by other tm.h files. */
394 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
395 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
397 /* Specify the dialect of assembler to use. New mnemonics is dialect one
398 and the old mnemonics are dialect zero. */
399 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
401 /* Types of costly dependences. */
402 enum rs6000_dependence_cost
404 max_dep_latency = 1000,
407 true_store_to_load_dep_costly,
408 store_to_load_dep_costly
411 /* Types of nop insertion schemes in sched target hook sched_finish. */
412 enum rs6000_nop_insertion
414 sched_finish_regroup_exact = 1000,
415 sched_finish_pad_groups,
419 /* Dispatch group termination caused by an insn. */
420 enum group_termination
426 /* This is meant to be overridden in target specific files. */
427 #define SUBTARGET_OPTIONS
429 #define TARGET_OPTIONS \
431 {"cpu=", &rs6000_select[1].string, \
432 N_("Use features of and schedule code for given CPU"), 0}, \
433 {"tune=", &rs6000_select[2].string, \
434 N_("Schedule code for given CPU"), 0}, \
435 {"debug=", &rs6000_debug_name, N_("Enable debug output"), 0}, \
436 {"traceback=", &rs6000_traceback_name, \
437 N_("Select full, part, or no traceback table"), 0}, \
438 {"abi=", &rs6000_abi_string, N_("Specify ABI to use"), 0}, \
439 {"long-double-", &rs6000_long_double_size_string, \
440 N_("Specify size of long double (64 or 128 bits)"), 0}, \
441 {"isel=", &rs6000_isel_string, \
442 N_("Specify yes/no if isel instructions should be generated"), 0}, \
443 {"spe=", &rs6000_spe_string, \
444 N_("Specify yes/no if SPE SIMD instructions should be generated"), 0},\
445 {"float-gprs=", &rs6000_float_gprs_string, \
446 N_("Specify yes/no if using floating point in the GPRs"), 0}, \
447 {"vrsave=", &rs6000_altivec_vrsave_string, \
448 N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec"), 0}, \
449 {"longcall", &rs6000_longcall_switch, \
450 N_("Avoid all range limits on call instructions"), 0}, \
451 {"no-longcall", &rs6000_longcall_switch, "", 0}, \
452 {"sched-costly-dep=", &rs6000_sched_costly_dep_str, \
453 N_("Determine which dependences between insns are considered costly"), 0}, \
454 {"insert-sched-nops=", &rs6000_sched_insert_nops_str, \
455 N_("Specify which post scheduling nop insertion scheme to apply"), 0}, \
456 {"align-", &rs6000_alignment_string, \
457 N_("Specify alignment of structure fields default/natural"), 0}, \
458 {"prioritize-restricted-insns=", &rs6000_sched_restricted_insns_priority_str, \
459 N_("Specify scheduling priority for dispatch slot restricted insns"), 0}, \
463 /* Support for a compile-time default CPU, et cetera. The rules are:
464 --with-cpu is ignored if -mcpu is specified.
465 --with-tune is ignored if -mtune is specified.
466 --with-float is ignored if -mhard-float or -msoft-float are
468 #define OPTION_DEFAULT_SPECS \
469 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
470 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
471 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
473 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
474 struct rs6000_cpu_select
482 extern struct rs6000_cpu_select rs6000_select[];
485 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
486 extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,eabi,aix,altivec} */
487 extern int rs6000_debug_stack; /* debug stack applications */
488 extern int rs6000_debug_arg; /* debug argument handling */
490 #define TARGET_DEBUG_STACK rs6000_debug_stack
491 #define TARGET_DEBUG_ARG rs6000_debug_arg
493 extern const char *rs6000_traceback_name; /* Type of traceback table. */
495 /* These are separate from target_flags because we've run out of bits
497 extern const char *rs6000_long_double_size_string;
498 extern int rs6000_long_double_type_size;
499 extern int rs6000_altivec_abi;
500 extern int rs6000_spe_abi;
501 extern int rs6000_isel;
502 extern int rs6000_spe;
503 extern int rs6000_float_gprs;
504 extern const char *rs6000_float_gprs_string;
505 extern const char *rs6000_isel_string;
506 extern const char *rs6000_spe_string;
507 extern const char *rs6000_altivec_vrsave_string;
508 extern int rs6000_altivec_vrsave;
509 extern const char *rs6000_longcall_switch;
510 extern int rs6000_default_long_calls;
511 extern const char* rs6000_alignment_string;
512 extern int rs6000_alignment_flags;
513 extern const char *rs6000_sched_restricted_insns_priority_str;
514 extern int rs6000_sched_restricted_insns_priority;
515 extern const char *rs6000_sched_costly_dep_str;
516 extern enum rs6000_dependence_cost rs6000_sched_costly_dep;
517 extern const char *rs6000_sched_insert_nops_str;
518 extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
520 /* Alignment options for fields in structures for sub-targets following
522 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
523 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
525 Override the macro definitions when compiling libobjc to avoid undefined
526 reference to rs6000_alignment_flags due to library's use of GCC alignment
527 macros which use the macros below. */
529 #ifndef IN_TARGET_LIBS
530 #define MASK_ALIGN_POWER 0x00000000
531 #define MASK_ALIGN_NATURAL 0x00000001
532 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
534 #define TARGET_ALIGN_NATURAL 0
537 /* Set a default value for DEFAULT_SCHED_COSTLY_DEP used by target hook
538 is_costly_dependence. */
539 #define DEFAULT_SCHED_COSTLY_DEP \
540 (rs6000_cpu == PROCESSOR_POWER4 ? store_to_load_dep_costly : no_dep_costly)
542 /* Define if the target has restricted dispatch slot instructions. */
543 #define DEFAULT_RESTRICTED_INSNS_PRIORITY (rs6000_cpu == PROCESSOR_POWER4 ? 1 : 0)
545 /* Set a default value for post scheduling nop insertion scheme
546 (used by taget hook sched_finish). */
547 #define DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME \
548 (rs6000_cpu == PROCESSOR_POWER4 ? sched_finish_regroup_exact : sched_finish_none)
550 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
551 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
552 #define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave
554 #define TARGET_SPE_ABI 0
556 #define TARGET_E500 0
557 #define TARGET_ISEL 0
558 #define TARGET_FPRS 1
560 /* Sometimes certain combinations of command options do not make sense
561 on a particular target machine. You can define a macro
562 `OVERRIDE_OPTIONS' to take account of this. This macro, if
563 defined, is executed once just after all the command options have
566 Do not use this macro to turn on various extra optimizations for
567 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
569 On the RS/6000 this is used to define the target cpu type. */
571 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
573 /* Define this to change the optimizations performed by default. */
574 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
576 /* Show we can debug even without a frame pointer. */
577 #define CAN_DEBUG_WITHOUT_FP
580 #define REGISTER_TARGET_PRAGMAS() do { \
581 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
584 /* Target #defines. */
585 #define TARGET_CPU_CPP_BUILTINS() \
586 rs6000_cpu_cpp_builtins (pfile)
588 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
589 we're compiling for. Some configurations may need to override it. */
590 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
593 if (BYTES_BIG_ENDIAN) \
595 builtin_define ("__BIG_ENDIAN__"); \
596 builtin_define ("_BIG_ENDIAN"); \
597 builtin_assert ("machine=bigendian"); \
601 builtin_define ("__LITTLE_ENDIAN__"); \
602 builtin_define ("_LITTLE_ENDIAN"); \
603 builtin_assert ("machine=littleendian"); \
608 /* Target machine storage layout. */
610 /* Define this macro if it is advisable to hold scalars in registers
611 in a wider mode than that declared by the program. In such cases,
612 the value is constrained to be within the bounds of the declared
613 type, but kept valid in the wider mode. The signedness of the
614 extension may differ from that of the type. */
616 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
617 if (GET_MODE_CLASS (MODE) == MODE_INT \
618 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
619 (MODE) = TARGET_32BIT ? SImode : DImode;
621 /* Define this if most significant bit is lowest numbered
622 in instructions that operate on numbered bit-fields. */
623 /* That is true on RS/6000. */
624 #define BITS_BIG_ENDIAN 1
626 /* Define this if most significant byte of a word is the lowest numbered. */
627 /* That is true on RS/6000. */
628 #define BYTES_BIG_ENDIAN 1
630 /* Define this if most significant word of a multiword number is lowest
633 For RS/6000 we can decide arbitrarily since there are no machine
634 instructions for them. Might as well be consistent with bits and bytes. */
635 #define WORDS_BIG_ENDIAN 1
637 #define MAX_BITS_PER_WORD 64
639 /* Width of a word, in units (bytes). */
640 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
642 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
644 #define MIN_UNITS_PER_WORD 4
646 #define UNITS_PER_FP_WORD 8
647 #define UNITS_PER_ALTIVEC_WORD 16
648 #define UNITS_PER_SPE_WORD 8
650 /* Type used for ptrdiff_t, as a string used in a declaration. */
651 #define PTRDIFF_TYPE "int"
653 /* Type used for size_t, as a string used in a declaration. */
654 #define SIZE_TYPE "long unsigned int"
656 /* Type used for wchar_t, as a string used in a declaration. */
657 #define WCHAR_TYPE "short unsigned int"
659 /* Width of wchar_t in bits. */
660 #define WCHAR_TYPE_SIZE 16
662 /* A C expression for the size in bits of the type `short' on the
663 target machine. If you don't define this, the default is half a
664 word. (If this would be less than one storage unit, it is
665 rounded up to one unit.) */
666 #define SHORT_TYPE_SIZE 16
668 /* A C expression for the size in bits of the type `int' on the
669 target machine. If you don't define this, the default is one
671 #define INT_TYPE_SIZE 32
673 /* A C expression for the size in bits of the type `long' on the
674 target machine. If you don't define this, the default is one
676 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
677 #define MAX_LONG_TYPE_SIZE 64
679 /* A C expression for the size in bits of the type `long long' on the
680 target machine. If you don't define this, the default is two
682 #define LONG_LONG_TYPE_SIZE 64
684 /* A C expression for the size in bits of the type `float' on the
685 target machine. If you don't define this, the default is one
687 #define FLOAT_TYPE_SIZE 32
689 /* A C expression for the size in bits of the type `double' on the
690 target machine. If you don't define this, the default is two
692 #define DOUBLE_TYPE_SIZE 64
694 /* A C expression for the size in bits of the type `long double' on
695 the target machine. If you don't define this, the default is two
697 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
699 /* Constant which presents upper bound of the above value. */
700 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
702 /* Define this to set long double type size to use in libgcc2.c, which can
703 not depend on target_flags. */
704 #ifdef __LONG_DOUBLE_128__
705 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
707 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
710 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
711 #define WIDEST_HARDWARE_FP_SIZE 64
713 /* Width in bits of a pointer.
714 See also the macro `Pmode' defined below. */
715 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
717 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
718 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
720 /* Boundary (in *bits*) on which stack pointer should be aligned. */
721 #define STACK_BOUNDARY ((TARGET_32BIT && !TARGET_ALTIVEC_ABI) ? 64 : 128)
723 /* Allocation boundary (in *bits*) for the code of a function. */
724 #define FUNCTION_BOUNDARY 32
726 /* No data type wants to be aligned rounder than this. */
727 #define BIGGEST_ALIGNMENT 128
729 /* A C expression to compute the alignment for a variables in the
730 local store. TYPE is the data type, and ALIGN is the alignment
731 that the object would ordinarily have. */
732 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
733 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
734 (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN)
736 /* Alignment of field after `int : 0' in a structure. */
737 #define EMPTY_FIELD_BOUNDARY 32
739 /* Every structure's size must be a multiple of this. */
740 #define STRUCTURE_SIZE_BOUNDARY 8
742 /* Return 1 if a structure or array containing FIELD should be
743 accessed using `BLKMODE'.
745 For the SPE, simd types are V2SI, and gcc can be tempted to put the
746 entire thing in a DI and use subregs to access the internals.
747 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
748 back-end. Because a single GPR can hold a V2SI, but not a DI, the
749 best thing to do is set structs to BLKmode and avoid Severe Tire
751 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
752 (TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE)
754 /* A bit-field declared as `int' forces `int' alignment for the struct. */
755 #define PCC_BITFIELD_TYPE_MATTERS 1
757 /* Make strings word-aligned so strcpy from constants will be faster.
758 Make vector constants quadword aligned. */
759 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
760 (TREE_CODE (EXP) == STRING_CST \
761 && (ALIGN) < BITS_PER_WORD \
765 /* Make arrays of chars word-aligned for the same reasons.
766 Align vectors to 128 bits. */
767 #define DATA_ALIGNMENT(TYPE, ALIGN) \
768 (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \
769 : TREE_CODE (TYPE) == ARRAY_TYPE \
770 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
771 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
773 /* Nonzero if move instructions will actually fail to work
774 when given unaligned data. */
775 #define STRICT_ALIGNMENT 0
777 /* Define this macro to be the value 1 if unaligned accesses have a cost
778 many times greater than aligned accesses, for example if they are
779 emulated in a trap handler. */
780 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
782 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
783 || (MODE) == DImode) \
786 /* Standard register usage. */
788 /* Number of actual hardware registers.
789 The hardware registers are assigned numbers for the compiler
790 from 0 to just below FIRST_PSEUDO_REGISTER.
791 All registers that the compiler knows about must be given numbers,
792 even those that are not normally considered general registers.
794 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
795 an MQ register, a count register, a link register, and 8 condition
796 register fields, which we view here as separate registers. AltiVec
797 adds 32 vector registers and a VRsave register.
799 In addition, the difference between the frame and argument pointers is
800 a function of the number of registers saved, so we need to have a
801 register for AP that will later be eliminated in favor of SP or FP.
802 This is a normal register, but it is fixed.
804 We also create a pseudo register for float/int conversions, that will
805 really represent the memory location used. It is represented here as
806 a register, in order to work around problems in allocating stack storage
807 in inline functions. */
809 #define FIRST_PSEUDO_REGISTER 113
811 /* This must be included for pre gcc 3.0 glibc compatibility. */
812 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
814 /* Add 32 dwarf columns for synthetic SPE registers. The SPE
815 synthetic registers are 113 through 145. */
816 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 32)
818 /* The SPE has an additional 32 synthetic registers starting at 1200.
819 We must map them here to sane values in the unwinder to avoid a
820 huge hole in the unwind tables.
822 FIXME: the AltiVec ABI has AltiVec registers being 1124-1155, and
823 the VRSAVE SPR (SPR256) assigned to register 356. When AltiVec EH
824 is verified to be working, this macro should be changed
826 #define DWARF_REG_TO_UNWIND_COLUMN(r) ((r) > 1200 ? ((r) - 1200 + 113) : (r))
828 /* 1 for registers that have pervasive standard uses
829 and are not available for the register allocator.
831 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
832 as a local register; for all other OS's r2 is the TOC pointer.
834 cr5 is not supposed to be used.
836 On System V implementations, r13 is fixed and not available for use. */
838 #define FIXED_REGISTERS \
839 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
840 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
841 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
842 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
843 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
844 /* AltiVec registers. */ \
845 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
846 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
851 /* 1 for registers not available across function calls.
852 These must include the FIXED_REGISTERS and also any
853 registers that can be used without being saved.
854 The latter must include the registers where values are returned
855 and the register where structure-value addresses are passed.
856 Aside from that, you can include as many other registers as you like. */
858 #define CALL_USED_REGISTERS \
859 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
860 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
861 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
862 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
863 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
864 /* AltiVec registers. */ \
865 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
866 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
871 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
872 the entire set of `FIXED_REGISTERS' be included.
873 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
874 This macro is optional. If not specified, it defaults to the value
875 of `CALL_USED_REGISTERS'. */
877 #define CALL_REALLY_USED_REGISTERS \
878 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
879 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
880 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
881 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
882 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
883 /* AltiVec registers. */ \
884 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
885 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
896 #define MAX_CR_REGNO 75
898 #define FIRST_ALTIVEC_REGNO 77
899 #define LAST_ALTIVEC_REGNO 108
900 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
901 #define VRSAVE_REGNO 109
902 #define VSCR_REGNO 110
903 #define SPE_ACC_REGNO 111
904 #define SPEFSCR_REGNO 112
906 /* List the order in which to allocate registers. Each register must be
907 listed once, even those in FIXED_REGISTERS.
909 We allocate in the following order:
910 fp0 (not saved or used for anything)
911 fp13 - fp2 (not saved; incoming fp arg registers)
912 fp1 (not saved; return value)
913 fp31 - fp14 (saved; order given to save least number)
914 cr7, cr6 (not saved or special)
915 cr1 (not saved, but used for FP operations)
916 cr0 (not saved, but used for arithmetic operations)
917 cr4, cr3, cr2 (saved)
918 r0 (not saved; cannot be base reg)
919 r9 (not saved; best for TImode)
920 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
921 r3 (not saved; return value register)
922 r31 - r13 (saved; order given to save least number)
923 r12 (not saved; if used for DImode or DFmode would use r13)
924 mq (not saved; best to use it if we can)
925 ctr (not saved; when we have the choice ctr is better)
927 cr5, r1, r2, ap, xer, vrsave, vscr (fixed)
928 spe_acc, spefscr (fixed)
931 v0 - v1 (not saved or used for anything)
932 v13 - v3 (not saved; incoming vector arg registers)
933 v2 (not saved; incoming vector arg reg; return value)
934 v19 - v14 (not saved or used for anything)
935 v31 - v20 (saved; order given to save least number)
939 #define MAYBE_R2_AVAILABLE
940 #define MAYBE_R2_FIXED 2,
942 #define MAYBE_R2_AVAILABLE 2,
943 #define MAYBE_R2_FIXED
946 #define REG_ALLOC_ORDER \
948 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
950 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
951 50, 49, 48, 47, 46, \
952 75, 74, 69, 68, 72, 71, 70, \
953 0, MAYBE_R2_AVAILABLE \
954 9, 11, 10, 8, 7, 6, 5, 4, \
956 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
957 18, 17, 16, 15, 14, 13, 12, \
959 73, 1, MAYBE_R2_FIXED 67, 76, \
960 /* AltiVec registers. */ \
962 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
964 96, 95, 94, 93, 92, 91, \
965 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \
970 /* True if register is floating-point. */
971 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
973 /* True if register is a condition register. */
974 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
976 /* True if register is a condition register, but not cr0. */
977 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
979 /* True if register is an integer register. */
980 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
982 /* SPE SIMD registers are just the GPRs. */
983 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
985 /* True if register is the XER register. */
986 #define XER_REGNO_P(N) ((N) == XER_REGNO)
988 /* True if register is an AltiVec register. */
989 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
991 /* Return number of consecutive hard regs needed starting at reg REGNO
992 to hold something of mode MODE.
993 This is ordinarily the length in words of a value of mode MODE
994 but can be less for certain modes in special long registers.
996 For the SPE, GPRs are 64 bits but only 32 bits are visible in
997 scalar instructions. The upper 32 bits are only available to the
1000 POWER and PowerPC GPRs hold 32 bits worth;
1001 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1003 #define HARD_REGNO_NREGS(REGNO, MODE) \
1004 (FP_REGNO_P (REGNO) \
1005 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1006 : (SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE)) \
1007 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD) \
1008 : ALTIVEC_REGNO_P (REGNO) \
1009 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \
1010 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1012 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1013 ((TARGET_32BIT && TARGET_POWERPC64 \
1014 && (MODE == DImode || MODE == DFmode) \
1015 && INT_REGNO_P (REGNO)) ? 1 : 0)
1017 #define ALTIVEC_VECTOR_MODE(MODE) \
1018 ((MODE) == V16QImode \
1019 || (MODE) == V8HImode \
1020 || (MODE) == V4SFmode \
1021 || (MODE) == V4SImode)
1023 #define SPE_VECTOR_MODE(MODE) \
1024 ((MODE) == V4HImode \
1025 || (MODE) == V2SFmode \
1026 || (MODE) == V1DImode \
1027 || (MODE) == V2SImode)
1029 /* Define this macro to be nonzero if the port is prepared to handle
1030 insns involving vector mode MODE. At the very least, it must have
1031 move patterns for this mode. */
1033 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1034 ((TARGET_SPE && SPE_VECTOR_MODE (MODE)) \
1035 || (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE)))
1037 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1038 For POWER and PowerPC, the GPRs can hold any mode, but values bigger
1039 than one register cannot go past R31. The float
1040 registers only can hold floating modes and DImode, and CR register only
1041 can hold CC modes. We cannot put TImode anywhere except general
1042 register and it must be able to fit within the register set. */
1044 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1045 (INT_REGNO_P (REGNO) ? \
1046 INT_REGNO_P (REGNO + HARD_REGNO_NREGS (REGNO, MODE) - 1) \
1047 : FP_REGNO_P (REGNO) ? \
1048 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1049 || (GET_MODE_CLASS (MODE) == MODE_INT \
1050 && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \
1051 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE) \
1052 : SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE) ? 1 \
1053 : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \
1054 : XER_REGNO_P (REGNO) ? (MODE) == PSImode \
1055 : GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
1057 /* Value is 1 if it is a good idea to tie two pseudo registers
1058 when one has mode MODE1 and one has mode MODE2.
1059 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1060 for any hard reg, then this must be 0 for correct output. */
1061 #define MODES_TIEABLE_P(MODE1, MODE2) \
1062 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
1063 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
1064 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
1065 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
1066 : GET_MODE_CLASS (MODE1) == MODE_CC \
1067 ? GET_MODE_CLASS (MODE2) == MODE_CC \
1068 : GET_MODE_CLASS (MODE2) == MODE_CC \
1069 ? GET_MODE_CLASS (MODE1) == MODE_CC \
1070 : SPE_VECTOR_MODE (MODE1) \
1071 ? SPE_VECTOR_MODE (MODE2) \
1072 : SPE_VECTOR_MODE (MODE2) \
1073 ? SPE_VECTOR_MODE (MODE1) \
1074 : ALTIVEC_VECTOR_MODE (MODE1) \
1075 ? ALTIVEC_VECTOR_MODE (MODE2) \
1076 : ALTIVEC_VECTOR_MODE (MODE2) \
1077 ? ALTIVEC_VECTOR_MODE (MODE1) \
1080 /* Post-reload, we can't use any new AltiVec registers, as we already
1081 emitted the vrsave mask. */
1083 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1084 (! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST])
1086 /* A C expression returning the cost of moving data from a register of class
1087 CLASS1 to one of CLASS2. */
1089 #define REGISTER_MOVE_COST rs6000_register_move_cost
1091 /* A C expressions returning the cost of moving data of MODE from a register to
1094 #define MEMORY_MOVE_COST rs6000_memory_move_cost
1096 /* Specify the cost of a branch insn; roughly the number of extra insns that
1097 should be added to avoid a branch.
1099 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1100 unscheduled conditional branch. */
1102 #define BRANCH_COST 3
1104 /* Override BRANCH_COST heuristic which empirically produces worse
1105 performance for fold_range_test(). */
1107 #define RANGE_TEST_NON_SHORT_CIRCUIT 0
1109 /* A fixed register used at prologue and epilogue generation to fix
1110 addressing modes. The SPE needs heavy addressing fixes at the last
1111 minute, and it's best to save a register for it.
1113 AltiVec also needs fixes, but we've gotten around using r11, which
1114 is actually wrong because when use_backchain_to_restore_sp is true,
1115 we end up clobbering r11.
1117 The AltiVec case needs to be fixed. Dunno if we should break ABI
1118 compatibility and reserve a register for it as well.. */
1120 #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11)
1122 /* Define this macro to change register usage conditional on target flags.
1123 Set MQ register fixed (already call_used) if not POWER architecture
1124 (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated.
1125 64-bit AIX reserves GPR13 for thread-private data.
1126 Conditionally disable FPRs. */
1128 #define CONDITIONAL_REGISTER_USAGE \
1131 if (! TARGET_POWER) \
1132 fixed_regs[64] = 1; \
1134 fixed_regs[13] = call_used_regs[13] \
1135 = call_really_used_regs[13] = 1; \
1136 if (TARGET_SOFT_FLOAT || !TARGET_FPRS) \
1137 for (i = 32; i < 64; i++) \
1138 fixed_regs[i] = call_used_regs[i] \
1139 = call_really_used_regs[i] = 1; \
1140 if (DEFAULT_ABI == ABI_V4 \
1141 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \
1143 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1144 if (DEFAULT_ABI == ABI_V4 \
1145 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \
1147 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1148 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1149 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1150 if (DEFAULT_ABI == ABI_DARWIN \
1151 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
1152 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1153 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1154 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
1155 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
1156 if (TARGET_ALTIVEC) \
1157 global_regs[VSCR_REGNO] = 1; \
1160 global_regs[SPEFSCR_REGNO] = 1; \
1161 fixed_regs[FIXED_SCRATCH] \
1162 = call_used_regs[FIXED_SCRATCH] \
1163 = call_really_used_regs[FIXED_SCRATCH] = 1; \
1165 if (! TARGET_ALTIVEC) \
1167 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \
1168 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; \
1169 call_really_used_regs[VRSAVE_REGNO] = 1; \
1171 if (TARGET_ALTIVEC_ABI) \
1172 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) \
1173 call_used_regs[i] = call_really_used_regs[i] = 1; \
1176 /* Specify the registers used for certain standard purposes.
1177 The values of these macros are register numbers. */
1179 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1180 /* #define PC_REGNUM */
1182 /* Register to use for pushing function arguments. */
1183 #define STACK_POINTER_REGNUM 1
1185 /* Base register for access to local variables of the function. */
1186 #define FRAME_POINTER_REGNUM 31
1188 /* Value should be nonzero if functions must have frame pointers.
1189 Zero means the frame pointer need not be set up (and parms
1190 may be accessed via the stack pointer) in functions that seem suitable.
1191 This is computed in `reload', in reload1.c. */
1192 #define FRAME_POINTER_REQUIRED 0
1194 /* Base register for access to arguments of the function. */
1195 #define ARG_POINTER_REGNUM 67
1197 /* Place to put static chain when calling a function that requires it. */
1198 #define STATIC_CHAIN_REGNUM 11
1200 /* Link register number. */
1201 #define LINK_REGISTER_REGNUM 65
1203 /* Count register number. */
1204 #define COUNT_REGISTER_REGNUM 66
1206 /* Define the classes of registers for register constraints in the
1207 machine description. Also define ranges of constants.
1209 One of the classes must always be named ALL_REGS and include all hard regs.
1210 If there is more than one class, another class must be named NO_REGS
1211 and contain no registers.
1213 The name GENERAL_REGS must be the name of a class (or an alias for
1214 another name such as ALL_REGS). This is the class of registers
1215 that is allowed by "g" or "r" in a register constraint.
1216 Also, registers outside this class are allocated only when
1217 instructions express preferences for them.
1219 The classes must be numbered in nondecreasing order; that is,
1220 a larger-numbered class must never be contained completely
1221 in a smaller-numbered class.
1223 For any two classes, it is very desirable that there be another
1224 class that represents their union. */
1226 /* The RS/6000 has three types of registers, fixed-point, floating-point,
1227 and condition registers, plus three special registers, MQ, CTR, and the
1228 link register. AltiVec adds a vector register class.
1230 However, r0 is special in that it cannot be used as a base register.
1231 So make a class for registers valid as base registers.
1233 Also, cr0 is the only condition code register that can be used in
1234 arithmetic insns, so make a separate class for it. */
1262 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1264 /* Give names of register classes as strings for dump file. */
1266 #define REG_CLASS_NAMES \
1277 "NON_SPECIAL_REGS", \
1281 "LINK_OR_CTR_REGS", \
1283 "SPEC_OR_GEN_REGS", \
1291 /* Define which registers fit in which classes.
1292 This is an initializer for a vector of HARD_REG_SET
1293 of length N_REG_CLASSES. */
1295 #define REG_CLASS_CONTENTS \
1297 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1298 { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \
1299 { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \
1300 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1301 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1302 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1303 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1304 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1305 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1306 { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
1307 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1308 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1309 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1310 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1311 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1312 { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
1313 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1314 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1315 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1316 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1317 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \
1320 /* The same information, inverted:
1321 Return the class number of the smallest class containing
1322 reg number REGNO. This could be a conditional expression
1323 or could index an array. */
1325 #define REGNO_REG_CLASS(REGNO) \
1326 ((REGNO) == 0 ? GENERAL_REGS \
1327 : (REGNO) < 32 ? BASE_REGS \
1328 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1329 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1330 : (REGNO) == CR0_REGNO ? CR0_REGS \
1331 : CR_REGNO_P (REGNO) ? CR_REGS \
1332 : (REGNO) == MQ_REGNO ? MQ_REGS \
1333 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1334 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1335 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1336 : (REGNO) == XER_REGNO ? XER_REGS \
1337 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1338 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1339 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
1340 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
1343 /* The class value for index registers, and the one for base regs. */
1344 #define INDEX_REG_CLASS GENERAL_REGS
1345 #define BASE_REG_CLASS BASE_REGS
1347 /* Get reg_class from a letter such as appears in the machine description. */
1349 #define REG_CLASS_FROM_LETTER(C) \
1350 ((C) == 'f' ? FLOAT_REGS \
1351 : (C) == 'b' ? BASE_REGS \
1352 : (C) == 'h' ? SPECIAL_REGS \
1353 : (C) == 'q' ? MQ_REGS \
1354 : (C) == 'c' ? CTR_REGS \
1355 : (C) == 'l' ? LINK_REGS \
1356 : (C) == 'v' ? ALTIVEC_REGS \
1357 : (C) == 'x' ? CR0_REGS \
1358 : (C) == 'y' ? CR_REGS \
1359 : (C) == 'z' ? XER_REGS \
1362 /* The letters I, J, K, L, M, N, and P in a register constraint string
1363 can be used to stand for particular ranges of immediate operands.
1364 This macro defines what the ranges are.
1365 C is the letter, and VALUE is a constant value.
1366 Return 1 if VALUE is in the range specified by C.
1368 `I' is a signed 16-bit constant
1369 `J' is a constant with only the high-order 16 bits nonzero
1370 `K' is a constant with only the low-order 16 bits nonzero
1371 `L' is a signed 16-bit constant shifted left 16 bits
1372 `M' is a constant that is greater than 31
1373 `N' is a positive constant that is an exact power of two
1374 `O' is the constant zero
1375 `P' is a constant whose negation is a signed 16-bit constant */
1377 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1378 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1379 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1380 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1381 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1382 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1383 : (C) == 'M' ? (VALUE) > 31 \
1384 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1385 : (C) == 'O' ? (VALUE) == 0 \
1386 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1389 /* Similar, but for floating constants, and defining letters G and H.
1390 Here VALUE is the CONST_DOUBLE rtx itself.
1392 We flag for special constants when we can copy the constant into
1393 a general register in two insns for DF/DI and one insn for SF.
1395 'H' is used for DI/DF constants that take 3 insns. */
1397 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1398 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1399 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1400 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1403 /* Optional extra constraints for this machine.
1405 'Q' means that is a memory operand that is just an offset from a reg.
1406 'R' is for AIX TOC entries.
1407 'S' is a constant that can be placed into a 64-bit mask operand
1408 'T' is a constant that can be placed into a 32-bit mask operand
1409 'U' is for V.4 small data references.
1410 'W' is a vector constant that can be easily generated (no mem refs).
1411 't' is for AND masks that can be performed by two rldic{l,r} insns. */
1413 #define EXTRA_CONSTRAINT(OP, C) \
1414 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1415 : (C) == 'R' ? legitimate_constant_pool_address_p (OP) \
1416 : (C) == 'S' ? mask64_operand (OP, DImode) \
1417 : (C) == 'T' ? mask_operand (OP, SImode) \
1418 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
1419 && small_data_operand (OP, GET_MODE (OP))) \
1420 : (C) == 't' ? (mask64_2_operand (OP, DImode) \
1421 && (fixed_regs[CR0_REGNO] \
1422 || !logical_operand (OP, DImode)) \
1423 && !mask64_operand (OP, DImode)) \
1424 : (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP))) \
1427 /* Given an rtx X being reloaded into a reg required to be
1428 in class CLASS, return the class of reg to actually use.
1429 In general this is just CLASS; but on some machines
1430 in some cases it is preferable to use a more restrictive class.
1432 On the RS/6000, we have to return NO_REGS when we want to reload a
1433 floating-point CONST_DOUBLE to force it to be copied to memory.
1435 We also don't want to reload integer values into floating-point
1436 registers if we can at all help it. In fact, this can
1437 cause reload to abort, if it tries to generate a reload of CTR
1438 into a FP register and discovers it doesn't have the memory location
1441 ??? Would it be a good idea to have reload do the converse, that is
1442 try to reload floating modes into FP registers if possible?
1445 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1446 (((GET_CODE (X) == CONST_DOUBLE \
1447 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1449 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1450 && (CLASS) == NON_SPECIAL_REGS) \
1454 /* Return the register class of a scratch register needed to copy IN into
1455 or out of a register in CLASS in MODE. If it can be done directly,
1456 NO_REGS is returned. */
1458 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1459 secondary_reload_class (CLASS, MODE, IN)
1461 /* If we are copying between FP or AltiVec registers and anything
1462 else, we need a memory location. */
1464 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1465 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1466 || (CLASS2) == FLOAT_REGS \
1467 || (CLASS1) == ALTIVEC_REGS \
1468 || (CLASS2) == ALTIVEC_REGS))
1470 /* Return the maximum number of consecutive registers
1471 needed to represent mode MODE in a register of class CLASS.
1473 On RS/6000, this is the size of MODE in words,
1474 except in the FP regs, where a single reg is enough for two words. */
1475 #define CLASS_MAX_NREGS(CLASS, MODE) \
1476 (((CLASS) == FLOAT_REGS) \
1477 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1478 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1481 /* Return a class of registers that cannot change FROM mode to TO mode. */
1483 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1484 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) \
1485 && GET_MODE_SIZE (FROM) >= 8 && GET_MODE_SIZE (TO) >= 8) \
1487 : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1488 ? reg_classes_intersect_p (FLOAT_REGS, CLASS) \
1489 : (TARGET_SPE && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1) \
1490 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
1493 /* Stack layout; function entry, exit and calling. */
1495 /* Enumeration to give which calling sequence to use. */
1498 ABI_AIX, /* IBM's AIX */
1499 ABI_V4, /* System V.4/eabi */
1500 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1503 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1505 /* Define this if pushing a word on the stack
1506 makes the stack pointer a smaller address. */
1507 #define STACK_GROWS_DOWNWARD
1509 /* Define this if the nominal address of the stack frame
1510 is at the high-address end of the local variables;
1511 that is, each additional local variable allocated
1512 goes at a more negative offset in the frame.
1514 On the RS/6000, we grow upwards, from the area after the outgoing
1516 /* #define FRAME_GROWS_DOWNWARD */
1518 /* Size of the outgoing register save area */
1519 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1520 || DEFAULT_ABI == ABI_DARWIN) \
1521 ? (TARGET_64BIT ? 64 : 32) \
1524 /* Size of the fixed area on the stack */
1525 #define RS6000_SAVE_AREA \
1526 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1527 << (TARGET_64BIT ? 1 : 0))
1529 /* MEM representing address to save the TOC register */
1530 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1531 plus_constant (stack_pointer_rtx, \
1532 (TARGET_32BIT ? 20 : 40)))
1534 /* Size of the V.4 varargs area if needed */
1535 #define RS6000_VARARGS_AREA 0
1537 /* Align an address */
1538 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1540 /* Size of V.4 varargs area in bytes */
1541 #define RS6000_VARARGS_SIZE \
1542 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
1544 /* Offset within stack frame to start allocating local variables at.
1545 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1546 first local allocated. Otherwise, it is the offset to the BEGINNING
1547 of the first local allocated.
1549 On the RS/6000, the frame pointer is the same as the stack pointer,
1550 except for dynamic allocations. So we start after the fixed area and
1551 outgoing parameter area. */
1553 #define STARTING_FRAME_OFFSET \
1554 (RS6000_ALIGN (current_function_outgoing_args_size, \
1555 TARGET_ALTIVEC ? 16 : 8) \
1556 + RS6000_VARARGS_AREA \
1559 /* Offset from the stack pointer register to an item dynamically
1560 allocated on the stack, e.g., by `alloca'.
1562 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1563 length of the outgoing arguments. The default is correct for most
1564 machines. See `function.c' for details. */
1565 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1566 (RS6000_ALIGN (current_function_outgoing_args_size, \
1567 TARGET_ALTIVEC ? 16 : 8) \
1568 + (STACK_POINTER_OFFSET))
1570 /* If we generate an insn to push BYTES bytes,
1571 this says how many the stack pointer really advances by.
1572 On RS/6000, don't define this because there are no push insns. */
1573 /* #define PUSH_ROUNDING(BYTES) */
1575 /* Offset of first parameter from the argument pointer register value.
1576 On the RS/6000, we define the argument pointer to the start of the fixed
1578 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1580 /* Offset from the argument pointer register value to the top of
1581 stack. This is different from FIRST_PARM_OFFSET because of the
1582 register save area. */
1583 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1585 /* Define this if stack space is still allocated for a parameter passed
1586 in a register. The value is the number of bytes allocated to this
1588 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1590 /* Define this if the above stack space is to be considered part of the
1591 space allocated by the caller. */
1592 #define OUTGOING_REG_PARM_STACK_SPACE
1594 /* This is the difference between the logical top of stack and the actual sp.
1596 For the RS/6000, sp points past the fixed area. */
1597 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1599 /* Define this if the maximum size of all the outgoing args is to be
1600 accumulated and pushed during the prologue. The amount can be
1601 found in the variable current_function_outgoing_args_size. */
1602 #define ACCUMULATE_OUTGOING_ARGS 1
1604 /* Value is the number of bytes of arguments automatically
1605 popped when returning from a subroutine call.
1606 FUNDECL is the declaration node of the function (as a tree),
1607 FUNTYPE is the data type of the function (as a tree),
1608 or for a library call it is an identifier node for the subroutine name.
1609 SIZE is the number of bytes of arguments passed on the stack. */
1611 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1613 /* Define how to find the value returned by a function.
1614 VALTYPE is the data type of the value (as a tree).
1615 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1616 otherwise, FUNC is 0. */
1618 #define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC))
1620 /* Define how to find the value returned by a library function
1621 assuming the value has mode MODE. */
1623 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1625 /* DRAFT_V4_STRUCT_RET defaults off. */
1626 #define DRAFT_V4_STRUCT_RET 0
1628 /* Let RETURN_IN_MEMORY control what happens. */
1629 #define DEFAULT_PCC_STRUCT_RETURN 0
1631 /* Mode of stack savearea.
1632 FUNCTION is VOIDmode because calling convention maintains SP.
1633 BLOCK needs Pmode for SP.
1634 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1635 #define STACK_SAVEAREA_MODE(LEVEL) \
1636 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1637 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1639 /* Minimum and maximum general purpose registers used to hold arguments. */
1640 #define GP_ARG_MIN_REG 3
1641 #define GP_ARG_MAX_REG 10
1642 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1644 /* Minimum and maximum floating point registers used to hold arguments. */
1645 #define FP_ARG_MIN_REG 33
1646 #define FP_ARG_AIX_MAX_REG 45
1647 #define FP_ARG_V4_MAX_REG 40
1648 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1649 || DEFAULT_ABI == ABI_DARWIN) \
1650 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1651 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1653 /* Minimum and maximum AltiVec registers used to hold arguments. */
1654 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1655 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1656 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1658 /* Return registers */
1659 #define GP_ARG_RETURN GP_ARG_MIN_REG
1660 #define FP_ARG_RETURN FP_ARG_MIN_REG
1661 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1663 /* Flags for the call/call_value rtl operations set up by function_arg */
1664 #define CALL_NORMAL 0x00000000 /* no special processing */
1665 /* Bits in 0x00000001 are unused. */
1666 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1667 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1668 #define CALL_LONG 0x00000008 /* always call indirect */
1669 #define CALL_LIBCALL 0x00000010 /* libcall */
1671 /* 1 if N is a possible register number for a function value
1672 as seen by the caller.
1674 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1675 #define FUNCTION_VALUE_REGNO_P(N) \
1676 ((N) == GP_ARG_RETURN \
1677 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT) \
1678 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC))
1680 /* 1 if N is a possible register number for function argument passing.
1681 On RS/6000, these are r3-r10 and fp1-fp13.
1682 On AltiVec, v2 - v13 are used for passing vectors. */
1683 #define FUNCTION_ARG_REGNO_P(N) \
1684 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1685 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1686 && TARGET_ALTIVEC) \
1687 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1688 && TARGET_HARD_FLOAT))
1690 /* A C structure for machine-specific, per-function data.
1691 This is added to the cfun structure. */
1692 typedef struct machine_function GTY(())
1694 /* Whether a System V.4 varargs area was created. */
1696 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
1697 int ra_needs_full_frame;
1698 /* Some local-dynamic symbol. */
1699 const char *some_ld_name;
1700 /* Whether the instruction chain has been scanned already. */
1701 int insn_chain_scanned_p;
1702 /* Flags if __builtin_return_address (0) was used. */
1706 /* Define a data type for recording info about an argument list
1707 during the scan of that argument list. This data type should
1708 hold all necessary information about the function itself
1709 and about the args processed so far, enough to enable macros
1710 such as FUNCTION_ARG to determine where the next arg should go.
1712 On the RS/6000, this is a structure. The first element is the number of
1713 total argument words, the second is used to store the next
1714 floating-point register number, and the third says how many more args we
1715 have prototype types for.
1717 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1718 the next available GP register, `fregno' is the next available FP
1719 register, and `words' is the number of words used on the stack.
1721 The varargs/stdarg support requires that this structure's size
1722 be a multiple of sizeof(int). */
1724 typedef struct rs6000_args
1726 int words; /* # words used for passing GP registers */
1727 int fregno; /* next available FP register */
1728 int vregno; /* next available AltiVec register */
1729 int nargs_prototype; /* # args left in the current prototype */
1730 int prototype; /* Whether a prototype was defined */
1731 int stdarg; /* Whether function is a stdarg function. */
1732 int call_cookie; /* Do special things for this call */
1733 int sysv_gregno; /* next available GP register */
1736 /* Define intermediate macro to compute the size (in registers) of an argument
1739 #define UNITS_PER_ARG (TARGET_32BIT ? 4 : 8)
1741 #define RS6000_ARG_SIZE(MODE, TYPE) \
1742 ((MODE) != BLKmode \
1743 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_ARG - 1)) / UNITS_PER_ARG \
1744 : (int_size_in_bytes (TYPE) + (UNITS_PER_ARG - 1)) / UNITS_PER_ARG)
1746 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1747 for a call to a function whose data type is FNTYPE.
1748 For a library call, FNTYPE is 0. */
1750 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1751 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE)
1753 /* Similar, but when scanning the definition of a procedure. We always
1754 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1756 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \
1757 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE)
1759 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1761 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1762 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE)
1764 /* Update the data in CUM to advance over an argument
1765 of mode MODE and data type TYPE.
1766 (TYPE is null for libcalls where that information may not be available.) */
1768 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1769 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1771 /* Determine where to put an argument to a function.
1772 Value is zero to push the argument on the stack,
1773 or a hard register in which to store the argument.
1775 MODE is the argument's machine mode.
1776 TYPE is the data type of the argument (as a tree).
1777 This is null for libcalls where that information may
1779 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1780 the preceding args and about the function being called.
1781 NAMED is nonzero if this argument is a named parameter
1782 (otherwise it is an extra parameter matching an ellipsis).
1784 On RS/6000 the first eight words of non-FP are normally in registers
1785 and the rest are pushed. The first 13 FP args are in registers.
1787 If this is floating-point and no prototype is specified, we use
1788 both an FP and integer register (or possibly FP reg and stack). Library
1789 functions (when TYPE is zero) always have the proper types for args,
1790 so we can pass the FP value just in one register. emit_library_function
1791 doesn't support EXPR_LIST anyway. */
1793 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1794 function_arg (&CUM, MODE, TYPE, NAMED)
1796 /* For an arg passed partly in registers and partly in memory,
1797 this is the number of registers used.
1798 For args passed entirely in registers or entirely in memory, zero. */
1800 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1801 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1803 /* A C expression that indicates when an argument must be passed by
1804 reference. If nonzero for an argument, a copy of that argument is
1805 made in memory and a pointer to the argument is passed instead of
1806 the argument itself. The pointer is passed in whatever way is
1807 appropriate for passing a pointer to that type. */
1809 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1810 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
1812 /* If defined, a C expression which determines whether, and in which
1813 direction, to pad out an argument with extra space. The value
1814 should be of type `enum direction': either `upward' to pad above
1815 the argument, `downward' to pad below, or `none' to inhibit
1818 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1820 /* If defined, a C expression that gives the alignment boundary, in bits,
1821 of an argument with the specified mode and type. If it is not defined,
1822 PARM_BOUNDARY is used for all arguments. */
1824 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1825 function_arg_boundary (MODE, TYPE)
1827 /* Define to nonzero if complex arguments should be split into their
1828 corresponding components.
1830 This should be set for Linux and Darwin as well, but we can't break
1831 the ABIs at the moment. For now, only AIX gets fixed. */
1832 #define SPLIT_COMPLEX_ARGS (DEFAULT_ABI == ABI_AIX)
1834 /* Implement `va_start' for varargs and stdarg. */
1835 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1836 rs6000_va_start (valist, nextarg)
1838 /* Implement `va_arg'. */
1839 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1840 rs6000_va_arg (valist, type)
1842 #define PAD_VARARGS_DOWN \
1843 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1845 /* Define this macro to be a nonzero value if the location where a function
1846 argument is passed depends on whether or not it is a named argument. */
1847 #define STRICT_ARGUMENT_NAMING 1
1849 /* Output assembler code to FILE to increment profiler label # LABELNO
1850 for profiling a function entry. */
1852 #define FUNCTION_PROFILER(FILE, LABELNO) \
1853 output_function_profiler ((FILE), (LABELNO));
1855 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1856 the stack pointer does not matter. No definition is equivalent to
1859 On the RS/6000, this is nonzero because we can restore the stack from
1860 its backpointer, which we maintain. */
1861 #define EXIT_IGNORE_STACK 1
1863 /* Define this macro as a C expression that is nonzero for registers
1864 that are used by the epilogue or the return' pattern. The stack
1865 and frame pointer registers are already be assumed to be used as
1868 #define EPILOGUE_USES(REGNO) \
1869 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1870 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1871 || (current_function_calls_eh_return \
1876 /* TRAMPOLINE_TEMPLATE deleted */
1878 /* Length in units of the trampoline for entering a nested function. */
1880 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1882 /* Emit RTL insns to initialize the variable parts of a trampoline.
1883 FNADDR is an RTX for the address of the function's pure code.
1884 CXT is an RTX for the static chain value for the function. */
1886 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1887 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1889 /* Definitions for __builtin_return_address and __builtin_frame_address.
1890 __builtin_return_address (0) should give link register (65), enable
1892 /* This should be uncommented, so that the link register is used, but
1893 currently this would result in unmatched insns and spilling fixed
1894 registers so we'll leave it for another day. When these problems are
1895 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1897 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1899 /* Number of bytes into the frame return addresses can be found. See
1900 rs6000_stack_info in rs6000.c for more information on how the different
1901 abi's store the return address. */
1902 #define RETURN_ADDRESS_OFFSET \
1903 ((DEFAULT_ABI == ABI_AIX \
1904 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
1905 (DEFAULT_ABI == ABI_V4) ? 4 : \
1906 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1908 /* The current return address is in link register (65). The return address
1909 of anything farther back is accessed normally at an offset of 8 from the
1911 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1912 (rs6000_return_addr (COUNT, FRAME))
1915 /* Definitions for register eliminations.
1917 We have two registers that can be eliminated on the RS/6000. First, the
1918 frame pointer register can often be eliminated in favor of the stack
1919 pointer register. Secondly, the argument pointer register can always be
1920 eliminated; it is replaced with either the stack or frame pointer.
1922 In addition, we use the elimination mechanism to see if r30 is needed
1923 Initially we assume that it isn't. If it is, we spill it. This is done
1924 by making it an eliminable register. We replace it with itself so that
1925 if it isn't needed, then existing uses won't be modified. */
1927 /* This is an array of structures. Each structure initializes one pair
1928 of eliminable registers. The "from" register number is given first,
1929 followed by "to". Eliminations of the same "from" register are listed
1930 in order of preference. */
1931 #define ELIMINABLE_REGS \
1932 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1933 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1934 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1935 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1937 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1938 Frame pointer elimination is automatically handled.
1940 For the RS/6000, if frame pointer elimination is being done, we would like
1941 to convert ap into fp, not sp.
1943 We need r30 if -mminimal-toc was specified, and there are constant pool
1946 #define CAN_ELIMINATE(FROM, TO) \
1947 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1948 ? ! frame_pointer_needed \
1949 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1950 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1953 /* Define the offset between two registers, one to be eliminated, and the other
1954 its replacement, at the start of a routine. */
1955 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1956 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1958 /* Addressing modes, and classification of registers for them. */
1960 #define HAVE_PRE_DECREMENT 1
1961 #define HAVE_PRE_INCREMENT 1
1963 /* Macros to check register numbers against specific register classes. */
1965 /* These assume that REGNO is a hard or pseudo reg number.
1966 They give nonzero only if REGNO is a hard reg of the suitable class
1967 or a pseudo reg currently allocated to a suitable hard reg.
1968 Since they use reg_renumber, they are safe only once reg_renumber
1969 has been allocated, which happens in local-alloc.c. */
1971 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1972 ((REGNO) < FIRST_PSEUDO_REGISTER \
1973 ? (REGNO) <= 31 || (REGNO) == 67 \
1974 : (reg_renumber[REGNO] >= 0 \
1975 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1977 #define REGNO_OK_FOR_BASE_P(REGNO) \
1978 ((REGNO) < FIRST_PSEUDO_REGISTER \
1979 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1980 : (reg_renumber[REGNO] > 0 \
1981 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1983 /* Maximum number of registers that can appear in a valid memory address. */
1985 #define MAX_REGS_PER_ADDRESS 2
1987 /* Recognize any constant value that is a valid address. */
1989 #define CONSTANT_ADDRESS_P(X) \
1990 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1991 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1992 || GET_CODE (X) == HIGH)
1994 /* Nonzero if the constant value X is a legitimate general operand.
1995 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1997 On the RS/6000, all integer constants are acceptable, most won't be valid
1998 for particular insns, though. Only easy FP constants are
2001 #define LEGITIMATE_CONSTANT_P(X) \
2002 (((GET_CODE (X) != CONST_DOUBLE \
2003 && GET_CODE (X) != CONST_VECTOR) \
2004 || GET_MODE (X) == VOIDmode \
2005 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
2006 || easy_fp_constant (X, GET_MODE (X)) \
2007 || easy_vector_constant (X, GET_MODE (X))) \
2008 && !rs6000_tls_referenced_p (X))
2010 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2011 and check its validity for a certain class.
2012 We have two alternate definitions for each of them.
2013 The usual definition accepts all pseudo regs; the other rejects
2014 them unless they have been allocated suitable hard regs.
2015 The symbol REG_OK_STRICT causes the latter definition to be used.
2017 Most source files want to accept pseudo regs in the hope that
2018 they will get allocated to the class that the insn wants them to be in.
2019 Source files for reload pass need to be strict.
2020 After reload, it makes no difference, since pseudo regs have
2021 been eliminated by then. */
2023 #ifdef REG_OK_STRICT
2024 # define REG_OK_STRICT_FLAG 1
2026 # define REG_OK_STRICT_FLAG 0
2029 /* Nonzero if X is a hard reg that can be used as an index
2030 or if it is a pseudo reg in the non-strict case. */
2031 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
2033 && (REGNO (X) <= 31 \
2034 || REGNO (X) == ARG_POINTER_REGNUM \
2035 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
2036 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
2038 /* Nonzero if X is a hard reg that can be used as a base reg
2039 or if it is a pseudo reg in the non-strict case. */
2040 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
2041 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
2043 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
2044 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
2046 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2047 that is a valid memory address for an instruction.
2048 The MODE argument is the machine mode for the MEM expression
2049 that wants to use this address.
2051 On the RS/6000, there are four valid address: a SYMBOL_REF that
2052 refers to a constant pool entry of an address (or the sum of it
2053 plus a constant), a short (16-bit signed) constant plus a register,
2054 the sum of two registers, or a register indirect, possibly with an
2055 auto-increment. For DFmode and DImode with a constant plus register,
2056 we must ensure that both words are addressable or PowerPC64 with offset
2059 For modes spanning multiple registers (DFmode in 32-bit GPRs,
2060 32-bit DImode, TImode), indexed addressing cannot be used because
2061 adjacent memory cells are accessed by adding word-sized offsets
2062 during assembly output. */
2064 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2065 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
2069 /* Try machine-dependent ways of modifying an illegitimate address
2070 to be legitimate. If we find one, return the new, valid address.
2071 This macro is used in only one place: `memory_address' in explow.c.
2073 OLDX is the address as it was before break_out_memory_refs was called.
2074 In some cases it is useful to look at this to decide what needs to be done.
2076 MODE and WIN are passed so that this macro can use
2077 GO_IF_LEGITIMATE_ADDRESS.
2079 It is always safe for this macro to do nothing. It exists to recognize
2080 opportunities to optimize the output.
2082 On RS/6000, first check for the sum of a register with a constant
2083 integer that is out of range. If so, generate code to add the
2084 constant with the low-order 16 bits masked to the register and force
2085 this result into another register (this can be done with `cau').
2086 Then generate an address of REG+(CONST&0xffff), allowing for the
2087 possibility of bit 16 being a one.
2089 Then check for the sum of a register and something not constant, try to
2090 load the other things into a register and return the sum. */
2092 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2093 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
2094 if (result != NULL_RTX) \
2101 /* Try a machine-dependent way of reloading an illegitimate address
2102 operand. If we find one, push the reload and jump to WIN. This
2103 macro is used in only one place: `find_reloads_address' in reload.c.
2105 Implemented on rs6000 by rs6000_legitimize_reload_address.
2106 Note that (X) is evaluated twice; this is safe in current usage. */
2108 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2111 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
2112 (int)(TYPE), (IND_LEVELS), &win); \
2117 /* Go to LABEL if ADDR (a legitimate address expression)
2118 has an effect that depends on the machine mode it is used for. */
2120 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2122 if (rs6000_mode_dependent_address (ADDR)) \
2126 /* The register number of the register used to address a table of
2127 static data addresses in memory. In some cases this register is
2128 defined by a processor's "application binary interface" (ABI).
2129 When this macro is defined, RTL is generated for this register
2130 once, as with the stack pointer and frame pointer registers. If
2131 this macro is not defined, it is up to the machine-dependent files
2132 to allocate such a register (if necessary). */
2134 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
2135 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
2137 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
2139 /* Define this macro if the register defined by
2140 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
2141 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
2143 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
2145 /* By generating position-independent code, when two different
2146 programs (A and B) share a common library (libC.a), the text of
2147 the library can be shared whether or not the library is linked at
2148 the same address for both programs. In some of these
2149 environments, position-independent code requires not only the use
2150 of different addressing modes, but also special code to enable the
2151 use of these addressing modes.
2153 The `FINALIZE_PIC' macro serves as a hook to emit these special
2154 codes once the function is being compiled into assembly code, but
2155 not before. (It is not done before, because in the case of
2156 compiling an inline function, it would lead to multiple PIC
2157 prologues being included in functions which used inline functions
2158 and were compiled to assembly language.) */
2160 /* #define FINALIZE_PIC */
2162 /* A C expression that is nonzero if X is a legitimate immediate
2163 operand on the target machine when generating position independent
2164 code. You can assume that X satisfies `CONSTANT_P', so you need
2165 not check this. You can also assume FLAG_PIC is true, so you need
2166 not check it either. You need not define this macro if all
2167 constants (including `SYMBOL_REF') can be immediate operands when
2168 generating position independent code. */
2170 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2172 /* Define this if some processing needs to be done immediately before
2173 emitting code for an insn. */
2175 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
2177 /* Specify the machine mode that this machine uses
2178 for the index in the tablejump instruction. */
2179 #define CASE_VECTOR_MODE SImode
2181 /* Define as C expression which evaluates to nonzero if the tablejump
2182 instruction expects the table to contain offsets from the address of the
2184 Do not define this if the table should contain absolute addresses. */
2185 #define CASE_VECTOR_PC_RELATIVE 1
2187 /* Define this as 1 if `char' should by default be signed; else as 0. */
2188 #define DEFAULT_SIGNED_CHAR 0
2190 /* This flag, if defined, says the same insns that convert to a signed fixnum
2191 also convert validly to an unsigned one. */
2193 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
2195 /* Max number of bytes we can move from memory to memory
2196 in one reasonably fast instruction. */
2197 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2198 #define MAX_MOVE_MAX 8
2200 /* Nonzero if access to memory by bytes is no faster than for words.
2201 Also nonzero if doing byte operations (specifically shifts) in registers
2203 #define SLOW_BYTE_ACCESS 1
2205 /* Define if operations between registers always perform the operation
2206 on the full register even if a narrower mode is specified. */
2207 #define WORD_REGISTER_OPERATIONS
2209 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2210 will either zero-extend or sign-extend. The value of this macro should
2211 be the code that says which one of the two operations is implicitly
2212 done, NIL if none. */
2213 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2215 /* Define if loading short immediate values into registers sign extends. */
2216 #define SHORT_IMMEDIATES_SIGN_EXTEND
2218 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2219 is done just by pretending it is already truncated. */
2220 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2222 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
2223 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2224 ((VALUE) = ((MODE) == SImode ? 32 : 64))
2226 /* The CTZ patterns return -1 for input of zero. */
2227 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1)
2229 /* Specify the machine mode that pointers have.
2230 After generation of rtl, the compiler makes no further distinction
2231 between pointers and any other objects of this machine mode. */
2232 #define Pmode (TARGET_32BIT ? SImode : DImode)
2234 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
2235 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
2237 /* Mode of a function address in a call instruction (for indexing purposes).
2238 Doesn't matter on RS/6000. */
2239 #define FUNCTION_MODE SImode
2241 /* Define this if addresses of constant functions
2242 shouldn't be put through pseudo regs where they can be cse'd.
2243 Desirable on machines where ordinary constants are expensive
2244 but a CALL with constant address is cheap. */
2245 #define NO_FUNCTION_CSE
2247 /* Define this to be nonzero if shift instructions ignore all but the low-order
2250 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2251 have been dropped from the PowerPC architecture. */
2253 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2255 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2256 should be adjusted to reflect any required changes. This macro is used when
2257 there is some systematic length adjustment required that would be difficult
2258 to express in the length attribute. */
2260 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2262 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2263 COMPARE, return the mode to be used for the comparison. For
2264 floating-point, CCFPmode should be used. CCUNSmode should be used
2265 for unsigned comparisons. CCEQmode should be used when we are
2266 doing an inequality comparison on the result of a
2267 comparison. CCmode should be used in all other cases. */
2269 #define SELECT_CC_MODE(OP,X,Y) \
2270 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2271 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2272 : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<' \
2273 ? CCEQmode : CCmode))
2275 /* Can the condition code MODE be safely reversed? This is safe in
2276 all cases on this port, because at present it doesn't use the
2277 trapping FP comparisons (fcmpo). */
2278 #define REVERSIBLE_CC_MODE(MODE) 1
2280 /* Given a condition code and a mode, return the inverse condition. */
2281 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
2283 /* Define the information needed to generate branch and scc insns. This is
2284 stored from the compare operation. */
2286 extern GTY(()) rtx rs6000_compare_op0;
2287 extern GTY(()) rtx rs6000_compare_op1;
2288 extern int rs6000_compare_fp_p;
2290 /* Control the assembler format that we output. */
2292 /* A C string constant describing how to begin a comment in the target
2293 assembler language. The compiler assumes that the comment will end at
2294 the end of the line. */
2295 #define ASM_COMMENT_START " #"
2297 /* Implicit library calls should use memcpy, not bcopy, etc. */
2299 #define TARGET_MEM_FUNCTIONS
2301 /* Flag to say the TOC is initialized */
2302 extern int toc_initialized;
2304 /* Macro to output a special constant pool entry. Go to WIN if we output
2305 it. Otherwise, it is written the usual way.
2307 On the RS/6000, toc entries are handled this way. */
2309 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2310 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2312 output_toc (FILE, X, LABELNO, MODE); \
2317 #ifdef HAVE_GAS_WEAK
2318 #define RS6000_WEAK 1
2320 #define RS6000_WEAK 0
2324 /* Used in lieu of ASM_WEAKEN_LABEL. */
2325 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2328 fputs ("\t.weak\t", (FILE)); \
2329 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2330 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2331 && DEFAULT_ABI == ABI_AIX) \
2334 fputs ("[DS]", (FILE)); \
2335 fputs ("\n\t.weak\t.", (FILE)); \
2336 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2338 fputc ('\n', (FILE)); \
2341 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2342 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2343 && DEFAULT_ABI == ABI_AIX) \
2345 fputs ("\t.set\t.", (FILE)); \
2346 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2347 fputs (",.", (FILE)); \
2348 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2349 fputc ('\n', (FILE)); \
2356 /* This implements the `alias' attribute. */
2357 #undef ASM_OUTPUT_DEF_FROM_DECLS
2358 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2361 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2362 const char *name = IDENTIFIER_POINTER (TARGET); \
2363 if (TREE_CODE (DECL) == FUNCTION_DECL \
2364 && DEFAULT_ABI == ABI_AIX) \
2366 if (TREE_PUBLIC (DECL)) \
2368 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2370 fputs ("\t.globl\t.", FILE); \
2371 RS6000_OUTPUT_BASENAME (FILE, alias); \
2372 putc ('\n', FILE); \
2375 else if (TARGET_XCOFF) \
2377 fputs ("\t.lglobl\t.", FILE); \
2378 RS6000_OUTPUT_BASENAME (FILE, alias); \
2379 putc ('\n', FILE); \
2381 fputs ("\t.set\t.", FILE); \
2382 RS6000_OUTPUT_BASENAME (FILE, alias); \
2383 fputs (",.", FILE); \
2384 RS6000_OUTPUT_BASENAME (FILE, name); \
2385 fputc ('\n', FILE); \
2387 ASM_OUTPUT_DEF (FILE, alias, name); \
2391 #define TARGET_ASM_FILE_START rs6000_file_start
2393 /* Output to assembler file text saying following lines
2394 may contain character constants, extra white space, comments, etc. */
2396 #define ASM_APP_ON ""
2398 /* Output to assembler file text saying following lines
2399 no longer contain unusual constructs. */
2401 #define ASM_APP_OFF ""
2403 /* How to refer to registers in assembler output.
2404 This sequence is indexed by compiler's hard-register-number (see above). */
2406 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2408 #define REGISTER_NAMES \
2410 &rs6000_reg_names[ 0][0], /* r0 */ \
2411 &rs6000_reg_names[ 1][0], /* r1 */ \
2412 &rs6000_reg_names[ 2][0], /* r2 */ \
2413 &rs6000_reg_names[ 3][0], /* r3 */ \
2414 &rs6000_reg_names[ 4][0], /* r4 */ \
2415 &rs6000_reg_names[ 5][0], /* r5 */ \
2416 &rs6000_reg_names[ 6][0], /* r6 */ \
2417 &rs6000_reg_names[ 7][0], /* r7 */ \
2418 &rs6000_reg_names[ 8][0], /* r8 */ \
2419 &rs6000_reg_names[ 9][0], /* r9 */ \
2420 &rs6000_reg_names[10][0], /* r10 */ \
2421 &rs6000_reg_names[11][0], /* r11 */ \
2422 &rs6000_reg_names[12][0], /* r12 */ \
2423 &rs6000_reg_names[13][0], /* r13 */ \
2424 &rs6000_reg_names[14][0], /* r14 */ \
2425 &rs6000_reg_names[15][0], /* r15 */ \
2426 &rs6000_reg_names[16][0], /* r16 */ \
2427 &rs6000_reg_names[17][0], /* r17 */ \
2428 &rs6000_reg_names[18][0], /* r18 */ \
2429 &rs6000_reg_names[19][0], /* r19 */ \
2430 &rs6000_reg_names[20][0], /* r20 */ \
2431 &rs6000_reg_names[21][0], /* r21 */ \
2432 &rs6000_reg_names[22][0], /* r22 */ \
2433 &rs6000_reg_names[23][0], /* r23 */ \
2434 &rs6000_reg_names[24][0], /* r24 */ \
2435 &rs6000_reg_names[25][0], /* r25 */ \
2436 &rs6000_reg_names[26][0], /* r26 */ \
2437 &rs6000_reg_names[27][0], /* r27 */ \
2438 &rs6000_reg_names[28][0], /* r28 */ \
2439 &rs6000_reg_names[29][0], /* r29 */ \
2440 &rs6000_reg_names[30][0], /* r30 */ \
2441 &rs6000_reg_names[31][0], /* r31 */ \
2443 &rs6000_reg_names[32][0], /* fr0 */ \
2444 &rs6000_reg_names[33][0], /* fr1 */ \
2445 &rs6000_reg_names[34][0], /* fr2 */ \
2446 &rs6000_reg_names[35][0], /* fr3 */ \
2447 &rs6000_reg_names[36][0], /* fr4 */ \
2448 &rs6000_reg_names[37][0], /* fr5 */ \
2449 &rs6000_reg_names[38][0], /* fr6 */ \
2450 &rs6000_reg_names[39][0], /* fr7 */ \
2451 &rs6000_reg_names[40][0], /* fr8 */ \
2452 &rs6000_reg_names[41][0], /* fr9 */ \
2453 &rs6000_reg_names[42][0], /* fr10 */ \
2454 &rs6000_reg_names[43][0], /* fr11 */ \
2455 &rs6000_reg_names[44][0], /* fr12 */ \
2456 &rs6000_reg_names[45][0], /* fr13 */ \
2457 &rs6000_reg_names[46][0], /* fr14 */ \
2458 &rs6000_reg_names[47][0], /* fr15 */ \
2459 &rs6000_reg_names[48][0], /* fr16 */ \
2460 &rs6000_reg_names[49][0], /* fr17 */ \
2461 &rs6000_reg_names[50][0], /* fr18 */ \
2462 &rs6000_reg_names[51][0], /* fr19 */ \
2463 &rs6000_reg_names[52][0], /* fr20 */ \
2464 &rs6000_reg_names[53][0], /* fr21 */ \
2465 &rs6000_reg_names[54][0], /* fr22 */ \
2466 &rs6000_reg_names[55][0], /* fr23 */ \
2467 &rs6000_reg_names[56][0], /* fr24 */ \
2468 &rs6000_reg_names[57][0], /* fr25 */ \
2469 &rs6000_reg_names[58][0], /* fr26 */ \
2470 &rs6000_reg_names[59][0], /* fr27 */ \
2471 &rs6000_reg_names[60][0], /* fr28 */ \
2472 &rs6000_reg_names[61][0], /* fr29 */ \
2473 &rs6000_reg_names[62][0], /* fr30 */ \
2474 &rs6000_reg_names[63][0], /* fr31 */ \
2476 &rs6000_reg_names[64][0], /* mq */ \
2477 &rs6000_reg_names[65][0], /* lr */ \
2478 &rs6000_reg_names[66][0], /* ctr */ \
2479 &rs6000_reg_names[67][0], /* ap */ \
2481 &rs6000_reg_names[68][0], /* cr0 */ \
2482 &rs6000_reg_names[69][0], /* cr1 */ \
2483 &rs6000_reg_names[70][0], /* cr2 */ \
2484 &rs6000_reg_names[71][0], /* cr3 */ \
2485 &rs6000_reg_names[72][0], /* cr4 */ \
2486 &rs6000_reg_names[73][0], /* cr5 */ \
2487 &rs6000_reg_names[74][0], /* cr6 */ \
2488 &rs6000_reg_names[75][0], /* cr7 */ \
2490 &rs6000_reg_names[76][0], /* xer */ \
2492 &rs6000_reg_names[77][0], /* v0 */ \
2493 &rs6000_reg_names[78][0], /* v1 */ \
2494 &rs6000_reg_names[79][0], /* v2 */ \
2495 &rs6000_reg_names[80][0], /* v3 */ \
2496 &rs6000_reg_names[81][0], /* v4 */ \
2497 &rs6000_reg_names[82][0], /* v5 */ \
2498 &rs6000_reg_names[83][0], /* v6 */ \
2499 &rs6000_reg_names[84][0], /* v7 */ \
2500 &rs6000_reg_names[85][0], /* v8 */ \
2501 &rs6000_reg_names[86][0], /* v9 */ \
2502 &rs6000_reg_names[87][0], /* v10 */ \
2503 &rs6000_reg_names[88][0], /* v11 */ \
2504 &rs6000_reg_names[89][0], /* v12 */ \
2505 &rs6000_reg_names[90][0], /* v13 */ \
2506 &rs6000_reg_names[91][0], /* v14 */ \
2507 &rs6000_reg_names[92][0], /* v15 */ \
2508 &rs6000_reg_names[93][0], /* v16 */ \
2509 &rs6000_reg_names[94][0], /* v17 */ \
2510 &rs6000_reg_names[95][0], /* v18 */ \
2511 &rs6000_reg_names[96][0], /* v19 */ \
2512 &rs6000_reg_names[97][0], /* v20 */ \
2513 &rs6000_reg_names[98][0], /* v21 */ \
2514 &rs6000_reg_names[99][0], /* v22 */ \
2515 &rs6000_reg_names[100][0], /* v23 */ \
2516 &rs6000_reg_names[101][0], /* v24 */ \
2517 &rs6000_reg_names[102][0], /* v25 */ \
2518 &rs6000_reg_names[103][0], /* v26 */ \
2519 &rs6000_reg_names[104][0], /* v27 */ \
2520 &rs6000_reg_names[105][0], /* v28 */ \
2521 &rs6000_reg_names[106][0], /* v29 */ \
2522 &rs6000_reg_names[107][0], /* v30 */ \
2523 &rs6000_reg_names[108][0], /* v31 */ \
2524 &rs6000_reg_names[109][0], /* vrsave */ \
2525 &rs6000_reg_names[110][0], /* vscr */ \
2526 &rs6000_reg_names[111][0], /* spe_acc */ \
2527 &rs6000_reg_names[112][0], /* spefscr */ \
2530 /* Table of additional register names to use in user input. */
2532 #define ADDITIONAL_REGISTER_NAMES \
2533 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2534 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2535 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2536 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2537 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2538 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2539 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2540 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2541 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2542 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2543 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2544 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2545 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2546 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2547 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2548 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2549 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2550 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2551 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2552 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2553 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2554 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2555 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2556 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2557 {"vrsave", 109}, {"vscr", 110}, \
2558 {"spe_acc", 111}, {"spefscr", 112}, \
2559 /* no additional names for: mq, lr, ctr, ap */ \
2560 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2561 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2562 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2564 /* Text to write out after a CALL that may be replaced by glue code by
2565 the loader. This depends on the AIX version. */
2566 #define RS6000_CALL_GLUE "cror 31,31,31"
2568 /* This is how to output an element of a case-vector that is relative. */
2570 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2571 do { char buf[100]; \
2572 fputs ("\t.long ", FILE); \
2573 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2574 assemble_name (FILE, buf); \
2576 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2577 assemble_name (FILE, buf); \
2578 putc ('\n', FILE); \
2581 /* This is how to output an assembler line
2582 that says to advance the location counter
2583 to a multiple of 2**LOG bytes. */
2585 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2587 fprintf (FILE, "\t.align %d\n", (LOG))
2589 /* Pick up the return address upon entry to a procedure. Used for
2590 dwarf2 unwind information. This also enables the table driven
2593 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2594 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2596 /* Describe how we implement __builtin_eh_return. */
2597 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2598 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2600 /* Print operand X (an rtx) in assembler syntax to file FILE.
2601 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2602 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2604 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2606 /* Define which CODE values are valid. */
2608 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2609 ((CODE) == '.' || (CODE) == '&')
2611 /* Print a memory address as an operand to reference that memory location. */
2613 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2615 /* Define the codes that are matched by predicates in rs6000.c. */
2617 #define PREDICATE_CODES \
2618 {"any_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2619 LABEL_REF, SUBREG, REG, MEM, PARALLEL}}, \
2620 {"zero_constant", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2621 LABEL_REF, SUBREG, REG, MEM}}, \
2622 {"short_cint_operand", {CONST_INT}}, \
2623 {"u_short_cint_operand", {CONST_INT}}, \
2624 {"non_short_cint_operand", {CONST_INT}}, \
2625 {"exact_log2_cint_operand", {CONST_INT}}, \
2626 {"gpc_reg_operand", {SUBREG, REG}}, \
2627 {"cc_reg_operand", {SUBREG, REG}}, \
2628 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
2629 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
2630 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
2631 {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \
2632 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
2633 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2634 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
2635 {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2636 {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2637 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2638 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2639 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
2640 {"rs6000_tls_symbol_ref", {SYMBOL_REF}}, \
2641 {"easy_fp_constant", {CONST_DOUBLE}}, \
2642 {"easy_vector_constant", {CONST_VECTOR}}, \
2643 {"easy_vector_constant_add_self", {CONST_VECTOR}}, \
2644 {"zero_fp_constant", {CONST_DOUBLE}}, \
2645 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
2646 {"lwa_operand", {SUBREG, MEM, REG}}, \
2647 {"volatile_mem_operand", {MEM}}, \
2648 {"offsettable_mem_operand", {MEM}}, \
2649 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
2650 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2651 {"non_add_cint_operand", {CONST_INT}}, \
2652 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2653 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2654 {"and64_2_operand", {SUBREG, REG, CONST_INT}}, \
2655 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2656 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
2657 {"mask_operand", {CONST_INT}}, \
2658 {"mask_operand_wrap", {CONST_INT}}, \
2659 {"mask64_operand", {CONST_INT}}, \
2660 {"mask64_2_operand", {CONST_INT}}, \
2661 {"count_register_operand", {REG}}, \
2662 {"xer_operand", {REG}}, \
2663 {"symbol_ref_operand", {SYMBOL_REF}}, \
2664 {"rs6000_tls_symbol_ref", {SYMBOL_REF}}, \
2665 {"call_operand", {SYMBOL_REF, REG}}, \
2666 {"current_file_function_operand", {SYMBOL_REF}}, \
2667 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \
2668 CONST_DOUBLE, SYMBOL_REF}}, \
2669 {"load_multiple_operation", {PARALLEL}}, \
2670 {"store_multiple_operation", {PARALLEL}}, \
2671 {"vrsave_operation", {PARALLEL}}, \
2672 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
2673 GT, LEU, LTU, GEU, GTU, \
2674 UNORDERED, ORDERED, \
2676 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \
2678 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
2679 GT, LEU, LTU, GEU, GTU, \
2680 UNORDERED, ORDERED, \
2682 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
2683 GT, LEU, LTU, GEU, GTU}}, \
2684 {"boolean_operator", {AND, IOR, XOR}}, \
2685 {"boolean_or_operator", {IOR, XOR}}, \
2686 {"altivec_register_operand", {REG}}, \
2687 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
2689 /* uncomment for disabling the corresponding default options */
2690 /* #define MACHINE_no_sched_interblock */
2691 /* #define MACHINE_no_sched_speculative */
2692 /* #define MACHINE_no_sched_speculative_load */
2694 /* General flags. */
2695 extern int flag_pic;
2696 extern int optimize;
2697 extern int flag_expensive_optimizations;
2698 extern int frame_pointer_needed;
2700 enum rs6000_builtins
2702 /* AltiVec builtins. */
2703 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2704 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2705 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2706 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2707 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2708 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2709 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2710 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2711 ALTIVEC_BUILTIN_VADDUBM,
2712 ALTIVEC_BUILTIN_VADDUHM,
2713 ALTIVEC_BUILTIN_VADDUWM,
2714 ALTIVEC_BUILTIN_VADDFP,
2715 ALTIVEC_BUILTIN_VADDCUW,
2716 ALTIVEC_BUILTIN_VADDUBS,
2717 ALTIVEC_BUILTIN_VADDSBS,
2718 ALTIVEC_BUILTIN_VADDUHS,
2719 ALTIVEC_BUILTIN_VADDSHS,
2720 ALTIVEC_BUILTIN_VADDUWS,
2721 ALTIVEC_BUILTIN_VADDSWS,
2722 ALTIVEC_BUILTIN_VAND,
2723 ALTIVEC_BUILTIN_VANDC,
2724 ALTIVEC_BUILTIN_VAVGUB,
2725 ALTIVEC_BUILTIN_VAVGSB,
2726 ALTIVEC_BUILTIN_VAVGUH,
2727 ALTIVEC_BUILTIN_VAVGSH,
2728 ALTIVEC_BUILTIN_VAVGUW,
2729 ALTIVEC_BUILTIN_VAVGSW,
2730 ALTIVEC_BUILTIN_VCFUX,
2731 ALTIVEC_BUILTIN_VCFSX,
2732 ALTIVEC_BUILTIN_VCTSXS,
2733 ALTIVEC_BUILTIN_VCTUXS,
2734 ALTIVEC_BUILTIN_VCMPBFP,
2735 ALTIVEC_BUILTIN_VCMPEQUB,
2736 ALTIVEC_BUILTIN_VCMPEQUH,
2737 ALTIVEC_BUILTIN_VCMPEQUW,
2738 ALTIVEC_BUILTIN_VCMPEQFP,
2739 ALTIVEC_BUILTIN_VCMPGEFP,
2740 ALTIVEC_BUILTIN_VCMPGTUB,
2741 ALTIVEC_BUILTIN_VCMPGTSB,
2742 ALTIVEC_BUILTIN_VCMPGTUH,
2743 ALTIVEC_BUILTIN_VCMPGTSH,
2744 ALTIVEC_BUILTIN_VCMPGTUW,
2745 ALTIVEC_BUILTIN_VCMPGTSW,
2746 ALTIVEC_BUILTIN_VCMPGTFP,
2747 ALTIVEC_BUILTIN_VEXPTEFP,
2748 ALTIVEC_BUILTIN_VLOGEFP,
2749 ALTIVEC_BUILTIN_VMADDFP,
2750 ALTIVEC_BUILTIN_VMAXUB,
2751 ALTIVEC_BUILTIN_VMAXSB,
2752 ALTIVEC_BUILTIN_VMAXUH,
2753 ALTIVEC_BUILTIN_VMAXSH,
2754 ALTIVEC_BUILTIN_VMAXUW,
2755 ALTIVEC_BUILTIN_VMAXSW,
2756 ALTIVEC_BUILTIN_VMAXFP,
2757 ALTIVEC_BUILTIN_VMHADDSHS,
2758 ALTIVEC_BUILTIN_VMHRADDSHS,
2759 ALTIVEC_BUILTIN_VMLADDUHM,
2760 ALTIVEC_BUILTIN_VMRGHB,
2761 ALTIVEC_BUILTIN_VMRGHH,
2762 ALTIVEC_BUILTIN_VMRGHW,
2763 ALTIVEC_BUILTIN_VMRGLB,
2764 ALTIVEC_BUILTIN_VMRGLH,
2765 ALTIVEC_BUILTIN_VMRGLW,
2766 ALTIVEC_BUILTIN_VMSUMUBM,
2767 ALTIVEC_BUILTIN_VMSUMMBM,
2768 ALTIVEC_BUILTIN_VMSUMUHM,
2769 ALTIVEC_BUILTIN_VMSUMSHM,
2770 ALTIVEC_BUILTIN_VMSUMUHS,
2771 ALTIVEC_BUILTIN_VMSUMSHS,
2772 ALTIVEC_BUILTIN_VMINUB,
2773 ALTIVEC_BUILTIN_VMINSB,
2774 ALTIVEC_BUILTIN_VMINUH,
2775 ALTIVEC_BUILTIN_VMINSH,
2776 ALTIVEC_BUILTIN_VMINUW,
2777 ALTIVEC_BUILTIN_VMINSW,
2778 ALTIVEC_BUILTIN_VMINFP,
2779 ALTIVEC_BUILTIN_VMULEUB,
2780 ALTIVEC_BUILTIN_VMULESB,
2781 ALTIVEC_BUILTIN_VMULEUH,
2782 ALTIVEC_BUILTIN_VMULESH,
2783 ALTIVEC_BUILTIN_VMULOUB,
2784 ALTIVEC_BUILTIN_VMULOSB,
2785 ALTIVEC_BUILTIN_VMULOUH,
2786 ALTIVEC_BUILTIN_VMULOSH,
2787 ALTIVEC_BUILTIN_VNMSUBFP,
2788 ALTIVEC_BUILTIN_VNOR,
2789 ALTIVEC_BUILTIN_VOR,
2790 ALTIVEC_BUILTIN_VSEL_4SI,
2791 ALTIVEC_BUILTIN_VSEL_4SF,
2792 ALTIVEC_BUILTIN_VSEL_8HI,
2793 ALTIVEC_BUILTIN_VSEL_16QI,
2794 ALTIVEC_BUILTIN_VPERM_4SI,
2795 ALTIVEC_BUILTIN_VPERM_4SF,
2796 ALTIVEC_BUILTIN_VPERM_8HI,
2797 ALTIVEC_BUILTIN_VPERM_16QI,
2798 ALTIVEC_BUILTIN_VPKUHUM,
2799 ALTIVEC_BUILTIN_VPKUWUM,
2800 ALTIVEC_BUILTIN_VPKPX,
2801 ALTIVEC_BUILTIN_VPKUHSS,
2802 ALTIVEC_BUILTIN_VPKSHSS,
2803 ALTIVEC_BUILTIN_VPKUWSS,
2804 ALTIVEC_BUILTIN_VPKSWSS,
2805 ALTIVEC_BUILTIN_VPKUHUS,
2806 ALTIVEC_BUILTIN_VPKSHUS,
2807 ALTIVEC_BUILTIN_VPKUWUS,
2808 ALTIVEC_BUILTIN_VPKSWUS,
2809 ALTIVEC_BUILTIN_VREFP,
2810 ALTIVEC_BUILTIN_VRFIM,
2811 ALTIVEC_BUILTIN_VRFIN,
2812 ALTIVEC_BUILTIN_VRFIP,
2813 ALTIVEC_BUILTIN_VRFIZ,
2814 ALTIVEC_BUILTIN_VRLB,
2815 ALTIVEC_BUILTIN_VRLH,
2816 ALTIVEC_BUILTIN_VRLW,
2817 ALTIVEC_BUILTIN_VRSQRTEFP,
2818 ALTIVEC_BUILTIN_VSLB,
2819 ALTIVEC_BUILTIN_VSLH,
2820 ALTIVEC_BUILTIN_VSLW,
2821 ALTIVEC_BUILTIN_VSL,
2822 ALTIVEC_BUILTIN_VSLO,
2823 ALTIVEC_BUILTIN_VSPLTB,
2824 ALTIVEC_BUILTIN_VSPLTH,
2825 ALTIVEC_BUILTIN_VSPLTW,
2826 ALTIVEC_BUILTIN_VSPLTISB,
2827 ALTIVEC_BUILTIN_VSPLTISH,
2828 ALTIVEC_BUILTIN_VSPLTISW,
2829 ALTIVEC_BUILTIN_VSRB,
2830 ALTIVEC_BUILTIN_VSRH,
2831 ALTIVEC_BUILTIN_VSRW,
2832 ALTIVEC_BUILTIN_VSRAB,
2833 ALTIVEC_BUILTIN_VSRAH,
2834 ALTIVEC_BUILTIN_VSRAW,
2835 ALTIVEC_BUILTIN_VSR,
2836 ALTIVEC_BUILTIN_VSRO,
2837 ALTIVEC_BUILTIN_VSUBUBM,
2838 ALTIVEC_BUILTIN_VSUBUHM,
2839 ALTIVEC_BUILTIN_VSUBUWM,
2840 ALTIVEC_BUILTIN_VSUBFP,
2841 ALTIVEC_BUILTIN_VSUBCUW,
2842 ALTIVEC_BUILTIN_VSUBUBS,
2843 ALTIVEC_BUILTIN_VSUBSBS,
2844 ALTIVEC_BUILTIN_VSUBUHS,
2845 ALTIVEC_BUILTIN_VSUBSHS,
2846 ALTIVEC_BUILTIN_VSUBUWS,
2847 ALTIVEC_BUILTIN_VSUBSWS,
2848 ALTIVEC_BUILTIN_VSUM4UBS,
2849 ALTIVEC_BUILTIN_VSUM4SBS,
2850 ALTIVEC_BUILTIN_VSUM4SHS,
2851 ALTIVEC_BUILTIN_VSUM2SWS,
2852 ALTIVEC_BUILTIN_VSUMSWS,
2853 ALTIVEC_BUILTIN_VXOR,
2854 ALTIVEC_BUILTIN_VSLDOI_16QI,
2855 ALTIVEC_BUILTIN_VSLDOI_8HI,
2856 ALTIVEC_BUILTIN_VSLDOI_4SI,
2857 ALTIVEC_BUILTIN_VSLDOI_4SF,
2858 ALTIVEC_BUILTIN_VUPKHSB,
2859 ALTIVEC_BUILTIN_VUPKHPX,
2860 ALTIVEC_BUILTIN_VUPKHSH,
2861 ALTIVEC_BUILTIN_VUPKLSB,
2862 ALTIVEC_BUILTIN_VUPKLPX,
2863 ALTIVEC_BUILTIN_VUPKLSH,
2864 ALTIVEC_BUILTIN_MTVSCR,
2865 ALTIVEC_BUILTIN_MFVSCR,
2866 ALTIVEC_BUILTIN_DSSALL,
2867 ALTIVEC_BUILTIN_DSS,
2868 ALTIVEC_BUILTIN_LVSL,
2869 ALTIVEC_BUILTIN_LVSR,
2870 ALTIVEC_BUILTIN_DSTT,
2871 ALTIVEC_BUILTIN_DSTST,
2872 ALTIVEC_BUILTIN_DSTSTT,
2873 ALTIVEC_BUILTIN_DST,
2874 ALTIVEC_BUILTIN_LVEBX,
2875 ALTIVEC_BUILTIN_LVEHX,
2876 ALTIVEC_BUILTIN_LVEWX,
2877 ALTIVEC_BUILTIN_LVXL,
2878 ALTIVEC_BUILTIN_LVX,
2879 ALTIVEC_BUILTIN_STVX,
2880 ALTIVEC_BUILTIN_STVEBX,
2881 ALTIVEC_BUILTIN_STVEHX,
2882 ALTIVEC_BUILTIN_STVEWX,
2883 ALTIVEC_BUILTIN_STVXL,
2884 ALTIVEC_BUILTIN_VCMPBFP_P,
2885 ALTIVEC_BUILTIN_VCMPEQFP_P,
2886 ALTIVEC_BUILTIN_VCMPEQUB_P,
2887 ALTIVEC_BUILTIN_VCMPEQUH_P,
2888 ALTIVEC_BUILTIN_VCMPEQUW_P,
2889 ALTIVEC_BUILTIN_VCMPGEFP_P,
2890 ALTIVEC_BUILTIN_VCMPGTFP_P,
2891 ALTIVEC_BUILTIN_VCMPGTSB_P,
2892 ALTIVEC_BUILTIN_VCMPGTSH_P,
2893 ALTIVEC_BUILTIN_VCMPGTSW_P,
2894 ALTIVEC_BUILTIN_VCMPGTUB_P,
2895 ALTIVEC_BUILTIN_VCMPGTUH_P,
2896 ALTIVEC_BUILTIN_VCMPGTUW_P,
2897 ALTIVEC_BUILTIN_ABSS_V4SI,
2898 ALTIVEC_BUILTIN_ABSS_V8HI,
2899 ALTIVEC_BUILTIN_ABSS_V16QI,
2900 ALTIVEC_BUILTIN_ABS_V4SI,
2901 ALTIVEC_BUILTIN_ABS_V4SF,
2902 ALTIVEC_BUILTIN_ABS_V8HI,
2903 ALTIVEC_BUILTIN_ABS_V16QI
2905 , SPE_BUILTIN_EVADDW,
2908 SPE_BUILTIN_EVDIVWS,
2909 SPE_BUILTIN_EVDIVWU,
2911 SPE_BUILTIN_EVFSADD,
2912 SPE_BUILTIN_EVFSDIV,
2913 SPE_BUILTIN_EVFSMUL,
2914 SPE_BUILTIN_EVFSSUB,
2918 SPE_BUILTIN_EVLHHESPLATX,
2919 SPE_BUILTIN_EVLHHOSSPLATX,
2920 SPE_BUILTIN_EVLHHOUSPLATX,
2921 SPE_BUILTIN_EVLWHEX,
2922 SPE_BUILTIN_EVLWHOSX,
2923 SPE_BUILTIN_EVLWHOUX,
2924 SPE_BUILTIN_EVLWHSPLATX,
2925 SPE_BUILTIN_EVLWWSPLATX,
2926 SPE_BUILTIN_EVMERGEHI,
2927 SPE_BUILTIN_EVMERGEHILO,
2928 SPE_BUILTIN_EVMERGELO,
2929 SPE_BUILTIN_EVMERGELOHI,
2930 SPE_BUILTIN_EVMHEGSMFAA,
2931 SPE_BUILTIN_EVMHEGSMFAN,
2932 SPE_BUILTIN_EVMHEGSMIAA,
2933 SPE_BUILTIN_EVMHEGSMIAN,
2934 SPE_BUILTIN_EVMHEGUMIAA,
2935 SPE_BUILTIN_EVMHEGUMIAN,
2936 SPE_BUILTIN_EVMHESMF,
2937 SPE_BUILTIN_EVMHESMFA,
2938 SPE_BUILTIN_EVMHESMFAAW,
2939 SPE_BUILTIN_EVMHESMFANW,
2940 SPE_BUILTIN_EVMHESMI,
2941 SPE_BUILTIN_EVMHESMIA,
2942 SPE_BUILTIN_EVMHESMIAAW,
2943 SPE_BUILTIN_EVMHESMIANW,
2944 SPE_BUILTIN_EVMHESSF,
2945 SPE_BUILTIN_EVMHESSFA,
2946 SPE_BUILTIN_EVMHESSFAAW,
2947 SPE_BUILTIN_EVMHESSFANW,
2948 SPE_BUILTIN_EVMHESSIAAW,
2949 SPE_BUILTIN_EVMHESSIANW,
2950 SPE_BUILTIN_EVMHEUMI,
2951 SPE_BUILTIN_EVMHEUMIA,
2952 SPE_BUILTIN_EVMHEUMIAAW,
2953 SPE_BUILTIN_EVMHEUMIANW,
2954 SPE_BUILTIN_EVMHEUSIAAW,
2955 SPE_BUILTIN_EVMHEUSIANW,
2956 SPE_BUILTIN_EVMHOGSMFAA,
2957 SPE_BUILTIN_EVMHOGSMFAN,
2958 SPE_BUILTIN_EVMHOGSMIAA,
2959 SPE_BUILTIN_EVMHOGSMIAN,
2960 SPE_BUILTIN_EVMHOGUMIAA,
2961 SPE_BUILTIN_EVMHOGUMIAN,
2962 SPE_BUILTIN_EVMHOSMF,
2963 SPE_BUILTIN_EVMHOSMFA,
2964 SPE_BUILTIN_EVMHOSMFAAW,
2965 SPE_BUILTIN_EVMHOSMFANW,
2966 SPE_BUILTIN_EVMHOSMI,
2967 SPE_BUILTIN_EVMHOSMIA,
2968 SPE_BUILTIN_EVMHOSMIAAW,
2969 SPE_BUILTIN_EVMHOSMIANW,
2970 SPE_BUILTIN_EVMHOSSF,
2971 SPE_BUILTIN_EVMHOSSFA,
2972 SPE_BUILTIN_EVMHOSSFAAW,
2973 SPE_BUILTIN_EVMHOSSFANW,
2974 SPE_BUILTIN_EVMHOSSIAAW,
2975 SPE_BUILTIN_EVMHOSSIANW,
2976 SPE_BUILTIN_EVMHOUMI,
2977 SPE_BUILTIN_EVMHOUMIA,
2978 SPE_BUILTIN_EVMHOUMIAAW,
2979 SPE_BUILTIN_EVMHOUMIANW,
2980 SPE_BUILTIN_EVMHOUSIAAW,
2981 SPE_BUILTIN_EVMHOUSIANW,
2982 SPE_BUILTIN_EVMWHSMF,
2983 SPE_BUILTIN_EVMWHSMFA,
2984 SPE_BUILTIN_EVMWHSMI,
2985 SPE_BUILTIN_EVMWHSMIA,
2986 SPE_BUILTIN_EVMWHSSF,
2987 SPE_BUILTIN_EVMWHSSFA,
2988 SPE_BUILTIN_EVMWHUMI,
2989 SPE_BUILTIN_EVMWHUMIA,
2990 SPE_BUILTIN_EVMWLSMIAAW,
2991 SPE_BUILTIN_EVMWLSMIANW,
2992 SPE_BUILTIN_EVMWLSSIAAW,
2993 SPE_BUILTIN_EVMWLSSIANW,
2994 SPE_BUILTIN_EVMWLUMI,
2995 SPE_BUILTIN_EVMWLUMIA,
2996 SPE_BUILTIN_EVMWLUMIAAW,
2997 SPE_BUILTIN_EVMWLUMIANW,
2998 SPE_BUILTIN_EVMWLUSIAAW,
2999 SPE_BUILTIN_EVMWLUSIANW,
3000 SPE_BUILTIN_EVMWSMF,
3001 SPE_BUILTIN_EVMWSMFA,
3002 SPE_BUILTIN_EVMWSMFAA,
3003 SPE_BUILTIN_EVMWSMFAN,
3004 SPE_BUILTIN_EVMWSMI,
3005 SPE_BUILTIN_EVMWSMIA,
3006 SPE_BUILTIN_EVMWSMIAA,
3007 SPE_BUILTIN_EVMWSMIAN,
3008 SPE_BUILTIN_EVMWHSSFAA,
3009 SPE_BUILTIN_EVMWSSF,
3010 SPE_BUILTIN_EVMWSSFA,
3011 SPE_BUILTIN_EVMWSSFAA,
3012 SPE_BUILTIN_EVMWSSFAN,
3013 SPE_BUILTIN_EVMWUMI,
3014 SPE_BUILTIN_EVMWUMIA,
3015 SPE_BUILTIN_EVMWUMIAA,
3016 SPE_BUILTIN_EVMWUMIAN,
3025 SPE_BUILTIN_EVSTDDX,
3026 SPE_BUILTIN_EVSTDHX,
3027 SPE_BUILTIN_EVSTDWX,
3028 SPE_BUILTIN_EVSTWHEX,
3029 SPE_BUILTIN_EVSTWHOX,
3030 SPE_BUILTIN_EVSTWWEX,
3031 SPE_BUILTIN_EVSTWWOX,
3032 SPE_BUILTIN_EVSUBFW,
3035 SPE_BUILTIN_EVADDSMIAAW,
3036 SPE_BUILTIN_EVADDSSIAAW,
3037 SPE_BUILTIN_EVADDUMIAAW,
3038 SPE_BUILTIN_EVADDUSIAAW,
3039 SPE_BUILTIN_EVCNTLSW,
3040 SPE_BUILTIN_EVCNTLZW,
3041 SPE_BUILTIN_EVEXTSB,
3042 SPE_BUILTIN_EVEXTSH,
3043 SPE_BUILTIN_EVFSABS,
3044 SPE_BUILTIN_EVFSCFSF,
3045 SPE_BUILTIN_EVFSCFSI,
3046 SPE_BUILTIN_EVFSCFUF,
3047 SPE_BUILTIN_EVFSCFUI,
3048 SPE_BUILTIN_EVFSCTSF,
3049 SPE_BUILTIN_EVFSCTSI,
3050 SPE_BUILTIN_EVFSCTSIZ,
3051 SPE_BUILTIN_EVFSCTUF,
3052 SPE_BUILTIN_EVFSCTUI,
3053 SPE_BUILTIN_EVFSCTUIZ,
3054 SPE_BUILTIN_EVFSNABS,
3055 SPE_BUILTIN_EVFSNEG,
3059 SPE_BUILTIN_EVSUBFSMIAAW,
3060 SPE_BUILTIN_EVSUBFSSIAAW,
3061 SPE_BUILTIN_EVSUBFUMIAAW,
3062 SPE_BUILTIN_EVSUBFUSIAAW,
3063 SPE_BUILTIN_EVADDIW,
3067 SPE_BUILTIN_EVLHHESPLAT,
3068 SPE_BUILTIN_EVLHHOSSPLAT,
3069 SPE_BUILTIN_EVLHHOUSPLAT,
3071 SPE_BUILTIN_EVLWHOS,
3072 SPE_BUILTIN_EVLWHOU,
3073 SPE_BUILTIN_EVLWHSPLAT,
3074 SPE_BUILTIN_EVLWWSPLAT,
3077 SPE_BUILTIN_EVSRWIS,
3078 SPE_BUILTIN_EVSRWIU,
3082 SPE_BUILTIN_EVSTWHE,
3083 SPE_BUILTIN_EVSTWHO,
3084 SPE_BUILTIN_EVSTWWE,
3085 SPE_BUILTIN_EVSTWWO,
3086 SPE_BUILTIN_EVSUBIFW,
3089 SPE_BUILTIN_EVCMPEQ,
3090 SPE_BUILTIN_EVCMPGTS,
3091 SPE_BUILTIN_EVCMPGTU,
3092 SPE_BUILTIN_EVCMPLTS,
3093 SPE_BUILTIN_EVCMPLTU,
3094 SPE_BUILTIN_EVFSCMPEQ,
3095 SPE_BUILTIN_EVFSCMPGT,
3096 SPE_BUILTIN_EVFSCMPLT,
3097 SPE_BUILTIN_EVFSTSTEQ,
3098 SPE_BUILTIN_EVFSTSTGT,
3099 SPE_BUILTIN_EVFSTSTLT,
3101 /* EVSEL compares. */
3102 SPE_BUILTIN_EVSEL_CMPEQ,
3103 SPE_BUILTIN_EVSEL_CMPGTS,
3104 SPE_BUILTIN_EVSEL_CMPGTU,
3105 SPE_BUILTIN_EVSEL_CMPLTS,
3106 SPE_BUILTIN_EVSEL_CMPLTU,
3107 SPE_BUILTIN_EVSEL_FSCMPEQ,
3108 SPE_BUILTIN_EVSEL_FSCMPGT,
3109 SPE_BUILTIN_EVSEL_FSCMPLT,
3110 SPE_BUILTIN_EVSEL_FSTSTEQ,
3111 SPE_BUILTIN_EVSEL_FSTSTGT,
3112 SPE_BUILTIN_EVSEL_FSTSTLT,
3114 SPE_BUILTIN_EVSPLATFI,
3115 SPE_BUILTIN_EVSPLATI,
3116 SPE_BUILTIN_EVMWHSSMAA,
3117 SPE_BUILTIN_EVMWHSMFAA,
3118 SPE_BUILTIN_EVMWHSMIAA,
3119 SPE_BUILTIN_EVMWHUSIAA,
3120 SPE_BUILTIN_EVMWHUMIAA,
3121 SPE_BUILTIN_EVMWHSSFAN,
3122 SPE_BUILTIN_EVMWHSSIAN,
3123 SPE_BUILTIN_EVMWHSMFAN,
3124 SPE_BUILTIN_EVMWHSMIAN,
3125 SPE_BUILTIN_EVMWHUSIAN,
3126 SPE_BUILTIN_EVMWHUMIAN,
3127 SPE_BUILTIN_EVMWHGSSFAA,
3128 SPE_BUILTIN_EVMWHGSMFAA,
3129 SPE_BUILTIN_EVMWHGSMIAA,
3130 SPE_BUILTIN_EVMWHGUMIAA,
3131 SPE_BUILTIN_EVMWHGSSFAN,
3132 SPE_BUILTIN_EVMWHGSMFAN,
3133 SPE_BUILTIN_EVMWHGSMIAN,
3134 SPE_BUILTIN_EVMWHGUMIAN,
3135 SPE_BUILTIN_MTSPEFSCR,
3136 SPE_BUILTIN_MFSPEFSCR,
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