1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 MA 02110-1301, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions. */
27 /* Definitions for the object file format. These are set at
30 #define OBJECT_XCOFF 1
33 #define OBJECT_MACHO 4
35 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
36 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
37 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
38 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
44 /* Control whether function entry points use a "dot" symbol when
48 /* Default string to use for cpu if not specified. */
49 #ifndef TARGET_CPU_DEFAULT
50 #define TARGET_CPU_DEFAULT ((char *)0)
53 /* If configured for PPC405, support PPC405CR Erratum77. */
54 #ifdef CONFIG_PPC405CR
55 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
57 #define PPC405_ERRATUM77 0
60 /* Common ASM definitions used by ASM_SPEC among the various targets
61 for handling -mcpu=xxx switches. */
62 #define ASM_CPU_SPEC \
64 %{mpower: %{!mpower2: -mpwr}} \
66 %{mpowerpc64*: -mppc64} \
67 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
68 %{mno-power: %{!mpowerpc*: -mcom}} \
69 %{!mno-power: %{!mpower*: %(asm_default)}}} \
70 %{mcpu=common: -mcom} \
71 %{mcpu=power: -mpwr} \
72 %{mcpu=power2: -mpwrx} \
73 %{mcpu=power3: -mppc64} \
74 %{mcpu=power4: -mpower4} \
75 %{mcpu=power5: -mpower4} \
76 %{mcpu=power5+: -mpower4} \
77 %{mcpu=powerpc: -mppc} \
79 %{mcpu=rios1: -mpwr} \
80 %{mcpu=rios2: -mpwrx} \
83 %{mcpu=rs64a: -mppc64} \
87 %{mcpu=405fp: -m405} \
89 %{mcpu=440fp: -m440} \
95 %{mcpu=ec603e: -mppc} \
98 %{mcpu=620: -mppc64} \
99 %{mcpu=630: -mppc64} \
103 %{mcpu=7400: -mppc -maltivec} \
104 %{mcpu=7450: -mppc -maltivec} \
105 %{mcpu=G4: -mppc -maltivec} \
110 %{mcpu=970: -mpower4 -maltivec} \
111 %{mcpu=G5: -mpower4 -maltivec} \
112 %{mcpu=8540: -me500} \
113 %{maltivec: -maltivec} \
116 #define CPP_DEFAULT_SPEC ""
118 #define ASM_DEFAULT_SPEC ""
120 /* This macro defines names of additional specifications to put in the specs
121 that can be used in various specifications like CC1_SPEC. Its definition
122 is an initializer with a subgrouping for each command option.
124 Each subgrouping contains a string constant, that defines the
125 specification name, and a string constant that used by the GCC driver
128 Do not define this macro if it does not need to do anything. */
130 #define SUBTARGET_EXTRA_SPECS
132 #define EXTRA_SPECS \
133 { "cpp_default", CPP_DEFAULT_SPEC }, \
134 { "asm_cpu", ASM_CPU_SPEC }, \
135 { "asm_default", ASM_DEFAULT_SPEC }, \
136 SUBTARGET_EXTRA_SPECS
138 /* Architecture type. */
140 /* Define TARGET_MFCRF if the target assembler does not support the
141 optional field operand for mfcr. */
143 #ifndef HAVE_AS_MFCRF
145 #define TARGET_MFCRF 0
148 /* Define TARGET_POPCNTB if the target assembler does not support the
149 popcount byte instruction. */
151 #ifndef HAVE_AS_POPCNTB
152 #undef TARGET_POPCNTB
153 #define TARGET_POPCNTB 0
156 /* Define TARGET_FPRND if the target assembler does not support the
157 fp rounding instructions. */
159 #ifndef HAVE_AS_FPRND
161 #define TARGET_FPRND 0
164 #ifndef TARGET_SECURE_PLT
165 #define TARGET_SECURE_PLT 0
168 #define TARGET_32BIT (! TARGET_64BIT)
171 #define HAVE_AS_TLS 0
174 /* Return 1 for a symbol ref for a thread-local storage symbol. */
175 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
176 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
179 /* For libgcc2 we make sure this is a compile time constant */
180 #if defined (__64BIT__) || defined (__powerpc64__)
181 #undef TARGET_POWERPC64
182 #define TARGET_POWERPC64 1
184 #undef TARGET_POWERPC64
185 #define TARGET_POWERPC64 0
188 /* The option machinery will define this. */
191 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
193 /* Processor type. Order must match cpu attribute in MD file. */
217 extern enum processor_type rs6000_cpu;
219 /* Recast the processor type to the cpu attribute. */
220 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
222 /* Define generic processor types based upon current deployment. */
223 #define PROCESSOR_COMMON PROCESSOR_PPC601
224 #define PROCESSOR_POWER PROCESSOR_RIOS1
225 #define PROCESSOR_POWERPC PROCESSOR_PPC604
226 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
228 /* Define the default processor. This is overridden by other tm.h files. */
229 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
230 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
232 /* Specify the dialect of assembler to use. New mnemonics is dialect one
233 and the old mnemonics are dialect zero. */
234 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
236 /* Types of costly dependences. */
237 enum rs6000_dependence_cost
239 max_dep_latency = 1000,
242 true_store_to_load_dep_costly,
243 store_to_load_dep_costly
246 /* Types of nop insertion schemes in sched target hook sched_finish. */
247 enum rs6000_nop_insertion
249 sched_finish_regroup_exact = 1000,
250 sched_finish_pad_groups,
254 /* Dispatch group termination caused by an insn. */
255 enum group_termination
261 /* Support for a compile-time default CPU, et cetera. The rules are:
262 --with-cpu is ignored if -mcpu is specified.
263 --with-tune is ignored if -mtune is specified.
264 --with-float is ignored if -mhard-float or -msoft-float are
266 #define OPTION_DEFAULT_SPECS \
267 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
268 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
269 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
271 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
272 struct rs6000_cpu_select
280 extern struct rs6000_cpu_select rs6000_select[];
283 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
284 extern int rs6000_debug_stack; /* debug stack applications */
285 extern int rs6000_debug_arg; /* debug argument handling */
287 #define TARGET_DEBUG_STACK rs6000_debug_stack
288 #define TARGET_DEBUG_ARG rs6000_debug_arg
290 extern const char *rs6000_traceback_name; /* Type of traceback table. */
292 /* These are separate from target_flags because we've run out of bits
294 extern int rs6000_long_double_type_size;
295 extern int rs6000_ieeequad;
296 extern int rs6000_altivec_abi;
297 extern int rs6000_spe_abi;
298 extern int rs6000_float_gprs;
299 extern int rs6000_alignment_flags;
300 extern const char *rs6000_sched_insert_nops_str;
301 extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
303 /* Alignment options for fields in structures for sub-targets following
305 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
306 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
308 Override the macro definitions when compiling libobjc to avoid undefined
309 reference to rs6000_alignment_flags due to library's use of GCC alignment
310 macros which use the macros below. */
312 #ifndef IN_TARGET_LIBS
313 #define MASK_ALIGN_POWER 0x00000000
314 #define MASK_ALIGN_NATURAL 0x00000001
315 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
317 #define TARGET_ALIGN_NATURAL 0
320 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
321 #define TARGET_IEEEQUAD rs6000_ieeequad
322 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
324 #define TARGET_SPE_ABI 0
326 #define TARGET_E500 0
327 #define TARGET_ISEL 0
328 #define TARGET_FPRS 1
329 #define TARGET_E500_SINGLE 0
330 #define TARGET_E500_DOUBLE 0
332 /* Sometimes certain combinations of command options do not make sense
333 on a particular target machine. You can define a macro
334 `OVERRIDE_OPTIONS' to take account of this. This macro, if
335 defined, is executed once just after all the command options have
338 Do not use this macro to turn on various extra optimizations for
339 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
341 On the RS/6000 this is used to define the target cpu type. */
343 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
345 /* Define this to change the optimizations performed by default. */
346 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
348 /* Show we can debug even without a frame pointer. */
349 #define CAN_DEBUG_WITHOUT_FP
352 #define REGISTER_TARGET_PRAGMAS() do { \
353 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
354 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
357 /* Target #defines. */
358 #define TARGET_CPU_CPP_BUILTINS() \
359 rs6000_cpu_cpp_builtins (pfile)
361 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
362 we're compiling for. Some configurations may need to override it. */
363 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
366 if (BYTES_BIG_ENDIAN) \
368 builtin_define ("__BIG_ENDIAN__"); \
369 builtin_define ("_BIG_ENDIAN"); \
370 builtin_assert ("machine=bigendian"); \
374 builtin_define ("__LITTLE_ENDIAN__"); \
375 builtin_define ("_LITTLE_ENDIAN"); \
376 builtin_assert ("machine=littleendian"); \
381 /* Target machine storage layout. */
383 /* Define this macro if it is advisable to hold scalars in registers
384 in a wider mode than that declared by the program. In such cases,
385 the value is constrained to be within the bounds of the declared
386 type, but kept valid in the wider mode. The signedness of the
387 extension may differ from that of the type. */
389 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
390 if (GET_MODE_CLASS (MODE) == MODE_INT \
391 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
392 (MODE) = TARGET_32BIT ? SImode : DImode;
394 /* Define this if most significant bit is lowest numbered
395 in instructions that operate on numbered bit-fields. */
396 /* That is true on RS/6000. */
397 #define BITS_BIG_ENDIAN 1
399 /* Define this if most significant byte of a word is the lowest numbered. */
400 /* That is true on RS/6000. */
401 #define BYTES_BIG_ENDIAN 1
403 /* Define this if most significant word of a multiword number is lowest
406 For RS/6000 we can decide arbitrarily since there are no machine
407 instructions for them. Might as well be consistent with bits and bytes. */
408 #define WORDS_BIG_ENDIAN 1
410 #define MAX_BITS_PER_WORD 64
412 /* Width of a word, in units (bytes). */
413 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
415 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
417 #define MIN_UNITS_PER_WORD 4
419 #define UNITS_PER_FP_WORD 8
420 #define UNITS_PER_ALTIVEC_WORD 16
421 #define UNITS_PER_SPE_WORD 8
423 /* Type used for ptrdiff_t, as a string used in a declaration. */
424 #define PTRDIFF_TYPE "int"
426 /* Type used for size_t, as a string used in a declaration. */
427 #define SIZE_TYPE "long unsigned int"
429 /* Type used for wchar_t, as a string used in a declaration. */
430 #define WCHAR_TYPE "short unsigned int"
432 /* Width of wchar_t in bits. */
433 #define WCHAR_TYPE_SIZE 16
435 /* A C expression for the size in bits of the type `short' on the
436 target machine. If you don't define this, the default is half a
437 word. (If this would be less than one storage unit, it is
438 rounded up to one unit.) */
439 #define SHORT_TYPE_SIZE 16
441 /* A C expression for the size in bits of the type `int' on the
442 target machine. If you don't define this, the default is one
444 #define INT_TYPE_SIZE 32
446 /* A C expression for the size in bits of the type `long' on the
447 target machine. If you don't define this, the default is one
449 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
451 /* A C expression for the size in bits of the type `long long' on the
452 target machine. If you don't define this, the default is two
454 #define LONG_LONG_TYPE_SIZE 64
456 /* A C expression for the size in bits of the type `float' on the
457 target machine. If you don't define this, the default is one
459 #define FLOAT_TYPE_SIZE 32
461 /* A C expression for the size in bits of the type `double' on the
462 target machine. If you don't define this, the default is two
464 #define DOUBLE_TYPE_SIZE 64
466 /* A C expression for the size in bits of the type `long double' on
467 the target machine. If you don't define this, the default is two
469 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
471 /* Define this to set long double type size to use in libgcc2.c, which can
472 not depend on target_flags. */
473 #ifdef __LONG_DOUBLE_128__
474 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
476 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
479 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
480 #define WIDEST_HARDWARE_FP_SIZE 64
482 /* Width in bits of a pointer.
483 See also the macro `Pmode' defined below. */
484 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
486 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
487 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
489 /* Boundary (in *bits*) on which stack pointer should be aligned. */
490 #define STACK_BOUNDARY \
491 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI) ? 64 : 128)
493 /* Allocation boundary (in *bits*) for the code of a function. */
494 #define FUNCTION_BOUNDARY 32
496 /* No data type wants to be aligned rounder than this. */
497 #define BIGGEST_ALIGNMENT 128
499 /* A C expression to compute the alignment for a variables in the
500 local store. TYPE is the data type, and ALIGN is the alignment
501 that the object would ordinarily have. */
502 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
503 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
504 (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 : \
505 (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN)
507 /* Alignment of field after `int : 0' in a structure. */
508 #define EMPTY_FIELD_BOUNDARY 32
510 /* Every structure's size must be a multiple of this. */
511 #define STRUCTURE_SIZE_BOUNDARY 8
513 /* Return 1 if a structure or array containing FIELD should be
514 accessed using `BLKMODE'.
516 For the SPE, simd types are V2SI, and gcc can be tempted to put the
517 entire thing in a DI and use subregs to access the internals.
518 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
519 back-end. Because a single GPR can hold a V2SI, but not a DI, the
520 best thing to do is set structs to BLKmode and avoid Severe Tire
523 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
524 fit into 1, whereas DI still needs two. */
525 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
526 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
527 || (TARGET_E500_DOUBLE && (MODE) == DFmode))
529 /* A bit-field declared as `int' forces `int' alignment for the struct. */
530 #define PCC_BITFIELD_TYPE_MATTERS 1
532 /* Make strings word-aligned so strcpy from constants will be faster.
533 Make vector constants quadword aligned. */
534 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
535 (TREE_CODE (EXP) == STRING_CST \
536 && (ALIGN) < BITS_PER_WORD \
540 /* Make arrays of chars word-aligned for the same reasons.
541 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
543 #define DATA_ALIGNMENT(TYPE, ALIGN) \
544 (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \
545 : (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 \
546 : TREE_CODE (TYPE) == ARRAY_TYPE \
547 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
548 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
550 /* Nonzero if move instructions will actually fail to work
551 when given unaligned data. */
552 #define STRICT_ALIGNMENT 0
554 /* Define this macro to be the value 1 if unaligned accesses have a cost
555 many times greater than aligned accesses, for example if they are
556 emulated in a trap handler. */
557 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
559 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
560 || (MODE) == DImode) \
563 /* Standard register usage. */
565 /* Number of actual hardware registers.
566 The hardware registers are assigned numbers for the compiler
567 from 0 to just below FIRST_PSEUDO_REGISTER.
568 All registers that the compiler knows about must be given numbers,
569 even those that are not normally considered general registers.
571 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
572 an MQ register, a count register, a link register, and 8 condition
573 register fields, which we view here as separate registers. AltiVec
574 adds 32 vector registers and a VRsave register.
576 In addition, the difference between the frame and argument pointers is
577 a function of the number of registers saved, so we need to have a
578 register for AP that will later be eliminated in favor of SP or FP.
579 This is a normal register, but it is fixed.
581 We also create a pseudo register for float/int conversions, that will
582 really represent the memory location used. It is represented here as
583 a register, in order to work around problems in allocating stack storage
586 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
587 pointer, which is eventually eliminated in favor of SP or FP. */
589 #define FIRST_PSEUDO_REGISTER 114
591 /* This must be included for pre gcc 3.0 glibc compatibility. */
592 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
594 /* Add 32 dwarf columns for synthetic SPE registers. */
595 #define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)
597 /* The SPE has an additional 32 synthetic registers, with DWARF debug
598 info numbering for these registers starting at 1200. While eh_frame
599 register numbering need not be the same as the debug info numbering,
600 we choose to number these regs for eh_frame at 1200 too. This allows
601 future versions of the rs6000 backend to add hard registers and
602 continue to use the gcc hard register numbering for eh_frame. If the
603 extra SPE registers in eh_frame were numbered starting from the
604 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
605 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
606 avoid invalidating older SPE eh_frame info.
608 We must map them here to avoid huge unwinder tables mostly consisting
610 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
611 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
613 /* Use gcc hard register numbering for eh_frame. */
614 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
616 /* 1 for registers that have pervasive standard uses
617 and are not available for the register allocator.
619 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
620 as a local register; for all other OS's r2 is the TOC pointer.
622 cr5 is not supposed to be used.
624 On System V implementations, r13 is fixed and not available for use. */
626 #define FIXED_REGISTERS \
627 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
628 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
629 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
630 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
631 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
632 /* AltiVec registers. */ \
633 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
634 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
639 /* 1 for registers not available across function calls.
640 These must include the FIXED_REGISTERS and also any
641 registers that can be used without being saved.
642 The latter must include the registers where values are returned
643 and the register where structure-value addresses are passed.
644 Aside from that, you can include as many other registers as you like. */
646 #define CALL_USED_REGISTERS \
647 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
648 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
649 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
650 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
651 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
652 /* AltiVec registers. */ \
653 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
654 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
659 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
660 the entire set of `FIXED_REGISTERS' be included.
661 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
662 This macro is optional. If not specified, it defaults to the value
663 of `CALL_USED_REGISTERS'. */
665 #define CALL_REALLY_USED_REGISTERS \
666 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
667 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
668 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
669 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
670 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
671 /* AltiVec registers. */ \
672 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
673 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
684 #define MAX_CR_REGNO 75
686 #define FIRST_ALTIVEC_REGNO 77
687 #define LAST_ALTIVEC_REGNO 108
688 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
689 #define VRSAVE_REGNO 109
690 #define VSCR_REGNO 110
691 #define SPE_ACC_REGNO 111
692 #define SPEFSCR_REGNO 112
694 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
695 #define FIRST_SAVED_FP_REGNO (14+32)
696 #define FIRST_SAVED_GP_REGNO 13
698 /* List the order in which to allocate registers. Each register must be
699 listed once, even those in FIXED_REGISTERS.
701 We allocate in the following order:
702 fp0 (not saved or used for anything)
703 fp13 - fp2 (not saved; incoming fp arg registers)
704 fp1 (not saved; return value)
705 fp31 - fp14 (saved; order given to save least number)
706 cr7, cr6 (not saved or special)
707 cr1 (not saved, but used for FP operations)
708 cr0 (not saved, but used for arithmetic operations)
709 cr4, cr3, cr2 (saved)
710 r0 (not saved; cannot be base reg)
711 r9 (not saved; best for TImode)
712 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
713 r3 (not saved; return value register)
714 r31 - r13 (saved; order given to save least number)
715 r12 (not saved; if used for DImode or DFmode would use r13)
716 mq (not saved; best to use it if we can)
717 ctr (not saved; when we have the choice ctr is better)
719 cr5, r1, r2, ap, xer (fixed)
720 v0 - v1 (not saved or used for anything)
721 v13 - v3 (not saved; incoming vector arg registers)
722 v2 (not saved; incoming vector arg reg; return value)
723 v19 - v14 (not saved or used for anything)
724 v31 - v20 (saved; order given to save least number)
726 spe_acc, spefscr (fixed)
731 #define MAYBE_R2_AVAILABLE
732 #define MAYBE_R2_FIXED 2,
734 #define MAYBE_R2_AVAILABLE 2,
735 #define MAYBE_R2_FIXED
738 #define REG_ALLOC_ORDER \
740 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
742 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
743 50, 49, 48, 47, 46, \
744 75, 74, 69, 68, 72, 71, 70, \
745 0, MAYBE_R2_AVAILABLE \
746 9, 11, 10, 8, 7, 6, 5, 4, \
748 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
749 18, 17, 16, 15, 14, 13, 12, \
751 73, 1, MAYBE_R2_FIXED 67, 76, \
752 /* AltiVec registers. */ \
754 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
756 96, 95, 94, 93, 92, 91, \
757 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
762 /* True if register is floating-point. */
763 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
765 /* True if register is a condition register. */
766 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
768 /* True if register is a condition register, but not cr0. */
769 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
771 /* True if register is an integer register. */
772 #define INT_REGNO_P(N) \
773 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
775 /* SPE SIMD registers are just the GPRs. */
776 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
778 /* True if register is the XER register. */
779 #define XER_REGNO_P(N) ((N) == XER_REGNO)
781 /* True if register is an AltiVec register. */
782 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
784 /* Return number of consecutive hard regs needed starting at reg REGNO
785 to hold something of mode MODE. */
787 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs ((REGNO), (MODE))
789 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
790 ((TARGET_32BIT && TARGET_POWERPC64 \
791 && (GET_MODE_SIZE (MODE) > 4) \
792 && INT_REGNO_P (REGNO)) ? 1 : 0)
794 #define ALTIVEC_VECTOR_MODE(MODE) \
795 ((MODE) == V16QImode \
796 || (MODE) == V8HImode \
797 || (MODE) == V4SFmode \
798 || (MODE) == V4SImode)
800 #define SPE_VECTOR_MODE(MODE) \
801 ((MODE) == V4HImode \
802 || (MODE) == V2SFmode \
803 || (MODE) == V1DImode \
804 || (MODE) == V2SImode)
806 #define UNITS_PER_SIMD_WORD \
807 (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD \
808 : (TARGET_SPE ? UNITS_PER_SPE_WORD : UNITS_PER_WORD))
810 /* Value is TRUE if hard register REGNO can hold a value of
811 machine-mode MODE. */
812 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
813 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
815 /* Value is 1 if it is a good idea to tie two pseudo registers
816 when one has mode MODE1 and one has mode MODE2.
817 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
818 for any hard reg, then this must be 0 for correct output. */
819 #define MODES_TIEABLE_P(MODE1, MODE2) \
820 (SCALAR_FLOAT_MODE_P (MODE1) \
821 ? SCALAR_FLOAT_MODE_P (MODE2) \
822 : SCALAR_FLOAT_MODE_P (MODE2) \
823 ? SCALAR_FLOAT_MODE_P (MODE1) \
824 : GET_MODE_CLASS (MODE1) == MODE_CC \
825 ? GET_MODE_CLASS (MODE2) == MODE_CC \
826 : GET_MODE_CLASS (MODE2) == MODE_CC \
827 ? GET_MODE_CLASS (MODE1) == MODE_CC \
828 : SPE_VECTOR_MODE (MODE1) \
829 ? SPE_VECTOR_MODE (MODE2) \
830 : SPE_VECTOR_MODE (MODE2) \
831 ? SPE_VECTOR_MODE (MODE1) \
832 : ALTIVEC_VECTOR_MODE (MODE1) \
833 ? ALTIVEC_VECTOR_MODE (MODE2) \
834 : ALTIVEC_VECTOR_MODE (MODE2) \
835 ? ALTIVEC_VECTOR_MODE (MODE1) \
838 /* Post-reload, we can't use any new AltiVec registers, as we already
839 emitted the vrsave mask. */
841 #define HARD_REGNO_RENAME_OK(SRC, DST) \
842 (! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST])
844 /* A C expression returning the cost of moving data from a register of class
845 CLASS1 to one of CLASS2. */
847 #define REGISTER_MOVE_COST rs6000_register_move_cost
849 /* A C expressions returning the cost of moving data of MODE from a register to
852 #define MEMORY_MOVE_COST rs6000_memory_move_cost
854 /* Specify the cost of a branch insn; roughly the number of extra insns that
855 should be added to avoid a branch.
857 Set this to 3 on the RS/6000 since that is roughly the average cost of an
858 unscheduled conditional branch. */
860 #define BRANCH_COST 3
862 /* Override BRANCH_COST heuristic which empirically produces worse
863 performance for removing short circuiting from the logical ops. */
865 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
867 /* A fixed register used at prologue and epilogue generation to fix
868 addressing modes. The SPE needs heavy addressing fixes at the last
869 minute, and it's best to save a register for it.
871 AltiVec also needs fixes, but we've gotten around using r11, which
872 is actually wrong because when use_backchain_to_restore_sp is true,
873 we end up clobbering r11.
875 The AltiVec case needs to be fixed. Dunno if we should break ABI
876 compatibility and reserve a register for it as well.. */
878 #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11)
880 /* Define this macro to change register usage conditional on target
883 #define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
885 /* Specify the registers used for certain standard purposes.
886 The values of these macros are register numbers. */
888 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
889 /* #define PC_REGNUM */
891 /* Register to use for pushing function arguments. */
892 #define STACK_POINTER_REGNUM 1
894 /* Base register for access to local variables of the function. */
895 #define HARD_FRAME_POINTER_REGNUM 31
897 /* Base register for access to local variables of the function. */
898 #define FRAME_POINTER_REGNUM 113
900 /* Value should be nonzero if functions must have frame pointers.
901 Zero means the frame pointer need not be set up (and parms
902 may be accessed via the stack pointer) in functions that seem suitable.
903 This is computed in `reload', in reload1.c. */
904 #define FRAME_POINTER_REQUIRED 0
906 /* Base register for access to arguments of the function. */
907 #define ARG_POINTER_REGNUM 67
909 /* Place to put static chain when calling a function that requires it. */
910 #define STATIC_CHAIN_REGNUM 11
912 /* Link register number. */
913 #define LINK_REGISTER_REGNUM 65
915 /* Count register number. */
916 #define COUNT_REGISTER_REGNUM 66
918 /* Define the classes of registers for register constraints in the
919 machine description. Also define ranges of constants.
921 One of the classes must always be named ALL_REGS and include all hard regs.
922 If there is more than one class, another class must be named NO_REGS
923 and contain no registers.
925 The name GENERAL_REGS must be the name of a class (or an alias for
926 another name such as ALL_REGS). This is the class of registers
927 that is allowed by "g" or "r" in a register constraint.
928 Also, registers outside this class are allocated only when
929 instructions express preferences for them.
931 The classes must be numbered in nondecreasing order; that is,
932 a larger-numbered class must never be contained completely
933 in a smaller-numbered class.
935 For any two classes, it is very desirable that there be another
936 class that represents their union. */
938 /* The RS/6000 has three types of registers, fixed-point, floating-point,
939 and condition registers, plus three special registers, MQ, CTR, and the
940 link register. AltiVec adds a vector register class.
942 However, r0 is special in that it cannot be used as a base register.
943 So make a class for registers valid as base registers.
945 Also, cr0 is the only condition code register that can be used in
946 arithmetic insns, so make a separate class for it. */
974 #define N_REG_CLASSES (int) LIM_REG_CLASSES
976 /* Give names of register classes as strings for dump file. */
978 #define REG_CLASS_NAMES \
989 "NON_SPECIAL_REGS", \
993 "LINK_OR_CTR_REGS", \
995 "SPEC_OR_GEN_REGS", \
1003 /* Define which registers fit in which classes.
1004 This is an initializer for a vector of HARD_REG_SET
1005 of length N_REG_CLASSES. */
1007 #define REG_CLASS_CONTENTS \
1009 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1010 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
1011 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
1012 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1013 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1014 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1015 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1016 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1017 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1018 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
1019 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1020 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1021 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1022 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1023 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1024 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
1025 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1026 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1027 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1028 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1029 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \
1032 /* The same information, inverted:
1033 Return the class number of the smallest class containing
1034 reg number REGNO. This could be a conditional expression
1035 or could index an array. */
1037 #define REGNO_REG_CLASS(REGNO) \
1038 ((REGNO) == 0 ? GENERAL_REGS \
1039 : (REGNO) < 32 ? BASE_REGS \
1040 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1041 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1042 : (REGNO) == CR0_REGNO ? CR0_REGS \
1043 : CR_REGNO_P (REGNO) ? CR_REGS \
1044 : (REGNO) == MQ_REGNO ? MQ_REGS \
1045 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1046 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1047 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1048 : (REGNO) == XER_REGNO ? XER_REGS \
1049 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1050 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1051 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
1052 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
1053 : (REGNO) == FRAME_POINTER_REGNUM ? BASE_REGS \
1056 /* The class value for index registers, and the one for base regs. */
1057 #define INDEX_REG_CLASS GENERAL_REGS
1058 #define BASE_REG_CLASS BASE_REGS
1060 /* Given an rtx X being reloaded into a reg required to be
1061 in class CLASS, return the class of reg to actually use.
1062 In general this is just CLASS; but on some machines
1063 in some cases it is preferable to use a more restrictive class.
1065 On the RS/6000, we have to return NO_REGS when we want to reload a
1066 floating-point CONST_DOUBLE to force it to be copied to memory.
1068 We also don't want to reload integer values into floating-point
1069 registers if we can at all help it. In fact, this can
1070 cause reload to die, if it tries to generate a reload of CTR
1071 into a FP register and discovers it doesn't have the memory location
1074 ??? Would it be a good idea to have reload do the converse, that is
1075 try to reload floating modes into FP registers if possible?
1078 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1080 && reg_classes_intersect_p ((CLASS), FLOAT_REGS)) \
1082 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1083 && (CLASS) == NON_SPECIAL_REGS) \
1087 /* Return the register class of a scratch register needed to copy IN into
1088 or out of a register in CLASS in MODE. If it can be done directly,
1089 NO_REGS is returned. */
1091 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1092 rs6000_secondary_reload_class (CLASS, MODE, IN)
1094 /* If we are copying between FP or AltiVec registers and anything
1095 else, we need a memory location. */
1097 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1098 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1099 || (CLASS2) == FLOAT_REGS \
1100 || (CLASS1) == ALTIVEC_REGS \
1101 || (CLASS2) == ALTIVEC_REGS))
1103 /* Return the maximum number of consecutive registers
1104 needed to represent mode MODE in a register of class CLASS.
1106 On RS/6000, this is the size of MODE in words,
1107 except in the FP regs, where a single reg is enough for two words. */
1108 #define CLASS_MAX_NREGS(CLASS, MODE) \
1109 (((CLASS) == FLOAT_REGS) \
1110 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1111 : (TARGET_E500_DOUBLE && (CLASS) == GENERAL_REGS && (MODE) == DFmode) \
1113 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1115 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
1117 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1118 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1119 ? ((GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8 \
1120 || TARGET_IEEEQUAD) \
1121 && reg_classes_intersect_p (FLOAT_REGS, CLASS)) \
1122 : (((TARGET_E500_DOUBLE \
1123 && ((((TO) == DFmode) + ((FROM) == DFmode)) == 1 \
1124 || (((TO) == DImode) + ((FROM) == DImode)) == 1)) \
1126 && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1)) \
1127 && reg_classes_intersect_p (GENERAL_REGS, CLASS)))
1129 /* Stack layout; function entry, exit and calling. */
1131 /* Enumeration to give which calling sequence to use. */
1134 ABI_AIX, /* IBM's AIX */
1135 ABI_V4, /* System V.4/eabi */
1136 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1139 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1141 /* Define this if pushing a word on the stack
1142 makes the stack pointer a smaller address. */
1143 #define STACK_GROWS_DOWNWARD
1145 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1146 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1148 /* Define this to nonzero if the nominal address of the stack frame
1149 is at the high-address end of the local variables;
1150 that is, each additional local variable allocated
1151 goes at a more negative offset in the frame.
1153 On the RS/6000, we grow upwards, from the area after the outgoing
1155 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0)
1157 /* Size of the outgoing register save area */
1158 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1159 || DEFAULT_ABI == ABI_DARWIN) \
1160 ? (TARGET_64BIT ? 64 : 32) \
1163 /* Size of the fixed area on the stack */
1164 #define RS6000_SAVE_AREA \
1165 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1166 << (TARGET_64BIT ? 1 : 0))
1168 /* MEM representing address to save the TOC register */
1169 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1170 plus_constant (stack_pointer_rtx, \
1171 (TARGET_32BIT ? 20 : 40)))
1173 /* Align an address */
1174 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1176 /* Offset within stack frame to start allocating local variables at.
1177 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1178 first local allocated. Otherwise, it is the offset to the BEGINNING
1179 of the first local allocated.
1181 On the RS/6000, the frame pointer is the same as the stack pointer,
1182 except for dynamic allocations. So we start after the fixed area and
1183 outgoing parameter area. */
1185 #define STARTING_FRAME_OFFSET \
1186 (FRAME_GROWS_DOWNWARD \
1188 : (RS6000_ALIGN (current_function_outgoing_args_size, \
1189 TARGET_ALTIVEC ? 16 : 8) \
1190 + RS6000_SAVE_AREA))
1192 /* Offset from the stack pointer register to an item dynamically
1193 allocated on the stack, e.g., by `alloca'.
1195 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1196 length of the outgoing arguments. The default is correct for most
1197 machines. See `function.c' for details. */
1198 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1199 (RS6000_ALIGN (current_function_outgoing_args_size, \
1200 TARGET_ALTIVEC ? 16 : 8) \
1201 + (STACK_POINTER_OFFSET))
1203 /* If we generate an insn to push BYTES bytes,
1204 this says how many the stack pointer really advances by.
1205 On RS/6000, don't define this because there are no push insns. */
1206 /* #define PUSH_ROUNDING(BYTES) */
1208 /* Offset of first parameter from the argument pointer register value.
1209 On the RS/6000, we define the argument pointer to the start of the fixed
1211 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1213 /* Offset from the argument pointer register value to the top of
1214 stack. This is different from FIRST_PARM_OFFSET because of the
1215 register save area. */
1216 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1218 /* Define this if stack space is still allocated for a parameter passed
1219 in a register. The value is the number of bytes allocated to this
1221 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1223 /* Define this if the above stack space is to be considered part of the
1224 space allocated by the caller. */
1225 #define OUTGOING_REG_PARM_STACK_SPACE
1227 /* This is the difference between the logical top of stack and the actual sp.
1229 For the RS/6000, sp points past the fixed area. */
1230 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1232 /* Define this if the maximum size of all the outgoing args is to be
1233 accumulated and pushed during the prologue. The amount can be
1234 found in the variable current_function_outgoing_args_size. */
1235 #define ACCUMULATE_OUTGOING_ARGS 1
1237 /* Value is the number of bytes of arguments automatically
1238 popped when returning from a subroutine call.
1239 FUNDECL is the declaration node of the function (as a tree),
1240 FUNTYPE is the data type of the function (as a tree),
1241 or for a library call it is an identifier node for the subroutine name.
1242 SIZE is the number of bytes of arguments passed on the stack. */
1244 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1246 /* Define how to find the value returned by a function.
1247 VALTYPE is the data type of the value (as a tree).
1248 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1249 otherwise, FUNC is 0. */
1251 #define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC))
1253 /* Define how to find the value returned by a library function
1254 assuming the value has mode MODE. */
1256 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1258 /* DRAFT_V4_STRUCT_RET defaults off. */
1259 #define DRAFT_V4_STRUCT_RET 0
1261 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1262 #define DEFAULT_PCC_STRUCT_RETURN 0
1264 /* Mode of stack savearea.
1265 FUNCTION is VOIDmode because calling convention maintains SP.
1266 BLOCK needs Pmode for SP.
1267 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1268 #define STACK_SAVEAREA_MODE(LEVEL) \
1269 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1270 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1272 /* Minimum and maximum general purpose registers used to hold arguments. */
1273 #define GP_ARG_MIN_REG 3
1274 #define GP_ARG_MAX_REG 10
1275 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1277 /* Minimum and maximum floating point registers used to hold arguments. */
1278 #define FP_ARG_MIN_REG 33
1279 #define FP_ARG_AIX_MAX_REG 45
1280 #define FP_ARG_V4_MAX_REG 40
1281 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1282 || DEFAULT_ABI == ABI_DARWIN) \
1283 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1284 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1286 /* Minimum and maximum AltiVec registers used to hold arguments. */
1287 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1288 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1289 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1291 /* Return registers */
1292 #define GP_ARG_RETURN GP_ARG_MIN_REG
1293 #define FP_ARG_RETURN FP_ARG_MIN_REG
1294 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1296 /* Flags for the call/call_value rtl operations set up by function_arg */
1297 #define CALL_NORMAL 0x00000000 /* no special processing */
1298 /* Bits in 0x00000001 are unused. */
1299 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1300 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1301 #define CALL_LONG 0x00000008 /* always call indirect */
1302 #define CALL_LIBCALL 0x00000010 /* libcall */
1304 /* We don't have prologue and epilogue functions to save/restore
1305 everything for most ABIs. */
1306 #define WORLD_SAVE_P(INFO) 0
1308 /* 1 if N is a possible register number for a function value
1309 as seen by the caller.
1311 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1312 #define FUNCTION_VALUE_REGNO_P(N) \
1313 ((N) == GP_ARG_RETURN \
1314 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
1315 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1317 /* 1 if N is a possible register number for function argument passing.
1318 On RS/6000, these are r3-r10 and fp1-fp13.
1319 On AltiVec, v2 - v13 are used for passing vectors. */
1320 #define FUNCTION_ARG_REGNO_P(N) \
1321 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1322 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1323 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1324 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1325 && TARGET_HARD_FLOAT && TARGET_FPRS))
1327 /* Define a data type for recording info about an argument list
1328 during the scan of that argument list. This data type should
1329 hold all necessary information about the function itself
1330 and about the args processed so far, enough to enable macros
1331 such as FUNCTION_ARG to determine where the next arg should go.
1333 On the RS/6000, this is a structure. The first element is the number of
1334 total argument words, the second is used to store the next
1335 floating-point register number, and the third says how many more args we
1336 have prototype types for.
1338 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1339 the next available GP register, `fregno' is the next available FP
1340 register, and `words' is the number of words used on the stack.
1342 The varargs/stdarg support requires that this structure's size
1343 be a multiple of sizeof(int). */
1345 typedef struct rs6000_args
1347 int words; /* # words used for passing GP registers */
1348 int fregno; /* next available FP register */
1349 int vregno; /* next available AltiVec register */
1350 int nargs_prototype; /* # args left in the current prototype */
1351 int prototype; /* Whether a prototype was defined */
1352 int stdarg; /* Whether function is a stdarg function. */
1353 int call_cookie; /* Do special things for this call */
1354 int sysv_gregno; /* next available GP register */
1355 int intoffset; /* running offset in struct (darwin64) */
1356 int use_stack; /* any part of struct on stack (darwin64) */
1357 int named; /* false for varargs params */
1360 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1361 for a call to a function whose data type is FNTYPE.
1362 For a library call, FNTYPE is 0. */
1364 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1365 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
1367 /* Similar, but when scanning the definition of a procedure. We always
1368 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1370 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1371 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
1373 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1375 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1376 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
1378 /* Update the data in CUM to advance over an argument
1379 of mode MODE and data type TYPE.
1380 (TYPE is null for libcalls where that information may not be available.) */
1382 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1383 function_arg_advance (&CUM, MODE, TYPE, NAMED, 0)
1385 /* Determine where to put an argument to a function.
1386 Value is zero to push the argument on the stack,
1387 or a hard register in which to store the argument.
1389 MODE is the argument's machine mode.
1390 TYPE is the data type of the argument (as a tree).
1391 This is null for libcalls where that information may
1393 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1394 the preceding args and about the function being called.
1395 NAMED is nonzero if this argument is a named parameter
1396 (otherwise it is an extra parameter matching an ellipsis).
1398 On RS/6000 the first eight words of non-FP are normally in registers
1399 and the rest are pushed. The first 13 FP args are in registers.
1401 If this is floating-point and no prototype is specified, we use
1402 both an FP and integer register (or possibly FP reg and stack). Library
1403 functions (when TYPE is zero) always have the proper types for args,
1404 so we can pass the FP value just in one register. emit_library_function
1405 doesn't support EXPR_LIST anyway. */
1407 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1408 function_arg (&CUM, MODE, TYPE, NAMED)
1410 /* If defined, a C expression which determines whether, and in which
1411 direction, to pad out an argument with extra space. The value
1412 should be of type `enum direction': either `upward' to pad above
1413 the argument, `downward' to pad below, or `none' to inhibit
1416 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1418 /* If defined, a C expression that gives the alignment boundary, in bits,
1419 of an argument with the specified mode and type. If it is not defined,
1420 PARM_BOUNDARY is used for all arguments. */
1422 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1423 function_arg_boundary (MODE, TYPE)
1425 /* Implement `va_start' for varargs and stdarg. */
1426 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1427 rs6000_va_start (valist, nextarg)
1429 #define PAD_VARARGS_DOWN \
1430 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1432 /* Output assembler code to FILE to increment profiler label # LABELNO
1433 for profiling a function entry. */
1435 #define FUNCTION_PROFILER(FILE, LABELNO) \
1436 output_function_profiler ((FILE), (LABELNO));
1438 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1439 the stack pointer does not matter. No definition is equivalent to
1442 On the RS/6000, this is nonzero because we can restore the stack from
1443 its backpointer, which we maintain. */
1444 #define EXIT_IGNORE_STACK 1
1446 /* Define this macro as a C expression that is nonzero for registers
1447 that are used by the epilogue or the return' pattern. The stack
1448 and frame pointer registers are already be assumed to be used as
1451 #define EPILOGUE_USES(REGNO) \
1452 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1453 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1454 || (current_function_calls_eh_return \
1459 /* TRAMPOLINE_TEMPLATE deleted */
1461 /* Length in units of the trampoline for entering a nested function. */
1463 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1465 /* Emit RTL insns to initialize the variable parts of a trampoline.
1466 FNADDR is an RTX for the address of the function's pure code.
1467 CXT is an RTX for the static chain value for the function. */
1469 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1470 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1472 /* Definitions for __builtin_return_address and __builtin_frame_address.
1473 __builtin_return_address (0) should give link register (65), enable
1475 /* This should be uncommented, so that the link register is used, but
1476 currently this would result in unmatched insns and spilling fixed
1477 registers so we'll leave it for another day. When these problems are
1478 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1480 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1482 /* Number of bytes into the frame return addresses can be found. See
1483 rs6000_stack_info in rs6000.c for more information on how the different
1484 abi's store the return address. */
1485 #define RETURN_ADDRESS_OFFSET \
1486 ((DEFAULT_ABI == ABI_AIX \
1487 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
1488 (DEFAULT_ABI == ABI_V4) ? 4 : \
1489 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1491 /* The current return address is in link register (65). The return address
1492 of anything farther back is accessed normally at an offset of 8 from the
1494 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1495 (rs6000_return_addr (COUNT, FRAME))
1498 /* Definitions for register eliminations.
1500 We have two registers that can be eliminated on the RS/6000. First, the
1501 frame pointer register can often be eliminated in favor of the stack
1502 pointer register. Secondly, the argument pointer register can always be
1503 eliminated; it is replaced with either the stack or frame pointer.
1505 In addition, we use the elimination mechanism to see if r30 is needed
1506 Initially we assume that it isn't. If it is, we spill it. This is done
1507 by making it an eliminable register. We replace it with itself so that
1508 if it isn't needed, then existing uses won't be modified. */
1510 /* This is an array of structures. Each structure initializes one pair
1511 of eliminable registers. The "from" register number is given first,
1512 followed by "to". Eliminations of the same "from" register are listed
1513 in order of preference. */
1514 #define ELIMINABLE_REGS \
1515 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1516 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1517 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1518 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1519 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1520 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1522 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1523 Frame pointer elimination is automatically handled.
1525 For the RS/6000, if frame pointer elimination is being done, we would like
1526 to convert ap into fp, not sp.
1528 We need r30 if -mminimal-toc was specified, and there are constant pool
1531 #define CAN_ELIMINATE(FROM, TO) \
1532 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1533 ? ! frame_pointer_needed \
1534 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1535 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1538 /* Define the offset between two registers, one to be eliminated, and the other
1539 its replacement, at the start of a routine. */
1540 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1541 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1543 /* Addressing modes, and classification of registers for them. */
1545 #define HAVE_PRE_DECREMENT 1
1546 #define HAVE_PRE_INCREMENT 1
1548 /* Macros to check register numbers against specific register classes. */
1550 /* These assume that REGNO is a hard or pseudo reg number.
1551 They give nonzero only if REGNO is a hard reg of the suitable class
1552 or a pseudo reg currently allocated to a suitable hard reg.
1553 Since they use reg_renumber, they are safe only once reg_renumber
1554 has been allocated, which happens in local-alloc.c. */
1556 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1557 ((REGNO) < FIRST_PSEUDO_REGISTER \
1558 ? (REGNO) <= 31 || (REGNO) == 67 \
1559 || (REGNO) == FRAME_POINTER_REGNUM \
1560 : (reg_renumber[REGNO] >= 0 \
1561 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1562 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1564 #define REGNO_OK_FOR_BASE_P(REGNO) \
1565 ((REGNO) < FIRST_PSEUDO_REGISTER \
1566 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1567 || (REGNO) == FRAME_POINTER_REGNUM \
1568 : (reg_renumber[REGNO] > 0 \
1569 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1570 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1572 /* Maximum number of registers that can appear in a valid memory address. */
1574 #define MAX_REGS_PER_ADDRESS 2
1576 /* Recognize any constant value that is a valid address. */
1578 #define CONSTANT_ADDRESS_P(X) \
1579 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1580 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1581 || GET_CODE (X) == HIGH)
1583 /* Nonzero if the constant value X is a legitimate general operand.
1584 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1586 On the RS/6000, all integer constants are acceptable, most won't be valid
1587 for particular insns, though. Only easy FP constants are
1590 #define LEGITIMATE_CONSTANT_P(X) \
1591 (((GET_CODE (X) != CONST_DOUBLE \
1592 && GET_CODE (X) != CONST_VECTOR) \
1593 || GET_MODE (X) == VOIDmode \
1594 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1595 || easy_fp_constant (X, GET_MODE (X)) \
1596 || easy_vector_constant (X, GET_MODE (X))) \
1597 && !rs6000_tls_referenced_p (X))
1599 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1600 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1601 && EASY_VECTOR_15((n) >> 1))
1603 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1604 and check its validity for a certain class.
1605 We have two alternate definitions for each of them.
1606 The usual definition accepts all pseudo regs; the other rejects
1607 them unless they have been allocated suitable hard regs.
1608 The symbol REG_OK_STRICT causes the latter definition to be used.
1610 Most source files want to accept pseudo regs in the hope that
1611 they will get allocated to the class that the insn wants them to be in.
1612 Source files for reload pass need to be strict.
1613 After reload, it makes no difference, since pseudo regs have
1614 been eliminated by then. */
1616 #ifdef REG_OK_STRICT
1617 # define REG_OK_STRICT_FLAG 1
1619 # define REG_OK_STRICT_FLAG 0
1622 /* Nonzero if X is a hard reg that can be used as an index
1623 or if it is a pseudo reg in the non-strict case. */
1624 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1625 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1626 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1628 /* Nonzero if X is a hard reg that can be used as a base reg
1629 or if it is a pseudo reg in the non-strict case. */
1630 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1631 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1632 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1634 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
1635 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
1637 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1638 that is a valid memory address for an instruction.
1639 The MODE argument is the machine mode for the MEM expression
1640 that wants to use this address.
1642 On the RS/6000, there are four valid addresses: a SYMBOL_REF that
1643 refers to a constant pool entry of an address (or the sum of it
1644 plus a constant), a short (16-bit signed) constant plus a register,
1645 the sum of two registers, or a register indirect, possibly with an
1646 auto-increment. For DFmode and DImode with a constant plus register,
1647 we must ensure that both words are addressable or PowerPC64 with offset
1650 For modes spanning multiple registers (DFmode in 32-bit GPRs,
1651 32-bit DImode, TImode), indexed addressing cannot be used because
1652 adjacent memory cells are accessed by adding word-sized offsets
1653 during assembly output. */
1655 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1656 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
1660 /* Try machine-dependent ways of modifying an illegitimate address
1661 to be legitimate. If we find one, return the new, valid address.
1662 This macro is used in only one place: `memory_address' in explow.c.
1664 OLDX is the address as it was before break_out_memory_refs was called.
1665 In some cases it is useful to look at this to decide what needs to be done.
1667 MODE and WIN are passed so that this macro can use
1668 GO_IF_LEGITIMATE_ADDRESS.
1670 It is always safe for this macro to do nothing. It exists to recognize
1671 opportunities to optimize the output.
1673 On RS/6000, first check for the sum of a register with a constant
1674 integer that is out of range. If so, generate code to add the
1675 constant with the low-order 16 bits masked to the register and force
1676 this result into another register (this can be done with `cau').
1677 Then generate an address of REG+(CONST&0xffff), allowing for the
1678 possibility of bit 16 being a one.
1680 Then check for the sum of a register and something not constant, try to
1681 load the other things into a register and return the sum. */
1683 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1684 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
1685 if (result != NULL_RTX) \
1692 /* Try a machine-dependent way of reloading an illegitimate address
1693 operand. If we find one, push the reload and jump to WIN. This
1694 macro is used in only one place: `find_reloads_address' in reload.c.
1696 Implemented on rs6000 by rs6000_legitimize_reload_address.
1697 Note that (X) is evaluated twice; this is safe in current usage. */
1699 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1702 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
1703 (int)(TYPE), (IND_LEVELS), &win); \
1708 /* Go to LABEL if ADDR (a legitimate address expression)
1709 has an effect that depends on the machine mode it is used for. */
1711 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1713 if (rs6000_mode_dependent_address (ADDR)) \
1717 /* The register number of the register used to address a table of
1718 static data addresses in memory. In some cases this register is
1719 defined by a processor's "application binary interface" (ABI).
1720 When this macro is defined, RTL is generated for this register
1721 once, as with the stack pointer and frame pointer registers. If
1722 this macro is not defined, it is up to the machine-dependent files
1723 to allocate such a register (if necessary). */
1725 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1726 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
1728 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1730 /* Define this macro if the register defined by
1731 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1732 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1734 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1736 /* A C expression that is nonzero if X is a legitimate immediate
1737 operand on the target machine when generating position independent
1738 code. You can assume that X satisfies `CONSTANT_P', so you need
1739 not check this. You can also assume FLAG_PIC is true, so you need
1740 not check it either. You need not define this macro if all
1741 constants (including `SYMBOL_REF') can be immediate operands when
1742 generating position independent code. */
1744 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1746 /* Define this if some processing needs to be done immediately before
1747 emitting code for an insn. */
1749 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
1751 /* Specify the machine mode that this machine uses
1752 for the index in the tablejump instruction. */
1753 #define CASE_VECTOR_MODE SImode
1755 /* Define as C expression which evaluates to nonzero if the tablejump
1756 instruction expects the table to contain offsets from the address of the
1758 Do not define this if the table should contain absolute addresses. */
1759 #define CASE_VECTOR_PC_RELATIVE 1
1761 /* Define this as 1 if `char' should by default be signed; else as 0. */
1762 #define DEFAULT_SIGNED_CHAR 0
1764 /* This flag, if defined, says the same insns that convert to a signed fixnum
1765 also convert validly to an unsigned one. */
1767 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
1769 /* An integer expression for the size in bits of the largest integer machine
1770 mode that should actually be used. */
1772 /* Allow pairs of registers to be used, which is the intent of the default. */
1773 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1775 /* Max number of bytes we can move from memory to memory
1776 in one reasonably fast instruction. */
1777 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1778 #define MAX_MOVE_MAX 8
1780 /* Nonzero if access to memory by bytes is no faster than for words.
1781 Also nonzero if doing byte operations (specifically shifts) in registers
1783 #define SLOW_BYTE_ACCESS 1
1785 /* Define if operations between registers always perform the operation
1786 on the full register even if a narrower mode is specified. */
1787 #define WORD_REGISTER_OPERATIONS
1789 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1790 will either zero-extend or sign-extend. The value of this macro should
1791 be the code that says which one of the two operations is implicitly
1792 done, UNKNOWN if none. */
1793 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1795 /* Define if loading short immediate values into registers sign extends. */
1796 #define SHORT_IMMEDIATES_SIGN_EXTEND
1798 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1799 is done just by pretending it is already truncated. */
1800 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1802 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
1803 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1804 ((VALUE) = ((MODE) == SImode ? 32 : 64))
1806 /* The CTZ patterns return -1 for input of zero. */
1807 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1)
1809 /* Specify the machine mode that pointers have.
1810 After generation of rtl, the compiler makes no further distinction
1811 between pointers and any other objects of this machine mode. */
1812 #define Pmode (TARGET_32BIT ? SImode : DImode)
1814 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
1815 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
1817 /* Mode of a function address in a call instruction (for indexing purposes).
1818 Doesn't matter on RS/6000. */
1819 #define FUNCTION_MODE SImode
1821 /* Define this if addresses of constant functions
1822 shouldn't be put through pseudo regs where they can be cse'd.
1823 Desirable on machines where ordinary constants are expensive
1824 but a CALL with constant address is cheap. */
1825 #define NO_FUNCTION_CSE
1827 /* Define this to be nonzero if shift instructions ignore all but the low-order
1830 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
1831 have been dropped from the PowerPC architecture. */
1833 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
1835 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
1836 should be adjusted to reflect any required changes. This macro is used when
1837 there is some systematic length adjustment required that would be difficult
1838 to express in the length attribute. */
1840 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
1842 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
1843 COMPARE, return the mode to be used for the comparison. For
1844 floating-point, CCFPmode should be used. CCUNSmode should be used
1845 for unsigned comparisons. CCEQmode should be used when we are
1846 doing an inequality comparison on the result of a
1847 comparison. CCmode should be used in all other cases. */
1849 #define SELECT_CC_MODE(OP,X,Y) \
1850 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
1851 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
1852 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
1853 ? CCEQmode : CCmode))
1855 /* Can the condition code MODE be safely reversed? This is safe in
1856 all cases on this port, because at present it doesn't use the
1857 trapping FP comparisons (fcmpo). */
1858 #define REVERSIBLE_CC_MODE(MODE) 1
1860 /* Given a condition code and a mode, return the inverse condition. */
1861 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
1863 /* Define the information needed to generate branch and scc insns. This is
1864 stored from the compare operation. */
1866 extern GTY(()) rtx rs6000_compare_op0;
1867 extern GTY(()) rtx rs6000_compare_op1;
1868 extern int rs6000_compare_fp_p;
1870 /* Control the assembler format that we output. */
1872 /* A C string constant describing how to begin a comment in the target
1873 assembler language. The compiler assumes that the comment will end at
1874 the end of the line. */
1875 #define ASM_COMMENT_START " #"
1877 /* Flag to say the TOC is initialized */
1878 extern int toc_initialized;
1880 /* Macro to output a special constant pool entry. Go to WIN if we output
1881 it. Otherwise, it is written the usual way.
1883 On the RS/6000, toc entries are handled this way. */
1885 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
1886 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
1888 output_toc (FILE, X, LABELNO, MODE); \
1893 #ifdef HAVE_GAS_WEAK
1894 #define RS6000_WEAK 1
1896 #define RS6000_WEAK 0
1900 /* Used in lieu of ASM_WEAKEN_LABEL. */
1901 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
1904 fputs ("\t.weak\t", (FILE)); \
1905 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1906 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1907 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1910 fputs ("[DS]", (FILE)); \
1911 fputs ("\n\t.weak\t.", (FILE)); \
1912 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1914 fputc ('\n', (FILE)); \
1917 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
1918 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1919 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1921 fputs ("\t.set\t.", (FILE)); \
1922 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1923 fputs (",.", (FILE)); \
1924 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
1925 fputc ('\n', (FILE)); \
1932 #if HAVE_GAS_WEAKREF
1933 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
1936 fputs ("\t.weakref\t", (FILE)); \
1937 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1938 fputs (", ", (FILE)); \
1939 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
1940 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1941 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1943 fputs ("\n\t.weakref\t.", (FILE)); \
1944 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1945 fputs (", .", (FILE)); \
1946 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
1948 fputc ('\n', (FILE)); \
1952 /* This implements the `alias' attribute. */
1953 #undef ASM_OUTPUT_DEF_FROM_DECLS
1954 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
1957 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
1958 const char *name = IDENTIFIER_POINTER (TARGET); \
1959 if (TREE_CODE (DECL) == FUNCTION_DECL \
1960 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1962 if (TREE_PUBLIC (DECL)) \
1964 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
1966 fputs ("\t.globl\t.", FILE); \
1967 RS6000_OUTPUT_BASENAME (FILE, alias); \
1968 putc ('\n', FILE); \
1971 else if (TARGET_XCOFF) \
1973 fputs ("\t.lglobl\t.", FILE); \
1974 RS6000_OUTPUT_BASENAME (FILE, alias); \
1975 putc ('\n', FILE); \
1977 fputs ("\t.set\t.", FILE); \
1978 RS6000_OUTPUT_BASENAME (FILE, alias); \
1979 fputs (",.", FILE); \
1980 RS6000_OUTPUT_BASENAME (FILE, name); \
1981 fputc ('\n', FILE); \
1983 ASM_OUTPUT_DEF (FILE, alias, name); \
1987 #define TARGET_ASM_FILE_START rs6000_file_start
1989 /* Output to assembler file text saying following lines
1990 may contain character constants, extra white space, comments, etc. */
1992 #define ASM_APP_ON ""
1994 /* Output to assembler file text saying following lines
1995 no longer contain unusual constructs. */
1997 #define ASM_APP_OFF ""
1999 /* How to refer to registers in assembler output.
2000 This sequence is indexed by compiler's hard-register-number (see above). */
2002 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2004 #define REGISTER_NAMES \
2006 &rs6000_reg_names[ 0][0], /* r0 */ \
2007 &rs6000_reg_names[ 1][0], /* r1 */ \
2008 &rs6000_reg_names[ 2][0], /* r2 */ \
2009 &rs6000_reg_names[ 3][0], /* r3 */ \
2010 &rs6000_reg_names[ 4][0], /* r4 */ \
2011 &rs6000_reg_names[ 5][0], /* r5 */ \
2012 &rs6000_reg_names[ 6][0], /* r6 */ \
2013 &rs6000_reg_names[ 7][0], /* r7 */ \
2014 &rs6000_reg_names[ 8][0], /* r8 */ \
2015 &rs6000_reg_names[ 9][0], /* r9 */ \
2016 &rs6000_reg_names[10][0], /* r10 */ \
2017 &rs6000_reg_names[11][0], /* r11 */ \
2018 &rs6000_reg_names[12][0], /* r12 */ \
2019 &rs6000_reg_names[13][0], /* r13 */ \
2020 &rs6000_reg_names[14][0], /* r14 */ \
2021 &rs6000_reg_names[15][0], /* r15 */ \
2022 &rs6000_reg_names[16][0], /* r16 */ \
2023 &rs6000_reg_names[17][0], /* r17 */ \
2024 &rs6000_reg_names[18][0], /* r18 */ \
2025 &rs6000_reg_names[19][0], /* r19 */ \
2026 &rs6000_reg_names[20][0], /* r20 */ \
2027 &rs6000_reg_names[21][0], /* r21 */ \
2028 &rs6000_reg_names[22][0], /* r22 */ \
2029 &rs6000_reg_names[23][0], /* r23 */ \
2030 &rs6000_reg_names[24][0], /* r24 */ \
2031 &rs6000_reg_names[25][0], /* r25 */ \
2032 &rs6000_reg_names[26][0], /* r26 */ \
2033 &rs6000_reg_names[27][0], /* r27 */ \
2034 &rs6000_reg_names[28][0], /* r28 */ \
2035 &rs6000_reg_names[29][0], /* r29 */ \
2036 &rs6000_reg_names[30][0], /* r30 */ \
2037 &rs6000_reg_names[31][0], /* r31 */ \
2039 &rs6000_reg_names[32][0], /* fr0 */ \
2040 &rs6000_reg_names[33][0], /* fr1 */ \
2041 &rs6000_reg_names[34][0], /* fr2 */ \
2042 &rs6000_reg_names[35][0], /* fr3 */ \
2043 &rs6000_reg_names[36][0], /* fr4 */ \
2044 &rs6000_reg_names[37][0], /* fr5 */ \
2045 &rs6000_reg_names[38][0], /* fr6 */ \
2046 &rs6000_reg_names[39][0], /* fr7 */ \
2047 &rs6000_reg_names[40][0], /* fr8 */ \
2048 &rs6000_reg_names[41][0], /* fr9 */ \
2049 &rs6000_reg_names[42][0], /* fr10 */ \
2050 &rs6000_reg_names[43][0], /* fr11 */ \
2051 &rs6000_reg_names[44][0], /* fr12 */ \
2052 &rs6000_reg_names[45][0], /* fr13 */ \
2053 &rs6000_reg_names[46][0], /* fr14 */ \
2054 &rs6000_reg_names[47][0], /* fr15 */ \
2055 &rs6000_reg_names[48][0], /* fr16 */ \
2056 &rs6000_reg_names[49][0], /* fr17 */ \
2057 &rs6000_reg_names[50][0], /* fr18 */ \
2058 &rs6000_reg_names[51][0], /* fr19 */ \
2059 &rs6000_reg_names[52][0], /* fr20 */ \
2060 &rs6000_reg_names[53][0], /* fr21 */ \
2061 &rs6000_reg_names[54][0], /* fr22 */ \
2062 &rs6000_reg_names[55][0], /* fr23 */ \
2063 &rs6000_reg_names[56][0], /* fr24 */ \
2064 &rs6000_reg_names[57][0], /* fr25 */ \
2065 &rs6000_reg_names[58][0], /* fr26 */ \
2066 &rs6000_reg_names[59][0], /* fr27 */ \
2067 &rs6000_reg_names[60][0], /* fr28 */ \
2068 &rs6000_reg_names[61][0], /* fr29 */ \
2069 &rs6000_reg_names[62][0], /* fr30 */ \
2070 &rs6000_reg_names[63][0], /* fr31 */ \
2072 &rs6000_reg_names[64][0], /* mq */ \
2073 &rs6000_reg_names[65][0], /* lr */ \
2074 &rs6000_reg_names[66][0], /* ctr */ \
2075 &rs6000_reg_names[67][0], /* ap */ \
2077 &rs6000_reg_names[68][0], /* cr0 */ \
2078 &rs6000_reg_names[69][0], /* cr1 */ \
2079 &rs6000_reg_names[70][0], /* cr2 */ \
2080 &rs6000_reg_names[71][0], /* cr3 */ \
2081 &rs6000_reg_names[72][0], /* cr4 */ \
2082 &rs6000_reg_names[73][0], /* cr5 */ \
2083 &rs6000_reg_names[74][0], /* cr6 */ \
2084 &rs6000_reg_names[75][0], /* cr7 */ \
2086 &rs6000_reg_names[76][0], /* xer */ \
2088 &rs6000_reg_names[77][0], /* v0 */ \
2089 &rs6000_reg_names[78][0], /* v1 */ \
2090 &rs6000_reg_names[79][0], /* v2 */ \
2091 &rs6000_reg_names[80][0], /* v3 */ \
2092 &rs6000_reg_names[81][0], /* v4 */ \
2093 &rs6000_reg_names[82][0], /* v5 */ \
2094 &rs6000_reg_names[83][0], /* v6 */ \
2095 &rs6000_reg_names[84][0], /* v7 */ \
2096 &rs6000_reg_names[85][0], /* v8 */ \
2097 &rs6000_reg_names[86][0], /* v9 */ \
2098 &rs6000_reg_names[87][0], /* v10 */ \
2099 &rs6000_reg_names[88][0], /* v11 */ \
2100 &rs6000_reg_names[89][0], /* v12 */ \
2101 &rs6000_reg_names[90][0], /* v13 */ \
2102 &rs6000_reg_names[91][0], /* v14 */ \
2103 &rs6000_reg_names[92][0], /* v15 */ \
2104 &rs6000_reg_names[93][0], /* v16 */ \
2105 &rs6000_reg_names[94][0], /* v17 */ \
2106 &rs6000_reg_names[95][0], /* v18 */ \
2107 &rs6000_reg_names[96][0], /* v19 */ \
2108 &rs6000_reg_names[97][0], /* v20 */ \
2109 &rs6000_reg_names[98][0], /* v21 */ \
2110 &rs6000_reg_names[99][0], /* v22 */ \
2111 &rs6000_reg_names[100][0], /* v23 */ \
2112 &rs6000_reg_names[101][0], /* v24 */ \
2113 &rs6000_reg_names[102][0], /* v25 */ \
2114 &rs6000_reg_names[103][0], /* v26 */ \
2115 &rs6000_reg_names[104][0], /* v27 */ \
2116 &rs6000_reg_names[105][0], /* v28 */ \
2117 &rs6000_reg_names[106][0], /* v29 */ \
2118 &rs6000_reg_names[107][0], /* v30 */ \
2119 &rs6000_reg_names[108][0], /* v31 */ \
2120 &rs6000_reg_names[109][0], /* vrsave */ \
2121 &rs6000_reg_names[110][0], /* vscr */ \
2122 &rs6000_reg_names[111][0], /* spe_acc */ \
2123 &rs6000_reg_names[112][0], /* spefscr */ \
2124 &rs6000_reg_names[113][0], /* sfp */ \
2127 /* Table of additional register names to use in user input. */
2129 #define ADDITIONAL_REGISTER_NAMES \
2130 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2131 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2132 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2133 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2134 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2135 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2136 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2137 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2138 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2139 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2140 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2141 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2142 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2143 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2144 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2145 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2146 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2147 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2148 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2149 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2150 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2151 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2152 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2153 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2154 {"vrsave", 109}, {"vscr", 110}, \
2155 {"spe_acc", 111}, {"spefscr", 112}, \
2156 /* no additional names for: mq, lr, ctr, ap */ \
2157 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2158 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2159 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2161 /* Text to write out after a CALL that may be replaced by glue code by
2162 the loader. This depends on the AIX version. */
2163 #define RS6000_CALL_GLUE "cror 31,31,31"
2165 /* This is how to output an element of a case-vector that is relative. */
2167 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2168 do { char buf[100]; \
2169 fputs ("\t.long ", FILE); \
2170 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2171 assemble_name (FILE, buf); \
2173 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2174 assemble_name (FILE, buf); \
2175 putc ('\n', FILE); \
2178 /* This is how to output an assembler line
2179 that says to advance the location counter
2180 to a multiple of 2**LOG bytes. */
2182 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2184 fprintf (FILE, "\t.align %d\n", (LOG))
2186 /* Pick up the return address upon entry to a procedure. Used for
2187 dwarf2 unwind information. This also enables the table driven
2190 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2191 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2193 /* Describe how we implement __builtin_eh_return. */
2194 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2195 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2197 /* Print operand X (an rtx) in assembler syntax to file FILE.
2198 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2199 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2201 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2203 /* Define which CODE values are valid. */
2205 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2206 ((CODE) == '.' || (CODE) == '&')
2208 /* Print a memory address as an operand to reference that memory location. */
2210 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2212 /* uncomment for disabling the corresponding default options */
2213 /* #define MACHINE_no_sched_interblock */
2214 /* #define MACHINE_no_sched_speculative */
2215 /* #define MACHINE_no_sched_speculative_load */
2217 /* General flags. */
2218 extern int flag_pic;
2219 extern int optimize;
2220 extern int flag_expensive_optimizations;
2221 extern int frame_pointer_needed;
2223 enum rs6000_builtins
2225 /* AltiVec builtins. */
2226 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2227 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2228 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2229 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2230 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2231 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2232 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2233 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2234 ALTIVEC_BUILTIN_VADDUBM,
2235 ALTIVEC_BUILTIN_VADDUHM,
2236 ALTIVEC_BUILTIN_VADDUWM,
2237 ALTIVEC_BUILTIN_VADDFP,
2238 ALTIVEC_BUILTIN_VADDCUW,
2239 ALTIVEC_BUILTIN_VADDUBS,
2240 ALTIVEC_BUILTIN_VADDSBS,
2241 ALTIVEC_BUILTIN_VADDUHS,
2242 ALTIVEC_BUILTIN_VADDSHS,
2243 ALTIVEC_BUILTIN_VADDUWS,
2244 ALTIVEC_BUILTIN_VADDSWS,
2245 ALTIVEC_BUILTIN_VAND,
2246 ALTIVEC_BUILTIN_VANDC,
2247 ALTIVEC_BUILTIN_VAVGUB,
2248 ALTIVEC_BUILTIN_VAVGSB,
2249 ALTIVEC_BUILTIN_VAVGUH,
2250 ALTIVEC_BUILTIN_VAVGSH,
2251 ALTIVEC_BUILTIN_VAVGUW,
2252 ALTIVEC_BUILTIN_VAVGSW,
2253 ALTIVEC_BUILTIN_VCFUX,
2254 ALTIVEC_BUILTIN_VCFSX,
2255 ALTIVEC_BUILTIN_VCTSXS,
2256 ALTIVEC_BUILTIN_VCTUXS,
2257 ALTIVEC_BUILTIN_VCMPBFP,
2258 ALTIVEC_BUILTIN_VCMPEQUB,
2259 ALTIVEC_BUILTIN_VCMPEQUH,
2260 ALTIVEC_BUILTIN_VCMPEQUW,
2261 ALTIVEC_BUILTIN_VCMPEQFP,
2262 ALTIVEC_BUILTIN_VCMPGEFP,
2263 ALTIVEC_BUILTIN_VCMPGTUB,
2264 ALTIVEC_BUILTIN_VCMPGTSB,
2265 ALTIVEC_BUILTIN_VCMPGTUH,
2266 ALTIVEC_BUILTIN_VCMPGTSH,
2267 ALTIVEC_BUILTIN_VCMPGTUW,
2268 ALTIVEC_BUILTIN_VCMPGTSW,
2269 ALTIVEC_BUILTIN_VCMPGTFP,
2270 ALTIVEC_BUILTIN_VEXPTEFP,
2271 ALTIVEC_BUILTIN_VLOGEFP,
2272 ALTIVEC_BUILTIN_VMADDFP,
2273 ALTIVEC_BUILTIN_VMAXUB,
2274 ALTIVEC_BUILTIN_VMAXSB,
2275 ALTIVEC_BUILTIN_VMAXUH,
2276 ALTIVEC_BUILTIN_VMAXSH,
2277 ALTIVEC_BUILTIN_VMAXUW,
2278 ALTIVEC_BUILTIN_VMAXSW,
2279 ALTIVEC_BUILTIN_VMAXFP,
2280 ALTIVEC_BUILTIN_VMHADDSHS,
2281 ALTIVEC_BUILTIN_VMHRADDSHS,
2282 ALTIVEC_BUILTIN_VMLADDUHM,
2283 ALTIVEC_BUILTIN_VMRGHB,
2284 ALTIVEC_BUILTIN_VMRGHH,
2285 ALTIVEC_BUILTIN_VMRGHW,
2286 ALTIVEC_BUILTIN_VMRGLB,
2287 ALTIVEC_BUILTIN_VMRGLH,
2288 ALTIVEC_BUILTIN_VMRGLW,
2289 ALTIVEC_BUILTIN_VMSUMUBM,
2290 ALTIVEC_BUILTIN_VMSUMMBM,
2291 ALTIVEC_BUILTIN_VMSUMUHM,
2292 ALTIVEC_BUILTIN_VMSUMSHM,
2293 ALTIVEC_BUILTIN_VMSUMUHS,
2294 ALTIVEC_BUILTIN_VMSUMSHS,
2295 ALTIVEC_BUILTIN_VMINUB,
2296 ALTIVEC_BUILTIN_VMINSB,
2297 ALTIVEC_BUILTIN_VMINUH,
2298 ALTIVEC_BUILTIN_VMINSH,
2299 ALTIVEC_BUILTIN_VMINUW,
2300 ALTIVEC_BUILTIN_VMINSW,
2301 ALTIVEC_BUILTIN_VMINFP,
2302 ALTIVEC_BUILTIN_VMULEUB,
2303 ALTIVEC_BUILTIN_VMULESB,
2304 ALTIVEC_BUILTIN_VMULEUH,
2305 ALTIVEC_BUILTIN_VMULESH,
2306 ALTIVEC_BUILTIN_VMULOUB,
2307 ALTIVEC_BUILTIN_VMULOSB,
2308 ALTIVEC_BUILTIN_VMULOUH,
2309 ALTIVEC_BUILTIN_VMULOSH,
2310 ALTIVEC_BUILTIN_VNMSUBFP,
2311 ALTIVEC_BUILTIN_VNOR,
2312 ALTIVEC_BUILTIN_VOR,
2313 ALTIVEC_BUILTIN_VSEL_4SI,
2314 ALTIVEC_BUILTIN_VSEL_4SF,
2315 ALTIVEC_BUILTIN_VSEL_8HI,
2316 ALTIVEC_BUILTIN_VSEL_16QI,
2317 ALTIVEC_BUILTIN_VPERM_4SI,
2318 ALTIVEC_BUILTIN_VPERM_4SF,
2319 ALTIVEC_BUILTIN_VPERM_8HI,
2320 ALTIVEC_BUILTIN_VPERM_16QI,
2321 ALTIVEC_BUILTIN_VPKUHUM,
2322 ALTIVEC_BUILTIN_VPKUWUM,
2323 ALTIVEC_BUILTIN_VPKPX,
2324 ALTIVEC_BUILTIN_VPKUHSS,
2325 ALTIVEC_BUILTIN_VPKSHSS,
2326 ALTIVEC_BUILTIN_VPKUWSS,
2327 ALTIVEC_BUILTIN_VPKSWSS,
2328 ALTIVEC_BUILTIN_VPKUHUS,
2329 ALTIVEC_BUILTIN_VPKSHUS,
2330 ALTIVEC_BUILTIN_VPKUWUS,
2331 ALTIVEC_BUILTIN_VPKSWUS,
2332 ALTIVEC_BUILTIN_VREFP,
2333 ALTIVEC_BUILTIN_VRFIM,
2334 ALTIVEC_BUILTIN_VRFIN,
2335 ALTIVEC_BUILTIN_VRFIP,
2336 ALTIVEC_BUILTIN_VRFIZ,
2337 ALTIVEC_BUILTIN_VRLB,
2338 ALTIVEC_BUILTIN_VRLH,
2339 ALTIVEC_BUILTIN_VRLW,
2340 ALTIVEC_BUILTIN_VRSQRTEFP,
2341 ALTIVEC_BUILTIN_VSLB,
2342 ALTIVEC_BUILTIN_VSLH,
2343 ALTIVEC_BUILTIN_VSLW,
2344 ALTIVEC_BUILTIN_VSL,
2345 ALTIVEC_BUILTIN_VSLO,
2346 ALTIVEC_BUILTIN_VSPLTB,
2347 ALTIVEC_BUILTIN_VSPLTH,
2348 ALTIVEC_BUILTIN_VSPLTW,
2349 ALTIVEC_BUILTIN_VSPLTISB,
2350 ALTIVEC_BUILTIN_VSPLTISH,
2351 ALTIVEC_BUILTIN_VSPLTISW,
2352 ALTIVEC_BUILTIN_VSRB,
2353 ALTIVEC_BUILTIN_VSRH,
2354 ALTIVEC_BUILTIN_VSRW,
2355 ALTIVEC_BUILTIN_VSRAB,
2356 ALTIVEC_BUILTIN_VSRAH,
2357 ALTIVEC_BUILTIN_VSRAW,
2358 ALTIVEC_BUILTIN_VSR,
2359 ALTIVEC_BUILTIN_VSRO,
2360 ALTIVEC_BUILTIN_VSUBUBM,
2361 ALTIVEC_BUILTIN_VSUBUHM,
2362 ALTIVEC_BUILTIN_VSUBUWM,
2363 ALTIVEC_BUILTIN_VSUBFP,
2364 ALTIVEC_BUILTIN_VSUBCUW,
2365 ALTIVEC_BUILTIN_VSUBUBS,
2366 ALTIVEC_BUILTIN_VSUBSBS,
2367 ALTIVEC_BUILTIN_VSUBUHS,
2368 ALTIVEC_BUILTIN_VSUBSHS,
2369 ALTIVEC_BUILTIN_VSUBUWS,
2370 ALTIVEC_BUILTIN_VSUBSWS,
2371 ALTIVEC_BUILTIN_VSUM4UBS,
2372 ALTIVEC_BUILTIN_VSUM4SBS,
2373 ALTIVEC_BUILTIN_VSUM4SHS,
2374 ALTIVEC_BUILTIN_VSUM2SWS,
2375 ALTIVEC_BUILTIN_VSUMSWS,
2376 ALTIVEC_BUILTIN_VXOR,
2377 ALTIVEC_BUILTIN_VSLDOI_16QI,
2378 ALTIVEC_BUILTIN_VSLDOI_8HI,
2379 ALTIVEC_BUILTIN_VSLDOI_4SI,
2380 ALTIVEC_BUILTIN_VSLDOI_4SF,
2381 ALTIVEC_BUILTIN_VUPKHSB,
2382 ALTIVEC_BUILTIN_VUPKHPX,
2383 ALTIVEC_BUILTIN_VUPKHSH,
2384 ALTIVEC_BUILTIN_VUPKLSB,
2385 ALTIVEC_BUILTIN_VUPKLPX,
2386 ALTIVEC_BUILTIN_VUPKLSH,
2387 ALTIVEC_BUILTIN_MTVSCR,
2388 ALTIVEC_BUILTIN_MFVSCR,
2389 ALTIVEC_BUILTIN_DSSALL,
2390 ALTIVEC_BUILTIN_DSS,
2391 ALTIVEC_BUILTIN_LVSL,
2392 ALTIVEC_BUILTIN_LVSR,
2393 ALTIVEC_BUILTIN_DSTT,
2394 ALTIVEC_BUILTIN_DSTST,
2395 ALTIVEC_BUILTIN_DSTSTT,
2396 ALTIVEC_BUILTIN_DST,
2397 ALTIVEC_BUILTIN_LVEBX,
2398 ALTIVEC_BUILTIN_LVEHX,
2399 ALTIVEC_BUILTIN_LVEWX,
2400 ALTIVEC_BUILTIN_LVXL,
2401 ALTIVEC_BUILTIN_LVX,
2402 ALTIVEC_BUILTIN_STVX,
2403 ALTIVEC_BUILTIN_STVEBX,
2404 ALTIVEC_BUILTIN_STVEHX,
2405 ALTIVEC_BUILTIN_STVEWX,
2406 ALTIVEC_BUILTIN_STVXL,
2407 ALTIVEC_BUILTIN_VCMPBFP_P,
2408 ALTIVEC_BUILTIN_VCMPEQFP_P,
2409 ALTIVEC_BUILTIN_VCMPEQUB_P,
2410 ALTIVEC_BUILTIN_VCMPEQUH_P,
2411 ALTIVEC_BUILTIN_VCMPEQUW_P,
2412 ALTIVEC_BUILTIN_VCMPGEFP_P,
2413 ALTIVEC_BUILTIN_VCMPGTFP_P,
2414 ALTIVEC_BUILTIN_VCMPGTSB_P,
2415 ALTIVEC_BUILTIN_VCMPGTSH_P,
2416 ALTIVEC_BUILTIN_VCMPGTSW_P,
2417 ALTIVEC_BUILTIN_VCMPGTUB_P,
2418 ALTIVEC_BUILTIN_VCMPGTUH_P,
2419 ALTIVEC_BUILTIN_VCMPGTUW_P,
2420 ALTIVEC_BUILTIN_ABSS_V4SI,
2421 ALTIVEC_BUILTIN_ABSS_V8HI,
2422 ALTIVEC_BUILTIN_ABSS_V16QI,
2423 ALTIVEC_BUILTIN_ABS_V4SI,
2424 ALTIVEC_BUILTIN_ABS_V4SF,
2425 ALTIVEC_BUILTIN_ABS_V8HI,
2426 ALTIVEC_BUILTIN_ABS_V16QI,
2427 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
2428 ALTIVEC_BUILTIN_MASK_FOR_STORE,
2429 ALTIVEC_BUILTIN_VEC_INIT_V4SI,
2430 ALTIVEC_BUILTIN_VEC_INIT_V8HI,
2431 ALTIVEC_BUILTIN_VEC_INIT_V16QI,
2432 ALTIVEC_BUILTIN_VEC_INIT_V4SF,
2433 ALTIVEC_BUILTIN_VEC_SET_V4SI,
2434 ALTIVEC_BUILTIN_VEC_SET_V8HI,
2435 ALTIVEC_BUILTIN_VEC_SET_V16QI,
2436 ALTIVEC_BUILTIN_VEC_SET_V4SF,
2437 ALTIVEC_BUILTIN_VEC_EXT_V4SI,
2438 ALTIVEC_BUILTIN_VEC_EXT_V8HI,
2439 ALTIVEC_BUILTIN_VEC_EXT_V16QI,
2440 ALTIVEC_BUILTIN_VEC_EXT_V4SF,
2442 /* Altivec overloaded builtins. */
2443 ALTIVEC_BUILTIN_VCMPEQ_P,
2444 ALTIVEC_BUILTIN_OVERLOADED_FIRST = ALTIVEC_BUILTIN_VCMPEQ_P,
2445 ALTIVEC_BUILTIN_VCMPGT_P,
2446 ALTIVEC_BUILTIN_VCMPGE_P,
2447 ALTIVEC_BUILTIN_VEC_ABS,
2448 ALTIVEC_BUILTIN_VEC_ABSS,
2449 ALTIVEC_BUILTIN_VEC_ADD,
2450 ALTIVEC_BUILTIN_VEC_ADDC,
2451 ALTIVEC_BUILTIN_VEC_ADDS,
2452 ALTIVEC_BUILTIN_VEC_AND,
2453 ALTIVEC_BUILTIN_VEC_ANDC,
2454 ALTIVEC_BUILTIN_VEC_AVG,
2455 ALTIVEC_BUILTIN_VEC_CEIL,
2456 ALTIVEC_BUILTIN_VEC_CMPB,
2457 ALTIVEC_BUILTIN_VEC_CMPEQ,
2458 ALTIVEC_BUILTIN_VEC_CMPEQUB,
2459 ALTIVEC_BUILTIN_VEC_CMPEQUH,
2460 ALTIVEC_BUILTIN_VEC_CMPEQUW,
2461 ALTIVEC_BUILTIN_VEC_CMPGE,
2462 ALTIVEC_BUILTIN_VEC_CMPGT,
2463 ALTIVEC_BUILTIN_VEC_CMPLE,
2464 ALTIVEC_BUILTIN_VEC_CMPLT,
2465 ALTIVEC_BUILTIN_VEC_CTF,
2466 ALTIVEC_BUILTIN_VEC_CTS,
2467 ALTIVEC_BUILTIN_VEC_CTU,
2468 ALTIVEC_BUILTIN_VEC_DST,
2469 ALTIVEC_BUILTIN_VEC_DSTST,
2470 ALTIVEC_BUILTIN_VEC_DSTSTT,
2471 ALTIVEC_BUILTIN_VEC_DSTT,
2472 ALTIVEC_BUILTIN_VEC_EXPTE,
2473 ALTIVEC_BUILTIN_VEC_FLOOR,
2474 ALTIVEC_BUILTIN_VEC_LD,
2475 ALTIVEC_BUILTIN_VEC_LDE,
2476 ALTIVEC_BUILTIN_VEC_LDL,
2477 ALTIVEC_BUILTIN_VEC_LOGE,
2478 ALTIVEC_BUILTIN_VEC_LVEBX,
2479 ALTIVEC_BUILTIN_VEC_LVEHX,
2480 ALTIVEC_BUILTIN_VEC_LVEWX,
2481 ALTIVEC_BUILTIN_VEC_LVSL,
2482 ALTIVEC_BUILTIN_VEC_LVSR,
2483 ALTIVEC_BUILTIN_VEC_MADD,
2484 ALTIVEC_BUILTIN_VEC_MADDS,
2485 ALTIVEC_BUILTIN_VEC_MAX,
2486 ALTIVEC_BUILTIN_VEC_MERGEH,
2487 ALTIVEC_BUILTIN_VEC_MERGEL,
2488 ALTIVEC_BUILTIN_VEC_MIN,
2489 ALTIVEC_BUILTIN_VEC_MLADD,
2490 ALTIVEC_BUILTIN_VEC_MPERM,
2491 ALTIVEC_BUILTIN_VEC_MRADDS,
2492 ALTIVEC_BUILTIN_VEC_MRGHB,
2493 ALTIVEC_BUILTIN_VEC_MRGHH,
2494 ALTIVEC_BUILTIN_VEC_MRGHW,
2495 ALTIVEC_BUILTIN_VEC_MRGLB,
2496 ALTIVEC_BUILTIN_VEC_MRGLH,
2497 ALTIVEC_BUILTIN_VEC_MRGLW,
2498 ALTIVEC_BUILTIN_VEC_MSUM,
2499 ALTIVEC_BUILTIN_VEC_MSUMS,
2500 ALTIVEC_BUILTIN_VEC_MTVSCR,
2501 ALTIVEC_BUILTIN_VEC_MULE,
2502 ALTIVEC_BUILTIN_VEC_MULO,
2503 ALTIVEC_BUILTIN_VEC_NMSUB,
2504 ALTIVEC_BUILTIN_VEC_NOR,
2505 ALTIVEC_BUILTIN_VEC_OR,
2506 ALTIVEC_BUILTIN_VEC_PACK,
2507 ALTIVEC_BUILTIN_VEC_PACKPX,
2508 ALTIVEC_BUILTIN_VEC_PACKS,
2509 ALTIVEC_BUILTIN_VEC_PACKSU,
2510 ALTIVEC_BUILTIN_VEC_PERM,
2511 ALTIVEC_BUILTIN_VEC_RE,
2512 ALTIVEC_BUILTIN_VEC_RL,
2513 ALTIVEC_BUILTIN_VEC_ROUND,
2514 ALTIVEC_BUILTIN_VEC_RSQRTE,
2515 ALTIVEC_BUILTIN_VEC_SEL,
2516 ALTIVEC_BUILTIN_VEC_SL,
2517 ALTIVEC_BUILTIN_VEC_SLD,
2518 ALTIVEC_BUILTIN_VEC_SLL,
2519 ALTIVEC_BUILTIN_VEC_SLO,
2520 ALTIVEC_BUILTIN_VEC_SPLAT,
2521 ALTIVEC_BUILTIN_VEC_SPLAT_S16,
2522 ALTIVEC_BUILTIN_VEC_SPLAT_S32,
2523 ALTIVEC_BUILTIN_VEC_SPLAT_S8,
2524 ALTIVEC_BUILTIN_VEC_SPLAT_U16,
2525 ALTIVEC_BUILTIN_VEC_SPLAT_U32,
2526 ALTIVEC_BUILTIN_VEC_SPLAT_U8,
2527 ALTIVEC_BUILTIN_VEC_SPLTB,
2528 ALTIVEC_BUILTIN_VEC_SPLTH,
2529 ALTIVEC_BUILTIN_VEC_SPLTW,
2530 ALTIVEC_BUILTIN_VEC_SR,
2531 ALTIVEC_BUILTIN_VEC_SRA,
2532 ALTIVEC_BUILTIN_VEC_SRL,
2533 ALTIVEC_BUILTIN_VEC_SRO,
2534 ALTIVEC_BUILTIN_VEC_ST,
2535 ALTIVEC_BUILTIN_VEC_STE,
2536 ALTIVEC_BUILTIN_VEC_STL,
2537 ALTIVEC_BUILTIN_VEC_STVEBX,
2538 ALTIVEC_BUILTIN_VEC_STVEHX,
2539 ALTIVEC_BUILTIN_VEC_STVEWX,
2540 ALTIVEC_BUILTIN_VEC_SUB,
2541 ALTIVEC_BUILTIN_VEC_SUBC,
2542 ALTIVEC_BUILTIN_VEC_SUBS,
2543 ALTIVEC_BUILTIN_VEC_SUM2S,
2544 ALTIVEC_BUILTIN_VEC_SUM4S,
2545 ALTIVEC_BUILTIN_VEC_SUMS,
2546 ALTIVEC_BUILTIN_VEC_TRUNC,
2547 ALTIVEC_BUILTIN_VEC_UNPACKH,
2548 ALTIVEC_BUILTIN_VEC_UNPACKL,
2549 ALTIVEC_BUILTIN_VEC_VADDFP,
2550 ALTIVEC_BUILTIN_VEC_VADDSBS,
2551 ALTIVEC_BUILTIN_VEC_VADDSHS,
2552 ALTIVEC_BUILTIN_VEC_VADDSWS,
2553 ALTIVEC_BUILTIN_VEC_VADDUBM,
2554 ALTIVEC_BUILTIN_VEC_VADDUBS,
2555 ALTIVEC_BUILTIN_VEC_VADDUHM,
2556 ALTIVEC_BUILTIN_VEC_VADDUHS,
2557 ALTIVEC_BUILTIN_VEC_VADDUWM,
2558 ALTIVEC_BUILTIN_VEC_VADDUWS,
2559 ALTIVEC_BUILTIN_VEC_VAVGSB,
2560 ALTIVEC_BUILTIN_VEC_VAVGSH,
2561 ALTIVEC_BUILTIN_VEC_VAVGSW,
2562 ALTIVEC_BUILTIN_VEC_VAVGUB,
2563 ALTIVEC_BUILTIN_VEC_VAVGUH,
2564 ALTIVEC_BUILTIN_VEC_VAVGUW,
2565 ALTIVEC_BUILTIN_VEC_VCFSX,
2566 ALTIVEC_BUILTIN_VEC_VCFUX,
2567 ALTIVEC_BUILTIN_VEC_VCMPEQFP,
2568 ALTIVEC_BUILTIN_VEC_VCMPEQUB,
2569 ALTIVEC_BUILTIN_VEC_VCMPEQUH,
2570 ALTIVEC_BUILTIN_VEC_VCMPEQUW,
2571 ALTIVEC_BUILTIN_VEC_VCMPGTFP,
2572 ALTIVEC_BUILTIN_VEC_VCMPGTSB,
2573 ALTIVEC_BUILTIN_VEC_VCMPGTSH,
2574 ALTIVEC_BUILTIN_VEC_VCMPGTSW,
2575 ALTIVEC_BUILTIN_VEC_VCMPGTUB,
2576 ALTIVEC_BUILTIN_VEC_VCMPGTUH,
2577 ALTIVEC_BUILTIN_VEC_VCMPGTUW,
2578 ALTIVEC_BUILTIN_VEC_VMAXFP,
2579 ALTIVEC_BUILTIN_VEC_VMAXSB,
2580 ALTIVEC_BUILTIN_VEC_VMAXSH,
2581 ALTIVEC_BUILTIN_VEC_VMAXSW,
2582 ALTIVEC_BUILTIN_VEC_VMAXUB,
2583 ALTIVEC_BUILTIN_VEC_VMAXUH,
2584 ALTIVEC_BUILTIN_VEC_VMAXUW,
2585 ALTIVEC_BUILTIN_VEC_VMINFP,
2586 ALTIVEC_BUILTIN_VEC_VMINSB,
2587 ALTIVEC_BUILTIN_VEC_VMINSH,
2588 ALTIVEC_BUILTIN_VEC_VMINSW,
2589 ALTIVEC_BUILTIN_VEC_VMINUB,
2590 ALTIVEC_BUILTIN_VEC_VMINUH,
2591 ALTIVEC_BUILTIN_VEC_VMINUW,
2592 ALTIVEC_BUILTIN_VEC_VMRGHB,
2593 ALTIVEC_BUILTIN_VEC_VMRGHH,
2594 ALTIVEC_BUILTIN_VEC_VMRGHW,
2595 ALTIVEC_BUILTIN_VEC_VMRGLB,
2596 ALTIVEC_BUILTIN_VEC_VMRGLH,
2597 ALTIVEC_BUILTIN_VEC_VMRGLW,
2598 ALTIVEC_BUILTIN_VEC_VMSUMMBM,
2599 ALTIVEC_BUILTIN_VEC_VMSUMSHM,
2600 ALTIVEC_BUILTIN_VEC_VMSUMSHS,
2601 ALTIVEC_BUILTIN_VEC_VMSUMUBM,
2602 ALTIVEC_BUILTIN_VEC_VMSUMUHM,
2603 ALTIVEC_BUILTIN_VEC_VMSUMUHS,
2604 ALTIVEC_BUILTIN_VEC_VMULESB,
2605 ALTIVEC_BUILTIN_VEC_VMULESH,
2606 ALTIVEC_BUILTIN_VEC_VMULEUB,
2607 ALTIVEC_BUILTIN_VEC_VMULEUH,
2608 ALTIVEC_BUILTIN_VEC_VMULOSB,
2609 ALTIVEC_BUILTIN_VEC_VMULOSH,
2610 ALTIVEC_BUILTIN_VEC_VMULOUB,
2611 ALTIVEC_BUILTIN_VEC_VMULOUH,
2612 ALTIVEC_BUILTIN_VEC_VPKSHSS,
2613 ALTIVEC_BUILTIN_VEC_VPKSHUS,
2614 ALTIVEC_BUILTIN_VEC_VPKSWSS,
2615 ALTIVEC_BUILTIN_VEC_VPKSWUS,
2616 ALTIVEC_BUILTIN_VEC_VPKUHUM,
2617 ALTIVEC_BUILTIN_VEC_VPKUHUS,
2618 ALTIVEC_BUILTIN_VEC_VPKUWUM,
2619 ALTIVEC_BUILTIN_VEC_VPKUWUS,
2620 ALTIVEC_BUILTIN_VEC_VRLB,
2621 ALTIVEC_BUILTIN_VEC_VRLH,
2622 ALTIVEC_BUILTIN_VEC_VRLW,
2623 ALTIVEC_BUILTIN_VEC_VSLB,
2624 ALTIVEC_BUILTIN_VEC_VSLH,
2625 ALTIVEC_BUILTIN_VEC_VSLW,
2626 ALTIVEC_BUILTIN_VEC_VSPLTB,
2627 ALTIVEC_BUILTIN_VEC_VSPLTH,
2628 ALTIVEC_BUILTIN_VEC_VSPLTW,
2629 ALTIVEC_BUILTIN_VEC_VSRAB,
2630 ALTIVEC_BUILTIN_VEC_VSRAH,
2631 ALTIVEC_BUILTIN_VEC_VSRAW,
2632 ALTIVEC_BUILTIN_VEC_VSRB,
2633 ALTIVEC_BUILTIN_VEC_VSRH,
2634 ALTIVEC_BUILTIN_VEC_VSRW,
2635 ALTIVEC_BUILTIN_VEC_VSUBFP,
2636 ALTIVEC_BUILTIN_VEC_VSUBSBS,
2637 ALTIVEC_BUILTIN_VEC_VSUBSHS,
2638 ALTIVEC_BUILTIN_VEC_VSUBSWS,
2639 ALTIVEC_BUILTIN_VEC_VSUBUBM,
2640 ALTIVEC_BUILTIN_VEC_VSUBUBS,
2641 ALTIVEC_BUILTIN_VEC_VSUBUHM,
2642 ALTIVEC_BUILTIN_VEC_VSUBUHS,
2643 ALTIVEC_BUILTIN_VEC_VSUBUWM,
2644 ALTIVEC_BUILTIN_VEC_VSUBUWS,
2645 ALTIVEC_BUILTIN_VEC_VSUM4SBS,
2646 ALTIVEC_BUILTIN_VEC_VSUM4SHS,
2647 ALTIVEC_BUILTIN_VEC_VSUM4UBS,
2648 ALTIVEC_BUILTIN_VEC_VUPKHPX,
2649 ALTIVEC_BUILTIN_VEC_VUPKHSB,
2650 ALTIVEC_BUILTIN_VEC_VUPKHSH,
2651 ALTIVEC_BUILTIN_VEC_VUPKLPX,
2652 ALTIVEC_BUILTIN_VEC_VUPKLSB,
2653 ALTIVEC_BUILTIN_VEC_VUPKLSH,
2654 ALTIVEC_BUILTIN_VEC_XOR,
2655 ALTIVEC_BUILTIN_VEC_STEP,
2656 ALTIVEC_BUILTIN_OVERLOADED_LAST = ALTIVEC_BUILTIN_VEC_STEP,
2662 SPE_BUILTIN_EVDIVWS,
2663 SPE_BUILTIN_EVDIVWU,
2665 SPE_BUILTIN_EVFSADD,
2666 SPE_BUILTIN_EVFSDIV,
2667 SPE_BUILTIN_EVFSMUL,
2668 SPE_BUILTIN_EVFSSUB,
2672 SPE_BUILTIN_EVLHHESPLATX,
2673 SPE_BUILTIN_EVLHHOSSPLATX,
2674 SPE_BUILTIN_EVLHHOUSPLATX,
2675 SPE_BUILTIN_EVLWHEX,
2676 SPE_BUILTIN_EVLWHOSX,
2677 SPE_BUILTIN_EVLWHOUX,
2678 SPE_BUILTIN_EVLWHSPLATX,
2679 SPE_BUILTIN_EVLWWSPLATX,
2680 SPE_BUILTIN_EVMERGEHI,
2681 SPE_BUILTIN_EVMERGEHILO,
2682 SPE_BUILTIN_EVMERGELO,
2683 SPE_BUILTIN_EVMERGELOHI,
2684 SPE_BUILTIN_EVMHEGSMFAA,
2685 SPE_BUILTIN_EVMHEGSMFAN,
2686 SPE_BUILTIN_EVMHEGSMIAA,
2687 SPE_BUILTIN_EVMHEGSMIAN,
2688 SPE_BUILTIN_EVMHEGUMIAA,
2689 SPE_BUILTIN_EVMHEGUMIAN,
2690 SPE_BUILTIN_EVMHESMF,
2691 SPE_BUILTIN_EVMHESMFA,
2692 SPE_BUILTIN_EVMHESMFAAW,
2693 SPE_BUILTIN_EVMHESMFANW,
2694 SPE_BUILTIN_EVMHESMI,
2695 SPE_BUILTIN_EVMHESMIA,
2696 SPE_BUILTIN_EVMHESMIAAW,
2697 SPE_BUILTIN_EVMHESMIANW,
2698 SPE_BUILTIN_EVMHESSF,
2699 SPE_BUILTIN_EVMHESSFA,
2700 SPE_BUILTIN_EVMHESSFAAW,
2701 SPE_BUILTIN_EVMHESSFANW,
2702 SPE_BUILTIN_EVMHESSIAAW,
2703 SPE_BUILTIN_EVMHESSIANW,
2704 SPE_BUILTIN_EVMHEUMI,
2705 SPE_BUILTIN_EVMHEUMIA,
2706 SPE_BUILTIN_EVMHEUMIAAW,
2707 SPE_BUILTIN_EVMHEUMIANW,
2708 SPE_BUILTIN_EVMHEUSIAAW,
2709 SPE_BUILTIN_EVMHEUSIANW,
2710 SPE_BUILTIN_EVMHOGSMFAA,
2711 SPE_BUILTIN_EVMHOGSMFAN,
2712 SPE_BUILTIN_EVMHOGSMIAA,
2713 SPE_BUILTIN_EVMHOGSMIAN,
2714 SPE_BUILTIN_EVMHOGUMIAA,
2715 SPE_BUILTIN_EVMHOGUMIAN,
2716 SPE_BUILTIN_EVMHOSMF,
2717 SPE_BUILTIN_EVMHOSMFA,
2718 SPE_BUILTIN_EVMHOSMFAAW,
2719 SPE_BUILTIN_EVMHOSMFANW,
2720 SPE_BUILTIN_EVMHOSMI,
2721 SPE_BUILTIN_EVMHOSMIA,
2722 SPE_BUILTIN_EVMHOSMIAAW,
2723 SPE_BUILTIN_EVMHOSMIANW,
2724 SPE_BUILTIN_EVMHOSSF,
2725 SPE_BUILTIN_EVMHOSSFA,
2726 SPE_BUILTIN_EVMHOSSFAAW,
2727 SPE_BUILTIN_EVMHOSSFANW,
2728 SPE_BUILTIN_EVMHOSSIAAW,
2729 SPE_BUILTIN_EVMHOSSIANW,
2730 SPE_BUILTIN_EVMHOUMI,
2731 SPE_BUILTIN_EVMHOUMIA,
2732 SPE_BUILTIN_EVMHOUMIAAW,
2733 SPE_BUILTIN_EVMHOUMIANW,
2734 SPE_BUILTIN_EVMHOUSIAAW,
2735 SPE_BUILTIN_EVMHOUSIANW,
2736 SPE_BUILTIN_EVMWHSMF,
2737 SPE_BUILTIN_EVMWHSMFA,
2738 SPE_BUILTIN_EVMWHSMI,
2739 SPE_BUILTIN_EVMWHSMIA,
2740 SPE_BUILTIN_EVMWHSSF,
2741 SPE_BUILTIN_EVMWHSSFA,
2742 SPE_BUILTIN_EVMWHUMI,
2743 SPE_BUILTIN_EVMWHUMIA,
2744 SPE_BUILTIN_EVMWLSMIAAW,
2745 SPE_BUILTIN_EVMWLSMIANW,
2746 SPE_BUILTIN_EVMWLSSIAAW,
2747 SPE_BUILTIN_EVMWLSSIANW,
2748 SPE_BUILTIN_EVMWLUMI,
2749 SPE_BUILTIN_EVMWLUMIA,
2750 SPE_BUILTIN_EVMWLUMIAAW,
2751 SPE_BUILTIN_EVMWLUMIANW,
2752 SPE_BUILTIN_EVMWLUSIAAW,
2753 SPE_BUILTIN_EVMWLUSIANW,
2754 SPE_BUILTIN_EVMWSMF,
2755 SPE_BUILTIN_EVMWSMFA,
2756 SPE_BUILTIN_EVMWSMFAA,
2757 SPE_BUILTIN_EVMWSMFAN,
2758 SPE_BUILTIN_EVMWSMI,
2759 SPE_BUILTIN_EVMWSMIA,
2760 SPE_BUILTIN_EVMWSMIAA,
2761 SPE_BUILTIN_EVMWSMIAN,
2762 SPE_BUILTIN_EVMWHSSFAA,
2763 SPE_BUILTIN_EVMWSSF,
2764 SPE_BUILTIN_EVMWSSFA,
2765 SPE_BUILTIN_EVMWSSFAA,
2766 SPE_BUILTIN_EVMWSSFAN,
2767 SPE_BUILTIN_EVMWUMI,
2768 SPE_BUILTIN_EVMWUMIA,
2769 SPE_BUILTIN_EVMWUMIAA,
2770 SPE_BUILTIN_EVMWUMIAN,
2779 SPE_BUILTIN_EVSTDDX,
2780 SPE_BUILTIN_EVSTDHX,
2781 SPE_BUILTIN_EVSTDWX,
2782 SPE_BUILTIN_EVSTWHEX,
2783 SPE_BUILTIN_EVSTWHOX,
2784 SPE_BUILTIN_EVSTWWEX,
2785 SPE_BUILTIN_EVSTWWOX,
2786 SPE_BUILTIN_EVSUBFW,
2789 SPE_BUILTIN_EVADDSMIAAW,
2790 SPE_BUILTIN_EVADDSSIAAW,
2791 SPE_BUILTIN_EVADDUMIAAW,
2792 SPE_BUILTIN_EVADDUSIAAW,
2793 SPE_BUILTIN_EVCNTLSW,
2794 SPE_BUILTIN_EVCNTLZW,
2795 SPE_BUILTIN_EVEXTSB,
2796 SPE_BUILTIN_EVEXTSH,
2797 SPE_BUILTIN_EVFSABS,
2798 SPE_BUILTIN_EVFSCFSF,
2799 SPE_BUILTIN_EVFSCFSI,
2800 SPE_BUILTIN_EVFSCFUF,
2801 SPE_BUILTIN_EVFSCFUI,
2802 SPE_BUILTIN_EVFSCTSF,
2803 SPE_BUILTIN_EVFSCTSI,
2804 SPE_BUILTIN_EVFSCTSIZ,
2805 SPE_BUILTIN_EVFSCTUF,
2806 SPE_BUILTIN_EVFSCTUI,
2807 SPE_BUILTIN_EVFSCTUIZ,
2808 SPE_BUILTIN_EVFSNABS,
2809 SPE_BUILTIN_EVFSNEG,
2813 SPE_BUILTIN_EVSUBFSMIAAW,
2814 SPE_BUILTIN_EVSUBFSSIAAW,
2815 SPE_BUILTIN_EVSUBFUMIAAW,
2816 SPE_BUILTIN_EVSUBFUSIAAW,
2817 SPE_BUILTIN_EVADDIW,
2821 SPE_BUILTIN_EVLHHESPLAT,
2822 SPE_BUILTIN_EVLHHOSSPLAT,
2823 SPE_BUILTIN_EVLHHOUSPLAT,
2825 SPE_BUILTIN_EVLWHOS,
2826 SPE_BUILTIN_EVLWHOU,
2827 SPE_BUILTIN_EVLWHSPLAT,
2828 SPE_BUILTIN_EVLWWSPLAT,
2831 SPE_BUILTIN_EVSRWIS,
2832 SPE_BUILTIN_EVSRWIU,
2836 SPE_BUILTIN_EVSTWHE,
2837 SPE_BUILTIN_EVSTWHO,
2838 SPE_BUILTIN_EVSTWWE,
2839 SPE_BUILTIN_EVSTWWO,
2840 SPE_BUILTIN_EVSUBIFW,
2843 SPE_BUILTIN_EVCMPEQ,
2844 SPE_BUILTIN_EVCMPGTS,
2845 SPE_BUILTIN_EVCMPGTU,
2846 SPE_BUILTIN_EVCMPLTS,
2847 SPE_BUILTIN_EVCMPLTU,
2848 SPE_BUILTIN_EVFSCMPEQ,
2849 SPE_BUILTIN_EVFSCMPGT,
2850 SPE_BUILTIN_EVFSCMPLT,
2851 SPE_BUILTIN_EVFSTSTEQ,
2852 SPE_BUILTIN_EVFSTSTGT,
2853 SPE_BUILTIN_EVFSTSTLT,
2855 /* EVSEL compares. */
2856 SPE_BUILTIN_EVSEL_CMPEQ,
2857 SPE_BUILTIN_EVSEL_CMPGTS,
2858 SPE_BUILTIN_EVSEL_CMPGTU,
2859 SPE_BUILTIN_EVSEL_CMPLTS,
2860 SPE_BUILTIN_EVSEL_CMPLTU,
2861 SPE_BUILTIN_EVSEL_FSCMPEQ,
2862 SPE_BUILTIN_EVSEL_FSCMPGT,
2863 SPE_BUILTIN_EVSEL_FSCMPLT,
2864 SPE_BUILTIN_EVSEL_FSTSTEQ,
2865 SPE_BUILTIN_EVSEL_FSTSTGT,
2866 SPE_BUILTIN_EVSEL_FSTSTLT,
2868 SPE_BUILTIN_EVSPLATFI,
2869 SPE_BUILTIN_EVSPLATI,
2870 SPE_BUILTIN_EVMWHSSMAA,
2871 SPE_BUILTIN_EVMWHSMFAA,
2872 SPE_BUILTIN_EVMWHSMIAA,
2873 SPE_BUILTIN_EVMWHUSIAA,
2874 SPE_BUILTIN_EVMWHUMIAA,
2875 SPE_BUILTIN_EVMWHSSFAN,
2876 SPE_BUILTIN_EVMWHSSIAN,
2877 SPE_BUILTIN_EVMWHSMFAN,
2878 SPE_BUILTIN_EVMWHSMIAN,
2879 SPE_BUILTIN_EVMWHUSIAN,
2880 SPE_BUILTIN_EVMWHUMIAN,
2881 SPE_BUILTIN_EVMWHGSSFAA,
2882 SPE_BUILTIN_EVMWHGSMFAA,
2883 SPE_BUILTIN_EVMWHGSMIAA,
2884 SPE_BUILTIN_EVMWHGUMIAA,
2885 SPE_BUILTIN_EVMWHGSSFAN,
2886 SPE_BUILTIN_EVMWHGSMFAN,
2887 SPE_BUILTIN_EVMWHGSMIAN,
2888 SPE_BUILTIN_EVMWHGUMIAN,
2889 SPE_BUILTIN_MTSPEFSCR,
2890 SPE_BUILTIN_MFSPEFSCR,
2893 RS6000_BUILTIN_COUNT
2896 enum rs6000_builtin_type_index
2898 RS6000_BTI_NOT_OPAQUE,
2899 RS6000_BTI_opaque_V2SI,
2900 RS6000_BTI_opaque_V2SF,
2901 RS6000_BTI_opaque_p_V2SI,
2902 RS6000_BTI_opaque_V4SI,
2910 RS6000_BTI_unsigned_V16QI,
2911 RS6000_BTI_unsigned_V8HI,
2912 RS6000_BTI_unsigned_V4SI,
2913 RS6000_BTI_bool_char, /* __bool char */
2914 RS6000_BTI_bool_short, /* __bool short */
2915 RS6000_BTI_bool_int, /* __bool int */
2916 RS6000_BTI_pixel, /* __pixel */
2917 RS6000_BTI_bool_V16QI, /* __vector __bool char */
2918 RS6000_BTI_bool_V8HI, /* __vector __bool short */
2919 RS6000_BTI_bool_V4SI, /* __vector __bool int */
2920 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
2921 RS6000_BTI_long, /* long_integer_type_node */
2922 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
2923 RS6000_BTI_INTQI, /* intQI_type_node */
2924 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
2925 RS6000_BTI_INTHI, /* intHI_type_node */
2926 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
2927 RS6000_BTI_INTSI, /* intSI_type_node */
2928 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
2929 RS6000_BTI_float, /* float_type_node */
2930 RS6000_BTI_void, /* void_type_node */
2935 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
2936 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
2937 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
2938 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2939 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
2940 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
2941 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
2942 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2943 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2944 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2945 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2946 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2947 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
2948 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
2949 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2950 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2951 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
2952 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2953 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2954 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2955 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
2956 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
2958 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
2959 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
2960 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
2961 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
2962 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
2963 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
2964 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
2965 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
2966 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
2967 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
2969 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
2970 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];