1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
23 /* Note that some other tm.h files include this one and then override
24 many of the definitions. */
26 /* Definitions for the object file format. These are set at
29 #define OBJECT_XCOFF 1
32 #define OBJECT_MACHO 4
34 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
35 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
36 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
37 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
43 /* Control whether function entry points use a "dot" symbol when
47 /* Default string to use for cpu if not specified. */
48 #ifndef TARGET_CPU_DEFAULT
49 #define TARGET_CPU_DEFAULT ((char *)0)
52 /* Common ASM definitions used by ASM_SPEC among the various targets
53 for handling -mcpu=xxx switches. */
54 #define ASM_CPU_SPEC \
56 %{mpower: %{!mpower2: -mpwr}} \
58 %{mpowerpc64*: -mppc64} \
59 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
60 %{mno-power: %{!mpowerpc*: -mcom}} \
61 %{!mno-power: %{!mpower*: %(asm_default)}}} \
62 %{mcpu=common: -mcom} \
63 %{mcpu=power: -mpwr} \
64 %{mcpu=power2: -mpwrx} \
65 %{mcpu=power3: -mppc64} \
66 %{mcpu=power4: -mpower4} \
67 %{mcpu=power5: -mpower4} \
68 %{mcpu=powerpc: -mppc} \
70 %{mcpu=rios1: -mpwr} \
71 %{mcpu=rios2: -mpwrx} \
74 %{mcpu=rs64a: -mppc64} \
78 %{mcpu=405fp: -m405} \
80 %{mcpu=440fp: -m440} \
86 %{mcpu=ec603e: -mppc} \
89 %{mcpu=620: -mppc64} \
90 %{mcpu=630: -mppc64} \
94 %{mcpu=7400: -mppc -maltivec} \
95 %{mcpu=7450: -mppc -maltivec} \
96 %{mcpu=G4: -mppc -maltivec} \
101 %{mcpu=970: -mpower4 -maltivec} \
102 %{mcpu=G5: -mpower4 -maltivec} \
103 %{mcpu=8540: -me500} \
104 %{maltivec: -maltivec} \
107 #define CPP_DEFAULT_SPEC ""
109 #define ASM_DEFAULT_SPEC ""
111 /* This macro defines names of additional specifications to put in the specs
112 that can be used in various specifications like CC1_SPEC. Its definition
113 is an initializer with a subgrouping for each command option.
115 Each subgrouping contains a string constant, that defines the
116 specification name, and a string constant that used by the GCC driver
119 Do not define this macro if it does not need to do anything. */
121 #define SUBTARGET_EXTRA_SPECS
123 #define EXTRA_SPECS \
124 { "cpp_default", CPP_DEFAULT_SPEC }, \
125 { "asm_cpu", ASM_CPU_SPEC }, \
126 { "asm_default", ASM_DEFAULT_SPEC }, \
127 SUBTARGET_EXTRA_SPECS
129 /* Architecture type. */
131 extern int target_flags;
133 /* Use POWER architecture instructions and MQ register. */
134 #define MASK_POWER 0x00000001
136 /* Use POWER2 extensions to POWER architecture. */
137 #define MASK_POWER2 0x00000002
139 /* Use PowerPC architecture instructions. */
140 #define MASK_POWERPC 0x00000004
142 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */
143 #define MASK_PPC_GPOPT 0x00000008
145 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */
146 #define MASK_PPC_GFXOPT 0x00000010
148 /* Use PowerPC-64 architecture instructions. */
149 #define MASK_POWERPC64 0x00000020
151 /* Use revised mnemonic names defined for PowerPC architecture. */
152 #define MASK_NEW_MNEMONICS 0x00000040
154 /* Disable placing fp constants in the TOC; can be turned on when the
156 #define MASK_NO_FP_IN_TOC 0x00000080
158 /* Disable placing symbol+offset constants in the TOC; can be turned on when
159 the TOC overflows. */
160 #define MASK_NO_SUM_IN_TOC 0x00000100
162 /* Output only one TOC entry per module. Normally linking fails if
163 there are more than 16K unique variables/constants in an executable. With
164 this option, linking fails only if there are more than 16K modules, or
165 if there are more than 16K unique variables/constant in a single module.
167 This is at the cost of having 2 extra loads and one extra store per
168 function, and one less allocable register. */
169 #define MASK_MINIMAL_TOC 0x00000200
171 /* Nonzero for the 64 bit ABIs: longs and pointers are 64 bits. The
172 chip is running in "64-bit mode", in which CR0 is set in dot
173 operations based on all 64 bits of the register, bdnz works on 64-bit
174 ctr, lr is 64 bits, and so on. Requires MASK_POWERPC64. */
175 #define MASK_64BIT 0x00000400
177 /* Disable use of FPRs. */
178 #define MASK_SOFT_FLOAT 0x00000800
180 /* Enable load/store multiple, even on PowerPC */
181 #define MASK_MULTIPLE 0x00001000
183 /* Use string instructions for block moves */
184 #define MASK_STRING 0x00002000
186 /* Disable update form of load/store */
187 #define MASK_NO_UPDATE 0x00004000
189 /* Disable fused multiply/add operations */
190 #define MASK_NO_FUSED_MADD 0x00008000
192 /* Nonzero if we need to schedule the prolog and epilog. */
193 #define MASK_SCHED_PROLOG 0x00010000
195 /* Use AltiVec instructions. */
196 #define MASK_ALTIVEC 0x00020000
198 /* Return small structures in memory (as the AIX ABI requires). */
199 #define MASK_AIX_STRUCT_RET 0x00040000
201 /* Use single field mfcr instruction. */
202 #define MASK_MFCRF 0x00080000
204 /* The only remaining free bits are 0x00600000. linux64.h uses
205 0x00100000, and sysv4.h uses 0x00800000 -> 0x40000000.
206 0x80000000 is not available because target_flags is signed. */
208 #define TARGET_POWER (target_flags & MASK_POWER)
209 #define TARGET_POWER2 (target_flags & MASK_POWER2)
210 #define TARGET_POWERPC (target_flags & MASK_POWERPC)
211 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
212 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
213 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
214 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
215 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
216 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
217 #define TARGET_64BIT (target_flags & MASK_64BIT)
218 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
219 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
220 #define TARGET_STRING (target_flags & MASK_STRING)
221 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
222 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
223 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
224 #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
225 #define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET)
227 /* Define TARGET_MFCRF if the target assembler supports the optional
228 field operand for mfcr and the target processor supports the
232 #define TARGET_MFCRF (target_flags & MASK_MFCRF)
234 #define TARGET_MFCRF 0
238 #define TARGET_32BIT (! TARGET_64BIT)
239 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
240 #define TARGET_UPDATE (! TARGET_NO_UPDATE)
241 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
243 /* Emit a dtp-relative reference to a TLS variable. */
246 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
247 rs6000_output_dwarf_dtprel (FILE, SIZE, X)
251 #define HAVE_AS_TLS 0
254 /* Return 1 for a symbol ref for a thread-local storage symbol. */
255 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
256 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
259 /* For libgcc2 we make sure this is a compile time constant */
260 #if defined (__64BIT__) || defined (__powerpc64__)
261 #define TARGET_POWERPC64 1
263 #define TARGET_POWERPC64 0
266 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
269 #define TARGET_XL_COMPAT 0
271 /* Run-time compilation parameters selecting different hardware subsets.
273 Macro to define tables used to set the flags.
274 This is a list in braces of pairs in braces,
275 each pair being { "NAME", VALUE }
276 where VALUE is the bits to set or minus the bits to clear.
277 An empty string NAME is used to identify the default VALUE. */
279 #define TARGET_SWITCHES \
280 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
281 N_("Use POWER instruction set")}, \
282 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
284 N_("Use POWER2 instruction set")}, \
285 {"no-power2", - MASK_POWER2, \
286 N_("Do not use POWER2 instruction set")}, \
287 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
289 N_("Do not use POWER instruction set")}, \
290 {"powerpc", MASK_POWERPC, \
291 N_("Use PowerPC instruction set")}, \
292 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
293 | MASK_PPC_GFXOPT | MASK_POWERPC64), \
294 N_("Do not use PowerPC instruction set")}, \
295 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
296 N_("Use PowerPC General Purpose group optional instructions")},\
297 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
298 N_("Do not use PowerPC General Purpose group optional instructions")},\
299 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
300 N_("Use PowerPC Graphics group optional instructions")},\
301 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
302 N_("Do not use PowerPC Graphics group optional instructions")},\
303 {"powerpc64", MASK_POWERPC64, \
304 N_("Use PowerPC-64 instruction set")}, \
305 {"no-powerpc64", - MASK_POWERPC64, \
306 N_("Do not use PowerPC-64 instruction set")}, \
307 {"altivec", MASK_ALTIVEC , \
308 N_("Use AltiVec instructions")}, \
309 {"no-altivec", - MASK_ALTIVEC , \
310 N_("Do not use AltiVec instructions")}, \
311 {"new-mnemonics", MASK_NEW_MNEMONICS, \
312 N_("Use new mnemonics for PowerPC architecture")},\
313 {"old-mnemonics", -MASK_NEW_MNEMONICS, \
314 N_("Use old mnemonics for PowerPC architecture")},\
315 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
316 | MASK_MINIMAL_TOC), \
317 N_("Put everything in the regular TOC")}, \
318 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
319 N_("Place floating point constants in TOC")}, \
320 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
321 N_("Do not place floating point constants in TOC")},\
322 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
323 N_("Place symbol+offset constants in TOC")}, \
324 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
325 N_("Do not place symbol+offset constants in TOC")},\
326 {"minimal-toc", MASK_MINIMAL_TOC, \
327 "Use only one TOC entry per procedure"}, \
328 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
330 {"no-minimal-toc", - MASK_MINIMAL_TOC, \
331 N_("Place variable addresses in the regular TOC")},\
332 {"hard-float", - MASK_SOFT_FLOAT, \
333 N_("Use hardware floating point")}, \
334 {"soft-float", MASK_SOFT_FLOAT, \
335 N_("Do not use hardware floating point")}, \
336 {"multiple", MASK_MULTIPLE, \
337 N_("Generate load/store multiple instructions")}, \
338 {"no-multiple", - MASK_MULTIPLE, \
339 N_("Do not generate load/store multiple instructions")},\
340 {"string", MASK_STRING, \
341 N_("Generate string instructions for block moves")},\
342 {"no-string", - MASK_STRING, \
343 N_("Do not generate string instructions for block moves")},\
344 {"update", - MASK_NO_UPDATE, \
345 N_("Generate load/store with update instructions")},\
346 {"no-update", MASK_NO_UPDATE, \
347 N_("Do not generate load/store with update instructions")},\
348 {"fused-madd", - MASK_NO_FUSED_MADD, \
349 N_("Generate fused multiply/add instructions")},\
350 {"no-fused-madd", MASK_NO_FUSED_MADD, \
351 N_("Do not generate fused multiply/add instructions")},\
352 {"sched-prolog", MASK_SCHED_PROLOG, \
354 {"no-sched-prolog", -MASK_SCHED_PROLOG, \
355 N_("Do not schedule the start and end of the procedure")},\
356 {"sched-epilog", MASK_SCHED_PROLOG, \
358 {"no-sched-epilog", -MASK_SCHED_PROLOG, \
360 {"aix-struct-return", MASK_AIX_STRUCT_RET, \
361 N_("Return all structures in memory (AIX default)")},\
362 {"svr4-struct-return", - MASK_AIX_STRUCT_RET, \
363 N_("Return small structures in registers (SVR4 default)")},\
364 {"no-aix-struct-return", - MASK_AIX_STRUCT_RET, \
366 {"no-svr4-struct-return", MASK_AIX_STRUCT_RET, \
368 {"mfcrf", MASK_MFCRF, \
369 N_("Generate single field mfcr instruction")}, \
370 {"no-mfcrf", - MASK_MFCRF, \
371 N_("Do not generate single field mfcr instruction")},\
373 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
376 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
378 /* This is meant to be redefined in the host dependent files */
379 #define SUBTARGET_SWITCHES
381 /* Processor type. Order must match cpu attribute in MD file. */
405 extern enum processor_type rs6000_cpu;
407 /* Recast the processor type to the cpu attribute. */
408 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
410 /* Define generic processor types based upon current deployment. */
411 #define PROCESSOR_COMMON PROCESSOR_PPC601
412 #define PROCESSOR_POWER PROCESSOR_RIOS1
413 #define PROCESSOR_POWERPC PROCESSOR_PPC604
414 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
416 /* Define the default processor. This is overridden by other tm.h files. */
417 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
418 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
420 /* Specify the dialect of assembler to use. New mnemonics is dialect one
421 and the old mnemonics are dialect zero. */
422 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
424 /* Types of costly dependences. */
425 enum rs6000_dependence_cost
427 max_dep_latency = 1000,
430 true_store_to_load_dep_costly,
431 store_to_load_dep_costly
434 /* Types of nop insertion schemes in sched target hook sched_finish. */
435 enum rs6000_nop_insertion
437 sched_finish_regroup_exact = 1000,
438 sched_finish_pad_groups,
442 /* Dispatch group termination caused by an insn. */
443 enum group_termination
449 /* This is meant to be overridden in target specific files. */
450 #define SUBTARGET_OPTIONS
452 #define TARGET_OPTIONS \
454 {"cpu=", &rs6000_select[1].string, \
455 N_("Use features of and schedule code for given CPU"), 0}, \
456 {"tune=", &rs6000_select[2].string, \
457 N_("Schedule code for given CPU"), 0}, \
458 {"debug=", &rs6000_debug_name, N_("Enable debug output"), 0}, \
459 {"traceback=", &rs6000_traceback_name, \
460 N_("Select full, part, or no traceback table"), 0}, \
461 {"abi=", &rs6000_abi_string, N_("Specify ABI to use"), 0}, \
462 {"long-double-", &rs6000_long_double_size_string, \
463 N_("Specify size of long double (64 or 128 bits)"), 0}, \
464 {"isel=", &rs6000_isel_string, \
465 N_("Specify yes/no if isel instructions should be generated"), 0}, \
466 {"spe=", &rs6000_spe_string, \
467 N_("Specify yes/no if SPE SIMD instructions should be generated"), 0},\
468 {"float-gprs=", &rs6000_float_gprs_string, \
469 N_("Specify yes/no if using floating point in the GPRs"), 0}, \
470 {"vrsave=", &rs6000_altivec_vrsave_string, \
471 N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec"), 0}, \
472 {"longcall", &rs6000_longcall_switch, \
473 N_("Avoid all range limits on call instructions"), 0}, \
474 {"no-longcall", &rs6000_longcall_switch, "", 0}, \
475 {"warn-altivec-long", &rs6000_warn_altivec_long_switch, \
476 N_("Warn about deprecated 'vector long ...' AltiVec type usage"), 0}, \
477 {"no-warn-altivec-long", &rs6000_warn_altivec_long_switch, "", 0}, \
478 {"sched-costly-dep=", &rs6000_sched_costly_dep_str, \
479 N_("Determine which dependences between insns are considered costly"), 0}, \
480 {"insert-sched-nops=", &rs6000_sched_insert_nops_str, \
481 N_("Specify which post scheduling nop insertion scheme to apply"), 0}, \
482 {"align-", &rs6000_alignment_string, \
483 N_("Specify alignment of structure fields default/natural"), 0}, \
484 {"prioritize-restricted-insns=", &rs6000_sched_restricted_insns_priority_str, \
485 N_("Specify scheduling priority for dispatch slot restricted insns"), 0}, \
489 /* Support for a compile-time default CPU, et cetera. The rules are:
490 --with-cpu is ignored if -mcpu is specified.
491 --with-tune is ignored if -mtune is specified.
492 --with-float is ignored if -mhard-float or -msoft-float are
494 #define OPTION_DEFAULT_SPECS \
495 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
496 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
497 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
499 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
500 struct rs6000_cpu_select
508 extern struct rs6000_cpu_select rs6000_select[];
511 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
512 extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,eabi,aix,altivec} */
513 extern int rs6000_debug_stack; /* debug stack applications */
514 extern int rs6000_debug_arg; /* debug argument handling */
516 #define TARGET_DEBUG_STACK rs6000_debug_stack
517 #define TARGET_DEBUG_ARG rs6000_debug_arg
519 extern const char *rs6000_traceback_name; /* Type of traceback table. */
521 /* These are separate from target_flags because we've run out of bits
523 extern const char *rs6000_long_double_size_string;
524 extern int rs6000_long_double_type_size;
525 extern int rs6000_altivec_abi;
526 extern int rs6000_spe_abi;
527 extern int rs6000_isel;
528 extern int rs6000_spe;
529 extern int rs6000_float_gprs;
530 extern const char *rs6000_float_gprs_string;
531 extern const char *rs6000_isel_string;
532 extern const char *rs6000_spe_string;
533 extern const char *rs6000_altivec_vrsave_string;
534 extern int rs6000_altivec_vrsave;
535 extern const char *rs6000_longcall_switch;
536 extern int rs6000_default_long_calls;
537 extern const char* rs6000_alignment_string;
538 extern int rs6000_alignment_flags;
539 extern const char *rs6000_sched_restricted_insns_priority_str;
540 extern int rs6000_sched_restricted_insns_priority;
541 extern const char *rs6000_sched_costly_dep_str;
542 extern enum rs6000_dependence_cost rs6000_sched_costly_dep;
543 extern const char *rs6000_sched_insert_nops_str;
544 extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
546 extern int rs6000_warn_altivec_long;
547 extern const char *rs6000_warn_altivec_long_switch;
549 /* Alignment options for fields in structures for sub-targets following
551 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
552 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
554 Override the macro definitions when compiling libobjc to avoid undefined
555 reference to rs6000_alignment_flags due to library's use of GCC alignment
556 macros which use the macros below. */
558 #ifndef IN_TARGET_LIBS
559 #define MASK_ALIGN_POWER 0x00000000
560 #define MASK_ALIGN_NATURAL 0x00000001
561 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
563 #define TARGET_ALIGN_NATURAL 0
566 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
567 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
568 #define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave
570 #define TARGET_SPE_ABI 0
572 #define TARGET_E500 0
573 #define TARGET_ISEL 0
574 #define TARGET_FPRS 1
575 #define TARGET_E500_SINGLE 0
576 #define TARGET_E500_DOUBLE 0
578 /* Sometimes certain combinations of command options do not make sense
579 on a particular target machine. You can define a macro
580 `OVERRIDE_OPTIONS' to take account of this. This macro, if
581 defined, is executed once just after all the command options have
584 Do not use this macro to turn on various extra optimizations for
585 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
587 On the RS/6000 this is used to define the target cpu type. */
589 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
591 /* Define this to change the optimizations performed by default. */
592 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
594 /* Show we can debug even without a frame pointer. */
595 #define CAN_DEBUG_WITHOUT_FP
598 #define REGISTER_TARGET_PRAGMAS() do { \
599 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
602 /* Target #defines. */
603 #define TARGET_CPU_CPP_BUILTINS() \
604 rs6000_cpu_cpp_builtins (pfile)
606 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
607 we're compiling for. Some configurations may need to override it. */
608 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
611 if (BYTES_BIG_ENDIAN) \
613 builtin_define ("__BIG_ENDIAN__"); \
614 builtin_define ("_BIG_ENDIAN"); \
615 builtin_assert ("machine=bigendian"); \
619 builtin_define ("__LITTLE_ENDIAN__"); \
620 builtin_define ("_LITTLE_ENDIAN"); \
621 builtin_assert ("machine=littleendian"); \
626 /* Target machine storage layout. */
628 /* Define this macro if it is advisable to hold scalars in registers
629 in a wider mode than that declared by the program. In such cases,
630 the value is constrained to be within the bounds of the declared
631 type, but kept valid in the wider mode. The signedness of the
632 extension may differ from that of the type. */
634 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
635 if (GET_MODE_CLASS (MODE) == MODE_INT \
636 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
637 (MODE) = TARGET_32BIT ? SImode : DImode;
639 /* Define this if most significant bit is lowest numbered
640 in instructions that operate on numbered bit-fields. */
641 /* That is true on RS/6000. */
642 #define BITS_BIG_ENDIAN 1
644 /* Define this if most significant byte of a word is the lowest numbered. */
645 /* That is true on RS/6000. */
646 #define BYTES_BIG_ENDIAN 1
648 /* Define this if most significant word of a multiword number is lowest
651 For RS/6000 we can decide arbitrarily since there are no machine
652 instructions for them. Might as well be consistent with bits and bytes. */
653 #define WORDS_BIG_ENDIAN 1
655 #define MAX_BITS_PER_WORD 64
657 /* Width of a word, in units (bytes). */
658 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
660 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
662 #define MIN_UNITS_PER_WORD 4
664 #define UNITS_PER_FP_WORD 8
665 #define UNITS_PER_ALTIVEC_WORD 16
666 #define UNITS_PER_SPE_WORD 8
668 /* Type used for ptrdiff_t, as a string used in a declaration. */
669 #define PTRDIFF_TYPE "int"
671 /* Type used for size_t, as a string used in a declaration. */
672 #define SIZE_TYPE "long unsigned int"
674 /* Type used for wchar_t, as a string used in a declaration. */
675 #define WCHAR_TYPE "short unsigned int"
677 /* Width of wchar_t in bits. */
678 #define WCHAR_TYPE_SIZE 16
680 /* A C expression for the size in bits of the type `short' on the
681 target machine. If you don't define this, the default is half a
682 word. (If this would be less than one storage unit, it is
683 rounded up to one unit.) */
684 #define SHORT_TYPE_SIZE 16
686 /* A C expression for the size in bits of the type `int' on the
687 target machine. If you don't define this, the default is one
689 #define INT_TYPE_SIZE 32
691 /* A C expression for the size in bits of the type `long' on the
692 target machine. If you don't define this, the default is one
694 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
696 /* A C expression for the size in bits of the type `long long' on the
697 target machine. If you don't define this, the default is two
699 #define LONG_LONG_TYPE_SIZE 64
701 /* A C expression for the size in bits of the type `float' on the
702 target machine. If you don't define this, the default is one
704 #define FLOAT_TYPE_SIZE 32
706 /* A C expression for the size in bits of the type `double' on the
707 target machine. If you don't define this, the default is two
709 #define DOUBLE_TYPE_SIZE 64
711 /* A C expression for the size in bits of the type `long double' on
712 the target machine. If you don't define this, the default is two
714 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
716 /* Define this to set long double type size to use in libgcc2.c, which can
717 not depend on target_flags. */
718 #ifdef __LONG_DOUBLE_128__
719 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
721 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
724 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
725 #define WIDEST_HARDWARE_FP_SIZE 64
727 /* Width in bits of a pointer.
728 See also the macro `Pmode' defined below. */
729 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
731 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
732 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
734 /* Boundary (in *bits*) on which stack pointer should be aligned. */
735 #define STACK_BOUNDARY \
736 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI) ? 64 : 128)
738 /* Allocation boundary (in *bits*) for the code of a function. */
739 #define FUNCTION_BOUNDARY 32
741 /* No data type wants to be aligned rounder than this. */
742 #define BIGGEST_ALIGNMENT 128
744 /* A C expression to compute the alignment for a variables in the
745 local store. TYPE is the data type, and ALIGN is the alignment
746 that the object would ordinarily have. */
747 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
748 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
749 (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 : \
750 (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN)
752 /* Alignment of field after `int : 0' in a structure. */
753 #define EMPTY_FIELD_BOUNDARY 32
755 /* Every structure's size must be a multiple of this. */
756 #define STRUCTURE_SIZE_BOUNDARY 8
758 /* Return 1 if a structure or array containing FIELD should be
759 accessed using `BLKMODE'.
761 For the SPE, simd types are V2SI, and gcc can be tempted to put the
762 entire thing in a DI and use subregs to access the internals.
763 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
764 back-end. Because a single GPR can hold a V2SI, but not a DI, the
765 best thing to do is set structs to BLKmode and avoid Severe Tire
768 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
769 fit into 1, whereas DI still needs two. */
770 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
771 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
772 || (TARGET_E500_DOUBLE && (MODE) == DFmode))
774 /* A bit-field declared as `int' forces `int' alignment for the struct. */
775 #define PCC_BITFIELD_TYPE_MATTERS 1
777 /* Make strings word-aligned so strcpy from constants will be faster.
778 Make vector constants quadword aligned. */
779 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
780 (TREE_CODE (EXP) == STRING_CST \
781 && (ALIGN) < BITS_PER_WORD \
785 /* Make arrays of chars word-aligned for the same reasons.
786 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
788 #define DATA_ALIGNMENT(TYPE, ALIGN) \
789 (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \
790 : (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 \
791 : TREE_CODE (TYPE) == ARRAY_TYPE \
792 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
793 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
795 /* Nonzero if move instructions will actually fail to work
796 when given unaligned data. */
797 #define STRICT_ALIGNMENT 0
799 /* Define this macro to be the value 1 if unaligned accesses have a cost
800 many times greater than aligned accesses, for example if they are
801 emulated in a trap handler. */
802 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
804 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
805 || (MODE) == DImode) \
808 /* Standard register usage. */
810 /* Number of actual hardware registers.
811 The hardware registers are assigned numbers for the compiler
812 from 0 to just below FIRST_PSEUDO_REGISTER.
813 All registers that the compiler knows about must be given numbers,
814 even those that are not normally considered general registers.
816 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
817 an MQ register, a count register, a link register, and 8 condition
818 register fields, which we view here as separate registers. AltiVec
819 adds 32 vector registers and a VRsave register.
821 In addition, the difference between the frame and argument pointers is
822 a function of the number of registers saved, so we need to have a
823 register for AP that will later be eliminated in favor of SP or FP.
824 This is a normal register, but it is fixed.
826 We also create a pseudo register for float/int conversions, that will
827 really represent the memory location used. It is represented here as
828 a register, in order to work around problems in allocating stack storage
829 in inline functions. */
831 #define FIRST_PSEUDO_REGISTER 113
833 /* This must be included for pre gcc 3.0 glibc compatibility. */
834 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
836 /* Add 32 dwarf columns for synthetic SPE registers. */
837 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 32)
839 /* The SPE has an additional 32 synthetic registers, with DWARF debug
840 info numbering for these registers starting at 1200. While eh_frame
841 register numbering need not be the same as the debug info numbering,
842 we choose to number these regs for eh_frame at 1200 too. This allows
843 future versions of the rs6000 backend to add hard registers and
844 continue to use the gcc hard register numbering for eh_frame. If the
845 extra SPE registers in eh_frame were numbered starting from the
846 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
847 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
848 avoid invalidating older SPE eh_frame info.
850 We must map them here to avoid huge unwinder tables mostly consisting
852 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
853 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER) : (r))
855 /* Use gcc hard register numbering for eh_frame. */
856 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
858 /* 1 for registers that have pervasive standard uses
859 and are not available for the register allocator.
861 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
862 as a local register; for all other OS's r2 is the TOC pointer.
864 cr5 is not supposed to be used.
866 On System V implementations, r13 is fixed and not available for use. */
868 #define FIXED_REGISTERS \
869 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
870 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
871 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
872 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
873 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
874 /* AltiVec registers. */ \
875 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
876 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
881 /* 1 for registers not available across function calls.
882 These must include the FIXED_REGISTERS and also any
883 registers that can be used without being saved.
884 The latter must include the registers where values are returned
885 and the register where structure-value addresses are passed.
886 Aside from that, you can include as many other registers as you like. */
888 #define CALL_USED_REGISTERS \
889 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
890 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
891 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
892 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
893 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
894 /* AltiVec registers. */ \
895 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
896 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
901 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
902 the entire set of `FIXED_REGISTERS' be included.
903 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
904 This macro is optional. If not specified, it defaults to the value
905 of `CALL_USED_REGISTERS'. */
907 #define CALL_REALLY_USED_REGISTERS \
908 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
909 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
910 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
911 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
912 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
913 /* AltiVec registers. */ \
914 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
915 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
926 #define MAX_CR_REGNO 75
928 #define FIRST_ALTIVEC_REGNO 77
929 #define LAST_ALTIVEC_REGNO 108
930 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
931 #define VRSAVE_REGNO 109
932 #define VSCR_REGNO 110
933 #define SPE_ACC_REGNO 111
934 #define SPEFSCR_REGNO 112
936 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
937 #define FIRST_SAVED_FP_REGNO (14+32)
938 #define FIRST_SAVED_GP_REGNO 13
940 /* List the order in which to allocate registers. Each register must be
941 listed once, even those in FIXED_REGISTERS.
943 We allocate in the following order:
944 fp0 (not saved or used for anything)
945 fp13 - fp2 (not saved; incoming fp arg registers)
946 fp1 (not saved; return value)
947 fp31 - fp14 (saved; order given to save least number)
948 cr7, cr6 (not saved or special)
949 cr1 (not saved, but used for FP operations)
950 cr0 (not saved, but used for arithmetic operations)
951 cr4, cr3, cr2 (saved)
952 r0 (not saved; cannot be base reg)
953 r9 (not saved; best for TImode)
954 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
955 r3 (not saved; return value register)
956 r31 - r13 (saved; order given to save least number)
957 r12 (not saved; if used for DImode or DFmode would use r13)
958 mq (not saved; best to use it if we can)
959 ctr (not saved; when we have the choice ctr is better)
961 cr5, r1, r2, ap, xer (fixed)
962 v0 - v1 (not saved or used for anything)
963 v13 - v3 (not saved; incoming vector arg registers)
964 v2 (not saved; incoming vector arg reg; return value)
965 v19 - v14 (not saved or used for anything)
966 v31 - v20 (saved; order given to save least number)
968 spe_acc, spefscr (fixed)
972 #define MAYBE_R2_AVAILABLE
973 #define MAYBE_R2_FIXED 2,
975 #define MAYBE_R2_AVAILABLE 2,
976 #define MAYBE_R2_FIXED
979 #define REG_ALLOC_ORDER \
981 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
983 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
984 50, 49, 48, 47, 46, \
985 75, 74, 69, 68, 72, 71, 70, \
986 0, MAYBE_R2_AVAILABLE \
987 9, 11, 10, 8, 7, 6, 5, 4, \
989 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
990 18, 17, 16, 15, 14, 13, 12, \
992 73, 1, MAYBE_R2_FIXED 67, 76, \
993 /* AltiVec registers. */ \
995 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
997 96, 95, 94, 93, 92, 91, \
998 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
1003 /* True if register is floating-point. */
1004 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
1006 /* True if register is a condition register. */
1007 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
1009 /* True if register is a condition register, but not cr0. */
1010 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
1012 /* True if register is an integer register. */
1013 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
1015 /* SPE SIMD registers are just the GPRs. */
1016 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
1018 /* True if register is the XER register. */
1019 #define XER_REGNO_P(N) ((N) == XER_REGNO)
1021 /* True if register is an AltiVec register. */
1022 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1024 /* Return number of consecutive hard regs needed starting at reg REGNO
1025 to hold something of mode MODE. */
1027 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs ((REGNO), (MODE))
1029 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1030 ((TARGET_32BIT && TARGET_POWERPC64 \
1031 && (GET_MODE_SIZE (MODE) > 4) \
1032 && INT_REGNO_P (REGNO)) ? 1 : 0)
1034 #define ALTIVEC_VECTOR_MODE(MODE) \
1035 ((MODE) == V16QImode \
1036 || (MODE) == V8HImode \
1037 || (MODE) == V4SFmode \
1038 || (MODE) == V4SImode)
1040 #define SPE_VECTOR_MODE(MODE) \
1041 ((MODE) == V4HImode \
1042 || (MODE) == V2SFmode \
1043 || (MODE) == V1DImode \
1044 || (MODE) == V2SImode)
1046 #define UNITS_PER_SIMD_WORD \
1047 (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD \
1048 : (TARGET_SPE ? UNITS_PER_SPE_WORD : UNITS_PER_WORD))
1050 /* Value is TRUE if hard register REGNO can hold a value of
1051 machine-mode MODE. */
1052 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1053 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
1055 /* Value is 1 if it is a good idea to tie two pseudo registers
1056 when one has mode MODE1 and one has mode MODE2.
1057 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1058 for any hard reg, then this must be 0 for correct output. */
1059 #define MODES_TIEABLE_P(MODE1, MODE2) \
1060 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
1061 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
1062 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
1063 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
1064 : GET_MODE_CLASS (MODE1) == MODE_CC \
1065 ? GET_MODE_CLASS (MODE2) == MODE_CC \
1066 : GET_MODE_CLASS (MODE2) == MODE_CC \
1067 ? GET_MODE_CLASS (MODE1) == MODE_CC \
1068 : SPE_VECTOR_MODE (MODE1) \
1069 ? SPE_VECTOR_MODE (MODE2) \
1070 : SPE_VECTOR_MODE (MODE2) \
1071 ? SPE_VECTOR_MODE (MODE1) \
1072 : ALTIVEC_VECTOR_MODE (MODE1) \
1073 ? ALTIVEC_VECTOR_MODE (MODE2) \
1074 : ALTIVEC_VECTOR_MODE (MODE2) \
1075 ? ALTIVEC_VECTOR_MODE (MODE1) \
1078 /* Post-reload, we can't use any new AltiVec registers, as we already
1079 emitted the vrsave mask. */
1081 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1082 (! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST])
1084 /* A C expression returning the cost of moving data from a register of class
1085 CLASS1 to one of CLASS2. */
1087 #define REGISTER_MOVE_COST rs6000_register_move_cost
1089 /* A C expressions returning the cost of moving data of MODE from a register to
1092 #define MEMORY_MOVE_COST rs6000_memory_move_cost
1094 /* Specify the cost of a branch insn; roughly the number of extra insns that
1095 should be added to avoid a branch.
1097 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1098 unscheduled conditional branch. */
1100 #define BRANCH_COST 3
1102 /* Override BRANCH_COST heuristic which empirically produces worse
1103 performance for removing short circuiting from the logical ops. */
1105 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1107 /* A fixed register used at prologue and epilogue generation to fix
1108 addressing modes. The SPE needs heavy addressing fixes at the last
1109 minute, and it's best to save a register for it.
1111 AltiVec also needs fixes, but we've gotten around using r11, which
1112 is actually wrong because when use_backchain_to_restore_sp is true,
1113 we end up clobbering r11.
1115 The AltiVec case needs to be fixed. Dunno if we should break ABI
1116 compatibility and reserve a register for it as well.. */
1118 #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11)
1120 /* Define this macro to change register usage conditional on target
1123 #define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
1125 /* Specify the registers used for certain standard purposes.
1126 The values of these macros are register numbers. */
1128 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1129 /* #define PC_REGNUM */
1131 /* Register to use for pushing function arguments. */
1132 #define STACK_POINTER_REGNUM 1
1134 /* Base register for access to local variables of the function. */
1135 #define FRAME_POINTER_REGNUM 31
1137 /* Value should be nonzero if functions must have frame pointers.
1138 Zero means the frame pointer need not be set up (and parms
1139 may be accessed via the stack pointer) in functions that seem suitable.
1140 This is computed in `reload', in reload1.c. */
1141 #define FRAME_POINTER_REQUIRED 0
1143 /* Base register for access to arguments of the function. */
1144 #define ARG_POINTER_REGNUM 67
1146 /* Place to put static chain when calling a function that requires it. */
1147 #define STATIC_CHAIN_REGNUM 11
1149 /* Link register number. */
1150 #define LINK_REGISTER_REGNUM 65
1152 /* Count register number. */
1153 #define COUNT_REGISTER_REGNUM 66
1155 /* Define the classes of registers for register constraints in the
1156 machine description. Also define ranges of constants.
1158 One of the classes must always be named ALL_REGS and include all hard regs.
1159 If there is more than one class, another class must be named NO_REGS
1160 and contain no registers.
1162 The name GENERAL_REGS must be the name of a class (or an alias for
1163 another name such as ALL_REGS). This is the class of registers
1164 that is allowed by "g" or "r" in a register constraint.
1165 Also, registers outside this class are allocated only when
1166 instructions express preferences for them.
1168 The classes must be numbered in nondecreasing order; that is,
1169 a larger-numbered class must never be contained completely
1170 in a smaller-numbered class.
1172 For any two classes, it is very desirable that there be another
1173 class that represents their union. */
1175 /* The RS/6000 has three types of registers, fixed-point, floating-point,
1176 and condition registers, plus three special registers, MQ, CTR, and the
1177 link register. AltiVec adds a vector register class.
1179 However, r0 is special in that it cannot be used as a base register.
1180 So make a class for registers valid as base registers.
1182 Also, cr0 is the only condition code register that can be used in
1183 arithmetic insns, so make a separate class for it. */
1211 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1213 /* Give names of register classes as strings for dump file. */
1215 #define REG_CLASS_NAMES \
1226 "NON_SPECIAL_REGS", \
1230 "LINK_OR_CTR_REGS", \
1232 "SPEC_OR_GEN_REGS", \
1240 /* Define which registers fit in which classes.
1241 This is an initializer for a vector of HARD_REG_SET
1242 of length N_REG_CLASSES. */
1244 #define REG_CLASS_CONTENTS \
1246 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1247 { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \
1248 { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \
1249 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1250 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1251 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1252 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1253 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1254 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1255 { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
1256 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1257 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1258 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1259 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1260 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1261 { 0xffffffff, 0x00000000, 0x0000000f, 0x00002000 }, /* SPEC_OR_GEN_REGS */ \
1262 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1263 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1264 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1265 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1266 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0001ffff } /* ALL_REGS */ \
1269 /* The same information, inverted:
1270 Return the class number of the smallest class containing
1271 reg number REGNO. This could be a conditional expression
1272 or could index an array. */
1274 #define REGNO_REG_CLASS(REGNO) \
1275 ((REGNO) == 0 ? GENERAL_REGS \
1276 : (REGNO) < 32 ? BASE_REGS \
1277 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1278 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1279 : (REGNO) == CR0_REGNO ? CR0_REGS \
1280 : CR_REGNO_P (REGNO) ? CR_REGS \
1281 : (REGNO) == MQ_REGNO ? MQ_REGS \
1282 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1283 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1284 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1285 : (REGNO) == XER_REGNO ? XER_REGS \
1286 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1287 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1288 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
1289 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
1292 /* The class value for index registers, and the one for base regs. */
1293 #define INDEX_REG_CLASS GENERAL_REGS
1294 #define BASE_REG_CLASS BASE_REGS
1296 /* Get reg_class from a letter such as appears in the machine description. */
1298 #define REG_CLASS_FROM_LETTER(C) \
1299 ((C) == 'f' ? ((TARGET_HARD_FLOAT && TARGET_FPRS) ? FLOAT_REGS : NO_REGS) \
1300 : (C) == 'b' ? BASE_REGS \
1301 : (C) == 'h' ? SPECIAL_REGS \
1302 : (C) == 'q' ? MQ_REGS \
1303 : (C) == 'c' ? CTR_REGS \
1304 : (C) == 'l' ? LINK_REGS \
1305 : (C) == 'v' ? ALTIVEC_REGS \
1306 : (C) == 'x' ? CR0_REGS \
1307 : (C) == 'y' ? CR_REGS \
1308 : (C) == 'z' ? XER_REGS \
1311 /* The letters I, J, K, L, M, N, and P in a register constraint string
1312 can be used to stand for particular ranges of immediate operands.
1313 This macro defines what the ranges are.
1314 C is the letter, and VALUE is a constant value.
1315 Return 1 if VALUE is in the range specified by C.
1317 `I' is a signed 16-bit constant
1318 `J' is a constant with only the high-order 16 bits nonzero
1319 `K' is a constant with only the low-order 16 bits nonzero
1320 `L' is a signed 16-bit constant shifted left 16 bits
1321 `M' is a constant that is greater than 31
1322 `N' is a positive constant that is an exact power of two
1323 `O' is the constant zero
1324 `P' is a constant whose negation is a signed 16-bit constant */
1326 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1327 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1328 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1329 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1330 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1331 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1332 : (C) == 'M' ? (VALUE) > 31 \
1333 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1334 : (C) == 'O' ? (VALUE) == 0 \
1335 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1338 /* Similar, but for floating constants, and defining letters G and H.
1339 Here VALUE is the CONST_DOUBLE rtx itself.
1341 We flag for special constants when we can copy the constant into
1342 a general register in two insns for DF/DI and one insn for SF.
1344 'H' is used for DI/DF constants that take 3 insns. */
1346 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1347 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1348 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1349 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1352 /* Optional extra constraints for this machine.
1354 'Q' means that is a memory operand that is just an offset from a reg.
1355 'R' is for AIX TOC entries.
1356 'S' is a constant that can be placed into a 64-bit mask operand
1357 'T' is a constant that can be placed into a 32-bit mask operand
1358 'U' is for V.4 small data references.
1359 'W' is a vector constant that can be easily generated (no mem refs).
1360 'Y' is a indexed or word-aligned displacement memory operand.
1361 'Z' is an indexed or indirect memory operand.
1362 't' is for AND masks that can be performed by two rldic{l,r} insns. */
1364 #define EXTRA_CONSTRAINT(OP, C) \
1365 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1366 : (C) == 'R' ? legitimate_constant_pool_address_p (OP) \
1367 : (C) == 'S' ? mask64_operand (OP, DImode) \
1368 : (C) == 'T' ? mask_operand (OP, SImode) \
1369 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
1370 && small_data_operand (OP, GET_MODE (OP))) \
1371 : (C) == 't' ? (mask64_2_operand (OP, DImode) \
1372 && (fixed_regs[CR0_REGNO] \
1373 || !logical_operand (OP, DImode)) \
1374 && !mask64_operand (OP, DImode)) \
1375 : (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP))) \
1376 : (C) == 'Y' ? (word_offset_memref_operand (OP, GET_MODE (OP))) \
1377 : (C) == 'Z' ? (indexed_or_indirect_operand (OP, GET_MODE (OP))) \
1380 /* Define which constraints are memory constraints. Tell reload
1381 that any memory address can be reloaded by copying the
1382 memory address into a base register if required. */
1384 #define EXTRA_MEMORY_CONSTRAINT(C, STR) \
1385 ((C) == 'Q' || (C) == 'Y' || (C) == 'Z')
1387 /* Given an rtx X being reloaded into a reg required to be
1388 in class CLASS, return the class of reg to actually use.
1389 In general this is just CLASS; but on some machines
1390 in some cases it is preferable to use a more restrictive class.
1392 On the RS/6000, we have to return NO_REGS when we want to reload a
1393 floating-point CONST_DOUBLE to force it to be copied to memory.
1395 We also don't want to reload integer values into floating-point
1396 registers if we can at all help it. In fact, this can
1397 cause reload to die, if it tries to generate a reload of CTR
1398 into a FP register and discovers it doesn't have the memory location
1401 ??? Would it be a good idea to have reload do the converse, that is
1402 try to reload floating modes into FP registers if possible?
1405 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1407 && reg_classes_intersect_p ((CLASS), FLOAT_REGS)) \
1409 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1410 && (CLASS) == NON_SPECIAL_REGS) \
1414 /* Return the register class of a scratch register needed to copy IN into
1415 or out of a register in CLASS in MODE. If it can be done directly,
1416 NO_REGS is returned. */
1418 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1419 secondary_reload_class (CLASS, MODE, IN)
1421 /* If we are copying between FP or AltiVec registers and anything
1422 else, we need a memory location. */
1424 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1425 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1426 || (CLASS2) == FLOAT_REGS \
1427 || (CLASS1) == ALTIVEC_REGS \
1428 || (CLASS2) == ALTIVEC_REGS))
1430 /* Return the maximum number of consecutive registers
1431 needed to represent mode MODE in a register of class CLASS.
1433 On RS/6000, this is the size of MODE in words,
1434 except in the FP regs, where a single reg is enough for two words. */
1435 #define CLASS_MAX_NREGS(CLASS, MODE) \
1436 (((CLASS) == FLOAT_REGS) \
1437 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1438 : (TARGET_E500_DOUBLE && (CLASS) == GENERAL_REGS && (MODE) == DFmode) \
1440 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1443 /* Return a class of registers that cannot change FROM mode to TO mode. */
1445 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1446 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) \
1447 && GET_MODE_SIZE (FROM) >= 8 && GET_MODE_SIZE (TO) >= 8) \
1449 : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1450 ? reg_classes_intersect_p (FLOAT_REGS, CLASS) \
1451 : (TARGET_E500_DOUBLE && (((TO) == DFmode) + ((FROM) == DFmode)) == 1) \
1452 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
1453 : (TARGET_E500_DOUBLE && (((TO) == DImode) + ((FROM) == DImode)) == 1) \
1454 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
1455 : (TARGET_SPE && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1) \
1456 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
1459 /* Stack layout; function entry, exit and calling. */
1461 /* Enumeration to give which calling sequence to use. */
1464 ABI_AIX, /* IBM's AIX */
1465 ABI_V4, /* System V.4/eabi */
1466 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1469 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1471 /* Define this if pushing a word on the stack
1472 makes the stack pointer a smaller address. */
1473 #define STACK_GROWS_DOWNWARD
1475 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1476 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1478 /* Define this if the nominal address of the stack frame
1479 is at the high-address end of the local variables;
1480 that is, each additional local variable allocated
1481 goes at a more negative offset in the frame.
1483 On the RS/6000, we grow upwards, from the area after the outgoing
1485 /* #define FRAME_GROWS_DOWNWARD */
1487 /* Size of the outgoing register save area */
1488 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1489 || DEFAULT_ABI == ABI_DARWIN) \
1490 ? (TARGET_64BIT ? 64 : 32) \
1493 /* Size of the fixed area on the stack */
1494 #define RS6000_SAVE_AREA \
1495 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1496 << (TARGET_64BIT ? 1 : 0))
1498 /* MEM representing address to save the TOC register */
1499 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1500 plus_constant (stack_pointer_rtx, \
1501 (TARGET_32BIT ? 20 : 40)))
1503 /* Size of the V.4 varargs area if needed */
1504 #define RS6000_VARARGS_AREA 0
1506 /* Align an address */
1507 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1509 /* Size of V.4 varargs area in bytes */
1510 #define RS6000_VARARGS_SIZE \
1511 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
1513 /* Offset within stack frame to start allocating local variables at.
1514 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1515 first local allocated. Otherwise, it is the offset to the BEGINNING
1516 of the first local allocated.
1518 On the RS/6000, the frame pointer is the same as the stack pointer,
1519 except for dynamic allocations. So we start after the fixed area and
1520 outgoing parameter area. */
1522 #define STARTING_FRAME_OFFSET \
1523 (RS6000_ALIGN (current_function_outgoing_args_size, \
1524 TARGET_ALTIVEC ? 16 : 8) \
1525 + RS6000_VARARGS_AREA \
1528 /* Offset from the stack pointer register to an item dynamically
1529 allocated on the stack, e.g., by `alloca'.
1531 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1532 length of the outgoing arguments. The default is correct for most
1533 machines. See `function.c' for details. */
1534 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1535 (RS6000_ALIGN (current_function_outgoing_args_size, \
1536 TARGET_ALTIVEC ? 16 : 8) \
1537 + (STACK_POINTER_OFFSET))
1539 /* If we generate an insn to push BYTES bytes,
1540 this says how many the stack pointer really advances by.
1541 On RS/6000, don't define this because there are no push insns. */
1542 /* #define PUSH_ROUNDING(BYTES) */
1544 /* Offset of first parameter from the argument pointer register value.
1545 On the RS/6000, we define the argument pointer to the start of the fixed
1547 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1549 /* Offset from the argument pointer register value to the top of
1550 stack. This is different from FIRST_PARM_OFFSET because of the
1551 register save area. */
1552 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1554 /* Define this if stack space is still allocated for a parameter passed
1555 in a register. The value is the number of bytes allocated to this
1557 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1559 /* Define this if the above stack space is to be considered part of the
1560 space allocated by the caller. */
1561 #define OUTGOING_REG_PARM_STACK_SPACE
1563 /* This is the difference between the logical top of stack and the actual sp.
1565 For the RS/6000, sp points past the fixed area. */
1566 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1568 /* Define this if the maximum size of all the outgoing args is to be
1569 accumulated and pushed during the prologue. The amount can be
1570 found in the variable current_function_outgoing_args_size. */
1571 #define ACCUMULATE_OUTGOING_ARGS 1
1573 /* Value is the number of bytes of arguments automatically
1574 popped when returning from a subroutine call.
1575 FUNDECL is the declaration node of the function (as a tree),
1576 FUNTYPE is the data type of the function (as a tree),
1577 or for a library call it is an identifier node for the subroutine name.
1578 SIZE is the number of bytes of arguments passed on the stack. */
1580 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1582 /* Define how to find the value returned by a function.
1583 VALTYPE is the data type of the value (as a tree).
1584 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1585 otherwise, FUNC is 0. */
1587 #define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC))
1589 /* Define how to find the value returned by a library function
1590 assuming the value has mode MODE. */
1592 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1594 /* DRAFT_V4_STRUCT_RET defaults off. */
1595 #define DRAFT_V4_STRUCT_RET 0
1597 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1598 #define DEFAULT_PCC_STRUCT_RETURN 0
1600 /* Mode of stack savearea.
1601 FUNCTION is VOIDmode because calling convention maintains SP.
1602 BLOCK needs Pmode for SP.
1603 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1604 #define STACK_SAVEAREA_MODE(LEVEL) \
1605 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1606 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1608 /* Minimum and maximum general purpose registers used to hold arguments. */
1609 #define GP_ARG_MIN_REG 3
1610 #define GP_ARG_MAX_REG 10
1611 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1613 /* Minimum and maximum floating point registers used to hold arguments. */
1614 #define FP_ARG_MIN_REG 33
1615 #define FP_ARG_AIX_MAX_REG 45
1616 #define FP_ARG_V4_MAX_REG 40
1617 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1618 || DEFAULT_ABI == ABI_DARWIN) \
1619 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1620 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1622 /* Minimum and maximum AltiVec registers used to hold arguments. */
1623 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1624 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1625 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1627 /* Return registers */
1628 #define GP_ARG_RETURN GP_ARG_MIN_REG
1629 #define FP_ARG_RETURN FP_ARG_MIN_REG
1630 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1632 /* Flags for the call/call_value rtl operations set up by function_arg */
1633 #define CALL_NORMAL 0x00000000 /* no special processing */
1634 /* Bits in 0x00000001 are unused. */
1635 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1636 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1637 #define CALL_LONG 0x00000008 /* always call indirect */
1638 #define CALL_LIBCALL 0x00000010 /* libcall */
1640 /* We don't have prologue and epilogue functions to save/restore
1641 everything for most ABIs. */
1642 #define WORLD_SAVE_P(INFO) 0
1644 /* 1 if N is a possible register number for a function value
1645 as seen by the caller.
1647 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1648 #define FUNCTION_VALUE_REGNO_P(N) \
1649 ((N) == GP_ARG_RETURN \
1650 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
1651 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1653 /* 1 if N is a possible register number for function argument passing.
1654 On RS/6000, these are r3-r10 and fp1-fp13.
1655 On AltiVec, v2 - v13 are used for passing vectors. */
1656 #define FUNCTION_ARG_REGNO_P(N) \
1657 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1658 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1659 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1660 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1661 && TARGET_HARD_FLOAT && TARGET_FPRS))
1663 /* A C structure for machine-specific, per-function data.
1664 This is added to the cfun structure. */
1665 typedef struct machine_function GTY(())
1667 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
1668 int ra_needs_full_frame;
1669 /* Some local-dynamic symbol. */
1670 const char *some_ld_name;
1671 /* Whether the instruction chain has been scanned already. */
1672 int insn_chain_scanned_p;
1673 /* Flags if __builtin_return_address (0) was used. */
1677 /* Define a data type for recording info about an argument list
1678 during the scan of that argument list. This data type should
1679 hold all necessary information about the function itself
1680 and about the args processed so far, enough to enable macros
1681 such as FUNCTION_ARG to determine where the next arg should go.
1683 On the RS/6000, this is a structure. The first element is the number of
1684 total argument words, the second is used to store the next
1685 floating-point register number, and the third says how many more args we
1686 have prototype types for.
1688 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1689 the next available GP register, `fregno' is the next available FP
1690 register, and `words' is the number of words used on the stack.
1692 The varargs/stdarg support requires that this structure's size
1693 be a multiple of sizeof(int). */
1695 typedef struct rs6000_args
1697 int words; /* # words used for passing GP registers */
1698 int fregno; /* next available FP register */
1699 int vregno; /* next available AltiVec register */
1700 int nargs_prototype; /* # args left in the current prototype */
1701 int prototype; /* Whether a prototype was defined */
1702 int stdarg; /* Whether function is a stdarg function. */
1703 int call_cookie; /* Do special things for this call */
1704 int sysv_gregno; /* next available GP register */
1705 int intoffset; /* running offset in struct (darwin64) */
1706 int use_stack; /* any part of struct on stack (darwin64) */
1707 int named; /* false for varargs params */
1710 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1711 for a call to a function whose data type is FNTYPE.
1712 For a library call, FNTYPE is 0. */
1714 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1715 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
1717 /* Similar, but when scanning the definition of a procedure. We always
1718 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1720 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1721 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
1723 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1725 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1726 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
1728 /* Update the data in CUM to advance over an argument
1729 of mode MODE and data type TYPE.
1730 (TYPE is null for libcalls where that information may not be available.) */
1732 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1733 function_arg_advance (&CUM, MODE, TYPE, NAMED, 0)
1735 /* Determine where to put an argument to a function.
1736 Value is zero to push the argument on the stack,
1737 or a hard register in which to store the argument.
1739 MODE is the argument's machine mode.
1740 TYPE is the data type of the argument (as a tree).
1741 This is null for libcalls where that information may
1743 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1744 the preceding args and about the function being called.
1745 NAMED is nonzero if this argument is a named parameter
1746 (otherwise it is an extra parameter matching an ellipsis).
1748 On RS/6000 the first eight words of non-FP are normally in registers
1749 and the rest are pushed. The first 13 FP args are in registers.
1751 If this is floating-point and no prototype is specified, we use
1752 both an FP and integer register (or possibly FP reg and stack). Library
1753 functions (when TYPE is zero) always have the proper types for args,
1754 so we can pass the FP value just in one register. emit_library_function
1755 doesn't support EXPR_LIST anyway. */
1757 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1758 function_arg (&CUM, MODE, TYPE, NAMED)
1760 /* If defined, a C expression which determines whether, and in which
1761 direction, to pad out an argument with extra space. The value
1762 should be of type `enum direction': either `upward' to pad above
1763 the argument, `downward' to pad below, or `none' to inhibit
1766 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1768 /* If defined, a C expression that gives the alignment boundary, in bits,
1769 of an argument with the specified mode and type. If it is not defined,
1770 PARM_BOUNDARY is used for all arguments. */
1772 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1773 function_arg_boundary (MODE, TYPE)
1775 /* Implement `va_start' for varargs and stdarg. */
1776 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1777 rs6000_va_start (valist, nextarg)
1779 #define PAD_VARARGS_DOWN \
1780 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1782 /* Output assembler code to FILE to increment profiler label # LABELNO
1783 for profiling a function entry. */
1785 #define FUNCTION_PROFILER(FILE, LABELNO) \
1786 output_function_profiler ((FILE), (LABELNO));
1788 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1789 the stack pointer does not matter. No definition is equivalent to
1792 On the RS/6000, this is nonzero because we can restore the stack from
1793 its backpointer, which we maintain. */
1794 #define EXIT_IGNORE_STACK 1
1796 /* Define this macro as a C expression that is nonzero for registers
1797 that are used by the epilogue or the return' pattern. The stack
1798 and frame pointer registers are already be assumed to be used as
1801 #define EPILOGUE_USES(REGNO) \
1802 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1803 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1804 || (current_function_calls_eh_return \
1809 /* TRAMPOLINE_TEMPLATE deleted */
1811 /* Length in units of the trampoline for entering a nested function. */
1813 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1815 /* Emit RTL insns to initialize the variable parts of a trampoline.
1816 FNADDR is an RTX for the address of the function's pure code.
1817 CXT is an RTX for the static chain value for the function. */
1819 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1820 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1822 /* Definitions for __builtin_return_address and __builtin_frame_address.
1823 __builtin_return_address (0) should give link register (65), enable
1825 /* This should be uncommented, so that the link register is used, but
1826 currently this would result in unmatched insns and spilling fixed
1827 registers so we'll leave it for another day. When these problems are
1828 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1830 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1832 /* Number of bytes into the frame return addresses can be found. See
1833 rs6000_stack_info in rs6000.c for more information on how the different
1834 abi's store the return address. */
1835 #define RETURN_ADDRESS_OFFSET \
1836 ((DEFAULT_ABI == ABI_AIX \
1837 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
1838 (DEFAULT_ABI == ABI_V4) ? 4 : \
1839 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1841 /* The current return address is in link register (65). The return address
1842 of anything farther back is accessed normally at an offset of 8 from the
1844 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1845 (rs6000_return_addr (COUNT, FRAME))
1848 /* Definitions for register eliminations.
1850 We have two registers that can be eliminated on the RS/6000. First, the
1851 frame pointer register can often be eliminated in favor of the stack
1852 pointer register. Secondly, the argument pointer register can always be
1853 eliminated; it is replaced with either the stack or frame pointer.
1855 In addition, we use the elimination mechanism to see if r30 is needed
1856 Initially we assume that it isn't. If it is, we spill it. This is done
1857 by making it an eliminable register. We replace it with itself so that
1858 if it isn't needed, then existing uses won't be modified. */
1860 /* This is an array of structures. Each structure initializes one pair
1861 of eliminable registers. The "from" register number is given first,
1862 followed by "to". Eliminations of the same "from" register are listed
1863 in order of preference. */
1864 #define ELIMINABLE_REGS \
1865 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1866 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1867 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1868 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1870 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1871 Frame pointer elimination is automatically handled.
1873 For the RS/6000, if frame pointer elimination is being done, we would like
1874 to convert ap into fp, not sp.
1876 We need r30 if -mminimal-toc was specified, and there are constant pool
1879 #define CAN_ELIMINATE(FROM, TO) \
1880 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1881 ? ! frame_pointer_needed \
1882 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1883 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1886 /* Define the offset between two registers, one to be eliminated, and the other
1887 its replacement, at the start of a routine. */
1888 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1889 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1891 /* Addressing modes, and classification of registers for them. */
1893 #define HAVE_PRE_DECREMENT 1
1894 #define HAVE_PRE_INCREMENT 1
1896 /* Macros to check register numbers against specific register classes. */
1898 /* These assume that REGNO is a hard or pseudo reg number.
1899 They give nonzero only if REGNO is a hard reg of the suitable class
1900 or a pseudo reg currently allocated to a suitable hard reg.
1901 Since they use reg_renumber, they are safe only once reg_renumber
1902 has been allocated, which happens in local-alloc.c. */
1904 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1905 ((REGNO) < FIRST_PSEUDO_REGISTER \
1906 ? (REGNO) <= 31 || (REGNO) == 67 \
1907 : (reg_renumber[REGNO] >= 0 \
1908 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1910 #define REGNO_OK_FOR_BASE_P(REGNO) \
1911 ((REGNO) < FIRST_PSEUDO_REGISTER \
1912 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1913 : (reg_renumber[REGNO] > 0 \
1914 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1916 /* Maximum number of registers that can appear in a valid memory address. */
1918 #define MAX_REGS_PER_ADDRESS 2
1920 /* Recognize any constant value that is a valid address. */
1922 #define CONSTANT_ADDRESS_P(X) \
1923 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1924 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1925 || GET_CODE (X) == HIGH)
1927 /* Nonzero if the constant value X is a legitimate general operand.
1928 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1930 On the RS/6000, all integer constants are acceptable, most won't be valid
1931 for particular insns, though. Only easy FP constants are
1934 #define LEGITIMATE_CONSTANT_P(X) \
1935 (((GET_CODE (X) != CONST_DOUBLE \
1936 && GET_CODE (X) != CONST_VECTOR) \
1937 || GET_MODE (X) == VOIDmode \
1938 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1939 || easy_fp_constant (X, GET_MODE (X)) \
1940 || easy_vector_constant (X, GET_MODE (X))) \
1941 && !rs6000_tls_referenced_p (X))
1943 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1944 #define EASY_VECTOR_15_ADD_SELF(n) ((n) >= 0x10 && (n) <= 0x1e && !((n) & 1))
1946 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1947 and check its validity for a certain class.
1948 We have two alternate definitions for each of them.
1949 The usual definition accepts all pseudo regs; the other rejects
1950 them unless they have been allocated suitable hard regs.
1951 The symbol REG_OK_STRICT causes the latter definition to be used.
1953 Most source files want to accept pseudo regs in the hope that
1954 they will get allocated to the class that the insn wants them to be in.
1955 Source files for reload pass need to be strict.
1956 After reload, it makes no difference, since pseudo regs have
1957 been eliminated by then. */
1959 #ifdef REG_OK_STRICT
1960 # define REG_OK_STRICT_FLAG 1
1962 # define REG_OK_STRICT_FLAG 0
1965 /* Nonzero if X is a hard reg that can be used as an index
1966 or if it is a pseudo reg in the non-strict case. */
1967 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1969 && (REGNO (X) <= 31 \
1970 || REGNO (X) == ARG_POINTER_REGNUM \
1971 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
1972 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
1974 /* Nonzero if X is a hard reg that can be used as a base reg
1975 or if it is a pseudo reg in the non-strict case. */
1976 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1977 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
1979 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
1980 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
1982 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1983 that is a valid memory address for an instruction.
1984 The MODE argument is the machine mode for the MEM expression
1985 that wants to use this address.
1987 On the RS/6000, there are four valid address: a SYMBOL_REF that
1988 refers to a constant pool entry of an address (or the sum of it
1989 plus a constant), a short (16-bit signed) constant plus a register,
1990 the sum of two registers, or a register indirect, possibly with an
1991 auto-increment. For DFmode and DImode with a constant plus register,
1992 we must ensure that both words are addressable or PowerPC64 with offset
1995 For modes spanning multiple registers (DFmode in 32-bit GPRs,
1996 32-bit DImode, TImode), indexed addressing cannot be used because
1997 adjacent memory cells are accessed by adding word-sized offsets
1998 during assembly output. */
2000 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2001 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
2005 /* Try machine-dependent ways of modifying an illegitimate address
2006 to be legitimate. If we find one, return the new, valid address.
2007 This macro is used in only one place: `memory_address' in explow.c.
2009 OLDX is the address as it was before break_out_memory_refs was called.
2010 In some cases it is useful to look at this to decide what needs to be done.
2012 MODE and WIN are passed so that this macro can use
2013 GO_IF_LEGITIMATE_ADDRESS.
2015 It is always safe for this macro to do nothing. It exists to recognize
2016 opportunities to optimize the output.
2018 On RS/6000, first check for the sum of a register with a constant
2019 integer that is out of range. If so, generate code to add the
2020 constant with the low-order 16 bits masked to the register and force
2021 this result into another register (this can be done with `cau').
2022 Then generate an address of REG+(CONST&0xffff), allowing for the
2023 possibility of bit 16 being a one.
2025 Then check for the sum of a register and something not constant, try to
2026 load the other things into a register and return the sum. */
2028 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2029 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
2030 if (result != NULL_RTX) \
2037 /* Try a machine-dependent way of reloading an illegitimate address
2038 operand. If we find one, push the reload and jump to WIN. This
2039 macro is used in only one place: `find_reloads_address' in reload.c.
2041 Implemented on rs6000 by rs6000_legitimize_reload_address.
2042 Note that (X) is evaluated twice; this is safe in current usage. */
2044 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2047 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
2048 (int)(TYPE), (IND_LEVELS), &win); \
2053 /* Go to LABEL if ADDR (a legitimate address expression)
2054 has an effect that depends on the machine mode it is used for. */
2056 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2058 if (rs6000_mode_dependent_address (ADDR)) \
2062 /* The register number of the register used to address a table of
2063 static data addresses in memory. In some cases this register is
2064 defined by a processor's "application binary interface" (ABI).
2065 When this macro is defined, RTL is generated for this register
2066 once, as with the stack pointer and frame pointer registers. If
2067 this macro is not defined, it is up to the machine-dependent files
2068 to allocate such a register (if necessary). */
2070 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
2071 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
2073 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
2075 /* Define this macro if the register defined by
2076 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
2077 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
2079 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
2081 /* By generating position-independent code, when two different
2082 programs (A and B) share a common library (libC.a), the text of
2083 the library can be shared whether or not the library is linked at
2084 the same address for both programs. In some of these
2085 environments, position-independent code requires not only the use
2086 of different addressing modes, but also special code to enable the
2087 use of these addressing modes.
2089 The `FINALIZE_PIC' macro serves as a hook to emit these special
2090 codes once the function is being compiled into assembly code, but
2091 not before. (It is not done before, because in the case of
2092 compiling an inline function, it would lead to multiple PIC
2093 prologues being included in functions which used inline functions
2094 and were compiled to assembly language.) */
2096 /* #define FINALIZE_PIC */
2098 /* A C expression that is nonzero if X is a legitimate immediate
2099 operand on the target machine when generating position independent
2100 code. You can assume that X satisfies `CONSTANT_P', so you need
2101 not check this. You can also assume FLAG_PIC is true, so you need
2102 not check it either. You need not define this macro if all
2103 constants (including `SYMBOL_REF') can be immediate operands when
2104 generating position independent code. */
2106 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2108 /* Define this if some processing needs to be done immediately before
2109 emitting code for an insn. */
2111 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
2113 /* Specify the machine mode that this machine uses
2114 for the index in the tablejump instruction. */
2115 #define CASE_VECTOR_MODE SImode
2117 /* Define as C expression which evaluates to nonzero if the tablejump
2118 instruction expects the table to contain offsets from the address of the
2120 Do not define this if the table should contain absolute addresses. */
2121 #define CASE_VECTOR_PC_RELATIVE 1
2123 /* Define this as 1 if `char' should by default be signed; else as 0. */
2124 #define DEFAULT_SIGNED_CHAR 0
2126 /* This flag, if defined, says the same insns that convert to a signed fixnum
2127 also convert validly to an unsigned one. */
2129 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
2131 /* An integer expression for the size in bits of the largest integer machine
2132 mode that should actually be used. */
2134 /* Allow pairs of registers to be used, which is the intent of the default. */
2135 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
2137 /* Max number of bytes we can move from memory to memory
2138 in one reasonably fast instruction. */
2139 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2140 #define MAX_MOVE_MAX 8
2142 /* Nonzero if access to memory by bytes is no faster than for words.
2143 Also nonzero if doing byte operations (specifically shifts) in registers
2145 #define SLOW_BYTE_ACCESS 1
2147 /* Define if operations between registers always perform the operation
2148 on the full register even if a narrower mode is specified. */
2149 #define WORD_REGISTER_OPERATIONS
2151 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2152 will either zero-extend or sign-extend. The value of this macro should
2153 be the code that says which one of the two operations is implicitly
2154 done, UNKNOWN if none. */
2155 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2157 /* Define if loading short immediate values into registers sign extends. */
2158 #define SHORT_IMMEDIATES_SIGN_EXTEND
2160 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2161 is done just by pretending it is already truncated. */
2162 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2164 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
2165 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2166 ((VALUE) = ((MODE) == SImode ? 32 : 64))
2168 /* The CTZ patterns return -1 for input of zero. */
2169 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1)
2171 /* Specify the machine mode that pointers have.
2172 After generation of rtl, the compiler makes no further distinction
2173 between pointers and any other objects of this machine mode. */
2174 #define Pmode (TARGET_32BIT ? SImode : DImode)
2176 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
2177 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
2179 /* Mode of a function address in a call instruction (for indexing purposes).
2180 Doesn't matter on RS/6000. */
2181 #define FUNCTION_MODE SImode
2183 /* Define this if addresses of constant functions
2184 shouldn't be put through pseudo regs where they can be cse'd.
2185 Desirable on machines where ordinary constants are expensive
2186 but a CALL with constant address is cheap. */
2187 #define NO_FUNCTION_CSE
2189 /* Define this to be nonzero if shift instructions ignore all but the low-order
2192 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2193 have been dropped from the PowerPC architecture. */
2195 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2197 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2198 should be adjusted to reflect any required changes. This macro is used when
2199 there is some systematic length adjustment required that would be difficult
2200 to express in the length attribute. */
2202 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2204 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2205 COMPARE, return the mode to be used for the comparison. For
2206 floating-point, CCFPmode should be used. CCUNSmode should be used
2207 for unsigned comparisons. CCEQmode should be used when we are
2208 doing an inequality comparison on the result of a
2209 comparison. CCmode should be used in all other cases. */
2211 #define SELECT_CC_MODE(OP,X,Y) \
2212 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2213 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2214 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
2215 ? CCEQmode : CCmode))
2217 /* Can the condition code MODE be safely reversed? This is safe in
2218 all cases on this port, because at present it doesn't use the
2219 trapping FP comparisons (fcmpo). */
2220 #define REVERSIBLE_CC_MODE(MODE) 1
2222 /* Given a condition code and a mode, return the inverse condition. */
2223 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
2225 /* Define the information needed to generate branch and scc insns. This is
2226 stored from the compare operation. */
2228 extern GTY(()) rtx rs6000_compare_op0;
2229 extern GTY(()) rtx rs6000_compare_op1;
2230 extern int rs6000_compare_fp_p;
2232 /* Control the assembler format that we output. */
2234 /* A C string constant describing how to begin a comment in the target
2235 assembler language. The compiler assumes that the comment will end at
2236 the end of the line. */
2237 #define ASM_COMMENT_START " #"
2239 /* Flag to say the TOC is initialized */
2240 extern int toc_initialized;
2242 /* Macro to output a special constant pool entry. Go to WIN if we output
2243 it. Otherwise, it is written the usual way.
2245 On the RS/6000, toc entries are handled this way. */
2247 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2248 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2250 output_toc (FILE, X, LABELNO, MODE); \
2255 #ifdef HAVE_GAS_WEAK
2256 #define RS6000_WEAK 1
2258 #define RS6000_WEAK 0
2262 /* Used in lieu of ASM_WEAKEN_LABEL. */
2263 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2266 fputs ("\t.weak\t", (FILE)); \
2267 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2268 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2269 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2272 fputs ("[DS]", (FILE)); \
2273 fputs ("\n\t.weak\t.", (FILE)); \
2274 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2276 fputc ('\n', (FILE)); \
2279 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2280 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2281 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2283 fputs ("\t.set\t.", (FILE)); \
2284 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2285 fputs (",.", (FILE)); \
2286 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2287 fputc ('\n', (FILE)); \
2294 /* This implements the `alias' attribute. */
2295 #undef ASM_OUTPUT_DEF_FROM_DECLS
2296 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2299 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2300 const char *name = IDENTIFIER_POINTER (TARGET); \
2301 if (TREE_CODE (DECL) == FUNCTION_DECL \
2302 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2304 if (TREE_PUBLIC (DECL)) \
2306 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2308 fputs ("\t.globl\t.", FILE); \
2309 RS6000_OUTPUT_BASENAME (FILE, alias); \
2310 putc ('\n', FILE); \
2313 else if (TARGET_XCOFF) \
2315 fputs ("\t.lglobl\t.", FILE); \
2316 RS6000_OUTPUT_BASENAME (FILE, alias); \
2317 putc ('\n', FILE); \
2319 fputs ("\t.set\t.", FILE); \
2320 RS6000_OUTPUT_BASENAME (FILE, alias); \
2321 fputs (",.", FILE); \
2322 RS6000_OUTPUT_BASENAME (FILE, name); \
2323 fputc ('\n', FILE); \
2325 ASM_OUTPUT_DEF (FILE, alias, name); \
2329 #define TARGET_ASM_FILE_START rs6000_file_start
2331 /* Output to assembler file text saying following lines
2332 may contain character constants, extra white space, comments, etc. */
2334 #define ASM_APP_ON ""
2336 /* Output to assembler file text saying following lines
2337 no longer contain unusual constructs. */
2339 #define ASM_APP_OFF ""
2341 /* How to refer to registers in assembler output.
2342 This sequence is indexed by compiler's hard-register-number (see above). */
2344 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2346 #define REGISTER_NAMES \
2348 &rs6000_reg_names[ 0][0], /* r0 */ \
2349 &rs6000_reg_names[ 1][0], /* r1 */ \
2350 &rs6000_reg_names[ 2][0], /* r2 */ \
2351 &rs6000_reg_names[ 3][0], /* r3 */ \
2352 &rs6000_reg_names[ 4][0], /* r4 */ \
2353 &rs6000_reg_names[ 5][0], /* r5 */ \
2354 &rs6000_reg_names[ 6][0], /* r6 */ \
2355 &rs6000_reg_names[ 7][0], /* r7 */ \
2356 &rs6000_reg_names[ 8][0], /* r8 */ \
2357 &rs6000_reg_names[ 9][0], /* r9 */ \
2358 &rs6000_reg_names[10][0], /* r10 */ \
2359 &rs6000_reg_names[11][0], /* r11 */ \
2360 &rs6000_reg_names[12][0], /* r12 */ \
2361 &rs6000_reg_names[13][0], /* r13 */ \
2362 &rs6000_reg_names[14][0], /* r14 */ \
2363 &rs6000_reg_names[15][0], /* r15 */ \
2364 &rs6000_reg_names[16][0], /* r16 */ \
2365 &rs6000_reg_names[17][0], /* r17 */ \
2366 &rs6000_reg_names[18][0], /* r18 */ \
2367 &rs6000_reg_names[19][0], /* r19 */ \
2368 &rs6000_reg_names[20][0], /* r20 */ \
2369 &rs6000_reg_names[21][0], /* r21 */ \
2370 &rs6000_reg_names[22][0], /* r22 */ \
2371 &rs6000_reg_names[23][0], /* r23 */ \
2372 &rs6000_reg_names[24][0], /* r24 */ \
2373 &rs6000_reg_names[25][0], /* r25 */ \
2374 &rs6000_reg_names[26][0], /* r26 */ \
2375 &rs6000_reg_names[27][0], /* r27 */ \
2376 &rs6000_reg_names[28][0], /* r28 */ \
2377 &rs6000_reg_names[29][0], /* r29 */ \
2378 &rs6000_reg_names[30][0], /* r30 */ \
2379 &rs6000_reg_names[31][0], /* r31 */ \
2381 &rs6000_reg_names[32][0], /* fr0 */ \
2382 &rs6000_reg_names[33][0], /* fr1 */ \
2383 &rs6000_reg_names[34][0], /* fr2 */ \
2384 &rs6000_reg_names[35][0], /* fr3 */ \
2385 &rs6000_reg_names[36][0], /* fr4 */ \
2386 &rs6000_reg_names[37][0], /* fr5 */ \
2387 &rs6000_reg_names[38][0], /* fr6 */ \
2388 &rs6000_reg_names[39][0], /* fr7 */ \
2389 &rs6000_reg_names[40][0], /* fr8 */ \
2390 &rs6000_reg_names[41][0], /* fr9 */ \
2391 &rs6000_reg_names[42][0], /* fr10 */ \
2392 &rs6000_reg_names[43][0], /* fr11 */ \
2393 &rs6000_reg_names[44][0], /* fr12 */ \
2394 &rs6000_reg_names[45][0], /* fr13 */ \
2395 &rs6000_reg_names[46][0], /* fr14 */ \
2396 &rs6000_reg_names[47][0], /* fr15 */ \
2397 &rs6000_reg_names[48][0], /* fr16 */ \
2398 &rs6000_reg_names[49][0], /* fr17 */ \
2399 &rs6000_reg_names[50][0], /* fr18 */ \
2400 &rs6000_reg_names[51][0], /* fr19 */ \
2401 &rs6000_reg_names[52][0], /* fr20 */ \
2402 &rs6000_reg_names[53][0], /* fr21 */ \
2403 &rs6000_reg_names[54][0], /* fr22 */ \
2404 &rs6000_reg_names[55][0], /* fr23 */ \
2405 &rs6000_reg_names[56][0], /* fr24 */ \
2406 &rs6000_reg_names[57][0], /* fr25 */ \
2407 &rs6000_reg_names[58][0], /* fr26 */ \
2408 &rs6000_reg_names[59][0], /* fr27 */ \
2409 &rs6000_reg_names[60][0], /* fr28 */ \
2410 &rs6000_reg_names[61][0], /* fr29 */ \
2411 &rs6000_reg_names[62][0], /* fr30 */ \
2412 &rs6000_reg_names[63][0], /* fr31 */ \
2414 &rs6000_reg_names[64][0], /* mq */ \
2415 &rs6000_reg_names[65][0], /* lr */ \
2416 &rs6000_reg_names[66][0], /* ctr */ \
2417 &rs6000_reg_names[67][0], /* ap */ \
2419 &rs6000_reg_names[68][0], /* cr0 */ \
2420 &rs6000_reg_names[69][0], /* cr1 */ \
2421 &rs6000_reg_names[70][0], /* cr2 */ \
2422 &rs6000_reg_names[71][0], /* cr3 */ \
2423 &rs6000_reg_names[72][0], /* cr4 */ \
2424 &rs6000_reg_names[73][0], /* cr5 */ \
2425 &rs6000_reg_names[74][0], /* cr6 */ \
2426 &rs6000_reg_names[75][0], /* cr7 */ \
2428 &rs6000_reg_names[76][0], /* xer */ \
2430 &rs6000_reg_names[77][0], /* v0 */ \
2431 &rs6000_reg_names[78][0], /* v1 */ \
2432 &rs6000_reg_names[79][0], /* v2 */ \
2433 &rs6000_reg_names[80][0], /* v3 */ \
2434 &rs6000_reg_names[81][0], /* v4 */ \
2435 &rs6000_reg_names[82][0], /* v5 */ \
2436 &rs6000_reg_names[83][0], /* v6 */ \
2437 &rs6000_reg_names[84][0], /* v7 */ \
2438 &rs6000_reg_names[85][0], /* v8 */ \
2439 &rs6000_reg_names[86][0], /* v9 */ \
2440 &rs6000_reg_names[87][0], /* v10 */ \
2441 &rs6000_reg_names[88][0], /* v11 */ \
2442 &rs6000_reg_names[89][0], /* v12 */ \
2443 &rs6000_reg_names[90][0], /* v13 */ \
2444 &rs6000_reg_names[91][0], /* v14 */ \
2445 &rs6000_reg_names[92][0], /* v15 */ \
2446 &rs6000_reg_names[93][0], /* v16 */ \
2447 &rs6000_reg_names[94][0], /* v17 */ \
2448 &rs6000_reg_names[95][0], /* v18 */ \
2449 &rs6000_reg_names[96][0], /* v19 */ \
2450 &rs6000_reg_names[97][0], /* v20 */ \
2451 &rs6000_reg_names[98][0], /* v21 */ \
2452 &rs6000_reg_names[99][0], /* v22 */ \
2453 &rs6000_reg_names[100][0], /* v23 */ \
2454 &rs6000_reg_names[101][0], /* v24 */ \
2455 &rs6000_reg_names[102][0], /* v25 */ \
2456 &rs6000_reg_names[103][0], /* v26 */ \
2457 &rs6000_reg_names[104][0], /* v27 */ \
2458 &rs6000_reg_names[105][0], /* v28 */ \
2459 &rs6000_reg_names[106][0], /* v29 */ \
2460 &rs6000_reg_names[107][0], /* v30 */ \
2461 &rs6000_reg_names[108][0], /* v31 */ \
2462 &rs6000_reg_names[109][0], /* vrsave */ \
2463 &rs6000_reg_names[110][0], /* vscr */ \
2464 &rs6000_reg_names[111][0], /* spe_acc */ \
2465 &rs6000_reg_names[112][0], /* spefscr */ \
2468 /* Table of additional register names to use in user input. */
2470 #define ADDITIONAL_REGISTER_NAMES \
2471 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2472 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2473 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2474 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2475 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2476 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2477 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2478 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2479 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2480 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2481 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2482 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2483 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2484 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2485 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2486 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2487 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2488 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2489 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2490 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2491 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2492 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2493 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2494 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2495 {"vrsave", 109}, {"vscr", 110}, \
2496 {"spe_acc", 111}, {"spefscr", 112}, \
2497 /* no additional names for: mq, lr, ctr, ap */ \
2498 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2499 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2500 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2502 /* Text to write out after a CALL that may be replaced by glue code by
2503 the loader. This depends on the AIX version. */
2504 #define RS6000_CALL_GLUE "cror 31,31,31"
2506 /* This is how to output an element of a case-vector that is relative. */
2508 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2509 do { char buf[100]; \
2510 fputs ("\t.long ", FILE); \
2511 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2512 assemble_name (FILE, buf); \
2514 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2515 assemble_name (FILE, buf); \
2516 putc ('\n', FILE); \
2519 /* This is how to output an assembler line
2520 that says to advance the location counter
2521 to a multiple of 2**LOG bytes. */
2523 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2525 fprintf (FILE, "\t.align %d\n", (LOG))
2527 /* Pick up the return address upon entry to a procedure. Used for
2528 dwarf2 unwind information. This also enables the table driven
2531 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2532 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2534 /* Describe how we implement __builtin_eh_return. */
2535 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2536 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2538 /* Print operand X (an rtx) in assembler syntax to file FILE.
2539 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2540 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2542 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2544 /* Define which CODE values are valid. */
2546 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2547 ((CODE) == '.' || (CODE) == '&')
2549 /* Print a memory address as an operand to reference that memory location. */
2551 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2553 /* uncomment for disabling the corresponding default options */
2554 /* #define MACHINE_no_sched_interblock */
2555 /* #define MACHINE_no_sched_speculative */
2556 /* #define MACHINE_no_sched_speculative_load */
2558 /* General flags. */
2559 extern int flag_pic;
2560 extern int optimize;
2561 extern int flag_expensive_optimizations;
2562 extern int frame_pointer_needed;
2564 enum rs6000_builtins
2566 /* AltiVec builtins. */
2567 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2568 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2569 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2570 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2571 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2572 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2573 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2574 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2575 ALTIVEC_BUILTIN_VADDUBM,
2576 ALTIVEC_BUILTIN_VADDUHM,
2577 ALTIVEC_BUILTIN_VADDUWM,
2578 ALTIVEC_BUILTIN_VADDFP,
2579 ALTIVEC_BUILTIN_VADDCUW,
2580 ALTIVEC_BUILTIN_VADDUBS,
2581 ALTIVEC_BUILTIN_VADDSBS,
2582 ALTIVEC_BUILTIN_VADDUHS,
2583 ALTIVEC_BUILTIN_VADDSHS,
2584 ALTIVEC_BUILTIN_VADDUWS,
2585 ALTIVEC_BUILTIN_VADDSWS,
2586 ALTIVEC_BUILTIN_VAND,
2587 ALTIVEC_BUILTIN_VANDC,
2588 ALTIVEC_BUILTIN_VAVGUB,
2589 ALTIVEC_BUILTIN_VAVGSB,
2590 ALTIVEC_BUILTIN_VAVGUH,
2591 ALTIVEC_BUILTIN_VAVGSH,
2592 ALTIVEC_BUILTIN_VAVGUW,
2593 ALTIVEC_BUILTIN_VAVGSW,
2594 ALTIVEC_BUILTIN_VCFUX,
2595 ALTIVEC_BUILTIN_VCFSX,
2596 ALTIVEC_BUILTIN_VCTSXS,
2597 ALTIVEC_BUILTIN_VCTUXS,
2598 ALTIVEC_BUILTIN_VCMPBFP,
2599 ALTIVEC_BUILTIN_VCMPEQUB,
2600 ALTIVEC_BUILTIN_VCMPEQUH,
2601 ALTIVEC_BUILTIN_VCMPEQUW,
2602 ALTIVEC_BUILTIN_VCMPEQFP,
2603 ALTIVEC_BUILTIN_VCMPGEFP,
2604 ALTIVEC_BUILTIN_VCMPGTUB,
2605 ALTIVEC_BUILTIN_VCMPGTSB,
2606 ALTIVEC_BUILTIN_VCMPGTUH,
2607 ALTIVEC_BUILTIN_VCMPGTSH,
2608 ALTIVEC_BUILTIN_VCMPGTUW,
2609 ALTIVEC_BUILTIN_VCMPGTSW,
2610 ALTIVEC_BUILTIN_VCMPGTFP,
2611 ALTIVEC_BUILTIN_VEXPTEFP,
2612 ALTIVEC_BUILTIN_VLOGEFP,
2613 ALTIVEC_BUILTIN_VMADDFP,
2614 ALTIVEC_BUILTIN_VMAXUB,
2615 ALTIVEC_BUILTIN_VMAXSB,
2616 ALTIVEC_BUILTIN_VMAXUH,
2617 ALTIVEC_BUILTIN_VMAXSH,
2618 ALTIVEC_BUILTIN_VMAXUW,
2619 ALTIVEC_BUILTIN_VMAXSW,
2620 ALTIVEC_BUILTIN_VMAXFP,
2621 ALTIVEC_BUILTIN_VMHADDSHS,
2622 ALTIVEC_BUILTIN_VMHRADDSHS,
2623 ALTIVEC_BUILTIN_VMLADDUHM,
2624 ALTIVEC_BUILTIN_VMRGHB,
2625 ALTIVEC_BUILTIN_VMRGHH,
2626 ALTIVEC_BUILTIN_VMRGHW,
2627 ALTIVEC_BUILTIN_VMRGLB,
2628 ALTIVEC_BUILTIN_VMRGLH,
2629 ALTIVEC_BUILTIN_VMRGLW,
2630 ALTIVEC_BUILTIN_VMSUMUBM,
2631 ALTIVEC_BUILTIN_VMSUMMBM,
2632 ALTIVEC_BUILTIN_VMSUMUHM,
2633 ALTIVEC_BUILTIN_VMSUMSHM,
2634 ALTIVEC_BUILTIN_VMSUMUHS,
2635 ALTIVEC_BUILTIN_VMSUMSHS,
2636 ALTIVEC_BUILTIN_VMINUB,
2637 ALTIVEC_BUILTIN_VMINSB,
2638 ALTIVEC_BUILTIN_VMINUH,
2639 ALTIVEC_BUILTIN_VMINSH,
2640 ALTIVEC_BUILTIN_VMINUW,
2641 ALTIVEC_BUILTIN_VMINSW,
2642 ALTIVEC_BUILTIN_VMINFP,
2643 ALTIVEC_BUILTIN_VMULEUB,
2644 ALTIVEC_BUILTIN_VMULESB,
2645 ALTIVEC_BUILTIN_VMULEUH,
2646 ALTIVEC_BUILTIN_VMULESH,
2647 ALTIVEC_BUILTIN_VMULOUB,
2648 ALTIVEC_BUILTIN_VMULOSB,
2649 ALTIVEC_BUILTIN_VMULOUH,
2650 ALTIVEC_BUILTIN_VMULOSH,
2651 ALTIVEC_BUILTIN_VNMSUBFP,
2652 ALTIVEC_BUILTIN_VNOR,
2653 ALTIVEC_BUILTIN_VOR,
2654 ALTIVEC_BUILTIN_VSEL_4SI,
2655 ALTIVEC_BUILTIN_VSEL_4SF,
2656 ALTIVEC_BUILTIN_VSEL_8HI,
2657 ALTIVEC_BUILTIN_VSEL_16QI,
2658 ALTIVEC_BUILTIN_VPERM_4SI,
2659 ALTIVEC_BUILTIN_VPERM_4SF,
2660 ALTIVEC_BUILTIN_VPERM_8HI,
2661 ALTIVEC_BUILTIN_VPERM_16QI,
2662 ALTIVEC_BUILTIN_VPKUHUM,
2663 ALTIVEC_BUILTIN_VPKUWUM,
2664 ALTIVEC_BUILTIN_VPKPX,
2665 ALTIVEC_BUILTIN_VPKUHSS,
2666 ALTIVEC_BUILTIN_VPKSHSS,
2667 ALTIVEC_BUILTIN_VPKUWSS,
2668 ALTIVEC_BUILTIN_VPKSWSS,
2669 ALTIVEC_BUILTIN_VPKUHUS,
2670 ALTIVEC_BUILTIN_VPKSHUS,
2671 ALTIVEC_BUILTIN_VPKUWUS,
2672 ALTIVEC_BUILTIN_VPKSWUS,
2673 ALTIVEC_BUILTIN_VREFP,
2674 ALTIVEC_BUILTIN_VRFIM,
2675 ALTIVEC_BUILTIN_VRFIN,
2676 ALTIVEC_BUILTIN_VRFIP,
2677 ALTIVEC_BUILTIN_VRFIZ,
2678 ALTIVEC_BUILTIN_VRLB,
2679 ALTIVEC_BUILTIN_VRLH,
2680 ALTIVEC_BUILTIN_VRLW,
2681 ALTIVEC_BUILTIN_VRSQRTEFP,
2682 ALTIVEC_BUILTIN_VSLB,
2683 ALTIVEC_BUILTIN_VSLH,
2684 ALTIVEC_BUILTIN_VSLW,
2685 ALTIVEC_BUILTIN_VSL,
2686 ALTIVEC_BUILTIN_VSLO,
2687 ALTIVEC_BUILTIN_VSPLTB,
2688 ALTIVEC_BUILTIN_VSPLTH,
2689 ALTIVEC_BUILTIN_VSPLTW,
2690 ALTIVEC_BUILTIN_VSPLTISB,
2691 ALTIVEC_BUILTIN_VSPLTISH,
2692 ALTIVEC_BUILTIN_VSPLTISW,
2693 ALTIVEC_BUILTIN_VSRB,
2694 ALTIVEC_BUILTIN_VSRH,
2695 ALTIVEC_BUILTIN_VSRW,
2696 ALTIVEC_BUILTIN_VSRAB,
2697 ALTIVEC_BUILTIN_VSRAH,
2698 ALTIVEC_BUILTIN_VSRAW,
2699 ALTIVEC_BUILTIN_VSR,
2700 ALTIVEC_BUILTIN_VSRO,
2701 ALTIVEC_BUILTIN_VSUBUBM,
2702 ALTIVEC_BUILTIN_VSUBUHM,
2703 ALTIVEC_BUILTIN_VSUBUWM,
2704 ALTIVEC_BUILTIN_VSUBFP,
2705 ALTIVEC_BUILTIN_VSUBCUW,
2706 ALTIVEC_BUILTIN_VSUBUBS,
2707 ALTIVEC_BUILTIN_VSUBSBS,
2708 ALTIVEC_BUILTIN_VSUBUHS,
2709 ALTIVEC_BUILTIN_VSUBSHS,
2710 ALTIVEC_BUILTIN_VSUBUWS,
2711 ALTIVEC_BUILTIN_VSUBSWS,
2712 ALTIVEC_BUILTIN_VSUM4UBS,
2713 ALTIVEC_BUILTIN_VSUM4SBS,
2714 ALTIVEC_BUILTIN_VSUM4SHS,
2715 ALTIVEC_BUILTIN_VSUM2SWS,
2716 ALTIVEC_BUILTIN_VSUMSWS,
2717 ALTIVEC_BUILTIN_VXOR,
2718 ALTIVEC_BUILTIN_VSLDOI_16QI,
2719 ALTIVEC_BUILTIN_VSLDOI_8HI,
2720 ALTIVEC_BUILTIN_VSLDOI_4SI,
2721 ALTIVEC_BUILTIN_VSLDOI_4SF,
2722 ALTIVEC_BUILTIN_VUPKHSB,
2723 ALTIVEC_BUILTIN_VUPKHPX,
2724 ALTIVEC_BUILTIN_VUPKHSH,
2725 ALTIVEC_BUILTIN_VUPKLSB,
2726 ALTIVEC_BUILTIN_VUPKLPX,
2727 ALTIVEC_BUILTIN_VUPKLSH,
2728 ALTIVEC_BUILTIN_MTVSCR,
2729 ALTIVEC_BUILTIN_MFVSCR,
2730 ALTIVEC_BUILTIN_DSSALL,
2731 ALTIVEC_BUILTIN_DSS,
2732 ALTIVEC_BUILTIN_LVSL,
2733 ALTIVEC_BUILTIN_LVSR,
2734 ALTIVEC_BUILTIN_DSTT,
2735 ALTIVEC_BUILTIN_DSTST,
2736 ALTIVEC_BUILTIN_DSTSTT,
2737 ALTIVEC_BUILTIN_DST,
2738 ALTIVEC_BUILTIN_LVEBX,
2739 ALTIVEC_BUILTIN_LVEHX,
2740 ALTIVEC_BUILTIN_LVEWX,
2741 ALTIVEC_BUILTIN_LVXL,
2742 ALTIVEC_BUILTIN_LVX,
2743 ALTIVEC_BUILTIN_STVX,
2744 ALTIVEC_BUILTIN_STVEBX,
2745 ALTIVEC_BUILTIN_STVEHX,
2746 ALTIVEC_BUILTIN_STVEWX,
2747 ALTIVEC_BUILTIN_STVXL,
2748 ALTIVEC_BUILTIN_VCMPBFP_P,
2749 ALTIVEC_BUILTIN_VCMPEQFP_P,
2750 ALTIVEC_BUILTIN_VCMPEQUB_P,
2751 ALTIVEC_BUILTIN_VCMPEQUH_P,
2752 ALTIVEC_BUILTIN_VCMPEQUW_P,
2753 ALTIVEC_BUILTIN_VCMPGEFP_P,
2754 ALTIVEC_BUILTIN_VCMPGTFP_P,
2755 ALTIVEC_BUILTIN_VCMPGTSB_P,
2756 ALTIVEC_BUILTIN_VCMPGTSH_P,
2757 ALTIVEC_BUILTIN_VCMPGTSW_P,
2758 ALTIVEC_BUILTIN_VCMPGTUB_P,
2759 ALTIVEC_BUILTIN_VCMPGTUH_P,
2760 ALTIVEC_BUILTIN_VCMPGTUW_P,
2761 ALTIVEC_BUILTIN_ABSS_V4SI,
2762 ALTIVEC_BUILTIN_ABSS_V8HI,
2763 ALTIVEC_BUILTIN_ABSS_V16QI,
2764 ALTIVEC_BUILTIN_ABS_V4SI,
2765 ALTIVEC_BUILTIN_ABS_V4SF,
2766 ALTIVEC_BUILTIN_ABS_V8HI,
2767 ALTIVEC_BUILTIN_ABS_V16QI,
2768 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
2769 ALTIVEC_BUILTIN_MASK_FOR_STORE,
2771 /* Altivec overloaded builtins. */
2772 ALTIVEC_BUILTIN_VCMPEQ_P,
2773 ALTIVEC_BUILTIN_OVERLOADED_FIRST = ALTIVEC_BUILTIN_VCMPEQ_P,
2774 ALTIVEC_BUILTIN_VCMPGT_P,
2775 ALTIVEC_BUILTIN_VCMPGE_P,
2776 ALTIVEC_BUILTIN_VEC_ABS,
2777 ALTIVEC_BUILTIN_VEC_ABSS,
2778 ALTIVEC_BUILTIN_VEC_ADD,
2779 ALTIVEC_BUILTIN_VEC_ADDC,
2780 ALTIVEC_BUILTIN_VEC_ADDS,
2781 ALTIVEC_BUILTIN_VEC_AND,
2782 ALTIVEC_BUILTIN_VEC_ANDC,
2783 ALTIVEC_BUILTIN_VEC_AVG,
2784 ALTIVEC_BUILTIN_VEC_CEIL,
2785 ALTIVEC_BUILTIN_VEC_CMPB,
2786 ALTIVEC_BUILTIN_VEC_CMPEQ,
2787 ALTIVEC_BUILTIN_VEC_CMPEQUB,
2788 ALTIVEC_BUILTIN_VEC_CMPEQUH,
2789 ALTIVEC_BUILTIN_VEC_CMPEQUW,
2790 ALTIVEC_BUILTIN_VEC_CMPGE,
2791 ALTIVEC_BUILTIN_VEC_CMPGT,
2792 ALTIVEC_BUILTIN_VEC_CMPLE,
2793 ALTIVEC_BUILTIN_VEC_CMPLT,
2794 ALTIVEC_BUILTIN_VEC_CTF,
2795 ALTIVEC_BUILTIN_VEC_CTS,
2796 ALTIVEC_BUILTIN_VEC_CTU,
2797 ALTIVEC_BUILTIN_VEC_DST,
2798 ALTIVEC_BUILTIN_VEC_DSTST,
2799 ALTIVEC_BUILTIN_VEC_DSTSTT,
2800 ALTIVEC_BUILTIN_VEC_DSTT,
2801 ALTIVEC_BUILTIN_VEC_EXPTE,
2802 ALTIVEC_BUILTIN_VEC_FLOOR,
2803 ALTIVEC_BUILTIN_VEC_LD,
2804 ALTIVEC_BUILTIN_VEC_LDE,
2805 ALTIVEC_BUILTIN_VEC_LDL,
2806 ALTIVEC_BUILTIN_VEC_LOGE,
2807 ALTIVEC_BUILTIN_VEC_LVEBX,
2808 ALTIVEC_BUILTIN_VEC_LVEHX,
2809 ALTIVEC_BUILTIN_VEC_LVEWX,
2810 ALTIVEC_BUILTIN_VEC_LVSL,
2811 ALTIVEC_BUILTIN_VEC_LVSR,
2812 ALTIVEC_BUILTIN_VEC_MADD,
2813 ALTIVEC_BUILTIN_VEC_MADDS,
2814 ALTIVEC_BUILTIN_VEC_MAX,
2815 ALTIVEC_BUILTIN_VEC_MERGEH,
2816 ALTIVEC_BUILTIN_VEC_MERGEL,
2817 ALTIVEC_BUILTIN_VEC_MIN,
2818 ALTIVEC_BUILTIN_VEC_MLADD,
2819 ALTIVEC_BUILTIN_VEC_MPERM,
2820 ALTIVEC_BUILTIN_VEC_MRADDS,
2821 ALTIVEC_BUILTIN_VEC_MRGHB,
2822 ALTIVEC_BUILTIN_VEC_MRGHH,
2823 ALTIVEC_BUILTIN_VEC_MRGHW,
2824 ALTIVEC_BUILTIN_VEC_MRGLB,
2825 ALTIVEC_BUILTIN_VEC_MRGLH,
2826 ALTIVEC_BUILTIN_VEC_MRGLW,
2827 ALTIVEC_BUILTIN_VEC_MSUM,
2828 ALTIVEC_BUILTIN_VEC_MSUMS,
2829 ALTIVEC_BUILTIN_VEC_MTVSCR,
2830 ALTIVEC_BUILTIN_VEC_MULE,
2831 ALTIVEC_BUILTIN_VEC_MULO,
2832 ALTIVEC_BUILTIN_VEC_NMSUB,
2833 ALTIVEC_BUILTIN_VEC_NOR,
2834 ALTIVEC_BUILTIN_VEC_OR,
2835 ALTIVEC_BUILTIN_VEC_PACK,
2836 ALTIVEC_BUILTIN_VEC_PACKPX,
2837 ALTIVEC_BUILTIN_VEC_PACKS,
2838 ALTIVEC_BUILTIN_VEC_PACKSU,
2839 ALTIVEC_BUILTIN_VEC_PERM,
2840 ALTIVEC_BUILTIN_VEC_RE,
2841 ALTIVEC_BUILTIN_VEC_RL,
2842 ALTIVEC_BUILTIN_VEC_ROUND,
2843 ALTIVEC_BUILTIN_VEC_RSQRTE,
2844 ALTIVEC_BUILTIN_VEC_SEL,
2845 ALTIVEC_BUILTIN_VEC_SL,
2846 ALTIVEC_BUILTIN_VEC_SLD,
2847 ALTIVEC_BUILTIN_VEC_SLL,
2848 ALTIVEC_BUILTIN_VEC_SLO,
2849 ALTIVEC_BUILTIN_VEC_SPLAT,
2850 ALTIVEC_BUILTIN_VEC_SPLAT_S16,
2851 ALTIVEC_BUILTIN_VEC_SPLAT_S32,
2852 ALTIVEC_BUILTIN_VEC_SPLAT_S8,
2853 ALTIVEC_BUILTIN_VEC_SPLAT_U16,
2854 ALTIVEC_BUILTIN_VEC_SPLAT_U32,
2855 ALTIVEC_BUILTIN_VEC_SPLAT_U8,
2856 ALTIVEC_BUILTIN_VEC_SPLTB,
2857 ALTIVEC_BUILTIN_VEC_SPLTH,
2858 ALTIVEC_BUILTIN_VEC_SPLTW,
2859 ALTIVEC_BUILTIN_VEC_SR,
2860 ALTIVEC_BUILTIN_VEC_SRA,
2861 ALTIVEC_BUILTIN_VEC_SRL,
2862 ALTIVEC_BUILTIN_VEC_SRO,
2863 ALTIVEC_BUILTIN_VEC_ST,
2864 ALTIVEC_BUILTIN_VEC_STE,
2865 ALTIVEC_BUILTIN_VEC_STL,
2866 ALTIVEC_BUILTIN_VEC_STVEBX,
2867 ALTIVEC_BUILTIN_VEC_STVEHX,
2868 ALTIVEC_BUILTIN_VEC_STVEWX,
2869 ALTIVEC_BUILTIN_VEC_SUB,
2870 ALTIVEC_BUILTIN_VEC_SUBC,
2871 ALTIVEC_BUILTIN_VEC_SUBS,
2872 ALTIVEC_BUILTIN_VEC_SUM2S,
2873 ALTIVEC_BUILTIN_VEC_SUM4S,
2874 ALTIVEC_BUILTIN_VEC_SUMS,
2875 ALTIVEC_BUILTIN_VEC_TRUNC,
2876 ALTIVEC_BUILTIN_VEC_UNPACKH,
2877 ALTIVEC_BUILTIN_VEC_UNPACKL,
2878 ALTIVEC_BUILTIN_VEC_VADDFP,
2879 ALTIVEC_BUILTIN_VEC_VADDSBS,
2880 ALTIVEC_BUILTIN_VEC_VADDSHS,
2881 ALTIVEC_BUILTIN_VEC_VADDSWS,
2882 ALTIVEC_BUILTIN_VEC_VADDUBM,
2883 ALTIVEC_BUILTIN_VEC_VADDUBS,
2884 ALTIVEC_BUILTIN_VEC_VADDUHM,
2885 ALTIVEC_BUILTIN_VEC_VADDUHS,
2886 ALTIVEC_BUILTIN_VEC_VADDUWM,
2887 ALTIVEC_BUILTIN_VEC_VADDUWS,
2888 ALTIVEC_BUILTIN_VEC_VAVGSB,
2889 ALTIVEC_BUILTIN_VEC_VAVGSH,
2890 ALTIVEC_BUILTIN_VEC_VAVGSW,
2891 ALTIVEC_BUILTIN_VEC_VAVGUB,
2892 ALTIVEC_BUILTIN_VEC_VAVGUH,
2893 ALTIVEC_BUILTIN_VEC_VAVGUW,
2894 ALTIVEC_BUILTIN_VEC_VCFSX,
2895 ALTIVEC_BUILTIN_VEC_VCFUX,
2896 ALTIVEC_BUILTIN_VEC_VCMPEQFP,
2897 ALTIVEC_BUILTIN_VEC_VCMPEQUB,
2898 ALTIVEC_BUILTIN_VEC_VCMPEQUH,
2899 ALTIVEC_BUILTIN_VEC_VCMPEQUW,
2900 ALTIVEC_BUILTIN_VEC_VCMPGTFP,
2901 ALTIVEC_BUILTIN_VEC_VCMPGTSB,
2902 ALTIVEC_BUILTIN_VEC_VCMPGTSH,
2903 ALTIVEC_BUILTIN_VEC_VCMPGTSW,
2904 ALTIVEC_BUILTIN_VEC_VCMPGTUB,
2905 ALTIVEC_BUILTIN_VEC_VCMPGTUH,
2906 ALTIVEC_BUILTIN_VEC_VCMPGTUW,
2907 ALTIVEC_BUILTIN_VEC_VMAXFP,
2908 ALTIVEC_BUILTIN_VEC_VMAXSB,
2909 ALTIVEC_BUILTIN_VEC_VMAXSH,
2910 ALTIVEC_BUILTIN_VEC_VMAXSW,
2911 ALTIVEC_BUILTIN_VEC_VMAXUB,
2912 ALTIVEC_BUILTIN_VEC_VMAXUH,
2913 ALTIVEC_BUILTIN_VEC_VMAXUW,
2914 ALTIVEC_BUILTIN_VEC_VMINFP,
2915 ALTIVEC_BUILTIN_VEC_VMINSB,
2916 ALTIVEC_BUILTIN_VEC_VMINSH,
2917 ALTIVEC_BUILTIN_VEC_VMINSW,
2918 ALTIVEC_BUILTIN_VEC_VMINUB,
2919 ALTIVEC_BUILTIN_VEC_VMINUH,
2920 ALTIVEC_BUILTIN_VEC_VMINUW,
2921 ALTIVEC_BUILTIN_VEC_VMRGHB,
2922 ALTIVEC_BUILTIN_VEC_VMRGHH,
2923 ALTIVEC_BUILTIN_VEC_VMRGHW,
2924 ALTIVEC_BUILTIN_VEC_VMRGLB,
2925 ALTIVEC_BUILTIN_VEC_VMRGLH,
2926 ALTIVEC_BUILTIN_VEC_VMRGLW,
2927 ALTIVEC_BUILTIN_VEC_VMSUMMBM,
2928 ALTIVEC_BUILTIN_VEC_VMSUMSHM,
2929 ALTIVEC_BUILTIN_VEC_VMSUMSHS,
2930 ALTIVEC_BUILTIN_VEC_VMSUMUBM,
2931 ALTIVEC_BUILTIN_VEC_VMSUMUHM,
2932 ALTIVEC_BUILTIN_VEC_VMSUMUHS,
2933 ALTIVEC_BUILTIN_VEC_VMULESB,
2934 ALTIVEC_BUILTIN_VEC_VMULESH,
2935 ALTIVEC_BUILTIN_VEC_VMULEUB,
2936 ALTIVEC_BUILTIN_VEC_VMULEUH,
2937 ALTIVEC_BUILTIN_VEC_VMULOSB,
2938 ALTIVEC_BUILTIN_VEC_VMULOSH,
2939 ALTIVEC_BUILTIN_VEC_VMULOUB,
2940 ALTIVEC_BUILTIN_VEC_VMULOUH,
2941 ALTIVEC_BUILTIN_VEC_VPKSHSS,
2942 ALTIVEC_BUILTIN_VEC_VPKSHUS,
2943 ALTIVEC_BUILTIN_VEC_VPKSWSS,
2944 ALTIVEC_BUILTIN_VEC_VPKSWUS,
2945 ALTIVEC_BUILTIN_VEC_VPKUHUM,
2946 ALTIVEC_BUILTIN_VEC_VPKUHUS,
2947 ALTIVEC_BUILTIN_VEC_VPKUWUM,
2948 ALTIVEC_BUILTIN_VEC_VPKUWUS,
2949 ALTIVEC_BUILTIN_VEC_VRLB,
2950 ALTIVEC_BUILTIN_VEC_VRLH,
2951 ALTIVEC_BUILTIN_VEC_VRLW,
2952 ALTIVEC_BUILTIN_VEC_VSLB,
2953 ALTIVEC_BUILTIN_VEC_VSLH,
2954 ALTIVEC_BUILTIN_VEC_VSLW,
2955 ALTIVEC_BUILTIN_VEC_VSPLTB,
2956 ALTIVEC_BUILTIN_VEC_VSPLTH,
2957 ALTIVEC_BUILTIN_VEC_VSPLTW,
2958 ALTIVEC_BUILTIN_VEC_VSRAB,
2959 ALTIVEC_BUILTIN_VEC_VSRAH,
2960 ALTIVEC_BUILTIN_VEC_VSRAW,
2961 ALTIVEC_BUILTIN_VEC_VSRB,
2962 ALTIVEC_BUILTIN_VEC_VSRH,
2963 ALTIVEC_BUILTIN_VEC_VSRW,
2964 ALTIVEC_BUILTIN_VEC_VSUBFP,
2965 ALTIVEC_BUILTIN_VEC_VSUBSBS,
2966 ALTIVEC_BUILTIN_VEC_VSUBSHS,
2967 ALTIVEC_BUILTIN_VEC_VSUBSWS,
2968 ALTIVEC_BUILTIN_VEC_VSUBUBM,
2969 ALTIVEC_BUILTIN_VEC_VSUBUBS,
2970 ALTIVEC_BUILTIN_VEC_VSUBUHM,
2971 ALTIVEC_BUILTIN_VEC_VSUBUHS,
2972 ALTIVEC_BUILTIN_VEC_VSUBUWM,
2973 ALTIVEC_BUILTIN_VEC_VSUBUWS,
2974 ALTIVEC_BUILTIN_VEC_VSUM4SBS,
2975 ALTIVEC_BUILTIN_VEC_VSUM4SHS,
2976 ALTIVEC_BUILTIN_VEC_VSUM4UBS,
2977 ALTIVEC_BUILTIN_VEC_VUPKHPX,
2978 ALTIVEC_BUILTIN_VEC_VUPKHSB,
2979 ALTIVEC_BUILTIN_VEC_VUPKHSH,
2980 ALTIVEC_BUILTIN_VEC_VUPKLPX,
2981 ALTIVEC_BUILTIN_VEC_VUPKLSB,
2982 ALTIVEC_BUILTIN_VEC_VUPKLSH,
2983 ALTIVEC_BUILTIN_VEC_XOR,
2984 ALTIVEC_BUILTIN_VEC_STEP,
2985 ALTIVEC_BUILTIN_OVERLOADED_LAST = ALTIVEC_BUILTIN_VEC_STEP,
2991 SPE_BUILTIN_EVDIVWS,
2992 SPE_BUILTIN_EVDIVWU,
2994 SPE_BUILTIN_EVFSADD,
2995 SPE_BUILTIN_EVFSDIV,
2996 SPE_BUILTIN_EVFSMUL,
2997 SPE_BUILTIN_EVFSSUB,
3001 SPE_BUILTIN_EVLHHESPLATX,
3002 SPE_BUILTIN_EVLHHOSSPLATX,
3003 SPE_BUILTIN_EVLHHOUSPLATX,
3004 SPE_BUILTIN_EVLWHEX,
3005 SPE_BUILTIN_EVLWHOSX,
3006 SPE_BUILTIN_EVLWHOUX,
3007 SPE_BUILTIN_EVLWHSPLATX,
3008 SPE_BUILTIN_EVLWWSPLATX,
3009 SPE_BUILTIN_EVMERGEHI,
3010 SPE_BUILTIN_EVMERGEHILO,
3011 SPE_BUILTIN_EVMERGELO,
3012 SPE_BUILTIN_EVMERGELOHI,
3013 SPE_BUILTIN_EVMHEGSMFAA,
3014 SPE_BUILTIN_EVMHEGSMFAN,
3015 SPE_BUILTIN_EVMHEGSMIAA,
3016 SPE_BUILTIN_EVMHEGSMIAN,
3017 SPE_BUILTIN_EVMHEGUMIAA,
3018 SPE_BUILTIN_EVMHEGUMIAN,
3019 SPE_BUILTIN_EVMHESMF,
3020 SPE_BUILTIN_EVMHESMFA,
3021 SPE_BUILTIN_EVMHESMFAAW,
3022 SPE_BUILTIN_EVMHESMFANW,
3023 SPE_BUILTIN_EVMHESMI,
3024 SPE_BUILTIN_EVMHESMIA,
3025 SPE_BUILTIN_EVMHESMIAAW,
3026 SPE_BUILTIN_EVMHESMIANW,
3027 SPE_BUILTIN_EVMHESSF,
3028 SPE_BUILTIN_EVMHESSFA,
3029 SPE_BUILTIN_EVMHESSFAAW,
3030 SPE_BUILTIN_EVMHESSFANW,
3031 SPE_BUILTIN_EVMHESSIAAW,
3032 SPE_BUILTIN_EVMHESSIANW,
3033 SPE_BUILTIN_EVMHEUMI,
3034 SPE_BUILTIN_EVMHEUMIA,
3035 SPE_BUILTIN_EVMHEUMIAAW,
3036 SPE_BUILTIN_EVMHEUMIANW,
3037 SPE_BUILTIN_EVMHEUSIAAW,
3038 SPE_BUILTIN_EVMHEUSIANW,
3039 SPE_BUILTIN_EVMHOGSMFAA,
3040 SPE_BUILTIN_EVMHOGSMFAN,
3041 SPE_BUILTIN_EVMHOGSMIAA,
3042 SPE_BUILTIN_EVMHOGSMIAN,
3043 SPE_BUILTIN_EVMHOGUMIAA,
3044 SPE_BUILTIN_EVMHOGUMIAN,
3045 SPE_BUILTIN_EVMHOSMF,
3046 SPE_BUILTIN_EVMHOSMFA,
3047 SPE_BUILTIN_EVMHOSMFAAW,
3048 SPE_BUILTIN_EVMHOSMFANW,
3049 SPE_BUILTIN_EVMHOSMI,
3050 SPE_BUILTIN_EVMHOSMIA,
3051 SPE_BUILTIN_EVMHOSMIAAW,
3052 SPE_BUILTIN_EVMHOSMIANW,
3053 SPE_BUILTIN_EVMHOSSF,
3054 SPE_BUILTIN_EVMHOSSFA,
3055 SPE_BUILTIN_EVMHOSSFAAW,
3056 SPE_BUILTIN_EVMHOSSFANW,
3057 SPE_BUILTIN_EVMHOSSIAAW,
3058 SPE_BUILTIN_EVMHOSSIANW,
3059 SPE_BUILTIN_EVMHOUMI,
3060 SPE_BUILTIN_EVMHOUMIA,
3061 SPE_BUILTIN_EVMHOUMIAAW,
3062 SPE_BUILTIN_EVMHOUMIANW,
3063 SPE_BUILTIN_EVMHOUSIAAW,
3064 SPE_BUILTIN_EVMHOUSIANW,
3065 SPE_BUILTIN_EVMWHSMF,
3066 SPE_BUILTIN_EVMWHSMFA,
3067 SPE_BUILTIN_EVMWHSMI,
3068 SPE_BUILTIN_EVMWHSMIA,
3069 SPE_BUILTIN_EVMWHSSF,
3070 SPE_BUILTIN_EVMWHSSFA,
3071 SPE_BUILTIN_EVMWHUMI,
3072 SPE_BUILTIN_EVMWHUMIA,
3073 SPE_BUILTIN_EVMWLSMIAAW,
3074 SPE_BUILTIN_EVMWLSMIANW,
3075 SPE_BUILTIN_EVMWLSSIAAW,
3076 SPE_BUILTIN_EVMWLSSIANW,
3077 SPE_BUILTIN_EVMWLUMI,
3078 SPE_BUILTIN_EVMWLUMIA,
3079 SPE_BUILTIN_EVMWLUMIAAW,
3080 SPE_BUILTIN_EVMWLUMIANW,
3081 SPE_BUILTIN_EVMWLUSIAAW,
3082 SPE_BUILTIN_EVMWLUSIANW,
3083 SPE_BUILTIN_EVMWSMF,
3084 SPE_BUILTIN_EVMWSMFA,
3085 SPE_BUILTIN_EVMWSMFAA,
3086 SPE_BUILTIN_EVMWSMFAN,
3087 SPE_BUILTIN_EVMWSMI,
3088 SPE_BUILTIN_EVMWSMIA,
3089 SPE_BUILTIN_EVMWSMIAA,
3090 SPE_BUILTIN_EVMWSMIAN,
3091 SPE_BUILTIN_EVMWHSSFAA,
3092 SPE_BUILTIN_EVMWSSF,
3093 SPE_BUILTIN_EVMWSSFA,
3094 SPE_BUILTIN_EVMWSSFAA,
3095 SPE_BUILTIN_EVMWSSFAN,
3096 SPE_BUILTIN_EVMWUMI,
3097 SPE_BUILTIN_EVMWUMIA,
3098 SPE_BUILTIN_EVMWUMIAA,
3099 SPE_BUILTIN_EVMWUMIAN,
3108 SPE_BUILTIN_EVSTDDX,
3109 SPE_BUILTIN_EVSTDHX,
3110 SPE_BUILTIN_EVSTDWX,
3111 SPE_BUILTIN_EVSTWHEX,
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