1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 Under Section 7 of GPL version 3, you are granted additional
20 permissions described in the GCC Runtime Library Exception, version
21 3.1, as published by the Free Software Foundation.
23 You should have received a copy of the GNU General Public License and
24 a copy of the GCC Runtime Library Exception along with this program;
25 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
26 <http://www.gnu.org/licenses/>. */
28 /* Note that some other tm.h files include this one and then override
29 many of the definitions. */
31 /* Definitions for the object file format. These are set at
34 #define OBJECT_XCOFF 1
37 #define OBJECT_MACHO 4
39 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
40 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
41 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
42 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
48 /* Control whether function entry points use a "dot" symbol when
52 /* Default string to use for cpu if not specified. */
53 #ifndef TARGET_CPU_DEFAULT
54 #define TARGET_CPU_DEFAULT ((char *)0)
57 /* If configured for PPC405, support PPC405CR Erratum77. */
58 #ifdef CONFIG_PPC405CR
59 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
61 #define PPC405_ERRATUM77 0
64 #ifndef TARGET_PAIRED_FLOAT
65 #define TARGET_PAIRED_FLOAT 0
68 #ifdef HAVE_AS_POPCNTB
69 #define ASM_CPU_POWER5_SPEC "-mpower5"
71 #define ASM_CPU_POWER5_SPEC "-mpower4"
75 #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec"
77 #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec"
80 #ifdef HAVE_AS_POPCNTD
81 #define ASM_CPU_POWER7_SPEC "-mpower7"
83 #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec"
87 #define ASM_CPU_476_SPEC "-m476"
89 #define ASM_CPU_476_SPEC "-mpower4"
92 /* Common ASM definitions used by ASM_SPEC among the various targets for
93 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
94 provide the default assembler options if the user uses -mcpu=native, so if
95 you make changes here, make them also there. */
96 #define ASM_CPU_SPEC \
98 %{mpower: %{!mpower2: -mpwr}} \
100 %{mpowerpc64*: -mppc64} \
101 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
102 %{mno-power: %{!mpowerpc*: -mcom}} \
103 %{!mno-power: %{!mpower*: %(asm_default)}}} \
104 %{mcpu=native: %(asm_cpu_native)} \
105 %{mcpu=common: -mcom} \
106 %{mcpu=cell: -mcell} \
107 %{mcpu=power: -mpwr} \
108 %{mcpu=power2: -mpwrx} \
109 %{mcpu=power3: -mppc64} \
110 %{mcpu=power4: -mpower4} \
111 %{mcpu=power5: %(asm_cpu_power5)} \
112 %{mcpu=power5+: %(asm_cpu_power5)} \
113 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \
114 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
115 %{mcpu=power7: %(asm_cpu_power7)} \
117 %{mcpu=powerpc: -mppc} \
118 %{mcpu=rios: -mpwr} \
119 %{mcpu=rios1: -mpwr} \
120 %{mcpu=rios2: -mpwrx} \
122 %{mcpu=rsc1: -mpwr} \
123 %{mcpu=rs64a: -mppc64} \
127 %{mcpu=405fp: -m405} \
129 %{mcpu=440fp: -m440} \
131 %{mcpu=464fp: -m440} \
132 %{mcpu=476: %(asm_cpu_476)} \
133 %{mcpu=476fp: %(asm_cpu_476)} \
138 %{mcpu=603e: -mppc} \
139 %{mcpu=ec603e: -mppc} \
141 %{mcpu=604e: -mppc} \
142 %{mcpu=620: -mppc64} \
143 %{mcpu=630: -mppc64} \
147 %{mcpu=7400: -mppc -maltivec} \
148 %{mcpu=7450: -mppc -maltivec} \
149 %{mcpu=G4: -mppc -maltivec} \
154 %{mcpu=970: -mpower4 -maltivec} \
155 %{mcpu=G5: -mpower4 -maltivec} \
156 %{mcpu=8540: -me500} \
157 %{mcpu=8548: -me500} \
158 %{mcpu=e300c2: -me300} \
159 %{mcpu=e300c3: -me300} \
160 %{mcpu=e500mc: -me500mc} \
161 %{mcpu=e500mc64: -me500mc64} \
162 %{maltivec: -maltivec} \
165 #define CPP_DEFAULT_SPEC ""
167 #define ASM_DEFAULT_SPEC ""
169 /* This macro defines names of additional specifications to put in the specs
170 that can be used in various specifications like CC1_SPEC. Its definition
171 is an initializer with a subgrouping for each command option.
173 Each subgrouping contains a string constant, that defines the
174 specification name, and a string constant that used by the GCC driver
177 Do not define this macro if it does not need to do anything. */
179 #define SUBTARGET_EXTRA_SPECS
181 #define EXTRA_SPECS \
182 { "cpp_default", CPP_DEFAULT_SPEC }, \
183 { "asm_cpu", ASM_CPU_SPEC }, \
184 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \
185 { "asm_default", ASM_DEFAULT_SPEC }, \
186 { "cc1_cpu", CC1_CPU_SPEC }, \
187 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
188 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
189 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \
190 { "asm_cpu_476", ASM_CPU_476_SPEC }, \
191 SUBTARGET_EXTRA_SPECS
193 /* -mcpu=native handling only makes sense with compiler running on
194 an PowerPC chip. If changing this condition, also change
195 the condition in driver-rs6000.c. */
196 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
197 /* In driver-rs6000.c. */
198 extern const char *host_detect_local_cpu (int argc, const char **argv);
199 #define EXTRA_SPEC_FUNCTIONS \
200 { "local_cpu_detect", host_detect_local_cpu },
201 #define HAVE_LOCAL_CPU_DETECT
202 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)"
205 #define ASM_CPU_NATIVE_SPEC "%(asm_default)"
209 #ifdef HAVE_LOCAL_CPU_DETECT
210 #define CC1_CPU_SPEC \
211 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
212 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
214 #define CC1_CPU_SPEC ""
218 /* Architecture type. */
220 /* Define TARGET_MFCRF if the target assembler does not support the
221 optional field operand for mfcr. */
223 #ifndef HAVE_AS_MFCRF
225 #define TARGET_MFCRF 0
228 /* Define TARGET_POPCNTB if the target assembler does not support the
229 popcount byte instruction. */
231 #ifndef HAVE_AS_POPCNTB
232 #undef TARGET_POPCNTB
233 #define TARGET_POPCNTB 0
236 /* Define TARGET_FPRND if the target assembler does not support the
237 fp rounding instructions. */
239 #ifndef HAVE_AS_FPRND
241 #define TARGET_FPRND 0
244 /* Define TARGET_CMPB if the target assembler does not support the
249 #define TARGET_CMPB 0
252 /* Define TARGET_MFPGPR if the target assembler does not support the
253 mffpr and mftgpr instructions. */
255 #ifndef HAVE_AS_MFPGPR
257 #define TARGET_MFPGPR 0
260 /* Define TARGET_DFP if the target assembler does not support decimal
261 floating point instructions. */
267 /* Define TARGET_POPCNTD if the target assembler does not support the
268 popcount word and double word instructions. */
270 #ifndef HAVE_AS_POPCNTD
271 #undef TARGET_POPCNTD
272 #define TARGET_POPCNTD 0
275 /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If
276 not, generate the lwsync code as an integer constant. */
277 #ifdef HAVE_AS_LWSYNC
278 #define TARGET_LWSYNC_INSTRUCTION 1
280 #define TARGET_LWSYNC_INSTRUCTION 0
283 /* Define TARGET_TLS_MARKERS if the target assembler does not support
284 arg markers for __tls_get_addr calls. */
285 #ifndef HAVE_AS_TLS_MARKERS
286 #undef TARGET_TLS_MARKERS
287 #define TARGET_TLS_MARKERS 0
289 #define TARGET_TLS_MARKERS tls_markers
292 #ifndef TARGET_SECURE_PLT
293 #define TARGET_SECURE_PLT 0
296 #define TARGET_32BIT (! TARGET_64BIT)
299 #define HAVE_AS_TLS 0
302 /* Return 1 for a symbol ref for a thread-local storage symbol. */
303 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
304 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
307 /* For libgcc2 we make sure this is a compile time constant */
308 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
309 #undef TARGET_POWERPC64
310 #define TARGET_POWERPC64 1
312 #undef TARGET_POWERPC64
313 #define TARGET_POWERPC64 0
316 /* The option machinery will define this. */
319 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
321 /* Processor type. Order must match cpu attribute in MD file. */
345 PROCESSOR_PPCE500MC64,
354 /* FPU operations supported.
355 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
356 also test TARGET_HARD_FLOAT. */
357 #define TARGET_SINGLE_FLOAT 1
358 #define TARGET_DOUBLE_FLOAT 1
359 #define TARGET_SINGLE_FPU 0
360 #define TARGET_SIMPLE_FPU 0
361 #define TARGET_XILINX_FPU 0
363 extern enum processor_type rs6000_cpu;
365 /* Recast the processor type to the cpu attribute. */
366 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
368 /* Define generic processor types based upon current deployment. */
369 #define PROCESSOR_COMMON PROCESSOR_PPC601
370 #define PROCESSOR_POWER PROCESSOR_RIOS1
371 #define PROCESSOR_POWERPC PROCESSOR_PPC604
372 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
374 /* Define the default processor. This is overridden by other tm.h files. */
375 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
376 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
378 /* FP processor type. */
381 FPU_NONE, /* No FPU */
382 FPU_SF_LITE, /* Limited Single Precision FPU */
383 FPU_DF_LITE, /* Limited Double Precision FPU */
384 FPU_SF_FULL, /* Full Single Precision FPU */
385 FPU_DF_FULL /* Full Double Single Precision FPU */
388 extern enum fpu_type_t fpu_type;
390 /* Specify the dialect of assembler to use. New mnemonics is dialect one
391 and the old mnemonics are dialect zero. */
392 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
394 /* Types of costly dependences. */
395 enum rs6000_dependence_cost
397 max_dep_latency = 1000,
400 true_store_to_load_dep_costly,
401 store_to_load_dep_costly
404 /* Types of nop insertion schemes in sched target hook sched_finish. */
405 enum rs6000_nop_insertion
407 sched_finish_regroup_exact = 1000,
408 sched_finish_pad_groups,
412 /* Dispatch group termination caused by an insn. */
413 enum group_termination
419 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
420 struct rs6000_cpu_select
428 extern struct rs6000_cpu_select rs6000_select[];
431 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
432 extern int rs6000_debug_stack; /* debug stack applications */
433 extern int rs6000_debug_arg; /* debug argument handling */
434 extern int rs6000_debug_reg; /* debug register handling */
435 extern int rs6000_debug_addr; /* debug memory addressing */
436 extern int rs6000_debug_cost; /* debug rtx_costs */
438 #define TARGET_DEBUG_STACK rs6000_debug_stack
439 #define TARGET_DEBUG_ARG rs6000_debug_arg
440 #define TARGET_DEBUG_REG rs6000_debug_reg
441 #define TARGET_DEBUG_ADDR rs6000_debug_addr
442 #define TARGET_DEBUG_COST rs6000_debug_cost
444 extern const char *rs6000_traceback_name; /* Type of traceback table. */
446 /* These are separate from target_flags because we've run out of bits
448 extern int rs6000_long_double_type_size;
449 extern int rs6000_ieeequad;
450 extern int rs6000_altivec_abi;
451 extern int rs6000_spe_abi;
452 extern int rs6000_spe;
453 extern int rs6000_float_gprs;
454 extern int rs6000_alignment_flags;
455 extern const char *rs6000_sched_insert_nops_str;
456 extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
457 extern int rs6000_xilinx_fpu;
459 /* Describe which vector unit to use for a given machine mode. */
461 VECTOR_NONE, /* Type is not a vector or not supported */
462 VECTOR_ALTIVEC, /* Use altivec for vector processing */
463 VECTOR_VSX, /* Use VSX for vector processing */
464 VECTOR_PAIRED, /* Use paired floating point for vectors */
465 VECTOR_SPE, /* Use SPE for vector processing */
466 VECTOR_OTHER /* Some other vector unit */
469 extern enum rs6000_vector rs6000_vector_unit[];
471 #define VECTOR_UNIT_NONE_P(MODE) \
472 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
474 #define VECTOR_UNIT_VSX_P(MODE) \
475 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
477 #define VECTOR_UNIT_ALTIVEC_P(MODE) \
478 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
480 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
481 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC \
482 || rs6000_vector_unit[(MODE)] == VECTOR_VSX)
484 /* Describe whether to use VSX loads or Altivec loads. For now, just use the
485 same unit as the vector unit we are using, but we may want to migrate to
486 using VSX style loads even for types handled by altivec. */
487 extern enum rs6000_vector rs6000_vector_mem[];
489 #define VECTOR_MEM_NONE_P(MODE) \
490 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
492 #define VECTOR_MEM_VSX_P(MODE) \
493 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
495 #define VECTOR_MEM_ALTIVEC_P(MODE) \
496 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
498 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
499 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC \
500 || rs6000_vector_mem[(MODE)] == VECTOR_VSX)
502 /* Return the alignment of a given vector type, which is set based on the
503 vector unit use. VSX for instance can load 32 or 64 bit aligned words
504 without problems, while Altivec requires 128-bit aligned vectors. */
505 extern int rs6000_vector_align[];
507 #define VECTOR_ALIGN(MODE) \
508 ((rs6000_vector_align[(MODE)] != 0) \
509 ? rs6000_vector_align[(MODE)] \
510 : (int)GET_MODE_BITSIZE ((MODE)))
512 /* Alignment options for fields in structures for sub-targets following
514 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
515 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
517 Override the macro definitions when compiling libobjc to avoid undefined
518 reference to rs6000_alignment_flags due to library's use of GCC alignment
519 macros which use the macros below. */
521 #ifndef IN_TARGET_LIBS
522 #define MASK_ALIGN_POWER 0x00000000
523 #define MASK_ALIGN_NATURAL 0x00000001
524 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
526 #define TARGET_ALIGN_NATURAL 0
529 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
530 #define TARGET_IEEEQUAD rs6000_ieeequad
531 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
532 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
534 #define TARGET_SPE_ABI 0
536 #define TARGET_E500 0
537 #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
538 #define TARGET_FPRS 1
539 #define TARGET_E500_SINGLE 0
540 #define TARGET_E500_DOUBLE 0
541 #define CHECK_E500_OPTIONS do { } while (0)
543 /* E500 processors only support plain "sync", not lwsync. */
544 #define TARGET_NO_LWSYNC TARGET_E500
546 /* Which machine supports the various reciprocal estimate instructions. */
547 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
548 && TARGET_FPRS && TARGET_SINGLE_FLOAT)
550 #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \
551 && TARGET_DOUBLE_FLOAT \
552 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
554 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
555 && TARGET_FPRS && TARGET_SINGLE_FLOAT)
557 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \
558 && TARGET_DOUBLE_FLOAT \
559 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
561 /* Whether the various reciprocal divide/square root estimate instructions
562 exist, and whether we should automatically generate code for the instruction
564 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */
565 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */
566 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */
567 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */
569 extern unsigned char rs6000_recip_bits[];
571 #define RS6000_RECIP_HAVE_RE_P(MODE) \
572 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE)
574 #define RS6000_RECIP_AUTO_RE_P(MODE) \
575 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE)
577 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \
578 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE)
580 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
581 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
583 #define RS6000_RECIP_HIGH_PRECISION_P(MODE) \
584 ((MODE) == SFmode || (MODE) == V4SFmode || TARGET_RECIP_PRECISION)
586 /* Sometimes certain combinations of command options do not make sense
587 on a particular target machine. You can define a macro
588 `OVERRIDE_OPTIONS' to take account of this. This macro, if
589 defined, is executed once just after all the command options have
592 Do not use this macro to turn on various extra optimizations for
593 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
595 On the RS/6000 this is used to define the target cpu type. */
597 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
599 /* Define this to change the optimizations performed by default. */
600 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
602 /* Show we can debug even without a frame pointer. */
603 #define CAN_DEBUG_WITHOUT_FP
606 #define REGISTER_TARGET_PRAGMAS() do { \
607 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
608 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
611 /* Target #defines. */
612 #define TARGET_CPU_CPP_BUILTINS() \
613 rs6000_cpu_cpp_builtins (pfile)
615 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
616 we're compiling for. Some configurations may need to override it. */
617 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
620 if (BYTES_BIG_ENDIAN) \
622 builtin_define ("__BIG_ENDIAN__"); \
623 builtin_define ("_BIG_ENDIAN"); \
624 builtin_assert ("machine=bigendian"); \
628 builtin_define ("__LITTLE_ENDIAN__"); \
629 builtin_define ("_LITTLE_ENDIAN"); \
630 builtin_assert ("machine=littleendian"); \
635 /* Target machine storage layout. */
637 /* Define this macro if it is advisable to hold scalars in registers
638 in a wider mode than that declared by the program. In such cases,
639 the value is constrained to be within the bounds of the declared
640 type, but kept valid in the wider mode. The signedness of the
641 extension may differ from that of the type. */
643 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
644 if (GET_MODE_CLASS (MODE) == MODE_INT \
645 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
646 (MODE) = TARGET_32BIT ? SImode : DImode;
648 /* Define this if most significant bit is lowest numbered
649 in instructions that operate on numbered bit-fields. */
650 /* That is true on RS/6000. */
651 #define BITS_BIG_ENDIAN 1
653 /* Define this if most significant byte of a word is the lowest numbered. */
654 /* That is true on RS/6000. */
655 #define BYTES_BIG_ENDIAN 1
657 /* Define this if most significant word of a multiword number is lowest
660 For RS/6000 we can decide arbitrarily since there are no machine
661 instructions for them. Might as well be consistent with bits and bytes. */
662 #define WORDS_BIG_ENDIAN 1
664 #define MAX_BITS_PER_WORD 64
666 /* Width of a word, in units (bytes). */
667 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
669 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
671 #define MIN_UNITS_PER_WORD 4
673 #define UNITS_PER_FP_WORD 8
674 #define UNITS_PER_ALTIVEC_WORD 16
675 #define UNITS_PER_VSX_WORD 16
676 #define UNITS_PER_SPE_WORD 8
677 #define UNITS_PER_PAIRED_WORD 8
679 /* Type used for ptrdiff_t, as a string used in a declaration. */
680 #define PTRDIFF_TYPE "int"
682 /* Type used for size_t, as a string used in a declaration. */
683 #define SIZE_TYPE "long unsigned int"
685 /* Type used for wchar_t, as a string used in a declaration. */
686 #define WCHAR_TYPE "short unsigned int"
688 /* Width of wchar_t in bits. */
689 #define WCHAR_TYPE_SIZE 16
691 /* A C expression for the size in bits of the type `short' on the
692 target machine. If you don't define this, the default is half a
693 word. (If this would be less than one storage unit, it is
694 rounded up to one unit.) */
695 #define SHORT_TYPE_SIZE 16
697 /* A C expression for the size in bits of the type `int' on the
698 target machine. If you don't define this, the default is one
700 #define INT_TYPE_SIZE 32
702 /* A C expression for the size in bits of the type `long' on the
703 target machine. If you don't define this, the default is one
705 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
707 /* A C expression for the size in bits of the type `long long' on the
708 target machine. If you don't define this, the default is two
710 #define LONG_LONG_TYPE_SIZE 64
712 /* A C expression for the size in bits of the type `float' on the
713 target machine. If you don't define this, the default is one
715 #define FLOAT_TYPE_SIZE 32
717 /* A C expression for the size in bits of the type `double' on the
718 target machine. If you don't define this, the default is two
720 #define DOUBLE_TYPE_SIZE 64
722 /* A C expression for the size in bits of the type `long double' on
723 the target machine. If you don't define this, the default is two
725 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
727 /* Define this to set long double type size to use in libgcc2.c, which can
728 not depend on target_flags. */
729 #ifdef __LONG_DOUBLE_128__
730 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
732 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
735 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
736 #define WIDEST_HARDWARE_FP_SIZE 64
738 /* Width in bits of a pointer.
739 See also the macro `Pmode' defined below. */
740 extern unsigned rs6000_pointer_size;
741 #define POINTER_SIZE rs6000_pointer_size
743 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
744 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
746 /* Boundary (in *bits*) on which stack pointer should be aligned. */
747 #define STACK_BOUNDARY \
748 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
751 /* Allocation boundary (in *bits*) for the code of a function. */
752 #define FUNCTION_BOUNDARY 32
754 /* No data type wants to be aligned rounder than this. */
755 #define BIGGEST_ALIGNMENT 128
757 /* A C expression to compute the alignment for a variables in the
758 local store. TYPE is the data type, and ALIGN is the alignment
759 that the object would ordinarily have. */
760 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
761 DATA_ALIGNMENT (TYPE, ALIGN)
763 /* Alignment of field after `int : 0' in a structure. */
764 #define EMPTY_FIELD_BOUNDARY 32
766 /* Every structure's size must be a multiple of this. */
767 #define STRUCTURE_SIZE_BOUNDARY 8
769 /* Return 1 if a structure or array containing FIELD should be
770 accessed using `BLKMODE'.
772 For the SPE, simd types are V2SI, and gcc can be tempted to put the
773 entire thing in a DI and use subregs to access the internals.
774 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
775 back-end. Because a single GPR can hold a V2SI, but not a DI, the
776 best thing to do is set structs to BLKmode and avoid Severe Tire
779 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
780 fit into 1, whereas DI still needs two. */
781 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
782 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
783 || (TARGET_E500_DOUBLE && (MODE) == DFmode))
785 /* A bit-field declared as `int' forces `int' alignment for the struct. */
786 #define PCC_BITFIELD_TYPE_MATTERS 1
788 /* Make strings word-aligned so strcpy from constants will be faster.
789 Make vector constants quadword aligned. */
790 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
791 (TREE_CODE (EXP) == STRING_CST \
792 && (STRICT_ALIGNMENT || !optimize_size) \
793 && (ALIGN) < BITS_PER_WORD \
797 /* Make arrays of chars word-aligned for the same reasons.
798 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
800 #define DATA_ALIGNMENT(TYPE, ALIGN) \
801 (TREE_CODE (TYPE) == VECTOR_TYPE \
802 ? (((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) \
803 || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) \
805 : ((TARGET_E500_DOUBLE \
806 && TREE_CODE (TYPE) == REAL_TYPE \
807 && TYPE_MODE (TYPE) == DFmode) \
809 : (TREE_CODE (TYPE) == ARRAY_TYPE \
810 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
811 && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN)))
813 /* Nonzero if move instructions will actually fail to work
814 when given unaligned data. */
815 #define STRICT_ALIGNMENT 0
817 /* Define this macro to be the value 1 if unaligned accesses have a cost
818 many times greater than aligned accesses, for example if they are
819 emulated in a trap handler. */
820 /* Altivec vector memory instructions simply ignore the low bits; SPE vector
821 memory instructions trap on unaligned accesses; VSX memory instructions are
822 aligned to 4 or 8 bytes. */
823 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
825 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
826 || (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode \
827 || (MODE) == DImode) \
829 || (VECTOR_MODE_P ((MODE)) && (((int)(ALIGN)) < VECTOR_ALIGN (MODE))))
832 /* Standard register usage. */
834 /* Number of actual hardware registers.
835 The hardware registers are assigned numbers for the compiler
836 from 0 to just below FIRST_PSEUDO_REGISTER.
837 All registers that the compiler knows about must be given numbers,
838 even those that are not normally considered general registers.
840 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
841 an MQ register, a count register, a link register, and 8 condition
842 register fields, which we view here as separate registers. AltiVec
843 adds 32 vector registers and a VRsave register.
845 In addition, the difference between the frame and argument pointers is
846 a function of the number of registers saved, so we need to have a
847 register for AP that will later be eliminated in favor of SP or FP.
848 This is a normal register, but it is fixed.
850 We also create a pseudo register for float/int conversions, that will
851 really represent the memory location used. It is represented here as
852 a register, in order to work around problems in allocating stack storage
855 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
856 pointer, which is eventually eliminated in favor of SP or FP. */
858 #define FIRST_PSEUDO_REGISTER 114
860 /* This must be included for pre gcc 3.0 glibc compatibility. */
861 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
863 /* Add 32 dwarf columns for synthetic SPE registers. */
864 #define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)
866 /* The SPE has an additional 32 synthetic registers, with DWARF debug
867 info numbering for these registers starting at 1200. While eh_frame
868 register numbering need not be the same as the debug info numbering,
869 we choose to number these regs for eh_frame at 1200 too. This allows
870 future versions of the rs6000 backend to add hard registers and
871 continue to use the gcc hard register numbering for eh_frame. If the
872 extra SPE registers in eh_frame were numbered starting from the
873 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
874 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
875 avoid invalidating older SPE eh_frame info.
877 We must map them here to avoid huge unwinder tables mostly consisting
879 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
880 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
882 /* Use standard DWARF numbering for DWARF debugging information. */
883 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
885 /* Use gcc hard register numbering for eh_frame. */
886 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
888 /* Map register numbers held in the call frame info that gcc has
889 collected using DWARF_FRAME_REGNUM to those that should be output in
890 .debug_frame and .eh_frame. We continue to use gcc hard reg numbers
891 for .eh_frame, but use the numbers mandated by the various ABIs for
892 .debug_frame. rs6000_emit_prologue has translated any combination of
893 CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves
894 the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */
895 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
896 ((FOR_EH) ? (REGNO) \
897 : (REGNO) == CR2_REGNO ? 64 \
898 : DBX_REGISTER_NUMBER (REGNO))
900 /* 1 for registers that have pervasive standard uses
901 and are not available for the register allocator.
903 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
904 as a local register; for all other OS's r2 is the TOC pointer.
906 cr5 is not supposed to be used.
908 On System V implementations, r13 is fixed and not available for use. */
910 #define FIXED_REGISTERS \
911 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
912 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
913 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
914 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
915 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
916 /* AltiVec registers. */ \
917 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
918 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
923 /* 1 for registers not available across function calls.
924 These must include the FIXED_REGISTERS and also any
925 registers that can be used without being saved.
926 The latter must include the registers where values are returned
927 and the register where structure-value addresses are passed.
928 Aside from that, you can include as many other registers as you like. */
930 #define CALL_USED_REGISTERS \
931 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
932 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
933 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
934 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
935 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
936 /* AltiVec registers. */ \
937 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
938 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
943 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
944 the entire set of `FIXED_REGISTERS' be included.
945 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
946 This macro is optional. If not specified, it defaults to the value
947 of `CALL_USED_REGISTERS'. */
949 #define CALL_REALLY_USED_REGISTERS \
950 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
951 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
952 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
953 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
954 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
955 /* AltiVec registers. */ \
956 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
957 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
962 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
964 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
965 #define FIRST_SAVED_FP_REGNO (14+32)
966 #define FIRST_SAVED_GP_REGNO 13
968 /* List the order in which to allocate registers. Each register must be
969 listed once, even those in FIXED_REGISTERS.
971 We allocate in the following order:
972 fp0 (not saved or used for anything)
973 fp13 - fp2 (not saved; incoming fp arg registers)
974 fp1 (not saved; return value)
975 fp31 - fp14 (saved; order given to save least number)
976 cr7, cr6 (not saved or special)
977 cr1 (not saved, but used for FP operations)
978 cr0 (not saved, but used for arithmetic operations)
979 cr4, cr3, cr2 (saved)
980 r0 (not saved; cannot be base reg)
981 r9 (not saved; best for TImode)
982 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
983 r3 (not saved; return value register)
984 r31 - r13 (saved; order given to save least number)
985 r12 (not saved; if used for DImode or DFmode would use r13)
986 mq (not saved; best to use it if we can)
987 ctr (not saved; when we have the choice ctr is better)
989 cr5, r1, r2, ap, ca (fixed)
990 v0 - v1 (not saved or used for anything)
991 v13 - v3 (not saved; incoming vector arg registers)
992 v2 (not saved; incoming vector arg reg; return value)
993 v19 - v14 (not saved or used for anything)
994 v31 - v20 (saved; order given to save least number)
996 spe_acc, spefscr (fixed)
1001 #define MAYBE_R2_AVAILABLE
1002 #define MAYBE_R2_FIXED 2,
1004 #define MAYBE_R2_AVAILABLE 2,
1005 #define MAYBE_R2_FIXED
1008 #define REG_ALLOC_ORDER \
1010 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
1012 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
1013 50, 49, 48, 47, 46, \
1014 75, 74, 69, 68, 72, 71, 70, \
1015 0, MAYBE_R2_AVAILABLE \
1016 9, 11, 10, 8, 7, 6, 5, 4, \
1018 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
1019 18, 17, 16, 15, 14, 13, 12, \
1021 73, 1, MAYBE_R2_FIXED 67, 76, \
1022 /* AltiVec registers. */ \
1024 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
1026 96, 95, 94, 93, 92, 91, \
1027 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
1032 /* True if register is floating-point. */
1033 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
1035 /* True if register is a condition register. */
1036 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
1038 /* True if register is a condition register, but not cr0. */
1039 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
1041 /* True if register is an integer register. */
1042 #define INT_REGNO_P(N) \
1043 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
1045 /* SPE SIMD registers are just the GPRs. */
1046 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
1048 /* PAIRED SIMD registers are just the FPRs. */
1049 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
1051 /* True if register is the CA register. */
1052 #define CA_REGNO_P(N) ((N) == CA_REGNO)
1054 /* True if register is an AltiVec register. */
1055 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1057 /* True if register is a VSX register. */
1058 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
1060 /* Alternate name for any vector register supporting floating point, no matter
1061 which instruction set(s) are available. */
1062 #define VFLOAT_REGNO_P(N) \
1063 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
1065 /* Alternate name for any vector register supporting integer, no matter which
1066 instruction set(s) are available. */
1067 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
1069 /* Alternate name for any vector register supporting logical operations, no
1070 matter which instruction set(s) are available. */
1071 #define VLOGICAL_REGNO_P(N) VFLOAT_REGNO_P (N)
1073 /* Return number of consecutive hard regs needed starting at reg REGNO
1074 to hold something of mode MODE. */
1076 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)]
1078 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1079 (((TARGET_32BIT && TARGET_POWERPC64 \
1080 && (GET_MODE_SIZE (MODE) > 4) \
1081 && INT_REGNO_P (REGNO)) ? 1 : 0) \
1082 || (TARGET_VSX && FP_REGNO_P (REGNO) \
1083 && GET_MODE_SIZE (MODE) > 8))
1085 #define VSX_VECTOR_MODE(MODE) \
1086 ((MODE) == V4SFmode \
1087 || (MODE) == V2DFmode) \
1089 #define VSX_SCALAR_MODE(MODE) \
1092 #define VSX_MODE(MODE) \
1093 (VSX_VECTOR_MODE (MODE) \
1094 || VSX_SCALAR_MODE (MODE))
1096 #define VSX_MOVE_MODE(MODE) \
1097 (VSX_VECTOR_MODE (MODE) \
1098 || VSX_SCALAR_MODE (MODE) \
1099 || ALTIVEC_VECTOR_MODE (MODE) \
1100 || (MODE) == TImode)
1102 #define ALTIVEC_VECTOR_MODE(MODE) \
1103 ((MODE) == V16QImode \
1104 || (MODE) == V8HImode \
1105 || (MODE) == V4SFmode \
1106 || (MODE) == V4SImode)
1108 #define SPE_VECTOR_MODE(MODE) \
1109 ((MODE) == V4HImode \
1110 || (MODE) == V2SFmode \
1111 || (MODE) == V1DImode \
1112 || (MODE) == V2SImode)
1114 #define PAIRED_VECTOR_MODE(MODE) \
1115 ((MODE) == V2SFmode)
1117 #define UNITS_PER_SIMD_WORD(MODE) \
1118 (TARGET_VSX ? UNITS_PER_VSX_WORD \
1119 : (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD \
1120 : (TARGET_SPE ? UNITS_PER_SPE_WORD \
1121 : (TARGET_PAIRED_FLOAT ? UNITS_PER_PAIRED_WORD \
1122 : UNITS_PER_WORD))))
1124 /* Value is TRUE if hard register REGNO can hold a value of
1125 machine-mode MODE. */
1126 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1127 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
1129 /* Value is 1 if it is a good idea to tie two pseudo registers
1130 when one has mode MODE1 and one has mode MODE2.
1131 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1132 for any hard reg, then this must be 0 for correct output. */
1133 #define MODES_TIEABLE_P(MODE1, MODE2) \
1134 (SCALAR_FLOAT_MODE_P (MODE1) \
1135 ? SCALAR_FLOAT_MODE_P (MODE2) \
1136 : SCALAR_FLOAT_MODE_P (MODE2) \
1137 ? SCALAR_FLOAT_MODE_P (MODE1) \
1138 : GET_MODE_CLASS (MODE1) == MODE_CC \
1139 ? GET_MODE_CLASS (MODE2) == MODE_CC \
1140 : GET_MODE_CLASS (MODE2) == MODE_CC \
1141 ? GET_MODE_CLASS (MODE1) == MODE_CC \
1142 : SPE_VECTOR_MODE (MODE1) \
1143 ? SPE_VECTOR_MODE (MODE2) \
1144 : SPE_VECTOR_MODE (MODE2) \
1145 ? SPE_VECTOR_MODE (MODE1) \
1146 : ALTIVEC_VECTOR_MODE (MODE1) \
1147 ? ALTIVEC_VECTOR_MODE (MODE2) \
1148 : ALTIVEC_VECTOR_MODE (MODE2) \
1149 ? ALTIVEC_VECTOR_MODE (MODE1) \
1150 : VSX_VECTOR_MODE (MODE1) \
1151 ? VSX_VECTOR_MODE (MODE2) \
1152 : VSX_VECTOR_MODE (MODE2) \
1153 ? VSX_VECTOR_MODE (MODE1) \
1156 /* Post-reload, we can't use any new AltiVec registers, as we already
1157 emitted the vrsave mask. */
1159 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1160 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
1162 /* A C expression returning the cost of moving data from a register of class
1163 CLASS1 to one of CLASS2. */
1165 #define REGISTER_MOVE_COST rs6000_register_move_cost
1167 /* A C expressions returning the cost of moving data of MODE from a register to
1170 #define MEMORY_MOVE_COST rs6000_memory_move_cost
1172 /* Specify the cost of a branch insn; roughly the number of extra insns that
1173 should be added to avoid a branch.
1175 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1176 unscheduled conditional branch. */
1178 #define BRANCH_COST(speed_p, predictable_p) 3
1180 /* Override BRANCH_COST heuristic which empirically produces worse
1181 performance for removing short circuiting from the logical ops. */
1183 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1185 /* A fixed register used at epilogue generation to address SPE registers
1186 with negative offsets. The 64-bit load/store instructions on the SPE
1187 only take positive offsets (and small ones at that), so we need to
1188 reserve a register for consing up negative offsets. */
1190 #define FIXED_SCRATCH 0
1192 /* Define this macro to change register usage conditional on target
1195 #define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
1197 /* Specify the registers used for certain standard purposes.
1198 The values of these macros are register numbers. */
1200 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1201 /* #define PC_REGNUM */
1203 /* Register to use for pushing function arguments. */
1204 #define STACK_POINTER_REGNUM 1
1206 /* Base register for access to local variables of the function. */
1207 #define HARD_FRAME_POINTER_REGNUM 31
1209 /* Base register for access to local variables of the function. */
1210 #define FRAME_POINTER_REGNUM 113
1212 /* Base register for access to arguments of the function. */
1213 #define ARG_POINTER_REGNUM 67
1215 /* Place to put static chain when calling a function that requires it. */
1216 #define STATIC_CHAIN_REGNUM 11
1219 /* Define the classes of registers for register constraints in the
1220 machine description. Also define ranges of constants.
1222 One of the classes must always be named ALL_REGS and include all hard regs.
1223 If there is more than one class, another class must be named NO_REGS
1224 and contain no registers.
1226 The name GENERAL_REGS must be the name of a class (or an alias for
1227 another name such as ALL_REGS). This is the class of registers
1228 that is allowed by "g" or "r" in a register constraint.
1229 Also, registers outside this class are allocated only when
1230 instructions express preferences for them.
1232 The classes must be numbered in nondecreasing order; that is,
1233 a larger-numbered class must never be contained completely
1234 in a smaller-numbered class.
1236 For any two classes, it is very desirable that there be another
1237 class that represents their union. */
1239 /* The RS/6000 has three types of registers, fixed-point, floating-point, and
1240 condition registers, plus three special registers, MQ, CTR, and the link
1241 register. AltiVec adds a vector register class. VSX registers overlap the
1242 FPR registers and the Altivec registers.
1244 However, r0 is special in that it cannot be used as a base register.
1245 So make a class for registers valid as base registers.
1247 Also, cr0 is the only condition code register that can be used in
1248 arithmetic insns, so make a separate class for it. */
1277 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1279 /* Give names of register classes as strings for dump file. */
1281 #define REG_CLASS_NAMES \
1293 "NON_SPECIAL_REGS", \
1297 "LINK_OR_CTR_REGS", \
1299 "SPEC_OR_GEN_REGS", \
1307 /* Define which registers fit in which classes.
1308 This is an initializer for a vector of HARD_REG_SET
1309 of length N_REG_CLASSES. */
1311 #define REG_CLASS_CONTENTS \
1313 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1314 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
1315 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
1316 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1317 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1318 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \
1319 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1320 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1321 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1322 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1323 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
1324 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1325 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1326 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1327 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1328 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1329 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
1330 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1331 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1332 { 0xffffffff, 0x00000000, 0x0000efff, 0x00020000 }, /* NON_FLOAT_REGS */ \
1333 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \
1334 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \
1337 /* The following macro defines cover classes for Integrated Register
1338 Allocator. Cover classes is a set of non-intersected register
1339 classes covering all hard registers used for register allocation
1340 purpose. Any move between two registers of a cover class should be
1341 cheaper than load or store of the registers. The macro value is
1342 array of register classes with LIM_REG_CLASSES used as the end
1345 We need two IRA_COVER_CLASSES, one for pre-VSX, and the other for VSX to
1346 account for the Altivec and Floating registers being subsets of the VSX
1349 #define IRA_COVER_CLASSES_PRE_VSX \
1351 GENERAL_REGS, SPECIAL_REGS, FLOAT_REGS, ALTIVEC_REGS, /* VSX_REGS, */ \
1352 /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \
1353 /* MQ_REGS, LINK_REGS, CTR_REGS, */ \
1354 CR_REGS, CA_REGS, LIM_REG_CLASSES \
1357 #define IRA_COVER_CLASSES_VSX \
1359 GENERAL_REGS, SPECIAL_REGS, /* FLOAT_REGS, ALTIVEC_REGS, */ VSX_REGS, \
1360 /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \
1361 /* MQ_REGS, LINK_REGS, CTR_REGS, */ \
1362 CR_REGS, CA_REGS, LIM_REG_CLASSES \
1365 /* The same information, inverted:
1366 Return the class number of the smallest class containing
1367 reg number REGNO. This could be a conditional expression
1368 or could index an array. */
1370 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
1373 #define REGNO_REG_CLASS(REGNO) \
1374 (gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \
1375 rs6000_regno_regclass[(REGNO)])
1378 #define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)]
1381 /* Register classes for various constraints that are based on the target
1383 enum r6000_reg_class_enum {
1384 RS6000_CONSTRAINT_d, /* fpr registers for double values */
1385 RS6000_CONSTRAINT_f, /* fpr registers for single values */
1386 RS6000_CONSTRAINT_v, /* Altivec registers */
1387 RS6000_CONSTRAINT_wa, /* Any VSX register */
1388 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
1389 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
1390 RS6000_CONSTRAINT_ws, /* VSX register for DF */
1391 RS6000_CONSTRAINT_MAX
1394 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
1396 /* The class value for index registers, and the one for base regs. */
1397 #define INDEX_REG_CLASS GENERAL_REGS
1398 #define BASE_REG_CLASS BASE_REGS
1400 /* Return whether a given register class can hold VSX objects. */
1401 #define VSX_REG_CLASS_P(CLASS) \
1402 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1404 /* Given an rtx X being reloaded into a reg required to be
1405 in class CLASS, return the class of reg to actually use.
1406 In general this is just CLASS; but on some machines
1407 in some cases it is preferable to use a more restrictive class.
1409 On the RS/6000, we have to return NO_REGS when we want to reload a
1410 floating-point CONST_DOUBLE to force it to be copied to memory.
1412 We also don't want to reload integer values into floating-point
1413 registers if we can at all help it. In fact, this can
1414 cause reload to die, if it tries to generate a reload of CTR
1415 into a FP register and discovers it doesn't have the memory location
1418 ??? Would it be a good idea to have reload do the converse, that is
1419 try to reload floating modes into FP registers if possible?
1422 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1423 rs6000_preferred_reload_class_ptr (X, CLASS)
1425 /* Return the register class of a scratch register needed to copy IN into
1426 or out of a register in CLASS in MODE. If it can be done directly,
1427 NO_REGS is returned. */
1429 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1430 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
1432 /* If we are copying between FP or AltiVec registers and anything
1433 else, we need a memory location. The exception is when we are
1434 targeting ppc64 and the move to/from fpr to gpr instructions
1437 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1438 rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE)
1440 /* For cpus that cannot load/store SDmode values from the 64-bit
1441 FP registers without using a full 64-bit load/store, we need
1442 to allocate a full 64-bit stack slot for them. */
1444 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1445 rs6000_secondary_memory_needed_rtx (MODE)
1447 /* Return the maximum number of consecutive registers
1448 needed to represent mode MODE in a register of class CLASS.
1450 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1451 a single reg is enough for two words, unless we have VSX, where the FP
1452 registers can hold 128 bits. */
1453 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
1455 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
1457 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1458 rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS)
1460 /* Stack layout; function entry, exit and calling. */
1462 /* Enumeration to give which calling sequence to use. */
1465 ABI_AIX, /* IBM's AIX */
1466 ABI_V4, /* System V.4/eabi */
1467 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1470 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1472 /* Define this if pushing a word on the stack
1473 makes the stack pointer a smaller address. */
1474 #define STACK_GROWS_DOWNWARD
1476 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1477 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1479 /* Define this to nonzero if the nominal address of the stack frame
1480 is at the high-address end of the local variables;
1481 that is, each additional local variable allocated
1482 goes at a more negative offset in the frame.
1484 On the RS/6000, we grow upwards, from the area after the outgoing
1486 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0)
1488 /* Size of the outgoing register save area */
1489 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1490 || DEFAULT_ABI == ABI_DARWIN) \
1491 ? (TARGET_64BIT ? 64 : 32) \
1494 /* Size of the fixed area on the stack */
1495 #define RS6000_SAVE_AREA \
1496 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1497 << (TARGET_64BIT ? 1 : 0))
1499 /* MEM representing address to save the TOC register */
1500 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1501 plus_constant (stack_pointer_rtx, \
1502 (TARGET_32BIT ? 20 : 40)))
1504 /* Align an address */
1505 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1507 /* Offset within stack frame to start allocating local variables at.
1508 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1509 first local allocated. Otherwise, it is the offset to the BEGINNING
1510 of the first local allocated.
1512 On the RS/6000, the frame pointer is the same as the stack pointer,
1513 except for dynamic allocations. So we start after the fixed area and
1514 outgoing parameter area. */
1516 #define STARTING_FRAME_OFFSET \
1517 (FRAME_GROWS_DOWNWARD \
1519 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1520 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1521 + RS6000_SAVE_AREA))
1523 /* Offset from the stack pointer register to an item dynamically
1524 allocated on the stack, e.g., by `alloca'.
1526 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1527 length of the outgoing arguments. The default is correct for most
1528 machines. See `function.c' for details. */
1529 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1530 (RS6000_ALIGN (crtl->outgoing_args_size, \
1531 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1532 + (STACK_POINTER_OFFSET))
1534 /* If we generate an insn to push BYTES bytes,
1535 this says how many the stack pointer really advances by.
1536 On RS/6000, don't define this because there are no push insns. */
1537 /* #define PUSH_ROUNDING(BYTES) */
1539 /* Offset of first parameter from the argument pointer register value.
1540 On the RS/6000, we define the argument pointer to the start of the fixed
1542 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1544 /* Offset from the argument pointer register value to the top of
1545 stack. This is different from FIRST_PARM_OFFSET because of the
1546 register save area. */
1547 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1549 /* Define this if stack space is still allocated for a parameter passed
1550 in a register. The value is the number of bytes allocated to this
1552 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1554 /* Define this if the above stack space is to be considered part of the
1555 space allocated by the caller. */
1556 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1558 /* This is the difference between the logical top of stack and the actual sp.
1560 For the RS/6000, sp points past the fixed area. */
1561 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1563 /* Define this if the maximum size of all the outgoing args is to be
1564 accumulated and pushed during the prologue. The amount can be
1565 found in the variable crtl->outgoing_args_size. */
1566 #define ACCUMULATE_OUTGOING_ARGS 1
1568 /* Value is the number of bytes of arguments automatically
1569 popped when returning from a subroutine call.
1570 FUNDECL is the declaration node of the function (as a tree),
1571 FUNTYPE is the data type of the function (as a tree),
1572 or for a library call it is an identifier node for the subroutine name.
1573 SIZE is the number of bytes of arguments passed on the stack. */
1575 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1577 /* Define how to find the value returned by a library function
1578 assuming the value has mode MODE. */
1580 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1582 /* DRAFT_V4_STRUCT_RET defaults off. */
1583 #define DRAFT_V4_STRUCT_RET 0
1585 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1586 #define DEFAULT_PCC_STRUCT_RETURN 0
1588 /* Mode of stack savearea.
1589 FUNCTION is VOIDmode because calling convention maintains SP.
1590 BLOCK needs Pmode for SP.
1591 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1592 #define STACK_SAVEAREA_MODE(LEVEL) \
1593 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1594 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1596 /* Minimum and maximum general purpose registers used to hold arguments. */
1597 #define GP_ARG_MIN_REG 3
1598 #define GP_ARG_MAX_REG 10
1599 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1601 /* Minimum and maximum floating point registers used to hold arguments. */
1602 #define FP_ARG_MIN_REG 33
1603 #define FP_ARG_AIX_MAX_REG 45
1604 #define FP_ARG_V4_MAX_REG 40
1605 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1606 || DEFAULT_ABI == ABI_DARWIN) \
1607 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1608 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1610 /* Minimum and maximum AltiVec registers used to hold arguments. */
1611 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1612 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1613 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1615 /* Return registers */
1616 #define GP_ARG_RETURN GP_ARG_MIN_REG
1617 #define FP_ARG_RETURN FP_ARG_MIN_REG
1618 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1620 /* Flags for the call/call_value rtl operations set up by function_arg */
1621 #define CALL_NORMAL 0x00000000 /* no special processing */
1622 /* Bits in 0x00000001 are unused. */
1623 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1624 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1625 #define CALL_LONG 0x00000008 /* always call indirect */
1626 #define CALL_LIBCALL 0x00000010 /* libcall */
1628 /* We don't have prologue and epilogue functions to save/restore
1629 everything for most ABIs. */
1630 #define WORLD_SAVE_P(INFO) 0
1632 /* 1 if N is a possible register number for a function value
1633 as seen by the caller.
1635 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1636 #define FUNCTION_VALUE_REGNO_P(N) \
1637 ((N) == GP_ARG_RETURN \
1638 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
1639 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1641 /* 1 if N is a possible register number for function argument passing.
1642 On RS/6000, these are r3-r10 and fp1-fp13.
1643 On AltiVec, v2 - v13 are used for passing vectors. */
1644 #define FUNCTION_ARG_REGNO_P(N) \
1645 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1646 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1647 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1648 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1649 && TARGET_HARD_FLOAT && TARGET_FPRS))
1651 /* Define a data type for recording info about an argument list
1652 during the scan of that argument list. This data type should
1653 hold all necessary information about the function itself
1654 and about the args processed so far, enough to enable macros
1655 such as FUNCTION_ARG to determine where the next arg should go.
1657 On the RS/6000, this is a structure. The first element is the number of
1658 total argument words, the second is used to store the next
1659 floating-point register number, and the third says how many more args we
1660 have prototype types for.
1662 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1663 the next available GP register, `fregno' is the next available FP
1664 register, and `words' is the number of words used on the stack.
1666 The varargs/stdarg support requires that this structure's size
1667 be a multiple of sizeof(int). */
1669 typedef struct rs6000_args
1671 int words; /* # words used for passing GP registers */
1672 int fregno; /* next available FP register */
1673 int vregno; /* next available AltiVec register */
1674 int nargs_prototype; /* # args left in the current prototype */
1675 int prototype; /* Whether a prototype was defined */
1676 int stdarg; /* Whether function is a stdarg function. */
1677 int call_cookie; /* Do special things for this call */
1678 int sysv_gregno; /* next available GP register */
1679 int intoffset; /* running offset in struct (darwin64) */
1680 int use_stack; /* any part of struct on stack (darwin64) */
1681 int named; /* false for varargs params */
1684 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1685 for a call to a function whose data type is FNTYPE.
1686 For a library call, FNTYPE is 0. */
1688 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1689 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
1691 /* Similar, but when scanning the definition of a procedure. We always
1692 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1694 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1695 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
1697 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1699 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1700 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
1702 /* Update the data in CUM to advance over an argument
1703 of mode MODE and data type TYPE.
1704 (TYPE is null for libcalls where that information may not be available.) */
1706 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1707 function_arg_advance (&CUM, MODE, TYPE, NAMED, 0)
1709 /* Determine where to put an argument to a function.
1710 Value is zero to push the argument on the stack,
1711 or a hard register in which to store the argument.
1713 MODE is the argument's machine mode.
1714 TYPE is the data type of the argument (as a tree).
1715 This is null for libcalls where that information may
1717 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1718 the preceding args and about the function being called.
1719 NAMED is nonzero if this argument is a named parameter
1720 (otherwise it is an extra parameter matching an ellipsis).
1722 On RS/6000 the first eight words of non-FP are normally in registers
1723 and the rest are pushed. The first 13 FP args are in registers.
1725 If this is floating-point and no prototype is specified, we use
1726 both an FP and integer register (or possibly FP reg and stack). Library
1727 functions (when TYPE is zero) always have the proper types for args,
1728 so we can pass the FP value just in one register. emit_library_function
1729 doesn't support EXPR_LIST anyway. */
1731 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1732 function_arg (&CUM, MODE, TYPE, NAMED)
1734 /* If defined, a C expression which determines whether, and in which
1735 direction, to pad out an argument with extra space. The value
1736 should be of type `enum direction': either `upward' to pad above
1737 the argument, `downward' to pad below, or `none' to inhibit
1740 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1742 /* If defined, a C expression that gives the alignment boundary, in bits,
1743 of an argument with the specified mode and type. If it is not defined,
1744 PARM_BOUNDARY is used for all arguments. */
1746 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1747 function_arg_boundary (MODE, TYPE)
1749 #define PAD_VARARGS_DOWN \
1750 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1752 /* Output assembler code to FILE to increment profiler label # LABELNO
1753 for profiling a function entry. */
1755 #define FUNCTION_PROFILER(FILE, LABELNO) \
1756 output_function_profiler ((FILE), (LABELNO));
1758 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1759 the stack pointer does not matter. No definition is equivalent to
1762 On the RS/6000, this is nonzero because we can restore the stack from
1763 its backpointer, which we maintain. */
1764 #define EXIT_IGNORE_STACK 1
1766 /* Define this macro as a C expression that is nonzero for registers
1767 that are used by the epilogue or the return' pattern. The stack
1768 and frame pointer registers are already be assumed to be used as
1771 #define EPILOGUE_USES(REGNO) \
1772 ((reload_completed && (REGNO) == LR_REGNO) \
1773 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1774 || (crtl->calls_eh_return \
1779 /* Length in units of the trampoline for entering a nested function. */
1781 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1783 /* Definitions for __builtin_return_address and __builtin_frame_address.
1784 __builtin_return_address (0) should give link register (65), enable
1786 /* This should be uncommented, so that the link register is used, but
1787 currently this would result in unmatched insns and spilling fixed
1788 registers so we'll leave it for another day. When these problems are
1789 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1791 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1793 /* Number of bytes into the frame return addresses can be found. See
1794 rs6000_stack_info in rs6000.c for more information on how the different
1795 abi's store the return address. */
1796 #define RETURN_ADDRESS_OFFSET \
1797 ((DEFAULT_ABI == ABI_AIX \
1798 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
1799 (DEFAULT_ABI == ABI_V4) ? 4 : \
1800 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1802 /* The current return address is in link register (65). The return address
1803 of anything farther back is accessed normally at an offset of 8 from the
1805 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1806 (rs6000_return_addr (COUNT, FRAME))
1809 /* Definitions for register eliminations.
1811 We have two registers that can be eliminated on the RS/6000. First, the
1812 frame pointer register can often be eliminated in favor of the stack
1813 pointer register. Secondly, the argument pointer register can always be
1814 eliminated; it is replaced with either the stack or frame pointer.
1816 In addition, we use the elimination mechanism to see if r30 is needed
1817 Initially we assume that it isn't. If it is, we spill it. This is done
1818 by making it an eliminable register. We replace it with itself so that
1819 if it isn't needed, then existing uses won't be modified. */
1821 /* This is an array of structures. Each structure initializes one pair
1822 of eliminable registers. The "from" register number is given first,
1823 followed by "to". Eliminations of the same "from" register are listed
1824 in order of preference. */
1825 #define ELIMINABLE_REGS \
1826 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1827 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1828 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1829 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1830 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1831 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1833 /* Define the offset between two registers, one to be eliminated, and the other
1834 its replacement, at the start of a routine. */
1835 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1836 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1838 /* Addressing modes, and classification of registers for them. */
1840 #define HAVE_PRE_DECREMENT 1
1841 #define HAVE_PRE_INCREMENT 1
1842 #define HAVE_PRE_MODIFY_DISP 1
1843 #define HAVE_PRE_MODIFY_REG 1
1845 /* Macros to check register numbers against specific register classes. */
1847 /* These assume that REGNO is a hard or pseudo reg number.
1848 They give nonzero only if REGNO is a hard reg of the suitable class
1849 or a pseudo reg currently allocated to a suitable hard reg.
1850 Since they use reg_renumber, they are safe only once reg_renumber
1851 has been allocated, which happens in local-alloc.c. */
1853 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1854 ((REGNO) < FIRST_PSEUDO_REGISTER \
1855 ? (REGNO) <= 31 || (REGNO) == 67 \
1856 || (REGNO) == FRAME_POINTER_REGNUM \
1857 : (reg_renumber[REGNO] >= 0 \
1858 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1859 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1861 #define REGNO_OK_FOR_BASE_P(REGNO) \
1862 ((REGNO) < FIRST_PSEUDO_REGISTER \
1863 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1864 || (REGNO) == FRAME_POINTER_REGNUM \
1865 : (reg_renumber[REGNO] > 0 \
1866 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1867 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1869 /* Nonzero if X is a hard reg that can be used as an index
1870 or if it is a pseudo reg in the non-strict case. */
1871 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1872 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1873 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1875 /* Nonzero if X is a hard reg that can be used as a base reg
1876 or if it is a pseudo reg in the non-strict case. */
1877 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1878 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1879 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1882 /* Maximum number of registers that can appear in a valid memory address. */
1884 #define MAX_REGS_PER_ADDRESS 2
1886 /* Recognize any constant value that is a valid address. */
1888 #define CONSTANT_ADDRESS_P(X) \
1889 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1890 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1891 || GET_CODE (X) == HIGH)
1893 /* Nonzero if the constant value X is a legitimate general operand.
1894 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1896 On the RS/6000, all integer constants are acceptable, most won't be valid
1897 for particular insns, though. Only easy FP constants are
1900 #define LEGITIMATE_CONSTANT_P(X) \
1901 (((GET_CODE (X) != CONST_DOUBLE \
1902 && GET_CODE (X) != CONST_VECTOR) \
1903 || GET_MODE (X) == VOIDmode \
1904 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1905 || easy_fp_constant (X, GET_MODE (X)) \
1906 || easy_vector_constant (X, GET_MODE (X))) \
1907 && !rs6000_tls_referenced_p (X))
1909 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1910 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1911 && EASY_VECTOR_15((n) >> 1) \
1914 #define EASY_VECTOR_MSB(n,mode) \
1915 (((unsigned HOST_WIDE_INT)n) == \
1916 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))
1919 /* Try a machine-dependent way of reloading an illegitimate address
1920 operand. If we find one, push the reload and jump to WIN. This
1921 macro is used in only one place: `find_reloads_address' in reload.c.
1923 Implemented on rs6000 by rs6000_legitimize_reload_address.
1924 Note that (X) is evaluated twice; this is safe in current usage. */
1926 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1929 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \
1930 (int)(TYPE), (IND_LEVELS), &win); \
1935 #define FIND_BASE_TERM rs6000_find_base_term
1937 /* The register number of the register used to address a table of
1938 static data addresses in memory. In some cases this register is
1939 defined by a processor's "application binary interface" (ABI).
1940 When this macro is defined, RTL is generated for this register
1941 once, as with the stack pointer and frame pointer registers. If
1942 this macro is not defined, it is up to the machine-dependent files
1943 to allocate such a register (if necessary). */
1945 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1946 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
1948 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1950 /* Define this macro if the register defined by
1951 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1952 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1954 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1956 /* A C expression that is nonzero if X is a legitimate immediate
1957 operand on the target machine when generating position independent
1958 code. You can assume that X satisfies `CONSTANT_P', so you need
1959 not check this. You can also assume FLAG_PIC is true, so you need
1960 not check it either. You need not define this macro if all
1961 constants (including `SYMBOL_REF') can be immediate operands when
1962 generating position independent code. */
1964 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1966 /* Define this if some processing needs to be done immediately before
1967 emitting code for an insn. */
1969 #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \
1970 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS)
1972 /* Specify the machine mode that this machine uses
1973 for the index in the tablejump instruction. */
1974 #define CASE_VECTOR_MODE SImode
1976 /* Define as C expression which evaluates to nonzero if the tablejump
1977 instruction expects the table to contain offsets from the address of the
1979 Do not define this if the table should contain absolute addresses. */
1980 #define CASE_VECTOR_PC_RELATIVE 1
1982 /* Define this as 1 if `char' should by default be signed; else as 0. */
1983 #define DEFAULT_SIGNED_CHAR 0
1985 /* This flag, if defined, says the same insns that convert to a signed fixnum
1986 also convert validly to an unsigned one. */
1988 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
1990 /* An integer expression for the size in bits of the largest integer machine
1991 mode that should actually be used. */
1993 /* Allow pairs of registers to be used, which is the intent of the default. */
1994 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1996 /* Max number of bytes we can move from memory to memory
1997 in one reasonably fast instruction. */
1998 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1999 #define MAX_MOVE_MAX 8
2001 /* Nonzero if access to memory by bytes is no faster than for words.
2002 Also nonzero if doing byte operations (specifically shifts) in registers
2004 #define SLOW_BYTE_ACCESS 1
2006 /* Define if operations between registers always perform the operation
2007 on the full register even if a narrower mode is specified. */
2008 #define WORD_REGISTER_OPERATIONS
2010 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2011 will either zero-extend or sign-extend. The value of this macro should
2012 be the code that says which one of the two operations is implicitly
2013 done, UNKNOWN if none. */
2014 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2016 /* Define if loading short immediate values into registers sign extends. */
2017 #define SHORT_IMMEDIATES_SIGN_EXTEND
2019 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2020 is done just by pretending it is already truncated. */
2021 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2023 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
2024 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2025 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1)
2027 /* The CTZ patterns return -1 for input of zero. */
2028 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
2030 /* Specify the machine mode that pointers have.
2031 After generation of rtl, the compiler makes no further distinction
2032 between pointers and any other objects of this machine mode. */
2033 extern unsigned rs6000_pmode;
2034 #define Pmode ((enum machine_mode)rs6000_pmode)
2036 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
2037 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
2039 /* Mode of a function address in a call instruction (for indexing purposes).
2040 Doesn't matter on RS/6000. */
2041 #define FUNCTION_MODE SImode
2043 /* Define this if addresses of constant functions
2044 shouldn't be put through pseudo regs where they can be cse'd.
2045 Desirable on machines where ordinary constants are expensive
2046 but a CALL with constant address is cheap. */
2047 #define NO_FUNCTION_CSE
2049 /* Define this to be nonzero if shift instructions ignore all but the low-order
2052 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2053 have been dropped from the PowerPC architecture. */
2055 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2057 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2058 should be adjusted to reflect any required changes. This macro is used when
2059 there is some systematic length adjustment required that would be difficult
2060 to express in the length attribute. */
2062 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2064 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2065 COMPARE, return the mode to be used for the comparison. For
2066 floating-point, CCFPmode should be used. CCUNSmode should be used
2067 for unsigned comparisons. CCEQmode should be used when we are
2068 doing an inequality comparison on the result of a
2069 comparison. CCmode should be used in all other cases. */
2071 #define SELECT_CC_MODE(OP,X,Y) \
2072 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
2073 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2074 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
2075 ? CCEQmode : CCmode))
2077 /* Can the condition code MODE be safely reversed? This is safe in
2078 all cases on this port, because at present it doesn't use the
2079 trapping FP comparisons (fcmpo). */
2080 #define REVERSIBLE_CC_MODE(MODE) 1
2082 /* Given a condition code and a mode, return the inverse condition. */
2083 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
2086 /* Control the assembler format that we output. */
2088 /* A C string constant describing how to begin a comment in the target
2089 assembler language. The compiler assumes that the comment will end at
2090 the end of the line. */
2091 #define ASM_COMMENT_START " #"
2093 /* Flag to say the TOC is initialized */
2094 extern int toc_initialized;
2096 /* Macro to output a special constant pool entry. Go to WIN if we output
2097 it. Otherwise, it is written the usual way.
2099 On the RS/6000, toc entries are handled this way. */
2101 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2102 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2104 output_toc (FILE, X, LABELNO, MODE); \
2109 #ifdef HAVE_GAS_WEAK
2110 #define RS6000_WEAK 1
2112 #define RS6000_WEAK 0
2116 /* Used in lieu of ASM_WEAKEN_LABEL. */
2117 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2120 fputs ("\t.weak\t", (FILE)); \
2121 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2122 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2123 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2126 fputs ("[DS]", (FILE)); \
2127 fputs ("\n\t.weak\t.", (FILE)); \
2128 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2130 fputc ('\n', (FILE)); \
2133 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2134 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2135 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2137 fputs ("\t.set\t.", (FILE)); \
2138 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2139 fputs (",.", (FILE)); \
2140 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2141 fputc ('\n', (FILE)); \
2148 #if HAVE_GAS_WEAKREF
2149 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
2152 fputs ("\t.weakref\t", (FILE)); \
2153 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2154 fputs (", ", (FILE)); \
2155 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2156 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2157 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2159 fputs ("\n\t.weakref\t.", (FILE)); \
2160 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2161 fputs (", .", (FILE)); \
2162 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2164 fputc ('\n', (FILE)); \
2168 /* This implements the `alias' attribute. */
2169 #undef ASM_OUTPUT_DEF_FROM_DECLS
2170 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2173 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2174 const char *name = IDENTIFIER_POINTER (TARGET); \
2175 if (TREE_CODE (DECL) == FUNCTION_DECL \
2176 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2178 if (TREE_PUBLIC (DECL)) \
2180 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2182 fputs ("\t.globl\t.", FILE); \
2183 RS6000_OUTPUT_BASENAME (FILE, alias); \
2184 putc ('\n', FILE); \
2187 else if (TARGET_XCOFF) \
2189 fputs ("\t.lglobl\t.", FILE); \
2190 RS6000_OUTPUT_BASENAME (FILE, alias); \
2191 putc ('\n', FILE); \
2193 fputs ("\t.set\t.", FILE); \
2194 RS6000_OUTPUT_BASENAME (FILE, alias); \
2195 fputs (",.", FILE); \
2196 RS6000_OUTPUT_BASENAME (FILE, name); \
2197 fputc ('\n', FILE); \
2199 ASM_OUTPUT_DEF (FILE, alias, name); \
2203 #define TARGET_ASM_FILE_START rs6000_file_start
2205 /* Output to assembler file text saying following lines
2206 may contain character constants, extra white space, comments, etc. */
2208 #define ASM_APP_ON ""
2210 /* Output to assembler file text saying following lines
2211 no longer contain unusual constructs. */
2213 #define ASM_APP_OFF ""
2215 /* How to refer to registers in assembler output.
2216 This sequence is indexed by compiler's hard-register-number (see above). */
2218 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2220 #define REGISTER_NAMES \
2222 &rs6000_reg_names[ 0][0], /* r0 */ \
2223 &rs6000_reg_names[ 1][0], /* r1 */ \
2224 &rs6000_reg_names[ 2][0], /* r2 */ \
2225 &rs6000_reg_names[ 3][0], /* r3 */ \
2226 &rs6000_reg_names[ 4][0], /* r4 */ \
2227 &rs6000_reg_names[ 5][0], /* r5 */ \
2228 &rs6000_reg_names[ 6][0], /* r6 */ \
2229 &rs6000_reg_names[ 7][0], /* r7 */ \
2230 &rs6000_reg_names[ 8][0], /* r8 */ \
2231 &rs6000_reg_names[ 9][0], /* r9 */ \
2232 &rs6000_reg_names[10][0], /* r10 */ \
2233 &rs6000_reg_names[11][0], /* r11 */ \
2234 &rs6000_reg_names[12][0], /* r12 */ \
2235 &rs6000_reg_names[13][0], /* r13 */ \
2236 &rs6000_reg_names[14][0], /* r14 */ \
2237 &rs6000_reg_names[15][0], /* r15 */ \
2238 &rs6000_reg_names[16][0], /* r16 */ \
2239 &rs6000_reg_names[17][0], /* r17 */ \
2240 &rs6000_reg_names[18][0], /* r18 */ \
2241 &rs6000_reg_names[19][0], /* r19 */ \
2242 &rs6000_reg_names[20][0], /* r20 */ \
2243 &rs6000_reg_names[21][0], /* r21 */ \
2244 &rs6000_reg_names[22][0], /* r22 */ \
2245 &rs6000_reg_names[23][0], /* r23 */ \
2246 &rs6000_reg_names[24][0], /* r24 */ \
2247 &rs6000_reg_names[25][0], /* r25 */ \
2248 &rs6000_reg_names[26][0], /* r26 */ \
2249 &rs6000_reg_names[27][0], /* r27 */ \
2250 &rs6000_reg_names[28][0], /* r28 */ \
2251 &rs6000_reg_names[29][0], /* r29 */ \
2252 &rs6000_reg_names[30][0], /* r30 */ \
2253 &rs6000_reg_names[31][0], /* r31 */ \
2255 &rs6000_reg_names[32][0], /* fr0 */ \
2256 &rs6000_reg_names[33][0], /* fr1 */ \
2257 &rs6000_reg_names[34][0], /* fr2 */ \
2258 &rs6000_reg_names[35][0], /* fr3 */ \
2259 &rs6000_reg_names[36][0], /* fr4 */ \
2260 &rs6000_reg_names[37][0], /* fr5 */ \
2261 &rs6000_reg_names[38][0], /* fr6 */ \
2262 &rs6000_reg_names[39][0], /* fr7 */ \
2263 &rs6000_reg_names[40][0], /* fr8 */ \
2264 &rs6000_reg_names[41][0], /* fr9 */ \
2265 &rs6000_reg_names[42][0], /* fr10 */ \
2266 &rs6000_reg_names[43][0], /* fr11 */ \
2267 &rs6000_reg_names[44][0], /* fr12 */ \
2268 &rs6000_reg_names[45][0], /* fr13 */ \
2269 &rs6000_reg_names[46][0], /* fr14 */ \
2270 &rs6000_reg_names[47][0], /* fr15 */ \
2271 &rs6000_reg_names[48][0], /* fr16 */ \
2272 &rs6000_reg_names[49][0], /* fr17 */ \
2273 &rs6000_reg_names[50][0], /* fr18 */ \
2274 &rs6000_reg_names[51][0], /* fr19 */ \
2275 &rs6000_reg_names[52][0], /* fr20 */ \
2276 &rs6000_reg_names[53][0], /* fr21 */ \
2277 &rs6000_reg_names[54][0], /* fr22 */ \
2278 &rs6000_reg_names[55][0], /* fr23 */ \
2279 &rs6000_reg_names[56][0], /* fr24 */ \
2280 &rs6000_reg_names[57][0], /* fr25 */ \
2281 &rs6000_reg_names[58][0], /* fr26 */ \
2282 &rs6000_reg_names[59][0], /* fr27 */ \
2283 &rs6000_reg_names[60][0], /* fr28 */ \
2284 &rs6000_reg_names[61][0], /* fr29 */ \
2285 &rs6000_reg_names[62][0], /* fr30 */ \
2286 &rs6000_reg_names[63][0], /* fr31 */ \
2288 &rs6000_reg_names[64][0], /* mq */ \
2289 &rs6000_reg_names[65][0], /* lr */ \
2290 &rs6000_reg_names[66][0], /* ctr */ \
2291 &rs6000_reg_names[67][0], /* ap */ \
2293 &rs6000_reg_names[68][0], /* cr0 */ \
2294 &rs6000_reg_names[69][0], /* cr1 */ \
2295 &rs6000_reg_names[70][0], /* cr2 */ \
2296 &rs6000_reg_names[71][0], /* cr3 */ \
2297 &rs6000_reg_names[72][0], /* cr4 */ \
2298 &rs6000_reg_names[73][0], /* cr5 */ \
2299 &rs6000_reg_names[74][0], /* cr6 */ \
2300 &rs6000_reg_names[75][0], /* cr7 */ \
2302 &rs6000_reg_names[76][0], /* ca */ \
2304 &rs6000_reg_names[77][0], /* v0 */ \
2305 &rs6000_reg_names[78][0], /* v1 */ \
2306 &rs6000_reg_names[79][0], /* v2 */ \
2307 &rs6000_reg_names[80][0], /* v3 */ \
2308 &rs6000_reg_names[81][0], /* v4 */ \
2309 &rs6000_reg_names[82][0], /* v5 */ \
2310 &rs6000_reg_names[83][0], /* v6 */ \
2311 &rs6000_reg_names[84][0], /* v7 */ \
2312 &rs6000_reg_names[85][0], /* v8 */ \
2313 &rs6000_reg_names[86][0], /* v9 */ \
2314 &rs6000_reg_names[87][0], /* v10 */ \
2315 &rs6000_reg_names[88][0], /* v11 */ \
2316 &rs6000_reg_names[89][0], /* v12 */ \
2317 &rs6000_reg_names[90][0], /* v13 */ \
2318 &rs6000_reg_names[91][0], /* v14 */ \
2319 &rs6000_reg_names[92][0], /* v15 */ \
2320 &rs6000_reg_names[93][0], /* v16 */ \
2321 &rs6000_reg_names[94][0], /* v17 */ \
2322 &rs6000_reg_names[95][0], /* v18 */ \
2323 &rs6000_reg_names[96][0], /* v19 */ \
2324 &rs6000_reg_names[97][0], /* v20 */ \
2325 &rs6000_reg_names[98][0], /* v21 */ \
2326 &rs6000_reg_names[99][0], /* v22 */ \
2327 &rs6000_reg_names[100][0], /* v23 */ \
2328 &rs6000_reg_names[101][0], /* v24 */ \
2329 &rs6000_reg_names[102][0], /* v25 */ \
2330 &rs6000_reg_names[103][0], /* v26 */ \
2331 &rs6000_reg_names[104][0], /* v27 */ \
2332 &rs6000_reg_names[105][0], /* v28 */ \
2333 &rs6000_reg_names[106][0], /* v29 */ \
2334 &rs6000_reg_names[107][0], /* v30 */ \
2335 &rs6000_reg_names[108][0], /* v31 */ \
2336 &rs6000_reg_names[109][0], /* vrsave */ \
2337 &rs6000_reg_names[110][0], /* vscr */ \
2338 &rs6000_reg_names[111][0], /* spe_acc */ \
2339 &rs6000_reg_names[112][0], /* spefscr */ \
2340 &rs6000_reg_names[113][0], /* sfp */ \
2343 /* Table of additional register names to use in user input. */
2345 #define ADDITIONAL_REGISTER_NAMES \
2346 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2347 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2348 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2349 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2350 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2351 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2352 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2353 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2354 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2355 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2356 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2357 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2358 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2359 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2360 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2361 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2362 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2363 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2364 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2365 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2366 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2367 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2368 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2369 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2370 {"vrsave", 109}, {"vscr", 110}, \
2371 {"spe_acc", 111}, {"spefscr", 112}, \
2372 /* no additional names for: mq, lr, ctr, ap */ \
2373 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2374 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2375 {"cc", 68}, {"sp", 1}, {"toc", 2}, \
2376 /* CA is only part of XER, but we do not model the other parts (yet). */ \
2378 /* VSX registers overlaid on top of FR, Altivec registers */ \
2379 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \
2380 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \
2381 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \
2382 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \
2383 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \
2384 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \
2385 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \
2386 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \
2387 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \
2388 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \
2389 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \
2390 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \
2391 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \
2392 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \
2393 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
2394 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108} }
2396 /* Text to write out after a CALL that may be replaced by glue code by
2397 the loader. This depends on the AIX version. */
2398 #define RS6000_CALL_GLUE "cror 31,31,31"
2400 /* This is how to output an element of a case-vector that is relative. */
2402 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2403 do { char buf[100]; \
2404 fputs ("\t.long ", FILE); \
2405 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2406 assemble_name (FILE, buf); \
2408 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2409 assemble_name (FILE, buf); \
2410 putc ('\n', FILE); \
2413 /* This is how to output an assembler line
2414 that says to advance the location counter
2415 to a multiple of 2**LOG bytes. */
2417 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2419 fprintf (FILE, "\t.align %d\n", (LOG))
2421 /* Pick up the return address upon entry to a procedure. Used for
2422 dwarf2 unwind information. This also enables the table driven
2425 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2426 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2428 /* Describe how we implement __builtin_eh_return. */
2429 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2430 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2432 /* Print operand X (an rtx) in assembler syntax to file FILE.
2433 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2434 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2436 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2438 /* Define which CODE values are valid. */
2440 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2441 ((CODE) == '.' || (CODE) == '&')
2443 /* Print a memory address as an operand to reference that memory location. */
2445 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2447 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
2449 if (!rs6000_output_addr_const_extra (STREAM, X)) \
2453 /* uncomment for disabling the corresponding default options */
2454 /* #define MACHINE_no_sched_interblock */
2455 /* #define MACHINE_no_sched_speculative */
2456 /* #define MACHINE_no_sched_speculative_load */
2458 /* General flags. */
2459 extern int flag_pic;
2460 extern int optimize;
2461 extern int flag_expensive_optimizations;
2462 extern int frame_pointer_needed;
2464 /* Classification of the builtin functions to properly set the declaration tree
2468 RS6000_BTC_MISC, /* assume builtin can do anything */
2469 RS6000_BTC_CONST, /* builtin is a 'const' function. */
2470 RS6000_BTC_PURE, /* builtin is a 'pure' function. */
2471 RS6000_BTC_FP_PURE /* builtin is 'pure' if rounding math. */
2474 /* Convenience macros to document the instruction type. */
2475 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches memory */
2476 #define RS6000_BTC_SAT RS6000_BTC_MISC /* VMX saturate sets VSCR register */
2478 #undef RS6000_BUILTIN
2479 #undef RS6000_BUILTIN_EQUATE
2480 #define RS6000_BUILTIN(NAME, TYPE) NAME,
2481 #define RS6000_BUILTIN_EQUATE(NAME, VALUE) NAME = VALUE,
2483 enum rs6000_builtins
2485 #include "rs6000-builtin.def"
2487 RS6000_BUILTIN_COUNT
2490 #undef RS6000_BUILTIN
2491 #undef RS6000_BUILTIN_EQUATE
2493 enum rs6000_builtin_type_index
2495 RS6000_BTI_NOT_OPAQUE,
2496 RS6000_BTI_opaque_V2SI,
2497 RS6000_BTI_opaque_V2SF,
2498 RS6000_BTI_opaque_p_V2SI,
2499 RS6000_BTI_opaque_V4SI,
2509 RS6000_BTI_unsigned_V16QI,
2510 RS6000_BTI_unsigned_V8HI,
2511 RS6000_BTI_unsigned_V4SI,
2512 RS6000_BTI_unsigned_V2DI,
2513 RS6000_BTI_bool_char, /* __bool char */
2514 RS6000_BTI_bool_short, /* __bool short */
2515 RS6000_BTI_bool_int, /* __bool int */
2516 RS6000_BTI_bool_long, /* __bool long */
2517 RS6000_BTI_pixel, /* __pixel */
2518 RS6000_BTI_bool_V16QI, /* __vector __bool char */
2519 RS6000_BTI_bool_V8HI, /* __vector __bool short */
2520 RS6000_BTI_bool_V4SI, /* __vector __bool int */
2521 RS6000_BTI_bool_V2DI, /* __vector __bool long */
2522 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
2523 RS6000_BTI_long, /* long_integer_type_node */
2524 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
2525 RS6000_BTI_INTQI, /* intQI_type_node */
2526 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
2527 RS6000_BTI_INTHI, /* intHI_type_node */
2528 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
2529 RS6000_BTI_INTSI, /* intSI_type_node */
2530 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
2531 RS6000_BTI_INTDI, /* intDI_type_node */
2532 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */
2533 RS6000_BTI_float, /* float_type_node */
2534 RS6000_BTI_double, /* double_type_node */
2535 RS6000_BTI_void, /* void_type_node */
2540 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
2541 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
2542 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
2543 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2544 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
2545 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
2546 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
2547 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
2548 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
2549 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2550 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2551 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2552 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2553 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2554 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
2555 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
2556 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
2557 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2558 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2559 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
2560 #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long])
2561 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2562 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2563 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2564 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
2565 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
2566 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
2568 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
2569 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
2570 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
2571 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
2572 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
2573 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
2574 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
2575 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
2576 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
2577 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
2578 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
2579 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
2580 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
2582 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
2583 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];