1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 Under Section 7 of GPL version 3, you are granted additional
20 permissions described in the GCC Runtime Library Exception, version
21 3.1, as published by the Free Software Foundation.
23 You should have received a copy of the GNU General Public License and
24 a copy of the GCC Runtime Library Exception along with this program;
25 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
26 <http://www.gnu.org/licenses/>. */
28 /* Note that some other tm.h files include this one and then override
29 many of the definitions. */
31 /* Definitions for the object file format. These are set at
34 #define OBJECT_XCOFF 1
37 #define OBJECT_MACHO 4
39 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
40 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
41 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
42 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
48 /* Control whether function entry points use a "dot" symbol when
52 /* Default string to use for cpu if not specified. */
53 #ifndef TARGET_CPU_DEFAULT
54 #define TARGET_CPU_DEFAULT ((char *)0)
57 /* If configured for PPC405, support PPC405CR Erratum77. */
58 #ifdef CONFIG_PPC405CR
59 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
61 #define PPC405_ERRATUM77 0
64 #ifndef TARGET_PAIRED_FLOAT
65 #define TARGET_PAIRED_FLOAT 0
68 #ifdef HAVE_AS_POPCNTB
69 #define ASM_CPU_POWER5_SPEC "-mpower5"
71 #define ASM_CPU_POWER5_SPEC "-mpower4"
75 #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec"
77 #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec"
80 #ifdef HAVE_AS_POPCNTD
81 #define ASM_CPU_POWER7_SPEC "-mpower7"
83 #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec"
86 /* Common ASM definitions used by ASM_SPEC among the various targets for
87 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
88 provide the default assembler options if the user uses -mcpu=native, so if
89 you make changes here, make them also there. */
90 #define ASM_CPU_SPEC \
92 %{mpower: %{!mpower2: -mpwr}} \
94 %{mpowerpc64*: -mppc64} \
95 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
96 %{mno-power: %{!mpowerpc*: -mcom}} \
97 %{!mno-power: %{!mpower*: %(asm_default)}}} \
98 %{mcpu=native: %(asm_cpu_native)} \
99 %{mcpu=common: -mcom} \
100 %{mcpu=cell: -mcell} \
101 %{mcpu=power: -mpwr} \
102 %{mcpu=power2: -mpwrx} \
103 %{mcpu=power3: -mppc64} \
104 %{mcpu=power4: -mpower4} \
105 %{mcpu=power5: %(asm_cpu_power5)} \
106 %{mcpu=power5+: %(asm_cpu_power5)} \
107 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \
108 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
109 %{mcpu=power7: %(asm_cpu_power7)} \
110 %{mcpu=powerpc: -mppc} \
111 %{mcpu=rios: -mpwr} \
112 %{mcpu=rios1: -mpwr} \
113 %{mcpu=rios2: -mpwrx} \
115 %{mcpu=rsc1: -mpwr} \
116 %{mcpu=rs64a: -mppc64} \
120 %{mcpu=405fp: -m405} \
122 %{mcpu=440fp: -m440} \
124 %{mcpu=464fp: -m440} \
129 %{mcpu=603e: -mppc} \
130 %{mcpu=ec603e: -mppc} \
132 %{mcpu=604e: -mppc} \
133 %{mcpu=620: -mppc64} \
134 %{mcpu=630: -mppc64} \
138 %{mcpu=7400: -mppc -maltivec} \
139 %{mcpu=7450: -mppc -maltivec} \
140 %{mcpu=G4: -mppc -maltivec} \
145 %{mcpu=970: -mpower4 -maltivec} \
146 %{mcpu=G5: -mpower4 -maltivec} \
147 %{mcpu=8540: -me500} \
148 %{mcpu=8548: -me500} \
149 %{mcpu=e300c2: -me300} \
150 %{mcpu=e300c3: -me300} \
151 %{mcpu=e500mc: -me500mc} \
152 %{maltivec: -maltivec} \
155 #define CPP_DEFAULT_SPEC ""
157 #define ASM_DEFAULT_SPEC ""
159 /* This macro defines names of additional specifications to put in the specs
160 that can be used in various specifications like CC1_SPEC. Its definition
161 is an initializer with a subgrouping for each command option.
163 Each subgrouping contains a string constant, that defines the
164 specification name, and a string constant that used by the GCC driver
167 Do not define this macro if it does not need to do anything. */
169 #define SUBTARGET_EXTRA_SPECS
171 #define EXTRA_SPECS \
172 { "cpp_default", CPP_DEFAULT_SPEC }, \
173 { "asm_cpu", ASM_CPU_SPEC }, \
174 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \
175 { "asm_default", ASM_DEFAULT_SPEC }, \
176 { "cc1_cpu", CC1_CPU_SPEC }, \
177 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
178 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
179 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \
180 SUBTARGET_EXTRA_SPECS
182 /* -mcpu=native handling only makes sense with compiler running on
183 an PowerPC chip. If changing this condition, also change
184 the condition in driver-rs6000.c. */
185 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
186 /* In driver-rs6000.c. */
187 extern const char *host_detect_local_cpu (int argc, const char **argv);
188 #define EXTRA_SPEC_FUNCTIONS \
189 { "local_cpu_detect", host_detect_local_cpu },
190 #define HAVE_LOCAL_CPU_DETECT
191 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)"
194 #define ASM_CPU_NATIVE_SPEC "%(asm_default)"
198 #ifdef HAVE_LOCAL_CPU_DETECT
199 #define CC1_CPU_SPEC \
200 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
201 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
203 #define CC1_CPU_SPEC ""
207 /* Architecture type. */
209 /* Define TARGET_MFCRF if the target assembler does not support the
210 optional field operand for mfcr. */
212 #ifndef HAVE_AS_MFCRF
214 #define TARGET_MFCRF 0
217 /* Define TARGET_POPCNTB if the target assembler does not support the
218 popcount byte instruction. */
220 #ifndef HAVE_AS_POPCNTB
221 #undef TARGET_POPCNTB
222 #define TARGET_POPCNTB 0
225 /* Define TARGET_FPRND if the target assembler does not support the
226 fp rounding instructions. */
228 #ifndef HAVE_AS_FPRND
230 #define TARGET_FPRND 0
233 /* Define TARGET_CMPB if the target assembler does not support the
238 #define TARGET_CMPB 0
241 /* Define TARGET_MFPGPR if the target assembler does not support the
242 mffpr and mftgpr instructions. */
244 #ifndef HAVE_AS_MFPGPR
246 #define TARGET_MFPGPR 0
249 /* Define TARGET_DFP if the target assembler does not support decimal
250 floating point instructions. */
256 /* Define TARGET_POPCNTD if the target assembler does not support the
257 popcount word and double word instructions. */
259 #ifndef HAVE_AS_POPCNTD
260 #undef TARGET_POPCNTD
261 #define TARGET_POPCNTD 0
264 /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If
265 not, generate the lwsync code as an integer constant. */
266 #ifdef HAVE_AS_LWSYNC
267 #define TARGET_LWSYNC_INSTRUCTION 1
269 #define TARGET_LWSYNC_INSTRUCTION 0
272 /* Define TARGET_TLS_MARKERS if the target assembler does not support
273 arg markers for __tls_get_addr calls. */
274 #ifndef HAVE_AS_TLS_MARKERS
275 #undef TARGET_TLS_MARKERS
276 #define TARGET_TLS_MARKERS 0
278 #define TARGET_TLS_MARKERS tls_markers
281 #ifndef TARGET_SECURE_PLT
282 #define TARGET_SECURE_PLT 0
285 #define TARGET_32BIT (! TARGET_64BIT)
288 #define HAVE_AS_TLS 0
291 /* Return 1 for a symbol ref for a thread-local storage symbol. */
292 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
293 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
296 /* For libgcc2 we make sure this is a compile time constant */
297 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
298 #undef TARGET_POWERPC64
299 #define TARGET_POWERPC64 1
301 #undef TARGET_POWERPC64
302 #define TARGET_POWERPC64 0
305 /* The option machinery will define this. */
308 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
310 /* Processor type. Order must match cpu attribute in MD file. */
340 /* FPU operations supported.
341 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
342 also test TARGET_HARD_FLOAT. */
343 #define TARGET_SINGLE_FLOAT 1
344 #define TARGET_DOUBLE_FLOAT 1
345 #define TARGET_SINGLE_FPU 0
346 #define TARGET_SIMPLE_FPU 0
347 #define TARGET_XILINX_FPU 0
349 extern enum processor_type rs6000_cpu;
351 /* Recast the processor type to the cpu attribute. */
352 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
354 /* Define generic processor types based upon current deployment. */
355 #define PROCESSOR_COMMON PROCESSOR_PPC601
356 #define PROCESSOR_POWER PROCESSOR_RIOS1
357 #define PROCESSOR_POWERPC PROCESSOR_PPC604
358 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
360 /* Define the default processor. This is overridden by other tm.h files. */
361 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
362 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
364 /* FP processor type. */
367 FPU_NONE, /* No FPU */
368 FPU_SF_LITE, /* Limited Single Precision FPU */
369 FPU_DF_LITE, /* Limited Double Precision FPU */
370 FPU_SF_FULL, /* Full Single Precision FPU */
371 FPU_DF_FULL /* Full Double Single Precision FPU */
374 extern enum fpu_type_t fpu_type;
376 /* Specify the dialect of assembler to use. New mnemonics is dialect one
377 and the old mnemonics are dialect zero. */
378 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
380 /* Types of costly dependences. */
381 enum rs6000_dependence_cost
383 max_dep_latency = 1000,
386 true_store_to_load_dep_costly,
387 store_to_load_dep_costly
390 /* Types of nop insertion schemes in sched target hook sched_finish. */
391 enum rs6000_nop_insertion
393 sched_finish_regroup_exact = 1000,
394 sched_finish_pad_groups,
398 /* Dispatch group termination caused by an insn. */
399 enum group_termination
405 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
406 struct rs6000_cpu_select
414 extern struct rs6000_cpu_select rs6000_select[];
417 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */
418 extern int rs6000_debug_stack; /* debug stack applications */
419 extern int rs6000_debug_arg; /* debug argument handling */
420 extern int rs6000_debug_reg; /* debug register handling */
421 extern int rs6000_debug_addr; /* debug memory addressing */
422 extern int rs6000_debug_cost; /* debug rtx_costs */
424 #define TARGET_DEBUG_STACK rs6000_debug_stack
425 #define TARGET_DEBUG_ARG rs6000_debug_arg
426 #define TARGET_DEBUG_REG rs6000_debug_reg
427 #define TARGET_DEBUG_ADDR rs6000_debug_addr
428 #define TARGET_DEBUG_COST rs6000_debug_cost
430 extern const char *rs6000_traceback_name; /* Type of traceback table. */
432 /* These are separate from target_flags because we've run out of bits
434 extern int rs6000_long_double_type_size;
435 extern int rs6000_ieeequad;
436 extern int rs6000_altivec_abi;
437 extern int rs6000_spe_abi;
438 extern int rs6000_spe;
439 extern int rs6000_float_gprs;
440 extern int rs6000_alignment_flags;
441 extern const char *rs6000_sched_insert_nops_str;
442 extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
443 extern int rs6000_xilinx_fpu;
445 /* Describe which vector unit to use for a given machine mode. */
447 VECTOR_NONE, /* Type is not a vector or not supported */
448 VECTOR_ALTIVEC, /* Use altivec for vector processing */
449 VECTOR_VSX, /* Use VSX for vector processing */
450 VECTOR_PAIRED, /* Use paired floating point for vectors */
451 VECTOR_SPE, /* Use SPE for vector processing */
452 VECTOR_OTHER /* Some other vector unit */
455 extern enum rs6000_vector rs6000_vector_unit[];
457 #define VECTOR_UNIT_NONE_P(MODE) \
458 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
460 #define VECTOR_UNIT_VSX_P(MODE) \
461 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
463 #define VECTOR_UNIT_ALTIVEC_P(MODE) \
464 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
466 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
467 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC \
468 || rs6000_vector_unit[(MODE)] == VECTOR_VSX)
470 /* Describe whether to use VSX loads or Altivec loads. For now, just use the
471 same unit as the vector unit we are using, but we may want to migrate to
472 using VSX style loads even for types handled by altivec. */
473 extern enum rs6000_vector rs6000_vector_mem[];
475 #define VECTOR_MEM_NONE_P(MODE) \
476 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
478 #define VECTOR_MEM_VSX_P(MODE) \
479 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
481 #define VECTOR_MEM_ALTIVEC_P(MODE) \
482 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
484 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
485 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC \
486 || rs6000_vector_mem[(MODE)] == VECTOR_VSX)
488 /* Return the alignment of a given vector type, which is set based on the
489 vector unit use. VSX for instance can load 32 or 64 bit aligned words
490 without problems, while Altivec requires 128-bit aligned vectors. */
491 extern int rs6000_vector_align[];
493 #define VECTOR_ALIGN(MODE) \
494 ((rs6000_vector_align[(MODE)] != 0) \
495 ? rs6000_vector_align[(MODE)] \
496 : (int)GET_MODE_BITSIZE ((MODE)))
498 /* Alignment options for fields in structures for sub-targets following
500 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
501 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
503 Override the macro definitions when compiling libobjc to avoid undefined
504 reference to rs6000_alignment_flags due to library's use of GCC alignment
505 macros which use the macros below. */
507 #ifndef IN_TARGET_LIBS
508 #define MASK_ALIGN_POWER 0x00000000
509 #define MASK_ALIGN_NATURAL 0x00000001
510 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
512 #define TARGET_ALIGN_NATURAL 0
515 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
516 #define TARGET_IEEEQUAD rs6000_ieeequad
517 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
518 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
520 #define TARGET_SPE_ABI 0
522 #define TARGET_E500 0
523 #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
524 #define TARGET_FPRS 1
525 #define TARGET_E500_SINGLE 0
526 #define TARGET_E500_DOUBLE 0
527 #define CHECK_E500_OPTIONS do { } while (0)
529 /* E500 processors only support plain "sync", not lwsync. */
530 #define TARGET_NO_LWSYNC TARGET_E500
532 /* Sometimes certain combinations of command options do not make sense
533 on a particular target machine. You can define a macro
534 `OVERRIDE_OPTIONS' to take account of this. This macro, if
535 defined, is executed once just after all the command options have
538 Do not use this macro to turn on various extra optimizations for
539 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
541 On the RS/6000 this is used to define the target cpu type. */
543 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
545 /* Define this to change the optimizations performed by default. */
546 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
548 /* Show we can debug even without a frame pointer. */
549 #define CAN_DEBUG_WITHOUT_FP
552 #define REGISTER_TARGET_PRAGMAS() do { \
553 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
554 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
557 /* Target #defines. */
558 #define TARGET_CPU_CPP_BUILTINS() \
559 rs6000_cpu_cpp_builtins (pfile)
561 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
562 we're compiling for. Some configurations may need to override it. */
563 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
566 if (BYTES_BIG_ENDIAN) \
568 builtin_define ("__BIG_ENDIAN__"); \
569 builtin_define ("_BIG_ENDIAN"); \
570 builtin_assert ("machine=bigendian"); \
574 builtin_define ("__LITTLE_ENDIAN__"); \
575 builtin_define ("_LITTLE_ENDIAN"); \
576 builtin_assert ("machine=littleendian"); \
581 /* Target machine storage layout. */
583 /* Define this macro if it is advisable to hold scalars in registers
584 in a wider mode than that declared by the program. In such cases,
585 the value is constrained to be within the bounds of the declared
586 type, but kept valid in the wider mode. The signedness of the
587 extension may differ from that of the type. */
589 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
590 if (GET_MODE_CLASS (MODE) == MODE_INT \
591 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
592 (MODE) = TARGET_32BIT ? SImode : DImode;
594 /* Define this if most significant bit is lowest numbered
595 in instructions that operate on numbered bit-fields. */
596 /* That is true on RS/6000. */
597 #define BITS_BIG_ENDIAN 1
599 /* Define this if most significant byte of a word is the lowest numbered. */
600 /* That is true on RS/6000. */
601 #define BYTES_BIG_ENDIAN 1
603 /* Define this if most significant word of a multiword number is lowest
606 For RS/6000 we can decide arbitrarily since there are no machine
607 instructions for them. Might as well be consistent with bits and bytes. */
608 #define WORDS_BIG_ENDIAN 1
610 #define MAX_BITS_PER_WORD 64
612 /* Width of a word, in units (bytes). */
613 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
615 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
617 #define MIN_UNITS_PER_WORD 4
619 #define UNITS_PER_FP_WORD 8
620 #define UNITS_PER_ALTIVEC_WORD 16
621 #define UNITS_PER_VSX_WORD 16
622 #define UNITS_PER_SPE_WORD 8
623 #define UNITS_PER_PAIRED_WORD 8
625 /* Type used for ptrdiff_t, as a string used in a declaration. */
626 #define PTRDIFF_TYPE "int"
628 /* Type used for size_t, as a string used in a declaration. */
629 #define SIZE_TYPE "long unsigned int"
631 /* Type used for wchar_t, as a string used in a declaration. */
632 #define WCHAR_TYPE "short unsigned int"
634 /* Width of wchar_t in bits. */
635 #define WCHAR_TYPE_SIZE 16
637 /* A C expression for the size in bits of the type `short' on the
638 target machine. If you don't define this, the default is half a
639 word. (If this would be less than one storage unit, it is
640 rounded up to one unit.) */
641 #define SHORT_TYPE_SIZE 16
643 /* A C expression for the size in bits of the type `int' on the
644 target machine. If you don't define this, the default is one
646 #define INT_TYPE_SIZE 32
648 /* A C expression for the size in bits of the type `long' on the
649 target machine. If you don't define this, the default is one
651 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
653 /* A C expression for the size in bits of the type `long long' on the
654 target machine. If you don't define this, the default is two
656 #define LONG_LONG_TYPE_SIZE 64
658 /* A C expression for the size in bits of the type `float' on the
659 target machine. If you don't define this, the default is one
661 #define FLOAT_TYPE_SIZE 32
663 /* A C expression for the size in bits of the type `double' on the
664 target machine. If you don't define this, the default is two
666 #define DOUBLE_TYPE_SIZE 64
668 /* A C expression for the size in bits of the type `long double' on
669 the target machine. If you don't define this, the default is two
671 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
673 /* Define this to set long double type size to use in libgcc2.c, which can
674 not depend on target_flags. */
675 #ifdef __LONG_DOUBLE_128__
676 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
678 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
681 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
682 #define WIDEST_HARDWARE_FP_SIZE 64
684 /* Width in bits of a pointer.
685 See also the macro `Pmode' defined below. */
686 extern unsigned rs6000_pointer_size;
687 #define POINTER_SIZE rs6000_pointer_size
689 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
690 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
692 /* Boundary (in *bits*) on which stack pointer should be aligned. */
693 #define STACK_BOUNDARY \
694 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
697 /* Allocation boundary (in *bits*) for the code of a function. */
698 #define FUNCTION_BOUNDARY 32
700 /* No data type wants to be aligned rounder than this. */
701 #define BIGGEST_ALIGNMENT 128
703 /* A C expression to compute the alignment for a variables in the
704 local store. TYPE is the data type, and ALIGN is the alignment
705 that the object would ordinarily have. */
706 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
707 DATA_ALIGNMENT (TYPE, ALIGN)
709 /* Alignment of field after `int : 0' in a structure. */
710 #define EMPTY_FIELD_BOUNDARY 32
712 /* Every structure's size must be a multiple of this. */
713 #define STRUCTURE_SIZE_BOUNDARY 8
715 /* Return 1 if a structure or array containing FIELD should be
716 accessed using `BLKMODE'.
718 For the SPE, simd types are V2SI, and gcc can be tempted to put the
719 entire thing in a DI and use subregs to access the internals.
720 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
721 back-end. Because a single GPR can hold a V2SI, but not a DI, the
722 best thing to do is set structs to BLKmode and avoid Severe Tire
725 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
726 fit into 1, whereas DI still needs two. */
727 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
728 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
729 || (TARGET_E500_DOUBLE && (MODE) == DFmode))
731 /* A bit-field declared as `int' forces `int' alignment for the struct. */
732 #define PCC_BITFIELD_TYPE_MATTERS 1
734 /* Make strings word-aligned so strcpy from constants will be faster.
735 Make vector constants quadword aligned. */
736 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
737 (TREE_CODE (EXP) == STRING_CST \
738 && (STRICT_ALIGNMENT || !optimize_size) \
739 && (ALIGN) < BITS_PER_WORD \
743 /* Make arrays of chars word-aligned for the same reasons.
744 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
746 #define DATA_ALIGNMENT(TYPE, ALIGN) \
747 (TREE_CODE (TYPE) == VECTOR_TYPE ? ((TARGET_SPE_ABI \
748 || TARGET_PAIRED_FLOAT) ? 64 : 128) \
749 : (TARGET_E500_DOUBLE \
750 && TYPE_MODE (TYPE) == DFmode) ? 64 \
751 : TREE_CODE (TYPE) == ARRAY_TYPE \
752 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
753 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
755 /* Nonzero if move instructions will actually fail to work
756 when given unaligned data. */
757 #define STRICT_ALIGNMENT 0
759 /* Define this macro to be the value 1 if unaligned accesses have a cost
760 many times greater than aligned accesses, for example if they are
761 emulated in a trap handler. */
762 /* Altivec vector memory instructions simply ignore the low bits; SPE vector
763 memory instructions trap on unaligned accesses; VSX memory instructions are
764 aligned to 4 or 8 bytes. */
765 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
767 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
768 || (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode \
769 || (MODE) == DImode) \
771 || (VECTOR_MODE_P ((MODE)) && (((int)(ALIGN)) < VECTOR_ALIGN (MODE))))
774 /* Standard register usage. */
776 /* Number of actual hardware registers.
777 The hardware registers are assigned numbers for the compiler
778 from 0 to just below FIRST_PSEUDO_REGISTER.
779 All registers that the compiler knows about must be given numbers,
780 even those that are not normally considered general registers.
782 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
783 an MQ register, a count register, a link register, and 8 condition
784 register fields, which we view here as separate registers. AltiVec
785 adds 32 vector registers and a VRsave register.
787 In addition, the difference between the frame and argument pointers is
788 a function of the number of registers saved, so we need to have a
789 register for AP that will later be eliminated in favor of SP or FP.
790 This is a normal register, but it is fixed.
792 We also create a pseudo register for float/int conversions, that will
793 really represent the memory location used. It is represented here as
794 a register, in order to work around problems in allocating stack storage
797 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
798 pointer, which is eventually eliminated in favor of SP or FP. */
800 #define FIRST_PSEUDO_REGISTER 114
802 /* This must be included for pre gcc 3.0 glibc compatibility. */
803 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
805 /* Add 32 dwarf columns for synthetic SPE registers. */
806 #define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)
808 /* The SPE has an additional 32 synthetic registers, with DWARF debug
809 info numbering for these registers starting at 1200. While eh_frame
810 register numbering need not be the same as the debug info numbering,
811 we choose to number these regs for eh_frame at 1200 too. This allows
812 future versions of the rs6000 backend to add hard registers and
813 continue to use the gcc hard register numbering for eh_frame. If the
814 extra SPE registers in eh_frame were numbered starting from the
815 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
816 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
817 avoid invalidating older SPE eh_frame info.
819 We must map them here to avoid huge unwinder tables mostly consisting
821 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
822 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
824 /* Use standard DWARF numbering for DWARF debugging information. */
825 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
827 /* Use gcc hard register numbering for eh_frame. */
828 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
830 /* Map register numbers held in the call frame info that gcc has
831 collected using DWARF_FRAME_REGNUM to those that should be output in
832 .debug_frame and .eh_frame. We continue to use gcc hard reg numbers
833 for .eh_frame, but use the numbers mandated by the various ABIs for
834 .debug_frame. rs6000_emit_prologue has translated any combination of
835 CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves
836 the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */
837 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
838 ((FOR_EH) ? (REGNO) \
839 : (REGNO) == CR2_REGNO ? 64 \
840 : DBX_REGISTER_NUMBER (REGNO))
842 /* 1 for registers that have pervasive standard uses
843 and are not available for the register allocator.
845 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
846 as a local register; for all other OS's r2 is the TOC pointer.
848 cr5 is not supposed to be used.
850 On System V implementations, r13 is fixed and not available for use. */
852 #define FIXED_REGISTERS \
853 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
854 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
855 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
856 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
857 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
858 /* AltiVec registers. */ \
859 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
860 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
865 /* 1 for registers not available across function calls.
866 These must include the FIXED_REGISTERS and also any
867 registers that can be used without being saved.
868 The latter must include the registers where values are returned
869 and the register where structure-value addresses are passed.
870 Aside from that, you can include as many other registers as you like. */
872 #define CALL_USED_REGISTERS \
873 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
874 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
875 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
876 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
877 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
878 /* AltiVec registers. */ \
879 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
880 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
885 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
886 the entire set of `FIXED_REGISTERS' be included.
887 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
888 This macro is optional. If not specified, it defaults to the value
889 of `CALL_USED_REGISTERS'. */
891 #define CALL_REALLY_USED_REGISTERS \
892 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
893 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
894 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
895 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
896 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
897 /* AltiVec registers. */ \
898 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
899 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
904 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
906 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
907 #define FIRST_SAVED_FP_REGNO (14+32)
908 #define FIRST_SAVED_GP_REGNO 13
910 /* List the order in which to allocate registers. Each register must be
911 listed once, even those in FIXED_REGISTERS.
913 We allocate in the following order:
914 fp0 (not saved or used for anything)
915 fp13 - fp2 (not saved; incoming fp arg registers)
916 fp1 (not saved; return value)
917 fp31 - fp14 (saved; order given to save least number)
918 cr7, cr6 (not saved or special)
919 cr1 (not saved, but used for FP operations)
920 cr0 (not saved, but used for arithmetic operations)
921 cr4, cr3, cr2 (saved)
922 r0 (not saved; cannot be base reg)
923 r9 (not saved; best for TImode)
924 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
925 r3 (not saved; return value register)
926 r31 - r13 (saved; order given to save least number)
927 r12 (not saved; if used for DImode or DFmode would use r13)
928 mq (not saved; best to use it if we can)
929 ctr (not saved; when we have the choice ctr is better)
931 cr5, r1, r2, ap, xer (fixed)
932 v0 - v1 (not saved or used for anything)
933 v13 - v3 (not saved; incoming vector arg registers)
934 v2 (not saved; incoming vector arg reg; return value)
935 v19 - v14 (not saved or used for anything)
936 v31 - v20 (saved; order given to save least number)
938 spe_acc, spefscr (fixed)
943 #define MAYBE_R2_AVAILABLE
944 #define MAYBE_R2_FIXED 2,
946 #define MAYBE_R2_AVAILABLE 2,
947 #define MAYBE_R2_FIXED
950 #define REG_ALLOC_ORDER \
952 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
954 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
955 50, 49, 48, 47, 46, \
956 75, 74, 69, 68, 72, 71, 70, \
957 0, MAYBE_R2_AVAILABLE \
958 9, 11, 10, 8, 7, 6, 5, 4, \
960 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
961 18, 17, 16, 15, 14, 13, 12, \
963 73, 1, MAYBE_R2_FIXED 67, 76, \
964 /* AltiVec registers. */ \
966 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
968 96, 95, 94, 93, 92, 91, \
969 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
974 /* True if register is floating-point. */
975 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
977 /* True if register is a condition register. */
978 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
980 /* True if register is a condition register, but not cr0. */
981 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
983 /* True if register is an integer register. */
984 #define INT_REGNO_P(N) \
985 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
987 /* SPE SIMD registers are just the GPRs. */
988 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
990 /* PAIRED SIMD registers are just the FPRs. */
991 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
993 /* True if register is the XER register. */
994 #define XER_REGNO_P(N) ((N) == XER_REGNO)
996 /* True if register is an AltiVec register. */
997 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
999 /* True if register is a VSX register. */
1000 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
1002 /* Alternate name for any vector register supporting floating point, no matter
1003 which instruction set(s) are available. */
1004 #define VFLOAT_REGNO_P(N) \
1005 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
1007 /* Alternate name for any vector register supporting integer, no matter which
1008 instruction set(s) are available. */
1009 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
1011 /* Alternate name for any vector register supporting logical operations, no
1012 matter which instruction set(s) are available. */
1013 #define VLOGICAL_REGNO_P(N) VFLOAT_REGNO_P (N)
1015 /* Return number of consecutive hard regs needed starting at reg REGNO
1016 to hold something of mode MODE. */
1018 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)]
1020 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1021 ((TARGET_32BIT && TARGET_POWERPC64 \
1022 && (GET_MODE_SIZE (MODE) > 4) \
1023 && INT_REGNO_P (REGNO)) ? 1 : 0)
1025 #define VSX_VECTOR_MODE(MODE) \
1026 ((MODE) == V4SFmode \
1027 || (MODE) == V2DFmode) \
1029 #define VSX_SCALAR_MODE(MODE) \
1032 #define VSX_MODE(MODE) \
1033 (VSX_VECTOR_MODE (MODE) \
1034 || VSX_SCALAR_MODE (MODE))
1036 #define VSX_MOVE_MODE(MODE) \
1037 (VSX_VECTOR_MODE (MODE) \
1038 || VSX_SCALAR_MODE (MODE) \
1039 || ALTIVEC_VECTOR_MODE (MODE) \
1040 || (MODE) == TImode)
1042 #define ALTIVEC_VECTOR_MODE(MODE) \
1043 ((MODE) == V16QImode \
1044 || (MODE) == V8HImode \
1045 || (MODE) == V4SFmode \
1046 || (MODE) == V4SImode)
1048 #define SPE_VECTOR_MODE(MODE) \
1049 ((MODE) == V4HImode \
1050 || (MODE) == V2SFmode \
1051 || (MODE) == V1DImode \
1052 || (MODE) == V2SImode)
1054 #define PAIRED_VECTOR_MODE(MODE) \
1055 ((MODE) == V2SFmode)
1057 #define UNITS_PER_SIMD_WORD(MODE) \
1058 (TARGET_VSX ? UNITS_PER_VSX_WORD \
1059 : (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD \
1060 : (TARGET_SPE ? UNITS_PER_SPE_WORD \
1061 : (TARGET_PAIRED_FLOAT ? UNITS_PER_PAIRED_WORD \
1062 : UNITS_PER_WORD))))
1064 /* Value is TRUE if hard register REGNO can hold a value of
1065 machine-mode MODE. */
1066 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1067 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
1069 /* Value is 1 if it is a good idea to tie two pseudo registers
1070 when one has mode MODE1 and one has mode MODE2.
1071 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1072 for any hard reg, then this must be 0 for correct output. */
1073 #define MODES_TIEABLE_P(MODE1, MODE2) \
1074 (SCALAR_FLOAT_MODE_P (MODE1) \
1075 ? SCALAR_FLOAT_MODE_P (MODE2) \
1076 : SCALAR_FLOAT_MODE_P (MODE2) \
1077 ? SCALAR_FLOAT_MODE_P (MODE1) \
1078 : GET_MODE_CLASS (MODE1) == MODE_CC \
1079 ? GET_MODE_CLASS (MODE2) == MODE_CC \
1080 : GET_MODE_CLASS (MODE2) == MODE_CC \
1081 ? GET_MODE_CLASS (MODE1) == MODE_CC \
1082 : SPE_VECTOR_MODE (MODE1) \
1083 ? SPE_VECTOR_MODE (MODE2) \
1084 : SPE_VECTOR_MODE (MODE2) \
1085 ? SPE_VECTOR_MODE (MODE1) \
1086 : ALTIVEC_VECTOR_MODE (MODE1) \
1087 ? ALTIVEC_VECTOR_MODE (MODE2) \
1088 : ALTIVEC_VECTOR_MODE (MODE2) \
1089 ? ALTIVEC_VECTOR_MODE (MODE1) \
1090 : VSX_VECTOR_MODE (MODE1) \
1091 ? VSX_VECTOR_MODE (MODE2) \
1092 : VSX_VECTOR_MODE (MODE2) \
1093 ? VSX_VECTOR_MODE (MODE1) \
1096 /* Post-reload, we can't use any new AltiVec registers, as we already
1097 emitted the vrsave mask. */
1099 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1100 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
1102 /* A C expression returning the cost of moving data from a register of class
1103 CLASS1 to one of CLASS2. */
1105 #define REGISTER_MOVE_COST rs6000_register_move_cost
1107 /* A C expressions returning the cost of moving data of MODE from a register to
1110 #define MEMORY_MOVE_COST rs6000_memory_move_cost
1112 /* Specify the cost of a branch insn; roughly the number of extra insns that
1113 should be added to avoid a branch.
1115 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1116 unscheduled conditional branch. */
1118 #define BRANCH_COST(speed_p, predictable_p) 3
1120 /* Override BRANCH_COST heuristic which empirically produces worse
1121 performance for removing short circuiting from the logical ops. */
1123 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1125 /* A fixed register used at epilogue generation to address SPE registers
1126 with negative offsets. The 64-bit load/store instructions on the SPE
1127 only take positive offsets (and small ones at that), so we need to
1128 reserve a register for consing up negative offsets. */
1130 #define FIXED_SCRATCH 0
1132 /* Define this macro to change register usage conditional on target
1135 #define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
1137 /* Specify the registers used for certain standard purposes.
1138 The values of these macros are register numbers. */
1140 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1141 /* #define PC_REGNUM */
1143 /* Register to use for pushing function arguments. */
1144 #define STACK_POINTER_REGNUM 1
1146 /* Base register for access to local variables of the function. */
1147 #define HARD_FRAME_POINTER_REGNUM 31
1149 /* Base register for access to local variables of the function. */
1150 #define FRAME_POINTER_REGNUM 113
1152 /* Base register for access to arguments of the function. */
1153 #define ARG_POINTER_REGNUM 67
1155 /* Place to put static chain when calling a function that requires it. */
1156 #define STATIC_CHAIN_REGNUM 11
1159 /* Define the classes of registers for register constraints in the
1160 machine description. Also define ranges of constants.
1162 One of the classes must always be named ALL_REGS and include all hard regs.
1163 If there is more than one class, another class must be named NO_REGS
1164 and contain no registers.
1166 The name GENERAL_REGS must be the name of a class (or an alias for
1167 another name such as ALL_REGS). This is the class of registers
1168 that is allowed by "g" or "r" in a register constraint.
1169 Also, registers outside this class are allocated only when
1170 instructions express preferences for them.
1172 The classes must be numbered in nondecreasing order; that is,
1173 a larger-numbered class must never be contained completely
1174 in a smaller-numbered class.
1176 For any two classes, it is very desirable that there be another
1177 class that represents their union. */
1179 /* The RS/6000 has three types of registers, fixed-point, floating-point, and
1180 condition registers, plus three special registers, MQ, CTR, and the link
1181 register. AltiVec adds a vector register class. VSX registers overlap the
1182 FPR registers and the Altivec registers.
1184 However, r0 is special in that it cannot be used as a base register.
1185 So make a class for registers valid as base registers.
1187 Also, cr0 is the only condition code register that can be used in
1188 arithmetic insns, so make a separate class for it. */
1217 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1219 /* Give names of register classes as strings for dump file. */
1221 #define REG_CLASS_NAMES \
1233 "NON_SPECIAL_REGS", \
1237 "LINK_OR_CTR_REGS", \
1239 "SPEC_OR_GEN_REGS", \
1247 /* Define which registers fit in which classes.
1248 This is an initializer for a vector of HARD_REG_SET
1249 of length N_REG_CLASSES. */
1251 #define REG_CLASS_CONTENTS \
1253 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1254 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
1255 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
1256 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1257 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1258 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \
1259 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1260 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1261 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1262 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1263 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
1264 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1265 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1266 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1267 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1268 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1269 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
1270 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1271 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1272 { 0xffffffff, 0x00000000, 0x0000efff, 0x00020000 }, /* NON_FLOAT_REGS */ \
1273 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1274 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \
1277 /* The following macro defines cover classes for Integrated Register
1278 Allocator. Cover classes is a set of non-intersected register
1279 classes covering all hard registers used for register allocation
1280 purpose. Any move between two registers of a cover class should be
1281 cheaper than load or store of the registers. The macro value is
1282 array of register classes with LIM_REG_CLASSES used as the end
1285 We need two IRA_COVER_CLASSES, one for pre-VSX, and the other for VSX to
1286 account for the Altivec and Floating registers being subsets of the VSX
1289 #define IRA_COVER_CLASSES_PRE_VSX \
1291 GENERAL_REGS, SPECIAL_REGS, FLOAT_REGS, ALTIVEC_REGS, /* VSX_REGS, */ \
1292 /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \
1293 /* MQ_REGS, LINK_REGS, CTR_REGS, */ \
1294 CR_REGS, XER_REGS, LIM_REG_CLASSES \
1297 #define IRA_COVER_CLASSES_VSX \
1299 GENERAL_REGS, SPECIAL_REGS, /* FLOAT_REGS, ALTIVEC_REGS, */ VSX_REGS, \
1300 /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \
1301 /* MQ_REGS, LINK_REGS, CTR_REGS, */ \
1302 CR_REGS, XER_REGS, LIM_REG_CLASSES \
1305 /* The same information, inverted:
1306 Return the class number of the smallest class containing
1307 reg number REGNO. This could be a conditional expression
1308 or could index an array. */
1310 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
1313 #define REGNO_REG_CLASS(REGNO) \
1314 (gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \
1315 rs6000_regno_regclass[(REGNO)])
1318 #define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)]
1321 /* Register classes for various constraints that are based on the target
1323 enum r6000_reg_class_enum {
1324 RS6000_CONSTRAINT_d, /* fpr registers for double values */
1325 RS6000_CONSTRAINT_f, /* fpr registers for single values */
1326 RS6000_CONSTRAINT_v, /* Altivec registers */
1327 RS6000_CONSTRAINT_wa, /* Any VSX register */
1328 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
1329 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
1330 RS6000_CONSTRAINT_ws, /* VSX register for DF */
1331 RS6000_CONSTRAINT_MAX
1334 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
1336 /* The class value for index registers, and the one for base regs. */
1337 #define INDEX_REG_CLASS GENERAL_REGS
1338 #define BASE_REG_CLASS BASE_REGS
1340 /* Return whether a given register class can hold VSX objects. */
1341 #define VSX_REG_CLASS_P(CLASS) \
1342 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1344 /* Given an rtx X being reloaded into a reg required to be
1345 in class CLASS, return the class of reg to actually use.
1346 In general this is just CLASS; but on some machines
1347 in some cases it is preferable to use a more restrictive class.
1349 On the RS/6000, we have to return NO_REGS when we want to reload a
1350 floating-point CONST_DOUBLE to force it to be copied to memory.
1352 We also don't want to reload integer values into floating-point
1353 registers if we can at all help it. In fact, this can
1354 cause reload to die, if it tries to generate a reload of CTR
1355 into a FP register and discovers it doesn't have the memory location
1358 ??? Would it be a good idea to have reload do the converse, that is
1359 try to reload floating modes into FP registers if possible?
1362 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1363 rs6000_preferred_reload_class_ptr (X, CLASS)
1365 /* Return the register class of a scratch register needed to copy IN into
1366 or out of a register in CLASS in MODE. If it can be done directly,
1367 NO_REGS is returned. */
1369 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1370 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
1372 /* If we are copying between FP or AltiVec registers and anything
1373 else, we need a memory location. The exception is when we are
1374 targeting ppc64 and the move to/from fpr to gpr instructions
1377 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1378 rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE)
1380 /* For cpus that cannot load/store SDmode values from the 64-bit
1381 FP registers without using a full 64-bit load/store, we need
1382 to allocate a full 64-bit stack slot for them. */
1384 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1385 rs6000_secondary_memory_needed_rtx (MODE)
1387 /* Return the maximum number of consecutive registers
1388 needed to represent mode MODE in a register of class CLASS.
1390 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1391 a single reg is enough for two words, unless we have VSX, where the FP
1392 registers can hold 128 bits. */
1393 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
1395 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
1397 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1398 rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS)
1400 /* Stack layout; function entry, exit and calling. */
1402 /* Enumeration to give which calling sequence to use. */
1405 ABI_AIX, /* IBM's AIX */
1406 ABI_V4, /* System V.4/eabi */
1407 ABI_DARWIN /* Apple's Darwin (OS X kernel) */
1410 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */
1412 /* Define this if pushing a word on the stack
1413 makes the stack pointer a smaller address. */
1414 #define STACK_GROWS_DOWNWARD
1416 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1417 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1419 /* Define this to nonzero if the nominal address of the stack frame
1420 is at the high-address end of the local variables;
1421 that is, each additional local variable allocated
1422 goes at a more negative offset in the frame.
1424 On the RS/6000, we grow upwards, from the area after the outgoing
1426 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0)
1428 /* Size of the outgoing register save area */
1429 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1430 || DEFAULT_ABI == ABI_DARWIN) \
1431 ? (TARGET_64BIT ? 64 : 32) \
1434 /* Size of the fixed area on the stack */
1435 #define RS6000_SAVE_AREA \
1436 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1437 << (TARGET_64BIT ? 1 : 0))
1439 /* MEM representing address to save the TOC register */
1440 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1441 plus_constant (stack_pointer_rtx, \
1442 (TARGET_32BIT ? 20 : 40)))
1444 /* Align an address */
1445 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1447 /* Offset within stack frame to start allocating local variables at.
1448 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1449 first local allocated. Otherwise, it is the offset to the BEGINNING
1450 of the first local allocated.
1452 On the RS/6000, the frame pointer is the same as the stack pointer,
1453 except for dynamic allocations. So we start after the fixed area and
1454 outgoing parameter area. */
1456 #define STARTING_FRAME_OFFSET \
1457 (FRAME_GROWS_DOWNWARD \
1459 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1460 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1461 + RS6000_SAVE_AREA))
1463 /* Offset from the stack pointer register to an item dynamically
1464 allocated on the stack, e.g., by `alloca'.
1466 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1467 length of the outgoing arguments. The default is correct for most
1468 machines. See `function.c' for details. */
1469 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1470 (RS6000_ALIGN (crtl->outgoing_args_size, \
1471 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1472 + (STACK_POINTER_OFFSET))
1474 /* If we generate an insn to push BYTES bytes,
1475 this says how many the stack pointer really advances by.
1476 On RS/6000, don't define this because there are no push insns. */
1477 /* #define PUSH_ROUNDING(BYTES) */
1479 /* Offset of first parameter from the argument pointer register value.
1480 On the RS/6000, we define the argument pointer to the start of the fixed
1482 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1484 /* Offset from the argument pointer register value to the top of
1485 stack. This is different from FIRST_PARM_OFFSET because of the
1486 register save area. */
1487 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1489 /* Define this if stack space is still allocated for a parameter passed
1490 in a register. The value is the number of bytes allocated to this
1492 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1494 /* Define this if the above stack space is to be considered part of the
1495 space allocated by the caller. */
1496 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1498 /* This is the difference between the logical top of stack and the actual sp.
1500 For the RS/6000, sp points past the fixed area. */
1501 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1503 /* Define this if the maximum size of all the outgoing args is to be
1504 accumulated and pushed during the prologue. The amount can be
1505 found in the variable crtl->outgoing_args_size. */
1506 #define ACCUMULATE_OUTGOING_ARGS 1
1508 /* Value is the number of bytes of arguments automatically
1509 popped when returning from a subroutine call.
1510 FUNDECL is the declaration node of the function (as a tree),
1511 FUNTYPE is the data type of the function (as a tree),
1512 or for a library call it is an identifier node for the subroutine name.
1513 SIZE is the number of bytes of arguments passed on the stack. */
1515 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1517 /* Define how to find the value returned by a function.
1518 VALTYPE is the data type of the value (as a tree).
1519 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1520 otherwise, FUNC is 0. */
1522 #define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC))
1524 /* Define how to find the value returned by a library function
1525 assuming the value has mode MODE. */
1527 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1529 /* DRAFT_V4_STRUCT_RET defaults off. */
1530 #define DRAFT_V4_STRUCT_RET 0
1532 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1533 #define DEFAULT_PCC_STRUCT_RETURN 0
1535 /* Mode of stack savearea.
1536 FUNCTION is VOIDmode because calling convention maintains SP.
1537 BLOCK needs Pmode for SP.
1538 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1539 #define STACK_SAVEAREA_MODE(LEVEL) \
1540 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1541 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1543 /* Minimum and maximum general purpose registers used to hold arguments. */
1544 #define GP_ARG_MIN_REG 3
1545 #define GP_ARG_MAX_REG 10
1546 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1548 /* Minimum and maximum floating point registers used to hold arguments. */
1549 #define FP_ARG_MIN_REG 33
1550 #define FP_ARG_AIX_MAX_REG 45
1551 #define FP_ARG_V4_MAX_REG 40
1552 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1553 || DEFAULT_ABI == ABI_DARWIN) \
1554 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1555 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1557 /* Minimum and maximum AltiVec registers used to hold arguments. */
1558 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1559 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1560 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1562 /* Return registers */
1563 #define GP_ARG_RETURN GP_ARG_MIN_REG
1564 #define FP_ARG_RETURN FP_ARG_MIN_REG
1565 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1567 /* Flags for the call/call_value rtl operations set up by function_arg */
1568 #define CALL_NORMAL 0x00000000 /* no special processing */
1569 /* Bits in 0x00000001 are unused. */
1570 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1571 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1572 #define CALL_LONG 0x00000008 /* always call indirect */
1573 #define CALL_LIBCALL 0x00000010 /* libcall */
1575 /* We don't have prologue and epilogue functions to save/restore
1576 everything for most ABIs. */
1577 #define WORLD_SAVE_P(INFO) 0
1579 /* 1 if N is a possible register number for a function value
1580 as seen by the caller.
1582 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1583 #define FUNCTION_VALUE_REGNO_P(N) \
1584 ((N) == GP_ARG_RETURN \
1585 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
1586 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1588 /* 1 if N is a possible register number for function argument passing.
1589 On RS/6000, these are r3-r10 and fp1-fp13.
1590 On AltiVec, v2 - v13 are used for passing vectors. */
1591 #define FUNCTION_ARG_REGNO_P(N) \
1592 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1593 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1594 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1595 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1596 && TARGET_HARD_FLOAT && TARGET_FPRS))
1598 /* Define a data type for recording info about an argument list
1599 during the scan of that argument list. This data type should
1600 hold all necessary information about the function itself
1601 and about the args processed so far, enough to enable macros
1602 such as FUNCTION_ARG to determine where the next arg should go.
1604 On the RS/6000, this is a structure. The first element is the number of
1605 total argument words, the second is used to store the next
1606 floating-point register number, and the third says how many more args we
1607 have prototype types for.
1609 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1610 the next available GP register, `fregno' is the next available FP
1611 register, and `words' is the number of words used on the stack.
1613 The varargs/stdarg support requires that this structure's size
1614 be a multiple of sizeof(int). */
1616 typedef struct rs6000_args
1618 int words; /* # words used for passing GP registers */
1619 int fregno; /* next available FP register */
1620 int vregno; /* next available AltiVec register */
1621 int nargs_prototype; /* # args left in the current prototype */
1622 int prototype; /* Whether a prototype was defined */
1623 int stdarg; /* Whether function is a stdarg function. */
1624 int call_cookie; /* Do special things for this call */
1625 int sysv_gregno; /* next available GP register */
1626 int intoffset; /* running offset in struct (darwin64) */
1627 int use_stack; /* any part of struct on stack (darwin64) */
1628 int named; /* false for varargs params */
1631 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1632 for a call to a function whose data type is FNTYPE.
1633 For a library call, FNTYPE is 0. */
1635 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1636 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
1638 /* Similar, but when scanning the definition of a procedure. We always
1639 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1641 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1642 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
1644 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1646 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1647 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
1649 /* Update the data in CUM to advance over an argument
1650 of mode MODE and data type TYPE.
1651 (TYPE is null for libcalls where that information may not be available.) */
1653 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1654 function_arg_advance (&CUM, MODE, TYPE, NAMED, 0)
1656 /* Determine where to put an argument to a function.
1657 Value is zero to push the argument on the stack,
1658 or a hard register in which to store the argument.
1660 MODE is the argument's machine mode.
1661 TYPE is the data type of the argument (as a tree).
1662 This is null for libcalls where that information may
1664 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1665 the preceding args and about the function being called.
1666 NAMED is nonzero if this argument is a named parameter
1667 (otherwise it is an extra parameter matching an ellipsis).
1669 On RS/6000 the first eight words of non-FP are normally in registers
1670 and the rest are pushed. The first 13 FP args are in registers.
1672 If this is floating-point and no prototype is specified, we use
1673 both an FP and integer register (or possibly FP reg and stack). Library
1674 functions (when TYPE is zero) always have the proper types for args,
1675 so we can pass the FP value just in one register. emit_library_function
1676 doesn't support EXPR_LIST anyway. */
1678 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1679 function_arg (&CUM, MODE, TYPE, NAMED)
1681 /* If defined, a C expression which determines whether, and in which
1682 direction, to pad out an argument with extra space. The value
1683 should be of type `enum direction': either `upward' to pad above
1684 the argument, `downward' to pad below, or `none' to inhibit
1687 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1689 /* If defined, a C expression that gives the alignment boundary, in bits,
1690 of an argument with the specified mode and type. If it is not defined,
1691 PARM_BOUNDARY is used for all arguments. */
1693 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1694 function_arg_boundary (MODE, TYPE)
1696 #define PAD_VARARGS_DOWN \
1697 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1699 /* Output assembler code to FILE to increment profiler label # LABELNO
1700 for profiling a function entry. */
1702 #define FUNCTION_PROFILER(FILE, LABELNO) \
1703 output_function_profiler ((FILE), (LABELNO));
1705 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1706 the stack pointer does not matter. No definition is equivalent to
1709 On the RS/6000, this is nonzero because we can restore the stack from
1710 its backpointer, which we maintain. */
1711 #define EXIT_IGNORE_STACK 1
1713 /* Define this macro as a C expression that is nonzero for registers
1714 that are used by the epilogue or the return' pattern. The stack
1715 and frame pointer registers are already be assumed to be used as
1718 #define EPILOGUE_USES(REGNO) \
1719 ((reload_completed && (REGNO) == LR_REGNO) \
1720 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1721 || (crtl->calls_eh_return \
1726 /* TRAMPOLINE_TEMPLATE deleted */
1728 /* Length in units of the trampoline for entering a nested function. */
1730 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1732 /* Emit RTL insns to initialize the variable parts of a trampoline.
1733 FNADDR is an RTX for the address of the function's pure code.
1734 CXT is an RTX for the static chain value for the function. */
1736 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1737 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1739 /* Definitions for __builtin_return_address and __builtin_frame_address.
1740 __builtin_return_address (0) should give link register (65), enable
1742 /* This should be uncommented, so that the link register is used, but
1743 currently this would result in unmatched insns and spilling fixed
1744 registers so we'll leave it for another day. When these problems are
1745 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1747 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1749 /* Number of bytes into the frame return addresses can be found. See
1750 rs6000_stack_info in rs6000.c for more information on how the different
1751 abi's store the return address. */
1752 #define RETURN_ADDRESS_OFFSET \
1753 ((DEFAULT_ABI == ABI_AIX \
1754 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
1755 (DEFAULT_ABI == ABI_V4) ? 4 : \
1756 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1758 /* The current return address is in link register (65). The return address
1759 of anything farther back is accessed normally at an offset of 8 from the
1761 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1762 (rs6000_return_addr (COUNT, FRAME))
1765 /* Definitions for register eliminations.
1767 We have two registers that can be eliminated on the RS/6000. First, the
1768 frame pointer register can often be eliminated in favor of the stack
1769 pointer register. Secondly, the argument pointer register can always be
1770 eliminated; it is replaced with either the stack or frame pointer.
1772 In addition, we use the elimination mechanism to see if r30 is needed
1773 Initially we assume that it isn't. If it is, we spill it. This is done
1774 by making it an eliminable register. We replace it with itself so that
1775 if it isn't needed, then existing uses won't be modified. */
1777 /* This is an array of structures. Each structure initializes one pair
1778 of eliminable registers. The "from" register number is given first,
1779 followed by "to". Eliminations of the same "from" register are listed
1780 in order of preference. */
1781 #define ELIMINABLE_REGS \
1782 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1783 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1784 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1785 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1786 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1787 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1789 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1790 Frame pointer elimination is automatically handled.
1792 For the RS/6000, if frame pointer elimination is being done, we would like
1793 to convert ap into fp, not sp.
1795 We need r30 if -mminimal-toc was specified, and there are constant pool
1798 #define CAN_ELIMINATE(FROM, TO) \
1799 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1800 ? ! frame_pointer_needed \
1801 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1802 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1805 /* Define the offset between two registers, one to be eliminated, and the other
1806 its replacement, at the start of a routine. */
1807 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1808 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1810 /* Addressing modes, and classification of registers for them. */
1812 #define HAVE_PRE_DECREMENT 1
1813 #define HAVE_PRE_INCREMENT 1
1814 #define HAVE_PRE_MODIFY_DISP 1
1815 #define HAVE_PRE_MODIFY_REG 1
1817 /* Macros to check register numbers against specific register classes. */
1819 /* These assume that REGNO is a hard or pseudo reg number.
1820 They give nonzero only if REGNO is a hard reg of the suitable class
1821 or a pseudo reg currently allocated to a suitable hard reg.
1822 Since they use reg_renumber, they are safe only once reg_renumber
1823 has been allocated, which happens in local-alloc.c. */
1825 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1826 ((REGNO) < FIRST_PSEUDO_REGISTER \
1827 ? (REGNO) <= 31 || (REGNO) == 67 \
1828 || (REGNO) == FRAME_POINTER_REGNUM \
1829 : (reg_renumber[REGNO] >= 0 \
1830 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1831 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1833 #define REGNO_OK_FOR_BASE_P(REGNO) \
1834 ((REGNO) < FIRST_PSEUDO_REGISTER \
1835 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1836 || (REGNO) == FRAME_POINTER_REGNUM \
1837 : (reg_renumber[REGNO] > 0 \
1838 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1839 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1841 /* Nonzero if X is a hard reg that can be used as an index
1842 or if it is a pseudo reg in the non-strict case. */
1843 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1844 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1845 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1847 /* Nonzero if X is a hard reg that can be used as a base reg
1848 or if it is a pseudo reg in the non-strict case. */
1849 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1850 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1851 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1854 /* Maximum number of registers that can appear in a valid memory address. */
1856 #define MAX_REGS_PER_ADDRESS 2
1858 /* Recognize any constant value that is a valid address. */
1860 #define CONSTANT_ADDRESS_P(X) \
1861 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1862 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1863 || GET_CODE (X) == HIGH)
1865 /* Nonzero if the constant value X is a legitimate general operand.
1866 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1868 On the RS/6000, all integer constants are acceptable, most won't be valid
1869 for particular insns, though. Only easy FP constants are
1872 #define LEGITIMATE_CONSTANT_P(X) \
1873 (((GET_CODE (X) != CONST_DOUBLE \
1874 && GET_CODE (X) != CONST_VECTOR) \
1875 || GET_MODE (X) == VOIDmode \
1876 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1877 || easy_fp_constant (X, GET_MODE (X)) \
1878 || easy_vector_constant (X, GET_MODE (X))) \
1879 && !rs6000_tls_referenced_p (X))
1881 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1882 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1883 && EASY_VECTOR_15((n) >> 1) \
1887 /* Try a machine-dependent way of reloading an illegitimate address
1888 operand. If we find one, push the reload and jump to WIN. This
1889 macro is used in only one place: `find_reloads_address' in reload.c.
1891 Implemented on rs6000 by rs6000_legitimize_reload_address.
1892 Note that (X) is evaluated twice; this is safe in current usage. */
1894 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1897 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \
1898 (int)(TYPE), (IND_LEVELS), &win); \
1903 /* Go to LABEL if ADDR (a legitimate address expression)
1904 has an effect that depends on the machine mode it is used for. */
1906 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1908 if (rs6000_mode_dependent_address_ptr (ADDR)) \
1912 #define FIND_BASE_TERM rs6000_find_base_term
1914 /* The register number of the register used to address a table of
1915 static data addresses in memory. In some cases this register is
1916 defined by a processor's "application binary interface" (ABI).
1917 When this macro is defined, RTL is generated for this register
1918 once, as with the stack pointer and frame pointer registers. If
1919 this macro is not defined, it is up to the machine-dependent files
1920 to allocate such a register (if necessary). */
1922 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1923 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
1925 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1927 /* Define this macro if the register defined by
1928 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1929 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1931 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1933 /* A C expression that is nonzero if X is a legitimate immediate
1934 operand on the target machine when generating position independent
1935 code. You can assume that X satisfies `CONSTANT_P', so you need
1936 not check this. You can also assume FLAG_PIC is true, so you need
1937 not check it either. You need not define this macro if all
1938 constants (including `SYMBOL_REF') can be immediate operands when
1939 generating position independent code. */
1941 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1943 /* Define this if some processing needs to be done immediately before
1944 emitting code for an insn. */
1946 #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \
1947 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS)
1949 /* Specify the machine mode that this machine uses
1950 for the index in the tablejump instruction. */
1951 #define CASE_VECTOR_MODE SImode
1953 /* Define as C expression which evaluates to nonzero if the tablejump
1954 instruction expects the table to contain offsets from the address of the
1956 Do not define this if the table should contain absolute addresses. */
1957 #define CASE_VECTOR_PC_RELATIVE 1
1959 /* Define this as 1 if `char' should by default be signed; else as 0. */
1960 #define DEFAULT_SIGNED_CHAR 0
1962 /* This flag, if defined, says the same insns that convert to a signed fixnum
1963 also convert validly to an unsigned one. */
1965 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
1967 /* An integer expression for the size in bits of the largest integer machine
1968 mode that should actually be used. */
1970 /* Allow pairs of registers to be used, which is the intent of the default. */
1971 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1973 /* Max number of bytes we can move from memory to memory
1974 in one reasonably fast instruction. */
1975 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1976 #define MAX_MOVE_MAX 8
1978 /* Nonzero if access to memory by bytes is no faster than for words.
1979 Also nonzero if doing byte operations (specifically shifts) in registers
1981 #define SLOW_BYTE_ACCESS 1
1983 /* Define if operations between registers always perform the operation
1984 on the full register even if a narrower mode is specified. */
1985 #define WORD_REGISTER_OPERATIONS
1987 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1988 will either zero-extend or sign-extend. The value of this macro should
1989 be the code that says which one of the two operations is implicitly
1990 done, UNKNOWN if none. */
1991 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1993 /* Define if loading short immediate values into registers sign extends. */
1994 #define SHORT_IMMEDIATES_SIGN_EXTEND
1996 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1997 is done just by pretending it is already truncated. */
1998 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2000 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
2001 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2002 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1)
2004 /* The CTZ patterns return -1 for input of zero. */
2005 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
2007 /* Specify the machine mode that pointers have.
2008 After generation of rtl, the compiler makes no further distinction
2009 between pointers and any other objects of this machine mode. */
2010 extern unsigned rs6000_pmode;
2011 #define Pmode ((enum machine_mode)rs6000_pmode)
2013 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
2014 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
2016 /* Mode of a function address in a call instruction (for indexing purposes).
2017 Doesn't matter on RS/6000. */
2018 #define FUNCTION_MODE SImode
2020 /* Define this if addresses of constant functions
2021 shouldn't be put through pseudo regs where they can be cse'd.
2022 Desirable on machines where ordinary constants are expensive
2023 but a CALL with constant address is cheap. */
2024 #define NO_FUNCTION_CSE
2026 /* Define this to be nonzero if shift instructions ignore all but the low-order
2029 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2030 have been dropped from the PowerPC architecture. */
2032 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2034 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2035 should be adjusted to reflect any required changes. This macro is used when
2036 there is some systematic length adjustment required that would be difficult
2037 to express in the length attribute. */
2039 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2041 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2042 COMPARE, return the mode to be used for the comparison. For
2043 floating-point, CCFPmode should be used. CCUNSmode should be used
2044 for unsigned comparisons. CCEQmode should be used when we are
2045 doing an inequality comparison on the result of a
2046 comparison. CCmode should be used in all other cases. */
2048 #define SELECT_CC_MODE(OP,X,Y) \
2049 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
2050 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2051 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
2052 ? CCEQmode : CCmode))
2054 /* Can the condition code MODE be safely reversed? This is safe in
2055 all cases on this port, because at present it doesn't use the
2056 trapping FP comparisons (fcmpo). */
2057 #define REVERSIBLE_CC_MODE(MODE) 1
2059 /* Given a condition code and a mode, return the inverse condition. */
2060 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
2063 /* Control the assembler format that we output. */
2065 /* A C string constant describing how to begin a comment in the target
2066 assembler language. The compiler assumes that the comment will end at
2067 the end of the line. */
2068 #define ASM_COMMENT_START " #"
2070 /* Flag to say the TOC is initialized */
2071 extern int toc_initialized;
2073 /* Macro to output a special constant pool entry. Go to WIN if we output
2074 it. Otherwise, it is written the usual way.
2076 On the RS/6000, toc entries are handled this way. */
2078 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2079 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2081 output_toc (FILE, X, LABELNO, MODE); \
2086 #ifdef HAVE_GAS_WEAK
2087 #define RS6000_WEAK 1
2089 #define RS6000_WEAK 0
2093 /* Used in lieu of ASM_WEAKEN_LABEL. */
2094 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2097 fputs ("\t.weak\t", (FILE)); \
2098 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2099 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2100 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2103 fputs ("[DS]", (FILE)); \
2104 fputs ("\n\t.weak\t.", (FILE)); \
2105 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2107 fputc ('\n', (FILE)); \
2110 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2111 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2112 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2114 fputs ("\t.set\t.", (FILE)); \
2115 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2116 fputs (",.", (FILE)); \
2117 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2118 fputc ('\n', (FILE)); \
2125 #if HAVE_GAS_WEAKREF
2126 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
2129 fputs ("\t.weakref\t", (FILE)); \
2130 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2131 fputs (", ", (FILE)); \
2132 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2133 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2134 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2136 fputs ("\n\t.weakref\t.", (FILE)); \
2137 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2138 fputs (", .", (FILE)); \
2139 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2141 fputc ('\n', (FILE)); \
2145 /* This implements the `alias' attribute. */
2146 #undef ASM_OUTPUT_DEF_FROM_DECLS
2147 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2150 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2151 const char *name = IDENTIFIER_POINTER (TARGET); \
2152 if (TREE_CODE (DECL) == FUNCTION_DECL \
2153 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2155 if (TREE_PUBLIC (DECL)) \
2157 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2159 fputs ("\t.globl\t.", FILE); \
2160 RS6000_OUTPUT_BASENAME (FILE, alias); \
2161 putc ('\n', FILE); \
2164 else if (TARGET_XCOFF) \
2166 fputs ("\t.lglobl\t.", FILE); \
2167 RS6000_OUTPUT_BASENAME (FILE, alias); \
2168 putc ('\n', FILE); \
2170 fputs ("\t.set\t.", FILE); \
2171 RS6000_OUTPUT_BASENAME (FILE, alias); \
2172 fputs (",.", FILE); \
2173 RS6000_OUTPUT_BASENAME (FILE, name); \
2174 fputc ('\n', FILE); \
2176 ASM_OUTPUT_DEF (FILE, alias, name); \
2180 #define TARGET_ASM_FILE_START rs6000_file_start
2182 /* Output to assembler file text saying following lines
2183 may contain character constants, extra white space, comments, etc. */
2185 #define ASM_APP_ON ""
2187 /* Output to assembler file text saying following lines
2188 no longer contain unusual constructs. */
2190 #define ASM_APP_OFF ""
2192 /* How to refer to registers in assembler output.
2193 This sequence is indexed by compiler's hard-register-number (see above). */
2195 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2197 #define REGISTER_NAMES \
2199 &rs6000_reg_names[ 0][0], /* r0 */ \
2200 &rs6000_reg_names[ 1][0], /* r1 */ \
2201 &rs6000_reg_names[ 2][0], /* r2 */ \
2202 &rs6000_reg_names[ 3][0], /* r3 */ \
2203 &rs6000_reg_names[ 4][0], /* r4 */ \
2204 &rs6000_reg_names[ 5][0], /* r5 */ \
2205 &rs6000_reg_names[ 6][0], /* r6 */ \
2206 &rs6000_reg_names[ 7][0], /* r7 */ \
2207 &rs6000_reg_names[ 8][0], /* r8 */ \
2208 &rs6000_reg_names[ 9][0], /* r9 */ \
2209 &rs6000_reg_names[10][0], /* r10 */ \
2210 &rs6000_reg_names[11][0], /* r11 */ \
2211 &rs6000_reg_names[12][0], /* r12 */ \
2212 &rs6000_reg_names[13][0], /* r13 */ \
2213 &rs6000_reg_names[14][0], /* r14 */ \
2214 &rs6000_reg_names[15][0], /* r15 */ \
2215 &rs6000_reg_names[16][0], /* r16 */ \
2216 &rs6000_reg_names[17][0], /* r17 */ \
2217 &rs6000_reg_names[18][0], /* r18 */ \
2218 &rs6000_reg_names[19][0], /* r19 */ \
2219 &rs6000_reg_names[20][0], /* r20 */ \
2220 &rs6000_reg_names[21][0], /* r21 */ \
2221 &rs6000_reg_names[22][0], /* r22 */ \
2222 &rs6000_reg_names[23][0], /* r23 */ \
2223 &rs6000_reg_names[24][0], /* r24 */ \
2224 &rs6000_reg_names[25][0], /* r25 */ \
2225 &rs6000_reg_names[26][0], /* r26 */ \
2226 &rs6000_reg_names[27][0], /* r27 */ \
2227 &rs6000_reg_names[28][0], /* r28 */ \
2228 &rs6000_reg_names[29][0], /* r29 */ \
2229 &rs6000_reg_names[30][0], /* r30 */ \
2230 &rs6000_reg_names[31][0], /* r31 */ \
2232 &rs6000_reg_names[32][0], /* fr0 */ \
2233 &rs6000_reg_names[33][0], /* fr1 */ \
2234 &rs6000_reg_names[34][0], /* fr2 */ \
2235 &rs6000_reg_names[35][0], /* fr3 */ \
2236 &rs6000_reg_names[36][0], /* fr4 */ \
2237 &rs6000_reg_names[37][0], /* fr5 */ \
2238 &rs6000_reg_names[38][0], /* fr6 */ \
2239 &rs6000_reg_names[39][0], /* fr7 */ \
2240 &rs6000_reg_names[40][0], /* fr8 */ \
2241 &rs6000_reg_names[41][0], /* fr9 */ \
2242 &rs6000_reg_names[42][0], /* fr10 */ \
2243 &rs6000_reg_names[43][0], /* fr11 */ \
2244 &rs6000_reg_names[44][0], /* fr12 */ \
2245 &rs6000_reg_names[45][0], /* fr13 */ \
2246 &rs6000_reg_names[46][0], /* fr14 */ \
2247 &rs6000_reg_names[47][0], /* fr15 */ \
2248 &rs6000_reg_names[48][0], /* fr16 */ \
2249 &rs6000_reg_names[49][0], /* fr17 */ \
2250 &rs6000_reg_names[50][0], /* fr18 */ \
2251 &rs6000_reg_names[51][0], /* fr19 */ \
2252 &rs6000_reg_names[52][0], /* fr20 */ \
2253 &rs6000_reg_names[53][0], /* fr21 */ \
2254 &rs6000_reg_names[54][0], /* fr22 */ \
2255 &rs6000_reg_names[55][0], /* fr23 */ \
2256 &rs6000_reg_names[56][0], /* fr24 */ \
2257 &rs6000_reg_names[57][0], /* fr25 */ \
2258 &rs6000_reg_names[58][0], /* fr26 */ \
2259 &rs6000_reg_names[59][0], /* fr27 */ \
2260 &rs6000_reg_names[60][0], /* fr28 */ \
2261 &rs6000_reg_names[61][0], /* fr29 */ \
2262 &rs6000_reg_names[62][0], /* fr30 */ \
2263 &rs6000_reg_names[63][0], /* fr31 */ \
2265 &rs6000_reg_names[64][0], /* mq */ \
2266 &rs6000_reg_names[65][0], /* lr */ \
2267 &rs6000_reg_names[66][0], /* ctr */ \
2268 &rs6000_reg_names[67][0], /* ap */ \
2270 &rs6000_reg_names[68][0], /* cr0 */ \
2271 &rs6000_reg_names[69][0], /* cr1 */ \
2272 &rs6000_reg_names[70][0], /* cr2 */ \
2273 &rs6000_reg_names[71][0], /* cr3 */ \
2274 &rs6000_reg_names[72][0], /* cr4 */ \
2275 &rs6000_reg_names[73][0], /* cr5 */ \
2276 &rs6000_reg_names[74][0], /* cr6 */ \
2277 &rs6000_reg_names[75][0], /* cr7 */ \
2279 &rs6000_reg_names[76][0], /* xer */ \
2281 &rs6000_reg_names[77][0], /* v0 */ \
2282 &rs6000_reg_names[78][0], /* v1 */ \
2283 &rs6000_reg_names[79][0], /* v2 */ \
2284 &rs6000_reg_names[80][0], /* v3 */ \
2285 &rs6000_reg_names[81][0], /* v4 */ \
2286 &rs6000_reg_names[82][0], /* v5 */ \
2287 &rs6000_reg_names[83][0], /* v6 */ \
2288 &rs6000_reg_names[84][0], /* v7 */ \
2289 &rs6000_reg_names[85][0], /* v8 */ \
2290 &rs6000_reg_names[86][0], /* v9 */ \
2291 &rs6000_reg_names[87][0], /* v10 */ \
2292 &rs6000_reg_names[88][0], /* v11 */ \
2293 &rs6000_reg_names[89][0], /* v12 */ \
2294 &rs6000_reg_names[90][0], /* v13 */ \
2295 &rs6000_reg_names[91][0], /* v14 */ \
2296 &rs6000_reg_names[92][0], /* v15 */ \
2297 &rs6000_reg_names[93][0], /* v16 */ \
2298 &rs6000_reg_names[94][0], /* v17 */ \
2299 &rs6000_reg_names[95][0], /* v18 */ \
2300 &rs6000_reg_names[96][0], /* v19 */ \
2301 &rs6000_reg_names[97][0], /* v20 */ \
2302 &rs6000_reg_names[98][0], /* v21 */ \
2303 &rs6000_reg_names[99][0], /* v22 */ \
2304 &rs6000_reg_names[100][0], /* v23 */ \
2305 &rs6000_reg_names[101][0], /* v24 */ \
2306 &rs6000_reg_names[102][0], /* v25 */ \
2307 &rs6000_reg_names[103][0], /* v26 */ \
2308 &rs6000_reg_names[104][0], /* v27 */ \
2309 &rs6000_reg_names[105][0], /* v28 */ \
2310 &rs6000_reg_names[106][0], /* v29 */ \
2311 &rs6000_reg_names[107][0], /* v30 */ \
2312 &rs6000_reg_names[108][0], /* v31 */ \
2313 &rs6000_reg_names[109][0], /* vrsave */ \
2314 &rs6000_reg_names[110][0], /* vscr */ \
2315 &rs6000_reg_names[111][0], /* spe_acc */ \
2316 &rs6000_reg_names[112][0], /* spefscr */ \
2317 &rs6000_reg_names[113][0], /* sfp */ \
2320 /* Table of additional register names to use in user input. */
2322 #define ADDITIONAL_REGISTER_NAMES \
2323 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2324 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2325 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2326 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2327 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2328 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2329 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2330 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2331 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2332 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2333 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2334 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2335 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2336 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2337 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2338 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2339 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2340 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2341 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2342 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2343 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2344 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2345 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2346 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2347 {"vrsave", 109}, {"vscr", 110}, \
2348 {"spe_acc", 111}, {"spefscr", 112}, \
2349 /* no additional names for: mq, lr, ctr, ap */ \
2350 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2351 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2352 {"cc", 68}, {"sp", 1}, {"toc", 2}, \
2353 /* VSX registers overlaid on top of FR, Altivec registers */ \
2354 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \
2355 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \
2356 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \
2357 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \
2358 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \
2359 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \
2360 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \
2361 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \
2362 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \
2363 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \
2364 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \
2365 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \
2366 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \
2367 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \
2368 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
2369 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108} }
2371 /* Text to write out after a CALL that may be replaced by glue code by
2372 the loader. This depends on the AIX version. */
2373 #define RS6000_CALL_GLUE "cror 31,31,31"
2375 /* This is how to output an element of a case-vector that is relative. */
2377 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2378 do { char buf[100]; \
2379 fputs ("\t.long ", FILE); \
2380 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2381 assemble_name (FILE, buf); \
2383 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2384 assemble_name (FILE, buf); \
2385 putc ('\n', FILE); \
2388 /* This is how to output an assembler line
2389 that says to advance the location counter
2390 to a multiple of 2**LOG bytes. */
2392 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2394 fprintf (FILE, "\t.align %d\n", (LOG))
2396 /* Pick up the return address upon entry to a procedure. Used for
2397 dwarf2 unwind information. This also enables the table driven
2400 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2401 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2403 /* Describe how we implement __builtin_eh_return. */
2404 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2405 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2407 /* Print operand X (an rtx) in assembler syntax to file FILE.
2408 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2409 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2411 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2413 /* Define which CODE values are valid. */
2415 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2416 ((CODE) == '.' || (CODE) == '&')
2418 /* Print a memory address as an operand to reference that memory location. */
2420 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2422 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
2424 if (!rs6000_output_addr_const_extra (STREAM, X)) \
2428 /* uncomment for disabling the corresponding default options */
2429 /* #define MACHINE_no_sched_interblock */
2430 /* #define MACHINE_no_sched_speculative */
2431 /* #define MACHINE_no_sched_speculative_load */
2433 /* General flags. */
2434 extern int flag_pic;
2435 extern int optimize;
2436 extern int flag_expensive_optimizations;
2437 extern int frame_pointer_needed;
2439 enum rs6000_builtins
2441 /* AltiVec builtins. */
2442 ALTIVEC_BUILTIN_ST_INTERNAL_4si,
2443 ALTIVEC_BUILTIN_LD_INTERNAL_4si,
2444 ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
2445 ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
2446 ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
2447 ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
2448 ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
2449 ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
2450 ALTIVEC_BUILTIN_VADDUBM,
2451 ALTIVEC_BUILTIN_VADDUHM,
2452 ALTIVEC_BUILTIN_VADDUWM,
2453 ALTIVEC_BUILTIN_VADDFP,
2454 ALTIVEC_BUILTIN_VADDCUW,
2455 ALTIVEC_BUILTIN_VADDUBS,
2456 ALTIVEC_BUILTIN_VADDSBS,
2457 ALTIVEC_BUILTIN_VADDUHS,
2458 ALTIVEC_BUILTIN_VADDSHS,
2459 ALTIVEC_BUILTIN_VADDUWS,
2460 ALTIVEC_BUILTIN_VADDSWS,
2461 ALTIVEC_BUILTIN_VAND,
2462 ALTIVEC_BUILTIN_VANDC,
2463 ALTIVEC_BUILTIN_VAVGUB,
2464 ALTIVEC_BUILTIN_VAVGSB,
2465 ALTIVEC_BUILTIN_VAVGUH,
2466 ALTIVEC_BUILTIN_VAVGSH,
2467 ALTIVEC_BUILTIN_VAVGUW,
2468 ALTIVEC_BUILTIN_VAVGSW,
2469 ALTIVEC_BUILTIN_VCFUX,
2470 ALTIVEC_BUILTIN_VCFSX,
2471 ALTIVEC_BUILTIN_VCTSXS,
2472 ALTIVEC_BUILTIN_VCTUXS,
2473 ALTIVEC_BUILTIN_VCMPBFP,
2474 ALTIVEC_BUILTIN_VCMPEQUB,
2475 ALTIVEC_BUILTIN_VCMPEQUH,
2476 ALTIVEC_BUILTIN_VCMPEQUW,
2477 ALTIVEC_BUILTIN_VCMPEQFP,
2478 ALTIVEC_BUILTIN_VCMPGEFP,
2479 ALTIVEC_BUILTIN_VCMPGTUB,
2480 ALTIVEC_BUILTIN_VCMPGTSB,
2481 ALTIVEC_BUILTIN_VCMPGTUH,
2482 ALTIVEC_BUILTIN_VCMPGTSH,
2483 ALTIVEC_BUILTIN_VCMPGTUW,
2484 ALTIVEC_BUILTIN_VCMPGTSW,
2485 ALTIVEC_BUILTIN_VCMPGTFP,
2486 ALTIVEC_BUILTIN_VEXPTEFP,
2487 ALTIVEC_BUILTIN_VLOGEFP,
2488 ALTIVEC_BUILTIN_VMADDFP,
2489 ALTIVEC_BUILTIN_VMAXUB,
2490 ALTIVEC_BUILTIN_VMAXSB,
2491 ALTIVEC_BUILTIN_VMAXUH,
2492 ALTIVEC_BUILTIN_VMAXSH,
2493 ALTIVEC_BUILTIN_VMAXUW,
2494 ALTIVEC_BUILTIN_VMAXSW,
2495 ALTIVEC_BUILTIN_VMAXFP,
2496 ALTIVEC_BUILTIN_VMHADDSHS,
2497 ALTIVEC_BUILTIN_VMHRADDSHS,
2498 ALTIVEC_BUILTIN_VMLADDUHM,
2499 ALTIVEC_BUILTIN_VMRGHB,
2500 ALTIVEC_BUILTIN_VMRGHH,
2501 ALTIVEC_BUILTIN_VMRGHW,
2502 ALTIVEC_BUILTIN_VMRGLB,
2503 ALTIVEC_BUILTIN_VMRGLH,
2504 ALTIVEC_BUILTIN_VMRGLW,
2505 ALTIVEC_BUILTIN_VMSUMUBM,
2506 ALTIVEC_BUILTIN_VMSUMMBM,
2507 ALTIVEC_BUILTIN_VMSUMUHM,
2508 ALTIVEC_BUILTIN_VMSUMSHM,
2509 ALTIVEC_BUILTIN_VMSUMUHS,
2510 ALTIVEC_BUILTIN_VMSUMSHS,
2511 ALTIVEC_BUILTIN_VMINUB,
2512 ALTIVEC_BUILTIN_VMINSB,
2513 ALTIVEC_BUILTIN_VMINUH,
2514 ALTIVEC_BUILTIN_VMINSH,
2515 ALTIVEC_BUILTIN_VMINUW,
2516 ALTIVEC_BUILTIN_VMINSW,
2517 ALTIVEC_BUILTIN_VMINFP,
2518 ALTIVEC_BUILTIN_VMULEUB,
2519 ALTIVEC_BUILTIN_VMULEUB_UNS,
2520 ALTIVEC_BUILTIN_VMULESB,
2521 ALTIVEC_BUILTIN_VMULEUH,
2522 ALTIVEC_BUILTIN_VMULEUH_UNS,
2523 ALTIVEC_BUILTIN_VMULESH,
2524 ALTIVEC_BUILTIN_VMULOUB,
2525 ALTIVEC_BUILTIN_VMULOUB_UNS,
2526 ALTIVEC_BUILTIN_VMULOSB,
2527 ALTIVEC_BUILTIN_VMULOUH,
2528 ALTIVEC_BUILTIN_VMULOUH_UNS,
2529 ALTIVEC_BUILTIN_VMULOSH,
2530 ALTIVEC_BUILTIN_VNMSUBFP,
2531 ALTIVEC_BUILTIN_VNOR,
2532 ALTIVEC_BUILTIN_VOR,
2533 ALTIVEC_BUILTIN_VSEL_2DF, /* needed for VSX */
2534 ALTIVEC_BUILTIN_VSEL_2DI, /* needed for VSX */
2535 ALTIVEC_BUILTIN_VSEL_4SI,
2536 ALTIVEC_BUILTIN_VSEL_4SF,
2537 ALTIVEC_BUILTIN_VSEL_8HI,
2538 ALTIVEC_BUILTIN_VSEL_16QI,
2539 ALTIVEC_BUILTIN_VSEL_2DI_UNS,
2540 ALTIVEC_BUILTIN_VSEL_4SI_UNS,
2541 ALTIVEC_BUILTIN_VSEL_8HI_UNS,
2542 ALTIVEC_BUILTIN_VSEL_16QI_UNS,
2543 ALTIVEC_BUILTIN_VPERM_2DF, /* needed for VSX */
2544 ALTIVEC_BUILTIN_VPERM_2DI, /* needed for VSX */
2545 ALTIVEC_BUILTIN_VPERM_4SI,
2546 ALTIVEC_BUILTIN_VPERM_4SF,
2547 ALTIVEC_BUILTIN_VPERM_8HI,
2548 ALTIVEC_BUILTIN_VPERM_16QI,
2549 ALTIVEC_BUILTIN_VPERM_2DI_UNS,
2550 ALTIVEC_BUILTIN_VPERM_4SI_UNS,
2551 ALTIVEC_BUILTIN_VPERM_8HI_UNS,
2552 ALTIVEC_BUILTIN_VPERM_16QI_UNS,
2553 ALTIVEC_BUILTIN_VPKUHUM,
2554 ALTIVEC_BUILTIN_VPKUWUM,
2555 ALTIVEC_BUILTIN_VPKPX,
2556 ALTIVEC_BUILTIN_VPKUHSS,
2557 ALTIVEC_BUILTIN_VPKSHSS,
2558 ALTIVEC_BUILTIN_VPKUWSS,
2559 ALTIVEC_BUILTIN_VPKSWSS,
2560 ALTIVEC_BUILTIN_VPKUHUS,
2561 ALTIVEC_BUILTIN_VPKSHUS,
2562 ALTIVEC_BUILTIN_VPKUWUS,
2563 ALTIVEC_BUILTIN_VPKSWUS,
2564 ALTIVEC_BUILTIN_VREFP,
2565 ALTIVEC_BUILTIN_VRFIM,
2566 ALTIVEC_BUILTIN_VRFIN,
2567 ALTIVEC_BUILTIN_VRFIP,
2568 ALTIVEC_BUILTIN_VRFIZ,
2569 ALTIVEC_BUILTIN_VRLB,
2570 ALTIVEC_BUILTIN_VRLH,
2571 ALTIVEC_BUILTIN_VRLW,
2572 ALTIVEC_BUILTIN_VRSQRTEFP,
2573 ALTIVEC_BUILTIN_VSLB,
2574 ALTIVEC_BUILTIN_VSLH,
2575 ALTIVEC_BUILTIN_VSLW,
2576 ALTIVEC_BUILTIN_VSL,
2577 ALTIVEC_BUILTIN_VSLO,
2578 ALTIVEC_BUILTIN_VSPLTB,
2579 ALTIVEC_BUILTIN_VSPLTH,
2580 ALTIVEC_BUILTIN_VSPLTW,
2581 ALTIVEC_BUILTIN_VSPLTISB,
2582 ALTIVEC_BUILTIN_VSPLTISH,
2583 ALTIVEC_BUILTIN_VSPLTISW,
2584 ALTIVEC_BUILTIN_VSRB,
2585 ALTIVEC_BUILTIN_VSRH,
2586 ALTIVEC_BUILTIN_VSRW,
2587 ALTIVEC_BUILTIN_VSRAB,
2588 ALTIVEC_BUILTIN_VSRAH,
2589 ALTIVEC_BUILTIN_VSRAW,
2590 ALTIVEC_BUILTIN_VSR,
2591 ALTIVEC_BUILTIN_VSRO,
2592 ALTIVEC_BUILTIN_VSUBUBM,
2593 ALTIVEC_BUILTIN_VSUBUHM,
2594 ALTIVEC_BUILTIN_VSUBUWM,
2595 ALTIVEC_BUILTIN_VSUBFP,
2596 ALTIVEC_BUILTIN_VSUBCUW,
2597 ALTIVEC_BUILTIN_VSUBUBS,
2598 ALTIVEC_BUILTIN_VSUBSBS,
2599 ALTIVEC_BUILTIN_VSUBUHS,
2600 ALTIVEC_BUILTIN_VSUBSHS,
2601 ALTIVEC_BUILTIN_VSUBUWS,
2602 ALTIVEC_BUILTIN_VSUBSWS,
2603 ALTIVEC_BUILTIN_VSUM4UBS,
2604 ALTIVEC_BUILTIN_VSUM4SBS,
2605 ALTIVEC_BUILTIN_VSUM4SHS,
2606 ALTIVEC_BUILTIN_VSUM2SWS,
2607 ALTIVEC_BUILTIN_VSUMSWS,
2608 ALTIVEC_BUILTIN_VXOR,
2609 ALTIVEC_BUILTIN_VSLDOI_16QI,
2610 ALTIVEC_BUILTIN_VSLDOI_8HI,
2611 ALTIVEC_BUILTIN_VSLDOI_4SI,
2612 ALTIVEC_BUILTIN_VSLDOI_4SF,
2613 ALTIVEC_BUILTIN_VUPKHSB,
2614 ALTIVEC_BUILTIN_VUPKHPX,
2615 ALTIVEC_BUILTIN_VUPKHSH,
2616 ALTIVEC_BUILTIN_VUPKLSB,
2617 ALTIVEC_BUILTIN_VUPKLPX,
2618 ALTIVEC_BUILTIN_VUPKLSH,
2619 ALTIVEC_BUILTIN_MTVSCR,
2620 ALTIVEC_BUILTIN_MFVSCR,
2621 ALTIVEC_BUILTIN_DSSALL,
2622 ALTIVEC_BUILTIN_DSS,
2623 ALTIVEC_BUILTIN_LVSL,
2624 ALTIVEC_BUILTIN_LVSR,
2625 ALTIVEC_BUILTIN_DSTT,
2626 ALTIVEC_BUILTIN_DSTST,
2627 ALTIVEC_BUILTIN_DSTSTT,
2628 ALTIVEC_BUILTIN_DST,
2629 ALTIVEC_BUILTIN_LVEBX,
2630 ALTIVEC_BUILTIN_LVEHX,
2631 ALTIVEC_BUILTIN_LVEWX,
2632 ALTIVEC_BUILTIN_LVXL,
2633 ALTIVEC_BUILTIN_LVX,
2634 ALTIVEC_BUILTIN_STVX,
2635 ALTIVEC_BUILTIN_LVLX,
2636 ALTIVEC_BUILTIN_LVLXL,
2637 ALTIVEC_BUILTIN_LVRX,
2638 ALTIVEC_BUILTIN_LVRXL,
2639 ALTIVEC_BUILTIN_STVEBX,
2640 ALTIVEC_BUILTIN_STVEHX,
2641 ALTIVEC_BUILTIN_STVEWX,
2642 ALTIVEC_BUILTIN_STVXL,
2643 ALTIVEC_BUILTIN_STVLX,
2644 ALTIVEC_BUILTIN_STVLXL,
2645 ALTIVEC_BUILTIN_STVRX,
2646 ALTIVEC_BUILTIN_STVRXL,
2647 ALTIVEC_BUILTIN_VCMPBFP_P,
2648 ALTIVEC_BUILTIN_VCMPEQFP_P,
2649 ALTIVEC_BUILTIN_VCMPEQUB_P,
2650 ALTIVEC_BUILTIN_VCMPEQUH_P,
2651 ALTIVEC_BUILTIN_VCMPEQUW_P,
2652 ALTIVEC_BUILTIN_VCMPGEFP_P,
2653 ALTIVEC_BUILTIN_VCMPGTFP_P,
2654 ALTIVEC_BUILTIN_VCMPGTSB_P,
2655 ALTIVEC_BUILTIN_VCMPGTSH_P,
2656 ALTIVEC_BUILTIN_VCMPGTSW_P,
2657 ALTIVEC_BUILTIN_VCMPGTUB_P,
2658 ALTIVEC_BUILTIN_VCMPGTUH_P,
2659 ALTIVEC_BUILTIN_VCMPGTUW_P,
2660 ALTIVEC_BUILTIN_ABSS_V4SI,
2661 ALTIVEC_BUILTIN_ABSS_V8HI,
2662 ALTIVEC_BUILTIN_ABSS_V16QI,
2663 ALTIVEC_BUILTIN_ABS_V4SI,
2664 ALTIVEC_BUILTIN_ABS_V4SF,
2665 ALTIVEC_BUILTIN_ABS_V8HI,
2666 ALTIVEC_BUILTIN_ABS_V16QI,
2667 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
2668 ALTIVEC_BUILTIN_MASK_FOR_STORE,
2669 ALTIVEC_BUILTIN_VEC_INIT_V4SI,
2670 ALTIVEC_BUILTIN_VEC_INIT_V8HI,
2671 ALTIVEC_BUILTIN_VEC_INIT_V16QI,
2672 ALTIVEC_BUILTIN_VEC_INIT_V4SF,
2673 ALTIVEC_BUILTIN_VEC_SET_V4SI,
2674 ALTIVEC_BUILTIN_VEC_SET_V8HI,
2675 ALTIVEC_BUILTIN_VEC_SET_V16QI,
2676 ALTIVEC_BUILTIN_VEC_SET_V4SF,
2677 ALTIVEC_BUILTIN_VEC_EXT_V4SI,
2678 ALTIVEC_BUILTIN_VEC_EXT_V8HI,
2679 ALTIVEC_BUILTIN_VEC_EXT_V16QI,
2680 ALTIVEC_BUILTIN_VEC_EXT_V4SF,
2682 /* Altivec overloaded builtins. */
2683 ALTIVEC_BUILTIN_VCMPEQ_P,
2684 ALTIVEC_BUILTIN_OVERLOADED_FIRST = ALTIVEC_BUILTIN_VCMPEQ_P,
2685 ALTIVEC_BUILTIN_VCMPGT_P,
2686 ALTIVEC_BUILTIN_VCMPGE_P,
2687 ALTIVEC_BUILTIN_VEC_ABS,
2688 ALTIVEC_BUILTIN_VEC_ABSS,
2689 ALTIVEC_BUILTIN_VEC_ADD,
2690 ALTIVEC_BUILTIN_VEC_ADDC,
2691 ALTIVEC_BUILTIN_VEC_ADDS,
2692 ALTIVEC_BUILTIN_VEC_AND,
2693 ALTIVEC_BUILTIN_VEC_ANDC,
2694 ALTIVEC_BUILTIN_VEC_AVG,
2695 ALTIVEC_BUILTIN_VEC_EXTRACT,
2696 ALTIVEC_BUILTIN_VEC_CEIL,
2697 ALTIVEC_BUILTIN_VEC_CMPB,
2698 ALTIVEC_BUILTIN_VEC_CMPEQ,
2699 ALTIVEC_BUILTIN_VEC_CMPEQUB,
2700 ALTIVEC_BUILTIN_VEC_CMPEQUH,
2701 ALTIVEC_BUILTIN_VEC_CMPEQUW,
2702 ALTIVEC_BUILTIN_VEC_CMPGE,
2703 ALTIVEC_BUILTIN_VEC_CMPGT,
2704 ALTIVEC_BUILTIN_VEC_CMPLE,
2705 ALTIVEC_BUILTIN_VEC_CMPLT,
2706 ALTIVEC_BUILTIN_VEC_CTF,
2707 ALTIVEC_BUILTIN_VEC_CTS,
2708 ALTIVEC_BUILTIN_VEC_CTU,
2709 ALTIVEC_BUILTIN_VEC_DST,
2710 ALTIVEC_BUILTIN_VEC_DSTST,
2711 ALTIVEC_BUILTIN_VEC_DSTSTT,
2712 ALTIVEC_BUILTIN_VEC_DSTT,
2713 ALTIVEC_BUILTIN_VEC_EXPTE,
2714 ALTIVEC_BUILTIN_VEC_FLOOR,
2715 ALTIVEC_BUILTIN_VEC_LD,
2716 ALTIVEC_BUILTIN_VEC_LDE,
2717 ALTIVEC_BUILTIN_VEC_LDL,
2718 ALTIVEC_BUILTIN_VEC_LOGE,
2719 ALTIVEC_BUILTIN_VEC_LVEBX,
2720 ALTIVEC_BUILTIN_VEC_LVEHX,
2721 ALTIVEC_BUILTIN_VEC_LVEWX,
2722 ALTIVEC_BUILTIN_VEC_LVLX,
2723 ALTIVEC_BUILTIN_VEC_LVLXL,
2724 ALTIVEC_BUILTIN_VEC_LVRX,
2725 ALTIVEC_BUILTIN_VEC_LVRXL,
2726 ALTIVEC_BUILTIN_VEC_LVSL,
2727 ALTIVEC_BUILTIN_VEC_LVSR,
2728 ALTIVEC_BUILTIN_VEC_MADD,
2729 ALTIVEC_BUILTIN_VEC_MADDS,
2730 ALTIVEC_BUILTIN_VEC_MAX,
2731 ALTIVEC_BUILTIN_VEC_MERGEH,
2732 ALTIVEC_BUILTIN_VEC_MERGEL,
2733 ALTIVEC_BUILTIN_VEC_MIN,
2734 ALTIVEC_BUILTIN_VEC_MLADD,
2735 ALTIVEC_BUILTIN_VEC_MPERM,
2736 ALTIVEC_BUILTIN_VEC_MRADDS,
2737 ALTIVEC_BUILTIN_VEC_MRGHB,
2738 ALTIVEC_BUILTIN_VEC_MRGHH,
2739 ALTIVEC_BUILTIN_VEC_MRGHW,
2740 ALTIVEC_BUILTIN_VEC_MRGLB,
2741 ALTIVEC_BUILTIN_VEC_MRGLH,
2742 ALTIVEC_BUILTIN_VEC_MRGLW,
2743 ALTIVEC_BUILTIN_VEC_MSUM,
2744 ALTIVEC_BUILTIN_VEC_MSUMS,
2745 ALTIVEC_BUILTIN_VEC_MTVSCR,
2746 ALTIVEC_BUILTIN_VEC_MULE,
2747 ALTIVEC_BUILTIN_VEC_MULO,
2748 ALTIVEC_BUILTIN_VEC_NMSUB,
2749 ALTIVEC_BUILTIN_VEC_NOR,
2750 ALTIVEC_BUILTIN_VEC_OR,
2751 ALTIVEC_BUILTIN_VEC_PACK,
2752 ALTIVEC_BUILTIN_VEC_PACKPX,
2753 ALTIVEC_BUILTIN_VEC_PACKS,
2754 ALTIVEC_BUILTIN_VEC_PACKSU,
2755 ALTIVEC_BUILTIN_VEC_PERM,
2756 ALTIVEC_BUILTIN_VEC_RE,
2757 ALTIVEC_BUILTIN_VEC_RL,
2758 ALTIVEC_BUILTIN_VEC_ROUND,
2759 ALTIVEC_BUILTIN_VEC_RSQRTE,
2760 ALTIVEC_BUILTIN_VEC_SEL,
2761 ALTIVEC_BUILTIN_VEC_SL,
2762 ALTIVEC_BUILTIN_VEC_SLD,
2763 ALTIVEC_BUILTIN_VEC_SLL,
2764 ALTIVEC_BUILTIN_VEC_SLO,
2765 ALTIVEC_BUILTIN_VEC_SPLAT,
2766 ALTIVEC_BUILTIN_VEC_SPLAT_S16,
2767 ALTIVEC_BUILTIN_VEC_SPLAT_S32,
2768 ALTIVEC_BUILTIN_VEC_SPLAT_S8,
2769 ALTIVEC_BUILTIN_VEC_SPLAT_U16,
2770 ALTIVEC_BUILTIN_VEC_SPLAT_U32,
2771 ALTIVEC_BUILTIN_VEC_SPLAT_U8,
2772 ALTIVEC_BUILTIN_VEC_SPLTB,
2773 ALTIVEC_BUILTIN_VEC_SPLTH,
2774 ALTIVEC_BUILTIN_VEC_SPLTW,
2775 ALTIVEC_BUILTIN_VEC_SR,
2776 ALTIVEC_BUILTIN_VEC_SRA,
2777 ALTIVEC_BUILTIN_VEC_SRL,
2778 ALTIVEC_BUILTIN_VEC_SRO,
2779 ALTIVEC_BUILTIN_VEC_ST,
2780 ALTIVEC_BUILTIN_VEC_STE,
2781 ALTIVEC_BUILTIN_VEC_STL,
2782 ALTIVEC_BUILTIN_VEC_STVEBX,
2783 ALTIVEC_BUILTIN_VEC_STVEHX,
2784 ALTIVEC_BUILTIN_VEC_STVEWX,
2785 ALTIVEC_BUILTIN_VEC_STVLX,
2786 ALTIVEC_BUILTIN_VEC_STVLXL,
2787 ALTIVEC_BUILTIN_VEC_STVRX,
2788 ALTIVEC_BUILTIN_VEC_STVRXL,
2789 ALTIVEC_BUILTIN_VEC_SUB,
2790 ALTIVEC_BUILTIN_VEC_SUBC,
2791 ALTIVEC_BUILTIN_VEC_SUBS,
2792 ALTIVEC_BUILTIN_VEC_SUM2S,
2793 ALTIVEC_BUILTIN_VEC_SUM4S,
2794 ALTIVEC_BUILTIN_VEC_SUMS,
2795 ALTIVEC_BUILTIN_VEC_TRUNC,
2796 ALTIVEC_BUILTIN_VEC_UNPACKH,
2797 ALTIVEC_BUILTIN_VEC_UNPACKL,
2798 ALTIVEC_BUILTIN_VEC_VADDFP,
2799 ALTIVEC_BUILTIN_VEC_VADDSBS,
2800 ALTIVEC_BUILTIN_VEC_VADDSHS,
2801 ALTIVEC_BUILTIN_VEC_VADDSWS,
2802 ALTIVEC_BUILTIN_VEC_VADDUBM,
2803 ALTIVEC_BUILTIN_VEC_VADDUBS,
2804 ALTIVEC_BUILTIN_VEC_VADDUHM,
2805 ALTIVEC_BUILTIN_VEC_VADDUHS,
2806 ALTIVEC_BUILTIN_VEC_VADDUWM,
2807 ALTIVEC_BUILTIN_VEC_VADDUWS,
2808 ALTIVEC_BUILTIN_VEC_VAVGSB,
2809 ALTIVEC_BUILTIN_VEC_VAVGSH,
2810 ALTIVEC_BUILTIN_VEC_VAVGSW,
2811 ALTIVEC_BUILTIN_VEC_VAVGUB,
2812 ALTIVEC_BUILTIN_VEC_VAVGUH,
2813 ALTIVEC_BUILTIN_VEC_VAVGUW,
2814 ALTIVEC_BUILTIN_VEC_VCFSX,
2815 ALTIVEC_BUILTIN_VEC_VCFUX,
2816 ALTIVEC_BUILTIN_VEC_VCMPEQFP,
2817 ALTIVEC_BUILTIN_VEC_VCMPEQUB,
2818 ALTIVEC_BUILTIN_VEC_VCMPEQUH,
2819 ALTIVEC_BUILTIN_VEC_VCMPEQUW,
2820 ALTIVEC_BUILTIN_VEC_VCMPGTFP,
2821 ALTIVEC_BUILTIN_VEC_VCMPGTSB,
2822 ALTIVEC_BUILTIN_VEC_VCMPGTSH,
2823 ALTIVEC_BUILTIN_VEC_VCMPGTSW,
2824 ALTIVEC_BUILTIN_VEC_VCMPGTUB,
2825 ALTIVEC_BUILTIN_VEC_VCMPGTUH,
2826 ALTIVEC_BUILTIN_VEC_VCMPGTUW,
2827 ALTIVEC_BUILTIN_VEC_VMAXFP,
2828 ALTIVEC_BUILTIN_VEC_VMAXSB,
2829 ALTIVEC_BUILTIN_VEC_VMAXSH,
2830 ALTIVEC_BUILTIN_VEC_VMAXSW,
2831 ALTIVEC_BUILTIN_VEC_VMAXUB,
2832 ALTIVEC_BUILTIN_VEC_VMAXUH,
2833 ALTIVEC_BUILTIN_VEC_VMAXUW,
2834 ALTIVEC_BUILTIN_VEC_VMINFP,
2835 ALTIVEC_BUILTIN_VEC_VMINSB,
2836 ALTIVEC_BUILTIN_VEC_VMINSH,
2837 ALTIVEC_BUILTIN_VEC_VMINSW,
2838 ALTIVEC_BUILTIN_VEC_VMINUB,
2839 ALTIVEC_BUILTIN_VEC_VMINUH,
2840 ALTIVEC_BUILTIN_VEC_VMINUW,
2841 ALTIVEC_BUILTIN_VEC_VMRGHB,
2842 ALTIVEC_BUILTIN_VEC_VMRGHH,
2843 ALTIVEC_BUILTIN_VEC_VMRGHW,
2844 ALTIVEC_BUILTIN_VEC_VMRGLB,
2845 ALTIVEC_BUILTIN_VEC_VMRGLH,
2846 ALTIVEC_BUILTIN_VEC_VMRGLW,
2847 ALTIVEC_BUILTIN_VEC_VMSUMMBM,
2848 ALTIVEC_BUILTIN_VEC_VMSUMSHM,
2849 ALTIVEC_BUILTIN_VEC_VMSUMSHS,
2850 ALTIVEC_BUILTIN_VEC_VMSUMUBM,
2851 ALTIVEC_BUILTIN_VEC_VMSUMUHM,
2852 ALTIVEC_BUILTIN_VEC_VMSUMUHS,
2853 ALTIVEC_BUILTIN_VEC_VMULESB,
2854 ALTIVEC_BUILTIN_VEC_VMULESH,
2855 ALTIVEC_BUILTIN_VEC_VMULEUB,
2856 ALTIVEC_BUILTIN_VEC_VMULEUH,
2857 ALTIVEC_BUILTIN_VEC_VMULOSB,
2858 ALTIVEC_BUILTIN_VEC_VMULOSH,
2859 ALTIVEC_BUILTIN_VEC_VMULOUB,
2860 ALTIVEC_BUILTIN_VEC_VMULOUH,
2861 ALTIVEC_BUILTIN_VEC_VPKSHSS,
2862 ALTIVEC_BUILTIN_VEC_VPKSHUS,
2863 ALTIVEC_BUILTIN_VEC_VPKSWSS,
2864 ALTIVEC_BUILTIN_VEC_VPKSWUS,
2865 ALTIVEC_BUILTIN_VEC_VPKUHUM,
2866 ALTIVEC_BUILTIN_VEC_VPKUHUS,
2867 ALTIVEC_BUILTIN_VEC_VPKUWUM,
2868 ALTIVEC_BUILTIN_VEC_VPKUWUS,
2869 ALTIVEC_BUILTIN_VEC_VRLB,
2870 ALTIVEC_BUILTIN_VEC_VRLH,
2871 ALTIVEC_BUILTIN_VEC_VRLW,
2872 ALTIVEC_BUILTIN_VEC_VSLB,
2873 ALTIVEC_BUILTIN_VEC_VSLH,
2874 ALTIVEC_BUILTIN_VEC_VSLW,
2875 ALTIVEC_BUILTIN_VEC_VSPLTB,
2876 ALTIVEC_BUILTIN_VEC_VSPLTH,
2877 ALTIVEC_BUILTIN_VEC_VSPLTW,
2878 ALTIVEC_BUILTIN_VEC_VSRAB,
2879 ALTIVEC_BUILTIN_VEC_VSRAH,
2880 ALTIVEC_BUILTIN_VEC_VSRAW,
2881 ALTIVEC_BUILTIN_VEC_VSRB,
2882 ALTIVEC_BUILTIN_VEC_VSRH,
2883 ALTIVEC_BUILTIN_VEC_VSRW,
2884 ALTIVEC_BUILTIN_VEC_VSUBFP,
2885 ALTIVEC_BUILTIN_VEC_VSUBSBS,
2886 ALTIVEC_BUILTIN_VEC_VSUBSHS,
2887 ALTIVEC_BUILTIN_VEC_VSUBSWS,
2888 ALTIVEC_BUILTIN_VEC_VSUBUBM,
2889 ALTIVEC_BUILTIN_VEC_VSUBUBS,
2890 ALTIVEC_BUILTIN_VEC_VSUBUHM,
2891 ALTIVEC_BUILTIN_VEC_VSUBUHS,
2892 ALTIVEC_BUILTIN_VEC_VSUBUWM,
2893 ALTIVEC_BUILTIN_VEC_VSUBUWS,
2894 ALTIVEC_BUILTIN_VEC_VSUM4SBS,
2895 ALTIVEC_BUILTIN_VEC_VSUM4SHS,
2896 ALTIVEC_BUILTIN_VEC_VSUM4UBS,
2897 ALTIVEC_BUILTIN_VEC_VUPKHPX,
2898 ALTIVEC_BUILTIN_VEC_VUPKHSB,
2899 ALTIVEC_BUILTIN_VEC_VUPKHSH,
2900 ALTIVEC_BUILTIN_VEC_VUPKLPX,
2901 ALTIVEC_BUILTIN_VEC_VUPKLSB,
2902 ALTIVEC_BUILTIN_VEC_VUPKLSH,
2903 ALTIVEC_BUILTIN_VEC_XOR,
2904 ALTIVEC_BUILTIN_VEC_STEP,
2905 ALTIVEC_BUILTIN_VEC_PROMOTE,
2906 ALTIVEC_BUILTIN_VEC_INSERT,
2907 ALTIVEC_BUILTIN_VEC_SPLATS,
2908 ALTIVEC_BUILTIN_OVERLOADED_LAST = ALTIVEC_BUILTIN_VEC_SPLATS,
2914 SPE_BUILTIN_EVDIVWS,
2915 SPE_BUILTIN_EVDIVWU,
2917 SPE_BUILTIN_EVFSADD,
2918 SPE_BUILTIN_EVFSDIV,
2919 SPE_BUILTIN_EVFSMUL,
2920 SPE_BUILTIN_EVFSSUB,
2924 SPE_BUILTIN_EVLHHESPLATX,
2925 SPE_BUILTIN_EVLHHOSSPLATX,
2926 SPE_BUILTIN_EVLHHOUSPLATX,
2927 SPE_BUILTIN_EVLWHEX,
2928 SPE_BUILTIN_EVLWHOSX,
2929 SPE_BUILTIN_EVLWHOUX,
2930 SPE_BUILTIN_EVLWHSPLATX,
2931 SPE_BUILTIN_EVLWWSPLATX,
2932 SPE_BUILTIN_EVMERGEHI,
2933 SPE_BUILTIN_EVMERGEHILO,
2934 SPE_BUILTIN_EVMERGELO,
2935 SPE_BUILTIN_EVMERGELOHI,
2936 SPE_BUILTIN_EVMHEGSMFAA,
2937 SPE_BUILTIN_EVMHEGSMFAN,
2938 SPE_BUILTIN_EVMHEGSMIAA,
2939 SPE_BUILTIN_EVMHEGSMIAN,
2940 SPE_BUILTIN_EVMHEGUMIAA,
2941 SPE_BUILTIN_EVMHEGUMIAN,
2942 SPE_BUILTIN_EVMHESMF,
2943 SPE_BUILTIN_EVMHESMFA,
2944 SPE_BUILTIN_EVMHESMFAAW,
2945 SPE_BUILTIN_EVMHESMFANW,
2946 SPE_BUILTIN_EVMHESMI,
2947 SPE_BUILTIN_EVMHESMIA,
2948 SPE_BUILTIN_EVMHESMIAAW,
2949 SPE_BUILTIN_EVMHESMIANW,
2950 SPE_BUILTIN_EVMHESSF,
2951 SPE_BUILTIN_EVMHESSFA,
2952 SPE_BUILTIN_EVMHESSFAAW,
2953 SPE_BUILTIN_EVMHESSFANW,
2954 SPE_BUILTIN_EVMHESSIAAW,
2955 SPE_BUILTIN_EVMHESSIANW,
2956 SPE_BUILTIN_EVMHEUMI,
2957 SPE_BUILTIN_EVMHEUMIA,
2958 SPE_BUILTIN_EVMHEUMIAAW,
2959 SPE_BUILTIN_EVMHEUMIANW,
2960 SPE_BUILTIN_EVMHEUSIAAW,
2961 SPE_BUILTIN_EVMHEUSIANW,
2962 SPE_BUILTIN_EVMHOGSMFAA,
2963 SPE_BUILTIN_EVMHOGSMFAN,
2964 SPE_BUILTIN_EVMHOGSMIAA,
2965 SPE_BUILTIN_EVMHOGSMIAN,
2966 SPE_BUILTIN_EVMHOGUMIAA,
2967 SPE_BUILTIN_EVMHOGUMIAN,
2968 SPE_BUILTIN_EVMHOSMF,
2969 SPE_BUILTIN_EVMHOSMFA,
2970 SPE_BUILTIN_EVMHOSMFAAW,
2971 SPE_BUILTIN_EVMHOSMFANW,
2972 SPE_BUILTIN_EVMHOSMI,
2973 SPE_BUILTIN_EVMHOSMIA,
2974 SPE_BUILTIN_EVMHOSMIAAW,
2975 SPE_BUILTIN_EVMHOSMIANW,
2976 SPE_BUILTIN_EVMHOSSF,
2977 SPE_BUILTIN_EVMHOSSFA,
2978 SPE_BUILTIN_EVMHOSSFAAW,
2979 SPE_BUILTIN_EVMHOSSFANW,
2980 SPE_BUILTIN_EVMHOSSIAAW,
2981 SPE_BUILTIN_EVMHOSSIANW,
2982 SPE_BUILTIN_EVMHOUMI,
2983 SPE_BUILTIN_EVMHOUMIA,
2984 SPE_BUILTIN_EVMHOUMIAAW,
2985 SPE_BUILTIN_EVMHOUMIANW,
2986 SPE_BUILTIN_EVMHOUSIAAW,
2987 SPE_BUILTIN_EVMHOUSIANW,
2988 SPE_BUILTIN_EVMWHSMF,
2989 SPE_BUILTIN_EVMWHSMFA,
2990 SPE_BUILTIN_EVMWHSMI,
2991 SPE_BUILTIN_EVMWHSMIA,
2992 SPE_BUILTIN_EVMWHSSF,
2993 SPE_BUILTIN_EVMWHSSFA,
2994 SPE_BUILTIN_EVMWHUMI,
2995 SPE_BUILTIN_EVMWHUMIA,
2996 SPE_BUILTIN_EVMWLSMIAAW,
2997 SPE_BUILTIN_EVMWLSMIANW,
2998 SPE_BUILTIN_EVMWLSSIAAW,
2999 SPE_BUILTIN_EVMWLSSIANW,
3000 SPE_BUILTIN_EVMWLUMI,
3001 SPE_BUILTIN_EVMWLUMIA,
3002 SPE_BUILTIN_EVMWLUMIAAW,
3003 SPE_BUILTIN_EVMWLUMIANW,
3004 SPE_BUILTIN_EVMWLUSIAAW,
3005 SPE_BUILTIN_EVMWLUSIANW,
3006 SPE_BUILTIN_EVMWSMF,
3007 SPE_BUILTIN_EVMWSMFA,
3008 SPE_BUILTIN_EVMWSMFAA,
3009 SPE_BUILTIN_EVMWSMFAN,
3010 SPE_BUILTIN_EVMWSMI,
3011 SPE_BUILTIN_EVMWSMIA,
3012 SPE_BUILTIN_EVMWSMIAA,
3013 SPE_BUILTIN_EVMWSMIAN,
3014 SPE_BUILTIN_EVMWHSSFAA,
3015 SPE_BUILTIN_EVMWSSF,
3016 SPE_BUILTIN_EVMWSSFA,
3017 SPE_BUILTIN_EVMWSSFAA,
3018 SPE_BUILTIN_EVMWSSFAN,
3019 SPE_BUILTIN_EVMWUMI,
3020 SPE_BUILTIN_EVMWUMIA,
3021 SPE_BUILTIN_EVMWUMIAA,
3022 SPE_BUILTIN_EVMWUMIAN,
3031 SPE_BUILTIN_EVSTDDX,
3032 SPE_BUILTIN_EVSTDHX,
3033 SPE_BUILTIN_EVSTDWX,
3034 SPE_BUILTIN_EVSTWHEX,
3035 SPE_BUILTIN_EVSTWHOX,
3036 SPE_BUILTIN_EVSTWWEX,
3037 SPE_BUILTIN_EVSTWWOX,
3038 SPE_BUILTIN_EVSUBFW,
3041 SPE_BUILTIN_EVADDSMIAAW,
3042 SPE_BUILTIN_EVADDSSIAAW,
3043 SPE_BUILTIN_EVADDUMIAAW,
3044 SPE_BUILTIN_EVADDUSIAAW,
3045 SPE_BUILTIN_EVCNTLSW,
3046 SPE_BUILTIN_EVCNTLZW,
3047 SPE_BUILTIN_EVEXTSB,
3048 SPE_BUILTIN_EVEXTSH,
3049 SPE_BUILTIN_EVFSABS,
3050 SPE_BUILTIN_EVFSCFSF,
3051 SPE_BUILTIN_EVFSCFSI,
3052 SPE_BUILTIN_EVFSCFUF,
3053 SPE_BUILTIN_EVFSCFUI,
3054 SPE_BUILTIN_EVFSCTSF,
3055 SPE_BUILTIN_EVFSCTSI,
3056 SPE_BUILTIN_EVFSCTSIZ,
3057 SPE_BUILTIN_EVFSCTUF,
3058 SPE_BUILTIN_EVFSCTUI,
3059 SPE_BUILTIN_EVFSCTUIZ,
3060 SPE_BUILTIN_EVFSNABS,
3061 SPE_BUILTIN_EVFSNEG,
3065 SPE_BUILTIN_EVSUBFSMIAAW,
3066 SPE_BUILTIN_EVSUBFSSIAAW,
3067 SPE_BUILTIN_EVSUBFUMIAAW,
3068 SPE_BUILTIN_EVSUBFUSIAAW,
3069 SPE_BUILTIN_EVADDIW,
3073 SPE_BUILTIN_EVLHHESPLAT,
3074 SPE_BUILTIN_EVLHHOSSPLAT,
3075 SPE_BUILTIN_EVLHHOUSPLAT,
3077 SPE_BUILTIN_EVLWHOS,
3078 SPE_BUILTIN_EVLWHOU,
3079 SPE_BUILTIN_EVLWHSPLAT,
3080 SPE_BUILTIN_EVLWWSPLAT,
3083 SPE_BUILTIN_EVSRWIS,
3084 SPE_BUILTIN_EVSRWIU,
3088 SPE_BUILTIN_EVSTWHE,
3089 SPE_BUILTIN_EVSTWHO,
3090 SPE_BUILTIN_EVSTWWE,
3091 SPE_BUILTIN_EVSTWWO,
3092 SPE_BUILTIN_EVSUBIFW,
3095 SPE_BUILTIN_EVCMPEQ,
3096 SPE_BUILTIN_EVCMPGTS,
3097 SPE_BUILTIN_EVCMPGTU,
3098 SPE_BUILTIN_EVCMPLTS,
3099 SPE_BUILTIN_EVCMPLTU,
3100 SPE_BUILTIN_EVFSCMPEQ,
3101 SPE_BUILTIN_EVFSCMPGT,
3102 SPE_BUILTIN_EVFSCMPLT,
3103 SPE_BUILTIN_EVFSTSTEQ,
3104 SPE_BUILTIN_EVFSTSTGT,
3105 SPE_BUILTIN_EVFSTSTLT,
3107 /* EVSEL compares. */
3108 SPE_BUILTIN_EVSEL_CMPEQ,
3109 SPE_BUILTIN_EVSEL_CMPGTS,
3110 SPE_BUILTIN_EVSEL_CMPGTU,
3111 SPE_BUILTIN_EVSEL_CMPLTS,
3112 SPE_BUILTIN_EVSEL_CMPLTU,
3113 SPE_BUILTIN_EVSEL_FSCMPEQ,
3114 SPE_BUILTIN_EVSEL_FSCMPGT,
3115 SPE_BUILTIN_EVSEL_FSCMPLT,
3116 SPE_BUILTIN_EVSEL_FSTSTEQ,
3117 SPE_BUILTIN_EVSEL_FSTSTGT,
3118 SPE_BUILTIN_EVSEL_FSTSTLT,
3120 SPE_BUILTIN_EVSPLATFI,
3121 SPE_BUILTIN_EVSPLATI,
3122 SPE_BUILTIN_EVMWHSSMAA,
3123 SPE_BUILTIN_EVMWHSMFAA,
3124 SPE_BUILTIN_EVMWHSMIAA,
3125 SPE_BUILTIN_EVMWHUSIAA,
3126 SPE_BUILTIN_EVMWHUMIAA,
3127 SPE_BUILTIN_EVMWHSSFAN,
3128 SPE_BUILTIN_EVMWHSSIAN,
3129 SPE_BUILTIN_EVMWHSMFAN,
3130 SPE_BUILTIN_EVMWHSMIAN,
3131 SPE_BUILTIN_EVMWHUSIAN,
3132 SPE_BUILTIN_EVMWHUMIAN,
3133 SPE_BUILTIN_EVMWHGSSFAA,
3134 SPE_BUILTIN_EVMWHGSMFAA,
3135 SPE_BUILTIN_EVMWHGSMIAA,
3136 SPE_BUILTIN_EVMWHGUMIAA,
3137 SPE_BUILTIN_EVMWHGSSFAN,
3138 SPE_BUILTIN_EVMWHGSMFAN,
3139 SPE_BUILTIN_EVMWHGSMIAN,
3140 SPE_BUILTIN_EVMWHGUMIAN,
3141 SPE_BUILTIN_MTSPEFSCR,
3142 SPE_BUILTIN_MFSPEFSCR,
3145 /* PAIRED builtins. */
3146 PAIRED_BUILTIN_DIVV2SF3,
3147 PAIRED_BUILTIN_ABSV2SF2,
3148 PAIRED_BUILTIN_NEGV2SF2,
3149 PAIRED_BUILTIN_SQRTV2SF2,
3150 PAIRED_BUILTIN_ADDV2SF3,
3151 PAIRED_BUILTIN_SUBV2SF3,
3152 PAIRED_BUILTIN_RESV2SF2,
3153 PAIRED_BUILTIN_MULV2SF3,
3154 PAIRED_BUILTIN_MSUB,
3155 PAIRED_BUILTIN_MADD,
3156 PAIRED_BUILTIN_NMSUB,
3157 PAIRED_BUILTIN_NMADD,
3158 PAIRED_BUILTIN_NABSV2SF2,
3159 PAIRED_BUILTIN_SUM0,
3160 PAIRED_BUILTIN_SUM1,
3161 PAIRED_BUILTIN_MULS0,
3162 PAIRED_BUILTIN_MULS1,
3163 PAIRED_BUILTIN_MERGE00,
3164 PAIRED_BUILTIN_MERGE01,
3165 PAIRED_BUILTIN_MERGE10,
3166 PAIRED_BUILTIN_MERGE11,
3167 PAIRED_BUILTIN_MADDS0,
3168 PAIRED_BUILTIN_MADDS1,
3171 PAIRED_BUILTIN_SELV2SF4,
3172 PAIRED_BUILTIN_CMPU0,
3173 PAIRED_BUILTIN_CMPU1,
3175 RS6000_BUILTIN_RECIP,
3176 RS6000_BUILTIN_RECIPF,
3177 RS6000_BUILTIN_RSQRTF,
3178 RS6000_BUILTIN_BSWAP_HI,
3183 VSX_BUILTIN_LXVD2UX,
3186 VSX_BUILTIN_LXVW4UX,
3188 VSX_BUILTIN_STXSDUX,
3190 VSX_BUILTIN_STXVD2UX,
3191 VSX_BUILTIN_STXVD2X,
3192 VSX_BUILTIN_STXVW4UX,
3193 VSX_BUILTIN_STXVW4X,
3194 VSX_BUILTIN_XSABSDP,
3195 VSX_BUILTIN_XSADDDP,
3196 VSX_BUILTIN_XSCMPODP,
3197 VSX_BUILTIN_XSCMPUDP,
3198 VSX_BUILTIN_XSCPSGNDP,
3199 VSX_BUILTIN_XSCVDPSP,
3200 VSX_BUILTIN_XSCVDPSXDS,
3201 VSX_BUILTIN_XSCVDPSXWS,
3202 VSX_BUILTIN_XSCVDPUXDS,
3203 VSX_BUILTIN_XSCVDPUXWS,
3204 VSX_BUILTIN_XSCVSPDP,
3205 VSX_BUILTIN_XSCVSXDDP,
3206 VSX_BUILTIN_XSCVUXDDP,
3207 VSX_BUILTIN_XSDIVDP,
3208 VSX_BUILTIN_XSMADDADP,
3209 VSX_BUILTIN_XSMADDMDP,
3210 VSX_BUILTIN_XSMAXDP,
3211 VSX_BUILTIN_XSMINDP,
3212 VSX_BUILTIN_XSMOVDP,
3213 VSX_BUILTIN_XSMSUBADP,
3214 VSX_BUILTIN_XSMSUBMDP,
3215 VSX_BUILTIN_XSMULDP,
3216 VSX_BUILTIN_XSNABSDP,
3217 VSX_BUILTIN_XSNEGDP,
3218 VSX_BUILTIN_XSNMADDADP,
3219 VSX_BUILTIN_XSNMADDMDP,
3220 VSX_BUILTIN_XSNMSUBADP,
3221 VSX_BUILTIN_XSNMSUBMDP,
3223 VSX_BUILTIN_XSRDPIC,
3224 VSX_BUILTIN_XSRDPIM,
3225 VSX_BUILTIN_XSRDPIP,
3226 VSX_BUILTIN_XSRDPIZ,
3228 VSX_BUILTIN_XSRSQRTEDP,
3229 VSX_BUILTIN_XSSQRTDP,
3230 VSX_BUILTIN_XSSUBDP,
3231 VSX_BUILTIN_XSTDIVDP_FE,
3232 VSX_BUILTIN_XSTDIVDP_FG,
3233 VSX_BUILTIN_XSTSQRTDP_FE,
3234 VSX_BUILTIN_XSTSQRTDP_FG,
3235 VSX_BUILTIN_XVABSDP,
3236 VSX_BUILTIN_XVABSSP,
3237 VSX_BUILTIN_XVADDDP,
3238 VSX_BUILTIN_XVADDSP,
3239 VSX_BUILTIN_XVCMPEQDP,
3240 VSX_BUILTIN_XVCMPEQSP,
3241 VSX_BUILTIN_XVCMPGEDP,
3242 VSX_BUILTIN_XVCMPGESP,
3243 VSX_BUILTIN_XVCMPGTDP,
3244 VSX_BUILTIN_XVCMPGTSP,
3245 VSX_BUILTIN_XVCMPEQDP_P,
3246 VSX_BUILTIN_XVCMPEQSP_P,
3247 VSX_BUILTIN_XVCMPGEDP_P,
3248 VSX_BUILTIN_XVCMPGESP_P,
3249 VSX_BUILTIN_XVCMPGTDP_P,
3250 VSX_BUILTIN_XVCMPGTSP_P,
3251 VSX_BUILTIN_XVCPSGNDP,
3252 VSX_BUILTIN_XVCPSGNSP,
3253 VSX_BUILTIN_XVCVDPSP,
3254 VSX_BUILTIN_XVCVDPSXDS,
3255 VSX_BUILTIN_XVCVDPSXWS,
3256 VSX_BUILTIN_XVCVDPUXDS,
3257 VSX_BUILTIN_XVCVDPUXDS_UNS,
3258 VSX_BUILTIN_XVCVDPUXWS,
3259 VSX_BUILTIN_XVCVSPDP,
3260 VSX_BUILTIN_XVCVSPSXDS,
3261 VSX_BUILTIN_XVCVSPSXWS,
3262 VSX_BUILTIN_XVCVSPUXDS,
3263 VSX_BUILTIN_XVCVSPUXWS,
3264 VSX_BUILTIN_XVCVSXDDP,
3265 VSX_BUILTIN_XVCVSXDSP,
3266 VSX_BUILTIN_XVCVSXWDP,
3267 VSX_BUILTIN_XVCVSXWSP,
3268 VSX_BUILTIN_XVCVUXDDP,
3269 VSX_BUILTIN_XVCVUXDDP_UNS,
3270 VSX_BUILTIN_XVCVUXDSP,
3271 VSX_BUILTIN_XVCVUXWDP,
3272 VSX_BUILTIN_XVCVUXWSP,
3273 VSX_BUILTIN_XVDIVDP,
3274 VSX_BUILTIN_XVDIVSP,
3275 VSX_BUILTIN_XVMADDDP,
3276 VSX_BUILTIN_XVMADDSP,
3277 VSX_BUILTIN_XVMAXDP,
3278 VSX_BUILTIN_XVMAXSP,
3279 VSX_BUILTIN_XVMINDP,
3280 VSX_BUILTIN_XVMINSP,
3281 VSX_BUILTIN_XVMSUBDP,
3282 VSX_BUILTIN_XVMSUBSP,
3283 VSX_BUILTIN_XVMULDP,
3284 VSX_BUILTIN_XVMULSP,
3285 VSX_BUILTIN_XVNABSDP,
3286 VSX_BUILTIN_XVNABSSP,
3287 VSX_BUILTIN_XVNEGDP,
3288 VSX_BUILTIN_XVNEGSP,
3289 VSX_BUILTIN_XVNMADDDP,
3290 VSX_BUILTIN_XVNMADDSP,
3291 VSX_BUILTIN_XVNMSUBDP,
3292 VSX_BUILTIN_XVNMSUBSP,
3294 VSX_BUILTIN_XVRDPIC,
3295 VSX_BUILTIN_XVRDPIM,
3296 VSX_BUILTIN_XVRDPIP,
3297 VSX_BUILTIN_XVRDPIZ,
3301 VSX_BUILTIN_XVRSPIC,
3302 VSX_BUILTIN_XVRSPIM,
3303 VSX_BUILTIN_XVRSPIP,
3304 VSX_BUILTIN_XVRSPIZ,
3305 VSX_BUILTIN_XVRSQRTEDP,
3306 VSX_BUILTIN_XVRSQRTESP,
3307 VSX_BUILTIN_XVSQRTDP,
3308 VSX_BUILTIN_XVSQRTSP,
3309 VSX_BUILTIN_XVSUBDP,
3310 VSX_BUILTIN_XVSUBSP,
3311 VSX_BUILTIN_XVTDIVDP_FE,
3312 VSX_BUILTIN_XVTDIVDP_FG,
3313 VSX_BUILTIN_XVTDIVSP_FE,
3314 VSX_BUILTIN_XVTDIVSP_FG,
3315 VSX_BUILTIN_XVTSQRTDP_FE,
3316 VSX_BUILTIN_XVTSQRTDP_FG,
3317 VSX_BUILTIN_XVTSQRTSP_FE,
3318 VSX_BUILTIN_XVTSQRTSP_FG,
3319 VSX_BUILTIN_XXSEL_2DI,
3320 VSX_BUILTIN_XXSEL_2DF,
3321 VSX_BUILTIN_XXSEL_4SI,
3322 VSX_BUILTIN_XXSEL_4SF,
3323 VSX_BUILTIN_XXSEL_8HI,
3324 VSX_BUILTIN_XXSEL_16QI,
3325 VSX_BUILTIN_XXSEL_2DI_UNS,
3326 VSX_BUILTIN_XXSEL_4SI_UNS,
3327 VSX_BUILTIN_XXSEL_8HI_UNS,
3328 VSX_BUILTIN_XXSEL_16QI_UNS,
3329 VSX_BUILTIN_VPERM_2DI,
3330 VSX_BUILTIN_VPERM_2DF,
3331 VSX_BUILTIN_VPERM_4SI,
3332 VSX_BUILTIN_VPERM_4SF,
3333 VSX_BUILTIN_VPERM_8HI,
3334 VSX_BUILTIN_VPERM_16QI,
3335 VSX_BUILTIN_VPERM_2DI_UNS,
3336 VSX_BUILTIN_VPERM_4SI_UNS,
3337 VSX_BUILTIN_VPERM_8HI_UNS,
3338 VSX_BUILTIN_VPERM_16QI_UNS,
3339 VSX_BUILTIN_XXPERMDI_2DF,
3340 VSX_BUILTIN_XXPERMDI_2DI,
3341 VSX_BUILTIN_XXPERMDI_4SF,
3342 VSX_BUILTIN_XXPERMDI_4SI,
3343 VSX_BUILTIN_XXPERMDI_8HI,
3344 VSX_BUILTIN_XXPERMDI_16QI,
3345 VSX_BUILTIN_CONCAT_2DF,
3346 VSX_BUILTIN_CONCAT_2DI,
3347 VSX_BUILTIN_SET_2DF,
3348 VSX_BUILTIN_SET_2DI,
3349 VSX_BUILTIN_SPLAT_2DF,
3350 VSX_BUILTIN_SPLAT_2DI,
3351 VSX_BUILTIN_XXMRGHW_4SF,
3352 VSX_BUILTIN_XXMRGHW_4SI,
3353 VSX_BUILTIN_XXMRGLW_4SF,
3354 VSX_BUILTIN_XXMRGLW_4SI,
3355 VSX_BUILTIN_XXSLDWI_16QI,
3356 VSX_BUILTIN_XXSLDWI_8HI,
3357 VSX_BUILTIN_XXSLDWI_4SI,
3358 VSX_BUILTIN_XXSLDWI_4SF,
3359 VSX_BUILTIN_XXSLDWI_2DI,
3360 VSX_BUILTIN_XXSLDWI_2DF,
3361 VSX_BUILTIN_VEC_INIT_V2DF,
3362 VSX_BUILTIN_VEC_INIT_V2DI,
3363 VSX_BUILTIN_VEC_SET_V2DF,
3364 VSX_BUILTIN_VEC_SET_V2DI,
3365 VSX_BUILTIN_VEC_EXT_V2DF,
3366 VSX_BUILTIN_VEC_EXT_V2DI,
3368 /* VSX overloaded builtins, add the overloaded functions not present in
3370 VSX_BUILTIN_VEC_MUL,
3371 VSX_BUILTIN_OVERLOADED_FIRST = VSX_BUILTIN_VEC_MUL,
3372 VSX_BUILTIN_VEC_MSUB,
3373 VSX_BUILTIN_VEC_NMADD,
3374 VSX_BUITLIN_VEC_NMSUB,
3375 VSX_BUILTIN_VEC_DIV,
3376 VSX_BUILTIN_VEC_XXMRGHW,
3377 VSX_BUILTIN_VEC_XXMRGLW,
3378 VSX_BUILTIN_VEC_XXPERMDI,
3379 VSX_BUILTIN_VEC_XXSLDWI,
3380 VSX_BUILTIN_VEC_XXSPLTD,
3381 VSX_BUILTIN_VEC_XXSPLTW,
3382 VSX_BUILTIN_OVERLOADED_LAST = VSX_BUILTIN_VEC_XXSPLTW,
3384 /* Combined VSX/Altivec builtins. */
3385 VECTOR_BUILTIN_FLOAT_V4SI_V4SF,
3386 VECTOR_BUILTIN_UNSFLOAT_V4SI_V4SF,
3387 VECTOR_BUILTIN_FIX_V4SF_V4SI,
3388 VECTOR_BUILTIN_FIXUNS_V4SF_V4SI,
3390 /* Power7 builtins, that aren't VSX instructions. */
3391 POWER7_BUILTIN_BPERMD,
3393 RS6000_BUILTIN_COUNT
3396 enum rs6000_builtin_type_index
3398 RS6000_BTI_NOT_OPAQUE,
3399 RS6000_BTI_opaque_V2SI,
3400 RS6000_BTI_opaque_V2SF,
3401 RS6000_BTI_opaque_p_V2SI,
3402 RS6000_BTI_opaque_V4SI,
3412 RS6000_BTI_unsigned_V16QI,
3413 RS6000_BTI_unsigned_V8HI,
3414 RS6000_BTI_unsigned_V4SI,
3415 RS6000_BTI_unsigned_V2DI,
3416 RS6000_BTI_bool_char, /* __bool char */
3417 RS6000_BTI_bool_short, /* __bool short */
3418 RS6000_BTI_bool_int, /* __bool int */
3419 RS6000_BTI_bool_long, /* __bool long */
3420 RS6000_BTI_pixel, /* __pixel */
3421 RS6000_BTI_bool_V16QI, /* __vector __bool char */
3422 RS6000_BTI_bool_V8HI, /* __vector __bool short */
3423 RS6000_BTI_bool_V4SI, /* __vector __bool int */
3424 RS6000_BTI_bool_V2DI, /* __vector __bool long */
3425 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
3426 RS6000_BTI_long, /* long_integer_type_node */
3427 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
3428 RS6000_BTI_INTQI, /* intQI_type_node */
3429 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
3430 RS6000_BTI_INTHI, /* intHI_type_node */
3431 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
3432 RS6000_BTI_INTSI, /* intSI_type_node */
3433 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
3434 RS6000_BTI_INTDI, /* intDI_type_node */
3435 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */
3436 RS6000_BTI_float, /* float_type_node */
3437 RS6000_BTI_double, /* double_type_node */
3438 RS6000_BTI_void, /* void_type_node */
3443 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
3444 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
3445 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
3446 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
3447 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
3448 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
3449 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
3450 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
3451 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
3452 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
3453 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
3454 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
3455 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
3456 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
3457 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
3458 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
3459 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
3460 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
3461 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
3462 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
3463 #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long])
3464 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
3465 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
3466 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
3467 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
3468 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
3469 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
3471 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
3472 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
3473 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
3474 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
3475 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
3476 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
3477 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
3478 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
3479 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
3480 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
3481 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
3482 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
3483 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
3485 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
3486 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];