1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
6 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 3, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
45 #include "diagnostic-core.h"
51 #include "target-def.h"
52 #include "common/common-target.h"
53 #include "langhooks.h"
55 #include "cfglayout.h"
57 #include "sched-int.h"
59 #include "tree-flow.h"
62 #include "tm-constrs.h"
65 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
68 #include "gstab.h" /* for N_SLINE */
71 #ifndef TARGET_NO_PROTOTYPE
72 #define TARGET_NO_PROTOTYPE 0
75 #define min(A,B) ((A) < (B) ? (A) : (B))
76 #define max(A,B) ((A) > (B) ? (A) : (B))
78 /* Structure used to define the rs6000 stack */
79 typedef struct rs6000_stack {
80 int reload_completed; /* stack info won't change from here on */
81 int first_gp_reg_save; /* first callee saved GP register used */
82 int first_fp_reg_save; /* first callee saved FP register used */
83 int first_altivec_reg_save; /* first callee saved AltiVec register used */
84 int lr_save_p; /* true if the link reg needs to be saved */
85 int cr_save_p; /* true if the CR reg needs to be saved */
86 unsigned int vrsave_mask; /* mask of vec registers to save */
87 int push_p; /* true if we need to allocate stack space */
88 int calls_p; /* true if the function makes any calls */
89 int world_save_p; /* true if we're saving *everything*:
90 r13-r31, cr, f14-f31, vrsave, v20-v31 */
91 enum rs6000_abi abi; /* which ABI to use */
92 int gp_save_offset; /* offset to save GP regs from initial SP */
93 int fp_save_offset; /* offset to save FP regs from initial SP */
94 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
95 int lr_save_offset; /* offset to save LR from initial SP */
96 int cr_save_offset; /* offset to save CR from initial SP */
97 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
98 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
99 int varargs_save_offset; /* offset to save the varargs registers */
100 int ehrd_offset; /* offset to EH return data */
101 int reg_size; /* register size (4 or 8) */
102 HOST_WIDE_INT vars_size; /* variable save area size */
103 int parm_size; /* outgoing parameter size */
104 int save_size; /* save area size */
105 int fixed_size; /* fixed size of stack frame */
106 int gp_size; /* size of saved GP registers */
107 int fp_size; /* size of saved FP registers */
108 int altivec_size; /* size of saved AltiVec registers */
109 int cr_size; /* size to hold CR if not in save_size */
110 int vrsave_size; /* size to hold VRSAVE if not in save_size */
111 int altivec_padding_size; /* size of altivec alignment padding if
113 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
114 int spe_padding_size;
115 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
116 int spe_64bit_regs_used;
120 /* A C structure for machine-specific, per-function data.
121 This is added to the cfun structure. */
122 typedef struct GTY(()) machine_function
124 /* Some local-dynamic symbol. */
125 const char *some_ld_name;
126 /* Whether the instruction chain has been scanned already. */
127 int insn_chain_scanned_p;
128 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
129 int ra_needs_full_frame;
130 /* Flags if __builtin_return_address (0) was used. */
132 /* Cache lr_save_p after expansion of builtin_eh_return. */
134 /* Whether we need to save the TOC to the reserved stack location in the
135 function prologue. */
136 bool save_toc_in_prologue;
137 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
138 varargs save area. */
139 HOST_WIDE_INT varargs_save_offset;
140 /* Temporary stack slot to use for SDmode copies. This slot is
141 64-bits wide and is allocated early enough so that the offset
142 does not overflow the 16-bit load/store offset field. */
143 rtx sdmode_stack_slot;
146 /* Support targetm.vectorize.builtin_mask_for_load. */
147 static GTY(()) tree altivec_builtin_mask_for_load;
149 /* Set to nonzero once AIX common-mode calls have been defined. */
150 static GTY(()) int common_mode_defined;
152 /* Label number of label created for -mrelocatable, to call to so we can
153 get the address of the GOT section */
154 static int rs6000_pic_labelno;
157 /* Counter for labels which are to be placed in .fixup. */
158 int fixuplabelno = 0;
161 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
164 /* Specify the machine mode that pointers have. After generation of rtl, the
165 compiler makes no further distinction between pointers and any other objects
166 of this machine mode. The type is unsigned since not all things that
167 include rs6000.h also include machmode.h. */
168 unsigned rs6000_pmode;
170 /* Width in bits of a pointer. */
171 unsigned rs6000_pointer_size;
173 #ifdef HAVE_AS_GNU_ATTRIBUTE
174 /* Flag whether floating point values have been passed/returned. */
175 static bool rs6000_passes_float;
176 /* Flag whether vector values have been passed/returned. */
177 static bool rs6000_passes_vector;
178 /* Flag whether small (<= 8 byte) structures have been returned. */
179 static bool rs6000_returns_struct;
182 /* Value is TRUE if register/mode pair is acceptable. */
183 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
185 /* Maximum number of registers needed for a given register class and mode. */
186 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
188 /* How many registers are needed for a given register and mode. */
189 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
191 /* Map register number to register class. */
192 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
194 /* Reload functions based on the type and the vector unit. */
195 static enum insn_code rs6000_vector_reload[NUM_MACHINE_MODES][2];
197 static int dbg_cost_ctrl;
199 /* Built in types. */
200 tree rs6000_builtin_types[RS6000_BTI_MAX];
201 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
203 /* Flag to say the TOC is initialized */
205 char toc_label_name[10];
207 /* Cached value of rs6000_variable_issue. This is cached in
208 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
209 static short cached_can_issue_more;
211 static GTY(()) section *read_only_data_section;
212 static GTY(()) section *private_data_section;
213 static GTY(()) section *read_only_private_data_section;
214 static GTY(()) section *sdata2_section;
215 static GTY(()) section *toc_section;
217 struct builtin_description
219 const unsigned int mask;
220 const enum insn_code icode;
221 const char *const name;
222 const enum rs6000_builtins code;
225 /* Describe the vector unit used for modes. */
226 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
227 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
229 /* Register classes for various constraints that are based on the target
231 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
233 /* Describe the alignment of a vector. */
234 int rs6000_vector_align[NUM_MACHINE_MODES];
236 /* Map selected modes to types for builtins. */
237 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
239 /* What modes to automatically generate reciprocal divide estimate (fre) and
240 reciprocal sqrt (frsqrte) for. */
241 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
243 /* Masks to determine which reciprocal esitmate instructions to generate
245 enum rs6000_recip_mask {
246 RECIP_SF_DIV = 0x001, /* Use divide estimate */
247 RECIP_DF_DIV = 0x002,
248 RECIP_V4SF_DIV = 0x004,
249 RECIP_V2DF_DIV = 0x008,
251 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
252 RECIP_DF_RSQRT = 0x020,
253 RECIP_V4SF_RSQRT = 0x040,
254 RECIP_V2DF_RSQRT = 0x080,
256 /* Various combination of flags for -mrecip=xxx. */
258 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
259 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
260 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
262 RECIP_HIGH_PRECISION = RECIP_ALL,
264 /* On low precision machines like the power5, don't enable double precision
265 reciprocal square root estimate, since it isn't accurate enough. */
266 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
269 /* -mrecip options. */
272 const char *string; /* option name */
273 unsigned int mask; /* mask bits to set */
274 } recip_options[] = {
275 { "all", RECIP_ALL },
276 { "none", RECIP_NONE },
277 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
279 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
280 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
281 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
282 | RECIP_V2DF_RSQRT) },
283 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
284 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
287 /* 2 argument gen function typedef. */
288 typedef rtx (*gen_2arg_fn_t) (rtx, rtx, rtx);
290 /* Pointer to function (in rs6000-c.c) that can define or undefine target
291 macros that have changed. Languages that don't support the preprocessor
292 don't link in rs6000-c.c, so we can't call it directly. */
293 void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned);
296 /* Target cpu costs. */
298 struct processor_costs {
299 const int mulsi; /* cost of SImode multiplication. */
300 const int mulsi_const; /* cost of SImode multiplication by constant. */
301 const int mulsi_const9; /* cost of SImode mult by short constant. */
302 const int muldi; /* cost of DImode multiplication. */
303 const int divsi; /* cost of SImode division. */
304 const int divdi; /* cost of DImode division. */
305 const int fp; /* cost of simple SFmode and DFmode insns. */
306 const int dmul; /* cost of DFmode multiplication (and fmadd). */
307 const int sdiv; /* cost of SFmode division (fdivs). */
308 const int ddiv; /* cost of DFmode division (fdiv). */
309 const int cache_line_size; /* cache line size in bytes. */
310 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
311 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
312 const int simultaneous_prefetches; /* number of parallel prefetch
316 const struct processor_costs *rs6000_cost;
318 /* Processor costs (relative to an add) */
320 /* Instruction size costs on 32bit processors. */
322 struct processor_costs size32_cost = {
323 COSTS_N_INSNS (1), /* mulsi */
324 COSTS_N_INSNS (1), /* mulsi_const */
325 COSTS_N_INSNS (1), /* mulsi_const9 */
326 COSTS_N_INSNS (1), /* muldi */
327 COSTS_N_INSNS (1), /* divsi */
328 COSTS_N_INSNS (1), /* divdi */
329 COSTS_N_INSNS (1), /* fp */
330 COSTS_N_INSNS (1), /* dmul */
331 COSTS_N_INSNS (1), /* sdiv */
332 COSTS_N_INSNS (1), /* ddiv */
339 /* Instruction size costs on 64bit processors. */
341 struct processor_costs size64_cost = {
342 COSTS_N_INSNS (1), /* mulsi */
343 COSTS_N_INSNS (1), /* mulsi_const */
344 COSTS_N_INSNS (1), /* mulsi_const9 */
345 COSTS_N_INSNS (1), /* muldi */
346 COSTS_N_INSNS (1), /* divsi */
347 COSTS_N_INSNS (1), /* divdi */
348 COSTS_N_INSNS (1), /* fp */
349 COSTS_N_INSNS (1), /* dmul */
350 COSTS_N_INSNS (1), /* sdiv */
351 COSTS_N_INSNS (1), /* ddiv */
358 /* Instruction costs on RIOS1 processors. */
360 struct processor_costs rios1_cost = {
361 COSTS_N_INSNS (5), /* mulsi */
362 COSTS_N_INSNS (4), /* mulsi_const */
363 COSTS_N_INSNS (3), /* mulsi_const9 */
364 COSTS_N_INSNS (5), /* muldi */
365 COSTS_N_INSNS (19), /* divsi */
366 COSTS_N_INSNS (19), /* divdi */
367 COSTS_N_INSNS (2), /* fp */
368 COSTS_N_INSNS (2), /* dmul */
369 COSTS_N_INSNS (19), /* sdiv */
370 COSTS_N_INSNS (19), /* ddiv */
371 128, /* cache line size */
377 /* Instruction costs on RIOS2 processors. */
379 struct processor_costs rios2_cost = {
380 COSTS_N_INSNS (2), /* mulsi */
381 COSTS_N_INSNS (2), /* mulsi_const */
382 COSTS_N_INSNS (2), /* mulsi_const9 */
383 COSTS_N_INSNS (2), /* muldi */
384 COSTS_N_INSNS (13), /* divsi */
385 COSTS_N_INSNS (13), /* divdi */
386 COSTS_N_INSNS (2), /* fp */
387 COSTS_N_INSNS (2), /* dmul */
388 COSTS_N_INSNS (17), /* sdiv */
389 COSTS_N_INSNS (17), /* ddiv */
390 256, /* cache line size */
396 /* Instruction costs on RS64A processors. */
398 struct processor_costs rs64a_cost = {
399 COSTS_N_INSNS (20), /* mulsi */
400 COSTS_N_INSNS (12), /* mulsi_const */
401 COSTS_N_INSNS (8), /* mulsi_const9 */
402 COSTS_N_INSNS (34), /* muldi */
403 COSTS_N_INSNS (65), /* divsi */
404 COSTS_N_INSNS (67), /* divdi */
405 COSTS_N_INSNS (4), /* fp */
406 COSTS_N_INSNS (4), /* dmul */
407 COSTS_N_INSNS (31), /* sdiv */
408 COSTS_N_INSNS (31), /* ddiv */
409 128, /* cache line size */
415 /* Instruction costs on MPCCORE processors. */
417 struct processor_costs mpccore_cost = {
418 COSTS_N_INSNS (2), /* mulsi */
419 COSTS_N_INSNS (2), /* mulsi_const */
420 COSTS_N_INSNS (2), /* mulsi_const9 */
421 COSTS_N_INSNS (2), /* muldi */
422 COSTS_N_INSNS (6), /* divsi */
423 COSTS_N_INSNS (6), /* divdi */
424 COSTS_N_INSNS (4), /* fp */
425 COSTS_N_INSNS (5), /* dmul */
426 COSTS_N_INSNS (10), /* sdiv */
427 COSTS_N_INSNS (17), /* ddiv */
428 32, /* cache line size */
434 /* Instruction costs on PPC403 processors. */
436 struct processor_costs ppc403_cost = {
437 COSTS_N_INSNS (4), /* mulsi */
438 COSTS_N_INSNS (4), /* mulsi_const */
439 COSTS_N_INSNS (4), /* mulsi_const9 */
440 COSTS_N_INSNS (4), /* muldi */
441 COSTS_N_INSNS (33), /* divsi */
442 COSTS_N_INSNS (33), /* divdi */
443 COSTS_N_INSNS (11), /* fp */
444 COSTS_N_INSNS (11), /* dmul */
445 COSTS_N_INSNS (11), /* sdiv */
446 COSTS_N_INSNS (11), /* ddiv */
447 32, /* cache line size */
453 /* Instruction costs on PPC405 processors. */
455 struct processor_costs ppc405_cost = {
456 COSTS_N_INSNS (5), /* mulsi */
457 COSTS_N_INSNS (4), /* mulsi_const */
458 COSTS_N_INSNS (3), /* mulsi_const9 */
459 COSTS_N_INSNS (5), /* muldi */
460 COSTS_N_INSNS (35), /* divsi */
461 COSTS_N_INSNS (35), /* divdi */
462 COSTS_N_INSNS (11), /* fp */
463 COSTS_N_INSNS (11), /* dmul */
464 COSTS_N_INSNS (11), /* sdiv */
465 COSTS_N_INSNS (11), /* ddiv */
466 32, /* cache line size */
472 /* Instruction costs on PPC440 processors. */
474 struct processor_costs ppc440_cost = {
475 COSTS_N_INSNS (3), /* mulsi */
476 COSTS_N_INSNS (2), /* mulsi_const */
477 COSTS_N_INSNS (2), /* mulsi_const9 */
478 COSTS_N_INSNS (3), /* muldi */
479 COSTS_N_INSNS (34), /* divsi */
480 COSTS_N_INSNS (34), /* divdi */
481 COSTS_N_INSNS (5), /* fp */
482 COSTS_N_INSNS (5), /* dmul */
483 COSTS_N_INSNS (19), /* sdiv */
484 COSTS_N_INSNS (33), /* ddiv */
485 32, /* cache line size */
491 /* Instruction costs on PPC476 processors. */
493 struct processor_costs ppc476_cost = {
494 COSTS_N_INSNS (4), /* mulsi */
495 COSTS_N_INSNS (4), /* mulsi_const */
496 COSTS_N_INSNS (4), /* mulsi_const9 */
497 COSTS_N_INSNS (4), /* muldi */
498 COSTS_N_INSNS (11), /* divsi */
499 COSTS_N_INSNS (11), /* divdi */
500 COSTS_N_INSNS (6), /* fp */
501 COSTS_N_INSNS (6), /* dmul */
502 COSTS_N_INSNS (19), /* sdiv */
503 COSTS_N_INSNS (33), /* ddiv */
504 32, /* l1 cache line size */
510 /* Instruction costs on PPC601 processors. */
512 struct processor_costs ppc601_cost = {
513 COSTS_N_INSNS (5), /* mulsi */
514 COSTS_N_INSNS (5), /* mulsi_const */
515 COSTS_N_INSNS (5), /* mulsi_const9 */
516 COSTS_N_INSNS (5), /* muldi */
517 COSTS_N_INSNS (36), /* divsi */
518 COSTS_N_INSNS (36), /* divdi */
519 COSTS_N_INSNS (4), /* fp */
520 COSTS_N_INSNS (5), /* dmul */
521 COSTS_N_INSNS (17), /* sdiv */
522 COSTS_N_INSNS (31), /* ddiv */
523 32, /* cache line size */
529 /* Instruction costs on PPC603 processors. */
531 struct processor_costs ppc603_cost = {
532 COSTS_N_INSNS (5), /* mulsi */
533 COSTS_N_INSNS (3), /* mulsi_const */
534 COSTS_N_INSNS (2), /* mulsi_const9 */
535 COSTS_N_INSNS (5), /* muldi */
536 COSTS_N_INSNS (37), /* divsi */
537 COSTS_N_INSNS (37), /* divdi */
538 COSTS_N_INSNS (3), /* fp */
539 COSTS_N_INSNS (4), /* dmul */
540 COSTS_N_INSNS (18), /* sdiv */
541 COSTS_N_INSNS (33), /* ddiv */
542 32, /* cache line size */
548 /* Instruction costs on PPC604 processors. */
550 struct processor_costs ppc604_cost = {
551 COSTS_N_INSNS (4), /* mulsi */
552 COSTS_N_INSNS (4), /* mulsi_const */
553 COSTS_N_INSNS (4), /* mulsi_const9 */
554 COSTS_N_INSNS (4), /* muldi */
555 COSTS_N_INSNS (20), /* divsi */
556 COSTS_N_INSNS (20), /* divdi */
557 COSTS_N_INSNS (3), /* fp */
558 COSTS_N_INSNS (3), /* dmul */
559 COSTS_N_INSNS (18), /* sdiv */
560 COSTS_N_INSNS (32), /* ddiv */
561 32, /* cache line size */
567 /* Instruction costs on PPC604e processors. */
569 struct processor_costs ppc604e_cost = {
570 COSTS_N_INSNS (2), /* mulsi */
571 COSTS_N_INSNS (2), /* mulsi_const */
572 COSTS_N_INSNS (2), /* mulsi_const9 */
573 COSTS_N_INSNS (2), /* muldi */
574 COSTS_N_INSNS (20), /* divsi */
575 COSTS_N_INSNS (20), /* divdi */
576 COSTS_N_INSNS (3), /* fp */
577 COSTS_N_INSNS (3), /* dmul */
578 COSTS_N_INSNS (18), /* sdiv */
579 COSTS_N_INSNS (32), /* ddiv */
580 32, /* cache line size */
586 /* Instruction costs on PPC620 processors. */
588 struct processor_costs ppc620_cost = {
589 COSTS_N_INSNS (5), /* mulsi */
590 COSTS_N_INSNS (4), /* mulsi_const */
591 COSTS_N_INSNS (3), /* mulsi_const9 */
592 COSTS_N_INSNS (7), /* muldi */
593 COSTS_N_INSNS (21), /* divsi */
594 COSTS_N_INSNS (37), /* divdi */
595 COSTS_N_INSNS (3), /* fp */
596 COSTS_N_INSNS (3), /* dmul */
597 COSTS_N_INSNS (18), /* sdiv */
598 COSTS_N_INSNS (32), /* ddiv */
599 128, /* cache line size */
605 /* Instruction costs on PPC630 processors. */
607 struct processor_costs ppc630_cost = {
608 COSTS_N_INSNS (5), /* mulsi */
609 COSTS_N_INSNS (4), /* mulsi_const */
610 COSTS_N_INSNS (3), /* mulsi_const9 */
611 COSTS_N_INSNS (7), /* muldi */
612 COSTS_N_INSNS (21), /* divsi */
613 COSTS_N_INSNS (37), /* divdi */
614 COSTS_N_INSNS (3), /* fp */
615 COSTS_N_INSNS (3), /* dmul */
616 COSTS_N_INSNS (17), /* sdiv */
617 COSTS_N_INSNS (21), /* ddiv */
618 128, /* cache line size */
624 /* Instruction costs on Cell processor. */
625 /* COSTS_N_INSNS (1) ~ one add. */
627 struct processor_costs ppccell_cost = {
628 COSTS_N_INSNS (9/2)+2, /* mulsi */
629 COSTS_N_INSNS (6/2), /* mulsi_const */
630 COSTS_N_INSNS (6/2), /* mulsi_const9 */
631 COSTS_N_INSNS (15/2)+2, /* muldi */
632 COSTS_N_INSNS (38/2), /* divsi */
633 COSTS_N_INSNS (70/2), /* divdi */
634 COSTS_N_INSNS (10/2), /* fp */
635 COSTS_N_INSNS (10/2), /* dmul */
636 COSTS_N_INSNS (74/2), /* sdiv */
637 COSTS_N_INSNS (74/2), /* ddiv */
638 128, /* cache line size */
644 /* Instruction costs on PPC750 and PPC7400 processors. */
646 struct processor_costs ppc750_cost = {
647 COSTS_N_INSNS (5), /* mulsi */
648 COSTS_N_INSNS (3), /* mulsi_const */
649 COSTS_N_INSNS (2), /* mulsi_const9 */
650 COSTS_N_INSNS (5), /* muldi */
651 COSTS_N_INSNS (17), /* divsi */
652 COSTS_N_INSNS (17), /* divdi */
653 COSTS_N_INSNS (3), /* fp */
654 COSTS_N_INSNS (3), /* dmul */
655 COSTS_N_INSNS (17), /* sdiv */
656 COSTS_N_INSNS (31), /* ddiv */
657 32, /* cache line size */
663 /* Instruction costs on PPC7450 processors. */
665 struct processor_costs ppc7450_cost = {
666 COSTS_N_INSNS (4), /* mulsi */
667 COSTS_N_INSNS (3), /* mulsi_const */
668 COSTS_N_INSNS (3), /* mulsi_const9 */
669 COSTS_N_INSNS (4), /* muldi */
670 COSTS_N_INSNS (23), /* divsi */
671 COSTS_N_INSNS (23), /* divdi */
672 COSTS_N_INSNS (5), /* fp */
673 COSTS_N_INSNS (5), /* dmul */
674 COSTS_N_INSNS (21), /* sdiv */
675 COSTS_N_INSNS (35), /* ddiv */
676 32, /* cache line size */
682 /* Instruction costs on PPC8540 processors. */
684 struct processor_costs ppc8540_cost = {
685 COSTS_N_INSNS (4), /* mulsi */
686 COSTS_N_INSNS (4), /* mulsi_const */
687 COSTS_N_INSNS (4), /* mulsi_const9 */
688 COSTS_N_INSNS (4), /* muldi */
689 COSTS_N_INSNS (19), /* divsi */
690 COSTS_N_INSNS (19), /* divdi */
691 COSTS_N_INSNS (4), /* fp */
692 COSTS_N_INSNS (4), /* dmul */
693 COSTS_N_INSNS (29), /* sdiv */
694 COSTS_N_INSNS (29), /* ddiv */
695 32, /* cache line size */
698 1, /* prefetch streams /*/
701 /* Instruction costs on E300C2 and E300C3 cores. */
703 struct processor_costs ppce300c2c3_cost = {
704 COSTS_N_INSNS (4), /* mulsi */
705 COSTS_N_INSNS (4), /* mulsi_const */
706 COSTS_N_INSNS (4), /* mulsi_const9 */
707 COSTS_N_INSNS (4), /* muldi */
708 COSTS_N_INSNS (19), /* divsi */
709 COSTS_N_INSNS (19), /* divdi */
710 COSTS_N_INSNS (3), /* fp */
711 COSTS_N_INSNS (4), /* dmul */
712 COSTS_N_INSNS (18), /* sdiv */
713 COSTS_N_INSNS (33), /* ddiv */
717 1, /* prefetch streams /*/
720 /* Instruction costs on PPCE500MC processors. */
722 struct processor_costs ppce500mc_cost = {
723 COSTS_N_INSNS (4), /* mulsi */
724 COSTS_N_INSNS (4), /* mulsi_const */
725 COSTS_N_INSNS (4), /* mulsi_const9 */
726 COSTS_N_INSNS (4), /* muldi */
727 COSTS_N_INSNS (14), /* divsi */
728 COSTS_N_INSNS (14), /* divdi */
729 COSTS_N_INSNS (8), /* fp */
730 COSTS_N_INSNS (10), /* dmul */
731 COSTS_N_INSNS (36), /* sdiv */
732 COSTS_N_INSNS (66), /* ddiv */
733 64, /* cache line size */
736 1, /* prefetch streams /*/
739 /* Instruction costs on PPCE500MC64 processors. */
741 struct processor_costs ppce500mc64_cost = {
742 COSTS_N_INSNS (4), /* mulsi */
743 COSTS_N_INSNS (4), /* mulsi_const */
744 COSTS_N_INSNS (4), /* mulsi_const9 */
745 COSTS_N_INSNS (4), /* muldi */
746 COSTS_N_INSNS (14), /* divsi */
747 COSTS_N_INSNS (14), /* divdi */
748 COSTS_N_INSNS (4), /* fp */
749 COSTS_N_INSNS (10), /* dmul */
750 COSTS_N_INSNS (36), /* sdiv */
751 COSTS_N_INSNS (66), /* ddiv */
752 64, /* cache line size */
755 1, /* prefetch streams /*/
758 /* Instruction costs on AppliedMicro Titan processors. */
760 struct processor_costs titan_cost = {
761 COSTS_N_INSNS (5), /* mulsi */
762 COSTS_N_INSNS (5), /* mulsi_const */
763 COSTS_N_INSNS (5), /* mulsi_const9 */
764 COSTS_N_INSNS (5), /* muldi */
765 COSTS_N_INSNS (18), /* divsi */
766 COSTS_N_INSNS (18), /* divdi */
767 COSTS_N_INSNS (10), /* fp */
768 COSTS_N_INSNS (10), /* dmul */
769 COSTS_N_INSNS (46), /* sdiv */
770 COSTS_N_INSNS (72), /* ddiv */
771 32, /* cache line size */
774 1, /* prefetch streams /*/
777 /* Instruction costs on POWER4 and POWER5 processors. */
779 struct processor_costs power4_cost = {
780 COSTS_N_INSNS (3), /* mulsi */
781 COSTS_N_INSNS (2), /* mulsi_const */
782 COSTS_N_INSNS (2), /* mulsi_const9 */
783 COSTS_N_INSNS (4), /* muldi */
784 COSTS_N_INSNS (18), /* divsi */
785 COSTS_N_INSNS (34), /* divdi */
786 COSTS_N_INSNS (3), /* fp */
787 COSTS_N_INSNS (3), /* dmul */
788 COSTS_N_INSNS (17), /* sdiv */
789 COSTS_N_INSNS (17), /* ddiv */
790 128, /* cache line size */
793 8, /* prefetch streams /*/
796 /* Instruction costs on POWER6 processors. */
798 struct processor_costs power6_cost = {
799 COSTS_N_INSNS (8), /* mulsi */
800 COSTS_N_INSNS (8), /* mulsi_const */
801 COSTS_N_INSNS (8), /* mulsi_const9 */
802 COSTS_N_INSNS (8), /* muldi */
803 COSTS_N_INSNS (22), /* divsi */
804 COSTS_N_INSNS (28), /* divdi */
805 COSTS_N_INSNS (3), /* fp */
806 COSTS_N_INSNS (3), /* dmul */
807 COSTS_N_INSNS (13), /* sdiv */
808 COSTS_N_INSNS (16), /* ddiv */
809 128, /* cache line size */
812 16, /* prefetch streams */
815 /* Instruction costs on POWER7 processors. */
817 struct processor_costs power7_cost = {
818 COSTS_N_INSNS (2), /* mulsi */
819 COSTS_N_INSNS (2), /* mulsi_const */
820 COSTS_N_INSNS (2), /* mulsi_const9 */
821 COSTS_N_INSNS (2), /* muldi */
822 COSTS_N_INSNS (18), /* divsi */
823 COSTS_N_INSNS (34), /* divdi */
824 COSTS_N_INSNS (3), /* fp */
825 COSTS_N_INSNS (3), /* dmul */
826 COSTS_N_INSNS (13), /* sdiv */
827 COSTS_N_INSNS (16), /* ddiv */
828 128, /* cache line size */
831 12, /* prefetch streams */
834 /* Instruction costs on POWER A2 processors. */
836 struct processor_costs ppca2_cost = {
837 COSTS_N_INSNS (16), /* mulsi */
838 COSTS_N_INSNS (16), /* mulsi_const */
839 COSTS_N_INSNS (16), /* mulsi_const9 */
840 COSTS_N_INSNS (16), /* muldi */
841 COSTS_N_INSNS (22), /* divsi */
842 COSTS_N_INSNS (28), /* divdi */
843 COSTS_N_INSNS (3), /* fp */
844 COSTS_N_INSNS (3), /* dmul */
845 COSTS_N_INSNS (59), /* sdiv */
846 COSTS_N_INSNS (72), /* ddiv */
850 16, /* prefetch streams */
854 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
855 #undef RS6000_BUILTIN_1
856 #undef RS6000_BUILTIN_2
857 #undef RS6000_BUILTIN_3
858 #undef RS6000_BUILTIN_A
859 #undef RS6000_BUILTIN_D
860 #undef RS6000_BUILTIN_E
861 #undef RS6000_BUILTIN_P
862 #undef RS6000_BUILTIN_Q
863 #undef RS6000_BUILTIN_S
864 #undef RS6000_BUILTIN_X
866 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
867 { NAME, ICODE, MASK, ATTR },
869 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
870 { NAME, ICODE, MASK, ATTR },
872 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
873 { NAME, ICODE, MASK, ATTR },
875 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
876 { NAME, ICODE, MASK, ATTR },
878 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
879 { NAME, ICODE, MASK, ATTR },
881 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
882 { NAME, ICODE, MASK, ATTR },
884 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
885 { NAME, ICODE, MASK, ATTR },
887 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
888 { NAME, ICODE, MASK, ATTR },
890 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
891 { NAME, ICODE, MASK, ATTR },
893 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
894 { NAME, ICODE, MASK, ATTR },
896 struct rs6000_builtin_info_type {
898 const enum insn_code icode;
903 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
905 #include "rs6000-builtin.def"
908 #undef RS6000_BUILTIN_1
909 #undef RS6000_BUILTIN_2
910 #undef RS6000_BUILTIN_3
911 #undef RS6000_BUILTIN_A
912 #undef RS6000_BUILTIN_D
913 #undef RS6000_BUILTIN_E
914 #undef RS6000_BUILTIN_P
915 #undef RS6000_BUILTIN_Q
916 #undef RS6000_BUILTIN_S
917 #undef RS6000_BUILTIN_X
919 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
920 static tree (*rs6000_veclib_handler) (tree, tree, tree);
923 static bool rs6000_function_ok_for_sibcall (tree, tree);
924 static const char *rs6000_invalid_within_doloop (const_rtx);
925 static bool rs6000_legitimate_address_p (enum machine_mode, rtx, bool);
926 static bool rs6000_debug_legitimate_address_p (enum machine_mode, rtx, bool);
927 static rtx rs6000_generate_compare (rtx, enum machine_mode);
928 static void rs6000_emit_stack_tie (void);
929 static bool spe_func_has_64bit_regs_p (void);
930 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
931 static unsigned rs6000_hash_constant (rtx);
932 static unsigned toc_hash_function (const void *);
933 static int toc_hash_eq (const void *, const void *);
934 static bool reg_offset_addressing_ok_p (enum machine_mode);
935 static bool virtual_stack_registers_memory_p (rtx);
936 static bool constant_pool_expr_p (rtx);
937 static bool legitimate_small_data_p (enum machine_mode, rtx);
938 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
939 static struct machine_function * rs6000_init_machine_status (void);
940 static bool rs6000_assemble_integer (rtx, unsigned int, int);
941 static bool no_global_regs_above (int, bool);
942 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
943 static void rs6000_assemble_visibility (tree, int);
945 static int rs6000_ra_ever_killed (void);
946 static bool rs6000_attribute_takes_identifier_p (const_tree);
947 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
948 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
949 static bool rs6000_ms_bitfield_layout_p (const_tree);
950 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
951 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
952 static const char *rs6000_mangle_type (const_tree);
953 static void rs6000_set_default_type_attributes (tree);
954 static rtx rs6000_savres_routine_sym (rs6000_stack_t *, bool, bool, bool);
955 static rtx rs6000_emit_stack_reset (rs6000_stack_t *, rtx, rtx, int, bool);
956 static bool rs6000_reg_live_or_pic_offset_p (int);
957 static tree rs6000_builtin_vectorized_libmass (tree, tree, tree);
958 static tree rs6000_builtin_vectorized_function (tree, tree, tree);
959 static void rs6000_restore_saved_cr (rtx, int);
960 static bool rs6000_output_addr_const_extra (FILE *, rtx);
961 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
962 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
963 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
965 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
966 static bool rs6000_return_in_memory (const_tree, const_tree);
967 static rtx rs6000_function_value (const_tree, const_tree, bool);
968 static void rs6000_file_start (void);
970 static int rs6000_elf_reloc_rw_mask (void);
971 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
972 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
973 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
974 static void rs6000_elf_asm_init_sections (void);
975 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
976 unsigned HOST_WIDE_INT);
977 static void rs6000_elf_encode_section_info (tree, rtx, int)
980 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, const_rtx);
981 static void rs6000_alloc_sdmode_stack_slot (void);
982 static void rs6000_instantiate_decls (void);
984 static void rs6000_xcoff_asm_output_anchor (rtx);
985 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
986 static void rs6000_xcoff_asm_init_sections (void);
987 static int rs6000_xcoff_reloc_rw_mask (void);
988 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
989 static section *rs6000_xcoff_select_section (tree, int,
990 unsigned HOST_WIDE_INT);
991 static void rs6000_xcoff_unique_section (tree, int);
992 static section *rs6000_xcoff_select_rtx_section
993 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
994 static const char * rs6000_xcoff_strip_name_encoding (const char *);
995 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
996 static void rs6000_xcoff_file_start (void);
997 static void rs6000_xcoff_file_end (void);
999 static int rs6000_variable_issue (FILE *, int, rtx, int);
1000 static int rs6000_register_move_cost (enum machine_mode,
1001 reg_class_t, reg_class_t);
1002 static int rs6000_memory_move_cost (enum machine_mode, reg_class_t, bool);
1003 static bool rs6000_rtx_costs (rtx, int, int, int, int *, bool);
1004 static bool rs6000_debug_rtx_costs (rtx, int, int, int, int *, bool);
1005 static int rs6000_debug_address_cost (rtx, bool);
1006 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
1007 static int rs6000_debug_adjust_cost (rtx, rtx, rtx, int);
1008 static void rs6000_sched_init (FILE *, int, int);
1009 static bool is_microcoded_insn (rtx);
1010 static bool is_nonpipeline_insn (rtx);
1011 static bool is_cracked_insn (rtx);
1012 static bool is_branch_slot_insn (rtx);
1013 static bool is_load_insn (rtx);
1014 static rtx get_store_dest (rtx pat);
1015 static bool is_store_insn (rtx);
1016 static bool set_to_load_agen (rtx,rtx);
1017 static bool adjacent_mem_locations (rtx,rtx);
1018 static int rs6000_adjust_priority (rtx, int);
1019 static int rs6000_issue_rate (void);
1020 static bool rs6000_is_costly_dependence (dep_t, int, int);
1021 static rtx get_next_active_insn (rtx, rtx);
1022 static bool insn_terminates_group_p (rtx , enum group_termination);
1023 static bool insn_must_be_first_in_group (rtx);
1024 static bool insn_must_be_last_in_group (rtx);
1025 static bool is_costly_group (rtx *, rtx);
1026 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
1027 static int redefine_groups (FILE *, int, rtx, rtx);
1028 static int pad_groups (FILE *, int, rtx, rtx);
1029 static void rs6000_sched_finish (FILE *, int);
1030 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
1031 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
1032 static int rs6000_use_sched_lookahead (void);
1033 static int rs6000_use_sched_lookahead_guard (rtx);
1034 static void * rs6000_alloc_sched_context (void);
1035 static void rs6000_init_sched_context (void *, bool);
1036 static void rs6000_set_sched_context (void *);
1037 static void rs6000_free_sched_context (void *);
1038 static tree rs6000_builtin_reciprocal (unsigned int, bool, bool);
1039 static tree rs6000_builtin_mask_for_load (void);
1040 static tree rs6000_builtin_mul_widen_even (tree);
1041 static tree rs6000_builtin_mul_widen_odd (tree);
1042 static bool rs6000_builtin_support_vector_misalignment (enum
1046 static int rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt,
1048 static enum machine_mode rs6000_preferred_simd_mode (enum machine_mode);
1050 static void def_builtin (const char *, tree, enum rs6000_builtins);
1051 static bool rs6000_vector_alignment_reachable (const_tree, bool);
1052 static void rs6000_init_builtins (void);
1053 static tree rs6000_builtin_decl (unsigned, bool);
1055 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
1056 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
1057 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
1058 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
1059 static void altivec_init_builtins (void);
1060 static unsigned builtin_hash_function (const void *);
1061 static int builtin_hash_eq (const void *, const void *);
1062 static tree builtin_function_type (enum machine_mode, enum machine_mode,
1063 enum machine_mode, enum machine_mode,
1064 enum rs6000_builtins, const char *name);
1065 static void rs6000_common_init_builtins (void);
1066 static void rs6000_init_libfuncs (void);
1068 static void paired_init_builtins (void);
1069 static rtx paired_expand_builtin (tree, rtx, bool *);
1070 static rtx paired_expand_lv_builtin (enum insn_code, tree, rtx);
1071 static rtx paired_expand_stv_builtin (enum insn_code, tree);
1072 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
1074 static void spe_init_builtins (void);
1075 static rtx spe_expand_builtin (tree, rtx, bool *);
1076 static rtx spe_expand_stv_builtin (enum insn_code, tree);
1077 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
1078 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
1079 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
1080 static rs6000_stack_t *rs6000_stack_info (void);
1081 static void debug_stack_info (rs6000_stack_t *);
1083 static rtx altivec_expand_builtin (tree, rtx, bool *);
1084 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
1085 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
1086 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
1087 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
1088 static rtx altivec_expand_predicate_builtin (enum insn_code, tree, rtx);
1089 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
1090 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
1091 static rtx altivec_expand_vec_set_builtin (tree);
1092 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
1093 static int get_element_number (tree, tree);
1094 static void rs6000_option_override (void);
1095 static int rs6000_loop_align_max_skip (rtx);
1096 static int first_altivec_reg_to_save (void);
1097 static unsigned int compute_vrsave_mask (void);
1098 static void compute_save_world_info (rs6000_stack_t *info_ptr);
1099 static void is_altivec_return_reg (rtx, void *);
1100 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
1101 int easy_vector_constant (rtx, enum machine_mode);
1102 static rtx rs6000_dwarf_register_span (rtx);
1103 static void rs6000_init_dwarf_reg_sizes_extra (tree);
1104 static rtx rs6000_legitimize_address (rtx, rtx, enum machine_mode);
1105 static rtx rs6000_debug_legitimize_address (rtx, rtx, enum machine_mode);
1106 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
1107 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
1108 static rtx rs6000_delegitimize_address (rtx);
1109 static bool rs6000_const_not_ok_for_debug_p (rtx);
1110 static rtx rs6000_tls_get_addr (void);
1111 static rtx rs6000_got_sym (void);
1112 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
1113 static const char *rs6000_get_some_local_dynamic_name (void);
1114 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
1115 static rtx rs6000_complex_function_value (enum machine_mode);
1116 static rtx rs6000_spe_function_arg (const CUMULATIVE_ARGS *,
1117 enum machine_mode, const_tree);
1118 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
1119 HOST_WIDE_INT, int);
1120 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
1123 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
1126 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
1127 const_tree, HOST_WIDE_INT,
1129 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree, bool, bool);
1130 static rtx rs6000_mixed_function_arg (enum machine_mode, const_tree, int);
1131 static void rs6000_function_arg_advance (cumulative_args_t, enum machine_mode,
1133 static rtx rs6000_function_arg (cumulative_args_t, enum machine_mode,
1135 static unsigned int rs6000_function_arg_boundary (enum machine_mode,
1137 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
1138 static void setup_incoming_varargs (cumulative_args_t,
1139 enum machine_mode, tree,
1141 static bool rs6000_pass_by_reference (cumulative_args_t, enum machine_mode,
1143 static int rs6000_arg_partial_bytes (cumulative_args_t, enum machine_mode,
1145 static const char *invalid_arg_for_unprototyped_fn (const_tree, const_tree, const_tree);
1147 static void macho_branch_islands (void);
1148 static int no_previous_def (tree function_name);
1149 static tree get_prev_label (tree function_name);
1150 static void rs6000_darwin_file_start (void);
1153 static tree rs6000_build_builtin_va_list (void);
1154 static void rs6000_va_start (tree, rtx);
1155 static tree rs6000_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
1156 static bool rs6000_must_pass_in_stack (enum machine_mode, const_tree);
1157 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
1158 static bool rs6000_vector_mode_supported_p (enum machine_mode);
1159 static rtx rs6000_emit_vector_compare_inner (enum rtx_code, rtx, rtx);
1160 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
1162 static tree rs6000_stack_protect_fail (void);
1164 static rtx rs6000_legitimize_reload_address (rtx, enum machine_mode, int, int,
1167 static rtx rs6000_debug_legitimize_reload_address (rtx, enum machine_mode, int,
1170 rtx (*rs6000_legitimize_reload_address_ptr) (rtx, enum machine_mode, int, int,
1172 = rs6000_legitimize_reload_address;
1174 static bool rs6000_mode_dependent_address_p (const_rtx);
1175 static bool rs6000_mode_dependent_address (const_rtx);
1176 static bool rs6000_debug_mode_dependent_address (const_rtx);
1177 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1178 = rs6000_mode_dependent_address;
1180 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
1181 enum machine_mode, rtx);
1182 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
1185 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1186 enum machine_mode, rtx)
1187 = rs6000_secondary_reload_class;
1189 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
1190 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
1192 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1193 = rs6000_preferred_reload_class;
1195 static bool rs6000_secondary_memory_needed (enum reg_class, enum reg_class,
1198 static bool rs6000_debug_secondary_memory_needed (enum reg_class,
1202 bool (*rs6000_secondary_memory_needed_ptr) (enum reg_class, enum reg_class,
1204 = rs6000_secondary_memory_needed;
1206 static bool rs6000_cannot_change_mode_class (enum machine_mode,
1209 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode,
1213 bool (*rs6000_cannot_change_mode_class_ptr) (enum machine_mode,
1216 = rs6000_cannot_change_mode_class;
1218 static reg_class_t rs6000_secondary_reload (bool, rtx, reg_class_t,
1220 struct secondary_reload_info *);
1222 const int INSN_NOT_AVAILABLE = -1;
1223 static enum machine_mode rs6000_eh_return_filter_mode (void);
1224 static bool rs6000_can_eliminate (const int, const int);
1225 static void rs6000_conditional_register_usage (void);
1226 static void rs6000_trampoline_init (rtx, tree, rtx);
1227 static bool rs6000_cannot_force_const_mem (enum machine_mode, rtx);
1228 static bool rs6000_legitimate_constant_p (enum machine_mode, rtx);
1229 static bool rs6000_save_toc_in_prologue_p (void);
1230 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
1231 static void rs6000_set_up_by_prologue (struct hard_reg_set_container *);
1233 /* Hash table stuff for keeping track of TOC entries. */
1235 struct GTY(()) toc_hash_struct
1237 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1238 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1240 enum machine_mode key_mode;
1244 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
1246 /* Hash table to keep track of the argument types for builtin functions. */
1248 struct GTY(()) builtin_hash_struct
1251 enum machine_mode mode[4]; /* return value + 3 arguments. */
1252 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1255 static GTY ((param_is (struct builtin_hash_struct))) htab_t builtin_hash_table;
1257 static bool rs6000_valid_attribute_p (tree, tree, tree, int);
1258 static void rs6000_function_specific_save (struct cl_target_option *);
1259 static void rs6000_function_specific_restore (struct cl_target_option *);
1260 static void rs6000_function_specific_print (FILE *, int,
1261 struct cl_target_option *);
1262 static bool rs6000_can_inline_p (tree, tree);
1263 static void rs6000_set_current_function (tree);
1266 /* Default register names. */
1267 char rs6000_reg_names[][8] =
1269 "0", "1", "2", "3", "4", "5", "6", "7",
1270 "8", "9", "10", "11", "12", "13", "14", "15",
1271 "16", "17", "18", "19", "20", "21", "22", "23",
1272 "24", "25", "26", "27", "28", "29", "30", "31",
1273 "0", "1", "2", "3", "4", "5", "6", "7",
1274 "8", "9", "10", "11", "12", "13", "14", "15",
1275 "16", "17", "18", "19", "20", "21", "22", "23",
1276 "24", "25", "26", "27", "28", "29", "30", "31",
1277 "mq", "lr", "ctr","ap",
1278 "0", "1", "2", "3", "4", "5", "6", "7",
1280 /* AltiVec registers. */
1281 "0", "1", "2", "3", "4", "5", "6", "7",
1282 "8", "9", "10", "11", "12", "13", "14", "15",
1283 "16", "17", "18", "19", "20", "21", "22", "23",
1284 "24", "25", "26", "27", "28", "29", "30", "31",
1286 /* SPE registers. */
1287 "spe_acc", "spefscr",
1288 /* Soft frame pointer. */
1292 #ifdef TARGET_REGNAMES
1293 static const char alt_reg_names[][8] =
1295 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1296 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1297 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1298 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1299 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1300 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1301 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1302 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1303 "mq", "lr", "ctr", "ap",
1304 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1306 /* AltiVec registers. */
1307 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1308 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1309 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1310 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1312 /* SPE registers. */
1313 "spe_acc", "spefscr",
1314 /* Soft frame pointer. */
1319 /* Table of valid machine attributes. */
1321 static const struct attribute_spec rs6000_attribute_table[] =
1323 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1324 affects_type_identity } */
1325 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute,
1327 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute,
1329 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute,
1331 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
1333 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
1335 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1336 SUBTARGET_ATTRIBUTE_TABLE,
1338 { NULL, 0, 0, false, false, false, NULL, false }
1341 #ifndef MASK_STRICT_ALIGN
1342 #define MASK_STRICT_ALIGN 0
1344 #ifndef TARGET_PROFILE_KERNEL
1345 #define TARGET_PROFILE_KERNEL 0
1348 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1349 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1351 /* Initialize the GCC target structure. */
1352 #undef TARGET_ATTRIBUTE_TABLE
1353 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1354 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1355 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1356 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1357 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1359 #undef TARGET_ASM_ALIGNED_DI_OP
1360 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1362 /* Default unaligned ops are only provided for ELF. Find the ops needed
1363 for non-ELF systems. */
1364 #ifndef OBJECT_FORMAT_ELF
1366 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1368 #undef TARGET_ASM_UNALIGNED_HI_OP
1369 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1370 #undef TARGET_ASM_UNALIGNED_SI_OP
1371 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1372 #undef TARGET_ASM_UNALIGNED_DI_OP
1373 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1376 #undef TARGET_ASM_UNALIGNED_HI_OP
1377 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1378 #undef TARGET_ASM_UNALIGNED_SI_OP
1379 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1380 #undef TARGET_ASM_UNALIGNED_DI_OP
1381 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1382 #undef TARGET_ASM_ALIGNED_DI_OP
1383 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1387 /* This hook deals with fixups for relocatable code and DI-mode objects
1389 #undef TARGET_ASM_INTEGER
1390 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1392 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1393 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1394 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1397 #undef TARGET_SET_UP_BY_PROLOGUE
1398 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1400 #undef TARGET_HAVE_TLS
1401 #define TARGET_HAVE_TLS HAVE_AS_TLS
1403 #undef TARGET_CANNOT_FORCE_CONST_MEM
1404 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1406 #undef TARGET_DELEGITIMIZE_ADDRESS
1407 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1409 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1410 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1412 #undef TARGET_ASM_FUNCTION_PROLOGUE
1413 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1414 #undef TARGET_ASM_FUNCTION_EPILOGUE
1415 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1417 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1418 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1420 #undef TARGET_LEGITIMIZE_ADDRESS
1421 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1423 #undef TARGET_SCHED_VARIABLE_ISSUE
1424 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1426 #undef TARGET_SCHED_ISSUE_RATE
1427 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1428 #undef TARGET_SCHED_ADJUST_COST
1429 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1430 #undef TARGET_SCHED_ADJUST_PRIORITY
1431 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1432 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1433 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1434 #undef TARGET_SCHED_INIT
1435 #define TARGET_SCHED_INIT rs6000_sched_init
1436 #undef TARGET_SCHED_FINISH
1437 #define TARGET_SCHED_FINISH rs6000_sched_finish
1438 #undef TARGET_SCHED_REORDER
1439 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1440 #undef TARGET_SCHED_REORDER2
1441 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1443 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1444 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1446 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1447 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1449 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1450 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1451 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1452 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1453 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1454 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1455 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1456 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1458 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1459 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1460 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1461 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1462 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1463 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1464 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1465 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1466 rs6000_builtin_support_vector_misalignment
1467 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1468 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1469 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1470 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1471 rs6000_builtin_vectorization_cost
1472 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1473 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1474 rs6000_preferred_simd_mode
1476 #undef TARGET_INIT_BUILTINS
1477 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1478 #undef TARGET_BUILTIN_DECL
1479 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1481 #undef TARGET_EXPAND_BUILTIN
1482 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1484 #undef TARGET_MANGLE_TYPE
1485 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1487 #undef TARGET_INIT_LIBFUNCS
1488 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1491 #undef TARGET_BINDS_LOCAL_P
1492 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1495 #undef TARGET_MS_BITFIELD_LAYOUT_P
1496 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1498 #undef TARGET_ASM_OUTPUT_MI_THUNK
1499 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1501 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1502 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1504 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1505 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1507 #undef TARGET_INVALID_WITHIN_DOLOOP
1508 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1510 #undef TARGET_REGISTER_MOVE_COST
1511 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1512 #undef TARGET_MEMORY_MOVE_COST
1513 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1514 #undef TARGET_RTX_COSTS
1515 #define TARGET_RTX_COSTS rs6000_rtx_costs
1516 #undef TARGET_ADDRESS_COST
1517 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
1519 #undef TARGET_DWARF_REGISTER_SPAN
1520 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1522 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1523 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1525 /* On rs6000, function arguments are promoted, as are function return
1527 #undef TARGET_PROMOTE_FUNCTION_MODE
1528 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1530 #undef TARGET_RETURN_IN_MEMORY
1531 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1533 #undef TARGET_SETUP_INCOMING_VARARGS
1534 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1536 /* Always strict argument naming on rs6000. */
1537 #undef TARGET_STRICT_ARGUMENT_NAMING
1538 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1539 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1540 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1541 #undef TARGET_SPLIT_COMPLEX_ARG
1542 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1543 #undef TARGET_MUST_PASS_IN_STACK
1544 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1545 #undef TARGET_PASS_BY_REFERENCE
1546 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1547 #undef TARGET_ARG_PARTIAL_BYTES
1548 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1549 #undef TARGET_FUNCTION_ARG_ADVANCE
1550 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1551 #undef TARGET_FUNCTION_ARG
1552 #define TARGET_FUNCTION_ARG rs6000_function_arg
1553 #undef TARGET_FUNCTION_ARG_BOUNDARY
1554 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1556 #undef TARGET_BUILD_BUILTIN_VA_LIST
1557 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1559 #undef TARGET_EXPAND_BUILTIN_VA_START
1560 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1562 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1563 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1565 #undef TARGET_EH_RETURN_FILTER_MODE
1566 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1568 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1569 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1571 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1572 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1574 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1575 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1577 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1578 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1580 #undef TARGET_OPTION_OVERRIDE
1581 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1583 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1584 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1585 rs6000_builtin_vectorized_function
1588 #undef TARGET_STACK_PROTECT_FAIL
1589 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1592 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1593 The PowerPC architecture requires only weak consistency among
1594 processors--that is, memory accesses between processors need not be
1595 sequentially consistent and memory accesses among processors can occur
1596 in any order. The ability to order memory accesses weakly provides
1597 opportunities for more efficient use of the system bus. Unless a
1598 dependency exists, the 604e allows read operations to precede store
1600 #undef TARGET_RELAXED_ORDERING
1601 #define TARGET_RELAXED_ORDERING true
1604 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1605 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1608 /* Use a 32-bit anchor range. This leads to sequences like:
1610 addis tmp,anchor,high
1613 where tmp itself acts as an anchor, and can be shared between
1614 accesses to the same 64k page. */
1615 #undef TARGET_MIN_ANCHOR_OFFSET
1616 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1617 #undef TARGET_MAX_ANCHOR_OFFSET
1618 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1619 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1620 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1622 #undef TARGET_BUILTIN_RECIPROCAL
1623 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1625 #undef TARGET_EXPAND_TO_RTL_HOOK
1626 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1628 #undef TARGET_INSTANTIATE_DECLS
1629 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1631 #undef TARGET_SECONDARY_RELOAD
1632 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1634 #undef TARGET_LEGITIMATE_ADDRESS_P
1635 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1637 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1638 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1640 #undef TARGET_CAN_ELIMINATE
1641 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1643 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1644 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1646 #undef TARGET_TRAMPOLINE_INIT
1647 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1649 #undef TARGET_FUNCTION_VALUE
1650 #define TARGET_FUNCTION_VALUE rs6000_function_value
1652 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1653 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1655 #undef TARGET_OPTION_SAVE
1656 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1658 #undef TARGET_OPTION_RESTORE
1659 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1661 #undef TARGET_OPTION_PRINT
1662 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1664 #undef TARGET_CAN_INLINE_P
1665 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1667 #undef TARGET_SET_CURRENT_FUNCTION
1668 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1670 #undef TARGET_LEGITIMATE_CONSTANT_P
1671 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1673 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1674 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1677 /* Simplifications for entries below. */
1680 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1681 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1684 /* Some OSs don't support saving the high part of 64-bit registers on context
1685 switch. Other OSs don't support saving Altivec registers. On those OSs, we
1686 don't touch the MASK_POWERPC64 or MASK_ALTIVEC settings; if the user wants
1687 either, the user must explicitly specify them and we won't interfere with
1688 the user's specification. */
1691 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1692 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1693 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1694 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1695 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP
1696 | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE
1697 | MASK_RECIP_PRECISION)
1700 /* Masks for instructions set at various powerpc ISAs. */
1702 ISA_2_1_MASKS = MASK_MFCRF,
1703 ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB),
1704 ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND),
1706 /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
1707 ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel,
1708 fre, fsqrt, etc. were no longer documented as optional. Group masks by
1709 server and embedded. */
1710 ISA_2_5_MASKS_EMBEDDED = (ISA_2_2_MASKS | MASK_CMPB | MASK_RECIP_PRECISION
1711 | MASK_PPC_GFXOPT | MASK_PPC_GPOPT),
1712 ISA_2_5_MASKS_SERVER = (ISA_2_5_MASKS_EMBEDDED | MASK_DFP),
1714 /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
1715 altivec is a win so enable it. */
1716 ISA_2_6_MASKS_EMBEDDED = (ISA_2_5_MASKS_EMBEDDED | MASK_POPCNTD),
1717 ISA_2_6_MASKS_SERVER = (ISA_2_5_MASKS_SERVER | MASK_POPCNTD | MASK_ALTIVEC
1723 const char *const name; /* Canonical processor name. */
1724 const enum processor_type processor; /* Processor type enum value. */
1725 const int target_enable; /* Target flags to enable. */
1728 static struct rs6000_ptt const processor_target_table[] =
1730 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1731 #include "rs6000-cpus.def"
1735 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1739 rs6000_cpu_name_lookup (const char *name)
1745 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
1746 if (! strcmp (name, processor_target_table[i].name))
1754 /* Return number of consecutive hard regs needed starting at reg REGNO
1755 to hold something of mode MODE.
1756 This is ordinarily the length in words of a value of mode MODE
1757 but can be less for certain modes in special long registers.
1759 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1760 scalar instructions. The upper 32 bits are only available to the
1763 POWER and PowerPC GPRs hold 32 bits worth;
1764 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1767 rs6000_hard_regno_nregs_internal (int regno, enum machine_mode mode)
1769 unsigned HOST_WIDE_INT reg_size;
1771 if (FP_REGNO_P (regno))
1772 reg_size = (VECTOR_MEM_VSX_P (mode)
1773 ? UNITS_PER_VSX_WORD
1774 : UNITS_PER_FP_WORD);
1776 else if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1777 reg_size = UNITS_PER_SPE_WORD;
1779 else if (ALTIVEC_REGNO_P (regno))
1780 reg_size = UNITS_PER_ALTIVEC_WORD;
1782 /* The value returned for SCmode in the E500 double case is 2 for
1783 ABI compatibility; storing an SCmode value in a single register
1784 would require function_arg and rs6000_spe_function_arg to handle
1785 SCmode so as to pass the value correctly in a pair of
1787 else if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode
1788 && !DECIMAL_FLOAT_MODE_P (mode))
1789 reg_size = UNITS_PER_FP_WORD;
1792 reg_size = UNITS_PER_WORD;
1794 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
1797 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1800 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1802 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
1804 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1805 implementations. Don't allow an item to be split between a FP register
1806 and an Altivec register. */
1807 if (VECTOR_MEM_VSX_P (mode))
1809 if (FP_REGNO_P (regno))
1810 return FP_REGNO_P (last_regno);
1812 if (ALTIVEC_REGNO_P (regno))
1813 return ALTIVEC_REGNO_P (last_regno);
1816 /* The GPRs can hold any mode, but values bigger than one register
1817 cannot go past R31. */
1818 if (INT_REGNO_P (regno))
1819 return INT_REGNO_P (last_regno);
1821 /* The float registers (except for VSX vector modes) can only hold floating
1822 modes and DImode. This excludes the 32-bit decimal float mode for
1824 if (FP_REGNO_P (regno))
1826 if (SCALAR_FLOAT_MODE_P (mode)
1827 && (mode != TDmode || (regno % 2) == 0)
1828 && FP_REGNO_P (last_regno))
1831 if (GET_MODE_CLASS (mode) == MODE_INT
1832 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
1835 if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
1836 && PAIRED_VECTOR_MODE (mode))
1842 /* The CR register can only hold CC modes. */
1843 if (CR_REGNO_P (regno))
1844 return GET_MODE_CLASS (mode) == MODE_CC;
1846 if (CA_REGNO_P (regno))
1847 return mode == BImode;
1849 /* AltiVec only in AldyVec registers. */
1850 if (ALTIVEC_REGNO_P (regno))
1851 return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode);
1853 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1854 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1857 /* We cannot put TImode anywhere except general register and it must be able
1858 to fit within the register set. In the future, allow TImode in the
1859 Altivec or VSX registers. */
1861 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1864 /* Print interesting facts about registers. */
1866 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
1870 for (r = first_regno; r <= last_regno; ++r)
1872 const char *comma = "";
1875 if (first_regno == last_regno)
1876 fprintf (stderr, "%s:\t", reg_name);
1878 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
1881 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1882 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
1886 fprintf (stderr, ",\n\t");
1891 if (rs6000_hard_regno_nregs[m][r] > 1)
1892 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
1893 rs6000_hard_regno_nregs[m][r]);
1895 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
1900 if (call_used_regs[r])
1904 fprintf (stderr, ",\n\t");
1909 len += fprintf (stderr, "%s%s", comma, "call-used");
1917 fprintf (stderr, ",\n\t");
1922 len += fprintf (stderr, "%s%s", comma, "fixed");
1928 fprintf (stderr, ",\n\t");
1932 fprintf (stderr, "%sregno = %d\n", comma, r);
1936 #define DEBUG_FMT_D "%-32s= %d\n"
1937 #define DEBUG_FMT_X "%-32s= 0x%x\n"
1938 #define DEBUG_FMT_S "%-32s= %s\n"
1940 /* Print various interesting information with -mdebug=reg. */
1942 rs6000_debug_reg_global (void)
1944 static const char *const tf[2] = { "false", "true" };
1945 const char *nl = (const char *)0;
1947 char costly_num[20];
1949 const char *costly_str;
1950 const char *nop_str;
1951 const char *trace_str;
1952 const char *abi_str;
1953 const char *cmodel_str;
1955 /* Map enum rs6000_vector to string. */
1956 static const char *rs6000_debug_vector_unit[] = {
1965 fprintf (stderr, "Register information: (last virtual reg = %d)\n",
1966 LAST_VIRTUAL_REGISTER);
1967 rs6000_debug_reg_print (0, 31, "gr");
1968 rs6000_debug_reg_print (32, 63, "fp");
1969 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
1972 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
1973 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
1974 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
1975 rs6000_debug_reg_print (MQ_REGNO, MQ_REGNO, "mq");
1976 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
1977 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
1978 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
1979 rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a");
1980 rs6000_debug_reg_print (SPEFSCR_REGNO, SPEFSCR_REGNO, "spe_f");
1984 "d reg_class = %s\n"
1985 "f reg_class = %s\n"
1986 "v reg_class = %s\n"
1987 "wa reg_class = %s\n"
1988 "wd reg_class = %s\n"
1989 "wf reg_class = %s\n"
1990 "ws reg_class = %s\n\n",
1991 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
1992 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
1993 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
1994 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
1995 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
1996 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
1997 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]]);
1999 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2000 if (rs6000_vector_unit[m] || rs6000_vector_mem[m])
2003 fprintf (stderr, "Vector mode: %-5s arithmetic: %-8s move: %-8s\n",
2005 rs6000_debug_vector_unit[ rs6000_vector_unit[m] ],
2006 rs6000_debug_vector_unit[ rs6000_vector_mem[m] ]);
2012 if (rs6000_recip_control)
2014 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
2016 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2017 if (rs6000_recip_bits[m])
2020 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2022 (RS6000_RECIP_AUTO_RE_P (m)
2024 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
2025 (RS6000_RECIP_AUTO_RSQRTE_P (m)
2027 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
2030 fputs ("\n", stderr);
2033 if (rs6000_cpu_index >= 0)
2034 fprintf (stderr, DEBUG_FMT_S, "cpu",
2035 processor_target_table[rs6000_cpu_index].name);
2037 if (rs6000_tune_index >= 0)
2038 fprintf (stderr, DEBUG_FMT_S, "tune",
2039 processor_target_table[rs6000_tune_index].name);
2041 switch (rs6000_sched_costly_dep)
2043 case max_dep_latency:
2044 costly_str = "max_dep_latency";
2048 costly_str = "no_dep_costly";
2051 case all_deps_costly:
2052 costly_str = "all_deps_costly";
2055 case true_store_to_load_dep_costly:
2056 costly_str = "true_store_to_load_dep_costly";
2059 case store_to_load_dep_costly:
2060 costly_str = "store_to_load_dep_costly";
2064 costly_str = costly_num;
2065 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
2069 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
2071 switch (rs6000_sched_insert_nops)
2073 case sched_finish_regroup_exact:
2074 nop_str = "sched_finish_regroup_exact";
2077 case sched_finish_pad_groups:
2078 nop_str = "sched_finish_pad_groups";
2081 case sched_finish_none:
2082 nop_str = "sched_finish_none";
2087 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
2091 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
2093 switch (rs6000_sdata)
2100 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
2104 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
2108 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
2113 switch (rs6000_traceback)
2115 case traceback_default: trace_str = "default"; break;
2116 case traceback_none: trace_str = "none"; break;
2117 case traceback_part: trace_str = "part"; break;
2118 case traceback_full: trace_str = "full"; break;
2119 default: trace_str = "unknown"; break;
2122 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
2124 switch (rs6000_current_cmodel)
2126 case CMODEL_SMALL: cmodel_str = "small"; break;
2127 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
2128 case CMODEL_LARGE: cmodel_str = "large"; break;
2129 default: cmodel_str = "unknown"; break;
2132 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
2134 switch (rs6000_current_abi)
2136 case ABI_NONE: abi_str = "none"; break;
2137 case ABI_AIX: abi_str = "aix"; break;
2138 case ABI_V4: abi_str = "V4"; break;
2139 case ABI_DARWIN: abi_str = "darwin"; break;
2140 default: abi_str = "unknown"; break;
2143 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
2145 if (rs6000_altivec_abi)
2146 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
2149 fprintf (stderr, DEBUG_FMT_S, "spe_abi", "true");
2151 if (rs6000_darwin64_abi)
2152 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
2154 if (rs6000_float_gprs)
2155 fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true");
2157 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
2158 fprintf (stderr, DEBUG_FMT_S, "align_branch",
2159 tf[!!rs6000_align_branch_targets]);
2160 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
2161 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
2162 rs6000_long_double_type_size);
2163 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
2164 (int)rs6000_sched_restricted_insns_priority);
2165 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
2167 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
2168 (int)RS6000_BUILTIN_COUNT);
2169 fprintf (stderr, DEBUG_FMT_X, "Builtin mask", rs6000_builtin_mask);
2172 /* Initialize the various global tables that are based on register size. */
2174 rs6000_init_hard_regno_mode_ok (bool global_init_p)
2180 /* Precalculate REGNO_REG_CLASS. */
2181 rs6000_regno_regclass[0] = GENERAL_REGS;
2182 for (r = 1; r < 32; ++r)
2183 rs6000_regno_regclass[r] = BASE_REGS;
2185 for (r = 32; r < 64; ++r)
2186 rs6000_regno_regclass[r] = FLOAT_REGS;
2188 for (r = 64; r < FIRST_PSEUDO_REGISTER; ++r)
2189 rs6000_regno_regclass[r] = NO_REGS;
2191 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
2192 rs6000_regno_regclass[r] = ALTIVEC_REGS;
2194 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
2195 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
2196 rs6000_regno_regclass[r] = CR_REGS;
2198 rs6000_regno_regclass[MQ_REGNO] = MQ_REGS;
2199 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
2200 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
2201 rs6000_regno_regclass[CA_REGNO] = CA_REGS;
2202 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
2203 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
2204 rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;
2205 rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS;
2206 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
2207 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
2209 /* Precalculate vector information, this must be set up before the
2210 rs6000_hard_regno_nregs_internal below. */
2211 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2213 rs6000_vector_unit[m] = rs6000_vector_mem[m] = VECTOR_NONE;
2214 rs6000_vector_reload[m][0] = CODE_FOR_nothing;
2215 rs6000_vector_reload[m][1] = CODE_FOR_nothing;
2218 for (c = 0; c < (int)(int)RS6000_CONSTRAINT_MAX; c++)
2219 rs6000_constraints[c] = NO_REGS;
2221 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2222 believes it can use native alignment or still uses 128-bit alignment. */
2223 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
2234 /* V2DF mode, VSX only. */
2237 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
2238 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
2239 rs6000_vector_align[V2DFmode] = align64;
2242 /* V4SF mode, either VSX or Altivec. */
2245 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
2246 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
2247 rs6000_vector_align[V4SFmode] = align32;
2249 else if (TARGET_ALTIVEC)
2251 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
2252 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
2253 rs6000_vector_align[V4SFmode] = align32;
2256 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2260 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
2261 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
2262 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
2263 rs6000_vector_align[V4SImode] = align32;
2264 rs6000_vector_align[V8HImode] = align32;
2265 rs6000_vector_align[V16QImode] = align32;
2269 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
2270 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
2271 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
2275 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
2276 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
2277 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
2281 /* V2DImode, only allow under VSX, which can do V2DI insert/splat/extract.
2282 Altivec doesn't have 64-bit support. */
2285 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
2286 rs6000_vector_unit[V2DImode] = VECTOR_NONE;
2287 rs6000_vector_align[V2DImode] = align64;
2290 /* DFmode, see if we want to use the VSX unit. */
2291 if (TARGET_VSX && TARGET_VSX_SCALAR_DOUBLE)
2293 rs6000_vector_unit[DFmode] = VECTOR_VSX;
2294 rs6000_vector_mem[DFmode]
2295 = (TARGET_VSX_SCALAR_MEMORY ? VECTOR_VSX : VECTOR_NONE);
2296 rs6000_vector_align[DFmode] = align64;
2299 /* TODO add SPE and paired floating point vector support. */
2301 /* Register class constaints for the constraints that depend on compile
2303 if (TARGET_HARD_FLOAT && TARGET_FPRS)
2304 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS;
2306 if (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
2307 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS;
2311 /* At present, we just use VSX_REGS, but we have different constraints
2312 based on the use, in case we want to fine tune the default register
2313 class used. wa = any VSX register, wf = register class to use for
2314 V4SF, wd = register class to use for V2DF, and ws = register classs to
2315 use for DF scalars. */
2316 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
2317 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS;
2318 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS;
2319 rs6000_constraints[RS6000_CONSTRAINT_ws] = (TARGET_VSX_SCALAR_MEMORY
2325 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
2327 /* Set up the reload helper functions. */
2328 if (TARGET_VSX || TARGET_ALTIVEC)
2332 rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_di_store;
2333 rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_di_load;
2334 rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_di_store;
2335 rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_di_load;
2336 rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_di_store;
2337 rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_di_load;
2338 rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_di_store;
2339 rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_di_load;
2340 rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_di_store;
2341 rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_di_load;
2342 rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_di_store;
2343 rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_di_load;
2344 if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY)
2346 rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_di_store;
2347 rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_di_load;
2352 rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_si_store;
2353 rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_si_load;
2354 rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_si_store;
2355 rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_si_load;
2356 rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_si_store;
2357 rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_si_load;
2358 rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_si_store;
2359 rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_si_load;
2360 rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_si_store;
2361 rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_si_load;
2362 rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_si_store;
2363 rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_si_load;
2364 if (TARGET_VSX && TARGET_VSX_SCALAR_MEMORY)
2366 rs6000_vector_reload[DFmode][0] = CODE_FOR_reload_df_si_store;
2367 rs6000_vector_reload[DFmode][1] = CODE_FOR_reload_df_si_load;
2372 /* Precalculate HARD_REGNO_NREGS. */
2373 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
2374 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2375 rs6000_hard_regno_nregs[m][r]
2376 = rs6000_hard_regno_nregs_internal (r, (enum machine_mode)m);
2378 /* Precalculate HARD_REGNO_MODE_OK. */
2379 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
2380 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2381 if (rs6000_hard_regno_mode_ok (r, (enum machine_mode)m))
2382 rs6000_hard_regno_mode_ok_p[m][r] = true;
2384 /* Precalculate CLASS_MAX_NREGS sizes. */
2385 for (c = 0; c < LIM_REG_CLASSES; ++c)
2389 if (TARGET_VSX && VSX_REG_CLASS_P (c))
2390 reg_size = UNITS_PER_VSX_WORD;
2392 else if (c == ALTIVEC_REGS)
2393 reg_size = UNITS_PER_ALTIVEC_WORD;
2395 else if (c == FLOAT_REGS)
2396 reg_size = UNITS_PER_FP_WORD;
2399 reg_size = UNITS_PER_WORD;
2401 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2402 rs6000_class_max_nregs[m][c]
2403 = (GET_MODE_SIZE (m) + reg_size - 1) / reg_size;
2406 if (TARGET_E500_DOUBLE)
2407 rs6000_class_max_nregs[DFmode][GENERAL_REGS] = 1;
2409 /* Calculate which modes to automatically generate code to use a the
2410 reciprocal divide and square root instructions. In the future, possibly
2411 automatically generate the instructions even if the user did not specify
2412 -mrecip. The older machines double precision reciprocal sqrt estimate is
2413 not accurate enough. */
2414 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
2416 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
2418 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
2419 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
2420 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
2421 if (VECTOR_UNIT_VSX_P (V2DFmode))
2422 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
2424 if (TARGET_FRSQRTES)
2425 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2427 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2428 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
2429 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2430 if (VECTOR_UNIT_VSX_P (V2DFmode))
2431 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2433 if (rs6000_recip_control)
2435 if (!flag_finite_math_only)
2436 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2437 if (flag_trapping_math)
2438 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2439 if (!flag_reciprocal_math)
2440 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2441 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
2443 if (RS6000_RECIP_HAVE_RE_P (SFmode)
2444 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
2445 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2447 if (RS6000_RECIP_HAVE_RE_P (DFmode)
2448 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
2449 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2451 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
2452 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
2453 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2455 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
2456 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
2457 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2459 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
2460 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
2461 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2463 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
2464 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
2465 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2467 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
2468 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
2469 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2471 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
2472 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
2473 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2477 if (global_init_p || TARGET_DEBUG_TARGET)
2479 if (TARGET_DEBUG_REG)
2480 rs6000_debug_reg_global ();
2482 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
2484 "SImode variable mult cost = %d\n"
2485 "SImode constant mult cost = %d\n"
2486 "SImode short constant mult cost = %d\n"
2487 "DImode multipliciation cost = %d\n"
2488 "SImode division cost = %d\n"
2489 "DImode division cost = %d\n"
2490 "Simple fp operation cost = %d\n"
2491 "DFmode multiplication cost = %d\n"
2492 "SFmode division cost = %d\n"
2493 "DFmode division cost = %d\n"
2494 "cache line size = %d\n"
2495 "l1 cache size = %d\n"
2496 "l2 cache size = %d\n"
2497 "simultaneous prefetches = %d\n"
2500 rs6000_cost->mulsi_const,
2501 rs6000_cost->mulsi_const9,
2509 rs6000_cost->cache_line_size,
2510 rs6000_cost->l1_cache_size,
2511 rs6000_cost->l2_cache_size,
2512 rs6000_cost->simultaneous_prefetches);
2517 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
2520 darwin_rs6000_override_options (void)
2522 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2524 rs6000_altivec_abi = 1;
2525 TARGET_ALTIVEC_VRSAVE = 1;
2526 rs6000_current_abi = ABI_DARWIN;
2528 if (DEFAULT_ABI == ABI_DARWIN
2530 darwin_one_byte_bool = 1;
2532 if (TARGET_64BIT && ! TARGET_POWERPC64)
2534 target_flags |= MASK_POWERPC64;
2535 warning (0, "-m64 requires PowerPC64 architecture, enabling");
2539 rs6000_default_long_calls = 1;
2540 target_flags |= MASK_SOFT_FLOAT;
2543 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
2545 if (!flag_mkernel && !flag_apple_kext
2547 && ! (target_flags_explicit & MASK_ALTIVEC))
2548 target_flags |= MASK_ALTIVEC;
2550 /* Unless the user (not the configurer) has explicitly overridden
2551 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
2552 G4 unless targetting the kernel. */
2555 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
2556 && ! (target_flags_explicit & MASK_ALTIVEC)
2557 && ! global_options_set.x_rs6000_cpu_index)
2559 target_flags |= MASK_ALTIVEC;
2564 /* If not otherwise specified by a target, make 'long double' equivalent to
2567 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
2568 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
2571 /* Return the builtin mask of the various options used that could affect which
2572 builtins were used. In the past we used target_flags, but we've run out of
2573 bits, and some options like SPE and PAIRED are no longer in
2577 rs6000_builtin_mask_calculate (void)
2579 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
2580 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
2581 | ((TARGET_SPE) ? RS6000_BTM_SPE : 0)
2582 | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)
2583 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
2584 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
2585 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
2586 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
2587 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
2588 | ((TARGET_POWERPC) ? RS6000_BTM_POWERPC : 0)
2589 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0));
2592 /* Override command line options. Mostly we process the processor type and
2593 sometimes adjust other TARGET_ options. */
2596 rs6000_option_override_internal (bool global_init_p)
2599 const char *default_cpu = OPTION_TARGET_CPU_DEFAULT;
2603 struct cl_target_option *main_target_opt
2604 = ((global_init_p || target_option_default_node == NULL)
2605 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
2607 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
2608 library functions, so warn about it. The flag may be useful for
2609 performance studies from time to time though, so don't disable it
2611 if (global_options_set.x_rs6000_alignment_flags
2612 && rs6000_alignment_flags == MASK_ALIGN_POWER
2613 && DEFAULT_ABI == ABI_DARWIN
2615 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2616 " it is incompatible with the installed C and C++ libraries");
2618 if (global_options_set.x_rs6000_spe_abi
2621 error ("not configured for SPE ABI");
2623 /* Numerous experiment shows that IRA based loop pressure
2624 calculation works better for RTL loop invariant motion on targets
2625 with enough (>= 32) registers. It is an expensive optimization.
2626 So it is on only for peak performance. */
2627 if (optimize >= 3 && global_init_p)
2628 flag_ira_loop_pressure = 1;
2630 /* Set the pointer size. */
2633 rs6000_pmode = (int)DImode;
2634 rs6000_pointer_size = 64;
2638 rs6000_pmode = (int)SImode;
2639 rs6000_pointer_size = 32;
2642 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
2643 #ifdef OS_MISSING_POWERPC64
2644 if (OS_MISSING_POWERPC64)
2645 set_masks &= ~MASK_POWERPC64;
2647 #ifdef OS_MISSING_ALTIVEC
2648 if (OS_MISSING_ALTIVEC)
2649 set_masks &= ~MASK_ALTIVEC;
2652 /* Don't override by the processor default if given explicitly. */
2653 set_masks &= ~target_flags_explicit;
2655 /* Identify the processor type. */
2658 if (TARGET_POWERPC64)
2659 default_cpu = "powerpc64";
2660 else if (TARGET_POWERPC)
2661 default_cpu = "powerpc";
2664 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
2665 the cpu in a target attribute or pragma, but did not specify a tuning
2666 option, use the cpu for the tuning option rather than the option specified
2667 with -mtune on the command line. */
2668 if (rs6000_cpu_index > 0)
2669 cpu_index = rs6000_cpu_index;
2670 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index > 0)
2671 rs6000_cpu_index = cpu_index = main_target_opt->x_rs6000_cpu_index;
2673 rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (default_cpu);
2675 if (rs6000_tune_index > 0)
2676 tune_index = rs6000_tune_index;
2678 rs6000_tune_index = tune_index = cpu_index;
2682 target_flags &= ~set_masks;
2683 target_flags |= (processor_target_table[cpu_index].target_enable
2687 rs6000_cpu = ((tune_index >= 0)
2688 ? processor_target_table[tune_index].processor
2690 ? PROCESSOR_DEFAULT64
2691 : PROCESSOR_DEFAULT));
2693 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
2694 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64)
2697 error ("AltiVec not supported in this target");
2699 error ("SPE not supported in this target");
2702 /* Disable Cell microcode if we are optimizing for the Cell
2703 and not optimizing for size. */
2704 if (rs6000_gen_cell_microcode == -1)
2705 rs6000_gen_cell_microcode = !(rs6000_cpu == PROCESSOR_CELL
2708 /* If we are optimizing big endian systems for space and it's OK to
2709 use instructions that would be microcoded on the Cell, use the
2710 load/store multiple and string instructions. */
2711 if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode)
2712 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
2714 /* Don't allow -mmultiple or -mstring on little endian systems
2715 unless the cpu is a 750, because the hardware doesn't support the
2716 instructions used in little endian mode, and causes an alignment
2717 trap. The 750 does not cause an alignment trap (except when the
2718 target is unaligned). */
2720 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
2722 if (TARGET_MULTIPLE)
2724 target_flags &= ~MASK_MULTIPLE;
2725 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
2726 warning (0, "-mmultiple is not supported on little endian systems");
2731 target_flags &= ~MASK_STRING;
2732 if ((target_flags_explicit & MASK_STRING) != 0)
2733 warning (0, "-mstring is not supported on little endian systems");
2737 /* Add some warnings for VSX. */
2740 const char *msg = NULL;
2741 if (!TARGET_HARD_FLOAT || !TARGET_FPRS
2742 || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
2744 if (target_flags_explicit & MASK_VSX)
2745 msg = N_("-mvsx requires hardware floating point");
2747 target_flags &= ~ MASK_VSX;
2749 else if (TARGET_PAIRED_FLOAT)
2750 msg = N_("-mvsx and -mpaired are incompatible");
2751 /* The hardware will allow VSX and little endian, but until we make sure
2752 things like vector select, etc. work don't allow VSX on little endian
2753 systems at this point. */
2754 else if (!BYTES_BIG_ENDIAN)
2755 msg = N_("-mvsx used with little endian code");
2756 else if (TARGET_AVOID_XFORM > 0)
2757 msg = N_("-mvsx needs indexed addressing");
2758 else if (!TARGET_ALTIVEC && (target_flags_explicit & MASK_ALTIVEC))
2760 if (target_flags_explicit & MASK_VSX)
2761 msg = N_("-mvsx and -mno-altivec are incompatible");
2763 msg = N_("-mno-altivec disables vsx");
2769 target_flags &= ~ MASK_VSX;
2770 target_flags_explicit |= MASK_VSX;
2774 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
2775 unless the user explicitly used the -mno-<option> to disable the code. */
2777 target_flags |= (ISA_2_6_MASKS_SERVER & ~target_flags_explicit);
2778 else if (TARGET_POPCNTD)
2779 target_flags |= (ISA_2_6_MASKS_EMBEDDED & ~target_flags_explicit);
2780 else if (TARGET_DFP)
2781 target_flags |= (ISA_2_5_MASKS_SERVER & ~target_flags_explicit);
2782 else if (TARGET_CMPB)
2783 target_flags |= (ISA_2_5_MASKS_EMBEDDED & ~target_flags_explicit);
2784 else if (TARGET_FPRND)
2785 target_flags |= (ISA_2_4_MASKS & ~target_flags_explicit);
2786 else if (TARGET_POPCNTB)
2787 target_flags |= (ISA_2_2_MASKS & ~target_flags_explicit);
2788 else if (TARGET_ALTIVEC)
2789 target_flags |= (MASK_PPC_GFXOPT & ~target_flags_explicit);
2791 /* E500mc does "better" if we inline more aggressively. Respect the
2792 user's opinion, though. */
2793 if (rs6000_block_move_inline_limit == 0
2794 && (rs6000_cpu == PROCESSOR_PPCE500MC
2795 || rs6000_cpu == PROCESSOR_PPCE500MC64))
2796 rs6000_block_move_inline_limit = 128;
2798 /* store_one_arg depends on expand_block_move to handle at least the
2799 size of reg_parm_stack_space. */
2800 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
2801 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
2805 /* If the appropriate debug option is enabled, replace the target hooks
2806 with debug versions that call the real version and then prints
2807 debugging information. */
2808 if (TARGET_DEBUG_COST)
2810 targetm.rtx_costs = rs6000_debug_rtx_costs;
2811 targetm.address_cost = rs6000_debug_address_cost;
2812 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
2815 if (TARGET_DEBUG_ADDR)
2817 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
2818 targetm.legitimize_address = rs6000_debug_legitimize_address;
2819 rs6000_secondary_reload_class_ptr
2820 = rs6000_debug_secondary_reload_class;
2821 rs6000_secondary_memory_needed_ptr
2822 = rs6000_debug_secondary_memory_needed;
2823 rs6000_cannot_change_mode_class_ptr
2824 = rs6000_debug_cannot_change_mode_class;
2825 rs6000_preferred_reload_class_ptr
2826 = rs6000_debug_preferred_reload_class;
2827 rs6000_legitimize_reload_address_ptr
2828 = rs6000_debug_legitimize_reload_address;
2829 rs6000_mode_dependent_address_ptr
2830 = rs6000_debug_mode_dependent_address;
2833 if (rs6000_veclibabi_name)
2835 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
2836 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
2839 error ("unknown vectorization library ABI type (%s) for "
2840 "-mveclibabi= switch", rs6000_veclibabi_name);
2846 if (!global_options_set.x_rs6000_long_double_type_size)
2848 if (main_target_opt != NULL
2849 && (main_target_opt->x_rs6000_long_double_type_size
2850 != RS6000_DEFAULT_LONG_DOUBLE_SIZE))
2851 error ("target attribute or pragma changes long double size");
2853 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2856 #ifndef POWERPC_LINUX
2857 if (!global_options_set.x_rs6000_ieeequad)
2858 rs6000_ieeequad = 1;
2861 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
2862 target attribute or pragma which automatically enables both options,
2863 unless the altivec ABI was set. This is set by default for 64-bit, but
2865 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
2866 target_flags &= ~((MASK_VSX | MASK_ALTIVEC) & ~target_flags_explicit);
2868 /* Enable Altivec ABI for AIX -maltivec. */
2869 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
2871 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
2872 error ("target attribute or pragma changes AltiVec ABI");
2874 rs6000_altivec_abi = 1;
2877 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
2878 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
2879 be explicitly overridden in either case. */
2882 if (!global_options_set.x_rs6000_altivec_abi
2883 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
2885 if (main_target_opt != NULL &&
2886 !main_target_opt->x_rs6000_altivec_abi)
2887 error ("target attribute or pragma changes AltiVec ABI");
2889 rs6000_altivec_abi = 1;
2892 /* Enable VRSAVE for AltiVec ABI, unless explicitly overridden. */
2893 if (!global_options_set.x_TARGET_ALTIVEC_VRSAVE)
2894 TARGET_ALTIVEC_VRSAVE = rs6000_altivec_abi;
2897 /* Set the Darwin64 ABI as default for 64-bit Darwin.
2898 So far, the only darwin64 targets are also MACH-O. */
2900 && DEFAULT_ABI == ABI_DARWIN
2903 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
2904 error ("target attribute or pragma changes darwin64 ABI");
2907 rs6000_darwin64_abi = 1;
2908 /* Default to natural alignment, for better performance. */
2909 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2913 /* Place FP constants in the constant pool instead of TOC
2914 if section anchors enabled. */
2915 if (flag_section_anchors)
2916 TARGET_NO_FP_IN_TOC = 1;
2918 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2919 SUBTARGET_OVERRIDE_OPTIONS;
2921 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2922 SUBSUBTARGET_OVERRIDE_OPTIONS;
2924 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
2925 SUB3TARGET_OVERRIDE_OPTIONS;
2928 if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC
2929 || rs6000_cpu == PROCESSOR_PPCE500MC64)
2931 /* The e500 and e500mc do not have string instructions, and we set
2932 MASK_STRING above when optimizing for size. */
2933 if ((target_flags & MASK_STRING) != 0)
2934 target_flags = target_flags & ~MASK_STRING;
2936 else if (global_options_set.x_rs6000_cpu_index)
2938 /* For the powerpc-eabispe configuration, we set all these by
2939 default, so let's unset them if we manually set another
2940 CPU that is not the E500. */
2941 if (main_target_opt != NULL
2942 && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi)
2943 || (main_target_opt->x_rs6000_spe != rs6000_spe)
2944 || (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs)))
2945 error ("target attribute or pragma changes SPE ABI");
2948 if (!global_options_set.x_rs6000_spe_abi)
2950 if (!global_options_set.x_rs6000_spe)
2952 if (!global_options_set.x_rs6000_float_gprs)
2953 rs6000_float_gprs = 0;
2955 if (!(target_flags_explicit & MASK_ISEL))
2956 target_flags &= ~MASK_ISEL;
2959 /* Detect invalid option combinations with E500. */
2962 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
2963 && rs6000_cpu != PROCESSOR_POWER5
2964 && rs6000_cpu != PROCESSOR_POWER6
2965 && rs6000_cpu != PROCESSOR_POWER7
2966 && rs6000_cpu != PROCESSOR_PPCA2
2967 && rs6000_cpu != PROCESSOR_CELL
2968 && rs6000_cpu != PROCESSOR_PPC476);
2969 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
2970 || rs6000_cpu == PROCESSOR_POWER5
2971 || rs6000_cpu == PROCESSOR_POWER7);
2972 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
2973 || rs6000_cpu == PROCESSOR_POWER5
2974 || rs6000_cpu == PROCESSOR_POWER6
2975 || rs6000_cpu == PROCESSOR_POWER7
2976 || rs6000_cpu == PROCESSOR_PPCE500MC
2977 || rs6000_cpu == PROCESSOR_PPCE500MC64);
2979 /* Allow debug switches to override the above settings. These are set to -1
2980 in rs6000.opt to indicate the user hasn't directly set the switch. */
2981 if (TARGET_ALWAYS_HINT >= 0)
2982 rs6000_always_hint = TARGET_ALWAYS_HINT;
2984 if (TARGET_SCHED_GROUPS >= 0)
2985 rs6000_sched_groups = TARGET_SCHED_GROUPS;
2987 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
2988 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
2990 rs6000_sched_restricted_insns_priority
2991 = (rs6000_sched_groups ? 1 : 0);
2993 /* Handle -msched-costly-dep option. */
2994 rs6000_sched_costly_dep
2995 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
2997 if (rs6000_sched_costly_dep_str)
2999 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
3000 rs6000_sched_costly_dep = no_dep_costly;
3001 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
3002 rs6000_sched_costly_dep = all_deps_costly;
3003 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
3004 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
3005 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
3006 rs6000_sched_costly_dep = store_to_load_dep_costly;
3008 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
3009 atoi (rs6000_sched_costly_dep_str));
3012 /* Handle -minsert-sched-nops option. */
3013 rs6000_sched_insert_nops
3014 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
3016 if (rs6000_sched_insert_nops_str)
3018 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
3019 rs6000_sched_insert_nops = sched_finish_none;
3020 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
3021 rs6000_sched_insert_nops = sched_finish_pad_groups;
3022 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
3023 rs6000_sched_insert_nops = sched_finish_regroup_exact;
3025 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
3026 atoi (rs6000_sched_insert_nops_str));
3031 #ifdef TARGET_REGNAMES
3032 /* If the user desires alternate register names, copy in the
3033 alternate names now. */
3034 if (TARGET_REGNAMES)
3035 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
3038 /* Set aix_struct_return last, after the ABI is determined.
3039 If -maix-struct-return or -msvr4-struct-return was explicitly
3040 used, don't override with the ABI default. */
3041 if (!global_options_set.x_aix_struct_return)
3042 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
3045 /* IBM XL compiler defaults to unsigned bitfields. */
3046 if (TARGET_XL_COMPAT)
3047 flag_signed_bitfields = 0;
3050 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
3051 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
3054 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
3056 /* We can only guarantee the availability of DI pseudo-ops when
3057 assembling for 64-bit targets. */
3060 targetm.asm_out.aligned_op.di = NULL;
3061 targetm.asm_out.unaligned_op.di = NULL;
3065 /* Set branch target alignment, if not optimizing for size. */
3068 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
3069 aligned 8byte to avoid misprediction by the branch predictor. */
3070 if (rs6000_cpu == PROCESSOR_TITAN
3071 || rs6000_cpu == PROCESSOR_CELL)
3073 if (align_functions <= 0)
3074 align_functions = 8;
3075 if (align_jumps <= 0)
3077 if (align_loops <= 0)
3080 if (rs6000_align_branch_targets)
3082 if (align_functions <= 0)
3083 align_functions = 16;
3084 if (align_jumps <= 0)
3086 if (align_loops <= 0)
3088 can_override_loop_align = 1;
3092 if (align_jumps_max_skip <= 0)
3093 align_jumps_max_skip = 15;
3094 if (align_loops_max_skip <= 0)
3095 align_loops_max_skip = 15;
3098 /* Arrange to save and restore machine status around nested functions. */
3099 init_machine_status = rs6000_init_machine_status;
3101 /* We should always be splitting complex arguments, but we can't break
3102 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
3103 if (DEFAULT_ABI != ABI_AIX)
3104 targetm.calls.split_complex_arg = NULL;
3107 /* Initialize rs6000_cost with the appropriate target costs. */
3109 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
3113 case PROCESSOR_RIOS1:
3114 rs6000_cost = &rios1_cost;
3117 case PROCESSOR_RIOS2:
3118 rs6000_cost = &rios2_cost;
3121 case PROCESSOR_RS64A:
3122 rs6000_cost = &rs64a_cost;
3125 case PROCESSOR_MPCCORE:
3126 rs6000_cost = &mpccore_cost;
3129 case PROCESSOR_PPC403:
3130 rs6000_cost = &ppc403_cost;
3133 case PROCESSOR_PPC405:
3134 rs6000_cost = &ppc405_cost;
3137 case PROCESSOR_PPC440:
3138 rs6000_cost = &ppc440_cost;
3141 case PROCESSOR_PPC476:
3142 rs6000_cost = &ppc476_cost;
3145 case PROCESSOR_PPC601:
3146 rs6000_cost = &ppc601_cost;
3149 case PROCESSOR_PPC603:
3150 rs6000_cost = &ppc603_cost;
3153 case PROCESSOR_PPC604:
3154 rs6000_cost = &ppc604_cost;
3157 case PROCESSOR_PPC604e:
3158 rs6000_cost = &ppc604e_cost;
3161 case PROCESSOR_PPC620:
3162 rs6000_cost = &ppc620_cost;
3165 case PROCESSOR_PPC630:
3166 rs6000_cost = &ppc630_cost;
3169 case PROCESSOR_CELL:
3170 rs6000_cost = &ppccell_cost;
3173 case PROCESSOR_PPC750:
3174 case PROCESSOR_PPC7400:
3175 rs6000_cost = &ppc750_cost;
3178 case PROCESSOR_PPC7450:
3179 rs6000_cost = &ppc7450_cost;
3182 case PROCESSOR_PPC8540:
3183 rs6000_cost = &ppc8540_cost;
3186 case PROCESSOR_PPCE300C2:
3187 case PROCESSOR_PPCE300C3:
3188 rs6000_cost = &ppce300c2c3_cost;
3191 case PROCESSOR_PPCE500MC:
3192 rs6000_cost = &ppce500mc_cost;
3195 case PROCESSOR_PPCE500MC64:
3196 rs6000_cost = &ppce500mc64_cost;
3199 case PROCESSOR_TITAN:
3200 rs6000_cost = &titan_cost;
3203 case PROCESSOR_POWER4:
3204 case PROCESSOR_POWER5:
3205 rs6000_cost = &power4_cost;
3208 case PROCESSOR_POWER6:
3209 rs6000_cost = &power6_cost;
3212 case PROCESSOR_POWER7:
3213 rs6000_cost = &power7_cost;
3216 case PROCESSOR_PPCA2:
3217 rs6000_cost = &ppca2_cost;
3226 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
3227 rs6000_cost->simultaneous_prefetches,
3228 global_options.x_param_values,
3229 global_options_set.x_param_values);
3230 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
3231 global_options.x_param_values,
3232 global_options_set.x_param_values);
3233 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
3234 rs6000_cost->cache_line_size,
3235 global_options.x_param_values,
3236 global_options_set.x_param_values);
3237 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
3238 global_options.x_param_values,
3239 global_options_set.x_param_values);
3241 /* If using typedef char *va_list, signal that
3242 __builtin_va_start (&ap, 0) can be optimized to
3243 ap = __builtin_next_arg (0). */
3244 if (DEFAULT_ABI != ABI_V4)
3245 targetm.expand_builtin_va_start = NULL;
3248 /* Set up single/double float flags.
3249 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3250 then set both flags. */
3251 if (TARGET_HARD_FLOAT && TARGET_FPRS
3252 && rs6000_single_float == 0 && rs6000_double_float == 0)
3253 rs6000_single_float = rs6000_double_float = 1;
3255 /* Reset single and double FP flags if target is E500. */
3258 rs6000_single_float = rs6000_double_float = 0;
3259 if (TARGET_E500_SINGLE)
3260 rs6000_single_float = 1;
3261 if (TARGET_E500_DOUBLE)
3262 rs6000_single_float = rs6000_double_float = 1;
3265 if (main_target_opt)
3267 if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
3268 error ("target attribute or pragma changes single precision floating "
3270 if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
3271 error ("target attribute or pragma changes double precision floating "
3275 /* If not explicitly specified via option, decide whether to generate indexed
3276 load/store instructions. */
3277 if (TARGET_AVOID_XFORM == -1)
3278 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3279 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3280 need indexed accesses and the type used is the scalar type of the element
3281 being loaded or stored. */
3282 TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB
3283 && !TARGET_ALTIVEC);
3285 /* Set the -mrecip options. */
3286 if (rs6000_recip_name)
3288 char *p = ASTRDUP (rs6000_recip_name);
3290 unsigned int mask, i;
3293 while ((q = strtok (p, ",")) != NULL)
3304 if (!strcmp (q, "default"))
3305 mask = ((TARGET_RECIP_PRECISION)
3306 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
3309 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
3310 if (!strcmp (q, recip_options[i].string))
3312 mask = recip_options[i].mask;
3316 if (i == ARRAY_SIZE (recip_options))
3318 error ("unknown option for -mrecip=%s", q);
3326 rs6000_recip_control &= ~mask;
3328 rs6000_recip_control |= mask;
3332 /* Set the builtin mask of the various options used that could affect which
3333 builtins were used. In the past we used target_flags, but we've run out
3334 of bits, and some options like SPE and PAIRED are no longer in
3336 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
3337 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
3338 fprintf (stderr, "new builtin mask = 0x%x%s%s%s%s\n", rs6000_builtin_mask,
3339 (rs6000_builtin_mask & RS6000_BTM_ALTIVEC) ? ", altivec" : "",
3340 (rs6000_builtin_mask & RS6000_BTM_VSX) ? ", vsx" : "",
3341 (rs6000_builtin_mask & RS6000_BTM_PAIRED) ? ", paired" : "",
3342 (rs6000_builtin_mask & RS6000_BTM_SPE) ? ", spe" : "");
3344 /* Initialize all of the registers. */
3345 rs6000_init_hard_regno_mode_ok (global_init_p);
3347 /* Save the initial options in case the user does function specific options */
3349 target_option_default_node = target_option_current_node
3350 = build_target_option_node ();
3352 /* If not explicitly specified via option, decide whether to generate the
3353 extra blr's required to preserve the link stack on some cpus (eg, 476). */
3354 if (TARGET_LINK_STACK == -1)
3355 SET_TARGET_LINK_STACK (rs6000_cpu == PROCESSOR_PPC476 && flag_pic);
3360 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
3361 define the target cpu type. */
3364 rs6000_option_override (void)
3366 (void) rs6000_option_override_internal (true);
3370 /* Implement targetm.vectorize.builtin_mask_for_load. */
3372 rs6000_builtin_mask_for_load (void)
3374 if (TARGET_ALTIVEC || TARGET_VSX)
3375 return altivec_builtin_mask_for_load;
3380 /* Implement LOOP_ALIGN. */
3382 rs6000_loop_align (rtx label)
3387 /* Don't override loop alignment if -falign-loops was specified. */
3388 if (!can_override_loop_align)
3389 return align_loops_log;
3391 bb = BLOCK_FOR_INSN (label);
3392 ninsns = num_loop_insns(bb->loop_father);
3394 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
3395 if (ninsns > 4 && ninsns <= 8
3396 && (rs6000_cpu == PROCESSOR_POWER4
3397 || rs6000_cpu == PROCESSOR_POWER5
3398 || rs6000_cpu == PROCESSOR_POWER6
3399 || rs6000_cpu == PROCESSOR_POWER7))
3402 return align_loops_log;
3405 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
3407 rs6000_loop_align_max_skip (rtx label)
3409 return (1 << rs6000_loop_align (label)) - 1;
3412 /* Implement targetm.vectorize.builtin_mul_widen_even. */
3414 rs6000_builtin_mul_widen_even (tree type)
3416 if (!TARGET_ALTIVEC)
3419 switch (TYPE_MODE (type))
3422 return TYPE_UNSIGNED (type)
3423 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH_UNS]
3424 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
3427 return TYPE_UNSIGNED (type)
3428 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB_UNS]
3429 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
3435 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
3437 rs6000_builtin_mul_widen_odd (tree type)
3439 if (!TARGET_ALTIVEC)
3442 switch (TYPE_MODE (type))
3445 return TYPE_UNSIGNED (type)
3446 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH_UNS]
3447 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
3450 return TYPE_UNSIGNED (type)
3451 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB_UNS]
3452 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
3459 /* Return true iff, data reference of TYPE can reach vector alignment (16)
3460 after applying N number of iterations. This routine does not determine
3461 how may iterations are required to reach desired alignment. */
3464 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
3471 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
3474 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
3484 /* Assuming that all other types are naturally aligned. CHECKME! */
3489 /* Return true if the vector misalignment factor is supported by the
3492 rs6000_builtin_support_vector_misalignment (enum machine_mode mode,
3499 /* Return if movmisalign pattern is not supported for this mode. */
3500 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
3503 if (misalignment == -1)
3505 /* Misalignment factor is unknown at compile time but we know
3506 it's word aligned. */
3507 if (rs6000_vector_alignment_reachable (type, is_packed))
3509 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
3511 if (element_size == 64 || element_size == 32)
3518 /* VSX supports word-aligned vector. */
3519 if (misalignment % 4 == 0)
3525 /* Implement targetm.vectorize.builtin_vectorization_cost. */
3527 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
3528 tree vectype, int misalign)
3532 switch (type_of_cost)
3542 case cond_branch_not_taken:
3550 case cond_branch_taken:
3553 case unaligned_load:
3554 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
3556 elements = TYPE_VECTOR_SUBPARTS (vectype);
3558 /* Double word aligned. */
3566 /* Double word aligned. */
3570 /* Unknown misalignment. */
3583 /* Misaligned loads are not supported. */
3588 case unaligned_store:
3589 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
3591 elements = TYPE_VECTOR_SUBPARTS (vectype);
3593 /* Double word aligned. */
3601 /* Double word aligned. */
3605 /* Unknown misalignment. */
3618 /* Misaligned stores are not supported. */
3628 /* Implement targetm.vectorize.preferred_simd_mode. */
3630 static enum machine_mode
3631 rs6000_preferred_simd_mode (enum machine_mode mode)
3640 if (TARGET_ALTIVEC || TARGET_VSX)
3664 if (TARGET_PAIRED_FLOAT
3670 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
3671 library with vectorized intrinsics. */
3674 rs6000_builtin_vectorized_libmass (tree fndecl, tree type_out, tree type_in)
3677 const char *suffix = NULL;
3678 tree fntype, new_fndecl, bdecl = NULL_TREE;
3681 enum machine_mode el_mode, in_mode;
3684 /* Libmass is suitable for unsafe math only as it does not correctly support
3685 parts of IEEE with the required precision such as denormals. Only support
3686 it if we have VSX to use the simd d2 or f4 functions.
3687 XXX: Add variable length support. */
3688 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
3691 el_mode = TYPE_MODE (TREE_TYPE (type_out));
3692 n = TYPE_VECTOR_SUBPARTS (type_out);
3693 in_mode = TYPE_MODE (TREE_TYPE (type_in));
3694 in_n = TYPE_VECTOR_SUBPARTS (type_in);
3695 if (el_mode != in_mode
3699 if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL)
3701 enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
3704 case BUILT_IN_ATAN2:
3705 case BUILT_IN_HYPOT:
3711 case BUILT_IN_ACOSH:
3713 case BUILT_IN_ASINH:
3715 case BUILT_IN_ATANH:
3723 case BUILT_IN_EXPM1:
3724 case BUILT_IN_LGAMMA:
3725 case BUILT_IN_LOG10:
3726 case BUILT_IN_LOG1P:
3734 bdecl = builtin_decl_implicit (fn);
3735 suffix = "d2"; /* pow -> powd2 */
3736 if (el_mode != DFmode
3741 case BUILT_IN_ATAN2F:
3742 case BUILT_IN_HYPOTF:
3747 case BUILT_IN_ACOSF:
3748 case BUILT_IN_ACOSHF:
3749 case BUILT_IN_ASINF:
3750 case BUILT_IN_ASINHF:
3751 case BUILT_IN_ATANF:
3752 case BUILT_IN_ATANHF:
3753 case BUILT_IN_CBRTF:
3755 case BUILT_IN_COSHF:
3757 case BUILT_IN_ERFCF:
3758 case BUILT_IN_EXP2F:
3760 case BUILT_IN_EXPM1F:
3761 case BUILT_IN_LGAMMAF:
3762 case BUILT_IN_LOG10F:
3763 case BUILT_IN_LOG1PF:
3764 case BUILT_IN_LOG2F:
3767 case BUILT_IN_SINHF:
3768 case BUILT_IN_SQRTF:
3770 case BUILT_IN_TANHF:
3771 bdecl = builtin_decl_implicit (fn);
3772 suffix = "4"; /* powf -> powf4 */
3773 if (el_mode != SFmode
3785 gcc_assert (suffix != NULL);
3786 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
3787 strcpy (name, bname + sizeof ("__builtin_") - 1);
3788 strcat (name, suffix);
3791 fntype = build_function_type_list (type_out, type_in, NULL);
3792 else if (n_args == 2)
3793 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
3797 /* Build a function declaration for the vectorized function. */
3798 new_fndecl = build_decl (BUILTINS_LOCATION,
3799 FUNCTION_DECL, get_identifier (name), fntype);
3800 TREE_PUBLIC (new_fndecl) = 1;
3801 DECL_EXTERNAL (new_fndecl) = 1;
3802 DECL_IS_NOVOPS (new_fndecl) = 1;
3803 TREE_READONLY (new_fndecl) = 1;
3808 /* Returns a function decl for a vectorized version of the builtin function
3809 with builtin function code FN and the result vector type TYPE, or NULL_TREE
3810 if it is not available. */
3813 rs6000_builtin_vectorized_function (tree fndecl, tree type_out,
3816 enum machine_mode in_mode, out_mode;
3819 if (TARGET_DEBUG_BUILTIN)
3820 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
3821 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
3822 GET_MODE_NAME (TYPE_MODE (type_out)),
3823 GET_MODE_NAME (TYPE_MODE (type_in)));
3825 if (TREE_CODE (type_out) != VECTOR_TYPE
3826 || TREE_CODE (type_in) != VECTOR_TYPE
3827 || !TARGET_VECTORIZE_BUILTINS)
3830 out_mode = TYPE_MODE (TREE_TYPE (type_out));
3831 out_n = TYPE_VECTOR_SUBPARTS (type_out);
3832 in_mode = TYPE_MODE (TREE_TYPE (type_in));
3833 in_n = TYPE_VECTOR_SUBPARTS (type_in);
3835 if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL)
3837 enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
3840 case BUILT_IN_COPYSIGN:
3841 if (VECTOR_UNIT_VSX_P (V2DFmode)
3842 && out_mode == DFmode && out_n == 2
3843 && in_mode == DFmode && in_n == 2)
3844 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
3846 case BUILT_IN_COPYSIGNF:
3847 if (out_mode != SFmode || out_n != 4
3848 || in_mode != SFmode || in_n != 4)
3850 if (VECTOR_UNIT_VSX_P (V4SFmode))
3851 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
3852 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3853 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
3856 if (VECTOR_UNIT_VSX_P (V2DFmode)
3857 && out_mode == DFmode && out_n == 2
3858 && in_mode == DFmode && in_n == 2)
3859 return rs6000_builtin_decls[VSX_BUILTIN_XVSQRTDP];
3861 case BUILT_IN_SQRTF:
3862 if (VECTOR_UNIT_VSX_P (V4SFmode)
3863 && out_mode == SFmode && out_n == 4
3864 && in_mode == SFmode && in_n == 4)
3865 return rs6000_builtin_decls[VSX_BUILTIN_XVSQRTSP];
3868 if (VECTOR_UNIT_VSX_P (V2DFmode)
3869 && out_mode == DFmode && out_n == 2
3870 && in_mode == DFmode && in_n == 2)
3871 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
3873 case BUILT_IN_CEILF:
3874 if (out_mode != SFmode || out_n != 4
3875 || in_mode != SFmode || in_n != 4)
3877 if (VECTOR_UNIT_VSX_P (V4SFmode))
3878 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
3879 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3880 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
3882 case BUILT_IN_FLOOR:
3883 if (VECTOR_UNIT_VSX_P (V2DFmode)
3884 && out_mode == DFmode && out_n == 2
3885 && in_mode == DFmode && in_n == 2)
3886 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
3888 case BUILT_IN_FLOORF:
3889 if (out_mode != SFmode || out_n != 4
3890 || in_mode != SFmode || in_n != 4)
3892 if (VECTOR_UNIT_VSX_P (V4SFmode))
3893 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
3894 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3895 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
3898 if (VECTOR_UNIT_VSX_P (V2DFmode)
3899 && out_mode == DFmode && out_n == 2
3900 && in_mode == DFmode && in_n == 2)
3901 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
3904 if (VECTOR_UNIT_VSX_P (V4SFmode)
3905 && out_mode == SFmode && out_n == 4
3906 && in_mode == SFmode && in_n == 4)
3907 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
3908 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
3909 && out_mode == SFmode && out_n == 4
3910 && in_mode == SFmode && in_n == 4)
3911 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
3913 case BUILT_IN_TRUNC:
3914 if (VECTOR_UNIT_VSX_P (V2DFmode)
3915 && out_mode == DFmode && out_n == 2
3916 && in_mode == DFmode && in_n == 2)
3917 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
3919 case BUILT_IN_TRUNCF:
3920 if (out_mode != SFmode || out_n != 4
3921 || in_mode != SFmode || in_n != 4)
3923 if (VECTOR_UNIT_VSX_P (V4SFmode))
3924 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
3925 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3926 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
3928 case BUILT_IN_NEARBYINT:
3929 if (VECTOR_UNIT_VSX_P (V2DFmode)
3930 && flag_unsafe_math_optimizations
3931 && out_mode == DFmode && out_n == 2
3932 && in_mode == DFmode && in_n == 2)
3933 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
3935 case BUILT_IN_NEARBYINTF:
3936 if (VECTOR_UNIT_VSX_P (V4SFmode)
3937 && flag_unsafe_math_optimizations
3938 && out_mode == SFmode && out_n == 4
3939 && in_mode == SFmode && in_n == 4)
3940 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
3943 if (VECTOR_UNIT_VSX_P (V2DFmode)
3944 && !flag_trapping_math
3945 && out_mode == DFmode && out_n == 2
3946 && in_mode == DFmode && in_n == 2)
3947 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
3949 case BUILT_IN_RINTF:
3950 if (VECTOR_UNIT_VSX_P (V4SFmode)
3951 && !flag_trapping_math
3952 && out_mode == SFmode && out_n == 4
3953 && in_mode == SFmode && in_n == 4)
3954 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
3961 else if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD)
3963 enum rs6000_builtins fn
3964 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
3967 case RS6000_BUILTIN_RSQRTF:
3968 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
3969 && out_mode == SFmode && out_n == 4
3970 && in_mode == SFmode && in_n == 4)
3971 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
3973 case RS6000_BUILTIN_RSQRT:
3974 if (VECTOR_UNIT_VSX_P (V2DFmode)
3975 && out_mode == DFmode && out_n == 2
3976 && in_mode == DFmode && in_n == 2)
3977 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
3979 case RS6000_BUILTIN_RECIPF:
3980 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
3981 && out_mode == SFmode && out_n == 4
3982 && in_mode == SFmode && in_n == 4)
3983 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
3985 case RS6000_BUILTIN_RECIP:
3986 if (VECTOR_UNIT_VSX_P (V2DFmode)
3987 && out_mode == DFmode && out_n == 2
3988 && in_mode == DFmode && in_n == 2)
3989 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
3996 /* Generate calls to libmass if appropriate. */
3997 if (rs6000_veclib_handler)
3998 return rs6000_veclib_handler (fndecl, type_out, type_in);
4003 /* Default CPU string for rs6000*_file_start functions. */
4004 static const char *rs6000_default_cpu;
4006 /* Do anything needed at the start of the asm file. */
4009 rs6000_file_start (void)
4012 const char *start = buffer;
4013 FILE *file = asm_out_file;
4015 rs6000_default_cpu = TARGET_CPU_DEFAULT;
4017 default_file_start ();
4019 #ifdef TARGET_BI_ARCH
4020 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
4021 rs6000_default_cpu = 0;
4024 if (flag_verbose_asm)
4026 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
4028 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
4030 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
4034 if (global_options_set.x_rs6000_cpu_index)
4036 fprintf (file, "%s -mcpu=%s", start,
4037 processor_target_table[rs6000_cpu_index].name);
4041 if (global_options_set.x_rs6000_tune_index)
4043 fprintf (file, "%s -mtune=%s", start,
4044 processor_target_table[rs6000_tune_index].name);
4048 if (PPC405_ERRATUM77)
4050 fprintf (file, "%s PPC405CR_ERRATUM77", start);
4054 #ifdef USING_ELFOS_H
4055 switch (rs6000_sdata)
4057 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
4058 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
4059 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
4060 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
4063 if (rs6000_sdata && g_switch_value)
4065 fprintf (file, "%s -G %d", start,
4075 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
4077 switch_to_section (toc_section);
4078 switch_to_section (text_section);
4083 /* Return nonzero if this function is known to have a null epilogue. */
4086 direct_return (void)
4088 if (reload_completed)
4090 rs6000_stack_t *info = rs6000_stack_info ();
4092 if (info->first_gp_reg_save == 32
4093 && info->first_fp_reg_save == 64
4094 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
4095 && ! info->lr_save_p
4096 && ! info->cr_save_p
4097 && info->vrsave_mask == 0
4105 /* Return the number of instructions it takes to form a constant in an
4106 integer register. */
4109 num_insns_constant_wide (HOST_WIDE_INT value)
4111 /* signed constant loadable with {cal|addi} */
4112 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
4115 /* constant loadable with {cau|addis} */
4116 else if ((value & 0xffff) == 0
4117 && (value >> 31 == -1 || value >> 31 == 0))
4120 #if HOST_BITS_PER_WIDE_INT == 64
4121 else if (TARGET_POWERPC64)
4123 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
4124 HOST_WIDE_INT high = value >> 31;
4126 if (high == 0 || high == -1)
4132 return num_insns_constant_wide (high) + 1;
4134 return num_insns_constant_wide (low) + 1;
4136 return (num_insns_constant_wide (high)
4137 + num_insns_constant_wide (low) + 1);
4146 num_insns_constant (rtx op, enum machine_mode mode)
4148 HOST_WIDE_INT low, high;
4150 switch (GET_CODE (op))
4153 #if HOST_BITS_PER_WIDE_INT == 64
4154 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
4155 && mask64_operand (op, mode))
4159 return num_insns_constant_wide (INTVAL (op));
4162 if (mode == SFmode || mode == SDmode)
4167 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
4168 if (DECIMAL_FLOAT_MODE_P (mode))
4169 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
4171 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4172 return num_insns_constant_wide ((HOST_WIDE_INT) l);
4175 if (mode == VOIDmode || mode == DImode)
4177 high = CONST_DOUBLE_HIGH (op);
4178 low = CONST_DOUBLE_LOW (op);
4185 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
4186 if (DECIMAL_FLOAT_MODE_P (mode))
4187 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
4189 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
4190 high = l[WORDS_BIG_ENDIAN == 0];
4191 low = l[WORDS_BIG_ENDIAN != 0];
4195 return (num_insns_constant_wide (low)
4196 + num_insns_constant_wide (high));
4199 if ((high == 0 && low >= 0)
4200 || (high == -1 && low < 0))
4201 return num_insns_constant_wide (low);
4203 else if (mask64_operand (op, mode))
4207 return num_insns_constant_wide (high) + 1;
4210 return (num_insns_constant_wide (high)
4211 + num_insns_constant_wide (low) + 1);
4219 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
4220 If the mode of OP is MODE_VECTOR_INT, this simply returns the
4221 corresponding element of the vector, but for V4SFmode and V2SFmode,
4222 the corresponding "float" is interpreted as an SImode integer. */
4225 const_vector_elt_as_int (rtx op, unsigned int elt)
4229 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
4230 gcc_assert (GET_MODE (op) != V2DImode
4231 && GET_MODE (op) != V2DFmode);
4233 tmp = CONST_VECTOR_ELT (op, elt);
4234 if (GET_MODE (op) == V4SFmode
4235 || GET_MODE (op) == V2SFmode)
4236 tmp = gen_lowpart (SImode, tmp);
4237 return INTVAL (tmp);
4240 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
4241 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
4242 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
4243 all items are set to the same value and contain COPIES replicas of the
4244 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
4245 operand and the others are set to the value of the operand's msb. */
4248 vspltis_constant (rtx op, unsigned step, unsigned copies)
4250 enum machine_mode mode = GET_MODE (op);
4251 enum machine_mode inner = GET_MODE_INNER (mode);
4259 HOST_WIDE_INT splat_val;
4260 HOST_WIDE_INT msb_val;
4262 if (mode == V2DImode || mode == V2DFmode)
4265 nunits = GET_MODE_NUNITS (mode);
4266 bitsize = GET_MODE_BITSIZE (inner);
4267 mask = GET_MODE_MASK (inner);
4269 val = const_vector_elt_as_int (op, nunits - 1);
4271 msb_val = val > 0 ? 0 : -1;
4273 /* Construct the value to be splatted, if possible. If not, return 0. */
4274 for (i = 2; i <= copies; i *= 2)
4276 HOST_WIDE_INT small_val;
4278 small_val = splat_val >> bitsize;
4280 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
4282 splat_val = small_val;
4285 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
4286 if (EASY_VECTOR_15 (splat_val))
4289 /* Also check if we can splat, and then add the result to itself. Do so if
4290 the value is positive, of if the splat instruction is using OP's mode;
4291 for splat_val < 0, the splat and the add should use the same mode. */
4292 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
4293 && (splat_val >= 0 || (step == 1 && copies == 1)))
4296 /* Also check if are loading up the most significant bit which can be done by
4297 loading up -1 and shifting the value left by -1. */
4298 else if (EASY_VECTOR_MSB (splat_val, inner))
4304 /* Check if VAL is present in every STEP-th element, and the
4305 other elements are filled with its most significant bit. */
4306 for (i = 0; i < nunits - 1; ++i)
4308 HOST_WIDE_INT desired_val;
4309 if (((i + 1) & (step - 1)) == 0)
4312 desired_val = msb_val;
4314 if (desired_val != const_vector_elt_as_int (op, i))
4322 /* Return true if OP is of the given MODE and can be synthesized
4323 with a vspltisb, vspltish or vspltisw. */
4326 easy_altivec_constant (rtx op, enum machine_mode mode)
4328 unsigned step, copies;
4330 if (mode == VOIDmode)
4331 mode = GET_MODE (op);
4332 else if (mode != GET_MODE (op))
4335 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
4337 if (mode == V2DFmode)
4338 return zero_constant (op, mode);
4340 if (mode == V2DImode)
4342 /* In case the compiler is built 32-bit, CONST_DOUBLE constants are not
4344 if (GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT
4345 || GET_CODE (CONST_VECTOR_ELT (op, 1)) != CONST_INT)
4348 if (zero_constant (op, mode))
4351 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
4352 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
4358 /* Start with a vspltisw. */
4359 step = GET_MODE_NUNITS (mode) / 4;
4362 if (vspltis_constant (op, step, copies))
4365 /* Then try with a vspltish. */
4371 if (vspltis_constant (op, step, copies))
4374 /* And finally a vspltisb. */
4380 if (vspltis_constant (op, step, copies))
4386 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
4387 result is OP. Abort if it is not possible. */
4390 gen_easy_altivec_constant (rtx op)
4392 enum machine_mode mode = GET_MODE (op);
4393 int nunits = GET_MODE_NUNITS (mode);
4394 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
4395 unsigned step = nunits / 4;
4396 unsigned copies = 1;
4398 /* Start with a vspltisw. */
4399 if (vspltis_constant (op, step, copies))
4400 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
4402 /* Then try with a vspltish. */
4408 if (vspltis_constant (op, step, copies))
4409 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
4411 /* And finally a vspltisb. */
4417 if (vspltis_constant (op, step, copies))
4418 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
4424 output_vec_const_move (rtx *operands)
4427 enum machine_mode mode;
4432 mode = GET_MODE (dest);
4436 if (zero_constant (vec, mode))
4437 return "xxlxor %x0,%x0,%x0";
4439 if (mode == V2DImode
4440 && INTVAL (CONST_VECTOR_ELT (vec, 0)) == -1
4441 && INTVAL (CONST_VECTOR_ELT (vec, 1)) == -1)
4442 return "vspltisw %0,-1";
4448 if (zero_constant (vec, mode))
4449 return "vxor %0,%0,%0";
4451 splat_vec = gen_easy_altivec_constant (vec);
4452 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
4453 operands[1] = XEXP (splat_vec, 0);
4454 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
4457 switch (GET_MODE (splat_vec))
4460 return "vspltisw %0,%1";
4463 return "vspltish %0,%1";
4466 return "vspltisb %0,%1";
4473 gcc_assert (TARGET_SPE);
4475 /* Vector constant 0 is handled as a splitter of V2SI, and in the
4476 pattern of V1DI, V4HI, and V2SF.
4478 FIXME: We should probably return # and add post reload
4479 splitters for these, but this way is so easy ;-). */
4480 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
4481 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
4482 operands[1] = CONST_VECTOR_ELT (vec, 0);
4483 operands[2] = CONST_VECTOR_ELT (vec, 1);
4485 return "li %0,%1\n\tevmergelo %0,%0,%0";
4487 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
4490 /* Initialize TARGET of vector PAIRED to VALS. */
4493 paired_expand_vector_init (rtx target, rtx vals)
4495 enum machine_mode mode = GET_MODE (target);
4496 int n_elts = GET_MODE_NUNITS (mode);
4498 rtx x, new_rtx, tmp, constant_op, op1, op2;
4501 for (i = 0; i < n_elts; ++i)
4503 x = XVECEXP (vals, 0, i);
4504 if (!(CONST_INT_P (x)
4505 || GET_CODE (x) == CONST_DOUBLE
4506 || GET_CODE (x) == CONST_FIXED))
4511 /* Load from constant pool. */
4512 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
4518 /* The vector is initialized only with non-constants. */
4519 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
4520 XVECEXP (vals, 0, 1));
4522 emit_move_insn (target, new_rtx);
4526 /* One field is non-constant and the other one is a constant. Load the
4527 constant from the constant pool and use ps_merge instruction to
4528 construct the whole vector. */
4529 op1 = XVECEXP (vals, 0, 0);
4530 op2 = XVECEXP (vals, 0, 1);
4532 constant_op = (CONSTANT_P (op1)) ? op1 : op2;
4534 tmp = gen_reg_rtx (GET_MODE (constant_op));
4535 emit_move_insn (tmp, constant_op);
4537 if (CONSTANT_P (op1))
4538 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
4540 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
4542 emit_move_insn (target, new_rtx);
4546 paired_expand_vector_move (rtx operands[])
4548 rtx op0 = operands[0], op1 = operands[1];
4550 emit_move_insn (op0, op1);
4553 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
4554 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
4555 operands for the relation operation COND. This is a recursive
4559 paired_emit_vector_compare (enum rtx_code rcode,
4560 rtx dest, rtx op0, rtx op1,
4561 rtx cc_op0, rtx cc_op1)
4563 rtx tmp = gen_reg_rtx (V2SFmode);
4566 gcc_assert (TARGET_PAIRED_FLOAT);
4567 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
4573 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
4577 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
4578 emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
4582 paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
4585 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
4588 tmp1 = gen_reg_rtx (V2SFmode);
4589 max = gen_reg_rtx (V2SFmode);
4590 min = gen_reg_rtx (V2SFmode);
4591 gen_reg_rtx (V2SFmode);
4593 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
4594 emit_insn (gen_selv2sf4
4595 (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
4596 emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
4597 emit_insn (gen_selv2sf4
4598 (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
4599 emit_insn (gen_subv2sf3 (tmp1, min, max));
4600 emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
4603 paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
4606 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
4609 paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
4612 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
4615 paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
4624 /* Emit vector conditional expression.
4625 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
4626 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
4629 paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
4630 rtx cond, rtx cc_op0, rtx cc_op1)
4632 enum rtx_code rcode = GET_CODE (cond);
4634 if (!TARGET_PAIRED_FLOAT)
4637 paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
4642 /* Initialize vector TARGET to VALS. */
4645 rs6000_expand_vector_init (rtx target, rtx vals)
4647 enum machine_mode mode = GET_MODE (target);
4648 enum machine_mode inner_mode = GET_MODE_INNER (mode);
4649 int n_elts = GET_MODE_NUNITS (mode);
4650 int n_var = 0, one_var = -1;
4651 bool all_same = true, all_const_zero = true;
4655 for (i = 0; i < n_elts; ++i)
4657 x = XVECEXP (vals, 0, i);
4658 if (!(CONST_INT_P (x)
4659 || GET_CODE (x) == CONST_DOUBLE
4660 || GET_CODE (x) == CONST_FIXED))
4661 ++n_var, one_var = i;
4662 else if (x != CONST0_RTX (inner_mode))
4663 all_const_zero = false;
4665 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
4671 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
4672 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
4673 if ((int_vector_p || TARGET_VSX) && all_const_zero)
4675 /* Zero register. */
4676 emit_insn (gen_rtx_SET (VOIDmode, target,
4677 gen_rtx_XOR (mode, target, target)));
4680 else if (int_vector_p && easy_vector_constant (const_vec, mode))
4682 /* Splat immediate. */
4683 emit_insn (gen_rtx_SET (VOIDmode, target, const_vec));
4688 /* Load from constant pool. */
4689 emit_move_insn (target, const_vec);
4694 /* Double word values on VSX can use xxpermdi or lxvdsx. */
4695 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
4699 rtx element = XVECEXP (vals, 0, 0);
4700 if (mode == V2DFmode)
4701 emit_insn (gen_vsx_splat_v2df (target, element));
4703 emit_insn (gen_vsx_splat_v2di (target, element));
4707 if (mode == V2DFmode)
4709 rtx op0 = copy_to_mode_reg (DFmode, XVECEXP (vals, 0, 0));
4710 rtx op1 = copy_to_mode_reg (DFmode, XVECEXP (vals, 0, 1));
4711 emit_insn (gen_vsx_concat_v2df (target, op0, op1));
4715 rtx op0 = copy_to_mode_reg (DImode, XVECEXP (vals, 0, 0));
4716 rtx op1 = copy_to_mode_reg (DImode, XVECEXP (vals, 0, 1));
4717 emit_insn (gen_vsx_concat_v2di (target, op0, op1));
4723 /* With single precision floating point on VSX, know that internally single
4724 precision is actually represented as a double, and either make 2 V2DF
4725 vectors, and convert these vectors to single precision, or do one
4726 conversion, and splat the result to the other elements. */
4727 if (mode == V4SFmode && VECTOR_MEM_VSX_P (mode))
4731 rtx freg = gen_reg_rtx (V4SFmode);
4732 rtx sreg = copy_to_reg (XVECEXP (vals, 0, 0));
4734 emit_insn (gen_vsx_xscvdpsp_scalar (freg, sreg));
4735 emit_insn (gen_vsx_xxspltw_v4sf (target, freg, const0_rtx));
4739 rtx dbl_even = gen_reg_rtx (V2DFmode);
4740 rtx dbl_odd = gen_reg_rtx (V2DFmode);
4741 rtx flt_even = gen_reg_rtx (V4SFmode);
4742 rtx flt_odd = gen_reg_rtx (V4SFmode);
4744 emit_insn (gen_vsx_concat_v2sf (dbl_even,
4745 copy_to_reg (XVECEXP (vals, 0, 0)),
4746 copy_to_reg (XVECEXP (vals, 0, 1))));
4747 emit_insn (gen_vsx_concat_v2sf (dbl_odd,
4748 copy_to_reg (XVECEXP (vals, 0, 2)),
4749 copy_to_reg (XVECEXP (vals, 0, 3))));
4750 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
4751 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
4752 rs6000_expand_extract_even (target, flt_even, flt_odd);
4757 /* Store value to stack temp. Load vector element. Splat. However, splat
4758 of 64-bit items is not supported on Altivec. */
4759 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
4761 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
4762 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
4763 XVECEXP (vals, 0, 0));
4764 x = gen_rtx_UNSPEC (VOIDmode,
4765 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
4766 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4768 gen_rtx_SET (VOIDmode,
4771 x = gen_rtx_VEC_SELECT (inner_mode, target,
4772 gen_rtx_PARALLEL (VOIDmode,
4773 gen_rtvec (1, const0_rtx)));
4774 emit_insn (gen_rtx_SET (VOIDmode, target,
4775 gen_rtx_VEC_DUPLICATE (mode, x)));
4779 /* One field is non-constant. Load constant then overwrite
4783 rtx copy = copy_rtx (vals);
4785 /* Load constant part of vector, substitute neighboring value for
4787 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
4788 rs6000_expand_vector_init (target, copy);
4790 /* Insert variable. */
4791 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
4795 /* Construct the vector in memory one field at a time
4796 and load the whole vector. */
4797 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
4798 for (i = 0; i < n_elts; i++)
4799 emit_move_insn (adjust_address_nv (mem, inner_mode,
4800 i * GET_MODE_SIZE (inner_mode)),
4801 XVECEXP (vals, 0, i));
4802 emit_move_insn (target, mem);
4805 /* Set field ELT of TARGET to VAL. */
4808 rs6000_expand_vector_set (rtx target, rtx val, int elt)
4810 enum machine_mode mode = GET_MODE (target);
4811 enum machine_mode inner_mode = GET_MODE_INNER (mode);
4812 rtx reg = gen_reg_rtx (mode);
4814 int width = GET_MODE_SIZE (inner_mode);
4817 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
4819 rtx (*set_func) (rtx, rtx, rtx, rtx)
4820 = ((mode == V2DFmode) ? gen_vsx_set_v2df : gen_vsx_set_v2di);
4821 emit_insn (set_func (target, target, val, GEN_INT (elt)));
4825 /* Load single variable value. */
4826 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
4827 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
4828 x = gen_rtx_UNSPEC (VOIDmode,
4829 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
4830 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4832 gen_rtx_SET (VOIDmode,
4836 /* Linear sequence. */
4837 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
4838 for (i = 0; i < 16; ++i)
4839 XVECEXP (mask, 0, i) = GEN_INT (i);
4841 /* Set permute mask to insert element into target. */
4842 for (i = 0; i < width; ++i)
4843 XVECEXP (mask, 0, elt*width + i)
4844 = GEN_INT (i + 0x10);
4845 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
4846 x = gen_rtx_UNSPEC (mode,
4847 gen_rtvec (3, target, reg,
4848 force_reg (V16QImode, x)),
4850 emit_insn (gen_rtx_SET (VOIDmode, target, x));
4853 /* Extract field ELT from VEC into TARGET. */
4856 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
4858 enum machine_mode mode = GET_MODE (vec);
4859 enum machine_mode inner_mode = GET_MODE_INNER (mode);
4862 if (VECTOR_MEM_VSX_P (mode))
4869 emit_insn (gen_vsx_extract_v2df (target, vec, GEN_INT (elt)));
4872 emit_insn (gen_vsx_extract_v2di (target, vec, GEN_INT (elt)));
4875 emit_insn (gen_vsx_extract_v4sf (target, vec, GEN_INT (elt)));
4880 /* Allocate mode-sized buffer. */
4881 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
4883 emit_move_insn (mem, vec);
4885 /* Add offset to field within buffer matching vector element. */
4886 mem = adjust_address_nv (mem, inner_mode, elt * GET_MODE_SIZE (inner_mode));
4888 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
4891 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
4892 implement ANDing by the mask IN. */
4894 build_mask64_2_operands (rtx in, rtx *out)
4896 #if HOST_BITS_PER_WIDE_INT >= 64
4897 unsigned HOST_WIDE_INT c, lsb, m1, m2;
4900 gcc_assert (GET_CODE (in) == CONST_INT);
4905 /* Assume c initially something like 0x00fff000000fffff. The idea
4906 is to rotate the word so that the middle ^^^^^^ group of zeros
4907 is at the MS end and can be cleared with an rldicl mask. We then
4908 rotate back and clear off the MS ^^ group of zeros with a
4910 c = ~c; /* c == 0xff000ffffff00000 */
4911 lsb = c & -c; /* lsb == 0x0000000000100000 */
4912 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
4913 c = ~c; /* c == 0x00fff000000fffff */
4914 c &= -lsb; /* c == 0x00fff00000000000 */
4915 lsb = c & -c; /* lsb == 0x0000100000000000 */
4916 c = ~c; /* c == 0xff000fffffffffff */
4917 c &= -lsb; /* c == 0xff00000000000000 */
4919 while ((lsb >>= 1) != 0)
4920 shift++; /* shift == 44 on exit from loop */
4921 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
4922 m1 = ~m1; /* m1 == 0x000000ffffffffff */
4923 m2 = ~c; /* m2 == 0x00ffffffffffffff */
4927 /* Assume c initially something like 0xff000f0000000000. The idea
4928 is to rotate the word so that the ^^^ middle group of zeros
4929 is at the LS end and can be cleared with an rldicr mask. We then
4930 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
4932 lsb = c & -c; /* lsb == 0x0000010000000000 */
4933 m2 = -lsb; /* m2 == 0xffffff0000000000 */
4934 c = ~c; /* c == 0x00fff0ffffffffff */
4935 c &= -lsb; /* c == 0x00fff00000000000 */
4936 lsb = c & -c; /* lsb == 0x0000100000000000 */
4937 c = ~c; /* c == 0xff000fffffffffff */
4938 c &= -lsb; /* c == 0xff00000000000000 */
4940 while ((lsb >>= 1) != 0)
4941 shift++; /* shift == 44 on exit from loop */
4942 m1 = ~c; /* m1 == 0x00ffffffffffffff */
4943 m1 >>= shift; /* m1 == 0x0000000000000fff */
4944 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
4947 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
4948 masks will be all 1's. We are guaranteed more than one transition. */
4949 out[0] = GEN_INT (64 - shift);
4950 out[1] = GEN_INT (m1);
4951 out[2] = GEN_INT (shift);
4952 out[3] = GEN_INT (m2);
4960 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
4963 invalid_e500_subreg (rtx op, enum machine_mode mode)
4965 if (TARGET_E500_DOUBLE)
4967 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
4968 subreg:TI and reg:TF. Decimal float modes are like integer
4969 modes (only low part of each register used) for this
4971 if (GET_CODE (op) == SUBREG
4972 && (mode == SImode || mode == DImode || mode == TImode
4973 || mode == DDmode || mode == TDmode)
4974 && REG_P (SUBREG_REG (op))
4975 && (GET_MODE (SUBREG_REG (op)) == DFmode
4976 || GET_MODE (SUBREG_REG (op)) == TFmode))
4979 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
4981 if (GET_CODE (op) == SUBREG
4982 && (mode == DFmode || mode == TFmode)
4983 && REG_P (SUBREG_REG (op))
4984 && (GET_MODE (SUBREG_REG (op)) == DImode
4985 || GET_MODE (SUBREG_REG (op)) == TImode
4986 || GET_MODE (SUBREG_REG (op)) == DDmode
4987 || GET_MODE (SUBREG_REG (op)) == TDmode))
4992 && GET_CODE (op) == SUBREG
4994 && REG_P (SUBREG_REG (op))
4995 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
5001 /* AIX increases natural record alignment to doubleword if the first
5002 field is an FP double while the FP fields remain word aligned. */
5005 rs6000_special_round_type_align (tree type, unsigned int computed,
5006 unsigned int specified)
5008 unsigned int align = MAX (computed, specified);
5009 tree field = TYPE_FIELDS (type);
5011 /* Skip all non field decls */
5012 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
5013 field = DECL_CHAIN (field);
5015 if (field != NULL && field != type)
5017 type = TREE_TYPE (field);
5018 while (TREE_CODE (type) == ARRAY_TYPE)
5019 type = TREE_TYPE (type);
5021 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
5022 align = MAX (align, 64);
5028 /* Darwin increases record alignment to the natural alignment of
5032 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
5033 unsigned int specified)
5035 unsigned int align = MAX (computed, specified);
5037 if (TYPE_PACKED (type))
5040 /* Find the first field, looking down into aggregates. */
5042 tree field = TYPE_FIELDS (type);
5043 /* Skip all non field decls */
5044 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
5045 field = DECL_CHAIN (field);
5048 /* A packed field does not contribute any extra alignment. */
5049 if (DECL_PACKED (field))
5051 type = TREE_TYPE (field);
5052 while (TREE_CODE (type) == ARRAY_TYPE)
5053 type = TREE_TYPE (type);
5054 } while (AGGREGATE_TYPE_P (type));
5056 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
5057 align = MAX (align, TYPE_ALIGN (type));
5062 /* Return 1 for an operand in small memory on V.4/eabi. */
5065 small_data_operand (rtx op ATTRIBUTE_UNUSED,
5066 enum machine_mode mode ATTRIBUTE_UNUSED)
5071 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
5074 if (DEFAULT_ABI != ABI_V4)
5077 /* Vector and float memory instructions have a limited offset on the
5078 SPE, so using a vector or float variable directly as an operand is
5081 && (SPE_VECTOR_MODE (mode) || FLOAT_MODE_P (mode)))
5084 if (GET_CODE (op) == SYMBOL_REF)
5087 else if (GET_CODE (op) != CONST
5088 || GET_CODE (XEXP (op, 0)) != PLUS
5089 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
5090 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
5095 rtx sum = XEXP (op, 0);
5096 HOST_WIDE_INT summand;
5098 /* We have to be careful here, because it is the referenced address
5099 that must be 32k from _SDA_BASE_, not just the symbol. */
5100 summand = INTVAL (XEXP (sum, 1));
5101 if (summand < 0 || summand > g_switch_value)
5104 sym_ref = XEXP (sum, 0);
5107 return SYMBOL_REF_SMALL_P (sym_ref);
5113 /* Return true if either operand is a general purpose register. */
5116 gpr_or_gpr_p (rtx op0, rtx op1)
5118 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
5119 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
5123 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
5126 reg_offset_addressing_ok_p (enum machine_mode mode)
5136 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. */
5137 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
5145 /* Paired vector modes. Only reg+reg addressing is valid. */
5146 if (TARGET_PAIRED_FLOAT)
5158 virtual_stack_registers_memory_p (rtx op)
5162 if (GET_CODE (op) == REG)
5163 regnum = REGNO (op);
5165 else if (GET_CODE (op) == PLUS
5166 && GET_CODE (XEXP (op, 0)) == REG
5167 && GET_CODE (XEXP (op, 1)) == CONST_INT)
5168 regnum = REGNO (XEXP (op, 0));
5173 return (regnum >= FIRST_VIRTUAL_REGISTER
5174 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
5177 /* Return true if memory accesses to OP are known to never straddle
5181 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
5182 enum machine_mode mode)
5185 unsigned HOST_WIDE_INT dsize, dalign;
5187 if (GET_CODE (op) != SYMBOL_REF)
5190 decl = SYMBOL_REF_DECL (op);
5193 if (GET_MODE_SIZE (mode) == 0)
5196 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
5197 replacing memory addresses with an anchor plus offset. We
5198 could find the decl by rummaging around in the block->objects
5199 VEC for the given offset but that seems like too much work. */
5201 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
5202 && SYMBOL_REF_ANCHOR_P (op)
5203 && SYMBOL_REF_BLOCK (op) != NULL)
5205 struct object_block *block = SYMBOL_REF_BLOCK (op);
5206 HOST_WIDE_INT lsb, mask;
5208 /* Given the alignment of the block.. */
5209 dalign = block->alignment;
5210 mask = dalign / BITS_PER_UNIT - 1;
5212 /* ..and the combined offset of the anchor and any offset
5213 to this block object.. */
5214 offset += SYMBOL_REF_BLOCK_OFFSET (op);
5215 lsb = offset & -offset;
5217 /* ..find how many bits of the alignment we know for the
5222 return dalign >= GET_MODE_SIZE (mode);
5227 if (TREE_CODE (decl) == FUNCTION_DECL)
5230 if (!DECL_SIZE_UNIT (decl))
5233 if (!host_integerp (DECL_SIZE_UNIT (decl), 1))
5236 dsize = tree_low_cst (DECL_SIZE_UNIT (decl), 1);
5240 dalign = DECL_ALIGN_UNIT (decl);
5241 return dalign >= dsize;
5244 type = TREE_TYPE (decl);
5246 if (TREE_CODE (decl) == STRING_CST)
5247 dsize = TREE_STRING_LENGTH (decl);
5248 else if (TYPE_SIZE_UNIT (type)
5249 && host_integerp (TYPE_SIZE_UNIT (type), 1))
5250 dsize = tree_low_cst (TYPE_SIZE_UNIT (type), 1);
5256 dalign = TYPE_ALIGN (type);
5257 if (CONSTANT_CLASS_P (decl))
5258 dalign = CONSTANT_ALIGNMENT (decl, dalign);
5260 dalign = DATA_ALIGNMENT (decl, dalign);
5261 dalign /= BITS_PER_UNIT;
5262 return dalign >= dsize;
5266 constant_pool_expr_p (rtx op)
5270 split_const (op, &base, &offset);
5271 return (GET_CODE (base) == SYMBOL_REF
5272 && CONSTANT_POOL_ADDRESS_P (base)
5273 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
5276 static rtx tocrel_base, tocrel_offset;
5279 toc_relative_expr_p (rtx op)
5281 if (GET_CODE (op) != CONST)
5284 split_const (op, &tocrel_base, &tocrel_offset);
5285 return (GET_CODE (tocrel_base) == UNSPEC
5286 && XINT (tocrel_base, 1) == UNSPEC_TOCREL);
5289 /* Return true if X is a constant pool address, and also for cmodel=medium
5290 if X is a toc-relative address known to be offsettable within MODE. */
5293 legitimate_constant_pool_address_p (const_rtx x, enum machine_mode mode,
5297 && (GET_CODE (x) == PLUS || GET_CODE (x) == LO_SUM)
5298 && GET_CODE (XEXP (x, 0)) == REG
5299 && (REGNO (XEXP (x, 0)) == TOC_REGISTER
5300 || ((TARGET_MINIMAL_TOC
5301 || TARGET_CMODEL != CMODEL_SMALL)
5302 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)))
5303 && toc_relative_expr_p (XEXP (x, 1))
5304 && (TARGET_CMODEL != CMODEL_MEDIUM
5305 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
5307 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
5308 INTVAL (tocrel_offset), mode)));
5312 legitimate_small_data_p (enum machine_mode mode, rtx x)
5314 return (DEFAULT_ABI == ABI_V4
5315 && !flag_pic && !TARGET_TOC
5316 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
5317 && small_data_operand (x, mode));
5320 /* SPE offset addressing is limited to 5-bits worth of double words. */
5321 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
5324 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
5326 unsigned HOST_WIDE_INT offset, extra;
5328 if (GET_CODE (x) != PLUS)
5330 if (GET_CODE (XEXP (x, 0)) != REG)
5332 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
5334 if (!reg_offset_addressing_ok_p (mode))
5335 return virtual_stack_registers_memory_p (x);
5336 if (legitimate_constant_pool_address_p (x, mode, strict))
5338 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5341 offset = INTVAL (XEXP (x, 1));
5349 /* SPE vector modes. */
5350 return SPE_CONST_OFFSET_OK (offset);
5353 if (TARGET_E500_DOUBLE)
5354 return SPE_CONST_OFFSET_OK (offset);
5356 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
5358 if (VECTOR_MEM_VSX_P (DFmode))
5363 /* On e500v2, we may have:
5365 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
5367 Which gets addressed with evldd instructions. */
5368 if (TARGET_E500_DOUBLE)
5369 return SPE_CONST_OFFSET_OK (offset);
5371 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
5373 else if (offset & 3)
5378 if (TARGET_E500_DOUBLE)
5379 return (SPE_CONST_OFFSET_OK (offset)
5380 && SPE_CONST_OFFSET_OK (offset + 8));
5384 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
5386 else if (offset & 3)
5397 return offset < 0x10000 - extra;
5401 legitimate_indexed_address_p (rtx x, int strict)
5405 if (GET_CODE (x) != PLUS)
5411 /* Recognize the rtl generated by reload which we know will later be
5412 replaced with proper base and index regs. */
5414 && reload_in_progress
5415 && (REG_P (op0) || GET_CODE (op0) == PLUS)
5419 return (REG_P (op0) && REG_P (op1)
5420 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
5421 && INT_REG_OK_FOR_INDEX_P (op1, strict))
5422 || (INT_REG_OK_FOR_BASE_P (op1, strict)
5423 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
5427 avoiding_indexed_address_p (enum machine_mode mode)
5429 /* Avoid indexed addressing for modes that have non-indexed
5430 load/store instruction forms. */
5431 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
5435 legitimate_indirect_address_p (rtx x, int strict)
5437 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
5441 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
5443 if (!TARGET_MACHO || !flag_pic
5444 || mode != SImode || GET_CODE (x) != MEM)
5448 if (GET_CODE (x) != LO_SUM)
5450 if (GET_CODE (XEXP (x, 0)) != REG)
5452 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
5456 return CONSTANT_P (x);
5460 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
5462 if (GET_CODE (x) != LO_SUM)
5464 if (GET_CODE (XEXP (x, 0)) != REG)
5466 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
5468 /* Restrict addressing for DI because of our SUBREG hackery. */
5469 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5470 || mode == DDmode || mode == TDmode
5475 if (TARGET_ELF || TARGET_MACHO)
5477 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
5481 if (GET_MODE_NUNITS (mode) != 1)
5483 if (GET_MODE_BITSIZE (mode) > 64
5484 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
5485 && !(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5486 && (mode == DFmode || mode == DDmode))))
5489 return CONSTANT_P (x);
5496 /* Try machine-dependent ways of modifying an illegitimate address
5497 to be legitimate. If we find one, return the new, valid address.
5498 This is used from only one place: `memory_address' in explow.c.
5500 OLDX is the address as it was before break_out_memory_refs was
5501 called. In some cases it is useful to look at this to decide what
5504 It is always safe for this function to do nothing. It exists to
5505 recognize opportunities to optimize the output.
5507 On RS/6000, first check for the sum of a register with a constant
5508 integer that is out of range. If so, generate code to add the
5509 constant with the low-order 16 bits masked to the register and force
5510 this result into another register (this can be done with `cau').
5511 Then generate an address of REG+(CONST&0xffff), allowing for the
5512 possibility of bit 16 being a one.
5514 Then check for the sum of a register and something not constant, try to
5515 load the other things into a register and return the sum. */
5518 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
5519 enum machine_mode mode)
5521 unsigned int extra = 0;
5523 if (!reg_offset_addressing_ok_p (mode))
5525 if (virtual_stack_registers_memory_p (x))
5528 /* In theory we should not be seeing addresses of the form reg+0,
5529 but just in case it is generated, optimize it away. */
5530 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
5531 return force_reg (Pmode, XEXP (x, 0));
5533 /* Make sure both operands are registers. */
5534 else if (GET_CODE (x) == PLUS)
5535 return gen_rtx_PLUS (Pmode,
5536 force_reg (Pmode, XEXP (x, 0)),
5537 force_reg (Pmode, XEXP (x, 1)));
5539 return force_reg (Pmode, x);
5541 if (GET_CODE (x) == SYMBOL_REF)
5543 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
5545 return rs6000_legitimize_tls_address (x, model);
5555 if (!TARGET_POWERPC64)
5563 extra = TARGET_POWERPC64 ? 8 : 12;
5569 if (GET_CODE (x) == PLUS
5570 && GET_CODE (XEXP (x, 0)) == REG
5571 && GET_CODE (XEXP (x, 1)) == CONST_INT
5572 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
5574 && !((TARGET_POWERPC64
5575 && (mode == DImode || mode == TImode)
5576 && (INTVAL (XEXP (x, 1)) & 3) != 0)
5577 || SPE_VECTOR_MODE (mode)
5578 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5579 || mode == DImode || mode == DDmode
5580 || mode == TDmode))))
5582 HOST_WIDE_INT high_int, low_int;
5584 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
5585 if (low_int >= 0x8000 - extra)
5587 high_int = INTVAL (XEXP (x, 1)) - low_int;
5588 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
5589 GEN_INT (high_int)), 0);
5590 return plus_constant (sum, low_int);
5592 else if (GET_CODE (x) == PLUS
5593 && GET_CODE (XEXP (x, 0)) == REG
5594 && GET_CODE (XEXP (x, 1)) != CONST_INT
5595 && GET_MODE_NUNITS (mode) == 1
5596 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5598 || ((mode != DImode && mode != DFmode && mode != DDmode)
5599 || (TARGET_E500_DOUBLE && mode != DDmode)))
5600 && (TARGET_POWERPC64 || mode != DImode)
5601 && !avoiding_indexed_address_p (mode)
5606 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
5607 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
5609 else if (SPE_VECTOR_MODE (mode)
5610 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5611 || mode == DDmode || mode == TDmode
5612 || mode == DImode)))
5616 /* We accept [reg + reg] and [reg + OFFSET]. */
5618 if (GET_CODE (x) == PLUS)
5620 rtx op1 = XEXP (x, 0);
5621 rtx op2 = XEXP (x, 1);
5624 op1 = force_reg (Pmode, op1);
5626 if (GET_CODE (op2) != REG
5627 && (GET_CODE (op2) != CONST_INT
5628 || !SPE_CONST_OFFSET_OK (INTVAL (op2))
5629 || (GET_MODE_SIZE (mode) > 8
5630 && !SPE_CONST_OFFSET_OK (INTVAL (op2) + 8))))
5631 op2 = force_reg (Pmode, op2);
5633 /* We can't always do [reg + reg] for these, because [reg +
5634 reg + offset] is not a legitimate addressing mode. */
5635 y = gen_rtx_PLUS (Pmode, op1, op2);
5637 if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2))
5638 return force_reg (Pmode, y);
5643 return force_reg (Pmode, x);
5649 && GET_CODE (x) != CONST_INT
5650 && GET_CODE (x) != CONST_DOUBLE
5652 && GET_MODE_NUNITS (mode) == 1
5653 && (GET_MODE_BITSIZE (mode) <= 32
5654 || ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5655 && (mode == DFmode || mode == DDmode))))
5657 rtx reg = gen_reg_rtx (Pmode);
5658 emit_insn (gen_elf_high (reg, x));
5659 return gen_rtx_LO_SUM (Pmode, reg, x);
5661 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
5664 && ! MACHO_DYNAMIC_NO_PIC_P
5666 && GET_CODE (x) != CONST_INT
5667 && GET_CODE (x) != CONST_DOUBLE
5669 && GET_MODE_NUNITS (mode) == 1
5670 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5671 || (mode != DFmode && mode != DDmode))
5675 rtx reg = gen_reg_rtx (Pmode);
5676 emit_insn (gen_macho_high (reg, x));
5677 return gen_rtx_LO_SUM (Pmode, reg, x);
5680 && GET_CODE (x) == SYMBOL_REF
5681 && constant_pool_expr_p (x)
5682 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
5684 rtx reg = TARGET_CMODEL != CMODEL_SMALL ? gen_reg_rtx (Pmode) : NULL_RTX;
5685 return create_TOC_reference (x, reg);
5691 /* Debug version of rs6000_legitimize_address. */
5693 rs6000_debug_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
5699 ret = rs6000_legitimize_address (x, oldx, mode);
5700 insns = get_insns ();
5706 "\nrs6000_legitimize_address: mode %s, old code %s, "
5707 "new code %s, modified\n",
5708 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
5709 GET_RTX_NAME (GET_CODE (ret)));
5711 fprintf (stderr, "Original address:\n");
5714 fprintf (stderr, "oldx:\n");
5717 fprintf (stderr, "New address:\n");
5722 fprintf (stderr, "Insns added:\n");
5723 debug_rtx_list (insns, 20);
5729 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
5730 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
5741 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5742 We need to emit DTP-relative relocations. */
5745 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
5750 fputs ("\t.long\t", file);
5753 fputs (DOUBLE_INT_ASM_OP, file);
5758 output_addr_const (file, x);
5759 fputs ("@dtprel+0x8000", file);
5762 /* In the name of slightly smaller debug output, and to cater to
5763 general assembler lossage, recognize various UNSPEC sequences
5764 and turn them back into a direct symbol reference. */
5767 rs6000_delegitimize_address (rtx orig_x)
5771 orig_x = delegitimize_mem_from_attrs (orig_x);
5776 if (GET_CODE (x) == (TARGET_CMODEL != CMODEL_SMALL ? LO_SUM : PLUS)
5777 && GET_CODE (XEXP (x, 1)) == CONST)
5779 rtx offset = NULL_RTX;
5781 y = XEXP (XEXP (x, 1), 0);
5782 if (GET_CODE (y) == PLUS
5783 && GET_MODE (y) == Pmode
5784 && CONST_INT_P (XEXP (y, 1)))
5786 offset = XEXP (y, 1);
5789 if (GET_CODE (y) == UNSPEC
5790 && XINT (y, 1) == UNSPEC_TOCREL
5791 && ((GET_CODE (XEXP (x, 0)) == REG
5792 && (REGNO (XEXP (x, 0)) == TOC_REGISTER
5793 || TARGET_MINIMAL_TOC
5794 || TARGET_CMODEL != CMODEL_SMALL))
5795 || (TARGET_CMODEL != CMODEL_SMALL
5796 && GET_CODE (XEXP (x, 0)) == CONST
5797 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
5798 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == REG
5799 && REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0)) == TOC_REGISTER
5800 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == HIGH
5801 && rtx_equal_p (XEXP (x, 1),
5802 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 1), 0)))))
5804 y = XVECEXP (y, 0, 0);
5805 if (offset != NULL_RTX)
5806 y = gen_rtx_PLUS (Pmode, y, offset);
5807 if (!MEM_P (orig_x))
5810 return replace_equiv_address_nv (orig_x, y);
5815 && GET_CODE (orig_x) == LO_SUM
5816 && GET_CODE (XEXP (orig_x, 1)) == CONST)
5818 y = XEXP (XEXP (orig_x, 1), 0);
5819 if (GET_CODE (y) == UNSPEC
5820 && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
5821 return XVECEXP (y, 0, 0);
5827 /* Return true if X shouldn't be emitted into the debug info.
5828 The linker doesn't like .toc section references from
5829 .debug_* sections, so reject .toc section symbols. */
5832 rs6000_const_not_ok_for_debug_p (rtx x)
5834 if (GET_CODE (x) == SYMBOL_REF
5835 && CONSTANT_POOL_ADDRESS_P (x))
5837 rtx c = get_pool_constant (x);
5838 enum machine_mode cmode = get_pool_mode (x);
5839 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
5846 /* Construct the SYMBOL_REF for the tls_get_addr function. */
5848 static GTY(()) rtx rs6000_tls_symbol;
5850 rs6000_tls_get_addr (void)
5852 if (!rs6000_tls_symbol)
5853 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
5855 return rs6000_tls_symbol;
5858 /* Construct the SYMBOL_REF for TLS GOT references. */
5860 static GTY(()) rtx rs6000_got_symbol;
5862 rs6000_got_sym (void)
5864 if (!rs6000_got_symbol)
5866 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
5867 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
5868 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
5871 return rs6000_got_symbol;
5874 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
5875 this (thread-local) address. */
5878 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
5882 dest = gen_reg_rtx (Pmode);
5883 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
5889 tlsreg = gen_rtx_REG (Pmode, 13);
5890 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
5894 tlsreg = gen_rtx_REG (Pmode, 2);
5895 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
5899 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
5903 tmp = gen_reg_rtx (Pmode);
5906 tlsreg = gen_rtx_REG (Pmode, 13);
5907 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
5911 tlsreg = gen_rtx_REG (Pmode, 2);
5912 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
5916 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
5918 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
5923 rtx r3, got, tga, tmp1, tmp2, call_insn;
5925 /* We currently use relocations like @got@tlsgd for tls, which
5926 means the linker will handle allocation of tls entries, placing
5927 them in the .got section. So use a pointer to the .got section,
5928 not one to secondary TOC sections used by 64-bit -mminimal-toc,
5929 or to secondary GOT sections used by 32-bit -fPIC. */
5931 got = gen_rtx_REG (Pmode, 2);
5935 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
5938 rtx gsym = rs6000_got_sym ();
5939 got = gen_reg_rtx (Pmode);
5941 rs6000_emit_move (got, gsym, Pmode);
5946 tmp1 = gen_reg_rtx (Pmode);
5947 tmp2 = gen_reg_rtx (Pmode);
5948 mem = gen_const_mem (Pmode, tmp1);
5949 lab = gen_label_rtx ();
5950 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
5951 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
5952 if (TARGET_LINK_STACK)
5953 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
5954 emit_move_insn (tmp2, mem);
5955 last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
5956 set_unique_reg_note (last, REG_EQUAL, gsym);
5961 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
5963 tga = rs6000_tls_get_addr ();
5964 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
5965 1, const0_rtx, Pmode);
5967 r3 = gen_rtx_REG (Pmode, 3);
5968 if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5969 insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
5970 else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
5971 insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
5972 else if (DEFAULT_ABI == ABI_V4)
5973 insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
5976 call_insn = last_call_insn ();
5977 PATTERN (call_insn) = insn;
5978 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
5979 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
5980 pic_offset_table_rtx);
5982 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
5984 tga = rs6000_tls_get_addr ();
5985 tmp1 = gen_reg_rtx (Pmode);
5986 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
5987 1, const0_rtx, Pmode);
5989 r3 = gen_rtx_REG (Pmode, 3);
5990 if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5991 insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
5992 else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
5993 insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
5994 else if (DEFAULT_ABI == ABI_V4)
5995 insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
5998 call_insn = last_call_insn ();
5999 PATTERN (call_insn) = insn;
6000 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
6001 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
6002 pic_offset_table_rtx);
6004 if (rs6000_tls_size == 16)
6007 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
6009 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
6011 else if (rs6000_tls_size == 32)
6013 tmp2 = gen_reg_rtx (Pmode);
6015 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
6017 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
6020 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
6022 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
6026 tmp2 = gen_reg_rtx (Pmode);
6028 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
6030 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
6032 insn = gen_rtx_SET (Pmode, dest,
6033 gen_rtx_PLUS (Pmode, tmp2, tmp1));
6039 /* IE, or 64-bit offset LE. */
6040 tmp2 = gen_reg_rtx (Pmode);
6042 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
6044 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
6047 insn = gen_tls_tls_64 (dest, tmp2, addr);
6049 insn = gen_tls_tls_32 (dest, tmp2, addr);
6057 /* Return 1 if X contains a thread-local symbol. */
6060 rs6000_tls_referenced_p (rtx x)
6062 if (! TARGET_HAVE_TLS)
6065 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
6068 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
6071 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
6073 if (GET_CODE (x) == CONST
6074 && GET_CODE (XEXP (x, 0)) == PLUS
6075 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH)
6078 return rs6000_tls_referenced_p (x);
6081 /* Return 1 if *X is a thread-local symbol. This is the same as
6082 rs6000_tls_symbol_ref except for the type of the unused argument. */
6085 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
6087 return RS6000_SYMBOL_REF_TLS_P (*x);
6090 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
6091 replace the input X, or the original X if no replacement is called for.
6092 The output parameter *WIN is 1 if the calling macro should goto WIN,
6095 For RS/6000, we wish to handle large displacements off a base
6096 register by splitting the addend across an addiu/addis and the mem insn.
6097 This cuts number of extra insns needed from 3 to 1.
6099 On Darwin, we use this to generate code for floating point constants.
6100 A movsf_low is generated so we wind up with 2 instructions rather than 3.
6101 The Darwin code is inside #if TARGET_MACHO because only then are the
6102 machopic_* functions defined. */
6104 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
6105 int opnum, int type,
6106 int ind_levels ATTRIBUTE_UNUSED, int *win)
6108 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
6110 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
6111 DFmode/DImode MEM. */
6114 && ((mode == DFmode && recog_data.operand_mode[0] == V2DFmode)
6115 || (mode == DImode && recog_data.operand_mode[0] == V2DImode)))
6116 reg_offset_p = false;
6118 /* We must recognize output that we have already generated ourselves. */
6119 if (GET_CODE (x) == PLUS
6120 && GET_CODE (XEXP (x, 0)) == PLUS
6121 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
6122 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6123 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6125 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6126 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
6127 opnum, (enum reload_type)type);
6132 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
6133 if (GET_CODE (x) == LO_SUM
6134 && GET_CODE (XEXP (x, 0)) == HIGH)
6136 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6137 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6138 opnum, (enum reload_type)type);
6144 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
6145 && GET_CODE (x) == LO_SUM
6146 && GET_CODE (XEXP (x, 0)) == PLUS
6147 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
6148 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
6149 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
6150 && machopic_operand_p (XEXP (x, 1)))
6152 /* Result of previous invocation of this function on Darwin
6153 floating point constant. */
6154 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6155 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6156 opnum, (enum reload_type)type);
6162 if (TARGET_CMODEL != CMODEL_SMALL
6163 && GET_CODE (x) == LO_SUM
6164 && GET_CODE (XEXP (x, 0)) == PLUS
6165 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
6166 && REGNO (XEXP (XEXP (x, 0), 0)) == TOC_REGISTER
6167 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST
6168 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == HIGH
6169 && GET_CODE (XEXP (x, 1)) == CONST
6170 && GET_CODE (XEXP (XEXP (x, 1), 0)) == UNSPEC
6171 && XINT (XEXP (XEXP (x, 1), 0), 1) == UNSPEC_TOCREL
6172 && rtx_equal_p (XEXP (XEXP (XEXP (XEXP (x, 0), 1), 0), 0), XEXP (x, 1)))
6174 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6175 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6176 opnum, (enum reload_type) type);
6181 /* Force ld/std non-word aligned offset into base register by wrapping
6183 if (GET_CODE (x) == PLUS
6184 && GET_CODE (XEXP (x, 0)) == REG
6185 && REGNO (XEXP (x, 0)) < 32
6186 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
6187 && GET_CODE (XEXP (x, 1)) == CONST_INT
6189 && (INTVAL (XEXP (x, 1)) & 3) != 0
6190 && VECTOR_MEM_NONE_P (mode)
6191 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
6192 && TARGET_POWERPC64)
6194 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
6195 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6196 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
6197 opnum, (enum reload_type) type);
6202 if (GET_CODE (x) == PLUS
6203 && GET_CODE (XEXP (x, 0)) == REG
6204 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
6205 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
6206 && GET_CODE (XEXP (x, 1)) == CONST_INT
6208 && !SPE_VECTOR_MODE (mode)
6209 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
6210 || mode == DDmode || mode == TDmode
6212 && VECTOR_MEM_NONE_P (mode))
6214 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
6215 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
6217 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
6219 /* Check for 32-bit overflow. */
6220 if (high + low != val)
6226 /* Reload the high part into a base reg; leave the low part
6227 in the mem directly. */
6229 x = gen_rtx_PLUS (GET_MODE (x),
6230 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
6234 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6235 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
6236 opnum, (enum reload_type)type);
6241 if (GET_CODE (x) == SYMBOL_REF
6243 && VECTOR_MEM_NONE_P (mode)
6244 && !SPE_VECTOR_MODE (mode)
6246 && DEFAULT_ABI == ABI_DARWIN
6247 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
6248 && machopic_symbol_defined_p (x)
6250 && DEFAULT_ABI == ABI_V4
6253 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
6254 The same goes for DImode without 64-bit gprs and DFmode and DDmode
6258 && (mode != DImode || TARGET_POWERPC64)
6259 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
6260 || (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)))
6265 rtx offset = machopic_gen_offset (x);
6266 x = gen_rtx_LO_SUM (GET_MODE (x),
6267 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
6268 gen_rtx_HIGH (Pmode, offset)), offset);
6272 x = gen_rtx_LO_SUM (GET_MODE (x),
6273 gen_rtx_HIGH (Pmode, x), x);
6275 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6276 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6277 opnum, (enum reload_type)type);
6282 /* Reload an offset address wrapped by an AND that represents the
6283 masking of the lower bits. Strip the outer AND and let reload
6284 convert the offset address into an indirect address. For VSX,
6285 force reload to create the address with an AND in a separate
6286 register, because we can't guarantee an altivec register will
6288 if (VECTOR_MEM_ALTIVEC_P (mode)
6289 && GET_CODE (x) == AND
6290 && GET_CODE (XEXP (x, 0)) == PLUS
6291 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
6292 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6293 && GET_CODE (XEXP (x, 1)) == CONST_INT
6294 && INTVAL (XEXP (x, 1)) == -16)
6303 && GET_CODE (x) == SYMBOL_REF
6304 && constant_pool_expr_p (x)
6305 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
6307 x = create_TOC_reference (x, NULL_RTX);
6308 if (TARGET_CMODEL != CMODEL_SMALL)
6309 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6310 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6311 opnum, (enum reload_type) type);
6319 /* Debug version of rs6000_legitimize_reload_address. */
6321 rs6000_debug_legitimize_reload_address (rtx x, enum machine_mode mode,
6322 int opnum, int type,
6323 int ind_levels, int *win)
6325 rtx ret = rs6000_legitimize_reload_address (x, mode, opnum, type,
6328 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
6329 "type = %d, ind_levels = %d, win = %d, original addr:\n",
6330 GET_MODE_NAME (mode), opnum, type, ind_levels, *win);
6334 fprintf (stderr, "Same address returned\n");
6336 fprintf (stderr, "NULL returned\n");
6339 fprintf (stderr, "New address:\n");
6346 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
6347 that is a valid memory address for an instruction.
6348 The MODE argument is the machine mode for the MEM expression
6349 that wants to use this address.
6351 On the RS/6000, there are four valid address: a SYMBOL_REF that
6352 refers to a constant pool entry of an address (or the sum of it
6353 plus a constant), a short (16-bit signed) constant plus a register,
6354 the sum of two registers, or a register indirect, possibly with an
6355 auto-increment. For DFmode, DDmode and DImode with a constant plus
6356 register, we must ensure that both words are addressable or PowerPC64
6357 with offset word aligned.
6359 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
6360 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
6361 because adjacent memory cells are accessed by adding word-sized offsets
6362 during assembly output. */
6364 rs6000_legitimate_address_p (enum machine_mode mode, rtx x, bool reg_ok_strict)
6366 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
6368 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
6369 if (VECTOR_MEM_ALTIVEC_P (mode)
6370 && GET_CODE (x) == AND
6371 && GET_CODE (XEXP (x, 1)) == CONST_INT
6372 && INTVAL (XEXP (x, 1)) == -16)
6375 if (RS6000_SYMBOL_REF_TLS_P (x))
6377 if (legitimate_indirect_address_p (x, reg_ok_strict))
6379 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
6380 && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
6381 && !SPE_VECTOR_MODE (mode)
6384 /* Restrict addressing for DI because of our SUBREG hackery. */
6385 && !(TARGET_E500_DOUBLE
6386 && (mode == DFmode || mode == DDmode || mode == DImode))
6388 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
6390 if (virtual_stack_registers_memory_p (x))
6392 if (reg_offset_p && legitimate_small_data_p (mode, x))
6395 && legitimate_constant_pool_address_p (x, mode, reg_ok_strict))
6397 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
6400 && GET_CODE (x) == PLUS
6401 && GET_CODE (XEXP (x, 0)) == REG
6402 && (XEXP (x, 0) == virtual_stack_vars_rtx
6403 || XEXP (x, 0) == arg_pointer_rtx)
6404 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6406 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
6411 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
6413 || (mode != DFmode && mode != DDmode)
6414 || (TARGET_E500_DOUBLE && mode != DDmode))
6415 && (TARGET_POWERPC64 || mode != DImode)
6416 && !avoiding_indexed_address_p (mode)
6417 && legitimate_indexed_address_p (x, reg_ok_strict))
6419 if (GET_CODE (x) == PRE_MODIFY
6423 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
6425 || ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE))
6426 && (TARGET_POWERPC64 || mode != DImode)
6427 && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
6428 && !SPE_VECTOR_MODE (mode)
6429 /* Restrict addressing for DI because of our SUBREG hackery. */
6430 && !(TARGET_E500_DOUBLE
6431 && (mode == DFmode || mode == DDmode || mode == DImode))
6433 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
6434 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
6435 || (!avoiding_indexed_address_p (mode)
6436 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
6437 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
6439 if (reg_offset_p && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
6444 /* Debug version of rs6000_legitimate_address_p. */
6446 rs6000_debug_legitimate_address_p (enum machine_mode mode, rtx x,
6449 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
6451 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
6452 "strict = %d, code = %s\n",
6453 ret ? "true" : "false",
6454 GET_MODE_NAME (mode),
6456 GET_RTX_NAME (GET_CODE (x)));
6462 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
6465 rs6000_mode_dependent_address_p (const_rtx addr)
6467 return rs6000_mode_dependent_address_ptr (addr);
6470 /* Go to LABEL if ADDR (a legitimate address expression)
6471 has an effect that depends on the machine mode it is used for.
6473 On the RS/6000 this is true of all integral offsets (since AltiVec
6474 and VSX modes don't allow them) or is a pre-increment or decrement.
6476 ??? Except that due to conceptual problems in offsettable_address_p
6477 we can't really report the problems of integral offsets. So leave
6478 this assuming that the adjustable offset must be valid for the
6479 sub-words of a TFmode operand, which is what we had before. */
6482 rs6000_mode_dependent_address (const_rtx addr)
6484 switch (GET_CODE (addr))
6487 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
6488 is considered a legitimate address before reload, so there
6489 are no offset restrictions in that case. Note that this
6490 condition is safe in strict mode because any address involving
6491 virtual_stack_vars_rtx or arg_pointer_rtx would already have
6492 been rejected as illegitimate. */
6493 if (XEXP (addr, 0) != virtual_stack_vars_rtx
6494 && XEXP (addr, 0) != arg_pointer_rtx
6495 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
6497 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
6498 return val + 12 + 0x8000 >= 0x10000;
6503 /* Anything in the constant pool is sufficiently aligned that
6504 all bytes have the same high part address. */
6505 return !legitimate_constant_pool_address_p (addr, QImode, false);
6507 /* Auto-increment cases are now treated generically in recog.c. */
6509 return TARGET_UPDATE;
6511 /* AND is only allowed in Altivec loads. */
6522 /* Debug version of rs6000_mode_dependent_address. */
6524 rs6000_debug_mode_dependent_address (const_rtx addr)
6526 bool ret = rs6000_mode_dependent_address (addr);
6528 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
6529 ret ? "true" : "false");
6535 /* Implement FIND_BASE_TERM. */
6538 rs6000_find_base_term (rtx op)
6542 split_const (op, &base, &offset);
6543 if (GET_CODE (base) == UNSPEC)
6544 switch (XINT (base, 1))
6547 case UNSPEC_MACHOPIC_OFFSET:
6548 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
6549 for aliasing purposes. */
6550 return XVECEXP (base, 0, 0);
6556 /* More elaborate version of recog's offsettable_memref_p predicate
6557 that works around the ??? note of rs6000_mode_dependent_address.
6558 In particular it accepts
6560 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
6562 in 32-bit mode, that the recog predicate rejects. */
6565 rs6000_offsettable_memref_p (rtx op)
6570 /* First mimic offsettable_memref_p. */
6571 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
6574 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
6575 the latter predicate knows nothing about the mode of the memory
6576 reference and, therefore, assumes that it is the largest supported
6577 mode (TFmode). As a consequence, legitimate offsettable memory
6578 references are rejected. rs6000_legitimate_offset_address_p contains
6579 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
6580 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
6583 /* Change register usage conditional on target flags. */
6585 rs6000_conditional_register_usage (void)
6589 if (TARGET_DEBUG_TARGET)
6590 fprintf (stderr, "rs6000_conditional_register_usage called\n");
6592 /* Set MQ register fixed (already call_used) if not POWER
6593 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
6598 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
6600 fixed_regs[13] = call_used_regs[13]
6601 = call_really_used_regs[13] = 1;
6603 /* Conditionally disable FPRs. */
6604 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
6605 for (i = 32; i < 64; i++)
6606 fixed_regs[i] = call_used_regs[i]
6607 = call_really_used_regs[i] = 1;
6609 /* The TOC register is not killed across calls in a way that is
6610 visible to the compiler. */
6611 if (DEFAULT_ABI == ABI_AIX)
6612 call_really_used_regs[2] = 0;
6614 if (DEFAULT_ABI == ABI_V4
6615 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
6617 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6619 if (DEFAULT_ABI == ABI_V4
6620 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
6622 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6623 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6624 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6626 if (DEFAULT_ABI == ABI_DARWIN
6627 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
6628 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6629 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6630 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6632 if (TARGET_TOC && TARGET_MINIMAL_TOC)
6633 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6634 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6638 global_regs[SPEFSCR_REGNO] = 1;
6639 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
6640 registers in prologues and epilogues. We no longer use r14
6641 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
6642 pool for link-compatibility with older versions of GCC. Once
6643 "old" code has died out, we can return r14 to the allocation
6646 = call_used_regs[14]
6647 = call_really_used_regs[14] = 1;
6650 if (!TARGET_ALTIVEC && !TARGET_VSX)
6652 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
6653 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
6654 call_really_used_regs[VRSAVE_REGNO] = 1;
6657 if (TARGET_ALTIVEC || TARGET_VSX)
6658 global_regs[VSCR_REGNO] = 1;
6660 if (TARGET_ALTIVEC_ABI)
6662 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
6663 call_used_regs[i] = call_really_used_regs[i] = 1;
6665 /* AIX reserves VR20:31 in non-extended ABI mode. */
6667 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
6668 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
6672 /* Try to output insns to set TARGET equal to the constant C if it can
6673 be done in less than N insns. Do all computations in MODE.
6674 Returns the place where the output has been placed if it can be
6675 done and the insns have been emitted. If it would take more than N
6676 insns, zero is returned and no insns and emitted. */
6679 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
6680 rtx source, int n ATTRIBUTE_UNUSED)
6682 rtx result, insn, set;
6683 HOST_WIDE_INT c0, c1;
6690 dest = gen_reg_rtx (mode);
6691 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
6695 result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
6697 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
6698 GEN_INT (INTVAL (source)
6699 & (~ (HOST_WIDE_INT) 0xffff))));
6700 emit_insn (gen_rtx_SET (VOIDmode, dest,
6701 gen_rtx_IOR (SImode, copy_rtx (result),
6702 GEN_INT (INTVAL (source) & 0xffff))));
6707 switch (GET_CODE (source))
6710 c0 = INTVAL (source);
6715 #if HOST_BITS_PER_WIDE_INT >= 64
6716 c0 = CONST_DOUBLE_LOW (source);
6719 c0 = CONST_DOUBLE_LOW (source);
6720 c1 = CONST_DOUBLE_HIGH (source);
6728 result = rs6000_emit_set_long_const (dest, c0, c1);
6735 insn = get_last_insn ();
6736 set = single_set (insn);
6737 if (! CONSTANT_P (SET_SRC (set)))
6738 set_unique_reg_note (insn, REG_EQUAL, source);
6743 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
6744 fall back to a straight forward decomposition. We do this to avoid
6745 exponential run times encountered when looking for longer sequences
6746 with rs6000_emit_set_const. */
6748 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
6750 if (!TARGET_POWERPC64)
6752 rtx operand1, operand2;
6754 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
6756 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
6758 emit_move_insn (operand1, GEN_INT (c1));
6759 emit_move_insn (operand2, GEN_INT (c2));
6763 HOST_WIDE_INT ud1, ud2, ud3, ud4;
6766 ud2 = (c1 & 0xffff0000) >> 16;
6767 #if HOST_BITS_PER_WIDE_INT >= 64
6771 ud4 = (c2 & 0xffff0000) >> 16;
6773 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
6774 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
6777 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
6779 emit_move_insn (dest, GEN_INT (ud1));
6782 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
6783 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
6786 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
6789 emit_move_insn (dest, GEN_INT (ud2 << 16));
6791 emit_move_insn (copy_rtx (dest),
6792 gen_rtx_IOR (DImode, copy_rtx (dest),
6795 else if (ud3 == 0 && ud4 == 0)
6797 gcc_assert (ud2 & 0x8000);
6798 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
6801 emit_move_insn (copy_rtx (dest),
6802 gen_rtx_IOR (DImode, copy_rtx (dest),
6804 emit_move_insn (copy_rtx (dest),
6805 gen_rtx_ZERO_EXTEND (DImode,
6806 gen_lowpart (SImode,
6809 else if ((ud4 == 0xffff && (ud3 & 0x8000))
6810 || (ud4 == 0 && ! (ud3 & 0x8000)))
6813 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
6816 emit_move_insn (dest, GEN_INT (ud3 << 16));
6819 emit_move_insn (copy_rtx (dest),
6820 gen_rtx_IOR (DImode, copy_rtx (dest),
6822 emit_move_insn (copy_rtx (dest),
6823 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
6826 emit_move_insn (copy_rtx (dest),
6827 gen_rtx_IOR (DImode, copy_rtx (dest),
6833 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
6836 emit_move_insn (dest, GEN_INT (ud4 << 16));
6839 emit_move_insn (copy_rtx (dest),
6840 gen_rtx_IOR (DImode, copy_rtx (dest),
6843 emit_move_insn (copy_rtx (dest),
6844 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
6847 emit_move_insn (copy_rtx (dest),
6848 gen_rtx_IOR (DImode, copy_rtx (dest),
6849 GEN_INT (ud2 << 16)));
6851 emit_move_insn (copy_rtx (dest),
6852 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
6858 /* Helper for the following. Get rid of [r+r] memory refs
6859 in cases where it won't work (TImode, TFmode, TDmode). */
6862 rs6000_eliminate_indexed_memrefs (rtx operands[2])
6864 if (reload_in_progress)
6867 if (GET_CODE (operands[0]) == MEM
6868 && GET_CODE (XEXP (operands[0], 0)) != REG
6869 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
6870 GET_MODE (operands[0]), false))
6872 = replace_equiv_address (operands[0],
6873 copy_addr_to_reg (XEXP (operands[0], 0)));
6875 if (GET_CODE (operands[1]) == MEM
6876 && GET_CODE (XEXP (operands[1], 0)) != REG
6877 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
6878 GET_MODE (operands[1]), false))
6880 = replace_equiv_address (operands[1],
6881 copy_addr_to_reg (XEXP (operands[1], 0)));
6884 /* Emit a move from SOURCE to DEST in mode MODE. */
6886 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
6890 operands[1] = source;
6892 if (TARGET_DEBUG_ADDR)
6895 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
6896 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
6897 GET_MODE_NAME (mode),
6900 can_create_pseudo_p ());
6902 fprintf (stderr, "source:\n");
6906 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
6907 if (GET_CODE (operands[1]) == CONST_DOUBLE
6908 && ! FLOAT_MODE_P (mode)
6909 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6911 /* FIXME. This should never happen. */
6912 /* Since it seems that it does, do the safe thing and convert
6914 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
6916 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
6917 || FLOAT_MODE_P (mode)
6918 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
6919 || CONST_DOUBLE_LOW (operands[1]) < 0)
6920 && (CONST_DOUBLE_HIGH (operands[1]) != -1
6921 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
6923 /* Check if GCC is setting up a block move that will end up using FP
6924 registers as temporaries. We must make sure this is acceptable. */
6925 if (GET_CODE (operands[0]) == MEM
6926 && GET_CODE (operands[1]) == MEM
6928 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
6929 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
6930 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
6931 ? 32 : MEM_ALIGN (operands[0])))
6932 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
6934 : MEM_ALIGN (operands[1]))))
6935 && ! MEM_VOLATILE_P (operands [0])
6936 && ! MEM_VOLATILE_P (operands [1]))
6938 emit_move_insn (adjust_address (operands[0], SImode, 0),
6939 adjust_address (operands[1], SImode, 0));
6940 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
6941 adjust_address (copy_rtx (operands[1]), SImode, 4));
6945 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
6946 && !gpc_reg_operand (operands[1], mode))
6947 operands[1] = force_reg (mode, operands[1]);
6949 if (mode == SFmode && ! TARGET_POWERPC
6950 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6951 && GET_CODE (operands[0]) == MEM)
6955 if (reload_in_progress || reload_completed)
6956 regnum = true_regnum (operands[1]);
6957 else if (GET_CODE (operands[1]) == REG)
6958 regnum = REGNO (operands[1]);
6962 /* If operands[1] is a register, on POWER it may have
6963 double-precision data in it, so truncate it to single
6965 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
6968 newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1])
6969 : gen_reg_rtx (mode));
6970 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
6971 operands[1] = newreg;
6975 /* Recognize the case where operand[1] is a reference to thread-local
6976 data and load its address to a register. */
6977 if (rs6000_tls_referenced_p (operands[1]))
6979 enum tls_model model;
6980 rtx tmp = operands[1];
6983 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
6985 addend = XEXP (XEXP (tmp, 0), 1);
6986 tmp = XEXP (XEXP (tmp, 0), 0);
6989 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
6990 model = SYMBOL_REF_TLS_MODEL (tmp);
6991 gcc_assert (model != 0);
6993 tmp = rs6000_legitimize_tls_address (tmp, model);
6996 tmp = gen_rtx_PLUS (mode, tmp, addend);
6997 tmp = force_operand (tmp, operands[0]);
7002 /* Handle the case where reload calls us with an invalid address. */
7003 if (reload_in_progress && mode == Pmode
7004 && (! general_operand (operands[1], mode)
7005 || ! nonimmediate_operand (operands[0], mode)))
7008 /* 128-bit constant floating-point values on Darwin should really be
7009 loaded as two parts. */
7010 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
7011 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
7013 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
7014 simplify_gen_subreg (DFmode, operands[1], mode, 0),
7016 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
7017 GET_MODE_SIZE (DFmode)),
7018 simplify_gen_subreg (DFmode, operands[1], mode,
7019 GET_MODE_SIZE (DFmode)),
7024 if (reload_in_progress && cfun->machine->sdmode_stack_slot != NULL_RTX)
7025 cfun->machine->sdmode_stack_slot =
7026 eliminate_regs (cfun->machine->sdmode_stack_slot, VOIDmode, NULL_RTX);
7028 if (reload_in_progress
7030 && MEM_P (operands[0])
7031 && rtx_equal_p (operands[0], cfun->machine->sdmode_stack_slot)
7032 && REG_P (operands[1]))
7034 if (FP_REGNO_P (REGNO (operands[1])))
7036 rtx mem = adjust_address_nv (operands[0], DDmode, 0);
7037 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
7038 emit_insn (gen_movsd_store (mem, operands[1]));
7040 else if (INT_REGNO_P (REGNO (operands[1])))
7042 rtx mem = adjust_address_nv (operands[0], mode, 4);
7043 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
7044 emit_insn (gen_movsd_hardfloat (mem, operands[1]));
7050 if (reload_in_progress
7052 && REG_P (operands[0])
7053 && MEM_P (operands[1])
7054 && rtx_equal_p (operands[1], cfun->machine->sdmode_stack_slot))
7056 if (FP_REGNO_P (REGNO (operands[0])))
7058 rtx mem = adjust_address_nv (operands[1], DDmode, 0);
7059 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
7060 emit_insn (gen_movsd_load (operands[0], mem));
7062 else if (INT_REGNO_P (REGNO (operands[0])))
7064 rtx mem = adjust_address_nv (operands[1], mode, 4);
7065 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
7066 emit_insn (gen_movsd_hardfloat (operands[0], mem));
7073 /* FIXME: In the long term, this switch statement should go away
7074 and be replaced by a sequence of tests based on things like
7080 if (CONSTANT_P (operands[1])
7081 && GET_CODE (operands[1]) != CONST_INT)
7082 operands[1] = force_const_mem (mode, operands[1]);
7087 rs6000_eliminate_indexed_memrefs (operands);
7094 if (CONSTANT_P (operands[1])
7095 && ! easy_fp_constant (operands[1], mode))
7096 operands[1] = force_const_mem (mode, operands[1]);
7109 if (CONSTANT_P (operands[1])
7110 && !easy_vector_constant (operands[1], mode))
7111 operands[1] = force_const_mem (mode, operands[1]);
7116 /* Use default pattern for address of ELF small data */
7119 && DEFAULT_ABI == ABI_V4
7120 && (GET_CODE (operands[1]) == SYMBOL_REF
7121 || GET_CODE (operands[1]) == CONST)
7122 && small_data_operand (operands[1], mode))
7124 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7128 if (DEFAULT_ABI == ABI_V4
7129 && mode == Pmode && mode == SImode
7130 && flag_pic == 1 && got_operand (operands[1], mode))
7132 emit_insn (gen_movsi_got (operands[0], operands[1]));
7136 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
7140 && CONSTANT_P (operands[1])
7141 && GET_CODE (operands[1]) != HIGH
7142 && GET_CODE (operands[1]) != CONST_INT)
7144 rtx target = (!can_create_pseudo_p ()
7146 : gen_reg_rtx (mode));
7148 /* If this is a function address on -mcall-aixdesc,
7149 convert it to the address of the descriptor. */
7150 if (DEFAULT_ABI == ABI_AIX
7151 && GET_CODE (operands[1]) == SYMBOL_REF
7152 && XSTR (operands[1], 0)[0] == '.')
7154 const char *name = XSTR (operands[1], 0);
7156 while (*name == '.')
7158 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
7159 CONSTANT_POOL_ADDRESS_P (new_ref)
7160 = CONSTANT_POOL_ADDRESS_P (operands[1]);
7161 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
7162 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
7163 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
7164 operands[1] = new_ref;
7167 if (DEFAULT_ABI == ABI_DARWIN)
7170 if (MACHO_DYNAMIC_NO_PIC_P)
7172 /* Take care of any required data indirection. */
7173 operands[1] = rs6000_machopic_legitimize_pic_address (
7174 operands[1], mode, operands[0]);
7175 if (operands[0] != operands[1])
7176 emit_insn (gen_rtx_SET (VOIDmode,
7177 operands[0], operands[1]));
7181 emit_insn (gen_macho_high (target, operands[1]));
7182 emit_insn (gen_macho_low (operands[0], target, operands[1]));
7186 emit_insn (gen_elf_high (target, operands[1]));
7187 emit_insn (gen_elf_low (operands[0], target, operands[1]));
7191 /* If this is a SYMBOL_REF that refers to a constant pool entry,
7192 and we have put it in the TOC, we just need to make a TOC-relative
7195 && GET_CODE (operands[1]) == SYMBOL_REF
7196 && constant_pool_expr_p (operands[1])
7197 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
7198 get_pool_mode (operands[1])))
7199 || (TARGET_CMODEL == CMODEL_MEDIUM
7200 && GET_CODE (operands[1]) == SYMBOL_REF
7201 && !CONSTANT_POOL_ADDRESS_P (operands[1])
7202 && SYMBOL_REF_LOCAL_P (operands[1])))
7205 if (TARGET_CMODEL != CMODEL_SMALL)
7207 if (can_create_pseudo_p ())
7208 reg = gen_reg_rtx (Pmode);
7212 operands[1] = create_TOC_reference (operands[1], reg);
7214 else if (mode == Pmode
7215 && CONSTANT_P (operands[1])
7216 && GET_CODE (operands[1]) != HIGH
7217 && !(TARGET_CMODEL != CMODEL_SMALL
7218 && GET_CODE (operands[1]) == CONST
7219 && GET_CODE (XEXP (operands[1], 0)) == PLUS
7220 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == HIGH)
7221 && ((GET_CODE (operands[1]) != CONST_INT
7222 && ! easy_fp_constant (operands[1], mode))
7223 || (GET_CODE (operands[1]) == CONST_INT
7224 && (num_insns_constant (operands[1], mode)
7225 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
7226 || (GET_CODE (operands[0]) == REG
7227 && FP_REGNO_P (REGNO (operands[0]))))
7228 && ! legitimate_constant_pool_address_p (operands[1], mode,
7230 && ! toc_relative_expr_p (operands[1])
7231 && (TARGET_CMODEL == CMODEL_SMALL
7232 || can_create_pseudo_p ()
7233 || (REG_P (operands[0])
7234 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
7238 /* Darwin uses a special PIC legitimizer. */
7239 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
7242 rs6000_machopic_legitimize_pic_address (operands[1], mode,
7244 if (operands[0] != operands[1])
7245 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7250 /* If we are to limit the number of things we put in the TOC and
7251 this is a symbol plus a constant we can add in one insn,
7252 just put the symbol in the TOC and add the constant. Don't do
7253 this if reload is in progress. */
7254 if (GET_CODE (operands[1]) == CONST
7255 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
7256 && GET_CODE (XEXP (operands[1], 0)) == PLUS
7257 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
7258 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
7259 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
7260 && ! side_effects_p (operands[0]))
7263 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
7264 rtx other = XEXP (XEXP (operands[1], 0), 1);
7266 sym = force_reg (mode, sym);
7267 emit_insn (gen_add3_insn (operands[0], sym, other));
7271 operands[1] = force_const_mem (mode, operands[1]);
7274 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
7275 && constant_pool_expr_p (XEXP (operands[1], 0))
7276 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
7277 get_pool_constant (XEXP (operands[1], 0)),
7278 get_pool_mode (XEXP (operands[1], 0))))
7282 if (TARGET_CMODEL != CMODEL_SMALL)
7284 if (can_create_pseudo_p ())
7285 reg = gen_reg_rtx (Pmode);
7289 tocref = create_TOC_reference (XEXP (operands[1], 0), reg);
7290 operands[1] = gen_const_mem (mode, tocref);
7291 set_mem_alias_set (operands[1], get_TOC_alias_set ());
7297 rs6000_eliminate_indexed_memrefs (operands);
7301 emit_insn (gen_rtx_PARALLEL (VOIDmode,
7303 gen_rtx_SET (VOIDmode,
7304 operands[0], operands[1]),
7305 gen_rtx_CLOBBER (VOIDmode,
7306 gen_rtx_SCRATCH (SImode)))));
7312 fatal_insn ("bad move", gen_rtx_SET (VOIDmode, dest, source));
7315 /* Above, we may have called force_const_mem which may have returned
7316 an invalid address. If we can, fix this up; otherwise, reload will
7317 have to deal with it. */
7318 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
7319 operands[1] = validize_mem (operands[1]);
7322 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7325 /* Nonzero if we can use a floating-point register to pass this arg. */
7326 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
7327 (SCALAR_FLOAT_MODE_P (MODE) \
7328 && (CUM)->fregno <= FP_ARG_MAX_REG \
7329 && TARGET_HARD_FLOAT && TARGET_FPRS)
7331 /* Nonzero if we can use an AltiVec register to pass this arg. */
7332 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
7333 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
7334 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
7335 && TARGET_ALTIVEC_ABI \
7338 /* Return a nonzero value to say to return the function value in
7339 memory, just as large structures are always returned. TYPE will be
7340 the data type of the value, and FNTYPE will be the type of the
7341 function doing the returning, or @code{NULL} for libcalls.
7343 The AIX ABI for the RS/6000 specifies that all structures are
7344 returned in memory. The Darwin ABI does the same.
7346 For the Darwin 64 Bit ABI, a function result can be returned in
7347 registers or in memory, depending on the size of the return data
7348 type. If it is returned in registers, the value occupies the same
7349 registers as it would if it were the first and only function
7350 argument. Otherwise, the function places its result in memory at
7351 the location pointed to by GPR3.
7353 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
7354 but a draft put them in memory, and GCC used to implement the draft
7355 instead of the final standard. Therefore, aix_struct_return
7356 controls this instead of DEFAULT_ABI; V.4 targets needing backward
7357 compatibility can change DRAFT_V4_STRUCT_RET to override the
7358 default, and -m switches get the final word. See
7359 rs6000_option_override_internal for more details.
7361 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
7362 long double support is enabled. These values are returned in memory.
7364 int_size_in_bytes returns -1 for variable size objects, which go in
7365 memory always. The cast to unsigned makes -1 > 8. */
7368 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
7370 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
7372 && rs6000_darwin64_abi
7373 && TREE_CODE (type) == RECORD_TYPE
7374 && int_size_in_bytes (type) > 0)
7376 CUMULATIVE_ARGS valcum;
7380 valcum.fregno = FP_ARG_MIN_REG;
7381 valcum.vregno = ALTIVEC_ARG_MIN_REG;
7382 /* Do a trial code generation as if this were going to be passed
7383 as an argument; if any part goes in memory, we return NULL. */
7384 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
7387 /* Otherwise fall through to more conventional ABI rules. */
7390 if (AGGREGATE_TYPE_P (type)
7391 && (aix_struct_return
7392 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
7395 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
7396 modes only exist for GCC vector types if -maltivec. */
7397 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
7398 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
7401 /* Return synthetic vectors in memory. */
7402 if (TREE_CODE (type) == VECTOR_TYPE
7403 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
7405 static bool warned_for_return_big_vectors = false;
7406 if (!warned_for_return_big_vectors)
7408 warning (0, "GCC vector returned by reference: "
7409 "non-standard ABI extension with no compatibility guarantee");
7410 warned_for_return_big_vectors = true;
7415 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
7421 #ifdef HAVE_AS_GNU_ATTRIBUTE
7422 /* Return TRUE if a call to function FNDECL may be one that
7423 potentially affects the function calling ABI of the object file. */
7426 call_ABI_of_interest (tree fndecl)
7428 if (cgraph_state == CGRAPH_STATE_EXPANSION)
7430 struct cgraph_node *c_node;
7432 /* Libcalls are always interesting. */
7433 if (fndecl == NULL_TREE)
7436 /* Any call to an external function is interesting. */
7437 if (DECL_EXTERNAL (fndecl))
7440 /* Interesting functions that we are emitting in this object file. */
7441 c_node = cgraph_get_node (fndecl);
7442 c_node = cgraph_function_or_thunk_node (c_node, NULL);
7443 return !cgraph_only_called_directly_p (c_node);
7449 /* Initialize a variable CUM of type CUMULATIVE_ARGS
7450 for a call to a function whose data type is FNTYPE.
7451 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
7453 For incoming args we set the number of arguments in the prototype large
7454 so we never return a PARALLEL. */
7457 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
7458 rtx libname ATTRIBUTE_UNUSED, int incoming,
7459 int libcall, int n_named_args,
7460 tree fndecl ATTRIBUTE_UNUSED,
7461 enum machine_mode return_mode ATTRIBUTE_UNUSED)
7463 static CUMULATIVE_ARGS zero_cumulative;
7465 *cum = zero_cumulative;
7467 cum->fregno = FP_ARG_MIN_REG;
7468 cum->vregno = ALTIVEC_ARG_MIN_REG;
7469 cum->prototype = (fntype && prototype_p (fntype));
7470 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
7471 ? CALL_LIBCALL : CALL_NORMAL);
7472 cum->sysv_gregno = GP_ARG_MIN_REG;
7473 cum->stdarg = stdarg_p (fntype);
7475 cum->nargs_prototype = 0;
7476 if (incoming || cum->prototype)
7477 cum->nargs_prototype = n_named_args;
7479 /* Check for a longcall attribute. */
7480 if ((!fntype && rs6000_default_long_calls)
7482 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
7483 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
7484 cum->call_cookie |= CALL_LONG;
7486 if (TARGET_DEBUG_ARG)
7488 fprintf (stderr, "\ninit_cumulative_args:");
7491 tree ret_type = TREE_TYPE (fntype);
7492 fprintf (stderr, " ret code = %s,",
7493 tree_code_name[ (int)TREE_CODE (ret_type) ]);
7496 if (cum->call_cookie & CALL_LONG)
7497 fprintf (stderr, " longcall,");
7499 fprintf (stderr, " proto = %d, nargs = %d\n",
7500 cum->prototype, cum->nargs_prototype);
7503 #ifdef HAVE_AS_GNU_ATTRIBUTE
7504 if (DEFAULT_ABI == ABI_V4)
7506 cum->escapes = call_ABI_of_interest (fndecl);
7513 return_type = TREE_TYPE (fntype);
7514 return_mode = TYPE_MODE (return_type);
7517 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
7519 if (return_type != NULL)
7521 if (TREE_CODE (return_type) == RECORD_TYPE
7522 && TYPE_TRANSPARENT_AGGR (return_type))
7524 return_type = TREE_TYPE (first_field (return_type));
7525 return_mode = TYPE_MODE (return_type);
7527 if (AGGREGATE_TYPE_P (return_type)
7528 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
7530 rs6000_returns_struct = true;
7532 if (SCALAR_FLOAT_MODE_P (return_mode))
7533 rs6000_passes_float = true;
7534 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode)
7535 || SPE_VECTOR_MODE (return_mode))
7536 rs6000_passes_vector = true;
7543 && TARGET_ALTIVEC_ABI
7544 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
7546 error ("cannot return value in vector register because"
7547 " altivec instructions are disabled, use -maltivec"
7552 /* Return true if TYPE must be passed on the stack and not in registers. */
7555 rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type)
7557 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
7558 return must_pass_in_stack_var_size (mode, type);
7560 return must_pass_in_stack_var_size_or_pad (mode, type);
7563 /* If defined, a C expression which determines whether, and in which
7564 direction, to pad out an argument with extra space. The value
7565 should be of type `enum direction': either `upward' to pad above
7566 the argument, `downward' to pad below, or `none' to inhibit
7569 For the AIX ABI structs are always stored left shifted in their
7573 function_arg_padding (enum machine_mode mode, const_tree type)
7575 #ifndef AGGREGATE_PADDING_FIXED
7576 #define AGGREGATE_PADDING_FIXED 0
7578 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
7579 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
7582 if (!AGGREGATE_PADDING_FIXED)
7584 /* GCC used to pass structures of the same size as integer types as
7585 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
7586 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
7587 passed padded downward, except that -mstrict-align further
7588 muddied the water in that multi-component structures of 2 and 4
7589 bytes in size were passed padded upward.
7591 The following arranges for best compatibility with previous
7592 versions of gcc, but removes the -mstrict-align dependency. */
7593 if (BYTES_BIG_ENDIAN)
7595 HOST_WIDE_INT size = 0;
7597 if (mode == BLKmode)
7599 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
7600 size = int_size_in_bytes (type);
7603 size = GET_MODE_SIZE (mode);
7605 if (size == 1 || size == 2 || size == 4)
7611 if (AGGREGATES_PAD_UPWARD_ALWAYS)
7613 if (type != 0 && AGGREGATE_TYPE_P (type))
7617 /* Fall back to the default. */
7618 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
7621 /* If defined, a C expression that gives the alignment boundary, in bits,
7622 of an argument with the specified mode and type. If it is not defined,
7623 PARM_BOUNDARY is used for all arguments.
7625 V.4 wants long longs and doubles to be double word aligned. Just
7626 testing the mode size is a boneheaded way to do this as it means
7627 that other types such as complex int are also double word aligned.
7628 However, we're stuck with this because changing the ABI might break
7629 existing library interfaces.
7631 Doubleword align SPE vectors.
7632 Quadword align Altivec/VSX vectors.
7633 Quadword align large synthetic vector types. */
7636 rs6000_function_arg_boundary (enum machine_mode mode, const_tree type)
7638 if (DEFAULT_ABI == ABI_V4
7639 && (GET_MODE_SIZE (mode) == 8
7640 || (TARGET_HARD_FLOAT
7642 && (mode == TFmode || mode == TDmode))))
7644 else if (SPE_VECTOR_MODE (mode)
7645 || (type && TREE_CODE (type) == VECTOR_TYPE
7646 && int_size_in_bytes (type) >= 8
7647 && int_size_in_bytes (type) < 16))
7649 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
7650 || (type && TREE_CODE (type) == VECTOR_TYPE
7651 && int_size_in_bytes (type) >= 16))
7653 else if (TARGET_MACHO
7654 && rs6000_darwin64_abi
7656 && type && TYPE_ALIGN (type) > 64)
7659 return PARM_BOUNDARY;
7662 /* For a function parm of MODE and TYPE, return the starting word in
7663 the parameter area. NWORDS of the parameter area are already used. */
7666 rs6000_parm_start (enum machine_mode mode, const_tree type,
7667 unsigned int nwords)
7670 unsigned int parm_offset;
7672 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
7673 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
7674 return nwords + (-(parm_offset + nwords) & align);
7677 /* Compute the size (in words) of a function argument. */
7679 static unsigned long
7680 rs6000_arg_size (enum machine_mode mode, const_tree type)
7684 if (mode != BLKmode)
7685 size = GET_MODE_SIZE (mode);
7687 size = int_size_in_bytes (type);
7690 return (size + 3) >> 2;
7692 return (size + 7) >> 3;
7695 /* Use this to flush pending int fields. */
7698 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
7699 HOST_WIDE_INT bitpos, int final)
7701 unsigned int startbit, endbit;
7702 int intregs, intoffset;
7703 enum machine_mode mode;
7705 /* Handle the situations where a float is taking up the first half
7706 of the GPR, and the other half is empty (typically due to
7707 alignment restrictions). We can detect this by a 8-byte-aligned
7708 int field, or by seeing that this is the final flush for this
7709 argument. Count the word and continue on. */
7710 if (cum->floats_in_gpr == 1
7711 && (cum->intoffset % 64 == 0
7712 || (cum->intoffset == -1 && final)))
7715 cum->floats_in_gpr = 0;
7718 if (cum->intoffset == -1)
7721 intoffset = cum->intoffset;
7722 cum->intoffset = -1;
7723 cum->floats_in_gpr = 0;
7725 if (intoffset % BITS_PER_WORD != 0)
7727 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
7729 if (mode == BLKmode)
7731 /* We couldn't find an appropriate mode, which happens,
7732 e.g., in packed structs when there are 3 bytes to load.
7733 Back intoffset back to the beginning of the word in this
7735 intoffset = intoffset & -BITS_PER_WORD;
7739 startbit = intoffset & -BITS_PER_WORD;
7740 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
7741 intregs = (endbit - startbit) / BITS_PER_WORD;
7742 cum->words += intregs;
7743 /* words should be unsigned. */
7744 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
7746 int pad = (endbit/BITS_PER_WORD) - cum->words;
7751 /* The darwin64 ABI calls for us to recurse down through structs,
7752 looking for elements passed in registers. Unfortunately, we have
7753 to track int register count here also because of misalignments
7754 in powerpc alignment mode. */
7757 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
7759 HOST_WIDE_INT startbitpos)
7763 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
7764 if (TREE_CODE (f) == FIELD_DECL)
7766 HOST_WIDE_INT bitpos = startbitpos;
7767 tree ftype = TREE_TYPE (f);
7768 enum machine_mode mode;
7769 if (ftype == error_mark_node)
7771 mode = TYPE_MODE (ftype);
7773 if (DECL_SIZE (f) != 0
7774 && host_integerp (bit_position (f), 1))
7775 bitpos += int_bit_position (f);
7777 /* ??? FIXME: else assume zero offset. */
7779 if (TREE_CODE (ftype) == RECORD_TYPE)
7780 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
7781 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
7783 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
7784 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
7785 cum->fregno += n_fpregs;
7786 /* Single-precision floats present a special problem for
7787 us, because they are smaller than an 8-byte GPR, and so
7788 the structure-packing rules combined with the standard
7789 varargs behavior mean that we want to pack float/float
7790 and float/int combinations into a single register's
7791 space. This is complicated by the arg advance flushing,
7792 which works on arbitrarily large groups of int-type
7796 if (cum->floats_in_gpr == 1)
7798 /* Two floats in a word; count the word and reset
7801 cum->floats_in_gpr = 0;
7803 else if (bitpos % 64 == 0)
7805 /* A float at the beginning of an 8-byte word;
7806 count it and put off adjusting cum->words until
7807 we see if a arg advance flush is going to do it
7809 cum->floats_in_gpr++;
7813 /* The float is at the end of a word, preceded
7814 by integer fields, so the arg advance flush
7815 just above has already set cum->words and
7816 everything is taken care of. */
7820 cum->words += n_fpregs;
7822 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
7824 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
7828 else if (cum->intoffset == -1)
7829 cum->intoffset = bitpos;
7833 /* Check for an item that needs to be considered specially under the darwin 64
7834 bit ABI. These are record types where the mode is BLK or the structure is
7837 rs6000_darwin64_struct_check_p (enum machine_mode mode, const_tree type)
7839 return rs6000_darwin64_abi
7840 && ((mode == BLKmode
7841 && TREE_CODE (type) == RECORD_TYPE
7842 && int_size_in_bytes (type) > 0)
7843 || (type && TREE_CODE (type) == RECORD_TYPE
7844 && int_size_in_bytes (type) == 8)) ? 1 : 0;
7847 /* Update the data in CUM to advance over an argument
7848 of mode MODE and data type TYPE.
7849 (TYPE is null for libcalls where that information may not be available.)
7851 Note that for args passed by reference, function_arg will be called
7852 with MODE and TYPE set to that of the pointer to the arg, not the arg
7856 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7857 const_tree type, bool named, int depth)
7859 /* Only tick off an argument if we're not recursing. */
7861 cum->nargs_prototype--;
7863 #ifdef HAVE_AS_GNU_ATTRIBUTE
7864 if (DEFAULT_ABI == ABI_V4
7867 if (SCALAR_FLOAT_MODE_P (mode))
7868 rs6000_passes_float = true;
7869 else if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
7870 rs6000_passes_vector = true;
7871 else if (SPE_VECTOR_MODE (mode)
7873 && cum->sysv_gregno <= GP_ARG_MAX_REG)
7874 rs6000_passes_vector = true;
7878 if (TARGET_ALTIVEC_ABI
7879 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
7880 || (type && TREE_CODE (type) == VECTOR_TYPE
7881 && int_size_in_bytes (type) == 16)))
7885 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
7888 if (!TARGET_ALTIVEC)
7889 error ("cannot pass argument in vector register because"
7890 " altivec instructions are disabled, use -maltivec"
7893 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
7894 even if it is going to be passed in a vector register.
7895 Darwin does the same for variable-argument functions. */
7896 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
7897 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
7907 /* Vector parameters must be 16-byte aligned. This places
7908 them at 2 mod 4 in terms of words in 32-bit mode, since
7909 the parameter save area starts at offset 24 from the
7910 stack. In 64-bit mode, they just have to start on an
7911 even word, since the parameter save area is 16-byte
7912 aligned. Space for GPRs is reserved even if the argument
7913 will be passed in memory. */
7915 align = (2 - cum->words) & 3;
7917 align = cum->words & 1;
7918 cum->words += align + rs6000_arg_size (mode, type);
7920 if (TARGET_DEBUG_ARG)
7922 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
7924 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
7925 cum->nargs_prototype, cum->prototype,
7926 GET_MODE_NAME (mode));
7930 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
7932 && cum->sysv_gregno <= GP_ARG_MAX_REG)
7935 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
7937 int size = int_size_in_bytes (type);
7938 /* Variable sized types have size == -1 and are
7939 treated as if consisting entirely of ints.
7940 Pad to 16 byte boundary if needed. */
7941 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
7942 && (cum->words % 2) != 0)
7944 /* For varargs, we can just go up by the size of the struct. */
7946 cum->words += (size + 7) / 8;
7949 /* It is tempting to say int register count just goes up by
7950 sizeof(type)/8, but this is wrong in a case such as
7951 { int; double; int; } [powerpc alignment]. We have to
7952 grovel through the fields for these too. */
7954 cum->floats_in_gpr = 0;
7955 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
7956 rs6000_darwin64_record_arg_advance_flush (cum,
7957 size * BITS_PER_UNIT, 1);
7959 if (TARGET_DEBUG_ARG)
7961 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
7962 cum->words, TYPE_ALIGN (type), size);
7964 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
7965 cum->nargs_prototype, cum->prototype,
7966 GET_MODE_NAME (mode));
7969 else if (DEFAULT_ABI == ABI_V4)
7971 if (TARGET_HARD_FLOAT && TARGET_FPRS
7972 && ((TARGET_SINGLE_FLOAT && mode == SFmode)
7973 || (TARGET_DOUBLE_FLOAT && mode == DFmode)
7974 || (mode == TFmode && !TARGET_IEEEQUAD)
7975 || mode == SDmode || mode == DDmode || mode == TDmode))
7977 /* _Decimal128 must use an even/odd register pair. This assumes
7978 that the register number is odd when fregno is odd. */
7979 if (mode == TDmode && (cum->fregno % 2) == 1)
7982 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
7983 <= FP_ARG_V4_MAX_REG)
7984 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
7987 cum->fregno = FP_ARG_V4_MAX_REG + 1;
7988 if (mode == DFmode || mode == TFmode
7989 || mode == DDmode || mode == TDmode)
7990 cum->words += cum->words & 1;
7991 cum->words += rs6000_arg_size (mode, type);
7996 int n_words = rs6000_arg_size (mode, type);
7997 int gregno = cum->sysv_gregno;
7999 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
8000 (r7,r8) or (r9,r10). As does any other 2 word item such
8001 as complex int due to a historical mistake. */
8003 gregno += (1 - gregno) & 1;
8005 /* Multi-reg args are not split between registers and stack. */
8006 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
8008 /* Long long and SPE vectors are aligned on the stack.
8009 So are other 2 word items such as complex int due to
8010 a historical mistake. */
8012 cum->words += cum->words & 1;
8013 cum->words += n_words;
8016 /* Note: continuing to accumulate gregno past when we've started
8017 spilling to the stack indicates the fact that we've started
8018 spilling to the stack to expand_builtin_saveregs. */
8019 cum->sysv_gregno = gregno + n_words;
8022 if (TARGET_DEBUG_ARG)
8024 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
8025 cum->words, cum->fregno);
8026 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
8027 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
8028 fprintf (stderr, "mode = %4s, named = %d\n",
8029 GET_MODE_NAME (mode), named);
8034 int n_words = rs6000_arg_size (mode, type);
8035 int start_words = cum->words;
8036 int align_words = rs6000_parm_start (mode, type, start_words);
8038 cum->words = align_words + n_words;
8040 if (SCALAR_FLOAT_MODE_P (mode)
8041 && TARGET_HARD_FLOAT && TARGET_FPRS)
8043 /* _Decimal128 must be passed in an even/odd float register pair.
8044 This assumes that the register number is odd when fregno is
8046 if (mode == TDmode && (cum->fregno % 2) == 1)
8048 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
8051 if (TARGET_DEBUG_ARG)
8053 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
8054 cum->words, cum->fregno);
8055 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
8056 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
8057 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
8058 named, align_words - start_words, depth);
8064 rs6000_function_arg_advance (cumulative_args_t cum, enum machine_mode mode,
8065 const_tree type, bool named)
8067 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
8072 spe_build_register_parallel (enum machine_mode mode, int gregno)
8079 r1 = gen_rtx_REG (DImode, gregno);
8080 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
8081 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
8085 r1 = gen_rtx_REG (DImode, gregno);
8086 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
8087 r3 = gen_rtx_REG (DImode, gregno + 2);
8088 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
8089 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
8092 r1 = gen_rtx_REG (DImode, gregno);
8093 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
8094 r3 = gen_rtx_REG (DImode, gregno + 2);
8095 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
8096 r5 = gen_rtx_REG (DImode, gregno + 4);
8097 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
8098 r7 = gen_rtx_REG (DImode, gregno + 6);
8099 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
8100 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
8107 /* Determine where to put a SIMD argument on the SPE. */
8109 rs6000_spe_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
8112 int gregno = cum->sysv_gregno;
8114 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
8115 are passed and returned in a pair of GPRs for ABI compatibility. */
8116 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
8117 || mode == DCmode || mode == TCmode))
8119 int n_words = rs6000_arg_size (mode, type);
8121 /* Doubles go in an odd/even register pair (r5/r6, etc). */
8123 gregno += (1 - gregno) & 1;
8125 /* Multi-reg args are not split between registers and stack. */
8126 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
8129 return spe_build_register_parallel (mode, gregno);
8133 int n_words = rs6000_arg_size (mode, type);
8135 /* SPE vectors are put in odd registers. */
8136 if (n_words == 2 && (gregno & 1) == 0)
8139 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
8142 enum machine_mode m = SImode;
8144 r1 = gen_rtx_REG (m, gregno);
8145 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
8146 r2 = gen_rtx_REG (m, gregno + 1);
8147 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
8148 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
8155 if (gregno <= GP_ARG_MAX_REG)
8156 return gen_rtx_REG (mode, gregno);
8162 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
8163 structure between cum->intoffset and bitpos to integer registers. */
8166 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
8167 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
8169 enum machine_mode mode;
8171 unsigned int startbit, endbit;
8172 int this_regno, intregs, intoffset;
8175 if (cum->intoffset == -1)
8178 intoffset = cum->intoffset;
8179 cum->intoffset = -1;
8181 /* If this is the trailing part of a word, try to only load that
8182 much into the register. Otherwise load the whole register. Note
8183 that in the latter case we may pick up unwanted bits. It's not a
8184 problem at the moment but may wish to revisit. */
8186 if (intoffset % BITS_PER_WORD != 0)
8188 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
8190 if (mode == BLKmode)
8192 /* We couldn't find an appropriate mode, which happens,
8193 e.g., in packed structs when there are 3 bytes to load.
8194 Back intoffset back to the beginning of the word in this
8196 intoffset = intoffset & -BITS_PER_WORD;
8203 startbit = intoffset & -BITS_PER_WORD;
8204 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
8205 intregs = (endbit - startbit) / BITS_PER_WORD;
8206 this_regno = cum->words + intoffset / BITS_PER_WORD;
8208 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
8211 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
8215 intoffset /= BITS_PER_UNIT;
8218 regno = GP_ARG_MIN_REG + this_regno;
8219 reg = gen_rtx_REG (mode, regno);
8221 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
8224 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
8228 while (intregs > 0);
8231 /* Recursive workhorse for the following. */
8234 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
8235 HOST_WIDE_INT startbitpos, rtx rvec[],
8240 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
8241 if (TREE_CODE (f) == FIELD_DECL)
8243 HOST_WIDE_INT bitpos = startbitpos;
8244 tree ftype = TREE_TYPE (f);
8245 enum machine_mode mode;
8246 if (ftype == error_mark_node)
8248 mode = TYPE_MODE (ftype);
8250 if (DECL_SIZE (f) != 0
8251 && host_integerp (bit_position (f), 1))
8252 bitpos += int_bit_position (f);
8254 /* ??? FIXME: else assume zero offset. */
8256 if (TREE_CODE (ftype) == RECORD_TYPE)
8257 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
8258 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
8260 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
8264 case SCmode: mode = SFmode; break;
8265 case DCmode: mode = DFmode; break;
8266 case TCmode: mode = TFmode; break;
8270 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
8271 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
8273 gcc_assert (cum->fregno == FP_ARG_MAX_REG
8274 && (mode == TFmode || mode == TDmode));
8275 /* Long double or _Decimal128 split over regs and memory. */
8276 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
8280 = gen_rtx_EXPR_LIST (VOIDmode,
8281 gen_rtx_REG (mode, cum->fregno++),
8282 GEN_INT (bitpos / BITS_PER_UNIT));
8283 if (mode == TFmode || mode == TDmode)
8286 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
8288 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
8290 = gen_rtx_EXPR_LIST (VOIDmode,
8291 gen_rtx_REG (mode, cum->vregno++),
8292 GEN_INT (bitpos / BITS_PER_UNIT));
8294 else if (cum->intoffset == -1)
8295 cum->intoffset = bitpos;
8299 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
8300 the register(s) to be used for each field and subfield of a struct
8301 being passed by value, along with the offset of where the
8302 register's value may be found in the block. FP fields go in FP
8303 register, vector fields go in vector registers, and everything
8304 else goes in int registers, packed as in memory.
8306 This code is also used for function return values. RETVAL indicates
8307 whether this is the case.
8309 Much of this is taken from the SPARC V9 port, which has a similar
8310 calling convention. */
8313 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
8314 bool named, bool retval)
8316 rtx rvec[FIRST_PSEUDO_REGISTER];
8317 int k = 1, kbase = 1;
8318 HOST_WIDE_INT typesize = int_size_in_bytes (type);
8319 /* This is a copy; modifications are not visible to our caller. */
8320 CUMULATIVE_ARGS copy_cum = *orig_cum;
8321 CUMULATIVE_ARGS *cum = ©_cum;
8323 /* Pad to 16 byte boundary if needed. */
8324 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
8325 && (cum->words % 2) != 0)
8332 /* Put entries into rvec[] for individual FP and vector fields, and
8333 for the chunks of memory that go in int regs. Note we start at
8334 element 1; 0 is reserved for an indication of using memory, and
8335 may or may not be filled in below. */
8336 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
8337 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
8339 /* If any part of the struct went on the stack put all of it there.
8340 This hack is because the generic code for
8341 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
8342 parts of the struct are not at the beginning. */
8346 return NULL_RTX; /* doesn't go in registers at all */
8348 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8350 if (k > 1 || cum->use_stack)
8351 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
8356 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
8359 rs6000_mixed_function_arg (enum machine_mode mode, const_tree type,
8364 rtx rvec[GP_ARG_NUM_REG + 1];
8366 if (align_words >= GP_ARG_NUM_REG)
8369 n_units = rs6000_arg_size (mode, type);
8371 /* Optimize the simple case where the arg fits in one gpr, except in
8372 the case of BLKmode due to assign_parms assuming that registers are
8373 BITS_PER_WORD wide. */
8375 || (n_units == 1 && mode != BLKmode))
8376 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8379 if (align_words + n_units > GP_ARG_NUM_REG)
8380 /* Not all of the arg fits in gprs. Say that it goes in memory too,
8381 using a magic NULL_RTX component.
8382 This is not strictly correct. Only some of the arg belongs in
8383 memory, not all of it. However, the normal scheme using
8384 function_arg_partial_nregs can result in unusual subregs, eg.
8385 (subreg:SI (reg:DF) 4), which are not handled well. The code to
8386 store the whole arg to memory is often more efficient than code
8387 to store pieces, and we know that space is available in the right
8388 place for the whole arg. */
8389 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8394 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
8395 rtx off = GEN_INT (i++ * 4);
8396 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
8398 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
8400 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
8403 /* Determine where to put an argument to a function.
8404 Value is zero to push the argument on the stack,
8405 or a hard register in which to store the argument.
8407 MODE is the argument's machine mode.
8408 TYPE is the data type of the argument (as a tree).
8409 This is null for libcalls where that information may
8411 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8412 the preceding args and about the function being called. It is
8413 not modified in this routine.
8414 NAMED is nonzero if this argument is a named parameter
8415 (otherwise it is an extra parameter matching an ellipsis).
8417 On RS/6000 the first eight words of non-FP are normally in registers
8418 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
8419 Under V.4, the first 8 FP args are in registers.
8421 If this is floating-point and no prototype is specified, we use
8422 both an FP and integer register (or possibly FP reg and stack). Library
8423 functions (when CALL_LIBCALL is set) always have the proper types for args,
8424 so we can pass the FP value just in one register. emit_library_function
8425 doesn't support PARALLEL anyway.
8427 Note that for args passed by reference, function_arg will be called
8428 with MODE and TYPE set to that of the pointer to the arg, not the arg
8432 rs6000_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
8433 const_tree type, bool named)
8435 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8436 enum rs6000_abi abi = DEFAULT_ABI;
8438 /* Return a marker to indicate whether CR1 needs to set or clear the
8439 bit that V.4 uses to say fp args were passed in registers.
8440 Assume that we don't need the marker for software floating point,
8441 or compiler generated library calls. */
8442 if (mode == VOIDmode)
8445 && (cum->call_cookie & CALL_LIBCALL) == 0
8447 || (cum->nargs_prototype < 0
8448 && (cum->prototype || TARGET_NO_PROTOTYPE))))
8450 /* For the SPE, we need to crxor CR6 always. */
8452 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
8453 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
8454 return GEN_INT (cum->call_cookie
8455 | ((cum->fregno == FP_ARG_MIN_REG)
8456 ? CALL_V4_SET_FP_ARGS
8457 : CALL_V4_CLEAR_FP_ARGS));
8460 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
8463 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
8465 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
8466 if (rslt != NULL_RTX)
8468 /* Else fall through to usual handling. */
8471 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
8472 if (TARGET_64BIT && ! cum->prototype)
8474 /* Vector parameters get passed in vector register
8475 and also in GPRs or memory, in absence of prototype. */
8478 align_words = (cum->words + 1) & ~1;
8480 if (align_words >= GP_ARG_NUM_REG)
8486 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8488 return gen_rtx_PARALLEL (mode,
8490 gen_rtx_EXPR_LIST (VOIDmode,
8492 gen_rtx_EXPR_LIST (VOIDmode,
8493 gen_rtx_REG (mode, cum->vregno),
8497 return gen_rtx_REG (mode, cum->vregno);
8498 else if (TARGET_ALTIVEC_ABI
8499 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
8500 || (type && TREE_CODE (type) == VECTOR_TYPE
8501 && int_size_in_bytes (type) == 16)))
8503 if (named || abi == ABI_V4)
8507 /* Vector parameters to varargs functions under AIX or Darwin
8508 get passed in memory and possibly also in GPRs. */
8509 int align, align_words, n_words;
8510 enum machine_mode part_mode;
8512 /* Vector parameters must be 16-byte aligned. This places them at
8513 2 mod 4 in terms of words in 32-bit mode, since the parameter
8514 save area starts at offset 24 from the stack. In 64-bit mode,
8515 they just have to start on an even word, since the parameter
8516 save area is 16-byte aligned. */
8518 align = (2 - cum->words) & 3;
8520 align = cum->words & 1;
8521 align_words = cum->words + align;
8523 /* Out of registers? Memory, then. */
8524 if (align_words >= GP_ARG_NUM_REG)
8527 if (TARGET_32BIT && TARGET_POWERPC64)
8528 return rs6000_mixed_function_arg (mode, type, align_words);
8530 /* The vector value goes in GPRs. Only the part of the
8531 value in GPRs is reported here. */
8533 n_words = rs6000_arg_size (mode, type);
8534 if (align_words + n_words > GP_ARG_NUM_REG)
8535 /* Fortunately, there are only two possibilities, the value
8536 is either wholly in GPRs or half in GPRs and half not. */
8539 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
8542 else if (TARGET_SPE_ABI && TARGET_SPE
8543 && (SPE_VECTOR_MODE (mode)
8544 || (TARGET_E500_DOUBLE && (mode == DFmode
8547 || mode == TCmode))))
8548 return rs6000_spe_function_arg (cum, mode, type);
8550 else if (abi == ABI_V4)
8552 if (TARGET_HARD_FLOAT && TARGET_FPRS
8553 && ((TARGET_SINGLE_FLOAT && mode == SFmode)
8554 || (TARGET_DOUBLE_FLOAT && mode == DFmode)
8555 || (mode == TFmode && !TARGET_IEEEQUAD)
8556 || mode == SDmode || mode == DDmode || mode == TDmode))
8558 /* _Decimal128 must use an even/odd register pair. This assumes
8559 that the register number is odd when fregno is odd. */
8560 if (mode == TDmode && (cum->fregno % 2) == 1)
8563 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
8564 <= FP_ARG_V4_MAX_REG)
8565 return gen_rtx_REG (mode, cum->fregno);
8571 int n_words = rs6000_arg_size (mode, type);
8572 int gregno = cum->sysv_gregno;
8574 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
8575 (r7,r8) or (r9,r10). As does any other 2 word item such
8576 as complex int due to a historical mistake. */
8578 gregno += (1 - gregno) & 1;
8580 /* Multi-reg args are not split between registers and stack. */
8581 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
8584 if (TARGET_32BIT && TARGET_POWERPC64)
8585 return rs6000_mixed_function_arg (mode, type,
8586 gregno - GP_ARG_MIN_REG);
8587 return gen_rtx_REG (mode, gregno);
8592 int align_words = rs6000_parm_start (mode, type, cum->words);
8594 /* _Decimal128 must be passed in an even/odd float register pair.
8595 This assumes that the register number is odd when fregno is odd. */
8596 if (mode == TDmode && (cum->fregno % 2) == 1)
8599 if (USE_FP_FOR_ARG_P (cum, mode, type))
8601 rtx rvec[GP_ARG_NUM_REG + 1];
8605 enum machine_mode fmode = mode;
8606 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
8608 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
8610 /* Currently, we only ever need one reg here because complex
8611 doubles are split. */
8612 gcc_assert (cum->fregno == FP_ARG_MAX_REG
8613 && (fmode == TFmode || fmode == TDmode));
8615 /* Long double or _Decimal128 split over regs and memory. */
8616 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
8619 /* Do we also need to pass this arg in the parameter save
8622 && (cum->nargs_prototype <= 0
8623 || (DEFAULT_ABI == ABI_AIX
8625 && align_words >= GP_ARG_NUM_REG)));
8627 if (!needs_psave && mode == fmode)
8628 return gen_rtx_REG (fmode, cum->fregno);
8633 /* Describe the part that goes in gprs or the stack.
8634 This piece must come first, before the fprs. */
8635 if (align_words < GP_ARG_NUM_REG)
8637 unsigned long n_words = rs6000_arg_size (mode, type);
8639 if (align_words + n_words > GP_ARG_NUM_REG
8640 || (TARGET_32BIT && TARGET_POWERPC64))
8642 /* If this is partially on the stack, then we only
8643 include the portion actually in registers here. */
8644 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
8647 if (align_words + n_words > GP_ARG_NUM_REG)
8648 /* Not all of the arg fits in gprs. Say that it
8649 goes in memory too, using a magic NULL_RTX
8650 component. Also see comment in
8651 rs6000_mixed_function_arg for why the normal
8652 function_arg_partial_nregs scheme doesn't work
8654 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
8658 r = gen_rtx_REG (rmode,
8659 GP_ARG_MIN_REG + align_words);
8660 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
8661 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
8663 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
8667 /* The whole arg fits in gprs. */
8668 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8669 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
8673 /* It's entirely in memory. */
8674 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8677 /* Describe where this piece goes in the fprs. */
8678 r = gen_rtx_REG (fmode, cum->fregno);
8679 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
8681 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
8683 else if (align_words < GP_ARG_NUM_REG)
8685 if (TARGET_32BIT && TARGET_POWERPC64)
8686 return rs6000_mixed_function_arg (mode, type, align_words);
8688 if (mode == BLKmode)
8691 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8698 /* For an arg passed partly in registers and partly in memory, this is
8699 the number of bytes passed in registers. For args passed entirely in
8700 registers or entirely in memory, zero. When an arg is described by a
8701 PARALLEL, perhaps using more than one register type, this function
8702 returns the number of bytes used by the first element of the PARALLEL. */
8705 rs6000_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
8706 tree type, bool named)
8708 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8712 if (DEFAULT_ABI == ABI_V4)
8715 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
8716 && cum->nargs_prototype >= 0)
8719 /* In this complicated case we just disable the partial_nregs code. */
8720 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
8723 align_words = rs6000_parm_start (mode, type, cum->words);
8725 if (USE_FP_FOR_ARG_P (cum, mode, type))
8727 /* If we are passing this arg in the fixed parameter save area
8728 (gprs or memory) as well as fprs, then this function should
8729 return the number of partial bytes passed in the parameter
8730 save area rather than partial bytes passed in fprs. */
8732 && (cum->nargs_prototype <= 0
8733 || (DEFAULT_ABI == ABI_AIX
8735 && align_words >= GP_ARG_NUM_REG)))
8737 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
8738 > FP_ARG_MAX_REG + 1)
8739 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
8740 else if (cum->nargs_prototype >= 0)
8744 if (align_words < GP_ARG_NUM_REG
8745 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
8746 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
8748 if (ret != 0 && TARGET_DEBUG_ARG)
8749 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
8754 /* A C expression that indicates when an argument must be passed by
8755 reference. If nonzero for an argument, a copy of that argument is
8756 made in memory and a pointer to the argument is passed instead of
8757 the argument itself. The pointer is passed in whatever way is
8758 appropriate for passing a pointer to that type.
8760 Under V.4, aggregates and long double are passed by reference.
8762 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
8763 reference unless the AltiVec vector extension ABI is in force.
8765 As an extension to all ABIs, variable sized types are passed by
8769 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
8770 enum machine_mode mode, const_tree type,
8771 bool named ATTRIBUTE_UNUSED)
8773 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
8775 if (TARGET_DEBUG_ARG)
8776 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
8783 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
8785 if (TARGET_DEBUG_ARG)
8786 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
8790 if (int_size_in_bytes (type) < 0)
8792 if (TARGET_DEBUG_ARG)
8793 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
8797 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8798 modes only exist for GCC vector types if -maltivec. */
8799 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
8801 if (TARGET_DEBUG_ARG)
8802 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
8806 /* Pass synthetic vectors in memory. */
8807 if (TREE_CODE (type) == VECTOR_TYPE
8808 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
8810 static bool warned_for_pass_big_vectors = false;
8811 if (TARGET_DEBUG_ARG)
8812 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
8813 if (!warned_for_pass_big_vectors)
8815 warning (0, "GCC vector passed by reference: "
8816 "non-standard ABI extension with no compatibility guarantee");
8817 warned_for_pass_big_vectors = true;
8826 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
8829 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
8834 for (i = 0; i < nregs; i++)
8836 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
8837 if (reload_completed)
8839 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
8842 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
8843 i * GET_MODE_SIZE (reg_mode));
8846 tem = replace_equiv_address (tem, XEXP (tem, 0));
8850 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
8854 /* Perform any needed actions needed for a function that is receiving a
8855 variable number of arguments.
8859 MODE and TYPE are the mode and type of the current parameter.
8861 PRETEND_SIZE is a variable that should be set to the amount of stack
8862 that must be pushed by the prolog to pretend that our caller pushed
8865 Normally, this macro will push all remaining incoming registers on the
8866 stack and set PRETEND_SIZE to the length of the registers pushed. */
8869 setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
8870 tree type, int *pretend_size ATTRIBUTE_UNUSED,
8873 CUMULATIVE_ARGS next_cum;
8874 int reg_size = TARGET_32BIT ? 4 : 8;
8875 rtx save_area = NULL_RTX, mem;
8876 int first_reg_offset;
8879 /* Skip the last named argument. */
8880 next_cum = *get_cumulative_args (cum);
8881 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
8883 if (DEFAULT_ABI == ABI_V4)
8885 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
8889 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
8890 HOST_WIDE_INT offset = 0;
8892 /* Try to optimize the size of the varargs save area.
8893 The ABI requires that ap.reg_save_area is doubleword
8894 aligned, but we don't need to allocate space for all
8895 the bytes, only those to which we actually will save
8897 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
8898 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
8899 if (TARGET_HARD_FLOAT && TARGET_FPRS
8900 && next_cum.fregno <= FP_ARG_V4_MAX_REG
8901 && cfun->va_list_fpr_size)
8904 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
8905 * UNITS_PER_FP_WORD;
8906 if (cfun->va_list_fpr_size
8907 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
8908 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
8910 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
8911 * UNITS_PER_FP_WORD;
8915 offset = -((first_reg_offset * reg_size) & ~7);
8916 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
8918 gpr_reg_num = cfun->va_list_gpr_size;
8919 if (reg_size == 4 && (first_reg_offset & 1))
8922 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
8925 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
8927 - (int) (GP_ARG_NUM_REG * reg_size);
8929 if (gpr_size + fpr_size)
8932 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
8933 gcc_assert (GET_CODE (reg_save_area) == MEM);
8934 reg_save_area = XEXP (reg_save_area, 0);
8935 if (GET_CODE (reg_save_area) == PLUS)
8937 gcc_assert (XEXP (reg_save_area, 0)
8938 == virtual_stack_vars_rtx);
8939 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
8940 offset += INTVAL (XEXP (reg_save_area, 1));
8943 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
8946 cfun->machine->varargs_save_offset = offset;
8947 save_area = plus_constant (virtual_stack_vars_rtx, offset);
8952 first_reg_offset = next_cum.words;
8953 save_area = virtual_incoming_args_rtx;
8955 if (targetm.calls.must_pass_in_stack (mode, type))
8956 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
8959 set = get_varargs_alias_set ();
8960 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
8961 && cfun->va_list_gpr_size)
8963 int nregs = GP_ARG_NUM_REG - first_reg_offset;
8965 if (va_list_gpr_counter_field)
8967 /* V4 va_list_gpr_size counts number of registers needed. */
8968 if (nregs > cfun->va_list_gpr_size)
8969 nregs = cfun->va_list_gpr_size;
8973 /* char * va_list instead counts number of bytes needed. */
8974 if (nregs > cfun->va_list_gpr_size / reg_size)
8975 nregs = cfun->va_list_gpr_size / reg_size;
8978 mem = gen_rtx_MEM (BLKmode,
8979 plus_constant (save_area,
8980 first_reg_offset * reg_size));
8981 MEM_NOTRAP_P (mem) = 1;
8982 set_mem_alias_set (mem, set);
8983 set_mem_align (mem, BITS_PER_WORD);
8985 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
8989 /* Save FP registers if needed. */
8990 if (DEFAULT_ABI == ABI_V4
8991 && TARGET_HARD_FLOAT && TARGET_FPRS
8993 && next_cum.fregno <= FP_ARG_V4_MAX_REG
8994 && cfun->va_list_fpr_size)
8996 int fregno = next_cum.fregno, nregs;
8997 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
8998 rtx lab = gen_label_rtx ();
8999 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
9000 * UNITS_PER_FP_WORD);
9003 (gen_rtx_SET (VOIDmode,
9005 gen_rtx_IF_THEN_ELSE (VOIDmode,
9006 gen_rtx_NE (VOIDmode, cr1,
9008 gen_rtx_LABEL_REF (VOIDmode, lab),
9012 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
9013 fregno++, off += UNITS_PER_FP_WORD, nregs++)
9015 mem = gen_rtx_MEM ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
9017 plus_constant (save_area, off));
9018 MEM_NOTRAP_P (mem) = 1;
9019 set_mem_alias_set (mem, set);
9020 set_mem_align (mem, GET_MODE_ALIGNMENT (
9021 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
9022 ? DFmode : SFmode));
9023 emit_move_insn (mem, gen_rtx_REG (
9024 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
9025 ? DFmode : SFmode, fregno));
9032 /* Create the va_list data type. */
9035 rs6000_build_builtin_va_list (void)
9037 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
9039 /* For AIX, prefer 'char *' because that's what the system
9040 header files like. */
9041 if (DEFAULT_ABI != ABI_V4)
9042 return build_pointer_type (char_type_node);
9044 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
9045 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
9046 get_identifier ("__va_list_tag"), record);
9048 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
9049 unsigned_char_type_node);
9050 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
9051 unsigned_char_type_node);
9052 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
9054 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
9055 get_identifier ("reserved"), short_unsigned_type_node);
9056 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
9057 get_identifier ("overflow_arg_area"),
9059 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
9060 get_identifier ("reg_save_area"),
9063 va_list_gpr_counter_field = f_gpr;
9064 va_list_fpr_counter_field = f_fpr;
9066 DECL_FIELD_CONTEXT (f_gpr) = record;
9067 DECL_FIELD_CONTEXT (f_fpr) = record;
9068 DECL_FIELD_CONTEXT (f_res) = record;
9069 DECL_FIELD_CONTEXT (f_ovf) = record;
9070 DECL_FIELD_CONTEXT (f_sav) = record;
9072 TYPE_STUB_DECL (record) = type_decl;
9073 TYPE_NAME (record) = type_decl;
9074 TYPE_FIELDS (record) = f_gpr;
9075 DECL_CHAIN (f_gpr) = f_fpr;
9076 DECL_CHAIN (f_fpr) = f_res;
9077 DECL_CHAIN (f_res) = f_ovf;
9078 DECL_CHAIN (f_ovf) = f_sav;
9080 layout_type (record);
9082 /* The correct type is an array type of one element. */
9083 return build_array_type (record, build_index_type (size_zero_node));
9086 /* Implement va_start. */
9089 rs6000_va_start (tree valist, rtx nextarg)
9091 HOST_WIDE_INT words, n_gpr, n_fpr;
9092 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
9093 tree gpr, fpr, ovf, sav, t;
9095 /* Only SVR4 needs something special. */
9096 if (DEFAULT_ABI != ABI_V4)
9098 std_expand_builtin_va_start (valist, nextarg);
9102 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9103 f_fpr = DECL_CHAIN (f_gpr);
9104 f_res = DECL_CHAIN (f_fpr);
9105 f_ovf = DECL_CHAIN (f_res);
9106 f_sav = DECL_CHAIN (f_ovf);
9108 valist = build_simple_mem_ref (valist);
9109 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9110 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
9112 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
9114 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
9117 /* Count number of gp and fp argument registers used. */
9118 words = crtl->args.info.words;
9119 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
9121 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
9124 if (TARGET_DEBUG_ARG)
9125 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
9126 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
9127 words, n_gpr, n_fpr);
9129 if (cfun->va_list_gpr_size)
9131 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
9132 build_int_cst (NULL_TREE, n_gpr));
9133 TREE_SIDE_EFFECTS (t) = 1;
9134 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9137 if (cfun->va_list_fpr_size)
9139 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
9140 build_int_cst (NULL_TREE, n_fpr));
9141 TREE_SIDE_EFFECTS (t) = 1;
9142 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9144 #ifdef HAVE_AS_GNU_ATTRIBUTE
9145 if (call_ABI_of_interest (cfun->decl))
9146 rs6000_passes_float = true;
9150 /* Find the overflow area. */
9151 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
9153 t = fold_build_pointer_plus_hwi (t, words * UNITS_PER_WORD);
9154 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
9155 TREE_SIDE_EFFECTS (t) = 1;
9156 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9158 /* If there were no va_arg invocations, don't set up the register
9160 if (!cfun->va_list_gpr_size
9161 && !cfun->va_list_fpr_size
9162 && n_gpr < GP_ARG_NUM_REG
9163 && n_fpr < FP_ARG_V4_MAX_REG)
9166 /* Find the register save area. */
9167 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
9168 if (cfun->machine->varargs_save_offset)
9169 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
9170 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
9171 TREE_SIDE_EFFECTS (t) = 1;
9172 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9175 /* Implement va_arg. */
9178 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
9181 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
9182 tree gpr, fpr, ovf, sav, reg, t, u;
9183 int size, rsize, n_reg, sav_ofs, sav_scale;
9184 tree lab_false, lab_over, addr;
9186 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
9190 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
9192 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
9193 return build_va_arg_indirect_ref (t);
9196 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
9197 earlier version of gcc, with the property that it always applied alignment
9198 adjustments to the va-args (even for zero-sized types). The cheapest way
9199 to deal with this is to replicate the effect of the part of
9200 std_gimplify_va_arg_expr that carries out the align adjust, for the case
9202 We don't need to check for pass-by-reference because of the test above.
9203 We can return a simplifed answer, since we know there's no offset to add. */
9206 && rs6000_darwin64_abi
9207 && integer_zerop (TYPE_SIZE (type)))
9209 unsigned HOST_WIDE_INT align, boundary;
9210 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
9211 align = PARM_BOUNDARY / BITS_PER_UNIT;
9212 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
9213 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
9214 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
9215 boundary /= BITS_PER_UNIT;
9216 if (boundary > align)
9219 /* This updates arg ptr by the amount that would be necessary
9220 to align the zero-sized (but not zero-alignment) item. */
9221 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
9222 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
9223 gimplify_and_add (t, pre_p);
9225 t = fold_convert (sizetype, valist_tmp);
9226 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
9227 fold_convert (TREE_TYPE (valist),
9228 fold_build2 (BIT_AND_EXPR, sizetype, t,
9229 size_int (-boundary))));
9230 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
9231 gimplify_and_add (t, pre_p);
9233 /* Since it is zero-sized there's no increment for the item itself. */
9234 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
9235 return build_va_arg_indirect_ref (valist_tmp);
9238 if (DEFAULT_ABI != ABI_V4)
9240 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
9242 tree elem_type = TREE_TYPE (type);
9243 enum machine_mode elem_mode = TYPE_MODE (elem_type);
9244 int elem_size = GET_MODE_SIZE (elem_mode);
9246 if (elem_size < UNITS_PER_WORD)
9248 tree real_part, imag_part;
9249 gimple_seq post = NULL;
9251 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
9253 /* Copy the value into a temporary, lest the formal temporary
9254 be reused out from under us. */
9255 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
9256 gimple_seq_add_seq (pre_p, post);
9258 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
9261 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
9265 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
9268 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9269 f_fpr = DECL_CHAIN (f_gpr);
9270 f_res = DECL_CHAIN (f_fpr);
9271 f_ovf = DECL_CHAIN (f_res);
9272 f_sav = DECL_CHAIN (f_ovf);
9274 valist = build_va_arg_indirect_ref (valist);
9275 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9276 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
9278 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
9280 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
9283 size = int_size_in_bytes (type);
9284 rsize = (size + 3) / 4;
9287 if (TARGET_HARD_FLOAT && TARGET_FPRS
9288 && ((TARGET_SINGLE_FLOAT && TYPE_MODE (type) == SFmode)
9289 || (TARGET_DOUBLE_FLOAT
9290 && (TYPE_MODE (type) == DFmode
9291 || TYPE_MODE (type) == TFmode
9292 || TYPE_MODE (type) == SDmode
9293 || TYPE_MODE (type) == DDmode
9294 || TYPE_MODE (type) == TDmode))))
9296 /* FP args go in FP registers, if present. */
9298 n_reg = (size + 7) / 8;
9299 sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
9300 sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
9301 if (TYPE_MODE (type) != SFmode && TYPE_MODE (type) != SDmode)
9306 /* Otherwise into GP registers. */
9315 /* Pull the value out of the saved registers.... */
9318 addr = create_tmp_var (ptr_type_node, "addr");
9320 /* AltiVec vectors never go in registers when -mabi=altivec. */
9321 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
9325 lab_false = create_artificial_label (input_location);
9326 lab_over = create_artificial_label (input_location);
9328 /* Long long and SPE vectors are aligned in the registers.
9329 As are any other 2 gpr item such as complex int due to a
9330 historical mistake. */
9332 if (n_reg == 2 && reg == gpr)
9335 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9336 build_int_cst (TREE_TYPE (reg), n_reg - 1));
9337 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
9338 unshare_expr (reg), u);
9340 /* _Decimal128 is passed in even/odd fpr pairs; the stored
9341 reg number is 0 for f1, so we want to make it odd. */
9342 else if (reg == fpr && TYPE_MODE (type) == TDmode)
9344 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9345 build_int_cst (TREE_TYPE (reg), 1));
9346 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
9349 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
9350 t = build2 (GE_EXPR, boolean_type_node, u, t);
9351 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9352 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9353 gimplify_and_add (t, pre_p);
9357 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9359 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9360 build_int_cst (TREE_TYPE (reg), n_reg));
9361 u = fold_convert (sizetype, u);
9362 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
9363 t = fold_build_pointer_plus (t, u);
9365 /* _Decimal32 varargs are located in the second word of the 64-bit
9366 FP register for 32-bit binaries. */
9367 if (!TARGET_POWERPC64
9368 && TARGET_HARD_FLOAT && TARGET_FPRS
9369 && TYPE_MODE (type) == SDmode)
9370 t = fold_build_pointer_plus_hwi (t, size);
9372 gimplify_assign (addr, t, pre_p);
9374 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9376 stmt = gimple_build_label (lab_false);
9377 gimple_seq_add_stmt (pre_p, stmt);
9379 if ((n_reg == 2 && !regalign) || n_reg > 2)
9381 /* Ensure that we don't find any more args in regs.
9382 Alignment has taken care of for special cases. */
9383 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
9387 /* ... otherwise out of the overflow area. */
9389 /* Care for on-stack alignment if needed. */
9393 t = fold_build_pointer_plus_hwi (t, align - 1);
9394 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
9395 build_int_cst (TREE_TYPE (t), -align));
9397 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9399 gimplify_assign (unshare_expr (addr), t, pre_p);
9401 t = fold_build_pointer_plus_hwi (t, size);
9402 gimplify_assign (unshare_expr (ovf), t, pre_p);
9406 stmt = gimple_build_label (lab_over);
9407 gimple_seq_add_stmt (pre_p, stmt);
9410 if (STRICT_ALIGNMENT
9411 && (TYPE_ALIGN (type)
9412 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
9414 /* The value (of type complex double, for example) may not be
9415 aligned in memory in the saved registers, so copy via a
9416 temporary. (This is the same code as used for SPARC.) */
9417 tree tmp = create_tmp_var (type, "va_arg_tmp");
9418 tree dest_addr = build_fold_addr_expr (tmp);
9420 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
9421 3, dest_addr, addr, size_int (rsize * 4));
9423 gimplify_and_add (copy, pre_p);
9427 addr = fold_convert (ptrtype, addr);
9428 return build_va_arg_indirect_ref (addr);
9434 def_builtin (const char *name, tree type, enum rs6000_builtins code)
9437 unsigned classify = rs6000_builtin_info[(int)code].attr;
9438 const char *attr_string = "";
9440 gcc_assert (name != NULL);
9441 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
9443 if (rs6000_builtin_decls[(int)code])
9444 fatal_error ("internal error: builtin function %s already processed", name);
9446 rs6000_builtin_decls[(int)code] = t =
9447 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
9449 /* Set any special attributes. */
9450 if ((classify & RS6000_BTC_CONST) != 0)
9452 /* const function, function only depends on the inputs. */
9453 TREE_READONLY (t) = 1;
9454 TREE_NOTHROW (t) = 1;
9455 attr_string = ", pure";
9457 else if ((classify & RS6000_BTC_PURE) != 0)
9459 /* pure function, function can read global memory, but does not set any
9461 DECL_PURE_P (t) = 1;
9462 TREE_NOTHROW (t) = 1;
9463 attr_string = ", const";
9465 else if ((classify & RS6000_BTC_FP) != 0)
9467 /* Function is a math function. If rounding mode is on, then treat the
9468 function as not reading global memory, but it can have arbitrary side
9469 effects. If it is off, then assume the function is a const function.
9470 This mimics the ATTR_MATHFN_FPROUNDING attribute in
9471 builtin-attribute.def that is used for the math functions. */
9472 TREE_NOTHROW (t) = 1;
9473 if (flag_rounding_math)
9475 DECL_PURE_P (t) = 1;
9476 DECL_IS_NOVOPS (t) = 1;
9477 attr_string = ", fp, pure";
9481 TREE_READONLY (t) = 1;
9482 attr_string = ", fp, const";
9485 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
9488 if (TARGET_DEBUG_BUILTIN)
9489 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
9490 (int)code, name, attr_string);
9493 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
9495 #undef RS6000_BUILTIN_1
9496 #undef RS6000_BUILTIN_2
9497 #undef RS6000_BUILTIN_3
9498 #undef RS6000_BUILTIN_A
9499 #undef RS6000_BUILTIN_D
9500 #undef RS6000_BUILTIN_E
9501 #undef RS6000_BUILTIN_P
9502 #undef RS6000_BUILTIN_Q
9503 #undef RS6000_BUILTIN_S
9504 #undef RS6000_BUILTIN_X
9506 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9507 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9508 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
9509 { MASK, ICODE, NAME, ENUM },
9511 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9512 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9513 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9514 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9515 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9516 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9517 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9519 static const struct builtin_description bdesc_3arg[] =
9521 #include "rs6000-builtin.def"
9524 /* DST operations: void foo (void *, const int, const char). */
9526 #undef RS6000_BUILTIN_1
9527 #undef RS6000_BUILTIN_2
9528 #undef RS6000_BUILTIN_3
9529 #undef RS6000_BUILTIN_A
9530 #undef RS6000_BUILTIN_D
9531 #undef RS6000_BUILTIN_E
9532 #undef RS6000_BUILTIN_P
9533 #undef RS6000_BUILTIN_Q
9534 #undef RS6000_BUILTIN_S
9535 #undef RS6000_BUILTIN_X
9537 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9538 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9539 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9540 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9541 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
9542 { MASK, ICODE, NAME, ENUM },
9544 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9545 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9546 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9547 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9548 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9550 static const struct builtin_description bdesc_dst[] =
9552 #include "rs6000-builtin.def"
9555 /* Simple binary operations: VECc = foo (VECa, VECb). */
9557 #undef RS6000_BUILTIN_1
9558 #undef RS6000_BUILTIN_2
9559 #undef RS6000_BUILTIN_3
9560 #undef RS6000_BUILTIN_A
9561 #undef RS6000_BUILTIN_D
9562 #undef RS6000_BUILTIN_E
9563 #undef RS6000_BUILTIN_P
9564 #undef RS6000_BUILTIN_Q
9565 #undef RS6000_BUILTIN_S
9566 #undef RS6000_BUILTIN_X
9568 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9569 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
9570 { MASK, ICODE, NAME, ENUM },
9572 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9573 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9574 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9575 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9576 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9577 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9578 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9579 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9581 static const struct builtin_description bdesc_2arg[] =
9583 #include "rs6000-builtin.def"
9586 #undef RS6000_BUILTIN_1
9587 #undef RS6000_BUILTIN_2
9588 #undef RS6000_BUILTIN_3
9589 #undef RS6000_BUILTIN_A
9590 #undef RS6000_BUILTIN_D
9591 #undef RS6000_BUILTIN_E
9592 #undef RS6000_BUILTIN_P
9593 #undef RS6000_BUILTIN_Q
9594 #undef RS6000_BUILTIN_S
9595 #undef RS6000_BUILTIN_X
9597 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9598 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9599 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9600 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9601 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9602 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9603 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
9604 { MASK, ICODE, NAME, ENUM },
9606 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9607 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9608 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9610 /* AltiVec predicates. */
9612 static const struct builtin_description bdesc_altivec_preds[] =
9614 #include "rs6000-builtin.def"
9617 /* SPE predicates. */
9618 #undef RS6000_BUILTIN_1
9619 #undef RS6000_BUILTIN_2
9620 #undef RS6000_BUILTIN_3
9621 #undef RS6000_BUILTIN_A
9622 #undef RS6000_BUILTIN_D
9623 #undef RS6000_BUILTIN_E
9624 #undef RS6000_BUILTIN_P
9625 #undef RS6000_BUILTIN_Q
9626 #undef RS6000_BUILTIN_S
9627 #undef RS6000_BUILTIN_X
9629 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9630 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9631 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9632 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9633 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9634 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9635 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9636 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9637 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
9638 { MASK, ICODE, NAME, ENUM },
9640 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9642 static const struct builtin_description bdesc_spe_predicates[] =
9644 #include "rs6000-builtin.def"
9647 /* SPE evsel predicates. */
9648 #undef RS6000_BUILTIN_1
9649 #undef RS6000_BUILTIN_2
9650 #undef RS6000_BUILTIN_3
9651 #undef RS6000_BUILTIN_A
9652 #undef RS6000_BUILTIN_D
9653 #undef RS6000_BUILTIN_E
9654 #undef RS6000_BUILTIN_P
9655 #undef RS6000_BUILTIN_Q
9656 #undef RS6000_BUILTIN_S
9657 #undef RS6000_BUILTIN_X
9659 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9660 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9661 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9662 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9663 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9664 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
9665 { MASK, ICODE, NAME, ENUM },
9667 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9668 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9669 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9670 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9672 static const struct builtin_description bdesc_spe_evsel[] =
9674 #include "rs6000-builtin.def"
9677 /* PAIRED predicates. */
9678 #undef RS6000_BUILTIN_1
9679 #undef RS6000_BUILTIN_2
9680 #undef RS6000_BUILTIN_3
9681 #undef RS6000_BUILTIN_A
9682 #undef RS6000_BUILTIN_D
9683 #undef RS6000_BUILTIN_E
9684 #undef RS6000_BUILTIN_P
9685 #undef RS6000_BUILTIN_Q
9686 #undef RS6000_BUILTIN_S
9687 #undef RS6000_BUILTIN_X
9689 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9690 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9691 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9692 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9693 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9694 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9695 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9696 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
9697 { MASK, ICODE, NAME, ENUM },
9699 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9700 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9702 static const struct builtin_description bdesc_paired_preds[] =
9704 #include "rs6000-builtin.def"
9707 /* ABS* operations. */
9709 #undef RS6000_BUILTIN_1
9710 #undef RS6000_BUILTIN_2
9711 #undef RS6000_BUILTIN_3
9712 #undef RS6000_BUILTIN_A
9713 #undef RS6000_BUILTIN_D
9714 #undef RS6000_BUILTIN_E
9715 #undef RS6000_BUILTIN_P
9716 #undef RS6000_BUILTIN_Q
9717 #undef RS6000_BUILTIN_S
9718 #undef RS6000_BUILTIN_X
9720 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9721 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9722 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9723 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
9724 { MASK, ICODE, NAME, ENUM },
9726 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9727 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9728 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9729 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9730 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9731 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9733 static const struct builtin_description bdesc_abs[] =
9735 #include "rs6000-builtin.def"
9738 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
9741 #undef RS6000_BUILTIN_1
9742 #undef RS6000_BUILTIN_2
9743 #undef RS6000_BUILTIN_3
9744 #undef RS6000_BUILTIN_A
9745 #undef RS6000_BUILTIN_E
9746 #undef RS6000_BUILTIN_D
9747 #undef RS6000_BUILTIN_P
9748 #undef RS6000_BUILTIN_Q
9749 #undef RS6000_BUILTIN_S
9750 #undef RS6000_BUILTIN_X
9752 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
9753 { MASK, ICODE, NAME, ENUM },
9755 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9756 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9757 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9758 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9759 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9760 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9761 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9762 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9763 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9765 static const struct builtin_description bdesc_1arg[] =
9767 #include "rs6000-builtin.def"
9770 #undef RS6000_BUILTIN_1
9771 #undef RS6000_BUILTIN_2
9772 #undef RS6000_BUILTIN_3
9773 #undef RS6000_BUILTIN_A
9774 #undef RS6000_BUILTIN_D
9775 #undef RS6000_BUILTIN_E
9776 #undef RS6000_BUILTIN_P
9777 #undef RS6000_BUILTIN_Q
9778 #undef RS6000_BUILTIN_S
9779 #undef RS6000_BUILTIN_X
9781 /* Return true if a builtin function is overloaded. */
9783 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
9785 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
9790 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
9793 tree arg0 = CALL_EXPR_ARG (exp, 0);
9794 rtx op0 = expand_normal (arg0);
9795 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9796 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9798 if (icode == CODE_FOR_nothing)
9799 /* Builtin not supported on this processor. */
9802 /* If we got invalid arguments bail out before generating bad rtl. */
9803 if (arg0 == error_mark_node)
9806 if (icode == CODE_FOR_altivec_vspltisb
9807 || icode == CODE_FOR_altivec_vspltish
9808 || icode == CODE_FOR_altivec_vspltisw
9809 || icode == CODE_FOR_spe_evsplatfi
9810 || icode == CODE_FOR_spe_evsplati)
9812 /* Only allow 5-bit *signed* literals. */
9813 if (GET_CODE (op0) != CONST_INT
9814 || INTVAL (op0) > 15
9815 || INTVAL (op0) < -16)
9817 error ("argument 1 must be a 5-bit signed literal");
9823 || GET_MODE (target) != tmode
9824 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9825 target = gen_reg_rtx (tmode);
9827 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9828 op0 = copy_to_mode_reg (mode0, op0);
9830 pat = GEN_FCN (icode) (target, op0);
9839 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
9841 rtx pat, scratch1, scratch2;
9842 tree arg0 = CALL_EXPR_ARG (exp, 0);
9843 rtx op0 = expand_normal (arg0);
9844 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9845 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9847 /* If we have invalid arguments, bail out before generating bad rtl. */
9848 if (arg0 == error_mark_node)
9852 || GET_MODE (target) != tmode
9853 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9854 target = gen_reg_rtx (tmode);
9856 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9857 op0 = copy_to_mode_reg (mode0, op0);
9859 scratch1 = gen_reg_rtx (mode0);
9860 scratch2 = gen_reg_rtx (mode0);
9862 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
9871 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
9874 tree arg0 = CALL_EXPR_ARG (exp, 0);
9875 tree arg1 = CALL_EXPR_ARG (exp, 1);
9876 rtx op0 = expand_normal (arg0);
9877 rtx op1 = expand_normal (arg1);
9878 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9879 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9880 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
9882 if (icode == CODE_FOR_nothing)
9883 /* Builtin not supported on this processor. */
9886 /* If we got invalid arguments bail out before generating bad rtl. */
9887 if (arg0 == error_mark_node || arg1 == error_mark_node)
9890 if (icode == CODE_FOR_altivec_vcfux
9891 || icode == CODE_FOR_altivec_vcfsx
9892 || icode == CODE_FOR_altivec_vctsxs
9893 || icode == CODE_FOR_altivec_vctuxs
9894 || icode == CODE_FOR_altivec_vspltb
9895 || icode == CODE_FOR_altivec_vsplth
9896 || icode == CODE_FOR_altivec_vspltw
9897 || icode == CODE_FOR_spe_evaddiw
9898 || icode == CODE_FOR_spe_evldd
9899 || icode == CODE_FOR_spe_evldh
9900 || icode == CODE_FOR_spe_evldw
9901 || icode == CODE_FOR_spe_evlhhesplat
9902 || icode == CODE_FOR_spe_evlhhossplat
9903 || icode == CODE_FOR_spe_evlhhousplat
9904 || icode == CODE_FOR_spe_evlwhe
9905 || icode == CODE_FOR_spe_evlwhos
9906 || icode == CODE_FOR_spe_evlwhou
9907 || icode == CODE_FOR_spe_evlwhsplat
9908 || icode == CODE_FOR_spe_evlwwsplat
9909 || icode == CODE_FOR_spe_evrlwi
9910 || icode == CODE_FOR_spe_evslwi
9911 || icode == CODE_FOR_spe_evsrwis
9912 || icode == CODE_FOR_spe_evsubifw
9913 || icode == CODE_FOR_spe_evsrwiu)
9915 /* Only allow 5-bit unsigned literals. */
9917 if (TREE_CODE (arg1) != INTEGER_CST
9918 || TREE_INT_CST_LOW (arg1) & ~0x1f)
9920 error ("argument 2 must be a 5-bit unsigned literal");
9926 || GET_MODE (target) != tmode
9927 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9928 target = gen_reg_rtx (tmode);
9930 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9931 op0 = copy_to_mode_reg (mode0, op0);
9932 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9933 op1 = copy_to_mode_reg (mode1, op1);
9935 pat = GEN_FCN (icode) (target, op0, op1);
9944 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
9947 tree cr6_form = CALL_EXPR_ARG (exp, 0);
9948 tree arg0 = CALL_EXPR_ARG (exp, 1);
9949 tree arg1 = CALL_EXPR_ARG (exp, 2);
9950 rtx op0 = expand_normal (arg0);
9951 rtx op1 = expand_normal (arg1);
9952 enum machine_mode tmode = SImode;
9953 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9954 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
9957 if (TREE_CODE (cr6_form) != INTEGER_CST)
9959 error ("argument 1 of __builtin_altivec_predicate must be a constant");
9963 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
9965 gcc_assert (mode0 == mode1);
9967 /* If we have invalid arguments, bail out before generating bad rtl. */
9968 if (arg0 == error_mark_node || arg1 == error_mark_node)
9972 || GET_MODE (target) != tmode
9973 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9974 target = gen_reg_rtx (tmode);
9976 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9977 op0 = copy_to_mode_reg (mode0, op0);
9978 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9979 op1 = copy_to_mode_reg (mode1, op1);
9981 scratch = gen_reg_rtx (mode0);
9983 pat = GEN_FCN (icode) (scratch, op0, op1);
9988 /* The vec_any* and vec_all* predicates use the same opcodes for two
9989 different operations, but the bits in CR6 will be different
9990 depending on what information we want. So we have to play tricks
9991 with CR6 to get the right bits out.
9993 If you think this is disgusting, look at the specs for the
9994 AltiVec predicates. */
9996 switch (cr6_form_int)
9999 emit_insn (gen_cr6_test_for_zero (target));
10002 emit_insn (gen_cr6_test_for_zero_reverse (target));
10005 emit_insn (gen_cr6_test_for_lt (target));
10008 emit_insn (gen_cr6_test_for_lt_reverse (target));
10011 error ("argument 1 of __builtin_altivec_predicate is out of range");
10019 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
10022 tree arg0 = CALL_EXPR_ARG (exp, 0);
10023 tree arg1 = CALL_EXPR_ARG (exp, 1);
10024 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10025 enum machine_mode mode0 = Pmode;
10026 enum machine_mode mode1 = Pmode;
10027 rtx op0 = expand_normal (arg0);
10028 rtx op1 = expand_normal (arg1);
10030 if (icode == CODE_FOR_nothing)
10031 /* Builtin not supported on this processor. */
10034 /* If we got invalid arguments bail out before generating bad rtl. */
10035 if (arg0 == error_mark_node || arg1 == error_mark_node)
10039 || GET_MODE (target) != tmode
10040 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10041 target = gen_reg_rtx (tmode);
10043 op1 = copy_to_mode_reg (mode1, op1);
10045 if (op0 == const0_rtx)
10047 addr = gen_rtx_MEM (tmode, op1);
10051 op0 = copy_to_mode_reg (mode0, op0);
10052 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
10055 pat = GEN_FCN (icode) (target, addr);
10065 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
10068 tree arg0 = CALL_EXPR_ARG (exp, 0);
10069 tree arg1 = CALL_EXPR_ARG (exp, 1);
10070 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10071 enum machine_mode mode0 = Pmode;
10072 enum machine_mode mode1 = Pmode;
10073 rtx op0 = expand_normal (arg0);
10074 rtx op1 = expand_normal (arg1);
10076 if (icode == CODE_FOR_nothing)
10077 /* Builtin not supported on this processor. */
10080 /* If we got invalid arguments bail out before generating bad rtl. */
10081 if (arg0 == error_mark_node || arg1 == error_mark_node)
10085 || GET_MODE (target) != tmode
10086 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10087 target = gen_reg_rtx (tmode);
10089 op1 = copy_to_mode_reg (mode1, op1);
10091 if (op0 == const0_rtx)
10093 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
10097 op0 = copy_to_mode_reg (mode0, op0);
10098 addr = gen_rtx_MEM (blk ? BLKmode : tmode, gen_rtx_PLUS (Pmode, op0, op1));
10101 pat = GEN_FCN (icode) (target, addr);
10111 spe_expand_stv_builtin (enum insn_code icode, tree exp)
10113 tree arg0 = CALL_EXPR_ARG (exp, 0);
10114 tree arg1 = CALL_EXPR_ARG (exp, 1);
10115 tree arg2 = CALL_EXPR_ARG (exp, 2);
10116 rtx op0 = expand_normal (arg0);
10117 rtx op1 = expand_normal (arg1);
10118 rtx op2 = expand_normal (arg2);
10120 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
10121 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
10122 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
10124 /* Invalid arguments. Bail before doing anything stoopid! */
10125 if (arg0 == error_mark_node
10126 || arg1 == error_mark_node
10127 || arg2 == error_mark_node)
10130 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
10131 op0 = copy_to_mode_reg (mode2, op0);
10132 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
10133 op1 = copy_to_mode_reg (mode0, op1);
10134 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
10135 op2 = copy_to_mode_reg (mode1, op2);
10137 pat = GEN_FCN (icode) (op1, op2, op0);
10144 paired_expand_stv_builtin (enum insn_code icode, tree exp)
10146 tree arg0 = CALL_EXPR_ARG (exp, 0);
10147 tree arg1 = CALL_EXPR_ARG (exp, 1);
10148 tree arg2 = CALL_EXPR_ARG (exp, 2);
10149 rtx op0 = expand_normal (arg0);
10150 rtx op1 = expand_normal (arg1);
10151 rtx op2 = expand_normal (arg2);
10153 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10154 enum machine_mode mode1 = Pmode;
10155 enum machine_mode mode2 = Pmode;
10157 /* Invalid arguments. Bail before doing anything stoopid! */
10158 if (arg0 == error_mark_node
10159 || arg1 == error_mark_node
10160 || arg2 == error_mark_node)
10163 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
10164 op0 = copy_to_mode_reg (tmode, op0);
10166 op2 = copy_to_mode_reg (mode2, op2);
10168 if (op1 == const0_rtx)
10170 addr = gen_rtx_MEM (tmode, op2);
10174 op1 = copy_to_mode_reg (mode1, op1);
10175 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
10178 pat = GEN_FCN (icode) (addr, op0);
10185 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
10187 tree arg0 = CALL_EXPR_ARG (exp, 0);
10188 tree arg1 = CALL_EXPR_ARG (exp, 1);
10189 tree arg2 = CALL_EXPR_ARG (exp, 2);
10190 rtx op0 = expand_normal (arg0);
10191 rtx op1 = expand_normal (arg1);
10192 rtx op2 = expand_normal (arg2);
10194 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10195 enum machine_mode smode = insn_data[icode].operand[1].mode;
10196 enum machine_mode mode1 = Pmode;
10197 enum machine_mode mode2 = Pmode;
10199 /* Invalid arguments. Bail before doing anything stoopid! */
10200 if (arg0 == error_mark_node
10201 || arg1 == error_mark_node
10202 || arg2 == error_mark_node)
10205 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
10206 op0 = copy_to_mode_reg (smode, op0);
10208 op2 = copy_to_mode_reg (mode2, op2);
10210 if (op1 == const0_rtx)
10212 addr = gen_rtx_MEM (tmode, op2);
10216 op1 = copy_to_mode_reg (mode1, op1);
10217 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
10220 pat = GEN_FCN (icode) (addr, op0);
10227 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
10230 tree arg0 = CALL_EXPR_ARG (exp, 0);
10231 tree arg1 = CALL_EXPR_ARG (exp, 1);
10232 tree arg2 = CALL_EXPR_ARG (exp, 2);
10233 rtx op0 = expand_normal (arg0);
10234 rtx op1 = expand_normal (arg1);
10235 rtx op2 = expand_normal (arg2);
10236 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10237 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
10238 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
10239 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
10241 if (icode == CODE_FOR_nothing)
10242 /* Builtin not supported on this processor. */
10245 /* If we got invalid arguments bail out before generating bad rtl. */
10246 if (arg0 == error_mark_node
10247 || arg1 == error_mark_node
10248 || arg2 == error_mark_node)
10251 /* Check and prepare argument depending on the instruction code.
10253 Note that a switch statement instead of the sequence of tests
10254 would be incorrect as many of the CODE_FOR values could be
10255 CODE_FOR_nothing and that would yield multiple alternatives
10256 with identical values. We'd never reach here at runtime in
10258 if (icode == CODE_FOR_altivec_vsldoi_v4sf
10259 || icode == CODE_FOR_altivec_vsldoi_v4si
10260 || icode == CODE_FOR_altivec_vsldoi_v8hi
10261 || icode == CODE_FOR_altivec_vsldoi_v16qi)
10263 /* Only allow 4-bit unsigned literals. */
10265 if (TREE_CODE (arg2) != INTEGER_CST
10266 || TREE_INT_CST_LOW (arg2) & ~0xf)
10268 error ("argument 3 must be a 4-bit unsigned literal");
10272 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
10273 || icode == CODE_FOR_vsx_xxpermdi_v2di
10274 || icode == CODE_FOR_vsx_xxsldwi_v16qi
10275 || icode == CODE_FOR_vsx_xxsldwi_v8hi
10276 || icode == CODE_FOR_vsx_xxsldwi_v4si
10277 || icode == CODE_FOR_vsx_xxsldwi_v4sf
10278 || icode == CODE_FOR_vsx_xxsldwi_v2di
10279 || icode == CODE_FOR_vsx_xxsldwi_v2df)
10281 /* Only allow 2-bit unsigned literals. */
10283 if (TREE_CODE (arg2) != INTEGER_CST
10284 || TREE_INT_CST_LOW (arg2) & ~0x3)
10286 error ("argument 3 must be a 2-bit unsigned literal");
10290 else if (icode == CODE_FOR_vsx_set_v2df
10291 || icode == CODE_FOR_vsx_set_v2di)
10293 /* Only allow 1-bit unsigned literals. */
10295 if (TREE_CODE (arg2) != INTEGER_CST
10296 || TREE_INT_CST_LOW (arg2) & ~0x1)
10298 error ("argument 3 must be a 1-bit unsigned literal");
10304 || GET_MODE (target) != tmode
10305 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10306 target = gen_reg_rtx (tmode);
10308 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10309 op0 = copy_to_mode_reg (mode0, op0);
10310 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10311 op1 = copy_to_mode_reg (mode1, op1);
10312 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
10313 op2 = copy_to_mode_reg (mode2, op2);
10315 if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
10316 pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
10318 pat = GEN_FCN (icode) (target, op0, op1, op2);
10326 /* Expand the lvx builtins. */
10328 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
10330 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10331 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10333 enum machine_mode tmode, mode0;
10335 enum insn_code icode;
10339 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
10340 icode = CODE_FOR_vector_altivec_load_v16qi;
10342 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
10343 icode = CODE_FOR_vector_altivec_load_v8hi;
10345 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
10346 icode = CODE_FOR_vector_altivec_load_v4si;
10348 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
10349 icode = CODE_FOR_vector_altivec_load_v4sf;
10351 case ALTIVEC_BUILTIN_LD_INTERNAL_2df:
10352 icode = CODE_FOR_vector_altivec_load_v2df;
10354 case ALTIVEC_BUILTIN_LD_INTERNAL_2di:
10355 icode = CODE_FOR_vector_altivec_load_v2di;
10358 *expandedp = false;
10364 arg0 = CALL_EXPR_ARG (exp, 0);
10365 op0 = expand_normal (arg0);
10366 tmode = insn_data[icode].operand[0].mode;
10367 mode0 = insn_data[icode].operand[1].mode;
10370 || GET_MODE (target) != tmode
10371 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10372 target = gen_reg_rtx (tmode);
10374 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10375 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
10377 pat = GEN_FCN (icode) (target, op0);
10384 /* Expand the stvx builtins. */
10386 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
10389 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10390 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10392 enum machine_mode mode0, mode1;
10394 enum insn_code icode;
10398 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
10399 icode = CODE_FOR_vector_altivec_store_v16qi;
10401 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
10402 icode = CODE_FOR_vector_altivec_store_v8hi;
10404 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
10405 icode = CODE_FOR_vector_altivec_store_v4si;
10407 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
10408 icode = CODE_FOR_vector_altivec_store_v4sf;
10410 case ALTIVEC_BUILTIN_ST_INTERNAL_2df:
10411 icode = CODE_FOR_vector_altivec_store_v2df;
10413 case ALTIVEC_BUILTIN_ST_INTERNAL_2di:
10414 icode = CODE_FOR_vector_altivec_store_v2di;
10417 *expandedp = false;
10421 arg0 = CALL_EXPR_ARG (exp, 0);
10422 arg1 = CALL_EXPR_ARG (exp, 1);
10423 op0 = expand_normal (arg0);
10424 op1 = expand_normal (arg1);
10425 mode0 = insn_data[icode].operand[0].mode;
10426 mode1 = insn_data[icode].operand[1].mode;
10428 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10429 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
10430 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
10431 op1 = copy_to_mode_reg (mode1, op1);
10433 pat = GEN_FCN (icode) (op0, op1);
10441 /* Expand the dst builtins. */
10443 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
10446 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10447 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10448 tree arg0, arg1, arg2;
10449 enum machine_mode mode0, mode1;
10450 rtx pat, op0, op1, op2;
10451 const struct builtin_description *d;
10454 *expandedp = false;
10456 /* Handle DST variants. */
10458 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
10459 if (d->code == fcode)
10461 arg0 = CALL_EXPR_ARG (exp, 0);
10462 arg1 = CALL_EXPR_ARG (exp, 1);
10463 arg2 = CALL_EXPR_ARG (exp, 2);
10464 op0 = expand_normal (arg0);
10465 op1 = expand_normal (arg1);
10466 op2 = expand_normal (arg2);
10467 mode0 = insn_data[d->icode].operand[0].mode;
10468 mode1 = insn_data[d->icode].operand[1].mode;
10470 /* Invalid arguments, bail out before generating bad rtl. */
10471 if (arg0 == error_mark_node
10472 || arg1 == error_mark_node
10473 || arg2 == error_mark_node)
10478 if (TREE_CODE (arg2) != INTEGER_CST
10479 || TREE_INT_CST_LOW (arg2) & ~0x3)
10481 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
10485 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
10486 op0 = copy_to_mode_reg (Pmode, op0);
10487 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
10488 op1 = copy_to_mode_reg (mode1, op1);
10490 pat = GEN_FCN (d->icode) (op0, op1, op2);
10500 /* Expand vec_init builtin. */
10502 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
10504 enum machine_mode tmode = TYPE_MODE (type);
10505 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
10506 int i, n_elt = GET_MODE_NUNITS (tmode);
10507 rtvec v = rtvec_alloc (n_elt);
10509 gcc_assert (VECTOR_MODE_P (tmode));
10510 gcc_assert (n_elt == call_expr_nargs (exp));
10512 for (i = 0; i < n_elt; ++i)
10514 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
10515 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
10518 if (!target || !register_operand (target, tmode))
10519 target = gen_reg_rtx (tmode);
10521 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
10525 /* Return the integer constant in ARG. Constrain it to be in the range
10526 of the subparts of VEC_TYPE; issue an error if not. */
10529 get_element_number (tree vec_type, tree arg)
10531 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
10533 if (!host_integerp (arg, 1)
10534 || (elt = tree_low_cst (arg, 1), elt > max))
10536 error ("selector must be an integer constant in the range 0..%wi", max);
10543 /* Expand vec_set builtin. */
10545 altivec_expand_vec_set_builtin (tree exp)
10547 enum machine_mode tmode, mode1;
10548 tree arg0, arg1, arg2;
10552 arg0 = CALL_EXPR_ARG (exp, 0);
10553 arg1 = CALL_EXPR_ARG (exp, 1);
10554 arg2 = CALL_EXPR_ARG (exp, 2);
10556 tmode = TYPE_MODE (TREE_TYPE (arg0));
10557 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
10558 gcc_assert (VECTOR_MODE_P (tmode));
10560 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
10561 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
10562 elt = get_element_number (TREE_TYPE (arg0), arg2);
10564 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
10565 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
10567 op0 = force_reg (tmode, op0);
10568 op1 = force_reg (mode1, op1);
10570 rs6000_expand_vector_set (op0, op1, elt);
10575 /* Expand vec_ext builtin. */
10577 altivec_expand_vec_ext_builtin (tree exp, rtx target)
10579 enum machine_mode tmode, mode0;
10584 arg0 = CALL_EXPR_ARG (exp, 0);
10585 arg1 = CALL_EXPR_ARG (exp, 1);
10587 op0 = expand_normal (arg0);
10588 elt = get_element_number (TREE_TYPE (arg0), arg1);
10590 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
10591 mode0 = TYPE_MODE (TREE_TYPE (arg0));
10592 gcc_assert (VECTOR_MODE_P (mode0));
10594 op0 = force_reg (mode0, op0);
10596 if (optimize || !target || !register_operand (target, tmode))
10597 target = gen_reg_rtx (tmode);
10599 rs6000_expand_vector_extract (target, op0, elt);
10604 /* Expand the builtin in EXP and store the result in TARGET. Store
10605 true in *EXPANDEDP if we found a builtin to expand. */
10607 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
10609 const struct builtin_description *d;
10611 enum insn_code icode;
10612 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10615 enum machine_mode tmode, mode0;
10616 enum rs6000_builtins fcode
10617 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
10619 if (rs6000_overloaded_builtin_p (fcode))
10622 error ("unresolved overload for Altivec builtin %qF", fndecl);
10624 /* Given it is invalid, just generate a normal call. */
10625 return expand_call (exp, target, false);
10628 target = altivec_expand_ld_builtin (exp, target, expandedp);
10632 target = altivec_expand_st_builtin (exp, target, expandedp);
10636 target = altivec_expand_dst_builtin (exp, target, expandedp);
10644 case ALTIVEC_BUILTIN_STVX:
10645 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
10646 case ALTIVEC_BUILTIN_STVEBX:
10647 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
10648 case ALTIVEC_BUILTIN_STVEHX:
10649 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
10650 case ALTIVEC_BUILTIN_STVEWX:
10651 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
10652 case ALTIVEC_BUILTIN_STVXL:
10653 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
10655 case ALTIVEC_BUILTIN_STVLX:
10656 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
10657 case ALTIVEC_BUILTIN_STVLXL:
10658 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
10659 case ALTIVEC_BUILTIN_STVRX:
10660 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
10661 case ALTIVEC_BUILTIN_STVRXL:
10662 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
10664 case VSX_BUILTIN_STXVD2X_V2DF:
10665 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
10666 case VSX_BUILTIN_STXVD2X_V2DI:
10667 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
10668 case VSX_BUILTIN_STXVW4X_V4SF:
10669 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
10670 case VSX_BUILTIN_STXVW4X_V4SI:
10671 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
10672 case VSX_BUILTIN_STXVW4X_V8HI:
10673 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
10674 case VSX_BUILTIN_STXVW4X_V16QI:
10675 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
10677 case ALTIVEC_BUILTIN_MFVSCR:
10678 icode = CODE_FOR_altivec_mfvscr;
10679 tmode = insn_data[icode].operand[0].mode;
10682 || GET_MODE (target) != tmode
10683 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10684 target = gen_reg_rtx (tmode);
10686 pat = GEN_FCN (icode) (target);
10692 case ALTIVEC_BUILTIN_MTVSCR:
10693 icode = CODE_FOR_altivec_mtvscr;
10694 arg0 = CALL_EXPR_ARG (exp, 0);
10695 op0 = expand_normal (arg0);
10696 mode0 = insn_data[icode].operand[0].mode;
10698 /* If we got invalid arguments bail out before generating bad rtl. */
10699 if (arg0 == error_mark_node)
10702 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10703 op0 = copy_to_mode_reg (mode0, op0);
10705 pat = GEN_FCN (icode) (op0);
10710 case ALTIVEC_BUILTIN_DSSALL:
10711 emit_insn (gen_altivec_dssall ());
10714 case ALTIVEC_BUILTIN_DSS:
10715 icode = CODE_FOR_altivec_dss;
10716 arg0 = CALL_EXPR_ARG (exp, 0);
10718 op0 = expand_normal (arg0);
10719 mode0 = insn_data[icode].operand[0].mode;
10721 /* If we got invalid arguments bail out before generating bad rtl. */
10722 if (arg0 == error_mark_node)
10725 if (TREE_CODE (arg0) != INTEGER_CST
10726 || TREE_INT_CST_LOW (arg0) & ~0x3)
10728 error ("argument to dss must be a 2-bit unsigned literal");
10732 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10733 op0 = copy_to_mode_reg (mode0, op0);
10735 emit_insn (gen_altivec_dss (op0));
10738 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
10739 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
10740 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
10741 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
10742 case VSX_BUILTIN_VEC_INIT_V2DF:
10743 case VSX_BUILTIN_VEC_INIT_V2DI:
10744 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
10746 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
10747 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
10748 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
10749 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
10750 case VSX_BUILTIN_VEC_SET_V2DF:
10751 case VSX_BUILTIN_VEC_SET_V2DI:
10752 return altivec_expand_vec_set_builtin (exp);
10754 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
10755 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
10756 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
10757 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
10758 case VSX_BUILTIN_VEC_EXT_V2DF:
10759 case VSX_BUILTIN_VEC_EXT_V2DI:
10760 return altivec_expand_vec_ext_builtin (exp, target);
10764 /* Fall through. */
10767 /* Expand abs* operations. */
10769 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
10770 if (d->code == fcode)
10771 return altivec_expand_abs_builtin (d->icode, exp, target);
10773 /* Expand the AltiVec predicates. */
10774 d = bdesc_altivec_preds;
10775 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
10776 if (d->code == fcode)
10777 return altivec_expand_predicate_builtin (d->icode, exp, target);
10779 /* LV* are funky. We initialized them differently. */
10782 case ALTIVEC_BUILTIN_LVSL:
10783 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
10784 exp, target, false);
10785 case ALTIVEC_BUILTIN_LVSR:
10786 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
10787 exp, target, false);
10788 case ALTIVEC_BUILTIN_LVEBX:
10789 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
10790 exp, target, false);
10791 case ALTIVEC_BUILTIN_LVEHX:
10792 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
10793 exp, target, false);
10794 case ALTIVEC_BUILTIN_LVEWX:
10795 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
10796 exp, target, false);
10797 case ALTIVEC_BUILTIN_LVXL:
10798 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
10799 exp, target, false);
10800 case ALTIVEC_BUILTIN_LVX:
10801 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
10802 exp, target, false);
10803 case ALTIVEC_BUILTIN_LVLX:
10804 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
10805 exp, target, true);
10806 case ALTIVEC_BUILTIN_LVLXL:
10807 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
10808 exp, target, true);
10809 case ALTIVEC_BUILTIN_LVRX:
10810 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
10811 exp, target, true);
10812 case ALTIVEC_BUILTIN_LVRXL:
10813 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
10814 exp, target, true);
10815 case VSX_BUILTIN_LXVD2X_V2DF:
10816 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
10817 exp, target, false);
10818 case VSX_BUILTIN_LXVD2X_V2DI:
10819 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
10820 exp, target, false);
10821 case VSX_BUILTIN_LXVW4X_V4SF:
10822 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
10823 exp, target, false);
10824 case VSX_BUILTIN_LXVW4X_V4SI:
10825 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
10826 exp, target, false);
10827 case VSX_BUILTIN_LXVW4X_V8HI:
10828 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
10829 exp, target, false);
10830 case VSX_BUILTIN_LXVW4X_V16QI:
10831 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
10832 exp, target, false);
10836 /* Fall through. */
10839 *expandedp = false;
10843 /* Expand the builtin in EXP and store the result in TARGET. Store
10844 true in *EXPANDEDP if we found a builtin to expand. */
10846 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
10848 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10849 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10850 const struct builtin_description *d;
10857 case PAIRED_BUILTIN_STX:
10858 return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
10859 case PAIRED_BUILTIN_LX:
10860 return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
10863 /* Fall through. */
10866 /* Expand the paired predicates. */
10867 d = bdesc_paired_preds;
10868 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
10869 if (d->code == fcode)
10870 return paired_expand_predicate_builtin (d->icode, exp, target);
10872 *expandedp = false;
10876 /* Binops that need to be initialized manually, but can be expanded
10877 automagically by rs6000_expand_binop_builtin. */
10878 static const struct builtin_description bdesc_2arg_spe[] =
10880 { RS6000_BTM_SPE, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
10881 { RS6000_BTM_SPE, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
10882 { RS6000_BTM_SPE, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
10883 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
10884 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
10885 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
10886 { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
10887 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
10888 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
10889 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
10890 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
10891 { RS6000_BTM_SPE, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
10892 { RS6000_BTM_SPE, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
10893 { RS6000_BTM_SPE, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
10894 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
10895 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
10896 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
10897 { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
10898 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
10899 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
10900 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
10901 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
10904 /* Expand the builtin in EXP and store the result in TARGET. Store
10905 true in *EXPANDEDP if we found a builtin to expand.
10907 This expands the SPE builtins that are not simple unary and binary
10910 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
10912 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10914 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10915 enum insn_code icode;
10916 enum machine_mode tmode, mode0;
10918 const struct builtin_description *d;
10923 /* Syntax check for a 5-bit unsigned immediate. */
10926 case SPE_BUILTIN_EVSTDD:
10927 case SPE_BUILTIN_EVSTDH:
10928 case SPE_BUILTIN_EVSTDW:
10929 case SPE_BUILTIN_EVSTWHE:
10930 case SPE_BUILTIN_EVSTWHO:
10931 case SPE_BUILTIN_EVSTWWE:
10932 case SPE_BUILTIN_EVSTWWO:
10933 arg1 = CALL_EXPR_ARG (exp, 2);
10934 if (TREE_CODE (arg1) != INTEGER_CST
10935 || TREE_INT_CST_LOW (arg1) & ~0x1f)
10937 error ("argument 2 must be a 5-bit unsigned literal");
10945 /* The evsplat*i instructions are not quite generic. */
10948 case SPE_BUILTIN_EVSPLATFI:
10949 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
10951 case SPE_BUILTIN_EVSPLATI:
10952 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
10958 d = bdesc_2arg_spe;
10959 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
10960 if (d->code == fcode)
10961 return rs6000_expand_binop_builtin (d->icode, exp, target);
10963 d = bdesc_spe_predicates;
10964 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
10965 if (d->code == fcode)
10966 return spe_expand_predicate_builtin (d->icode, exp, target);
10968 d = bdesc_spe_evsel;
10969 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
10970 if (d->code == fcode)
10971 return spe_expand_evsel_builtin (d->icode, exp, target);
10975 case SPE_BUILTIN_EVSTDDX:
10976 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
10977 case SPE_BUILTIN_EVSTDHX:
10978 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
10979 case SPE_BUILTIN_EVSTDWX:
10980 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
10981 case SPE_BUILTIN_EVSTWHEX:
10982 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
10983 case SPE_BUILTIN_EVSTWHOX:
10984 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
10985 case SPE_BUILTIN_EVSTWWEX:
10986 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
10987 case SPE_BUILTIN_EVSTWWOX:
10988 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
10989 case SPE_BUILTIN_EVSTDD:
10990 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
10991 case SPE_BUILTIN_EVSTDH:
10992 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
10993 case SPE_BUILTIN_EVSTDW:
10994 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
10995 case SPE_BUILTIN_EVSTWHE:
10996 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
10997 case SPE_BUILTIN_EVSTWHO:
10998 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
10999 case SPE_BUILTIN_EVSTWWE:
11000 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
11001 case SPE_BUILTIN_EVSTWWO:
11002 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
11003 case SPE_BUILTIN_MFSPEFSCR:
11004 icode = CODE_FOR_spe_mfspefscr;
11005 tmode = insn_data[icode].operand[0].mode;
11008 || GET_MODE (target) != tmode
11009 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11010 target = gen_reg_rtx (tmode);
11012 pat = GEN_FCN (icode) (target);
11017 case SPE_BUILTIN_MTSPEFSCR:
11018 icode = CODE_FOR_spe_mtspefscr;
11019 arg0 = CALL_EXPR_ARG (exp, 0);
11020 op0 = expand_normal (arg0);
11021 mode0 = insn_data[icode].operand[0].mode;
11023 if (arg0 == error_mark_node)
11026 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
11027 op0 = copy_to_mode_reg (mode0, op0);
11029 pat = GEN_FCN (icode) (op0);
11037 *expandedp = false;
11042 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
11044 rtx pat, scratch, tmp;
11045 tree form = CALL_EXPR_ARG (exp, 0);
11046 tree arg0 = CALL_EXPR_ARG (exp, 1);
11047 tree arg1 = CALL_EXPR_ARG (exp, 2);
11048 rtx op0 = expand_normal (arg0);
11049 rtx op1 = expand_normal (arg1);
11050 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11051 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11053 enum rtx_code code;
11055 if (TREE_CODE (form) != INTEGER_CST)
11057 error ("argument 1 of __builtin_paired_predicate must be a constant");
11061 form_int = TREE_INT_CST_LOW (form);
11063 gcc_assert (mode0 == mode1);
11065 if (arg0 == error_mark_node || arg1 == error_mark_node)
11069 || GET_MODE (target) != SImode
11070 || !(*insn_data[icode].operand[0].predicate) (target, SImode))
11071 target = gen_reg_rtx (SImode);
11072 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
11073 op0 = copy_to_mode_reg (mode0, op0);
11074 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
11075 op1 = copy_to_mode_reg (mode1, op1);
11077 scratch = gen_reg_rtx (CCFPmode);
11079 pat = GEN_FCN (icode) (scratch, op0, op1);
11101 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
11104 error ("argument 1 of __builtin_paired_predicate is out of range");
11108 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
11109 emit_move_insn (target, tmp);
11114 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
11116 rtx pat, scratch, tmp;
11117 tree form = CALL_EXPR_ARG (exp, 0);
11118 tree arg0 = CALL_EXPR_ARG (exp, 1);
11119 tree arg1 = CALL_EXPR_ARG (exp, 2);
11120 rtx op0 = expand_normal (arg0);
11121 rtx op1 = expand_normal (arg1);
11122 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11123 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11125 enum rtx_code code;
11127 if (TREE_CODE (form) != INTEGER_CST)
11129 error ("argument 1 of __builtin_spe_predicate must be a constant");
11133 form_int = TREE_INT_CST_LOW (form);
11135 gcc_assert (mode0 == mode1);
11137 if (arg0 == error_mark_node || arg1 == error_mark_node)
11141 || GET_MODE (target) != SImode
11142 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
11143 target = gen_reg_rtx (SImode);
11145 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11146 op0 = copy_to_mode_reg (mode0, op0);
11147 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11148 op1 = copy_to_mode_reg (mode1, op1);
11150 scratch = gen_reg_rtx (CCmode);
11152 pat = GEN_FCN (icode) (scratch, op0, op1);
11157 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
11158 _lower_. We use one compare, but look in different bits of the
11159 CR for each variant.
11161 There are 2 elements in each SPE simd type (upper/lower). The CR
11162 bits are set as follows:
11164 BIT0 | BIT 1 | BIT 2 | BIT 3
11165 U | L | (U | L) | (U & L)
11167 So, for an "all" relationship, BIT 3 would be set.
11168 For an "any" relationship, BIT 2 would be set. Etc.
11170 Following traditional nomenclature, these bits map to:
11172 BIT0 | BIT 1 | BIT 2 | BIT 3
11175 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
11180 /* All variant. OV bit. */
11182 /* We need to get to the OV bit, which is the ORDERED bit. We
11183 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
11184 that's ugly and will make validate_condition_mode die.
11185 So let's just use another pattern. */
11186 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
11188 /* Any variant. EQ bit. */
11192 /* Upper variant. LT bit. */
11196 /* Lower variant. GT bit. */
11201 error ("argument 1 of __builtin_spe_predicate is out of range");
11205 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
11206 emit_move_insn (target, tmp);
11211 /* The evsel builtins look like this:
11213 e = __builtin_spe_evsel_OP (a, b, c, d);
11215 and work like this:
11217 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
11218 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
11222 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
11225 tree arg0 = CALL_EXPR_ARG (exp, 0);
11226 tree arg1 = CALL_EXPR_ARG (exp, 1);
11227 tree arg2 = CALL_EXPR_ARG (exp, 2);
11228 tree arg3 = CALL_EXPR_ARG (exp, 3);
11229 rtx op0 = expand_normal (arg0);
11230 rtx op1 = expand_normal (arg1);
11231 rtx op2 = expand_normal (arg2);
11232 rtx op3 = expand_normal (arg3);
11233 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11234 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11236 gcc_assert (mode0 == mode1);
11238 if (arg0 == error_mark_node || arg1 == error_mark_node
11239 || arg2 == error_mark_node || arg3 == error_mark_node)
11243 || GET_MODE (target) != mode0
11244 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
11245 target = gen_reg_rtx (mode0);
11247 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11248 op0 = copy_to_mode_reg (mode0, op0);
11249 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
11250 op1 = copy_to_mode_reg (mode0, op1);
11251 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
11252 op2 = copy_to_mode_reg (mode0, op2);
11253 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
11254 op3 = copy_to_mode_reg (mode0, op3);
11256 /* Generate the compare. */
11257 scratch = gen_reg_rtx (CCmode);
11258 pat = GEN_FCN (icode) (scratch, op0, op1);
11263 if (mode0 == V2SImode)
11264 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
11266 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
11271 /* Raise an error message for a builtin function that is called without the
11272 appropriate target options being set. */
11275 rs6000_invalid_builtin (enum rs6000_builtins fncode)
11277 size_t uns_fncode = (size_t)fncode;
11278 const char *name = rs6000_builtin_info[uns_fncode].name;
11279 unsigned fnmask = rs6000_builtin_info[uns_fncode].mask;
11281 gcc_assert (name != NULL);
11282 if ((fnmask & RS6000_BTM_CELL) != 0)
11283 error ("Builtin function %s is only valid for the cell processor", name);
11284 else if ((fnmask & RS6000_BTM_VSX) != 0)
11285 error ("Builtin function %s requires the -mvsx option", name);
11286 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
11287 error ("Builtin function %s requires the -maltivec option", name);
11288 else if ((fnmask & RS6000_BTM_PAIRED) != 0)
11289 error ("Builtin function %s requires the -mpaired option", name);
11290 else if ((fnmask & RS6000_BTM_SPE) != 0)
11291 error ("Builtin function %s requires the -mspe option", name);
11293 error ("Builtin function %s is not supported with the current options",
11297 /* Expand an expression EXP that calls a built-in function,
11298 with result going to TARGET if that's convenient
11299 (and in mode MODE if that's convenient).
11300 SUBTARGET may be used as the target for computing one of EXP's operands.
11301 IGNORE is nonzero if the value is to be ignored. */
11304 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11305 enum machine_mode mode ATTRIBUTE_UNUSED,
11306 int ignore ATTRIBUTE_UNUSED)
11308 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11309 enum rs6000_builtins fcode
11310 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
11311 size_t uns_fcode = (size_t)fcode;
11312 const struct builtin_description *d;
11316 unsigned mask = rs6000_builtin_info[uns_fcode].mask;
11317 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
11319 if (TARGET_DEBUG_BUILTIN)
11321 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
11322 const char *name1 = rs6000_builtin_info[uns_fcode].name;
11323 const char *name2 = ((icode != CODE_FOR_nothing)
11324 ? get_insn_name ((int)icode)
11328 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
11330 default: name3 = "unknown"; break;
11331 case RS6000_BTC_SPECIAL: name3 = "special"; break;
11332 case RS6000_BTC_UNARY: name3 = "unary"; break;
11333 case RS6000_BTC_BINARY: name3 = "binary"; break;
11334 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
11335 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
11336 case RS6000_BTC_ABS: name3 = "abs"; break;
11337 case RS6000_BTC_EVSEL: name3 = "evsel"; break;
11338 case RS6000_BTC_DST: name3 = "dst"; break;
11343 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
11344 (name1) ? name1 : "---", fcode,
11345 (name2) ? name2 : "---", (int)icode,
11347 func_valid_p ? "" : ", not valid");
11352 rs6000_invalid_builtin (fcode);
11354 /* Given it is invalid, just generate a normal call. */
11355 return expand_call (exp, target, ignore);
11360 case RS6000_BUILTIN_RECIP:
11361 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
11363 case RS6000_BUILTIN_RECIPF:
11364 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
11366 case RS6000_BUILTIN_RSQRTF:
11367 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
11369 case RS6000_BUILTIN_RSQRT:
11370 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
11372 case RS6000_BUILTIN_BSWAP_HI:
11373 return rs6000_expand_unop_builtin (CODE_FOR_bswaphi2, exp, target);
11375 case POWER7_BUILTIN_BPERMD:
11376 return rs6000_expand_binop_builtin (((TARGET_64BIT)
11377 ? CODE_FOR_bpermd_di
11378 : CODE_FOR_bpermd_si), exp, target);
11380 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
11381 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
11383 int icode = (int) CODE_FOR_altivec_lvsr;
11384 enum machine_mode tmode = insn_data[icode].operand[0].mode;
11385 enum machine_mode mode = insn_data[icode].operand[1].mode;
11389 gcc_assert (TARGET_ALTIVEC);
11391 arg = CALL_EXPR_ARG (exp, 0);
11392 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
11393 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
11394 addr = memory_address (mode, op);
11395 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
11399 /* For the load case need to negate the address. */
11400 op = gen_reg_rtx (GET_MODE (addr));
11401 emit_insn (gen_rtx_SET (VOIDmode, op,
11402 gen_rtx_NEG (GET_MODE (addr), addr)));
11404 op = gen_rtx_MEM (mode, op);
11407 || GET_MODE (target) != tmode
11408 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11409 target = gen_reg_rtx (tmode);
11411 /*pat = gen_altivec_lvsr (target, op);*/
11412 pat = GEN_FCN (icode) (target, op);
11420 case ALTIVEC_BUILTIN_VCFUX:
11421 case ALTIVEC_BUILTIN_VCFSX:
11422 case ALTIVEC_BUILTIN_VCTUXS:
11423 case ALTIVEC_BUILTIN_VCTSXS:
11424 /* FIXME: There's got to be a nicer way to handle this case than
11425 constructing a new CALL_EXPR. */
11426 if (call_expr_nargs (exp) == 1)
11428 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
11429 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
11437 if (TARGET_ALTIVEC)
11439 ret = altivec_expand_builtin (exp, target, &success);
11446 ret = spe_expand_builtin (exp, target, &success);
11451 if (TARGET_PAIRED_FLOAT)
11453 ret = paired_expand_builtin (exp, target, &success);
11459 gcc_assert (TARGET_ALTIVEC || TARGET_VSX || TARGET_SPE || TARGET_PAIRED_FLOAT);
11461 /* Handle simple unary operations. */
11463 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
11464 if (d->code == fcode)
11465 return rs6000_expand_unop_builtin (d->icode, exp, target);
11467 /* Handle simple binary operations. */
11469 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11470 if (d->code == fcode)
11471 return rs6000_expand_binop_builtin (d->icode, exp, target);
11473 /* Handle simple ternary operations. */
11475 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
11476 if (d->code == fcode)
11477 return rs6000_expand_ternop_builtin (d->icode, exp, target);
11479 gcc_unreachable ();
11483 rs6000_init_builtins (void)
11487 enum machine_mode mode;
11489 if (TARGET_DEBUG_BUILTIN)
11490 fprintf (stderr, "rs6000_init_builtins%s%s%s%s\n",
11491 (TARGET_PAIRED_FLOAT) ? ", paired" : "",
11492 (TARGET_SPE) ? ", spe" : "",
11493 (TARGET_ALTIVEC) ? ", altivec" : "",
11494 (TARGET_VSX) ? ", vsx" : "");
11496 V2SI_type_node = build_vector_type (intSI_type_node, 2);
11497 V2SF_type_node = build_vector_type (float_type_node, 2);
11498 V2DI_type_node = build_vector_type (intDI_type_node, 2);
11499 V2DF_type_node = build_vector_type (double_type_node, 2);
11500 V4HI_type_node = build_vector_type (intHI_type_node, 4);
11501 V4SI_type_node = build_vector_type (intSI_type_node, 4);
11502 V4SF_type_node = build_vector_type (float_type_node, 4);
11503 V8HI_type_node = build_vector_type (intHI_type_node, 8);
11504 V16QI_type_node = build_vector_type (intQI_type_node, 16);
11506 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
11507 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
11508 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
11509 unsigned_V2DI_type_node = build_vector_type (unsigned_intDI_type_node, 2);
11511 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
11512 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
11513 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
11514 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
11516 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
11517 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
11518 'vector unsigned short'. */
11520 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
11521 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
11522 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
11523 bool_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
11524 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
11526 long_integer_type_internal_node = long_integer_type_node;
11527 long_unsigned_type_internal_node = long_unsigned_type_node;
11528 long_long_integer_type_internal_node = long_long_integer_type_node;
11529 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
11530 intQI_type_internal_node = intQI_type_node;
11531 uintQI_type_internal_node = unsigned_intQI_type_node;
11532 intHI_type_internal_node = intHI_type_node;
11533 uintHI_type_internal_node = unsigned_intHI_type_node;
11534 intSI_type_internal_node = intSI_type_node;
11535 uintSI_type_internal_node = unsigned_intSI_type_node;
11536 intDI_type_internal_node = intDI_type_node;
11537 uintDI_type_internal_node = unsigned_intDI_type_node;
11538 float_type_internal_node = float_type_node;
11539 double_type_internal_node = double_type_node;
11540 void_type_internal_node = void_type_node;
11542 /* Initialize the modes for builtin_function_type, mapping a machine mode to
11544 builtin_mode_to_type[QImode][0] = integer_type_node;
11545 builtin_mode_to_type[HImode][0] = integer_type_node;
11546 builtin_mode_to_type[SImode][0] = intSI_type_node;
11547 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
11548 builtin_mode_to_type[DImode][0] = intDI_type_node;
11549 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
11550 builtin_mode_to_type[SFmode][0] = float_type_node;
11551 builtin_mode_to_type[DFmode][0] = double_type_node;
11552 builtin_mode_to_type[V2SImode][0] = V2SI_type_node;
11553 builtin_mode_to_type[V2SFmode][0] = V2SF_type_node;
11554 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
11555 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
11556 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
11557 builtin_mode_to_type[V4HImode][0] = V4HI_type_node;
11558 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
11559 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
11560 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
11561 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
11562 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
11563 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
11564 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
11566 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11567 get_identifier ("__bool char"),
11568 bool_char_type_node);
11569 TYPE_NAME (bool_char_type_node) = tdecl;
11570 (*lang_hooks.decls.pushdecl) (tdecl);
11571 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11572 get_identifier ("__bool short"),
11573 bool_short_type_node);
11574 TYPE_NAME (bool_short_type_node) = tdecl;
11575 (*lang_hooks.decls.pushdecl) (tdecl);
11576 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11577 get_identifier ("__bool int"),
11578 bool_int_type_node);
11579 TYPE_NAME (bool_int_type_node) = tdecl;
11580 (*lang_hooks.decls.pushdecl) (tdecl);
11581 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL, get_identifier ("__pixel"),
11583 TYPE_NAME (pixel_type_node) = tdecl;
11584 (*lang_hooks.decls.pushdecl) (tdecl);
11586 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
11587 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
11588 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
11589 bool_V2DI_type_node = build_vector_type (bool_long_type_node, 2);
11590 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
11592 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11593 get_identifier ("__vector unsigned char"),
11594 unsigned_V16QI_type_node);
11595 TYPE_NAME (unsigned_V16QI_type_node) = tdecl;
11596 (*lang_hooks.decls.pushdecl) (tdecl);
11597 tdecl = build_decl (BUILTINS_LOCATION,
11598 TYPE_DECL, get_identifier ("__vector signed char"),
11600 TYPE_NAME (V16QI_type_node) = tdecl;
11601 (*lang_hooks.decls.pushdecl) (tdecl);
11602 tdecl = build_decl (BUILTINS_LOCATION,
11603 TYPE_DECL, get_identifier ("__vector __bool char"),
11604 bool_V16QI_type_node);
11605 TYPE_NAME ( bool_V16QI_type_node) = tdecl;
11606 (*lang_hooks.decls.pushdecl) (tdecl);
11608 tdecl = build_decl (BUILTINS_LOCATION,
11609 TYPE_DECL, get_identifier ("__vector unsigned short"),
11610 unsigned_V8HI_type_node);
11611 TYPE_NAME (unsigned_V8HI_type_node) = tdecl;
11612 (*lang_hooks.decls.pushdecl) (tdecl);
11613 tdecl = build_decl (BUILTINS_LOCATION,
11614 TYPE_DECL, get_identifier ("__vector signed short"),
11616 TYPE_NAME (V8HI_type_node) = tdecl;
11617 (*lang_hooks.decls.pushdecl) (tdecl);
11618 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11619 get_identifier ("__vector __bool short"),
11620 bool_V8HI_type_node);
11621 TYPE_NAME (bool_V8HI_type_node) = tdecl;
11622 (*lang_hooks.decls.pushdecl) (tdecl);
11624 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11625 get_identifier ("__vector unsigned int"),
11626 unsigned_V4SI_type_node);
11627 TYPE_NAME (unsigned_V4SI_type_node) = tdecl;
11628 (*lang_hooks.decls.pushdecl) (tdecl);
11629 tdecl = build_decl (BUILTINS_LOCATION,
11630 TYPE_DECL, get_identifier ("__vector signed int"),
11632 TYPE_NAME (V4SI_type_node) = tdecl;
11633 (*lang_hooks.decls.pushdecl) (tdecl);
11634 tdecl = build_decl (BUILTINS_LOCATION,
11635 TYPE_DECL, get_identifier ("__vector __bool int"),
11636 bool_V4SI_type_node);
11637 TYPE_NAME (bool_V4SI_type_node) = tdecl;
11638 (*lang_hooks.decls.pushdecl) (tdecl);
11640 tdecl = build_decl (BUILTINS_LOCATION,
11641 TYPE_DECL, get_identifier ("__vector float"),
11643 TYPE_NAME (V4SF_type_node) = tdecl;
11644 (*lang_hooks.decls.pushdecl) (tdecl);
11645 tdecl = build_decl (BUILTINS_LOCATION,
11646 TYPE_DECL, get_identifier ("__vector __pixel"),
11647 pixel_V8HI_type_node);
11648 TYPE_NAME (pixel_V8HI_type_node) = tdecl;
11649 (*lang_hooks.decls.pushdecl) (tdecl);
11651 tdecl = build_decl (BUILTINS_LOCATION,
11652 TYPE_DECL, get_identifier ("__vector double"),
11654 TYPE_NAME (V2DF_type_node) = tdecl;
11655 (*lang_hooks.decls.pushdecl) (tdecl);
11657 tdecl = build_decl (BUILTINS_LOCATION,
11658 TYPE_DECL, get_identifier ("__vector long"),
11660 TYPE_NAME (V2DI_type_node) = tdecl;
11661 (*lang_hooks.decls.pushdecl) (tdecl);
11663 tdecl = build_decl (BUILTINS_LOCATION,
11664 TYPE_DECL, get_identifier ("__vector unsigned long"),
11665 unsigned_V2DI_type_node);
11666 TYPE_NAME (unsigned_V2DI_type_node) = tdecl;
11667 (*lang_hooks.decls.pushdecl) (tdecl);
11669 tdecl = build_decl (BUILTINS_LOCATION,
11670 TYPE_DECL, get_identifier ("__vector __bool long"),
11671 bool_V2DI_type_node);
11672 TYPE_NAME (bool_V2DI_type_node) = tdecl;
11673 (*lang_hooks.decls.pushdecl) (tdecl);
11675 /* Paired and SPE builtins are only available if you build a compiler with
11676 the appropriate options, so only create those builtins with the
11677 appropriate compiler option. Create Altivec and VSX builtins on machines
11678 with at least the general purpose extensions (970 and newer) to allow the
11679 use of the target attribute. */
11680 if (TARGET_PAIRED_FLOAT)
11681 paired_init_builtins ();
11683 spe_init_builtins ();
11684 if (TARGET_EXTRA_BUILTINS)
11685 altivec_init_builtins ();
11686 if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT)
11687 rs6000_common_init_builtins ();
11689 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
11690 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
11691 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
11693 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
11694 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
11695 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
11697 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
11698 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
11699 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
11701 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
11702 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
11703 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
11705 mode = (TARGET_64BIT) ? DImode : SImode;
11706 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
11707 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
11708 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
11710 /* Don't use builtin_function_type here, as it maps HI/QI to SI. */
11711 ftype = build_function_type_list (unsigned_intHI_type_node,
11712 unsigned_intHI_type_node,
11714 def_builtin ("__builtin_bswap16", ftype, RS6000_BUILTIN_BSWAP_HI);
11717 /* AIX libm provides clog as __clog. */
11718 if ((tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
11719 set_user_assembler_name (tdecl, "__clog");
11722 #ifdef SUBTARGET_INIT_BUILTINS
11723 SUBTARGET_INIT_BUILTINS;
11727 /* Returns the rs6000 builtin decl for CODE. */
11730 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
11734 if (code >= RS6000_BUILTIN_COUNT)
11735 return error_mark_node;
11737 fnmask = rs6000_builtin_info[code].mask;
11738 if ((fnmask & rs6000_builtin_mask) != fnmask)
11740 rs6000_invalid_builtin ((enum rs6000_builtins)code);
11741 return error_mark_node;
11744 return rs6000_builtin_decls[code];
11748 spe_init_builtins (void)
11750 tree puint_type_node = build_pointer_type (unsigned_type_node);
11751 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
11752 const struct builtin_description *d;
11755 tree v2si_ftype_4_v2si
11756 = build_function_type_list (opaque_V2SI_type_node,
11757 opaque_V2SI_type_node,
11758 opaque_V2SI_type_node,
11759 opaque_V2SI_type_node,
11760 opaque_V2SI_type_node,
11763 tree v2sf_ftype_4_v2sf
11764 = build_function_type_list (opaque_V2SF_type_node,
11765 opaque_V2SF_type_node,
11766 opaque_V2SF_type_node,
11767 opaque_V2SF_type_node,
11768 opaque_V2SF_type_node,
11771 tree int_ftype_int_v2si_v2si
11772 = build_function_type_list (integer_type_node,
11774 opaque_V2SI_type_node,
11775 opaque_V2SI_type_node,
11778 tree int_ftype_int_v2sf_v2sf
11779 = build_function_type_list (integer_type_node,
11781 opaque_V2SF_type_node,
11782 opaque_V2SF_type_node,
11785 tree void_ftype_v2si_puint_int
11786 = build_function_type_list (void_type_node,
11787 opaque_V2SI_type_node,
11792 tree void_ftype_v2si_puint_char
11793 = build_function_type_list (void_type_node,
11794 opaque_V2SI_type_node,
11799 tree void_ftype_v2si_pv2si_int
11800 = build_function_type_list (void_type_node,
11801 opaque_V2SI_type_node,
11802 opaque_p_V2SI_type_node,
11806 tree void_ftype_v2si_pv2si_char
11807 = build_function_type_list (void_type_node,
11808 opaque_V2SI_type_node,
11809 opaque_p_V2SI_type_node,
11813 tree void_ftype_int
11814 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
11816 tree int_ftype_void
11817 = build_function_type_list (integer_type_node, NULL_TREE);
11819 tree v2si_ftype_pv2si_int
11820 = build_function_type_list (opaque_V2SI_type_node,
11821 opaque_p_V2SI_type_node,
11825 tree v2si_ftype_puint_int
11826 = build_function_type_list (opaque_V2SI_type_node,
11831 tree v2si_ftype_pushort_int
11832 = build_function_type_list (opaque_V2SI_type_node,
11837 tree v2si_ftype_signed_char
11838 = build_function_type_list (opaque_V2SI_type_node,
11839 signed_char_type_node,
11842 (*lang_hooks.decls.pushdecl)
11843 (build_decl (BUILTINS_LOCATION, TYPE_DECL,
11844 get_identifier ("__ev64_opaque__"),
11845 opaque_V2SI_type_node));
11847 /* Initialize irregular SPE builtins. */
11849 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
11850 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
11851 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
11852 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
11853 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
11854 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
11855 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
11856 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
11857 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
11858 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
11859 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
11860 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
11861 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
11862 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
11863 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
11864 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
11865 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
11866 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
11869 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
11870 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
11871 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
11872 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
11873 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
11874 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
11875 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
11876 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
11877 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
11878 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
11879 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
11880 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
11881 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
11882 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
11883 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
11884 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
11885 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
11886 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
11887 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
11888 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
11889 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
11890 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
11893 d = bdesc_spe_predicates;
11894 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
11898 switch (insn_data[d->icode].operand[1].mode)
11901 type = int_ftype_int_v2si_v2si;
11904 type = int_ftype_int_v2sf_v2sf;
11907 gcc_unreachable ();
11910 def_builtin (d->name, type, d->code);
11913 /* Evsel predicates. */
11914 d = bdesc_spe_evsel;
11915 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
11919 switch (insn_data[d->icode].operand[1].mode)
11922 type = v2si_ftype_4_v2si;
11925 type = v2sf_ftype_4_v2sf;
11928 gcc_unreachable ();
11931 def_builtin (d->name, type, d->code);
11936 paired_init_builtins (void)
11938 const struct builtin_description *d;
11941 tree int_ftype_int_v2sf_v2sf
11942 = build_function_type_list (integer_type_node,
11947 tree pcfloat_type_node =
11948 build_pointer_type (build_qualified_type
11949 (float_type_node, TYPE_QUAL_CONST));
11951 tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
11952 long_integer_type_node,
11955 tree void_ftype_v2sf_long_pcfloat =
11956 build_function_type_list (void_type_node,
11958 long_integer_type_node,
11963 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat,
11964 PAIRED_BUILTIN_LX);
11967 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
11968 PAIRED_BUILTIN_STX);
11971 d = bdesc_paired_preds;
11972 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
11976 if (TARGET_DEBUG_BUILTIN)
11977 fprintf (stderr, "paired pred #%d, insn = %s [%d], mode = %s\n",
11978 (int)i, get_insn_name (d->icode), (int)d->icode,
11979 GET_MODE_NAME (insn_data[d->icode].operand[1].mode));
11981 switch (insn_data[d->icode].operand[1].mode)
11984 type = int_ftype_int_v2sf_v2sf;
11987 gcc_unreachable ();
11990 def_builtin (d->name, type, d->code);
11995 altivec_init_builtins (void)
11997 const struct builtin_description *d;
12002 tree pvoid_type_node = build_pointer_type (void_type_node);
12004 tree pcvoid_type_node
12005 = build_pointer_type (build_qualified_type (void_type_node,
12008 tree int_ftype_opaque
12009 = build_function_type_list (integer_type_node,
12010 opaque_V4SI_type_node, NULL_TREE);
12011 tree opaque_ftype_opaque
12012 = build_function_type_list (integer_type_node, NULL_TREE);
12013 tree opaque_ftype_opaque_int
12014 = build_function_type_list (opaque_V4SI_type_node,
12015 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
12016 tree opaque_ftype_opaque_opaque_int
12017 = build_function_type_list (opaque_V4SI_type_node,
12018 opaque_V4SI_type_node, opaque_V4SI_type_node,
12019 integer_type_node, NULL_TREE);
12020 tree int_ftype_int_opaque_opaque
12021 = build_function_type_list (integer_type_node,
12022 integer_type_node, opaque_V4SI_type_node,
12023 opaque_V4SI_type_node, NULL_TREE);
12024 tree int_ftype_int_v4si_v4si
12025 = build_function_type_list (integer_type_node,
12026 integer_type_node, V4SI_type_node,
12027 V4SI_type_node, NULL_TREE);
12028 tree void_ftype_v4si
12029 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
12030 tree v8hi_ftype_void
12031 = build_function_type_list (V8HI_type_node, NULL_TREE);
12032 tree void_ftype_void
12033 = build_function_type_list (void_type_node, NULL_TREE);
12034 tree void_ftype_int
12035 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
12037 tree opaque_ftype_long_pcvoid
12038 = build_function_type_list (opaque_V4SI_type_node,
12039 long_integer_type_node, pcvoid_type_node,
12041 tree v16qi_ftype_long_pcvoid
12042 = build_function_type_list (V16QI_type_node,
12043 long_integer_type_node, pcvoid_type_node,
12045 tree v8hi_ftype_long_pcvoid
12046 = build_function_type_list (V8HI_type_node,
12047 long_integer_type_node, pcvoid_type_node,
12049 tree v4si_ftype_long_pcvoid
12050 = build_function_type_list (V4SI_type_node,
12051 long_integer_type_node, pcvoid_type_node,
12053 tree v4sf_ftype_long_pcvoid
12054 = build_function_type_list (V4SF_type_node,
12055 long_integer_type_node, pcvoid_type_node,
12057 tree v2df_ftype_long_pcvoid
12058 = build_function_type_list (V2DF_type_node,
12059 long_integer_type_node, pcvoid_type_node,
12061 tree v2di_ftype_long_pcvoid
12062 = build_function_type_list (V2DI_type_node,
12063 long_integer_type_node, pcvoid_type_node,
12066 tree void_ftype_opaque_long_pvoid
12067 = build_function_type_list (void_type_node,
12068 opaque_V4SI_type_node, long_integer_type_node,
12069 pvoid_type_node, NULL_TREE);
12070 tree void_ftype_v4si_long_pvoid
12071 = build_function_type_list (void_type_node,
12072 V4SI_type_node, long_integer_type_node,
12073 pvoid_type_node, NULL_TREE);
12074 tree void_ftype_v16qi_long_pvoid
12075 = build_function_type_list (void_type_node,
12076 V16QI_type_node, long_integer_type_node,
12077 pvoid_type_node, NULL_TREE);
12078 tree void_ftype_v8hi_long_pvoid
12079 = build_function_type_list (void_type_node,
12080 V8HI_type_node, long_integer_type_node,
12081 pvoid_type_node, NULL_TREE);
12082 tree void_ftype_v4sf_long_pvoid
12083 = build_function_type_list (void_type_node,
12084 V4SF_type_node, long_integer_type_node,
12085 pvoid_type_node, NULL_TREE);
12086 tree void_ftype_v2df_long_pvoid
12087 = build_function_type_list (void_type_node,
12088 V2DF_type_node, long_integer_type_node,
12089 pvoid_type_node, NULL_TREE);
12090 tree void_ftype_v2di_long_pvoid
12091 = build_function_type_list (void_type_node,
12092 V2DI_type_node, long_integer_type_node,
12093 pvoid_type_node, NULL_TREE);
12094 tree int_ftype_int_v8hi_v8hi
12095 = build_function_type_list (integer_type_node,
12096 integer_type_node, V8HI_type_node,
12097 V8HI_type_node, NULL_TREE);
12098 tree int_ftype_int_v16qi_v16qi
12099 = build_function_type_list (integer_type_node,
12100 integer_type_node, V16QI_type_node,
12101 V16QI_type_node, NULL_TREE);
12102 tree int_ftype_int_v4sf_v4sf
12103 = build_function_type_list (integer_type_node,
12104 integer_type_node, V4SF_type_node,
12105 V4SF_type_node, NULL_TREE);
12106 tree int_ftype_int_v2df_v2df
12107 = build_function_type_list (integer_type_node,
12108 integer_type_node, V2DF_type_node,
12109 V2DF_type_node, NULL_TREE);
12110 tree v4si_ftype_v4si
12111 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
12112 tree v8hi_ftype_v8hi
12113 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
12114 tree v16qi_ftype_v16qi
12115 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
12116 tree v4sf_ftype_v4sf
12117 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
12118 tree v2df_ftype_v2df
12119 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
12120 tree void_ftype_pcvoid_int_int
12121 = build_function_type_list (void_type_node,
12122 pcvoid_type_node, integer_type_node,
12123 integer_type_node, NULL_TREE);
12125 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
12126 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
12127 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
12128 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
12129 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
12130 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
12131 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
12132 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
12133 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
12134 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
12135 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
12136 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
12137 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
12138 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
12139 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
12140 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
12141 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
12142 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
12143 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
12144 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
12145 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
12146 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
12147 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
12148 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
12149 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
12150 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
12151 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
12152 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
12153 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
12154 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
12156 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
12157 VSX_BUILTIN_LXVD2X_V2DF);
12158 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
12159 VSX_BUILTIN_LXVD2X_V2DI);
12160 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
12161 VSX_BUILTIN_LXVW4X_V4SF);
12162 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
12163 VSX_BUILTIN_LXVW4X_V4SI);
12164 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
12165 VSX_BUILTIN_LXVW4X_V8HI);
12166 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
12167 VSX_BUILTIN_LXVW4X_V16QI);
12168 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
12169 VSX_BUILTIN_STXVD2X_V2DF);
12170 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
12171 VSX_BUILTIN_STXVD2X_V2DI);
12172 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
12173 VSX_BUILTIN_STXVW4X_V4SF);
12174 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
12175 VSX_BUILTIN_STXVW4X_V4SI);
12176 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
12177 VSX_BUILTIN_STXVW4X_V8HI);
12178 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
12179 VSX_BUILTIN_STXVW4X_V16QI);
12180 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
12181 VSX_BUILTIN_VEC_LD);
12182 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
12183 VSX_BUILTIN_VEC_ST);
12185 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
12186 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
12187 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
12189 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
12190 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
12191 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
12192 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
12193 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
12194 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
12195 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
12196 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
12197 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
12198 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
12199 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
12200 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
12202 /* Cell builtins. */
12203 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
12204 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
12205 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
12206 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
12208 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
12209 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
12210 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
12211 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
12213 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
12214 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
12215 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
12216 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
12218 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
12219 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
12220 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
12221 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
12223 /* Add the DST variants. */
12225 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
12226 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
12228 /* Initialize the predicates. */
12229 d = bdesc_altivec_preds;
12230 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
12232 enum machine_mode mode1;
12235 if (rs6000_overloaded_builtin_p (d->code))
12238 mode1 = insn_data[d->icode].operand[1].mode;
12243 type = int_ftype_int_opaque_opaque;
12246 type = int_ftype_int_v4si_v4si;
12249 type = int_ftype_int_v8hi_v8hi;
12252 type = int_ftype_int_v16qi_v16qi;
12255 type = int_ftype_int_v4sf_v4sf;
12258 type = int_ftype_int_v2df_v2df;
12261 gcc_unreachable ();
12264 def_builtin (d->name, type, d->code);
12267 /* Initialize the abs* operators. */
12269 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
12271 enum machine_mode mode0;
12274 mode0 = insn_data[d->icode].operand[0].mode;
12279 type = v4si_ftype_v4si;
12282 type = v8hi_ftype_v8hi;
12285 type = v16qi_ftype_v16qi;
12288 type = v4sf_ftype_v4sf;
12291 type = v2df_ftype_v2df;
12294 gcc_unreachable ();
12297 def_builtin (d->name, type, d->code);
12300 /* Initialize target builtin that implements
12301 targetm.vectorize.builtin_mask_for_load. */
12303 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
12304 v16qi_ftype_long_pcvoid,
12305 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
12306 BUILT_IN_MD, NULL, NULL_TREE);
12307 TREE_READONLY (decl) = 1;
12308 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
12309 altivec_builtin_mask_for_load = decl;
12311 /* Access to the vec_init patterns. */
12312 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
12313 integer_type_node, integer_type_node,
12314 integer_type_node, NULL_TREE);
12315 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
12317 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
12318 short_integer_type_node,
12319 short_integer_type_node,
12320 short_integer_type_node,
12321 short_integer_type_node,
12322 short_integer_type_node,
12323 short_integer_type_node,
12324 short_integer_type_node, NULL_TREE);
12325 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
12327 ftype = build_function_type_list (V16QI_type_node, char_type_node,
12328 char_type_node, char_type_node,
12329 char_type_node, char_type_node,
12330 char_type_node, char_type_node,
12331 char_type_node, char_type_node,
12332 char_type_node, char_type_node,
12333 char_type_node, char_type_node,
12334 char_type_node, char_type_node,
12335 char_type_node, NULL_TREE);
12336 def_builtin ("__builtin_vec_init_v16qi", ftype,
12337 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
12339 ftype = build_function_type_list (V4SF_type_node, float_type_node,
12340 float_type_node, float_type_node,
12341 float_type_node, NULL_TREE);
12342 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
12344 /* VSX builtins. */
12345 ftype = build_function_type_list (V2DF_type_node, double_type_node,
12346 double_type_node, NULL_TREE);
12347 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
12349 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
12350 intDI_type_node, NULL_TREE);
12351 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
12353 /* Access to the vec_set patterns. */
12354 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
12356 integer_type_node, NULL_TREE);
12357 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
12359 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
12361 integer_type_node, NULL_TREE);
12362 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
12364 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
12366 integer_type_node, NULL_TREE);
12367 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
12369 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
12371 integer_type_node, NULL_TREE);
12372 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
12374 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
12376 integer_type_node, NULL_TREE);
12377 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
12379 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
12381 integer_type_node, NULL_TREE);
12382 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
12384 /* Access to the vec_extract patterns. */
12385 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
12386 integer_type_node, NULL_TREE);
12387 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
12389 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
12390 integer_type_node, NULL_TREE);
12391 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
12393 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
12394 integer_type_node, NULL_TREE);
12395 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
12397 ftype = build_function_type_list (float_type_node, V4SF_type_node,
12398 integer_type_node, NULL_TREE);
12399 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
12401 ftype = build_function_type_list (double_type_node, V2DF_type_node,
12402 integer_type_node, NULL_TREE);
12403 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
12405 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
12406 integer_type_node, NULL_TREE);
12407 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
12410 /* Hash function for builtin functions with up to 3 arguments and a return
12413 builtin_hash_function (const void *hash_entry)
12417 const struct builtin_hash_struct *bh =
12418 (const struct builtin_hash_struct *) hash_entry;
12420 for (i = 0; i < 4; i++)
12422 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
12423 ret = (ret * 2) + bh->uns_p[i];
12429 /* Compare builtin hash entries H1 and H2 for equivalence. */
12431 builtin_hash_eq (const void *h1, const void *h2)
12433 const struct builtin_hash_struct *p1 = (const struct builtin_hash_struct *) h1;
12434 const struct builtin_hash_struct *p2 = (const struct builtin_hash_struct *) h2;
12436 return ((p1->mode[0] == p2->mode[0])
12437 && (p1->mode[1] == p2->mode[1])
12438 && (p1->mode[2] == p2->mode[2])
12439 && (p1->mode[3] == p2->mode[3])
12440 && (p1->uns_p[0] == p2->uns_p[0])
12441 && (p1->uns_p[1] == p2->uns_p[1])
12442 && (p1->uns_p[2] == p2->uns_p[2])
12443 && (p1->uns_p[3] == p2->uns_p[3]));
12446 /* Map types for builtin functions with an explicit return type and up to 3
12447 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
12448 of the argument. */
12450 builtin_function_type (enum machine_mode mode_ret, enum machine_mode mode_arg0,
12451 enum machine_mode mode_arg1, enum machine_mode mode_arg2,
12452 enum rs6000_builtins builtin, const char *name)
12454 struct builtin_hash_struct h;
12455 struct builtin_hash_struct *h2;
12459 tree ret_type = NULL_TREE;
12460 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
12462 /* Create builtin_hash_table. */
12463 if (builtin_hash_table == NULL)
12464 builtin_hash_table = htab_create_ggc (1500, builtin_hash_function,
12465 builtin_hash_eq, NULL);
12467 h.type = NULL_TREE;
12468 h.mode[0] = mode_ret;
12469 h.mode[1] = mode_arg0;
12470 h.mode[2] = mode_arg1;
12471 h.mode[3] = mode_arg2;
12477 /* If the builtin is a type that produces unsigned results or takes unsigned
12478 arguments, and it is returned as a decl for the vectorizer (such as
12479 widening multiplies, permute), make sure the arguments and return value
12480 are type correct. */
12483 /* unsigned 2 argument functions. */
12484 case ALTIVEC_BUILTIN_VMULEUB_UNS:
12485 case ALTIVEC_BUILTIN_VMULEUH_UNS:
12486 case ALTIVEC_BUILTIN_VMULOUB_UNS:
12487 case ALTIVEC_BUILTIN_VMULOUH_UNS:
12493 /* unsigned 3 argument functions. */
12494 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
12495 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
12496 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
12497 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
12498 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
12499 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
12500 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
12501 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
12502 case VSX_BUILTIN_VPERM_16QI_UNS:
12503 case VSX_BUILTIN_VPERM_8HI_UNS:
12504 case VSX_BUILTIN_VPERM_4SI_UNS:
12505 case VSX_BUILTIN_VPERM_2DI_UNS:
12506 case VSX_BUILTIN_XXSEL_16QI_UNS:
12507 case VSX_BUILTIN_XXSEL_8HI_UNS:
12508 case VSX_BUILTIN_XXSEL_4SI_UNS:
12509 case VSX_BUILTIN_XXSEL_2DI_UNS:
12516 /* signed permute functions with unsigned char mask. */
12517 case ALTIVEC_BUILTIN_VPERM_16QI:
12518 case ALTIVEC_BUILTIN_VPERM_8HI:
12519 case ALTIVEC_BUILTIN_VPERM_4SI:
12520 case ALTIVEC_BUILTIN_VPERM_4SF:
12521 case ALTIVEC_BUILTIN_VPERM_2DI:
12522 case ALTIVEC_BUILTIN_VPERM_2DF:
12523 case VSX_BUILTIN_VPERM_16QI:
12524 case VSX_BUILTIN_VPERM_8HI:
12525 case VSX_BUILTIN_VPERM_4SI:
12526 case VSX_BUILTIN_VPERM_4SF:
12527 case VSX_BUILTIN_VPERM_2DI:
12528 case VSX_BUILTIN_VPERM_2DF:
12532 /* unsigned args, signed return. */
12533 case VSX_BUILTIN_XVCVUXDDP_UNS:
12534 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
12538 /* signed args, unsigned return. */
12539 case VSX_BUILTIN_XVCVDPUXDS_UNS:
12540 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
12548 /* Figure out how many args are present. */
12549 while (num_args > 0 && h.mode[num_args] == VOIDmode)
12553 fatal_error ("internal error: builtin function %s had no type", name);
12555 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
12556 if (!ret_type && h.uns_p[0])
12557 ret_type = builtin_mode_to_type[h.mode[0]][0];
12560 fatal_error ("internal error: builtin function %s had an unexpected "
12561 "return type %s", name, GET_MODE_NAME (h.mode[0]));
12563 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
12564 arg_type[i] = NULL_TREE;
12566 for (i = 0; i < num_args; i++)
12568 int m = (int) h.mode[i+1];
12569 int uns_p = h.uns_p[i+1];
12571 arg_type[i] = builtin_mode_to_type[m][uns_p];
12572 if (!arg_type[i] && uns_p)
12573 arg_type[i] = builtin_mode_to_type[m][0];
12576 fatal_error ("internal error: builtin function %s, argument %d "
12577 "had unexpected argument type %s", name, i,
12578 GET_MODE_NAME (m));
12581 found = htab_find_slot (builtin_hash_table, &h, INSERT);
12582 if (*found == NULL)
12584 h2 = ggc_alloc_builtin_hash_struct ();
12586 *found = (void *)h2;
12588 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
12589 arg_type[2], NULL_TREE);
12592 return ((struct builtin_hash_struct *)(*found))->type;
12596 rs6000_common_init_builtins (void)
12598 const struct builtin_description *d;
12601 tree opaque_ftype_opaque = NULL_TREE;
12602 tree opaque_ftype_opaque_opaque = NULL_TREE;
12603 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
12604 tree v2si_ftype_qi = NULL_TREE;
12605 tree v2si_ftype_v2si_qi = NULL_TREE;
12606 tree v2si_ftype_int_qi = NULL_TREE;
12607 unsigned builtin_mask = rs6000_builtin_mask;
12609 if (!TARGET_PAIRED_FLOAT)
12611 builtin_mode_to_type[V2SImode][0] = opaque_V2SI_type_node;
12612 builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node;
12615 /* Paired and SPE builtins are only available if you build a compiler with
12616 the appropriate options, so only create those builtins with the
12617 appropriate compiler option. Create Altivec and VSX builtins on machines
12618 with at least the general purpose extensions (970 and newer) to allow the
12619 use of the target attribute.. */
12621 if (TARGET_EXTRA_BUILTINS)
12622 builtin_mask |= RS6000_BTM_COMMON;
12624 /* Add the ternary operators. */
12626 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
12629 unsigned mask = d->mask;
12631 if ((mask & builtin_mask) != mask)
12633 if (TARGET_DEBUG_BUILTIN)
12634 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
12638 if (rs6000_overloaded_builtin_p (d->code))
12640 if (! (type = opaque_ftype_opaque_opaque_opaque))
12641 type = opaque_ftype_opaque_opaque_opaque
12642 = build_function_type_list (opaque_V4SI_type_node,
12643 opaque_V4SI_type_node,
12644 opaque_V4SI_type_node,
12645 opaque_V4SI_type_node,
12650 enum insn_code icode = d->icode;
12651 if (d->name == 0 || icode == CODE_FOR_nothing)
12654 type = builtin_function_type (insn_data[icode].operand[0].mode,
12655 insn_data[icode].operand[1].mode,
12656 insn_data[icode].operand[2].mode,
12657 insn_data[icode].operand[3].mode,
12661 def_builtin (d->name, type, d->code);
12664 /* Add the binary operators. */
12666 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12668 enum machine_mode mode0, mode1, mode2;
12670 unsigned mask = d->mask;
12672 if ((mask & builtin_mask) != mask)
12674 if (TARGET_DEBUG_BUILTIN)
12675 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
12679 if (rs6000_overloaded_builtin_p (d->code))
12681 if (! (type = opaque_ftype_opaque_opaque))
12682 type = opaque_ftype_opaque_opaque
12683 = build_function_type_list (opaque_V4SI_type_node,
12684 opaque_V4SI_type_node,
12685 opaque_V4SI_type_node,
12690 enum insn_code icode = d->icode;
12691 if (d->name == 0 || icode == CODE_FOR_nothing)
12694 mode0 = insn_data[icode].operand[0].mode;
12695 mode1 = insn_data[icode].operand[1].mode;
12696 mode2 = insn_data[icode].operand[2].mode;
12698 if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
12700 if (! (type = v2si_ftype_v2si_qi))
12701 type = v2si_ftype_v2si_qi
12702 = build_function_type_list (opaque_V2SI_type_node,
12703 opaque_V2SI_type_node,
12708 else if (mode0 == V2SImode && GET_MODE_CLASS (mode1) == MODE_INT
12709 && mode2 == QImode)
12711 if (! (type = v2si_ftype_int_qi))
12712 type = v2si_ftype_int_qi
12713 = build_function_type_list (opaque_V2SI_type_node,
12720 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
12724 def_builtin (d->name, type, d->code);
12727 /* Add the simple unary operators. */
12729 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12731 enum machine_mode mode0, mode1;
12733 unsigned mask = d->mask;
12735 if ((mask & builtin_mask) != mask)
12737 if (TARGET_DEBUG_BUILTIN)
12738 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
12742 if (rs6000_overloaded_builtin_p (d->code))
12744 if (! (type = opaque_ftype_opaque))
12745 type = opaque_ftype_opaque
12746 = build_function_type_list (opaque_V4SI_type_node,
12747 opaque_V4SI_type_node,
12752 enum insn_code icode = d->icode;
12753 if (d->name == 0 || icode == CODE_FOR_nothing)
12756 mode0 = insn_data[icode].operand[0].mode;
12757 mode1 = insn_data[icode].operand[1].mode;
12759 if (mode0 == V2SImode && mode1 == QImode)
12761 if (! (type = v2si_ftype_qi))
12762 type = v2si_ftype_qi
12763 = build_function_type_list (opaque_V2SI_type_node,
12769 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
12773 def_builtin (d->name, type, d->code);
12778 rs6000_init_libfuncs (void)
12780 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
12781 && !TARGET_POWER2 && !TARGET_POWERPC)
12783 /* AIX library routines for float->int conversion. */
12784 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
12785 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
12786 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
12787 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
12790 if (!TARGET_IEEEQUAD)
12791 /* AIX/Darwin/64-bit Linux quad floating point routines. */
12792 if (!TARGET_XL_COMPAT)
12794 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
12795 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
12796 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
12797 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
12799 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
12801 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
12802 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
12803 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
12804 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
12805 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
12806 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
12807 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
12809 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
12810 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
12811 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
12812 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
12813 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
12814 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
12815 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
12816 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
12819 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
12820 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
12824 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
12825 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
12826 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
12827 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
12831 /* 32-bit SVR4 quad floating point routines. */
12833 set_optab_libfunc (add_optab, TFmode, "_q_add");
12834 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
12835 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
12836 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
12837 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
12838 if (TARGET_PPC_GPOPT || TARGET_POWER2)
12839 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
12841 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
12842 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
12843 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
12844 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
12845 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
12846 set_optab_libfunc (le_optab, TFmode, "_q_fle");
12848 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
12849 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
12850 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
12851 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
12852 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
12853 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
12854 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
12855 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
12860 /* Expand a block clear operation, and return 1 if successful. Return 0
12861 if we should let the compiler generate normal code.
12863 operands[0] is the destination
12864 operands[1] is the length
12865 operands[3] is the alignment */
12868 expand_block_clear (rtx operands[])
12870 rtx orig_dest = operands[0];
12871 rtx bytes_rtx = operands[1];
12872 rtx align_rtx = operands[3];
12873 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
12874 HOST_WIDE_INT align;
12875 HOST_WIDE_INT bytes;
12880 /* If this is not a fixed size move, just call memcpy */
12884 /* This must be a fixed size alignment */
12885 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
12886 align = INTVAL (align_rtx) * BITS_PER_UNIT;
12888 /* Anything to clear? */
12889 bytes = INTVAL (bytes_rtx);
12893 /* Use the builtin memset after a point, to avoid huge code bloat.
12894 When optimize_size, avoid any significant code bloat; calling
12895 memset is about 4 instructions, so allow for one instruction to
12896 load zero and three to do clearing. */
12897 if (TARGET_ALTIVEC && align >= 128)
12899 else if (TARGET_POWERPC64 && align >= 32)
12901 else if (TARGET_SPE && align >= 64)
12906 if (optimize_size && bytes > 3 * clear_step)
12908 if (! optimize_size && bytes > 8 * clear_step)
12911 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
12913 enum machine_mode mode = BLKmode;
12916 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
12921 else if (bytes >= 8 && TARGET_SPE && align >= 64)
12926 else if (bytes >= 8 && TARGET_POWERPC64
12927 /* 64-bit loads and stores require word-aligned
12929 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
12934 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
12935 { /* move 4 bytes */
12939 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
12940 { /* move 2 bytes */
12944 else /* move 1 byte at a time */
12950 dest = adjust_address (orig_dest, mode, offset);
12952 emit_move_insn (dest, CONST0_RTX (mode));
12959 /* Expand a block move operation, and return 1 if successful. Return 0
12960 if we should let the compiler generate normal code.
12962 operands[0] is the destination
12963 operands[1] is the source
12964 operands[2] is the length
12965 operands[3] is the alignment */
12967 #define MAX_MOVE_REG 4
12970 expand_block_move (rtx operands[])
12972 rtx orig_dest = operands[0];
12973 rtx orig_src = operands[1];
12974 rtx bytes_rtx = operands[2];
12975 rtx align_rtx = operands[3];
12976 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
12981 rtx stores[MAX_MOVE_REG];
12984 /* If this is not a fixed size move, just call memcpy */
12988 /* This must be a fixed size alignment */
12989 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
12990 align = INTVAL (align_rtx) * BITS_PER_UNIT;
12992 /* Anything to move? */
12993 bytes = INTVAL (bytes_rtx);
12997 if (bytes > rs6000_block_move_inline_limit)
13000 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
13003 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
13004 rtx (*mov) (rtx, rtx);
13006 enum machine_mode mode = BLKmode;
13009 /* Altivec first, since it will be faster than a string move
13010 when it applies, and usually not significantly larger. */
13011 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
13015 gen_func.mov = gen_movv4si;
13017 else if (TARGET_SPE && bytes >= 8 && align >= 64)
13021 gen_func.mov = gen_movv2si;
13023 else if (TARGET_STRING
13024 && bytes > 24 /* move up to 32 bytes at a time */
13030 && ! fixed_regs[10]
13031 && ! fixed_regs[11]
13032 && ! fixed_regs[12])
13034 move_bytes = (bytes > 32) ? 32 : bytes;
13035 gen_func.movmemsi = gen_movmemsi_8reg;
13037 else if (TARGET_STRING
13038 && bytes > 16 /* move up to 24 bytes at a time */
13044 && ! fixed_regs[10])
13046 move_bytes = (bytes > 24) ? 24 : bytes;
13047 gen_func.movmemsi = gen_movmemsi_6reg;
13049 else if (TARGET_STRING
13050 && bytes > 8 /* move up to 16 bytes at a time */
13054 && ! fixed_regs[8])
13056 move_bytes = (bytes > 16) ? 16 : bytes;
13057 gen_func.movmemsi = gen_movmemsi_4reg;
13059 else if (bytes >= 8 && TARGET_POWERPC64
13060 /* 64-bit loads and stores require word-aligned
13062 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
13066 gen_func.mov = gen_movdi;
13068 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
13069 { /* move up to 8 bytes at a time */
13070 move_bytes = (bytes > 8) ? 8 : bytes;
13071 gen_func.movmemsi = gen_movmemsi_2reg;
13073 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
13074 { /* move 4 bytes */
13077 gen_func.mov = gen_movsi;
13079 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
13080 { /* move 2 bytes */
13083 gen_func.mov = gen_movhi;
13085 else if (TARGET_STRING && bytes > 1)
13086 { /* move up to 4 bytes at a time */
13087 move_bytes = (bytes > 4) ? 4 : bytes;
13088 gen_func.movmemsi = gen_movmemsi_1reg;
13090 else /* move 1 byte at a time */
13094 gen_func.mov = gen_movqi;
13097 src = adjust_address (orig_src, mode, offset);
13098 dest = adjust_address (orig_dest, mode, offset);
13100 if (mode != BLKmode)
13102 rtx tmp_reg = gen_reg_rtx (mode);
13104 emit_insn ((*gen_func.mov) (tmp_reg, src));
13105 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
13108 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
13111 for (i = 0; i < num_reg; i++)
13112 emit_insn (stores[i]);
13116 if (mode == BLKmode)
13118 /* Move the address into scratch registers. The movmemsi
13119 patterns require zero offset. */
13120 if (!REG_P (XEXP (src, 0)))
13122 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
13123 src = replace_equiv_address (src, src_reg);
13125 set_mem_size (src, move_bytes);
13127 if (!REG_P (XEXP (dest, 0)))
13129 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
13130 dest = replace_equiv_address (dest, dest_reg);
13132 set_mem_size (dest, move_bytes);
13134 emit_insn ((*gen_func.movmemsi) (dest, src,
13135 GEN_INT (move_bytes & 31),
13144 /* Return a string to perform a load_multiple operation.
13145 operands[0] is the vector.
13146 operands[1] is the source address.
13147 operands[2] is the first destination register. */
13150 rs6000_output_load_multiple (rtx operands[3])
13152 /* We have to handle the case where the pseudo used to contain the address
13153 is assigned to one of the output registers. */
13155 int words = XVECLEN (operands[0], 0);
13158 if (XVECLEN (operands[0], 0) == 1)
13159 return "{l|lwz} %2,0(%1)";
13161 for (i = 0; i < words; i++)
13162 if (refers_to_regno_p (REGNO (operands[2]) + i,
13163 REGNO (operands[2]) + i + 1, operands[1], 0))
13167 xop[0] = GEN_INT (4 * (words-1));
13168 xop[1] = operands[1];
13169 xop[2] = operands[2];
13170 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
13175 xop[0] = GEN_INT (4 * (words-1));
13176 xop[1] = operands[1];
13177 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
13178 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
13183 for (j = 0; j < words; j++)
13186 xop[0] = GEN_INT (j * 4);
13187 xop[1] = operands[1];
13188 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
13189 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
13191 xop[0] = GEN_INT (i * 4);
13192 xop[1] = operands[1];
13193 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
13198 return "{lsi|lswi} %2,%1,%N0";
13202 /* A validation routine: say whether CODE, a condition code, and MODE
13203 match. The other alternatives either don't make sense or should
13204 never be generated. */
13207 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
13209 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
13210 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
13211 && GET_MODE_CLASS (mode) == MODE_CC);
13213 /* These don't make sense. */
13214 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
13215 || mode != CCUNSmode);
13217 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
13218 || mode == CCUNSmode);
13220 gcc_assert (mode == CCFPmode
13221 || (code != ORDERED && code != UNORDERED
13222 && code != UNEQ && code != LTGT
13223 && code != UNGT && code != UNLT
13224 && code != UNGE && code != UNLE));
13226 /* These should never be generated except for
13227 flag_finite_math_only. */
13228 gcc_assert (mode != CCFPmode
13229 || flag_finite_math_only
13230 || (code != LE && code != GE
13231 && code != UNEQ && code != LTGT
13232 && code != UNGT && code != UNLT));
13234 /* These are invalid; the information is not there. */
13235 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
13239 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
13240 mask required to convert the result of a rotate insn into a shift
13241 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
13244 includes_lshift_p (rtx shiftop, rtx andop)
13246 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
13248 shift_mask <<= INTVAL (shiftop);
13250 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
13253 /* Similar, but for right shift. */
13256 includes_rshift_p (rtx shiftop, rtx andop)
13258 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
13260 shift_mask >>= INTVAL (shiftop);
13262 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
13265 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
13266 to perform a left shift. It must have exactly SHIFTOP least
13267 significant 0's, then one or more 1's, then zero or more 0's. */
13270 includes_rldic_lshift_p (rtx shiftop, rtx andop)
13272 if (GET_CODE (andop) == CONST_INT)
13274 HOST_WIDE_INT c, lsb, shift_mask;
13276 c = INTVAL (andop);
13277 if (c == 0 || c == ~0)
13281 shift_mask <<= INTVAL (shiftop);
13283 /* Find the least significant one bit. */
13286 /* It must coincide with the LSB of the shift mask. */
13287 if (-lsb != shift_mask)
13290 /* Invert to look for the next transition (if any). */
13293 /* Remove the low group of ones (originally low group of zeros). */
13296 /* Again find the lsb, and check we have all 1's above. */
13300 else if (GET_CODE (andop) == CONST_DOUBLE
13301 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
13303 HOST_WIDE_INT low, high, lsb;
13304 HOST_WIDE_INT shift_mask_low, shift_mask_high;
13306 low = CONST_DOUBLE_LOW (andop);
13307 if (HOST_BITS_PER_WIDE_INT < 64)
13308 high = CONST_DOUBLE_HIGH (andop);
13310 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
13311 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
13314 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
13316 shift_mask_high = ~0;
13317 if (INTVAL (shiftop) > 32)
13318 shift_mask_high <<= INTVAL (shiftop) - 32;
13320 lsb = high & -high;
13322 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
13328 lsb = high & -high;
13329 return high == -lsb;
13332 shift_mask_low = ~0;
13333 shift_mask_low <<= INTVAL (shiftop);
13337 if (-lsb != shift_mask_low)
13340 if (HOST_BITS_PER_WIDE_INT < 64)
13345 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
13347 lsb = high & -high;
13348 return high == -lsb;
13352 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
13358 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
13359 to perform a left shift. It must have SHIFTOP or more least
13360 significant 0's, with the remainder of the word 1's. */
13363 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
13365 if (GET_CODE (andop) == CONST_INT)
13367 HOST_WIDE_INT c, lsb, shift_mask;
13370 shift_mask <<= INTVAL (shiftop);
13371 c = INTVAL (andop);
13373 /* Find the least significant one bit. */
13376 /* It must be covered by the shift mask.
13377 This test also rejects c == 0. */
13378 if ((lsb & shift_mask) == 0)
13381 /* Check we have all 1's above the transition, and reject all 1's. */
13382 return c == -lsb && lsb != 1;
13384 else if (GET_CODE (andop) == CONST_DOUBLE
13385 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
13387 HOST_WIDE_INT low, lsb, shift_mask_low;
13389 low = CONST_DOUBLE_LOW (andop);
13391 if (HOST_BITS_PER_WIDE_INT < 64)
13393 HOST_WIDE_INT high, shift_mask_high;
13395 high = CONST_DOUBLE_HIGH (andop);
13399 shift_mask_high = ~0;
13400 if (INTVAL (shiftop) > 32)
13401 shift_mask_high <<= INTVAL (shiftop) - 32;
13403 lsb = high & -high;
13405 if ((lsb & shift_mask_high) == 0)
13408 return high == -lsb;
13414 shift_mask_low = ~0;
13415 shift_mask_low <<= INTVAL (shiftop);
13419 if ((lsb & shift_mask_low) == 0)
13422 return low == -lsb && lsb != 1;
13428 /* Return 1 if operands will generate a valid arguments to rlwimi
13429 instruction for insert with right shift in 64-bit mode. The mask may
13430 not start on the first bit or stop on the last bit because wrap-around
13431 effects of instruction do not correspond to semantics of RTL insn. */
13434 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
13436 if (INTVAL (startop) > 32
13437 && INTVAL (startop) < 64
13438 && INTVAL (sizeop) > 1
13439 && INTVAL (sizeop) + INTVAL (startop) < 64
13440 && INTVAL (shiftop) > 0
13441 && INTVAL (sizeop) + INTVAL (shiftop) < 32
13442 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
13448 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
13449 for lfq and stfq insns iff the registers are hard registers. */
13452 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
13454 /* We might have been passed a SUBREG. */
13455 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
13458 /* We might have been passed non floating point registers. */
13459 if (!FP_REGNO_P (REGNO (reg1))
13460 || !FP_REGNO_P (REGNO (reg2)))
13463 return (REGNO (reg1) == REGNO (reg2) - 1);
13466 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
13467 addr1 and addr2 must be in consecutive memory locations
13468 (addr2 == addr1 + 8). */
13471 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
13474 unsigned int reg1, reg2;
13475 int offset1, offset2;
13477 /* The mems cannot be volatile. */
13478 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
13481 addr1 = XEXP (mem1, 0);
13482 addr2 = XEXP (mem2, 0);
13484 /* Extract an offset (if used) from the first addr. */
13485 if (GET_CODE (addr1) == PLUS)
13487 /* If not a REG, return zero. */
13488 if (GET_CODE (XEXP (addr1, 0)) != REG)
13492 reg1 = REGNO (XEXP (addr1, 0));
13493 /* The offset must be constant! */
13494 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
13496 offset1 = INTVAL (XEXP (addr1, 1));
13499 else if (GET_CODE (addr1) != REG)
13503 reg1 = REGNO (addr1);
13504 /* This was a simple (mem (reg)) expression. Offset is 0. */
13508 /* And now for the second addr. */
13509 if (GET_CODE (addr2) == PLUS)
13511 /* If not a REG, return zero. */
13512 if (GET_CODE (XEXP (addr2, 0)) != REG)
13516 reg2 = REGNO (XEXP (addr2, 0));
13517 /* The offset must be constant. */
13518 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
13520 offset2 = INTVAL (XEXP (addr2, 1));
13523 else if (GET_CODE (addr2) != REG)
13527 reg2 = REGNO (addr2);
13528 /* This was a simple (mem (reg)) expression. Offset is 0. */
13532 /* Both of these must have the same base register. */
13536 /* The offset for the second addr must be 8 more than the first addr. */
13537 if (offset2 != offset1 + 8)
13540 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
13547 rs6000_secondary_memory_needed_rtx (enum machine_mode mode)
13549 static bool eliminated = false;
13552 if (mode != SDmode)
13553 ret = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
13556 rtx mem = cfun->machine->sdmode_stack_slot;
13557 gcc_assert (mem != NULL_RTX);
13561 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
13562 cfun->machine->sdmode_stack_slot = mem;
13568 if (TARGET_DEBUG_ADDR)
13570 fprintf (stderr, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
13571 GET_MODE_NAME (mode));
13573 fprintf (stderr, "\tNULL_RTX\n");
13582 rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)
13584 /* Don't walk into types. */
13585 if (*tp == NULL_TREE || *tp == error_mark_node || TYPE_P (*tp))
13587 *walk_subtrees = 0;
13591 switch (TREE_CODE (*tp))
13600 case VIEW_CONVERT_EXPR:
13601 if (TYPE_MODE (TREE_TYPE (*tp)) == SDmode)
13611 enum reload_reg_type {
13613 VECTOR_REGISTER_TYPE,
13614 OTHER_REGISTER_TYPE
13617 static enum reload_reg_type
13618 rs6000_reload_register_type (enum reg_class rclass)
13624 return GPR_REGISTER_TYPE;
13629 return VECTOR_REGISTER_TYPE;
13632 return OTHER_REGISTER_TYPE;
13636 /* Inform reload about cases where moving X with a mode MODE to a register in
13637 RCLASS requires an extra scratch or immediate register. Return the class
13638 needed for the immediate register.
13640 For VSX and Altivec, we may need a register to convert sp+offset into
13643 For misaligned 64-bit gpr loads and stores we need a register to
13644 convert an offset address to indirect. */
13647 rs6000_secondary_reload (bool in_p,
13649 reg_class_t rclass_i,
13650 enum machine_mode mode,
13651 secondary_reload_info *sri)
13653 enum reg_class rclass = (enum reg_class) rclass_i;
13654 reg_class_t ret = ALL_REGS;
13655 enum insn_code icode;
13656 bool default_p = false;
13658 sri->icode = CODE_FOR_nothing;
13660 /* Convert vector loads and stores into gprs to use an additional base
13662 icode = rs6000_vector_reload[mode][in_p != false];
13663 if (icode != CODE_FOR_nothing)
13666 sri->icode = CODE_FOR_nothing;
13667 sri->extra_cost = 0;
13669 if (GET_CODE (x) == MEM)
13671 rtx addr = XEXP (x, 0);
13673 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
13674 an extra register in that case, but it would need an extra
13675 register if the addressing is reg+reg or (reg+reg)&(-16). */
13676 if (rclass == GENERAL_REGS || rclass == BASE_REGS)
13678 if (!legitimate_indirect_address_p (addr, false)
13679 && !rs6000_legitimate_offset_address_p (TImode, addr, false))
13681 sri->icode = icode;
13682 /* account for splitting the loads, and converting the
13683 address from reg+reg to reg. */
13684 sri->extra_cost = (((TARGET_64BIT) ? 3 : 5)
13685 + ((GET_CODE (addr) == AND) ? 1 : 0));
13688 /* Loads to and stores from vector registers can only do reg+reg
13689 addressing. Altivec registers can also do (reg+reg)&(-16). */
13690 else if (rclass == VSX_REGS || rclass == ALTIVEC_REGS
13691 || rclass == FLOAT_REGS || rclass == NO_REGS)
13693 if (!VECTOR_MEM_ALTIVEC_P (mode)
13694 && GET_CODE (addr) == AND
13695 && GET_CODE (XEXP (addr, 1)) == CONST_INT
13696 && INTVAL (XEXP (addr, 1)) == -16
13697 && (legitimate_indirect_address_p (XEXP (addr, 0), false)
13698 || legitimate_indexed_address_p (XEXP (addr, 0), false)))
13700 sri->icode = icode;
13701 sri->extra_cost = ((GET_CODE (XEXP (addr, 0)) == PLUS)
13704 else if (!legitimate_indirect_address_p (addr, false)
13705 && (rclass == NO_REGS
13706 || !legitimate_indexed_address_p (addr, false)))
13708 sri->icode = icode;
13709 sri->extra_cost = 1;
13712 icode = CODE_FOR_nothing;
13714 /* Any other loads, including to pseudo registers which haven't been
13715 assigned to a register yet, default to require a scratch
13719 sri->icode = icode;
13720 sri->extra_cost = 2;
13723 else if (REG_P (x))
13725 int regno = true_regnum (x);
13727 icode = CODE_FOR_nothing;
13728 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
13732 enum reg_class xclass = REGNO_REG_CLASS (regno);
13733 enum reload_reg_type rtype1 = rs6000_reload_register_type (rclass);
13734 enum reload_reg_type rtype2 = rs6000_reload_register_type (xclass);
13736 /* If memory is needed, use default_secondary_reload to create the
13738 if (rtype1 != rtype2 || rtype1 == OTHER_REGISTER_TYPE)
13747 else if (TARGET_POWERPC64
13748 && rs6000_reload_register_type (rclass) == GPR_REGISTER_TYPE
13750 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
13752 rtx addr = XEXP (x, 0);
13754 if (GET_CODE (addr) == PRE_MODIFY)
13755 addr = XEXP (addr, 1);
13756 else if (GET_CODE (addr) == LO_SUM
13757 && GET_CODE (XEXP (addr, 0)) == REG
13758 && GET_CODE (XEXP (addr, 1)) == CONST)
13759 addr = XEXP (XEXP (addr, 1), 0);
13761 if (GET_CODE (addr) == PLUS
13762 && GET_CODE (XEXP (addr, 1)) == CONST_INT
13763 && (INTVAL (XEXP (addr, 1)) & 3) != 0)
13766 sri->icode = CODE_FOR_reload_di_load;
13768 sri->icode = CODE_FOR_reload_di_store;
13769 sri->extra_cost = 2;
13779 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
13781 gcc_assert (ret != ALL_REGS);
13783 if (TARGET_DEBUG_ADDR)
13786 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
13788 reg_class_names[ret],
13789 in_p ? "true" : "false",
13790 reg_class_names[rclass],
13791 GET_MODE_NAME (mode));
13794 fprintf (stderr, ", default secondary reload");
13796 if (sri->icode != CODE_FOR_nothing)
13797 fprintf (stderr, ", reload func = %s, extra cost = %d\n",
13798 insn_data[sri->icode].name, sri->extra_cost);
13800 fprintf (stderr, "\n");
13808 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
13809 to SP+reg addressing. */
13812 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
13814 int regno = true_regnum (reg);
13815 enum machine_mode mode = GET_MODE (reg);
13816 enum reg_class rclass;
13818 rtx and_op2 = NULL_RTX;
13821 rtx scratch_or_premodify = scratch;
13825 if (TARGET_DEBUG_ADDR)
13827 fprintf (stderr, "\nrs6000_secondary_reload_inner, type = %s\n",
13828 store_p ? "store" : "load");
13829 fprintf (stderr, "reg:\n");
13831 fprintf (stderr, "mem:\n");
13833 fprintf (stderr, "scratch:\n");
13834 debug_rtx (scratch);
13837 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
13838 gcc_assert (GET_CODE (mem) == MEM);
13839 rclass = REGNO_REG_CLASS (regno);
13840 addr = XEXP (mem, 0);
13844 /* GPRs can handle reg + small constant, all other addresses need to use
13845 the scratch register. */
13848 if (GET_CODE (addr) == AND)
13850 and_op2 = XEXP (addr, 1);
13851 addr = XEXP (addr, 0);
13854 if (GET_CODE (addr) == PRE_MODIFY)
13856 scratch_or_premodify = XEXP (addr, 0);
13857 gcc_assert (REG_P (scratch_or_premodify));
13858 gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);
13859 addr = XEXP (addr, 1);
13862 if (GET_CODE (addr) == PLUS
13863 && (!rs6000_legitimate_offset_address_p (TImode, addr, false)
13864 || and_op2 != NULL_RTX))
13866 addr_op1 = XEXP (addr, 0);
13867 addr_op2 = XEXP (addr, 1);
13868 gcc_assert (legitimate_indirect_address_p (addr_op1, false));
13870 if (!REG_P (addr_op2)
13871 && (GET_CODE (addr_op2) != CONST_INT
13872 || !satisfies_constraint_I (addr_op2)))
13874 if (TARGET_DEBUG_ADDR)
13877 "\nMove plus addr to register %s, mode = %s: ",
13878 rs6000_reg_names[REGNO (scratch)],
13879 GET_MODE_NAME (mode));
13880 debug_rtx (addr_op2);
13882 rs6000_emit_move (scratch, addr_op2, Pmode);
13883 addr_op2 = scratch;
13886 emit_insn (gen_rtx_SET (VOIDmode,
13887 scratch_or_premodify,
13888 gen_rtx_PLUS (Pmode,
13892 addr = scratch_or_premodify;
13893 scratch_or_premodify = scratch;
13895 else if (!legitimate_indirect_address_p (addr, false)
13896 && !rs6000_legitimate_offset_address_p (TImode, addr, false))
13898 if (TARGET_DEBUG_ADDR)
13900 fprintf (stderr, "\nMove addr to register %s, mode = %s: ",
13901 rs6000_reg_names[REGNO (scratch_or_premodify)],
13902 GET_MODE_NAME (mode));
13905 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
13906 addr = scratch_or_premodify;
13907 scratch_or_premodify = scratch;
13911 /* Float/Altivec registers can only handle reg+reg addressing. Move
13912 other addresses into a scratch register. */
13917 /* With float regs, we need to handle the AND ourselves, since we can't
13918 use the Altivec instruction with an implicit AND -16. Allow scalar
13919 loads to float registers to use reg+offset even if VSX. */
13920 if (GET_CODE (addr) == AND
13921 && (rclass != ALTIVEC_REGS || GET_MODE_SIZE (mode) != 16
13922 || GET_CODE (XEXP (addr, 1)) != CONST_INT
13923 || INTVAL (XEXP (addr, 1)) != -16
13924 || !VECTOR_MEM_ALTIVEC_P (mode)))
13926 and_op2 = XEXP (addr, 1);
13927 addr = XEXP (addr, 0);
13930 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
13931 as the address later. */
13932 if (GET_CODE (addr) == PRE_MODIFY
13933 && (!VECTOR_MEM_VSX_P (mode)
13934 || and_op2 != NULL_RTX
13935 || !legitimate_indexed_address_p (XEXP (addr, 1), false)))
13937 scratch_or_premodify = XEXP (addr, 0);
13938 gcc_assert (legitimate_indirect_address_p (scratch_or_premodify,
13940 gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);
13941 addr = XEXP (addr, 1);
13944 if (legitimate_indirect_address_p (addr, false) /* reg */
13945 || legitimate_indexed_address_p (addr, false) /* reg+reg */
13946 || GET_CODE (addr) == PRE_MODIFY /* VSX pre-modify */
13947 || (GET_CODE (addr) == AND /* Altivec memory */
13948 && GET_CODE (XEXP (addr, 1)) == CONST_INT
13949 && INTVAL (XEXP (addr, 1)) == -16
13950 && VECTOR_MEM_ALTIVEC_P (mode))
13951 || (rclass == FLOAT_REGS /* legacy float mem */
13952 && GET_MODE_SIZE (mode) == 8
13953 && and_op2 == NULL_RTX
13954 && scratch_or_premodify == scratch
13955 && rs6000_legitimate_offset_address_p (mode, addr, false)))
13958 else if (GET_CODE (addr) == PLUS)
13960 addr_op1 = XEXP (addr, 0);
13961 addr_op2 = XEXP (addr, 1);
13962 gcc_assert (REG_P (addr_op1));
13964 if (TARGET_DEBUG_ADDR)
13966 fprintf (stderr, "\nMove plus addr to register %s, mode = %s: ",
13967 rs6000_reg_names[REGNO (scratch)], GET_MODE_NAME (mode));
13968 debug_rtx (addr_op2);
13970 rs6000_emit_move (scratch, addr_op2, Pmode);
13971 emit_insn (gen_rtx_SET (VOIDmode,
13972 scratch_or_premodify,
13973 gen_rtx_PLUS (Pmode,
13976 addr = scratch_or_premodify;
13977 scratch_or_premodify = scratch;
13980 else if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == CONST
13981 || GET_CODE (addr) == CONST_INT || REG_P (addr))
13983 if (TARGET_DEBUG_ADDR)
13985 fprintf (stderr, "\nMove addr to register %s, mode = %s: ",
13986 rs6000_reg_names[REGNO (scratch_or_premodify)],
13987 GET_MODE_NAME (mode));
13991 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
13992 addr = scratch_or_premodify;
13993 scratch_or_premodify = scratch;
13997 gcc_unreachable ();
14002 gcc_unreachable ();
14005 /* If the original address involved a pre-modify that we couldn't use the VSX
14006 memory instruction with update, and we haven't taken care of already,
14007 store the address in the pre-modify register and use that as the
14009 if (scratch_or_premodify != scratch && scratch_or_premodify != addr)
14011 emit_insn (gen_rtx_SET (VOIDmode, scratch_or_premodify, addr));
14012 addr = scratch_or_premodify;
14015 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
14016 memory instruction, recreate the AND now, including the clobber which is
14017 generated by the general ANDSI3/ANDDI3 patterns for the
14018 andi. instruction. */
14019 if (and_op2 != NULL_RTX)
14021 if (! legitimate_indirect_address_p (addr, false))
14023 emit_insn (gen_rtx_SET (VOIDmode, scratch, addr));
14027 if (TARGET_DEBUG_ADDR)
14029 fprintf (stderr, "\nAnd addr to register %s, mode = %s: ",
14030 rs6000_reg_names[REGNO (scratch)], GET_MODE_NAME (mode));
14031 debug_rtx (and_op2);
14034 and_rtx = gen_rtx_SET (VOIDmode,
14036 gen_rtx_AND (Pmode,
14040 cc_clobber = gen_rtx_CLOBBER (CCmode, gen_rtx_SCRATCH (CCmode));
14041 emit_insn (gen_rtx_PARALLEL (VOIDmode,
14042 gen_rtvec (2, and_rtx, cc_clobber)));
14046 /* Adjust the address if it changed. */
14047 if (addr != XEXP (mem, 0))
14049 mem = change_address (mem, mode, addr);
14050 if (TARGET_DEBUG_ADDR)
14051 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
14054 /* Now create the move. */
14056 emit_insn (gen_rtx_SET (VOIDmode, mem, reg));
14058 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
14063 /* Convert reloads involving 64-bit gprs and misaligned offset
14064 addressing to use indirect addressing. */
14067 rs6000_secondary_reload_ppc64 (rtx reg, rtx mem, rtx scratch, bool store_p)
14069 int regno = true_regnum (reg);
14070 enum reg_class rclass;
14072 rtx scratch_or_premodify = scratch;
14074 if (TARGET_DEBUG_ADDR)
14076 fprintf (stderr, "\nrs6000_secondary_reload_ppc64, type = %s\n",
14077 store_p ? "store" : "load");
14078 fprintf (stderr, "reg:\n");
14080 fprintf (stderr, "mem:\n");
14082 fprintf (stderr, "scratch:\n");
14083 debug_rtx (scratch);
14086 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
14087 gcc_assert (GET_CODE (mem) == MEM);
14088 rclass = REGNO_REG_CLASS (regno);
14089 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
14090 addr = XEXP (mem, 0);
14092 if (GET_CODE (addr) == PRE_MODIFY)
14094 scratch_or_premodify = XEXP (addr, 0);
14095 gcc_assert (REG_P (scratch_or_premodify));
14096 addr = XEXP (addr, 1);
14098 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
14100 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
14102 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
14104 /* Now create the move. */
14106 emit_insn (gen_rtx_SET (VOIDmode, mem, reg));
14108 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
14113 /* Allocate a 64-bit stack slot to be used for copying SDmode
14114 values through if this function has any SDmode references. */
14117 rs6000_alloc_sdmode_stack_slot (void)
14121 gimple_stmt_iterator gsi;
14123 gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX);
14126 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
14128 tree ret = walk_gimple_op (gsi_stmt (gsi), rs6000_check_sdmode, NULL);
14131 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
14132 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
14138 /* Check for any SDmode parameters of the function. */
14139 for (t = DECL_ARGUMENTS (cfun->decl); t; t = DECL_CHAIN (t))
14141 if (TREE_TYPE (t) == error_mark_node)
14144 if (TYPE_MODE (TREE_TYPE (t)) == SDmode
14145 || TYPE_MODE (DECL_ARG_TYPE (t)) == SDmode)
14147 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
14148 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
14156 rs6000_instantiate_decls (void)
14158 if (cfun->machine->sdmode_stack_slot != NULL_RTX)
14159 instantiate_decl_rtl (cfun->machine->sdmode_stack_slot);
14162 /* Given an rtx X being reloaded into a reg required to be
14163 in class CLASS, return the class of reg to actually use.
14164 In general this is just CLASS; but on some machines
14165 in some cases it is preferable to use a more restrictive class.
14167 On the RS/6000, we have to return NO_REGS when we want to reload a
14168 floating-point CONST_DOUBLE to force it to be copied to memory.
14170 We also don't want to reload integer values into floating-point
14171 registers if we can at all help it. In fact, this can
14172 cause reload to die, if it tries to generate a reload of CTR
14173 into a FP register and discovers it doesn't have the memory location
14176 ??? Would it be a good idea to have reload do the converse, that is
14177 try to reload floating modes into FP registers if possible?
14180 static enum reg_class
14181 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
14183 enum machine_mode mode = GET_MODE (x);
14185 if (VECTOR_UNIT_VSX_P (mode)
14186 && x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
14189 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
14190 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
14191 && easy_vector_constant (x, mode))
14192 return ALTIVEC_REGS;
14194 if (CONSTANT_P (x) && reg_classes_intersect_p (rclass, FLOAT_REGS))
14197 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
14198 return GENERAL_REGS;
14200 /* For VSX, prefer the traditional registers for 64-bit values because we can
14201 use the non-VSX loads. Prefer the Altivec registers if Altivec is
14202 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
14203 prefer Altivec loads.. */
14204 if (rclass == VSX_REGS)
14206 if (GET_MODE_SIZE (mode) <= 8)
14209 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode))
14210 return ALTIVEC_REGS;
14218 /* Debug version of rs6000_preferred_reload_class. */
14219 static enum reg_class
14220 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
14222 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
14225 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
14227 reg_class_names[ret], reg_class_names[rclass],
14228 GET_MODE_NAME (GET_MODE (x)));
14234 /* If we are copying between FP or AltiVec registers and anything else, we need
14235 a memory location. The exception is when we are targeting ppc64 and the
14236 move to/from fpr to gpr instructions are available. Also, under VSX, you
14237 can copy vector registers from the FP register set to the Altivec register
14238 set and vice versa. */
14241 rs6000_secondary_memory_needed (enum reg_class class1,
14242 enum reg_class class2,
14243 enum machine_mode mode)
14245 if (class1 == class2)
14248 /* Under VSX, there are 3 register classes that values could be in (VSX_REGS,
14249 ALTIVEC_REGS, and FLOAT_REGS). We don't need to use memory to copy
14250 between these classes. But we need memory for other things that can go in
14251 FLOAT_REGS like SFmode. */
14253 && (VECTOR_MEM_VSX_P (mode) || VECTOR_UNIT_VSX_P (mode))
14254 && (class1 == VSX_REGS || class1 == ALTIVEC_REGS
14255 || class1 == FLOAT_REGS))
14256 return (class2 != VSX_REGS && class2 != ALTIVEC_REGS
14257 && class2 != FLOAT_REGS);
14259 if (class1 == VSX_REGS || class2 == VSX_REGS)
14262 if (class1 == FLOAT_REGS
14263 && (!TARGET_MFPGPR || !TARGET_POWERPC64
14264 || ((mode != DFmode)
14265 && (mode != DDmode)
14266 && (mode != DImode))))
14269 if (class2 == FLOAT_REGS
14270 && (!TARGET_MFPGPR || !TARGET_POWERPC64
14271 || ((mode != DFmode)
14272 && (mode != DDmode)
14273 && (mode != DImode))))
14276 if (class1 == ALTIVEC_REGS || class2 == ALTIVEC_REGS)
14282 /* Debug version of rs6000_secondary_memory_needed. */
14284 rs6000_debug_secondary_memory_needed (enum reg_class class1,
14285 enum reg_class class2,
14286 enum machine_mode mode)
14288 bool ret = rs6000_secondary_memory_needed (class1, class2, mode);
14291 "rs6000_secondary_memory_needed, return: %s, class1 = %s, "
14292 "class2 = %s, mode = %s\n",
14293 ret ? "true" : "false", reg_class_names[class1],
14294 reg_class_names[class2], GET_MODE_NAME (mode));
14299 /* Return the register class of a scratch register needed to copy IN into
14300 or out of a register in RCLASS in MODE. If it can be done directly,
14301 NO_REGS is returned. */
14303 static enum reg_class
14304 rs6000_secondary_reload_class (enum reg_class rclass, enum machine_mode mode,
14309 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
14311 && MACHOPIC_INDIRECT
14315 /* We cannot copy a symbolic operand directly into anything
14316 other than BASE_REGS for TARGET_ELF. So indicate that a
14317 register from BASE_REGS is needed as an intermediate
14320 On Darwin, pic addresses require a load from memory, which
14321 needs a base register. */
14322 if (rclass != BASE_REGS
14323 && (GET_CODE (in) == SYMBOL_REF
14324 || GET_CODE (in) == HIGH
14325 || GET_CODE (in) == LABEL_REF
14326 || GET_CODE (in) == CONST))
14330 if (GET_CODE (in) == REG)
14332 regno = REGNO (in);
14333 if (regno >= FIRST_PSEUDO_REGISTER)
14335 regno = true_regnum (in);
14336 if (regno >= FIRST_PSEUDO_REGISTER)
14340 else if (GET_CODE (in) == SUBREG)
14342 regno = true_regnum (in);
14343 if (regno >= FIRST_PSEUDO_REGISTER)
14349 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
14351 if (rclass == GENERAL_REGS || rclass == BASE_REGS
14352 || (regno >= 0 && INT_REGNO_P (regno)))
14355 /* Constants, memory, and FP registers can go into FP registers. */
14356 if ((regno == -1 || FP_REGNO_P (regno))
14357 && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
14358 return (mode != SDmode) ? NO_REGS : GENERAL_REGS;
14360 /* Memory, and FP/altivec registers can go into fp/altivec registers under
14363 && (regno == -1 || VSX_REGNO_P (regno))
14364 && VSX_REG_CLASS_P (rclass))
14367 /* Memory, and AltiVec registers can go into AltiVec registers. */
14368 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
14369 && rclass == ALTIVEC_REGS)
14372 /* We can copy among the CR registers. */
14373 if ((rclass == CR_REGS || rclass == CR0_REGS)
14374 && regno >= 0 && CR_REGNO_P (regno))
14377 /* Otherwise, we need GENERAL_REGS. */
14378 return GENERAL_REGS;
14381 /* Debug version of rs6000_secondary_reload_class. */
14382 static enum reg_class
14383 rs6000_debug_secondary_reload_class (enum reg_class rclass,
14384 enum machine_mode mode, rtx in)
14386 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
14388 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
14389 "mode = %s, input rtx:\n",
14390 reg_class_names[ret], reg_class_names[rclass],
14391 GET_MODE_NAME (mode));
14397 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
14400 rs6000_cannot_change_mode_class (enum machine_mode from,
14401 enum machine_mode to,
14402 enum reg_class rclass)
14404 unsigned from_size = GET_MODE_SIZE (from);
14405 unsigned to_size = GET_MODE_SIZE (to);
14407 if (from_size != to_size)
14409 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
14410 return ((from_size < 8 || to_size < 8 || TARGET_IEEEQUAD)
14411 && reg_classes_intersect_p (xclass, rclass));
14414 if (TARGET_E500_DOUBLE
14415 && ((((to) == DFmode) + ((from) == DFmode)) == 1
14416 || (((to) == TFmode) + ((from) == TFmode)) == 1
14417 || (((to) == DDmode) + ((from) == DDmode)) == 1
14418 || (((to) == TDmode) + ((from) == TDmode)) == 1
14419 || (((to) == DImode) + ((from) == DImode)) == 1))
14422 /* Since the VSX register set includes traditional floating point registers
14423 and altivec registers, just check for the size being different instead of
14424 trying to check whether the modes are vector modes. Otherwise it won't
14425 allow say DF and DI to change classes. */
14426 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
14427 return (from_size != 8 && from_size != 16);
14429 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
14430 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
14433 if (TARGET_SPE && (SPE_VECTOR_MODE (from) + SPE_VECTOR_MODE (to)) == 1
14434 && reg_classes_intersect_p (GENERAL_REGS, rclass))
14440 /* Debug version of rs6000_cannot_change_mode_class. */
14442 rs6000_debug_cannot_change_mode_class (enum machine_mode from,
14443 enum machine_mode to,
14444 enum reg_class rclass)
14446 bool ret = rs6000_cannot_change_mode_class (from, to, rclass);
14449 "rs6000_cannot_change_mode_class, return %s, from = %s, "
14450 "to = %s, rclass = %s\n",
14451 ret ? "true" : "false",
14452 GET_MODE_NAME (from), GET_MODE_NAME (to),
14453 reg_class_names[rclass]);
14458 /* Given a comparison operation, return the bit number in CCR to test. We
14459 know this is a valid comparison.
14461 SCC_P is 1 if this is for an scc. That means that %D will have been
14462 used instead of %C, so the bits will be in different places.
14464 Return -1 if OP isn't a valid comparison for some reason. */
14467 ccr_bit (rtx op, int scc_p)
14469 enum rtx_code code = GET_CODE (op);
14470 enum machine_mode cc_mode;
14475 if (!COMPARISON_P (op))
14478 reg = XEXP (op, 0);
14480 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
14482 cc_mode = GET_MODE (reg);
14483 cc_regnum = REGNO (reg);
14484 base_bit = 4 * (cc_regnum - CR0_REGNO);
14486 validate_condition_mode (code, cc_mode);
14488 /* When generating a sCOND operation, only positive conditions are
14491 || code == EQ || code == GT || code == LT || code == UNORDERED
14492 || code == GTU || code == LTU);
14497 return scc_p ? base_bit + 3 : base_bit + 2;
14499 return base_bit + 2;
14500 case GT: case GTU: case UNLE:
14501 return base_bit + 1;
14502 case LT: case LTU: case UNGE:
14504 case ORDERED: case UNORDERED:
14505 return base_bit + 3;
14508 /* If scc, we will have done a cror to put the bit in the
14509 unordered position. So test that bit. For integer, this is ! LT
14510 unless this is an scc insn. */
14511 return scc_p ? base_bit + 3 : base_bit;
14514 return scc_p ? base_bit + 3 : base_bit + 1;
14517 gcc_unreachable ();
14521 /* Return the GOT register. */
14524 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
14526 /* The second flow pass currently (June 1999) can't update
14527 regs_ever_live without disturbing other parts of the compiler, so
14528 update it here to make the prolog/epilogue code happy. */
14529 if (!can_create_pseudo_p ()
14530 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
14531 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
14533 crtl->uses_pic_offset_table = 1;
14535 return pic_offset_table_rtx;
14538 static rs6000_stack_t stack_info;
14540 /* Function to init struct machine_function.
14541 This will be called, via a pointer variable,
14542 from push_function_context. */
14544 static struct machine_function *
14545 rs6000_init_machine_status (void)
14547 stack_info.reload_completed = 0;
14548 return ggc_alloc_cleared_machine_function ();
14551 /* These macros test for integers and extract the low-order bits. */
14553 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
14554 && GET_MODE (X) == VOIDmode)
14556 #define INT_LOWPART(X) \
14557 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
14560 extract_MB (rtx op)
14563 unsigned long val = INT_LOWPART (op);
14565 /* If the high bit is zero, the value is the first 1 bit we find
14567 if ((val & 0x80000000) == 0)
14569 gcc_assert (val & 0xffffffff);
14572 while (((val <<= 1) & 0x80000000) == 0)
14577 /* If the high bit is set and the low bit is not, or the mask is all
14578 1's, the value is zero. */
14579 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
14582 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
14585 while (((val >>= 1) & 1) != 0)
14592 extract_ME (rtx op)
14595 unsigned long val = INT_LOWPART (op);
14597 /* If the low bit is zero, the value is the first 1 bit we find from
14599 if ((val & 1) == 0)
14601 gcc_assert (val & 0xffffffff);
14604 while (((val >>= 1) & 1) == 0)
14610 /* If the low bit is set and the high bit is not, or the mask is all
14611 1's, the value is 31. */
14612 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
14615 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
14618 while (((val <<= 1) & 0x80000000) != 0)
14624 /* Locate some local-dynamic symbol still in use by this function
14625 so that we can print its name in some tls_ld pattern. */
14627 static const char *
14628 rs6000_get_some_local_dynamic_name (void)
14632 if (cfun->machine->some_ld_name)
14633 return cfun->machine->some_ld_name;
14635 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
14637 && for_each_rtx (&PATTERN (insn),
14638 rs6000_get_some_local_dynamic_name_1, 0))
14639 return cfun->machine->some_ld_name;
14641 gcc_unreachable ();
14644 /* Helper function for rs6000_get_some_local_dynamic_name. */
14647 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
14651 if (GET_CODE (x) == SYMBOL_REF)
14653 const char *str = XSTR (x, 0);
14654 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
14656 cfun->machine->some_ld_name = str;
14664 /* Write out a function code label. */
14667 rs6000_output_function_entry (FILE *file, const char *fname)
14669 if (fname[0] != '.')
14671 switch (DEFAULT_ABI)
14674 gcc_unreachable ();
14680 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
14689 RS6000_OUTPUT_BASENAME (file, fname);
14692 /* Print an operand. Recognize special options, documented below. */
14695 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
14696 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
14698 #define SMALL_DATA_RELOC "sda21"
14699 #define SMALL_DATA_REG 0
14703 print_operand (FILE *file, rtx x, int code)
14707 unsigned HOST_WIDE_INT uval;
14712 /* Write out an instruction after the call which may be replaced
14713 with glue code by the loader. This depends on the AIX version. */
14714 asm_fprintf (file, RS6000_CALL_GLUE);
14717 /* %a is output_address. */
14720 /* If X is a constant integer whose low-order 5 bits are zero,
14721 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
14722 in the AIX assembler where "sri" with a zero shift count
14723 writes a trash instruction. */
14724 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
14731 /* If constant, low-order 16 bits of constant, unsigned.
14732 Otherwise, write normally. */
14734 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
14736 print_operand (file, x, 0);
14740 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
14741 for 64-bit mask direction. */
14742 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
14745 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
14749 /* X is a CR register. Print the number of the GT bit of the CR. */
14750 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14751 output_operand_lossage ("invalid %%c value");
14753 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
14757 /* Like 'J' but get to the GT bit only. */
14758 gcc_assert (GET_CODE (x) == REG);
14760 /* Bit 1 is GT bit. */
14761 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
14763 /* Add one for shift count in rlinm for scc. */
14764 fprintf (file, "%d", i + 1);
14768 /* X is a CR register. Print the number of the EQ bit of the CR */
14769 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14770 output_operand_lossage ("invalid %%E value");
14772 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
14776 /* X is a CR register. Print the shift count needed to move it
14777 to the high-order four bits. */
14778 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14779 output_operand_lossage ("invalid %%f value");
14781 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
14785 /* Similar, but print the count for the rotate in the opposite
14787 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14788 output_operand_lossage ("invalid %%F value");
14790 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
14794 /* X is a constant integer. If it is negative, print "m",
14795 otherwise print "z". This is to make an aze or ame insn. */
14796 if (GET_CODE (x) != CONST_INT)
14797 output_operand_lossage ("invalid %%G value");
14798 else if (INTVAL (x) >= 0)
14805 /* If constant, output low-order five bits. Otherwise, write
14808 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
14810 print_operand (file, x, 0);
14814 /* If constant, output low-order six bits. Otherwise, write
14817 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
14819 print_operand (file, x, 0);
14823 /* Print `i' if this is a constant, else nothing. */
14829 /* Write the bit number in CCR for jump. */
14830 i = ccr_bit (x, 0);
14832 output_operand_lossage ("invalid %%j code");
14834 fprintf (file, "%d", i);
14838 /* Similar, but add one for shift count in rlinm for scc and pass
14839 scc flag to `ccr_bit'. */
14840 i = ccr_bit (x, 1);
14842 output_operand_lossage ("invalid %%J code");
14844 /* If we want bit 31, write a shift count of zero, not 32. */
14845 fprintf (file, "%d", i == 31 ? 0 : i + 1);
14849 /* X must be a constant. Write the 1's complement of the
14852 output_operand_lossage ("invalid %%k value");
14854 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
14858 /* X must be a symbolic constant on ELF. Write an
14859 expression suitable for an 'addi' that adds in the low 16
14860 bits of the MEM. */
14861 if (GET_CODE (x) == CONST)
14863 if (GET_CODE (XEXP (x, 0)) != PLUS
14864 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
14865 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
14866 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
14867 output_operand_lossage ("invalid %%K value");
14869 print_operand_address (file, x);
14870 fputs ("@l", file);
14873 /* %l is output_asm_label. */
14876 /* Write second word of DImode or DFmode reference. Works on register
14877 or non-indexed memory only. */
14878 if (GET_CODE (x) == REG)
14879 fputs (reg_names[REGNO (x) + 1], file);
14880 else if (GET_CODE (x) == MEM)
14882 /* Handle possible auto-increment. Since it is pre-increment and
14883 we have already done it, we can just use an offset of word. */
14884 if (GET_CODE (XEXP (x, 0)) == PRE_INC
14885 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
14886 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
14888 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
14889 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
14892 output_address (XEXP (adjust_address_nv (x, SImode,
14896 if (small_data_operand (x, GET_MODE (x)))
14897 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
14898 reg_names[SMALL_DATA_REG]);
14903 /* MB value for a mask operand. */
14904 if (! mask_operand (x, SImode))
14905 output_operand_lossage ("invalid %%m value");
14907 fprintf (file, "%d", extract_MB (x));
14911 /* ME value for a mask operand. */
14912 if (! mask_operand (x, SImode))
14913 output_operand_lossage ("invalid %%M value");
14915 fprintf (file, "%d", extract_ME (x));
14918 /* %n outputs the negative of its operand. */
14921 /* Write the number of elements in the vector times 4. */
14922 if (GET_CODE (x) != PARALLEL)
14923 output_operand_lossage ("invalid %%N value");
14925 fprintf (file, "%d", XVECLEN (x, 0) * 4);
14929 /* Similar, but subtract 1 first. */
14930 if (GET_CODE (x) != PARALLEL)
14931 output_operand_lossage ("invalid %%O value");
14933 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
14937 /* X is a CONST_INT that is a power of two. Output the logarithm. */
14939 || INT_LOWPART (x) < 0
14940 || (i = exact_log2 (INT_LOWPART (x))) < 0)
14941 output_operand_lossage ("invalid %%p value");
14943 fprintf (file, "%d", i);
14947 /* The operand must be an indirect memory reference. The result
14948 is the register name. */
14949 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
14950 || REGNO (XEXP (x, 0)) >= 32)
14951 output_operand_lossage ("invalid %%P value");
14953 fputs (reg_names[REGNO (XEXP (x, 0))], file);
14957 /* This outputs the logical code corresponding to a boolean
14958 expression. The expression may have one or both operands
14959 negated (if one, only the first one). For condition register
14960 logical operations, it will also treat the negated
14961 CR codes as NOTs, but not handle NOTs of them. */
14963 const char *const *t = 0;
14965 enum rtx_code code = GET_CODE (x);
14966 static const char * const tbl[3][3] = {
14967 { "and", "andc", "nor" },
14968 { "or", "orc", "nand" },
14969 { "xor", "eqv", "xor" } };
14973 else if (code == IOR)
14975 else if (code == XOR)
14978 output_operand_lossage ("invalid %%q value");
14980 if (GET_CODE (XEXP (x, 0)) != NOT)
14984 if (GET_CODE (XEXP (x, 1)) == NOT)
15002 /* X is a CR register. Print the mask for `mtcrf'. */
15003 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
15004 output_operand_lossage ("invalid %%R value");
15006 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
15010 /* Low 5 bits of 32 - value */
15012 output_operand_lossage ("invalid %%s value");
15014 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
15018 /* PowerPC64 mask position. All 0's is excluded.
15019 CONST_INT 32-bit mask is considered sign-extended so any
15020 transition must occur within the CONST_INT, not on the boundary. */
15021 if (! mask64_operand (x, DImode))
15022 output_operand_lossage ("invalid %%S value");
15024 uval = INT_LOWPART (x);
15026 if (uval & 1) /* Clear Left */
15028 #if HOST_BITS_PER_WIDE_INT > 64
15029 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
15033 else /* Clear Right */
15036 #if HOST_BITS_PER_WIDE_INT > 64
15037 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
15043 gcc_assert (i >= 0);
15044 fprintf (file, "%d", i);
15048 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
15049 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
15051 /* Bit 3 is OV bit. */
15052 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
15054 /* If we want bit 31, write a shift count of zero, not 32. */
15055 fprintf (file, "%d", i == 31 ? 0 : i + 1);
15059 /* Print the symbolic name of a branch target register. */
15060 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
15061 && REGNO (x) != CTR_REGNO))
15062 output_operand_lossage ("invalid %%T value");
15063 else if (REGNO (x) == LR_REGNO)
15064 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
15066 fputs ("ctr", file);
15070 /* High-order 16 bits of constant for use in unsigned operand. */
15072 output_operand_lossage ("invalid %%u value");
15074 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
15075 (INT_LOWPART (x) >> 16) & 0xffff);
15079 /* High-order 16 bits of constant for use in signed operand. */
15081 output_operand_lossage ("invalid %%v value");
15083 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
15084 (INT_LOWPART (x) >> 16) & 0xffff);
15088 /* Print `u' if this has an auto-increment or auto-decrement. */
15089 if (GET_CODE (x) == MEM
15090 && (GET_CODE (XEXP (x, 0)) == PRE_INC
15091 || GET_CODE (XEXP (x, 0)) == PRE_DEC
15092 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
15097 /* Print the trap code for this operand. */
15098 switch (GET_CODE (x))
15101 fputs ("eq", file); /* 4 */
15104 fputs ("ne", file); /* 24 */
15107 fputs ("lt", file); /* 16 */
15110 fputs ("le", file); /* 20 */
15113 fputs ("gt", file); /* 8 */
15116 fputs ("ge", file); /* 12 */
15119 fputs ("llt", file); /* 2 */
15122 fputs ("lle", file); /* 6 */
15125 fputs ("lgt", file); /* 1 */
15128 fputs ("lge", file); /* 5 */
15131 gcc_unreachable ();
15136 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
15139 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
15140 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
15142 print_operand (file, x, 0);
15146 /* MB value for a PowerPC64 rldic operand. */
15147 val = (GET_CODE (x) == CONST_INT
15148 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
15153 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
15154 if ((val <<= 1) < 0)
15157 #if HOST_BITS_PER_WIDE_INT == 32
15158 if (GET_CODE (x) == CONST_INT && i >= 0)
15159 i += 32; /* zero-extend high-part was all 0's */
15160 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
15162 val = CONST_DOUBLE_LOW (x);
15168 for ( ; i < 64; i++)
15169 if ((val <<= 1) < 0)
15174 fprintf (file, "%d", i + 1);
15178 /* X is a FPR or Altivec register used in a VSX context. */
15179 if (GET_CODE (x) != REG || !VSX_REGNO_P (REGNO (x)))
15180 output_operand_lossage ("invalid %%x value");
15183 int reg = REGNO (x);
15184 int vsx_reg = (FP_REGNO_P (reg)
15186 : reg - FIRST_ALTIVEC_REGNO + 32);
15188 #ifdef TARGET_REGNAMES
15189 if (TARGET_REGNAMES)
15190 fprintf (file, "%%vs%d", vsx_reg);
15193 fprintf (file, "%d", vsx_reg);
15198 if (GET_CODE (x) == MEM
15199 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
15200 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
15201 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
15206 /* Like 'L', for third word of TImode */
15207 if (GET_CODE (x) == REG)
15208 fputs (reg_names[REGNO (x) + 2], file);
15209 else if (GET_CODE (x) == MEM)
15211 if (GET_CODE (XEXP (x, 0)) == PRE_INC
15212 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
15213 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
15214 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15215 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
15217 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
15218 if (small_data_operand (x, GET_MODE (x)))
15219 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15220 reg_names[SMALL_DATA_REG]);
15225 /* X is a SYMBOL_REF. Write out the name preceded by a
15226 period and without any trailing data in brackets. Used for function
15227 names. If we are configured for System V (or the embedded ABI) on
15228 the PowerPC, do not emit the period, since those systems do not use
15229 TOCs and the like. */
15230 gcc_assert (GET_CODE (x) == SYMBOL_REF);
15232 /* Mark the decl as referenced so that cgraph will output the
15234 if (SYMBOL_REF_DECL (x))
15235 mark_decl_referenced (SYMBOL_REF_DECL (x));
15237 /* For macho, check to see if we need a stub. */
15240 const char *name = XSTR (x, 0);
15242 if (darwin_emit_branch_islands
15243 && MACHOPIC_INDIRECT
15244 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
15245 name = machopic_indirection_name (x, /*stub_p=*/true);
15247 assemble_name (file, name);
15249 else if (!DOT_SYMBOLS)
15250 assemble_name (file, XSTR (x, 0));
15252 rs6000_output_function_entry (file, XSTR (x, 0));
15256 /* Like 'L', for last word of TImode. */
15257 if (GET_CODE (x) == REG)
15258 fputs (reg_names[REGNO (x) + 3], file);
15259 else if (GET_CODE (x) == MEM)
15261 if (GET_CODE (XEXP (x, 0)) == PRE_INC
15262 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
15263 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
15264 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15265 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
15267 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
15268 if (small_data_operand (x, GET_MODE (x)))
15269 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15270 reg_names[SMALL_DATA_REG]);
15274 /* Print AltiVec or SPE memory operand. */
15279 gcc_assert (GET_CODE (x) == MEM);
15283 /* Ugly hack because %y is overloaded. */
15284 if ((TARGET_SPE || TARGET_E500_DOUBLE)
15285 && (GET_MODE_SIZE (GET_MODE (x)) == 8
15286 || GET_MODE (x) == TFmode
15287 || GET_MODE (x) == TImode))
15289 /* Handle [reg]. */
15290 if (GET_CODE (tmp) == REG)
15292 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
15295 /* Handle [reg+UIMM]. */
15296 else if (GET_CODE (tmp) == PLUS &&
15297 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
15301 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
15303 x = INTVAL (XEXP (tmp, 1));
15304 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
15308 /* Fall through. Must be [reg+reg]. */
15310 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x))
15311 && GET_CODE (tmp) == AND
15312 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
15313 && INTVAL (XEXP (tmp, 1)) == -16)
15314 tmp = XEXP (tmp, 0);
15315 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
15316 && GET_CODE (tmp) == PRE_MODIFY)
15317 tmp = XEXP (tmp, 1);
15318 if (GET_CODE (tmp) == REG)
15319 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
15322 if (!GET_CODE (tmp) == PLUS
15323 || !REG_P (XEXP (tmp, 0))
15324 || !REG_P (XEXP (tmp, 1)))
15326 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
15330 if (REGNO (XEXP (tmp, 0)) == 0)
15331 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
15332 reg_names[ REGNO (XEXP (tmp, 0)) ]);
15334 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
15335 reg_names[ REGNO (XEXP (tmp, 1)) ]);
15341 if (GET_CODE (x) == REG)
15342 fprintf (file, "%s", reg_names[REGNO (x)]);
15343 else if (GET_CODE (x) == MEM)
15345 /* We need to handle PRE_INC and PRE_DEC here, since we need to
15346 know the width from the mode. */
15347 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
15348 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
15349 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
15350 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
15351 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
15352 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
15353 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15354 output_address (XEXP (XEXP (x, 0), 1));
15356 output_address (XEXP (x, 0));
15360 if (toc_relative_expr_p (x))
15361 /* This hack along with a corresponding hack in
15362 rs6000_output_addr_const_extra arranges to output addends
15363 where the assembler expects to find them. eg.
15364 (const (plus (unspec [symbol_ref ("x") tocrel]) 4))
15365 without this hack would be output as "x@toc+4". We
15367 output_addr_const (file, tocrel_base);
15369 output_addr_const (file, x);
15374 assemble_name (file, rs6000_get_some_local_dynamic_name ());
15378 output_operand_lossage ("invalid %%xn code");
15382 /* Print the address of an operand. */
15385 print_operand_address (FILE *file, rtx x)
15387 if (GET_CODE (x) == REG)
15388 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
15389 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
15390 || GET_CODE (x) == LABEL_REF)
15392 output_addr_const (file, x);
15393 if (small_data_operand (x, GET_MODE (x)))
15394 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15395 reg_names[SMALL_DATA_REG]);
15397 gcc_assert (!TARGET_TOC);
15399 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
15401 gcc_assert (REG_P (XEXP (x, 0)));
15402 if (REGNO (XEXP (x, 0)) == 0)
15403 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
15404 reg_names[ REGNO (XEXP (x, 0)) ]);
15406 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
15407 reg_names[ REGNO (XEXP (x, 1)) ]);
15409 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
15410 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
15411 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
15413 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
15414 && CONSTANT_P (XEXP (x, 1)))
15416 fprintf (file, "lo16(");
15417 output_addr_const (file, XEXP (x, 1));
15418 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
15421 else if (legitimate_constant_pool_address_p (x, QImode, true))
15423 /* This hack along with a corresponding hack in
15424 rs6000_output_addr_const_extra arranges to output addends
15425 where the assembler expects to find them. eg.
15427 . (const (plus (unspec [symbol_ref ("x") tocrel]) 8)))
15428 without this hack would be output as "x@toc+8@l(9)". We
15429 want "x+8@toc@l(9)". */
15430 output_addr_const (file, tocrel_base);
15431 if (GET_CODE (x) == LO_SUM)
15432 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
15434 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
15437 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
15438 && CONSTANT_P (XEXP (x, 1)))
15440 output_addr_const (file, XEXP (x, 1));
15441 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
15445 gcc_unreachable ();
15448 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
15451 rs6000_output_addr_const_extra (FILE *file, rtx x)
15453 if (GET_CODE (x) == UNSPEC)
15454 switch (XINT (x, 1))
15456 case UNSPEC_TOCREL:
15457 gcc_assert (GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF);
15458 output_addr_const (file, XVECEXP (x, 0, 0));
15459 if (x == tocrel_base && tocrel_offset != const0_rtx)
15461 if (INTVAL (tocrel_offset) >= 0)
15462 fprintf (file, "+");
15463 output_addr_const (file, tocrel_offset);
15465 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
15468 assemble_name (file, toc_label_name);
15470 else if (TARGET_ELF)
15471 fputs ("@toc", file);
15475 case UNSPEC_MACHOPIC_OFFSET:
15476 output_addr_const (file, XVECEXP (x, 0, 0));
15478 machopic_output_function_base_name (file);
15485 /* Target hook for assembling integer objects. The PowerPC version has
15486 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
15487 is defined. It also needs to handle DI-mode objects on 64-bit
15491 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
15493 #ifdef RELOCATABLE_NEEDS_FIXUP
15494 /* Special handling for SI values. */
15495 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
15497 static int recurse = 0;
15499 /* For -mrelocatable, we mark all addresses that need to be fixed up in
15500 the .fixup section. Since the TOC section is already relocated, we
15501 don't need to mark it here. We used to skip the text section, but it
15502 should never be valid for relocated addresses to be placed in the text
15504 if (TARGET_RELOCATABLE
15505 && in_section != toc_section
15507 && GET_CODE (x) != CONST_INT
15508 && GET_CODE (x) != CONST_DOUBLE
15514 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
15516 ASM_OUTPUT_LABEL (asm_out_file, buf);
15517 fprintf (asm_out_file, "\t.long\t(");
15518 output_addr_const (asm_out_file, x);
15519 fprintf (asm_out_file, ")@fixup\n");
15520 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
15521 ASM_OUTPUT_ALIGN (asm_out_file, 2);
15522 fprintf (asm_out_file, "\t.long\t");
15523 assemble_name (asm_out_file, buf);
15524 fprintf (asm_out_file, "\n\t.previous\n");
15528 /* Remove initial .'s to turn a -mcall-aixdesc function
15529 address into the address of the descriptor, not the function
15531 else if (GET_CODE (x) == SYMBOL_REF
15532 && XSTR (x, 0)[0] == '.'
15533 && DEFAULT_ABI == ABI_AIX)
15535 const char *name = XSTR (x, 0);
15536 while (*name == '.')
15539 fprintf (asm_out_file, "\t.long\t%s\n", name);
15543 #endif /* RELOCATABLE_NEEDS_FIXUP */
15544 return default_assemble_integer (x, size, aligned_p);
15547 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
15548 /* Emit an assembler directive to set symbol visibility for DECL to
15549 VISIBILITY_TYPE. */
15552 rs6000_assemble_visibility (tree decl, int vis)
15554 /* Functions need to have their entry point symbol visibility set as
15555 well as their descriptor symbol visibility. */
15556 if (DEFAULT_ABI == ABI_AIX
15558 && TREE_CODE (decl) == FUNCTION_DECL)
15560 static const char * const visibility_types[] = {
15561 NULL, "internal", "hidden", "protected"
15564 const char *name, *type;
15566 name = ((* targetm.strip_name_encoding)
15567 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
15568 type = visibility_types[vis];
15570 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
15571 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
15574 default_assemble_visibility (decl, vis);
15579 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
15581 /* Reversal of FP compares takes care -- an ordered compare
15582 becomes an unordered compare and vice versa. */
15583 if (mode == CCFPmode
15584 && (!flag_finite_math_only
15585 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
15586 || code == UNEQ || code == LTGT))
15587 return reverse_condition_maybe_unordered (code);
15589 return reverse_condition (code);
15592 /* Generate a compare for CODE. Return a brand-new rtx that
15593 represents the result of the compare. */
15596 rs6000_generate_compare (rtx cmp, enum machine_mode mode)
15598 enum machine_mode comp_mode;
15599 rtx compare_result;
15600 enum rtx_code code = GET_CODE (cmp);
15601 rtx op0 = XEXP (cmp, 0);
15602 rtx op1 = XEXP (cmp, 1);
15604 if (FLOAT_MODE_P (mode))
15605 comp_mode = CCFPmode;
15606 else if (code == GTU || code == LTU
15607 || code == GEU || code == LEU)
15608 comp_mode = CCUNSmode;
15609 else if ((code == EQ || code == NE)
15610 && GET_CODE (op0) == SUBREG
15611 && GET_CODE (op1) == SUBREG
15612 && SUBREG_PROMOTED_UNSIGNED_P (op0)
15613 && SUBREG_PROMOTED_UNSIGNED_P (op1))
15614 /* These are unsigned values, perhaps there will be a later
15615 ordering compare that can be shared with this one.
15616 Unfortunately we cannot detect the signedness of the operands
15617 for non-subregs. */
15618 comp_mode = CCUNSmode;
15620 comp_mode = CCmode;
15622 /* First, the compare. */
15623 compare_result = gen_reg_rtx (comp_mode);
15625 /* E500 FP compare instructions on the GPRs. Yuck! */
15626 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
15627 && FLOAT_MODE_P (mode))
15629 rtx cmp, or_result, compare_result2;
15630 enum machine_mode op_mode = GET_MODE (op0);
15632 if (op_mode == VOIDmode)
15633 op_mode = GET_MODE (op1);
15635 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
15636 This explains the following mess. */
15640 case EQ: case UNEQ: case NE: case LTGT:
15644 cmp = (flag_finite_math_only && !flag_trapping_math)
15645 ? gen_tstsfeq_gpr (compare_result, op0, op1)
15646 : gen_cmpsfeq_gpr (compare_result, op0, op1);
15650 cmp = (flag_finite_math_only && !flag_trapping_math)
15651 ? gen_tstdfeq_gpr (compare_result, op0, op1)
15652 : gen_cmpdfeq_gpr (compare_result, op0, op1);
15656 cmp = (flag_finite_math_only && !flag_trapping_math)
15657 ? gen_tsttfeq_gpr (compare_result, op0, op1)
15658 : gen_cmptfeq_gpr (compare_result, op0, op1);
15662 gcc_unreachable ();
15666 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
15670 cmp = (flag_finite_math_only && !flag_trapping_math)
15671 ? gen_tstsfgt_gpr (compare_result, op0, op1)
15672 : gen_cmpsfgt_gpr (compare_result, op0, op1);
15676 cmp = (flag_finite_math_only && !flag_trapping_math)
15677 ? gen_tstdfgt_gpr (compare_result, op0, op1)
15678 : gen_cmpdfgt_gpr (compare_result, op0, op1);
15682 cmp = (flag_finite_math_only && !flag_trapping_math)
15683 ? gen_tsttfgt_gpr (compare_result, op0, op1)
15684 : gen_cmptfgt_gpr (compare_result, op0, op1);
15688 gcc_unreachable ();
15692 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
15696 cmp = (flag_finite_math_only && !flag_trapping_math)
15697 ? gen_tstsflt_gpr (compare_result, op0, op1)
15698 : gen_cmpsflt_gpr (compare_result, op0, op1);
15702 cmp = (flag_finite_math_only && !flag_trapping_math)
15703 ? gen_tstdflt_gpr (compare_result, op0, op1)
15704 : gen_cmpdflt_gpr (compare_result, op0, op1);
15708 cmp = (flag_finite_math_only && !flag_trapping_math)
15709 ? gen_tsttflt_gpr (compare_result, op0, op1)
15710 : gen_cmptflt_gpr (compare_result, op0, op1);
15714 gcc_unreachable ();
15718 gcc_unreachable ();
15721 /* Synthesize LE and GE from LT/GT || EQ. */
15722 if (code == LE || code == GE || code == LEU || code == GEU)
15728 case LE: code = LT; break;
15729 case GE: code = GT; break;
15730 case LEU: code = LT; break;
15731 case GEU: code = GT; break;
15732 default: gcc_unreachable ();
15735 compare_result2 = gen_reg_rtx (CCFPmode);
15741 cmp = (flag_finite_math_only && !flag_trapping_math)
15742 ? gen_tstsfeq_gpr (compare_result2, op0, op1)
15743 : gen_cmpsfeq_gpr (compare_result2, op0, op1);
15747 cmp = (flag_finite_math_only && !flag_trapping_math)
15748 ? gen_tstdfeq_gpr (compare_result2, op0, op1)
15749 : gen_cmpdfeq_gpr (compare_result2, op0, op1);
15753 cmp = (flag_finite_math_only && !flag_trapping_math)
15754 ? gen_tsttfeq_gpr (compare_result2, op0, op1)
15755 : gen_cmptfeq_gpr (compare_result2, op0, op1);
15759 gcc_unreachable ();
15763 /* OR them together. */
15764 or_result = gen_reg_rtx (CCFPmode);
15765 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
15767 compare_result = or_result;
15772 if (code == NE || code == LTGT)
15782 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
15783 CLOBBERs to match cmptf_internal2 pattern. */
15784 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
15785 && GET_MODE (op0) == TFmode
15786 && !TARGET_IEEEQUAD
15787 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
15788 emit_insn (gen_rtx_PARALLEL (VOIDmode,
15790 gen_rtx_SET (VOIDmode,
15792 gen_rtx_COMPARE (comp_mode, op0, op1)),
15793 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15794 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15795 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15796 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15797 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15798 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15799 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15800 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15801 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
15802 else if (GET_CODE (op1) == UNSPEC
15803 && XINT (op1, 1) == UNSPEC_SP_TEST)
15805 rtx op1b = XVECEXP (op1, 0, 0);
15806 comp_mode = CCEQmode;
15807 compare_result = gen_reg_rtx (CCEQmode);
15809 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
15811 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
15814 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
15815 gen_rtx_COMPARE (comp_mode, op0, op1)));
15818 /* Some kinds of FP comparisons need an OR operation;
15819 under flag_finite_math_only we don't bother. */
15820 if (FLOAT_MODE_P (mode)
15821 && !flag_finite_math_only
15822 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
15823 && (code == LE || code == GE
15824 || code == UNEQ || code == LTGT
15825 || code == UNGT || code == UNLT))
15827 enum rtx_code or1, or2;
15828 rtx or1_rtx, or2_rtx, compare2_rtx;
15829 rtx or_result = gen_reg_rtx (CCEQmode);
15833 case LE: or1 = LT; or2 = EQ; break;
15834 case GE: or1 = GT; or2 = EQ; break;
15835 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
15836 case LTGT: or1 = LT; or2 = GT; break;
15837 case UNGT: or1 = UNORDERED; or2 = GT; break;
15838 case UNLT: or1 = UNORDERED; or2 = LT; break;
15839 default: gcc_unreachable ();
15841 validate_condition_mode (or1, comp_mode);
15842 validate_condition_mode (or2, comp_mode);
15843 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
15844 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
15845 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
15846 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
15848 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
15850 compare_result = or_result;
15854 validate_condition_mode (code, GET_MODE (compare_result));
15856 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
15860 /* Emit the RTL for an sISEL pattern. */
15863 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED, rtx operands[])
15865 rs6000_emit_int_cmove (operands[0], operands[1], const1_rtx, const0_rtx);
15869 rs6000_emit_sCOND (enum machine_mode mode, rtx operands[])
15872 enum machine_mode op_mode;
15873 enum rtx_code cond_code;
15874 rtx result = operands[0];
15876 if (TARGET_ISEL && (mode == SImode || mode == DImode))
15878 rs6000_emit_sISEL (mode, operands);
15882 condition_rtx = rs6000_generate_compare (operands[1], mode);
15883 cond_code = GET_CODE (condition_rtx);
15885 if (FLOAT_MODE_P (mode)
15886 && !TARGET_FPRS && TARGET_HARD_FLOAT)
15890 PUT_MODE (condition_rtx, SImode);
15891 t = XEXP (condition_rtx, 0);
15893 gcc_assert (cond_code == NE || cond_code == EQ);
15895 if (cond_code == NE)
15896 emit_insn (gen_e500_flip_gt_bit (t, t));
15898 emit_insn (gen_move_from_CR_gt_bit (result, t));
15902 if (cond_code == NE
15903 || cond_code == GE || cond_code == LE
15904 || cond_code == GEU || cond_code == LEU
15905 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
15907 rtx not_result = gen_reg_rtx (CCEQmode);
15908 rtx not_op, rev_cond_rtx;
15909 enum machine_mode cc_mode;
15911 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
15913 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
15914 SImode, XEXP (condition_rtx, 0), const0_rtx);
15915 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
15916 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
15917 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
15920 op_mode = GET_MODE (XEXP (operands[1], 0));
15921 if (op_mode == VOIDmode)
15922 op_mode = GET_MODE (XEXP (operands[1], 1));
15924 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
15926 PUT_MODE (condition_rtx, DImode);
15927 convert_move (result, condition_rtx, 0);
15931 PUT_MODE (condition_rtx, SImode);
15932 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
15936 /* Emit a branch of kind CODE to location LOC. */
15939 rs6000_emit_cbranch (enum machine_mode mode, rtx operands[])
15941 rtx condition_rtx, loc_ref;
15943 condition_rtx = rs6000_generate_compare (operands[0], mode);
15944 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
15945 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
15946 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
15947 loc_ref, pc_rtx)));
15950 /* Return the string to output a conditional branch to LABEL, which is
15951 the operand number of the label, or -1 if the branch is really a
15952 conditional return.
15954 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
15955 condition code register and its mode specifies what kind of
15956 comparison we made.
15958 REVERSED is nonzero if we should reverse the sense of the comparison.
15960 INSN is the insn. */
15963 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
15965 static char string[64];
15966 enum rtx_code code = GET_CODE (op);
15967 rtx cc_reg = XEXP (op, 0);
15968 enum machine_mode mode = GET_MODE (cc_reg);
15969 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
15970 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
15971 int really_reversed = reversed ^ need_longbranch;
15977 validate_condition_mode (code, mode);
15979 /* Work out which way this really branches. We could use
15980 reverse_condition_maybe_unordered here always but this
15981 makes the resulting assembler clearer. */
15982 if (really_reversed)
15984 /* Reversal of FP compares takes care -- an ordered compare
15985 becomes an unordered compare and vice versa. */
15986 if (mode == CCFPmode)
15987 code = reverse_condition_maybe_unordered (code);
15989 code = reverse_condition (code);
15992 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
15994 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
15999 /* Opposite of GT. */
16008 gcc_unreachable ();
16014 /* Not all of these are actually distinct opcodes, but
16015 we distinguish them for clarity of the resulting assembler. */
16016 case NE: case LTGT:
16017 ccode = "ne"; break;
16018 case EQ: case UNEQ:
16019 ccode = "eq"; break;
16021 ccode = "ge"; break;
16022 case GT: case GTU: case UNGT:
16023 ccode = "gt"; break;
16025 ccode = "le"; break;
16026 case LT: case LTU: case UNLT:
16027 ccode = "lt"; break;
16028 case UNORDERED: ccode = "un"; break;
16029 case ORDERED: ccode = "nu"; break;
16030 case UNGE: ccode = "nl"; break;
16031 case UNLE: ccode = "ng"; break;
16033 gcc_unreachable ();
16036 /* Maybe we have a guess as to how likely the branch is.
16037 The old mnemonics don't have a way to specify this information. */
16039 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
16040 if (note != NULL_RTX)
16042 /* PROB is the difference from 50%. */
16043 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
16045 /* Only hint for highly probable/improbable branches on newer
16046 cpus as static prediction overrides processor dynamic
16047 prediction. For older cpus we may as well always hint, but
16048 assume not taken for branches that are very close to 50% as a
16049 mispredicted taken branch is more expensive than a
16050 mispredicted not-taken branch. */
16051 if (rs6000_always_hint
16052 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
16053 && br_prob_note_reliable_p (note)))
16055 if (abs (prob) > REG_BR_PROB_BASE / 20
16056 && ((prob > 0) ^ need_longbranch))
16064 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
16066 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
16068 /* We need to escape any '%' characters in the reg_names string.
16069 Assume they'd only be the first character.... */
16070 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
16072 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
16076 /* If the branch distance was too far, we may have to use an
16077 unconditional branch to go the distance. */
16078 if (need_longbranch)
16079 s += sprintf (s, ",$+8\n\tb %s", label);
16081 s += sprintf (s, ",%s", label);
16087 /* Return the string to flip the GT bit on a CR. */
16089 output_e500_flip_gt_bit (rtx dst, rtx src)
16091 static char string[64];
16094 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
16095 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
16098 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
16099 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
16101 sprintf (string, "crnot %d,%d", a, b);
16105 /* Return insn for VSX or Altivec comparisons. */
16108 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
16111 enum machine_mode mode = GET_MODE (op0);
16119 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
16125 mask = gen_reg_rtx (mode);
16126 emit_insn (gen_rtx_SET (VOIDmode,
16128 gen_rtx_fmt_ee (code, mode, op0, op1)));
16135 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
16136 DMODE is expected destination mode. This is a recursive function. */
16139 rs6000_emit_vector_compare (enum rtx_code rcode,
16141 enum machine_mode dmode)
16144 bool swap_operands = false;
16145 bool try_again = false;
16147 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
16148 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
16150 /* See if the comparison works as is. */
16151 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
16159 swap_operands = true;
16164 swap_operands = true;
16172 /* Invert condition and try again.
16173 e.g., A != B becomes ~(A==B). */
16175 enum rtx_code rev_code;
16176 enum insn_code nor_code;
16179 rev_code = reverse_condition_maybe_unordered (rcode);
16180 if (rev_code == UNKNOWN)
16183 nor_code = optab_handler (one_cmpl_optab, dmode);
16184 if (nor_code == CODE_FOR_nothing)
16187 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
16191 mask = gen_reg_rtx (dmode);
16192 emit_insn (GEN_FCN (nor_code) (mask, mask2));
16200 /* Try GT/GTU/LT/LTU OR EQ */
16203 enum insn_code ior_code;
16204 enum rtx_code new_code;
16225 gcc_unreachable ();
16228 ior_code = optab_handler (ior_optab, dmode);
16229 if (ior_code == CODE_FOR_nothing)
16232 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
16236 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
16240 mask = gen_reg_rtx (dmode);
16241 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
16259 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
16264 /* You only get two chances. */
16268 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
16269 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
16270 operands for the relation operation COND. */
16273 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
16274 rtx cond, rtx cc_op0, rtx cc_op1)
16276 enum machine_mode dest_mode = GET_MODE (dest);
16277 enum machine_mode mask_mode = GET_MODE (cc_op0);
16278 enum rtx_code rcode = GET_CODE (cond);
16279 enum machine_mode cc_mode = CCmode;
16283 bool invert_move = false;
16285 if (VECTOR_UNIT_NONE_P (dest_mode))
16288 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
16289 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
16293 /* Swap operands if we can, and fall back to doing the operation as
16294 specified, and doing a NOR to invert the test. */
16300 /* Invert condition and try again.
16301 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
16302 invert_move = true;
16303 rcode = reverse_condition_maybe_unordered (rcode);
16304 if (rcode == UNKNOWN)
16308 /* Mark unsigned tests with CCUNSmode. */
16313 cc_mode = CCUNSmode;
16320 /* Get the vector mask for the given relational operations. */
16321 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
16329 op_true = op_false;
16333 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
16334 CONST0_RTX (dest_mode));
16335 emit_insn (gen_rtx_SET (VOIDmode,
16337 gen_rtx_IF_THEN_ELSE (dest_mode,
16344 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
16345 operands of the last comparison is nonzero/true, FALSE_COND if it
16346 is zero/false. Return 0 if the hardware has no such operation. */
16349 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
16351 enum rtx_code code = GET_CODE (op);
16352 rtx op0 = XEXP (op, 0);
16353 rtx op1 = XEXP (op, 1);
16354 REAL_VALUE_TYPE c1;
16355 enum machine_mode compare_mode = GET_MODE (op0);
16356 enum machine_mode result_mode = GET_MODE (dest);
16358 bool is_against_zero;
16360 /* These modes should always match. */
16361 if (GET_MODE (op1) != compare_mode
16362 /* In the isel case however, we can use a compare immediate, so
16363 op1 may be a small constant. */
16364 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
16366 if (GET_MODE (true_cond) != result_mode)
16368 if (GET_MODE (false_cond) != result_mode)
16371 /* First, work out if the hardware can do this at all, or
16372 if it's too slow.... */
16373 if (!FLOAT_MODE_P (compare_mode))
16376 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
16379 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
16380 && SCALAR_FLOAT_MODE_P (compare_mode))
16383 is_against_zero = op1 == CONST0_RTX (compare_mode);
16385 /* A floating-point subtract might overflow, underflow, or produce
16386 an inexact result, thus changing the floating-point flags, so it
16387 can't be generated if we care about that. It's safe if one side
16388 of the construct is zero, since then no subtract will be
16390 if (SCALAR_FLOAT_MODE_P (compare_mode)
16391 && flag_trapping_math && ! is_against_zero)
16394 /* Eliminate half of the comparisons by switching operands, this
16395 makes the remaining code simpler. */
16396 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
16397 || code == LTGT || code == LT || code == UNLE)
16399 code = reverse_condition_maybe_unordered (code);
16401 true_cond = false_cond;
16405 /* UNEQ and LTGT take four instructions for a comparison with zero,
16406 it'll probably be faster to use a branch here too. */
16407 if (code == UNEQ && HONOR_NANS (compare_mode))
16410 if (GET_CODE (op1) == CONST_DOUBLE)
16411 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
16413 /* We're going to try to implement comparisons by performing
16414 a subtract, then comparing against zero. Unfortunately,
16415 Inf - Inf is NaN which is not zero, and so if we don't
16416 know that the operand is finite and the comparison
16417 would treat EQ different to UNORDERED, we can't do it. */
16418 if (HONOR_INFINITIES (compare_mode)
16419 && code != GT && code != UNGE
16420 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
16421 /* Constructs of the form (a OP b ? a : b) are safe. */
16422 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
16423 || (! rtx_equal_p (op0, true_cond)
16424 && ! rtx_equal_p (op1, true_cond))))
16427 /* At this point we know we can use fsel. */
16429 /* Reduce the comparison to a comparison against zero. */
16430 if (! is_against_zero)
16432 temp = gen_reg_rtx (compare_mode);
16433 emit_insn (gen_rtx_SET (VOIDmode, temp,
16434 gen_rtx_MINUS (compare_mode, op0, op1)));
16436 op1 = CONST0_RTX (compare_mode);
16439 /* If we don't care about NaNs we can reduce some of the comparisons
16440 down to faster ones. */
16441 if (! HONOR_NANS (compare_mode))
16447 true_cond = false_cond;
16460 /* Now, reduce everything down to a GE. */
16467 temp = gen_reg_rtx (compare_mode);
16468 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16473 temp = gen_reg_rtx (compare_mode);
16474 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
16479 temp = gen_reg_rtx (compare_mode);
16480 emit_insn (gen_rtx_SET (VOIDmode, temp,
16481 gen_rtx_NEG (compare_mode,
16482 gen_rtx_ABS (compare_mode, op0))));
16487 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
16488 temp = gen_reg_rtx (result_mode);
16489 emit_insn (gen_rtx_SET (VOIDmode, temp,
16490 gen_rtx_IF_THEN_ELSE (result_mode,
16491 gen_rtx_GE (VOIDmode,
16493 true_cond, false_cond)));
16494 false_cond = true_cond;
16497 temp = gen_reg_rtx (compare_mode);
16498 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16503 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
16504 temp = gen_reg_rtx (result_mode);
16505 emit_insn (gen_rtx_SET (VOIDmode, temp,
16506 gen_rtx_IF_THEN_ELSE (result_mode,
16507 gen_rtx_GE (VOIDmode,
16509 true_cond, false_cond)));
16510 true_cond = false_cond;
16513 temp = gen_reg_rtx (compare_mode);
16514 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16519 gcc_unreachable ();
16522 emit_insn (gen_rtx_SET (VOIDmode, dest,
16523 gen_rtx_IF_THEN_ELSE (result_mode,
16524 gen_rtx_GE (VOIDmode,
16526 true_cond, false_cond)));
16530 /* Same as above, but for ints (isel). */
16533 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
16535 rtx condition_rtx, cr;
16536 enum machine_mode mode = GET_MODE (dest);
16537 enum rtx_code cond_code;
16538 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
16541 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
16544 /* We still have to do the compare, because isel doesn't do a
16545 compare, it just looks at the CRx bits set by a previous compare
16547 condition_rtx = rs6000_generate_compare (op, mode);
16548 cond_code = GET_CODE (condition_rtx);
16549 cr = XEXP (condition_rtx, 0);
16550 signedp = GET_MODE (cr) == CCmode;
16552 isel_func = (mode == SImode
16553 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
16554 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
16558 case LT: case GT: case LTU: case GTU: case EQ:
16559 /* isel handles these directly. */
16563 /* We need to swap the sense of the comparison. */
16566 true_cond = false_cond;
16568 PUT_CODE (condition_rtx, reverse_condition (cond_code));
16573 false_cond = force_reg (mode, false_cond);
16574 if (true_cond != const0_rtx)
16575 true_cond = force_reg (mode, true_cond);
16577 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
16583 output_isel (rtx *operands)
16585 enum rtx_code code;
16587 code = GET_CODE (operands[1]);
16589 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
16591 gcc_assert (GET_CODE (operands[2]) == REG
16592 && GET_CODE (operands[3]) == REG);
16593 PUT_CODE (operands[1], reverse_condition (code));
16594 return "isel %0,%3,%2,%j1";
16597 return "isel %0,%2,%3,%j1";
16601 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
16603 enum machine_mode mode = GET_MODE (op0);
16607 /* VSX/altivec have direct min/max insns. */
16608 if ((code == SMAX || code == SMIN)
16609 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
16610 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
16612 emit_insn (gen_rtx_SET (VOIDmode,
16614 gen_rtx_fmt_ee (code, mode, op0, op1)));
16618 if (code == SMAX || code == SMIN)
16623 if (code == SMAX || code == UMAX)
16624 target = emit_conditional_move (dest, c, op0, op1, mode,
16625 op0, op1, mode, 0);
16627 target = emit_conditional_move (dest, c, op0, op1, mode,
16628 op1, op0, mode, 0);
16629 gcc_assert (target);
16630 if (target != dest)
16631 emit_move_insn (dest, target);
16634 /* A subroutine of the atomic operation splitters. Jump to LABEL if
16635 COND is true. Mark the jump as unlikely to be taken. */
16638 emit_unlikely_jump (rtx cond, rtx label)
16640 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
16643 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
16644 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
16645 add_reg_note (x, REG_BR_PROB, very_unlikely);
16648 /* A subroutine of the atomic operation splitters. Emit a load-locked
16649 instruction in MODE. */
16652 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
16654 rtx (*fn) (rtx, rtx) = NULL;
16659 fn = gen_load_lockedsi;
16662 fn = gen_load_lockeddi;
16665 gcc_unreachable ();
16667 emit_insn (fn (reg, mem));
16670 /* A subroutine of the atomic operation splitters. Emit a store-conditional
16671 instruction in MODE. */
16674 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
16676 rtx (*fn) (rtx, rtx, rtx) = NULL;
16681 fn = gen_store_conditionalsi;
16684 fn = gen_store_conditionaldi;
16687 gcc_unreachable ();
16690 /* Emit sync before stwcx. to address PPC405 Erratum. */
16691 if (PPC405_ERRATUM77)
16692 emit_insn (gen_hwsync ());
16694 emit_insn (fn (res, mem, val));
16697 /* Expand barriers before and after a load_locked/store_cond sequence. */
16700 rs6000_pre_atomic_barrier (enum memmodel model)
16704 case MEMMODEL_RELAXED:
16705 case MEMMODEL_CONSUME:
16706 case MEMMODEL_ACQUIRE:
16708 case MEMMODEL_RELEASE:
16709 case MEMMODEL_ACQ_REL:
16710 emit_insn (gen_lwsync ());
16712 case MEMMODEL_SEQ_CST:
16713 emit_insn (gen_hwsync ());
16716 gcc_unreachable ();
16721 rs6000_post_atomic_barrier (enum memmodel model)
16725 case MEMMODEL_RELAXED:
16726 case MEMMODEL_CONSUME:
16727 case MEMMODEL_RELEASE:
16729 case MEMMODEL_ACQUIRE:
16730 case MEMMODEL_ACQ_REL:
16731 case MEMMODEL_SEQ_CST:
16732 emit_insn (gen_isync ());
16735 gcc_unreachable ();
16739 /* A subroutine of the various atomic expanders. For sub-word operations,
16740 we must adjust things to operate on SImode. Given the original MEM,
16741 return a new aligned memory. Also build and return the quantities by
16742 which to shift and mask. */
16745 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
16747 rtx addr, align, shift, mask, mem;
16748 HOST_WIDE_INT shift_mask;
16749 enum machine_mode mode = GET_MODE (orig_mem);
16751 /* For smaller modes, we have to implement this via SImode. */
16752 shift_mask = (mode == QImode ? 0x18 : 0x10);
16754 addr = XEXP (orig_mem, 0);
16755 addr = force_reg (GET_MODE (addr), addr);
16757 /* Aligned memory containing subword. Generate a new memory. We
16758 do not want any of the existing MEM_ATTR data, as we're now
16759 accessing memory outside the original object. */
16760 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
16761 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16762 mem = gen_rtx_MEM (SImode, align);
16763 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
16764 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
16765 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
16767 /* Shift amount for subword relative to aligned word. */
16768 shift = gen_reg_rtx (SImode);
16769 addr = gen_lowpart (SImode, addr);
16770 emit_insn (gen_rlwinm (shift, addr, GEN_INT (3), GEN_INT (shift_mask)));
16771 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
16772 shift, 1, OPTAB_LIB_WIDEN);
16775 /* Mask for insertion. */
16776 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
16777 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
16783 /* A subroutine of the various atomic expanders. For sub-word operands,
16784 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
16787 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
16791 x = gen_reg_rtx (SImode);
16792 emit_insn (gen_rtx_SET (VOIDmode, x,
16793 gen_rtx_AND (SImode,
16794 gen_rtx_NOT (SImode, mask),
16797 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
16802 /* A subroutine of the various atomic expanders. For sub-word operands,
16803 extract WIDE to NARROW via SHIFT. */
16806 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
16808 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
16809 wide, 1, OPTAB_LIB_WIDEN);
16810 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
16813 /* Expand an atomic compare and swap operation. */
16816 rs6000_expand_atomic_compare_and_swap (rtx operands[])
16818 rtx boolval, retval, mem, oldval, newval, cond;
16819 rtx label1, label2, x, mask, shift;
16820 enum machine_mode mode;
16821 enum memmodel mod_s, mod_f;
16824 boolval = operands[0];
16825 retval = operands[1];
16827 oldval = operands[3];
16828 newval = operands[4];
16829 is_weak = (INTVAL (operands[5]) != 0);
16830 mod_s = (enum memmodel) INTVAL (operands[6]);
16831 mod_f = (enum memmodel) INTVAL (operands[7]);
16832 mode = GET_MODE (mem);
16834 mask = shift = NULL_RTX;
16835 if (mode == QImode || mode == HImode)
16837 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
16839 /* Shift and mask OLDVAL into position with the word. */
16840 oldval = convert_modes (SImode, mode, oldval, 1);
16841 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
16842 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16844 /* Shift and mask NEWVAL into position within the word. */
16845 newval = convert_modes (SImode, mode, newval, 1);
16846 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
16847 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16849 /* Prepare to adjust the return value. */
16850 retval = gen_reg_rtx (SImode);
16853 else if (reg_overlap_mentioned_p (retval, oldval))
16854 oldval = copy_to_reg (oldval);
16856 rs6000_pre_atomic_barrier (mod_s);
16861 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16862 emit_label (XEXP (label1, 0));
16864 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16866 emit_load_locked (mode, retval, mem);
16871 x = expand_simple_binop (SImode, AND, retval, mask,
16872 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16875 cond = gen_reg_rtx (CCmode);
16876 x = gen_rtx_COMPARE (CCmode, x, oldval);
16877 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
16879 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16880 emit_unlikely_jump (x, label2);
16884 x = rs6000_mask_atomic_subword (retval, newval, mask);
16886 emit_store_conditional (mode, cond, mem, x);
16890 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16891 emit_unlikely_jump (x, label1);
16894 if (mod_f != MEMMODEL_RELAXED)
16895 emit_label (XEXP (label2, 0));
16897 rs6000_post_atomic_barrier (mod_s);
16899 if (mod_f == MEMMODEL_RELAXED)
16900 emit_label (XEXP (label2, 0));
16903 rs6000_finish_atomic_subword (operands[1], retval, shift);
16905 /* In all cases, CR0 contains EQ on success, and NE on failure. */
16906 x = gen_rtx_EQ (SImode, cond, const0_rtx);
16907 emit_insn (gen_rtx_SET (VOIDmode, boolval, x));
16910 /* Expand an atomic exchange operation. */
16913 rs6000_expand_atomic_exchange (rtx operands[])
16915 rtx retval, mem, val, cond;
16916 enum machine_mode mode;
16917 enum memmodel model;
16918 rtx label, x, mask, shift;
16920 retval = operands[0];
16923 model = (enum memmodel) INTVAL (operands[3]);
16924 mode = GET_MODE (mem);
16926 mask = shift = NULL_RTX;
16927 if (mode == QImode || mode == HImode)
16929 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
16931 /* Shift and mask VAL into position with the word. */
16932 val = convert_modes (SImode, mode, val, 1);
16933 val = expand_simple_binop (SImode, ASHIFT, val, shift,
16934 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16936 /* Prepare to adjust the return value. */
16937 retval = gen_reg_rtx (SImode);
16941 rs6000_pre_atomic_barrier (model);
16943 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16944 emit_label (XEXP (label, 0));
16946 emit_load_locked (mode, retval, mem);
16950 x = rs6000_mask_atomic_subword (retval, val, mask);
16952 cond = gen_reg_rtx (CCmode);
16953 emit_store_conditional (mode, cond, mem, x);
16955 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16956 emit_unlikely_jump (x, label);
16958 rs6000_post_atomic_barrier (model);
16961 rs6000_finish_atomic_subword (operands[0], retval, shift);
16964 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
16965 to perform. MEM is the memory on which to operate. VAL is the second
16966 operand of the binary operator. BEFORE and AFTER are optional locations to
16967 return the value of MEM either before of after the operation. MODEL_RTX
16968 is a CONST_INT containing the memory model to use. */
16971 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
16972 rtx orig_before, rtx orig_after, rtx model_rtx)
16974 enum memmodel model = (enum memmodel) INTVAL (model_rtx);
16975 enum machine_mode mode = GET_MODE (mem);
16976 rtx label, x, cond, mask, shift;
16977 rtx before = orig_before, after = orig_after;
16979 mask = shift = NULL_RTX;
16980 if (mode == QImode || mode == HImode)
16982 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
16984 /* Shift and mask VAL into position with the word. */
16985 val = convert_modes (SImode, mode, val, 1);
16986 val = expand_simple_binop (SImode, ASHIFT, val, shift,
16987 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16993 /* We've already zero-extended VAL. That is sufficient to
16994 make certain that it does not affect other bits. */
16999 /* If we make certain that all of the other bits in VAL are
17000 set, that will be sufficient to not affect other bits. */
17001 x = gen_rtx_NOT (SImode, mask);
17002 x = gen_rtx_IOR (SImode, x, val);
17003 emit_insn (gen_rtx_SET (VOIDmode, val, x));
17010 /* These will all affect bits outside the field and need
17011 adjustment via MASK within the loop. */
17015 gcc_unreachable ();
17018 /* Prepare to adjust the return value. */
17019 before = gen_reg_rtx (SImode);
17021 after = gen_reg_rtx (SImode);
17025 rs6000_pre_atomic_barrier (model);
17027 label = gen_label_rtx ();
17028 emit_label (label);
17029 label = gen_rtx_LABEL_REF (VOIDmode, label);
17031 if (before == NULL_RTX)
17032 before = gen_reg_rtx (mode);
17034 emit_load_locked (mode, before, mem);
17038 x = expand_simple_binop (mode, AND, before, val,
17039 NULL_RTX, 1, OPTAB_LIB_WIDEN);
17040 after = expand_simple_unop (mode, NOT, x, after, 1);
17044 after = expand_simple_binop (mode, code, before, val,
17045 after, 1, OPTAB_LIB_WIDEN);
17051 x = expand_simple_binop (SImode, AND, after, mask,
17052 NULL_RTX, 1, OPTAB_LIB_WIDEN);
17053 x = rs6000_mask_atomic_subword (before, x, mask);
17056 cond = gen_reg_rtx (CCmode);
17057 emit_store_conditional (mode, cond, mem, x);
17059 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
17060 emit_unlikely_jump (x, label);
17062 rs6000_post_atomic_barrier (model);
17067 rs6000_finish_atomic_subword (orig_before, before, shift);
17069 rs6000_finish_atomic_subword (orig_after, after, shift);
17071 else if (orig_after && after != orig_after)
17072 emit_move_insn (orig_after, after);
17075 /* Emit instructions to move SRC to DST. Called by splitters for
17076 multi-register moves. It will emit at most one instruction for
17077 each register that is accessed; that is, it won't emit li/lis pairs
17078 (or equivalent for 64-bit code). One of SRC or DST must be a hard
17082 rs6000_split_multireg_move (rtx dst, rtx src)
17084 /* The register number of the first register being moved. */
17086 /* The mode that is to be moved. */
17087 enum machine_mode mode;
17088 /* The mode that the move is being done in, and its size. */
17089 enum machine_mode reg_mode;
17091 /* The number of registers that will be moved. */
17094 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
17095 mode = GET_MODE (dst);
17096 nregs = hard_regno_nregs[reg][mode];
17097 if (FP_REGNO_P (reg))
17098 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
17099 ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
17100 else if (ALTIVEC_REGNO_P (reg))
17101 reg_mode = V16QImode;
17102 else if (TARGET_E500_DOUBLE && mode == TFmode)
17105 reg_mode = word_mode;
17106 reg_mode_size = GET_MODE_SIZE (reg_mode);
17108 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
17110 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
17112 /* Move register range backwards, if we might have destructive
17115 for (i = nregs - 1; i >= 0; i--)
17116 emit_insn (gen_rtx_SET (VOIDmode,
17117 simplify_gen_subreg (reg_mode, dst, mode,
17118 i * reg_mode_size),
17119 simplify_gen_subreg (reg_mode, src, mode,
17120 i * reg_mode_size)));
17126 bool used_update = false;
17127 rtx restore_basereg = NULL_RTX;
17129 if (MEM_P (src) && INT_REGNO_P (reg))
17133 if (GET_CODE (XEXP (src, 0)) == PRE_INC
17134 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
17137 breg = XEXP (XEXP (src, 0), 0);
17138 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
17139 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
17140 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
17141 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
17142 src = replace_equiv_address (src, breg);
17144 else if (! rs6000_offsettable_memref_p (src))
17146 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
17148 rtx basereg = XEXP (XEXP (src, 0), 0);
17151 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
17152 emit_insn (gen_rtx_SET (VOIDmode, ndst,
17153 gen_rtx_MEM (reg_mode, XEXP (src, 0))));
17154 used_update = true;
17157 emit_insn (gen_rtx_SET (VOIDmode, basereg,
17158 XEXP (XEXP (src, 0), 1)));
17159 src = replace_equiv_address (src, basereg);
17163 rtx basereg = gen_rtx_REG (Pmode, reg);
17164 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
17165 src = replace_equiv_address (src, basereg);
17169 breg = XEXP (src, 0);
17170 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
17171 breg = XEXP (breg, 0);
17173 /* If the base register we are using to address memory is
17174 also a destination reg, then change that register last. */
17176 && REGNO (breg) >= REGNO (dst)
17177 && REGNO (breg) < REGNO (dst) + nregs)
17178 j = REGNO (breg) - REGNO (dst);
17180 else if (MEM_P (dst) && INT_REGNO_P (reg))
17184 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
17185 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
17188 breg = XEXP (XEXP (dst, 0), 0);
17189 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
17190 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
17191 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
17193 /* We have to update the breg before doing the store.
17194 Use store with update, if available. */
17198 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
17199 emit_insn (TARGET_32BIT
17200 ? (TARGET_POWERPC64
17201 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
17202 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
17203 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
17204 used_update = true;
17207 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
17208 dst = replace_equiv_address (dst, breg);
17210 else if (!rs6000_offsettable_memref_p (dst)
17211 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
17213 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
17215 rtx basereg = XEXP (XEXP (dst, 0), 0);
17218 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
17219 emit_insn (gen_rtx_SET (VOIDmode,
17220 gen_rtx_MEM (reg_mode, XEXP (dst, 0)), nsrc));
17221 used_update = true;
17224 emit_insn (gen_rtx_SET (VOIDmode, basereg,
17225 XEXP (XEXP (dst, 0), 1)));
17226 dst = replace_equiv_address (dst, basereg);
17230 rtx basereg = XEXP (XEXP (dst, 0), 0);
17231 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
17232 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
17234 && REG_P (offsetreg)
17235 && REGNO (basereg) != REGNO (offsetreg));
17236 if (REGNO (basereg) == 0)
17238 rtx tmp = offsetreg;
17239 offsetreg = basereg;
17242 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
17243 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
17244 dst = replace_equiv_address (dst, basereg);
17247 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
17248 gcc_assert (rs6000_offsettable_memref_p (dst));
17251 for (i = 0; i < nregs; i++)
17253 /* Calculate index to next subword. */
17258 /* If compiler already emitted move of first word by
17259 store with update, no need to do anything. */
17260 if (j == 0 && used_update)
17263 emit_insn (gen_rtx_SET (VOIDmode,
17264 simplify_gen_subreg (reg_mode, dst, mode,
17265 j * reg_mode_size),
17266 simplify_gen_subreg (reg_mode, src, mode,
17267 j * reg_mode_size)));
17269 if (restore_basereg != NULL_RTX)
17270 emit_insn (restore_basereg);
17275 /* This page contains routines that are used to determine what the
17276 function prologue and epilogue code will do and write them out. */
17278 /* Return the first fixed-point register that is required to be
17279 saved. 32 if none. */
17282 first_reg_to_save (void)
17286 /* Find lowest numbered live register. */
17287 for (first_reg = 13; first_reg <= 31; first_reg++)
17288 if (df_regs_ever_live_p (first_reg)
17289 && (! call_used_regs[first_reg]
17290 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
17291 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
17292 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
17293 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
17298 && crtl->uses_pic_offset_table
17299 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
17300 return RS6000_PIC_OFFSET_TABLE_REGNUM;
17306 /* Similar, for FP regs. */
17309 first_fp_reg_to_save (void)
17313 /* Find lowest numbered live register. */
17314 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
17315 if (df_regs_ever_live_p (first_reg))
17321 /* Similar, for AltiVec regs. */
17324 first_altivec_reg_to_save (void)
17328 /* Stack frame remains as is unless we are in AltiVec ABI. */
17329 if (! TARGET_ALTIVEC_ABI)
17330 return LAST_ALTIVEC_REGNO + 1;
17332 /* On Darwin, the unwind routines are compiled without
17333 TARGET_ALTIVEC, and use save_world to save/restore the
17334 altivec registers when necessary. */
17335 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
17336 && ! TARGET_ALTIVEC)
17337 return FIRST_ALTIVEC_REGNO + 20;
17339 /* Find lowest numbered live register. */
17340 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
17341 if (df_regs_ever_live_p (i))
17347 /* Return a 32-bit mask of the AltiVec registers we need to set in
17348 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
17349 the 32-bit word is 0. */
17351 static unsigned int
17352 compute_vrsave_mask (void)
17354 unsigned int i, mask = 0;
17356 /* On Darwin, the unwind routines are compiled without
17357 TARGET_ALTIVEC, and use save_world to save/restore the
17358 call-saved altivec registers when necessary. */
17359 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
17360 && ! TARGET_ALTIVEC)
17363 /* First, find out if we use _any_ altivec registers. */
17364 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
17365 if (df_regs_ever_live_p (i))
17366 mask |= ALTIVEC_REG_BIT (i);
17371 /* Next, remove the argument registers from the set. These must
17372 be in the VRSAVE mask set by the caller, so we don't need to add
17373 them in again. More importantly, the mask we compute here is
17374 used to generate CLOBBERs in the set_vrsave insn, and we do not
17375 wish the argument registers to die. */
17376 for (i = crtl->args.info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
17377 mask &= ~ALTIVEC_REG_BIT (i);
17379 /* Similarly, remove the return value from the set. */
17382 diddle_return_value (is_altivec_return_reg, &yes);
17384 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
17390 /* For a very restricted set of circumstances, we can cut down the
17391 size of prologues/epilogues by calling our own save/restore-the-world
17395 compute_save_world_info (rs6000_stack_t *info_ptr)
17397 info_ptr->world_save_p = 1;
17398 info_ptr->world_save_p
17399 = (WORLD_SAVE_P (info_ptr)
17400 && DEFAULT_ABI == ABI_DARWIN
17401 && !cfun->has_nonlocal_label
17402 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
17403 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
17404 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
17405 && info_ptr->cr_save_p);
17407 /* This will not work in conjunction with sibcalls. Make sure there
17408 are none. (This check is expensive, but seldom executed.) */
17409 if (WORLD_SAVE_P (info_ptr))
17412 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
17413 if ( GET_CODE (insn) == CALL_INSN
17414 && SIBLING_CALL_P (insn))
17416 info_ptr->world_save_p = 0;
17421 if (WORLD_SAVE_P (info_ptr))
17423 /* Even if we're not touching VRsave, make sure there's room on the
17424 stack for it, if it looks like we're calling SAVE_WORLD, which
17425 will attempt to save it. */
17426 info_ptr->vrsave_size = 4;
17428 /* If we are going to save the world, we need to save the link register too. */
17429 info_ptr->lr_save_p = 1;
17431 /* "Save" the VRsave register too if we're saving the world. */
17432 if (info_ptr->vrsave_mask == 0)
17433 info_ptr->vrsave_mask = compute_vrsave_mask ();
17435 /* Because the Darwin register save/restore routines only handle
17436 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
17438 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
17439 && (info_ptr->first_altivec_reg_save
17440 >= FIRST_SAVED_ALTIVEC_REGNO));
17447 is_altivec_return_reg (rtx reg, void *xyes)
17449 bool *yes = (bool *) xyes;
17450 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
17455 /* Determine the strategy for savings/restoring registers. */
17458 SAVRES_MULTIPLE = 0x1,
17459 SAVE_INLINE_FPRS = 0x2,
17460 SAVE_INLINE_GPRS = 0x4,
17461 REST_INLINE_FPRS = 0x8,
17462 REST_INLINE_GPRS = 0x10,
17463 SAVE_NOINLINE_GPRS_SAVES_LR = 0x20,
17464 SAVE_NOINLINE_FPRS_SAVES_LR = 0x40,
17465 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x80
17469 rs6000_savres_strategy (rs6000_stack_t *info,
17470 bool using_static_chain_p)
17474 if (TARGET_MULTIPLE
17475 && !TARGET_POWERPC64
17476 && !(TARGET_SPE_ABI && info->spe_64bit_regs_used)
17477 && info->first_gp_reg_save < 31
17478 && no_global_regs_above (info->first_gp_reg_save, /*gpr=*/true))
17479 strategy |= SAVRES_MULTIPLE;
17481 if (crtl->calls_eh_return
17482 || cfun->machine->ra_need_lr
17483 || info->total_size > 32767)
17484 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
17485 | SAVE_INLINE_GPRS | REST_INLINE_GPRS);
17487 if (info->first_fp_reg_save == 64
17488 || FP_SAVE_INLINE (info->first_fp_reg_save)
17489 /* The out-of-line FP routines use double-precision stores;
17490 we can't use those routines if we don't have such stores. */
17491 || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT)
17492 || !no_global_regs_above (info->first_fp_reg_save, /*gpr=*/false))
17493 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
17495 if (info->first_gp_reg_save == 32
17496 || GP_SAVE_INLINE (info->first_gp_reg_save)
17497 || !((strategy & SAVRES_MULTIPLE)
17498 || no_global_regs_above (info->first_gp_reg_save, /*gpr=*/true)))
17499 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17501 /* Don't bother to try to save things out-of-line if r11 is occupied
17502 by the static chain. It would require too much fiddling and the
17503 static chain is rarely used anyway. FPRs are saved w.r.t the stack
17504 pointer on Darwin. */
17505 if (using_static_chain_p)
17506 strategy |= (DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
17507 | SAVE_INLINE_GPRS;
17509 /* If we are going to use store multiple, then don't even bother
17510 with the out-of-line routines, since the store-multiple
17511 instruction will always be smaller. */
17512 if ((strategy & SAVRES_MULTIPLE))
17513 strategy |= SAVE_INLINE_GPRS;
17515 /* The situation is more complicated with load multiple. We'd
17516 prefer to use the out-of-line routines for restores, since the
17517 "exit" out-of-line routines can handle the restore of LR and the
17518 frame teardown. However if doesn't make sense to use the
17519 out-of-line routine if that is the only reason we'd need to save
17520 LR, and we can't use the "exit" out-of-line gpr restore if we
17521 have saved some fprs; In those cases it is advantageous to use
17522 load multiple when available. */
17523 if ((strategy & SAVRES_MULTIPLE)
17524 && (!info->lr_save_p
17525 || info->first_fp_reg_save != 64))
17526 strategy |= REST_INLINE_GPRS;
17528 /* We can only use load multiple or the out-of-line routines to
17529 restore if we've used store multiple or out-of-line routines
17530 in the prologue, i.e. if we've saved all the registers from
17531 first_gp_reg_save. Otherwise, we risk loading garbage. */
17532 if ((strategy & (SAVE_INLINE_GPRS | SAVRES_MULTIPLE)) == SAVE_INLINE_GPRS)
17533 strategy |= REST_INLINE_GPRS;
17535 /* Saving CR interferes with the exit routines used on the SPE, so
17538 && info->spe_64bit_regs_used
17539 && info->cr_save_p)
17540 strategy |= REST_INLINE_GPRS;
17542 #ifdef POWERPC_LINUX
17545 if (!(strategy & SAVE_INLINE_FPRS))
17546 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
17547 else if (!(strategy & SAVE_INLINE_GPRS)
17548 && info->first_fp_reg_save == 64)
17549 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
17552 if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
17553 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
17555 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
17556 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
17561 /* Calculate the stack information for the current function. This is
17562 complicated by having two separate calling sequences, the AIX calling
17563 sequence and the V.4 calling sequence.
17565 AIX (and Darwin/Mac OS X) stack frames look like:
17567 SP----> +---------------------------------------+
17568 | back chain to caller | 0 0
17569 +---------------------------------------+
17570 | saved CR | 4 8 (8-11)
17571 +---------------------------------------+
17573 +---------------------------------------+
17574 | reserved for compilers | 12 24
17575 +---------------------------------------+
17576 | reserved for binders | 16 32
17577 +---------------------------------------+
17578 | saved TOC pointer | 20 40
17579 +---------------------------------------+
17580 | Parameter save area (P) | 24 48
17581 +---------------------------------------+
17582 | Alloca space (A) | 24+P etc.
17583 +---------------------------------------+
17584 | Local variable space (L) | 24+P+A
17585 +---------------------------------------+
17586 | Float/int conversion temporary (X) | 24+P+A+L
17587 +---------------------------------------+
17588 | Save area for AltiVec registers (W) | 24+P+A+L+X
17589 +---------------------------------------+
17590 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
17591 +---------------------------------------+
17592 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
17593 +---------------------------------------+
17594 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
17595 +---------------------------------------+
17596 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
17597 +---------------------------------------+
17598 old SP->| back chain to caller's caller |
17599 +---------------------------------------+
17601 The required alignment for AIX configurations is two words (i.e., 8
17605 V.4 stack frames look like:
17607 SP----> +---------------------------------------+
17608 | back chain to caller | 0
17609 +---------------------------------------+
17610 | caller's saved LR | 4
17611 +---------------------------------------+
17612 | Parameter save area (P) | 8
17613 +---------------------------------------+
17614 | Alloca space (A) | 8+P
17615 +---------------------------------------+
17616 | Varargs save area (V) | 8+P+A
17617 +---------------------------------------+
17618 | Local variable space (L) | 8+P+A+V
17619 +---------------------------------------+
17620 | Float/int conversion temporary (X) | 8+P+A+V+L
17621 +---------------------------------------+
17622 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
17623 +---------------------------------------+
17624 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
17625 +---------------------------------------+
17626 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
17627 +---------------------------------------+
17628 | SPE: area for 64-bit GP registers |
17629 +---------------------------------------+
17630 | SPE alignment padding |
17631 +---------------------------------------+
17632 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
17633 +---------------------------------------+
17634 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
17635 +---------------------------------------+
17636 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
17637 +---------------------------------------+
17638 old SP->| back chain to caller's caller |
17639 +---------------------------------------+
17641 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
17642 given. (But note below and in sysv4.h that we require only 8 and
17643 may round up the size of our stack frame anyways. The historical
17644 reason is early versions of powerpc-linux which didn't properly
17645 align the stack at program startup. A happy side-effect is that
17646 -mno-eabi libraries can be used with -meabi programs.)
17648 The EABI configuration defaults to the V.4 layout. However,
17649 the stack alignment requirements may differ. If -mno-eabi is not
17650 given, the required stack alignment is 8 bytes; if -mno-eabi is
17651 given, the required alignment is 16 bytes. (But see V.4 comment
17654 #ifndef ABI_STACK_BOUNDARY
17655 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
17658 static rs6000_stack_t *
17659 rs6000_stack_info (void)
17661 rs6000_stack_t *info_ptr = &stack_info;
17662 int reg_size = TARGET_32BIT ? 4 : 8;
17666 HOST_WIDE_INT non_fixed_size;
17667 bool using_static_chain_p;
17669 if (reload_completed && info_ptr->reload_completed)
17672 memset (info_ptr, 0, sizeof (*info_ptr));
17673 info_ptr->reload_completed = reload_completed;
17677 /* Cache value so we don't rescan instruction chain over and over. */
17678 if (cfun->machine->insn_chain_scanned_p == 0)
17679 cfun->machine->insn_chain_scanned_p
17680 = spe_func_has_64bit_regs_p () + 1;
17681 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
17684 /* Select which calling sequence. */
17685 info_ptr->abi = DEFAULT_ABI;
17687 /* Calculate which registers need to be saved & save area size. */
17688 info_ptr->first_gp_reg_save = first_reg_to_save ();
17689 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
17690 even if it currently looks like we won't. Reload may need it to
17691 get at a constant; if so, it will have already created a constant
17692 pool entry for it. */
17693 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
17694 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
17695 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
17696 && crtl->uses_const_pool
17697 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
17698 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
17700 first_gp = info_ptr->first_gp_reg_save;
17702 info_ptr->gp_size = reg_size * (32 - first_gp);
17704 /* For the SPE, we have an additional upper 32-bits on each GPR.
17705 Ideally we should save the entire 64-bits only when the upper
17706 half is used in SIMD instructions. Since we only record
17707 registers live (not the size they are used in), this proves
17708 difficult because we'd have to traverse the instruction chain at
17709 the right time, taking reload into account. This is a real pain,
17710 so we opt to save the GPRs in 64-bits always if but one register
17711 gets used in 64-bits. Otherwise, all the registers in the frame
17712 get saved in 32-bits.
17714 So... since when we save all GPRs (except the SP) in 64-bits, the
17715 traditional GP save area will be empty. */
17716 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
17717 info_ptr->gp_size = 0;
17719 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
17720 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
17722 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
17723 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
17724 - info_ptr->first_altivec_reg_save);
17726 /* Does this function call anything? */
17727 info_ptr->calls_p = (! current_function_is_leaf
17728 || cfun->machine->ra_needs_full_frame);
17730 /* Determine if we need to save the condition code registers. */
17731 if (df_regs_ever_live_p (CR2_REGNO)
17732 || df_regs_ever_live_p (CR3_REGNO)
17733 || df_regs_ever_live_p (CR4_REGNO))
17735 info_ptr->cr_save_p = 1;
17736 if (DEFAULT_ABI == ABI_V4)
17737 info_ptr->cr_size = reg_size;
17740 /* If the current function calls __builtin_eh_return, then we need
17741 to allocate stack space for registers that will hold data for
17742 the exception handler. */
17743 if (crtl->calls_eh_return)
17746 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
17749 /* SPE saves EH registers in 64-bits. */
17750 ehrd_size = i * (TARGET_SPE_ABI
17751 && info_ptr->spe_64bit_regs_used != 0
17752 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
17757 /* Determine various sizes. */
17758 info_ptr->reg_size = reg_size;
17759 info_ptr->fixed_size = RS6000_SAVE_AREA;
17760 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
17761 info_ptr->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
17762 TARGET_ALTIVEC ? 16 : 8);
17763 if (FRAME_GROWS_DOWNWARD)
17764 info_ptr->vars_size
17765 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
17766 + info_ptr->parm_size,
17767 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
17768 - (info_ptr->fixed_size + info_ptr->vars_size
17769 + info_ptr->parm_size);
17771 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
17772 info_ptr->spe_gp_size = 8 * (32 - first_gp);
17774 info_ptr->spe_gp_size = 0;
17776 if (TARGET_ALTIVEC_ABI)
17777 info_ptr->vrsave_mask = compute_vrsave_mask ();
17779 info_ptr->vrsave_mask = 0;
17781 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
17782 info_ptr->vrsave_size = 4;
17784 info_ptr->vrsave_size = 0;
17786 compute_save_world_info (info_ptr);
17788 /* Calculate the offsets. */
17789 switch (DEFAULT_ABI)
17793 gcc_unreachable ();
17797 info_ptr->fp_save_offset = - info_ptr->fp_size;
17798 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
17800 if (TARGET_ALTIVEC_ABI)
17802 info_ptr->vrsave_save_offset
17803 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
17805 /* Align stack so vector save area is on a quadword boundary.
17806 The padding goes above the vectors. */
17807 if (info_ptr->altivec_size != 0)
17808 info_ptr->altivec_padding_size
17809 = info_ptr->vrsave_save_offset & 0xF;
17811 info_ptr->altivec_padding_size = 0;
17813 info_ptr->altivec_save_offset
17814 = info_ptr->vrsave_save_offset
17815 - info_ptr->altivec_padding_size
17816 - info_ptr->altivec_size;
17817 gcc_assert (info_ptr->altivec_size == 0
17818 || info_ptr->altivec_save_offset % 16 == 0);
17820 /* Adjust for AltiVec case. */
17821 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
17824 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
17825 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
17826 info_ptr->lr_save_offset = 2*reg_size;
17830 info_ptr->fp_save_offset = - info_ptr->fp_size;
17831 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
17832 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
17834 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
17836 /* Align stack so SPE GPR save area is aligned on a
17837 double-word boundary. */
17838 if (info_ptr->spe_gp_size != 0 && info_ptr->cr_save_offset != 0)
17839 info_ptr->spe_padding_size
17840 = 8 - (-info_ptr->cr_save_offset % 8);
17842 info_ptr->spe_padding_size = 0;
17844 info_ptr->spe_gp_save_offset
17845 = info_ptr->cr_save_offset
17846 - info_ptr->spe_padding_size
17847 - info_ptr->spe_gp_size;
17849 /* Adjust for SPE case. */
17850 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
17852 else if (TARGET_ALTIVEC_ABI)
17854 info_ptr->vrsave_save_offset
17855 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
17857 /* Align stack so vector save area is on a quadword boundary. */
17858 if (info_ptr->altivec_size != 0)
17859 info_ptr->altivec_padding_size
17860 = 16 - (-info_ptr->vrsave_save_offset % 16);
17862 info_ptr->altivec_padding_size = 0;
17864 info_ptr->altivec_save_offset
17865 = info_ptr->vrsave_save_offset
17866 - info_ptr->altivec_padding_size
17867 - info_ptr->altivec_size;
17869 /* Adjust for AltiVec case. */
17870 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
17873 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
17874 info_ptr->ehrd_offset -= ehrd_size;
17875 info_ptr->lr_save_offset = reg_size;
17879 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
17880 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
17881 + info_ptr->gp_size
17882 + info_ptr->altivec_size
17883 + info_ptr->altivec_padding_size
17884 + info_ptr->spe_gp_size
17885 + info_ptr->spe_padding_size
17887 + info_ptr->cr_size
17888 + info_ptr->vrsave_size,
17891 non_fixed_size = (info_ptr->vars_size
17892 + info_ptr->parm_size
17893 + info_ptr->save_size);
17895 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
17896 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
17898 /* Determine if we need to save the link register. */
17899 if (info_ptr->calls_p
17900 || (DEFAULT_ABI == ABI_AIX
17902 && !TARGET_PROFILE_KERNEL)
17903 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
17904 #ifdef TARGET_RELOCATABLE
17905 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
17907 || rs6000_ra_ever_killed ())
17908 info_ptr->lr_save_p = 1;
17910 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
17911 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
17912 && call_used_regs[STATIC_CHAIN_REGNUM]);
17913 info_ptr->savres_strategy = rs6000_savres_strategy (info_ptr,
17914 using_static_chain_p);
17916 if (!(info_ptr->savres_strategy & SAVE_INLINE_GPRS)
17917 || !(info_ptr->savres_strategy & SAVE_INLINE_FPRS)
17918 || !(info_ptr->savres_strategy & REST_INLINE_GPRS)
17919 || !(info_ptr->savres_strategy & REST_INLINE_FPRS))
17920 info_ptr->lr_save_p = 1;
17922 if (info_ptr->lr_save_p)
17923 df_set_regs_ever_live (LR_REGNO, true);
17925 /* Determine if we need to allocate any stack frame:
17927 For AIX we need to push the stack if a frame pointer is needed
17928 (because the stack might be dynamically adjusted), if we are
17929 debugging, if we make calls, or if the sum of fp_save, gp_save,
17930 and local variables are more than the space needed to save all
17931 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
17932 + 18*8 = 288 (GPR13 reserved).
17934 For V.4 we don't have the stack cushion that AIX uses, but assume
17935 that the debugger can handle stackless frames. */
17937 if (info_ptr->calls_p)
17938 info_ptr->push_p = 1;
17940 else if (DEFAULT_ABI == ABI_V4)
17941 info_ptr->push_p = non_fixed_size != 0;
17943 else if (frame_pointer_needed)
17944 info_ptr->push_p = 1;
17946 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
17947 info_ptr->push_p = 1;
17950 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
17952 /* Zero offsets if we're not saving those registers. */
17953 if (info_ptr->fp_size == 0)
17954 info_ptr->fp_save_offset = 0;
17956 if (info_ptr->gp_size == 0)
17957 info_ptr->gp_save_offset = 0;
17959 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
17960 info_ptr->altivec_save_offset = 0;
17962 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
17963 info_ptr->vrsave_save_offset = 0;
17965 if (! TARGET_SPE_ABI
17966 || info_ptr->spe_64bit_regs_used == 0
17967 || info_ptr->spe_gp_size == 0)
17968 info_ptr->spe_gp_save_offset = 0;
17970 if (! info_ptr->lr_save_p)
17971 info_ptr->lr_save_offset = 0;
17973 if (! info_ptr->cr_save_p)
17974 info_ptr->cr_save_offset = 0;
17979 /* Return true if the current function uses any GPRs in 64-bit SIMD
17983 spe_func_has_64bit_regs_p (void)
17987 /* Functions that save and restore all the call-saved registers will
17988 need to save/restore the registers in 64-bits. */
17989 if (crtl->calls_eh_return
17990 || cfun->calls_setjmp
17991 || crtl->has_nonlocal_goto)
17994 insns = get_insns ();
17996 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
18002 /* FIXME: This should be implemented with attributes...
18004 (set_attr "spe64" "true")....then,
18005 if (get_spe64(insn)) return true;
18007 It's the only reliable way to do the stuff below. */
18009 i = PATTERN (insn);
18010 if (GET_CODE (i) == SET)
18012 enum machine_mode mode = GET_MODE (SET_SRC (i));
18014 if (SPE_VECTOR_MODE (mode))
18016 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
18026 debug_stack_info (rs6000_stack_t *info)
18028 const char *abi_string;
18031 info = rs6000_stack_info ();
18033 fprintf (stderr, "\nStack information for function %s:\n",
18034 ((current_function_decl && DECL_NAME (current_function_decl))
18035 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
18040 default: abi_string = "Unknown"; break;
18041 case ABI_NONE: abi_string = "NONE"; break;
18042 case ABI_AIX: abi_string = "AIX"; break;
18043 case ABI_DARWIN: abi_string = "Darwin"; break;
18044 case ABI_V4: abi_string = "V.4"; break;
18047 fprintf (stderr, "\tABI = %5s\n", abi_string);
18049 if (TARGET_ALTIVEC_ABI)
18050 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
18052 if (TARGET_SPE_ABI)
18053 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
18055 if (info->first_gp_reg_save != 32)
18056 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
18058 if (info->first_fp_reg_save != 64)
18059 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
18061 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
18062 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
18063 info->first_altivec_reg_save);
18065 if (info->lr_save_p)
18066 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
18068 if (info->cr_save_p)
18069 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
18071 if (info->vrsave_mask)
18072 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
18075 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
18078 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
18080 if (info->gp_save_offset)
18081 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
18083 if (info->fp_save_offset)
18084 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
18086 if (info->altivec_save_offset)
18087 fprintf (stderr, "\taltivec_save_offset = %5d\n",
18088 info->altivec_save_offset);
18090 if (info->spe_gp_save_offset)
18091 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
18092 info->spe_gp_save_offset);
18094 if (info->vrsave_save_offset)
18095 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
18096 info->vrsave_save_offset);
18098 if (info->lr_save_offset)
18099 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
18101 if (info->cr_save_offset)
18102 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
18104 if (info->varargs_save_offset)
18105 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
18107 if (info->total_size)
18108 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
18111 if (info->vars_size)
18112 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
18115 if (info->parm_size)
18116 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
18118 if (info->fixed_size)
18119 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
18122 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
18124 if (info->spe_gp_size)
18125 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
18128 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
18130 if (info->altivec_size)
18131 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
18133 if (info->vrsave_size)
18134 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
18136 if (info->altivec_padding_size)
18137 fprintf (stderr, "\taltivec_padding_size= %5d\n",
18138 info->altivec_padding_size);
18140 if (info->spe_padding_size)
18141 fprintf (stderr, "\tspe_padding_size = %5d\n",
18142 info->spe_padding_size);
18145 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
18147 if (info->save_size)
18148 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
18150 if (info->reg_size != 4)
18151 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
18153 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
18155 fprintf (stderr, "\n");
18159 rs6000_return_addr (int count, rtx frame)
18161 /* Currently we don't optimize very well between prolog and body
18162 code and for PIC code the code can be actually quite bad, so
18163 don't try to be too clever here. */
18164 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
18166 cfun->machine->ra_needs_full_frame = 1;
18173 plus_constant (copy_to_reg
18174 (gen_rtx_MEM (Pmode,
18175 memory_address (Pmode, frame))),
18176 RETURN_ADDRESS_OFFSET)));
18179 cfun->machine->ra_need_lr = 1;
18180 return get_hard_reg_initial_val (Pmode, LR_REGNO);
18183 /* Say whether a function is a candidate for sibcall handling or not. */
18186 rs6000_function_ok_for_sibcall (tree decl, tree exp)
18191 fntype = TREE_TYPE (decl);
18193 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
18195 /* We can't do it if the called function has more vector parameters
18196 than the current function; there's nowhere to put the VRsave code. */
18197 if (TARGET_ALTIVEC_ABI
18198 && TARGET_ALTIVEC_VRSAVE
18199 && !(decl && decl == current_function_decl))
18201 function_args_iterator args_iter;
18205 /* Functions with vector parameters are required to have a
18206 prototype, so the argument type info must be available
18208 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
18209 if (TREE_CODE (type) == VECTOR_TYPE
18210 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
18213 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
18214 if (TREE_CODE (type) == VECTOR_TYPE
18215 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
18222 /* Under the AIX ABI we can't allow calls to non-local functions,
18223 because the callee may have a different TOC pointer to the
18224 caller and there's no way to ensure we restore the TOC when we
18225 return. With the secure-plt SYSV ABI we can't make non-local
18226 calls when -fpic/PIC because the plt call stubs use r30. */
18227 if (DEFAULT_ABI == ABI_DARWIN
18228 || (DEFAULT_ABI == ABI_AIX
18230 && !DECL_EXTERNAL (decl)
18231 && (*targetm.binds_local_p) (decl))
18232 || (DEFAULT_ABI == ABI_V4
18233 && (!TARGET_SECURE_PLT
18236 && (*targetm.binds_local_p) (decl)))))
18238 tree attr_list = TYPE_ATTRIBUTES (fntype);
18240 if (!lookup_attribute ("longcall", attr_list)
18241 || lookup_attribute ("shortcall", attr_list))
18248 /* NULL if INSN insn is valid within a low-overhead loop.
18249 Otherwise return why doloop cannot be applied.
18250 PowerPC uses the COUNT register for branch on table instructions. */
18252 static const char *
18253 rs6000_invalid_within_doloop (const_rtx insn)
18256 return "Function call in the loop.";
18259 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
18260 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
18261 return "Computed branch in the loop.";
18267 rs6000_ra_ever_killed (void)
18273 if (cfun->is_thunk)
18276 if (cfun->machine->lr_save_state)
18277 return cfun->machine->lr_save_state - 1;
18279 /* regs_ever_live has LR marked as used if any sibcalls are present,
18280 but this should not force saving and restoring in the
18281 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
18282 clobbers LR, so that is inappropriate. */
18284 /* Also, the prologue can generate a store into LR that
18285 doesn't really count, like this:
18288 bcl to set PIC register
18292 When we're called from the epilogue, we need to avoid counting
18293 this as a store. */
18295 push_topmost_sequence ();
18296 top = get_insns ();
18297 pop_topmost_sequence ();
18298 reg = gen_rtx_REG (Pmode, LR_REGNO);
18300 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
18306 if (!SIBLING_CALL_P (insn))
18309 else if (find_regno_note (insn, REG_INC, LR_REGNO))
18311 else if (set_of (reg, insn) != NULL_RTX
18312 && !prologue_epilogue_contains (insn))
18319 /* Emit instructions needed to load the TOC register.
18320 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
18321 a constant pool; or for SVR4 -fpic. */
18324 rs6000_emit_load_toc_table (int fromprolog)
18327 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
18329 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
18332 rtx lab, tmp1, tmp2, got;
18334 lab = gen_label_rtx ();
18335 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
18336 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18338 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
18340 got = rs6000_got_sym ();
18341 tmp1 = tmp2 = dest;
18344 tmp1 = gen_reg_rtx (Pmode);
18345 tmp2 = gen_reg_rtx (Pmode);
18347 emit_insn (gen_load_toc_v4_PIC_1 (lab));
18348 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
18349 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
18350 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
18352 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
18354 emit_insn (gen_load_toc_v4_pic_si ());
18355 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18357 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
18360 rtx temp0 = (fromprolog
18361 ? gen_rtx_REG (Pmode, 0)
18362 : gen_reg_rtx (Pmode));
18368 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
18369 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18371 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
18372 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18374 emit_insn (gen_load_toc_v4_PIC_1 (symF));
18375 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18376 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
18382 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
18383 lab = gen_label_rtx ();
18384 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
18385 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18386 if (TARGET_LINK_STACK)
18387 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
18388 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
18390 emit_insn (gen_addsi3 (dest, temp0, dest));
18392 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
18394 /* This is for AIX code running in non-PIC ELF32. */
18397 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
18398 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18400 emit_insn (gen_elf_high (dest, realsym));
18401 emit_insn (gen_elf_low (dest, dest, realsym));
18405 gcc_assert (DEFAULT_ABI == ABI_AIX);
18408 emit_insn (gen_load_toc_aix_si (dest));
18410 emit_insn (gen_load_toc_aix_di (dest));
18414 /* Emit instructions to restore the link register after determining where
18415 its value has been stored. */
18418 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
18420 rs6000_stack_t *info = rs6000_stack_info ();
18423 operands[0] = source;
18424 operands[1] = scratch;
18426 if (info->lr_save_p)
18428 rtx frame_rtx = stack_pointer_rtx;
18429 HOST_WIDE_INT sp_offset = 0;
18432 if (frame_pointer_needed
18433 || cfun->calls_alloca
18434 || info->total_size > 32767)
18436 tmp = gen_frame_mem (Pmode, frame_rtx);
18437 emit_move_insn (operands[1], tmp);
18438 frame_rtx = operands[1];
18440 else if (info->push_p)
18441 sp_offset = info->total_size;
18443 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
18444 tmp = gen_frame_mem (Pmode, tmp);
18445 emit_move_insn (tmp, operands[0]);
18448 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
18450 /* Freeze lr_save_p. We've just emitted rtl that depends on the
18451 state of lr_save_p so any change from here on would be a bug. In
18452 particular, stop rs6000_ra_ever_killed from considering the SET
18453 of lr we may have added just above. */
18454 cfun->machine->lr_save_state = info->lr_save_p + 1;
18457 static GTY(()) alias_set_type set = -1;
18460 get_TOC_alias_set (void)
18463 set = new_alias_set ();
18467 /* This returns nonzero if the current function uses the TOC. This is
18468 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
18469 is generated by the ABI_V4 load_toc_* patterns. */
18476 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
18479 rtx pat = PATTERN (insn);
18482 if (GET_CODE (pat) == PARALLEL)
18483 for (i = 0; i < XVECLEN (pat, 0); i++)
18485 rtx sub = XVECEXP (pat, 0, i);
18486 if (GET_CODE (sub) == USE)
18488 sub = XEXP (sub, 0);
18489 if (GET_CODE (sub) == UNSPEC
18490 && XINT (sub, 1) == UNSPEC_TOC)
18500 create_TOC_reference (rtx symbol, rtx largetoc_reg)
18502 rtx tocrel, tocreg;
18504 if (TARGET_DEBUG_ADDR)
18506 if (GET_CODE (symbol) == SYMBOL_REF)
18507 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
18511 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
18512 GET_RTX_NAME (GET_CODE (symbol)));
18513 debug_rtx (symbol);
18517 if (!can_create_pseudo_p ())
18518 df_set_regs_ever_live (TOC_REGISTER, true);
18520 tocrel = gen_rtx_CONST (Pmode,
18521 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol),
18523 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
18524 if (TARGET_CMODEL != CMODEL_SMALL)
18526 rtx hi = gen_rtx_CONST (Pmode,
18527 gen_rtx_PLUS (Pmode, tocreg,
18528 gen_rtx_HIGH (Pmode, tocrel)));
18529 if (largetoc_reg != NULL)
18531 emit_move_insn (largetoc_reg, hi);
18534 return gen_rtx_LO_SUM (Pmode, hi, copy_rtx (tocrel));
18537 return gen_rtx_PLUS (Pmode, tocreg, tocrel);
18540 /* Issue assembly directives that create a reference to the given DWARF
18541 FRAME_TABLE_LABEL from the current function section. */
18543 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
18545 fprintf (asm_out_file, "\t.ref %s\n",
18546 TARGET_STRIP_NAME_ENCODING (frame_table_label));
18549 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
18550 and the change to the stack pointer. */
18553 rs6000_emit_stack_tie (void)
18555 rtx mem = gen_frame_mem (BLKmode,
18556 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
18558 emit_insn (gen_stack_tie (mem));
18561 /* Emit the correct code for allocating stack space, as insns.
18562 If COPY_REG, make sure a copy of the old frame is left there.
18563 The generated code may use hard register 0 as a temporary. */
18566 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg)
18569 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
18570 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
18571 rtx todec = gen_int_mode (-size, Pmode);
18574 if (INTVAL (todec) != -size)
18576 warning (0, "stack frame too large");
18577 emit_insn (gen_trap ());
18581 if (crtl->limit_stack)
18583 if (REG_P (stack_limit_rtx)
18584 && REGNO (stack_limit_rtx) > 1
18585 && REGNO (stack_limit_rtx) <= 31)
18587 emit_insn (gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size)));
18588 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
18591 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
18593 && DEFAULT_ABI == ABI_V4)
18595 rtx toload = gen_rtx_CONST (VOIDmode,
18596 gen_rtx_PLUS (Pmode,
18600 emit_insn (gen_elf_high (tmp_reg, toload));
18601 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
18602 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
18606 warning (0, "stack limit expression is not supported");
18610 emit_move_insn (copy_reg, stack_reg);
18614 /* Need a note here so that try_split doesn't get confused. */
18615 if (get_last_insn () == NULL_RTX)
18616 emit_note (NOTE_INSN_DELETED);
18617 insn = emit_move_insn (tmp_reg, todec);
18618 try_split (PATTERN (insn), insn, 0);
18622 insn = emit_insn (TARGET_32BIT
18623 ? gen_movsi_update_stack (stack_reg, stack_reg,
18625 : gen_movdi_di_update_stack (stack_reg, stack_reg,
18626 todec, stack_reg));
18627 /* Since we didn't use gen_frame_mem to generate the MEM, grab
18628 it now and set the alias set/attributes. The above gen_*_update
18629 calls will generate a PARALLEL with the MEM set being the first
18631 par = PATTERN (insn);
18632 gcc_assert (GET_CODE (par) == PARALLEL);
18633 set = XVECEXP (par, 0, 0);
18634 gcc_assert (GET_CODE (set) == SET);
18635 mem = SET_DEST (set);
18636 gcc_assert (MEM_P (mem));
18637 MEM_NOTRAP_P (mem) = 1;
18638 set_mem_alias_set (mem, get_frame_alias_set ());
18640 RTX_FRAME_RELATED_P (insn) = 1;
18641 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
18642 gen_rtx_SET (VOIDmode, stack_reg,
18643 gen_rtx_PLUS (Pmode, stack_reg,
18644 GEN_INT (-size))));
18647 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
18649 #if PROBE_INTERVAL > 32768
18650 #error Cannot use indexed addressing mode for stack probing
18653 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
18654 inclusive. These are offsets from the current stack pointer. */
18657 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
18659 /* See if we have a constant small number of probes to generate. If so,
18660 that's the easy case. */
18661 if (first + size <= 32768)
18665 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
18666 it exceeds SIZE. If only one probe is needed, this will not
18667 generate any code. Then probe at FIRST + SIZE. */
18668 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
18669 emit_stack_probe (plus_constant (stack_pointer_rtx, -(first + i)));
18671 emit_stack_probe (plus_constant (stack_pointer_rtx, -(first + size)));
18674 /* Otherwise, do the same as above, but in a loop. Note that we must be
18675 extra careful with variables wrapping around because we might be at
18676 the very top (or the very bottom) of the address space and we have
18677 to be able to handle this case properly; in particular, we use an
18678 equality test for the loop condition. */
18681 HOST_WIDE_INT rounded_size;
18682 rtx r12 = gen_rtx_REG (Pmode, 12);
18683 rtx r0 = gen_rtx_REG (Pmode, 0);
18685 /* Sanity check for the addressing mode we're going to use. */
18686 gcc_assert (first <= 32768);
18688 /* Step 1: round SIZE to the previous multiple of the interval. */
18690 rounded_size = size & -PROBE_INTERVAL;
18693 /* Step 2: compute initial and final value of the loop counter. */
18695 /* TEST_ADDR = SP + FIRST. */
18696 emit_insn (gen_rtx_SET (VOIDmode, r12,
18697 plus_constant (stack_pointer_rtx, -first)));
18699 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
18700 if (rounded_size > 32768)
18702 emit_move_insn (r0, GEN_INT (-rounded_size));
18703 emit_insn (gen_rtx_SET (VOIDmode, r0,
18704 gen_rtx_PLUS (Pmode, r12, r0)));
18707 emit_insn (gen_rtx_SET (VOIDmode, r0,
18708 plus_constant (r12, -rounded_size)));
18711 /* Step 3: the loop
18713 while (TEST_ADDR != LAST_ADDR)
18715 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
18719 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
18720 until it is equal to ROUNDED_SIZE. */
18723 emit_insn (gen_probe_stack_rangedi (r12, r12, r0));
18725 emit_insn (gen_probe_stack_rangesi (r12, r12, r0));
18728 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
18729 that SIZE is equal to ROUNDED_SIZE. */
18731 if (size != rounded_size)
18732 emit_stack_probe (plus_constant (r12, rounded_size - size));
18736 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
18737 absolute addresses. */
18740 output_probe_stack_range (rtx reg1, rtx reg2)
18742 static int labelno = 0;
18743 char loop_lab[32], end_lab[32];
18746 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
18747 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
18749 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
18751 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
18755 output_asm_insn ("{cmp|cmpd} 0,%0,%1", xops);
18757 output_asm_insn ("{cmp|cmpw} 0,%0,%1", xops);
18759 fputs ("\tbeq 0,", asm_out_file);
18760 assemble_name_raw (asm_out_file, end_lab);
18761 fputc ('\n', asm_out_file);
18763 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
18764 xops[1] = GEN_INT (-PROBE_INTERVAL);
18765 output_asm_insn ("{cal %0,%1(%0)|addi %0,%0,%1}", xops);
18767 /* Probe at TEST_ADDR and branch. */
18768 xops[1] = gen_rtx_REG (Pmode, 0);
18769 output_asm_insn ("{st|stw} %1,0(%0)", xops);
18770 fprintf (asm_out_file, "\tb ");
18771 assemble_name_raw (asm_out_file, loop_lab);
18772 fputc ('\n', asm_out_file);
18774 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
18779 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
18780 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
18781 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
18782 deduce these equivalences by itself so it wasn't necessary to hold
18783 its hand so much. */
18786 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
18787 rtx reg2, rtx rreg)
18791 /* copy_rtx will not make unique copies of registers, so we need to
18792 ensure we don't have unwanted sharing here. */
18794 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
18797 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
18799 real = copy_rtx (PATTERN (insn));
18801 if (reg2 != NULL_RTX)
18802 real = replace_rtx (real, reg2, rreg);
18804 real = replace_rtx (real, reg,
18805 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
18806 STACK_POINTER_REGNUM),
18809 /* We expect that 'real' is either a SET or a PARALLEL containing
18810 SETs (and possibly other stuff). In a PARALLEL, all the SETs
18811 are important so they all have to be marked RTX_FRAME_RELATED_P. */
18813 if (GET_CODE (real) == SET)
18817 temp = simplify_rtx (SET_SRC (set));
18819 SET_SRC (set) = temp;
18820 temp = simplify_rtx (SET_DEST (set));
18822 SET_DEST (set) = temp;
18823 if (GET_CODE (SET_DEST (set)) == MEM)
18825 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
18827 XEXP (SET_DEST (set), 0) = temp;
18834 gcc_assert (GET_CODE (real) == PARALLEL);
18835 for (i = 0; i < XVECLEN (real, 0); i++)
18836 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
18838 rtx set = XVECEXP (real, 0, i);
18840 temp = simplify_rtx (SET_SRC (set));
18842 SET_SRC (set) = temp;
18843 temp = simplify_rtx (SET_DEST (set));
18845 SET_DEST (set) = temp;
18846 if (GET_CODE (SET_DEST (set)) == MEM)
18848 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
18850 XEXP (SET_DEST (set), 0) = temp;
18852 RTX_FRAME_RELATED_P (set) = 1;
18856 RTX_FRAME_RELATED_P (insn) = 1;
18857 add_reg_note (insn, REG_FRAME_RELATED_EXPR, real);
18862 /* Returns an insn that has a vrsave set operation with the
18863 appropriate CLOBBERs. */
18866 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
18869 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
18870 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
18873 = gen_rtx_SET (VOIDmode,
18875 gen_rtx_UNSPEC_VOLATILE (SImode,
18876 gen_rtvec (2, reg, vrsave),
18877 UNSPECV_SET_VRSAVE));
18881 /* We need to clobber the registers in the mask so the scheduler
18882 does not move sets to VRSAVE before sets of AltiVec registers.
18884 However, if the function receives nonlocal gotos, reload will set
18885 all call saved registers live. We will end up with:
18887 (set (reg 999) (mem))
18888 (parallel [ (set (reg vrsave) (unspec blah))
18889 (clobber (reg 999))])
18891 The clobber will cause the store into reg 999 to be dead, and
18892 flow will attempt to delete an epilogue insn. In this case, we
18893 need an unspec use/set of the register. */
18895 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
18896 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
18898 if (!epiloguep || call_used_regs [i])
18899 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
18900 gen_rtx_REG (V4SImode, i));
18903 rtx reg = gen_rtx_REG (V4SImode, i);
18906 = gen_rtx_SET (VOIDmode,
18908 gen_rtx_UNSPEC (V4SImode,
18909 gen_rtvec (1, reg), 27));
18913 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
18915 for (i = 0; i < nclobs; ++i)
18916 XVECEXP (insn, 0, i) = clobs[i];
18921 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
18922 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
18925 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
18926 unsigned int regno, int offset, HOST_WIDE_INT total_size)
18928 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
18929 rtx replacea, replaceb;
18931 int_rtx = GEN_INT (offset);
18933 /* Some cases that need register indexed addressing. */
18934 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
18935 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
18936 || (TARGET_E500_DOUBLE && mode == DFmode)
18938 && SPE_VECTOR_MODE (mode)
18939 && !SPE_CONST_OFFSET_OK (offset)))
18941 /* Whomever calls us must make sure r11 is available in the
18942 flow path of instructions in the prologue. */
18943 offset_rtx = gen_rtx_REG (Pmode, 11);
18944 emit_move_insn (offset_rtx, int_rtx);
18946 replacea = offset_rtx;
18947 replaceb = int_rtx;
18951 offset_rtx = int_rtx;
18952 replacea = NULL_RTX;
18953 replaceb = NULL_RTX;
18956 reg = gen_rtx_REG (mode, regno);
18957 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
18958 mem = gen_frame_mem (mode, addr);
18960 insn = emit_move_insn (mem, reg);
18962 return rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
18965 /* Emit an offset memory reference suitable for a frame store, while
18966 converting to a valid addressing mode. */
18969 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
18971 rtx int_rtx, offset_rtx;
18973 int_rtx = GEN_INT (offset);
18975 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
18976 || (TARGET_E500_DOUBLE && mode == DFmode))
18978 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
18979 emit_move_insn (offset_rtx, int_rtx);
18982 offset_rtx = int_rtx;
18984 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
18987 /* Look for user-defined global regs. We should not save and restore these,
18988 and cannot use stmw/lmw if there are any in its range. */
18991 no_global_regs_above (int first, bool gpr)
18994 int last = gpr ? 32 : 64;
18995 for (i = first; i < last; i++)
18996 if (global_regs[i])
19001 #ifndef TARGET_FIX_AND_CONTINUE
19002 #define TARGET_FIX_AND_CONTINUE 0
19005 /* It's really GPR 13 and FPR 14, but we need the smaller of the two. */
19006 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
19007 #define LAST_SAVRES_REGISTER 31
19008 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
19010 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][8];
19012 /* Temporary holding space for an out-of-line register save/restore
19014 static char savres_routine_name[30];
19016 /* Return the name for an out-of-line register save/restore routine.
19017 We are saving/restoring GPRs if GPR is true. */
19020 rs6000_savres_routine_name (rs6000_stack_t *info, int regno,
19021 bool savep, bool gpr, bool lr)
19023 const char *prefix = "";
19024 const char *suffix = "";
19026 /* Different targets are supposed to define
19027 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
19028 routine name could be defined with:
19030 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
19032 This is a nice idea in practice, but in reality, things are
19033 complicated in several ways:
19035 - ELF targets have save/restore routines for GPRs.
19037 - SPE targets use different prefixes for 32/64-bit registers, and
19038 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
19040 - PPC64 ELF targets have routines for save/restore of GPRs that
19041 differ in what they do with the link register, so having a set
19042 prefix doesn't work. (We only use one of the save routines at
19043 the moment, though.)
19045 - PPC32 elf targets have "exit" versions of the restore routines
19046 that restore the link register and can save some extra space.
19047 These require an extra suffix. (There are also "tail" versions
19048 of the restore routines and "GOT" versions of the save routines,
19049 but we don't generate those at present. Same problems apply,
19052 We deal with all this by synthesizing our own prefix/suffix and
19053 using that for the simple sprintf call shown above. */
19056 /* No floating point saves on the SPE. */
19060 prefix = info->spe_64bit_regs_used ? "_save64gpr_" : "_save32gpr_";
19062 prefix = info->spe_64bit_regs_used ? "_rest64gpr_" : "_rest32gpr_";
19067 else if (DEFAULT_ABI == ABI_V4)
19073 prefix = savep ? "_savegpr_" : "_restgpr_";
19075 prefix = savep ? "_savefpr_" : "_restfpr_";
19080 else if (DEFAULT_ABI == ABI_AIX)
19082 #ifndef POWERPC_LINUX
19083 /* No out-of-line save/restore routines for GPRs on AIX. */
19084 gcc_assert (!TARGET_AIX || !gpr);
19090 ? (lr ? "_savegpr0_" : "_savegpr1_")
19091 : (lr ? "_restgpr0_" : "_restgpr1_"));
19092 #ifdef POWERPC_LINUX
19094 prefix = (savep ? "_savefpr_" : "_restfpr_");
19098 prefix = savep ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
19099 suffix = savep ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
19103 if (DEFAULT_ABI == ABI_DARWIN)
19105 /* The Darwin approach is (slightly) different, in order to be
19106 compatible with code generated by the system toolchain. There is a
19107 single symbol for the start of save sequence, and the code here
19108 embeds an offset into that code on the basis of the first register
19110 prefix = savep ? "save" : "rest" ;
19112 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31",
19113 prefix, (lr ? "x" : ""), (regno == 13 ? "" : "+"),
19114 (regno-13) * 4, prefix, regno);
19116 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31",
19117 prefix, (regno == 14 ? "" : "+"), (regno-14) * 4, prefix, regno);
19120 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
19122 return savres_routine_name;
19125 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
19126 We are saving/restoring GPRs if GPR is true. */
19129 rs6000_savres_routine_sym (rs6000_stack_t *info, bool savep,
19132 int regno = gpr ? info->first_gp_reg_save : (info->first_fp_reg_save - 32);
19134 int select = ((savep ? 1 : 0) << 2
19136 /* On the SPE, we never have any FPRs, but we do have
19137 32/64-bit versions of the routines. */
19138 ? (info->spe_64bit_regs_used ? 1 : 0)
19139 : (gpr ? 1 : 0)) << 1)
19142 /* Don't generate bogus routine names. */
19143 gcc_assert (FIRST_SAVRES_REGISTER <= regno
19144 && regno <= LAST_SAVRES_REGISTER);
19146 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
19152 name = rs6000_savres_routine_name (info, regno, savep, gpr, lr);
19154 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
19155 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
19156 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
19162 /* Emit a sequence of insns, including a stack tie if needed, for
19163 resetting the stack pointer. If SAVRES is true, then don't reset the
19164 stack pointer, but move the base of the frame into r11 for use by
19165 out-of-line register restore routines. */
19168 rs6000_emit_stack_reset (rs6000_stack_t *info,
19169 rtx sp_reg_rtx, rtx frame_reg_rtx,
19170 int sp_offset, bool savres)
19172 /* This blockage is needed so that sched doesn't decide to move
19173 the sp change before the register restores. */
19174 if (DEFAULT_ABI == ABI_V4
19176 && info->spe_64bit_regs_used != 0
19177 && info->first_gp_reg_save != 32))
19178 rs6000_emit_stack_tie ();
19180 if (frame_reg_rtx != sp_reg_rtx)
19182 if (sp_offset != 0)
19184 rtx dest_reg = savres ? gen_rtx_REG (Pmode, 11) : sp_reg_rtx;
19185 rtx insn = emit_insn (gen_add3_insn (dest_reg, frame_reg_rtx,
19186 GEN_INT (sp_offset)));
19191 return emit_move_insn (sp_reg_rtx, frame_reg_rtx);
19193 else if (sp_offset != 0)
19195 /* If we are restoring registers out-of-line, we will be using the
19196 "exit" variants of the restore routines, which will reset the
19197 stack for us. But we do need to point r11 into the right place
19198 for those routines. */
19199 rtx dest_reg = (savres
19200 ? gen_rtx_REG (Pmode, 11)
19203 rtx insn = emit_insn (gen_add3_insn (dest_reg, sp_reg_rtx,
19204 GEN_INT (sp_offset)));
19211 /* Construct a parallel rtx describing the effect of a call to an
19212 out-of-line register save/restore routine, and emit the insn
19213 or jump_insn as appropriate. */
19216 rs6000_emit_savres_rtx (rs6000_stack_t *info,
19217 rtx frame_reg_rtx, int save_area_offset,
19218 enum machine_mode reg_mode,
19219 bool savep, bool gpr, bool lr)
19222 int offset, start_reg, end_reg, n_regs, use_reg;
19223 int reg_size = GET_MODE_SIZE (reg_mode);
19230 ? info->first_gp_reg_save
19231 : info->first_fp_reg_save);
19232 end_reg = gpr ? 32 : 64;
19233 n_regs = end_reg - start_reg;
19234 p = rtvec_alloc ((lr ? 4 : 3) + n_regs);
19237 RTVEC_ELT (p, offset++) = ret_rtx;
19239 RTVEC_ELT (p, offset++)
19240 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
19242 sym = rs6000_savres_routine_sym (info, savep, gpr, lr);
19243 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
19244 use_reg = DEFAULT_ABI == ABI_AIX ? (gpr && !lr ? 12 : 1)
19245 : DEFAULT_ABI == ABI_DARWIN && !gpr ? 1
19247 RTVEC_ELT (p, offset++)
19248 = gen_rtx_USE (VOIDmode,
19249 gen_rtx_REG (Pmode, use_reg));
19251 for (i = 0; i < end_reg - start_reg; i++)
19253 rtx addr, reg, mem;
19254 reg = gen_rtx_REG (reg_mode, start_reg + i);
19255 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19256 GEN_INT (save_area_offset + reg_size*i));
19257 mem = gen_frame_mem (reg_mode, addr);
19259 RTVEC_ELT (p, i + offset) = gen_rtx_SET (VOIDmode,
19261 savep ? reg : mem);
19266 rtx addr, reg, mem;
19267 reg = gen_rtx_REG (Pmode, 0);
19268 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19269 GEN_INT (info->lr_save_offset));
19270 mem = gen_frame_mem (Pmode, addr);
19271 RTVEC_ELT (p, i + offset) = gen_rtx_SET (VOIDmode, mem, reg);
19274 par = gen_rtx_PARALLEL (VOIDmode, p);
19278 insn = emit_jump_insn (par);
19279 JUMP_LABEL (insn) = ret_rtx;
19282 insn = emit_insn (par);
19286 /* Determine whether the gp REG is really used. */
19289 rs6000_reg_live_or_pic_offset_p (int reg)
19291 /* If the function calls eh_return, claim used all the registers that would
19292 be checked for liveness otherwise. This is required for the PIC offset
19293 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
19294 register allocation purposes in this case. */
19296 return (((crtl->calls_eh_return || df_regs_ever_live_p (reg))
19297 && (!call_used_regs[reg]
19298 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
19299 && !TARGET_SINGLE_PIC_BASE
19300 && TARGET_TOC && TARGET_MINIMAL_TOC)))
19301 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
19302 && !TARGET_SINGLE_PIC_BASE
19303 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
19304 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
19307 /* Emit function prologue as insns. */
19310 rs6000_emit_prologue (void)
19312 rs6000_stack_t *info = rs6000_stack_info ();
19313 enum machine_mode reg_mode = Pmode;
19314 int reg_size = TARGET_32BIT ? 4 : 8;
19315 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
19316 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
19317 rtx frame_reg_rtx = sp_reg_rtx;
19318 rtx cr_save_rtx = NULL_RTX;
19321 int saving_FPRs_inline;
19322 int saving_GPRs_inline;
19323 int using_store_multiple;
19324 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
19325 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
19326 && call_used_regs[STATIC_CHAIN_REGNUM]);
19327 HOST_WIDE_INT sp_offset = 0;
19329 if (flag_stack_usage_info)
19330 current_function_static_stack_size = info->total_size;
19332 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && info->total_size)
19333 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT, info->total_size);
19335 if (TARGET_FIX_AND_CONTINUE)
19337 /* gdb on darwin arranges to forward a function from the old
19338 address by modifying the first 5 instructions of the function
19339 to branch to the overriding function. This is necessary to
19340 permit function pointers that point to the old function to
19341 actually forward to the new function. */
19342 emit_insn (gen_nop ());
19343 emit_insn (gen_nop ());
19344 emit_insn (gen_nop ());
19345 emit_insn (gen_nop ());
19346 emit_insn (gen_nop ());
19349 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
19351 reg_mode = V2SImode;
19355 strategy = info->savres_strategy;
19356 using_store_multiple = strategy & SAVRES_MULTIPLE;
19357 saving_FPRs_inline = strategy & SAVE_INLINE_FPRS;
19358 saving_GPRs_inline = strategy & SAVE_INLINE_GPRS;
19360 /* For V.4, update stack before we do any saving and set back pointer. */
19361 if (! WORLD_SAVE_P (info)
19363 && (DEFAULT_ABI == ABI_V4
19364 || crtl->calls_eh_return))
19366 bool need_r11 = (TARGET_SPE
19367 ? (!saving_GPRs_inline
19368 && info->spe_64bit_regs_used == 0)
19369 : (!saving_FPRs_inline || !saving_GPRs_inline));
19370 rtx copy_reg = need_r11 ? gen_rtx_REG (Pmode, 11) : NULL;
19372 if (info->total_size < 32767)
19373 sp_offset = info->total_size;
19375 frame_reg_rtx = copy_reg;
19376 else if (info->cr_save_p
19378 || info->first_fp_reg_save < 64
19379 || info->first_gp_reg_save < 32
19380 || info->altivec_size != 0
19381 || info->vrsave_mask != 0
19382 || crtl->calls_eh_return)
19384 copy_reg = frame_ptr_rtx;
19385 frame_reg_rtx = copy_reg;
19389 /* The prologue won't be saving any regs so there is no need
19390 to set up a frame register to access any frame save area.
19391 We also won't be using sp_offset anywhere below, but set
19392 the correct value anyway to protect against future
19393 changes to this function. */
19394 sp_offset = info->total_size;
19396 rs6000_emit_allocate_stack (info->total_size, copy_reg);
19397 if (frame_reg_rtx != sp_reg_rtx)
19398 rs6000_emit_stack_tie ();
19401 /* Handle world saves specially here. */
19402 if (WORLD_SAVE_P (info))
19409 /* save_world expects lr in r0. */
19410 reg0 = gen_rtx_REG (Pmode, 0);
19411 if (info->lr_save_p)
19413 insn = emit_move_insn (reg0,
19414 gen_rtx_REG (Pmode, LR_REGNO));
19415 RTX_FRAME_RELATED_P (insn) = 1;
19418 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
19419 assumptions about the offsets of various bits of the stack
19421 gcc_assert (info->gp_save_offset == -220
19422 && info->fp_save_offset == -144
19423 && info->lr_save_offset == 8
19424 && info->cr_save_offset == 4
19427 && (!crtl->calls_eh_return
19428 || info->ehrd_offset == -432)
19429 && info->vrsave_save_offset == -224
19430 && info->altivec_save_offset == -416);
19432 treg = gen_rtx_REG (SImode, 11);
19433 emit_move_insn (treg, GEN_INT (-info->total_size));
19435 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
19436 in R11. It also clobbers R12, so beware! */
19438 /* Preserve CR2 for save_world prologues */
19440 sz += 32 - info->first_gp_reg_save;
19441 sz += 64 - info->first_fp_reg_save;
19442 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
19443 p = rtvec_alloc (sz);
19445 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
19446 gen_rtx_REG (SImode,
19448 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
19449 gen_rtx_SYMBOL_REF (Pmode,
19451 /* We do floats first so that the instruction pattern matches
19453 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
19455 rtx reg = gen_rtx_REG (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
19456 ? DFmode : SFmode),
19457 info->first_fp_reg_save + i);
19458 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19459 GEN_INT (info->fp_save_offset
19460 + sp_offset + 8 * i));
19461 rtx mem = gen_frame_mem (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
19462 ? DFmode : SFmode), addr);
19464 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
19466 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
19468 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
19469 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19470 GEN_INT (info->altivec_save_offset
19471 + sp_offset + 16 * i));
19472 rtx mem = gen_frame_mem (V4SImode, addr);
19474 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
19476 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19478 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
19479 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19480 GEN_INT (info->gp_save_offset
19481 + sp_offset + reg_size * i));
19482 rtx mem = gen_frame_mem (reg_mode, addr);
19484 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
19488 /* CR register traditionally saved as CR2. */
19489 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
19490 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19491 GEN_INT (info->cr_save_offset
19493 rtx mem = gen_frame_mem (reg_mode, addr);
19495 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
19497 /* Explain about use of R0. */
19498 if (info->lr_save_p)
19500 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19501 GEN_INT (info->lr_save_offset
19503 rtx mem = gen_frame_mem (reg_mode, addr);
19505 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
19507 /* Explain what happens to the stack pointer. */
19509 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
19510 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
19513 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
19514 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19515 treg, GEN_INT (-info->total_size));
19516 sp_offset = info->total_size;
19519 /* If we use the link register, get it into r0. */
19520 if (!WORLD_SAVE_P (info) && info->lr_save_p)
19522 rtx addr, reg, mem;
19524 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
19525 gen_rtx_REG (Pmode, LR_REGNO));
19526 RTX_FRAME_RELATED_P (insn) = 1;
19528 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
19529 | SAVE_NOINLINE_FPRS_SAVES_LR)))
19531 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19532 GEN_INT (info->lr_save_offset + sp_offset));
19533 reg = gen_rtx_REG (Pmode, 0);
19534 mem = gen_rtx_MEM (Pmode, addr);
19535 /* This should not be of rs6000_sr_alias_set, because of
19536 __builtin_return_address. */
19538 insn = emit_move_insn (mem, reg);
19539 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19540 NULL_RTX, NULL_RTX);
19544 /* If we need to save CR, put it into r12 or r11. */
19545 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
19550 = gen_rtx_REG (SImode, DEFAULT_ABI == ABI_AIX && !saving_GPRs_inline
19552 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
19553 RTX_FRAME_RELATED_P (insn) = 1;
19554 /* Now, there's no way that dwarf2out_frame_debug_expr is going
19555 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
19556 But that's OK. All we have to do is specify that _one_ condition
19557 code register is saved in this stack slot. The thrower's epilogue
19558 will then restore all the call-saved registers.
19559 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
19560 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
19561 gen_rtx_REG (SImode, CR2_REGNO));
19562 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
19565 /* Do any required saving of fpr's. If only one or two to save, do
19566 it ourselves. Otherwise, call function. */
19567 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
19570 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
19571 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
19572 && ! call_used_regs[info->first_fp_reg_save+i]))
19573 emit_frame_save (frame_reg_rtx, frame_ptr_rtx,
19574 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
19576 info->first_fp_reg_save + i,
19577 info->fp_save_offset + sp_offset + 8 * i,
19580 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
19582 insn = rs6000_emit_savres_rtx (info, frame_reg_rtx,
19583 info->fp_save_offset + sp_offset,
19585 /*savep=*/true, /*gpr=*/false,
19587 & SAVE_NOINLINE_FPRS_SAVES_LR)
19589 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19590 NULL_RTX, NULL_RTX);
19593 /* Save GPRs. This is done as a PARALLEL if we are using
19594 the store-multiple instructions. */
19595 if (!WORLD_SAVE_P (info)
19597 && info->spe_64bit_regs_used != 0
19598 && info->first_gp_reg_save != 32)
19601 rtx spe_save_area_ptr;
19602 int save_ptr_to_sp;
19603 int ool_adjust = 0;
19605 /* Determine whether we can address all of the registers that need
19606 to be saved with an offset from frame_reg_rtx that fits in
19607 the small const field for SPE memory instructions. */
19608 int spe_regs_addressable
19609 = (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + sp_offset
19610 + reg_size * (32 - info->first_gp_reg_save - 1))
19611 && saving_GPRs_inline);
19614 if (spe_regs_addressable)
19616 spe_save_area_ptr = frame_reg_rtx;
19617 save_ptr_to_sp = info->total_size - sp_offset;
19618 spe_offset = info->spe_gp_save_offset + sp_offset;
19622 /* Make r11 point to the start of the SPE save area. We need
19623 to be careful here if r11 is holding the static chain. If
19624 it is, then temporarily save it in r0. */
19627 if (!saving_GPRs_inline)
19628 ool_adjust = 8 * (info->first_gp_reg_save
19629 - (FIRST_SAVRES_REGISTER + 1));
19630 offset = info->spe_gp_save_offset + sp_offset - ool_adjust;
19631 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
19632 save_ptr_to_sp = info->total_size - sp_offset + offset;
19635 if (using_static_chain_p)
19637 rtx r0 = gen_rtx_REG (Pmode, 0);
19638 gcc_assert (info->first_gp_reg_save > 11);
19640 emit_move_insn (r0, spe_save_area_ptr);
19642 emit_insn (gen_addsi3 (spe_save_area_ptr,
19643 frame_reg_rtx, GEN_INT (offset)));
19644 if (REGNO (frame_reg_rtx) == 11)
19645 sp_offset = -info->spe_gp_save_offset + ool_adjust;
19648 if (saving_GPRs_inline)
19650 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19651 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
19653 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
19654 rtx offset, addr, mem;
19656 /* We're doing all this to ensure that the offset fits into
19657 the immediate offset of 'evstdd'. */
19658 gcc_assert (SPE_CONST_OFFSET_OK (reg_size * i + spe_offset));
19660 offset = GEN_INT (reg_size * i + spe_offset);
19661 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
19662 mem = gen_rtx_MEM (V2SImode, addr);
19664 insn = emit_move_insn (mem, reg);
19666 rs6000_frame_related (insn,
19667 spe_save_area_ptr, save_ptr_to_sp,
19668 NULL_RTX, NULL_RTX);
19673 insn = rs6000_emit_savres_rtx (info, spe_save_area_ptr,
19674 ool_adjust, reg_mode,
19675 /*savep=*/true, /*gpr=*/true,
19678 rs6000_frame_related (insn, spe_save_area_ptr, save_ptr_to_sp,
19679 NULL_RTX, NULL_RTX);
19682 /* Move the static chain pointer back. */
19683 if (using_static_chain_p && !spe_regs_addressable)
19684 emit_move_insn (spe_save_area_ptr, gen_rtx_REG (Pmode, 0));
19686 else if (!WORLD_SAVE_P (info) && !saving_GPRs_inline)
19688 if (DEFAULT_ABI == ABI_DARWIN)
19690 rtx dest_reg = gen_rtx_REG (Pmode, 11);
19691 if (info->first_fp_reg_save == 64)
19693 /* we only need a copy, no fprs were saved. */
19694 if (dest_reg != frame_reg_rtx)
19695 emit_move_insn (dest_reg, frame_reg_rtx);
19699 int save_off = 8 * (64 - info->first_fp_reg_save);
19700 rtx offset = GEN_INT (sp_offset - save_off);
19702 if (REGNO (dest_reg) == REGNO (frame_reg_rtx))
19703 sp_offset = save_off;
19704 emit_insn (gen_add3_insn (dest_reg, frame_reg_rtx, offset));
19707 /* Need to adjust r11 (r12) if we saved any FPRs. */
19708 else if (info->first_fp_reg_save != 64)
19710 rtx dest_reg = gen_rtx_REG (Pmode, DEFAULT_ABI == ABI_AIX ? 12 : 11);
19711 int save_off = 8 * (64 - info->first_fp_reg_save);
19712 rtx offset = GEN_INT (sp_offset - save_off);
19714 if (REGNO (dest_reg) == REGNO (frame_reg_rtx))
19715 sp_offset = save_off;
19716 emit_insn (gen_add3_insn (dest_reg, frame_reg_rtx, offset));
19719 insn = rs6000_emit_savres_rtx (info, frame_reg_rtx,
19720 info->gp_save_offset + sp_offset,
19722 /*savep=*/true, /*gpr=*/true,
19724 & SAVE_NOINLINE_GPRS_SAVES_LR)
19726 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19727 NULL_RTX, NULL_RTX);
19729 else if (!WORLD_SAVE_P (info) && using_store_multiple)
19733 p = rtvec_alloc (32 - info->first_gp_reg_save);
19734 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19736 rtx addr, reg, mem;
19737 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
19738 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19739 GEN_INT (info->gp_save_offset
19742 mem = gen_frame_mem (reg_mode, addr);
19744 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
19746 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
19747 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19748 NULL_RTX, NULL_RTX);
19750 else if (!WORLD_SAVE_P (info))
19753 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19754 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
19756 rtx addr, reg, mem;
19757 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
19759 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19760 GEN_INT (info->gp_save_offset
19763 mem = gen_frame_mem (reg_mode, addr);
19765 insn = emit_move_insn (mem, reg);
19766 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19767 NULL_RTX, NULL_RTX);
19771 /* ??? There's no need to emit actual instructions here, but it's the
19772 easiest way to get the frame unwind information emitted. */
19773 if (crtl->calls_eh_return)
19775 unsigned int i, regno;
19779 regno = EH_RETURN_DATA_REGNO (i);
19780 if (regno == INVALID_REGNUM)
19783 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
19784 info->ehrd_offset + sp_offset
19785 + reg_size * (int) i,
19790 /* In AIX ABI we need to make sure r2 is really saved. */
19791 if (TARGET_AIX && crtl->calls_eh_return)
19793 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
19794 rtx save_insn, join_insn, note;
19795 long toc_restore_insn;
19797 gcc_assert (frame_reg_rtx == frame_ptr_rtx
19798 || frame_reg_rtx == sp_reg_rtx);
19799 tmp_reg = gen_rtx_REG (Pmode, 11);
19800 tmp_reg_si = gen_rtx_REG (SImode, 11);
19801 if (using_static_chain_p)
19802 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
19803 gcc_assert (saving_GPRs_inline && saving_FPRs_inline);
19804 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
19805 /* Peek at instruction to which this function returns. If it's
19806 restoring r2, then we know we've already saved r2. We can't
19807 unconditionally save r2 because the value we have will already
19808 be updated if we arrived at this function via a plt call or
19809 toc adjusting stub. */
19810 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
19811 toc_restore_insn = TARGET_32BIT ? 0x80410014 : 0xE8410028;
19812 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
19813 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
19814 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
19815 validate_condition_mode (EQ, CCUNSmode);
19816 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
19817 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
19818 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
19819 toc_save_done = gen_label_rtx ();
19820 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
19821 gen_rtx_EQ (VOIDmode, compare_result,
19823 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
19825 jump = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, jump));
19826 JUMP_LABEL (jump) = toc_save_done;
19827 LABEL_NUSES (toc_save_done) += 1;
19829 save_insn = emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode,
19830 TOC_REGNUM, sp_offset + 5 * reg_size,
19833 emit_label (toc_save_done);
19835 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
19836 have a CFG that has different saves along different paths.
19837 Move the note to a dummy blockage insn, which describes that
19838 R2 is unconditionally saved after the label. */
19839 /* ??? An alternate representation might be a special insn pattern
19840 containing both the branch and the store. That might let the
19841 code that minimizes the number of DW_CFA_advance opcodes better
19842 freedom in placing the annotations. */
19843 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
19845 remove_note (save_insn, note);
19846 RTX_FRAME_RELATED_P (save_insn) = 0;
19848 join_insn = emit_insn (gen_blockage ());
19849 REG_NOTES (join_insn) = note;
19850 RTX_FRAME_RELATED_P (join_insn) = 1;
19852 if (using_static_chain_p)
19853 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
19856 /* Save CR if we use any that must be preserved. */
19857 if (!WORLD_SAVE_P (info) && info->cr_save_p)
19859 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19860 GEN_INT (info->cr_save_offset + sp_offset));
19861 rtx mem = gen_frame_mem (SImode, addr);
19862 /* See the large comment above about why CR2_REGNO is used. */
19863 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
19865 /* If r12 was used to hold the original sp, copy cr into r0 now
19867 if (REGNO (frame_reg_rtx) == 12)
19871 cr_save_rtx = gen_rtx_REG (SImode, 0);
19872 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
19873 RTX_FRAME_RELATED_P (insn) = 1;
19874 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
19875 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
19877 insn = emit_move_insn (mem, cr_save_rtx);
19879 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19880 NULL_RTX, NULL_RTX);
19883 /* Update stack and set back pointer unless this is V.4,
19884 for which it was done previously. */
19885 if (!WORLD_SAVE_P (info) && info->push_p
19886 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
19888 rtx copy_reg = NULL;
19890 if (info->total_size < 32767)
19891 sp_offset = info->total_size;
19892 else if (info->altivec_size != 0
19893 || info->vrsave_mask != 0)
19895 copy_reg = frame_ptr_rtx;
19896 frame_reg_rtx = copy_reg;
19899 sp_offset = info->total_size;
19900 rs6000_emit_allocate_stack (info->total_size, copy_reg);
19901 if (frame_reg_rtx != sp_reg_rtx)
19902 rs6000_emit_stack_tie ();
19905 /* Set frame pointer, if needed. */
19906 if (frame_pointer_needed)
19908 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
19910 RTX_FRAME_RELATED_P (insn) = 1;
19913 /* Save AltiVec registers if needed. Save here because the red zone does
19914 not include AltiVec registers. */
19915 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
19919 /* There should be a non inline version of this, for when we
19920 are saving lots of vector registers. */
19921 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
19922 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
19924 rtx areg, savereg, mem;
19927 offset = info->altivec_save_offset + sp_offset
19928 + 16 * (i - info->first_altivec_reg_save);
19930 savereg = gen_rtx_REG (V4SImode, i);
19932 areg = gen_rtx_REG (Pmode, 0);
19933 emit_move_insn (areg, GEN_INT (offset));
19935 /* AltiVec addressing mode is [reg+reg]. */
19936 mem = gen_frame_mem (V4SImode,
19937 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
19939 insn = emit_move_insn (mem, savereg);
19941 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19942 areg, GEN_INT (offset));
19946 /* VRSAVE is a bit vector representing which AltiVec registers
19947 are used. The OS uses this to determine which vector
19948 registers to save on a context switch. We need to save
19949 VRSAVE on the stack frame, add whatever AltiVec registers we
19950 used in this function, and do the corresponding magic in the
19953 if (!WORLD_SAVE_P (info)
19955 && TARGET_ALTIVEC_VRSAVE
19956 && info->vrsave_mask != 0)
19958 rtx reg, mem, vrsave;
19961 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
19962 as frame_reg_rtx and r11 as the static chain pointer for
19963 nested functions. */
19964 reg = gen_rtx_REG (SImode, 0);
19965 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
19967 emit_insn (gen_get_vrsave_internal (reg));
19969 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
19972 offset = info->vrsave_save_offset + sp_offset;
19973 mem = gen_frame_mem (SImode,
19974 gen_rtx_PLUS (Pmode, frame_reg_rtx,
19975 GEN_INT (offset)));
19976 insn = emit_move_insn (mem, reg);
19978 /* Include the registers in the mask. */
19979 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
19981 insn = emit_insn (generate_set_vrsave (reg, info, 0));
19984 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
19985 if (!TARGET_SINGLE_PIC_BASE
19986 && ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
19987 || (DEFAULT_ABI == ABI_V4
19988 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
19989 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
19991 /* If emit_load_toc_table will use the link register, we need to save
19992 it. We use R12 for this purpose because emit_load_toc_table
19993 can use register 0. This allows us to use a plain 'blr' to return
19994 from the procedure more often. */
19995 int save_LR_around_toc_setup = (TARGET_ELF
19996 && DEFAULT_ABI != ABI_AIX
19998 && ! info->lr_save_p
19999 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
20000 if (save_LR_around_toc_setup)
20002 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
20004 insn = emit_move_insn (frame_ptr_rtx, lr);
20005 RTX_FRAME_RELATED_P (insn) = 1;
20007 rs6000_emit_load_toc_table (TRUE);
20009 insn = emit_move_insn (lr, frame_ptr_rtx);
20010 add_reg_note (insn, REG_CFA_RESTORE, lr);
20011 RTX_FRAME_RELATED_P (insn) = 1;
20014 rs6000_emit_load_toc_table (TRUE);
20018 if (!TARGET_SINGLE_PIC_BASE
20019 && DEFAULT_ABI == ABI_DARWIN
20020 && flag_pic && crtl->uses_pic_offset_table)
20022 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
20023 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
20025 /* Save and restore LR locally around this call (in R0). */
20026 if (!info->lr_save_p)
20027 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
20029 emit_insn (gen_load_macho_picbase (src));
20031 emit_move_insn (gen_rtx_REG (Pmode,
20032 RS6000_PIC_OFFSET_TABLE_REGNUM),
20035 if (!info->lr_save_p)
20036 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
20040 /* If we need to, save the TOC register after doing the stack setup.
20041 Do not emit eh frame info for this save. The unwinder wants info,
20042 conceptually attached to instructions in this function, about
20043 register values in the caller of this function. This R2 may have
20044 already been changed from the value in the caller.
20045 We don't attempt to write accurate DWARF EH frame info for R2
20046 because code emitted by gcc for a (non-pointer) function call
20047 doesn't save and restore R2. Instead, R2 is managed out-of-line
20048 by a linker generated plt call stub when the function resides in
20049 a shared library. This behaviour is costly to describe in DWARF,
20050 both in terms of the size of DWARF info and the time taken in the
20051 unwinder to interpret it. R2 changes, apart from the
20052 calls_eh_return case earlier in this function, are handled by
20053 linux-unwind.h frob_update_context. */
20054 if (rs6000_save_toc_in_prologue_p ())
20056 rtx addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, GEN_INT (5 * reg_size));
20057 rtx mem = gen_frame_mem (reg_mode, addr);
20058 emit_move_insn (mem, gen_rtx_REG (reg_mode, TOC_REGNUM));
20062 /* Write function prologue. */
20065 rs6000_output_function_prologue (FILE *file,
20066 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
20068 rs6000_stack_t *info = rs6000_stack_info ();
20070 if (TARGET_DEBUG_STACK)
20071 debug_stack_info (info);
20073 /* Write .extern for any function we will call to save and restore
20075 if (info->first_fp_reg_save < 64
20079 int regno = info->first_fp_reg_save - 32;
20081 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
20083 name = rs6000_savres_routine_name (info, regno, /*savep=*/true,
20084 /*gpr=*/false, /*lr=*/false);
20085 fprintf (file, "\t.extern %s\n", name);
20087 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
20089 name = rs6000_savres_routine_name (info, regno, /*savep=*/false,
20090 /*gpr=*/false, /*lr=*/true);
20091 fprintf (file, "\t.extern %s\n", name);
20095 /* Write .extern for AIX common mode routines, if needed. */
20096 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
20098 fputs ("\t.extern __mulh\n", file);
20099 fputs ("\t.extern __mull\n", file);
20100 fputs ("\t.extern __divss\n", file);
20101 fputs ("\t.extern __divus\n", file);
20102 fputs ("\t.extern __quoss\n", file);
20103 fputs ("\t.extern __quous\n", file);
20104 common_mode_defined = 1;
20107 rs6000_pic_labelno++;
20110 /* Non-zero if vmx regs are restored before the frame pop, zero if
20111 we restore after the pop when possible. */
20112 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
20114 /* Reload CR from REG. */
20117 rs6000_restore_saved_cr (rtx reg, int using_mfcr_multiple)
20122 if (using_mfcr_multiple)
20124 for (i = 0; i < 8; i++)
20125 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
20127 gcc_assert (count);
20130 if (using_mfcr_multiple && count > 1)
20135 p = rtvec_alloc (count);
20138 for (i = 0; i < 8; i++)
20139 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
20141 rtvec r = rtvec_alloc (2);
20142 RTVEC_ELT (r, 0) = reg;
20143 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
20144 RTVEC_ELT (p, ndx) =
20145 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
20146 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
20149 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
20150 gcc_assert (ndx == count);
20153 for (i = 0; i < 8; i++)
20154 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
20156 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
20162 /* Return true if OFFSET from stack pointer can be clobbered by signals.
20163 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
20164 below stack pointer not cloberred by signals. */
20167 offset_below_red_zone_p (HOST_WIDE_INT offset)
20169 return offset < (DEFAULT_ABI == ABI_V4
20171 : TARGET_32BIT ? -220 : -288);
20174 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
20177 emit_cfa_restores (rtx cfa_restores)
20179 rtx insn = get_last_insn ();
20180 rtx *loc = ®_NOTES (insn);
20183 loc = &XEXP (*loc, 1);
20184 *loc = cfa_restores;
20185 RTX_FRAME_RELATED_P (insn) = 1;
20188 /* Emit function epilogue as insns. */
20191 rs6000_emit_epilogue (int sibcall)
20193 rs6000_stack_t *info;
20194 int restoring_GPRs_inline;
20195 int restoring_FPRs_inline;
20196 int using_load_multiple;
20197 int using_mtcr_multiple;
20198 int use_backchain_to_restore_sp;
20202 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
20203 rtx frame_reg_rtx = sp_reg_rtx;
20204 rtx cfa_restores = NULL_RTX;
20206 rtx cr_save_reg = NULL_RTX;
20207 enum machine_mode reg_mode = Pmode;
20208 int reg_size = TARGET_32BIT ? 4 : 8;
20211 info = rs6000_stack_info ();
20213 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
20215 reg_mode = V2SImode;
20219 strategy = info->savres_strategy;
20220 using_load_multiple = strategy & SAVRES_MULTIPLE;
20221 restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS);
20222 restoring_GPRs_inline = sibcall || (strategy & REST_INLINE_GPRS);
20223 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
20224 || rs6000_cpu == PROCESSOR_PPC603
20225 || rs6000_cpu == PROCESSOR_PPC750
20227 /* Restore via the backchain when we have a large frame, since this
20228 is more efficient than an addis, addi pair. The second condition
20229 here will not trigger at the moment; We don't actually need a
20230 frame pointer for alloca, but the generic parts of the compiler
20231 give us one anyway. */
20232 use_backchain_to_restore_sp = (info->total_size > 32767 - info->lr_save_offset
20233 || (cfun->calls_alloca
20234 && !frame_pointer_needed));
20235 restore_lr = (info->lr_save_p
20236 && (restoring_FPRs_inline
20237 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
20238 && (restoring_GPRs_inline
20239 || info->first_fp_reg_save < 64));
20241 if (WORLD_SAVE_P (info))
20245 const char *alloc_rname;
20248 /* eh_rest_world_r10 will return to the location saved in the LR
20249 stack slot (which is not likely to be our caller.)
20250 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
20251 rest_world is similar, except any R10 parameter is ignored.
20252 The exception-handling stuff that was here in 2.95 is no
20253 longer necessary. */
20257 + 32 - info->first_gp_reg_save
20258 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
20259 + 63 + 1 - info->first_fp_reg_save);
20261 strcpy (rname, ((crtl->calls_eh_return) ?
20262 "*eh_rest_world_r10" : "*rest_world"));
20263 alloc_rname = ggc_strdup (rname);
20266 RTVEC_ELT (p, j++) = ret_rtx;
20267 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
20268 gen_rtx_REG (Pmode,
20271 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
20272 /* The instruction pattern requires a clobber here;
20273 it is shared with the restVEC helper. */
20275 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
20278 /* CR register traditionally saved as CR2. */
20279 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
20280 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20281 GEN_INT (info->cr_save_offset));
20282 rtx mem = gen_frame_mem (reg_mode, addr);
20284 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
20286 if (flag_shrink_wrap)
20288 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20289 gen_rtx_REG (Pmode, LR_REGNO),
20291 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20295 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20297 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
20298 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20299 GEN_INT (info->gp_save_offset
20301 rtx mem = gen_frame_mem (reg_mode, addr);
20303 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
20304 if (flag_shrink_wrap)
20305 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20307 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
20309 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
20310 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20311 GEN_INT (info->altivec_save_offset
20313 rtx mem = gen_frame_mem (V4SImode, addr);
20315 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
20316 if (flag_shrink_wrap)
20317 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20319 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
20321 rtx reg = gen_rtx_REG (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
20322 ? DFmode : SFmode),
20323 info->first_fp_reg_save + i);
20324 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20325 GEN_INT (info->fp_save_offset
20327 rtx mem = gen_frame_mem (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
20328 ? DFmode : SFmode), addr);
20330 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
20331 if (flag_shrink_wrap)
20332 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20335 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
20337 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
20339 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
20341 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
20343 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
20344 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
20346 if (flag_shrink_wrap)
20348 REG_NOTES (insn) = cfa_restores;
20349 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
20350 RTX_FRAME_RELATED_P (insn) = 1;
20355 /* frame_reg_rtx + sp_offset points to the top of this stack frame. */
20357 sp_offset = info->total_size;
20359 /* Restore AltiVec registers if we must do so before adjusting the
20361 if (TARGET_ALTIVEC_ABI
20362 && info->altivec_size != 0
20363 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20364 || (DEFAULT_ABI != ABI_V4
20365 && offset_below_red_zone_p (info->altivec_save_offset))))
20369 if (use_backchain_to_restore_sp)
20371 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20372 emit_move_insn (frame_reg_rtx,
20373 gen_rtx_MEM (Pmode, sp_reg_rtx));
20376 else if (frame_pointer_needed)
20377 frame_reg_rtx = hard_frame_pointer_rtx;
20379 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20380 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
20382 rtx addr, areg, mem, reg;
20384 areg = gen_rtx_REG (Pmode, 0);
20386 (areg, GEN_INT (info->altivec_save_offset
20388 + 16 * (i - info->first_altivec_reg_save)));
20390 /* AltiVec addressing mode is [reg+reg]. */
20391 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
20392 mem = gen_frame_mem (V4SImode, addr);
20394 reg = gen_rtx_REG (V4SImode, i);
20395 emit_move_insn (reg, mem);
20396 if (flag_shrink_wrap
20397 || offset_below_red_zone_p (info->altivec_save_offset
20398 + (i - info->first_altivec_reg_save)
20400 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
20405 /* Restore VRSAVE if we must do so before adjusting the stack. */
20407 && TARGET_ALTIVEC_VRSAVE
20408 && info->vrsave_mask != 0
20409 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20410 || (DEFAULT_ABI != ABI_V4
20411 && offset_below_red_zone_p (info->vrsave_save_offset))))
20413 rtx addr, mem, reg;
20415 if (frame_reg_rtx == sp_reg_rtx)
20417 if (use_backchain_to_restore_sp)
20419 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20420 emit_move_insn (frame_reg_rtx,
20421 gen_rtx_MEM (Pmode, sp_reg_rtx));
20424 else if (frame_pointer_needed)
20425 frame_reg_rtx = hard_frame_pointer_rtx;
20428 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20429 GEN_INT (info->vrsave_save_offset + sp_offset));
20430 mem = gen_frame_mem (SImode, addr);
20431 reg = gen_rtx_REG (SImode, 12);
20432 emit_move_insn (reg, mem);
20434 emit_insn (generate_set_vrsave (reg, info, 1));
20438 /* If we have a large stack frame, restore the old stack pointer
20439 using the backchain. */
20440 if (use_backchain_to_restore_sp)
20442 if (frame_reg_rtx == sp_reg_rtx)
20444 /* Under V.4, don't reset the stack pointer until after we're done
20445 loading the saved registers. */
20446 if (DEFAULT_ABI == ABI_V4)
20447 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20449 insn = emit_move_insn (frame_reg_rtx,
20450 gen_rtx_MEM (Pmode, sp_reg_rtx));
20453 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20454 && DEFAULT_ABI == ABI_V4)
20455 /* frame_reg_rtx has been set up by the altivec restore. */
20459 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
20460 frame_reg_rtx = sp_reg_rtx;
20463 /* If we have a frame pointer, we can restore the old stack pointer
20465 else if (frame_pointer_needed)
20467 frame_reg_rtx = sp_reg_rtx;
20468 if (DEFAULT_ABI == ABI_V4)
20469 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20470 /* Prevent reordering memory accesses against stack pointer restore. */
20471 else if (cfun->calls_alloca
20472 || offset_below_red_zone_p (-info->total_size))
20474 rtx mem1 = gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx);
20475 rtx mem2 = gen_rtx_MEM (BLKmode, sp_reg_rtx);
20476 MEM_NOTRAP_P (mem1) = 1;
20477 MEM_NOTRAP_P (mem2) = 1;
20478 emit_insn (gen_frame_tie (mem1, mem2));
20481 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
20482 GEN_INT (info->total_size)));
20485 else if (info->push_p
20486 && DEFAULT_ABI != ABI_V4
20487 && !crtl->calls_eh_return)
20489 /* Prevent reordering memory accesses against stack pointer restore. */
20490 if (cfun->calls_alloca
20491 || offset_below_red_zone_p (-info->total_size))
20493 rtx mem = gen_rtx_MEM (BLKmode, sp_reg_rtx);
20494 MEM_NOTRAP_P (mem) = 1;
20495 emit_insn (gen_stack_tie (mem));
20497 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
20498 GEN_INT (info->total_size)));
20501 if (insn && frame_reg_rtx == sp_reg_rtx)
20505 REG_NOTES (insn) = cfa_restores;
20506 cfa_restores = NULL_RTX;
20508 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
20509 RTX_FRAME_RELATED_P (insn) = 1;
20512 /* Restore AltiVec registers if we have not done so already. */
20513 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20514 && TARGET_ALTIVEC_ABI
20515 && info->altivec_size != 0
20516 && (DEFAULT_ABI == ABI_V4
20517 || !offset_below_red_zone_p (info->altivec_save_offset)))
20521 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20522 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
20524 rtx addr, areg, mem, reg;
20526 areg = gen_rtx_REG (Pmode, 0);
20528 (areg, GEN_INT (info->altivec_save_offset
20530 + 16 * (i - info->first_altivec_reg_save)));
20532 /* AltiVec addressing mode is [reg+reg]. */
20533 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
20534 mem = gen_frame_mem (V4SImode, addr);
20536 reg = gen_rtx_REG (V4SImode, i);
20537 emit_move_insn (reg, mem);
20538 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
20539 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
20544 /* Restore VRSAVE if we have not done so already. */
20545 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20547 && TARGET_ALTIVEC_VRSAVE
20548 && info->vrsave_mask != 0
20549 && (DEFAULT_ABI == ABI_V4
20550 || !offset_below_red_zone_p (info->vrsave_save_offset)))
20552 rtx addr, mem, reg;
20554 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20555 GEN_INT (info->vrsave_save_offset + sp_offset));
20556 mem = gen_frame_mem (SImode, addr);
20557 reg = gen_rtx_REG (SImode, 12);
20558 emit_move_insn (reg, mem);
20560 emit_insn (generate_set_vrsave (reg, info, 1));
20563 /* Get the old lr if we saved it. If we are restoring registers
20564 out-of-line, then the out-of-line routines can do this for us. */
20565 if (restore_lr && restoring_GPRs_inline)
20567 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
20568 info->lr_save_offset + sp_offset);
20570 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
20573 /* Get the old cr if we saved it. */
20574 if (info->cr_save_p)
20576 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20577 GEN_INT (info->cr_save_offset + sp_offset));
20578 rtx mem = gen_frame_mem (SImode, addr);
20580 cr_save_reg = gen_rtx_REG (SImode,
20581 DEFAULT_ABI == ABI_AIX
20582 && !restoring_GPRs_inline
20583 && info->first_fp_reg_save < 64
20585 emit_move_insn (cr_save_reg, mem);
20588 /* Set LR here to try to overlap restores below. */
20589 if (restore_lr && restoring_GPRs_inline)
20590 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
20591 gen_rtx_REG (Pmode, 0));
20593 /* Load exception handler data registers, if needed. */
20594 if (crtl->calls_eh_return)
20596 unsigned int i, regno;
20600 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20601 GEN_INT (sp_offset + 5 * reg_size));
20602 rtx mem = gen_frame_mem (reg_mode, addr);
20604 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
20611 regno = EH_RETURN_DATA_REGNO (i);
20612 if (regno == INVALID_REGNUM)
20615 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
20616 info->ehrd_offset + sp_offset
20617 + reg_size * (int) i);
20619 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
20623 /* Restore GPRs. This is done as a PARALLEL if we are using
20624 the load-multiple instructions. */
20626 && info->spe_64bit_regs_used
20627 && info->first_gp_reg_save != 32)
20629 /* Determine whether we can address all of the registers that need
20630 to be saved with an offset from frame_reg_rtx that fits in
20631 the small const field for SPE memory instructions. */
20632 int spe_regs_addressable
20633 = (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + sp_offset
20634 + reg_size * (32 - info->first_gp_reg_save - 1))
20635 && restoring_GPRs_inline);
20637 int ool_adjust = 0;
20639 if (spe_regs_addressable)
20640 spe_offset = info->spe_gp_save_offset + sp_offset;
20643 rtx old_frame_reg_rtx = frame_reg_rtx;
20644 /* Make r11 point to the start of the SPE save area. We worried about
20645 not clobbering it when we were saving registers in the prologue.
20646 There's no need to worry here because the static chain is passed
20647 anew to every function. */
20649 if (!restoring_GPRs_inline)
20650 ool_adjust = 8 * (info->first_gp_reg_save
20651 - (FIRST_SAVRES_REGISTER + 1));
20652 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20653 emit_insn (gen_addsi3 (frame_reg_rtx, old_frame_reg_rtx,
20654 GEN_INT (info->spe_gp_save_offset
20657 /* Keep the invariant that frame_reg_rtx + sp_offset points
20658 at the top of the stack frame. */
20659 sp_offset = -info->spe_gp_save_offset + ool_adjust;
20664 if (restoring_GPRs_inline)
20666 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20667 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
20669 rtx offset, addr, mem, reg;
20671 /* We're doing all this to ensure that the immediate offset
20672 fits into the immediate field of 'evldd'. */
20673 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
20675 offset = GEN_INT (spe_offset + reg_size * i);
20676 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, offset);
20677 mem = gen_rtx_MEM (V2SImode, addr);
20678 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
20680 emit_move_insn (reg, mem);
20684 rs6000_emit_savres_rtx (info, frame_reg_rtx,
20685 ool_adjust, reg_mode,
20686 /*savep=*/false, /*gpr=*/true,
20689 else if (!restoring_GPRs_inline)
20691 /* We are jumping to an out-of-line function. */
20692 bool can_use_exit = info->first_fp_reg_save == 64;
20694 /* Emit stack reset code if we need it. */
20697 rs6000_emit_stack_reset (info, sp_reg_rtx, frame_reg_rtx,
20698 sp_offset, can_use_exit);
20699 if (DEFAULT_ABI == ABI_DARWIN)
20700 /* we only need a copy, no fprs were saved. */
20701 emit_move_insn (gen_rtx_REG (Pmode, 11), frame_reg_rtx);
20703 if (info->cr_save_p)
20704 rs6000_restore_saved_cr (cr_save_reg, using_mtcr_multiple);
20708 rtx src_reg = gen_rtx_REG (Pmode, DEFAULT_ABI == ABI_AIX ? 12 : 11);
20710 emit_insn (gen_add3_insn (src_reg, frame_reg_rtx,
20711 GEN_INT (sp_offset - info->fp_size)));
20712 if (REGNO (frame_reg_rtx) == REGNO (src_reg))
20713 sp_offset = info->fp_size;
20716 rs6000_emit_savres_rtx (info, frame_reg_rtx,
20717 info->gp_save_offset, reg_mode,
20718 /*savep=*/false, /*gpr=*/true,
20719 /*lr=*/can_use_exit);
20721 else if (using_load_multiple)
20724 p = rtvec_alloc (32 - info->first_gp_reg_save);
20725 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20727 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20728 GEN_INT (info->gp_save_offset
20731 rtx mem = gen_frame_mem (reg_mode, addr);
20732 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
20734 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, reg, mem);
20736 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
20740 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20741 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
20743 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20744 GEN_INT (info->gp_save_offset
20747 rtx mem = gen_frame_mem (reg_mode, addr);
20748 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
20750 emit_move_insn (reg, mem);
20754 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
20756 /* If the frame pointer was used then we can't delay emitting
20757 a REG_CFA_DEF_CFA note. This must happen on the insn that
20758 restores the frame pointer, r31. We may have already emitted
20759 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
20760 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
20761 be harmless if emitted. */
20762 if (frame_pointer_needed)
20764 insn = get_last_insn ();
20765 add_reg_note (insn, REG_CFA_DEF_CFA,
20766 plus_constant (frame_reg_rtx, sp_offset));
20767 RTX_FRAME_RELATED_P (insn) = 1;
20770 /* Set up cfa_restores. We always need these when
20771 shrink-wrapping. If not shrink-wrapping then we only need
20772 the cfa_restore when the stack location is no longer valid.
20773 The cfa_restores must be emitted on or before the insn that
20774 invalidates the stack, and of course must not be emitted
20775 before the insn that actually does the restore. The latter
20776 is why the LR cfa_restore condition below is a little
20777 complicated. It's also why it is a bad idea to emit the
20778 cfa_restores as a group on the last instruction here that
20779 actually does a restore: That insn may be reordered with
20780 respect to others doing restores. */
20781 if (info->cr_save_p)
20782 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20783 gen_rtx_REG (SImode, CR2_REGNO),
20785 if (flag_shrink_wrap
20787 || (info->lr_save_p
20788 && !restoring_GPRs_inline
20789 && info->first_fp_reg_save == 64)))
20790 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20791 gen_rtx_REG (Pmode, LR_REGNO),
20794 for (i = info->first_gp_reg_save; i < 32; i++)
20795 if (!restoring_GPRs_inline
20796 || using_load_multiple
20797 || rs6000_reg_live_or_pic_offset_p (i))
20799 rtx reg = gen_rtx_REG (reg_mode, i);
20801 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20805 if (!restoring_GPRs_inline
20806 && info->first_fp_reg_save == 64)
20808 /* We are jumping to an out-of-line function. */
20810 emit_cfa_restores (cfa_restores);
20814 if (restore_lr && !restoring_GPRs_inline)
20816 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
20817 info->lr_save_offset + sp_offset);
20819 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
20820 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
20821 gen_rtx_REG (Pmode, 0));
20824 /* Restore fpr's if we need to do it without calling a function. */
20825 if (restoring_FPRs_inline)
20826 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
20827 if ((df_regs_ever_live_p (info->first_fp_reg_save + i)
20828 && !call_used_regs[info->first_fp_reg_save + i]))
20830 rtx addr, mem, reg;
20831 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20832 GEN_INT (info->fp_save_offset
20835 mem = gen_frame_mem (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
20836 ? DFmode : SFmode), addr);
20837 reg = gen_rtx_REG (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
20838 ? DFmode : SFmode),
20839 info->first_fp_reg_save + i);
20841 emit_move_insn (reg, mem);
20842 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
20843 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20846 /* If we saved cr, restore it here. Just those that were used. */
20847 if (info->cr_save_p)
20848 rs6000_restore_saved_cr (cr_save_reg, using_mtcr_multiple);
20850 /* If this is V.4, unwind the stack pointer after all of the loads
20852 insn = rs6000_emit_stack_reset (info, sp_reg_rtx, frame_reg_rtx,
20853 sp_offset, !restoring_FPRs_inline);
20858 REG_NOTES (insn) = cfa_restores;
20859 cfa_restores = NULL_RTX;
20861 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
20862 RTX_FRAME_RELATED_P (insn) = 1;
20865 if (crtl->calls_eh_return)
20867 rtx sa = EH_RETURN_STACKADJ_RTX;
20868 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
20874 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
20875 if (! restoring_FPRs_inline)
20877 p = rtvec_alloc (4 + 64 - info->first_fp_reg_save);
20878 RTVEC_ELT (p, 0) = ret_rtx;
20884 /* We can't hang the cfa_restores off a simple return,
20885 since the shrink-wrap code sometimes uses an existing
20886 return. This means there might be a path from
20887 pre-prologue code to this return, and dwarf2cfi code
20888 wants the eh_frame unwinder state to be the same on
20889 all paths to any point. So we need to emit the
20890 cfa_restores before the return. For -m64 we really
20891 don't need epilogue cfa_restores at all, except for
20892 this irritating dwarf2cfi with shrink-wrap
20893 requirement; The stack red-zone means eh_frame info
20894 from the prologue telling the unwinder to restore
20895 from the stack is perfectly good right to the end of
20897 emit_insn (gen_blockage ());
20898 emit_cfa_restores (cfa_restores);
20899 cfa_restores = NULL_RTX;
20901 p = rtvec_alloc (2);
20902 RTVEC_ELT (p, 0) = simple_return_rtx;
20905 RTVEC_ELT (p, 1) = ((restoring_FPRs_inline || !lr)
20906 ? gen_rtx_USE (VOIDmode,
20907 gen_rtx_REG (Pmode, LR_REGNO))
20908 : gen_rtx_CLOBBER (VOIDmode,
20909 gen_rtx_REG (Pmode, LR_REGNO)));
20911 /* If we have to restore more than two FP registers, branch to the
20912 restore function. It will return to our caller. */
20913 if (! restoring_FPRs_inline)
20918 if ((DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
20920 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20921 gen_rtx_REG (Pmode, LR_REGNO),
20924 sym = rs6000_savres_routine_sym (info,
20928 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym);
20929 RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode,
20930 gen_rtx_REG (Pmode,
20931 DEFAULT_ABI == ABI_AIX
20933 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
20935 rtx addr, mem, reg;
20937 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
20938 GEN_INT (info->fp_save_offset + 8 * i));
20939 mem = gen_frame_mem (DFmode, addr);
20940 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
20942 RTVEC_ELT (p, i + 4) = gen_rtx_SET (VOIDmode, reg, mem);
20943 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
20944 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
20949 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
20955 /* Ensure the cfa_restores are hung off an insn that won't
20956 be reordered above other restores. */
20957 emit_insn (gen_blockage ());
20959 emit_cfa_restores (cfa_restores);
20963 /* Write function epilogue. */
20966 rs6000_output_function_epilogue (FILE *file,
20967 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
20970 macho_branch_islands ();
20971 /* Mach-O doesn't support labels at the end of objects, so if
20972 it looks like we might want one, insert a NOP. */
20974 rtx insn = get_last_insn ();
20975 rtx deleted_debug_label = NULL_RTX;
20978 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
20980 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
20981 notes only, instead set their CODE_LABEL_NUMBER to -1,
20982 otherwise there would be code generation differences
20983 in between -g and -g0. */
20984 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
20985 deleted_debug_label = insn;
20986 insn = PREV_INSN (insn);
20991 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
20992 fputs ("\tnop\n", file);
20993 else if (deleted_debug_label)
20994 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
20995 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
20996 CODE_LABEL_NUMBER (insn) = -1;
21000 /* Output a traceback table here. See /usr/include/sys/debug.h for info
21003 We don't output a traceback table if -finhibit-size-directive was
21004 used. The documentation for -finhibit-size-directive reads
21005 ``don't output a @code{.size} assembler directive, or anything
21006 else that would cause trouble if the function is split in the
21007 middle, and the two halves are placed at locations far apart in
21008 memory.'' The traceback table has this property, since it
21009 includes the offset from the start of the function to the
21010 traceback table itself.
21012 System V.4 Powerpc's (and the embedded ABI derived from it) use a
21013 different traceback table. */
21014 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
21015 && rs6000_traceback != traceback_none && !cfun->is_thunk)
21017 const char *fname = NULL;
21018 const char *language_string = lang_hooks.name;
21019 int fixed_parms = 0, float_parms = 0, parm_info = 0;
21021 int optional_tbtab;
21022 rs6000_stack_t *info = rs6000_stack_info ();
21024 if (rs6000_traceback == traceback_full)
21025 optional_tbtab = 1;
21026 else if (rs6000_traceback == traceback_part)
21027 optional_tbtab = 0;
21029 optional_tbtab = !optimize_size && !TARGET_ELF;
21031 if (optional_tbtab)
21033 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
21034 while (*fname == '.') /* V.4 encodes . in the name */
21037 /* Need label immediately before tbtab, so we can compute
21038 its offset from the function start. */
21039 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
21040 ASM_OUTPUT_LABEL (file, fname);
21043 /* The .tbtab pseudo-op can only be used for the first eight
21044 expressions, since it can't handle the possibly variable
21045 length fields that follow. However, if you omit the optional
21046 fields, the assembler outputs zeros for all optional fields
21047 anyways, giving each variable length field is minimum length
21048 (as defined in sys/debug.h). Thus we can not use the .tbtab
21049 pseudo-op at all. */
21051 /* An all-zero word flags the start of the tbtab, for debuggers
21052 that have to find it by searching forward from the entry
21053 point or from the current pc. */
21054 fputs ("\t.long 0\n", file);
21056 /* Tbtab format type. Use format type 0. */
21057 fputs ("\t.byte 0,", file);
21059 /* Language type. Unfortunately, there does not seem to be any
21060 official way to discover the language being compiled, so we
21061 use language_string.
21062 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
21063 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
21064 a number, so for now use 9. LTO and Go aren't assigned numbers
21065 either, so for now use 0. */
21066 if (! strcmp (language_string, "GNU C")
21067 || ! strcmp (language_string, "GNU GIMPLE")
21068 || ! strcmp (language_string, "GNU Go"))
21070 else if (! strcmp (language_string, "GNU F77")
21071 || ! strcmp (language_string, "GNU Fortran"))
21073 else if (! strcmp (language_string, "GNU Pascal"))
21075 else if (! strcmp (language_string, "GNU Ada"))
21077 else if (! strcmp (language_string, "GNU C++")
21078 || ! strcmp (language_string, "GNU Objective-C++"))
21080 else if (! strcmp (language_string, "GNU Java"))
21082 else if (! strcmp (language_string, "GNU Objective-C"))
21085 gcc_unreachable ();
21086 fprintf (file, "%d,", i);
21088 /* 8 single bit fields: global linkage (not set for C extern linkage,
21089 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
21090 from start of procedure stored in tbtab, internal function, function
21091 has controlled storage, function has no toc, function uses fp,
21092 function logs/aborts fp operations. */
21093 /* Assume that fp operations are used if any fp reg must be saved. */
21094 fprintf (file, "%d,",
21095 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
21097 /* 6 bitfields: function is interrupt handler, name present in
21098 proc table, function calls alloca, on condition directives
21099 (controls stack walks, 3 bits), saves condition reg, saves
21101 /* The `function calls alloca' bit seems to be set whenever reg 31 is
21102 set up as a frame pointer, even when there is no alloca call. */
21103 fprintf (file, "%d,",
21104 ((optional_tbtab << 6)
21105 | ((optional_tbtab & frame_pointer_needed) << 5)
21106 | (info->cr_save_p << 1)
21107 | (info->lr_save_p)));
21109 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
21111 fprintf (file, "%d,",
21112 (info->push_p << 7) | (64 - info->first_fp_reg_save));
21114 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
21115 fprintf (file, "%d,", (32 - first_reg_to_save ()));
21117 if (optional_tbtab)
21119 /* Compute the parameter info from the function decl argument
21122 int next_parm_info_bit = 31;
21124 for (decl = DECL_ARGUMENTS (current_function_decl);
21125 decl; decl = DECL_CHAIN (decl))
21127 rtx parameter = DECL_INCOMING_RTL (decl);
21128 enum machine_mode mode = GET_MODE (parameter);
21130 if (GET_CODE (parameter) == REG)
21132 if (SCALAR_FLOAT_MODE_P (mode))
21153 gcc_unreachable ();
21156 /* If only one bit will fit, don't or in this entry. */
21157 if (next_parm_info_bit > 0)
21158 parm_info |= (bits << (next_parm_info_bit - 1));
21159 next_parm_info_bit -= 2;
21163 fixed_parms += ((GET_MODE_SIZE (mode)
21164 + (UNITS_PER_WORD - 1))
21166 next_parm_info_bit -= 1;
21172 /* Number of fixed point parameters. */
21173 /* This is actually the number of words of fixed point parameters; thus
21174 an 8 byte struct counts as 2; and thus the maximum value is 8. */
21175 fprintf (file, "%d,", fixed_parms);
21177 /* 2 bitfields: number of floating point parameters (7 bits), parameters
21179 /* This is actually the number of fp registers that hold parameters;
21180 and thus the maximum value is 13. */
21181 /* Set parameters on stack bit if parameters are not in their original
21182 registers, regardless of whether they are on the stack? Xlc
21183 seems to set the bit when not optimizing. */
21184 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
21186 if (! optional_tbtab)
21189 /* Optional fields follow. Some are variable length. */
21191 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
21192 11 double float. */
21193 /* There is an entry for each parameter in a register, in the order that
21194 they occur in the parameter list. Any intervening arguments on the
21195 stack are ignored. If the list overflows a long (max possible length
21196 34 bits) then completely leave off all elements that don't fit. */
21197 /* Only emit this long if there was at least one parameter. */
21198 if (fixed_parms || float_parms)
21199 fprintf (file, "\t.long %d\n", parm_info);
21201 /* Offset from start of code to tb table. */
21202 fputs ("\t.long ", file);
21203 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
21204 RS6000_OUTPUT_BASENAME (file, fname);
21206 rs6000_output_function_entry (file, fname);
21209 /* Interrupt handler mask. */
21210 /* Omit this long, since we never set the interrupt handler bit
21213 /* Number of CTL (controlled storage) anchors. */
21214 /* Omit this long, since the has_ctl bit is never set above. */
21216 /* Displacement into stack of each CTL anchor. */
21217 /* Omit this list of longs, because there are no CTL anchors. */
21219 /* Length of function name. */
21222 fprintf (file, "\t.short %d\n", (int) strlen (fname));
21224 /* Function name. */
21225 assemble_string (fname, strlen (fname));
21227 /* Register for alloca automatic storage; this is always reg 31.
21228 Only emit this if the alloca bit was set above. */
21229 if (frame_pointer_needed)
21230 fputs ("\t.byte 31\n", file);
21232 fputs ("\t.align 2\n", file);
21236 /* A C compound statement that outputs the assembler code for a thunk
21237 function, used to implement C++ virtual function calls with
21238 multiple inheritance. The thunk acts as a wrapper around a virtual
21239 function, adjusting the implicit object parameter before handing
21240 control off to the real function.
21242 First, emit code to add the integer DELTA to the location that
21243 contains the incoming first argument. Assume that this argument
21244 contains a pointer, and is the one used to pass the `this' pointer
21245 in C++. This is the incoming argument *before* the function
21246 prologue, e.g. `%o0' on a sparc. The addition must preserve the
21247 values of all other incoming arguments.
21249 After the addition, emit code to jump to FUNCTION, which is a
21250 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
21251 not touch the return address. Hence returning from FUNCTION will
21252 return to whoever called the current `thunk'.
21254 The effect must be as if FUNCTION had been called directly with the
21255 adjusted first argument. This macro is responsible for emitting
21256 all of the code for a thunk function; output_function_prologue()
21257 and output_function_epilogue() are not invoked.
21259 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
21260 been extracted from it.) It might possibly be useful on some
21261 targets, but probably not.
21263 If you do not define this macro, the target-independent code in the
21264 C++ frontend will generate a less efficient heavyweight thunk that
21265 calls FUNCTION instead of jumping to it. The generic approach does
21266 not support varargs. */
21269 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
21270 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
21273 rtx this_rtx, insn, funexp;
21275 reload_completed = 1;
21276 epilogue_completed = 1;
21278 /* Mark the end of the (empty) prologue. */
21279 emit_note (NOTE_INSN_PROLOGUE_END);
21281 /* Find the "this" pointer. If the function returns a structure,
21282 the structure return pointer is in r3. */
21283 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
21284 this_rtx = gen_rtx_REG (Pmode, 4);
21286 this_rtx = gen_rtx_REG (Pmode, 3);
21288 /* Apply the constant offset, if required. */
21290 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
21292 /* Apply the offset from the vtable, if required. */
21295 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
21296 rtx tmp = gen_rtx_REG (Pmode, 12);
21298 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
21299 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
21301 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
21302 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
21306 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
21308 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
21310 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
21313 /* Generate a tail call to the target function. */
21314 if (!TREE_USED (function))
21316 assemble_external (function);
21317 TREE_USED (function) = 1;
21319 funexp = XEXP (DECL_RTL (function), 0);
21320 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
21323 if (MACHOPIC_INDIRECT)
21324 funexp = machopic_indirect_call_target (funexp);
21327 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
21328 generate sibcall RTL explicitly. */
21329 insn = emit_call_insn (
21330 gen_rtx_PARALLEL (VOIDmode,
21332 gen_rtx_CALL (VOIDmode,
21333 funexp, const0_rtx),
21334 gen_rtx_USE (VOIDmode, const0_rtx),
21335 gen_rtx_USE (VOIDmode,
21336 gen_rtx_REG (SImode,
21338 simple_return_rtx)));
21339 SIBLING_CALL_P (insn) = 1;
21342 /* Run just enough of rest_of_compilation to get the insns emitted.
21343 There's not really enough bulk here to make other passes such as
21344 instruction scheduling worth while. Note that use_thunk calls
21345 assemble_start_function and assemble_end_function. */
21346 insn = get_insns ();
21347 insn_locators_alloc ();
21348 shorten_branches (insn);
21349 final_start_function (insn, file, 1);
21350 final (insn, file, 1);
21351 final_end_function ();
21353 reload_completed = 0;
21354 epilogue_completed = 0;
21357 /* A quick summary of the various types of 'constant-pool tables'
21360 Target Flags Name One table per
21361 AIX (none) AIX TOC object file
21362 AIX -mfull-toc AIX TOC object file
21363 AIX -mminimal-toc AIX minimal TOC translation unit
21364 SVR4/EABI (none) SVR4 SDATA object file
21365 SVR4/EABI -fpic SVR4 pic object file
21366 SVR4/EABI -fPIC SVR4 PIC translation unit
21367 SVR4/EABI -mrelocatable EABI TOC function
21368 SVR4/EABI -maix AIX TOC object file
21369 SVR4/EABI -maix -mminimal-toc
21370 AIX minimal TOC translation unit
21372 Name Reg. Set by entries contains:
21373 made by addrs? fp? sum?
21375 AIX TOC 2 crt0 as Y option option
21376 AIX minimal TOC 30 prolog gcc Y Y option
21377 SVR4 SDATA 13 crt0 gcc N Y N
21378 SVR4 pic 30 prolog ld Y not yet N
21379 SVR4 PIC 30 prolog gcc Y option option
21380 EABI TOC 30 prolog gcc Y option option
21384 /* Hash functions for the hash table. */
21387 rs6000_hash_constant (rtx k)
21389 enum rtx_code code = GET_CODE (k);
21390 enum machine_mode mode = GET_MODE (k);
21391 unsigned result = (code << 3) ^ mode;
21392 const char *format;
21395 format = GET_RTX_FORMAT (code);
21396 flen = strlen (format);
21402 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
21405 if (mode != VOIDmode)
21406 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
21418 for (; fidx < flen; fidx++)
21419 switch (format[fidx])
21424 const char *str = XSTR (k, fidx);
21425 len = strlen (str);
21426 result = result * 613 + len;
21427 for (i = 0; i < len; i++)
21428 result = result * 613 + (unsigned) str[i];
21433 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
21437 result = result * 613 + (unsigned) XINT (k, fidx);
21440 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
21441 result = result * 613 + (unsigned) XWINT (k, fidx);
21445 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
21446 result = result * 613 + (unsigned) (XWINT (k, fidx)
21453 gcc_unreachable ();
21460 toc_hash_function (const void *hash_entry)
21462 const struct toc_hash_struct *thc =
21463 (const struct toc_hash_struct *) hash_entry;
21464 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
21467 /* Compare H1 and H2 for equivalence. */
21470 toc_hash_eq (const void *h1, const void *h2)
21472 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
21473 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
21475 if (((const struct toc_hash_struct *) h1)->key_mode
21476 != ((const struct toc_hash_struct *) h2)->key_mode)
21479 return rtx_equal_p (r1, r2);
21482 /* These are the names given by the C++ front-end to vtables, and
21483 vtable-like objects. Ideally, this logic should not be here;
21484 instead, there should be some programmatic way of inquiring as
21485 to whether or not an object is a vtable. */
21487 #define VTABLE_NAME_P(NAME) \
21488 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
21489 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
21490 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
21491 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
21492 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
21494 #ifdef NO_DOLLAR_IN_LABEL
21495 /* Return a GGC-allocated character string translating dollar signs in
21496 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
21499 rs6000_xcoff_strip_dollar (const char *name)
21505 q = (const char *) strchr (name, '$');
21507 if (q == 0 || q == name)
21510 len = strlen (name);
21511 strip = XALLOCAVEC (char, len + 1);
21512 strcpy (strip, name);
21513 p = strip + (q - name);
21517 p = strchr (p + 1, '$');
21520 return ggc_alloc_string (strip, len);
21525 rs6000_output_symbol_ref (FILE *file, rtx x)
21527 /* Currently C++ toc references to vtables can be emitted before it
21528 is decided whether the vtable is public or private. If this is
21529 the case, then the linker will eventually complain that there is
21530 a reference to an unknown section. Thus, for vtables only,
21531 we emit the TOC reference to reference the symbol and not the
21533 const char *name = XSTR (x, 0);
21535 if (VTABLE_NAME_P (name))
21537 RS6000_OUTPUT_BASENAME (file, name);
21540 assemble_name (file, name);
21543 /* Output a TOC entry. We derive the entry name from what is being
21547 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
21550 const char *name = buf;
21552 HOST_WIDE_INT offset = 0;
21554 gcc_assert (!TARGET_NO_TOC);
21556 /* When the linker won't eliminate them, don't output duplicate
21557 TOC entries (this happens on AIX if there is any kind of TOC,
21558 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
21560 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
21562 struct toc_hash_struct *h;
21565 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
21566 time because GGC is not initialized at that point. */
21567 if (toc_hash_table == NULL)
21568 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
21569 toc_hash_eq, NULL);
21571 h = ggc_alloc_toc_hash_struct ();
21573 h->key_mode = mode;
21574 h->labelno = labelno;
21576 found = htab_find_slot (toc_hash_table, h, INSERT);
21577 if (*found == NULL)
21579 else /* This is indeed a duplicate.
21580 Set this label equal to that label. */
21582 fputs ("\t.set ", file);
21583 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
21584 fprintf (file, "%d,", labelno);
21585 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
21586 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
21592 /* If we're going to put a double constant in the TOC, make sure it's
21593 aligned properly when strict alignment is on. */
21594 if (GET_CODE (x) == CONST_DOUBLE
21595 && STRICT_ALIGNMENT
21596 && GET_MODE_BITSIZE (mode) >= 64
21597 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
21598 ASM_OUTPUT_ALIGN (file, 3);
21601 (*targetm.asm_out.internal_label) (file, "LC", labelno);
21603 /* Handle FP constants specially. Note that if we have a minimal
21604 TOC, things we put here aren't actually in the TOC, so we can allow
21606 if (GET_CODE (x) == CONST_DOUBLE &&
21607 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
21609 REAL_VALUE_TYPE rv;
21612 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
21613 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
21614 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
21616 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
21620 if (TARGET_MINIMAL_TOC)
21621 fputs (DOUBLE_INT_ASM_OP, file);
21623 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
21624 k[0] & 0xffffffff, k[1] & 0xffffffff,
21625 k[2] & 0xffffffff, k[3] & 0xffffffff);
21626 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
21627 k[0] & 0xffffffff, k[1] & 0xffffffff,
21628 k[2] & 0xffffffff, k[3] & 0xffffffff);
21633 if (TARGET_MINIMAL_TOC)
21634 fputs ("\t.long ", file);
21636 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
21637 k[0] & 0xffffffff, k[1] & 0xffffffff,
21638 k[2] & 0xffffffff, k[3] & 0xffffffff);
21639 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
21640 k[0] & 0xffffffff, k[1] & 0xffffffff,
21641 k[2] & 0xffffffff, k[3] & 0xffffffff);
21645 else if (GET_CODE (x) == CONST_DOUBLE &&
21646 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
21648 REAL_VALUE_TYPE rv;
21651 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
21653 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
21654 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
21656 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
21660 if (TARGET_MINIMAL_TOC)
21661 fputs (DOUBLE_INT_ASM_OP, file);
21663 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
21664 k[0] & 0xffffffff, k[1] & 0xffffffff);
21665 fprintf (file, "0x%lx%08lx\n",
21666 k[0] & 0xffffffff, k[1] & 0xffffffff);
21671 if (TARGET_MINIMAL_TOC)
21672 fputs ("\t.long ", file);
21674 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
21675 k[0] & 0xffffffff, k[1] & 0xffffffff);
21676 fprintf (file, "0x%lx,0x%lx\n",
21677 k[0] & 0xffffffff, k[1] & 0xffffffff);
21681 else if (GET_CODE (x) == CONST_DOUBLE &&
21682 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
21684 REAL_VALUE_TYPE rv;
21687 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
21688 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
21689 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
21691 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
21695 if (TARGET_MINIMAL_TOC)
21696 fputs (DOUBLE_INT_ASM_OP, file);
21698 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
21699 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
21704 if (TARGET_MINIMAL_TOC)
21705 fputs ("\t.long ", file);
21707 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
21708 fprintf (file, "0x%lx\n", l & 0xffffffff);
21712 else if (GET_MODE (x) == VOIDmode
21713 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
21715 unsigned HOST_WIDE_INT low;
21716 HOST_WIDE_INT high;
21718 if (GET_CODE (x) == CONST_DOUBLE)
21720 low = CONST_DOUBLE_LOW (x);
21721 high = CONST_DOUBLE_HIGH (x);
21724 #if HOST_BITS_PER_WIDE_INT == 32
21727 high = (low & 0x80000000) ? ~0 : 0;
21731 low = INTVAL (x) & 0xffffffff;
21732 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
21736 /* TOC entries are always Pmode-sized, but since this
21737 is a bigendian machine then if we're putting smaller
21738 integer constants in the TOC we have to pad them.
21739 (This is still a win over putting the constants in
21740 a separate constant pool, because then we'd have
21741 to have both a TOC entry _and_ the actual constant.)
21743 For a 32-bit target, CONST_INT values are loaded and shifted
21744 entirely within `low' and can be stored in one TOC entry. */
21746 /* It would be easy to make this work, but it doesn't now. */
21747 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
21749 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
21751 #if HOST_BITS_PER_WIDE_INT == 32
21752 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
21753 POINTER_SIZE, &low, &high, 0);
21756 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
21757 high = (HOST_WIDE_INT) low >> 32;
21764 if (TARGET_MINIMAL_TOC)
21765 fputs (DOUBLE_INT_ASM_OP, file);
21767 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
21768 (long) high & 0xffffffff, (long) low & 0xffffffff);
21769 fprintf (file, "0x%lx%08lx\n",
21770 (long) high & 0xffffffff, (long) low & 0xffffffff);
21775 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
21777 if (TARGET_MINIMAL_TOC)
21778 fputs ("\t.long ", file);
21780 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
21781 (long) high & 0xffffffff, (long) low & 0xffffffff);
21782 fprintf (file, "0x%lx,0x%lx\n",
21783 (long) high & 0xffffffff, (long) low & 0xffffffff);
21787 if (TARGET_MINIMAL_TOC)
21788 fputs ("\t.long ", file);
21790 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
21791 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
21797 if (GET_CODE (x) == CONST)
21799 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
21800 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
21802 base = XEXP (XEXP (x, 0), 0);
21803 offset = INTVAL (XEXP (XEXP (x, 0), 1));
21806 switch (GET_CODE (base))
21809 name = XSTR (base, 0);
21813 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
21814 CODE_LABEL_NUMBER (XEXP (base, 0)));
21818 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
21822 gcc_unreachable ();
21825 if (TARGET_MINIMAL_TOC)
21826 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
21829 fputs ("\t.tc ", file);
21830 RS6000_OUTPUT_BASENAME (file, name);
21833 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
21835 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
21837 fputs ("[TC],", file);
21840 /* Currently C++ toc references to vtables can be emitted before it
21841 is decided whether the vtable is public or private. If this is
21842 the case, then the linker will eventually complain that there is
21843 a TOC reference to an unknown section. Thus, for vtables only,
21844 we emit the TOC reference to reference the symbol and not the
21846 if (VTABLE_NAME_P (name))
21848 RS6000_OUTPUT_BASENAME (file, name);
21850 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
21851 else if (offset > 0)
21852 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
21855 output_addr_const (file, x);
21859 /* Output an assembler pseudo-op to write an ASCII string of N characters
21860 starting at P to FILE.
21862 On the RS/6000, we have to do this using the .byte operation and
21863 write out special characters outside the quoted string.
21864 Also, the assembler is broken; very long strings are truncated,
21865 so we must artificially break them up early. */
21868 output_ascii (FILE *file, const char *p, int n)
21871 int i, count_string;
21872 const char *for_string = "\t.byte \"";
21873 const char *for_decimal = "\t.byte ";
21874 const char *to_close = NULL;
21877 for (i = 0; i < n; i++)
21880 if (c >= ' ' && c < 0177)
21883 fputs (for_string, file);
21886 /* Write two quotes to get one. */
21894 for_decimal = "\"\n\t.byte ";
21898 if (count_string >= 512)
21900 fputs (to_close, file);
21902 for_string = "\t.byte \"";
21903 for_decimal = "\t.byte ";
21911 fputs (for_decimal, file);
21912 fprintf (file, "%d", c);
21914 for_string = "\n\t.byte \"";
21915 for_decimal = ", ";
21921 /* Now close the string if we have written one. Then end the line. */
21923 fputs (to_close, file);
21926 /* Generate a unique section name for FILENAME for a section type
21927 represented by SECTION_DESC. Output goes into BUF.
21929 SECTION_DESC can be any string, as long as it is different for each
21930 possible section type.
21932 We name the section in the same manner as xlc. The name begins with an
21933 underscore followed by the filename (after stripping any leading directory
21934 names) with the last period replaced by the string SECTION_DESC. If
21935 FILENAME does not contain a period, SECTION_DESC is appended to the end of
21939 rs6000_gen_section_name (char **buf, const char *filename,
21940 const char *section_desc)
21942 const char *q, *after_last_slash, *last_period = 0;
21946 after_last_slash = filename;
21947 for (q = filename; *q; q++)
21950 after_last_slash = q + 1;
21951 else if (*q == '.')
21955 len = strlen (after_last_slash) + strlen (section_desc) + 2;
21956 *buf = (char *) xmalloc (len);
21961 for (q = after_last_slash; *q; q++)
21963 if (q == last_period)
21965 strcpy (p, section_desc);
21966 p += strlen (section_desc);
21970 else if (ISALNUM (*q))
21974 if (last_period == 0)
21975 strcpy (p, section_desc);
21980 /* Emit profile function. */
21983 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
21985 /* Non-standard profiling for kernels, which just saves LR then calls
21986 _mcount without worrying about arg saves. The idea is to change
21987 the function prologue as little as possible as it isn't easy to
21988 account for arg save/restore code added just for _mcount. */
21989 if (TARGET_PROFILE_KERNEL)
21992 if (DEFAULT_ABI == ABI_AIX)
21994 #ifndef NO_PROFILE_COUNTERS
21995 # define NO_PROFILE_COUNTERS 0
21997 if (NO_PROFILE_COUNTERS)
21998 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
21999 LCT_NORMAL, VOIDmode, 0);
22003 const char *label_name;
22006 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
22007 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
22008 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
22010 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
22011 LCT_NORMAL, VOIDmode, 1, fun, Pmode);
22014 else if (DEFAULT_ABI == ABI_DARWIN)
22016 const char *mcount_name = RS6000_MCOUNT;
22017 int caller_addr_regno = LR_REGNO;
22019 /* Be conservative and always set this, at least for now. */
22020 crtl->uses_pic_offset_table = 1;
22023 /* For PIC code, set up a stub and collect the caller's address
22024 from r0, which is where the prologue puts it. */
22025 if (MACHOPIC_INDIRECT
22026 && crtl->uses_pic_offset_table)
22027 caller_addr_regno = 0;
22029 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
22030 LCT_NORMAL, VOIDmode, 1,
22031 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
22035 /* Write function profiler code. */
22038 output_function_profiler (FILE *file, int labelno)
22042 switch (DEFAULT_ABI)
22045 gcc_unreachable ();
22050 warning (0, "no profiling of 64-bit code for this ABI");
22053 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
22054 fprintf (file, "\tmflr %s\n", reg_names[0]);
22055 if (NO_PROFILE_COUNTERS)
22057 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22058 reg_names[0], reg_names[1]);
22060 else if (TARGET_SECURE_PLT && flag_pic)
22062 if (TARGET_LINK_STACK)
22065 get_ppc476_thunk_name (name);
22066 asm_fprintf (file, "\tbl %s\n", name);
22069 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
22070 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22071 reg_names[0], reg_names[1]);
22072 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
22073 asm_fprintf (file, "\t{cau|addis} %s,%s,",
22074 reg_names[12], reg_names[12]);
22075 assemble_name (file, buf);
22076 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
22077 assemble_name (file, buf);
22078 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
22080 else if (flag_pic == 1)
22082 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
22083 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22084 reg_names[0], reg_names[1]);
22085 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
22086 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
22087 assemble_name (file, buf);
22088 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
22090 else if (flag_pic > 1)
22092 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22093 reg_names[0], reg_names[1]);
22094 /* Now, we need to get the address of the label. */
22095 if (TARGET_LINK_STACK)
22098 get_ppc476_thunk_name (name);
22099 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
22100 assemble_name (file, buf);
22101 fputs ("-.\n1:", file);
22102 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
22103 asm_fprintf (file, "\taddi %s,%s,4\n",
22104 reg_names[11], reg_names[11]);
22108 fputs ("\tbcl 20,31,1f\n\t.long ", file);
22109 assemble_name (file, buf);
22110 fputs ("-.\n1:", file);
22111 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
22113 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
22114 reg_names[0], reg_names[11]);
22115 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
22116 reg_names[0], reg_names[0], reg_names[11]);
22120 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
22121 assemble_name (file, buf);
22122 fputs ("@ha\n", file);
22123 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22124 reg_names[0], reg_names[1]);
22125 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
22126 assemble_name (file, buf);
22127 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
22130 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
22131 fprintf (file, "\tbl %s%s\n",
22132 RS6000_MCOUNT, flag_pic ? "@plt" : "");
22137 if (!TARGET_PROFILE_KERNEL)
22139 /* Don't do anything, done in output_profile_hook (). */
22143 gcc_assert (!TARGET_32BIT);
22145 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
22146 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
22148 if (cfun->static_chain_decl != NULL)
22150 asm_fprintf (file, "\tstd %s,24(%s)\n",
22151 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
22152 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
22153 asm_fprintf (file, "\tld %s,24(%s)\n",
22154 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
22157 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
22165 /* The following variable value is the last issued insn. */
22167 static rtx last_scheduled_insn;
22169 /* The following variable helps to balance issuing of load and
22170 store instructions */
22172 static int load_store_pendulum;
22174 /* Power4 load update and store update instructions are cracked into a
22175 load or store and an integer insn which are executed in the same cycle.
22176 Branches have their own dispatch slot which does not count against the
22177 GCC issue rate, but it changes the program flow so there are no other
22178 instructions to issue in this cycle. */
22181 rs6000_variable_issue_1 (rtx insn, int more)
22183 last_scheduled_insn = insn;
22184 if (GET_CODE (PATTERN (insn)) == USE
22185 || GET_CODE (PATTERN (insn)) == CLOBBER)
22187 cached_can_issue_more = more;
22188 return cached_can_issue_more;
22191 if (insn_terminates_group_p (insn, current_group))
22193 cached_can_issue_more = 0;
22194 return cached_can_issue_more;
22197 /* If no reservation, but reach here */
22198 if (recog_memoized (insn) < 0)
22201 if (rs6000_sched_groups)
22203 if (is_microcoded_insn (insn))
22204 cached_can_issue_more = 0;
22205 else if (is_cracked_insn (insn))
22206 cached_can_issue_more = more > 2 ? more - 2 : 0;
22208 cached_can_issue_more = more - 1;
22210 return cached_can_issue_more;
22213 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
22216 cached_can_issue_more = more - 1;
22217 return cached_can_issue_more;
22221 rs6000_variable_issue (FILE *stream, int verbose, rtx insn, int more)
22223 int r = rs6000_variable_issue_1 (insn, more);
22225 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
22229 /* Adjust the cost of a scheduling dependency. Return the new cost of
22230 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
22233 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
22235 enum attr_type attr_type;
22237 if (! recog_memoized (insn))
22240 switch (REG_NOTE_KIND (link))
22244 /* Data dependency; DEP_INSN writes a register that INSN reads
22245 some cycles later. */
22247 /* Separate a load from a narrower, dependent store. */
22248 if (rs6000_sched_groups
22249 && GET_CODE (PATTERN (insn)) == SET
22250 && GET_CODE (PATTERN (dep_insn)) == SET
22251 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
22252 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
22253 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
22254 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
22257 attr_type = get_attr_type (insn);
22262 /* Tell the first scheduling pass about the latency between
22263 a mtctr and bctr (and mtlr and br/blr). The first
22264 scheduling pass will not know about this latency since
22265 the mtctr instruction, which has the latency associated
22266 to it, will be generated by reload. */
22267 return TARGET_POWER ? 5 : 4;
22269 /* Leave some extra cycles between a compare and its
22270 dependent branch, to inhibit expensive mispredicts. */
22271 if ((rs6000_cpu_attr == CPU_PPC603
22272 || rs6000_cpu_attr == CPU_PPC604
22273 || rs6000_cpu_attr == CPU_PPC604E
22274 || rs6000_cpu_attr == CPU_PPC620
22275 || rs6000_cpu_attr == CPU_PPC630
22276 || rs6000_cpu_attr == CPU_PPC750
22277 || rs6000_cpu_attr == CPU_PPC7400
22278 || rs6000_cpu_attr == CPU_PPC7450
22279 || rs6000_cpu_attr == CPU_POWER4
22280 || rs6000_cpu_attr == CPU_POWER5
22281 || rs6000_cpu_attr == CPU_POWER7
22282 || rs6000_cpu_attr == CPU_CELL)
22283 && recog_memoized (dep_insn)
22284 && (INSN_CODE (dep_insn) >= 0))
22286 switch (get_attr_type (dep_insn))
22290 case TYPE_DELAYED_COMPARE:
22291 case TYPE_IMUL_COMPARE:
22292 case TYPE_LMUL_COMPARE:
22293 case TYPE_FPCOMPARE:
22294 case TYPE_CR_LOGICAL:
22295 case TYPE_DELAYED_CR:
22304 case TYPE_STORE_UX:
22306 case TYPE_FPSTORE_U:
22307 case TYPE_FPSTORE_UX:
22308 if ((rs6000_cpu == PROCESSOR_POWER6)
22309 && recog_memoized (dep_insn)
22310 && (INSN_CODE (dep_insn) >= 0))
22313 if (GET_CODE (PATTERN (insn)) != SET)
22314 /* If this happens, we have to extend this to schedule
22315 optimally. Return default for now. */
22318 /* Adjust the cost for the case where the value written
22319 by a fixed point operation is used as the address
22320 gen value on a store. */
22321 switch (get_attr_type (dep_insn))
22328 if (! store_data_bypass_p (dep_insn, insn))
22332 case TYPE_LOAD_EXT:
22333 case TYPE_LOAD_EXT_U:
22334 case TYPE_LOAD_EXT_UX:
22335 case TYPE_VAR_SHIFT_ROTATE:
22336 case TYPE_VAR_DELAYED_COMPARE:
22338 if (! store_data_bypass_p (dep_insn, insn))
22344 case TYPE_FAST_COMPARE:
22347 case TYPE_INSERT_WORD:
22348 case TYPE_INSERT_DWORD:
22349 case TYPE_FPLOAD_U:
22350 case TYPE_FPLOAD_UX:
22352 case TYPE_STORE_UX:
22353 case TYPE_FPSTORE_U:
22354 case TYPE_FPSTORE_UX:
22356 if (! store_data_bypass_p (dep_insn, insn))
22364 case TYPE_IMUL_COMPARE:
22365 case TYPE_LMUL_COMPARE:
22367 if (! store_data_bypass_p (dep_insn, insn))
22373 if (! store_data_bypass_p (dep_insn, insn))
22379 if (! store_data_bypass_p (dep_insn, insn))
22392 case TYPE_LOAD_EXT:
22393 case TYPE_LOAD_EXT_U:
22394 case TYPE_LOAD_EXT_UX:
22395 if ((rs6000_cpu == PROCESSOR_POWER6)
22396 && recog_memoized (dep_insn)
22397 && (INSN_CODE (dep_insn) >= 0))
22400 /* Adjust the cost for the case where the value written
22401 by a fixed point instruction is used within the address
22402 gen portion of a subsequent load(u)(x) */
22403 switch (get_attr_type (dep_insn))
22410 if (set_to_load_agen (dep_insn, insn))
22414 case TYPE_LOAD_EXT:
22415 case TYPE_LOAD_EXT_U:
22416 case TYPE_LOAD_EXT_UX:
22417 case TYPE_VAR_SHIFT_ROTATE:
22418 case TYPE_VAR_DELAYED_COMPARE:
22420 if (set_to_load_agen (dep_insn, insn))
22426 case TYPE_FAST_COMPARE:
22429 case TYPE_INSERT_WORD:
22430 case TYPE_INSERT_DWORD:
22431 case TYPE_FPLOAD_U:
22432 case TYPE_FPLOAD_UX:
22434 case TYPE_STORE_UX:
22435 case TYPE_FPSTORE_U:
22436 case TYPE_FPSTORE_UX:
22438 if (set_to_load_agen (dep_insn, insn))
22446 case TYPE_IMUL_COMPARE:
22447 case TYPE_LMUL_COMPARE:
22449 if (set_to_load_agen (dep_insn, insn))
22455 if (set_to_load_agen (dep_insn, insn))
22461 if (set_to_load_agen (dep_insn, insn))
22472 if ((rs6000_cpu == PROCESSOR_POWER6)
22473 && recog_memoized (dep_insn)
22474 && (INSN_CODE (dep_insn) >= 0)
22475 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
22482 /* Fall out to return default cost. */
22486 case REG_DEP_OUTPUT:
22487 /* Output dependency; DEP_INSN writes a register that INSN writes some
22489 if ((rs6000_cpu == PROCESSOR_POWER6)
22490 && recog_memoized (dep_insn)
22491 && (INSN_CODE (dep_insn) >= 0))
22493 attr_type = get_attr_type (insn);
22498 if (get_attr_type (dep_insn) == TYPE_FP)
22502 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
22510 /* Anti dependency; DEP_INSN reads a register that INSN writes some
22515 gcc_unreachable ();
22521 /* Debug version of rs6000_adjust_cost. */
22524 rs6000_debug_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
22526 int ret = rs6000_adjust_cost (insn, link, dep_insn, cost);
22532 switch (REG_NOTE_KIND (link))
22534 default: dep = "unknown depencency"; break;
22535 case REG_DEP_TRUE: dep = "data dependency"; break;
22536 case REG_DEP_OUTPUT: dep = "output dependency"; break;
22537 case REG_DEP_ANTI: dep = "anti depencency"; break;
22541 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
22542 "%s, insn:\n", ret, cost, dep);
22550 /* The function returns a true if INSN is microcoded.
22551 Return false otherwise. */
22554 is_microcoded_insn (rtx insn)
22556 if (!insn || !NONDEBUG_INSN_P (insn)
22557 || GET_CODE (PATTERN (insn)) == USE
22558 || GET_CODE (PATTERN (insn)) == CLOBBER)
22561 if (rs6000_cpu_attr == CPU_CELL)
22562 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
22564 if (rs6000_sched_groups)
22566 enum attr_type type = get_attr_type (insn);
22567 if (type == TYPE_LOAD_EXT_U
22568 || type == TYPE_LOAD_EXT_UX
22569 || type == TYPE_LOAD_UX
22570 || type == TYPE_STORE_UX
22571 || type == TYPE_MFCR)
22578 /* The function returns true if INSN is cracked into 2 instructions
22579 by the processor (and therefore occupies 2 issue slots). */
22582 is_cracked_insn (rtx insn)
22584 if (!insn || !NONDEBUG_INSN_P (insn)
22585 || GET_CODE (PATTERN (insn)) == USE
22586 || GET_CODE (PATTERN (insn)) == CLOBBER)
22589 if (rs6000_sched_groups)
22591 enum attr_type type = get_attr_type (insn);
22592 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
22593 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
22594 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
22595 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
22596 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
22597 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
22598 || type == TYPE_IDIV || type == TYPE_LDIV
22599 || type == TYPE_INSERT_WORD)
22606 /* The function returns true if INSN can be issued only from
22607 the branch slot. */
22610 is_branch_slot_insn (rtx insn)
22612 if (!insn || !NONDEBUG_INSN_P (insn)
22613 || GET_CODE (PATTERN (insn)) == USE
22614 || GET_CODE (PATTERN (insn)) == CLOBBER)
22617 if (rs6000_sched_groups)
22619 enum attr_type type = get_attr_type (insn);
22620 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
22628 /* The function returns true if out_inst sets a value that is
22629 used in the address generation computation of in_insn */
22631 set_to_load_agen (rtx out_insn, rtx in_insn)
22633 rtx out_set, in_set;
22635 /* For performance reasons, only handle the simple case where
22636 both loads are a single_set. */
22637 out_set = single_set (out_insn);
22640 in_set = single_set (in_insn);
22642 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
22648 /* The function returns true if the target storage location of
22649 out_insn is adjacent to the target storage location of in_insn */
22650 /* Return 1 if memory locations are adjacent. */
22653 adjacent_mem_locations (rtx insn1, rtx insn2)
22656 rtx a = get_store_dest (PATTERN (insn1));
22657 rtx b = get_store_dest (PATTERN (insn2));
22659 if ((GET_CODE (XEXP (a, 0)) == REG
22660 || (GET_CODE (XEXP (a, 0)) == PLUS
22661 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
22662 && (GET_CODE (XEXP (b, 0)) == REG
22663 || (GET_CODE (XEXP (b, 0)) == PLUS
22664 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
22666 HOST_WIDE_INT val0 = 0, val1 = 0, val_diff;
22669 if (GET_CODE (XEXP (a, 0)) == PLUS)
22671 reg0 = XEXP (XEXP (a, 0), 0);
22672 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
22675 reg0 = XEXP (a, 0);
22677 if (GET_CODE (XEXP (b, 0)) == PLUS)
22679 reg1 = XEXP (XEXP (b, 0), 0);
22680 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
22683 reg1 = XEXP (b, 0);
22685 val_diff = val1 - val0;
22687 return ((REGNO (reg0) == REGNO (reg1))
22688 && ((MEM_SIZE_KNOWN_P (a) && val_diff == MEM_SIZE (a))
22689 || (MEM_SIZE_KNOWN_P (b) && val_diff == -MEM_SIZE (b))));
22695 /* A C statement (sans semicolon) to update the integer scheduling
22696 priority INSN_PRIORITY (INSN). Increase the priority to execute the
22697 INSN earlier, reduce the priority to execute INSN later. Do not
22698 define this macro if you do not need to adjust the scheduling
22699 priorities of insns. */
22702 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
22704 /* On machines (like the 750) which have asymmetric integer units,
22705 where one integer unit can do multiply and divides and the other
22706 can't, reduce the priority of multiply/divide so it is scheduled
22707 before other integer operations. */
22710 if (! INSN_P (insn))
22713 if (GET_CODE (PATTERN (insn)) == USE)
22716 switch (rs6000_cpu_attr) {
22718 switch (get_attr_type (insn))
22725 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
22726 priority, priority);
22727 if (priority >= 0 && priority < 0x01000000)
22734 if (insn_must_be_first_in_group (insn)
22735 && reload_completed
22736 && current_sched_info->sched_max_insns_priority
22737 && rs6000_sched_restricted_insns_priority)
22740 /* Prioritize insns that can be dispatched only in the first
22742 if (rs6000_sched_restricted_insns_priority == 1)
22743 /* Attach highest priority to insn. This means that in
22744 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
22745 precede 'priority' (critical path) considerations. */
22746 return current_sched_info->sched_max_insns_priority;
22747 else if (rs6000_sched_restricted_insns_priority == 2)
22748 /* Increase priority of insn by a minimal amount. This means that in
22749 haifa-sched.c:ready_sort(), only 'priority' (critical path)
22750 considerations precede dispatch-slot restriction considerations. */
22751 return (priority + 1);
22754 if (rs6000_cpu == PROCESSOR_POWER6
22755 && ((load_store_pendulum == -2 && is_load_insn (insn))
22756 || (load_store_pendulum == 2 && is_store_insn (insn))))
22757 /* Attach highest priority to insn if the scheduler has just issued two
22758 stores and this instruction is a load, or two loads and this instruction
22759 is a store. Power6 wants loads and stores scheduled alternately
22761 return current_sched_info->sched_max_insns_priority;
22766 /* Return true if the instruction is nonpipelined on the Cell. */
22768 is_nonpipeline_insn (rtx insn)
22770 enum attr_type type;
22771 if (!insn || !NONDEBUG_INSN_P (insn)
22772 || GET_CODE (PATTERN (insn)) == USE
22773 || GET_CODE (PATTERN (insn)) == CLOBBER)
22776 type = get_attr_type (insn);
22777 if (type == TYPE_IMUL
22778 || type == TYPE_IMUL2
22779 || type == TYPE_IMUL3
22780 || type == TYPE_LMUL
22781 || type == TYPE_IDIV
22782 || type == TYPE_LDIV
22783 || type == TYPE_SDIV
22784 || type == TYPE_DDIV
22785 || type == TYPE_SSQRT
22786 || type == TYPE_DSQRT
22787 || type == TYPE_MFCR
22788 || type == TYPE_MFCRF
22789 || type == TYPE_MFJMPR)
22797 /* Return how many instructions the machine can issue per cycle. */
22800 rs6000_issue_rate (void)
22802 /* Unless scheduling for register pressure, use issue rate of 1 for
22803 first scheduling pass to decrease degradation. */
22804 if (!reload_completed && !flag_sched_pressure)
22807 switch (rs6000_cpu_attr) {
22808 case CPU_RIOS1: /* ? */
22810 case CPU_PPC601: /* ? */
22819 case CPU_PPCE300C2:
22820 case CPU_PPCE300C3:
22821 case CPU_PPCE500MC:
22822 case CPU_PPCE500MC64:
22842 /* Return how many instructions to look ahead for better insn
22846 rs6000_use_sched_lookahead (void)
22848 if (rs6000_cpu_attr == CPU_PPC8540)
22850 if (rs6000_cpu_attr == CPU_CELL)
22851 return (reload_completed ? 8 : 0);
22855 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
22857 rs6000_use_sched_lookahead_guard (rtx insn)
22859 if (rs6000_cpu_attr != CPU_CELL)
22862 if (insn == NULL_RTX || !INSN_P (insn))
22865 if (!reload_completed
22866 || is_nonpipeline_insn (insn)
22867 || is_microcoded_insn (insn))
22873 /* Determine is PAT refers to memory. */
22876 is_mem_ref (rtx pat)
22882 /* stack_tie does not produce any real memory traffic. */
22883 if (GET_CODE (pat) == UNSPEC
22884 && XINT (pat, 1) == UNSPEC_TIE)
22887 if (GET_CODE (pat) == MEM)
22890 /* Recursively process the pattern. */
22891 fmt = GET_RTX_FORMAT (GET_CODE (pat));
22893 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
22896 ret |= is_mem_ref (XEXP (pat, i));
22897 else if (fmt[i] == 'E')
22898 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
22899 ret |= is_mem_ref (XVECEXP (pat, i, j));
22905 /* Determine if PAT is a PATTERN of a load insn. */
22908 is_load_insn1 (rtx pat)
22910 if (!pat || pat == NULL_RTX)
22913 if (GET_CODE (pat) == SET)
22914 return is_mem_ref (SET_SRC (pat));
22916 if (GET_CODE (pat) == PARALLEL)
22920 for (i = 0; i < XVECLEN (pat, 0); i++)
22921 if (is_load_insn1 (XVECEXP (pat, 0, i)))
22928 /* Determine if INSN loads from memory. */
22931 is_load_insn (rtx insn)
22933 if (!insn || !INSN_P (insn))
22936 if (GET_CODE (insn) == CALL_INSN)
22939 return is_load_insn1 (PATTERN (insn));
22942 /* Determine if PAT is a PATTERN of a store insn. */
22945 is_store_insn1 (rtx pat)
22947 if (!pat || pat == NULL_RTX)
22950 if (GET_CODE (pat) == SET)
22951 return is_mem_ref (SET_DEST (pat));
22953 if (GET_CODE (pat) == PARALLEL)
22957 for (i = 0; i < XVECLEN (pat, 0); i++)
22958 if (is_store_insn1 (XVECEXP (pat, 0, i)))
22965 /* Determine if INSN stores to memory. */
22968 is_store_insn (rtx insn)
22970 if (!insn || !INSN_P (insn))
22973 return is_store_insn1 (PATTERN (insn));
22976 /* Return the dest of a store insn. */
22979 get_store_dest (rtx pat)
22981 gcc_assert (is_store_insn1 (pat));
22983 if (GET_CODE (pat) == SET)
22984 return SET_DEST (pat);
22985 else if (GET_CODE (pat) == PARALLEL)
22989 for (i = 0; i < XVECLEN (pat, 0); i++)
22991 rtx inner_pat = XVECEXP (pat, 0, i);
22992 if (GET_CODE (inner_pat) == SET
22993 && is_mem_ref (SET_DEST (inner_pat)))
22997 /* We shouldn't get here, because we should have either a simple
22998 store insn or a store with update which are covered above. */
23002 /* Returns whether the dependence between INSN and NEXT is considered
23003 costly by the given target. */
23006 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
23011 /* If the flag is not enabled - no dependence is considered costly;
23012 allow all dependent insns in the same group.
23013 This is the most aggressive option. */
23014 if (rs6000_sched_costly_dep == no_dep_costly)
23017 /* If the flag is set to 1 - a dependence is always considered costly;
23018 do not allow dependent instructions in the same group.
23019 This is the most conservative option. */
23020 if (rs6000_sched_costly_dep == all_deps_costly)
23023 insn = DEP_PRO (dep);
23024 next = DEP_CON (dep);
23026 if (rs6000_sched_costly_dep == store_to_load_dep_costly
23027 && is_load_insn (next)
23028 && is_store_insn (insn))
23029 /* Prevent load after store in the same group. */
23032 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
23033 && is_load_insn (next)
23034 && is_store_insn (insn)
23035 && DEP_TYPE (dep) == REG_DEP_TRUE)
23036 /* Prevent load after store in the same group if it is a true
23040 /* The flag is set to X; dependences with latency >= X are considered costly,
23041 and will not be scheduled in the same group. */
23042 if (rs6000_sched_costly_dep <= max_dep_latency
23043 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
23049 /* Return the next insn after INSN that is found before TAIL is reached,
23050 skipping any "non-active" insns - insns that will not actually occupy
23051 an issue slot. Return NULL_RTX if such an insn is not found. */
23054 get_next_active_insn (rtx insn, rtx tail)
23056 if (insn == NULL_RTX || insn == tail)
23061 insn = NEXT_INSN (insn);
23062 if (insn == NULL_RTX || insn == tail)
23067 || (NONJUMP_INSN_P (insn)
23068 && GET_CODE (PATTERN (insn)) != USE
23069 && GET_CODE (PATTERN (insn)) != CLOBBER
23070 && INSN_CODE (insn) != CODE_FOR_stack_tie))
23076 /* We are about to begin issuing insns for this clock cycle. */
23079 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
23080 rtx *ready ATTRIBUTE_UNUSED,
23081 int *pn_ready ATTRIBUTE_UNUSED,
23082 int clock_var ATTRIBUTE_UNUSED)
23084 int n_ready = *pn_ready;
23087 fprintf (dump, "// rs6000_sched_reorder :\n");
23089 /* Reorder the ready list, if the second to last ready insn
23090 is a nonepipeline insn. */
23091 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
23093 if (is_nonpipeline_insn (ready[n_ready - 1])
23094 && (recog_memoized (ready[n_ready - 2]) > 0))
23095 /* Simply swap first two insns. */
23097 rtx tmp = ready[n_ready - 1];
23098 ready[n_ready - 1] = ready[n_ready - 2];
23099 ready[n_ready - 2] = tmp;
23103 if (rs6000_cpu == PROCESSOR_POWER6)
23104 load_store_pendulum = 0;
23106 return rs6000_issue_rate ();
23109 /* Like rs6000_sched_reorder, but called after issuing each insn. */
23112 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
23113 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
23116 fprintf (dump, "// rs6000_sched_reorder2 :\n");
23118 /* For Power6, we need to handle some special cases to try and keep the
23119 store queue from overflowing and triggering expensive flushes.
23121 This code monitors how load and store instructions are being issued
23122 and skews the ready list one way or the other to increase the likelihood
23123 that a desired instruction is issued at the proper time.
23125 A couple of things are done. First, we maintain a "load_store_pendulum"
23126 to track the current state of load/store issue.
23128 - If the pendulum is at zero, then no loads or stores have been
23129 issued in the current cycle so we do nothing.
23131 - If the pendulum is 1, then a single load has been issued in this
23132 cycle and we attempt to locate another load in the ready list to
23135 - If the pendulum is -2, then two stores have already been
23136 issued in this cycle, so we increase the priority of the first load
23137 in the ready list to increase it's likelihood of being chosen first
23140 - If the pendulum is -1, then a single store has been issued in this
23141 cycle and we attempt to locate another store in the ready list to
23142 issue with it, preferring a store to an adjacent memory location to
23143 facilitate store pairing in the store queue.
23145 - If the pendulum is 2, then two loads have already been
23146 issued in this cycle, so we increase the priority of the first store
23147 in the ready list to increase it's likelihood of being chosen first
23150 - If the pendulum < -2 or > 2, then do nothing.
23152 Note: This code covers the most common scenarios. There exist non
23153 load/store instructions which make use of the LSU and which
23154 would need to be accounted for to strictly model the behavior
23155 of the machine. Those instructions are currently unaccounted
23156 for to help minimize compile time overhead of this code.
23158 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
23164 if (is_store_insn (last_scheduled_insn))
23165 /* Issuing a store, swing the load_store_pendulum to the left */
23166 load_store_pendulum--;
23167 else if (is_load_insn (last_scheduled_insn))
23168 /* Issuing a load, swing the load_store_pendulum to the right */
23169 load_store_pendulum++;
23171 return cached_can_issue_more;
23173 /* If the pendulum is balanced, or there is only one instruction on
23174 the ready list, then all is well, so return. */
23175 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
23176 return cached_can_issue_more;
23178 if (load_store_pendulum == 1)
23180 /* A load has been issued in this cycle. Scan the ready list
23181 for another load to issue with it */
23186 if (is_load_insn (ready[pos]))
23188 /* Found a load. Move it to the head of the ready list,
23189 and adjust it's priority so that it is more likely to
23192 for (i=pos; i<*pn_ready-1; i++)
23193 ready[i] = ready[i + 1];
23194 ready[*pn_ready-1] = tmp;
23196 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23197 INSN_PRIORITY (tmp)++;
23203 else if (load_store_pendulum == -2)
23205 /* Two stores have been issued in this cycle. Increase the
23206 priority of the first load in the ready list to favor it for
23207 issuing in the next cycle. */
23212 if (is_load_insn (ready[pos])
23214 && INSN_PRIORITY_KNOWN (ready[pos]))
23216 INSN_PRIORITY (ready[pos])++;
23218 /* Adjust the pendulum to account for the fact that a load
23219 was found and increased in priority. This is to prevent
23220 increasing the priority of multiple loads */
23221 load_store_pendulum--;
23228 else if (load_store_pendulum == -1)
23230 /* A store has been issued in this cycle. Scan the ready list for
23231 another store to issue with it, preferring a store to an adjacent
23233 int first_store_pos = -1;
23239 if (is_store_insn (ready[pos]))
23241 /* Maintain the index of the first store found on the
23243 if (first_store_pos == -1)
23244 first_store_pos = pos;
23246 if (is_store_insn (last_scheduled_insn)
23247 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
23249 /* Found an adjacent store. Move it to the head of the
23250 ready list, and adjust it's priority so that it is
23251 more likely to stay there */
23253 for (i=pos; i<*pn_ready-1; i++)
23254 ready[i] = ready[i + 1];
23255 ready[*pn_ready-1] = tmp;
23257 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23258 INSN_PRIORITY (tmp)++;
23260 first_store_pos = -1;
23268 if (first_store_pos >= 0)
23270 /* An adjacent store wasn't found, but a non-adjacent store was,
23271 so move the non-adjacent store to the front of the ready
23272 list, and adjust its priority so that it is more likely to
23274 tmp = ready[first_store_pos];
23275 for (i=first_store_pos; i<*pn_ready-1; i++)
23276 ready[i] = ready[i + 1];
23277 ready[*pn_ready-1] = tmp;
23278 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23279 INSN_PRIORITY (tmp)++;
23282 else if (load_store_pendulum == 2)
23284 /* Two loads have been issued in this cycle. Increase the priority
23285 of the first store in the ready list to favor it for issuing in
23291 if (is_store_insn (ready[pos])
23293 && INSN_PRIORITY_KNOWN (ready[pos]))
23295 INSN_PRIORITY (ready[pos])++;
23297 /* Adjust the pendulum to account for the fact that a store
23298 was found and increased in priority. This is to prevent
23299 increasing the priority of multiple stores */
23300 load_store_pendulum++;
23309 return cached_can_issue_more;
23312 /* Return whether the presence of INSN causes a dispatch group termination
23313 of group WHICH_GROUP.
23315 If WHICH_GROUP == current_group, this function will return true if INSN
23316 causes the termination of the current group (i.e, the dispatch group to
23317 which INSN belongs). This means that INSN will be the last insn in the
23318 group it belongs to.
23320 If WHICH_GROUP == previous_group, this function will return true if INSN
23321 causes the termination of the previous group (i.e, the dispatch group that
23322 precedes the group to which INSN belongs). This means that INSN will be
23323 the first insn in the group it belongs to). */
23326 insn_terminates_group_p (rtx insn, enum group_termination which_group)
23333 first = insn_must_be_first_in_group (insn);
23334 last = insn_must_be_last_in_group (insn);
23339 if (which_group == current_group)
23341 else if (which_group == previous_group)
23349 insn_must_be_first_in_group (rtx insn)
23351 enum attr_type type;
23354 || GET_CODE (insn) == NOTE
23355 || DEBUG_INSN_P (insn)
23356 || GET_CODE (PATTERN (insn)) == USE
23357 || GET_CODE (PATTERN (insn)) == CLOBBER)
23360 switch (rs6000_cpu)
23362 case PROCESSOR_POWER5:
23363 if (is_cracked_insn (insn))
23365 case PROCESSOR_POWER4:
23366 if (is_microcoded_insn (insn))
23369 if (!rs6000_sched_groups)
23372 type = get_attr_type (insn);
23379 case TYPE_DELAYED_CR:
23380 case TYPE_CR_LOGICAL:
23394 case PROCESSOR_POWER6:
23395 type = get_attr_type (insn);
23399 case TYPE_INSERT_DWORD:
23403 case TYPE_VAR_SHIFT_ROTATE:
23410 case TYPE_INSERT_WORD:
23411 case TYPE_DELAYED_COMPARE:
23412 case TYPE_IMUL_COMPARE:
23413 case TYPE_LMUL_COMPARE:
23414 case TYPE_FPCOMPARE:
23425 case TYPE_LOAD_EXT_UX:
23427 case TYPE_STORE_UX:
23428 case TYPE_FPLOAD_U:
23429 case TYPE_FPLOAD_UX:
23430 case TYPE_FPSTORE_U:
23431 case TYPE_FPSTORE_UX:
23437 case PROCESSOR_POWER7:
23438 type = get_attr_type (insn);
23442 case TYPE_CR_LOGICAL:
23449 case TYPE_DELAYED_COMPARE:
23450 case TYPE_VAR_DELAYED_COMPARE:
23456 case TYPE_LOAD_EXT:
23457 case TYPE_LOAD_EXT_U:
23458 case TYPE_LOAD_EXT_UX:
23460 case TYPE_STORE_UX:
23461 case TYPE_FPLOAD_U:
23462 case TYPE_FPLOAD_UX:
23463 case TYPE_FPSTORE_U:
23464 case TYPE_FPSTORE_UX:
23480 insn_must_be_last_in_group (rtx insn)
23482 enum attr_type type;
23485 || GET_CODE (insn) == NOTE
23486 || DEBUG_INSN_P (insn)
23487 || GET_CODE (PATTERN (insn)) == USE
23488 || GET_CODE (PATTERN (insn)) == CLOBBER)
23491 switch (rs6000_cpu) {
23492 case PROCESSOR_POWER4:
23493 case PROCESSOR_POWER5:
23494 if (is_microcoded_insn (insn))
23497 if (is_branch_slot_insn (insn))
23501 case PROCESSOR_POWER6:
23502 type = get_attr_type (insn);
23509 case TYPE_VAR_SHIFT_ROTATE:
23516 case TYPE_DELAYED_COMPARE:
23517 case TYPE_IMUL_COMPARE:
23518 case TYPE_LMUL_COMPARE:
23519 case TYPE_FPCOMPARE:
23533 case PROCESSOR_POWER7:
23534 type = get_attr_type (insn);
23542 case TYPE_LOAD_EXT_U:
23543 case TYPE_LOAD_EXT_UX:
23544 case TYPE_STORE_UX:
23557 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
23558 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
23561 is_costly_group (rtx *group_insns, rtx next_insn)
23564 int issue_rate = rs6000_issue_rate ();
23566 for (i = 0; i < issue_rate; i++)
23568 sd_iterator_def sd_it;
23570 rtx insn = group_insns[i];
23575 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
23577 rtx next = DEP_CON (dep);
23579 if (next == next_insn
23580 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
23588 /* Utility of the function redefine_groups.
23589 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
23590 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
23591 to keep it "far" (in a separate group) from GROUP_INSNS, following
23592 one of the following schemes, depending on the value of the flag
23593 -minsert_sched_nops = X:
23594 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
23595 in order to force NEXT_INSN into a separate group.
23596 (2) X < sched_finish_regroup_exact: insert exactly X nops.
23597 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
23598 insertion (has a group just ended, how many vacant issue slots remain in the
23599 last group, and how many dispatch groups were encountered so far). */
23602 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
23603 rtx next_insn, bool *group_end, int can_issue_more,
23608 int issue_rate = rs6000_issue_rate ();
23609 bool end = *group_end;
23612 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
23613 return can_issue_more;
23615 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
23616 return can_issue_more;
23618 force = is_costly_group (group_insns, next_insn);
23620 return can_issue_more;
23622 if (sched_verbose > 6)
23623 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
23624 *group_count ,can_issue_more);
23626 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
23629 can_issue_more = 0;
23631 /* Since only a branch can be issued in the last issue_slot, it is
23632 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
23633 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
23634 in this case the last nop will start a new group and the branch
23635 will be forced to the new group. */
23636 if (can_issue_more && !is_branch_slot_insn (next_insn))
23639 while (can_issue_more > 0)
23642 emit_insn_before (nop, next_insn);
23650 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
23652 int n_nops = rs6000_sched_insert_nops;
23654 /* Nops can't be issued from the branch slot, so the effective
23655 issue_rate for nops is 'issue_rate - 1'. */
23656 if (can_issue_more == 0)
23657 can_issue_more = issue_rate;
23659 if (can_issue_more == 0)
23661 can_issue_more = issue_rate - 1;
23664 for (i = 0; i < issue_rate; i++)
23666 group_insns[i] = 0;
23673 emit_insn_before (nop, next_insn);
23674 if (can_issue_more == issue_rate - 1) /* new group begins */
23677 if (can_issue_more == 0)
23679 can_issue_more = issue_rate - 1;
23682 for (i = 0; i < issue_rate; i++)
23684 group_insns[i] = 0;
23690 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
23693 /* Is next_insn going to start a new group? */
23696 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
23697 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
23698 || (can_issue_more < issue_rate &&
23699 insn_terminates_group_p (next_insn, previous_group)));
23700 if (*group_end && end)
23703 if (sched_verbose > 6)
23704 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
23705 *group_count, can_issue_more);
23706 return can_issue_more;
23709 return can_issue_more;
23712 /* This function tries to synch the dispatch groups that the compiler "sees"
23713 with the dispatch groups that the processor dispatcher is expected to
23714 form in practice. It tries to achieve this synchronization by forcing the
23715 estimated processor grouping on the compiler (as opposed to the function
23716 'pad_goups' which tries to force the scheduler's grouping on the processor).
23718 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
23719 examines the (estimated) dispatch groups that will be formed by the processor
23720 dispatcher. It marks these group boundaries to reflect the estimated
23721 processor grouping, overriding the grouping that the scheduler had marked.
23722 Depending on the value of the flag '-minsert-sched-nops' this function can
23723 force certain insns into separate groups or force a certain distance between
23724 them by inserting nops, for example, if there exists a "costly dependence"
23727 The function estimates the group boundaries that the processor will form as
23728 follows: It keeps track of how many vacant issue slots are available after
23729 each insn. A subsequent insn will start a new group if one of the following
23731 - no more vacant issue slots remain in the current dispatch group.
23732 - only the last issue slot, which is the branch slot, is vacant, but the next
23733 insn is not a branch.
23734 - only the last 2 or less issue slots, including the branch slot, are vacant,
23735 which means that a cracked insn (which occupies two issue slots) can't be
23736 issued in this group.
23737 - less than 'issue_rate' slots are vacant, and the next insn always needs to
23738 start a new group. */
23741 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
23743 rtx insn, next_insn;
23745 int can_issue_more;
23748 int group_count = 0;
23752 issue_rate = rs6000_issue_rate ();
23753 group_insns = XALLOCAVEC (rtx, issue_rate);
23754 for (i = 0; i < issue_rate; i++)
23756 group_insns[i] = 0;
23758 can_issue_more = issue_rate;
23760 insn = get_next_active_insn (prev_head_insn, tail);
23763 while (insn != NULL_RTX)
23765 slot = (issue_rate - can_issue_more);
23766 group_insns[slot] = insn;
23768 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
23769 if (insn_terminates_group_p (insn, current_group))
23770 can_issue_more = 0;
23772 next_insn = get_next_active_insn (insn, tail);
23773 if (next_insn == NULL_RTX)
23774 return group_count + 1;
23776 /* Is next_insn going to start a new group? */
23778 = (can_issue_more == 0
23779 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
23780 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
23781 || (can_issue_more < issue_rate &&
23782 insn_terminates_group_p (next_insn, previous_group)));
23784 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
23785 next_insn, &group_end, can_issue_more,
23791 can_issue_more = 0;
23792 for (i = 0; i < issue_rate; i++)
23794 group_insns[i] = 0;
23798 if (GET_MODE (next_insn) == TImode && can_issue_more)
23799 PUT_MODE (next_insn, VOIDmode);
23800 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
23801 PUT_MODE (next_insn, TImode);
23804 if (can_issue_more == 0)
23805 can_issue_more = issue_rate;
23808 return group_count;
23811 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
23812 dispatch group boundaries that the scheduler had marked. Pad with nops
23813 any dispatch groups which have vacant issue slots, in order to force the
23814 scheduler's grouping on the processor dispatcher. The function
23815 returns the number of dispatch groups found. */
23818 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
23820 rtx insn, next_insn;
23823 int can_issue_more;
23825 int group_count = 0;
23827 /* Initialize issue_rate. */
23828 issue_rate = rs6000_issue_rate ();
23829 can_issue_more = issue_rate;
23831 insn = get_next_active_insn (prev_head_insn, tail);
23832 next_insn = get_next_active_insn (insn, tail);
23834 while (insn != NULL_RTX)
23837 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
23839 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
23841 if (next_insn == NULL_RTX)
23846 /* If the scheduler had marked group termination at this location
23847 (between insn and next_insn), and neither insn nor next_insn will
23848 force group termination, pad the group with nops to force group
23851 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
23852 && !insn_terminates_group_p (insn, current_group)
23853 && !insn_terminates_group_p (next_insn, previous_group))
23855 if (!is_branch_slot_insn (next_insn))
23858 while (can_issue_more)
23861 emit_insn_before (nop, next_insn);
23866 can_issue_more = issue_rate;
23871 next_insn = get_next_active_insn (insn, tail);
23874 return group_count;
23877 /* We're beginning a new block. Initialize data structures as necessary. */
23880 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
23881 int sched_verbose ATTRIBUTE_UNUSED,
23882 int max_ready ATTRIBUTE_UNUSED)
23884 last_scheduled_insn = NULL_RTX;
23885 load_store_pendulum = 0;
23888 /* The following function is called at the end of scheduling BB.
23889 After reload, it inserts nops at insn group bundling. */
23892 rs6000_sched_finish (FILE *dump, int sched_verbose)
23897 fprintf (dump, "=== Finishing schedule.\n");
23899 if (reload_completed && rs6000_sched_groups)
23901 /* Do not run sched_finish hook when selective scheduling enabled. */
23902 if (sel_sched_p ())
23905 if (rs6000_sched_insert_nops == sched_finish_none)
23908 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
23909 n_groups = pad_groups (dump, sched_verbose,
23910 current_sched_info->prev_head,
23911 current_sched_info->next_tail);
23913 n_groups = redefine_groups (dump, sched_verbose,
23914 current_sched_info->prev_head,
23915 current_sched_info->next_tail);
23917 if (sched_verbose >= 6)
23919 fprintf (dump, "ngroups = %d\n", n_groups);
23920 print_rtl (dump, current_sched_info->prev_head);
23921 fprintf (dump, "Done finish_sched\n");
23926 struct _rs6000_sched_context
23928 short cached_can_issue_more;
23929 rtx last_scheduled_insn;
23930 int load_store_pendulum;
23933 typedef struct _rs6000_sched_context rs6000_sched_context_def;
23934 typedef rs6000_sched_context_def *rs6000_sched_context_t;
23936 /* Allocate store for new scheduling context. */
23938 rs6000_alloc_sched_context (void)
23940 return xmalloc (sizeof (rs6000_sched_context_def));
23943 /* If CLEAN_P is true then initializes _SC with clean data,
23944 and from the global context otherwise. */
23946 rs6000_init_sched_context (void *_sc, bool clean_p)
23948 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
23952 sc->cached_can_issue_more = 0;
23953 sc->last_scheduled_insn = NULL_RTX;
23954 sc->load_store_pendulum = 0;
23958 sc->cached_can_issue_more = cached_can_issue_more;
23959 sc->last_scheduled_insn = last_scheduled_insn;
23960 sc->load_store_pendulum = load_store_pendulum;
23964 /* Sets the global scheduling context to the one pointed to by _SC. */
23966 rs6000_set_sched_context (void *_sc)
23968 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
23970 gcc_assert (sc != NULL);
23972 cached_can_issue_more = sc->cached_can_issue_more;
23973 last_scheduled_insn = sc->last_scheduled_insn;
23974 load_store_pendulum = sc->load_store_pendulum;
23979 rs6000_free_sched_context (void *_sc)
23981 gcc_assert (_sc != NULL);
23987 /* Length in units of the trampoline for entering a nested function. */
23990 rs6000_trampoline_size (void)
23994 switch (DEFAULT_ABI)
23997 gcc_unreachable ();
24000 ret = (TARGET_32BIT) ? 12 : 24;
24005 ret = (TARGET_32BIT) ? 40 : 48;
24012 /* Emit RTL insns to initialize the variable parts of a trampoline.
24013 FNADDR is an RTX for the address of the function's pure code.
24014 CXT is an RTX for the static chain value for the function. */
24017 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
24019 int regsize = (TARGET_32BIT) ? 4 : 8;
24020 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
24021 rtx ctx_reg = force_reg (Pmode, cxt);
24022 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
24024 switch (DEFAULT_ABI)
24027 gcc_unreachable ();
24029 /* Under AIX, just build the 3 word function descriptor */
24032 rtx fnmem, fn_reg, toc_reg;
24034 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
24035 error ("-mno-r11 must not be used if you have trampolines");
24037 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
24038 fn_reg = gen_reg_rtx (Pmode);
24039 toc_reg = gen_reg_rtx (Pmode);
24041 /* Macro to shorten the code expansions below. */
24042 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
24044 m_tramp = replace_equiv_address (m_tramp, addr);
24046 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
24047 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
24048 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
24049 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
24050 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
24056 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
24059 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
24060 LCT_NORMAL, VOIDmode, 4,
24062 GEN_INT (rs6000_trampoline_size ()), SImode,
24070 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
24071 identifier as an argument, so the front end shouldn't look it up. */
24074 rs6000_attribute_takes_identifier_p (const_tree attr_id)
24076 return is_attribute_p ("altivec", attr_id);
24079 /* Handle the "altivec" attribute. The attribute may have
24080 arguments as follows:
24082 __attribute__((altivec(vector__)))
24083 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
24084 __attribute__((altivec(bool__))) (always followed by 'unsigned')
24086 and may appear more than once (e.g., 'vector bool char') in a
24087 given declaration. */
24090 rs6000_handle_altivec_attribute (tree *node,
24091 tree name ATTRIBUTE_UNUSED,
24093 int flags ATTRIBUTE_UNUSED,
24094 bool *no_add_attrs)
24096 tree type = *node, result = NULL_TREE;
24097 enum machine_mode mode;
24100 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
24101 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
24102 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
24105 while (POINTER_TYPE_P (type)
24106 || TREE_CODE (type) == FUNCTION_TYPE
24107 || TREE_CODE (type) == METHOD_TYPE
24108 || TREE_CODE (type) == ARRAY_TYPE)
24109 type = TREE_TYPE (type);
24111 mode = TYPE_MODE (type);
24113 /* Check for invalid AltiVec type qualifiers. */
24114 if (type == long_double_type_node)
24115 error ("use of %<long double%> in AltiVec types is invalid");
24116 else if (type == boolean_type_node)
24117 error ("use of boolean types in AltiVec types is invalid");
24118 else if (TREE_CODE (type) == COMPLEX_TYPE)
24119 error ("use of %<complex%> in AltiVec types is invalid");
24120 else if (DECIMAL_FLOAT_MODE_P (mode))
24121 error ("use of decimal floating point types in AltiVec types is invalid");
24122 else if (!TARGET_VSX)
24124 if (type == long_unsigned_type_node || type == long_integer_type_node)
24127 error ("use of %<long%> in AltiVec types is invalid for "
24128 "64-bit code without -mvsx");
24129 else if (rs6000_warn_altivec_long)
24130 warning (0, "use of %<long%> in AltiVec types is deprecated; "
24133 else if (type == long_long_unsigned_type_node
24134 || type == long_long_integer_type_node)
24135 error ("use of %<long long%> in AltiVec types is invalid without "
24137 else if (type == double_type_node)
24138 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
24141 switch (altivec_type)
24144 unsigned_p = TYPE_UNSIGNED (type);
24148 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
24151 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
24154 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
24157 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
24159 case SFmode: result = V4SF_type_node; break;
24160 case DFmode: result = V2DF_type_node; break;
24161 /* If the user says 'vector int bool', we may be handed the 'bool'
24162 attribute _before_ the 'vector' attribute, and so select the
24163 proper type in the 'b' case below. */
24164 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
24165 case V2DImode: case V2DFmode:
24173 case DImode: case V2DImode: result = bool_V2DI_type_node; break;
24174 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
24175 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
24176 case QImode: case V16QImode: result = bool_V16QI_type_node;
24183 case V8HImode: result = pixel_V8HI_type_node;
24189 /* Propagate qualifiers attached to the element type
24190 onto the vector type. */
24191 if (result && result != type && TYPE_QUALS (type))
24192 result = build_qualified_type (result, TYPE_QUALS (type));
24194 *no_add_attrs = true; /* No need to hang on to the attribute. */
24197 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
24202 /* AltiVec defines four built-in scalar types that serve as vector
24203 elements; we must teach the compiler how to mangle them. */
24205 static const char *
24206 rs6000_mangle_type (const_tree type)
24208 type = TYPE_MAIN_VARIANT (type);
24210 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
24211 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
24214 if (type == bool_char_type_node) return "U6__boolc";
24215 if (type == bool_short_type_node) return "U6__bools";
24216 if (type == pixel_type_node) return "u7__pixel";
24217 if (type == bool_int_type_node) return "U6__booli";
24218 if (type == bool_long_type_node) return "U6__booll";
24220 /* Mangle IBM extended float long double as `g' (__float128) on
24221 powerpc*-linux where long-double-64 previously was the default. */
24222 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
24224 && TARGET_LONG_DOUBLE_128
24225 && !TARGET_IEEEQUAD)
24228 /* For all other types, use normal C++ mangling. */
24232 /* Handle a "longcall" or "shortcall" attribute; arguments as in
24233 struct attribute_spec.handler. */
24236 rs6000_handle_longcall_attribute (tree *node, tree name,
24237 tree args ATTRIBUTE_UNUSED,
24238 int flags ATTRIBUTE_UNUSED,
24239 bool *no_add_attrs)
24241 if (TREE_CODE (*node) != FUNCTION_TYPE
24242 && TREE_CODE (*node) != FIELD_DECL
24243 && TREE_CODE (*node) != TYPE_DECL)
24245 warning (OPT_Wattributes, "%qE attribute only applies to functions",
24247 *no_add_attrs = true;
24253 /* Set longcall attributes on all functions declared when
24254 rs6000_default_long_calls is true. */
24256 rs6000_set_default_type_attributes (tree type)
24258 if (rs6000_default_long_calls
24259 && (TREE_CODE (type) == FUNCTION_TYPE
24260 || TREE_CODE (type) == METHOD_TYPE))
24261 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
24263 TYPE_ATTRIBUTES (type));
24266 darwin_set_default_type_attributes (type);
24270 /* Return a reference suitable for calling a function with the
24271 longcall attribute. */
24274 rs6000_longcall_ref (rtx call_ref)
24276 const char *call_name;
24279 if (GET_CODE (call_ref) != SYMBOL_REF)
24282 /* System V adds '.' to the internal name, so skip them. */
24283 call_name = XSTR (call_ref, 0);
24284 if (*call_name == '.')
24286 while (*call_name == '.')
24289 node = get_identifier (call_name);
24290 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
24293 return force_reg (Pmode, call_ref);
24296 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
24297 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
24300 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
24301 struct attribute_spec.handler. */
24303 rs6000_handle_struct_attribute (tree *node, tree name,
24304 tree args ATTRIBUTE_UNUSED,
24305 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
24308 if (DECL_P (*node))
24310 if (TREE_CODE (*node) == TYPE_DECL)
24311 type = &TREE_TYPE (*node);
24316 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
24317 || TREE_CODE (*type) == UNION_TYPE)))
24319 warning (OPT_Wattributes, "%qE attribute ignored", name);
24320 *no_add_attrs = true;
24323 else if ((is_attribute_p ("ms_struct", name)
24324 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
24325 || ((is_attribute_p ("gcc_struct", name)
24326 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
24328 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
24330 *no_add_attrs = true;
24337 rs6000_ms_bitfield_layout_p (const_tree record_type)
24339 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
24340 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
24341 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
24344 #ifdef USING_ELFOS_H
24346 /* A get_unnamed_section callback, used for switching to toc_section. */
24349 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
24351 if (DEFAULT_ABI == ABI_AIX
24352 && TARGET_MINIMAL_TOC
24353 && !TARGET_RELOCATABLE)
24355 if (!toc_initialized)
24357 toc_initialized = 1;
24358 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
24359 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
24360 fprintf (asm_out_file, "\t.tc ");
24361 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
24362 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24363 fprintf (asm_out_file, "\n");
24365 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24366 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24367 fprintf (asm_out_file, " = .+32768\n");
24370 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24372 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
24373 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
24376 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24377 if (!toc_initialized)
24379 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24380 fprintf (asm_out_file, " = .+32768\n");
24381 toc_initialized = 1;
24386 /* Implement TARGET_ASM_INIT_SECTIONS. */
24389 rs6000_elf_asm_init_sections (void)
24392 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
24395 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
24396 SDATA2_SECTION_ASM_OP);
24399 /* Implement TARGET_SELECT_RTX_SECTION. */
24402 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
24403 unsigned HOST_WIDE_INT align)
24405 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
24406 return toc_section;
24408 return default_elf_select_rtx_section (mode, x, align);
24411 /* For a SYMBOL_REF, set generic flags and then perform some
24412 target-specific processing.
24414 When the AIX ABI is requested on a non-AIX system, replace the
24415 function name with the real name (with a leading .) rather than the
24416 function descriptor name. This saves a lot of overriding code to
24417 read the prefixes. */
24420 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
24422 default_encode_section_info (decl, rtl, first);
24425 && TREE_CODE (decl) == FUNCTION_DECL
24427 && DEFAULT_ABI == ABI_AIX)
24429 rtx sym_ref = XEXP (rtl, 0);
24430 size_t len = strlen (XSTR (sym_ref, 0));
24431 char *str = XALLOCAVEC (char, len + 2);
24433 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
24434 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
24439 compare_section_name (const char *section, const char *templ)
24443 len = strlen (templ);
24444 return (strncmp (section, templ, len) == 0
24445 && (section[len] == 0 || section[len] == '.'));
24449 rs6000_elf_in_small_data_p (const_tree decl)
24451 if (rs6000_sdata == SDATA_NONE)
24454 /* We want to merge strings, so we never consider them small data. */
24455 if (TREE_CODE (decl) == STRING_CST)
24458 /* Functions are never in the small data area. */
24459 if (TREE_CODE (decl) == FUNCTION_DECL)
24462 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
24464 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
24465 if (compare_section_name (section, ".sdata")
24466 || compare_section_name (section, ".sdata2")
24467 || compare_section_name (section, ".gnu.linkonce.s")
24468 || compare_section_name (section, ".sbss")
24469 || compare_section_name (section, ".sbss2")
24470 || compare_section_name (section, ".gnu.linkonce.sb")
24471 || strcmp (section, ".PPC.EMB.sdata0") == 0
24472 || strcmp (section, ".PPC.EMB.sbss0") == 0)
24477 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
24480 && size <= g_switch_value
24481 /* If it's not public, and we're not going to reference it there,
24482 there's no need to put it in the small data section. */
24483 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
24490 #endif /* USING_ELFOS_H */
24492 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
24495 rs6000_use_blocks_for_constant_p (enum machine_mode mode, const_rtx x)
24497 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
24500 /* Return a REG that occurs in ADDR with coefficient 1.
24501 ADDR can be effectively incremented by incrementing REG.
24503 r0 is special and we must not select it as an address
24504 register by this routine since our caller will try to
24505 increment the returned register via an "la" instruction. */
24508 find_addr_reg (rtx addr)
24510 while (GET_CODE (addr) == PLUS)
24512 if (GET_CODE (XEXP (addr, 0)) == REG
24513 && REGNO (XEXP (addr, 0)) != 0)
24514 addr = XEXP (addr, 0);
24515 else if (GET_CODE (XEXP (addr, 1)) == REG
24516 && REGNO (XEXP (addr, 1)) != 0)
24517 addr = XEXP (addr, 1);
24518 else if (CONSTANT_P (XEXP (addr, 0)))
24519 addr = XEXP (addr, 1);
24520 else if (CONSTANT_P (XEXP (addr, 1)))
24521 addr = XEXP (addr, 0);
24523 gcc_unreachable ();
24525 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
24530 rs6000_fatal_bad_address (rtx op)
24532 fatal_insn ("bad address", op);
24537 typedef struct branch_island_d {
24538 tree function_name;
24543 DEF_VEC_O(branch_island);
24544 DEF_VEC_ALLOC_O(branch_island,gc);
24546 static VEC(branch_island,gc) *branch_islands;
24548 /* Remember to generate a branch island for far calls to the given
24552 add_compiler_branch_island (tree label_name, tree function_name,
24555 branch_island *bi = VEC_safe_push (branch_island, gc, branch_islands, NULL);
24557 bi->function_name = function_name;
24558 bi->label_name = label_name;
24559 bi->line_number = line_number;
24562 /* Generate far-jump branch islands for everything recorded in
24563 branch_islands. Invoked immediately after the last instruction of
24564 the epilogue has been emitted; the branch islands must be appended
24565 to, and contiguous with, the function body. Mach-O stubs are
24566 generated in machopic_output_stub(). */
24569 macho_branch_islands (void)
24573 while (!VEC_empty (branch_island, branch_islands))
24575 branch_island *bi = VEC_last (branch_island, branch_islands);
24576 const char *label = IDENTIFIER_POINTER (bi->label_name);
24577 const char *name = IDENTIFIER_POINTER (bi->function_name);
24578 char name_buf[512];
24579 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
24580 if (name[0] == '*' || name[0] == '&')
24581 strcpy (name_buf, name+1);
24585 strcpy (name_buf+1, name);
24587 strcpy (tmp_buf, "\n");
24588 strcat (tmp_buf, label);
24589 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
24590 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
24591 dbxout_stabd (N_SLINE, bi->line_number);
24592 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
24595 if (TARGET_LINK_STACK)
24598 get_ppc476_thunk_name (name);
24599 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
24600 strcat (tmp_buf, name);
24601 strcat (tmp_buf, "\n");
24602 strcat (tmp_buf, label);
24603 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
24607 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
24608 strcat (tmp_buf, label);
24609 strcat (tmp_buf, "_pic\n");
24610 strcat (tmp_buf, label);
24611 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
24614 strcat (tmp_buf, "\taddis r11,r11,ha16(");
24615 strcat (tmp_buf, name_buf);
24616 strcat (tmp_buf, " - ");
24617 strcat (tmp_buf, label);
24618 strcat (tmp_buf, "_pic)\n");
24620 strcat (tmp_buf, "\tmtlr r0\n");
24622 strcat (tmp_buf, "\taddi r12,r11,lo16(");
24623 strcat (tmp_buf, name_buf);
24624 strcat (tmp_buf, " - ");
24625 strcat (tmp_buf, label);
24626 strcat (tmp_buf, "_pic)\n");
24628 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
24632 strcat (tmp_buf, ":\nlis r12,hi16(");
24633 strcat (tmp_buf, name_buf);
24634 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
24635 strcat (tmp_buf, name_buf);
24636 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
24638 output_asm_insn (tmp_buf, 0);
24639 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
24640 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
24641 dbxout_stabd (N_SLINE, bi->line_number);
24642 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
24643 VEC_pop (branch_island, branch_islands);
24647 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
24648 already there or not. */
24651 no_previous_def (tree function_name)
24656 FOR_EACH_VEC_ELT (branch_island, branch_islands, ix, bi)
24657 if (function_name == bi->function_name)
24662 /* GET_PREV_LABEL gets the label name from the previous definition of
24666 get_prev_label (tree function_name)
24671 FOR_EACH_VEC_ELT (branch_island, branch_islands, ix, bi)
24672 if (function_name == bi->function_name)
24673 return bi->label_name;
24677 /* INSN is either a function call or a millicode call. It may have an
24678 unconditional jump in its delay slot.
24680 CALL_DEST is the routine we are calling. */
24683 output_call (rtx insn, rtx *operands, int dest_operand_number,
24684 int cookie_operand_number)
24686 static char buf[256];
24687 if (darwin_emit_branch_islands
24688 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
24689 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
24692 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
24694 if (no_previous_def (funname))
24696 rtx label_rtx = gen_label_rtx ();
24697 char *label_buf, temp_buf[256];
24698 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
24699 CODE_LABEL_NUMBER (label_rtx));
24700 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
24701 labelname = get_identifier (label_buf);
24702 add_compiler_branch_island (labelname, funname, insn_line (insn));
24705 labelname = get_prev_label (funname);
24707 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
24708 instruction will reach 'foo', otherwise link as 'bl L42'".
24709 "L42" should be a 'branch island', that will do a far jump to
24710 'foo'. Branch islands are generated in
24711 macho_branch_islands(). */
24712 sprintf (buf, "jbsr %%z%d,%.246s",
24713 dest_operand_number, IDENTIFIER_POINTER (labelname));
24716 sprintf (buf, "bl %%z%d", dest_operand_number);
24720 /* Generate PIC and indirect symbol stubs. */
24723 machopic_output_stub (FILE *file, const char *symb, const char *stub)
24725 unsigned int length;
24726 char *symbol_name, *lazy_ptr_name;
24727 char *local_label_0;
24728 static int label = 0;
24730 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
24731 symb = (*targetm.strip_name_encoding) (symb);
24734 length = strlen (symb);
24735 symbol_name = XALLOCAVEC (char, length + 32);
24736 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
24738 lazy_ptr_name = XALLOCAVEC (char, length + 32);
24739 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
24742 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
24744 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
24748 fprintf (file, "\t.align 5\n");
24750 fprintf (file, "%s:\n", stub);
24751 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
24754 local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
24755 sprintf (local_label_0, "\"L%011d$spb\"", label);
24757 fprintf (file, "\tmflr r0\n");
24758 if (TARGET_LINK_STACK)
24761 get_ppc476_thunk_name (name);
24762 fprintf (file, "\tbl %s\n", name);
24763 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
24767 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
24768 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
24770 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
24771 lazy_ptr_name, local_label_0);
24772 fprintf (file, "\tmtlr r0\n");
24773 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
24774 (TARGET_64BIT ? "ldu" : "lwzu"),
24775 lazy_ptr_name, local_label_0);
24776 fprintf (file, "\tmtctr r12\n");
24777 fprintf (file, "\tbctr\n");
24781 fprintf (file, "\t.align 4\n");
24783 fprintf (file, "%s:\n", stub);
24784 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
24786 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
24787 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
24788 (TARGET_64BIT ? "ldu" : "lwzu"),
24790 fprintf (file, "\tmtctr r12\n");
24791 fprintf (file, "\tbctr\n");
24794 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
24795 fprintf (file, "%s:\n", lazy_ptr_name);
24796 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
24797 fprintf (file, "%sdyld_stub_binding_helper\n",
24798 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
24801 /* Legitimize PIC addresses. If the address is already
24802 position-independent, we return ORIG. Newly generated
24803 position-independent addresses go into a reg. This is REG if non
24804 zero, otherwise we allocate register(s) as necessary. */
24806 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
24809 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
24814 if (reg == NULL && ! reload_in_progress && ! reload_completed)
24815 reg = gen_reg_rtx (Pmode);
24817 if (GET_CODE (orig) == CONST)
24821 if (GET_CODE (XEXP (orig, 0)) == PLUS
24822 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
24825 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
24827 /* Use a different reg for the intermediate value, as
24828 it will be marked UNCHANGING. */
24829 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
24830 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
24833 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
24836 if (GET_CODE (offset) == CONST_INT)
24838 if (SMALL_INT (offset))
24839 return plus_constant (base, INTVAL (offset));
24840 else if (! reload_in_progress && ! reload_completed)
24841 offset = force_reg (Pmode, offset);
24844 rtx mem = force_const_mem (Pmode, orig);
24845 return machopic_legitimize_pic_address (mem, Pmode, reg);
24848 return gen_rtx_PLUS (Pmode, base, offset);
24851 /* Fall back on generic machopic code. */
24852 return machopic_legitimize_pic_address (orig, mode, reg);
24855 /* Output a .machine directive for the Darwin assembler, and call
24856 the generic start_file routine. */
24859 rs6000_darwin_file_start (void)
24861 static const struct
24867 { "ppc64", "ppc64", MASK_64BIT },
24868 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
24869 { "power4", "ppc970", 0 },
24870 { "G5", "ppc970", 0 },
24871 { "7450", "ppc7450", 0 },
24872 { "7400", "ppc7400", MASK_ALTIVEC },
24873 { "G4", "ppc7400", 0 },
24874 { "750", "ppc750", 0 },
24875 { "740", "ppc750", 0 },
24876 { "G3", "ppc750", 0 },
24877 { "604e", "ppc604e", 0 },
24878 { "604", "ppc604", 0 },
24879 { "603e", "ppc603", 0 },
24880 { "603", "ppc603", 0 },
24881 { "601", "ppc601", 0 },
24882 { NULL, "ppc", 0 } };
24883 const char *cpu_id = "";
24886 rs6000_file_start ();
24887 darwin_file_start ();
24889 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
24891 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
24892 cpu_id = rs6000_default_cpu;
24894 if (global_options_set.x_rs6000_cpu_index)
24895 cpu_id = processor_target_table[rs6000_cpu_index].name;
24897 /* Look through the mapping array. Pick the first name that either
24898 matches the argument, has a bit set in IF_SET that is also set
24899 in the target flags, or has a NULL name. */
24902 while (mapping[i].arg != NULL
24903 && strcmp (mapping[i].arg, cpu_id) != 0
24904 && (mapping[i].if_set & target_flags) == 0)
24907 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
24910 #endif /* TARGET_MACHO */
24914 rs6000_elf_reloc_rw_mask (void)
24918 else if (DEFAULT_ABI == ABI_AIX)
24924 /* Record an element in the table of global constructors. SYMBOL is
24925 a SYMBOL_REF of the function to be called; PRIORITY is a number
24926 between 0 and MAX_INIT_PRIORITY.
24928 This differs from default_named_section_asm_out_constructor in
24929 that we have special handling for -mrelocatable. */
24932 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
24934 const char *section = ".ctors";
24937 if (priority != DEFAULT_INIT_PRIORITY)
24939 sprintf (buf, ".ctors.%.5u",
24940 /* Invert the numbering so the linker puts us in the proper
24941 order; constructors are run from right to left, and the
24942 linker sorts in increasing order. */
24943 MAX_INIT_PRIORITY - priority);
24947 switch_to_section (get_section (section, SECTION_WRITE, NULL));
24948 assemble_align (POINTER_SIZE);
24950 if (TARGET_RELOCATABLE)
24952 fputs ("\t.long (", asm_out_file);
24953 output_addr_const (asm_out_file, symbol);
24954 fputs (")@fixup\n", asm_out_file);
24957 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
24961 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
24963 const char *section = ".dtors";
24966 if (priority != DEFAULT_INIT_PRIORITY)
24968 sprintf (buf, ".dtors.%.5u",
24969 /* Invert the numbering so the linker puts us in the proper
24970 order; constructors are run from right to left, and the
24971 linker sorts in increasing order. */
24972 MAX_INIT_PRIORITY - priority);
24976 switch_to_section (get_section (section, SECTION_WRITE, NULL));
24977 assemble_align (POINTER_SIZE);
24979 if (TARGET_RELOCATABLE)
24981 fputs ("\t.long (", asm_out_file);
24982 output_addr_const (asm_out_file, symbol);
24983 fputs (")@fixup\n", asm_out_file);
24986 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
24990 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
24994 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
24995 ASM_OUTPUT_LABEL (file, name);
24996 fputs (DOUBLE_INT_ASM_OP, file);
24997 rs6000_output_function_entry (file, name);
24998 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
25001 fputs ("\t.size\t", file);
25002 assemble_name (file, name);
25003 fputs (",24\n\t.type\t.", file);
25004 assemble_name (file, name);
25005 fputs (",@function\n", file);
25006 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
25008 fputs ("\t.globl\t.", file);
25009 assemble_name (file, name);
25014 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
25015 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
25016 rs6000_output_function_entry (file, name);
25017 fputs (":\n", file);
25021 if (TARGET_RELOCATABLE
25022 && !TARGET_SECURE_PLT
25023 && (get_pool_size () != 0 || crtl->profile)
25028 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
25030 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
25031 fprintf (file, "\t.long ");
25032 assemble_name (file, buf);
25034 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
25035 assemble_name (file, buf);
25039 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
25040 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
25042 if (DEFAULT_ABI == ABI_AIX)
25044 const char *desc_name, *orig_name;
25046 orig_name = (*targetm.strip_name_encoding) (name);
25047 desc_name = orig_name;
25048 while (*desc_name == '.')
25051 if (TREE_PUBLIC (decl))
25052 fprintf (file, "\t.globl %s\n", desc_name);
25054 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
25055 fprintf (file, "%s:\n", desc_name);
25056 fprintf (file, "\t.long %s\n", orig_name);
25057 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
25058 if (DEFAULT_ABI == ABI_AIX)
25059 fputs ("\t.long 0\n", file);
25060 fprintf (file, "\t.previous\n");
25062 ASM_OUTPUT_LABEL (file, name);
25066 rs6000_elf_file_end (void)
25068 #ifdef HAVE_AS_GNU_ATTRIBUTE
25069 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
25071 if (rs6000_passes_float)
25072 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
25073 ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) ? 1
25074 : (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT) ? 3
25076 if (rs6000_passes_vector)
25077 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
25078 (TARGET_ALTIVEC_ABI ? 2
25079 : TARGET_SPE_ABI ? 3
25081 if (rs6000_returns_struct)
25082 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
25083 aix_struct_return ? 2 : 1);
25086 #ifdef POWERPC_LINUX
25088 file_end_indicate_exec_stack ();
25095 rs6000_xcoff_asm_output_anchor (rtx symbol)
25099 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
25100 SYMBOL_REF_BLOCK_OFFSET (symbol));
25101 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
25105 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
25107 fputs (GLOBAL_ASM_OP, stream);
25108 RS6000_OUTPUT_BASENAME (stream, name);
25109 putc ('\n', stream);
25112 /* A get_unnamed_decl callback, used for read-only sections. PTR
25113 points to the section string variable. */
25116 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
25118 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
25119 *(const char *const *) directive,
25120 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
25123 /* Likewise for read-write sections. */
25126 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
25128 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
25129 *(const char *const *) directive,
25130 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
25133 /* A get_unnamed_section callback, used for switching to toc_section. */
25136 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
25138 if (TARGET_MINIMAL_TOC)
25140 /* toc_section is always selected at least once from
25141 rs6000_xcoff_file_start, so this is guaranteed to
25142 always be defined once and only once in each file. */
25143 if (!toc_initialized)
25145 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
25146 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
25147 toc_initialized = 1;
25149 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
25150 (TARGET_32BIT ? "" : ",3"));
25153 fputs ("\t.toc\n", asm_out_file);
25156 /* Implement TARGET_ASM_INIT_SECTIONS. */
25159 rs6000_xcoff_asm_init_sections (void)
25161 read_only_data_section
25162 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
25163 &xcoff_read_only_section_name);
25165 private_data_section
25166 = get_unnamed_section (SECTION_WRITE,
25167 rs6000_xcoff_output_readwrite_section_asm_op,
25168 &xcoff_private_data_section_name);
25170 read_only_private_data_section
25171 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
25172 &xcoff_private_data_section_name);
25175 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
25177 readonly_data_section = read_only_data_section;
25178 exception_section = data_section;
25182 rs6000_xcoff_reloc_rw_mask (void)
25188 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
25189 tree decl ATTRIBUTE_UNUSED)
25192 static const char * const suffix[3] = { "PR", "RO", "RW" };
25194 if (flags & SECTION_CODE)
25196 else if (flags & SECTION_WRITE)
25201 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
25202 (flags & SECTION_CODE) ? "." : "",
25203 name, suffix[smclass], flags & SECTION_ENTSIZE);
25207 rs6000_xcoff_select_section (tree decl, int reloc,
25208 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
25210 if (decl_readonly_section (decl, reloc))
25212 if (TREE_PUBLIC (decl))
25213 return read_only_data_section;
25215 return read_only_private_data_section;
25219 if (TREE_PUBLIC (decl))
25220 return data_section;
25222 return private_data_section;
25227 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
25231 /* Use select_section for private and uninitialized data. */
25232 if (!TREE_PUBLIC (decl)
25233 || DECL_COMMON (decl)
25234 || DECL_INITIAL (decl) == NULL_TREE
25235 || DECL_INITIAL (decl) == error_mark_node
25236 || (flag_zero_initialized_in_bss
25237 && initializer_zerop (DECL_INITIAL (decl))))
25240 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
25241 name = (*targetm.strip_name_encoding) (name);
25242 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
25245 /* Select section for constant in constant pool.
25247 On RS/6000, all constants are in the private read-only data area.
25248 However, if this is being placed in the TOC it must be output as a
25252 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
25253 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
25255 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
25256 return toc_section;
25258 return read_only_private_data_section;
25261 /* Remove any trailing [DS] or the like from the symbol name. */
25263 static const char *
25264 rs6000_xcoff_strip_name_encoding (const char *name)
25269 len = strlen (name);
25270 if (name[len - 1] == ']')
25271 return ggc_alloc_string (name, len - 4);
25276 /* Section attributes. AIX is always PIC. */
25278 static unsigned int
25279 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
25281 unsigned int align;
25282 unsigned int flags = default_section_type_flags (decl, name, reloc);
25284 /* Align to at least UNIT size. */
25285 if (flags & SECTION_CODE || !decl)
25286 align = MIN_UNITS_PER_WORD;
25288 /* Increase alignment of large objects if not already stricter. */
25289 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
25290 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
25291 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
25293 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
25296 /* Output at beginning of assembler file.
25298 Initialize the section names for the RS/6000 at this point.
25300 Specify filename, including full path, to assembler.
25302 We want to go into the TOC section so at least one .toc will be emitted.
25303 Also, in order to output proper .bs/.es pairs, we need at least one static
25304 [RW] section emitted.
25306 Finally, declare mcount when profiling to make the assembler happy. */
25309 rs6000_xcoff_file_start (void)
25311 rs6000_gen_section_name (&xcoff_bss_section_name,
25312 main_input_filename, ".bss_");
25313 rs6000_gen_section_name (&xcoff_private_data_section_name,
25314 main_input_filename, ".rw_");
25315 rs6000_gen_section_name (&xcoff_read_only_section_name,
25316 main_input_filename, ".ro_");
25318 fputs ("\t.file\t", asm_out_file);
25319 output_quoted_string (asm_out_file, main_input_filename);
25320 fputc ('\n', asm_out_file);
25321 if (write_symbols != NO_DEBUG)
25322 switch_to_section (private_data_section);
25323 switch_to_section (text_section);
25325 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
25326 rs6000_file_start ();
25329 /* Output at end of assembler file.
25330 On the RS/6000, referencing data should automatically pull in text. */
25333 rs6000_xcoff_file_end (void)
25335 switch_to_section (text_section);
25336 fputs ("_section_.text:\n", asm_out_file);
25337 switch_to_section (data_section);
25338 fputs (TARGET_32BIT
25339 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
25342 #endif /* TARGET_XCOFF */
25344 /* Compute a (partial) cost for rtx X. Return true if the complete
25345 cost has been computed, and false if subexpressions should be
25346 scanned. In either case, *TOTAL contains the cost result. */
25349 rs6000_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
25350 int *total, bool speed)
25352 enum machine_mode mode = GET_MODE (x);
25356 /* On the RS/6000, if it is valid in the insn, it is free. */
25358 if (((outer_code == SET
25359 || outer_code == PLUS
25360 || outer_code == MINUS)
25361 && (satisfies_constraint_I (x)
25362 || satisfies_constraint_L (x)))
25363 || (outer_code == AND
25364 && (satisfies_constraint_K (x)
25366 ? satisfies_constraint_L (x)
25367 : satisfies_constraint_J (x))
25368 || mask_operand (x, mode)
25370 && mask64_operand (x, DImode))))
25371 || ((outer_code == IOR || outer_code == XOR)
25372 && (satisfies_constraint_K (x)
25374 ? satisfies_constraint_L (x)
25375 : satisfies_constraint_J (x))))
25376 || outer_code == ASHIFT
25377 || outer_code == ASHIFTRT
25378 || outer_code == LSHIFTRT
25379 || outer_code == ROTATE
25380 || outer_code == ROTATERT
25381 || outer_code == ZERO_EXTRACT
25382 || (outer_code == MULT
25383 && satisfies_constraint_I (x))
25384 || ((outer_code == DIV || outer_code == UDIV
25385 || outer_code == MOD || outer_code == UMOD)
25386 && exact_log2 (INTVAL (x)) >= 0)
25387 || (outer_code == COMPARE
25388 && (satisfies_constraint_I (x)
25389 || satisfies_constraint_K (x)))
25390 || ((outer_code == EQ || outer_code == NE)
25391 && (satisfies_constraint_I (x)
25392 || satisfies_constraint_K (x)
25394 ? satisfies_constraint_L (x)
25395 : satisfies_constraint_J (x))))
25396 || (outer_code == GTU
25397 && satisfies_constraint_I (x))
25398 || (outer_code == LTU
25399 && satisfies_constraint_P (x)))
25404 else if ((outer_code == PLUS
25405 && reg_or_add_cint_operand (x, VOIDmode))
25406 || (outer_code == MINUS
25407 && reg_or_sub_cint_operand (x, VOIDmode))
25408 || ((outer_code == SET
25409 || outer_code == IOR
25410 || outer_code == XOR)
25412 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
25414 *total = COSTS_N_INSNS (1);
25420 if (mode == DImode && code == CONST_DOUBLE)
25422 if ((outer_code == IOR || outer_code == XOR)
25423 && CONST_DOUBLE_HIGH (x) == 0
25424 && (CONST_DOUBLE_LOW (x)
25425 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
25430 else if ((outer_code == AND && and64_2_operand (x, DImode))
25431 || ((outer_code == SET
25432 || outer_code == IOR
25433 || outer_code == XOR)
25434 && CONST_DOUBLE_HIGH (x) == 0))
25436 *total = COSTS_N_INSNS (1);
25446 /* When optimizing for size, MEM should be slightly more expensive
25447 than generating address, e.g., (plus (reg) (const)).
25448 L1 cache latency is about two instructions. */
25449 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
25458 if (FLOAT_MODE_P (mode))
25459 *total = rs6000_cost->fp;
25461 *total = COSTS_N_INSNS (1);
25465 if (GET_CODE (XEXP (x, 1)) == CONST_INT
25466 && satisfies_constraint_I (XEXP (x, 1)))
25468 if (INTVAL (XEXP (x, 1)) >= -256
25469 && INTVAL (XEXP (x, 1)) <= 255)
25470 *total = rs6000_cost->mulsi_const9;
25472 *total = rs6000_cost->mulsi_const;
25474 else if (mode == SFmode)
25475 *total = rs6000_cost->fp;
25476 else if (FLOAT_MODE_P (mode))
25477 *total = rs6000_cost->dmul;
25478 else if (mode == DImode)
25479 *total = rs6000_cost->muldi;
25481 *total = rs6000_cost->mulsi;
25485 if (mode == SFmode)
25486 *total = rs6000_cost->fp;
25488 *total = rs6000_cost->dmul;
25493 if (FLOAT_MODE_P (mode))
25495 *total = mode == DFmode ? rs6000_cost->ddiv
25496 : rs6000_cost->sdiv;
25503 if (GET_CODE (XEXP (x, 1)) == CONST_INT
25504 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
25506 if (code == DIV || code == MOD)
25508 *total = COSTS_N_INSNS (2);
25511 *total = COSTS_N_INSNS (1);
25515 if (GET_MODE (XEXP (x, 1)) == DImode)
25516 *total = rs6000_cost->divdi;
25518 *total = rs6000_cost->divsi;
25520 /* Add in shift and subtract for MOD. */
25521 if (code == MOD || code == UMOD)
25522 *total += COSTS_N_INSNS (2);
25527 *total = COSTS_N_INSNS (4);
25531 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
25535 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
25539 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
25551 *total = COSTS_N_INSNS (1);
25559 /* Handle mul_highpart. */
25560 if (outer_code == TRUNCATE
25561 && GET_CODE (XEXP (x, 0)) == MULT)
25563 if (mode == DImode)
25564 *total = rs6000_cost->muldi;
25566 *total = rs6000_cost->mulsi;
25569 else if (outer_code == AND)
25572 *total = COSTS_N_INSNS (1);
25577 if (GET_CODE (XEXP (x, 0)) == MEM)
25580 *total = COSTS_N_INSNS (1);
25586 if (!FLOAT_MODE_P (mode))
25588 *total = COSTS_N_INSNS (1);
25594 case UNSIGNED_FLOAT:
25597 case FLOAT_TRUNCATE:
25598 *total = rs6000_cost->fp;
25602 if (mode == DFmode)
25605 *total = rs6000_cost->fp;
25609 switch (XINT (x, 1))
25612 *total = rs6000_cost->fp;
25624 *total = COSTS_N_INSNS (1);
25627 else if (FLOAT_MODE_P (mode)
25628 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
25630 *total = rs6000_cost->fp;
25638 /* Carry bit requires mode == Pmode.
25639 NEG or PLUS already counted so only add one. */
25641 && (outer_code == NEG || outer_code == PLUS))
25643 *total = COSTS_N_INSNS (1);
25646 if (outer_code == SET)
25648 if (XEXP (x, 1) == const0_rtx)
25650 if (TARGET_ISEL && !TARGET_MFCRF)
25651 *total = COSTS_N_INSNS (8);
25653 *total = COSTS_N_INSNS (2);
25656 else if (mode == Pmode)
25658 *total = COSTS_N_INSNS (3);
25667 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
25669 if (TARGET_ISEL && !TARGET_MFCRF)
25670 *total = COSTS_N_INSNS (8);
25672 *total = COSTS_N_INSNS (2);
25676 if (outer_code == COMPARE)
25690 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
25693 rs6000_debug_rtx_costs (rtx x, int code, int outer_code, int opno, int *total,
25696 bool ret = rs6000_rtx_costs (x, code, outer_code, opno, total, speed);
25699 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
25700 "opno = %d, total = %d, speed = %s, x:\n",
25701 ret ? "complete" : "scan inner",
25702 GET_RTX_NAME (code),
25703 GET_RTX_NAME (outer_code),
25706 speed ? "true" : "false");
25713 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
25716 rs6000_debug_address_cost (rtx x, bool speed)
25718 int ret = TARGET_ADDRESS_COST (x, speed);
25720 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
25721 ret, speed ? "true" : "false");
25728 /* A C expression returning the cost of moving data from a register of class
25729 CLASS1 to one of CLASS2. */
25732 rs6000_register_move_cost (enum machine_mode mode,
25733 reg_class_t from, reg_class_t to)
25737 if (TARGET_DEBUG_COST)
25740 /* Moves from/to GENERAL_REGS. */
25741 if (reg_classes_intersect_p (to, GENERAL_REGS)
25742 || reg_classes_intersect_p (from, GENERAL_REGS))
25744 reg_class_t rclass = from;
25746 if (! reg_classes_intersect_p (to, GENERAL_REGS))
25749 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
25750 ret = (rs6000_memory_move_cost (mode, rclass, false)
25751 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
25753 /* It's more expensive to move CR_REGS than CR0_REGS because of the
25755 else if (rclass == CR_REGS)
25758 /* For those processors that have slow LR/CTR moves, make them more
25759 expensive than memory in order to bias spills to memory .*/
25760 else if ((rs6000_cpu == PROCESSOR_POWER6
25761 || rs6000_cpu == PROCESSOR_POWER7)
25762 && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
25763 ret = 6 * hard_regno_nregs[0][mode];
25766 /* A move will cost one instruction per GPR moved. */
25767 ret = 2 * hard_regno_nregs[0][mode];
25770 /* If we have VSX, we can easily move between FPR or Altivec registers. */
25771 else if (VECTOR_UNIT_VSX_P (mode)
25772 && reg_classes_intersect_p (to, VSX_REGS)
25773 && reg_classes_intersect_p (from, VSX_REGS))
25774 ret = 2 * hard_regno_nregs[32][mode];
25776 /* Moving between two similar registers is just one instruction. */
25777 else if (reg_classes_intersect_p (to, from))
25778 ret = (mode == TFmode || mode == TDmode) ? 4 : 2;
25780 /* Everything else has to go through GENERAL_REGS. */
25782 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
25783 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
25785 if (TARGET_DEBUG_COST)
25787 if (dbg_cost_ctrl == 1)
25789 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
25790 ret, GET_MODE_NAME (mode), reg_class_names[from],
25791 reg_class_names[to]);
25798 /* A C expressions returning the cost of moving data of MODE from a register to
25802 rs6000_memory_move_cost (enum machine_mode mode, reg_class_t rclass,
25803 bool in ATTRIBUTE_UNUSED)
25807 if (TARGET_DEBUG_COST)
25810 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
25811 ret = 4 * hard_regno_nregs[0][mode];
25812 else if (reg_classes_intersect_p (rclass, FLOAT_REGS))
25813 ret = 4 * hard_regno_nregs[32][mode];
25814 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
25815 ret = 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
25817 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
25819 if (TARGET_DEBUG_COST)
25821 if (dbg_cost_ctrl == 1)
25823 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
25824 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
25831 /* Returns a code for a target-specific builtin that implements
25832 reciprocal of the function, or NULL_TREE if not available. */
25835 rs6000_builtin_reciprocal (unsigned int fn, bool md_fn,
25836 bool sqrt ATTRIBUTE_UNUSED)
25838 if (optimize_insn_for_size_p ())
25844 case VSX_BUILTIN_XVSQRTDP:
25845 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
25848 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
25850 case VSX_BUILTIN_XVSQRTSP:
25851 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
25854 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
25863 case BUILT_IN_SQRT:
25864 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode))
25867 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRT];
25869 case BUILT_IN_SQRTF:
25870 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode))
25873 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRTF];
25880 /* Load up a constant. If the mode is a vector mode, splat the value across
25881 all of the vector elements. */
25884 rs6000_load_constant_and_splat (enum machine_mode mode, REAL_VALUE_TYPE dconst)
25888 if (mode == SFmode || mode == DFmode)
25890 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, mode);
25891 reg = force_reg (mode, d);
25893 else if (mode == V4SFmode)
25895 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, SFmode);
25896 rtvec v = gen_rtvec (4, d, d, d, d);
25897 reg = gen_reg_rtx (mode);
25898 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
25900 else if (mode == V2DFmode)
25902 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, DFmode);
25903 rtvec v = gen_rtvec (2, d, d);
25904 reg = gen_reg_rtx (mode);
25905 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
25908 gcc_unreachable ();
25913 /* Generate an FMA instruction. */
25916 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
25918 enum machine_mode mode = GET_MODE (target);
25921 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
25922 gcc_assert (dst != NULL);
25925 emit_move_insn (target, dst);
25928 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
25931 rs6000_emit_msub (rtx target, rtx m1, rtx m2, rtx a)
25933 enum machine_mode mode = GET_MODE (target);
25936 /* Altivec does not support fms directly;
25937 generate in terms of fma in that case. */
25938 if (optab_handler (fms_optab, mode) != CODE_FOR_nothing)
25939 dst = expand_ternary_op (mode, fms_optab, m1, m2, a, target, 0);
25942 a = expand_unop (mode, neg_optab, a, NULL_RTX, 0);
25943 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
25945 gcc_assert (dst != NULL);
25948 emit_move_insn (target, dst);
25951 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
25954 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
25956 enum machine_mode mode = GET_MODE (dst);
25959 /* This is a tad more complicated, since the fnma_optab is for
25960 a different expression: fma(-m1, m2, a), which is the same
25961 thing except in the case of signed zeros.
25963 Fortunately we know that if FMA is supported that FNMSUB is
25964 also supported in the ISA. Just expand it directly. */
25966 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
25968 r = gen_rtx_NEG (mode, a);
25969 r = gen_rtx_FMA (mode, m1, m2, r);
25970 r = gen_rtx_NEG (mode, r);
25971 emit_insn (gen_rtx_SET (VOIDmode, dst, r));
25974 /* Newton-Raphson approximation of floating point divide with just 2 passes
25975 (either single precision floating point, or newer machines with higher
25976 accuracy estimates). Support both scalar and vector divide. Assumes no
25977 trapping math and finite arguments. */
25980 rs6000_emit_swdiv_high_precision (rtx dst, rtx n, rtx d)
25982 enum machine_mode mode = GET_MODE (dst);
25983 rtx x0, e0, e1, y1, u0, v0;
25984 enum insn_code code = optab_handler (smul_optab, mode);
25985 gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
25986 rtx one = rs6000_load_constant_and_splat (mode, dconst1);
25988 gcc_assert (code != CODE_FOR_nothing);
25990 /* x0 = 1./d estimate */
25991 x0 = gen_reg_rtx (mode);
25992 emit_insn (gen_rtx_SET (VOIDmode, x0,
25993 gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
25996 e0 = gen_reg_rtx (mode);
25997 rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - (d * x0) */
25999 e1 = gen_reg_rtx (mode);
26000 rs6000_emit_madd (e1, e0, e0, e0); /* e1 = (e0 * e0) + e0 */
26002 y1 = gen_reg_rtx (mode);
26003 rs6000_emit_madd (y1, e1, x0, x0); /* y1 = (e1 * x0) + x0 */
26005 u0 = gen_reg_rtx (mode);
26006 emit_insn (gen_mul (u0, n, y1)); /* u0 = n * y1 */
26008 v0 = gen_reg_rtx (mode);
26009 rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - (d * u0) */
26011 rs6000_emit_madd (dst, v0, y1, u0); /* dst = (v0 * y1) + u0 */
26014 /* Newton-Raphson approximation of floating point divide that has a low
26015 precision estimate. Assumes no trapping math and finite arguments. */
26018 rs6000_emit_swdiv_low_precision (rtx dst, rtx n, rtx d)
26020 enum machine_mode mode = GET_MODE (dst);
26021 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
26022 enum insn_code code = optab_handler (smul_optab, mode);
26023 gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
26025 gcc_assert (code != CODE_FOR_nothing);
26027 one = rs6000_load_constant_and_splat (mode, dconst1);
26029 /* x0 = 1./d estimate */
26030 x0 = gen_reg_rtx (mode);
26031 emit_insn (gen_rtx_SET (VOIDmode, x0,
26032 gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
26035 e0 = gen_reg_rtx (mode);
26036 rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - d * x0 */
26038 y1 = gen_reg_rtx (mode);
26039 rs6000_emit_madd (y1, e0, x0, x0); /* y1 = x0 + e0 * x0 */
26041 e1 = gen_reg_rtx (mode);
26042 emit_insn (gen_mul (e1, e0, e0)); /* e1 = e0 * e0 */
26044 y2 = gen_reg_rtx (mode);
26045 rs6000_emit_madd (y2, e1, y1, y1); /* y2 = y1 + e1 * y1 */
26047 e2 = gen_reg_rtx (mode);
26048 emit_insn (gen_mul (e2, e1, e1)); /* e2 = e1 * e1 */
26050 y3 = gen_reg_rtx (mode);
26051 rs6000_emit_madd (y3, e2, y2, y2); /* y3 = y2 + e2 * y2 */
26053 u0 = gen_reg_rtx (mode);
26054 emit_insn (gen_mul (u0, n, y3)); /* u0 = n * y3 */
26056 v0 = gen_reg_rtx (mode);
26057 rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - d * u0 */
26059 rs6000_emit_madd (dst, v0, y3, u0); /* dst = u0 + v0 * y3 */
26062 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
26063 add a reg_note saying that this was a division. Support both scalar and
26064 vector divide. Assumes no trapping math and finite arguments. */
26067 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
26069 enum machine_mode mode = GET_MODE (dst);
26071 if (RS6000_RECIP_HIGH_PRECISION_P (mode))
26072 rs6000_emit_swdiv_high_precision (dst, n, d);
26074 rs6000_emit_swdiv_low_precision (dst, n, d);
26077 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
26080 /* Newton-Raphson approximation of single/double-precision floating point
26081 rsqrt. Assumes no trapping math and finite arguments. */
26084 rs6000_emit_swrsqrt (rtx dst, rtx src)
26086 enum machine_mode mode = GET_MODE (src);
26087 rtx x0 = gen_reg_rtx (mode);
26088 rtx y = gen_reg_rtx (mode);
26089 int passes = (TARGET_RECIP_PRECISION) ? 2 : 3;
26090 REAL_VALUE_TYPE dconst3_2;
26093 enum insn_code code = optab_handler (smul_optab, mode);
26094 gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
26096 gcc_assert (code != CODE_FOR_nothing);
26098 /* Load up the constant 1.5 either as a scalar, or as a vector. */
26099 real_from_integer (&dconst3_2, VOIDmode, 3, 0, 0);
26100 SET_REAL_EXP (&dconst3_2, REAL_EXP (&dconst3_2) - 1);
26102 halfthree = rs6000_load_constant_and_splat (mode, dconst3_2);
26104 /* x0 = rsqrt estimate */
26105 emit_insn (gen_rtx_SET (VOIDmode, x0,
26106 gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
26109 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
26110 rs6000_emit_msub (y, src, halfthree, src);
26112 for (i = 0; i < passes; i++)
26114 rtx x1 = gen_reg_rtx (mode);
26115 rtx u = gen_reg_rtx (mode);
26116 rtx v = gen_reg_rtx (mode);
26118 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
26119 emit_insn (gen_mul (u, x0, x0));
26120 rs6000_emit_nmsub (v, y, u, halfthree);
26121 emit_insn (gen_mul (x1, x0, v));
26125 emit_move_insn (dst, x0);
26129 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
26130 (Power7) targets. DST is the target, and SRC is the argument operand. */
26133 rs6000_emit_popcount (rtx dst, rtx src)
26135 enum machine_mode mode = GET_MODE (dst);
26138 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
26139 if (TARGET_POPCNTD)
26141 if (mode == SImode)
26142 emit_insn (gen_popcntdsi2 (dst, src));
26144 emit_insn (gen_popcntddi2 (dst, src));
26148 tmp1 = gen_reg_rtx (mode);
26150 if (mode == SImode)
26152 emit_insn (gen_popcntbsi2 (tmp1, src));
26153 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
26155 tmp2 = force_reg (SImode, tmp2);
26156 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
26160 emit_insn (gen_popcntbdi2 (tmp1, src));
26161 tmp2 = expand_mult (DImode, tmp1,
26162 GEN_INT ((HOST_WIDE_INT)
26163 0x01010101 << 32 | 0x01010101),
26165 tmp2 = force_reg (DImode, tmp2);
26166 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
26171 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
26172 target, and SRC is the argument operand. */
26175 rs6000_emit_parity (rtx dst, rtx src)
26177 enum machine_mode mode = GET_MODE (dst);
26180 tmp = gen_reg_rtx (mode);
26182 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
26185 if (mode == SImode)
26187 emit_insn (gen_popcntbsi2 (tmp, src));
26188 emit_insn (gen_paritysi2_cmpb (dst, tmp));
26192 emit_insn (gen_popcntbdi2 (tmp, src));
26193 emit_insn (gen_paritydi2_cmpb (dst, tmp));
26198 if (mode == SImode)
26200 /* Is mult+shift >= shift+xor+shift+xor? */
26201 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
26203 rtx tmp1, tmp2, tmp3, tmp4;
26205 tmp1 = gen_reg_rtx (SImode);
26206 emit_insn (gen_popcntbsi2 (tmp1, src));
26208 tmp2 = gen_reg_rtx (SImode);
26209 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
26210 tmp3 = gen_reg_rtx (SImode);
26211 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
26213 tmp4 = gen_reg_rtx (SImode);
26214 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
26215 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
26218 rs6000_emit_popcount (tmp, src);
26219 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
26223 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
26224 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
26226 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
26228 tmp1 = gen_reg_rtx (DImode);
26229 emit_insn (gen_popcntbdi2 (tmp1, src));
26231 tmp2 = gen_reg_rtx (DImode);
26232 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
26233 tmp3 = gen_reg_rtx (DImode);
26234 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
26236 tmp4 = gen_reg_rtx (DImode);
26237 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
26238 tmp5 = gen_reg_rtx (DImode);
26239 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
26241 tmp6 = gen_reg_rtx (DImode);
26242 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
26243 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
26246 rs6000_emit_popcount (tmp, src);
26247 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
26251 /* Expand an Altivec constant permutation. Return true if we match
26252 an efficient implementation; false to fall back to VPERM. */
26255 altivec_expand_vec_perm_const (rtx operands[4])
26257 struct altivec_perm_insn {
26258 enum insn_code impl;
26259 unsigned char perm[16];
26261 static const struct altivec_perm_insn patterns[] = {
26262 { CODE_FOR_altivec_vpkuhum,
26263 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
26264 { CODE_FOR_altivec_vpkuwum,
26265 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
26266 { CODE_FOR_altivec_vmrghb,
26267 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
26268 { CODE_FOR_altivec_vmrghh,
26269 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
26270 { CODE_FOR_altivec_vmrghw,
26271 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
26272 { CODE_FOR_altivec_vmrglb,
26273 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
26274 { CODE_FOR_altivec_vmrglh,
26275 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
26276 { CODE_FOR_altivec_vmrglw,
26277 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } }
26280 unsigned int i, j, elt, which;
26281 unsigned char perm[16];
26282 rtx target, op0, op1, sel, x;
26285 target = operands[0];
26290 /* Unpack the constant selector. */
26291 for (i = which = 0; i < 16; ++i)
26293 rtx e = XVECEXP (sel, 0, i);
26294 elt = INTVAL (e) & 31;
26295 which |= (elt < 16 ? 1 : 2);
26299 /* Simplify the constant selector based on operands. */
26303 gcc_unreachable ();
26307 if (!rtx_equal_p (op0, op1))
26312 for (i = 0; i < 16; ++i)
26324 /* Look for splat patterns. */
26329 for (i = 0; i < 16; ++i)
26330 if (perm[i] != elt)
26334 emit_insn (gen_altivec_vspltb (target, op0, GEN_INT (elt)));
26340 for (i = 0; i < 16; i += 2)
26341 if (perm[i] != elt || perm[i + 1] != elt + 1)
26345 x = gen_reg_rtx (V8HImode);
26346 emit_insn (gen_altivec_vsplth (x, gen_lowpart (V8HImode, op0),
26347 GEN_INT (elt / 2)));
26348 emit_move_insn (target, gen_lowpart (V16QImode, x));
26355 for (i = 0; i < 16; i += 4)
26357 || perm[i + 1] != elt + 1
26358 || perm[i + 2] != elt + 2
26359 || perm[i + 3] != elt + 3)
26363 x = gen_reg_rtx (V4SImode);
26364 emit_insn (gen_altivec_vspltw (x, gen_lowpart (V4SImode, op0),
26365 GEN_INT (elt / 4)));
26366 emit_move_insn (target, gen_lowpart (V16QImode, x));
26372 /* Look for merge and pack patterns. */
26373 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
26377 elt = patterns[j].perm[0];
26378 if (perm[0] == elt)
26380 else if (perm[0] == elt + 16)
26384 for (i = 1; i < 16; ++i)
26386 elt = patterns[j].perm[i];
26388 elt = (elt >= 16 ? elt - 16 : elt + 16);
26389 else if (one_vec && elt >= 16)
26391 if (perm[i] != elt)
26396 enum insn_code icode = patterns[j].impl;
26397 enum machine_mode omode = insn_data[icode].operand[0].mode;
26398 enum machine_mode imode = insn_data[icode].operand[1].mode;
26401 x = op0, op0 = op1, op1 = x;
26402 if (imode != V16QImode)
26404 op0 = gen_lowpart (imode, op0);
26405 op1 = gen_lowpart (imode, op1);
26407 if (omode == V16QImode)
26410 x = gen_reg_rtx (omode);
26411 emit_insn (GEN_FCN (icode) (x, op0, op1));
26412 if (omode != V16QImode)
26413 emit_move_insn (target, gen_lowpart (V16QImode, x));
26421 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
26422 Return true if we match an efficient implementation. */
26425 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
26426 unsigned char perm0, unsigned char perm1)
26430 /* If both selectors come from the same operand, fold to single op. */
26431 if ((perm0 & 2) == (perm1 & 2))
26438 /* If both operands are equal, fold to simpler permutation. */
26439 if (rtx_equal_p (op0, op1))
26442 perm1 = (perm1 & 1) + 2;
26444 /* If the first selector comes from the second operand, swap. */
26445 else if (perm0 & 2)
26451 x = op0, op0 = op1, op1 = x;
26453 /* If the second selector does not come from the second operand, fail. */
26454 else if ((perm1 & 2) == 0)
26458 if (target != NULL)
26460 enum machine_mode vmode, dmode;
26463 vmode = GET_MODE (target);
26464 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
26465 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4);
26467 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
26468 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
26469 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
26470 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26476 rs6000_expand_vec_perm_const (rtx operands[4])
26478 rtx target, op0, op1, sel;
26479 unsigned char perm0, perm1;
26481 target = operands[0];
26486 /* Unpack the constant selector. */
26487 perm0 = INTVAL (XVECEXP (sel, 0, 0)) & 3;
26488 perm1 = INTVAL (XVECEXP (sel, 0, 1)) & 3;
26490 return rs6000_expand_vec_perm_const_1 (target, op0, op1, perm0, perm1);
26493 /* Test whether a constant permutation is supported. */
26496 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode,
26497 const unsigned char *sel)
26499 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
26500 if (TARGET_ALTIVEC)
26503 /* Check for ps_merge* or evmerge* insns. */
26504 if ((TARGET_PAIRED_FLOAT && vmode == V2SFmode)
26505 || (TARGET_SPE && vmode == V2SImode))
26507 rtx op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
26508 rtx op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
26509 return rs6000_expand_vec_perm_const_1 (NULL, op0, op1, sel[0], sel[1]);
26515 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
26518 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
26519 enum machine_mode vmode, unsigned nelt, rtx perm[])
26521 enum machine_mode imode;
26525 if (GET_MODE_CLASS (vmode) != MODE_VECTOR_INT)
26527 imode = GET_MODE_INNER (vmode);
26528 imode = mode_for_size (GET_MODE_BITSIZE (imode), MODE_INT, 0);
26529 imode = mode_for_vector (imode, nelt);
26532 x = gen_rtx_CONST_VECTOR (imode, gen_rtvec_v (nelt, perm));
26533 x = expand_vec_perm (vmode, op0, op1, x, target);
26535 emit_move_insn (target, x);
26538 /* Expand an extract even operation. */
26541 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
26543 enum machine_mode vmode = GET_MODE (target);
26544 unsigned i, nelt = GET_MODE_NUNITS (vmode);
26547 for (i = 0; i < nelt; i++)
26548 perm[i] = GEN_INT (i * 2);
26550 rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
26553 /* Expand a vector interleave operation. */
26556 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
26558 enum machine_mode vmode = GET_MODE (target);
26559 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
26562 high = (highp == BYTES_BIG_ENDIAN ? 0 : nelt / 2);
26563 for (i = 0; i < nelt / 2; i++)
26565 perm[i * 2] = GEN_INT (i + high);
26566 perm[i * 2 + 1] = GEN_INT (i + nelt + high);
26569 rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
26572 /* Return an RTX representing where to find the function value of a
26573 function returning MODE. */
26575 rs6000_complex_function_value (enum machine_mode mode)
26577 unsigned int regno;
26579 enum machine_mode inner = GET_MODE_INNER (mode);
26580 unsigned int inner_bytes = GET_MODE_SIZE (inner);
26582 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
26583 regno = FP_ARG_RETURN;
26586 regno = GP_ARG_RETURN;
26588 /* 32-bit is OK since it'll go in r3/r4. */
26589 if (TARGET_32BIT && inner_bytes >= 4)
26590 return gen_rtx_REG (mode, regno);
26593 if (inner_bytes >= 8)
26594 return gen_rtx_REG (mode, regno);
26596 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
26598 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
26599 GEN_INT (inner_bytes));
26600 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
26603 /* Target hook for TARGET_FUNCTION_VALUE.
26605 On the SPE, both FPs and vectors are returned in r3.
26607 On RS/6000 an integer value is in r3 and a floating-point value is in
26608 fp1, unless -msoft-float. */
26611 rs6000_function_value (const_tree valtype,
26612 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
26613 bool outgoing ATTRIBUTE_UNUSED)
26615 enum machine_mode mode;
26616 unsigned int regno;
26618 /* Special handling for structs in darwin64. */
26620 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
26622 CUMULATIVE_ARGS valcum;
26626 valcum.fregno = FP_ARG_MIN_REG;
26627 valcum.vregno = ALTIVEC_ARG_MIN_REG;
26628 /* Do a trial code generation as if this were going to be passed as
26629 an argument; if any part goes in memory, we return NULL. */
26630 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
26633 /* Otherwise fall through to standard ABI rules. */
26636 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
26638 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
26639 return gen_rtx_PARALLEL (DImode,
26641 gen_rtx_EXPR_LIST (VOIDmode,
26642 gen_rtx_REG (SImode, GP_ARG_RETURN),
26644 gen_rtx_EXPR_LIST (VOIDmode,
26645 gen_rtx_REG (SImode,
26646 GP_ARG_RETURN + 1),
26649 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
26651 return gen_rtx_PARALLEL (DCmode,
26653 gen_rtx_EXPR_LIST (VOIDmode,
26654 gen_rtx_REG (SImode, GP_ARG_RETURN),
26656 gen_rtx_EXPR_LIST (VOIDmode,
26657 gen_rtx_REG (SImode,
26658 GP_ARG_RETURN + 1),
26660 gen_rtx_EXPR_LIST (VOIDmode,
26661 gen_rtx_REG (SImode,
26662 GP_ARG_RETURN + 2),
26664 gen_rtx_EXPR_LIST (VOIDmode,
26665 gen_rtx_REG (SImode,
26666 GP_ARG_RETURN + 3),
26670 mode = TYPE_MODE (valtype);
26671 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
26672 || POINTER_TYPE_P (valtype))
26673 mode = TARGET_32BIT ? SImode : DImode;
26675 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
26676 /* _Decimal128 must use an even/odd register pair. */
26677 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
26678 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS
26679 && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
26680 regno = FP_ARG_RETURN;
26681 else if (TREE_CODE (valtype) == COMPLEX_TYPE
26682 && targetm.calls.split_complex_arg)
26683 return rs6000_complex_function_value (mode);
26684 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
26685 return register is used in both cases, and we won't see V2DImode/V2DFmode
26686 for pure altivec, combine the two cases. */
26687 else if (TREE_CODE (valtype) == VECTOR_TYPE
26688 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
26689 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
26690 regno = ALTIVEC_ARG_RETURN;
26691 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
26692 && (mode == DFmode || mode == DCmode
26693 || mode == TFmode || mode == TCmode))
26694 return spe_build_register_parallel (mode, GP_ARG_RETURN);
26696 regno = GP_ARG_RETURN;
26698 return gen_rtx_REG (mode, regno);
26701 /* Define how to find the value returned by a library function
26702 assuming the value has mode MODE. */
26704 rs6000_libcall_value (enum machine_mode mode)
26706 unsigned int regno;
26708 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
26710 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
26711 return gen_rtx_PARALLEL (DImode,
26713 gen_rtx_EXPR_LIST (VOIDmode,
26714 gen_rtx_REG (SImode, GP_ARG_RETURN),
26716 gen_rtx_EXPR_LIST (VOIDmode,
26717 gen_rtx_REG (SImode,
26718 GP_ARG_RETURN + 1),
26722 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
26723 /* _Decimal128 must use an even/odd register pair. */
26724 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
26725 else if (SCALAR_FLOAT_MODE_P (mode)
26726 && TARGET_HARD_FLOAT && TARGET_FPRS
26727 && ((TARGET_SINGLE_FLOAT && mode == SFmode) || TARGET_DOUBLE_FLOAT))
26728 regno = FP_ARG_RETURN;
26729 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
26730 return register is used in both cases, and we won't see V2DImode/V2DFmode
26731 for pure altivec, combine the two cases. */
26732 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
26733 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
26734 regno = ALTIVEC_ARG_RETURN;
26735 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
26736 return rs6000_complex_function_value (mode);
26737 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
26738 && (mode == DFmode || mode == DCmode
26739 || mode == TFmode || mode == TCmode))
26740 return spe_build_register_parallel (mode, GP_ARG_RETURN);
26742 regno = GP_ARG_RETURN;
26744 return gen_rtx_REG (mode, regno);
26748 /* Given FROM and TO register numbers, say whether this elimination is allowed.
26749 Frame pointer elimination is automatically handled.
26751 For the RS/6000, if frame pointer elimination is being done, we would like
26752 to convert ap into fp, not sp.
26754 We need r30 if -mminimal-toc was specified, and there are constant pool
26758 rs6000_can_eliminate (const int from, const int to)
26760 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
26761 ? ! frame_pointer_needed
26762 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
26763 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0
26767 /* Define the offset between two registers, FROM to be eliminated and its
26768 replacement TO, at the start of a routine. */
26770 rs6000_initial_elimination_offset (int from, int to)
26772 rs6000_stack_t *info = rs6000_stack_info ();
26773 HOST_WIDE_INT offset;
26775 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
26776 offset = info->push_p ? 0 : -info->total_size;
26777 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
26779 offset = info->push_p ? 0 : -info->total_size;
26780 if (FRAME_GROWS_DOWNWARD)
26781 offset += info->fixed_size + info->vars_size + info->parm_size;
26783 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
26784 offset = FRAME_GROWS_DOWNWARD
26785 ? info->fixed_size + info->vars_size + info->parm_size
26787 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
26788 offset = info->total_size;
26789 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
26790 offset = info->push_p ? info->total_size : 0;
26791 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
26794 gcc_unreachable ();
26800 rs6000_dwarf_register_span (rtx reg)
26804 unsigned regno = REGNO (reg);
26805 enum machine_mode mode = GET_MODE (reg);
26809 && (SPE_VECTOR_MODE (GET_MODE (reg))
26810 || (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode)
26811 && mode != SFmode && mode != SDmode && mode != SCmode)))
26816 regno = REGNO (reg);
26818 /* The duality of the SPE register size wreaks all kinds of havoc.
26819 This is a way of distinguishing r0 in 32-bits from r0 in
26821 words = (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
26822 gcc_assert (words <= 4);
26823 for (i = 0; i < words; i++, regno++)
26825 if (BYTES_BIG_ENDIAN)
26827 parts[2 * i] = gen_rtx_REG (SImode, regno + 1200);
26828 parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
26832 parts[2 * i] = gen_rtx_REG (SImode, regno);
26833 parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200);
26837 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (words * 2, parts));
26840 /* Fill in sizes for SPE register high parts in table used by unwinder. */
26843 rs6000_init_dwarf_reg_sizes_extra (tree address)
26848 enum machine_mode mode = TYPE_MODE (char_type_node);
26849 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
26850 rtx mem = gen_rtx_MEM (BLKmode, addr);
26851 rtx value = gen_int_mode (4, mode);
26853 for (i = 1201; i < 1232; i++)
26855 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
26856 HOST_WIDE_INT offset
26857 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
26859 emit_move_insn (adjust_address (mem, mode, offset), value);
26864 /* Map internal gcc register numbers to DWARF2 register numbers. */
26867 rs6000_dbx_register_number (unsigned int regno)
26869 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
26871 if (regno == MQ_REGNO)
26873 if (regno == LR_REGNO)
26875 if (regno == CTR_REGNO)
26877 if (CR_REGNO_P (regno))
26878 return regno - CR0_REGNO + 86;
26879 if (regno == CA_REGNO)
26880 return 101; /* XER */
26881 if (ALTIVEC_REGNO_P (regno))
26882 return regno - FIRST_ALTIVEC_REGNO + 1124;
26883 if (regno == VRSAVE_REGNO)
26885 if (regno == VSCR_REGNO)
26887 if (regno == SPE_ACC_REGNO)
26889 if (regno == SPEFSCR_REGNO)
26891 /* SPE high reg number. We get these values of regno from
26892 rs6000_dwarf_register_span. */
26893 gcc_assert (regno >= 1200 && regno < 1232);
26897 /* target hook eh_return_filter_mode */
26898 static enum machine_mode
26899 rs6000_eh_return_filter_mode (void)
26901 return TARGET_32BIT ? SImode : word_mode;
26904 /* Target hook for scalar_mode_supported_p. */
26906 rs6000_scalar_mode_supported_p (enum machine_mode mode)
26908 if (DECIMAL_FLOAT_MODE_P (mode))
26909 return default_decimal_float_supported_p ();
26911 return default_scalar_mode_supported_p (mode);
26914 /* Target hook for vector_mode_supported_p. */
26916 rs6000_vector_mode_supported_p (enum machine_mode mode)
26919 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
26922 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
26925 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
26932 /* Target hook for invalid_arg_for_unprototyped_fn. */
26933 static const char *
26934 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
26936 return (!rs6000_darwin64_abi
26938 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
26939 && (funcdecl == NULL_TREE
26940 || (TREE_CODE (funcdecl) == FUNCTION_DECL
26941 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
26942 ? N_("AltiVec argument passed to unprototyped function")
26946 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
26947 setup by using __stack_chk_fail_local hidden function instead of
26948 calling __stack_chk_fail directly. Otherwise it is better to call
26949 __stack_chk_fail directly. */
26951 static tree ATTRIBUTE_UNUSED
26952 rs6000_stack_protect_fail (void)
26954 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
26955 ? default_hidden_stack_protect_fail ()
26956 : default_external_stack_protect_fail ();
26960 rs6000_final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
26961 int num_operands ATTRIBUTE_UNUSED)
26963 if (rs6000_warn_cell_microcode)
26966 int insn_code_number = recog_memoized (insn);
26967 location_t location = locator_location (INSN_LOCATOR (insn));
26969 /* Punt on insns we cannot recognize. */
26970 if (insn_code_number < 0)
26973 temp = get_insn_template (insn_code_number, insn);
26975 if (get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS)
26976 warning_at (location, OPT_mwarn_cell_microcode,
26977 "emitting microcode insn %s\t[%s] #%d",
26978 temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
26979 else if (get_attr_cell_micro (insn) == CELL_MICRO_CONDITIONAL)
26980 warning_at (location, OPT_mwarn_cell_microcode,
26981 "emitting conditional microcode insn %s\t[%s] #%d",
26982 temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
26987 /* Mask options that we want to support inside of attribute((target)) and
26988 #pragma GCC target operations. Note, we do not include things like
26989 64/32-bit, endianess, hard/soft floating point, etc. that would have
26990 different calling sequences. */
26992 struct rs6000_opt_mask {
26993 const char *name; /* option name */
26994 int mask; /* mask to set */
26995 bool invert; /* invert sense of mask */
26996 bool valid_target; /* option is a target option */
26999 static struct rs6000_opt_mask const rs6000_opt_masks[] =
27001 { "altivec", MASK_ALTIVEC, false, true },
27002 { "cmpb", MASK_CMPB, false, true },
27003 { "dlmzb", MASK_DLMZB, false, true },
27004 { "fprnd", MASK_FPRND, false, true },
27005 { "hard-dfp", MASK_DFP, false, true },
27006 { "isel", MASK_ISEL, false, true },
27007 { "mfcrf", MASK_MFCRF, false, true },
27008 { "mfpgpr", MASK_MFPGPR, false, true },
27009 { "mulhw", MASK_MULHW, false, true },
27010 { "multiple", MASK_MULTIPLE, false, true },
27011 { "update", MASK_NO_UPDATE, true , true },
27012 { "popcntb", MASK_POPCNTB, false, true },
27013 { "popcntd", MASK_POPCNTD, false, true },
27014 { "powerpc-gfxopt", MASK_PPC_GFXOPT, false, true },
27015 { "powerpc-gpopt", MASK_PPC_GPOPT, false, true },
27016 { "recip-precision", MASK_RECIP_PRECISION, false, true },
27017 { "string", MASK_STRING, false, true },
27018 { "vsx", MASK_VSX, false, true },
27021 { "aix64", MASK_64BIT, false, false },
27022 { "aix32", MASK_64BIT, true, false },
27024 { "64", MASK_64BIT, false, false },
27025 { "32", MASK_64BIT, true, false },
27029 { "eabi", MASK_EABI, false, false },
27031 #ifdef MASK_LITTLE_ENDIAN
27032 { "little", MASK_LITTLE_ENDIAN, false, false },
27033 { "big", MASK_LITTLE_ENDIAN, true, false },
27035 #ifdef MASK_RELOCATABLE
27036 { "relocatable", MASK_RELOCATABLE, false, false },
27038 #ifdef MASK_STRICT_ALIGN
27039 { "strict-align", MASK_STRICT_ALIGN, false, false },
27041 { "power", MASK_POWER, false, false },
27042 { "power2", MASK_POWER2, false, false },
27043 { "powerpc", MASK_POWERPC, false, false },
27044 { "soft-float", MASK_SOFT_FLOAT, false, false },
27045 { "string", MASK_STRING, false, false },
27048 /* Builtin mask mapping for printing the flags. */
27049 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
27051 { "altivec", RS6000_BTM_ALTIVEC, false, false },
27052 { "vsx", RS6000_BTM_VSX, false, false },
27053 { "spe", RS6000_BTM_SPE, false, false },
27054 { "paired", RS6000_BTM_PAIRED, false, false },
27055 { "fre", RS6000_BTM_FRE, false, false },
27056 { "fres", RS6000_BTM_FRES, false, false },
27057 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
27058 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
27059 { "popcntd", RS6000_BTM_POPCNTD, false, false },
27060 { "powerpc", RS6000_BTM_POWERPC, false, false },
27061 { "cell", RS6000_BTM_CELL, false, false },
27064 /* Option variables that we want to support inside attribute((target)) and
27065 #pragma GCC target operations. */
27067 struct rs6000_opt_var {
27068 const char *name; /* option name */
27069 size_t global_offset; /* offset of the option in global_options. */
27070 size_t target_offset; /* offset of the option in target optiosn. */
27073 static struct rs6000_opt_var const rs6000_opt_vars[] =
27076 offsetof (struct gcc_options, x_TARGET_FRIZ),
27077 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
27078 { "avoid-indexed-addresses",
27079 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
27080 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
27082 offsetof (struct gcc_options, x_rs6000_paired_float),
27083 offsetof (struct cl_target_option, x_rs6000_paired_float), },
27085 offsetof (struct gcc_options, x_rs6000_default_long_calls),
27086 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
27089 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
27090 parsing. Return true if there were no errors. */
27093 rs6000_inner_target_options (tree args, bool attr_p)
27097 if (args == NULL_TREE)
27100 else if (TREE_CODE (args) == STRING_CST)
27102 char *p = ASTRDUP (TREE_STRING_POINTER (args));
27105 while ((q = strtok (p, ",")) != NULL)
27107 bool error_p = false;
27108 bool not_valid_p = false;
27109 const char *cpu_opt = NULL;
27112 if (strncmp (q, "cpu=", 4) == 0)
27114 int cpu_index = rs6000_cpu_name_lookup (q+4);
27115 if (cpu_index >= 0)
27116 rs6000_cpu_index = cpu_index;
27123 else if (strncmp (q, "tune=", 5) == 0)
27125 int tune_index = rs6000_cpu_name_lookup (q+5);
27126 if (tune_index >= 0)
27127 rs6000_tune_index = tune_index;
27137 bool invert = false;
27141 if (strncmp (r, "no-", 3) == 0)
27147 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
27148 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
27150 int mask = rs6000_opt_masks[i].mask;
27152 if (!rs6000_opt_masks[i].valid_target)
27153 not_valid_p = true;
27157 target_flags_explicit |= mask;
27159 /* VSX needs altivec, so -mvsx automagically sets
27161 if (mask == MASK_VSX && !invert)
27162 mask |= MASK_ALTIVEC;
27164 if (rs6000_opt_masks[i].invert)
27168 target_flags &= ~mask;
27170 target_flags |= mask;
27175 if (error_p && !not_valid_p)
27177 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
27178 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
27180 size_t j = rs6000_opt_vars[i].global_offset;
27181 *((int *) ((char *)&global_options + j)) = !invert;
27190 const char *eprefix, *esuffix;
27195 eprefix = "__attribute__((__target__(";
27200 eprefix = "#pragma GCC target ";
27205 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt, eprefix,
27207 else if (not_valid_p)
27208 error ("%s\"%s\"%s is not allowed", eprefix, q, esuffix);
27210 error ("%s\"%s\"%s is invalid", eprefix, q, esuffix);
27215 else if (TREE_CODE (args) == TREE_LIST)
27219 tree value = TREE_VALUE (args);
27222 bool ret2 = rs6000_inner_target_options (value, attr_p);
27226 args = TREE_CHAIN (args);
27228 while (args != NULL_TREE);
27232 gcc_unreachable ();
27237 /* Print out the target options as a list for -mdebug=target. */
27240 rs6000_debug_target_options (tree args, const char *prefix)
27242 if (args == NULL_TREE)
27243 fprintf (stderr, "%s<NULL>", prefix);
27245 else if (TREE_CODE (args) == STRING_CST)
27247 char *p = ASTRDUP (TREE_STRING_POINTER (args));
27250 while ((q = strtok (p, ",")) != NULL)
27253 fprintf (stderr, "%s\"%s\"", prefix, q);
27258 else if (TREE_CODE (args) == TREE_LIST)
27262 tree value = TREE_VALUE (args);
27265 rs6000_debug_target_options (value, prefix);
27268 args = TREE_CHAIN (args);
27270 while (args != NULL_TREE);
27274 gcc_unreachable ();
27280 /* Hook to validate attribute((target("..."))). */
27283 rs6000_valid_attribute_p (tree fndecl,
27284 tree ARG_UNUSED (name),
27288 struct cl_target_option cur_target;
27290 tree old_optimize = build_optimization_node ();
27291 tree new_target, new_optimize;
27292 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
27294 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
27296 if (TARGET_DEBUG_TARGET)
27298 tree tname = DECL_NAME (fndecl);
27299 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
27301 fprintf (stderr, "function: %.*s\n",
27302 (int) IDENTIFIER_LENGTH (tname),
27303 IDENTIFIER_POINTER (tname));
27305 fprintf (stderr, "function: unknown\n");
27307 fprintf (stderr, "args:");
27308 rs6000_debug_target_options (args, " ");
27309 fprintf (stderr, "\n");
27312 fprintf (stderr, "flags: 0x%x\n", flags);
27314 fprintf (stderr, "--------------------\n");
27317 old_optimize = build_optimization_node ();
27318 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
27320 /* If the function changed the optimization levels as well as setting target
27321 options, start with the optimizations specified. */
27322 if (func_optimize && func_optimize != old_optimize)
27323 cl_optimization_restore (&global_options,
27324 TREE_OPTIMIZATION (func_optimize));
27326 /* The target attributes may also change some optimization flags, so update
27327 the optimization options if necessary. */
27328 cl_target_option_save (&cur_target, &global_options);
27329 rs6000_cpu_index = rs6000_tune_index = -1;
27330 ret = rs6000_inner_target_options (args, true);
27332 /* Set up any additional state. */
27335 ret = rs6000_option_override_internal (false);
27336 new_target = build_target_option_node ();
27341 new_optimize = build_optimization_node ();
27348 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
27350 if (old_optimize != new_optimize)
27351 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
27354 cl_target_option_restore (&global_options, &cur_target);
27356 if (old_optimize != new_optimize)
27357 cl_optimization_restore (&global_options,
27358 TREE_OPTIMIZATION (old_optimize));
27364 /* Hook to validate the current #pragma GCC target and set the state, and
27365 update the macros based on what was changed. If ARGS is NULL, then
27366 POP_TARGET is used to reset the options. */
27369 rs6000_pragma_target_parse (tree args, tree pop_target)
27371 tree prev_tree = build_target_option_node ();
27373 struct cl_target_option *prev_opt, *cur_opt;
27374 unsigned prev_bumask, cur_bumask, diff_bumask;
27375 int prev_flags, cur_flags, diff_flags;
27377 if (TARGET_DEBUG_TARGET)
27379 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
27380 fprintf (stderr, "args:");
27381 rs6000_debug_target_options (args, " ");
27382 fprintf (stderr, "\n");
27386 fprintf (stderr, "pop_target:\n");
27387 debug_tree (pop_target);
27390 fprintf (stderr, "pop_target: <NULL>\n");
27392 fprintf (stderr, "--------------------\n");
27397 cur_tree = ((pop_target)
27399 : target_option_default_node);
27400 cl_target_option_restore (&global_options,
27401 TREE_TARGET_OPTION (cur_tree));
27405 rs6000_cpu_index = rs6000_tune_index = -1;
27406 if (!rs6000_inner_target_options (args, false)
27407 || !rs6000_option_override_internal (false)
27408 || (cur_tree = build_target_option_node ()) == NULL_TREE)
27410 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
27411 fprintf (stderr, "invalid pragma\n");
27417 target_option_current_node = cur_tree;
27419 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
27420 change the macros that are defined. */
27421 if (rs6000_target_modify_macros_ptr)
27423 prev_opt = TREE_TARGET_OPTION (prev_tree);
27424 prev_bumask = prev_opt->x_rs6000_builtin_mask;
27425 prev_flags = prev_opt->x_target_flags;
27427 cur_opt = TREE_TARGET_OPTION (cur_tree);
27428 cur_flags = cur_opt->x_target_flags;
27429 cur_bumask = cur_opt->x_rs6000_builtin_mask;
27431 diff_bumask = (prev_bumask ^ cur_bumask);
27432 diff_flags = (prev_flags ^ cur_flags);
27434 if ((diff_flags != 0) || (diff_bumask != 0))
27436 /* Delete old macros. */
27437 rs6000_target_modify_macros_ptr (false,
27438 prev_flags & diff_flags,
27439 prev_bumask & diff_bumask);
27441 /* Define new macros. */
27442 rs6000_target_modify_macros_ptr (true,
27443 cur_flags & diff_flags,
27444 cur_bumask & diff_bumask);
27452 /* Remember the last target of rs6000_set_current_function. */
27453 static GTY(()) tree rs6000_previous_fndecl;
27455 /* Establish appropriate back-end context for processing the function
27456 FNDECL. The argument might be NULL to indicate processing at top
27457 level, outside of any function scope. */
27459 rs6000_set_current_function (tree fndecl)
27461 tree old_tree = (rs6000_previous_fndecl
27462 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl)
27465 tree new_tree = (fndecl
27466 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
27469 if (TARGET_DEBUG_TARGET)
27471 bool print_final = false;
27472 fprintf (stderr, "\n==================== rs6000_set_current_function");
27475 fprintf (stderr, ", fndecl %s (%p)",
27476 (DECL_NAME (fndecl)
27477 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
27478 : "<unknown>"), (void *)fndecl);
27480 if (rs6000_previous_fndecl)
27481 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
27483 fprintf (stderr, "\n");
27486 fprintf (stderr, "\nnew fndecl target specific options:\n");
27487 debug_tree (new_tree);
27488 print_final = true;
27493 fprintf (stderr, "\nold fndecl target specific options:\n");
27494 debug_tree (old_tree);
27495 print_final = true;
27499 fprintf (stderr, "--------------------\n");
27502 /* Only change the context if the function changes. This hook is called
27503 several times in the course of compiling a function, and we don't want to
27504 slow things down too much or call target_reinit when it isn't safe. */
27505 if (fndecl && fndecl != rs6000_previous_fndecl)
27507 rs6000_previous_fndecl = fndecl;
27508 if (old_tree == new_tree)
27513 cl_target_option_restore (&global_options,
27514 TREE_TARGET_OPTION (new_tree));
27520 struct cl_target_option *def
27521 = TREE_TARGET_OPTION (target_option_current_node);
27523 cl_target_option_restore (&global_options, def);
27530 /* Save the current options */
27533 rs6000_function_specific_save (struct cl_target_option *ptr)
27535 ptr->rs6000_target_flags_explicit = target_flags_explicit;
27538 /* Restore the current options */
27541 rs6000_function_specific_restore (struct cl_target_option *ptr)
27543 target_flags_explicit = ptr->rs6000_target_flags_explicit;
27544 (void) rs6000_option_override_internal (false);
27547 /* Print the current options */
27550 rs6000_function_specific_print (FILE *file, int indent,
27551 struct cl_target_option *ptr)
27554 int flags = ptr->x_target_flags;
27555 unsigned bu_mask = ptr->x_rs6000_builtin_mask;
27557 /* Print the various mask options. */
27558 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
27559 if ((flags & rs6000_opt_masks[i].mask) != 0)
27561 flags &= ~ rs6000_opt_masks[i].mask;
27562 fprintf (file, "%*s-m%s%s\n", indent, "",
27563 rs6000_opt_masks[i].invert ? "no-" : "",
27564 rs6000_opt_masks[i].name);
27567 /* Print the various options that are variables. */
27568 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
27570 size_t j = rs6000_opt_vars[i].target_offset;
27571 if (((signed char *) ptr)[j])
27572 fprintf (file, "%*s-m%s\n", indent, "",
27573 rs6000_opt_vars[i].name);
27576 /* Print the various builtin flags. */
27577 fprintf (file, "%*sbuiltin mask = 0x%x\n", indent, "", bu_mask);
27578 for (i = 0; i < ARRAY_SIZE (rs6000_builtin_mask_names); i++)
27579 if ((bu_mask & rs6000_builtin_mask_names[i].mask) != 0)
27581 fprintf (file, "%*s%s builtins supported\n", indent, "",
27582 rs6000_builtin_mask_names[i].name);
27587 /* Hook to determine if one function can safely inline another. */
27590 rs6000_can_inline_p (tree caller, tree callee)
27593 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
27594 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
27596 /* If callee has no option attributes, then it is ok to inline. */
27600 /* If caller has no option attributes, but callee does then it is not ok to
27602 else if (!caller_tree)
27607 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
27608 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
27610 /* Callee's options should a subset of the caller's, i.e. a vsx function
27611 can inline an altivec function but a non-vsx function can't inline a
27613 if ((caller_opts->x_target_flags & callee_opts->x_target_flags)
27614 == callee_opts->x_target_flags)
27618 if (TARGET_DEBUG_TARGET)
27619 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
27620 (DECL_NAME (caller)
27621 ? IDENTIFIER_POINTER (DECL_NAME (caller))
27623 (DECL_NAME (callee)
27624 ? IDENTIFIER_POINTER (DECL_NAME (callee))
27626 (ret ? "can" : "cannot"));
27631 /* Allocate a stack temp and fixup the address so it meets the particular
27632 memory requirements (either offetable or REG+REG addressing). */
27635 rs6000_allocate_stack_temp (enum machine_mode mode,
27636 bool offsettable_p,
27639 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
27640 rtx addr = XEXP (stack, 0);
27641 int strict_p = (reload_in_progress || reload_completed);
27643 if (!legitimate_indirect_address_p (addr, strict_p))
27646 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p))
27647 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
27649 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
27650 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
27656 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
27657 to such a form to deal with memory reference instructions like STFIWX that
27658 only take reg+reg addressing. */
27661 rs6000_address_for_fpconvert (rtx x)
27663 int strict_p = (reload_in_progress || reload_completed);
27666 gcc_assert (MEM_P (x));
27667 addr = XEXP (x, 0);
27668 if (! legitimate_indirect_address_p (addr, strict_p)
27669 && ! legitimate_indexed_address_p (addr, strict_p))
27671 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
27673 rtx reg = XEXP (addr, 0);
27674 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
27675 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
27676 gcc_assert (REG_P (reg));
27677 emit_insn (gen_add3_insn (reg, reg, size_rtx));
27680 else if (GET_CODE (addr) == PRE_MODIFY)
27682 rtx reg = XEXP (addr, 0);
27683 rtx expr = XEXP (addr, 1);
27684 gcc_assert (REG_P (reg));
27685 gcc_assert (GET_CODE (expr) == PLUS);
27686 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
27690 x = replace_equiv_address (x, copy_addr_to_reg (addr));
27696 /* Given a memory reference, if it is not in the form for altivec memory
27697 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
27698 convert to the altivec format. */
27701 rs6000_address_for_altivec (rtx x)
27703 gcc_assert (MEM_P (x));
27704 if (!altivec_indexed_or_indirect_operand (x, GET_MODE (x)))
27706 rtx addr = XEXP (x, 0);
27707 int strict_p = (reload_in_progress || reload_completed);
27709 if (!legitimate_indexed_address_p (addr, strict_p)
27710 && !legitimate_indirect_address_p (addr, strict_p))
27711 addr = copy_to_mode_reg (Pmode, addr);
27713 addr = gen_rtx_AND (Pmode, addr, GEN_INT (-16));
27714 x = change_address (x, GET_MODE (x), addr);
27720 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
27722 On the RS/6000, all integer constants are acceptable, most won't be valid
27723 for particular insns, though. Only easy FP constants are acceptable. */
27726 rs6000_legitimate_constant_p (enum machine_mode mode, rtx x)
27728 if (rs6000_tls_referenced_p (x))
27731 return ((GET_CODE (x) != CONST_DOUBLE && GET_CODE (x) != CONST_VECTOR)
27732 || GET_MODE (x) == VOIDmode
27733 || (TARGET_POWERPC64 && mode == DImode)
27734 || easy_fp_constant (x, mode)
27735 || easy_vector_constant (x, mode));
27739 /* A function pointer under AIX is a pointer to a data area whose first word
27740 contains the actual address of the function, whose second word contains a
27741 pointer to its TOC, and whose third word contains a value to place in the
27742 static chain register (r11). Note that if we load the static chain, our
27743 "trampoline" need not have any executable code. */
27746 rs6000_call_indirect_aix (rtx value, rtx func_desc, rtx flag)
27752 rtx stack_toc_offset;
27754 rtx func_toc_offset;
27756 rtx func_sc_offset;
27759 rtx (*call_func) (rtx, rtx, rtx, rtx);
27760 rtx (*call_value_func) (rtx, rtx, rtx, rtx, rtx);
27762 stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
27763 toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
27765 /* Load up address of the actual function. */
27766 func_desc = force_reg (Pmode, func_desc);
27767 func_addr = gen_reg_rtx (Pmode);
27768 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));
27773 stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_32BIT);
27774 func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_32BIT);
27775 func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_32BIT);
27776 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
27778 call_func = gen_call_indirect_aix32bit;
27779 call_value_func = gen_call_value_indirect_aix32bit;
27783 call_func = gen_call_indirect_aix32bit_nor11;
27784 call_value_func = gen_call_value_indirect_aix32bit_nor11;
27789 stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_64BIT);
27790 func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_64BIT);
27791 func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_64BIT);
27792 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
27794 call_func = gen_call_indirect_aix64bit;
27795 call_value_func = gen_call_value_indirect_aix64bit;
27799 call_func = gen_call_indirect_aix64bit_nor11;
27800 call_value_func = gen_call_value_indirect_aix64bit_nor11;
27804 /* Reserved spot to store the TOC. */
27805 stack_toc_mem = gen_frame_mem (Pmode,
27806 gen_rtx_PLUS (Pmode,
27808 stack_toc_offset));
27811 gcc_assert (cfun->machine);
27813 /* Can we optimize saving the TOC in the prologue or do we need to do it at
27815 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
27816 cfun->machine->save_toc_in_prologue = true;
27820 MEM_VOLATILE_P (stack_toc_mem) = 1;
27821 emit_move_insn (stack_toc_mem, toc_reg);
27824 /* Calculate the address to load the TOC of the called function. We don't
27825 actually load this until the split after reload. */
27826 func_toc_mem = gen_rtx_MEM (Pmode,
27827 gen_rtx_PLUS (Pmode,
27831 /* If we have a static chain, load it up. */
27832 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
27834 func_sc_mem = gen_rtx_MEM (Pmode,
27835 gen_rtx_PLUS (Pmode,
27839 sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
27840 emit_move_insn (sc_reg, func_sc_mem);
27843 /* Create the call. */
27845 insn = call_value_func (value, func_addr, flag, func_toc_mem,
27848 insn = call_func (func_addr, flag, func_toc_mem, stack_toc_mem);
27850 emit_call_insn (insn);
27853 /* Return whether we need to always update the saved TOC pointer when we update
27854 the stack pointer. */
27857 rs6000_save_toc_in_prologue_p (void)
27859 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
27862 #ifdef HAVE_GAS_HIDDEN
27863 # define USE_HIDDEN_LINKONCE 1
27865 # define USE_HIDDEN_LINKONCE 0
27868 /* Fills in the label name that should be used for a 476 link stack thunk. */
27871 get_ppc476_thunk_name (char name[32])
27873 gcc_assert (TARGET_LINK_STACK);
27875 if (USE_HIDDEN_LINKONCE)
27876 sprintf (name, "__ppc476.get_thunk");
27878 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
27881 /* This function emits the simple thunk routine that is used to preserve
27882 the link stack on the 476 cpu. */
27885 rs6000_code_end (void)
27890 if (!TARGET_LINK_STACK)
27893 get_ppc476_thunk_name (name);
27895 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
27896 build_function_type_list (void_type_node, NULL_TREE));
27897 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
27898 NULL_TREE, void_type_node);
27899 TREE_PUBLIC (decl) = 1;
27900 TREE_STATIC (decl) = 1;
27902 if (USE_HIDDEN_LINKONCE)
27904 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
27905 targetm.asm_out.unique_section (decl, 0);
27906 switch_to_section (get_named_section (decl, NULL, 0));
27907 DECL_WEAK (decl) = 1;
27908 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
27909 targetm.asm_out.globalize_label (asm_out_file, name);
27910 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
27911 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
27915 switch_to_section (text_section);
27916 ASM_OUTPUT_LABEL (asm_out_file, name);
27919 DECL_INITIAL (decl) = make_node (BLOCK);
27920 current_function_decl = decl;
27921 init_function_start (decl);
27922 first_function_block_is_cold = false;
27923 /* Make sure unwind info is emitted for the thunk if needed. */
27924 final_start_function (emit_barrier (), asm_out_file, 1);
27926 fputs ("\tblr\n", asm_out_file);
27928 final_end_function ();
27929 init_insn_lengths ();
27930 free_after_compilation (cfun);
27932 current_function_decl = NULL;
27935 /* Add r30 to hard reg set if the prologue sets it up and it is not
27936 pic_offset_table_rtx. */
27939 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
27941 if (!TARGET_SINGLE_PIC_BASE
27943 && TARGET_MINIMAL_TOC
27944 && get_pool_size () != 0)
27945 add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
27948 struct gcc_target targetm = TARGET_INITIALIZER;
27950 #include "gt-rs6000.h"