1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
58 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
61 #include "gstab.h" /* for N_SLINE */
64 #ifndef TARGET_NO_PROTOTYPE
65 #define TARGET_NO_PROTOTYPE 0
68 #define min(A,B) ((A) < (B) ? (A) : (B))
69 #define max(A,B) ((A) > (B) ? (A) : (B))
71 /* Structure used to define the rs6000 stack */
72 typedef struct rs6000_stack {
73 int first_gp_reg_save; /* first callee saved GP register used */
74 int first_fp_reg_save; /* first callee saved FP register used */
75 int first_altivec_reg_save; /* first callee saved AltiVec register used */
76 int lr_save_p; /* true if the link reg needs to be saved */
77 int cr_save_p; /* true if the CR reg needs to be saved */
78 unsigned int vrsave_mask; /* mask of vec registers to save */
79 int toc_save_p; /* true if the TOC needs to be saved */
80 int push_p; /* true if we need to allocate stack space */
81 int calls_p; /* true if the function makes any calls */
82 int world_save_p; /* true if we're saving *everything*:
83 r13-r31, cr, f14-f31, vrsave, v20-v31 */
84 enum rs6000_abi abi; /* which ABI to use */
85 int gp_save_offset; /* offset to save GP regs from initial SP */
86 int fp_save_offset; /* offset to save FP regs from initial SP */
87 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset; /* offset to save LR from initial SP */
89 int cr_save_offset; /* offset to save CR from initial SP */
90 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
92 int toc_save_offset; /* offset to save the TOC pointer */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 int varargs_size; /* size to hold V.4 args passed in regs */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int lr_size; /* size to hold LR if not in save_size */
106 int vrsave_size; /* size to hold VRSAVE if not in save_size */
107 int altivec_padding_size; /* size of altivec alignment padding if
109 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
110 int spe_padding_size;
111 int toc_size; /* size to hold TOC if not in save_size */
112 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
113 int spe_64bit_regs_used;
116 /* Target cpu type */
118 enum processor_type rs6000_cpu;
119 struct rs6000_cpu_select rs6000_select[3] =
121 /* switch name, tune arch */
122 { (const char *)0, "--with-cpu=", 1, 1 },
123 { (const char *)0, "-mcpu=", 1, 1 },
124 { (const char *)0, "-mtune=", 1, 0 },
127 /* Always emit branch hint bits. */
128 static GTY(()) bool rs6000_always_hint;
130 /* Schedule instructions for group formation. */
131 static GTY(()) bool rs6000_sched_groups;
133 /* Support adjust_priority scheduler hook
134 and -mprioritize-restricted-insns= option. */
135 const char *rs6000_sched_restricted_insns_priority_str;
136 int rs6000_sched_restricted_insns_priority;
138 /* Support for -msched-costly-dep option. */
139 const char *rs6000_sched_costly_dep_str;
140 enum rs6000_dependence_cost rs6000_sched_costly_dep;
142 /* Support for -minsert-sched-nops option. */
143 const char *rs6000_sched_insert_nops_str;
144 enum rs6000_nop_insertion rs6000_sched_insert_nops;
146 /* Support targetm.vectorize.builtin_mask_for_load. */
147 static GTY(()) tree altivec_builtin_mask_for_load;
149 /* Size of long double */
150 const char *rs6000_long_double_size_string;
151 int rs6000_long_double_type_size;
153 /* Whether -mabi=altivec has appeared */
154 int rs6000_altivec_abi;
156 /* Whether VRSAVE instructions should be generated. */
157 int rs6000_altivec_vrsave;
159 /* String from -mvrsave= option. */
160 const char *rs6000_altivec_vrsave_string;
162 /* Nonzero if we want SPE ABI extensions. */
165 /* Whether isel instructions should be generated. */
168 /* Whether SPE simd instructions should be generated. */
171 /* Nonzero if floating point operations are done in the GPRs. */
172 int rs6000_float_gprs = 0;
174 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
175 int rs6000_darwin64_abi;
177 /* String from -mfloat-gprs=. */
178 const char *rs6000_float_gprs_string;
180 /* String from -misel=. */
181 const char *rs6000_isel_string;
183 /* String from -mspe=. */
184 const char *rs6000_spe_string;
186 /* Set to nonzero once AIX common-mode calls have been defined. */
187 static GTY(()) int common_mode_defined;
189 /* Save information from a "cmpxx" operation until the branch or scc is
191 rtx rs6000_compare_op0, rs6000_compare_op1;
192 int rs6000_compare_fp_p;
194 /* Label number of label created for -mrelocatable, to call to so we can
195 get the address of the GOT section */
196 int rs6000_pic_labelno;
199 /* Which abi to adhere to */
200 const char *rs6000_abi_name;
202 /* Semantics of the small data area */
203 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
205 /* Which small data model to use */
206 const char *rs6000_sdata_name = (char *)0;
208 /* Counter for labels which are to be placed in .fixup. */
209 int fixuplabelno = 0;
212 /* Bit size of immediate TLS offsets and string from which it is decoded. */
213 int rs6000_tls_size = 32;
214 const char *rs6000_tls_size_string;
216 /* ABI enumeration available for subtarget to use. */
217 enum rs6000_abi rs6000_current_abi;
219 /* ABI string from -mabi= option. */
220 const char *rs6000_abi_string;
222 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
226 const char *rs6000_debug_name;
227 int rs6000_debug_stack; /* debug stack applications */
228 int rs6000_debug_arg; /* debug argument handling */
230 /* Value is TRUE if register/mode pair is acceptable. */
231 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
234 static GTY(()) tree opaque_V2SI_type_node;
235 static GTY(()) tree opaque_V2SF_type_node;
236 static GTY(()) tree opaque_p_V2SI_type_node;
237 static GTY(()) tree V16QI_type_node;
238 static GTY(()) tree V2SI_type_node;
239 static GTY(()) tree V2SF_type_node;
240 static GTY(()) tree V4HI_type_node;
241 static GTY(()) tree V4SI_type_node;
242 static GTY(()) tree V4SF_type_node;
243 static GTY(()) tree V8HI_type_node;
244 static GTY(()) tree unsigned_V16QI_type_node;
245 static GTY(()) tree unsigned_V8HI_type_node;
246 static GTY(()) tree unsigned_V4SI_type_node;
247 static GTY(()) tree bool_char_type_node; /* __bool char */
248 static GTY(()) tree bool_short_type_node; /* __bool short */
249 static GTY(()) tree bool_int_type_node; /* __bool int */
250 static GTY(()) tree pixel_type_node; /* __pixel */
251 static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */
252 static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */
253 static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */
254 static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */
256 int rs6000_warn_altivec_long = 1; /* On by default. */
257 const char *rs6000_warn_altivec_long_switch;
259 const char *rs6000_traceback_name;
261 traceback_default = 0,
267 /* Flag to say the TOC is initialized */
269 char toc_label_name[10];
271 /* Alias set for saves and restores from the rs6000 stack. */
272 static GTY(()) int rs6000_sr_alias_set;
274 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
275 The only place that looks at this is rs6000_set_default_type_attributes;
276 everywhere else should rely on the presence or absence of a longcall
277 attribute on the function declaration. Exception: init_cumulative_args
278 looks at it too, for libcalls. */
279 int rs6000_default_long_calls;
280 const char *rs6000_longcall_switch;
282 /* Control alignment for fields within structures. */
283 /* String from -malign-XXXXX. */
284 const char *rs6000_alignment_string;
285 int rs6000_alignment_flags;
287 struct builtin_description
289 /* mask is not const because we're going to alter it below. This
290 nonsense will go away when we rewrite the -march infrastructure
291 to give us more target flag bits. */
293 const enum insn_code icode;
294 const char *const name;
295 const enum rs6000_builtins code;
298 /* Target cpu costs. */
300 struct processor_costs {
301 const int mulsi; /* cost of SImode multiplication. */
302 const int mulsi_const; /* cost of SImode multiplication by constant. */
303 const int mulsi_const9; /* cost of SImode mult by short constant. */
304 const int muldi; /* cost of DImode multiplication. */
305 const int divsi; /* cost of SImode division. */
306 const int divdi; /* cost of DImode division. */
307 const int fp; /* cost of simple SFmode and DFmode insns. */
308 const int dmul; /* cost of DFmode multiplication (and fmadd). */
309 const int sdiv; /* cost of SFmode division (fdivs). */
310 const int ddiv; /* cost of DFmode division (fdiv). */
313 const struct processor_costs *rs6000_cost;
315 /* Processor costs (relative to an add) */
317 /* Instruction size costs on 32bit processors. */
319 struct processor_costs size32_cost = {
320 COSTS_N_INSNS (1), /* mulsi */
321 COSTS_N_INSNS (1), /* mulsi_const */
322 COSTS_N_INSNS (1), /* mulsi_const9 */
323 COSTS_N_INSNS (1), /* muldi */
324 COSTS_N_INSNS (1), /* divsi */
325 COSTS_N_INSNS (1), /* divdi */
326 COSTS_N_INSNS (1), /* fp */
327 COSTS_N_INSNS (1), /* dmul */
328 COSTS_N_INSNS (1), /* sdiv */
329 COSTS_N_INSNS (1), /* ddiv */
332 /* Instruction size costs on 64bit processors. */
334 struct processor_costs size64_cost = {
335 COSTS_N_INSNS (1), /* mulsi */
336 COSTS_N_INSNS (1), /* mulsi_const */
337 COSTS_N_INSNS (1), /* mulsi_const9 */
338 COSTS_N_INSNS (1), /* muldi */
339 COSTS_N_INSNS (1), /* divsi */
340 COSTS_N_INSNS (1), /* divdi */
341 COSTS_N_INSNS (1), /* fp */
342 COSTS_N_INSNS (1), /* dmul */
343 COSTS_N_INSNS (1), /* sdiv */
344 COSTS_N_INSNS (1), /* ddiv */
347 /* Instruction costs on RIOS1 processors. */
349 struct processor_costs rios1_cost = {
350 COSTS_N_INSNS (5), /* mulsi */
351 COSTS_N_INSNS (4), /* mulsi_const */
352 COSTS_N_INSNS (3), /* mulsi_const9 */
353 COSTS_N_INSNS (5), /* muldi */
354 COSTS_N_INSNS (19), /* divsi */
355 COSTS_N_INSNS (19), /* divdi */
356 COSTS_N_INSNS (2), /* fp */
357 COSTS_N_INSNS (2), /* dmul */
358 COSTS_N_INSNS (19), /* sdiv */
359 COSTS_N_INSNS (19), /* ddiv */
362 /* Instruction costs on RIOS2 processors. */
364 struct processor_costs rios2_cost = {
365 COSTS_N_INSNS (2), /* mulsi */
366 COSTS_N_INSNS (2), /* mulsi_const */
367 COSTS_N_INSNS (2), /* mulsi_const9 */
368 COSTS_N_INSNS (2), /* muldi */
369 COSTS_N_INSNS (13), /* divsi */
370 COSTS_N_INSNS (13), /* divdi */
371 COSTS_N_INSNS (2), /* fp */
372 COSTS_N_INSNS (2), /* dmul */
373 COSTS_N_INSNS (17), /* sdiv */
374 COSTS_N_INSNS (17), /* ddiv */
377 /* Instruction costs on RS64A processors. */
379 struct processor_costs rs64a_cost = {
380 COSTS_N_INSNS (20), /* mulsi */
381 COSTS_N_INSNS (12), /* mulsi_const */
382 COSTS_N_INSNS (8), /* mulsi_const9 */
383 COSTS_N_INSNS (34), /* muldi */
384 COSTS_N_INSNS (65), /* divsi */
385 COSTS_N_INSNS (67), /* divdi */
386 COSTS_N_INSNS (4), /* fp */
387 COSTS_N_INSNS (4), /* dmul */
388 COSTS_N_INSNS (31), /* sdiv */
389 COSTS_N_INSNS (31), /* ddiv */
392 /* Instruction costs on MPCCORE processors. */
394 struct processor_costs mpccore_cost = {
395 COSTS_N_INSNS (2), /* mulsi */
396 COSTS_N_INSNS (2), /* mulsi_const */
397 COSTS_N_INSNS (2), /* mulsi_const9 */
398 COSTS_N_INSNS (2), /* muldi */
399 COSTS_N_INSNS (6), /* divsi */
400 COSTS_N_INSNS (6), /* divdi */
401 COSTS_N_INSNS (4), /* fp */
402 COSTS_N_INSNS (5), /* dmul */
403 COSTS_N_INSNS (10), /* sdiv */
404 COSTS_N_INSNS (17), /* ddiv */
407 /* Instruction costs on PPC403 processors. */
409 struct processor_costs ppc403_cost = {
410 COSTS_N_INSNS (4), /* mulsi */
411 COSTS_N_INSNS (4), /* mulsi_const */
412 COSTS_N_INSNS (4), /* mulsi_const9 */
413 COSTS_N_INSNS (4), /* muldi */
414 COSTS_N_INSNS (33), /* divsi */
415 COSTS_N_INSNS (33), /* divdi */
416 COSTS_N_INSNS (11), /* fp */
417 COSTS_N_INSNS (11), /* dmul */
418 COSTS_N_INSNS (11), /* sdiv */
419 COSTS_N_INSNS (11), /* ddiv */
422 /* Instruction costs on PPC405 processors. */
424 struct processor_costs ppc405_cost = {
425 COSTS_N_INSNS (5), /* mulsi */
426 COSTS_N_INSNS (4), /* mulsi_const */
427 COSTS_N_INSNS (3), /* mulsi_const9 */
428 COSTS_N_INSNS (5), /* muldi */
429 COSTS_N_INSNS (35), /* divsi */
430 COSTS_N_INSNS (35), /* divdi */
431 COSTS_N_INSNS (11), /* fp */
432 COSTS_N_INSNS (11), /* dmul */
433 COSTS_N_INSNS (11), /* sdiv */
434 COSTS_N_INSNS (11), /* ddiv */
437 /* Instruction costs on PPC440 processors. */
439 struct processor_costs ppc440_cost = {
440 COSTS_N_INSNS (3), /* mulsi */
441 COSTS_N_INSNS (2), /* mulsi_const */
442 COSTS_N_INSNS (2), /* mulsi_const9 */
443 COSTS_N_INSNS (3), /* muldi */
444 COSTS_N_INSNS (34), /* divsi */
445 COSTS_N_INSNS (34), /* divdi */
446 COSTS_N_INSNS (5), /* fp */
447 COSTS_N_INSNS (5), /* dmul */
448 COSTS_N_INSNS (19), /* sdiv */
449 COSTS_N_INSNS (33), /* ddiv */
452 /* Instruction costs on PPC601 processors. */
454 struct processor_costs ppc601_cost = {
455 COSTS_N_INSNS (5), /* mulsi */
456 COSTS_N_INSNS (5), /* mulsi_const */
457 COSTS_N_INSNS (5), /* mulsi_const9 */
458 COSTS_N_INSNS (5), /* muldi */
459 COSTS_N_INSNS (36), /* divsi */
460 COSTS_N_INSNS (36), /* divdi */
461 COSTS_N_INSNS (4), /* fp */
462 COSTS_N_INSNS (5), /* dmul */
463 COSTS_N_INSNS (17), /* sdiv */
464 COSTS_N_INSNS (31), /* ddiv */
467 /* Instruction costs on PPC603 processors. */
469 struct processor_costs ppc603_cost = {
470 COSTS_N_INSNS (5), /* mulsi */
471 COSTS_N_INSNS (3), /* mulsi_const */
472 COSTS_N_INSNS (2), /* mulsi_const9 */
473 COSTS_N_INSNS (5), /* muldi */
474 COSTS_N_INSNS (37), /* divsi */
475 COSTS_N_INSNS (37), /* divdi */
476 COSTS_N_INSNS (3), /* fp */
477 COSTS_N_INSNS (4), /* dmul */
478 COSTS_N_INSNS (18), /* sdiv */
479 COSTS_N_INSNS (33), /* ddiv */
482 /* Instruction costs on PPC604 processors. */
484 struct processor_costs ppc604_cost = {
485 COSTS_N_INSNS (4), /* mulsi */
486 COSTS_N_INSNS (4), /* mulsi_const */
487 COSTS_N_INSNS (4), /* mulsi_const9 */
488 COSTS_N_INSNS (4), /* muldi */
489 COSTS_N_INSNS (20), /* divsi */
490 COSTS_N_INSNS (20), /* divdi */
491 COSTS_N_INSNS (3), /* fp */
492 COSTS_N_INSNS (3), /* dmul */
493 COSTS_N_INSNS (18), /* sdiv */
494 COSTS_N_INSNS (32), /* ddiv */
497 /* Instruction costs on PPC604e processors. */
499 struct processor_costs ppc604e_cost = {
500 COSTS_N_INSNS (2), /* mulsi */
501 COSTS_N_INSNS (2), /* mulsi_const */
502 COSTS_N_INSNS (2), /* mulsi_const9 */
503 COSTS_N_INSNS (2), /* muldi */
504 COSTS_N_INSNS (20), /* divsi */
505 COSTS_N_INSNS (20), /* divdi */
506 COSTS_N_INSNS (3), /* fp */
507 COSTS_N_INSNS (3), /* dmul */
508 COSTS_N_INSNS (18), /* sdiv */
509 COSTS_N_INSNS (32), /* ddiv */
512 /* Instruction costs on PPC620 processors. */
514 struct processor_costs ppc620_cost = {
515 COSTS_N_INSNS (5), /* mulsi */
516 COSTS_N_INSNS (4), /* mulsi_const */
517 COSTS_N_INSNS (3), /* mulsi_const9 */
518 COSTS_N_INSNS (7), /* muldi */
519 COSTS_N_INSNS (21), /* divsi */
520 COSTS_N_INSNS (37), /* divdi */
521 COSTS_N_INSNS (3), /* fp */
522 COSTS_N_INSNS (3), /* dmul */
523 COSTS_N_INSNS (18), /* sdiv */
524 COSTS_N_INSNS (32), /* ddiv */
527 /* Instruction costs on PPC630 processors. */
529 struct processor_costs ppc630_cost = {
530 COSTS_N_INSNS (5), /* mulsi */
531 COSTS_N_INSNS (4), /* mulsi_const */
532 COSTS_N_INSNS (3), /* mulsi_const9 */
533 COSTS_N_INSNS (7), /* muldi */
534 COSTS_N_INSNS (21), /* divsi */
535 COSTS_N_INSNS (37), /* divdi */
536 COSTS_N_INSNS (3), /* fp */
537 COSTS_N_INSNS (3), /* dmul */
538 COSTS_N_INSNS (17), /* sdiv */
539 COSTS_N_INSNS (21), /* ddiv */
542 /* Instruction costs on PPC750 and PPC7400 processors. */
544 struct processor_costs ppc750_cost = {
545 COSTS_N_INSNS (5), /* mulsi */
546 COSTS_N_INSNS (3), /* mulsi_const */
547 COSTS_N_INSNS (2), /* mulsi_const9 */
548 COSTS_N_INSNS (5), /* muldi */
549 COSTS_N_INSNS (17), /* divsi */
550 COSTS_N_INSNS (17), /* divdi */
551 COSTS_N_INSNS (3), /* fp */
552 COSTS_N_INSNS (3), /* dmul */
553 COSTS_N_INSNS (17), /* sdiv */
554 COSTS_N_INSNS (31), /* ddiv */
557 /* Instruction costs on PPC7450 processors. */
559 struct processor_costs ppc7450_cost = {
560 COSTS_N_INSNS (4), /* mulsi */
561 COSTS_N_INSNS (3), /* mulsi_const */
562 COSTS_N_INSNS (3), /* mulsi_const9 */
563 COSTS_N_INSNS (4), /* muldi */
564 COSTS_N_INSNS (23), /* divsi */
565 COSTS_N_INSNS (23), /* divdi */
566 COSTS_N_INSNS (5), /* fp */
567 COSTS_N_INSNS (5), /* dmul */
568 COSTS_N_INSNS (21), /* sdiv */
569 COSTS_N_INSNS (35), /* ddiv */
572 /* Instruction costs on PPC8540 processors. */
574 struct processor_costs ppc8540_cost = {
575 COSTS_N_INSNS (4), /* mulsi */
576 COSTS_N_INSNS (4), /* mulsi_const */
577 COSTS_N_INSNS (4), /* mulsi_const9 */
578 COSTS_N_INSNS (4), /* muldi */
579 COSTS_N_INSNS (19), /* divsi */
580 COSTS_N_INSNS (19), /* divdi */
581 COSTS_N_INSNS (4), /* fp */
582 COSTS_N_INSNS (4), /* dmul */
583 COSTS_N_INSNS (29), /* sdiv */
584 COSTS_N_INSNS (29), /* ddiv */
587 /* Instruction costs on POWER4 and POWER5 processors. */
589 struct processor_costs power4_cost = {
590 COSTS_N_INSNS (3), /* mulsi */
591 COSTS_N_INSNS (2), /* mulsi_const */
592 COSTS_N_INSNS (2), /* mulsi_const9 */
593 COSTS_N_INSNS (4), /* muldi */
594 COSTS_N_INSNS (18), /* divsi */
595 COSTS_N_INSNS (34), /* divdi */
596 COSTS_N_INSNS (3), /* fp */
597 COSTS_N_INSNS (3), /* dmul */
598 COSTS_N_INSNS (17), /* sdiv */
599 COSTS_N_INSNS (17), /* ddiv */
603 static bool rs6000_function_ok_for_sibcall (tree, tree);
604 static rtx rs6000_generate_compare (enum rtx_code);
605 static void rs6000_maybe_dead (rtx);
606 static void rs6000_emit_stack_tie (void);
607 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
608 static rtx spe_synthesize_frame_save (rtx);
609 static bool spe_func_has_64bit_regs_p (void);
610 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
612 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
613 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
614 static unsigned rs6000_hash_constant (rtx);
615 static unsigned toc_hash_function (const void *);
616 static int toc_hash_eq (const void *, const void *);
617 static int constant_pool_expr_1 (rtx, int *, int *);
618 static bool constant_pool_expr_p (rtx);
619 static bool legitimate_small_data_p (enum machine_mode, rtx);
620 static bool legitimate_indexed_address_p (rtx, int);
621 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
622 static struct machine_function * rs6000_init_machine_status (void);
623 static bool rs6000_assemble_integer (rtx, unsigned int, int);
624 #ifdef HAVE_GAS_HIDDEN
625 static void rs6000_assemble_visibility (tree, int);
627 static int rs6000_ra_ever_killed (void);
628 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
629 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
630 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
631 static const char *rs6000_mangle_fundamental_type (tree);
632 extern const struct attribute_spec rs6000_attribute_table[];
633 static void rs6000_set_default_type_attributes (tree);
634 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
635 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
636 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
638 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
639 static bool rs6000_return_in_memory (tree, tree);
640 static void rs6000_file_start (void);
642 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
643 static void rs6000_elf_asm_out_constructor (rtx, int);
644 static void rs6000_elf_asm_out_destructor (rtx, int);
645 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
646 static void rs6000_elf_unique_section (tree, int);
647 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
648 unsigned HOST_WIDE_INT);
649 static void rs6000_elf_encode_section_info (tree, rtx, int)
651 static bool rs6000_elf_in_small_data_p (tree);
654 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
655 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
656 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
657 static void rs6000_xcoff_unique_section (tree, int);
658 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
659 unsigned HOST_WIDE_INT);
660 static const char * rs6000_xcoff_strip_name_encoding (const char *);
661 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
662 static void rs6000_xcoff_file_start (void);
663 static void rs6000_xcoff_file_end (void);
666 static bool rs6000_binds_local_p (tree);
668 static int rs6000_variable_issue (FILE *, int, rtx, int);
669 static bool rs6000_rtx_costs (rtx, int, int, int *);
670 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
671 static bool is_microcoded_insn (rtx);
672 static int is_dispatch_slot_restricted (rtx);
673 static bool is_cracked_insn (rtx);
674 static bool is_branch_slot_insn (rtx);
675 static int rs6000_adjust_priority (rtx, int);
676 static int rs6000_issue_rate (void);
677 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
678 static rtx get_next_active_insn (rtx, rtx);
679 static bool insn_terminates_group_p (rtx , enum group_termination);
680 static bool is_costly_group (rtx *, rtx);
681 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
682 static int redefine_groups (FILE *, int, rtx, rtx);
683 static int pad_groups (FILE *, int, rtx, rtx);
684 static void rs6000_sched_finish (FILE *, int);
685 static int rs6000_use_sched_lookahead (void);
686 static tree rs6000_builtin_mask_for_load (void);
688 static void rs6000_init_builtins (void);
689 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
690 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
691 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
692 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
693 static void altivec_init_builtins (void);
694 static void rs6000_common_init_builtins (void);
695 static void rs6000_init_libfuncs (void);
697 static void enable_mask_for_builtins (struct builtin_description *, int,
698 enum rs6000_builtins,
699 enum rs6000_builtins);
700 static tree build_opaque_vector_type (tree, int);
701 static void spe_init_builtins (void);
702 static rtx spe_expand_builtin (tree, rtx, bool *);
703 static rtx spe_expand_stv_builtin (enum insn_code, tree);
704 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
705 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
706 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
707 static rs6000_stack_t *rs6000_stack_info (void);
708 static void debug_stack_info (rs6000_stack_t *);
710 static rtx altivec_expand_builtin (tree, rtx, bool *);
711 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
712 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
713 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
714 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
715 static rtx altivec_expand_predicate_builtin (enum insn_code,
716 const char *, tree, rtx);
717 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
718 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
719 static void rs6000_parse_abi_options (void);
720 static void rs6000_parse_alignment_option (void);
721 static void rs6000_parse_tls_size_option (void);
722 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
723 static void rs6000_parse_float_gprs_option (void);
724 static int first_altivec_reg_to_save (void);
725 static unsigned int compute_vrsave_mask (void);
726 static void compute_save_world_info (rs6000_stack_t *info_ptr);
727 static void is_altivec_return_reg (rtx, void *);
728 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
729 int easy_vector_constant (rtx, enum machine_mode);
730 static bool is_ev64_opaque_type (tree);
731 static rtx rs6000_dwarf_register_span (rtx);
732 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
733 static rtx rs6000_tls_get_addr (void);
734 static rtx rs6000_got_sym (void);
735 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
736 static const char *rs6000_get_some_local_dynamic_name (void);
737 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
738 static rtx rs6000_complex_function_value (enum machine_mode);
739 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
740 enum machine_mode, tree);
741 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
743 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
744 tree, HOST_WIDE_INT);
745 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
748 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
751 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
752 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
753 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
754 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
755 enum machine_mode, tree,
757 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
759 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
761 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
763 static void macho_branch_islands (void);
764 static void add_compiler_branch_island (tree, tree, int);
765 static int no_previous_def (tree function_name);
766 static tree get_prev_label (tree function_name);
767 static void rs6000_darwin_file_start (void);
770 static tree rs6000_build_builtin_va_list (void);
771 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
772 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
773 static bool rs6000_vector_mode_supported_p (enum machine_mode);
774 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
776 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
778 static int get_vsel_insn (enum machine_mode);
779 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
782 const int INSN_NOT_AVAILABLE = -1;
783 static enum machine_mode rs6000_eh_return_filter_mode (void);
785 /* Hash table stuff for keeping track of TOC entries. */
787 struct toc_hash_struct GTY(())
789 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
790 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
792 enum machine_mode key_mode;
796 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
798 /* Default register names. */
799 char rs6000_reg_names[][8] =
801 "0", "1", "2", "3", "4", "5", "6", "7",
802 "8", "9", "10", "11", "12", "13", "14", "15",
803 "16", "17", "18", "19", "20", "21", "22", "23",
804 "24", "25", "26", "27", "28", "29", "30", "31",
805 "0", "1", "2", "3", "4", "5", "6", "7",
806 "8", "9", "10", "11", "12", "13", "14", "15",
807 "16", "17", "18", "19", "20", "21", "22", "23",
808 "24", "25", "26", "27", "28", "29", "30", "31",
809 "mq", "lr", "ctr","ap",
810 "0", "1", "2", "3", "4", "5", "6", "7",
812 /* AltiVec registers. */
813 "0", "1", "2", "3", "4", "5", "6", "7",
814 "8", "9", "10", "11", "12", "13", "14", "15",
815 "16", "17", "18", "19", "20", "21", "22", "23",
816 "24", "25", "26", "27", "28", "29", "30", "31",
822 #ifdef TARGET_REGNAMES
823 static const char alt_reg_names[][8] =
825 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
826 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
827 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
828 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
829 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
830 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
831 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
832 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
833 "mq", "lr", "ctr", "ap",
834 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
836 /* AltiVec registers. */
837 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
838 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
839 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
840 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
847 #ifndef MASK_STRICT_ALIGN
848 #define MASK_STRICT_ALIGN 0
850 #ifndef TARGET_PROFILE_KERNEL
851 #define TARGET_PROFILE_KERNEL 0
854 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
855 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
857 /* Initialize the GCC target structure. */
858 #undef TARGET_ATTRIBUTE_TABLE
859 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
860 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
861 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
863 #undef TARGET_ASM_ALIGNED_DI_OP
864 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
866 /* Default unaligned ops are only provided for ELF. Find the ops needed
867 for non-ELF systems. */
868 #ifndef OBJECT_FORMAT_ELF
870 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
872 #undef TARGET_ASM_UNALIGNED_HI_OP
873 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
874 #undef TARGET_ASM_UNALIGNED_SI_OP
875 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
876 #undef TARGET_ASM_UNALIGNED_DI_OP
877 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
880 #undef TARGET_ASM_UNALIGNED_HI_OP
881 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
882 #undef TARGET_ASM_UNALIGNED_SI_OP
883 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
884 #undef TARGET_ASM_UNALIGNED_DI_OP
885 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
886 #undef TARGET_ASM_ALIGNED_DI_OP
887 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
891 /* This hook deals with fixups for relocatable code and DI-mode objects
893 #undef TARGET_ASM_INTEGER
894 #define TARGET_ASM_INTEGER rs6000_assemble_integer
896 #ifdef HAVE_GAS_HIDDEN
897 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
898 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
901 #undef TARGET_HAVE_TLS
902 #define TARGET_HAVE_TLS HAVE_AS_TLS
904 #undef TARGET_CANNOT_FORCE_CONST_MEM
905 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
907 #undef TARGET_ASM_FUNCTION_PROLOGUE
908 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
909 #undef TARGET_ASM_FUNCTION_EPILOGUE
910 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
912 #undef TARGET_SCHED_VARIABLE_ISSUE
913 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
915 #undef TARGET_SCHED_ISSUE_RATE
916 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
917 #undef TARGET_SCHED_ADJUST_COST
918 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
919 #undef TARGET_SCHED_ADJUST_PRIORITY
920 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
921 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
922 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
923 #undef TARGET_SCHED_FINISH
924 #define TARGET_SCHED_FINISH rs6000_sched_finish
926 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
927 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
929 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
930 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
932 #undef TARGET_INIT_BUILTINS
933 #define TARGET_INIT_BUILTINS rs6000_init_builtins
935 #undef TARGET_EXPAND_BUILTIN
936 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
938 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
939 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
941 #undef TARGET_INIT_LIBFUNCS
942 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
945 #undef TARGET_BINDS_LOCAL_P
946 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
949 #undef TARGET_ASM_OUTPUT_MI_THUNK
950 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
952 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
953 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
955 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
956 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
958 #undef TARGET_RTX_COSTS
959 #define TARGET_RTX_COSTS rs6000_rtx_costs
960 #undef TARGET_ADDRESS_COST
961 #define TARGET_ADDRESS_COST hook_int_rtx_0
963 #undef TARGET_VECTOR_OPAQUE_P
964 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
966 #undef TARGET_DWARF_REGISTER_SPAN
967 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
969 /* On rs6000, function arguments are promoted, as are function return
971 #undef TARGET_PROMOTE_FUNCTION_ARGS
972 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
973 #undef TARGET_PROMOTE_FUNCTION_RETURN
974 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
976 #undef TARGET_RETURN_IN_MEMORY
977 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
979 #undef TARGET_SETUP_INCOMING_VARARGS
980 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
982 /* Always strict argument naming on rs6000. */
983 #undef TARGET_STRICT_ARGUMENT_NAMING
984 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
985 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
986 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
987 #undef TARGET_SPLIT_COMPLEX_ARG
988 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
989 #undef TARGET_MUST_PASS_IN_STACK
990 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
991 #undef TARGET_PASS_BY_REFERENCE
992 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
993 #undef TARGET_ARG_PARTIAL_BYTES
994 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
996 #undef TARGET_BUILD_BUILTIN_VA_LIST
997 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
999 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1000 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1002 #undef TARGET_EH_RETURN_FILTER_MODE
1003 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1005 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1006 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1008 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1009 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1011 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1012 The PowerPC architecture requires only weak consistency among
1013 processors--that is, memory accesses between processors need not be
1014 sequentially consistent and memory accesses among processors can occur
1015 in any order. The ability to order memory accesses weakly provides
1016 opportunities for more efficient use of the system bus. Unless a
1017 dependency exists, the 604e allows read operations to precede store
1019 #undef TARGET_RELAXED_ORDERING
1020 #define TARGET_RELAXED_ORDERING true
1022 struct gcc_target targetm = TARGET_INITIALIZER;
1025 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1028 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1030 /* The GPRs can hold any mode, but values bigger than one register
1031 cannot go past R31. */
1032 if (INT_REGNO_P (regno))
1033 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1035 /* The float registers can only hold floating modes and DImode. */
1036 if (FP_REGNO_P (regno))
1038 (GET_MODE_CLASS (mode) == MODE_FLOAT
1039 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1040 || (GET_MODE_CLASS (mode) == MODE_INT
1041 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1043 /* The CR register can only hold CC modes. */
1044 if (CR_REGNO_P (regno))
1045 return GET_MODE_CLASS (mode) == MODE_CC;
1047 if (XER_REGNO_P (regno))
1048 return mode == PSImode;
1050 /* AltiVec only in AldyVec registers. */
1051 if (ALTIVEC_REGNO_P (regno))
1052 return ALTIVEC_VECTOR_MODE (mode);
1054 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1055 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1058 /* We cannot put TImode anywhere except general register and it must be
1059 able to fit within the register set. */
1061 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1064 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1066 rs6000_init_hard_regno_mode_ok (void)
1070 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1071 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1072 if (rs6000_hard_regno_mode_ok (r, m))
1073 rs6000_hard_regno_mode_ok_p[m][r] = true;
1076 /* If not otherwise specified by a target, make 'long double' equivalent to
1079 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1080 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1083 /* Override command line options. Mostly we process the processor
1084 type and sometimes adjust other TARGET_ options. */
1087 rs6000_override_options (const char *default_cpu)
1090 struct rs6000_cpu_select *ptr;
1093 /* Simplifications for entries below. */
1096 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1097 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1100 /* This table occasionally claims that a processor does not support
1101 a particular feature even though it does, but the feature is slower
1102 than the alternative. Thus, it shouldn't be relied on as a
1103 complete description of the processor's support.
1105 Please keep this list in order, and don't forget to update the
1106 documentation in invoke.texi when adding a new processor or
1110 const char *const name; /* Canonical processor name. */
1111 const enum processor_type processor; /* Processor type enum value. */
1112 const int target_enable; /* Target flags to enable. */
1113 } const processor_target_table[]
1114 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1115 {"403", PROCESSOR_PPC403,
1116 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1117 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1118 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1119 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1120 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1121 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1122 {"601", PROCESSOR_PPC601,
1123 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1124 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1125 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1126 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1127 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1128 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1129 {"620", PROCESSOR_PPC620,
1130 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1131 {"630", PROCESSOR_PPC630,
1132 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1133 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1134 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1135 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1136 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1137 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1138 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1139 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1140 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1141 /* 8548 has a dummy entry for now. */
1142 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1143 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1144 {"970", PROCESSOR_POWER4,
1145 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1146 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1147 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1148 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1149 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1150 {"G5", PROCESSOR_POWER4,
1151 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1152 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1153 {"power2", PROCESSOR_POWER,
1154 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1155 {"power3", PROCESSOR_PPC630,
1156 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1157 {"power4", PROCESSOR_POWER4,
1158 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1159 {"power5", PROCESSOR_POWER5,
1160 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1161 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1162 {"powerpc64", PROCESSOR_POWERPC64,
1163 POWERPC_BASE_MASK | MASK_POWERPC64},
1164 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1165 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1166 {"rios2", PROCESSOR_RIOS2,
1167 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1168 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1169 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1170 {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
1173 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1175 /* Some OSs don't support saving the high part of 64-bit registers on
1176 context switch. Other OSs don't support saving Altivec registers.
1177 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1178 settings; if the user wants either, the user must explicitly specify
1179 them and we won't interfere with the user's specification. */
1182 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1183 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1184 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1188 rs6000_init_hard_regno_mode_ok ();
1190 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1191 #ifdef OS_MISSING_POWERPC64
1192 if (OS_MISSING_POWERPC64)
1193 set_masks &= ~MASK_POWERPC64;
1195 #ifdef OS_MISSING_ALTIVEC
1196 if (OS_MISSING_ALTIVEC)
1197 set_masks &= ~MASK_ALTIVEC;
1200 /* Don't override by the processor default if given explicitly. */
1201 set_masks &= ~target_flags_explicit;
1203 /* Identify the processor type. */
1204 rs6000_select[0].string = default_cpu;
1205 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1207 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1209 ptr = &rs6000_select[i];
1210 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1212 for (j = 0; j < ptt_size; j++)
1213 if (! strcmp (ptr->string, processor_target_table[j].name))
1215 if (ptr->set_tune_p)
1216 rs6000_cpu = processor_target_table[j].processor;
1218 if (ptr->set_arch_p)
1220 target_flags &= ~set_masks;
1221 target_flags |= (processor_target_table[j].target_enable
1228 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1235 /* If we are optimizing big endian systems for space, use the load/store
1236 multiple and string instructions. */
1237 if (BYTES_BIG_ENDIAN && optimize_size)
1238 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1240 /* Don't allow -mmultiple or -mstring on little endian systems
1241 unless the cpu is a 750, because the hardware doesn't support the
1242 instructions used in little endian mode, and causes an alignment
1243 trap. The 750 does not cause an alignment trap (except when the
1244 target is unaligned). */
1246 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1248 if (TARGET_MULTIPLE)
1250 target_flags &= ~MASK_MULTIPLE;
1251 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1252 warning ("-mmultiple is not supported on little endian systems");
1257 target_flags &= ~MASK_STRING;
1258 if ((target_flags_explicit & MASK_STRING) != 0)
1259 warning ("-mstring is not supported on little endian systems");
1263 /* Set debug flags */
1264 if (rs6000_debug_name)
1266 if (! strcmp (rs6000_debug_name, "all"))
1267 rs6000_debug_stack = rs6000_debug_arg = 1;
1268 else if (! strcmp (rs6000_debug_name, "stack"))
1269 rs6000_debug_stack = 1;
1270 else if (! strcmp (rs6000_debug_name, "arg"))
1271 rs6000_debug_arg = 1;
1273 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1276 if (rs6000_traceback_name)
1278 if (! strncmp (rs6000_traceback_name, "full", 4))
1279 rs6000_traceback = traceback_full;
1280 else if (! strncmp (rs6000_traceback_name, "part", 4))
1281 rs6000_traceback = traceback_part;
1282 else if (! strncmp (rs6000_traceback_name, "no", 2))
1283 rs6000_traceback = traceback_none;
1285 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1286 rs6000_traceback_name);
1289 /* Set size of long double */
1290 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1291 if (rs6000_long_double_size_string)
1294 int size = strtol (rs6000_long_double_size_string, &tail, 10);
1295 if (*tail != '\0' || (size != 64 && size != 128))
1296 error ("Unknown switch -mlong-double-%s",
1297 rs6000_long_double_size_string);
1299 rs6000_long_double_type_size = size;
1302 /* Set Altivec ABI as default for powerpc64 linux. */
1303 if (TARGET_ELF && TARGET_64BIT)
1305 rs6000_altivec_abi = 1;
1306 rs6000_altivec_vrsave = 1;
1309 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1310 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1312 rs6000_darwin64_abi = 1;
1313 /* Setting to empty string is same as "-mone-byte-bool". */
1315 darwin_one_byte_bool = "";
1317 /* Default to natural alignment, for better performance. */
1318 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1321 /* Handle -mabi= options. */
1322 rs6000_parse_abi_options ();
1324 /* Handle -malign-XXXXX option. */
1325 rs6000_parse_alignment_option ();
1327 rs6000_parse_float_gprs_option ();
1329 /* Handle generic -mFOO=YES/NO options. */
1330 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
1331 &rs6000_altivec_vrsave);
1332 rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
1334 rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
1336 /* Handle -mtls-size option. */
1337 rs6000_parse_tls_size_option ();
1339 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1340 SUBTARGET_OVERRIDE_OPTIONS;
1342 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1343 SUBSUBTARGET_OVERRIDE_OPTIONS;
1345 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1346 SUB3TARGET_OVERRIDE_OPTIONS;
1352 error ("AltiVec and E500 instructions cannot coexist");
1354 /* The e500 does not have string instructions, and we set
1355 MASK_STRING above when optimizing for size. */
1356 if ((target_flags & MASK_STRING) != 0)
1357 target_flags = target_flags & ~MASK_STRING;
1359 /* No SPE means 64-bit long doubles, even if an E500. */
1360 if (rs6000_spe_string != 0
1361 && !strcmp (rs6000_spe_string, "no"))
1362 rs6000_long_double_type_size = 64;
1364 else if (rs6000_select[1].string != NULL)
1366 /* For the powerpc-eabispe configuration, we set all these by
1367 default, so let's unset them if we manually set another
1368 CPU that is not the E500. */
1369 if (rs6000_abi_string == 0)
1371 if (rs6000_spe_string == 0)
1373 if (rs6000_float_gprs_string == 0)
1374 rs6000_float_gprs = 0;
1375 if (rs6000_isel_string == 0)
1377 if (rs6000_long_double_size_string == 0)
1378 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1381 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1382 && rs6000_cpu != PROCESSOR_POWER5);
1383 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1384 || rs6000_cpu == PROCESSOR_POWER5);
1386 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
1387 using TARGET_OPTIONS to handle a toggle switch, but we're out of
1388 bits in target_flags so TARGET_SWITCHES cannot be used.
1389 Assumption here is that rs6000_longcall_switch points into the
1390 text of the complete option, rather than being a copy, so we can
1391 scan back for the presence or absence of the no- modifier. */
1392 if (rs6000_longcall_switch)
1394 const char *base = rs6000_longcall_switch;
1395 while (base[-1] != 'm') base--;
1397 if (*rs6000_longcall_switch != '\0')
1398 error ("invalid option %qs", base);
1399 rs6000_default_long_calls = (base[0] != 'n');
1402 /* Handle -m(no-)warn-altivec-long similarly. */
1403 if (rs6000_warn_altivec_long_switch)
1405 const char *base = rs6000_warn_altivec_long_switch;
1406 while (base[-1] != 'm') base--;
1408 if (*rs6000_warn_altivec_long_switch != '\0')
1409 error ("invalid option %qs", base);
1410 rs6000_warn_altivec_long = (base[0] != 'n');
1413 /* Handle -mprioritize-restricted-insns option. */
1414 rs6000_sched_restricted_insns_priority
1415 = (rs6000_sched_groups ? 1 : 0);
1416 if (rs6000_sched_restricted_insns_priority_str)
1417 rs6000_sched_restricted_insns_priority =
1418 atoi (rs6000_sched_restricted_insns_priority_str);
1420 /* Handle -msched-costly-dep option. */
1421 rs6000_sched_costly_dep
1422 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1423 if (rs6000_sched_costly_dep_str)
1425 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1426 rs6000_sched_costly_dep = no_dep_costly;
1427 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1428 rs6000_sched_costly_dep = all_deps_costly;
1429 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1430 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1431 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1432 rs6000_sched_costly_dep = store_to_load_dep_costly;
1434 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1437 /* Handle -minsert-sched-nops option. */
1438 rs6000_sched_insert_nops
1439 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1440 if (rs6000_sched_insert_nops_str)
1442 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1443 rs6000_sched_insert_nops = sched_finish_none;
1444 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1445 rs6000_sched_insert_nops = sched_finish_pad_groups;
1446 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1447 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1449 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1452 #ifdef TARGET_REGNAMES
1453 /* If the user desires alternate register names, copy in the
1454 alternate names now. */
1455 if (TARGET_REGNAMES)
1456 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1459 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1460 If -maix-struct-return or -msvr4-struct-return was explicitly
1461 used, don't override with the ABI default. */
1462 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
1464 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
1465 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
1467 target_flags |= MASK_AIX_STRUCT_RET;
1470 if (TARGET_LONG_DOUBLE_128
1471 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1472 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1474 /* Allocate an alias set for register saves & restores from stack. */
1475 rs6000_sr_alias_set = new_alias_set ();
1478 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1480 /* We can only guarantee the availability of DI pseudo-ops when
1481 assembling for 64-bit targets. */
1484 targetm.asm_out.aligned_op.di = NULL;
1485 targetm.asm_out.unaligned_op.di = NULL;
1488 /* Set branch target alignment, if not optimizing for size. */
1491 if (rs6000_sched_groups)
1493 if (align_functions <= 0)
1494 align_functions = 16;
1495 if (align_jumps <= 0)
1497 if (align_loops <= 0)
1500 if (align_jumps_max_skip <= 0)
1501 align_jumps_max_skip = 15;
1502 if (align_loops_max_skip <= 0)
1503 align_loops_max_skip = 15;
1506 /* Arrange to save and restore machine status around nested functions. */
1507 init_machine_status = rs6000_init_machine_status;
1509 /* We should always be splitting complex arguments, but we can't break
1510 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1511 if (DEFAULT_ABI != ABI_AIX)
1512 targetm.calls.split_complex_arg = NULL;
1514 /* Initialize rs6000_cost with the appropriate target costs. */
1516 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1520 case PROCESSOR_RIOS1:
1521 rs6000_cost = &rios1_cost;
1524 case PROCESSOR_RIOS2:
1525 rs6000_cost = &rios2_cost;
1528 case PROCESSOR_RS64A:
1529 rs6000_cost = &rs64a_cost;
1532 case PROCESSOR_MPCCORE:
1533 rs6000_cost = &mpccore_cost;
1536 case PROCESSOR_PPC403:
1537 rs6000_cost = &ppc403_cost;
1540 case PROCESSOR_PPC405:
1541 rs6000_cost = &ppc405_cost;
1544 case PROCESSOR_PPC440:
1545 rs6000_cost = &ppc440_cost;
1548 case PROCESSOR_PPC601:
1549 rs6000_cost = &ppc601_cost;
1552 case PROCESSOR_PPC603:
1553 rs6000_cost = &ppc603_cost;
1556 case PROCESSOR_PPC604:
1557 rs6000_cost = &ppc604_cost;
1560 case PROCESSOR_PPC604e:
1561 rs6000_cost = &ppc604e_cost;
1564 case PROCESSOR_PPC620:
1565 rs6000_cost = &ppc620_cost;
1568 case PROCESSOR_PPC630:
1569 rs6000_cost = &ppc630_cost;
1572 case PROCESSOR_PPC750:
1573 case PROCESSOR_PPC7400:
1574 rs6000_cost = &ppc750_cost;
1577 case PROCESSOR_PPC7450:
1578 rs6000_cost = &ppc7450_cost;
1581 case PROCESSOR_PPC8540:
1582 rs6000_cost = &ppc8540_cost;
1585 case PROCESSOR_POWER4:
1586 case PROCESSOR_POWER5:
1587 rs6000_cost = &power4_cost;
1595 /* Implement targetm.vectorize.builtin_mask_for_load. */
1597 rs6000_builtin_mask_for_load (void)
1600 return altivec_builtin_mask_for_load;
1605 /* Handle generic options of the form -mfoo=yes/no.
1606 NAME is the option name.
1607 VALUE is the option value.
1608 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1609 whether the option value is 'yes' or 'no' respectively. */
1611 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1615 else if (!strcmp (value, "yes"))
1617 else if (!strcmp (value, "no"))
1620 error ("unknown -m%s= option specified: '%s'", name, value);
1623 /* Handle -mabi= options. */
1625 rs6000_parse_abi_options (void)
1627 if (rs6000_abi_string == 0)
1629 else if (! strcmp (rs6000_abi_string, "altivec"))
1631 rs6000_altivec_abi = 1;
1634 else if (! strcmp (rs6000_abi_string, "no-altivec"))
1635 rs6000_altivec_abi = 0;
1636 else if (! strcmp (rs6000_abi_string, "spe"))
1639 rs6000_altivec_abi = 0;
1640 if (!TARGET_SPE_ABI)
1641 error ("not configured for ABI: '%s'", rs6000_abi_string);
1644 /* These are here for testing during development only, do not
1645 document in the manual please. */
1646 else if (! strcmp (rs6000_abi_string, "d64"))
1648 rs6000_darwin64_abi = 1;
1649 warning ("Using darwin64 ABI");
1651 else if (! strcmp (rs6000_abi_string, "d32"))
1653 rs6000_darwin64_abi = 0;
1654 warning ("Using old darwin ABI");
1657 else if (! strcmp (rs6000_abi_string, "no-spe"))
1660 error ("unknown ABI specified: '%s'", rs6000_abi_string);
1663 /* Handle -mfloat-gprs= options. */
1665 rs6000_parse_float_gprs_option (void)
1667 if (rs6000_float_gprs_string == 0)
1669 else if (! strcmp (rs6000_float_gprs_string, "yes")
1670 || ! strcmp (rs6000_float_gprs_string, "single"))
1671 rs6000_float_gprs = 1;
1672 else if (! strcmp (rs6000_float_gprs_string, "double"))
1673 rs6000_float_gprs = 2;
1674 else if (! strcmp (rs6000_float_gprs_string, "no"))
1675 rs6000_float_gprs = 0;
1677 error ("invalid option for -mfloat-gprs");
1680 /* Handle -malign-XXXXXX options. */
1682 rs6000_parse_alignment_option (void)
1684 if (rs6000_alignment_string == 0)
1686 else if (! strcmp (rs6000_alignment_string, "power"))
1688 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1689 some C library functions, so warn about it. The flag may be
1690 useful for performance studies from time to time though, so
1691 don't disable it entirely. */
1692 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1693 warning ("-malign-power is not supported for 64-bit Darwin;"
1694 " it is incompatible with the installed C and C++ libraries");
1695 rs6000_alignment_flags = MASK_ALIGN_POWER;
1697 else if (! strcmp (rs6000_alignment_string, "natural"))
1698 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1700 error ("unknown -malign-XXXXX option specified: '%s'",
1701 rs6000_alignment_string);
1704 /* Validate and record the size specified with the -mtls-size option. */
1707 rs6000_parse_tls_size_option (void)
1709 if (rs6000_tls_size_string == 0)
1711 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1712 rs6000_tls_size = 16;
1713 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1714 rs6000_tls_size = 32;
1715 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1716 rs6000_tls_size = 64;
1718 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1722 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1726 /* Do anything needed at the start of the asm file. */
1729 rs6000_file_start (void)
1733 const char *start = buffer;
1734 struct rs6000_cpu_select *ptr;
1735 const char *default_cpu = TARGET_CPU_DEFAULT;
1736 FILE *file = asm_out_file;
1738 default_file_start ();
1740 #ifdef TARGET_BI_ARCH
1741 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1745 if (flag_verbose_asm)
1747 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1748 rs6000_select[0].string = default_cpu;
1750 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1752 ptr = &rs6000_select[i];
1753 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1755 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1760 #ifdef USING_ELFOS_H
1761 switch (rs6000_sdata)
1763 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1764 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1765 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1766 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1769 if (rs6000_sdata && g_switch_value)
1771 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1781 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1789 /* Return nonzero if this function is known to have a null epilogue. */
1792 direct_return (void)
1794 if (reload_completed)
1796 rs6000_stack_t *info = rs6000_stack_info ();
1798 if (info->first_gp_reg_save == 32
1799 && info->first_fp_reg_save == 64
1800 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1801 && ! info->lr_save_p
1802 && ! info->cr_save_p
1803 && info->vrsave_mask == 0
1811 /* Return the number of instructions it takes to form a constant in an
1812 integer register. */
1815 num_insns_constant_wide (HOST_WIDE_INT value)
1817 /* signed constant loadable with {cal|addi} */
1818 if (CONST_OK_FOR_LETTER_P (value, 'I'))
1821 /* constant loadable with {cau|addis} */
1822 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1825 #if HOST_BITS_PER_WIDE_INT == 64
1826 else if (TARGET_POWERPC64)
1828 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1829 HOST_WIDE_INT high = value >> 31;
1831 if (high == 0 || high == -1)
1837 return num_insns_constant_wide (high) + 1;
1839 return (num_insns_constant_wide (high)
1840 + num_insns_constant_wide (low) + 1);
1849 num_insns_constant (rtx op, enum machine_mode mode)
1851 if (GET_CODE (op) == CONST_INT)
1853 #if HOST_BITS_PER_WIDE_INT == 64
1854 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1855 && mask64_operand (op, mode))
1859 return num_insns_constant_wide (INTVAL (op));
1862 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
1867 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1868 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1869 return num_insns_constant_wide ((HOST_WIDE_INT) l);
1872 else if (GET_CODE (op) == CONST_DOUBLE)
1878 int endian = (WORDS_BIG_ENDIAN == 0);
1880 if (mode == VOIDmode || mode == DImode)
1882 high = CONST_DOUBLE_HIGH (op);
1883 low = CONST_DOUBLE_LOW (op);
1887 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1888 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1890 low = l[1 - endian];
1894 return (num_insns_constant_wide (low)
1895 + num_insns_constant_wide (high));
1899 if (high == 0 && low >= 0)
1900 return num_insns_constant_wide (low);
1902 else if (high == -1 && low < 0)
1903 return num_insns_constant_wide (low);
1905 else if (mask64_operand (op, mode))
1909 return num_insns_constant_wide (high) + 1;
1912 return (num_insns_constant_wide (high)
1913 + num_insns_constant_wide (low) + 1);
1921 /* Returns the constant for the splat instruction, if exists. */
1924 easy_vector_splat_const (int cst, enum machine_mode mode)
1929 if (EASY_VECTOR_15 (cst)
1930 || EASY_VECTOR_15_ADD_SELF (cst))
1932 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
1938 if (EASY_VECTOR_15 (cst)
1939 || EASY_VECTOR_15_ADD_SELF (cst))
1941 if ((cst & 0xff) != ((cst >> 8) & 0xff))
1947 if (EASY_VECTOR_15 (cst)
1948 || EASY_VECTOR_15_ADD_SELF (cst))
1956 /* Return nonzero if all elements of a vector have the same value. */
1959 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1963 units = CONST_VECTOR_NUNITS (op);
1965 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1966 for (i = 1; i < units; ++i)
1967 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
1969 if (i == units && easy_vector_splat_const (cst, mode))
1974 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
1977 gen_easy_vector_constant_add_self (rtx op)
1981 units = GET_MODE_NUNITS (GET_MODE (op));
1982 v = rtvec_alloc (units);
1984 for (i = 0; i < units; i++)
1986 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
1987 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
1991 output_vec_const_move (rtx *operands)
1994 enum machine_mode mode;
2000 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2001 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2002 mode = GET_MODE (dest);
2006 if (zero_constant (vec, mode))
2007 return "vxor %0,%0,%0";
2008 else if (easy_vector_constant (vec, mode))
2010 operands[1] = GEN_INT (cst);
2014 if (EASY_VECTOR_15 (cst))
2016 operands[1] = GEN_INT (cst);
2017 return "vspltisw %0,%1";
2019 else if (EASY_VECTOR_15_ADD_SELF (cst))
2025 if (EASY_VECTOR_15 (cst))
2027 operands[1] = GEN_INT (cst);
2028 return "vspltish %0,%1";
2030 else if (EASY_VECTOR_15_ADD_SELF (cst))
2036 if (EASY_VECTOR_15 (cst))
2038 operands[1] = GEN_INT (cst);
2039 return "vspltisb %0,%1";
2041 else if (EASY_VECTOR_15_ADD_SELF (cst))
2054 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2055 pattern of V1DI, V4HI, and V2SF.
2057 FIXME: We should probably return # and add post reload
2058 splitters for these, but this way is so easy ;-). */
2059 operands[1] = GEN_INT (cst);
2060 operands[2] = GEN_INT (cst2);
2062 return "li %0,%1\n\tevmergelo %0,%0,%0";
2064 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2071 mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED,
2074 if (GET_CODE (op) == CONST_INT)
2076 HOST_WIDE_INT c, lsb;
2081 /* Disallow all zeros. */
2085 /* We can use a single rlwinm insn if no upper bits of C are set
2086 AND there are zero, one or two transitions in the _whole_ of
2088 one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff);
2090 /* We don't change the number of transitions by inverting,
2091 so make sure we start with the LS bit zero. */
2095 /* Find the first transition. */
2098 /* Invert to look for a second transition. */
2101 /* Erase first transition. */
2104 /* Find the second transition. */
2107 /* Invert to look for a third transition. */
2110 /* Erase second transition. */
2113 if (one_ok && !(allow_one || c))
2116 /* Find the third transition (if any). */
2119 /* Match if all the bits above are 1's (or c is zero). */
2125 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2126 implement ANDing by the mask IN. */
2128 build_mask64_2_operands (rtx in, rtx *out)
2130 #if HOST_BITS_PER_WIDE_INT >= 64
2131 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2134 if (GET_CODE (in) != CONST_INT)
2140 /* Assume c initially something like 0x00fff000000fffff. The idea
2141 is to rotate the word so that the middle ^^^^^^ group of zeros
2142 is at the MS end and can be cleared with an rldicl mask. We then
2143 rotate back and clear off the MS ^^ group of zeros with a
2145 c = ~c; /* c == 0xff000ffffff00000 */
2146 lsb = c & -c; /* lsb == 0x0000000000100000 */
2147 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2148 c = ~c; /* c == 0x00fff000000fffff */
2149 c &= -lsb; /* c == 0x00fff00000000000 */
2150 lsb = c & -c; /* lsb == 0x0000100000000000 */
2151 c = ~c; /* c == 0xff000fffffffffff */
2152 c &= -lsb; /* c == 0xff00000000000000 */
2154 while ((lsb >>= 1) != 0)
2155 shift++; /* shift == 44 on exit from loop */
2156 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2157 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2158 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2162 /* Assume c initially something like 0xff000f0000000000. The idea
2163 is to rotate the word so that the ^^^ middle group of zeros
2164 is at the LS end and can be cleared with an rldicr mask. We then
2165 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2167 lsb = c & -c; /* lsb == 0x0000010000000000 */
2168 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2169 c = ~c; /* c == 0x00fff0ffffffffff */
2170 c &= -lsb; /* c == 0x00fff00000000000 */
2171 lsb = c & -c; /* lsb == 0x0000100000000000 */
2172 c = ~c; /* c == 0xff000fffffffffff */
2173 c &= -lsb; /* c == 0xff00000000000000 */
2175 while ((lsb >>= 1) != 0)
2176 shift++; /* shift == 44 on exit from loop */
2177 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2178 m1 >>= shift; /* m1 == 0x0000000000000fff */
2179 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2182 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2183 masks will be all 1's. We are guaranteed more than one transition. */
2184 out[0] = GEN_INT (64 - shift);
2185 out[1] = GEN_INT (m1);
2186 out[2] = GEN_INT (shift);
2187 out[3] = GEN_INT (m2);
2195 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2198 invalid_e500_subreg (rtx op, enum machine_mode mode)
2200 /* Reject (subreg:SI (reg:DF)). */
2201 if (GET_CODE (op) == SUBREG
2203 && REG_P (SUBREG_REG (op))
2204 && GET_MODE (SUBREG_REG (op)) == DFmode)
2207 /* Reject (subreg:DF (reg:DI)). */
2208 if (GET_CODE (op) == SUBREG
2210 && REG_P (SUBREG_REG (op))
2211 && GET_MODE (SUBREG_REG (op)) == DImode)
2217 /* Darwin, AIX increases natural record alignment to doubleword if the first
2218 field is an FP double while the FP fields remain word aligned. */
2221 rs6000_special_round_type_align (tree type, int computed, int specified)
2223 tree field = TYPE_FIELDS (type);
2225 /* Skip all non field decls */
2226 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2227 field = TREE_CHAIN (field);
2229 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
2230 return MAX (computed, specified);
2232 return MAX (MAX (computed, specified), 64);
2235 /* Return 1 for an operand in small memory on V.4/eabi. */
2238 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2239 enum machine_mode mode ATTRIBUTE_UNUSED)
2244 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2247 if (DEFAULT_ABI != ABI_V4)
2250 if (GET_CODE (op) == SYMBOL_REF)
2253 else if (GET_CODE (op) != CONST
2254 || GET_CODE (XEXP (op, 0)) != PLUS
2255 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2256 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2261 rtx sum = XEXP (op, 0);
2262 HOST_WIDE_INT summand;
2264 /* We have to be careful here, because it is the referenced address
2265 that must be 32k from _SDA_BASE_, not just the symbol. */
2266 summand = INTVAL (XEXP (sum, 1));
2267 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2270 sym_ref = XEXP (sum, 0);
2273 return SYMBOL_REF_SMALL_P (sym_ref);
2279 /* Return true if either operand is a general purpose register. */
2282 gpr_or_gpr_p (rtx op0, rtx op1)
2284 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2285 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2289 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2292 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2294 switch (GET_CODE (op))
2297 if (RS6000_SYMBOL_REF_TLS_P (op))
2299 else if (CONSTANT_POOL_ADDRESS_P (op))
2301 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2309 else if (! strcmp (XSTR (op, 0), toc_label_name))
2318 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2319 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2321 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2330 constant_pool_expr_p (rtx op)
2334 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2338 toc_relative_expr_p (rtx op)
2342 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2346 legitimate_constant_pool_address_p (rtx x)
2349 && GET_CODE (x) == PLUS
2350 && GET_CODE (XEXP (x, 0)) == REG
2351 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2352 && constant_pool_expr_p (XEXP (x, 1)));
2356 legitimate_small_data_p (enum machine_mode mode, rtx x)
2358 return (DEFAULT_ABI == ABI_V4
2359 && !flag_pic && !TARGET_TOC
2360 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2361 && small_data_operand (x, mode));
2364 /* SPE offset addressing is limited to 5-bits worth of double words. */
2365 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2368 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2370 unsigned HOST_WIDE_INT offset, extra;
2372 if (GET_CODE (x) != PLUS)
2374 if (GET_CODE (XEXP (x, 0)) != REG)
2376 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2378 if (legitimate_constant_pool_address_p (x))
2380 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2383 offset = INTVAL (XEXP (x, 1));
2391 /* AltiVec vector modes. Only reg+reg addressing is valid here,
2392 which leaves the only valid constant offset of zero, which by
2393 canonicalization rules is also invalid. */
2400 /* SPE vector modes. */
2401 return SPE_CONST_OFFSET_OK (offset);
2404 if (TARGET_E500_DOUBLE)
2405 return SPE_CONST_OFFSET_OK (offset);
2408 /* On e500v2, we may have:
2410 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2412 Which gets addressed with evldd instructions. */
2413 if (TARGET_E500_DOUBLE)
2414 return SPE_CONST_OFFSET_OK (offset);
2416 if (mode == DFmode || !TARGET_POWERPC64)
2418 else if (offset & 3)
2424 if (mode == TFmode || !TARGET_POWERPC64)
2426 else if (offset & 3)
2437 return (offset < 0x10000) && (offset + extra < 0x10000);
2441 legitimate_indexed_address_p (rtx x, int strict)
2445 if (GET_CODE (x) != PLUS)
2451 if (!REG_P (op0) || !REG_P (op1))
2454 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2455 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2456 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2457 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
2461 legitimate_indirect_address_p (rtx x, int strict)
2463 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2467 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2469 if (!TARGET_MACHO || !flag_pic
2470 || mode != SImode || GET_CODE (x) != MEM)
2474 if (GET_CODE (x) != LO_SUM)
2476 if (GET_CODE (XEXP (x, 0)) != REG)
2478 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2482 return CONSTANT_P (x);
2486 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2488 if (GET_CODE (x) != LO_SUM)
2490 if (GET_CODE (XEXP (x, 0)) != REG)
2492 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2494 /* Restrict addressing for DI because of our SUBREG hackery. */
2495 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
2499 if (TARGET_ELF || TARGET_MACHO)
2501 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2505 if (GET_MODE_NUNITS (mode) != 1)
2507 if (GET_MODE_BITSIZE (mode) > 64
2508 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2509 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
2512 return CONSTANT_P (x);
2519 /* Try machine-dependent ways of modifying an illegitimate address
2520 to be legitimate. If we find one, return the new, valid address.
2521 This is used from only one place: `memory_address' in explow.c.
2523 OLDX is the address as it was before break_out_memory_refs was
2524 called. In some cases it is useful to look at this to decide what
2527 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2529 It is always safe for this function to do nothing. It exists to
2530 recognize opportunities to optimize the output.
2532 On RS/6000, first check for the sum of a register with a constant
2533 integer that is out of range. If so, generate code to add the
2534 constant with the low-order 16 bits masked to the register and force
2535 this result into another register (this can be done with `cau').
2536 Then generate an address of REG+(CONST&0xffff), allowing for the
2537 possibility of bit 16 being a one.
2539 Then check for the sum of a register and something not constant, try to
2540 load the other things into a register and return the sum. */
2543 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2544 enum machine_mode mode)
2546 if (GET_CODE (x) == SYMBOL_REF)
2548 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2550 return rs6000_legitimize_tls_address (x, model);
2553 if (GET_CODE (x) == PLUS
2554 && GET_CODE (XEXP (x, 0)) == REG
2555 && GET_CODE (XEXP (x, 1)) == CONST_INT
2556 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2558 HOST_WIDE_INT high_int, low_int;
2560 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2561 high_int = INTVAL (XEXP (x, 1)) - low_int;
2562 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2563 GEN_INT (high_int)), 0);
2564 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2566 else if (GET_CODE (x) == PLUS
2567 && GET_CODE (XEXP (x, 0)) == REG
2568 && GET_CODE (XEXP (x, 1)) != CONST_INT
2569 && GET_MODE_NUNITS (mode) == 1
2570 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2572 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2574 && (TARGET_POWERPC64 || mode != DImode)
2577 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2578 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2580 else if (ALTIVEC_VECTOR_MODE (mode))
2584 /* Make sure both operands are registers. */
2585 if (GET_CODE (x) == PLUS)
2586 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2587 force_reg (Pmode, XEXP (x, 1)));
2589 reg = force_reg (Pmode, x);
2592 else if (SPE_VECTOR_MODE (mode)
2593 || (TARGET_E500_DOUBLE && (mode == DFmode
2594 || mode == DImode)))
2598 /* We accept [reg + reg] and [reg + OFFSET]. */
2600 if (GET_CODE (x) == PLUS)
2602 rtx op1 = XEXP (x, 0);
2603 rtx op2 = XEXP (x, 1);
2605 op1 = force_reg (Pmode, op1);
2607 if (GET_CODE (op2) != REG
2608 && (GET_CODE (op2) != CONST_INT
2609 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2610 op2 = force_reg (Pmode, op2);
2612 return gen_rtx_PLUS (Pmode, op1, op2);
2615 return force_reg (Pmode, x);
2621 && GET_CODE (x) != CONST_INT
2622 && GET_CODE (x) != CONST_DOUBLE
2624 && GET_MODE_NUNITS (mode) == 1
2625 && (GET_MODE_BITSIZE (mode) <= 32
2626 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2628 rtx reg = gen_reg_rtx (Pmode);
2629 emit_insn (gen_elf_high (reg, x));
2630 return gen_rtx_LO_SUM (Pmode, reg, x);
2632 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2635 && ! MACHO_DYNAMIC_NO_PIC_P
2637 && GET_CODE (x) != CONST_INT
2638 && GET_CODE (x) != CONST_DOUBLE
2640 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2644 rtx reg = gen_reg_rtx (Pmode);
2645 emit_insn (gen_macho_high (reg, x));
2646 return gen_rtx_LO_SUM (Pmode, reg, x);
2649 && constant_pool_expr_p (x)
2650 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2652 return create_TOC_reference (x);
2658 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
2659 We need to emit DTP-relative relocations. */
2662 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
2667 fputs ("\t.long\t", file);
2670 fputs (DOUBLE_INT_ASM_OP, file);
2675 output_addr_const (file, x);
2676 fputs ("@dtprel+0x8000", file);
2679 /* Construct the SYMBOL_REF for the tls_get_addr function. */
2681 static GTY(()) rtx rs6000_tls_symbol;
2683 rs6000_tls_get_addr (void)
2685 if (!rs6000_tls_symbol)
2686 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2688 return rs6000_tls_symbol;
2691 /* Construct the SYMBOL_REF for TLS GOT references. */
2693 static GTY(()) rtx rs6000_got_symbol;
2695 rs6000_got_sym (void)
2697 if (!rs6000_got_symbol)
2699 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2700 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2701 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
2704 return rs6000_got_symbol;
2707 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2708 this (thread-local) address. */
2711 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
2715 dest = gen_reg_rtx (Pmode);
2716 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
2722 tlsreg = gen_rtx_REG (Pmode, 13);
2723 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
2727 tlsreg = gen_rtx_REG (Pmode, 2);
2728 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
2732 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
2736 tmp = gen_reg_rtx (Pmode);
2739 tlsreg = gen_rtx_REG (Pmode, 13);
2740 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
2744 tlsreg = gen_rtx_REG (Pmode, 2);
2745 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
2749 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
2751 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
2756 rtx r3, got, tga, tmp1, tmp2, eqv;
2759 got = gen_rtx_REG (Pmode, TOC_REGISTER);
2763 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
2766 rtx gsym = rs6000_got_sym ();
2767 got = gen_reg_rtx (Pmode);
2769 rs6000_emit_move (got, gsym, Pmode);
2772 rtx tempLR, tmp3, mem;
2775 tempLR = gen_reg_rtx (Pmode);
2776 tmp1 = gen_reg_rtx (Pmode);
2777 tmp2 = gen_reg_rtx (Pmode);
2778 tmp3 = gen_reg_rtx (Pmode);
2779 mem = gen_const_mem (Pmode, tmp1);
2781 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
2782 emit_move_insn (tmp1, tempLR);
2783 emit_move_insn (tmp2, mem);
2784 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
2785 last = emit_move_insn (got, tmp3);
2786 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
2788 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
2790 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
2796 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
2798 r3 = gen_rtx_REG (Pmode, 3);
2800 insn = gen_tls_gd_64 (r3, got, addr);
2802 insn = gen_tls_gd_32 (r3, got, addr);
2805 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2806 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2807 insn = emit_call_insn (insn);
2808 CONST_OR_PURE_CALL_P (insn) = 1;
2809 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2810 insn = get_insns ();
2812 emit_libcall_block (insn, dest, r3, addr);
2814 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
2816 r3 = gen_rtx_REG (Pmode, 3);
2818 insn = gen_tls_ld_64 (r3, got);
2820 insn = gen_tls_ld_32 (r3, got);
2823 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2824 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2825 insn = emit_call_insn (insn);
2826 CONST_OR_PURE_CALL_P (insn) = 1;
2827 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2828 insn = get_insns ();
2830 tmp1 = gen_reg_rtx (Pmode);
2831 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2833 emit_libcall_block (insn, tmp1, r3, eqv);
2834 if (rs6000_tls_size == 16)
2837 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
2839 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
2841 else if (rs6000_tls_size == 32)
2843 tmp2 = gen_reg_rtx (Pmode);
2845 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
2847 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
2850 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
2852 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
2856 tmp2 = gen_reg_rtx (Pmode);
2858 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
2860 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
2862 insn = gen_rtx_SET (Pmode, dest,
2863 gen_rtx_PLUS (Pmode, tmp2, tmp1));
2869 /* IE, or 64 bit offset LE. */
2870 tmp2 = gen_reg_rtx (Pmode);
2872 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
2874 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
2877 insn = gen_tls_tls_64 (dest, tmp2, addr);
2879 insn = gen_tls_tls_32 (dest, tmp2, addr);
2887 /* Return 1 if X contains a thread-local symbol. */
2890 rs6000_tls_referenced_p (rtx x)
2892 if (! TARGET_HAVE_TLS)
2895 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
2898 /* Return 1 if *X is a thread-local symbol. This is the same as
2899 rs6000_tls_symbol_ref except for the type of the unused argument. */
2902 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
2904 return RS6000_SYMBOL_REF_TLS_P (*x);
2907 /* The convention appears to be to define this wherever it is used.
2908 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
2909 is now used here. */
2910 #ifndef REG_MODE_OK_FOR_BASE_P
2911 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
2914 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
2915 replace the input X, or the original X if no replacement is called for.
2916 The output parameter *WIN is 1 if the calling macro should goto WIN,
2919 For RS/6000, we wish to handle large displacements off a base
2920 register by splitting the addend across an addiu/addis and the mem insn.
2921 This cuts number of extra insns needed from 3 to 1.
2923 On Darwin, we use this to generate code for floating point constants.
2924 A movsf_low is generated so we wind up with 2 instructions rather than 3.
2925 The Darwin code is inside #if TARGET_MACHO because only then is
2926 machopic_function_base_name() defined. */
2928 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
2929 int opnum, int type,
2930 int ind_levels ATTRIBUTE_UNUSED, int *win)
2932 /* We must recognize output that we have already generated ourselves. */
2933 if (GET_CODE (x) == PLUS
2934 && GET_CODE (XEXP (x, 0)) == PLUS
2935 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2936 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2937 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2939 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2940 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2941 opnum, (enum reload_type)type);
2947 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
2948 && GET_CODE (x) == LO_SUM
2949 && GET_CODE (XEXP (x, 0)) == PLUS
2950 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
2951 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
2952 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
2953 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
2954 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
2955 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
2956 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
2958 /* Result of previous invocation of this function on Darwin
2959 floating point constant. */
2960 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2961 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
2962 opnum, (enum reload_type)type);
2968 /* Force ld/std non-word aligned offset into base register by wrapping
2970 if (GET_CODE (x) == PLUS
2971 && GET_CODE (XEXP (x, 0)) == REG
2972 && REGNO (XEXP (x, 0)) < 32
2973 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
2974 && GET_CODE (XEXP (x, 1)) == CONST_INT
2975 && (INTVAL (XEXP (x, 1)) & 3) != 0
2976 && !ALTIVEC_VECTOR_MODE (mode)
2977 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
2978 && TARGET_POWERPC64)
2980 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
2981 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2982 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2983 opnum, (enum reload_type) type);
2988 if (GET_CODE (x) == PLUS
2989 && GET_CODE (XEXP (x, 0)) == REG
2990 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2991 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
2992 && GET_CODE (XEXP (x, 1)) == CONST_INT
2993 && !SPE_VECTOR_MODE (mode)
2994 && !(TARGET_E500_DOUBLE && (mode == DFmode
2996 && !ALTIVEC_VECTOR_MODE (mode))
2998 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2999 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3001 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3003 /* Check for 32-bit overflow. */
3004 if (high + low != val)
3010 /* Reload the high part into a base reg; leave the low part
3011 in the mem directly. */
3013 x = gen_rtx_PLUS (GET_MODE (x),
3014 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3018 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3019 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3020 opnum, (enum reload_type)type);
3026 if (GET_CODE (x) == SYMBOL_REF
3027 && DEFAULT_ABI == ABI_DARWIN
3028 && !ALTIVEC_VECTOR_MODE (mode)
3029 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3030 /* Don't do this for TFmode, since the result isn't offsettable.
3031 The same goes for DImode without 64-bit gprs. */
3033 && (mode != DImode || TARGET_POWERPC64))
3037 rtx offset = gen_rtx_CONST (Pmode,
3038 gen_rtx_MINUS (Pmode, x,
3039 machopic_function_base_sym ()));
3040 x = gen_rtx_LO_SUM (GET_MODE (x),
3041 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3042 gen_rtx_HIGH (Pmode, offset)), offset);
3045 x = gen_rtx_LO_SUM (GET_MODE (x),
3046 gen_rtx_HIGH (Pmode, x), x);
3048 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3049 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3050 opnum, (enum reload_type)type);
3057 && constant_pool_expr_p (x)
3058 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3060 (x) = create_TOC_reference (x);
3068 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3069 that is a valid memory address for an instruction.
3070 The MODE argument is the machine mode for the MEM expression
3071 that wants to use this address.
3073 On the RS/6000, there are four valid address: a SYMBOL_REF that
3074 refers to a constant pool entry of an address (or the sum of it
3075 plus a constant), a short (16-bit signed) constant plus a register,
3076 the sum of two registers, or a register indirect, possibly with an
3077 auto-increment. For DFmode and DImode with a constant plus register,
3078 we must ensure that both words are addressable or PowerPC64 with offset
3081 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3082 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3083 adjacent memory cells are accessed by adding word-sized offsets
3084 during assembly output. */
3086 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3088 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3090 && ALTIVEC_VECTOR_MODE (mode)
3091 && GET_CODE (x) == AND
3092 && GET_CODE (XEXP (x, 1)) == CONST_INT
3093 && INTVAL (XEXP (x, 1)) == -16)
3096 if (RS6000_SYMBOL_REF_TLS_P (x))
3098 if (legitimate_indirect_address_p (x, reg_ok_strict))
3100 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3101 && !ALTIVEC_VECTOR_MODE (mode)
3102 && !SPE_VECTOR_MODE (mode)
3103 /* Restrict addressing for DI because of our SUBREG hackery. */
3104 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3106 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3108 if (legitimate_small_data_p (mode, x))
3110 if (legitimate_constant_pool_address_p (x))
3112 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3114 && GET_CODE (x) == PLUS
3115 && GET_CODE (XEXP (x, 0)) == REG
3116 && (XEXP (x, 0) == virtual_stack_vars_rtx
3117 || XEXP (x, 0) == arg_pointer_rtx)
3118 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3120 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3124 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3126 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3127 && (TARGET_POWERPC64 || mode != DImode)
3128 && legitimate_indexed_address_p (x, reg_ok_strict))
3130 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3135 /* Go to LABEL if ADDR (a legitimate address expression)
3136 has an effect that depends on the machine mode it is used for.
3138 On the RS/6000 this is true of all integral offsets (since AltiVec
3139 modes don't allow them) or is a pre-increment or decrement.
3141 ??? Except that due to conceptual problems in offsettable_address_p
3142 we can't really report the problems of integral offsets. So leave
3143 this assuming that the adjustable offset must be valid for the
3144 sub-words of a TFmode operand, which is what we had before. */
3147 rs6000_mode_dependent_address (rtx addr)
3149 switch (GET_CODE (addr))
3152 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3154 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3155 return val + 12 + 0x8000 >= 0x10000;
3164 return TARGET_UPDATE;
3173 /* Return number of consecutive hard regs needed starting at reg REGNO
3174 to hold something of mode MODE.
3175 This is ordinarily the length in words of a value of mode MODE
3176 but can be less for certain modes in special long registers.
3178 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3179 scalar instructions. The upper 32 bits are only available to the
3182 POWER and PowerPC GPRs hold 32 bits worth;
3183 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3186 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3188 if (FP_REGNO_P (regno))
3189 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3191 if (TARGET_E500_DOUBLE && mode == DFmode)
3194 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3195 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3197 if (ALTIVEC_REGNO_P (regno))
3199 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3201 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3204 /* Change register usage conditional on target flags. */
3206 rs6000_conditional_register_usage (void)
3210 /* Set MQ register fixed (already call_used) if not POWER
3211 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3216 /* 64-bit AIX reserves GPR13 for thread-private data. */
3218 fixed_regs[13] = call_used_regs[13]
3219 = call_really_used_regs[13] = 1;
3221 /* Conditionally disable FPRs. */
3222 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3223 for (i = 32; i < 64; i++)
3224 fixed_regs[i] = call_used_regs[i]
3225 = call_really_used_regs[i] = 1;
3227 if (DEFAULT_ABI == ABI_V4
3228 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3230 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3232 if (DEFAULT_ABI == ABI_V4
3233 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3235 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3236 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3237 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3239 if (DEFAULT_ABI == ABI_DARWIN
3240 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3241 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3242 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3243 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3244 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3246 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3247 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3248 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3251 global_regs[VSCR_REGNO] = 1;
3255 global_regs[SPEFSCR_REGNO] = 1;
3256 fixed_regs[FIXED_SCRATCH]
3257 = call_used_regs[FIXED_SCRATCH]
3258 = call_really_used_regs[FIXED_SCRATCH] = 1;
3261 if (! TARGET_ALTIVEC)
3263 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3264 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3265 call_really_used_regs[VRSAVE_REGNO] = 1;
3268 if (TARGET_ALTIVEC_ABI)
3269 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3270 call_used_regs[i] = call_really_used_regs[i] = 1;
3273 /* Try to output insns to set TARGET equal to the constant C if it can
3274 be done in less than N insns. Do all computations in MODE.
3275 Returns the place where the output has been placed if it can be
3276 done and the insns have been emitted. If it would take more than N
3277 insns, zero is returned and no insns and emitted. */
3280 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3281 rtx source, int n ATTRIBUTE_UNUSED)
3283 rtx result, insn, set;
3284 HOST_WIDE_INT c0, c1;
3286 if (mode == QImode || mode == HImode)
3289 dest = gen_reg_rtx (mode);
3290 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3293 else if (mode == SImode)
3295 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3297 emit_insn (gen_rtx_SET (VOIDmode, result,
3298 GEN_INT (INTVAL (source)
3299 & (~ (HOST_WIDE_INT) 0xffff))));
3300 emit_insn (gen_rtx_SET (VOIDmode, dest,
3301 gen_rtx_IOR (SImode, result,
3302 GEN_INT (INTVAL (source) & 0xffff))));
3305 else if (mode == DImode)
3307 if (GET_CODE (source) == CONST_INT)
3309 c0 = INTVAL (source);
3312 else if (GET_CODE (source) == CONST_DOUBLE)
3314 #if HOST_BITS_PER_WIDE_INT >= 64
3315 c0 = CONST_DOUBLE_LOW (source);
3318 c0 = CONST_DOUBLE_LOW (source);
3319 c1 = CONST_DOUBLE_HIGH (source);
3325 result = rs6000_emit_set_long_const (dest, c0, c1);
3330 insn = get_last_insn ();
3331 set = single_set (insn);
3332 if (! CONSTANT_P (SET_SRC (set)))
3333 set_unique_reg_note (insn, REG_EQUAL, source);
3338 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3339 fall back to a straight forward decomposition. We do this to avoid
3340 exponential run times encountered when looking for longer sequences
3341 with rs6000_emit_set_const. */
3343 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3345 if (!TARGET_POWERPC64)
3347 rtx operand1, operand2;
3349 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3351 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3353 emit_move_insn (operand1, GEN_INT (c1));
3354 emit_move_insn (operand2, GEN_INT (c2));
3358 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3361 ud2 = (c1 & 0xffff0000) >> 16;
3362 #if HOST_BITS_PER_WIDE_INT >= 64
3366 ud4 = (c2 & 0xffff0000) >> 16;
3368 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3369 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3372 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3374 emit_move_insn (dest, GEN_INT (ud1));
3377 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3378 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3381 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3384 emit_move_insn (dest, GEN_INT (ud2 << 16));
3386 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3388 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3389 || (ud4 == 0 && ! (ud3 & 0x8000)))
3392 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3395 emit_move_insn (dest, GEN_INT (ud3 << 16));
3398 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3399 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3401 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3406 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3409 emit_move_insn (dest, GEN_INT (ud4 << 16));
3412 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3414 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3416 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3417 GEN_INT (ud2 << 16)));
3419 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3425 /* Helper for the following. Get rid of [r+r] memory refs
3426 in cases where it won't work (TImode, TFmode). */
3429 rs6000_eliminate_indexed_memrefs (rtx operands[2])
3431 if (GET_CODE (operands[0]) == MEM
3432 && GET_CODE (XEXP (operands[0], 0)) != REG
3433 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
3434 && ! reload_in_progress)
3436 = replace_equiv_address (operands[0],
3437 copy_addr_to_reg (XEXP (operands[0], 0)));
3439 if (GET_CODE (operands[1]) == MEM
3440 && GET_CODE (XEXP (operands[1], 0)) != REG
3441 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
3442 && ! reload_in_progress)
3444 = replace_equiv_address (operands[1],
3445 copy_addr_to_reg (XEXP (operands[1], 0)));
3448 /* Emit a move from SOURCE to DEST in mode MODE. */
3450 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3454 operands[1] = source;
3456 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3457 if (GET_CODE (operands[1]) == CONST_DOUBLE
3458 && ! FLOAT_MODE_P (mode)
3459 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3461 /* FIXME. This should never happen. */
3462 /* Since it seems that it does, do the safe thing and convert
3464 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3466 if (GET_CODE (operands[1]) == CONST_DOUBLE
3467 && ! FLOAT_MODE_P (mode)
3468 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
3469 && CONST_DOUBLE_LOW (operands[1]) >= 0)
3470 || (CONST_DOUBLE_HIGH (operands[1]) == -1
3471 && CONST_DOUBLE_LOW (operands[1]) < 0)))
3474 /* Check if GCC is setting up a block move that will end up using FP
3475 registers as temporaries. We must make sure this is acceptable. */
3476 if (GET_CODE (operands[0]) == MEM
3477 && GET_CODE (operands[1]) == MEM
3479 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3480 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3481 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3482 ? 32 : MEM_ALIGN (operands[0])))
3483 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3485 : MEM_ALIGN (operands[1]))))
3486 && ! MEM_VOLATILE_P (operands [0])
3487 && ! MEM_VOLATILE_P (operands [1]))
3489 emit_move_insn (adjust_address (operands[0], SImode, 0),
3490 adjust_address (operands[1], SImode, 0));
3491 emit_move_insn (adjust_address (operands[0], SImode, 4),
3492 adjust_address (operands[1], SImode, 4));
3496 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
3497 && !gpc_reg_operand (operands[1], mode))
3498 operands[1] = force_reg (mode, operands[1]);
3500 if (mode == SFmode && ! TARGET_POWERPC
3501 && TARGET_HARD_FLOAT && TARGET_FPRS
3502 && GET_CODE (operands[0]) == MEM)
3506 if (reload_in_progress || reload_completed)
3507 regnum = true_regnum (operands[1]);
3508 else if (GET_CODE (operands[1]) == REG)
3509 regnum = REGNO (operands[1]);
3513 /* If operands[1] is a register, on POWER it may have
3514 double-precision data in it, so truncate it to single
3516 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3519 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3520 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3521 operands[1] = newreg;
3525 /* Recognize the case where operand[1] is a reference to thread-local
3526 data and load its address to a register. */
3527 if (GET_CODE (operands[1]) == SYMBOL_REF)
3529 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
3531 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
3534 /* Handle the case where reload calls us with an invalid address. */
3535 if (reload_in_progress && mode == Pmode
3536 && (! general_operand (operands[1], mode)
3537 || ! nonimmediate_operand (operands[0], mode)))
3540 /* 128-bit constant floating-point values on Darwin should really be
3541 loaded as two parts. */
3542 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3543 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3544 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3546 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3547 know how to get a DFmode SUBREG of a TFmode. */
3548 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3549 simplify_gen_subreg (DImode, operands[1], mode, 0),
3551 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3552 GET_MODE_SIZE (DImode)),
3553 simplify_gen_subreg (DImode, operands[1], mode,
3554 GET_MODE_SIZE (DImode)),
3559 /* FIXME: In the long term, this switch statement should go away
3560 and be replaced by a sequence of tests based on things like
3566 if (CONSTANT_P (operands[1])
3567 && GET_CODE (operands[1]) != CONST_INT)
3568 operands[1] = force_const_mem (mode, operands[1]);
3572 rs6000_eliminate_indexed_memrefs (operands);
3577 if (CONSTANT_P (operands[1])
3578 && ! easy_fp_constant (operands[1], mode))
3579 operands[1] = force_const_mem (mode, operands[1]);
3590 if (CONSTANT_P (operands[1])
3591 && !easy_vector_constant (operands[1], mode))
3592 operands[1] = force_const_mem (mode, operands[1]);
3597 /* Use default pattern for address of ELF small data */
3600 && DEFAULT_ABI == ABI_V4
3601 && (GET_CODE (operands[1]) == SYMBOL_REF
3602 || GET_CODE (operands[1]) == CONST)
3603 && small_data_operand (operands[1], mode))
3605 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3609 if (DEFAULT_ABI == ABI_V4
3610 && mode == Pmode && mode == SImode
3611 && flag_pic == 1 && got_operand (operands[1], mode))
3613 emit_insn (gen_movsi_got (operands[0], operands[1]));
3617 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
3621 && CONSTANT_P (operands[1])
3622 && GET_CODE (operands[1]) != HIGH
3623 && GET_CODE (operands[1]) != CONST_INT)
3625 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
3627 /* If this is a function address on -mcall-aixdesc,
3628 convert it to the address of the descriptor. */
3629 if (DEFAULT_ABI == ABI_AIX
3630 && GET_CODE (operands[1]) == SYMBOL_REF
3631 && XSTR (operands[1], 0)[0] == '.')
3633 const char *name = XSTR (operands[1], 0);
3635 while (*name == '.')
3637 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3638 CONSTANT_POOL_ADDRESS_P (new_ref)
3639 = CONSTANT_POOL_ADDRESS_P (operands[1]);
3640 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
3641 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
3642 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
3643 operands[1] = new_ref;
3646 if (DEFAULT_ABI == ABI_DARWIN)
3649 if (MACHO_DYNAMIC_NO_PIC_P)
3651 /* Take care of any required data indirection. */
3652 operands[1] = rs6000_machopic_legitimize_pic_address (
3653 operands[1], mode, operands[0]);
3654 if (operands[0] != operands[1])
3655 emit_insn (gen_rtx_SET (VOIDmode,
3656 operands[0], operands[1]));
3660 emit_insn (gen_macho_high (target, operands[1]));
3661 emit_insn (gen_macho_low (operands[0], target, operands[1]));
3665 emit_insn (gen_elf_high (target, operands[1]));
3666 emit_insn (gen_elf_low (operands[0], target, operands[1]));
3670 /* If this is a SYMBOL_REF that refers to a constant pool entry,
3671 and we have put it in the TOC, we just need to make a TOC-relative
3674 && GET_CODE (operands[1]) == SYMBOL_REF
3675 && constant_pool_expr_p (operands[1])
3676 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
3677 get_pool_mode (operands[1])))
3679 operands[1] = create_TOC_reference (operands[1]);
3681 else if (mode == Pmode
3682 && CONSTANT_P (operands[1])
3683 && ((GET_CODE (operands[1]) != CONST_INT
3684 && ! easy_fp_constant (operands[1], mode))
3685 || (GET_CODE (operands[1]) == CONST_INT
3686 && num_insns_constant (operands[1], mode) > 2)
3687 || (GET_CODE (operands[0]) == REG
3688 && FP_REGNO_P (REGNO (operands[0]))))
3689 && GET_CODE (operands[1]) != HIGH
3690 && ! legitimate_constant_pool_address_p (operands[1])
3691 && ! toc_relative_expr_p (operands[1]))
3693 /* Emit a USE operation so that the constant isn't deleted if
3694 expensive optimizations are turned on because nobody
3695 references it. This should only be done for operands that
3696 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3697 This should not be done for operands that contain LABEL_REFs.
3698 For now, we just handle the obvious case. */
3699 if (GET_CODE (operands[1]) != LABEL_REF)
3700 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
3703 /* Darwin uses a special PIC legitimizer. */
3704 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
3707 rs6000_machopic_legitimize_pic_address (operands[1], mode,
3709 if (operands[0] != operands[1])
3710 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3715 /* If we are to limit the number of things we put in the TOC and
3716 this is a symbol plus a constant we can add in one insn,
3717 just put the symbol in the TOC and add the constant. Don't do
3718 this if reload is in progress. */
3719 if (GET_CODE (operands[1]) == CONST
3720 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3721 && GET_CODE (XEXP (operands[1], 0)) == PLUS
3722 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
3723 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3724 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3725 && ! side_effects_p (operands[0]))
3728 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
3729 rtx other = XEXP (XEXP (operands[1], 0), 1);
3731 sym = force_reg (mode, sym);
3733 emit_insn (gen_addsi3 (operands[0], sym, other));
3735 emit_insn (gen_adddi3 (operands[0], sym, other));
3739 operands[1] = force_const_mem (mode, operands[1]);
3742 && constant_pool_expr_p (XEXP (operands[1], 0))
3743 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
3744 get_pool_constant (XEXP (operands[1], 0)),
3745 get_pool_mode (XEXP (operands[1], 0))))
3748 = gen_const_mem (mode,
3749 create_TOC_reference (XEXP (operands[1], 0)));
3750 set_mem_alias_set (operands[1], get_TOC_alias_set ());
3756 rs6000_eliminate_indexed_memrefs (operands);
3760 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3762 gen_rtx_SET (VOIDmode,
3763 operands[0], operands[1]),
3764 gen_rtx_CLOBBER (VOIDmode,
3765 gen_rtx_SCRATCH (SImode)))));
3774 /* Above, we may have called force_const_mem which may have returned
3775 an invalid address. If we can, fix this up; otherwise, reload will
3776 have to deal with it. */
3777 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
3778 operands[1] = validize_mem (operands[1]);
3781 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3784 /* Nonzero if we can use a floating-point register to pass this arg. */
3785 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
3786 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
3787 && (CUM)->fregno <= FP_ARG_MAX_REG \
3788 && TARGET_HARD_FLOAT && TARGET_FPRS)
3790 /* Nonzero if we can use an AltiVec register to pass this arg. */
3791 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
3792 (ALTIVEC_VECTOR_MODE (MODE) \
3793 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
3794 && TARGET_ALTIVEC_ABI \
3797 /* Return a nonzero value to say to return the function value in
3798 memory, just as large structures are always returned. TYPE will be
3799 the data type of the value, and FNTYPE will be the type of the
3800 function doing the returning, or @code{NULL} for libcalls.
3802 The AIX ABI for the RS/6000 specifies that all structures are
3803 returned in memory. The Darwin ABI does the same. The SVR4 ABI
3804 specifies that structures <= 8 bytes are returned in r3/r4, but a
3805 draft put them in memory, and GCC used to implement the draft
3806 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
3807 controls this instead of DEFAULT_ABI; V.4 targets needing backward
3808 compatibility can change DRAFT_V4_STRUCT_RET to override the
3809 default, and -m switches get the final word. See
3810 rs6000_override_options for more details.
3812 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
3813 long double support is enabled. These values are returned in memory.
3815 int_size_in_bytes returns -1 for variable size objects, which go in
3816 memory always. The cast to unsigned makes -1 > 8. */
3819 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3821 /* In the darwin64 abi, try to use registers for larger structs
3823 if (rs6000_darwin64_abi
3824 && TREE_CODE (type) == RECORD_TYPE
3825 && int_size_in_bytes (type) > 0)
3827 CUMULATIVE_ARGS valcum;
3831 valcum.fregno = FP_ARG_MIN_REG;
3832 valcum.vregno = ALTIVEC_ARG_MIN_REG;
3833 /* Do a trial code generation as if this were going to be passed
3834 as an argument; if any part goes in memory, we return NULL. */
3835 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
3838 /* Otherwise fall through to more conventional ABI rules. */
3841 if (AGGREGATE_TYPE_P (type)
3842 && (TARGET_AIX_STRUCT_RET
3843 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
3846 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
3847 modes only exist for GCC vector types if -maltivec. */
3848 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
3849 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
3852 /* Return synthetic vectors in memory. */
3853 if (TREE_CODE (type) == VECTOR_TYPE
3854 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
3856 static bool warned_for_return_big_vectors = false;
3857 if (!warned_for_return_big_vectors)
3859 warning ("GCC vector returned by reference: "
3860 "non-standard ABI extension with no compatibility guarantee");
3861 warned_for_return_big_vectors = true;
3866 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
3872 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3873 for a call to a function whose data type is FNTYPE.
3874 For a library call, FNTYPE is 0.
3876 For incoming args we set the number of arguments in the prototype large
3877 so we never return a PARALLEL. */
3880 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3881 rtx libname ATTRIBUTE_UNUSED, int incoming,
3882 int libcall, int n_named_args)
3884 static CUMULATIVE_ARGS zero_cumulative;
3886 *cum = zero_cumulative;
3888 cum->fregno = FP_ARG_MIN_REG;
3889 cum->vregno = ALTIVEC_ARG_MIN_REG;
3890 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3891 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
3892 ? CALL_LIBCALL : CALL_NORMAL);
3893 cum->sysv_gregno = GP_ARG_MIN_REG;
3894 cum->stdarg = fntype
3895 && (TYPE_ARG_TYPES (fntype) != 0
3896 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3897 != void_type_node));
3899 cum->nargs_prototype = 0;
3900 if (incoming || cum->prototype)
3901 cum->nargs_prototype = n_named_args;
3903 /* Check for a longcall attribute. */
3904 if ((!fntype && rs6000_default_long_calls)
3906 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
3907 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
3908 cum->call_cookie |= CALL_LONG;
3910 if (TARGET_DEBUG_ARG)
3912 fprintf (stderr, "\ninit_cumulative_args:");
3915 tree ret_type = TREE_TYPE (fntype);
3916 fprintf (stderr, " ret code = %s,",
3917 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3920 if (cum->call_cookie & CALL_LONG)
3921 fprintf (stderr, " longcall,");
3923 fprintf (stderr, " proto = %d, nargs = %d\n",
3924 cum->prototype, cum->nargs_prototype);
3929 && TARGET_ALTIVEC_ABI
3930 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
3932 error ("Cannot return value in vector register because"
3933 " altivec instructions are disabled, use -maltivec"
3934 " to enable them.");
3938 /* Return true if TYPE must be passed on the stack and not in registers. */
3941 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
3943 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
3944 return must_pass_in_stack_var_size (mode, type);
3946 return must_pass_in_stack_var_size_or_pad (mode, type);
3949 /* If defined, a C expression which determines whether, and in which
3950 direction, to pad out an argument with extra space. The value
3951 should be of type `enum direction': either `upward' to pad above
3952 the argument, `downward' to pad below, or `none' to inhibit
3955 For the AIX ABI structs are always stored left shifted in their
3959 function_arg_padding (enum machine_mode mode, tree type)
3961 #ifndef AGGREGATE_PADDING_FIXED
3962 #define AGGREGATE_PADDING_FIXED 0
3964 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
3965 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
3968 if (!AGGREGATE_PADDING_FIXED)
3970 /* GCC used to pass structures of the same size as integer types as
3971 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
3972 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
3973 passed padded downward, except that -mstrict-align further
3974 muddied the water in that multi-component structures of 2 and 4
3975 bytes in size were passed padded upward.
3977 The following arranges for best compatibility with previous
3978 versions of gcc, but removes the -mstrict-align dependency. */
3979 if (BYTES_BIG_ENDIAN)
3981 HOST_WIDE_INT size = 0;
3983 if (mode == BLKmode)
3985 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
3986 size = int_size_in_bytes (type);
3989 size = GET_MODE_SIZE (mode);
3991 if (size == 1 || size == 2 || size == 4)
3997 if (AGGREGATES_PAD_UPWARD_ALWAYS)
3999 if (type != 0 && AGGREGATE_TYPE_P (type))
4003 /* Fall back to the default. */
4004 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4007 /* If defined, a C expression that gives the alignment boundary, in bits,
4008 of an argument with the specified mode and type. If it is not defined,
4009 PARM_BOUNDARY is used for all arguments.
4011 V.4 wants long longs to be double word aligned.
4012 Doubleword align SPE vectors.
4013 Quadword align Altivec vectors.
4014 Quadword align large synthetic vector types. */
4017 function_arg_boundary (enum machine_mode mode, tree type)
4019 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4021 else if (SPE_VECTOR_MODE (mode)
4022 || (type && TREE_CODE (type) == VECTOR_TYPE
4023 && int_size_in_bytes (type) >= 8
4024 && int_size_in_bytes (type) < 16))
4026 else if (ALTIVEC_VECTOR_MODE (mode)
4027 || (type && TREE_CODE (type) == VECTOR_TYPE
4028 && int_size_in_bytes (type) >= 16))
4030 else if (rs6000_darwin64_abi && mode == BLKmode
4031 && type && TYPE_ALIGN (type) > 64)
4034 return PARM_BOUNDARY;
4037 /* For a function parm of MODE and TYPE, return the starting word in
4038 the parameter area. NWORDS of the parameter area are already used. */
4041 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4044 unsigned int parm_offset;
4046 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4047 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4048 return nwords + (-(parm_offset + nwords) & align);
4051 /* Compute the size (in words) of a function argument. */
4053 static unsigned long
4054 rs6000_arg_size (enum machine_mode mode, tree type)
4058 if (mode != BLKmode)
4059 size = GET_MODE_SIZE (mode);
4061 size = int_size_in_bytes (type);
4064 return (size + 3) >> 2;
4066 return (size + 7) >> 3;
4069 /* Use this to flush pending int fields. */
4072 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4073 HOST_WIDE_INT bitpos)
4075 unsigned int startbit, endbit;
4076 int intregs, intoffset;
4077 enum machine_mode mode;
4079 if (cum->intoffset == -1)
4082 intoffset = cum->intoffset;
4083 cum->intoffset = -1;
4085 if (intoffset % BITS_PER_WORD != 0)
4087 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4089 if (mode == BLKmode)
4091 /* We couldn't find an appropriate mode, which happens,
4092 e.g., in packed structs when there are 3 bytes to load.
4093 Back intoffset back to the beginning of the word in this
4095 intoffset = intoffset & -BITS_PER_WORD;
4099 startbit = intoffset & -BITS_PER_WORD;
4100 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4101 intregs = (endbit - startbit) / BITS_PER_WORD;
4102 cum->words += intregs;
4105 /* The darwin64 ABI calls for us to recurse down through structs,
4106 looking for elements passed in registers. Unfortunately, we have
4107 to track int register count here also because of misalignments
4108 in powerpc alignment mode. */
4111 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4113 HOST_WIDE_INT startbitpos)
4117 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4118 if (TREE_CODE (f) == FIELD_DECL)
4120 HOST_WIDE_INT bitpos = startbitpos;
4121 tree ftype = TREE_TYPE (f);
4122 enum machine_mode mode = TYPE_MODE (ftype);
4124 if (DECL_SIZE (f) != 0
4125 && host_integerp (bit_position (f), 1))
4126 bitpos += int_bit_position (f);
4128 /* ??? FIXME: else assume zero offset. */
4130 if (TREE_CODE (ftype) == RECORD_TYPE)
4131 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4132 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4134 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4135 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4136 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4138 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4140 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4144 else if (cum->intoffset == -1)
4145 cum->intoffset = bitpos;
4149 /* Update the data in CUM to advance over an argument
4150 of mode MODE and data type TYPE.
4151 (TYPE is null for libcalls where that information may not be available.)
4153 Note that for args passed by reference, function_arg will be called
4154 with MODE and TYPE set to that of the pointer to the arg, not the arg
4158 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4159 tree type, int named, int depth)
4163 /* Only tick off an argument if we're not recursing. */
4165 cum->nargs_prototype--;
4167 if (TARGET_ALTIVEC_ABI
4168 && (ALTIVEC_VECTOR_MODE (mode)
4169 || (type && TREE_CODE (type) == VECTOR_TYPE
4170 && int_size_in_bytes (type) == 16)))
4174 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4177 if (!TARGET_ALTIVEC)
4178 error ("Cannot pass argument in vector register because"
4179 " altivec instructions are disabled, use -maltivec"
4180 " to enable them.");
4182 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4183 even if it is going to be passed in a vector register.
4184 Darwin does the same for variable-argument functions. */
4185 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4186 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4196 /* Vector parameters must be 16-byte aligned. This places
4197 them at 2 mod 4 in terms of words in 32-bit mode, since
4198 the parameter save area starts at offset 24 from the
4199 stack. In 64-bit mode, they just have to start on an
4200 even word, since the parameter save area is 16-byte
4201 aligned. Space for GPRs is reserved even if the argument
4202 will be passed in memory. */
4204 align = (2 - cum->words) & 3;
4206 align = cum->words & 1;
4207 cum->words += align + rs6000_arg_size (mode, type);
4209 if (TARGET_DEBUG_ARG)
4211 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4213 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4214 cum->nargs_prototype, cum->prototype,
4215 GET_MODE_NAME (mode));
4219 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4221 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4224 else if (rs6000_darwin64_abi
4226 && TREE_CODE (type) == RECORD_TYPE
4227 && (size = int_size_in_bytes (type)) > 0)
4229 /* Variable sized types have size == -1 and are
4230 treated as if consisting entirely of ints.
4231 Pad to 16 byte boundary if needed. */
4232 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4233 && (cum->words % 2) != 0)
4235 /* For varargs, we can just go up by the size of the struct. */
4237 cum->words += (size + 7) / 8;
4240 /* It is tempting to say int register count just goes up by
4241 sizeof(type)/8, but this is wrong in a case such as
4242 { int; double; int; } [powerpc alignment]. We have to
4243 grovel through the fields for these too. */
4245 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4246 rs6000_darwin64_record_arg_advance_flush (cum,
4247 size * BITS_PER_UNIT);
4250 else if (DEFAULT_ABI == ABI_V4)
4252 if (TARGET_HARD_FLOAT && TARGET_FPRS
4253 && (mode == SFmode || mode == DFmode))
4255 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4260 cum->words += cum->words & 1;
4261 cum->words += rs6000_arg_size (mode, type);
4266 int n_words = rs6000_arg_size (mode, type);
4267 int gregno = cum->sysv_gregno;
4269 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4270 (r7,r8) or (r9,r10). As does any other 2 word item such
4271 as complex int due to a historical mistake. */
4273 gregno += (1 - gregno) & 1;
4275 /* Multi-reg args are not split between registers and stack. */
4276 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4278 /* Long long and SPE vectors are aligned on the stack.
4279 So are other 2 word items such as complex int due to
4280 a historical mistake. */
4282 cum->words += cum->words & 1;
4283 cum->words += n_words;
4286 /* Note: continuing to accumulate gregno past when we've started
4287 spilling to the stack indicates the fact that we've started
4288 spilling to the stack to expand_builtin_saveregs. */
4289 cum->sysv_gregno = gregno + n_words;
4292 if (TARGET_DEBUG_ARG)
4294 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4295 cum->words, cum->fregno);
4296 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4297 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4298 fprintf (stderr, "mode = %4s, named = %d\n",
4299 GET_MODE_NAME (mode), named);
4304 int n_words = rs6000_arg_size (mode, type);
4305 int start_words = cum->words;
4306 int align_words = rs6000_parm_start (mode, type, start_words);
4308 cum->words = align_words + n_words;
4310 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4311 && TARGET_HARD_FLOAT && TARGET_FPRS)
4312 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4314 if (TARGET_DEBUG_ARG)
4316 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4317 cum->words, cum->fregno);
4318 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4319 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4320 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
4321 named, align_words - start_words, depth);
4327 spe_build_register_parallel (enum machine_mode mode, int gregno)
4333 r1 = gen_rtx_REG (DImode, gregno);
4334 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4335 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
4337 else if (mode == DCmode)
4339 r1 = gen_rtx_REG (DImode, gregno);
4340 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4341 r3 = gen_rtx_REG (DImode, gregno + 2);
4342 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4343 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
4349 /* Determine where to put a SIMD argument on the SPE. */
4351 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4354 int gregno = cum->sysv_gregno;
4356 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4357 are passed and returned in a pair of GPRs for ABI compatibility. */
4358 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
4360 int n_words = rs6000_arg_size (mode, type);
4362 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4364 gregno += (1 - gregno) & 1;
4366 /* Multi-reg args are not split between registers and stack. */
4367 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4370 return spe_build_register_parallel (mode, gregno);
4374 int n_words = rs6000_arg_size (mode, type);
4376 /* SPE vectors are put in odd registers. */
4377 if (n_words == 2 && (gregno & 1) == 0)
4380 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4383 enum machine_mode m = SImode;
4385 r1 = gen_rtx_REG (m, gregno);
4386 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4387 r2 = gen_rtx_REG (m, gregno + 1);
4388 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4389 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4396 if (gregno <= GP_ARG_MAX_REG)
4397 return gen_rtx_REG (mode, gregno);
4403 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4404 structure between cum->intoffset and bitpos to integer registers. */
4407 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4408 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
4410 enum machine_mode mode;
4412 unsigned int startbit, endbit;
4413 int this_regno, intregs, intoffset;
4416 if (cum->intoffset == -1)
4419 intoffset = cum->intoffset;
4420 cum->intoffset = -1;
4422 /* If this is the trailing part of a word, try to only load that
4423 much into the register. Otherwise load the whole register. Note
4424 that in the latter case we may pick up unwanted bits. It's not a
4425 problem at the moment but may wish to revisit. */
4427 if (intoffset % BITS_PER_WORD != 0)
4429 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4431 if (mode == BLKmode)
4433 /* We couldn't find an appropriate mode, which happens,
4434 e.g., in packed structs when there are 3 bytes to load.
4435 Back intoffset back to the beginning of the word in this
4437 intoffset = intoffset & -BITS_PER_WORD;
4444 startbit = intoffset & -BITS_PER_WORD;
4445 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4446 intregs = (endbit - startbit) / BITS_PER_WORD;
4447 this_regno = cum->words + intoffset / BITS_PER_WORD;
4449 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4452 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4456 intoffset /= BITS_PER_UNIT;
4459 regno = GP_ARG_MIN_REG + this_regno;
4460 reg = gen_rtx_REG (mode, regno);
4462 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4465 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4469 while (intregs > 0);
4472 /* Recursive workhorse for the following. */
4475 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4476 HOST_WIDE_INT startbitpos, rtx rvec[],
4481 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4482 if (TREE_CODE (f) == FIELD_DECL)
4484 HOST_WIDE_INT bitpos = startbitpos;
4485 tree ftype = TREE_TYPE (f);
4486 enum machine_mode mode = TYPE_MODE (ftype);
4488 if (DECL_SIZE (f) != 0
4489 && host_integerp (bit_position (f), 1))
4490 bitpos += int_bit_position (f);
4492 /* ??? FIXME: else assume zero offset. */
4494 if (TREE_CODE (ftype) == RECORD_TYPE)
4495 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4496 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
4501 case SCmode: mode = SFmode; break;
4502 case DCmode: mode = DFmode; break;
4503 case TCmode: mode = TFmode; break;
4507 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4509 = gen_rtx_EXPR_LIST (VOIDmode,
4510 gen_rtx_REG (mode, cum->fregno++),
4511 GEN_INT (bitpos / BITS_PER_UNIT));
4515 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4517 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4519 = gen_rtx_EXPR_LIST (VOIDmode,
4520 gen_rtx_REG (mode, cum->vregno++),
4521 GEN_INT (bitpos / BITS_PER_UNIT));
4523 else if (cum->intoffset == -1)
4524 cum->intoffset = bitpos;
4528 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4529 the register(s) to be used for each field and subfield of a struct
4530 being passed by value, along with the offset of where the
4531 register's value may be found in the block. FP fields go in FP
4532 register, vector fields go in vector registers, and everything
4533 else goes in int registers, packed as in memory.
4535 This code is also used for function return values. RETVAL indicates
4536 whether this is the case.
4538 Much of this is taken from the Sparc V9 port, which has a similar
4539 calling convention. */
4542 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4543 int named, bool retval)
4545 rtx rvec[FIRST_PSEUDO_REGISTER];
4546 int k = 1, kbase = 1;
4547 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4548 /* This is a copy; modifications are not visible to our caller. */
4549 CUMULATIVE_ARGS copy_cum = *orig_cum;
4550 CUMULATIVE_ARGS *cum = ©_cum;
4552 /* Pad to 16 byte boundary if needed. */
4553 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4554 && (cum->words % 2) != 0)
4561 /* Put entries into rvec[] for individual FP and vector fields, and
4562 for the chunks of memory that go in int regs. Note we start at
4563 element 1; 0 is reserved for an indication of using memory, and
4564 may or may not be filled in below. */
4565 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
4566 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
4568 /* If any part of the struct went on the stack put all of it there.
4569 This hack is because the generic code for
4570 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4571 parts of the struct are not at the beginning. */
4575 return NULL_RTX; /* doesn't go in registers at all */
4577 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4579 if (k > 1 || cum->use_stack)
4580 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
4585 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4588 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
4592 rtx rvec[GP_ARG_NUM_REG + 1];
4594 if (align_words >= GP_ARG_NUM_REG)
4597 n_units = rs6000_arg_size (mode, type);
4599 /* Optimize the simple case where the arg fits in one gpr, except in
4600 the case of BLKmode due to assign_parms assuming that registers are
4601 BITS_PER_WORD wide. */
4603 || (n_units == 1 && mode != BLKmode))
4604 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4607 if (align_words + n_units > GP_ARG_NUM_REG)
4608 /* Not all of the arg fits in gprs. Say that it goes in memory too,
4609 using a magic NULL_RTX component.
4610 FIXME: This is not strictly correct. Only some of the arg
4611 belongs in memory, not all of it. However, there isn't any way
4612 to do this currently, apart from building rtx descriptions for
4613 the pieces of memory we want stored. Due to bugs in the generic
4614 code we can't use the normal function_arg_partial_nregs scheme
4615 with the PARALLEL arg description we emit here.
4616 In any case, the code to store the whole arg to memory is often
4617 more efficient than code to store pieces, and we know that space
4618 is available in the right place for the whole arg. */
4619 /* FIXME: This should be fixed since the conversion to
4620 TARGET_ARG_PARTIAL_BYTES. */
4621 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4626 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
4627 rtx off = GEN_INT (i++ * 4);
4628 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4630 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
4632 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4635 /* Determine where to put an argument to a function.
4636 Value is zero to push the argument on the stack,
4637 or a hard register in which to store the argument.
4639 MODE is the argument's machine mode.
4640 TYPE is the data type of the argument (as a tree).
4641 This is null for libcalls where that information may
4643 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4644 the preceding args and about the function being called. It is
4645 not modified in this routine.
4646 NAMED is nonzero if this argument is a named parameter
4647 (otherwise it is an extra parameter matching an ellipsis).
4649 On RS/6000 the first eight words of non-FP are normally in registers
4650 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4651 Under V.4, the first 8 FP args are in registers.
4653 If this is floating-point and no prototype is specified, we use
4654 both an FP and integer register (or possibly FP reg and stack). Library
4655 functions (when CALL_LIBCALL is set) always have the proper types for args,
4656 so we can pass the FP value just in one register. emit_library_function
4657 doesn't support PARALLEL anyway.
4659 Note that for args passed by reference, function_arg will be called
4660 with MODE and TYPE set to that of the pointer to the arg, not the arg
4664 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4665 tree type, int named)
4667 enum rs6000_abi abi = DEFAULT_ABI;
4669 /* Return a marker to indicate whether CR1 needs to set or clear the
4670 bit that V.4 uses to say fp args were passed in registers.
4671 Assume that we don't need the marker for software floating point,
4672 or compiler generated library calls. */
4673 if (mode == VOIDmode)
4676 && cum->nargs_prototype < 0
4677 && (cum->call_cookie & CALL_LIBCALL) == 0
4678 && (cum->prototype || TARGET_NO_PROTOTYPE))
4680 /* For the SPE, we need to crxor CR6 always. */
4682 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4683 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4684 return GEN_INT (cum->call_cookie
4685 | ((cum->fregno == FP_ARG_MIN_REG)
4686 ? CALL_V4_SET_FP_ARGS
4687 : CALL_V4_CLEAR_FP_ARGS));
4690 return GEN_INT (cum->call_cookie);
4693 if (rs6000_darwin64_abi && mode == BLKmode
4694 && TREE_CODE (type) == RECORD_TYPE)
4696 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
4697 if (rslt != NULL_RTX)
4699 /* Else fall through to usual handling. */
4702 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4703 if (TARGET_64BIT && ! cum->prototype)
4705 /* Vector parameters get passed in vector register
4706 and also in GPRs or memory, in absence of prototype. */
4709 align_words = (cum->words + 1) & ~1;
4711 if (align_words >= GP_ARG_NUM_REG)
4717 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4719 return gen_rtx_PARALLEL (mode,
4721 gen_rtx_EXPR_LIST (VOIDmode,
4723 gen_rtx_EXPR_LIST (VOIDmode,
4724 gen_rtx_REG (mode, cum->vregno),
4728 return gen_rtx_REG (mode, cum->vregno);
4729 else if (TARGET_ALTIVEC_ABI
4730 && (ALTIVEC_VECTOR_MODE (mode)
4731 || (type && TREE_CODE (type) == VECTOR_TYPE
4732 && int_size_in_bytes (type) == 16)))
4734 if (named || abi == ABI_V4)
4738 /* Vector parameters to varargs functions under AIX or Darwin
4739 get passed in memory and possibly also in GPRs. */
4740 int align, align_words, n_words;
4741 enum machine_mode part_mode;
4743 /* Vector parameters must be 16-byte aligned. This places them at
4744 2 mod 4 in terms of words in 32-bit mode, since the parameter
4745 save area starts at offset 24 from the stack. In 64-bit mode,
4746 they just have to start on an even word, since the parameter
4747 save area is 16-byte aligned. */
4749 align = (2 - cum->words) & 3;
4751 align = cum->words & 1;
4752 align_words = cum->words + align;
4754 /* Out of registers? Memory, then. */
4755 if (align_words >= GP_ARG_NUM_REG)
4758 if (TARGET_32BIT && TARGET_POWERPC64)
4759 return rs6000_mixed_function_arg (mode, type, align_words);
4761 /* The vector value goes in GPRs. Only the part of the
4762 value in GPRs is reported here. */
4764 n_words = rs6000_arg_size (mode, type);
4765 if (align_words + n_words > GP_ARG_NUM_REG)
4766 /* Fortunately, there are only two possibilities, the value
4767 is either wholly in GPRs or half in GPRs and half not. */
4770 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
4773 else if (TARGET_SPE_ABI && TARGET_SPE
4774 && (SPE_VECTOR_MODE (mode)
4775 || (TARGET_E500_DOUBLE && (mode == DFmode
4776 || mode == DCmode))))
4777 return rs6000_spe_function_arg (cum, mode, type);
4779 else if (abi == ABI_V4)
4781 if (TARGET_HARD_FLOAT && TARGET_FPRS
4782 && (mode == SFmode || mode == DFmode))
4784 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4785 return gen_rtx_REG (mode, cum->fregno);
4791 int n_words = rs6000_arg_size (mode, type);
4792 int gregno = cum->sysv_gregno;
4794 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4795 (r7,r8) or (r9,r10). As does any other 2 word item such
4796 as complex int due to a historical mistake. */
4798 gregno += (1 - gregno) & 1;
4800 /* Multi-reg args are not split between registers and stack. */
4801 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4804 if (TARGET_32BIT && TARGET_POWERPC64)
4805 return rs6000_mixed_function_arg (mode, type,
4806 gregno - GP_ARG_MIN_REG);
4807 return gen_rtx_REG (mode, gregno);
4812 int align_words = rs6000_parm_start (mode, type, cum->words);
4814 if (USE_FP_FOR_ARG_P (cum, mode, type))
4816 rtx rvec[GP_ARG_NUM_REG + 1];
4820 enum machine_mode fmode = mode;
4821 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
4823 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
4825 /* Currently, we only ever need one reg here because complex
4826 doubles are split. */
4827 if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode)
4830 /* Long double split over regs and memory. */
4834 /* Do we also need to pass this arg in the parameter save
4837 && (cum->nargs_prototype <= 0
4838 || (DEFAULT_ABI == ABI_AIX
4840 && align_words >= GP_ARG_NUM_REG)));
4842 if (!needs_psave && mode == fmode)
4843 return gen_rtx_REG (fmode, cum->fregno);
4848 /* Describe the part that goes in gprs or the stack.
4849 This piece must come first, before the fprs. */
4850 if (align_words < GP_ARG_NUM_REG)
4852 unsigned long n_words = rs6000_arg_size (mode, type);
4854 if (align_words + n_words > GP_ARG_NUM_REG
4855 || (TARGET_32BIT && TARGET_POWERPC64))
4857 /* If this is partially on the stack, then we only
4858 include the portion actually in registers here. */
4859 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
4862 if (align_words + n_words > GP_ARG_NUM_REG
4863 && (TARGET_32BIT && TARGET_POWERPC64))
4864 /* Not all of the arg fits in gprs. Say that it
4865 goes in memory too, using a magic NULL_RTX
4866 component. Also see comment in
4867 rs6000_mixed_function_arg for why the normal
4868 function_arg_partial_nregs scheme doesn't work
4870 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
4874 r = gen_rtx_REG (rmode,
4875 GP_ARG_MIN_REG + align_words);
4876 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
4877 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4879 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
4883 /* The whole arg fits in gprs. */
4884 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4885 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
4889 /* It's entirely in memory. */
4890 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4893 /* Describe where this piece goes in the fprs. */
4894 r = gen_rtx_REG (fmode, cum->fregno);
4895 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
4897 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4899 else if (align_words < GP_ARG_NUM_REG)
4901 if (TARGET_32BIT && TARGET_POWERPC64)
4902 return rs6000_mixed_function_arg (mode, type, align_words);
4904 if (mode == BLKmode)
4907 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4914 /* For an arg passed partly in registers and partly in memory, this is
4915 the number of bytes passed in registers. For args passed entirely in
4916 registers or entirely in memory, zero. When an arg is described by a
4917 PARALLEL, perhaps using more than one register type, this function
4918 returns the number of bytes used by the first element of the PARALLEL. */
4921 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4922 tree type, bool named)
4927 if (DEFAULT_ABI == ABI_V4)
4930 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
4931 && cum->nargs_prototype >= 0)
4934 /* In this complicated case we just disable the partial_nregs code. */
4935 if (rs6000_darwin64_abi && mode == BLKmode
4936 && TREE_CODE (type) == RECORD_TYPE
4937 && int_size_in_bytes (type) > 0)
4940 align_words = rs6000_parm_start (mode, type, cum->words);
4942 if (USE_FP_FOR_ARG_P (cum, mode, type)
4943 /* If we are passing this arg in the fixed parameter save area
4944 (gprs or memory) as well as fprs, then this function should
4945 return the number of bytes passed in the parameter save area
4946 rather than bytes passed in fprs. */
4948 && (cum->nargs_prototype <= 0
4949 || (DEFAULT_ABI == ABI_AIX
4951 && align_words >= GP_ARG_NUM_REG))))
4953 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
4954 ret = FP_ARG_MAX_REG + 1 - cum->fregno;
4955 else if (cum->nargs_prototype >= 0)
4959 if (align_words < GP_ARG_NUM_REG
4960 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
4961 ret = GP_ARG_NUM_REG - align_words;
4963 ret *= (TARGET_32BIT ? 4 : 8);
4965 if (ret != 0 && TARGET_DEBUG_ARG)
4966 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
4971 /* A C expression that indicates when an argument must be passed by
4972 reference. If nonzero for an argument, a copy of that argument is
4973 made in memory and a pointer to the argument is passed instead of
4974 the argument itself. The pointer is passed in whatever way is
4975 appropriate for passing a pointer to that type.
4977 Under V.4, aggregates and long double are passed by reference.
4979 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
4980 reference unless the AltiVec vector extension ABI is in force.
4982 As an extension to all ABIs, variable sized types are passed by
4986 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4987 enum machine_mode mode, tree type,
4988 bool named ATTRIBUTE_UNUSED)
4990 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
4992 if (TARGET_DEBUG_ARG)
4993 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5000 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5002 if (TARGET_DEBUG_ARG)
5003 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5007 if (int_size_in_bytes (type) < 0)
5009 if (TARGET_DEBUG_ARG)
5010 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5014 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5015 modes only exist for GCC vector types if -maltivec. */
5016 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5018 if (TARGET_DEBUG_ARG)
5019 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5023 /* Pass synthetic vectors in memory. */
5024 if (TREE_CODE (type) == VECTOR_TYPE
5025 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5027 static bool warned_for_pass_big_vectors = false;
5028 if (TARGET_DEBUG_ARG)
5029 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5030 if (!warned_for_pass_big_vectors)
5032 warning ("GCC vector passed by reference: "
5033 "non-standard ABI extension with no compatibility guarantee");
5034 warned_for_pass_big_vectors = true;
5043 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5046 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5051 for (i = 0; i < nregs; i++)
5053 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5054 if (reload_completed)
5056 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5059 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5060 i * GET_MODE_SIZE (reg_mode));
5063 tem = replace_equiv_address (tem, XEXP (tem, 0));
5065 if (tem == NULL_RTX)
5068 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5072 /* Perform any needed actions needed for a function that is receiving a
5073 variable number of arguments.
5077 MODE and TYPE are the mode and type of the current parameter.
5079 PRETEND_SIZE is a variable that should be set to the amount of stack
5080 that must be pushed by the prolog to pretend that our caller pushed
5083 Normally, this macro will push all remaining incoming registers on the
5084 stack and set PRETEND_SIZE to the length of the registers pushed. */
5087 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5088 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5091 CUMULATIVE_ARGS next_cum;
5092 int reg_size = TARGET_32BIT ? 4 : 8;
5093 rtx save_area = NULL_RTX, mem;
5094 int first_reg_offset, set;
5096 /* Skip the last named argument. */
5098 function_arg_advance (&next_cum, mode, type, 1, 0);
5100 if (DEFAULT_ABI == ABI_V4)
5103 save_area = plus_constant (virtual_stack_vars_rtx,
5104 - RS6000_VARARGS_SIZE);
5106 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5110 first_reg_offset = next_cum.words;
5111 save_area = virtual_incoming_args_rtx;
5113 if (targetm.calls.must_pass_in_stack (mode, type))
5114 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5117 set = get_varargs_alias_set ();
5118 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5119 && cfun->va_list_gpr_size)
5121 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5123 if (va_list_gpr_counter_field)
5125 /* V4 va_list_gpr_size counts number of registers needed. */
5126 if (nregs > cfun->va_list_gpr_size)
5127 nregs = cfun->va_list_gpr_size;
5131 /* char * va_list instead counts number of bytes needed. */
5132 if (nregs > cfun->va_list_gpr_size / reg_size)
5133 nregs = cfun->va_list_gpr_size / reg_size;
5136 mem = gen_rtx_MEM (BLKmode,
5137 plus_constant (save_area,
5138 first_reg_offset * reg_size)),
5139 set_mem_alias_set (mem, set);
5140 set_mem_align (mem, BITS_PER_WORD);
5142 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5146 /* Save FP registers if needed. */
5147 if (DEFAULT_ABI == ABI_V4
5148 && TARGET_HARD_FLOAT && TARGET_FPRS
5150 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5151 && cfun->va_list_fpr_size)
5153 int fregno = next_cum.fregno, nregs;
5154 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5155 rtx lab = gen_label_rtx ();
5156 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
5159 (gen_rtx_SET (VOIDmode,
5161 gen_rtx_IF_THEN_ELSE (VOIDmode,
5162 gen_rtx_NE (VOIDmode, cr1,
5164 gen_rtx_LABEL_REF (VOIDmode, lab),
5168 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
5169 fregno++, off += 8, nregs++)
5171 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5172 set_mem_alias_set (mem, set);
5173 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5174 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5181 /* Create the va_list data type. */
5184 rs6000_build_builtin_va_list (void)
5186 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5188 /* For AIX, prefer 'char *' because that's what the system
5189 header files like. */
5190 if (DEFAULT_ABI != ABI_V4)
5191 return build_pointer_type (char_type_node);
5193 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5194 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5196 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5197 unsigned_char_type_node);
5198 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5199 unsigned_char_type_node);
5200 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5202 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5203 short_unsigned_type_node);
5204 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5206 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5209 va_list_gpr_counter_field = f_gpr;
5210 va_list_fpr_counter_field = f_fpr;
5212 DECL_FIELD_CONTEXT (f_gpr) = record;
5213 DECL_FIELD_CONTEXT (f_fpr) = record;
5214 DECL_FIELD_CONTEXT (f_res) = record;
5215 DECL_FIELD_CONTEXT (f_ovf) = record;
5216 DECL_FIELD_CONTEXT (f_sav) = record;
5218 TREE_CHAIN (record) = type_decl;
5219 TYPE_NAME (record) = type_decl;
5220 TYPE_FIELDS (record) = f_gpr;
5221 TREE_CHAIN (f_gpr) = f_fpr;
5222 TREE_CHAIN (f_fpr) = f_res;
5223 TREE_CHAIN (f_res) = f_ovf;
5224 TREE_CHAIN (f_ovf) = f_sav;
5226 layout_type (record);
5228 /* The correct type is an array type of one element. */
5229 return build_array_type (record, build_index_type (size_zero_node));
5232 /* Implement va_start. */
5235 rs6000_va_start (tree valist, rtx nextarg)
5237 HOST_WIDE_INT words, n_gpr, n_fpr;
5238 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5239 tree gpr, fpr, ovf, sav, t;
5241 /* Only SVR4 needs something special. */
5242 if (DEFAULT_ABI != ABI_V4)
5244 std_expand_builtin_va_start (valist, nextarg);
5248 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5249 f_fpr = TREE_CHAIN (f_gpr);
5250 f_res = TREE_CHAIN (f_fpr);
5251 f_ovf = TREE_CHAIN (f_res);
5252 f_sav = TREE_CHAIN (f_ovf);
5254 valist = build_va_arg_indirect_ref (valist);
5255 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5256 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5257 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5258 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5260 /* Count number of gp and fp argument registers used. */
5261 words = current_function_args_info.words;
5262 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5264 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5267 if (TARGET_DEBUG_ARG)
5268 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5269 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5270 words, n_gpr, n_fpr);
5272 if (cfun->va_list_gpr_size)
5274 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5275 build_int_cst (NULL_TREE, n_gpr));
5276 TREE_SIDE_EFFECTS (t) = 1;
5277 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5280 if (cfun->va_list_fpr_size)
5282 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5283 build_int_cst (NULL_TREE, n_fpr));
5284 TREE_SIDE_EFFECTS (t) = 1;
5285 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5288 /* Find the overflow area. */
5289 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5291 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
5292 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5293 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5294 TREE_SIDE_EFFECTS (t) = 1;
5295 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5297 /* If there were no va_arg invocations, don't set up the register
5299 if (!cfun->va_list_gpr_size
5300 && !cfun->va_list_fpr_size
5301 && n_gpr < GP_ARG_NUM_REG
5302 && n_fpr < FP_ARG_V4_MAX_REG)
5305 /* Find the register save area. */
5306 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5307 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
5308 build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE));
5309 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5310 TREE_SIDE_EFFECTS (t) = 1;
5311 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5314 /* Implement va_arg. */
5317 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5319 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5320 tree gpr, fpr, ovf, sav, reg, t, u;
5321 int size, rsize, n_reg, sav_ofs, sav_scale;
5322 tree lab_false, lab_over, addr;
5324 tree ptrtype = build_pointer_type (type);
5326 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5328 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5329 return build_va_arg_indirect_ref (t);
5332 if (DEFAULT_ABI != ABI_V4)
5334 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5336 tree elem_type = TREE_TYPE (type);
5337 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5338 int elem_size = GET_MODE_SIZE (elem_mode);
5340 if (elem_size < UNITS_PER_WORD)
5342 tree real_part, imag_part;
5343 tree post = NULL_TREE;
5345 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5347 /* Copy the value into a temporary, lest the formal temporary
5348 be reused out from under us. */
5349 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5350 append_to_statement_list (post, pre_p);
5352 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5355 return build (COMPLEX_EXPR, type, real_part, imag_part);
5359 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5362 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5363 f_fpr = TREE_CHAIN (f_gpr);
5364 f_res = TREE_CHAIN (f_fpr);
5365 f_ovf = TREE_CHAIN (f_res);
5366 f_sav = TREE_CHAIN (f_ovf);
5368 valist = build_va_arg_indirect_ref (valist);
5369 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5370 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5371 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5372 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5374 size = int_size_in_bytes (type);
5375 rsize = (size + 3) / 4;
5378 if (TARGET_HARD_FLOAT && TARGET_FPRS
5379 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
5381 /* FP args go in FP registers, if present. */
5386 if (TYPE_MODE (type) == DFmode)
5391 /* Otherwise into GP registers. */
5400 /* Pull the value out of the saved registers.... */
5403 addr = create_tmp_var (ptr_type_node, "addr");
5404 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5406 /* AltiVec vectors never go in registers when -mabi=altivec. */
5407 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5411 lab_false = create_artificial_label ();
5412 lab_over = create_artificial_label ();
5414 /* Long long and SPE vectors are aligned in the registers.
5415 As are any other 2 gpr item such as complex int due to a
5416 historical mistake. */
5420 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5421 size_int (n_reg - 1));
5422 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5425 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5426 t = build2 (GE_EXPR, boolean_type_node, u, t);
5427 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5428 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5429 gimplify_and_add (t, pre_p);
5433 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5435 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5436 u = build1 (CONVERT_EXPR, integer_type_node, u);
5437 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5438 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5440 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5441 gimplify_and_add (t, pre_p);
5443 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5444 gimplify_and_add (t, pre_p);
5446 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5447 append_to_statement_list (t, pre_p);
5451 /* Ensure that we don't find any more args in regs.
5452 Alignment has taken care of the n_reg == 2 case. */
5453 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
5454 gimplify_and_add (t, pre_p);
5458 /* ... otherwise out of the overflow area. */
5460 /* Care for on-stack alignment if needed. */
5464 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
5465 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5466 build_int_cst (NULL_TREE, -align));
5468 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5470 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5471 gimplify_and_add (u, pre_p);
5473 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
5474 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5475 gimplify_and_add (t, pre_p);
5479 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5480 append_to_statement_list (t, pre_p);
5483 addr = fold_convert (ptrtype, addr);
5484 return build_va_arg_indirect_ref (addr);
5489 #define def_builtin(MASK, NAME, TYPE, CODE) \
5491 if ((MASK) & target_flags) \
5492 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
5496 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5498 static const struct builtin_description bdesc_3arg[] =
5500 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5501 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5502 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5503 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5504 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5505 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5506 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5507 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5508 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5509 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
5510 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
5511 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5512 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5513 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5514 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5515 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5516 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5517 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5518 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5519 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5520 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5521 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5522 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
5525 /* DST operations: void foo (void *, const int, const char). */
5527 static const struct builtin_description bdesc_dst[] =
5529 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5530 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5531 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
5532 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
5535 /* Simple binary operations: VECc = foo (VECa, VECb). */
5537 static struct builtin_description bdesc_2arg[] =
5539 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5540 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5541 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5542 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
5543 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5544 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5545 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5546 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5547 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5548 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5549 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
5550 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
5551 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
5552 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5553 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5554 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5555 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5556 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5557 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
5558 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5559 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
5560 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
5561 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
5562 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
5563 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
5564 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
5565 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
5566 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
5567 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
5568 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
5569 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
5570 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
5571 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
5572 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
5573 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
5574 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
5575 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
5576 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
5577 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
5578 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
5579 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
5580 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
5581 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
5582 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
5583 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
5584 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
5585 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
5586 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
5587 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
5588 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
5589 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
5590 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
5591 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
5592 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
5593 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
5594 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
5595 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
5596 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
5597 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
5598 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
5599 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
5600 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
5601 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
5602 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
5603 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
5604 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
5605 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
5606 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
5607 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
5608 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
5609 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
5610 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
5611 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
5612 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
5613 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
5614 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
5615 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
5616 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
5617 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
5618 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
5619 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
5620 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
5621 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
5622 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
5623 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
5624 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
5625 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
5626 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
5627 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
5628 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
5629 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
5630 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
5631 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
5632 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
5633 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
5634 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
5635 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
5636 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
5637 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
5638 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
5639 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
5640 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
5641 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
5642 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
5643 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
5644 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
5645 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
5646 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
5647 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
5648 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
5649 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
5650 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
5651 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
5653 /* Place holder, leave as first spe builtin. */
5654 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
5655 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
5656 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
5657 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
5658 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
5659 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
5660 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
5661 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
5662 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
5663 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
5664 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
5665 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
5666 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
5667 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
5668 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
5669 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
5670 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
5671 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
5672 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
5673 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
5674 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
5675 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
5676 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
5677 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
5678 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
5679 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
5680 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
5681 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
5682 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5683 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
5684 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
5685 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
5686 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
5687 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
5688 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
5689 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
5690 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
5691 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
5692 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
5693 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
5694 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
5695 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
5696 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
5697 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
5698 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
5699 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
5700 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
5701 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
5702 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
5703 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
5704 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
5705 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
5706 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
5707 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
5708 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
5709 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
5710 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
5711 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
5712 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
5713 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
5714 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
5715 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
5716 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
5717 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
5718 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
5719 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
5720 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
5721 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
5722 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
5723 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
5724 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
5725 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
5726 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
5727 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
5728 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
5729 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
5730 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
5731 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
5732 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
5733 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
5734 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
5735 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
5736 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
5737 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
5738 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
5739 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
5740 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
5741 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
5742 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
5743 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
5744 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
5745 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
5746 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
5747 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
5748 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
5749 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
5750 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
5751 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
5752 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
5753 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
5754 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
5755 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
5756 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
5757 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
5758 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
5759 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
5760 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
5761 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
5762 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
5764 /* SPE binary operations expecting a 5-bit unsigned literal. */
5765 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
5767 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
5768 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
5769 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
5770 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
5771 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
5772 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
5773 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
5774 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
5775 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
5776 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
5777 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
5778 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
5779 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
5780 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
5781 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
5782 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
5783 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
5784 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
5785 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
5786 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
5787 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
5788 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
5789 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
5790 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
5791 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
5792 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
5794 /* Place-holder. Leave as last binary SPE builtin. */
5795 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
5798 /* AltiVec predicates. */
5800 struct builtin_description_predicates
5802 const unsigned int mask;
5803 const enum insn_code icode;
5805 const char *const name;
5806 const enum rs6000_builtins code;
5809 static const struct builtin_description_predicates bdesc_altivec_preds[] =
5811 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
5812 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
5813 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
5814 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
5815 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
5816 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
5817 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
5818 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
5819 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
5820 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
5821 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
5822 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
5823 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
5826 /* SPE predicates. */
5827 static struct builtin_description bdesc_spe_predicates[] =
5829 /* Place-holder. Leave as first. */
5830 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
5831 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
5832 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
5833 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
5834 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
5835 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
5836 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
5837 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
5838 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
5839 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
5840 /* Place-holder. Leave as last. */
5841 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
5844 /* SPE evsel predicates. */
5845 static struct builtin_description bdesc_spe_evsel[] =
5847 /* Place-holder. Leave as first. */
5848 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
5849 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
5850 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
5851 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
5852 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
5853 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
5854 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
5855 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
5856 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
5857 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
5858 /* Place-holder. Leave as last. */
5859 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
5862 /* ABS* operations. */
5864 static const struct builtin_description bdesc_abs[] =
5866 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
5867 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
5868 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
5869 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
5870 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
5871 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
5872 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
5875 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
5878 static struct builtin_description bdesc_1arg[] =
5880 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
5881 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
5882 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
5883 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
5884 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
5885 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
5886 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
5887 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
5888 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
5889 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
5890 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
5891 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
5892 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
5893 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
5894 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
5895 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
5896 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
5898 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
5899 end with SPE_BUILTIN_EVSUBFUSIAAW. */
5900 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
5901 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
5902 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
5903 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
5904 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
5905 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
5906 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
5907 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
5908 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
5909 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
5910 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
5911 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
5912 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
5913 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
5914 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
5915 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
5916 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
5917 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
5918 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
5919 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
5920 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
5921 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
5922 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
5923 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
5924 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
5925 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
5926 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
5927 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
5929 /* Place-holder. Leave as last unary SPE builtin. */
5930 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
5934 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
5937 tree arg0 = TREE_VALUE (arglist);
5938 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5939 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5940 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5942 if (icode == CODE_FOR_nothing)
5943 /* Builtin not supported on this processor. */
5946 /* If we got invalid arguments bail out before generating bad rtl. */
5947 if (arg0 == error_mark_node)
5950 if (icode == CODE_FOR_altivec_vspltisb
5951 || icode == CODE_FOR_altivec_vspltish
5952 || icode == CODE_FOR_altivec_vspltisw
5953 || icode == CODE_FOR_spe_evsplatfi
5954 || icode == CODE_FOR_spe_evsplati)
5956 /* Only allow 5-bit *signed* literals. */
5957 if (GET_CODE (op0) != CONST_INT
5958 || INTVAL (op0) > 0x1f
5959 || INTVAL (op0) < -0x1f)
5961 error ("argument 1 must be a 5-bit signed literal");
5967 || GET_MODE (target) != tmode
5968 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5969 target = gen_reg_rtx (tmode);
5971 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5972 op0 = copy_to_mode_reg (mode0, op0);
5974 pat = GEN_FCN (icode) (target, op0);
5983 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
5985 rtx pat, scratch1, scratch2;
5986 tree arg0 = TREE_VALUE (arglist);
5987 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5988 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5989 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5991 /* If we have invalid arguments, bail out before generating bad rtl. */
5992 if (arg0 == error_mark_node)
5996 || GET_MODE (target) != tmode
5997 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5998 target = gen_reg_rtx (tmode);
6000 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6001 op0 = copy_to_mode_reg (mode0, op0);
6003 scratch1 = gen_reg_rtx (mode0);
6004 scratch2 = gen_reg_rtx (mode0);
6006 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6015 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6018 tree arg0 = TREE_VALUE (arglist);
6019 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6020 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6021 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6022 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6023 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6024 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6026 if (icode == CODE_FOR_nothing)
6027 /* Builtin not supported on this processor. */
6030 /* If we got invalid arguments bail out before generating bad rtl. */
6031 if (arg0 == error_mark_node || arg1 == error_mark_node)
6034 if (icode == CODE_FOR_altivec_vcfux
6035 || icode == CODE_FOR_altivec_vcfsx
6036 || icode == CODE_FOR_altivec_vctsxs
6037 || icode == CODE_FOR_altivec_vctuxs
6038 || icode == CODE_FOR_altivec_vspltb
6039 || icode == CODE_FOR_altivec_vsplth
6040 || icode == CODE_FOR_altivec_vspltw
6041 || icode == CODE_FOR_spe_evaddiw
6042 || icode == CODE_FOR_spe_evldd
6043 || icode == CODE_FOR_spe_evldh
6044 || icode == CODE_FOR_spe_evldw
6045 || icode == CODE_FOR_spe_evlhhesplat
6046 || icode == CODE_FOR_spe_evlhhossplat
6047 || icode == CODE_FOR_spe_evlhhousplat
6048 || icode == CODE_FOR_spe_evlwhe
6049 || icode == CODE_FOR_spe_evlwhos
6050 || icode == CODE_FOR_spe_evlwhou
6051 || icode == CODE_FOR_spe_evlwhsplat
6052 || icode == CODE_FOR_spe_evlwwsplat
6053 || icode == CODE_FOR_spe_evrlwi
6054 || icode == CODE_FOR_spe_evslwi
6055 || icode == CODE_FOR_spe_evsrwis
6056 || icode == CODE_FOR_spe_evsubifw
6057 || icode == CODE_FOR_spe_evsrwiu)
6059 /* Only allow 5-bit unsigned literals. */
6061 if (TREE_CODE (arg1) != INTEGER_CST
6062 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6064 error ("argument 2 must be a 5-bit unsigned literal");
6070 || GET_MODE (target) != tmode
6071 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6072 target = gen_reg_rtx (tmode);
6074 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6075 op0 = copy_to_mode_reg (mode0, op0);
6076 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6077 op1 = copy_to_mode_reg (mode1, op1);
6079 pat = GEN_FCN (icode) (target, op0, op1);
6088 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6089 tree arglist, rtx target)
6092 tree cr6_form = TREE_VALUE (arglist);
6093 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6094 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6095 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6096 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6097 enum machine_mode tmode = SImode;
6098 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6099 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6102 if (TREE_CODE (cr6_form) != INTEGER_CST)
6104 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6108 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6113 /* If we have invalid arguments, bail out before generating bad rtl. */
6114 if (arg0 == error_mark_node || arg1 == error_mark_node)
6118 || GET_MODE (target) != tmode
6119 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6120 target = gen_reg_rtx (tmode);
6122 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6123 op0 = copy_to_mode_reg (mode0, op0);
6124 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6125 op1 = copy_to_mode_reg (mode1, op1);
6127 scratch = gen_reg_rtx (mode0);
6129 pat = GEN_FCN (icode) (scratch, op0, op1,
6130 gen_rtx_SYMBOL_REF (Pmode, opcode));
6135 /* The vec_any* and vec_all* predicates use the same opcodes for two
6136 different operations, but the bits in CR6 will be different
6137 depending on what information we want. So we have to play tricks
6138 with CR6 to get the right bits out.
6140 If you think this is disgusting, look at the specs for the
6141 AltiVec predicates. */
6143 switch (cr6_form_int)
6146 emit_insn (gen_cr6_test_for_zero (target));
6149 emit_insn (gen_cr6_test_for_zero_reverse (target));
6152 emit_insn (gen_cr6_test_for_lt (target));
6155 emit_insn (gen_cr6_test_for_lt_reverse (target));
6158 error ("argument 1 of __builtin_altivec_predicate is out of range");
6166 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6169 tree arg0 = TREE_VALUE (arglist);
6170 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6171 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6172 enum machine_mode mode0 = Pmode;
6173 enum machine_mode mode1 = Pmode;
6174 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6175 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6177 if (icode == CODE_FOR_nothing)
6178 /* Builtin not supported on this processor. */
6181 /* If we got invalid arguments bail out before generating bad rtl. */
6182 if (arg0 == error_mark_node || arg1 == error_mark_node)
6186 || GET_MODE (target) != tmode
6187 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6188 target = gen_reg_rtx (tmode);
6190 op1 = copy_to_mode_reg (mode1, op1);
6192 if (op0 == const0_rtx)
6194 addr = gen_rtx_MEM (tmode, op1);
6198 op0 = copy_to_mode_reg (mode0, op0);
6199 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6202 pat = GEN_FCN (icode) (target, addr);
6212 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6214 tree arg0 = TREE_VALUE (arglist);
6215 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6216 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6217 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6218 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6219 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6221 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6222 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6223 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6225 /* Invalid arguments. Bail before doing anything stoopid! */
6226 if (arg0 == error_mark_node
6227 || arg1 == error_mark_node
6228 || arg2 == error_mark_node)
6231 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6232 op0 = copy_to_mode_reg (mode2, op0);
6233 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6234 op1 = copy_to_mode_reg (mode0, op1);
6235 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6236 op2 = copy_to_mode_reg (mode1, op2);
6238 pat = GEN_FCN (icode) (op1, op2, op0);
6245 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6247 tree arg0 = TREE_VALUE (arglist);
6248 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6249 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6250 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6251 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6252 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6254 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6255 enum machine_mode mode1 = Pmode;
6256 enum machine_mode mode2 = Pmode;
6258 /* Invalid arguments. Bail before doing anything stoopid! */
6259 if (arg0 == error_mark_node
6260 || arg1 == error_mark_node
6261 || arg2 == error_mark_node)
6264 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6265 op0 = copy_to_mode_reg (tmode, op0);
6267 op2 = copy_to_mode_reg (mode2, op2);
6269 if (op1 == const0_rtx)
6271 addr = gen_rtx_MEM (tmode, op2);
6275 op1 = copy_to_mode_reg (mode1, op1);
6276 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6279 pat = GEN_FCN (icode) (addr, op0);
6286 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6289 tree arg0 = TREE_VALUE (arglist);
6290 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6291 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6292 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6293 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6294 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6295 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6296 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6297 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6298 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6300 if (icode == CODE_FOR_nothing)
6301 /* Builtin not supported on this processor. */
6304 /* If we got invalid arguments bail out before generating bad rtl. */
6305 if (arg0 == error_mark_node
6306 || arg1 == error_mark_node
6307 || arg2 == error_mark_node)
6310 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6311 || icode == CODE_FOR_altivec_vsldoi_v4si
6312 || icode == CODE_FOR_altivec_vsldoi_v8hi
6313 || icode == CODE_FOR_altivec_vsldoi_v16qi)
6315 /* Only allow 4-bit unsigned literals. */
6317 if (TREE_CODE (arg2) != INTEGER_CST
6318 || TREE_INT_CST_LOW (arg2) & ~0xf)
6320 error ("argument 3 must be a 4-bit unsigned literal");
6326 || GET_MODE (target) != tmode
6327 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6328 target = gen_reg_rtx (tmode);
6330 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6331 op0 = copy_to_mode_reg (mode0, op0);
6332 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6333 op1 = copy_to_mode_reg (mode1, op1);
6334 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6335 op2 = copy_to_mode_reg (mode2, op2);
6337 pat = GEN_FCN (icode) (target, op0, op1, op2);
6345 /* Expand the lvx builtins. */
6347 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
6349 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6350 tree arglist = TREE_OPERAND (exp, 1);
6351 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6353 enum machine_mode tmode, mode0;
6355 enum insn_code icode;
6359 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
6360 icode = CODE_FOR_altivec_lvx_v16qi;
6362 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
6363 icode = CODE_FOR_altivec_lvx_v8hi;
6365 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
6366 icode = CODE_FOR_altivec_lvx_v4si;
6368 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
6369 icode = CODE_FOR_altivec_lvx_v4sf;
6378 arg0 = TREE_VALUE (arglist);
6379 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6380 tmode = insn_data[icode].operand[0].mode;
6381 mode0 = insn_data[icode].operand[1].mode;
6384 || GET_MODE (target) != tmode
6385 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6386 target = gen_reg_rtx (tmode);
6388 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6389 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6391 pat = GEN_FCN (icode) (target, op0);
6398 /* Expand the stvx builtins. */
6400 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6403 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6404 tree arglist = TREE_OPERAND (exp, 1);
6405 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6407 enum machine_mode mode0, mode1;
6409 enum insn_code icode;
6413 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
6414 icode = CODE_FOR_altivec_stvx_v16qi;
6416 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
6417 icode = CODE_FOR_altivec_stvx_v8hi;
6419 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
6420 icode = CODE_FOR_altivec_stvx_v4si;
6422 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
6423 icode = CODE_FOR_altivec_stvx_v4sf;
6430 arg0 = TREE_VALUE (arglist);
6431 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6432 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6433 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6434 mode0 = insn_data[icode].operand[0].mode;
6435 mode1 = insn_data[icode].operand[1].mode;
6437 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6438 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6439 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6440 op1 = copy_to_mode_reg (mode1, op1);
6442 pat = GEN_FCN (icode) (op0, op1);
6450 /* Expand the dst builtins. */
6452 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6455 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6456 tree arglist = TREE_OPERAND (exp, 1);
6457 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6458 tree arg0, arg1, arg2;
6459 enum machine_mode mode0, mode1, mode2;
6460 rtx pat, op0, op1, op2;
6461 struct builtin_description *d;
6466 /* Handle DST variants. */
6467 d = (struct builtin_description *) bdesc_dst;
6468 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6469 if (d->code == fcode)
6471 arg0 = TREE_VALUE (arglist);
6472 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6473 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6474 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6475 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6476 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6477 mode0 = insn_data[d->icode].operand[0].mode;
6478 mode1 = insn_data[d->icode].operand[1].mode;
6479 mode2 = insn_data[d->icode].operand[2].mode;
6481 /* Invalid arguments, bail out before generating bad rtl. */
6482 if (arg0 == error_mark_node
6483 || arg1 == error_mark_node
6484 || arg2 == error_mark_node)
6489 if (TREE_CODE (arg2) != INTEGER_CST
6490 || TREE_INT_CST_LOW (arg2) & ~0x3)
6492 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
6496 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
6497 op0 = copy_to_mode_reg (Pmode, op0);
6498 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
6499 op1 = copy_to_mode_reg (mode1, op1);
6501 pat = GEN_FCN (d->icode) (op0, op1, op2);
6511 /* Expand the builtin in EXP and store the result in TARGET. Store
6512 true in *EXPANDEDP if we found a builtin to expand. */
6514 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
6516 struct builtin_description *d;
6517 struct builtin_description_predicates *dp;
6519 enum insn_code icode;
6520 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6521 tree arglist = TREE_OPERAND (exp, 1);
6524 enum machine_mode tmode, mode0;
6525 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6527 target = altivec_expand_ld_builtin (exp, target, expandedp);
6531 target = altivec_expand_st_builtin (exp, target, expandedp);
6535 target = altivec_expand_dst_builtin (exp, target, expandedp);
6543 case ALTIVEC_BUILTIN_STVX:
6544 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
6545 case ALTIVEC_BUILTIN_STVEBX:
6546 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
6547 case ALTIVEC_BUILTIN_STVEHX:
6548 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
6549 case ALTIVEC_BUILTIN_STVEWX:
6550 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
6551 case ALTIVEC_BUILTIN_STVXL:
6552 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
6554 case ALTIVEC_BUILTIN_MFVSCR:
6555 icode = CODE_FOR_altivec_mfvscr;
6556 tmode = insn_data[icode].operand[0].mode;
6559 || GET_MODE (target) != tmode
6560 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6561 target = gen_reg_rtx (tmode);
6563 pat = GEN_FCN (icode) (target);
6569 case ALTIVEC_BUILTIN_MTVSCR:
6570 icode = CODE_FOR_altivec_mtvscr;
6571 arg0 = TREE_VALUE (arglist);
6572 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6573 mode0 = insn_data[icode].operand[0].mode;
6575 /* If we got invalid arguments bail out before generating bad rtl. */
6576 if (arg0 == error_mark_node)
6579 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6580 op0 = copy_to_mode_reg (mode0, op0);
6582 pat = GEN_FCN (icode) (op0);
6587 case ALTIVEC_BUILTIN_DSSALL:
6588 emit_insn (gen_altivec_dssall ());
6591 case ALTIVEC_BUILTIN_DSS:
6592 icode = CODE_FOR_altivec_dss;
6593 arg0 = TREE_VALUE (arglist);
6595 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6596 mode0 = insn_data[icode].operand[0].mode;
6598 /* If we got invalid arguments bail out before generating bad rtl. */
6599 if (arg0 == error_mark_node)
6602 if (TREE_CODE (arg0) != INTEGER_CST
6603 || TREE_INT_CST_LOW (arg0) & ~0x3)
6605 error ("argument to dss must be a 2-bit unsigned literal");
6609 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6610 op0 = copy_to_mode_reg (mode0, op0);
6612 emit_insn (gen_altivec_dss (op0));
6615 case ALTIVEC_BUILTIN_COMPILETIME_ERROR:
6616 arg0 = TREE_VALUE (arglist);
6617 while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR
6618 || TREE_CODE (arg0) == ARRAY_REF)
6619 arg0 = TREE_OPERAND (arg0, 0);
6620 error ("invalid parameter combination for %qs AltiVec intrinsic",
6621 TREE_STRING_POINTER (arg0));
6626 /* Expand abs* operations. */
6627 d = (struct builtin_description *) bdesc_abs;
6628 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
6629 if (d->code == fcode)
6630 return altivec_expand_abs_builtin (d->icode, arglist, target);
6632 /* Expand the AltiVec predicates. */
6633 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
6634 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
6635 if (dp->code == fcode)
6636 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
6639 /* LV* are funky. We initialized them differently. */
6642 case ALTIVEC_BUILTIN_LVSL:
6643 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
6645 case ALTIVEC_BUILTIN_LVSR:
6646 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
6648 case ALTIVEC_BUILTIN_LVEBX:
6649 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
6651 case ALTIVEC_BUILTIN_LVEHX:
6652 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
6654 case ALTIVEC_BUILTIN_LVEWX:
6655 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
6657 case ALTIVEC_BUILTIN_LVXL:
6658 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
6660 case ALTIVEC_BUILTIN_LVX:
6661 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
6672 /* Binops that need to be initialized manually, but can be expanded
6673 automagically by rs6000_expand_binop_builtin. */
6674 static struct builtin_description bdesc_2arg_spe[] =
6676 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
6677 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
6678 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
6679 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
6680 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
6681 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
6682 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
6683 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
6684 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
6685 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
6686 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
6687 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
6688 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
6689 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
6690 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
6691 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
6692 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
6693 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
6694 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
6695 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
6696 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
6697 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
6700 /* Expand the builtin in EXP and store the result in TARGET. Store
6701 true in *EXPANDEDP if we found a builtin to expand.
6703 This expands the SPE builtins that are not simple unary and binary
6706 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
6708 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6709 tree arglist = TREE_OPERAND (exp, 1);
6711 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6712 enum insn_code icode;
6713 enum machine_mode tmode, mode0;
6715 struct builtin_description *d;
6720 /* Syntax check for a 5-bit unsigned immediate. */
6723 case SPE_BUILTIN_EVSTDD:
6724 case SPE_BUILTIN_EVSTDH:
6725 case SPE_BUILTIN_EVSTDW:
6726 case SPE_BUILTIN_EVSTWHE:
6727 case SPE_BUILTIN_EVSTWHO:
6728 case SPE_BUILTIN_EVSTWWE:
6729 case SPE_BUILTIN_EVSTWWO:
6730 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6731 if (TREE_CODE (arg1) != INTEGER_CST
6732 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6734 error ("argument 2 must be a 5-bit unsigned literal");
6742 /* The evsplat*i instructions are not quite generic. */
6745 case SPE_BUILTIN_EVSPLATFI:
6746 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
6748 case SPE_BUILTIN_EVSPLATI:
6749 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
6755 d = (struct builtin_description *) bdesc_2arg_spe;
6756 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
6757 if (d->code == fcode)
6758 return rs6000_expand_binop_builtin (d->icode, arglist, target);
6760 d = (struct builtin_description *) bdesc_spe_predicates;
6761 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
6762 if (d->code == fcode)
6763 return spe_expand_predicate_builtin (d->icode, arglist, target);
6765 d = (struct builtin_description *) bdesc_spe_evsel;
6766 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
6767 if (d->code == fcode)
6768 return spe_expand_evsel_builtin (d->icode, arglist, target);
6772 case SPE_BUILTIN_EVSTDDX:
6773 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
6774 case SPE_BUILTIN_EVSTDHX:
6775 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
6776 case SPE_BUILTIN_EVSTDWX:
6777 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
6778 case SPE_BUILTIN_EVSTWHEX:
6779 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
6780 case SPE_BUILTIN_EVSTWHOX:
6781 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
6782 case SPE_BUILTIN_EVSTWWEX:
6783 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
6784 case SPE_BUILTIN_EVSTWWOX:
6785 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
6786 case SPE_BUILTIN_EVSTDD:
6787 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
6788 case SPE_BUILTIN_EVSTDH:
6789 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
6790 case SPE_BUILTIN_EVSTDW:
6791 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
6792 case SPE_BUILTIN_EVSTWHE:
6793 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
6794 case SPE_BUILTIN_EVSTWHO:
6795 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
6796 case SPE_BUILTIN_EVSTWWE:
6797 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
6798 case SPE_BUILTIN_EVSTWWO:
6799 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
6800 case SPE_BUILTIN_MFSPEFSCR:
6801 icode = CODE_FOR_spe_mfspefscr;
6802 tmode = insn_data[icode].operand[0].mode;
6805 || GET_MODE (target) != tmode
6806 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6807 target = gen_reg_rtx (tmode);
6809 pat = GEN_FCN (icode) (target);
6814 case SPE_BUILTIN_MTSPEFSCR:
6815 icode = CODE_FOR_spe_mtspefscr;
6816 arg0 = TREE_VALUE (arglist);
6817 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6818 mode0 = insn_data[icode].operand[0].mode;
6820 if (arg0 == error_mark_node)
6823 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6824 op0 = copy_to_mode_reg (mode0, op0);
6826 pat = GEN_FCN (icode) (op0);
6839 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
6841 rtx pat, scratch, tmp;
6842 tree form = TREE_VALUE (arglist);
6843 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6844 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6845 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6846 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6847 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6848 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6852 if (TREE_CODE (form) != INTEGER_CST)
6854 error ("argument 1 of __builtin_spe_predicate must be a constant");
6858 form_int = TREE_INT_CST_LOW (form);
6863 if (arg0 == error_mark_node || arg1 == error_mark_node)
6867 || GET_MODE (target) != SImode
6868 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
6869 target = gen_reg_rtx (SImode);
6871 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6872 op0 = copy_to_mode_reg (mode0, op0);
6873 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6874 op1 = copy_to_mode_reg (mode1, op1);
6876 scratch = gen_reg_rtx (CCmode);
6878 pat = GEN_FCN (icode) (scratch, op0, op1);
6883 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
6884 _lower_. We use one compare, but look in different bits of the
6885 CR for each variant.
6887 There are 2 elements in each SPE simd type (upper/lower). The CR
6888 bits are set as follows:
6890 BIT0 | BIT 1 | BIT 2 | BIT 3
6891 U | L | (U | L) | (U & L)
6893 So, for an "all" relationship, BIT 3 would be set.
6894 For an "any" relationship, BIT 2 would be set. Etc.
6896 Following traditional nomenclature, these bits map to:
6898 BIT0 | BIT 1 | BIT 2 | BIT 3
6901 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
6906 /* All variant. OV bit. */
6908 /* We need to get to the OV bit, which is the ORDERED bit. We
6909 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
6910 that's ugly and will trigger a validate_condition_mode abort.
6911 So let's just use another pattern. */
6912 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
6914 /* Any variant. EQ bit. */
6918 /* Upper variant. LT bit. */
6922 /* Lower variant. GT bit. */
6927 error ("argument 1 of __builtin_spe_predicate is out of range");
6931 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
6932 emit_move_insn (target, tmp);
6937 /* The evsel builtins look like this:
6939 e = __builtin_spe_evsel_OP (a, b, c, d);
6943 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
6944 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
6948 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
6951 tree arg0 = TREE_VALUE (arglist);
6952 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6953 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6954 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
6955 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6956 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6957 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6958 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
6959 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6960 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6965 if (arg0 == error_mark_node || arg1 == error_mark_node
6966 || arg2 == error_mark_node || arg3 == error_mark_node)
6970 || GET_MODE (target) != mode0
6971 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
6972 target = gen_reg_rtx (mode0);
6974 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6975 op0 = copy_to_mode_reg (mode0, op0);
6976 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6977 op1 = copy_to_mode_reg (mode0, op1);
6978 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6979 op2 = copy_to_mode_reg (mode0, op2);
6980 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
6981 op3 = copy_to_mode_reg (mode0, op3);
6983 /* Generate the compare. */
6984 scratch = gen_reg_rtx (CCmode);
6985 pat = GEN_FCN (icode) (scratch, op0, op1);
6990 if (mode0 == V2SImode)
6991 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
6993 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
6998 /* Expand an expression EXP that calls a built-in function,
6999 with result going to TARGET if that's convenient
7000 (and in mode MODE if that's convenient).
7001 SUBTARGET may be used as the target for computing one of EXP's operands.
7002 IGNORE is nonzero if the value is to be ignored. */
7005 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7006 enum machine_mode mode ATTRIBUTE_UNUSED,
7007 int ignore ATTRIBUTE_UNUSED)
7009 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7010 tree arglist = TREE_OPERAND (exp, 1);
7011 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7012 struct builtin_description *d;
7017 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7018 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7020 int icode = (int) CODE_FOR_altivec_lvsr;
7021 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7022 enum machine_mode mode = insn_data[icode].operand[1].mode;
7026 if (!TARGET_ALTIVEC)
7029 arg = TREE_VALUE (arglist);
7030 if (TREE_CODE (TREE_TYPE (arg)) != POINTER_TYPE)
7032 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7033 addr = memory_address (mode, op);
7034 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7038 /* For the load case need to negate the address. */
7039 op = gen_reg_rtx (GET_MODE (addr));
7040 emit_insn (gen_rtx_SET (VOIDmode, op,
7041 gen_rtx_NEG (GET_MODE (addr), addr)));
7043 op = gen_rtx_MEM (mode, op);
7046 || GET_MODE (target) != tmode
7047 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7048 target = gen_reg_rtx (tmode);
7050 /*pat = gen_altivec_lvsr (target, op);*/
7051 pat = GEN_FCN (icode) (target, op);
7061 ret = altivec_expand_builtin (exp, target, &success);
7068 ret = spe_expand_builtin (exp, target, &success);
7074 if (TARGET_ALTIVEC || TARGET_SPE)
7076 /* Handle simple unary operations. */
7077 d = (struct builtin_description *) bdesc_1arg;
7078 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7079 if (d->code == fcode)
7080 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7082 /* Handle simple binary operations. */
7083 d = (struct builtin_description *) bdesc_2arg;
7084 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7085 if (d->code == fcode)
7086 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7088 /* Handle simple ternary operations. */
7089 d = (struct builtin_description *) bdesc_3arg;
7090 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7091 if (d->code == fcode)
7092 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7100 build_opaque_vector_type (tree node, int nunits)
7102 node = copy_node (node);
7103 TYPE_MAIN_VARIANT (node) = node;
7104 return build_vector_type (node, nunits);
7108 rs6000_init_builtins (void)
7110 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7111 V2SF_type_node = build_vector_type (float_type_node, 2);
7112 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7113 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7114 V4SF_type_node = build_vector_type (float_type_node, 4);
7115 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7116 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7118 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7119 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7120 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7122 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7123 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7124 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7126 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7127 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7128 'vector unsigned short'. */
7130 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7131 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7132 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7133 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7135 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7136 get_identifier ("__bool char"),
7137 bool_char_type_node));
7138 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7139 get_identifier ("__bool short"),
7140 bool_short_type_node));
7141 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7142 get_identifier ("__bool int"),
7143 bool_int_type_node));
7144 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7145 get_identifier ("__pixel"),
7148 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7149 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7150 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7151 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7153 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7154 get_identifier ("__vector unsigned char"),
7155 unsigned_V16QI_type_node));
7156 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7157 get_identifier ("__vector signed char"),
7159 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7160 get_identifier ("__vector __bool char"),
7161 bool_V16QI_type_node));
7163 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7164 get_identifier ("__vector unsigned short"),
7165 unsigned_V8HI_type_node));
7166 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7167 get_identifier ("__vector signed short"),
7169 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7170 get_identifier ("__vector __bool short"),
7171 bool_V8HI_type_node));
7173 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7174 get_identifier ("__vector unsigned int"),
7175 unsigned_V4SI_type_node));
7176 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7177 get_identifier ("__vector signed int"),
7179 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7180 get_identifier ("__vector __bool int"),
7181 bool_V4SI_type_node));
7183 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7184 get_identifier ("__vector float"),
7186 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7187 get_identifier ("__vector __pixel"),
7188 pixel_V8HI_type_node));
7191 spe_init_builtins ();
7193 altivec_init_builtins ();
7194 if (TARGET_ALTIVEC || TARGET_SPE)
7195 rs6000_common_init_builtins ();
7198 /* Search through a set of builtins and enable the mask bits.
7199 DESC is an array of builtins.
7200 SIZE is the total number of builtins.
7201 START is the builtin enum at which to start.
7202 END is the builtin enum at which to end. */
7204 enable_mask_for_builtins (struct builtin_description *desc, int size,
7205 enum rs6000_builtins start,
7206 enum rs6000_builtins end)
7210 for (i = 0; i < size; ++i)
7211 if (desc[i].code == start)
7217 for (; i < size; ++i)
7219 /* Flip all the bits on. */
7220 desc[i].mask = target_flags;
7221 if (desc[i].code == end)
7227 spe_init_builtins (void)
7229 tree endlink = void_list_node;
7230 tree puint_type_node = build_pointer_type (unsigned_type_node);
7231 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
7232 struct builtin_description *d;
7235 tree v2si_ftype_4_v2si
7236 = build_function_type
7237 (opaque_V2SI_type_node,
7238 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7239 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7240 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7241 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7244 tree v2sf_ftype_4_v2sf
7245 = build_function_type
7246 (opaque_V2SF_type_node,
7247 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7248 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7249 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7250 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7253 tree int_ftype_int_v2si_v2si
7254 = build_function_type
7256 tree_cons (NULL_TREE, integer_type_node,
7257 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7258 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7261 tree int_ftype_int_v2sf_v2sf
7262 = build_function_type
7264 tree_cons (NULL_TREE, integer_type_node,
7265 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7266 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7269 tree void_ftype_v2si_puint_int
7270 = build_function_type (void_type_node,
7271 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7272 tree_cons (NULL_TREE, puint_type_node,
7273 tree_cons (NULL_TREE,
7277 tree void_ftype_v2si_puint_char
7278 = build_function_type (void_type_node,
7279 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7280 tree_cons (NULL_TREE, puint_type_node,
7281 tree_cons (NULL_TREE,
7285 tree void_ftype_v2si_pv2si_int
7286 = build_function_type (void_type_node,
7287 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7288 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7289 tree_cons (NULL_TREE,
7293 tree void_ftype_v2si_pv2si_char
7294 = build_function_type (void_type_node,
7295 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7296 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7297 tree_cons (NULL_TREE,
7302 = build_function_type (void_type_node,
7303 tree_cons (NULL_TREE, integer_type_node, endlink));
7306 = build_function_type (integer_type_node, endlink);
7308 tree v2si_ftype_pv2si_int
7309 = build_function_type (opaque_V2SI_type_node,
7310 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7311 tree_cons (NULL_TREE, integer_type_node,
7314 tree v2si_ftype_puint_int
7315 = build_function_type (opaque_V2SI_type_node,
7316 tree_cons (NULL_TREE, puint_type_node,
7317 tree_cons (NULL_TREE, integer_type_node,
7320 tree v2si_ftype_pushort_int
7321 = build_function_type (opaque_V2SI_type_node,
7322 tree_cons (NULL_TREE, pushort_type_node,
7323 tree_cons (NULL_TREE, integer_type_node,
7326 tree v2si_ftype_signed_char
7327 = build_function_type (opaque_V2SI_type_node,
7328 tree_cons (NULL_TREE, signed_char_type_node,
7331 /* The initialization of the simple binary and unary builtins is
7332 done in rs6000_common_init_builtins, but we have to enable the
7333 mask bits here manually because we have run out of `target_flags'
7334 bits. We really need to redesign this mask business. */
7336 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
7337 ARRAY_SIZE (bdesc_2arg),
7340 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
7341 ARRAY_SIZE (bdesc_1arg),
7343 SPE_BUILTIN_EVSUBFUSIAAW);
7344 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
7345 ARRAY_SIZE (bdesc_spe_predicates),
7346 SPE_BUILTIN_EVCMPEQ,
7347 SPE_BUILTIN_EVFSTSTLT);
7348 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
7349 ARRAY_SIZE (bdesc_spe_evsel),
7350 SPE_BUILTIN_EVSEL_CMPGTS,
7351 SPE_BUILTIN_EVSEL_FSTSTEQ);
7353 (*lang_hooks.decls.pushdecl)
7354 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
7355 opaque_V2SI_type_node));
7357 /* Initialize irregular SPE builtins. */
7359 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
7360 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
7361 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
7362 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
7363 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
7364 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
7365 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
7366 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
7367 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
7368 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
7369 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
7370 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
7371 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
7372 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
7373 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
7374 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
7375 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
7376 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
7379 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
7380 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
7381 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
7382 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
7383 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
7384 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
7385 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
7386 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
7387 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
7388 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
7389 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
7390 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
7391 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
7392 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
7393 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
7394 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
7395 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
7396 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
7397 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
7398 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
7399 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
7400 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
7403 d = (struct builtin_description *) bdesc_spe_predicates;
7404 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
7408 switch (insn_data[d->icode].operand[1].mode)
7411 type = int_ftype_int_v2si_v2si;
7414 type = int_ftype_int_v2sf_v2sf;
7420 def_builtin (d->mask, d->name, type, d->code);
7423 /* Evsel predicates. */
7424 d = (struct builtin_description *) bdesc_spe_evsel;
7425 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
7429 switch (insn_data[d->icode].operand[1].mode)
7432 type = v2si_ftype_4_v2si;
7435 type = v2sf_ftype_4_v2sf;
7441 def_builtin (d->mask, d->name, type, d->code);
7446 altivec_init_builtins (void)
7448 struct builtin_description *d;
7449 struct builtin_description_predicates *dp;
7451 tree pfloat_type_node = build_pointer_type (float_type_node);
7452 tree pint_type_node = build_pointer_type (integer_type_node);
7453 tree pshort_type_node = build_pointer_type (short_integer_type_node);
7454 tree pchar_type_node = build_pointer_type (char_type_node);
7456 tree pvoid_type_node = build_pointer_type (void_type_node);
7458 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
7459 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
7460 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
7461 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
7463 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
7465 tree int_ftype_int_v4si_v4si
7466 = build_function_type_list (integer_type_node,
7467 integer_type_node, V4SI_type_node,
7468 V4SI_type_node, NULL_TREE);
7469 tree v4sf_ftype_pcfloat
7470 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
7471 tree void_ftype_pfloat_v4sf
7472 = build_function_type_list (void_type_node,
7473 pfloat_type_node, V4SF_type_node, NULL_TREE);
7474 tree v4si_ftype_pcint
7475 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
7476 tree void_ftype_pint_v4si
7477 = build_function_type_list (void_type_node,
7478 pint_type_node, V4SI_type_node, NULL_TREE);
7479 tree v8hi_ftype_pcshort
7480 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
7481 tree void_ftype_pshort_v8hi
7482 = build_function_type_list (void_type_node,
7483 pshort_type_node, V8HI_type_node, NULL_TREE);
7484 tree v16qi_ftype_pcchar
7485 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
7486 tree void_ftype_pchar_v16qi
7487 = build_function_type_list (void_type_node,
7488 pchar_type_node, V16QI_type_node, NULL_TREE);
7489 tree void_ftype_v4si
7490 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
7491 tree v8hi_ftype_void
7492 = build_function_type (V8HI_type_node, void_list_node);
7493 tree void_ftype_void
7494 = build_function_type (void_type_node, void_list_node);
7496 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
7498 tree v16qi_ftype_long_pcvoid
7499 = build_function_type_list (V16QI_type_node,
7500 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7501 tree v8hi_ftype_long_pcvoid
7502 = build_function_type_list (V8HI_type_node,
7503 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7504 tree v4si_ftype_long_pcvoid
7505 = build_function_type_list (V4SI_type_node,
7506 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7508 tree void_ftype_v4si_long_pvoid
7509 = build_function_type_list (void_type_node,
7510 V4SI_type_node, long_integer_type_node,
7511 pvoid_type_node, NULL_TREE);
7512 tree void_ftype_v16qi_long_pvoid
7513 = build_function_type_list (void_type_node,
7514 V16QI_type_node, long_integer_type_node,
7515 pvoid_type_node, NULL_TREE);
7516 tree void_ftype_v8hi_long_pvoid
7517 = build_function_type_list (void_type_node,
7518 V8HI_type_node, long_integer_type_node,
7519 pvoid_type_node, NULL_TREE);
7520 tree int_ftype_int_v8hi_v8hi
7521 = build_function_type_list (integer_type_node,
7522 integer_type_node, V8HI_type_node,
7523 V8HI_type_node, NULL_TREE);
7524 tree int_ftype_int_v16qi_v16qi
7525 = build_function_type_list (integer_type_node,
7526 integer_type_node, V16QI_type_node,
7527 V16QI_type_node, NULL_TREE);
7528 tree int_ftype_int_v4sf_v4sf
7529 = build_function_type_list (integer_type_node,
7530 integer_type_node, V4SF_type_node,
7531 V4SF_type_node, NULL_TREE);
7532 tree v4si_ftype_v4si
7533 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
7534 tree v8hi_ftype_v8hi
7535 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
7536 tree v16qi_ftype_v16qi
7537 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
7538 tree v4sf_ftype_v4sf
7539 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7540 tree void_ftype_pcvoid_int_int
7541 = build_function_type_list (void_type_node,
7542 pcvoid_type_node, integer_type_node,
7543 integer_type_node, NULL_TREE);
7544 tree int_ftype_pcchar
7545 = build_function_type_list (integer_type_node,
7546 pcchar_type_node, NULL_TREE);
7548 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
7549 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
7550 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
7551 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
7552 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
7553 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
7554 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
7555 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
7556 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
7557 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
7558 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
7559 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
7560 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
7561 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
7562 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
7563 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
7564 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
7565 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
7566 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
7567 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
7568 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
7569 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
7570 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
7571 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
7572 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
7573 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
7574 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
7575 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
7576 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
7577 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
7578 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
7579 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
7581 /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */
7582 def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar,
7583 ALTIVEC_BUILTIN_COMPILETIME_ERROR);
7585 /* Add the DST variants. */
7586 d = (struct builtin_description *) bdesc_dst;
7587 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7588 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
7590 /* Initialize the predicates. */
7591 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7592 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7594 enum machine_mode mode1;
7597 mode1 = insn_data[dp->icode].operand[1].mode;
7602 type = int_ftype_int_v4si_v4si;
7605 type = int_ftype_int_v8hi_v8hi;
7608 type = int_ftype_int_v16qi_v16qi;
7611 type = int_ftype_int_v4sf_v4sf;
7617 def_builtin (dp->mask, dp->name, type, dp->code);
7620 /* Initialize the abs* operators. */
7621 d = (struct builtin_description *) bdesc_abs;
7622 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7624 enum machine_mode mode0;
7627 mode0 = insn_data[d->icode].operand[0].mode;
7632 type = v4si_ftype_v4si;
7635 type = v8hi_ftype_v8hi;
7638 type = v16qi_ftype_v16qi;
7641 type = v4sf_ftype_v4sf;
7647 def_builtin (d->mask, d->name, type, d->code);
7654 /* Initialize target builtin that implements
7655 targetm.vectorize.builtin_mask_for_load. */
7657 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
7658 v16qi_ftype_long_pcvoid,
7659 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
7661 tree_cons (get_identifier ("const"),
7662 NULL_TREE, NULL_TREE));
7663 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
7664 altivec_builtin_mask_for_load = decl;
7669 rs6000_common_init_builtins (void)
7671 struct builtin_description *d;
7674 tree v4sf_ftype_v4sf_v4sf_v16qi
7675 = build_function_type_list (V4SF_type_node,
7676 V4SF_type_node, V4SF_type_node,
7677 V16QI_type_node, NULL_TREE);
7678 tree v4si_ftype_v4si_v4si_v16qi
7679 = build_function_type_list (V4SI_type_node,
7680 V4SI_type_node, V4SI_type_node,
7681 V16QI_type_node, NULL_TREE);
7682 tree v8hi_ftype_v8hi_v8hi_v16qi
7683 = build_function_type_list (V8HI_type_node,
7684 V8HI_type_node, V8HI_type_node,
7685 V16QI_type_node, NULL_TREE);
7686 tree v16qi_ftype_v16qi_v16qi_v16qi
7687 = build_function_type_list (V16QI_type_node,
7688 V16QI_type_node, V16QI_type_node,
7689 V16QI_type_node, NULL_TREE);
7691 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
7693 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
7694 tree v16qi_ftype_int
7695 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
7696 tree v8hi_ftype_v16qi
7697 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
7698 tree v4sf_ftype_v4sf
7699 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7701 tree v2si_ftype_v2si_v2si
7702 = build_function_type_list (opaque_V2SI_type_node,
7703 opaque_V2SI_type_node,
7704 opaque_V2SI_type_node, NULL_TREE);
7706 tree v2sf_ftype_v2sf_v2sf
7707 = build_function_type_list (opaque_V2SF_type_node,
7708 opaque_V2SF_type_node,
7709 opaque_V2SF_type_node, NULL_TREE);
7711 tree v2si_ftype_int_int
7712 = build_function_type_list (opaque_V2SI_type_node,
7713 integer_type_node, integer_type_node,
7716 tree v2si_ftype_v2si
7717 = build_function_type_list (opaque_V2SI_type_node,
7718 opaque_V2SI_type_node, NULL_TREE);
7720 tree v2sf_ftype_v2sf
7721 = build_function_type_list (opaque_V2SF_type_node,
7722 opaque_V2SF_type_node, NULL_TREE);
7724 tree v2sf_ftype_v2si
7725 = build_function_type_list (opaque_V2SF_type_node,
7726 opaque_V2SI_type_node, NULL_TREE);
7728 tree v2si_ftype_v2sf
7729 = build_function_type_list (opaque_V2SI_type_node,
7730 opaque_V2SF_type_node, NULL_TREE);
7732 tree v2si_ftype_v2si_char
7733 = build_function_type_list (opaque_V2SI_type_node,
7734 opaque_V2SI_type_node,
7735 char_type_node, NULL_TREE);
7737 tree v2si_ftype_int_char
7738 = build_function_type_list (opaque_V2SI_type_node,
7739 integer_type_node, char_type_node, NULL_TREE);
7741 tree v2si_ftype_char
7742 = build_function_type_list (opaque_V2SI_type_node,
7743 char_type_node, NULL_TREE);
7745 tree int_ftype_int_int
7746 = build_function_type_list (integer_type_node,
7747 integer_type_node, integer_type_node,
7750 tree v4si_ftype_v4si_v4si
7751 = build_function_type_list (V4SI_type_node,
7752 V4SI_type_node, V4SI_type_node, NULL_TREE);
7753 tree v4sf_ftype_v4si_int
7754 = build_function_type_list (V4SF_type_node,
7755 V4SI_type_node, integer_type_node, NULL_TREE);
7756 tree v4si_ftype_v4sf_int
7757 = build_function_type_list (V4SI_type_node,
7758 V4SF_type_node, integer_type_node, NULL_TREE);
7759 tree v4si_ftype_v4si_int
7760 = build_function_type_list (V4SI_type_node,
7761 V4SI_type_node, integer_type_node, NULL_TREE);
7762 tree v8hi_ftype_v8hi_int
7763 = build_function_type_list (V8HI_type_node,
7764 V8HI_type_node, integer_type_node, NULL_TREE);
7765 tree v16qi_ftype_v16qi_int
7766 = build_function_type_list (V16QI_type_node,
7767 V16QI_type_node, integer_type_node, NULL_TREE);
7768 tree v16qi_ftype_v16qi_v16qi_int
7769 = build_function_type_list (V16QI_type_node,
7770 V16QI_type_node, V16QI_type_node,
7771 integer_type_node, NULL_TREE);
7772 tree v8hi_ftype_v8hi_v8hi_int
7773 = build_function_type_list (V8HI_type_node,
7774 V8HI_type_node, V8HI_type_node,
7775 integer_type_node, NULL_TREE);
7776 tree v4si_ftype_v4si_v4si_int
7777 = build_function_type_list (V4SI_type_node,
7778 V4SI_type_node, V4SI_type_node,
7779 integer_type_node, NULL_TREE);
7780 tree v4sf_ftype_v4sf_v4sf_int
7781 = build_function_type_list (V4SF_type_node,
7782 V4SF_type_node, V4SF_type_node,
7783 integer_type_node, NULL_TREE);
7784 tree v4sf_ftype_v4sf_v4sf
7785 = build_function_type_list (V4SF_type_node,
7786 V4SF_type_node, V4SF_type_node, NULL_TREE);
7787 tree v4sf_ftype_v4sf_v4sf_v4si
7788 = build_function_type_list (V4SF_type_node,
7789 V4SF_type_node, V4SF_type_node,
7790 V4SI_type_node, NULL_TREE);
7791 tree v4sf_ftype_v4sf_v4sf_v4sf
7792 = build_function_type_list (V4SF_type_node,
7793 V4SF_type_node, V4SF_type_node,
7794 V4SF_type_node, NULL_TREE);
7795 tree v4si_ftype_v4si_v4si_v4si
7796 = build_function_type_list (V4SI_type_node,
7797 V4SI_type_node, V4SI_type_node,
7798 V4SI_type_node, NULL_TREE);
7799 tree v8hi_ftype_v8hi_v8hi
7800 = build_function_type_list (V8HI_type_node,
7801 V8HI_type_node, V8HI_type_node, NULL_TREE);
7802 tree v8hi_ftype_v8hi_v8hi_v8hi
7803 = build_function_type_list (V8HI_type_node,
7804 V8HI_type_node, V8HI_type_node,
7805 V8HI_type_node, NULL_TREE);
7806 tree v4si_ftype_v8hi_v8hi_v4si
7807 = build_function_type_list (V4SI_type_node,
7808 V8HI_type_node, V8HI_type_node,
7809 V4SI_type_node, NULL_TREE);
7810 tree v4si_ftype_v16qi_v16qi_v4si
7811 = build_function_type_list (V4SI_type_node,
7812 V16QI_type_node, V16QI_type_node,
7813 V4SI_type_node, NULL_TREE);
7814 tree v16qi_ftype_v16qi_v16qi
7815 = build_function_type_list (V16QI_type_node,
7816 V16QI_type_node, V16QI_type_node, NULL_TREE);
7817 tree v4si_ftype_v4sf_v4sf
7818 = build_function_type_list (V4SI_type_node,
7819 V4SF_type_node, V4SF_type_node, NULL_TREE);
7820 tree v8hi_ftype_v16qi_v16qi
7821 = build_function_type_list (V8HI_type_node,
7822 V16QI_type_node, V16QI_type_node, NULL_TREE);
7823 tree v4si_ftype_v8hi_v8hi
7824 = build_function_type_list (V4SI_type_node,
7825 V8HI_type_node, V8HI_type_node, NULL_TREE);
7826 tree v8hi_ftype_v4si_v4si
7827 = build_function_type_list (V8HI_type_node,
7828 V4SI_type_node, V4SI_type_node, NULL_TREE);
7829 tree v16qi_ftype_v8hi_v8hi
7830 = build_function_type_list (V16QI_type_node,
7831 V8HI_type_node, V8HI_type_node, NULL_TREE);
7832 tree v4si_ftype_v16qi_v4si
7833 = build_function_type_list (V4SI_type_node,
7834 V16QI_type_node, V4SI_type_node, NULL_TREE);
7835 tree v4si_ftype_v16qi_v16qi
7836 = build_function_type_list (V4SI_type_node,
7837 V16QI_type_node, V16QI_type_node, NULL_TREE);
7838 tree v4si_ftype_v8hi_v4si
7839 = build_function_type_list (V4SI_type_node,
7840 V8HI_type_node, V4SI_type_node, NULL_TREE);
7841 tree v4si_ftype_v8hi
7842 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
7843 tree int_ftype_v4si_v4si
7844 = build_function_type_list (integer_type_node,
7845 V4SI_type_node, V4SI_type_node, NULL_TREE);
7846 tree int_ftype_v4sf_v4sf
7847 = build_function_type_list (integer_type_node,
7848 V4SF_type_node, V4SF_type_node, NULL_TREE);
7849 tree int_ftype_v16qi_v16qi
7850 = build_function_type_list (integer_type_node,
7851 V16QI_type_node, V16QI_type_node, NULL_TREE);
7852 tree int_ftype_v8hi_v8hi
7853 = build_function_type_list (integer_type_node,
7854 V8HI_type_node, V8HI_type_node, NULL_TREE);
7856 /* Add the simple ternary operators. */
7857 d = (struct builtin_description *) bdesc_3arg;
7858 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7861 enum machine_mode mode0, mode1, mode2, mode3;
7864 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7867 mode0 = insn_data[d->icode].operand[0].mode;
7868 mode1 = insn_data[d->icode].operand[1].mode;
7869 mode2 = insn_data[d->icode].operand[2].mode;
7870 mode3 = insn_data[d->icode].operand[3].mode;
7872 /* When all four are of the same mode. */
7873 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
7878 type = v4si_ftype_v4si_v4si_v4si;
7881 type = v4sf_ftype_v4sf_v4sf_v4sf;
7884 type = v8hi_ftype_v8hi_v8hi_v8hi;
7887 type = v16qi_ftype_v16qi_v16qi_v16qi;
7893 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
7898 type = v4si_ftype_v4si_v4si_v16qi;
7901 type = v4sf_ftype_v4sf_v4sf_v16qi;
7904 type = v8hi_ftype_v8hi_v8hi_v16qi;
7907 type = v16qi_ftype_v16qi_v16qi_v16qi;
7913 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
7914 && mode3 == V4SImode)
7915 type = v4si_ftype_v16qi_v16qi_v4si;
7916 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
7917 && mode3 == V4SImode)
7918 type = v4si_ftype_v8hi_v8hi_v4si;
7919 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
7920 && mode3 == V4SImode)
7921 type = v4sf_ftype_v4sf_v4sf_v4si;
7923 /* vchar, vchar, vchar, 4 bit literal. */
7924 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
7926 type = v16qi_ftype_v16qi_v16qi_int;
7928 /* vshort, vshort, vshort, 4 bit literal. */
7929 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
7931 type = v8hi_ftype_v8hi_v8hi_int;
7933 /* vint, vint, vint, 4 bit literal. */
7934 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
7936 type = v4si_ftype_v4si_v4si_int;
7938 /* vfloat, vfloat, vfloat, 4 bit literal. */
7939 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
7941 type = v4sf_ftype_v4sf_v4sf_int;
7946 def_builtin (d->mask, d->name, type, d->code);
7949 /* Add the simple binary operators. */
7950 d = (struct builtin_description *) bdesc_2arg;
7951 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7953 enum machine_mode mode0, mode1, mode2;
7956 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7959 mode0 = insn_data[d->icode].operand[0].mode;
7960 mode1 = insn_data[d->icode].operand[1].mode;
7961 mode2 = insn_data[d->icode].operand[2].mode;
7963 /* When all three operands are of the same mode. */
7964 if (mode0 == mode1 && mode1 == mode2)
7969 type = v4sf_ftype_v4sf_v4sf;
7972 type = v4si_ftype_v4si_v4si;
7975 type = v16qi_ftype_v16qi_v16qi;
7978 type = v8hi_ftype_v8hi_v8hi;
7981 type = v2si_ftype_v2si_v2si;
7984 type = v2sf_ftype_v2sf_v2sf;
7987 type = int_ftype_int_int;
7994 /* A few other combos we really don't want to do manually. */
7996 /* vint, vfloat, vfloat. */
7997 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
7998 type = v4si_ftype_v4sf_v4sf;
8000 /* vshort, vchar, vchar. */
8001 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8002 type = v8hi_ftype_v16qi_v16qi;
8004 /* vint, vshort, vshort. */
8005 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8006 type = v4si_ftype_v8hi_v8hi;
8008 /* vshort, vint, vint. */
8009 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8010 type = v8hi_ftype_v4si_v4si;
8012 /* vchar, vshort, vshort. */
8013 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8014 type = v16qi_ftype_v8hi_v8hi;
8016 /* vint, vchar, vint. */
8017 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8018 type = v4si_ftype_v16qi_v4si;
8020 /* vint, vchar, vchar. */
8021 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8022 type = v4si_ftype_v16qi_v16qi;
8024 /* vint, vshort, vint. */
8025 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8026 type = v4si_ftype_v8hi_v4si;
8028 /* vint, vint, 5 bit literal. */
8029 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
8030 type = v4si_ftype_v4si_int;
8032 /* vshort, vshort, 5 bit literal. */
8033 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8034 type = v8hi_ftype_v8hi_int;
8036 /* vchar, vchar, 5 bit literal. */
8037 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8038 type = v16qi_ftype_v16qi_int;
8040 /* vfloat, vint, 5 bit literal. */
8041 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8042 type = v4sf_ftype_v4si_int;
8044 /* vint, vfloat, 5 bit literal. */
8045 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
8046 type = v4si_ftype_v4sf_int;
8048 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8049 type = v2si_ftype_int_int;
8051 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8052 type = v2si_ftype_v2si_char;
8054 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8055 type = v2si_ftype_int_char;
8058 else if (mode0 == SImode)
8063 type = int_ftype_v4si_v4si;
8066 type = int_ftype_v4sf_v4sf;
8069 type = int_ftype_v16qi_v16qi;
8072 type = int_ftype_v8hi_v8hi;
8082 def_builtin (d->mask, d->name, type, d->code);
8085 /* Add the simple unary operators. */
8086 d = (struct builtin_description *) bdesc_1arg;
8087 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8089 enum machine_mode mode0, mode1;
8092 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8095 mode0 = insn_data[d->icode].operand[0].mode;
8096 mode1 = insn_data[d->icode].operand[1].mode;
8098 if (mode0 == V4SImode && mode1 == QImode)
8099 type = v4si_ftype_int;
8100 else if (mode0 == V8HImode && mode1 == QImode)
8101 type = v8hi_ftype_int;
8102 else if (mode0 == V16QImode && mode1 == QImode)
8103 type = v16qi_ftype_int;
8104 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8105 type = v4sf_ftype_v4sf;
8106 else if (mode0 == V8HImode && mode1 == V16QImode)
8107 type = v8hi_ftype_v16qi;
8108 else if (mode0 == V4SImode && mode1 == V8HImode)
8109 type = v4si_ftype_v8hi;
8110 else if (mode0 == V2SImode && mode1 == V2SImode)
8111 type = v2si_ftype_v2si;
8112 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8113 type = v2sf_ftype_v2sf;
8114 else if (mode0 == V2SFmode && mode1 == V2SImode)
8115 type = v2sf_ftype_v2si;
8116 else if (mode0 == V2SImode && mode1 == V2SFmode)
8117 type = v2si_ftype_v2sf;
8118 else if (mode0 == V2SImode && mode1 == QImode)
8119 type = v2si_ftype_char;
8123 def_builtin (d->mask, d->name, type, d->code);
8128 rs6000_init_libfuncs (void)
8130 if (!TARGET_HARD_FLOAT)
8133 if (DEFAULT_ABI != ABI_V4)
8135 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
8137 /* AIX library routines for float->int conversion. */
8138 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
8139 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
8140 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
8141 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
8144 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
8145 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
8146 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
8147 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
8148 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
8152 /* 32-bit SVR4 quad floating point routines. */
8154 set_optab_libfunc (add_optab, TFmode, "_q_add");
8155 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
8156 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
8157 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
8158 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
8159 if (TARGET_PPC_GPOPT || TARGET_POWER2)
8160 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
8162 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
8163 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
8164 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
8165 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
8166 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
8167 set_optab_libfunc (le_optab, TFmode, "_q_fle");
8169 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
8170 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
8171 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
8172 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
8173 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
8174 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
8175 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
8180 /* Expand a block clear operation, and return 1 if successful. Return 0
8181 if we should let the compiler generate normal code.
8183 operands[0] is the destination
8184 operands[1] is the length
8185 operands[2] is the alignment */
8188 expand_block_clear (rtx operands[])
8190 rtx orig_dest = operands[0];
8191 rtx bytes_rtx = operands[1];
8192 rtx align_rtx = operands[2];
8193 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
8194 HOST_WIDE_INT align;
8195 HOST_WIDE_INT bytes;
8200 /* If this is not a fixed size move, just call memcpy */
8204 /* If this is not a fixed size alignment, abort */
8205 if (GET_CODE (align_rtx) != CONST_INT)
8207 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8209 /* Anything to clear? */
8210 bytes = INTVAL (bytes_rtx);
8214 /* Use the builtin memset after a point, to avoid huge code bloat.
8215 When optimize_size, avoid any significant code bloat; calling
8216 memset is about 4 instructions, so allow for one instruction to
8217 load zero and three to do clearing. */
8218 if (TARGET_ALTIVEC && align >= 128)
8220 else if (TARGET_POWERPC64 && align >= 32)
8225 if (optimize_size && bytes > 3 * clear_step)
8227 if (! optimize_size && bytes > 8 * clear_step)
8230 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
8232 enum machine_mode mode = BLKmode;
8235 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
8240 else if (bytes >= 8 && TARGET_POWERPC64
8241 /* 64-bit loads and stores require word-aligned
8243 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8248 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
8249 { /* move 4 bytes */
8253 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
8254 { /* move 2 bytes */
8258 else /* move 1 byte at a time */
8264 dest = adjust_address (orig_dest, mode, offset);
8266 emit_move_insn (dest, CONST0_RTX (mode));
8273 /* Expand a block move operation, and return 1 if successful. Return 0
8274 if we should let the compiler generate normal code.
8276 operands[0] is the destination
8277 operands[1] is the source
8278 operands[2] is the length
8279 operands[3] is the alignment */
8281 #define MAX_MOVE_REG 4
8284 expand_block_move (rtx operands[])
8286 rtx orig_dest = operands[0];
8287 rtx orig_src = operands[1];
8288 rtx bytes_rtx = operands[2];
8289 rtx align_rtx = operands[3];
8290 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
8295 rtx stores[MAX_MOVE_REG];
8298 /* If this is not a fixed size move, just call memcpy */
8302 /* If this is not a fixed size alignment, abort */
8303 if (GET_CODE (align_rtx) != CONST_INT)
8305 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8307 /* Anything to move? */
8308 bytes = INTVAL (bytes_rtx);
8312 /* store_one_arg depends on expand_block_move to handle at least the size of
8313 reg_parm_stack_space. */
8314 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
8317 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
8320 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
8321 rtx (*mov) (rtx, rtx);
8323 enum machine_mode mode = BLKmode;
8326 /* Altivec first, since it will be faster than a string move
8327 when it applies, and usually not significantly larger. */
8328 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
8332 gen_func.mov = gen_movv4si;
8334 else if (TARGET_STRING
8335 && bytes > 24 /* move up to 32 bytes at a time */
8343 && ! fixed_regs[12])
8345 move_bytes = (bytes > 32) ? 32 : bytes;
8346 gen_func.movmemsi = gen_movmemsi_8reg;
8348 else if (TARGET_STRING
8349 && bytes > 16 /* move up to 24 bytes at a time */
8355 && ! fixed_regs[10])
8357 move_bytes = (bytes > 24) ? 24 : bytes;
8358 gen_func.movmemsi = gen_movmemsi_6reg;
8360 else if (TARGET_STRING
8361 && bytes > 8 /* move up to 16 bytes at a time */
8367 move_bytes = (bytes > 16) ? 16 : bytes;
8368 gen_func.movmemsi = gen_movmemsi_4reg;
8370 else if (bytes >= 8 && TARGET_POWERPC64
8371 /* 64-bit loads and stores require word-aligned
8373 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8377 gen_func.mov = gen_movdi;
8379 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
8380 { /* move up to 8 bytes at a time */
8381 move_bytes = (bytes > 8) ? 8 : bytes;
8382 gen_func.movmemsi = gen_movmemsi_2reg;
8384 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
8385 { /* move 4 bytes */
8388 gen_func.mov = gen_movsi;
8390 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
8391 { /* move 2 bytes */
8394 gen_func.mov = gen_movhi;
8396 else if (TARGET_STRING && bytes > 1)
8397 { /* move up to 4 bytes at a time */
8398 move_bytes = (bytes > 4) ? 4 : bytes;
8399 gen_func.movmemsi = gen_movmemsi_1reg;
8401 else /* move 1 byte at a time */
8405 gen_func.mov = gen_movqi;
8408 src = adjust_address (orig_src, mode, offset);
8409 dest = adjust_address (orig_dest, mode, offset);
8411 if (mode != BLKmode)
8413 rtx tmp_reg = gen_reg_rtx (mode);
8415 emit_insn ((*gen_func.mov) (tmp_reg, src));
8416 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
8419 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
8422 for (i = 0; i < num_reg; i++)
8423 emit_insn (stores[i]);
8427 if (mode == BLKmode)
8429 /* Move the address into scratch registers. The movmemsi
8430 patterns require zero offset. */
8431 if (!REG_P (XEXP (src, 0)))
8433 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
8434 src = replace_equiv_address (src, src_reg);
8436 set_mem_size (src, GEN_INT (move_bytes));
8438 if (!REG_P (XEXP (dest, 0)))
8440 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
8441 dest = replace_equiv_address (dest, dest_reg);
8443 set_mem_size (dest, GEN_INT (move_bytes));
8445 emit_insn ((*gen_func.movmemsi) (dest, src,
8446 GEN_INT (move_bytes & 31),
8455 /* Return a string to perform a load_multiple operation.
8456 operands[0] is the vector.
8457 operands[1] is the source address.
8458 operands[2] is the first destination register. */
8461 rs6000_output_load_multiple (rtx operands[3])
8463 /* We have to handle the case where the pseudo used to contain the address
8464 is assigned to one of the output registers. */
8466 int words = XVECLEN (operands[0], 0);
8469 if (XVECLEN (operands[0], 0) == 1)
8470 return "{l|lwz} %2,0(%1)";
8472 for (i = 0; i < words; i++)
8473 if (refers_to_regno_p (REGNO (operands[2]) + i,
8474 REGNO (operands[2]) + i + 1, operands[1], 0))
8478 xop[0] = GEN_INT (4 * (words-1));
8479 xop[1] = operands[1];
8480 xop[2] = operands[2];
8481 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
8486 xop[0] = GEN_INT (4 * (words-1));
8487 xop[1] = operands[1];
8488 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
8489 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
8494 for (j = 0; j < words; j++)
8497 xop[0] = GEN_INT (j * 4);
8498 xop[1] = operands[1];
8499 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
8500 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
8502 xop[0] = GEN_INT (i * 4);
8503 xop[1] = operands[1];
8504 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
8509 return "{lsi|lswi} %2,%1,%N0";
8513 /* A validation routine: say whether CODE, a condition code, and MODE
8514 match. The other alternatives either don't make sense or should
8515 never be generated. */
8518 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
8520 if ((GET_RTX_CLASS (code) != RTX_COMPARE
8521 && GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
8522 || GET_MODE_CLASS (mode) != MODE_CC)
8525 /* These don't make sense. */
8526 if ((code == GT || code == LT || code == GE || code == LE)
8527 && mode == CCUNSmode)
8530 if ((code == GTU || code == LTU || code == GEU || code == LEU)
8531 && mode != CCUNSmode)
8534 if (mode != CCFPmode
8535 && (code == ORDERED || code == UNORDERED
8536 || code == UNEQ || code == LTGT
8537 || code == UNGT || code == UNLT
8538 || code == UNGE || code == UNLE))
8541 /* These should never be generated except for
8542 flag_finite_math_only. */
8543 if (mode == CCFPmode
8544 && ! flag_finite_math_only
8545 && (code == LE || code == GE
8546 || code == UNEQ || code == LTGT
8547 || code == UNGT || code == UNLT))
8550 /* These are invalid; the information is not there. */
8551 if (mode == CCEQmode
8552 && code != EQ && code != NE)
8557 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
8558 mask required to convert the result of a rotate insn into a shift
8559 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
8562 includes_lshift_p (rtx shiftop, rtx andop)
8564 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8566 shift_mask <<= INTVAL (shiftop);
8568 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8571 /* Similar, but for right shift. */
8574 includes_rshift_p (rtx shiftop, rtx andop)
8576 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8578 shift_mask >>= INTVAL (shiftop);
8580 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8583 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
8584 to perform a left shift. It must have exactly SHIFTOP least
8585 significant 0's, then one or more 1's, then zero or more 0's. */
8588 includes_rldic_lshift_p (rtx shiftop, rtx andop)
8590 if (GET_CODE (andop) == CONST_INT)
8592 HOST_WIDE_INT c, lsb, shift_mask;
8595 if (c == 0 || c == ~0)
8599 shift_mask <<= INTVAL (shiftop);
8601 /* Find the least significant one bit. */
8604 /* It must coincide with the LSB of the shift mask. */
8605 if (-lsb != shift_mask)
8608 /* Invert to look for the next transition (if any). */
8611 /* Remove the low group of ones (originally low group of zeros). */
8614 /* Again find the lsb, and check we have all 1's above. */
8618 else if (GET_CODE (andop) == CONST_DOUBLE
8619 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8621 HOST_WIDE_INT low, high, lsb;
8622 HOST_WIDE_INT shift_mask_low, shift_mask_high;
8624 low = CONST_DOUBLE_LOW (andop);
8625 if (HOST_BITS_PER_WIDE_INT < 64)
8626 high = CONST_DOUBLE_HIGH (andop);
8628 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
8629 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
8632 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8634 shift_mask_high = ~0;
8635 if (INTVAL (shiftop) > 32)
8636 shift_mask_high <<= INTVAL (shiftop) - 32;
8640 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
8647 return high == -lsb;
8650 shift_mask_low = ~0;
8651 shift_mask_low <<= INTVAL (shiftop);
8655 if (-lsb != shift_mask_low)
8658 if (HOST_BITS_PER_WIDE_INT < 64)
8663 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8666 return high == -lsb;
8670 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
8676 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
8677 to perform a left shift. It must have SHIFTOP or more least
8678 significant 0's, with the remainder of the word 1's. */
8681 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
8683 if (GET_CODE (andop) == CONST_INT)
8685 HOST_WIDE_INT c, lsb, shift_mask;
8688 shift_mask <<= INTVAL (shiftop);
8691 /* Find the least significant one bit. */
8694 /* It must be covered by the shift mask.
8695 This test also rejects c == 0. */
8696 if ((lsb & shift_mask) == 0)
8699 /* Check we have all 1's above the transition, and reject all 1's. */
8700 return c == -lsb && lsb != 1;
8702 else if (GET_CODE (andop) == CONST_DOUBLE
8703 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8705 HOST_WIDE_INT low, lsb, shift_mask_low;
8707 low = CONST_DOUBLE_LOW (andop);
8709 if (HOST_BITS_PER_WIDE_INT < 64)
8711 HOST_WIDE_INT high, shift_mask_high;
8713 high = CONST_DOUBLE_HIGH (andop);
8717 shift_mask_high = ~0;
8718 if (INTVAL (shiftop) > 32)
8719 shift_mask_high <<= INTVAL (shiftop) - 32;
8723 if ((lsb & shift_mask_high) == 0)
8726 return high == -lsb;
8732 shift_mask_low = ~0;
8733 shift_mask_low <<= INTVAL (shiftop);
8737 if ((lsb & shift_mask_low) == 0)
8740 return low == -lsb && lsb != 1;
8746 /* Return 1 if operands will generate a valid arguments to rlwimi
8747 instruction for insert with right shift in 64-bit mode. The mask may
8748 not start on the first bit or stop on the last bit because wrap-around
8749 effects of instruction do not correspond to semantics of RTL insn. */
8752 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
8754 if (INTVAL (startop) < 64
8755 && INTVAL (startop) > 32
8756 && (INTVAL (sizeop) + INTVAL (startop) < 64)
8757 && (INTVAL (sizeop) + INTVAL (startop) > 33)
8758 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
8759 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
8760 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
8766 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
8767 for lfq and stfq insns iff the registers are hard registers. */
8770 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
8772 /* We might have been passed a SUBREG. */
8773 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
8776 /* We might have been passed non floating point registers. */
8777 if (!FP_REGNO_P (REGNO (reg1))
8778 || !FP_REGNO_P (REGNO (reg2)))
8781 return (REGNO (reg1) == REGNO (reg2) - 1);
8784 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
8785 addr1 and addr2 must be in consecutive memory locations
8786 (addr2 == addr1 + 8). */
8789 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
8795 /* The mems cannot be volatile. */
8796 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
8799 addr1 = XEXP (mem1, 0);
8800 addr2 = XEXP (mem2, 0);
8802 /* Extract an offset (if used) from the first addr. */
8803 if (GET_CODE (addr1) == PLUS)
8805 /* If not a REG, return zero. */
8806 if (GET_CODE (XEXP (addr1, 0)) != REG)
8810 reg1 = REGNO (XEXP (addr1, 0));
8811 /* The offset must be constant! */
8812 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
8814 offset1 = INTVAL (XEXP (addr1, 1));
8817 else if (GET_CODE (addr1) != REG)
8821 reg1 = REGNO (addr1);
8822 /* This was a simple (mem (reg)) expression. Offset is 0. */
8826 /* Make sure the second address is a (mem (plus (reg) (const_int)))
8827 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
8828 register as addr1. */
8829 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
8831 if (GET_CODE (addr2) != PLUS)
8834 if (GET_CODE (XEXP (addr2, 0)) != REG
8835 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
8838 if (reg1 != REGNO (XEXP (addr2, 0)))
8841 /* The offset for the second addr must be 8 more than the first addr. */
8842 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
8845 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
8850 /* Return the register class of a scratch register needed to copy IN into
8851 or out of a register in CLASS in MODE. If it can be done directly,
8852 NO_REGS is returned. */
8855 secondary_reload_class (enum reg_class class,
8856 enum machine_mode mode ATTRIBUTE_UNUSED,
8861 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
8863 && MACHOPIC_INDIRECT
8867 /* We cannot copy a symbolic operand directly into anything
8868 other than BASE_REGS for TARGET_ELF. So indicate that a
8869 register from BASE_REGS is needed as an intermediate
8872 On Darwin, pic addresses require a load from memory, which
8873 needs a base register. */
8874 if (class != BASE_REGS
8875 && (GET_CODE (in) == SYMBOL_REF
8876 || GET_CODE (in) == HIGH
8877 || GET_CODE (in) == LABEL_REF
8878 || GET_CODE (in) == CONST))
8882 if (GET_CODE (in) == REG)
8885 if (regno >= FIRST_PSEUDO_REGISTER)
8887 regno = true_regnum (in);
8888 if (regno >= FIRST_PSEUDO_REGISTER)
8892 else if (GET_CODE (in) == SUBREG)
8894 regno = true_regnum (in);
8895 if (regno >= FIRST_PSEUDO_REGISTER)
8901 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
8903 if (class == GENERAL_REGS || class == BASE_REGS
8904 || (regno >= 0 && INT_REGNO_P (regno)))
8907 /* Constants, memory, and FP registers can go into FP registers. */
8908 if ((regno == -1 || FP_REGNO_P (regno))
8909 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
8912 /* Memory, and AltiVec registers can go into AltiVec registers. */
8913 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
8914 && class == ALTIVEC_REGS)
8917 /* We can copy among the CR registers. */
8918 if ((class == CR_REGS || class == CR0_REGS)
8919 && regno >= 0 && CR_REGNO_P (regno))
8922 /* Otherwise, we need GENERAL_REGS. */
8923 return GENERAL_REGS;
8926 /* Given a comparison operation, return the bit number in CCR to test. We
8927 know this is a valid comparison.
8929 SCC_P is 1 if this is for an scc. That means that %D will have been
8930 used instead of %C, so the bits will be in different places.
8932 Return -1 if OP isn't a valid comparison for some reason. */
8935 ccr_bit (rtx op, int scc_p)
8937 enum rtx_code code = GET_CODE (op);
8938 enum machine_mode cc_mode;
8943 if (!COMPARISON_P (op))
8948 if (GET_CODE (reg) != REG
8949 || ! CR_REGNO_P (REGNO (reg)))
8952 cc_mode = GET_MODE (reg);
8953 cc_regnum = REGNO (reg);
8954 base_bit = 4 * (cc_regnum - CR0_REGNO);
8956 validate_condition_mode (code, cc_mode);
8958 /* When generating a sCOND operation, only positive conditions are
8960 if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
8961 && code != GTU && code != LTU)
8967 return scc_p ? base_bit + 3 : base_bit + 2;
8969 return base_bit + 2;
8970 case GT: case GTU: case UNLE:
8971 return base_bit + 1;
8972 case LT: case LTU: case UNGE:
8974 case ORDERED: case UNORDERED:
8975 return base_bit + 3;
8978 /* If scc, we will have done a cror to put the bit in the
8979 unordered position. So test that bit. For integer, this is ! LT
8980 unless this is an scc insn. */
8981 return scc_p ? base_bit + 3 : base_bit;
8984 return scc_p ? base_bit + 3 : base_bit + 1;
8991 /* Return the GOT register. */
8994 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
8996 /* The second flow pass currently (June 1999) can't update
8997 regs_ever_live without disturbing other parts of the compiler, so
8998 update it here to make the prolog/epilogue code happy. */
8999 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
9000 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9002 current_function_uses_pic_offset_table = 1;
9004 return pic_offset_table_rtx;
9007 /* Function to init struct machine_function.
9008 This will be called, via a pointer variable,
9009 from push_function_context. */
9011 static struct machine_function *
9012 rs6000_init_machine_status (void)
9014 return ggc_alloc_cleared (sizeof (machine_function));
9017 /* These macros test for integers and extract the low-order bits. */
9019 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9020 && GET_MODE (X) == VOIDmode)
9022 #define INT_LOWPART(X) \
9023 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9029 unsigned long val = INT_LOWPART (op);
9031 /* If the high bit is zero, the value is the first 1 bit we find
9033 if ((val & 0x80000000) == 0)
9035 if ((val & 0xffffffff) == 0)
9039 while (((val <<= 1) & 0x80000000) == 0)
9044 /* If the high bit is set and the low bit is not, or the mask is all
9045 1's, the value is zero. */
9046 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
9049 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9052 while (((val >>= 1) & 1) != 0)
9062 unsigned long val = INT_LOWPART (op);
9064 /* If the low bit is zero, the value is the first 1 bit we find from
9068 if ((val & 0xffffffff) == 0)
9072 while (((val >>= 1) & 1) == 0)
9078 /* If the low bit is set and the high bit is not, or the mask is all
9079 1's, the value is 31. */
9080 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
9083 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9086 while (((val <<= 1) & 0x80000000) != 0)
9092 /* Locate some local-dynamic symbol still in use by this function
9093 so that we can print its name in some tls_ld pattern. */
9096 rs6000_get_some_local_dynamic_name (void)
9100 if (cfun->machine->some_ld_name)
9101 return cfun->machine->some_ld_name;
9103 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9105 && for_each_rtx (&PATTERN (insn),
9106 rs6000_get_some_local_dynamic_name_1, 0))
9107 return cfun->machine->some_ld_name;
9112 /* Helper function for rs6000_get_some_local_dynamic_name. */
9115 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9119 if (GET_CODE (x) == SYMBOL_REF)
9121 const char *str = XSTR (x, 0);
9122 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9124 cfun->machine->some_ld_name = str;
9132 /* Write out a function code label. */
9135 rs6000_output_function_entry (FILE *file, const char *fname)
9137 if (fname[0] != '.')
9139 switch (DEFAULT_ABI)
9148 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
9157 RS6000_OUTPUT_BASENAME (file, fname);
9159 assemble_name (file, fname);
9162 /* Print an operand. Recognize special options, documented below. */
9165 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
9166 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
9168 #define SMALL_DATA_RELOC "sda21"
9169 #define SMALL_DATA_REG 0
9173 print_operand (FILE *file, rtx x, int code)
9177 unsigned HOST_WIDE_INT uval;
9182 /* Write out an instruction after the call which may be replaced
9183 with glue code by the loader. This depends on the AIX version. */
9184 asm_fprintf (file, RS6000_CALL_GLUE);
9187 /* %a is output_address. */
9190 /* If X is a constant integer whose low-order 5 bits are zero,
9191 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
9192 in the AIX assembler where "sri" with a zero shift count
9193 writes a trash instruction. */
9194 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
9201 /* If constant, low-order 16 bits of constant, unsigned.
9202 Otherwise, write normally. */
9204 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
9206 print_operand (file, x, 0);
9210 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
9211 for 64-bit mask direction. */
9212 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
9215 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
9219 /* X is a CR register. Print the number of the GT bit of the CR. */
9220 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9221 output_operand_lossage ("invalid %%E value");
9223 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
9227 /* Like 'J' but get to the EQ bit. */
9228 if (GET_CODE (x) != REG)
9231 /* Bit 1 is EQ bit. */
9232 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
9234 fprintf (file, "%d", i);
9238 /* X is a CR register. Print the number of the EQ bit of the CR */
9239 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9240 output_operand_lossage ("invalid %%E value");
9242 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
9246 /* X is a CR register. Print the shift count needed to move it
9247 to the high-order four bits. */
9248 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9249 output_operand_lossage ("invalid %%f value");
9251 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
9255 /* Similar, but print the count for the rotate in the opposite
9257 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9258 output_operand_lossage ("invalid %%F value");
9260 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
9264 /* X is a constant integer. If it is negative, print "m",
9265 otherwise print "z". This is to make an aze or ame insn. */
9266 if (GET_CODE (x) != CONST_INT)
9267 output_operand_lossage ("invalid %%G value");
9268 else if (INTVAL (x) >= 0)
9275 /* If constant, output low-order five bits. Otherwise, write
9278 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
9280 print_operand (file, x, 0);
9284 /* If constant, output low-order six bits. Otherwise, write
9287 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
9289 print_operand (file, x, 0);
9293 /* Print `i' if this is a constant, else nothing. */
9299 /* Write the bit number in CCR for jump. */
9302 output_operand_lossage ("invalid %%j code");
9304 fprintf (file, "%d", i);
9308 /* Similar, but add one for shift count in rlinm for scc and pass
9309 scc flag to `ccr_bit'. */
9312 output_operand_lossage ("invalid %%J code");
9314 /* If we want bit 31, write a shift count of zero, not 32. */
9315 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9319 /* X must be a constant. Write the 1's complement of the
9322 output_operand_lossage ("invalid %%k value");
9324 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
9328 /* X must be a symbolic constant on ELF. Write an
9329 expression suitable for an 'addi' that adds in the low 16
9331 if (GET_CODE (x) != CONST)
9333 print_operand_address (file, x);
9338 if (GET_CODE (XEXP (x, 0)) != PLUS
9339 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
9340 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
9341 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
9342 output_operand_lossage ("invalid %%K value");
9343 print_operand_address (file, XEXP (XEXP (x, 0), 0));
9345 /* For GNU as, there must be a non-alphanumeric character
9346 between 'l' and the number. The '-' is added by
9347 print_operand() already. */
9348 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
9350 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
9354 /* %l is output_asm_label. */
9357 /* Write second word of DImode or DFmode reference. Works on register
9358 or non-indexed memory only. */
9359 if (GET_CODE (x) == REG)
9360 fputs (reg_names[REGNO (x) + 1], file);
9361 else if (GET_CODE (x) == MEM)
9363 /* Handle possible auto-increment. Since it is pre-increment and
9364 we have already done it, we can just use an offset of word. */
9365 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9366 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9367 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
9370 output_address (XEXP (adjust_address_nv (x, SImode,
9374 if (small_data_operand (x, GET_MODE (x)))
9375 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9376 reg_names[SMALL_DATA_REG]);
9381 /* MB value for a mask operand. */
9382 if (! mask_operand (x, SImode))
9383 output_operand_lossage ("invalid %%m value");
9385 fprintf (file, "%d", extract_MB (x));
9389 /* ME value for a mask operand. */
9390 if (! mask_operand (x, SImode))
9391 output_operand_lossage ("invalid %%M value");
9393 fprintf (file, "%d", extract_ME (x));
9396 /* %n outputs the negative of its operand. */
9399 /* Write the number of elements in the vector times 4. */
9400 if (GET_CODE (x) != PARALLEL)
9401 output_operand_lossage ("invalid %%N value");
9403 fprintf (file, "%d", XVECLEN (x, 0) * 4);
9407 /* Similar, but subtract 1 first. */
9408 if (GET_CODE (x) != PARALLEL)
9409 output_operand_lossage ("invalid %%O value");
9411 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
9415 /* X is a CONST_INT that is a power of two. Output the logarithm. */
9417 || INT_LOWPART (x) < 0
9418 || (i = exact_log2 (INT_LOWPART (x))) < 0)
9419 output_operand_lossage ("invalid %%p value");
9421 fprintf (file, "%d", i);
9425 /* The operand must be an indirect memory reference. The result
9426 is the register name. */
9427 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
9428 || REGNO (XEXP (x, 0)) >= 32)
9429 output_operand_lossage ("invalid %%P value");
9431 fputs (reg_names[REGNO (XEXP (x, 0))], file);
9435 /* This outputs the logical code corresponding to a boolean
9436 expression. The expression may have one or both operands
9437 negated (if one, only the first one). For condition register
9438 logical operations, it will also treat the negated
9439 CR codes as NOTs, but not handle NOTs of them. */
9441 const char *const *t = 0;
9443 enum rtx_code code = GET_CODE (x);
9444 static const char * const tbl[3][3] = {
9445 { "and", "andc", "nor" },
9446 { "or", "orc", "nand" },
9447 { "xor", "eqv", "xor" } };
9451 else if (code == IOR)
9453 else if (code == XOR)
9456 output_operand_lossage ("invalid %%q value");
9458 if (GET_CODE (XEXP (x, 0)) != NOT)
9462 if (GET_CODE (XEXP (x, 1)) == NOT)
9480 /* X is a CR register. Print the mask for `mtcrf'. */
9481 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9482 output_operand_lossage ("invalid %%R value");
9484 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
9488 /* Low 5 bits of 32 - value */
9490 output_operand_lossage ("invalid %%s value");
9492 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
9496 /* PowerPC64 mask position. All 0's is excluded.
9497 CONST_INT 32-bit mask is considered sign-extended so any
9498 transition must occur within the CONST_INT, not on the boundary. */
9499 if (! mask64_operand (x, DImode))
9500 output_operand_lossage ("invalid %%S value");
9502 uval = INT_LOWPART (x);
9504 if (uval & 1) /* Clear Left */
9506 #if HOST_BITS_PER_WIDE_INT > 64
9507 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9511 else /* Clear Right */
9514 #if HOST_BITS_PER_WIDE_INT > 64
9515 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9523 fprintf (file, "%d", i);
9527 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
9528 if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
9531 /* Bit 3 is OV bit. */
9532 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
9534 /* If we want bit 31, write a shift count of zero, not 32. */
9535 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9539 /* Print the symbolic name of a branch target register. */
9540 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
9541 && REGNO (x) != COUNT_REGISTER_REGNUM))
9542 output_operand_lossage ("invalid %%T value");
9543 else if (REGNO (x) == LINK_REGISTER_REGNUM)
9544 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
9546 fputs ("ctr", file);
9550 /* High-order 16 bits of constant for use in unsigned operand. */
9552 output_operand_lossage ("invalid %%u value");
9554 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9555 (INT_LOWPART (x) >> 16) & 0xffff);
9559 /* High-order 16 bits of constant for use in signed operand. */
9561 output_operand_lossage ("invalid %%v value");
9563 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9564 (INT_LOWPART (x) >> 16) & 0xffff);
9568 /* Print `u' if this has an auto-increment or auto-decrement. */
9569 if (GET_CODE (x) == MEM
9570 && (GET_CODE (XEXP (x, 0)) == PRE_INC
9571 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
9576 /* Print the trap code for this operand. */
9577 switch (GET_CODE (x))
9580 fputs ("eq", file); /* 4 */
9583 fputs ("ne", file); /* 24 */
9586 fputs ("lt", file); /* 16 */
9589 fputs ("le", file); /* 20 */
9592 fputs ("gt", file); /* 8 */
9595 fputs ("ge", file); /* 12 */
9598 fputs ("llt", file); /* 2 */
9601 fputs ("lle", file); /* 6 */
9604 fputs ("lgt", file); /* 1 */
9607 fputs ("lge", file); /* 5 */
9615 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
9618 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
9619 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
9621 print_operand (file, x, 0);
9625 /* MB value for a PowerPC64 rldic operand. */
9626 val = (GET_CODE (x) == CONST_INT
9627 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
9632 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
9633 if ((val <<= 1) < 0)
9636 #if HOST_BITS_PER_WIDE_INT == 32
9637 if (GET_CODE (x) == CONST_INT && i >= 0)
9638 i += 32; /* zero-extend high-part was all 0's */
9639 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
9641 val = CONST_DOUBLE_LOW (x);
9648 for ( ; i < 64; i++)
9649 if ((val <<= 1) < 0)
9654 fprintf (file, "%d", i + 1);
9658 if (GET_CODE (x) == MEM
9659 && legitimate_indexed_address_p (XEXP (x, 0), 0))
9664 /* Like 'L', for third word of TImode */
9665 if (GET_CODE (x) == REG)
9666 fputs (reg_names[REGNO (x) + 2], file);
9667 else if (GET_CODE (x) == MEM)
9669 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9670 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9671 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9673 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
9674 if (small_data_operand (x, GET_MODE (x)))
9675 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9676 reg_names[SMALL_DATA_REG]);
9681 /* X is a SYMBOL_REF. Write out the name preceded by a
9682 period and without any trailing data in brackets. Used for function
9683 names. If we are configured for System V (or the embedded ABI) on
9684 the PowerPC, do not emit the period, since those systems do not use
9685 TOCs and the like. */
9686 if (GET_CODE (x) != SYMBOL_REF)
9689 /* Mark the decl as referenced so that cgraph will output the
9691 if (SYMBOL_REF_DECL (x))
9692 mark_decl_referenced (SYMBOL_REF_DECL (x));
9694 /* For macho, check to see if we need a stub. */
9697 const char *name = XSTR (x, 0);
9699 if (MACHOPIC_INDIRECT
9700 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
9701 name = machopic_indirection_name (x, /*stub_p=*/true);
9703 assemble_name (file, name);
9705 else if (!DOT_SYMBOLS)
9706 assemble_name (file, XSTR (x, 0));
9708 rs6000_output_function_entry (file, XSTR (x, 0));
9712 /* Like 'L', for last word of TImode. */
9713 if (GET_CODE (x) == REG)
9714 fputs (reg_names[REGNO (x) + 3], file);
9715 else if (GET_CODE (x) == MEM)
9717 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9718 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9719 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9721 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
9722 if (small_data_operand (x, GET_MODE (x)))
9723 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9724 reg_names[SMALL_DATA_REG]);
9728 /* Print AltiVec or SPE memory operand. */
9733 if (GET_CODE (x) != MEM)
9741 if (GET_CODE (tmp) == REG)
9743 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
9746 /* Handle [reg+UIMM]. */
9747 else if (GET_CODE (tmp) == PLUS &&
9748 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
9752 if (GET_CODE (XEXP (tmp, 0)) != REG)
9755 x = INTVAL (XEXP (tmp, 1));
9756 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
9760 /* Fall through. Must be [reg+reg]. */
9763 && GET_CODE (tmp) == AND
9764 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
9765 && INTVAL (XEXP (tmp, 1)) == -16)
9766 tmp = XEXP (tmp, 0);
9767 if (GET_CODE (tmp) == REG)
9768 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
9769 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
9771 if (REGNO (XEXP (tmp, 0)) == 0)
9772 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
9773 reg_names[ REGNO (XEXP (tmp, 0)) ]);
9775 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
9776 reg_names[ REGNO (XEXP (tmp, 1)) ]);
9784 if (GET_CODE (x) == REG)
9785 fprintf (file, "%s", reg_names[REGNO (x)]);
9786 else if (GET_CODE (x) == MEM)
9788 /* We need to handle PRE_INC and PRE_DEC here, since we need to
9789 know the width from the mode. */
9790 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
9791 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
9792 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9793 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
9794 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
9795 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9797 output_address (XEXP (x, 0));
9800 output_addr_const (file, x);
9804 assemble_name (file, rs6000_get_some_local_dynamic_name ());
9808 output_operand_lossage ("invalid %%xn code");
9812 /* Print the address of an operand. */
9815 print_operand_address (FILE *file, rtx x)
9817 if (GET_CODE (x) == REG)
9818 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9819 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
9820 || GET_CODE (x) == LABEL_REF)
9822 output_addr_const (file, x);
9823 if (small_data_operand (x, GET_MODE (x)))
9824 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9825 reg_names[SMALL_DATA_REG]);
9826 else if (TARGET_TOC)
9829 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
9831 if (REGNO (XEXP (x, 0)) == 0)
9832 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
9833 reg_names[ REGNO (XEXP (x, 0)) ]);
9835 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
9836 reg_names[ REGNO (XEXP (x, 1)) ]);
9838 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
9839 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
9840 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
9842 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9843 && CONSTANT_P (XEXP (x, 1)))
9845 output_addr_const (file, XEXP (x, 1));
9846 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9850 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9851 && CONSTANT_P (XEXP (x, 1)))
9853 fprintf (file, "lo16(");
9854 output_addr_const (file, XEXP (x, 1));
9855 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9858 else if (legitimate_constant_pool_address_p (x))
9860 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
9862 rtx contains_minus = XEXP (x, 1);
9866 /* Find the (minus (sym) (toc)) buried in X, and temporarily
9867 turn it into (sym) for output_addr_const. */
9868 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
9869 contains_minus = XEXP (contains_minus, 0);
9871 minus = XEXP (contains_minus, 0);
9872 symref = XEXP (minus, 0);
9873 XEXP (contains_minus, 0) = symref;
9878 name = XSTR (symref, 0);
9879 newname = alloca (strlen (name) + sizeof ("@toc"));
9880 strcpy (newname, name);
9881 strcat (newname, "@toc");
9882 XSTR (symref, 0) = newname;
9884 output_addr_const (file, XEXP (x, 1));
9886 XSTR (symref, 0) = name;
9887 XEXP (contains_minus, 0) = minus;
9890 output_addr_const (file, XEXP (x, 1));
9892 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
9898 /* Target hook for assembling integer objects. The PowerPC version has
9899 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
9900 is defined. It also needs to handle DI-mode objects on 64-bit
9904 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
9906 #ifdef RELOCATABLE_NEEDS_FIXUP
9907 /* Special handling for SI values. */
9908 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
9910 extern int in_toc_section (void);
9911 static int recurse = 0;
9913 /* For -mrelocatable, we mark all addresses that need to be fixed up
9914 in the .fixup section. */
9915 if (TARGET_RELOCATABLE
9916 && !in_toc_section ()
9917 && !in_text_section ()
9918 && !in_unlikely_text_section ()
9920 && GET_CODE (x) != CONST_INT
9921 && GET_CODE (x) != CONST_DOUBLE
9927 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
9929 ASM_OUTPUT_LABEL (asm_out_file, buf);
9930 fprintf (asm_out_file, "\t.long\t(");
9931 output_addr_const (asm_out_file, x);
9932 fprintf (asm_out_file, ")@fixup\n");
9933 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
9934 ASM_OUTPUT_ALIGN (asm_out_file, 2);
9935 fprintf (asm_out_file, "\t.long\t");
9936 assemble_name (asm_out_file, buf);
9937 fprintf (asm_out_file, "\n\t.previous\n");
9941 /* Remove initial .'s to turn a -mcall-aixdesc function
9942 address into the address of the descriptor, not the function
9944 else if (GET_CODE (x) == SYMBOL_REF
9945 && XSTR (x, 0)[0] == '.'
9946 && DEFAULT_ABI == ABI_AIX)
9948 const char *name = XSTR (x, 0);
9949 while (*name == '.')
9952 fprintf (asm_out_file, "\t.long\t%s\n", name);
9956 #endif /* RELOCATABLE_NEEDS_FIXUP */
9957 return default_assemble_integer (x, size, aligned_p);
9960 #ifdef HAVE_GAS_HIDDEN
9961 /* Emit an assembler directive to set symbol visibility for DECL to
9965 rs6000_assemble_visibility (tree decl, int vis)
9967 /* Functions need to have their entry point symbol visibility set as
9968 well as their descriptor symbol visibility. */
9969 if (DEFAULT_ABI == ABI_AIX
9971 && TREE_CODE (decl) == FUNCTION_DECL)
9973 static const char * const visibility_types[] = {
9974 NULL, "internal", "hidden", "protected"
9977 const char *name, *type;
9979 name = ((* targetm.strip_name_encoding)
9980 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
9981 type = visibility_types[vis];
9983 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
9984 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
9987 default_assemble_visibility (decl, vis);
9992 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
9994 /* Reversal of FP compares takes care -- an ordered compare
9995 becomes an unordered compare and vice versa. */
9996 if (mode == CCFPmode
9997 && (!flag_finite_math_only
9998 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
9999 || code == UNEQ || code == LTGT))
10000 return reverse_condition_maybe_unordered (code);
10002 return reverse_condition (code);
10005 /* Generate a compare for CODE. Return a brand-new rtx that
10006 represents the result of the compare. */
10009 rs6000_generate_compare (enum rtx_code code)
10011 enum machine_mode comp_mode;
10012 rtx compare_result;
10014 if (rs6000_compare_fp_p)
10015 comp_mode = CCFPmode;
10016 else if (code == GTU || code == LTU
10017 || code == GEU || code == LEU)
10018 comp_mode = CCUNSmode;
10019 else if ((code == EQ || code == NE)
10020 && GET_CODE (rs6000_compare_op0) == SUBREG
10021 && GET_CODE (rs6000_compare_op1) == SUBREG
10022 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
10023 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
10024 /* These are unsigned values, perhaps there will be a later
10025 ordering compare that can be shared with this one.
10026 Unfortunately we cannot detect the signedness of the operands
10027 for non-subregs. */
10028 comp_mode = CCUNSmode;
10030 comp_mode = CCmode;
10032 /* First, the compare. */
10033 compare_result = gen_reg_rtx (comp_mode);
10035 /* SPE FP compare instructions on the GPRs. Yuck! */
10036 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10037 && rs6000_compare_fp_p)
10039 rtx cmp, or_result, compare_result2;
10040 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
10042 if (op_mode == VOIDmode)
10043 op_mode = GET_MODE (rs6000_compare_op1);
10045 /* Note: The E500 comparison instructions set the GT bit (x +
10046 1), on success. This explains the mess. */
10050 case EQ: case UNEQ: case NE: case LTGT:
10051 if (op_mode == SFmode)
10052 cmp = flag_unsafe_math_optimizations
10053 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
10054 rs6000_compare_op1)
10055 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
10056 rs6000_compare_op1);
10057 else if (op_mode == DFmode)
10058 cmp = flag_unsafe_math_optimizations
10059 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
10060 rs6000_compare_op1)
10061 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
10062 rs6000_compare_op1);
10065 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
10066 if (op_mode == SFmode)
10067 cmp = flag_unsafe_math_optimizations
10068 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
10069 rs6000_compare_op1)
10070 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
10071 rs6000_compare_op1);
10072 else if (op_mode == DFmode)
10073 cmp = flag_unsafe_math_optimizations
10074 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
10075 rs6000_compare_op1)
10076 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
10077 rs6000_compare_op1);
10080 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
10081 if (op_mode == SFmode)
10082 cmp = flag_unsafe_math_optimizations
10083 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
10084 rs6000_compare_op1)
10085 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
10086 rs6000_compare_op1);
10087 else if (op_mode == DFmode)
10088 cmp = flag_unsafe_math_optimizations
10089 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
10090 rs6000_compare_op1)
10091 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
10092 rs6000_compare_op1);
10099 /* Synthesize LE and GE from LT/GT || EQ. */
10100 if (code == LE || code == GE || code == LEU || code == GEU)
10106 case LE: code = LT; break;
10107 case GE: code = GT; break;
10108 case LEU: code = LT; break;
10109 case GEU: code = GT; break;
10113 compare_result2 = gen_reg_rtx (CCFPmode);
10116 if (op_mode == SFmode)
10117 cmp = flag_unsafe_math_optimizations
10118 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
10119 rs6000_compare_op1)
10120 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
10121 rs6000_compare_op1);
10122 else if (op_mode == DFmode)
10123 cmp = flag_unsafe_math_optimizations
10124 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
10125 rs6000_compare_op1)
10126 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
10127 rs6000_compare_op1);
10131 /* OR them together. */
10132 or_result = gen_reg_rtx (CCFPmode);
10133 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
10135 compare_result = or_result;
10140 if (code == NE || code == LTGT)
10150 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
10151 CLOBBERs to match cmptf_internal2 pattern. */
10152 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
10153 && GET_MODE (rs6000_compare_op0) == TFmode
10154 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10155 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
10156 emit_insn (gen_rtx_PARALLEL (VOIDmode,
10158 gen_rtx_SET (VOIDmode,
10160 gen_rtx_COMPARE (comp_mode,
10161 rs6000_compare_op0,
10162 rs6000_compare_op1)),
10163 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10164 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10165 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10166 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10167 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10168 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10169 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10170 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
10172 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
10173 gen_rtx_COMPARE (comp_mode,
10174 rs6000_compare_op0,
10175 rs6000_compare_op1)));
10178 /* Some kinds of FP comparisons need an OR operation;
10179 under flag_finite_math_only we don't bother. */
10180 if (rs6000_compare_fp_p
10181 && !flag_finite_math_only
10182 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
10183 && (code == LE || code == GE
10184 || code == UNEQ || code == LTGT
10185 || code == UNGT || code == UNLT))
10187 enum rtx_code or1, or2;
10188 rtx or1_rtx, or2_rtx, compare2_rtx;
10189 rtx or_result = gen_reg_rtx (CCEQmode);
10193 case LE: or1 = LT; or2 = EQ; break;
10194 case GE: or1 = GT; or2 = EQ; break;
10195 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
10196 case LTGT: or1 = LT; or2 = GT; break;
10197 case UNGT: or1 = UNORDERED; or2 = GT; break;
10198 case UNLT: or1 = UNORDERED; or2 = LT; break;
10201 validate_condition_mode (or1, comp_mode);
10202 validate_condition_mode (or2, comp_mode);
10203 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
10204 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
10205 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
10206 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
10208 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
10210 compare_result = or_result;
10214 validate_condition_mode (code, GET_MODE (compare_result));
10216 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
10220 /* Emit the RTL for an sCOND pattern. */
10223 rs6000_emit_sCOND (enum rtx_code code, rtx result)
10226 enum machine_mode op_mode;
10227 enum rtx_code cond_code;
10229 condition_rtx = rs6000_generate_compare (code);
10230 cond_code = GET_CODE (condition_rtx);
10232 if (TARGET_E500 && rs6000_compare_fp_p
10233 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10237 PUT_MODE (condition_rtx, SImode);
10238 t = XEXP (condition_rtx, 0);
10240 if (cond_code != NE && cond_code != EQ)
10243 if (cond_code == NE)
10244 emit_insn (gen_e500_flip_gt_bit (t, t));
10246 emit_insn (gen_move_from_CR_gt_bit (result, t));
10250 if (cond_code == NE
10251 || cond_code == GE || cond_code == LE
10252 || cond_code == GEU || cond_code == LEU
10253 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
10255 rtx not_result = gen_reg_rtx (CCEQmode);
10256 rtx not_op, rev_cond_rtx;
10257 enum machine_mode cc_mode;
10259 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
10261 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
10262 SImode, XEXP (condition_rtx, 0), const0_rtx);
10263 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
10264 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
10265 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
10268 op_mode = GET_MODE (rs6000_compare_op0);
10269 if (op_mode == VOIDmode)
10270 op_mode = GET_MODE (rs6000_compare_op1);
10272 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
10274 PUT_MODE (condition_rtx, DImode);
10275 convert_move (result, condition_rtx, 0);
10279 PUT_MODE (condition_rtx, SImode);
10280 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
10284 /* Emit a branch of kind CODE to location LOC. */
10287 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
10289 rtx condition_rtx, loc_ref;
10291 condition_rtx = rs6000_generate_compare (code);
10292 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
10293 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10294 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
10295 loc_ref, pc_rtx)));
10298 /* Return the string to output a conditional branch to LABEL, which is
10299 the operand number of the label, or -1 if the branch is really a
10300 conditional return.
10302 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
10303 condition code register and its mode specifies what kind of
10304 comparison we made.
10306 REVERSED is nonzero if we should reverse the sense of the comparison.
10308 INSN is the insn. */
10311 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
10313 static char string[64];
10314 enum rtx_code code = GET_CODE (op);
10315 rtx cc_reg = XEXP (op, 0);
10316 enum machine_mode mode = GET_MODE (cc_reg);
10317 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
10318 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
10319 int really_reversed = reversed ^ need_longbranch;
10325 validate_condition_mode (code, mode);
10327 /* Work out which way this really branches. We could use
10328 reverse_condition_maybe_unordered here always but this
10329 makes the resulting assembler clearer. */
10330 if (really_reversed)
10332 /* Reversal of FP compares takes care -- an ordered compare
10333 becomes an unordered compare and vice versa. */
10334 if (mode == CCFPmode)
10335 code = reverse_condition_maybe_unordered (code);
10337 code = reverse_condition (code);
10340 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
10342 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
10345 /* Opposite of GT. */
10347 else if (code == NE)
10355 /* Not all of these are actually distinct opcodes, but
10356 we distinguish them for clarity of the resulting assembler. */
10357 case NE: case LTGT:
10358 ccode = "ne"; break;
10359 case EQ: case UNEQ:
10360 ccode = "eq"; break;
10362 ccode = "ge"; break;
10363 case GT: case GTU: case UNGT:
10364 ccode = "gt"; break;
10366 ccode = "le"; break;
10367 case LT: case LTU: case UNLT:
10368 ccode = "lt"; break;
10369 case UNORDERED: ccode = "un"; break;
10370 case ORDERED: ccode = "nu"; break;
10371 case UNGE: ccode = "nl"; break;
10372 case UNLE: ccode = "ng"; break;
10377 /* Maybe we have a guess as to how likely the branch is.
10378 The old mnemonics don't have a way to specify this information. */
10380 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
10381 if (note != NULL_RTX)
10383 /* PROB is the difference from 50%. */
10384 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
10386 /* Only hint for highly probable/improbable branches on newer
10387 cpus as static prediction overrides processor dynamic
10388 prediction. For older cpus we may as well always hint, but
10389 assume not taken for branches that are very close to 50% as a
10390 mispredicted taken branch is more expensive than a
10391 mispredicted not-taken branch. */
10392 if (rs6000_always_hint
10393 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
10395 if (abs (prob) > REG_BR_PROB_BASE / 20
10396 && ((prob > 0) ^ need_longbranch))
10404 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
10406 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
10408 /* We need to escape any '%' characters in the reg_names string.
10409 Assume they'd only be the first character.... */
10410 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
10412 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
10416 /* If the branch distance was too far, we may have to use an
10417 unconditional branch to go the distance. */
10418 if (need_longbranch)
10419 s += sprintf (s, ",$+8\n\tb %s", label);
10421 s += sprintf (s, ",%s", label);
10427 /* Return the string to flip the GT bit on a CR. */
10429 output_e500_flip_gt_bit (rtx dst, rtx src)
10431 static char string[64];
10434 if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst))
10435 || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src)))
10439 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
10440 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
10442 sprintf (string, "crnot %d,%d", a, b);
10446 /* Return insn index for the vector compare instruction for given CODE,
10447 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
10451 get_vec_cmp_insn (enum rtx_code code,
10452 enum machine_mode dest_mode,
10453 enum machine_mode op_mode)
10455 if (!TARGET_ALTIVEC)
10456 return INSN_NOT_AVAILABLE;
10461 if (dest_mode == V16QImode && op_mode == V16QImode)
10462 return UNSPEC_VCMPEQUB;
10463 if (dest_mode == V8HImode && op_mode == V8HImode)
10464 return UNSPEC_VCMPEQUH;
10465 if (dest_mode == V4SImode && op_mode == V4SImode)
10466 return UNSPEC_VCMPEQUW;
10467 if (dest_mode == V4SImode && op_mode == V4SFmode)
10468 return UNSPEC_VCMPEQFP;
10471 if (dest_mode == V4SImode && op_mode == V4SFmode)
10472 return UNSPEC_VCMPGEFP;
10474 if (dest_mode == V16QImode && op_mode == V16QImode)
10475 return UNSPEC_VCMPGTSB;
10476 if (dest_mode == V8HImode && op_mode == V8HImode)
10477 return UNSPEC_VCMPGTSH;
10478 if (dest_mode == V4SImode && op_mode == V4SImode)
10479 return UNSPEC_VCMPGTSW;
10480 if (dest_mode == V4SImode && op_mode == V4SFmode)
10481 return UNSPEC_VCMPGTFP;
10484 if (dest_mode == V16QImode && op_mode == V16QImode)
10485 return UNSPEC_VCMPGTUB;
10486 if (dest_mode == V8HImode && op_mode == V8HImode)
10487 return UNSPEC_VCMPGTUH;
10488 if (dest_mode == V4SImode && op_mode == V4SImode)
10489 return UNSPEC_VCMPGTUW;
10494 return INSN_NOT_AVAILABLE;
10497 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
10498 DMODE is expected destination mode. This is a recursive function. */
10501 rs6000_emit_vector_compare (enum rtx_code rcode,
10503 enum machine_mode dmode)
10507 enum machine_mode dest_mode;
10508 enum machine_mode op_mode = GET_MODE (op1);
10510 #ifdef ENABLE_CHECKING
10511 if (!TARGET_ALTIVEC)
10514 if (GET_MODE (op0) != GET_MODE (op1))
10518 /* Floating point vector compare instructions uses destination V4SImode.
10519 Move destination to appropriate mode later. */
10520 if (dmode == V4SFmode)
10521 dest_mode = V4SImode;
10525 mask = gen_reg_rtx (dest_mode);
10526 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
10528 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
10530 bool swap_operands = false;
10531 bool try_again = false;
10536 swap_operands = true;
10541 swap_operands = true;
10545 /* Treat A != B as ~(A==B). */
10547 enum insn_code nor_code;
10548 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
10551 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
10552 if (nor_code == CODE_FOR_nothing)
10554 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
10556 if (dmode != dest_mode)
10558 rtx temp = gen_reg_rtx (dest_mode);
10559 convert_move (temp, mask, 0);
10569 /* Try GT/GTU/LT/LTU OR EQ */
10572 enum insn_code ior_code;
10573 enum rtx_code new_code;
10577 else if (rcode == GEU)
10579 else if (rcode == LE)
10581 else if (rcode == LEU)
10586 c_rtx = rs6000_emit_vector_compare (new_code,
10587 op0, op1, dest_mode);
10588 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
10591 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
10592 if (ior_code == CODE_FOR_nothing)
10594 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
10595 if (dmode != dest_mode)
10597 rtx temp = gen_reg_rtx (dest_mode);
10598 convert_move (temp, mask, 0);
10610 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
10611 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
10612 /* You only get two chances. */
10625 emit_insn (gen_rtx_fmt_ee (SET,
10628 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
10629 gen_rtvec (2, op0, op1),
10631 if (dmode != dest_mode)
10633 rtx temp = gen_reg_rtx (dest_mode);
10634 convert_move (temp, mask, 0);
10640 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
10641 valid insn doesn exist for given mode. */
10644 get_vsel_insn (enum machine_mode mode)
10649 return UNSPEC_VSEL4SI;
10652 return UNSPEC_VSEL4SF;
10655 return UNSPEC_VSEL8HI;
10658 return UNSPEC_VSEL16QI;
10661 return INSN_NOT_AVAILABLE;
10664 return INSN_NOT_AVAILABLE;
10667 /* Emit vector select insn where DEST is destination using
10668 operands OP1, OP2 and MASK. */
10671 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
10674 enum machine_mode dest_mode = GET_MODE (dest);
10675 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
10677 temp = gen_reg_rtx (dest_mode);
10679 /* For each vector element, select op1 when mask is 1 otherwise
10681 t = gen_rtx_fmt_ee (SET, VOIDmode, temp,
10682 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
10683 gen_rtvec (3, op2, op1, mask),
10686 emit_move_insn (dest, temp);
10690 /* Emit vector conditional expression.
10691 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
10692 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
10695 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
10696 rtx cond, rtx cc_op0, rtx cc_op1)
10698 enum machine_mode dest_mode = GET_MODE (dest);
10699 enum rtx_code rcode = GET_CODE (cond);
10702 if (!TARGET_ALTIVEC)
10705 /* Get the vector mask for the given relational operations. */
10706 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
10708 rs6000_emit_vector_select (dest, op1, op2, mask);
10713 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
10714 operands of the last comparison is nonzero/true, FALSE_COND if it
10715 is zero/false. Return 0 if the hardware has no such operation. */
10718 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
10720 enum rtx_code code = GET_CODE (op);
10721 rtx op0 = rs6000_compare_op0;
10722 rtx op1 = rs6000_compare_op1;
10723 REAL_VALUE_TYPE c1;
10724 enum machine_mode compare_mode = GET_MODE (op0);
10725 enum machine_mode result_mode = GET_MODE (dest);
10727 bool is_against_zero;
10729 /* These modes should always match. */
10730 if (GET_MODE (op1) != compare_mode
10731 /* In the isel case however, we can use a compare immediate, so
10732 op1 may be a small constant. */
10733 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
10735 if (GET_MODE (true_cond) != result_mode)
10737 if (GET_MODE (false_cond) != result_mode)
10740 /* First, work out if the hardware can do this at all, or
10741 if it's too slow.... */
10742 if (! rs6000_compare_fp_p)
10745 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
10748 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
10749 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
10752 is_against_zero = op1 == CONST0_RTX (compare_mode);
10754 /* A floating-point subtract might overflow, underflow, or produce
10755 an inexact result, thus changing the floating-point flags, so it
10756 can't be generated if we care about that. It's safe if one side
10757 of the construct is zero, since then no subtract will be
10759 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT
10760 && flag_trapping_math && ! is_against_zero)
10763 /* Eliminate half of the comparisons by switching operands, this
10764 makes the remaining code simpler. */
10765 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
10766 || code == LTGT || code == LT || code == UNLE)
10768 code = reverse_condition_maybe_unordered (code);
10770 true_cond = false_cond;
10774 /* UNEQ and LTGT take four instructions for a comparison with zero,
10775 it'll probably be faster to use a branch here too. */
10776 if (code == UNEQ && HONOR_NANS (compare_mode))
10779 if (GET_CODE (op1) == CONST_DOUBLE)
10780 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
10782 /* We're going to try to implement comparisons by performing
10783 a subtract, then comparing against zero. Unfortunately,
10784 Inf - Inf is NaN which is not zero, and so if we don't
10785 know that the operand is finite and the comparison
10786 would treat EQ different to UNORDERED, we can't do it. */
10787 if (HONOR_INFINITIES (compare_mode)
10788 && code != GT && code != UNGE
10789 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
10790 /* Constructs of the form (a OP b ? a : b) are safe. */
10791 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
10792 || (! rtx_equal_p (op0, true_cond)
10793 && ! rtx_equal_p (op1, true_cond))))
10796 /* At this point we know we can use fsel. */
10798 /* Reduce the comparison to a comparison against zero. */
10799 if (! is_against_zero)
10801 temp = gen_reg_rtx (compare_mode);
10802 emit_insn (gen_rtx_SET (VOIDmode, temp,
10803 gen_rtx_MINUS (compare_mode, op0, op1)));
10805 op1 = CONST0_RTX (compare_mode);
10808 /* If we don't care about NaNs we can reduce some of the comparisons
10809 down to faster ones. */
10810 if (! HONOR_NANS (compare_mode))
10816 true_cond = false_cond;
10829 /* Now, reduce everything down to a GE. */
10836 temp = gen_reg_rtx (compare_mode);
10837 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10842 temp = gen_reg_rtx (compare_mode);
10843 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
10848 temp = gen_reg_rtx (compare_mode);
10849 emit_insn (gen_rtx_SET (VOIDmode, temp,
10850 gen_rtx_NEG (compare_mode,
10851 gen_rtx_ABS (compare_mode, op0))));
10856 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
10857 temp = gen_reg_rtx (result_mode);
10858 emit_insn (gen_rtx_SET (VOIDmode, temp,
10859 gen_rtx_IF_THEN_ELSE (result_mode,
10860 gen_rtx_GE (VOIDmode,
10862 true_cond, false_cond)));
10863 false_cond = true_cond;
10866 temp = gen_reg_rtx (compare_mode);
10867 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10872 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
10873 temp = gen_reg_rtx (result_mode);
10874 emit_insn (gen_rtx_SET (VOIDmode, temp,
10875 gen_rtx_IF_THEN_ELSE (result_mode,
10876 gen_rtx_GE (VOIDmode,
10878 true_cond, false_cond)));
10879 true_cond = false_cond;
10882 temp = gen_reg_rtx (compare_mode);
10883 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10891 emit_insn (gen_rtx_SET (VOIDmode, dest,
10892 gen_rtx_IF_THEN_ELSE (result_mode,
10893 gen_rtx_GE (VOIDmode,
10895 true_cond, false_cond)));
10899 /* Same as above, but for ints (isel). */
10902 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
10904 rtx condition_rtx, cr;
10906 /* All isel implementations thus far are 32-bits. */
10907 if (GET_MODE (rs6000_compare_op0) != SImode)
10910 /* We still have to do the compare, because isel doesn't do a
10911 compare, it just looks at the CRx bits set by a previous compare
10913 condition_rtx = rs6000_generate_compare (GET_CODE (op));
10914 cr = XEXP (condition_rtx, 0);
10916 if (GET_MODE (cr) == CCmode)
10917 emit_insn (gen_isel_signed (dest, condition_rtx,
10918 true_cond, false_cond, cr));
10920 emit_insn (gen_isel_unsigned (dest, condition_rtx,
10921 true_cond, false_cond, cr));
10927 output_isel (rtx *operands)
10929 enum rtx_code code;
10931 code = GET_CODE (operands[1]);
10932 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
10934 PUT_CODE (operands[1], reverse_condition (code));
10935 return "isel %0,%3,%2,%j1";
10938 return "isel %0,%2,%3,%j1";
10942 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
10944 enum machine_mode mode = GET_MODE (op0);
10948 if (code == SMAX || code == SMIN)
10953 if (code == SMAX || code == UMAX)
10954 target = emit_conditional_move (dest, c, op0, op1, mode,
10955 op0, op1, mode, 0);
10957 target = emit_conditional_move (dest, c, op0, op1, mode,
10958 op1, op0, mode, 0);
10959 if (target == NULL_RTX)
10961 if (target != dest)
10962 emit_move_insn (dest, target);
10965 /* Emit instructions to move SRC to DST. Called by splitters for
10966 multi-register moves. It will emit at most one instruction for
10967 each register that is accessed; that is, it won't emit li/lis pairs
10968 (or equivalent for 64-bit code). One of SRC or DST must be a hard
10972 rs6000_split_multireg_move (rtx dst, rtx src)
10974 /* The register number of the first register being moved. */
10976 /* The mode that is to be moved. */
10977 enum machine_mode mode;
10978 /* The mode that the move is being done in, and its size. */
10979 enum machine_mode reg_mode;
10981 /* The number of registers that will be moved. */
10984 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
10985 mode = GET_MODE (dst);
10986 nregs = HARD_REGNO_NREGS (reg, mode);
10987 if (FP_REGNO_P (reg))
10989 else if (ALTIVEC_REGNO_P (reg))
10990 reg_mode = V16QImode;
10992 reg_mode = word_mode;
10993 reg_mode_size = GET_MODE_SIZE (reg_mode);
10995 if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
10998 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
11000 /* Move register range backwards, if we might have destructive
11003 for (i = nregs - 1; i >= 0; i--)
11004 emit_insn (gen_rtx_SET (VOIDmode,
11005 simplify_gen_subreg (reg_mode, dst, mode,
11006 i * reg_mode_size),
11007 simplify_gen_subreg (reg_mode, src, mode,
11008 i * reg_mode_size)));
11014 bool used_update = false;
11016 if (MEM_P (src) && INT_REGNO_P (reg))
11020 if (GET_CODE (XEXP (src, 0)) == PRE_INC
11021 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
11024 breg = XEXP (XEXP (src, 0), 0);
11025 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
11026 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
11027 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
11028 emit_insn (TARGET_32BIT
11029 ? gen_addsi3 (breg, breg, delta_rtx)
11030 : gen_adddi3 (breg, breg, delta_rtx));
11031 src = gen_rtx_MEM (mode, breg);
11033 else if (! offsettable_memref_p (src))
11035 rtx newsrc, basereg;
11036 basereg = gen_rtx_REG (Pmode, reg);
11037 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
11038 newsrc = gen_rtx_MEM (GET_MODE (src), basereg);
11039 MEM_COPY_ATTRIBUTES (newsrc, src);
11043 breg = XEXP (src, 0);
11044 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
11045 breg = XEXP (breg, 0);
11047 /* If the base register we are using to address memory is
11048 also a destination reg, then change that register last. */
11050 && REGNO (breg) >= REGNO (dst)
11051 && REGNO (breg) < REGNO (dst) + nregs)
11052 j = REGNO (breg) - REGNO (dst);
11055 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
11059 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
11060 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
11063 breg = XEXP (XEXP (dst, 0), 0);
11064 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
11065 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
11066 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
11068 /* We have to update the breg before doing the store.
11069 Use store with update, if available. */
11073 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
11074 emit_insn (TARGET_32BIT
11075 ? (TARGET_POWERPC64
11076 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
11077 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
11078 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
11079 used_update = true;
11082 emit_insn (TARGET_32BIT
11083 ? gen_addsi3 (breg, breg, delta_rtx)
11084 : gen_adddi3 (breg, breg, delta_rtx));
11085 dst = gen_rtx_MEM (mode, breg);
11087 else if (! offsettable_memref_p (dst))
11091 for (i = 0; i < nregs; i++)
11093 /* Calculate index to next subword. */
11098 /* If compiler already emitted move of first word by
11099 store with update, no need to do anything. */
11100 if (j == 0 && used_update)
11103 emit_insn (gen_rtx_SET (VOIDmode,
11104 simplify_gen_subreg (reg_mode, dst, mode,
11105 j * reg_mode_size),
11106 simplify_gen_subreg (reg_mode, src, mode,
11107 j * reg_mode_size)));
11113 /* This page contains routines that are used to determine what the
11114 function prologue and epilogue code will do and write them out. */
11116 /* Return the first fixed-point register that is required to be
11117 saved. 32 if none. */
11120 first_reg_to_save (void)
11124 /* Find lowest numbered live register. */
11125 for (first_reg = 13; first_reg <= 31; first_reg++)
11126 if (regs_ever_live[first_reg]
11127 && (! call_used_regs[first_reg]
11128 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
11129 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
11130 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
11131 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
11136 && current_function_uses_pic_offset_table
11137 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
11138 return RS6000_PIC_OFFSET_TABLE_REGNUM;
11144 /* Similar, for FP regs. */
11147 first_fp_reg_to_save (void)
11151 /* Find lowest numbered live register. */
11152 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
11153 if (regs_ever_live[first_reg])
11159 /* Similar, for AltiVec regs. */
11162 first_altivec_reg_to_save (void)
11166 /* Stack frame remains as is unless we are in AltiVec ABI. */
11167 if (! TARGET_ALTIVEC_ABI)
11168 return LAST_ALTIVEC_REGNO + 1;
11170 /* Find lowest numbered live register. */
11171 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
11172 if (regs_ever_live[i])
11178 /* Return a 32-bit mask of the AltiVec registers we need to set in
11179 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
11180 the 32-bit word is 0. */
11182 static unsigned int
11183 compute_vrsave_mask (void)
11185 unsigned int i, mask = 0;
11187 /* First, find out if we use _any_ altivec registers. */
11188 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
11189 if (regs_ever_live[i])
11190 mask |= ALTIVEC_REG_BIT (i);
11195 /* Next, remove the argument registers from the set. These must
11196 be in the VRSAVE mask set by the caller, so we don't need to add
11197 them in again. More importantly, the mask we compute here is
11198 used to generate CLOBBERs in the set_vrsave insn, and we do not
11199 wish the argument registers to die. */
11200 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
11201 mask &= ~ALTIVEC_REG_BIT (i);
11203 /* Similarly, remove the return value from the set. */
11206 diddle_return_value (is_altivec_return_reg, &yes);
11208 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
11214 /* For a very restricted set of circumstances, we can cut down the
11215 size of prologues/epilogues by calling our own save/restore-the-world
11219 compute_save_world_info (rs6000_stack_t *info_ptr)
11221 info_ptr->world_save_p = 1;
11222 info_ptr->world_save_p
11223 = (WORLD_SAVE_P (info_ptr)
11224 && DEFAULT_ABI == ABI_DARWIN
11225 && ! (current_function_calls_setjmp && flag_exceptions)
11226 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
11227 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
11228 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
11229 && info_ptr->cr_save_p);
11231 /* This will not work in conjunction with sibcalls. Make sure there
11232 are none. (This check is expensive, but seldom executed.) */
11233 if (WORLD_SAVE_P (info_ptr))
11236 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
11237 if ( GET_CODE (insn) == CALL_INSN
11238 && SIBLING_CALL_P (insn))
11240 info_ptr->world_save_p = 0;
11245 if (WORLD_SAVE_P (info_ptr))
11247 /* Even if we're not touching VRsave, make sure there's room on the
11248 stack for it, if it looks like we're calling SAVE_WORLD, which
11249 will attempt to save it. */
11250 info_ptr->vrsave_size = 4;
11252 /* "Save" the VRsave register too if we're saving the world. */
11253 if (info_ptr->vrsave_mask == 0)
11254 info_ptr->vrsave_mask = compute_vrsave_mask ();
11256 /* Because the Darwin register save/restore routines only handle
11257 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
11258 check and abort if there's something worng. */
11259 if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO
11260 || info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO)
11268 is_altivec_return_reg (rtx reg, void *xyes)
11270 bool *yes = (bool *) xyes;
11271 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
11276 /* Calculate the stack information for the current function. This is
11277 complicated by having two separate calling sequences, the AIX calling
11278 sequence and the V.4 calling sequence.
11280 AIX (and Darwin/Mac OS X) stack frames look like:
11282 SP----> +---------------------------------------+
11283 | back chain to caller | 0 0
11284 +---------------------------------------+
11285 | saved CR | 4 8 (8-11)
11286 +---------------------------------------+
11288 +---------------------------------------+
11289 | reserved for compilers | 12 24
11290 +---------------------------------------+
11291 | reserved for binders | 16 32
11292 +---------------------------------------+
11293 | saved TOC pointer | 20 40
11294 +---------------------------------------+
11295 | Parameter save area (P) | 24 48
11296 +---------------------------------------+
11297 | Alloca space (A) | 24+P etc.
11298 +---------------------------------------+
11299 | Local variable space (L) | 24+P+A
11300 +---------------------------------------+
11301 | Float/int conversion temporary (X) | 24+P+A+L
11302 +---------------------------------------+
11303 | Save area for AltiVec registers (W) | 24+P+A+L+X
11304 +---------------------------------------+
11305 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
11306 +---------------------------------------+
11307 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
11308 +---------------------------------------+
11309 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
11310 +---------------------------------------+
11311 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
11312 +---------------------------------------+
11313 old SP->| back chain to caller's caller |
11314 +---------------------------------------+
11316 The required alignment for AIX configurations is two words (i.e., 8
11320 V.4 stack frames look like:
11322 SP----> +---------------------------------------+
11323 | back chain to caller | 0
11324 +---------------------------------------+
11325 | caller's saved LR | 4
11326 +---------------------------------------+
11327 | Parameter save area (P) | 8
11328 +---------------------------------------+
11329 | Alloca space (A) | 8+P
11330 +---------------------------------------+
11331 | Varargs save area (V) | 8+P+A
11332 +---------------------------------------+
11333 | Local variable space (L) | 8+P+A+V
11334 +---------------------------------------+
11335 | Float/int conversion temporary (X) | 8+P+A+V+L
11336 +---------------------------------------+
11337 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
11338 +---------------------------------------+
11339 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
11340 +---------------------------------------+
11341 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
11342 +---------------------------------------+
11343 | SPE: area for 64-bit GP registers |
11344 +---------------------------------------+
11345 | SPE alignment padding |
11346 +---------------------------------------+
11347 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
11348 +---------------------------------------+
11349 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
11350 +---------------------------------------+
11351 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
11352 +---------------------------------------+
11353 old SP->| back chain to caller's caller |
11354 +---------------------------------------+
11356 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
11357 given. (But note below and in sysv4.h that we require only 8 and
11358 may round up the size of our stack frame anyways. The historical
11359 reason is early versions of powerpc-linux which didn't properly
11360 align the stack at program startup. A happy side-effect is that
11361 -mno-eabi libraries can be used with -meabi programs.)
11363 The EABI configuration defaults to the V.4 layout. However,
11364 the stack alignment requirements may differ. If -mno-eabi is not
11365 given, the required stack alignment is 8 bytes; if -mno-eabi is
11366 given, the required alignment is 16 bytes. (But see V.4 comment
11369 #ifndef ABI_STACK_BOUNDARY
11370 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
11373 static rs6000_stack_t *
11374 rs6000_stack_info (void)
11376 static rs6000_stack_t info, zero_info;
11377 rs6000_stack_t *info_ptr = &info;
11378 int reg_size = TARGET_32BIT ? 4 : 8;
11381 HOST_WIDE_INT non_fixed_size;
11383 /* Zero all fields portably. */
11388 /* Cache value so we don't rescan instruction chain over and over. */
11389 if (cfun->machine->insn_chain_scanned_p == 0)
11390 cfun->machine->insn_chain_scanned_p
11391 = spe_func_has_64bit_regs_p () + 1;
11392 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
11395 /* Select which calling sequence. */
11396 info_ptr->abi = DEFAULT_ABI;
11398 /* Calculate which registers need to be saved & save area size. */
11399 info_ptr->first_gp_reg_save = first_reg_to_save ();
11400 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
11401 even if it currently looks like we won't. */
11402 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
11403 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
11404 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
11405 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
11406 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
11408 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
11410 /* For the SPE, we have an additional upper 32-bits on each GPR.
11411 Ideally we should save the entire 64-bits only when the upper
11412 half is used in SIMD instructions. Since we only record
11413 registers live (not the size they are used in), this proves
11414 difficult because we'd have to traverse the instruction chain at
11415 the right time, taking reload into account. This is a real pain,
11416 so we opt to save the GPRs in 64-bits always if but one register
11417 gets used in 64-bits. Otherwise, all the registers in the frame
11418 get saved in 32-bits.
11420 So... since when we save all GPRs (except the SP) in 64-bits, the
11421 traditional GP save area will be empty. */
11422 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
11423 info_ptr->gp_size = 0;
11425 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
11426 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
11428 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
11429 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
11430 - info_ptr->first_altivec_reg_save);
11432 /* Does this function call anything? */
11433 info_ptr->calls_p = (! current_function_is_leaf
11434 || cfun->machine->ra_needs_full_frame);
11436 /* Determine if we need to save the link register. */
11437 if (rs6000_ra_ever_killed ()
11438 || (DEFAULT_ABI == ABI_AIX
11439 && current_function_profile
11440 && !TARGET_PROFILE_KERNEL)
11441 #ifdef TARGET_RELOCATABLE
11442 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
11444 || (info_ptr->first_fp_reg_save != 64
11445 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
11446 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
11447 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
11448 || (DEFAULT_ABI == ABI_DARWIN
11450 && current_function_uses_pic_offset_table)
11451 || info_ptr->calls_p)
11453 info_ptr->lr_save_p = 1;
11454 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
11457 /* Determine if we need to save the condition code registers. */
11458 if (regs_ever_live[CR2_REGNO]
11459 || regs_ever_live[CR3_REGNO]
11460 || regs_ever_live[CR4_REGNO])
11462 info_ptr->cr_save_p = 1;
11463 if (DEFAULT_ABI == ABI_V4)
11464 info_ptr->cr_size = reg_size;
11467 /* If the current function calls __builtin_eh_return, then we need
11468 to allocate stack space for registers that will hold data for
11469 the exception handler. */
11470 if (current_function_calls_eh_return)
11473 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
11476 /* SPE saves EH registers in 64-bits. */
11477 ehrd_size = i * (TARGET_SPE_ABI
11478 && info_ptr->spe_64bit_regs_used != 0
11479 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
11484 /* Determine various sizes. */
11485 info_ptr->reg_size = reg_size;
11486 info_ptr->fixed_size = RS6000_SAVE_AREA;
11487 info_ptr->varargs_size = RS6000_VARARGS_AREA;
11488 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
11489 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
11490 TARGET_ALTIVEC ? 16 : 8);
11492 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
11493 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
11495 info_ptr->spe_gp_size = 0;
11497 if (TARGET_ALTIVEC_ABI)
11498 info_ptr->vrsave_mask = compute_vrsave_mask ();
11500 info_ptr->vrsave_mask = 0;
11502 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
11503 info_ptr->vrsave_size = 4;
11505 info_ptr->vrsave_size = 0;
11507 compute_save_world_info (info_ptr);
11509 /* Calculate the offsets. */
11510 switch (DEFAULT_ABI)
11518 info_ptr->fp_save_offset = - info_ptr->fp_size;
11519 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
11521 if (TARGET_ALTIVEC_ABI)
11523 info_ptr->vrsave_save_offset
11524 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
11526 /* Align stack so vector save area is on a quadword boundary. */
11527 if (info_ptr->altivec_size != 0)
11528 info_ptr->altivec_padding_size
11529 = 16 - (-info_ptr->vrsave_save_offset % 16);
11531 info_ptr->altivec_padding_size = 0;
11533 info_ptr->altivec_save_offset
11534 = info_ptr->vrsave_save_offset
11535 - info_ptr->altivec_padding_size
11536 - info_ptr->altivec_size;
11538 /* Adjust for AltiVec case. */
11539 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
11542 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
11543 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
11544 info_ptr->lr_save_offset = 2*reg_size;
11548 info_ptr->fp_save_offset = - info_ptr->fp_size;
11549 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
11550 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
11552 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
11554 /* Align stack so SPE GPR save area is aligned on a
11555 double-word boundary. */
11556 if (info_ptr->spe_gp_size != 0)
11557 info_ptr->spe_padding_size
11558 = 8 - (-info_ptr->cr_save_offset % 8);
11560 info_ptr->spe_padding_size = 0;
11562 info_ptr->spe_gp_save_offset
11563 = info_ptr->cr_save_offset
11564 - info_ptr->spe_padding_size
11565 - info_ptr->spe_gp_size;
11567 /* Adjust for SPE case. */
11568 info_ptr->toc_save_offset
11569 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
11571 else if (TARGET_ALTIVEC_ABI)
11573 info_ptr->vrsave_save_offset
11574 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
11576 /* Align stack so vector save area is on a quadword boundary. */
11577 if (info_ptr->altivec_size != 0)
11578 info_ptr->altivec_padding_size
11579 = 16 - (-info_ptr->vrsave_save_offset % 16);
11581 info_ptr->altivec_padding_size = 0;
11583 info_ptr->altivec_save_offset
11584 = info_ptr->vrsave_save_offset
11585 - info_ptr->altivec_padding_size
11586 - info_ptr->altivec_size;
11588 /* Adjust for AltiVec case. */
11589 info_ptr->toc_save_offset
11590 = info_ptr->altivec_save_offset - info_ptr->toc_size;
11593 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
11594 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
11595 info_ptr->lr_save_offset = reg_size;
11599 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
11600 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
11601 + info_ptr->gp_size
11602 + info_ptr->altivec_size
11603 + info_ptr->altivec_padding_size
11604 + info_ptr->spe_gp_size
11605 + info_ptr->spe_padding_size
11607 + info_ptr->cr_size
11608 + info_ptr->lr_size
11609 + info_ptr->vrsave_size
11610 + info_ptr->toc_size,
11613 non_fixed_size = (info_ptr->vars_size
11614 + info_ptr->parm_size
11615 + info_ptr->save_size
11616 + info_ptr->varargs_size);
11618 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
11619 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
11621 /* Determine if we need to allocate any stack frame:
11623 For AIX we need to push the stack if a frame pointer is needed
11624 (because the stack might be dynamically adjusted), if we are
11625 debugging, if we make calls, or if the sum of fp_save, gp_save,
11626 and local variables are more than the space needed to save all
11627 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
11628 + 18*8 = 288 (GPR13 reserved).
11630 For V.4 we don't have the stack cushion that AIX uses, but assume
11631 that the debugger can handle stackless frames. */
11633 if (info_ptr->calls_p)
11634 info_ptr->push_p = 1;
11636 else if (DEFAULT_ABI == ABI_V4)
11637 info_ptr->push_p = non_fixed_size != 0;
11639 else if (frame_pointer_needed)
11640 info_ptr->push_p = 1;
11642 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
11643 info_ptr->push_p = 1;
11646 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
11648 /* Zero offsets if we're not saving those registers. */
11649 if (info_ptr->fp_size == 0)
11650 info_ptr->fp_save_offset = 0;
11652 if (info_ptr->gp_size == 0)
11653 info_ptr->gp_save_offset = 0;
11655 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
11656 info_ptr->altivec_save_offset = 0;
11658 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
11659 info_ptr->vrsave_save_offset = 0;
11661 if (! TARGET_SPE_ABI
11662 || info_ptr->spe_64bit_regs_used == 0
11663 || info_ptr->spe_gp_size == 0)
11664 info_ptr->spe_gp_save_offset = 0;
11666 if (! info_ptr->lr_save_p)
11667 info_ptr->lr_save_offset = 0;
11669 if (! info_ptr->cr_save_p)
11670 info_ptr->cr_save_offset = 0;
11672 if (! info_ptr->toc_save_p)
11673 info_ptr->toc_save_offset = 0;
11678 /* Return true if the current function uses any GPRs in 64-bit SIMD
11682 spe_func_has_64bit_regs_p (void)
11686 /* Functions that save and restore all the call-saved registers will
11687 need to save/restore the registers in 64-bits. */
11688 if (current_function_calls_eh_return
11689 || current_function_calls_setjmp
11690 || current_function_has_nonlocal_goto)
11693 insns = get_insns ();
11695 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
11701 /* FIXME: This should be implemented with attributes...
11703 (set_attr "spe64" "true")....then,
11704 if (get_spe64(insn)) return true;
11706 It's the only reliable way to do the stuff below. */
11708 i = PATTERN (insn);
11709 if (GET_CODE (i) == SET)
11711 enum machine_mode mode = GET_MODE (SET_SRC (i));
11713 if (SPE_VECTOR_MODE (mode))
11715 if (TARGET_E500_DOUBLE && mode == DFmode)
11725 debug_stack_info (rs6000_stack_t *info)
11727 const char *abi_string;
11730 info = rs6000_stack_info ();
11732 fprintf (stderr, "\nStack information for function %s:\n",
11733 ((current_function_decl && DECL_NAME (current_function_decl))
11734 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
11739 default: abi_string = "Unknown"; break;
11740 case ABI_NONE: abi_string = "NONE"; break;
11741 case ABI_AIX: abi_string = "AIX"; break;
11742 case ABI_DARWIN: abi_string = "Darwin"; break;
11743 case ABI_V4: abi_string = "V.4"; break;
11746 fprintf (stderr, "\tABI = %5s\n", abi_string);
11748 if (TARGET_ALTIVEC_ABI)
11749 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
11751 if (TARGET_SPE_ABI)
11752 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
11754 if (info->first_gp_reg_save != 32)
11755 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
11757 if (info->first_fp_reg_save != 64)
11758 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
11760 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
11761 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
11762 info->first_altivec_reg_save);
11764 if (info->lr_save_p)
11765 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
11767 if (info->cr_save_p)
11768 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
11770 if (info->toc_save_p)
11771 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
11773 if (info->vrsave_mask)
11774 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
11777 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
11780 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
11782 if (info->gp_save_offset)
11783 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
11785 if (info->fp_save_offset)
11786 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
11788 if (info->altivec_save_offset)
11789 fprintf (stderr, "\taltivec_save_offset = %5d\n",
11790 info->altivec_save_offset);
11792 if (info->spe_gp_save_offset)
11793 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
11794 info->spe_gp_save_offset);
11796 if (info->vrsave_save_offset)
11797 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
11798 info->vrsave_save_offset);
11800 if (info->lr_save_offset)
11801 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
11803 if (info->cr_save_offset)
11804 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
11806 if (info->toc_save_offset)
11807 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
11809 if (info->varargs_save_offset)
11810 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
11812 if (info->total_size)
11813 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
11816 if (info->varargs_size)
11817 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
11819 if (info->vars_size)
11820 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
11823 if (info->parm_size)
11824 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
11826 if (info->fixed_size)
11827 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
11830 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
11832 if (info->spe_gp_size)
11833 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
11836 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
11838 if (info->altivec_size)
11839 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
11841 if (info->vrsave_size)
11842 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
11844 if (info->altivec_padding_size)
11845 fprintf (stderr, "\taltivec_padding_size= %5d\n",
11846 info->altivec_padding_size);
11848 if (info->spe_padding_size)
11849 fprintf (stderr, "\tspe_padding_size = %5d\n",
11850 info->spe_padding_size);
11853 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
11856 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
11858 if (info->toc_size)
11859 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
11861 if (info->save_size)
11862 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
11864 if (info->reg_size != 4)
11865 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
11867 fprintf (stderr, "\n");
11871 rs6000_return_addr (int count, rtx frame)
11873 /* Currently we don't optimize very well between prolog and body
11874 code and for PIC code the code can be actually quite bad, so
11875 don't try to be too clever here. */
11876 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
11878 cfun->machine->ra_needs_full_frame = 1;
11885 plus_constant (copy_to_reg
11886 (gen_rtx_MEM (Pmode,
11887 memory_address (Pmode, frame))),
11888 RETURN_ADDRESS_OFFSET)));
11891 cfun->machine->ra_need_lr = 1;
11892 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
11895 /* Say whether a function is a candidate for sibcall handling or not.
11896 We do not allow indirect calls to be optimized into sibling calls.
11897 Also, we can't do it if there are any vector parameters; there's
11898 nowhere to put the VRsave code so it works; note that functions with
11899 vector parameters are required to have a prototype, so the argument
11900 type info must be available here. (The tail recursion case can work
11901 with vector parameters, but there's no way to distinguish here.) */
11903 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
11908 if (TARGET_ALTIVEC_VRSAVE)
11910 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
11911 type; type = TREE_CHAIN (type))
11913 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
11917 if (DEFAULT_ABI == ABI_DARWIN
11918 || (*targetm.binds_local_p) (decl))
11920 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
11922 if (!lookup_attribute ("longcall", attr_list)
11923 || lookup_attribute ("shortcall", attr_list))
11931 rs6000_ra_ever_killed (void)
11937 if (current_function_is_thunk)
11940 /* regs_ever_live has LR marked as used if any sibcalls are present,
11941 but this should not force saving and restoring in the
11942 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
11943 clobbers LR, so that is inappropriate. */
11945 /* Also, the prologue can generate a store into LR that
11946 doesn't really count, like this:
11949 bcl to set PIC register
11953 When we're called from the epilogue, we need to avoid counting
11954 this as a store. */
11956 push_topmost_sequence ();
11957 top = get_insns ();
11958 pop_topmost_sequence ();
11959 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11961 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
11965 if (FIND_REG_INC_NOTE (insn, reg))
11967 else if (GET_CODE (insn) == CALL_INSN
11968 && !SIBLING_CALL_P (insn))
11970 else if (set_of (reg, insn) != NULL_RTX
11971 && !prologue_epilogue_contains (insn))
11978 /* Add a REG_MAYBE_DEAD note to the insn. */
11980 rs6000_maybe_dead (rtx insn)
11982 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
11987 /* Emit instructions needed to load the TOC register.
11988 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
11989 a constant pool; or for SVR4 -fpic. */
11992 rs6000_emit_load_toc_table (int fromprolog)
11995 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11997 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11999 rtx temp = (fromprolog
12000 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12001 : gen_reg_rtx (Pmode));
12002 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
12004 rs6000_maybe_dead (insn);
12005 insn = emit_move_insn (dest, temp);
12007 rs6000_maybe_dead (insn);
12009 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
12012 rtx tempLR = (fromprolog
12013 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12014 : gen_reg_rtx (Pmode));
12015 rtx temp0 = (fromprolog
12016 ? gen_rtx_REG (Pmode, 0)
12017 : gen_reg_rtx (Pmode));
12023 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
12024 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12026 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
12027 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12029 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
12031 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
12032 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
12040 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
12041 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
12042 emit_move_insn (dest, tempLR);
12043 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
12045 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
12047 rs6000_maybe_dead (insn);
12049 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
12051 /* This is for AIX code running in non-PIC ELF32. */
12054 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
12055 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12057 insn = emit_insn (gen_elf_high (dest, realsym));
12059 rs6000_maybe_dead (insn);
12060 insn = emit_insn (gen_elf_low (dest, dest, realsym));
12062 rs6000_maybe_dead (insn);
12064 else if (DEFAULT_ABI == ABI_AIX)
12067 insn = emit_insn (gen_load_toc_aix_si (dest));
12069 insn = emit_insn (gen_load_toc_aix_di (dest));
12071 rs6000_maybe_dead (insn);
12077 /* Emit instructions to restore the link register after determining where
12078 its value has been stored. */
12081 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
12083 rs6000_stack_t *info = rs6000_stack_info ();
12086 operands[0] = source;
12087 operands[1] = scratch;
12089 if (info->lr_save_p)
12091 rtx frame_rtx = stack_pointer_rtx;
12092 HOST_WIDE_INT sp_offset = 0;
12095 if (frame_pointer_needed
12096 || current_function_calls_alloca
12097 || info->total_size > 32767)
12099 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
12100 frame_rtx = operands[1];
12102 else if (info->push_p)
12103 sp_offset = info->total_size;
12105 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
12106 tmp = gen_rtx_MEM (Pmode, tmp);
12107 emit_move_insn (tmp, operands[0]);
12110 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
12113 static GTY(()) int set = -1;
12116 get_TOC_alias_set (void)
12119 set = new_alias_set ();
12123 /* This returns nonzero if the current function uses the TOC. This is
12124 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
12125 is generated by the ABI_V4 load_toc_* patterns. */
12132 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12135 rtx pat = PATTERN (insn);
12138 if (GET_CODE (pat) == PARALLEL)
12139 for (i = 0; i < XVECLEN (pat, 0); i++)
12141 rtx sub = XVECEXP (pat, 0, i);
12142 if (GET_CODE (sub) == USE)
12144 sub = XEXP (sub, 0);
12145 if (GET_CODE (sub) == UNSPEC
12146 && XINT (sub, 1) == UNSPEC_TOC)
12156 create_TOC_reference (rtx symbol)
12158 return gen_rtx_PLUS (Pmode,
12159 gen_rtx_REG (Pmode, TOC_REGISTER),
12160 gen_rtx_CONST (Pmode,
12161 gen_rtx_MINUS (Pmode, symbol,
12162 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
12165 /* If _Unwind_* has been called from within the same module,
12166 toc register is not guaranteed to be saved to 40(1) on function
12167 entry. Save it there in that case. */
12170 rs6000_aix_emit_builtin_unwind_init (void)
12173 rtx stack_top = gen_reg_rtx (Pmode);
12174 rtx opcode_addr = gen_reg_rtx (Pmode);
12175 rtx opcode = gen_reg_rtx (SImode);
12176 rtx tocompare = gen_reg_rtx (SImode);
12177 rtx no_toc_save_needed = gen_label_rtx ();
12179 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
12180 emit_move_insn (stack_top, mem);
12182 mem = gen_rtx_MEM (Pmode,
12183 gen_rtx_PLUS (Pmode, stack_top,
12184 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
12185 emit_move_insn (opcode_addr, mem);
12186 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
12187 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
12188 : 0xE8410028, SImode));
12190 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
12191 SImode, NULL_RTX, NULL_RTX,
12192 no_toc_save_needed);
12194 mem = gen_rtx_MEM (Pmode,
12195 gen_rtx_PLUS (Pmode, stack_top,
12196 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
12197 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
12198 emit_label (no_toc_save_needed);
12201 /* This ties together stack memory (MEM with an alias set of
12202 rs6000_sr_alias_set) and the change to the stack pointer. */
12205 rs6000_emit_stack_tie (void)
12207 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
12209 set_mem_alias_set (mem, rs6000_sr_alias_set);
12210 emit_insn (gen_stack_tie (mem));
12213 /* Emit the correct code for allocating stack space, as insns.
12214 If COPY_R12, make sure a copy of the old frame is left in r12.
12215 The generated code may use hard register 0 as a temporary. */
12218 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
12221 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12222 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
12223 rtx todec = gen_int_mode (-size, Pmode);
12225 if (INTVAL (todec) != -size)
12227 warning ("stack frame too large");
12228 emit_insn (gen_trap ());
12232 if (current_function_limit_stack)
12234 if (REG_P (stack_limit_rtx)
12235 && REGNO (stack_limit_rtx) > 1
12236 && REGNO (stack_limit_rtx) <= 31)
12238 emit_insn (TARGET_32BIT
12239 ? gen_addsi3 (tmp_reg,
12242 : gen_adddi3 (tmp_reg,
12246 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12249 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
12251 && DEFAULT_ABI == ABI_V4)
12253 rtx toload = gen_rtx_CONST (VOIDmode,
12254 gen_rtx_PLUS (Pmode,
12258 emit_insn (gen_elf_high (tmp_reg, toload));
12259 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
12260 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12264 warning ("stack limit expression is not supported");
12267 if (copy_r12 || ! TARGET_UPDATE)
12268 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
12274 /* Need a note here so that try_split doesn't get confused. */
12275 if (get_last_insn () == NULL_RTX)
12276 emit_note (NOTE_INSN_DELETED);
12277 insn = emit_move_insn (tmp_reg, todec);
12278 try_split (PATTERN (insn), insn, 0);
12282 insn = emit_insn (TARGET_32BIT
12283 ? gen_movsi_update (stack_reg, stack_reg,
12285 : gen_movdi_di_update (stack_reg, stack_reg,
12286 todec, stack_reg));
12290 insn = emit_insn (TARGET_32BIT
12291 ? gen_addsi3 (stack_reg, stack_reg, todec)
12292 : gen_adddi3 (stack_reg, stack_reg, todec));
12293 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
12294 gen_rtx_REG (Pmode, 12));
12297 RTX_FRAME_RELATED_P (insn) = 1;
12299 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12300 gen_rtx_SET (VOIDmode, stack_reg,
12301 gen_rtx_PLUS (Pmode, stack_reg,
12306 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
12307 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
12308 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
12309 deduce these equivalences by itself so it wasn't necessary to hold
12310 its hand so much. */
12313 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
12314 rtx reg2, rtx rreg)
12318 /* copy_rtx will not make unique copies of registers, so we need to
12319 ensure we don't have unwanted sharing here. */
12321 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12324 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12326 real = copy_rtx (PATTERN (insn));
12328 if (reg2 != NULL_RTX)
12329 real = replace_rtx (real, reg2, rreg);
12331 real = replace_rtx (real, reg,
12332 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
12333 STACK_POINTER_REGNUM),
12336 /* We expect that 'real' is either a SET or a PARALLEL containing
12337 SETs (and possibly other stuff). In a PARALLEL, all the SETs
12338 are important so they all have to be marked RTX_FRAME_RELATED_P. */
12340 if (GET_CODE (real) == SET)
12344 temp = simplify_rtx (SET_SRC (set));
12346 SET_SRC (set) = temp;
12347 temp = simplify_rtx (SET_DEST (set));
12349 SET_DEST (set) = temp;
12350 if (GET_CODE (SET_DEST (set)) == MEM)
12352 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
12354 XEXP (SET_DEST (set), 0) = temp;
12357 else if (GET_CODE (real) == PARALLEL)
12360 for (i = 0; i < XVECLEN (real, 0); i++)
12361 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
12363 rtx set = XVECEXP (real, 0, i);
12365 temp = simplify_rtx (SET_SRC (set));
12367 SET_SRC (set) = temp;
12368 temp = simplify_rtx (SET_DEST (set));
12370 SET_DEST (set) = temp;
12371 if (GET_CODE (SET_DEST (set)) == MEM)
12373 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
12375 XEXP (SET_DEST (set), 0) = temp;
12377 RTX_FRAME_RELATED_P (set) = 1;
12384 real = spe_synthesize_frame_save (real);
12386 RTX_FRAME_RELATED_P (insn) = 1;
12387 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12392 /* Given an SPE frame note, return a PARALLEL of SETs with the
12393 original note, plus a synthetic register save. */
12396 spe_synthesize_frame_save (rtx real)
12398 rtx synth, offset, reg, real2;
12400 if (GET_CODE (real) != SET
12401 || GET_MODE (SET_SRC (real)) != V2SImode)
12404 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
12405 frame related note. The parallel contains a set of the register
12406 being saved, and another set to a synthetic register (n+1200).
12407 This is so we can differentiate between 64-bit and 32-bit saves.
12408 Words cannot describe this nastiness. */
12410 if (GET_CODE (SET_DEST (real)) != MEM
12411 || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
12412 || GET_CODE (SET_SRC (real)) != REG)
12416 (set (mem (plus (reg x) (const y)))
12419 (set (mem (plus (reg x) (const y+4)))
12423 real2 = copy_rtx (real);
12424 PUT_MODE (SET_DEST (real2), SImode);
12425 reg = SET_SRC (real2);
12426 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
12427 synth = copy_rtx (real2);
12429 if (BYTES_BIG_ENDIAN)
12431 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
12432 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
12435 reg = SET_SRC (synth);
12437 synth = replace_rtx (synth, reg,
12438 gen_rtx_REG (SImode, REGNO (reg) + 1200));
12440 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
12441 synth = replace_rtx (synth, offset,
12442 GEN_INT (INTVAL (offset)
12443 + (BYTES_BIG_ENDIAN ? 0 : 4)));
12445 RTX_FRAME_RELATED_P (synth) = 1;
12446 RTX_FRAME_RELATED_P (real2) = 1;
12447 if (BYTES_BIG_ENDIAN)
12448 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
12450 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
12455 /* Returns an insn that has a vrsave set operation with the
12456 appropriate CLOBBERs. */
12459 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
12462 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
12463 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
12466 = gen_rtx_SET (VOIDmode,
12468 gen_rtx_UNSPEC_VOLATILE (SImode,
12469 gen_rtvec (2, reg, vrsave),
12474 /* We need to clobber the registers in the mask so the scheduler
12475 does not move sets to VRSAVE before sets of AltiVec registers.
12477 However, if the function receives nonlocal gotos, reload will set
12478 all call saved registers live. We will end up with:
12480 (set (reg 999) (mem))
12481 (parallel [ (set (reg vrsave) (unspec blah))
12482 (clobber (reg 999))])
12484 The clobber will cause the store into reg 999 to be dead, and
12485 flow will attempt to delete an epilogue insn. In this case, we
12486 need an unspec use/set of the register. */
12488 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12489 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12491 if (!epiloguep || call_used_regs [i])
12492 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
12493 gen_rtx_REG (V4SImode, i));
12496 rtx reg = gen_rtx_REG (V4SImode, i);
12499 = gen_rtx_SET (VOIDmode,
12501 gen_rtx_UNSPEC (V4SImode,
12502 gen_rtvec (1, reg), 27));
12506 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
12508 for (i = 0; i < nclobs; ++i)
12509 XVECEXP (insn, 0, i) = clobs[i];
12514 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
12515 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
12518 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
12519 unsigned int regno, int offset, HOST_WIDE_INT total_size)
12521 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
12522 rtx replacea, replaceb;
12524 int_rtx = GEN_INT (offset);
12526 /* Some cases that need register indexed addressing. */
12527 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12528 || (TARGET_E500_DOUBLE && mode == DFmode)
12530 && SPE_VECTOR_MODE (mode)
12531 && !SPE_CONST_OFFSET_OK (offset)))
12533 /* Whomever calls us must make sure r11 is available in the
12534 flow path of instructions in the prologue. */
12535 offset_rtx = gen_rtx_REG (Pmode, 11);
12536 emit_move_insn (offset_rtx, int_rtx);
12538 replacea = offset_rtx;
12539 replaceb = int_rtx;
12543 offset_rtx = int_rtx;
12544 replacea = NULL_RTX;
12545 replaceb = NULL_RTX;
12548 reg = gen_rtx_REG (mode, regno);
12549 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
12550 mem = gen_rtx_MEM (mode, addr);
12551 set_mem_alias_set (mem, rs6000_sr_alias_set);
12553 insn = emit_move_insn (mem, reg);
12555 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
12558 /* Emit an offset memory reference suitable for a frame store, while
12559 converting to a valid addressing mode. */
12562 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
12564 rtx int_rtx, offset_rtx;
12566 int_rtx = GEN_INT (offset);
12568 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
12569 || (TARGET_E500_DOUBLE && mode == DFmode))
12571 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12572 emit_move_insn (offset_rtx, int_rtx);
12575 offset_rtx = int_rtx;
12577 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
12580 #ifndef TARGET_FIX_AND_CONTINUE
12581 #define TARGET_FIX_AND_CONTINUE 0
12584 /* Emit function prologue as insns. */
12587 rs6000_emit_prologue (void)
12589 rs6000_stack_t *info = rs6000_stack_info ();
12590 enum machine_mode reg_mode = Pmode;
12591 int reg_size = TARGET_32BIT ? 4 : 8;
12592 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12593 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
12594 rtx frame_reg_rtx = sp_reg_rtx;
12595 rtx cr_save_rtx = NULL_RTX;
12597 int saving_FPRs_inline;
12598 int using_store_multiple;
12599 HOST_WIDE_INT sp_offset = 0;
12601 if (TARGET_FIX_AND_CONTINUE)
12603 /* gdb on darwin arranges to forward a function from the old
12604 address by modifying the first 5 instructions of the function
12605 to branch to the overriding function. This is necessary to
12606 permit function pointers that point to the old function to
12607 actually forward to the new function. */
12608 emit_insn (gen_nop ());
12609 emit_insn (gen_nop ());
12610 emit_insn (gen_nop ());
12611 emit_insn (gen_nop ());
12612 emit_insn (gen_nop ());
12615 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12617 reg_mode = V2SImode;
12621 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
12622 && (!TARGET_SPE_ABI
12623 || info->spe_64bit_regs_used == 0)
12624 && info->first_gp_reg_save < 31);
12625 saving_FPRs_inline = (info->first_fp_reg_save == 64
12626 || FP_SAVE_INLINE (info->first_fp_reg_save)
12627 || current_function_calls_eh_return
12628 || cfun->machine->ra_need_lr);
12630 /* For V.4, update stack before we do any saving and set back pointer. */
12632 && (DEFAULT_ABI == ABI_V4
12633 || current_function_calls_eh_return))
12635 if (info->total_size < 32767)
12636 sp_offset = info->total_size;
12638 frame_reg_rtx = frame_ptr_rtx;
12639 rs6000_emit_allocate_stack (info->total_size,
12640 (frame_reg_rtx != sp_reg_rtx
12641 && (info->cr_save_p
12643 || info->first_fp_reg_save < 64
12644 || info->first_gp_reg_save < 32
12646 if (frame_reg_rtx != sp_reg_rtx)
12647 rs6000_emit_stack_tie ();
12650 /* Handle world saves specially here. */
12651 if (WORLD_SAVE_P (info))
12657 /* save_world expects lr in r0. */
12658 if (info->lr_save_p)
12660 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
12661 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12662 RTX_FRAME_RELATED_P (insn) = 1;
12665 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
12666 assumptions about the offsets of various bits of the stack
12667 frame. Abort if things aren't what they should be. */
12668 if (info->gp_save_offset != -220
12669 || info->fp_save_offset != -144
12670 || info->lr_save_offset != 8
12671 || info->cr_save_offset != 4
12673 || !info->lr_save_p
12674 || (current_function_calls_eh_return && info->ehrd_offset != -432)
12675 || (info->vrsave_save_offset != -224
12676 || info->altivec_save_offset != (-224 -16 -192)))
12679 treg = gen_rtx_REG (SImode, 11);
12680 emit_move_insn (treg, GEN_INT (-info->total_size));
12682 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
12683 in R11. It also clobbers R12, so beware! */
12685 /* Preserve CR2 for save_world prologues */
12687 sz += 32 - info->first_gp_reg_save;
12688 sz += 64 - info->first_fp_reg_save;
12689 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
12690 p = rtvec_alloc (sz);
12692 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
12693 gen_rtx_REG (Pmode,
12694 LINK_REGISTER_REGNUM));
12695 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
12696 gen_rtx_SYMBOL_REF (Pmode,
12698 /* We do floats first so that the instruction pattern matches
12700 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12702 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
12703 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12704 GEN_INT (info->fp_save_offset
12705 + sp_offset + 8 * i));
12706 rtx mem = gen_rtx_MEM (DFmode, addr);
12707 set_mem_alias_set (mem, rs6000_sr_alias_set);
12709 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12711 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
12713 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
12714 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12715 GEN_INT (info->altivec_save_offset
12716 + sp_offset + 16 * i));
12717 rtx mem = gen_rtx_MEM (V4SImode, addr);
12718 set_mem_alias_set (mem, rs6000_sr_alias_set);
12720 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12722 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12724 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12725 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12726 GEN_INT (info->gp_save_offset
12727 + sp_offset + reg_size * i));
12728 rtx mem = gen_rtx_MEM (reg_mode, addr);
12729 set_mem_alias_set (mem, rs6000_sr_alias_set);
12731 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12735 /* CR register traditionally saved as CR2. */
12736 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
12737 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12738 GEN_INT (info->cr_save_offset
12740 rtx mem = gen_rtx_MEM (reg_mode, addr);
12741 set_mem_alias_set (mem, rs6000_sr_alias_set);
12743 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12745 /* Prevent any attempt to delete the setting of r0 and treg! */
12746 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
12747 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
12748 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
12750 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12751 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12752 NULL_RTX, NULL_RTX);
12754 if (current_function_calls_eh_return)
12759 unsigned int regno = EH_RETURN_DATA_REGNO (i);
12760 if (regno == INVALID_REGNUM)
12762 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
12763 info->ehrd_offset + sp_offset
12764 + reg_size * (int) i,
12770 /* Save AltiVec registers if needed. */
12771 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
12775 /* There should be a non inline version of this, for when we
12776 are saving lots of vector registers. */
12777 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
12778 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12780 rtx areg, savereg, mem;
12783 offset = info->altivec_save_offset + sp_offset
12784 + 16 * (i - info->first_altivec_reg_save);
12786 savereg = gen_rtx_REG (V4SImode, i);
12788 areg = gen_rtx_REG (Pmode, 0);
12789 emit_move_insn (areg, GEN_INT (offset));
12791 /* AltiVec addressing mode is [reg+reg]. */
12792 mem = gen_rtx_MEM (V4SImode,
12793 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
12795 set_mem_alias_set (mem, rs6000_sr_alias_set);
12797 insn = emit_move_insn (mem, savereg);
12799 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12800 areg, GEN_INT (offset));
12804 /* VRSAVE is a bit vector representing which AltiVec registers
12805 are used. The OS uses this to determine which vector
12806 registers to save on a context switch. We need to save
12807 VRSAVE on the stack frame, add whatever AltiVec registers we
12808 used in this function, and do the corresponding magic in the
12811 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
12812 && !WORLD_SAVE_P (info) && info->vrsave_mask != 0)
12814 rtx reg, mem, vrsave;
12817 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
12818 as frame_reg_rtx and r11 as the static chain pointer for
12819 nested functions. */
12820 reg = gen_rtx_REG (SImode, 0);
12821 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
12823 emit_insn (gen_get_vrsave_internal (reg));
12825 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
12828 offset = info->vrsave_save_offset + sp_offset;
12830 = gen_rtx_MEM (SImode,
12831 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
12832 set_mem_alias_set (mem, rs6000_sr_alias_set);
12833 insn = emit_move_insn (mem, reg);
12835 /* Include the registers in the mask. */
12836 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
12838 insn = emit_insn (generate_set_vrsave (reg, info, 0));
12841 /* If we use the link register, get it into r0. */
12842 if (!WORLD_SAVE_P (info) && info->lr_save_p)
12844 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
12845 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12846 RTX_FRAME_RELATED_P (insn) = 1;
12849 /* If we need to save CR, put it into r12. */
12850 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
12854 cr_save_rtx = gen_rtx_REG (SImode, 12);
12855 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
12856 RTX_FRAME_RELATED_P (insn) = 1;
12857 /* Now, there's no way that dwarf2out_frame_debug_expr is going
12858 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
12859 But that's OK. All we have to do is specify that _one_ condition
12860 code register is saved in this stack slot. The thrower's epilogue
12861 will then restore all the call-saved registers.
12862 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
12863 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
12864 gen_rtx_REG (SImode, CR2_REGNO));
12865 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12870 /* Do any required saving of fpr's. If only one or two to save, do
12871 it ourselves. Otherwise, call function. */
12872 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
12875 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12876 if ((regs_ever_live[info->first_fp_reg_save+i]
12877 && ! call_used_regs[info->first_fp_reg_save+i]))
12878 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
12879 info->first_fp_reg_save + i,
12880 info->fp_save_offset + sp_offset + 8 * i,
12883 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
12887 const char *alloc_rname;
12889 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
12891 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
12892 gen_rtx_REG (Pmode,
12893 LINK_REGISTER_REGNUM));
12894 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
12895 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
12896 alloc_rname = ggc_strdup (rname);
12897 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
12898 gen_rtx_SYMBOL_REF (Pmode,
12900 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12902 rtx addr, reg, mem;
12903 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
12904 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12905 GEN_INT (info->fp_save_offset
12906 + sp_offset + 8*i));
12907 mem = gen_rtx_MEM (DFmode, addr);
12908 set_mem_alias_set (mem, rs6000_sr_alias_set);
12910 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
12912 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12913 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12914 NULL_RTX, NULL_RTX);
12917 /* Save GPRs. This is done as a PARALLEL if we are using
12918 the store-multiple instructions. */
12919 if (!WORLD_SAVE_P (info) && using_store_multiple)
12923 p = rtvec_alloc (32 - info->first_gp_reg_save);
12924 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12926 rtx addr, reg, mem;
12927 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12928 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12929 GEN_INT (info->gp_save_offset
12932 mem = gen_rtx_MEM (reg_mode, addr);
12933 set_mem_alias_set (mem, rs6000_sr_alias_set);
12935 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
12937 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12938 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12939 NULL_RTX, NULL_RTX);
12941 else if (!WORLD_SAVE_P (info))
12944 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12945 if ((regs_ever_live[info->first_gp_reg_save+i]
12946 && (! call_used_regs[info->first_gp_reg_save+i]
12947 || (i+info->first_gp_reg_save
12948 == RS6000_PIC_OFFSET_TABLE_REGNUM
12949 && TARGET_TOC && TARGET_MINIMAL_TOC)))
12950 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
12951 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12952 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
12954 rtx addr, reg, mem;
12955 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12957 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12959 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
12962 if (!SPE_CONST_OFFSET_OK (offset))
12964 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12965 emit_move_insn (b, GEN_INT (offset));
12968 b = GEN_INT (offset);
12970 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
12971 mem = gen_rtx_MEM (V2SImode, addr);
12972 set_mem_alias_set (mem, rs6000_sr_alias_set);
12973 insn = emit_move_insn (mem, reg);
12975 if (GET_CODE (b) == CONST_INT)
12976 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12977 NULL_RTX, NULL_RTX);
12979 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12980 b, GEN_INT (offset));
12984 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12985 GEN_INT (info->gp_save_offset
12988 mem = gen_rtx_MEM (reg_mode, addr);
12989 set_mem_alias_set (mem, rs6000_sr_alias_set);
12991 insn = emit_move_insn (mem, reg);
12992 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12993 NULL_RTX, NULL_RTX);
12998 /* ??? There's no need to emit actual instructions here, but it's the
12999 easiest way to get the frame unwind information emitted. */
13000 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
13002 unsigned int i, regno;
13004 /* In AIX ABI we need to pretend we save r2 here. */
13007 rtx addr, reg, mem;
13009 reg = gen_rtx_REG (reg_mode, 2);
13010 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13011 GEN_INT (sp_offset + 5 * reg_size));
13012 mem = gen_rtx_MEM (reg_mode, addr);
13013 set_mem_alias_set (mem, rs6000_sr_alias_set);
13015 insn = emit_move_insn (mem, reg);
13016 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13017 NULL_RTX, NULL_RTX);
13018 PATTERN (insn) = gen_blockage ();
13023 regno = EH_RETURN_DATA_REGNO (i);
13024 if (regno == INVALID_REGNUM)
13027 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13028 info->ehrd_offset + sp_offset
13029 + reg_size * (int) i,
13034 /* Save lr if we used it. */
13035 if (!WORLD_SAVE_P (info) && info->lr_save_p)
13037 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13038 GEN_INT (info->lr_save_offset + sp_offset));
13039 rtx reg = gen_rtx_REG (Pmode, 0);
13040 rtx mem = gen_rtx_MEM (Pmode, addr);
13041 /* This should not be of rs6000_sr_alias_set, because of
13042 __builtin_return_address. */
13044 insn = emit_move_insn (mem, reg);
13045 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13046 NULL_RTX, NULL_RTX);
13049 /* Save CR if we use any that must be preserved. */
13050 if (!WORLD_SAVE_P (info) && info->cr_save_p)
13052 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13053 GEN_INT (info->cr_save_offset + sp_offset));
13054 rtx mem = gen_rtx_MEM (SImode, addr);
13055 /* See the large comment above about why CR2_REGNO is used. */
13056 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
13058 set_mem_alias_set (mem, rs6000_sr_alias_set);
13060 /* If r12 was used to hold the original sp, copy cr into r0 now
13062 if (REGNO (frame_reg_rtx) == 12)
13066 cr_save_rtx = gen_rtx_REG (SImode, 0);
13067 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13068 RTX_FRAME_RELATED_P (insn) = 1;
13069 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
13070 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13075 insn = emit_move_insn (mem, cr_save_rtx);
13077 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13078 NULL_RTX, NULL_RTX);
13081 /* Update stack and set back pointer unless this is V.4,
13082 for which it was done previously. */
13083 if (!WORLD_SAVE_P (info) && info->push_p
13084 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
13085 rs6000_emit_allocate_stack (info->total_size, FALSE);
13087 /* Set frame pointer, if needed. */
13088 if (frame_pointer_needed)
13090 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
13092 RTX_FRAME_RELATED_P (insn) = 1;
13095 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
13096 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
13097 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
13098 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
13100 /* If emit_load_toc_table will use the link register, we need to save
13101 it. We use R12 for this purpose because emit_load_toc_table
13102 can use register 0. This allows us to use a plain 'blr' to return
13103 from the procedure more often. */
13104 int save_LR_around_toc_setup = (TARGET_ELF
13105 && DEFAULT_ABI != ABI_AIX
13107 && ! info->lr_save_p
13108 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
13109 if (save_LR_around_toc_setup)
13111 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13113 insn = emit_move_insn (frame_ptr_rtx, lr);
13114 rs6000_maybe_dead (insn);
13115 RTX_FRAME_RELATED_P (insn) = 1;
13117 rs6000_emit_load_toc_table (TRUE);
13119 insn = emit_move_insn (lr, frame_ptr_rtx);
13120 rs6000_maybe_dead (insn);
13121 RTX_FRAME_RELATED_P (insn) = 1;
13124 rs6000_emit_load_toc_table (TRUE);
13128 if (DEFAULT_ABI == ABI_DARWIN
13129 && flag_pic && current_function_uses_pic_offset_table)
13131 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13132 rtx src = machopic_function_base_sym ();
13134 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
13136 insn = emit_move_insn (gen_rtx_REG (Pmode,
13137 RS6000_PIC_OFFSET_TABLE_REGNUM),
13139 rs6000_maybe_dead (insn);
13144 /* Write function prologue. */
13147 rs6000_output_function_prologue (FILE *file,
13148 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13150 rs6000_stack_t *info = rs6000_stack_info ();
13152 if (TARGET_DEBUG_STACK)
13153 debug_stack_info (info);
13155 /* Write .extern for any function we will call to save and restore
13157 if (info->first_fp_reg_save < 64
13158 && !FP_SAVE_INLINE (info->first_fp_reg_save))
13159 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
13160 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
13161 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
13162 RESTORE_FP_SUFFIX);
13164 /* Write .extern for AIX common mode routines, if needed. */
13165 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
13167 fputs ("\t.extern __mulh\n", file);
13168 fputs ("\t.extern __mull\n", file);
13169 fputs ("\t.extern __divss\n", file);
13170 fputs ("\t.extern __divus\n", file);
13171 fputs ("\t.extern __quoss\n", file);
13172 fputs ("\t.extern __quous\n", file);
13173 common_mode_defined = 1;
13176 if (! HAVE_prologue)
13180 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
13181 the "toplevel" insn chain. */
13182 emit_note (NOTE_INSN_DELETED);
13183 rs6000_emit_prologue ();
13184 emit_note (NOTE_INSN_DELETED);
13186 /* Expand INSN_ADDRESSES so final() doesn't crash. */
13190 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13192 INSN_ADDRESSES_NEW (insn, addr);
13197 if (TARGET_DEBUG_STACK)
13198 debug_rtx_list (get_insns (), 100);
13199 final (get_insns (), file, FALSE);
13203 rs6000_pic_labelno++;
13206 /* Emit function epilogue as insns.
13208 At present, dwarf2out_frame_debug_expr doesn't understand
13209 register restores, so we don't bother setting RTX_FRAME_RELATED_P
13210 anywhere in the epilogue. Most of the insns below would in any case
13211 need special notes to explain where r11 is in relation to the stack. */
13214 rs6000_emit_epilogue (int sibcall)
13216 rs6000_stack_t *info;
13217 int restoring_FPRs_inline;
13218 int using_load_multiple;
13219 int using_mfcr_multiple;
13220 int use_backchain_to_restore_sp;
13222 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
13223 rtx frame_reg_rtx = sp_reg_rtx;
13224 enum machine_mode reg_mode = Pmode;
13225 int reg_size = TARGET_32BIT ? 4 : 8;
13228 info = rs6000_stack_info ();
13230 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13232 reg_mode = V2SImode;
13236 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
13237 && (!TARGET_SPE_ABI
13238 || info->spe_64bit_regs_used == 0)
13239 && info->first_gp_reg_save < 31);
13240 restoring_FPRs_inline = (sibcall
13241 || current_function_calls_eh_return
13242 || info->first_fp_reg_save == 64
13243 || FP_SAVE_INLINE (info->first_fp_reg_save));
13244 use_backchain_to_restore_sp = (frame_pointer_needed
13245 || current_function_calls_alloca
13246 || info->total_size > 32767);
13247 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
13248 || rs6000_cpu == PROCESSOR_PPC603
13249 || rs6000_cpu == PROCESSOR_PPC750
13252 if (WORLD_SAVE_P (info))
13256 const char *alloc_rname;
13259 /* eh_rest_world_r10 will return to the location saved in the LR
13260 stack slot (which is not likely to be our caller.)
13261 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
13262 rest_world is similar, except any R10 parameter is ignored.
13263 The exception-handling stuff that was here in 2.95 is no
13264 longer necessary. */
13268 + 32 - info->first_gp_reg_save
13269 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
13270 + 63 + 1 - info->first_fp_reg_save);
13272 strcpy (rname, ((current_function_calls_eh_return) ?
13273 "*eh_rest_world_r10" : "*rest_world"));
13274 alloc_rname = ggc_strdup (rname);
13277 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
13278 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
13279 gen_rtx_REG (Pmode,
13280 LINK_REGISTER_REGNUM));
13282 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
13283 /* The instruction pattern requires a clobber here;
13284 it is shared with the restVEC helper. */
13286 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
13289 /* CR register traditionally saved as CR2. */
13290 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13291 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13292 GEN_INT (info->cr_save_offset));
13293 rtx mem = gen_rtx_MEM (reg_mode, addr);
13294 set_mem_alias_set (mem, rs6000_sr_alias_set);
13296 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13299 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13301 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13302 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13303 GEN_INT (info->gp_save_offset
13305 rtx mem = gen_rtx_MEM (reg_mode, addr);
13306 set_mem_alias_set (mem, rs6000_sr_alias_set);
13308 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13310 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
13312 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13313 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13314 GEN_INT (info->altivec_save_offset
13316 rtx mem = gen_rtx_MEM (V4SImode, addr);
13317 set_mem_alias_set (mem, rs6000_sr_alias_set);
13319 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13321 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
13323 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13324 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13325 GEN_INT (info->fp_save_offset
13327 rtx mem = gen_rtx_MEM (DFmode, addr);
13328 set_mem_alias_set (mem, rs6000_sr_alias_set);
13330 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13333 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
13335 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
13337 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
13339 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
13341 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
13342 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
13347 /* If we have a frame pointer, a call to alloca, or a large stack
13348 frame, restore the old stack pointer using the backchain. Otherwise,
13349 we know what size to update it with. */
13350 if (use_backchain_to_restore_sp)
13352 /* Under V.4, don't reset the stack pointer until after we're done
13353 loading the saved registers. */
13354 if (DEFAULT_ABI == ABI_V4)
13355 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
13357 emit_move_insn (frame_reg_rtx,
13358 gen_rtx_MEM (Pmode, sp_reg_rtx));
13361 else if (info->push_p)
13363 if (DEFAULT_ABI == ABI_V4
13364 || current_function_calls_eh_return)
13365 sp_offset = info->total_size;
13368 emit_insn (TARGET_32BIT
13369 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
13370 GEN_INT (info->total_size))
13371 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
13372 GEN_INT (info->total_size)));
13376 /* Restore AltiVec registers if needed. */
13377 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
13381 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
13382 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13384 rtx addr, areg, mem;
13386 areg = gen_rtx_REG (Pmode, 0);
13388 (areg, GEN_INT (info->altivec_save_offset
13390 + 16 * (i - info->first_altivec_reg_save)));
13392 /* AltiVec addressing mode is [reg+reg]. */
13393 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
13394 mem = gen_rtx_MEM (V4SImode, addr);
13395 set_mem_alias_set (mem, rs6000_sr_alias_set);
13397 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
13401 /* Restore VRSAVE if needed. */
13402 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
13403 && info->vrsave_mask != 0)
13405 rtx addr, mem, reg;
13407 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13408 GEN_INT (info->vrsave_save_offset + sp_offset));
13409 mem = gen_rtx_MEM (SImode, addr);
13410 set_mem_alias_set (mem, rs6000_sr_alias_set);
13411 reg = gen_rtx_REG (SImode, 12);
13412 emit_move_insn (reg, mem);
13414 emit_insn (generate_set_vrsave (reg, info, 1));
13417 /* Get the old lr if we saved it. */
13418 if (info->lr_save_p)
13420 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
13421 info->lr_save_offset + sp_offset);
13423 set_mem_alias_set (mem, rs6000_sr_alias_set);
13425 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
13428 /* Get the old cr if we saved it. */
13429 if (info->cr_save_p)
13431 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13432 GEN_INT (info->cr_save_offset + sp_offset));
13433 rtx mem = gen_rtx_MEM (SImode, addr);
13435 set_mem_alias_set (mem, rs6000_sr_alias_set);
13437 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
13440 /* Set LR here to try to overlap restores below. */
13441 if (info->lr_save_p)
13442 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
13443 gen_rtx_REG (Pmode, 0));
13445 /* Load exception handler data registers, if needed. */
13446 if (current_function_calls_eh_return)
13448 unsigned int i, regno;
13452 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13453 GEN_INT (sp_offset + 5 * reg_size));
13454 rtx mem = gen_rtx_MEM (reg_mode, addr);
13456 set_mem_alias_set (mem, rs6000_sr_alias_set);
13458 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
13465 regno = EH_RETURN_DATA_REGNO (i);
13466 if (regno == INVALID_REGNUM)
13469 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
13470 info->ehrd_offset + sp_offset
13471 + reg_size * (int) i);
13472 set_mem_alias_set (mem, rs6000_sr_alias_set);
13474 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
13478 /* Restore GPRs. This is done as a PARALLEL if we are using
13479 the load-multiple instructions. */
13480 if (using_load_multiple)
13483 p = rtvec_alloc (32 - info->first_gp_reg_save);
13484 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13486 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13487 GEN_INT (info->gp_save_offset
13490 rtx mem = gen_rtx_MEM (reg_mode, addr);
13492 set_mem_alias_set (mem, rs6000_sr_alias_set);
13495 gen_rtx_SET (VOIDmode,
13496 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
13499 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13502 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13503 if ((regs_ever_live[info->first_gp_reg_save+i]
13504 && (! call_used_regs[info->first_gp_reg_save+i]
13505 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
13506 && TARGET_TOC && TARGET_MINIMAL_TOC)))
13507 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
13508 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13509 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
13511 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13512 GEN_INT (info->gp_save_offset
13515 rtx mem = gen_rtx_MEM (reg_mode, addr);
13517 /* Restore 64-bit quantities for SPE. */
13518 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13520 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
13523 if (!SPE_CONST_OFFSET_OK (offset))
13525 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13526 emit_move_insn (b, GEN_INT (offset));
13529 b = GEN_INT (offset);
13531 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
13532 mem = gen_rtx_MEM (V2SImode, addr);
13535 set_mem_alias_set (mem, rs6000_sr_alias_set);
13537 emit_move_insn (gen_rtx_REG (reg_mode,
13538 info->first_gp_reg_save + i), mem);
13541 /* Restore fpr's if we need to do it without calling a function. */
13542 if (restoring_FPRs_inline)
13543 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13544 if ((regs_ever_live[info->first_fp_reg_save+i]
13545 && ! call_used_regs[info->first_fp_reg_save+i]))
13548 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13549 GEN_INT (info->fp_save_offset
13552 mem = gen_rtx_MEM (DFmode, addr);
13553 set_mem_alias_set (mem, rs6000_sr_alias_set);
13555 emit_move_insn (gen_rtx_REG (DFmode,
13556 info->first_fp_reg_save + i),
13560 /* If we saved cr, restore it here. Just those that were used. */
13561 if (info->cr_save_p)
13563 rtx r12_rtx = gen_rtx_REG (SImode, 12);
13566 if (using_mfcr_multiple)
13568 for (i = 0; i < 8; i++)
13569 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
13575 if (using_mfcr_multiple && count > 1)
13580 p = rtvec_alloc (count);
13583 for (i = 0; i < 8; i++)
13584 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
13586 rtvec r = rtvec_alloc (2);
13587 RTVEC_ELT (r, 0) = r12_rtx;
13588 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
13589 RTVEC_ELT (p, ndx) =
13590 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
13591 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
13594 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13599 for (i = 0; i < 8; i++)
13600 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
13602 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
13608 /* If this is V.4, unwind the stack pointer after all of the loads
13609 have been done. We need to emit a block here so that sched
13610 doesn't decide to move the sp change before the register restores
13611 (which may not have any obvious dependency on the stack). This
13612 doesn't hurt performance, because there is no scheduling that can
13613 be done after this point. */
13614 if (DEFAULT_ABI == ABI_V4
13615 || current_function_calls_eh_return)
13617 if (frame_reg_rtx != sp_reg_rtx)
13618 rs6000_emit_stack_tie ();
13620 if (use_backchain_to_restore_sp)
13622 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
13624 else if (sp_offset != 0)
13626 emit_insn (TARGET_32BIT
13627 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
13628 GEN_INT (sp_offset))
13629 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
13630 GEN_INT (sp_offset)));
13634 if (current_function_calls_eh_return)
13636 rtx sa = EH_RETURN_STACKADJ_RTX;
13637 emit_insn (TARGET_32BIT
13638 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
13639 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
13645 if (! restoring_FPRs_inline)
13646 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
13648 p = rtvec_alloc (2);
13650 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
13651 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
13652 gen_rtx_REG (Pmode,
13653 LINK_REGISTER_REGNUM));
13655 /* If we have to restore more than two FP registers, branch to the
13656 restore function. It will return to our caller. */
13657 if (! restoring_FPRs_inline)
13661 const char *alloc_rname;
13663 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
13664 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
13665 alloc_rname = ggc_strdup (rname);
13666 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
13667 gen_rtx_SYMBOL_REF (Pmode,
13670 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13673 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
13674 GEN_INT (info->fp_save_offset + 8*i));
13675 mem = gen_rtx_MEM (DFmode, addr);
13676 set_mem_alias_set (mem, rs6000_sr_alias_set);
13678 RTVEC_ELT (p, i+3) =
13679 gen_rtx_SET (VOIDmode,
13680 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
13685 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
13689 /* Write function epilogue. */
13692 rs6000_output_function_epilogue (FILE *file,
13693 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13695 rs6000_stack_t *info = rs6000_stack_info ();
13697 if (! HAVE_epilogue)
13699 rtx insn = get_last_insn ();
13700 /* If the last insn was a BARRIER, we don't have to write anything except
13701 the trace table. */
13702 if (GET_CODE (insn) == NOTE)
13703 insn = prev_nonnote_insn (insn);
13704 if (insn == 0 || GET_CODE (insn) != BARRIER)
13706 /* This is slightly ugly, but at least we don't have two
13707 copies of the epilogue-emitting code. */
13710 /* A NOTE_INSN_DELETED is supposed to be at the start
13711 and end of the "toplevel" insn chain. */
13712 emit_note (NOTE_INSN_DELETED);
13713 rs6000_emit_epilogue (FALSE);
13714 emit_note (NOTE_INSN_DELETED);
13716 /* Expand INSN_ADDRESSES so final() doesn't crash. */
13720 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13722 INSN_ADDRESSES_NEW (insn, addr);
13727 if (TARGET_DEBUG_STACK)
13728 debug_rtx_list (get_insns (), 100);
13729 final (get_insns (), file, FALSE);
13735 macho_branch_islands ();
13736 /* Mach-O doesn't support labels at the end of objects, so if
13737 it looks like we might want one, insert a NOP. */
13739 rtx insn = get_last_insn ();
13742 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
13743 insn = PREV_INSN (insn);
13747 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
13748 fputs ("\tnop\n", file);
13752 /* Output a traceback table here. See /usr/include/sys/debug.h for info
13755 We don't output a traceback table if -finhibit-size-directive was
13756 used. The documentation for -finhibit-size-directive reads
13757 ``don't output a @code{.size} assembler directive, or anything
13758 else that would cause trouble if the function is split in the
13759 middle, and the two halves are placed at locations far apart in
13760 memory.'' The traceback table has this property, since it
13761 includes the offset from the start of the function to the
13762 traceback table itself.
13764 System V.4 Powerpc's (and the embedded ABI derived from it) use a
13765 different traceback table. */
13766 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
13767 && rs6000_traceback != traceback_none)
13769 const char *fname = NULL;
13770 const char *language_string = lang_hooks.name;
13771 int fixed_parms = 0, float_parms = 0, parm_info = 0;
13773 int optional_tbtab;
13775 if (rs6000_traceback == traceback_full)
13776 optional_tbtab = 1;
13777 else if (rs6000_traceback == traceback_part)
13778 optional_tbtab = 0;
13780 optional_tbtab = !optimize_size && !TARGET_ELF;
13782 if (optional_tbtab)
13784 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13785 while (*fname == '.') /* V.4 encodes . in the name */
13788 /* Need label immediately before tbtab, so we can compute
13789 its offset from the function start. */
13790 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
13791 ASM_OUTPUT_LABEL (file, fname);
13794 /* The .tbtab pseudo-op can only be used for the first eight
13795 expressions, since it can't handle the possibly variable
13796 length fields that follow. However, if you omit the optional
13797 fields, the assembler outputs zeros for all optional fields
13798 anyways, giving each variable length field is minimum length
13799 (as defined in sys/debug.h). Thus we can not use the .tbtab
13800 pseudo-op at all. */
13802 /* An all-zero word flags the start of the tbtab, for debuggers
13803 that have to find it by searching forward from the entry
13804 point or from the current pc. */
13805 fputs ("\t.long 0\n", file);
13807 /* Tbtab format type. Use format type 0. */
13808 fputs ("\t.byte 0,", file);
13810 /* Language type. Unfortunately, there does not seem to be any
13811 official way to discover the language being compiled, so we
13812 use language_string.
13813 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
13814 Java is 13. Objective-C is 14. */
13815 if (! strcmp (language_string, "GNU C"))
13817 else if (! strcmp (language_string, "GNU F77")
13818 || ! strcmp (language_string, "GNU F95"))
13820 else if (! strcmp (language_string, "GNU Pascal"))
13822 else if (! strcmp (language_string, "GNU Ada"))
13824 else if (! strcmp (language_string, "GNU C++"))
13826 else if (! strcmp (language_string, "GNU Java"))
13828 else if (! strcmp (language_string, "GNU Objective-C"))
13832 fprintf (file, "%d,", i);
13834 /* 8 single bit fields: global linkage (not set for C extern linkage,
13835 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
13836 from start of procedure stored in tbtab, internal function, function
13837 has controlled storage, function has no toc, function uses fp,
13838 function logs/aborts fp operations. */
13839 /* Assume that fp operations are used if any fp reg must be saved. */
13840 fprintf (file, "%d,",
13841 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
13843 /* 6 bitfields: function is interrupt handler, name present in
13844 proc table, function calls alloca, on condition directives
13845 (controls stack walks, 3 bits), saves condition reg, saves
13847 /* The `function calls alloca' bit seems to be set whenever reg 31 is
13848 set up as a frame pointer, even when there is no alloca call. */
13849 fprintf (file, "%d,",
13850 ((optional_tbtab << 6)
13851 | ((optional_tbtab & frame_pointer_needed) << 5)
13852 | (info->cr_save_p << 1)
13853 | (info->lr_save_p)));
13855 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
13857 fprintf (file, "%d,",
13858 (info->push_p << 7) | (64 - info->first_fp_reg_save));
13860 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
13861 fprintf (file, "%d,", (32 - first_reg_to_save ()));
13863 if (optional_tbtab)
13865 /* Compute the parameter info from the function decl argument
13868 int next_parm_info_bit = 31;
13870 for (decl = DECL_ARGUMENTS (current_function_decl);
13871 decl; decl = TREE_CHAIN (decl))
13873 rtx parameter = DECL_INCOMING_RTL (decl);
13874 enum machine_mode mode = GET_MODE (parameter);
13876 if (GET_CODE (parameter) == REG)
13878 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
13884 if (mode == SFmode)
13886 else if (mode == DFmode || mode == TFmode)
13891 /* If only one bit will fit, don't or in this entry. */
13892 if (next_parm_info_bit > 0)
13893 parm_info |= (bits << (next_parm_info_bit - 1));
13894 next_parm_info_bit -= 2;
13898 fixed_parms += ((GET_MODE_SIZE (mode)
13899 + (UNITS_PER_WORD - 1))
13901 next_parm_info_bit -= 1;
13907 /* Number of fixed point parameters. */
13908 /* This is actually the number of words of fixed point parameters; thus
13909 an 8 byte struct counts as 2; and thus the maximum value is 8. */
13910 fprintf (file, "%d,", fixed_parms);
13912 /* 2 bitfields: number of floating point parameters (7 bits), parameters
13914 /* This is actually the number of fp registers that hold parameters;
13915 and thus the maximum value is 13. */
13916 /* Set parameters on stack bit if parameters are not in their original
13917 registers, regardless of whether they are on the stack? Xlc
13918 seems to set the bit when not optimizing. */
13919 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
13921 if (! optional_tbtab)
13924 /* Optional fields follow. Some are variable length. */
13926 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
13927 11 double float. */
13928 /* There is an entry for each parameter in a register, in the order that
13929 they occur in the parameter list. Any intervening arguments on the
13930 stack are ignored. If the list overflows a long (max possible length
13931 34 bits) then completely leave off all elements that don't fit. */
13932 /* Only emit this long if there was at least one parameter. */
13933 if (fixed_parms || float_parms)
13934 fprintf (file, "\t.long %d\n", parm_info);
13936 /* Offset from start of code to tb table. */
13937 fputs ("\t.long ", file);
13938 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
13940 RS6000_OUTPUT_BASENAME (file, fname);
13942 assemble_name (file, fname);
13944 rs6000_output_function_entry (file, fname);
13947 /* Interrupt handler mask. */
13948 /* Omit this long, since we never set the interrupt handler bit
13951 /* Number of CTL (controlled storage) anchors. */
13952 /* Omit this long, since the has_ctl bit is never set above. */
13954 /* Displacement into stack of each CTL anchor. */
13955 /* Omit this list of longs, because there are no CTL anchors. */
13957 /* Length of function name. */
13960 fprintf (file, "\t.short %d\n", (int) strlen (fname));
13962 /* Function name. */
13963 assemble_string (fname, strlen (fname));
13965 /* Register for alloca automatic storage; this is always reg 31.
13966 Only emit this if the alloca bit was set above. */
13967 if (frame_pointer_needed)
13968 fputs ("\t.byte 31\n", file);
13970 fputs ("\t.align 2\n", file);
13974 /* A C compound statement that outputs the assembler code for a thunk
13975 function, used to implement C++ virtual function calls with
13976 multiple inheritance. The thunk acts as a wrapper around a virtual
13977 function, adjusting the implicit object parameter before handing
13978 control off to the real function.
13980 First, emit code to add the integer DELTA to the location that
13981 contains the incoming first argument. Assume that this argument
13982 contains a pointer, and is the one used to pass the `this' pointer
13983 in C++. This is the incoming argument *before* the function
13984 prologue, e.g. `%o0' on a sparc. The addition must preserve the
13985 values of all other incoming arguments.
13987 After the addition, emit code to jump to FUNCTION, which is a
13988 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
13989 not touch the return address. Hence returning from FUNCTION will
13990 return to whoever called the current `thunk'.
13992 The effect must be as if FUNCTION had been called directly with the
13993 adjusted first argument. This macro is responsible for emitting
13994 all of the code for a thunk function; output_function_prologue()
13995 and output_function_epilogue() are not invoked.
13997 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
13998 been extracted from it.) It might possibly be useful on some
13999 targets, but probably not.
14001 If you do not define this macro, the target-independent code in the
14002 C++ frontend will generate a less efficient heavyweight thunk that
14003 calls FUNCTION instead of jumping to it. The generic approach does
14004 not support varargs. */
14007 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
14008 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
14011 rtx this, insn, funexp;
14013 reload_completed = 1;
14014 epilogue_completed = 1;
14015 no_new_pseudos = 1;
14016 reset_block_changes ();
14018 /* Mark the end of the (empty) prologue. */
14019 emit_note (NOTE_INSN_PROLOGUE_END);
14021 /* Find the "this" pointer. If the function returns a structure,
14022 the structure return pointer is in r3. */
14023 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
14024 this = gen_rtx_REG (Pmode, 4);
14026 this = gen_rtx_REG (Pmode, 3);
14028 /* Apply the constant offset, if required. */
14031 rtx delta_rtx = GEN_INT (delta);
14032 emit_insn (TARGET_32BIT
14033 ? gen_addsi3 (this, this, delta_rtx)
14034 : gen_adddi3 (this, this, delta_rtx));
14037 /* Apply the offset from the vtable, if required. */
14040 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
14041 rtx tmp = gen_rtx_REG (Pmode, 12);
14043 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
14044 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
14046 emit_insn (TARGET_32BIT
14047 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
14048 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
14049 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
14053 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
14055 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
14057 emit_insn (TARGET_32BIT
14058 ? gen_addsi3 (this, this, tmp)
14059 : gen_adddi3 (this, this, tmp));
14062 /* Generate a tail call to the target function. */
14063 if (!TREE_USED (function))
14065 assemble_external (function);
14066 TREE_USED (function) = 1;
14068 funexp = XEXP (DECL_RTL (function), 0);
14069 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
14072 if (MACHOPIC_INDIRECT)
14073 funexp = machopic_indirect_call_target (funexp);
14076 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
14077 generate sibcall RTL explicitly to avoid constraint abort. */
14078 insn = emit_call_insn (
14079 gen_rtx_PARALLEL (VOIDmode,
14081 gen_rtx_CALL (VOIDmode,
14082 funexp, const0_rtx),
14083 gen_rtx_USE (VOIDmode, const0_rtx),
14084 gen_rtx_USE (VOIDmode,
14085 gen_rtx_REG (SImode,
14086 LINK_REGISTER_REGNUM)),
14087 gen_rtx_RETURN (VOIDmode))));
14088 SIBLING_CALL_P (insn) = 1;
14091 /* Run just enough of rest_of_compilation to get the insns emitted.
14092 There's not really enough bulk here to make other passes such as
14093 instruction scheduling worth while. Note that use_thunk calls
14094 assemble_start_function and assemble_end_function. */
14095 insn = get_insns ();
14096 insn_locators_initialize ();
14097 shorten_branches (insn);
14098 final_start_function (insn, file, 1);
14099 final (insn, file, 1);
14100 final_end_function ();
14102 reload_completed = 0;
14103 epilogue_completed = 0;
14104 no_new_pseudos = 0;
14107 /* A quick summary of the various types of 'constant-pool tables'
14110 Target Flags Name One table per
14111 AIX (none) AIX TOC object file
14112 AIX -mfull-toc AIX TOC object file
14113 AIX -mminimal-toc AIX minimal TOC translation unit
14114 SVR4/EABI (none) SVR4 SDATA object file
14115 SVR4/EABI -fpic SVR4 pic object file
14116 SVR4/EABI -fPIC SVR4 PIC translation unit
14117 SVR4/EABI -mrelocatable EABI TOC function
14118 SVR4/EABI -maix AIX TOC object file
14119 SVR4/EABI -maix -mminimal-toc
14120 AIX minimal TOC translation unit
14122 Name Reg. Set by entries contains:
14123 made by addrs? fp? sum?
14125 AIX TOC 2 crt0 as Y option option
14126 AIX minimal TOC 30 prolog gcc Y Y option
14127 SVR4 SDATA 13 crt0 gcc N Y N
14128 SVR4 pic 30 prolog ld Y not yet N
14129 SVR4 PIC 30 prolog gcc Y option option
14130 EABI TOC 30 prolog gcc Y option option
14134 /* Hash functions for the hash table. */
14137 rs6000_hash_constant (rtx k)
14139 enum rtx_code code = GET_CODE (k);
14140 enum machine_mode mode = GET_MODE (k);
14141 unsigned result = (code << 3) ^ mode;
14142 const char *format;
14145 format = GET_RTX_FORMAT (code);
14146 flen = strlen (format);
14152 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
14155 if (mode != VOIDmode)
14156 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
14168 for (; fidx < flen; fidx++)
14169 switch (format[fidx])
14174 const char *str = XSTR (k, fidx);
14175 len = strlen (str);
14176 result = result * 613 + len;
14177 for (i = 0; i < len; i++)
14178 result = result * 613 + (unsigned) str[i];
14183 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
14187 result = result * 613 + (unsigned) XINT (k, fidx);
14190 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
14191 result = result * 613 + (unsigned) XWINT (k, fidx);
14195 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
14196 result = result * 613 + (unsigned) (XWINT (k, fidx)
14210 toc_hash_function (const void *hash_entry)
14212 const struct toc_hash_struct *thc =
14213 (const struct toc_hash_struct *) hash_entry;
14214 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
14217 /* Compare H1 and H2 for equivalence. */
14220 toc_hash_eq (const void *h1, const void *h2)
14222 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
14223 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
14225 if (((const struct toc_hash_struct *) h1)->key_mode
14226 != ((const struct toc_hash_struct *) h2)->key_mode)
14229 return rtx_equal_p (r1, r2);
14232 /* These are the names given by the C++ front-end to vtables, and
14233 vtable-like objects. Ideally, this logic should not be here;
14234 instead, there should be some programmatic way of inquiring as
14235 to whether or not an object is a vtable. */
14237 #define VTABLE_NAME_P(NAME) \
14238 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
14239 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
14240 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
14241 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
14242 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
14245 rs6000_output_symbol_ref (FILE *file, rtx x)
14247 /* Currently C++ toc references to vtables can be emitted before it
14248 is decided whether the vtable is public or private. If this is
14249 the case, then the linker will eventually complain that there is
14250 a reference to an unknown section. Thus, for vtables only,
14251 we emit the TOC reference to reference the symbol and not the
14253 const char *name = XSTR (x, 0);
14255 if (VTABLE_NAME_P (name))
14257 RS6000_OUTPUT_BASENAME (file, name);
14260 assemble_name (file, name);
14263 /* Output a TOC entry. We derive the entry name from what is being
14267 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
14270 const char *name = buf;
14271 const char *real_name;
14278 /* When the linker won't eliminate them, don't output duplicate
14279 TOC entries (this happens on AIX if there is any kind of TOC,
14280 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
14282 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
14284 struct toc_hash_struct *h;
14287 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
14288 time because GGC is not initialized at that point. */
14289 if (toc_hash_table == NULL)
14290 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
14291 toc_hash_eq, NULL);
14293 h = ggc_alloc (sizeof (*h));
14295 h->key_mode = mode;
14296 h->labelno = labelno;
14298 found = htab_find_slot (toc_hash_table, h, 1);
14299 if (*found == NULL)
14301 else /* This is indeed a duplicate.
14302 Set this label equal to that label. */
14304 fputs ("\t.set ", file);
14305 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
14306 fprintf (file, "%d,", labelno);
14307 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
14308 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
14314 /* If we're going to put a double constant in the TOC, make sure it's
14315 aligned properly when strict alignment is on. */
14316 if (GET_CODE (x) == CONST_DOUBLE
14317 && STRICT_ALIGNMENT
14318 && GET_MODE_BITSIZE (mode) >= 64
14319 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
14320 ASM_OUTPUT_ALIGN (file, 3);
14323 (*targetm.asm_out.internal_label) (file, "LC", labelno);
14325 /* Handle FP constants specially. Note that if we have a minimal
14326 TOC, things we put here aren't actually in the TOC, so we can allow
14328 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
14330 REAL_VALUE_TYPE rv;
14333 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14334 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
14338 if (TARGET_MINIMAL_TOC)
14339 fputs (DOUBLE_INT_ASM_OP, file);
14341 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14342 k[0] & 0xffffffff, k[1] & 0xffffffff,
14343 k[2] & 0xffffffff, k[3] & 0xffffffff);
14344 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
14345 k[0] & 0xffffffff, k[1] & 0xffffffff,
14346 k[2] & 0xffffffff, k[3] & 0xffffffff);
14351 if (TARGET_MINIMAL_TOC)
14352 fputs ("\t.long ", file);
14354 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14355 k[0] & 0xffffffff, k[1] & 0xffffffff,
14356 k[2] & 0xffffffff, k[3] & 0xffffffff);
14357 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
14358 k[0] & 0xffffffff, k[1] & 0xffffffff,
14359 k[2] & 0xffffffff, k[3] & 0xffffffff);
14363 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
14365 REAL_VALUE_TYPE rv;
14368 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14369 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
14373 if (TARGET_MINIMAL_TOC)
14374 fputs (DOUBLE_INT_ASM_OP, file);
14376 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
14377 k[0] & 0xffffffff, k[1] & 0xffffffff);
14378 fprintf (file, "0x%lx%08lx\n",
14379 k[0] & 0xffffffff, k[1] & 0xffffffff);
14384 if (TARGET_MINIMAL_TOC)
14385 fputs ("\t.long ", file);
14387 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
14388 k[0] & 0xffffffff, k[1] & 0xffffffff);
14389 fprintf (file, "0x%lx,0x%lx\n",
14390 k[0] & 0xffffffff, k[1] & 0xffffffff);
14394 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
14396 REAL_VALUE_TYPE rv;
14399 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14400 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
14404 if (TARGET_MINIMAL_TOC)
14405 fputs (DOUBLE_INT_ASM_OP, file);
14407 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
14408 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
14413 if (TARGET_MINIMAL_TOC)
14414 fputs ("\t.long ", file);
14416 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
14417 fprintf (file, "0x%lx\n", l & 0xffffffff);
14421 else if (GET_MODE (x) == VOIDmode
14422 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
14424 unsigned HOST_WIDE_INT low;
14425 HOST_WIDE_INT high;
14427 if (GET_CODE (x) == CONST_DOUBLE)
14429 low = CONST_DOUBLE_LOW (x);
14430 high = CONST_DOUBLE_HIGH (x);
14433 #if HOST_BITS_PER_WIDE_INT == 32
14436 high = (low & 0x80000000) ? ~0 : 0;
14440 low = INTVAL (x) & 0xffffffff;
14441 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
14445 /* TOC entries are always Pmode-sized, but since this
14446 is a bigendian machine then if we're putting smaller
14447 integer constants in the TOC we have to pad them.
14448 (This is still a win over putting the constants in
14449 a separate constant pool, because then we'd have
14450 to have both a TOC entry _and_ the actual constant.)
14452 For a 32-bit target, CONST_INT values are loaded and shifted
14453 entirely within `low' and can be stored in one TOC entry. */
14455 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
14456 abort ();/* It would be easy to make this work, but it doesn't now. */
14458 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
14460 #if HOST_BITS_PER_WIDE_INT == 32
14461 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
14462 POINTER_SIZE, &low, &high, 0);
14465 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
14466 high = (HOST_WIDE_INT) low >> 32;
14473 if (TARGET_MINIMAL_TOC)
14474 fputs (DOUBLE_INT_ASM_OP, file);
14476 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
14477 (long) high & 0xffffffff, (long) low & 0xffffffff);
14478 fprintf (file, "0x%lx%08lx\n",
14479 (long) high & 0xffffffff, (long) low & 0xffffffff);
14484 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
14486 if (TARGET_MINIMAL_TOC)
14487 fputs ("\t.long ", file);
14489 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
14490 (long) high & 0xffffffff, (long) low & 0xffffffff);
14491 fprintf (file, "0x%lx,0x%lx\n",
14492 (long) high & 0xffffffff, (long) low & 0xffffffff);
14496 if (TARGET_MINIMAL_TOC)
14497 fputs ("\t.long ", file);
14499 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
14500 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
14506 if (GET_CODE (x) == CONST)
14508 if (GET_CODE (XEXP (x, 0)) != PLUS)
14511 base = XEXP (XEXP (x, 0), 0);
14512 offset = INTVAL (XEXP (XEXP (x, 0), 1));
14515 if (GET_CODE (base) == SYMBOL_REF)
14516 name = XSTR (base, 0);
14517 else if (GET_CODE (base) == LABEL_REF)
14518 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
14519 else if (GET_CODE (base) == CODE_LABEL)
14520 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
14524 real_name = (*targetm.strip_name_encoding) (name);
14525 if (TARGET_MINIMAL_TOC)
14526 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
14529 fprintf (file, "\t.tc %s", real_name);
14532 fprintf (file, ".N%d", - offset);
14534 fprintf (file, ".P%d", offset);
14536 fputs ("[TC],", file);
14539 /* Currently C++ toc references to vtables can be emitted before it
14540 is decided whether the vtable is public or private. If this is
14541 the case, then the linker will eventually complain that there is
14542 a TOC reference to an unknown section. Thus, for vtables only,
14543 we emit the TOC reference to reference the symbol and not the
14545 if (VTABLE_NAME_P (name))
14547 RS6000_OUTPUT_BASENAME (file, name);
14549 fprintf (file, "%d", offset);
14550 else if (offset > 0)
14551 fprintf (file, "+%d", offset);
14554 output_addr_const (file, x);
14558 /* Output an assembler pseudo-op to write an ASCII string of N characters
14559 starting at P to FILE.
14561 On the RS/6000, we have to do this using the .byte operation and
14562 write out special characters outside the quoted string.
14563 Also, the assembler is broken; very long strings are truncated,
14564 so we must artificially break them up early. */
14567 output_ascii (FILE *file, const char *p, int n)
14570 int i, count_string;
14571 const char *for_string = "\t.byte \"";
14572 const char *for_decimal = "\t.byte ";
14573 const char *to_close = NULL;
14576 for (i = 0; i < n; i++)
14579 if (c >= ' ' && c < 0177)
14582 fputs (for_string, file);
14585 /* Write two quotes to get one. */
14593 for_decimal = "\"\n\t.byte ";
14597 if (count_string >= 512)
14599 fputs (to_close, file);
14601 for_string = "\t.byte \"";
14602 for_decimal = "\t.byte ";
14610 fputs (for_decimal, file);
14611 fprintf (file, "%d", c);
14613 for_string = "\n\t.byte \"";
14614 for_decimal = ", ";
14620 /* Now close the string if we have written one. Then end the line. */
14622 fputs (to_close, file);
14625 /* Generate a unique section name for FILENAME for a section type
14626 represented by SECTION_DESC. Output goes into BUF.
14628 SECTION_DESC can be any string, as long as it is different for each
14629 possible section type.
14631 We name the section in the same manner as xlc. The name begins with an
14632 underscore followed by the filename (after stripping any leading directory
14633 names) with the last period replaced by the string SECTION_DESC. If
14634 FILENAME does not contain a period, SECTION_DESC is appended to the end of
14638 rs6000_gen_section_name (char **buf, const char *filename,
14639 const char *section_desc)
14641 const char *q, *after_last_slash, *last_period = 0;
14645 after_last_slash = filename;
14646 for (q = filename; *q; q++)
14649 after_last_slash = q + 1;
14650 else if (*q == '.')
14654 len = strlen (after_last_slash) + strlen (section_desc) + 2;
14655 *buf = (char *) xmalloc (len);
14660 for (q = after_last_slash; *q; q++)
14662 if (q == last_period)
14664 strcpy (p, section_desc);
14665 p += strlen (section_desc);
14669 else if (ISALNUM (*q))
14673 if (last_period == 0)
14674 strcpy (p, section_desc);
14679 /* Emit profile function. */
14682 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
14684 if (TARGET_PROFILE_KERNEL)
14687 if (DEFAULT_ABI == ABI_AIX)
14689 #ifndef NO_PROFILE_COUNTERS
14690 # define NO_PROFILE_COUNTERS 0
14692 if (NO_PROFILE_COUNTERS)
14693 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
14697 const char *label_name;
14700 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
14701 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
14702 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
14704 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
14708 else if (DEFAULT_ABI == ABI_DARWIN)
14710 const char *mcount_name = RS6000_MCOUNT;
14711 int caller_addr_regno = LINK_REGISTER_REGNUM;
14713 /* Be conservative and always set this, at least for now. */
14714 current_function_uses_pic_offset_table = 1;
14717 /* For PIC code, set up a stub and collect the caller's address
14718 from r0, which is where the prologue puts it. */
14719 if (MACHOPIC_INDIRECT
14720 && current_function_uses_pic_offset_table)
14721 caller_addr_regno = 0;
14723 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
14725 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
14729 /* Write function profiler code. */
14732 output_function_profiler (FILE *file, int labelno)
14737 switch (DEFAULT_ABI)
14746 warning ("no profiling of 64-bit code for this ABI");
14749 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
14750 fprintf (file, "\tmflr %s\n", reg_names[0]);
14753 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
14754 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
14755 reg_names[0], save_lr, reg_names[1]);
14756 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
14757 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
14758 assemble_name (file, buf);
14759 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
14761 else if (flag_pic > 1)
14763 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
14764 reg_names[0], save_lr, reg_names[1]);
14765 /* Now, we need to get the address of the label. */
14766 fputs ("\tbl 1f\n\t.long ", file);
14767 assemble_name (file, buf);
14768 fputs ("-.\n1:", file);
14769 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
14770 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
14771 reg_names[0], reg_names[11]);
14772 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
14773 reg_names[0], reg_names[0], reg_names[11]);
14777 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
14778 assemble_name (file, buf);
14779 fputs ("@ha\n", file);
14780 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
14781 reg_names[0], save_lr, reg_names[1]);
14782 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
14783 assemble_name (file, buf);
14784 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
14787 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
14788 fprintf (file, "\tbl %s%s\n",
14789 RS6000_MCOUNT, flag_pic ? "@plt" : "");
14794 if (!TARGET_PROFILE_KERNEL)
14796 /* Don't do anything, done in output_profile_hook (). */
14803 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
14804 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
14806 if (cfun->static_chain_decl != NULL)
14808 asm_fprintf (file, "\tstd %s,24(%s)\n",
14809 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
14810 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
14811 asm_fprintf (file, "\tld %s,24(%s)\n",
14812 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
14815 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
14822 /* Power4 load update and store update instructions are cracked into a
14823 load or store and an integer insn which are executed in the same cycle.
14824 Branches have their own dispatch slot which does not count against the
14825 GCC issue rate, but it changes the program flow so there are no other
14826 instructions to issue in this cycle. */
14829 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
14830 int verbose ATTRIBUTE_UNUSED,
14831 rtx insn, int more)
14833 if (GET_CODE (PATTERN (insn)) == USE
14834 || GET_CODE (PATTERN (insn)) == CLOBBER)
14837 if (rs6000_sched_groups)
14839 if (is_microcoded_insn (insn))
14841 else if (is_cracked_insn (insn))
14842 return more > 2 ? more - 2 : 0;
14848 /* Adjust the cost of a scheduling dependency. Return the new cost of
14849 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
14852 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
14854 if (! recog_memoized (insn))
14857 if (REG_NOTE_KIND (link) != 0)
14860 if (REG_NOTE_KIND (link) == 0)
14862 /* Data dependency; DEP_INSN writes a register that INSN reads
14863 some cycles later. */
14865 /* Separate a load from a narrower, dependent store. */
14866 if (rs6000_sched_groups
14867 && GET_CODE (PATTERN (insn)) == SET
14868 && GET_CODE (PATTERN (dep_insn)) == SET
14869 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
14870 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
14871 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
14872 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
14875 switch (get_attr_type (insn))
14878 /* Tell the first scheduling pass about the latency between
14879 a mtctr and bctr (and mtlr and br/blr). The first
14880 scheduling pass will not know about this latency since
14881 the mtctr instruction, which has the latency associated
14882 to it, will be generated by reload. */
14883 return TARGET_POWER ? 5 : 4;
14885 /* Leave some extra cycles between a compare and its
14886 dependent branch, to inhibit expensive mispredicts. */
14887 if ((rs6000_cpu_attr == CPU_PPC603
14888 || rs6000_cpu_attr == CPU_PPC604
14889 || rs6000_cpu_attr == CPU_PPC604E
14890 || rs6000_cpu_attr == CPU_PPC620
14891 || rs6000_cpu_attr == CPU_PPC630
14892 || rs6000_cpu_attr == CPU_PPC750
14893 || rs6000_cpu_attr == CPU_PPC7400
14894 || rs6000_cpu_attr == CPU_PPC7450
14895 || rs6000_cpu_attr == CPU_POWER4
14896 || rs6000_cpu_attr == CPU_POWER5)
14897 && recog_memoized (dep_insn)
14898 && (INSN_CODE (dep_insn) >= 0)
14899 && (get_attr_type (dep_insn) == TYPE_CMP
14900 || get_attr_type (dep_insn) == TYPE_COMPARE
14901 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
14902 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
14903 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
14904 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
14905 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
14906 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
14911 /* Fall out to return default cost. */
14917 /* The function returns a true if INSN is microcoded.
14918 Return false otherwise. */
14921 is_microcoded_insn (rtx insn)
14923 if (!insn || !INSN_P (insn)
14924 || GET_CODE (PATTERN (insn)) == USE
14925 || GET_CODE (PATTERN (insn)) == CLOBBER)
14928 if (rs6000_sched_groups)
14930 enum attr_type type = get_attr_type (insn);
14931 if (type == TYPE_LOAD_EXT_U
14932 || type == TYPE_LOAD_EXT_UX
14933 || type == TYPE_LOAD_UX
14934 || type == TYPE_STORE_UX
14935 || type == TYPE_MFCR)
14942 /* The function returns a nonzero value if INSN can be scheduled only
14943 as the first insn in a dispatch group ("dispatch-slot restricted").
14944 In this case, the returned value indicates how many dispatch slots
14945 the insn occupies (at the beginning of the group).
14946 Return 0 otherwise. */
14949 is_dispatch_slot_restricted (rtx insn)
14951 enum attr_type type;
14953 if (!rs6000_sched_groups)
14957 || insn == NULL_RTX
14958 || GET_CODE (insn) == NOTE
14959 || GET_CODE (PATTERN (insn)) == USE
14960 || GET_CODE (PATTERN (insn)) == CLOBBER)
14963 type = get_attr_type (insn);
14970 case TYPE_DELAYED_CR:
14971 case TYPE_CR_LOGICAL:
14979 if (rs6000_cpu == PROCESSOR_POWER5
14980 && is_cracked_insn (insn))
14986 /* The function returns true if INSN is cracked into 2 instructions
14987 by the processor (and therefore occupies 2 issue slots). */
14990 is_cracked_insn (rtx insn)
14992 if (!insn || !INSN_P (insn)
14993 || GET_CODE (PATTERN (insn)) == USE
14994 || GET_CODE (PATTERN (insn)) == CLOBBER)
14997 if (rs6000_sched_groups)
14999 enum attr_type type = get_attr_type (insn);
15000 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
15001 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
15002 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
15003 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
15004 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
15005 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
15006 || type == TYPE_IDIV || type == TYPE_LDIV
15007 || type == TYPE_INSERT_WORD)
15014 /* The function returns true if INSN can be issued only from
15015 the branch slot. */
15018 is_branch_slot_insn (rtx insn)
15020 if (!insn || !INSN_P (insn)
15021 || GET_CODE (PATTERN (insn)) == USE
15022 || GET_CODE (PATTERN (insn)) == CLOBBER)
15025 if (rs6000_sched_groups)
15027 enum attr_type type = get_attr_type (insn);
15028 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
15036 /* A C statement (sans semicolon) to update the integer scheduling
15037 priority INSN_PRIORITY (INSN). Increase the priority to execute the
15038 INSN earlier, reduce the priority to execute INSN later. Do not
15039 define this macro if you do not need to adjust the scheduling
15040 priorities of insns. */
15043 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
15045 /* On machines (like the 750) which have asymmetric integer units,
15046 where one integer unit can do multiply and divides and the other
15047 can't, reduce the priority of multiply/divide so it is scheduled
15048 before other integer operations. */
15051 if (! INSN_P (insn))
15054 if (GET_CODE (PATTERN (insn)) == USE)
15057 switch (rs6000_cpu_attr) {
15059 switch (get_attr_type (insn))
15066 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
15067 priority, priority);
15068 if (priority >= 0 && priority < 0x01000000)
15075 if (is_dispatch_slot_restricted (insn)
15076 && reload_completed
15077 && current_sched_info->sched_max_insns_priority
15078 && rs6000_sched_restricted_insns_priority)
15081 /* Prioritize insns that can be dispatched only in the first
15083 if (rs6000_sched_restricted_insns_priority == 1)
15084 /* Attach highest priority to insn. This means that in
15085 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
15086 precede 'priority' (critical path) considerations. */
15087 return current_sched_info->sched_max_insns_priority;
15088 else if (rs6000_sched_restricted_insns_priority == 2)
15089 /* Increase priority of insn by a minimal amount. This means that in
15090 haifa-sched.c:ready_sort(), only 'priority' (critical path)
15091 considerations precede dispatch-slot restriction considerations. */
15092 return (priority + 1);
15098 /* Return how many instructions the machine can issue per cycle. */
15101 rs6000_issue_rate (void)
15103 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
15104 if (!reload_completed)
15107 switch (rs6000_cpu_attr) {
15108 case CPU_RIOS1: /* ? */
15110 case CPU_PPC601: /* ? */
15133 /* Return how many instructions to look ahead for better insn
15137 rs6000_use_sched_lookahead (void)
15139 if (rs6000_cpu_attr == CPU_PPC8540)
15144 /* Determine is PAT refers to memory. */
15147 is_mem_ref (rtx pat)
15153 if (GET_CODE (pat) == MEM)
15156 /* Recursively process the pattern. */
15157 fmt = GET_RTX_FORMAT (GET_CODE (pat));
15159 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
15162 ret |= is_mem_ref (XEXP (pat, i));
15163 else if (fmt[i] == 'E')
15164 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
15165 ret |= is_mem_ref (XVECEXP (pat, i, j));
15171 /* Determine if PAT is a PATTERN of a load insn. */
15174 is_load_insn1 (rtx pat)
15176 if (!pat || pat == NULL_RTX)
15179 if (GET_CODE (pat) == SET)
15180 return is_mem_ref (SET_SRC (pat));
15182 if (GET_CODE (pat) == PARALLEL)
15186 for (i = 0; i < XVECLEN (pat, 0); i++)
15187 if (is_load_insn1 (XVECEXP (pat, 0, i)))
15194 /* Determine if INSN loads from memory. */
15197 is_load_insn (rtx insn)
15199 if (!insn || !INSN_P (insn))
15202 if (GET_CODE (insn) == CALL_INSN)
15205 return is_load_insn1 (PATTERN (insn));
15208 /* Determine if PAT is a PATTERN of a store insn. */
15211 is_store_insn1 (rtx pat)
15213 if (!pat || pat == NULL_RTX)
15216 if (GET_CODE (pat) == SET)
15217 return is_mem_ref (SET_DEST (pat));
15219 if (GET_CODE (pat) == PARALLEL)
15223 for (i = 0; i < XVECLEN (pat, 0); i++)
15224 if (is_store_insn1 (XVECEXP (pat, 0, i)))
15231 /* Determine if INSN stores to memory. */
15234 is_store_insn (rtx insn)
15236 if (!insn || !INSN_P (insn))
15239 return is_store_insn1 (PATTERN (insn));
15242 /* Returns whether the dependence between INSN and NEXT is considered
15243 costly by the given target. */
15246 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
15249 /* If the flag is not enabled - no dependence is considered costly;
15250 allow all dependent insns in the same group.
15251 This is the most aggressive option. */
15252 if (rs6000_sched_costly_dep == no_dep_costly)
15255 /* If the flag is set to 1 - a dependence is always considered costly;
15256 do not allow dependent instructions in the same group.
15257 This is the most conservative option. */
15258 if (rs6000_sched_costly_dep == all_deps_costly)
15261 if (rs6000_sched_costly_dep == store_to_load_dep_costly
15262 && is_load_insn (next)
15263 && is_store_insn (insn))
15264 /* Prevent load after store in the same group. */
15267 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
15268 && is_load_insn (next)
15269 && is_store_insn (insn)
15270 && (!link || (int) REG_NOTE_KIND (link) == 0))
15271 /* Prevent load after store in the same group if it is a true
15275 /* The flag is set to X; dependences with latency >= X are considered costly,
15276 and will not be scheduled in the same group. */
15277 if (rs6000_sched_costly_dep <= max_dep_latency
15278 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
15284 /* Return the next insn after INSN that is found before TAIL is reached,
15285 skipping any "non-active" insns - insns that will not actually occupy
15286 an issue slot. Return NULL_RTX if such an insn is not found. */
15289 get_next_active_insn (rtx insn, rtx tail)
15293 if (!insn || insn == tail)
15296 next_insn = NEXT_INSN (insn);
15299 && next_insn != tail
15300 && (GET_CODE (next_insn) == NOTE
15301 || GET_CODE (PATTERN (next_insn)) == USE
15302 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
15304 next_insn = NEXT_INSN (next_insn);
15307 if (!next_insn || next_insn == tail)
15313 /* Return whether the presence of INSN causes a dispatch group termination
15314 of group WHICH_GROUP.
15316 If WHICH_GROUP == current_group, this function will return true if INSN
15317 causes the termination of the current group (i.e, the dispatch group to
15318 which INSN belongs). This means that INSN will be the last insn in the
15319 group it belongs to.
15321 If WHICH_GROUP == previous_group, this function will return true if INSN
15322 causes the termination of the previous group (i.e, the dispatch group that
15323 precedes the group to which INSN belongs). This means that INSN will be
15324 the first insn in the group it belongs to). */
15327 insn_terminates_group_p (rtx insn, enum group_termination which_group)
15329 enum attr_type type;
15334 type = get_attr_type (insn);
15336 if (is_microcoded_insn (insn))
15339 if (which_group == current_group)
15341 if (is_branch_slot_insn (insn))
15345 else if (which_group == previous_group)
15347 if (is_dispatch_slot_restricted (insn))
15355 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
15356 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
15359 is_costly_group (rtx *group_insns, rtx next_insn)
15364 int issue_rate = rs6000_issue_rate ();
15366 for (i = 0; i < issue_rate; i++)
15368 rtx insn = group_insns[i];
15371 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
15373 rtx next = XEXP (link, 0);
15374 if (next == next_insn)
15376 cost = insn_cost (insn, link, next_insn);
15377 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
15386 /* Utility of the function redefine_groups.
15387 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
15388 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
15389 to keep it "far" (in a separate group) from GROUP_INSNS, following
15390 one of the following schemes, depending on the value of the flag
15391 -minsert_sched_nops = X:
15392 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
15393 in order to force NEXT_INSN into a separate group.
15394 (2) X < sched_finish_regroup_exact: insert exactly X nops.
15395 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
15396 insertion (has a group just ended, how many vacant issue slots remain in the
15397 last group, and how many dispatch groups were encountered so far). */
15400 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
15401 rtx next_insn, bool *group_end, int can_issue_more,
15406 int issue_rate = rs6000_issue_rate ();
15407 bool end = *group_end;
15410 if (next_insn == NULL_RTX)
15411 return can_issue_more;
15413 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
15414 return can_issue_more;
15416 force = is_costly_group (group_insns, next_insn);
15418 return can_issue_more;
15420 if (sched_verbose > 6)
15421 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
15422 *group_count ,can_issue_more);
15424 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
15427 can_issue_more = 0;
15429 /* Since only a branch can be issued in the last issue_slot, it is
15430 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
15431 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
15432 in this case the last nop will start a new group and the branch
15433 will be forced to the new group. */
15434 if (can_issue_more && !is_branch_slot_insn (next_insn))
15437 while (can_issue_more > 0)
15440 emit_insn_before (nop, next_insn);
15448 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
15450 int n_nops = rs6000_sched_insert_nops;
15452 /* Nops can't be issued from the branch slot, so the effective
15453 issue_rate for nops is 'issue_rate - 1'. */
15454 if (can_issue_more == 0)
15455 can_issue_more = issue_rate;
15457 if (can_issue_more == 0)
15459 can_issue_more = issue_rate - 1;
15462 for (i = 0; i < issue_rate; i++)
15464 group_insns[i] = 0;
15471 emit_insn_before (nop, next_insn);
15472 if (can_issue_more == issue_rate - 1) /* new group begins */
15475 if (can_issue_more == 0)
15477 can_issue_more = issue_rate - 1;
15480 for (i = 0; i < issue_rate; i++)
15482 group_insns[i] = 0;
15488 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
15491 /* Is next_insn going to start a new group? */
15494 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
15495 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
15496 || (can_issue_more < issue_rate &&
15497 insn_terminates_group_p (next_insn, previous_group)));
15498 if (*group_end && end)
15501 if (sched_verbose > 6)
15502 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
15503 *group_count, can_issue_more);
15504 return can_issue_more;
15507 return can_issue_more;
15510 /* This function tries to synch the dispatch groups that the compiler "sees"
15511 with the dispatch groups that the processor dispatcher is expected to
15512 form in practice. It tries to achieve this synchronization by forcing the
15513 estimated processor grouping on the compiler (as opposed to the function
15514 'pad_goups' which tries to force the scheduler's grouping on the processor).
15516 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
15517 examines the (estimated) dispatch groups that will be formed by the processor
15518 dispatcher. It marks these group boundaries to reflect the estimated
15519 processor grouping, overriding the grouping that the scheduler had marked.
15520 Depending on the value of the flag '-minsert-sched-nops' this function can
15521 force certain insns into separate groups or force a certain distance between
15522 them by inserting nops, for example, if there exists a "costly dependence"
15525 The function estimates the group boundaries that the processor will form as
15526 folllows: It keeps track of how many vacant issue slots are available after
15527 each insn. A subsequent insn will start a new group if one of the following
15529 - no more vacant issue slots remain in the current dispatch group.
15530 - only the last issue slot, which is the branch slot, is vacant, but the next
15531 insn is not a branch.
15532 - only the last 2 or less issue slots, including the branch slot, are vacant,
15533 which means that a cracked insn (which occupies two issue slots) can't be
15534 issued in this group.
15535 - less than 'issue_rate' slots are vacant, and the next insn always needs to
15536 start a new group. */
15539 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
15541 rtx insn, next_insn;
15543 int can_issue_more;
15546 int group_count = 0;
15550 issue_rate = rs6000_issue_rate ();
15551 group_insns = alloca (issue_rate * sizeof (rtx));
15552 for (i = 0; i < issue_rate; i++)
15554 group_insns[i] = 0;
15556 can_issue_more = issue_rate;
15558 insn = get_next_active_insn (prev_head_insn, tail);
15561 while (insn != NULL_RTX)
15563 slot = (issue_rate - can_issue_more);
15564 group_insns[slot] = insn;
15566 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
15567 if (insn_terminates_group_p (insn, current_group))
15568 can_issue_more = 0;
15570 next_insn = get_next_active_insn (insn, tail);
15571 if (next_insn == NULL_RTX)
15572 return group_count + 1;
15574 /* Is next_insn going to start a new group? */
15576 = (can_issue_more == 0
15577 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
15578 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
15579 || (can_issue_more < issue_rate &&
15580 insn_terminates_group_p (next_insn, previous_group)));
15582 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
15583 next_insn, &group_end, can_issue_more,
15589 can_issue_more = 0;
15590 for (i = 0; i < issue_rate; i++)
15592 group_insns[i] = 0;
15596 if (GET_MODE (next_insn) == TImode && can_issue_more)
15597 PUT_MODE (next_insn, VOIDmode);
15598 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
15599 PUT_MODE (next_insn, TImode);
15602 if (can_issue_more == 0)
15603 can_issue_more = issue_rate;
15606 return group_count;
15609 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
15610 dispatch group boundaries that the scheduler had marked. Pad with nops
15611 any dispatch groups which have vacant issue slots, in order to force the
15612 scheduler's grouping on the processor dispatcher. The function
15613 returns the number of dispatch groups found. */
15616 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
15618 rtx insn, next_insn;
15621 int can_issue_more;
15623 int group_count = 0;
15625 /* Initialize issue_rate. */
15626 issue_rate = rs6000_issue_rate ();
15627 can_issue_more = issue_rate;
15629 insn = get_next_active_insn (prev_head_insn, tail);
15630 next_insn = get_next_active_insn (insn, tail);
15632 while (insn != NULL_RTX)
15635 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
15637 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
15639 if (next_insn == NULL_RTX)
15644 /* If the scheduler had marked group termination at this location
15645 (between insn and next_indn), and neither insn nor next_insn will
15646 force group termination, pad the group with nops to force group
15649 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
15650 && !insn_terminates_group_p (insn, current_group)
15651 && !insn_terminates_group_p (next_insn, previous_group))
15653 if (!is_branch_slot_insn (next_insn))
15656 while (can_issue_more)
15659 emit_insn_before (nop, next_insn);
15664 can_issue_more = issue_rate;
15669 next_insn = get_next_active_insn (insn, tail);
15672 return group_count;
15675 /* The following function is called at the end of scheduling BB.
15676 After reload, it inserts nops at insn group bundling. */
15679 rs6000_sched_finish (FILE *dump, int sched_verbose)
15684 fprintf (dump, "=== Finishing schedule.\n");
15686 if (reload_completed && rs6000_sched_groups)
15688 if (rs6000_sched_insert_nops == sched_finish_none)
15691 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
15692 n_groups = pad_groups (dump, sched_verbose,
15693 current_sched_info->prev_head,
15694 current_sched_info->next_tail);
15696 n_groups = redefine_groups (dump, sched_verbose,
15697 current_sched_info->prev_head,
15698 current_sched_info->next_tail);
15700 if (sched_verbose >= 6)
15702 fprintf (dump, "ngroups = %d\n", n_groups);
15703 print_rtl (dump, current_sched_info->prev_head);
15704 fprintf (dump, "Done finish_sched\n");
15709 /* Length in units of the trampoline for entering a nested function. */
15712 rs6000_trampoline_size (void)
15716 switch (DEFAULT_ABI)
15722 ret = (TARGET_32BIT) ? 12 : 24;
15727 ret = (TARGET_32BIT) ? 40 : 48;
15734 /* Emit RTL insns to initialize the variable parts of a trampoline.
15735 FNADDR is an RTX for the address of the function's pure code.
15736 CXT is an RTX for the static chain value for the function. */
15739 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
15741 enum machine_mode pmode = Pmode;
15742 int regsize = (TARGET_32BIT) ? 4 : 8;
15743 rtx ctx_reg = force_reg (pmode, cxt);
15745 switch (DEFAULT_ABI)
15750 /* Macros to shorten the code expansions below. */
15751 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
15752 #define MEM_PLUS(addr,offset) \
15753 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
15755 /* Under AIX, just build the 3 word function descriptor */
15758 rtx fn_reg = gen_reg_rtx (pmode);
15759 rtx toc_reg = gen_reg_rtx (pmode);
15760 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
15761 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
15762 emit_move_insn (MEM_DEREF (addr), fn_reg);
15763 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
15764 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
15768 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
15771 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
15772 FALSE, VOIDmode, 4,
15774 GEN_INT (rs6000_trampoline_size ()), SImode,
15784 /* Table of valid machine attributes. */
15786 const struct attribute_spec rs6000_attribute_table[] =
15788 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
15789 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
15790 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
15791 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
15792 #ifdef SUBTARGET_ATTRIBUTE_TABLE
15793 SUBTARGET_ATTRIBUTE_TABLE,
15795 { NULL, 0, 0, false, false, false, NULL }
15798 /* Handle the "altivec" attribute. The attribute may have
15799 arguments as follows:
15801 __attribute__((altivec(vector__)))
15802 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
15803 __attribute__((altivec(bool__))) (always followed by 'unsigned')
15805 and may appear more than once (e.g., 'vector bool char') in a
15806 given declaration. */
15809 rs6000_handle_altivec_attribute (tree *node,
15810 tree name ATTRIBUTE_UNUSED,
15812 int flags ATTRIBUTE_UNUSED,
15813 bool *no_add_attrs)
15815 tree type = *node, result = NULL_TREE;
15816 enum machine_mode mode;
15819 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
15820 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
15821 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
15824 while (POINTER_TYPE_P (type)
15825 || TREE_CODE (type) == FUNCTION_TYPE
15826 || TREE_CODE (type) == METHOD_TYPE
15827 || TREE_CODE (type) == ARRAY_TYPE)
15828 type = TREE_TYPE (type);
15830 mode = TYPE_MODE (type);
15832 /* Check for invalid AltiVec type qualifiers. */
15833 if (type == long_unsigned_type_node || type == long_integer_type_node)
15836 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
15837 else if (rs6000_warn_altivec_long)
15838 warning ("use of %<long%> in AltiVec types is deprecated; use %<int%>");
15840 else if (type == long_long_unsigned_type_node
15841 || type == long_long_integer_type_node)
15842 error ("use of %<long long%> in AltiVec types is invalid");
15843 else if (type == double_type_node)
15844 error ("use of %<double%> in AltiVec types is invalid");
15845 else if (type == long_double_type_node)
15846 error ("use of %<long double%> in AltiVec types is invalid");
15847 else if (type == boolean_type_node)
15848 error ("use of boolean types in AltiVec types is invalid");
15849 else if (TREE_CODE (type) == COMPLEX_TYPE)
15850 error ("use of %<complex%> in AltiVec types is invalid");
15852 switch (altivec_type)
15855 unsigned_p = TYPE_UNSIGNED (type);
15859 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
15862 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
15865 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
15867 case SFmode: result = V4SF_type_node; break;
15868 /* If the user says 'vector int bool', we may be handed the 'bool'
15869 attribute _before_ the 'vector' attribute, and so select the
15870 proper type in the 'b' case below. */
15871 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
15879 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
15880 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
15881 case QImode: case V16QImode: result = bool_V16QI_type_node;
15888 case V8HImode: result = pixel_V8HI_type_node;
15894 if (result && result != type && TYPE_READONLY (type))
15895 result = build_qualified_type (result, TYPE_QUAL_CONST);
15897 *no_add_attrs = true; /* No need to hang on to the attribute. */
15900 *node = reconstruct_complex_type (*node, result);
15905 /* AltiVec defines four built-in scalar types that serve as vector
15906 elements; we must teach the compiler how to mangle them. */
15908 static const char *
15909 rs6000_mangle_fundamental_type (tree type)
15911 if (type == bool_char_type_node) return "U6__boolc";
15912 if (type == bool_short_type_node) return "U6__bools";
15913 if (type == pixel_type_node) return "u7__pixel";
15914 if (type == bool_int_type_node) return "U6__booli";
15916 /* For all other types, use normal C++ mangling. */
15920 /* Handle a "longcall" or "shortcall" attribute; arguments as in
15921 struct attribute_spec.handler. */
15924 rs6000_handle_longcall_attribute (tree *node, tree name,
15925 tree args ATTRIBUTE_UNUSED,
15926 int flags ATTRIBUTE_UNUSED,
15927 bool *no_add_attrs)
15929 if (TREE_CODE (*node) != FUNCTION_TYPE
15930 && TREE_CODE (*node) != FIELD_DECL
15931 && TREE_CODE (*node) != TYPE_DECL)
15933 warning ("%qs attribute only applies to functions",
15934 IDENTIFIER_POINTER (name));
15935 *no_add_attrs = true;
15941 /* Set longcall attributes on all functions declared when
15942 rs6000_default_long_calls is true. */
15944 rs6000_set_default_type_attributes (tree type)
15946 if (rs6000_default_long_calls
15947 && (TREE_CODE (type) == FUNCTION_TYPE
15948 || TREE_CODE (type) == METHOD_TYPE))
15949 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
15951 TYPE_ATTRIBUTES (type));
15954 /* Return a reference suitable for calling a function with the
15955 longcall attribute. */
15958 rs6000_longcall_ref (rtx call_ref)
15960 const char *call_name;
15963 if (GET_CODE (call_ref) != SYMBOL_REF)
15966 /* System V adds '.' to the internal name, so skip them. */
15967 call_name = XSTR (call_ref, 0);
15968 if (*call_name == '.')
15970 while (*call_name == '.')
15973 node = get_identifier (call_name);
15974 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
15977 return force_reg (Pmode, call_ref);
15980 #ifdef USING_ELFOS_H
15982 /* A C statement or statements to switch to the appropriate section
15983 for output of RTX in mode MODE. You can assume that RTX is some
15984 kind of constant in RTL. The argument MODE is redundant except in
15985 the case of a `const_int' rtx. Select the section by calling
15986 `text_section' or one of the alternatives for other sections.
15988 Do not define this macro if you put all constants in the read-only
15992 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
15993 unsigned HOST_WIDE_INT align)
15995 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
15998 default_elf_select_rtx_section (mode, x, align);
16001 /* A C statement or statements to switch to the appropriate
16002 section for output of DECL. DECL is either a `VAR_DECL' node
16003 or a constant of some sort. RELOC indicates whether forming
16004 the initial value of DECL requires link-time relocations. */
16007 rs6000_elf_select_section (tree decl, int reloc,
16008 unsigned HOST_WIDE_INT align)
16010 /* Pretend that we're always building for a shared library when
16011 ABI_AIX, because otherwise we end up with dynamic relocations
16012 in read-only sections. This happens for function pointers,
16013 references to vtables in typeinfo, and probably other cases. */
16014 default_elf_select_section_1 (decl, reloc, align,
16015 flag_pic || DEFAULT_ABI == ABI_AIX);
16018 /* A C statement to build up a unique section name, expressed as a
16019 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
16020 RELOC indicates whether the initial value of EXP requires
16021 link-time relocations. If you do not define this macro, GCC will use
16022 the symbol name prefixed by `.' as the section name. Note - this
16023 macro can now be called for uninitialized data items as well as
16024 initialized data and functions. */
16027 rs6000_elf_unique_section (tree decl, int reloc)
16029 /* As above, pretend that we're always building for a shared library
16030 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
16031 default_unique_section_1 (decl, reloc,
16032 flag_pic || DEFAULT_ABI == ABI_AIX);
16035 /* For a SYMBOL_REF, set generic flags and then perform some
16036 target-specific processing.
16038 When the AIX ABI is requested on a non-AIX system, replace the
16039 function name with the real name (with a leading .) rather than the
16040 function descriptor name. This saves a lot of overriding code to
16041 read the prefixes. */
16044 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
16046 default_encode_section_info (decl, rtl, first);
16049 && TREE_CODE (decl) == FUNCTION_DECL
16051 && DEFAULT_ABI == ABI_AIX)
16053 rtx sym_ref = XEXP (rtl, 0);
16054 size_t len = strlen (XSTR (sym_ref, 0));
16055 char *str = alloca (len + 2);
16057 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
16058 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
16063 rs6000_elf_in_small_data_p (tree decl)
16065 if (rs6000_sdata == SDATA_NONE)
16068 /* We want to merge strings, so we never consider them small data. */
16069 if (TREE_CODE (decl) == STRING_CST)
16072 /* Functions are never in the small data area. */
16073 if (TREE_CODE (decl) == FUNCTION_DECL)
16076 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
16078 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
16079 if (strcmp (section, ".sdata") == 0
16080 || strcmp (section, ".sdata2") == 0
16081 || strcmp (section, ".sbss") == 0
16082 || strcmp (section, ".sbss2") == 0
16083 || strcmp (section, ".PPC.EMB.sdata0") == 0
16084 || strcmp (section, ".PPC.EMB.sbss0") == 0)
16089 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
16092 && (unsigned HOST_WIDE_INT) size <= g_switch_value
16093 /* If it's not public, and we're not going to reference it there,
16094 there's no need to put it in the small data section. */
16095 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
16102 #endif /* USING_ELFOS_H */
16105 /* Return a REG that occurs in ADDR with coefficient 1.
16106 ADDR can be effectively incremented by incrementing REG.
16108 r0 is special and we must not select it as an address
16109 register by this routine since our caller will try to
16110 increment the returned register via an "la" instruction. */
16113 find_addr_reg (rtx addr)
16115 while (GET_CODE (addr) == PLUS)
16117 if (GET_CODE (XEXP (addr, 0)) == REG
16118 && REGNO (XEXP (addr, 0)) != 0)
16119 addr = XEXP (addr, 0);
16120 else if (GET_CODE (XEXP (addr, 1)) == REG
16121 && REGNO (XEXP (addr, 1)) != 0)
16122 addr = XEXP (addr, 1);
16123 else if (CONSTANT_P (XEXP (addr, 0)))
16124 addr = XEXP (addr, 1);
16125 else if (CONSTANT_P (XEXP (addr, 1)))
16126 addr = XEXP (addr, 0);
16130 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
16136 rs6000_fatal_bad_address (rtx op)
16138 fatal_insn ("bad address", op);
16143 static tree branch_island_list = 0;
16145 /* Remember to generate a branch island for far calls to the given
16149 add_compiler_branch_island (tree label_name, tree function_name,
16152 tree branch_island = build_tree_list (function_name, label_name);
16153 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
16154 TREE_CHAIN (branch_island) = branch_island_list;
16155 branch_island_list = branch_island;
16158 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
16159 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
16160 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
16161 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
16163 /* Generate far-jump branch islands for everything on the
16164 branch_island_list. Invoked immediately after the last instruction
16165 of the epilogue has been emitted; the branch-islands must be
16166 appended to, and contiguous with, the function body. Mach-O stubs
16167 are generated in machopic_output_stub(). */
16170 macho_branch_islands (void)
16173 tree branch_island;
16175 for (branch_island = branch_island_list;
16177 branch_island = TREE_CHAIN (branch_island))
16179 const char *label =
16180 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
16182 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
16183 char name_buf[512];
16184 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
16185 if (name[0] == '*' || name[0] == '&')
16186 strcpy (name_buf, name+1);
16190 strcpy (name_buf+1, name);
16192 strcpy (tmp_buf, "\n");
16193 strcat (tmp_buf, label);
16194 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
16195 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
16196 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
16197 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
16200 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
16201 strcat (tmp_buf, label);
16202 strcat (tmp_buf, "_pic\n");
16203 strcat (tmp_buf, label);
16204 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
16206 strcat (tmp_buf, "\taddis r11,r11,ha16(");
16207 strcat (tmp_buf, name_buf);
16208 strcat (tmp_buf, " - ");
16209 strcat (tmp_buf, label);
16210 strcat (tmp_buf, "_pic)\n");
16212 strcat (tmp_buf, "\tmtlr r0\n");
16214 strcat (tmp_buf, "\taddi r12,r11,lo16(");
16215 strcat (tmp_buf, name_buf);
16216 strcat (tmp_buf, " - ");
16217 strcat (tmp_buf, label);
16218 strcat (tmp_buf, "_pic)\n");
16220 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
16224 strcat (tmp_buf, ":\nlis r12,hi16(");
16225 strcat (tmp_buf, name_buf);
16226 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
16227 strcat (tmp_buf, name_buf);
16228 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
16230 output_asm_insn (tmp_buf, 0);
16231 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
16232 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
16233 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
16234 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
16237 branch_island_list = 0;
16240 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
16241 already there or not. */
16244 no_previous_def (tree function_name)
16246 tree branch_island;
16247 for (branch_island = branch_island_list;
16249 branch_island = TREE_CHAIN (branch_island))
16250 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
16255 /* GET_PREV_LABEL gets the label name from the previous definition of
16259 get_prev_label (tree function_name)
16261 tree branch_island;
16262 for (branch_island = branch_island_list;
16264 branch_island = TREE_CHAIN (branch_island))
16265 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
16266 return BRANCH_ISLAND_LABEL_NAME (branch_island);
16270 /* INSN is either a function call or a millicode call. It may have an
16271 unconditional jump in its delay slot.
16273 CALL_DEST is the routine we are calling. */
16276 output_call (rtx insn, rtx *operands, int dest_operand_number,
16277 int cookie_operand_number)
16279 static char buf[256];
16280 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
16281 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
16284 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
16286 if (no_previous_def (funname))
16288 int line_number = 0;
16289 rtx label_rtx = gen_label_rtx ();
16290 char *label_buf, temp_buf[256];
16291 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
16292 CODE_LABEL_NUMBER (label_rtx));
16293 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
16294 labelname = get_identifier (label_buf);
16295 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
16297 line_number = NOTE_LINE_NUMBER (insn);
16298 add_compiler_branch_island (labelname, funname, line_number);
16301 labelname = get_prev_label (funname);
16303 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
16304 instruction will reach 'foo', otherwise link as 'bl L42'".
16305 "L42" should be a 'branch island', that will do a far jump to
16306 'foo'. Branch islands are generated in
16307 macho_branch_islands(). */
16308 sprintf (buf, "jbsr %%z%d,%.246s",
16309 dest_operand_number, IDENTIFIER_POINTER (labelname));
16312 sprintf (buf, "bl %%z%d", dest_operand_number);
16316 /* Generate PIC and indirect symbol stubs. */
16319 machopic_output_stub (FILE *file, const char *symb, const char *stub)
16321 unsigned int length;
16322 char *symbol_name, *lazy_ptr_name;
16323 char *local_label_0;
16324 static int label = 0;
16326 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
16327 symb = (*targetm.strip_name_encoding) (symb);
16330 length = strlen (symb);
16331 symbol_name = alloca (length + 32);
16332 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
16334 lazy_ptr_name = alloca (length + 32);
16335 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
16338 machopic_picsymbol_stub1_section ();
16340 machopic_symbol_stub1_section ();
16344 fprintf (file, "\t.align 5\n");
16346 fprintf (file, "%s:\n", stub);
16347 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16350 local_label_0 = alloca (sizeof ("\"L0000000000$spb\""));
16351 sprintf (local_label_0, "\"L%011d$spb\"", label);
16353 fprintf (file, "\tmflr r0\n");
16354 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
16355 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
16356 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
16357 lazy_ptr_name, local_label_0);
16358 fprintf (file, "\tmtlr r0\n");
16359 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
16360 (TARGET_64BIT ? "ldu" : "lwzu"),
16361 lazy_ptr_name, local_label_0);
16362 fprintf (file, "\tmtctr r12\n");
16363 fprintf (file, "\tbctr\n");
16367 fprintf (file, "\t.align 4\n");
16369 fprintf (file, "%s:\n", stub);
16370 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16372 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
16373 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
16374 (TARGET_64BIT ? "ldu" : "lwzu"),
16376 fprintf (file, "\tmtctr r12\n");
16377 fprintf (file, "\tbctr\n");
16380 machopic_lazy_symbol_ptr_section ();
16381 fprintf (file, "%s:\n", lazy_ptr_name);
16382 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16383 fprintf (file, "%sdyld_stub_binding_helper\n",
16384 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
16387 /* Legitimize PIC addresses. If the address is already
16388 position-independent, we return ORIG. Newly generated
16389 position-independent addresses go into a reg. This is REG if non
16390 zero, otherwise we allocate register(s) as necessary. */
16392 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
16395 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
16400 if (reg == NULL && ! reload_in_progress && ! reload_completed)
16401 reg = gen_reg_rtx (Pmode);
16403 if (GET_CODE (orig) == CONST)
16405 if (GET_CODE (XEXP (orig, 0)) == PLUS
16406 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
16409 if (GET_CODE (XEXP (orig, 0)) == PLUS)
16411 /* Use a different reg for the intermediate value, as
16412 it will be marked UNCHANGING. */
16413 rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
16416 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
16419 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
16425 if (GET_CODE (offset) == CONST_INT)
16427 if (SMALL_INT (offset))
16428 return plus_constant (base, INTVAL (offset));
16429 else if (! reload_in_progress && ! reload_completed)
16430 offset = force_reg (Pmode, offset);
16433 rtx mem = force_const_mem (Pmode, orig);
16434 return machopic_legitimize_pic_address (mem, Pmode, reg);
16437 return gen_rtx_PLUS (Pmode, base, offset);
16440 /* Fall back on generic machopic code. */
16441 return machopic_legitimize_pic_address (orig, mode, reg);
16444 /* This is just a placeholder to make linking work without having to
16445 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
16446 ever needed for Darwin (not too likely!) this would have to get a
16447 real definition. */
16454 /* Output a .machine directive for the Darwin assembler, and call
16455 the generic start_file routine. */
16458 rs6000_darwin_file_start (void)
16460 static const struct
16466 { "ppc64", "ppc64", MASK_64BIT },
16467 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
16468 { "power4", "ppc970", 0 },
16469 { "G5", "ppc970", 0 },
16470 { "7450", "ppc7450", 0 },
16471 { "7400", "ppc7400", MASK_ALTIVEC },
16472 { "G4", "ppc7400", 0 },
16473 { "750", "ppc750", 0 },
16474 { "740", "ppc750", 0 },
16475 { "G3", "ppc750", 0 },
16476 { "604e", "ppc604e", 0 },
16477 { "604", "ppc604", 0 },
16478 { "603e", "ppc603", 0 },
16479 { "603", "ppc603", 0 },
16480 { "601", "ppc601", 0 },
16481 { NULL, "ppc", 0 } };
16482 const char *cpu_id = "";
16485 rs6000_file_start ();
16487 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
16488 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
16489 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
16490 && rs6000_select[i].string[0] != '\0')
16491 cpu_id = rs6000_select[i].string;
16493 /* Look through the mapping array. Pick the first name that either
16494 matches the argument, has a bit set in IF_SET that is also set
16495 in the target flags, or has a NULL name. */
16498 while (mapping[i].arg != NULL
16499 && strcmp (mapping[i].arg, cpu_id) != 0
16500 && (mapping[i].if_set & target_flags) == 0)
16503 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
16506 #endif /* TARGET_MACHO */
16509 static unsigned int
16510 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
16512 return default_section_type_flags_1 (decl, name, reloc,
16513 flag_pic || DEFAULT_ABI == ABI_AIX);
16516 /* Record an element in the table of global constructors. SYMBOL is
16517 a SYMBOL_REF of the function to be called; PRIORITY is a number
16518 between 0 and MAX_INIT_PRIORITY.
16520 This differs from default_named_section_asm_out_constructor in
16521 that we have special handling for -mrelocatable. */
16524 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
16526 const char *section = ".ctors";
16529 if (priority != DEFAULT_INIT_PRIORITY)
16531 sprintf (buf, ".ctors.%.5u",
16532 /* Invert the numbering so the linker puts us in the proper
16533 order; constructors are run from right to left, and the
16534 linker sorts in increasing order. */
16535 MAX_INIT_PRIORITY - priority);
16539 named_section_flags (section, SECTION_WRITE);
16540 assemble_align (POINTER_SIZE);
16542 if (TARGET_RELOCATABLE)
16544 fputs ("\t.long (", asm_out_file);
16545 output_addr_const (asm_out_file, symbol);
16546 fputs (")@fixup\n", asm_out_file);
16549 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
16553 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
16555 const char *section = ".dtors";
16558 if (priority != DEFAULT_INIT_PRIORITY)
16560 sprintf (buf, ".dtors.%.5u",
16561 /* Invert the numbering so the linker puts us in the proper
16562 order; constructors are run from right to left, and the
16563 linker sorts in increasing order. */
16564 MAX_INIT_PRIORITY - priority);
16568 named_section_flags (section, SECTION_WRITE);
16569 assemble_align (POINTER_SIZE);
16571 if (TARGET_RELOCATABLE)
16573 fputs ("\t.long (", asm_out_file);
16574 output_addr_const (asm_out_file, symbol);
16575 fputs (")@fixup\n", asm_out_file);
16578 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
16582 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
16586 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
16587 ASM_OUTPUT_LABEL (file, name);
16588 fputs (DOUBLE_INT_ASM_OP, file);
16589 rs6000_output_function_entry (file, name);
16590 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
16593 fputs ("\t.size\t", file);
16594 assemble_name (file, name);
16595 fputs (",24\n\t.type\t.", file);
16596 assemble_name (file, name);
16597 fputs (",@function\n", file);
16598 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
16600 fputs ("\t.globl\t.", file);
16601 assemble_name (file, name);
16606 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
16607 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
16608 rs6000_output_function_entry (file, name);
16609 fputs (":\n", file);
16613 if (TARGET_RELOCATABLE
16614 && (get_pool_size () != 0 || current_function_profile)
16619 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
16621 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
16622 fprintf (file, "\t.long ");
16623 assemble_name (file, buf);
16625 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
16626 assemble_name (file, buf);
16630 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
16631 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
16633 if (DEFAULT_ABI == ABI_AIX)
16635 const char *desc_name, *orig_name;
16637 orig_name = (*targetm.strip_name_encoding) (name);
16638 desc_name = orig_name;
16639 while (*desc_name == '.')
16642 if (TREE_PUBLIC (decl))
16643 fprintf (file, "\t.globl %s\n", desc_name);
16645 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
16646 fprintf (file, "%s:\n", desc_name);
16647 fprintf (file, "\t.long %s\n", orig_name);
16648 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
16649 if (DEFAULT_ABI == ABI_AIX)
16650 fputs ("\t.long 0\n", file);
16651 fprintf (file, "\t.previous\n");
16653 ASM_OUTPUT_LABEL (file, name);
16659 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
16661 fputs (GLOBAL_ASM_OP, stream);
16662 RS6000_OUTPUT_BASENAME (stream, name);
16663 putc ('\n', stream);
16667 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
16668 tree decl ATTRIBUTE_UNUSED)
16671 static const char * const suffix[3] = { "PR", "RO", "RW" };
16673 if (flags & SECTION_CODE)
16675 else if (flags & SECTION_WRITE)
16680 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
16681 (flags & SECTION_CODE) ? "." : "",
16682 name, suffix[smclass], flags & SECTION_ENTSIZE);
16686 rs6000_xcoff_select_section (tree decl, int reloc,
16687 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
16689 if (decl_readonly_section_1 (decl, reloc, 1))
16691 if (TREE_PUBLIC (decl))
16692 read_only_data_section ();
16694 read_only_private_data_section ();
16698 if (TREE_PUBLIC (decl))
16701 private_data_section ();
16706 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
16710 /* Use select_section for private and uninitialized data. */
16711 if (!TREE_PUBLIC (decl)
16712 || DECL_COMMON (decl)
16713 || DECL_INITIAL (decl) == NULL_TREE
16714 || DECL_INITIAL (decl) == error_mark_node
16715 || (flag_zero_initialized_in_bss
16716 && initializer_zerop (DECL_INITIAL (decl))))
16719 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
16720 name = (*targetm.strip_name_encoding) (name);
16721 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
16724 /* Select section for constant in constant pool.
16726 On RS/6000, all constants are in the private read-only data area.
16727 However, if this is being placed in the TOC it must be output as a
16731 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
16732 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
16734 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
16737 read_only_private_data_section ();
16740 /* Remove any trailing [DS] or the like from the symbol name. */
16742 static const char *
16743 rs6000_xcoff_strip_name_encoding (const char *name)
16748 len = strlen (name);
16749 if (name[len - 1] == ']')
16750 return ggc_alloc_string (name, len - 4);
16755 /* Section attributes. AIX is always PIC. */
16757 static unsigned int
16758 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
16760 unsigned int align;
16761 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
16763 /* Align to at least UNIT size. */
16764 if (flags & SECTION_CODE)
16765 align = MIN_UNITS_PER_WORD;
16767 /* Increase alignment of large objects if not already stricter. */
16768 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
16769 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
16770 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
16772 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
16775 /* Output at beginning of assembler file.
16777 Initialize the section names for the RS/6000 at this point.
16779 Specify filename, including full path, to assembler.
16781 We want to go into the TOC section so at least one .toc will be emitted.
16782 Also, in order to output proper .bs/.es pairs, we need at least one static
16783 [RW] section emitted.
16785 Finally, declare mcount when profiling to make the assembler happy. */
16788 rs6000_xcoff_file_start (void)
16790 rs6000_gen_section_name (&xcoff_bss_section_name,
16791 main_input_filename, ".bss_");
16792 rs6000_gen_section_name (&xcoff_private_data_section_name,
16793 main_input_filename, ".rw_");
16794 rs6000_gen_section_name (&xcoff_read_only_section_name,
16795 main_input_filename, ".ro_");
16797 fputs ("\t.file\t", asm_out_file);
16798 output_quoted_string (asm_out_file, main_input_filename);
16799 fputc ('\n', asm_out_file);
16800 if (write_symbols != NO_DEBUG)
16801 private_data_section ();
16804 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
16805 rs6000_file_start ();
16808 /* Output at end of assembler file.
16809 On the RS/6000, referencing data should automatically pull in text. */
16812 rs6000_xcoff_file_end (void)
16815 fputs ("_section_.text:\n", asm_out_file);
16817 fputs (TARGET_32BIT
16818 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
16821 #endif /* TARGET_XCOFF */
16824 /* Cross-module name binding. Darwin does not support overriding
16825 functions at dynamic-link time. */
16828 rs6000_binds_local_p (tree decl)
16830 return default_binds_local_p_1 (decl, 0);
16834 /* Compute a (partial) cost for rtx X. Return true if the complete
16835 cost has been computed, and false if subexpressions should be
16836 scanned. In either case, *TOTAL contains the cost result. */
16839 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
16841 enum machine_mode mode = GET_MODE (x);
16845 /* On the RS/6000, if it is valid in the insn, it is free. */
16847 if (((outer_code == SET
16848 || outer_code == PLUS
16849 || outer_code == MINUS)
16850 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
16851 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
16852 || (outer_code == AND
16853 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16854 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
16855 mode == SImode ? 'L' : 'J'))
16856 || mask_operand (x, VOIDmode)))
16857 || ((outer_code == IOR || outer_code == XOR)
16858 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16859 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
16860 mode == SImode ? 'L' : 'J'))))
16861 || outer_code == ASHIFT
16862 || outer_code == ASHIFTRT
16863 || outer_code == LSHIFTRT
16864 || outer_code == ROTATE
16865 || outer_code == ROTATERT
16866 || outer_code == ZERO_EXTRACT
16867 || (outer_code == MULT
16868 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
16869 || ((outer_code == DIV || outer_code == UDIV
16870 || outer_code == MOD || outer_code == UMOD)
16871 && exact_log2 (INTVAL (x)) >= 0)
16872 || (outer_code == COMPARE
16873 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
16874 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
16875 || (outer_code == EQ
16876 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
16877 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16878 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
16879 mode == SImode ? 'L' : 'J'))))
16880 || (outer_code == GTU
16881 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
16882 || (outer_code == LTU
16883 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
16888 else if ((outer_code == PLUS
16889 && reg_or_add_cint64_operand (x, VOIDmode))
16890 || (outer_code == MINUS
16891 && reg_or_sub_cint64_operand (x, VOIDmode))
16892 || ((outer_code == SET
16893 || outer_code == IOR
16894 || outer_code == XOR)
16896 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
16898 *total = COSTS_N_INSNS (1);
16905 && ((outer_code == AND
16906 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16907 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
16908 || mask64_operand (x, DImode)))
16909 || ((outer_code == IOR || outer_code == XOR)
16910 && CONST_DOUBLE_HIGH (x) == 0
16911 && (CONST_DOUBLE_LOW (x)
16912 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
16917 else if (mode == DImode
16918 && (outer_code == SET
16919 || outer_code == IOR
16920 || outer_code == XOR)
16921 && CONST_DOUBLE_HIGH (x) == 0)
16923 *total = COSTS_N_INSNS (1);
16932 /* When optimizing for size, MEM should be slightly more expensive
16933 than generating address, e.g., (plus (reg) (const)).
16934 L1 cache latency is about two instructions. */
16935 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
16943 if (mode == DFmode)
16945 if (GET_CODE (XEXP (x, 0)) == MULT)
16947 /* FNMA accounted in outer NEG. */
16948 if (outer_code == NEG)
16949 *total = rs6000_cost->dmul - rs6000_cost->fp;
16951 *total = rs6000_cost->dmul;
16954 *total = rs6000_cost->fp;
16956 else if (mode == SFmode)
16958 /* FNMA accounted in outer NEG. */
16959 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
16962 *total = rs6000_cost->fp;
16964 else if (GET_CODE (XEXP (x, 0)) == MULT)
16966 /* The rs6000 doesn't have shift-and-add instructions. */
16967 rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total);
16968 *total += COSTS_N_INSNS (1);
16971 *total = COSTS_N_INSNS (1);
16975 if (mode == DFmode)
16977 if (GET_CODE (XEXP (x, 0)) == MULT)
16979 /* FNMA accounted in outer NEG. */
16980 if (outer_code == NEG)
16983 *total = rs6000_cost->dmul;
16986 *total = rs6000_cost->fp;
16988 else if (mode == SFmode)
16990 /* FNMA accounted in outer NEG. */
16991 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
16994 *total = rs6000_cost->fp;
16996 else if (GET_CODE (XEXP (x, 0)) == MULT)
16998 /* The rs6000 doesn't have shift-and-sub instructions. */
16999 rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total);
17000 *total += COSTS_N_INSNS (1);
17003 *total = COSTS_N_INSNS (1);
17007 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17008 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
17010 if (INTVAL (XEXP (x, 1)) >= -256
17011 && INTVAL (XEXP (x, 1)) <= 255)
17012 *total = rs6000_cost->mulsi_const9;
17014 *total = rs6000_cost->mulsi_const;
17016 /* FMA accounted in outer PLUS/MINUS. */
17017 else if ((mode == DFmode || mode == SFmode)
17018 && (outer_code == PLUS || outer_code == MINUS))
17020 else if (mode == DFmode)
17021 *total = rs6000_cost->dmul;
17022 else if (mode == SFmode)
17023 *total = rs6000_cost->fp;
17024 else if (mode == DImode)
17025 *total = rs6000_cost->muldi;
17027 *total = rs6000_cost->mulsi;
17032 if (FLOAT_MODE_P (mode))
17034 *total = mode == DFmode ? rs6000_cost->ddiv
17035 : rs6000_cost->sdiv;
17042 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17043 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
17045 if (code == DIV || code == MOD)
17047 *total = COSTS_N_INSNS (2);
17050 *total = COSTS_N_INSNS (1);
17054 if (GET_MODE (XEXP (x, 1)) == DImode)
17055 *total = rs6000_cost->divdi;
17057 *total = rs6000_cost->divsi;
17059 /* Add in shift and subtract for MOD. */
17060 if (code == MOD || code == UMOD)
17061 *total += COSTS_N_INSNS (2);
17065 *total = COSTS_N_INSNS (4);
17069 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
17080 *total = COSTS_N_INSNS (1);
17088 /* Handle mul_highpart. */
17089 if (outer_code == TRUNCATE
17090 && GET_CODE (XEXP (x, 0)) == MULT)
17092 if (mode == DImode)
17093 *total = rs6000_cost->muldi;
17095 *total = rs6000_cost->mulsi;
17098 else if (outer_code == AND)
17101 *total = COSTS_N_INSNS (1);
17106 if (GET_CODE (XEXP (x, 0)) == MEM)
17109 *total = COSTS_N_INSNS (1);
17115 if (!FLOAT_MODE_P (mode))
17117 *total = COSTS_N_INSNS (1);
17123 case UNSIGNED_FLOAT:
17127 case FLOAT_TRUNCATE:
17128 *total = rs6000_cost->fp;
17132 switch (XINT (x, 1))
17135 *total = rs6000_cost->fp;
17147 *total = COSTS_N_INSNS (1);
17150 else if (FLOAT_MODE_P (mode)
17151 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
17153 *total = rs6000_cost->fp;
17161 /* Carry bit requires mode == Pmode.
17162 NEG or PLUS already counted so only add one. */
17164 && (outer_code == NEG || outer_code == PLUS))
17166 *total = COSTS_N_INSNS (1);
17169 if (outer_code == SET)
17171 if (XEXP (x, 1) == const0_rtx)
17173 *total = COSTS_N_INSNS (2);
17176 else if (mode == Pmode)
17178 *total = COSTS_N_INSNS (3);
17187 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
17189 *total = COSTS_N_INSNS (2);
17193 if (outer_code == COMPARE)
17207 /* A C expression returning the cost of moving data from a register of class
17208 CLASS1 to one of CLASS2. */
17211 rs6000_register_move_cost (enum machine_mode mode,
17212 enum reg_class from, enum reg_class to)
17214 /* Moves from/to GENERAL_REGS. */
17215 if (reg_classes_intersect_p (to, GENERAL_REGS)
17216 || reg_classes_intersect_p (from, GENERAL_REGS))
17218 if (! reg_classes_intersect_p (to, GENERAL_REGS))
17221 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
17222 return (rs6000_memory_move_cost (mode, from, 0)
17223 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
17225 /* It's more expensive to move CR_REGS than CR0_REGS because of the
17227 else if (from == CR_REGS)
17231 /* A move will cost one instruction per GPR moved. */
17232 return 2 * HARD_REGNO_NREGS (0, mode);
17235 /* Moving between two similar registers is just one instruction. */
17236 else if (reg_classes_intersect_p (to, from))
17237 return mode == TFmode ? 4 : 2;
17239 /* Everything else has to go through GENERAL_REGS. */
17241 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
17242 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
17245 /* A C expressions returning the cost of moving data of MODE from a register to
17249 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
17250 int in ATTRIBUTE_UNUSED)
17252 if (reg_classes_intersect_p (class, GENERAL_REGS))
17253 return 4 * HARD_REGNO_NREGS (0, mode);
17254 else if (reg_classes_intersect_p (class, FLOAT_REGS))
17255 return 4 * HARD_REGNO_NREGS (32, mode);
17256 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
17257 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
17259 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
17262 /* Return an RTX representing where to find the function value of a
17263 function returning MODE. */
17265 rs6000_complex_function_value (enum machine_mode mode)
17267 unsigned int regno;
17269 enum machine_mode inner = GET_MODE_INNER (mode);
17270 unsigned int inner_bytes = GET_MODE_SIZE (inner);
17272 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
17273 regno = FP_ARG_RETURN;
17276 regno = GP_ARG_RETURN;
17278 /* 32-bit is OK since it'll go in r3/r4. */
17279 if (TARGET_32BIT && inner_bytes >= 4)
17280 return gen_rtx_REG (mode, regno);
17283 if (inner_bytes >= 8)
17284 return gen_rtx_REG (mode, regno);
17286 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
17288 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
17289 GEN_INT (inner_bytes));
17290 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
17293 /* Define how to find the value returned by a function.
17294 VALTYPE is the data type of the value (as a tree).
17295 If the precise function being called is known, FUNC is its FUNCTION_DECL;
17296 otherwise, FUNC is 0.
17298 On the SPE, both FPs and vectors are returned in r3.
17300 On RS/6000 an integer value is in r3 and a floating-point value is in
17301 fp1, unless -msoft-float. */
17304 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
17306 enum machine_mode mode;
17307 unsigned int regno;
17309 /* Special handling for structs in darwin64. */
17310 if (rs6000_darwin64_abi
17311 && TYPE_MODE (valtype) == BLKmode
17312 && TREE_CODE (valtype) == RECORD_TYPE
17313 && int_size_in_bytes (valtype) > 0)
17315 CUMULATIVE_ARGS valcum;
17319 valcum.fregno = FP_ARG_MIN_REG;
17320 valcum.vregno = ALTIVEC_ARG_MIN_REG;
17321 /* Do a trial code generation as if this were going to be passed as
17322 an argument; if any part goes in memory, we return NULL. */
17323 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
17326 /* Otherwise fall through to standard ABI rules. */
17329 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
17331 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17332 return gen_rtx_PARALLEL (DImode,
17334 gen_rtx_EXPR_LIST (VOIDmode,
17335 gen_rtx_REG (SImode, GP_ARG_RETURN),
17337 gen_rtx_EXPR_LIST (VOIDmode,
17338 gen_rtx_REG (SImode,
17339 GP_ARG_RETURN + 1),
17343 if ((INTEGRAL_TYPE_P (valtype)
17344 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
17345 || POINTER_TYPE_P (valtype))
17346 mode = TARGET_32BIT ? SImode : DImode;
17348 mode = TYPE_MODE (valtype);
17350 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
17351 regno = FP_ARG_RETURN;
17352 else if (TREE_CODE (valtype) == COMPLEX_TYPE
17353 && targetm.calls.split_complex_arg)
17354 return rs6000_complex_function_value (mode);
17355 else if (TREE_CODE (valtype) == VECTOR_TYPE
17356 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
17357 && ALTIVEC_VECTOR_MODE (mode))
17358 regno = ALTIVEC_ARG_RETURN;
17359 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
17360 && (mode == DFmode || mode == DCmode))
17361 return spe_build_register_parallel (mode, GP_ARG_RETURN);
17363 regno = GP_ARG_RETURN;
17365 return gen_rtx_REG (mode, regno);
17368 /* Define how to find the value returned by a library function
17369 assuming the value has mode MODE. */
17371 rs6000_libcall_value (enum machine_mode mode)
17373 unsigned int regno;
17375 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
17377 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17378 return gen_rtx_PARALLEL (DImode,
17380 gen_rtx_EXPR_LIST (VOIDmode,
17381 gen_rtx_REG (SImode, GP_ARG_RETURN),
17383 gen_rtx_EXPR_LIST (VOIDmode,
17384 gen_rtx_REG (SImode,
17385 GP_ARG_RETURN + 1),
17389 if (GET_MODE_CLASS (mode) == MODE_FLOAT
17390 && TARGET_HARD_FLOAT && TARGET_FPRS)
17391 regno = FP_ARG_RETURN;
17392 else if (ALTIVEC_VECTOR_MODE (mode)
17393 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
17394 regno = ALTIVEC_ARG_RETURN;
17395 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
17396 return rs6000_complex_function_value (mode);
17397 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
17398 && (mode == DFmode || mode == DCmode))
17399 return spe_build_register_parallel (mode, GP_ARG_RETURN);
17401 regno = GP_ARG_RETURN;
17403 return gen_rtx_REG (mode, regno);
17406 /* Define the offset between two registers, FROM to be eliminated and its
17407 replacement TO, at the start of a routine. */
17409 rs6000_initial_elimination_offset (int from, int to)
17411 rs6000_stack_t *info = rs6000_stack_info ();
17412 HOST_WIDE_INT offset;
17414 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
17415 offset = info->push_p ? 0 : -info->total_size;
17416 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
17417 offset = info->total_size;
17418 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
17419 offset = info->push_p ? info->total_size : 0;
17420 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
17428 /* Return true if TYPE is of type __ev64_opaque__. */
17431 is_ev64_opaque_type (tree type)
17434 && (type == opaque_V2SI_type_node
17435 || type == opaque_V2SF_type_node
17436 || type == opaque_p_V2SI_type_node));
17440 rs6000_dwarf_register_span (rtx reg)
17445 && (SPE_VECTOR_MODE (GET_MODE (reg))
17446 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
17451 regno = REGNO (reg);
17453 /* The duality of the SPE register size wreaks all kinds of havoc.
17454 This is a way of distinguishing r0 in 32-bits from r0 in
17457 gen_rtx_PARALLEL (VOIDmode,
17460 gen_rtx_REG (SImode, regno + 1200),
17461 gen_rtx_REG (SImode, regno))
17463 gen_rtx_REG (SImode, regno),
17464 gen_rtx_REG (SImode, regno + 1200)));
17467 /* Map internal gcc register numbers to DWARF2 register numbers. */
17470 rs6000_dbx_register_number (unsigned int regno)
17472 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
17474 if (regno == MQ_REGNO)
17476 if (regno == LINK_REGISTER_REGNUM)
17478 if (regno == COUNT_REGISTER_REGNUM)
17480 if (CR_REGNO_P (regno))
17481 return regno - CR0_REGNO + 86;
17482 if (regno == XER_REGNO)
17484 if (ALTIVEC_REGNO_P (regno))
17485 return regno - FIRST_ALTIVEC_REGNO + 1124;
17486 if (regno == VRSAVE_REGNO)
17488 if (regno == VSCR_REGNO)
17490 if (regno == SPE_ACC_REGNO)
17492 if (regno == SPEFSCR_REGNO)
17494 /* SPE high reg number. We get these values of regno from
17495 rs6000_dwarf_register_span. */
17496 if (regno >= 1200 && regno < 1232)
17502 /* target hook eh_return_filter_mode */
17503 static enum machine_mode
17504 rs6000_eh_return_filter_mode (void)
17506 return TARGET_32BIT ? SImode : word_mode;
17509 /* Target hook for vector_mode_supported_p. */
17511 rs6000_vector_mode_supported_p (enum machine_mode mode)
17514 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
17517 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
17524 /* Target hook for invalid_arg_for_unprototyped_fn. */
17525 static const char *
17526 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
17528 return (!rs6000_darwin64_abi
17530 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
17531 && (funcdecl == NULL_TREE
17532 || (TREE_CODE (funcdecl) == FUNCTION_DECL
17533 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
17534 ? N_("AltiVec argument passed to unprototyped function")
17538 #include "gt-rs6000.h"