1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
57 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
60 #include "gstab.h" /* for N_SLINE */
63 #ifndef TARGET_NO_PROTOTYPE
64 #define TARGET_NO_PROTOTYPE 0
67 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
68 #define EASY_VECTOR_15_ADD_SELF(n) ((n) >= 0x10 && (n) <= 0x1e && !((n) & 1))
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack {
75 int first_gp_reg_save; /* first callee saved GP register used */
76 int first_fp_reg_save; /* first callee saved FP register used */
77 int first_altivec_reg_save; /* first callee saved AltiVec register used */
78 int lr_save_p; /* true if the link reg needs to be saved */
79 int cr_save_p; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask; /* mask of vec registers to save */
81 int toc_save_p; /* true if the TOC needs to be saved */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int toc_save_offset; /* offset to save the TOC pointer */
95 int varargs_save_offset; /* offset to save the varargs registers */
96 int ehrd_offset; /* offset to EH return data */
97 int reg_size; /* register size (4 or 8) */
98 int varargs_size; /* size to hold V.4 args passed in regs */
99 HOST_WIDE_INT vars_size; /* variable save area size */
100 int parm_size; /* outgoing parameter size */
101 int save_size; /* save area size */
102 int fixed_size; /* fixed size of stack frame */
103 int gp_size; /* size of saved GP registers */
104 int fp_size; /* size of saved FP registers */
105 int altivec_size; /* size of saved AltiVec registers */
106 int cr_size; /* size to hold CR if not in save_size */
107 int lr_size; /* size to hold LR if not in save_size */
108 int vrsave_size; /* size to hold VRSAVE if not in save_size */
109 int altivec_padding_size; /* size of altivec alignment padding if
111 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
112 int spe_padding_size;
113 int toc_size; /* size to hold TOC if not in save_size */
114 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
115 int spe_64bit_regs_used;
118 /* Target cpu type */
120 enum processor_type rs6000_cpu;
121 struct rs6000_cpu_select rs6000_select[3] =
123 /* switch name, tune arch */
124 { (const char *)0, "--with-cpu=", 1, 1 },
125 { (const char *)0, "-mcpu=", 1, 1 },
126 { (const char *)0, "-mtune=", 1, 0 },
129 /* Always emit branch hint bits. */
130 static GTY(()) bool rs6000_always_hint;
132 /* Schedule instructions for group formation. */
133 static GTY(()) bool rs6000_sched_groups;
135 /* Support adjust_priority scheduler hook
136 and -mprioritize-restricted-insns= option. */
137 const char *rs6000_sched_restricted_insns_priority_str;
138 int rs6000_sched_restricted_insns_priority;
140 /* Support for -msched-costly-dep option. */
141 const char *rs6000_sched_costly_dep_str;
142 enum rs6000_dependence_cost rs6000_sched_costly_dep;
144 /* Support for -minsert-sched-nops option. */
145 const char *rs6000_sched_insert_nops_str;
146 enum rs6000_nop_insertion rs6000_sched_insert_nops;
148 /* Support targetm.vectorize.builtin_mask_for_load. */
149 static GTY(()) tree altivec_builtin_mask_for_load;
151 /* Size of long double */
152 const char *rs6000_long_double_size_string;
153 int rs6000_long_double_type_size;
155 /* Whether -mabi=altivec has appeared */
156 int rs6000_altivec_abi;
158 /* Whether VRSAVE instructions should be generated. */
159 int rs6000_altivec_vrsave;
161 /* String from -mvrsave= option. */
162 const char *rs6000_altivec_vrsave_string;
164 /* Nonzero if we want SPE ABI extensions. */
167 /* Whether isel instructions should be generated. */
170 /* Whether SPE simd instructions should be generated. */
173 /* Nonzero if floating point operations are done in the GPRs. */
174 int rs6000_float_gprs = 0;
176 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
177 int rs6000_darwin64_abi;
179 /* String from -mfloat-gprs=. */
180 const char *rs6000_float_gprs_string;
182 /* String from -misel=. */
183 const char *rs6000_isel_string;
185 /* String from -mspe=. */
186 const char *rs6000_spe_string;
188 /* Set to nonzero once AIX common-mode calls have been defined. */
189 static GTY(()) int common_mode_defined;
191 /* Save information from a "cmpxx" operation until the branch or scc is
193 rtx rs6000_compare_op0, rs6000_compare_op1;
194 int rs6000_compare_fp_p;
196 /* Label number of label created for -mrelocatable, to call to so we can
197 get the address of the GOT section */
198 int rs6000_pic_labelno;
201 /* Which abi to adhere to */
202 const char *rs6000_abi_name;
204 /* Semantics of the small data area */
205 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
207 /* Which small data model to use */
208 const char *rs6000_sdata_name = (char *)0;
210 /* Counter for labels which are to be placed in .fixup. */
211 int fixuplabelno = 0;
214 /* Bit size of immediate TLS offsets and string from which it is decoded. */
215 int rs6000_tls_size = 32;
216 const char *rs6000_tls_size_string;
218 /* ABI enumeration available for subtarget to use. */
219 enum rs6000_abi rs6000_current_abi;
221 /* ABI string from -mabi= option. */
222 const char *rs6000_abi_string;
224 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
228 const char *rs6000_debug_name;
229 int rs6000_debug_stack; /* debug stack applications */
230 int rs6000_debug_arg; /* debug argument handling */
232 /* Value is TRUE if register/mode pair is accepatable. */
233 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
236 static GTY(()) tree opaque_V2SI_type_node;
237 static GTY(()) tree opaque_V2SF_type_node;
238 static GTY(()) tree opaque_p_V2SI_type_node;
239 static GTY(()) tree V16QI_type_node;
240 static GTY(()) tree V2SI_type_node;
241 static GTY(()) tree V2SF_type_node;
242 static GTY(()) tree V4HI_type_node;
243 static GTY(()) tree V4SI_type_node;
244 static GTY(()) tree V4SF_type_node;
245 static GTY(()) tree V8HI_type_node;
246 static GTY(()) tree unsigned_V16QI_type_node;
247 static GTY(()) tree unsigned_V8HI_type_node;
248 static GTY(()) tree unsigned_V4SI_type_node;
249 static GTY(()) tree bool_char_type_node; /* __bool char */
250 static GTY(()) tree bool_short_type_node; /* __bool short */
251 static GTY(()) tree bool_int_type_node; /* __bool int */
252 static GTY(()) tree pixel_type_node; /* __pixel */
253 static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */
254 static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */
255 static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */
256 static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */
258 int rs6000_warn_altivec_long = 1; /* On by default. */
259 const char *rs6000_warn_altivec_long_switch;
261 const char *rs6000_traceback_name;
263 traceback_default = 0,
269 /* Flag to say the TOC is initialized */
271 char toc_label_name[10];
273 /* Alias set for saves and restores from the rs6000 stack. */
274 static GTY(()) int rs6000_sr_alias_set;
276 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
277 The only place that looks at this is rs6000_set_default_type_attributes;
278 everywhere else should rely on the presence or absence of a longcall
279 attribute on the function declaration. Exception: init_cumulative_args
280 looks at it too, for libcalls. */
281 int rs6000_default_long_calls;
282 const char *rs6000_longcall_switch;
284 /* Control alignment for fields within structures. */
285 /* String from -malign-XXXXX. */
286 const char *rs6000_alignment_string;
287 int rs6000_alignment_flags;
289 struct builtin_description
291 /* mask is not const because we're going to alter it below. This
292 nonsense will go away when we rewrite the -march infrastructure
293 to give us more target flag bits. */
295 const enum insn_code icode;
296 const char *const name;
297 const enum rs6000_builtins code;
300 /* Target cpu costs. */
302 struct processor_costs {
303 const int mulsi; /* cost of SImode multiplication. */
304 const int mulsi_const; /* cost of SImode multiplication by constant. */
305 const int mulsi_const9; /* cost of SImode mult by short constant. */
306 const int muldi; /* cost of DImode multiplication. */
307 const int divsi; /* cost of SImode division. */
308 const int divdi; /* cost of DImode division. */
309 const int fp; /* cost of simple SFmode and DFmode insns. */
310 const int dmul; /* cost of DFmode multiplication (and fmadd). */
311 const int sdiv; /* cost of SFmode division (fdivs). */
312 const int ddiv; /* cost of DFmode division (fdiv). */
315 const struct processor_costs *rs6000_cost;
317 /* Processor costs (relative to an add) */
319 /* Instruction size costs on 32bit processors. */
321 struct processor_costs size32_cost = {
322 COSTS_N_INSNS (1), /* mulsi */
323 COSTS_N_INSNS (1), /* mulsi_const */
324 COSTS_N_INSNS (1), /* mulsi_const9 */
325 COSTS_N_INSNS (1), /* muldi */
326 COSTS_N_INSNS (1), /* divsi */
327 COSTS_N_INSNS (1), /* divdi */
328 COSTS_N_INSNS (1), /* fp */
329 COSTS_N_INSNS (1), /* dmul */
330 COSTS_N_INSNS (1), /* sdiv */
331 COSTS_N_INSNS (1), /* ddiv */
334 /* Instruction size costs on 64bit processors. */
336 struct processor_costs size64_cost = {
337 COSTS_N_INSNS (1), /* mulsi */
338 COSTS_N_INSNS (1), /* mulsi_const */
339 COSTS_N_INSNS (1), /* mulsi_const9 */
340 COSTS_N_INSNS (1), /* muldi */
341 COSTS_N_INSNS (1), /* divsi */
342 COSTS_N_INSNS (1), /* divdi */
343 COSTS_N_INSNS (1), /* fp */
344 COSTS_N_INSNS (1), /* dmul */
345 COSTS_N_INSNS (1), /* sdiv */
346 COSTS_N_INSNS (1), /* ddiv */
349 /* Instruction costs on RIOS1 processors. */
351 struct processor_costs rios1_cost = {
352 COSTS_N_INSNS (5), /* mulsi */
353 COSTS_N_INSNS (4), /* mulsi_const */
354 COSTS_N_INSNS (3), /* mulsi_const9 */
355 COSTS_N_INSNS (5), /* muldi */
356 COSTS_N_INSNS (19), /* divsi */
357 COSTS_N_INSNS (19), /* divdi */
358 COSTS_N_INSNS (2), /* fp */
359 COSTS_N_INSNS (2), /* dmul */
360 COSTS_N_INSNS (19), /* sdiv */
361 COSTS_N_INSNS (19), /* ddiv */
364 /* Instruction costs on RIOS2 processors. */
366 struct processor_costs rios2_cost = {
367 COSTS_N_INSNS (2), /* mulsi */
368 COSTS_N_INSNS (2), /* mulsi_const */
369 COSTS_N_INSNS (2), /* mulsi_const9 */
370 COSTS_N_INSNS (2), /* muldi */
371 COSTS_N_INSNS (13), /* divsi */
372 COSTS_N_INSNS (13), /* divdi */
373 COSTS_N_INSNS (2), /* fp */
374 COSTS_N_INSNS (2), /* dmul */
375 COSTS_N_INSNS (17), /* sdiv */
376 COSTS_N_INSNS (17), /* ddiv */
379 /* Instruction costs on RS64A processors. */
381 struct processor_costs rs64a_cost = {
382 COSTS_N_INSNS (20), /* mulsi */
383 COSTS_N_INSNS (12), /* mulsi_const */
384 COSTS_N_INSNS (8), /* mulsi_const9 */
385 COSTS_N_INSNS (34), /* muldi */
386 COSTS_N_INSNS (65), /* divsi */
387 COSTS_N_INSNS (67), /* divdi */
388 COSTS_N_INSNS (4), /* fp */
389 COSTS_N_INSNS (4), /* dmul */
390 COSTS_N_INSNS (31), /* sdiv */
391 COSTS_N_INSNS (31), /* ddiv */
394 /* Instruction costs on MPCCORE processors. */
396 struct processor_costs mpccore_cost = {
397 COSTS_N_INSNS (2), /* mulsi */
398 COSTS_N_INSNS (2), /* mulsi_const */
399 COSTS_N_INSNS (2), /* mulsi_const9 */
400 COSTS_N_INSNS (2), /* muldi */
401 COSTS_N_INSNS (6), /* divsi */
402 COSTS_N_INSNS (6), /* divdi */
403 COSTS_N_INSNS (4), /* fp */
404 COSTS_N_INSNS (5), /* dmul */
405 COSTS_N_INSNS (10), /* sdiv */
406 COSTS_N_INSNS (17), /* ddiv */
409 /* Instruction costs on PPC403 processors. */
411 struct processor_costs ppc403_cost = {
412 COSTS_N_INSNS (4), /* mulsi */
413 COSTS_N_INSNS (4), /* mulsi_const */
414 COSTS_N_INSNS (4), /* mulsi_const9 */
415 COSTS_N_INSNS (4), /* muldi */
416 COSTS_N_INSNS (33), /* divsi */
417 COSTS_N_INSNS (33), /* divdi */
418 COSTS_N_INSNS (11), /* fp */
419 COSTS_N_INSNS (11), /* dmul */
420 COSTS_N_INSNS (11), /* sdiv */
421 COSTS_N_INSNS (11), /* ddiv */
424 /* Instruction costs on PPC405 processors. */
426 struct processor_costs ppc405_cost = {
427 COSTS_N_INSNS (5), /* mulsi */
428 COSTS_N_INSNS (4), /* mulsi_const */
429 COSTS_N_INSNS (3), /* mulsi_const9 */
430 COSTS_N_INSNS (5), /* muldi */
431 COSTS_N_INSNS (35), /* divsi */
432 COSTS_N_INSNS (35), /* divdi */
433 COSTS_N_INSNS (11), /* fp */
434 COSTS_N_INSNS (11), /* dmul */
435 COSTS_N_INSNS (11), /* sdiv */
436 COSTS_N_INSNS (11), /* ddiv */
439 /* Instruction costs on PPC440 processors. */
441 struct processor_costs ppc440_cost = {
442 COSTS_N_INSNS (3), /* mulsi */
443 COSTS_N_INSNS (2), /* mulsi_const */
444 COSTS_N_INSNS (2), /* mulsi_const9 */
445 COSTS_N_INSNS (3), /* muldi */
446 COSTS_N_INSNS (34), /* divsi */
447 COSTS_N_INSNS (34), /* divdi */
448 COSTS_N_INSNS (5), /* fp */
449 COSTS_N_INSNS (5), /* dmul */
450 COSTS_N_INSNS (19), /* sdiv */
451 COSTS_N_INSNS (33), /* ddiv */
454 /* Instruction costs on PPC601 processors. */
456 struct processor_costs ppc601_cost = {
457 COSTS_N_INSNS (5), /* mulsi */
458 COSTS_N_INSNS (5), /* mulsi_const */
459 COSTS_N_INSNS (5), /* mulsi_const9 */
460 COSTS_N_INSNS (5), /* muldi */
461 COSTS_N_INSNS (36), /* divsi */
462 COSTS_N_INSNS (36), /* divdi */
463 COSTS_N_INSNS (4), /* fp */
464 COSTS_N_INSNS (5), /* dmul */
465 COSTS_N_INSNS (17), /* sdiv */
466 COSTS_N_INSNS (31), /* ddiv */
469 /* Instruction costs on PPC603 processors. */
471 struct processor_costs ppc603_cost = {
472 COSTS_N_INSNS (5), /* mulsi */
473 COSTS_N_INSNS (3), /* mulsi_const */
474 COSTS_N_INSNS (2), /* mulsi_const9 */
475 COSTS_N_INSNS (5), /* muldi */
476 COSTS_N_INSNS (37), /* divsi */
477 COSTS_N_INSNS (37), /* divdi */
478 COSTS_N_INSNS (3), /* fp */
479 COSTS_N_INSNS (4), /* dmul */
480 COSTS_N_INSNS (18), /* sdiv */
481 COSTS_N_INSNS (33), /* ddiv */
484 /* Instruction costs on PPC604 processors. */
486 struct processor_costs ppc604_cost = {
487 COSTS_N_INSNS (4), /* mulsi */
488 COSTS_N_INSNS (4), /* mulsi_const */
489 COSTS_N_INSNS (4), /* mulsi_const9 */
490 COSTS_N_INSNS (4), /* muldi */
491 COSTS_N_INSNS (20), /* divsi */
492 COSTS_N_INSNS (20), /* divdi */
493 COSTS_N_INSNS (3), /* fp */
494 COSTS_N_INSNS (3), /* dmul */
495 COSTS_N_INSNS (18), /* sdiv */
496 COSTS_N_INSNS (32), /* ddiv */
499 /* Instruction costs on PPC604e processors. */
501 struct processor_costs ppc604e_cost = {
502 COSTS_N_INSNS (2), /* mulsi */
503 COSTS_N_INSNS (2), /* mulsi_const */
504 COSTS_N_INSNS (2), /* mulsi_const9 */
505 COSTS_N_INSNS (2), /* muldi */
506 COSTS_N_INSNS (20), /* divsi */
507 COSTS_N_INSNS (20), /* divdi */
508 COSTS_N_INSNS (3), /* fp */
509 COSTS_N_INSNS (3), /* dmul */
510 COSTS_N_INSNS (18), /* sdiv */
511 COSTS_N_INSNS (32), /* ddiv */
514 /* Instruction costs on PPC620 processors. */
516 struct processor_costs ppc620_cost = {
517 COSTS_N_INSNS (5), /* mulsi */
518 COSTS_N_INSNS (4), /* mulsi_const */
519 COSTS_N_INSNS (3), /* mulsi_const9 */
520 COSTS_N_INSNS (7), /* muldi */
521 COSTS_N_INSNS (21), /* divsi */
522 COSTS_N_INSNS (37), /* divdi */
523 COSTS_N_INSNS (3), /* fp */
524 COSTS_N_INSNS (3), /* dmul */
525 COSTS_N_INSNS (18), /* sdiv */
526 COSTS_N_INSNS (32), /* ddiv */
529 /* Instruction costs on PPC630 processors. */
531 struct processor_costs ppc630_cost = {
532 COSTS_N_INSNS (5), /* mulsi */
533 COSTS_N_INSNS (4), /* mulsi_const */
534 COSTS_N_INSNS (3), /* mulsi_const9 */
535 COSTS_N_INSNS (7), /* muldi */
536 COSTS_N_INSNS (21), /* divsi */
537 COSTS_N_INSNS (37), /* divdi */
538 COSTS_N_INSNS (3), /* fp */
539 COSTS_N_INSNS (3), /* dmul */
540 COSTS_N_INSNS (17), /* sdiv */
541 COSTS_N_INSNS (21), /* ddiv */
544 /* Instruction costs on PPC750 and PPC7400 processors. */
546 struct processor_costs ppc750_cost = {
547 COSTS_N_INSNS (5), /* mulsi */
548 COSTS_N_INSNS (3), /* mulsi_const */
549 COSTS_N_INSNS (2), /* mulsi_const9 */
550 COSTS_N_INSNS (5), /* muldi */
551 COSTS_N_INSNS (17), /* divsi */
552 COSTS_N_INSNS (17), /* divdi */
553 COSTS_N_INSNS (3), /* fp */
554 COSTS_N_INSNS (3), /* dmul */
555 COSTS_N_INSNS (17), /* sdiv */
556 COSTS_N_INSNS (31), /* ddiv */
559 /* Instruction costs on PPC7450 processors. */
561 struct processor_costs ppc7450_cost = {
562 COSTS_N_INSNS (4), /* mulsi */
563 COSTS_N_INSNS (3), /* mulsi_const */
564 COSTS_N_INSNS (3), /* mulsi_const9 */
565 COSTS_N_INSNS (4), /* muldi */
566 COSTS_N_INSNS (23), /* divsi */
567 COSTS_N_INSNS (23), /* divdi */
568 COSTS_N_INSNS (5), /* fp */
569 COSTS_N_INSNS (5), /* dmul */
570 COSTS_N_INSNS (21), /* sdiv */
571 COSTS_N_INSNS (35), /* ddiv */
574 /* Instruction costs on PPC8540 processors. */
576 struct processor_costs ppc8540_cost = {
577 COSTS_N_INSNS (4), /* mulsi */
578 COSTS_N_INSNS (4), /* mulsi_const */
579 COSTS_N_INSNS (4), /* mulsi_const9 */
580 COSTS_N_INSNS (4), /* muldi */
581 COSTS_N_INSNS (19), /* divsi */
582 COSTS_N_INSNS (19), /* divdi */
583 COSTS_N_INSNS (4), /* fp */
584 COSTS_N_INSNS (4), /* dmul */
585 COSTS_N_INSNS (29), /* sdiv */
586 COSTS_N_INSNS (29), /* ddiv */
589 /* Instruction costs on POWER4 and POWER5 processors. */
591 struct processor_costs power4_cost = {
592 COSTS_N_INSNS (3), /* mulsi */
593 COSTS_N_INSNS (2), /* mulsi_const */
594 COSTS_N_INSNS (2), /* mulsi_const9 */
595 COSTS_N_INSNS (4), /* muldi */
596 COSTS_N_INSNS (18), /* divsi */
597 COSTS_N_INSNS (34), /* divdi */
598 COSTS_N_INSNS (3), /* fp */
599 COSTS_N_INSNS (3), /* dmul */
600 COSTS_N_INSNS (17), /* sdiv */
601 COSTS_N_INSNS (17), /* ddiv */
605 static bool rs6000_function_ok_for_sibcall (tree, tree);
606 static int num_insns_constant_wide (HOST_WIDE_INT);
607 static void validate_condition_mode (enum rtx_code, enum machine_mode);
608 static rtx rs6000_generate_compare (enum rtx_code);
609 static void rs6000_maybe_dead (rtx);
610 static void rs6000_emit_stack_tie (void);
611 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
612 static rtx spe_synthesize_frame_save (rtx);
613 static bool spe_func_has_64bit_regs_p (void);
614 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
616 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
617 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
618 static unsigned rs6000_hash_constant (rtx);
619 static unsigned toc_hash_function (const void *);
620 static int toc_hash_eq (const void *, const void *);
621 static int constant_pool_expr_1 (rtx, int *, int *);
622 static bool constant_pool_expr_p (rtx);
623 static bool toc_relative_expr_p (rtx);
624 static bool legitimate_small_data_p (enum machine_mode, rtx);
625 static bool legitimate_indexed_address_p (rtx, int);
626 static bool legitimate_indirect_address_p (rtx, int);
627 static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode);
628 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
629 static struct machine_function * rs6000_init_machine_status (void);
630 static bool rs6000_assemble_integer (rtx, unsigned int, int);
631 #ifdef HAVE_GAS_HIDDEN
632 static void rs6000_assemble_visibility (tree, int);
634 static int rs6000_ra_ever_killed (void);
635 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
636 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
637 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
638 static const char *rs6000_mangle_fundamental_type (tree);
639 extern const struct attribute_spec rs6000_attribute_table[];
640 static void rs6000_set_default_type_attributes (tree);
641 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
642 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
643 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
645 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
646 static bool rs6000_return_in_memory (tree, tree);
647 static void rs6000_file_start (void);
649 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
650 static void rs6000_elf_asm_out_constructor (rtx, int);
651 static void rs6000_elf_asm_out_destructor (rtx, int);
652 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
653 static void rs6000_elf_unique_section (tree, int);
654 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
655 unsigned HOST_WIDE_INT);
656 static void rs6000_elf_encode_section_info (tree, rtx, int)
658 static bool rs6000_elf_in_small_data_p (tree);
661 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
662 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
663 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
664 static void rs6000_xcoff_unique_section (tree, int);
665 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
666 unsigned HOST_WIDE_INT);
667 static const char * rs6000_xcoff_strip_name_encoding (const char *);
668 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
669 static void rs6000_xcoff_file_start (void);
670 static void rs6000_xcoff_file_end (void);
673 static bool rs6000_binds_local_p (tree);
675 static int rs6000_variable_issue (FILE *, int, rtx, int);
676 static bool rs6000_rtx_costs (rtx, int, int, int *);
677 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
678 static bool is_microcoded_insn (rtx);
679 static int is_dispatch_slot_restricted (rtx);
680 static bool is_cracked_insn (rtx);
681 static bool is_branch_slot_insn (rtx);
682 static int rs6000_adjust_priority (rtx, int);
683 static int rs6000_issue_rate (void);
684 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
685 static rtx get_next_active_insn (rtx, rtx);
686 static bool insn_terminates_group_p (rtx , enum group_termination);
687 static bool is_costly_group (rtx *, rtx);
688 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
689 static int redefine_groups (FILE *, int, rtx, rtx);
690 static int pad_groups (FILE *, int, rtx, rtx);
691 static void rs6000_sched_finish (FILE *, int);
692 static int rs6000_use_sched_lookahead (void);
693 static tree rs6000_builtin_mask_for_load (void);
695 static void rs6000_init_builtins (void);
696 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
697 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
698 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
699 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
700 static void altivec_init_builtins (void);
701 static void rs6000_common_init_builtins (void);
702 static void rs6000_init_libfuncs (void);
704 static void enable_mask_for_builtins (struct builtin_description *, int,
705 enum rs6000_builtins,
706 enum rs6000_builtins);
707 static tree build_opaque_vector_type (tree, int);
708 static void spe_init_builtins (void);
709 static rtx spe_expand_builtin (tree, rtx, bool *);
710 static rtx spe_expand_stv_builtin (enum insn_code, tree);
711 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
712 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
713 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
714 static rs6000_stack_t *rs6000_stack_info (void);
715 static void debug_stack_info (rs6000_stack_t *);
717 static rtx altivec_expand_builtin (tree, rtx, bool *);
718 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
719 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
720 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
721 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
722 static rtx altivec_expand_predicate_builtin (enum insn_code,
723 const char *, tree, rtx);
724 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
725 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
726 static void rs6000_parse_abi_options (void);
727 static void rs6000_parse_alignment_option (void);
728 static void rs6000_parse_tls_size_option (void);
729 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
730 static void rs6000_parse_float_gprs_option (void);
731 static int first_altivec_reg_to_save (void);
732 static unsigned int compute_vrsave_mask (void);
733 static void compute_save_world_info(rs6000_stack_t *info_ptr);
734 static void is_altivec_return_reg (rtx, void *);
735 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
736 int easy_vector_constant (rtx, enum machine_mode);
737 static int easy_vector_same (rtx, enum machine_mode);
738 static int easy_vector_splat_const (int, enum machine_mode);
739 static bool is_ev64_opaque_type (tree);
740 static rtx rs6000_dwarf_register_span (rtx);
741 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
742 static rtx rs6000_tls_get_addr (void);
743 static rtx rs6000_got_sym (void);
744 static inline int rs6000_tls_symbol_ref_1 (rtx *, void *);
745 static const char *rs6000_get_some_local_dynamic_name (void);
746 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
747 static rtx rs6000_complex_function_value (enum machine_mode);
748 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
749 enum machine_mode, tree);
750 static rtx rs6000_darwin64_function_arg (CUMULATIVE_ARGS *,
751 enum machine_mode, tree, int);
752 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
753 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
754 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
755 enum machine_mode, tree,
757 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
760 static void macho_branch_islands (void);
761 static void add_compiler_branch_island (tree, tree, int);
762 static int no_previous_def (tree function_name);
763 static tree get_prev_label (tree function_name);
764 static void rs6000_darwin_file_start (void);
767 static tree rs6000_build_builtin_va_list (void);
768 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
769 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
770 static bool rs6000_vector_mode_supported_p (enum machine_mode);
771 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
773 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
775 static int get_vsel_insn (enum machine_mode);
776 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
779 const int INSN_NOT_AVAILABLE = -1;
780 static enum machine_mode rs6000_eh_return_filter_mode (void);
782 /* Hash table stuff for keeping track of TOC entries. */
784 struct toc_hash_struct GTY(())
786 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
787 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
789 enum machine_mode key_mode;
793 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
795 /* Default register names. */
796 char rs6000_reg_names[][8] =
798 "0", "1", "2", "3", "4", "5", "6", "7",
799 "8", "9", "10", "11", "12", "13", "14", "15",
800 "16", "17", "18", "19", "20", "21", "22", "23",
801 "24", "25", "26", "27", "28", "29", "30", "31",
802 "0", "1", "2", "3", "4", "5", "6", "7",
803 "8", "9", "10", "11", "12", "13", "14", "15",
804 "16", "17", "18", "19", "20", "21", "22", "23",
805 "24", "25", "26", "27", "28", "29", "30", "31",
806 "mq", "lr", "ctr","ap",
807 "0", "1", "2", "3", "4", "5", "6", "7",
809 /* AltiVec registers. */
810 "0", "1", "2", "3", "4", "5", "6", "7",
811 "8", "9", "10", "11", "12", "13", "14", "15",
812 "16", "17", "18", "19", "20", "21", "22", "23",
813 "24", "25", "26", "27", "28", "29", "30", "31",
819 #ifdef TARGET_REGNAMES
820 static const char alt_reg_names[][8] =
822 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
823 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
824 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
825 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
826 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
827 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
828 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
829 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
830 "mq", "lr", "ctr", "ap",
831 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
833 /* AltiVec registers. */
834 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
835 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
836 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
837 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
844 #ifndef MASK_STRICT_ALIGN
845 #define MASK_STRICT_ALIGN 0
847 #ifndef TARGET_PROFILE_KERNEL
848 #define TARGET_PROFILE_KERNEL 0
851 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
852 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
854 /* Return 1 for a symbol ref for a thread-local storage symbol. */
855 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
856 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
858 /* Initialize the GCC target structure. */
859 #undef TARGET_ATTRIBUTE_TABLE
860 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
861 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
862 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
864 #undef TARGET_ASM_ALIGNED_DI_OP
865 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
867 /* Default unaligned ops are only provided for ELF. Find the ops needed
868 for non-ELF systems. */
869 #ifndef OBJECT_FORMAT_ELF
871 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
873 #undef TARGET_ASM_UNALIGNED_HI_OP
874 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
875 #undef TARGET_ASM_UNALIGNED_SI_OP
876 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
877 #undef TARGET_ASM_UNALIGNED_DI_OP
878 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
881 #undef TARGET_ASM_UNALIGNED_HI_OP
882 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
883 #undef TARGET_ASM_UNALIGNED_SI_OP
884 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
885 #undef TARGET_ASM_UNALIGNED_DI_OP
886 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
887 #undef TARGET_ASM_ALIGNED_DI_OP
888 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
892 /* This hook deals with fixups for relocatable code and DI-mode objects
894 #undef TARGET_ASM_INTEGER
895 #define TARGET_ASM_INTEGER rs6000_assemble_integer
897 #ifdef HAVE_GAS_HIDDEN
898 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
899 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
902 #undef TARGET_HAVE_TLS
903 #define TARGET_HAVE_TLS HAVE_AS_TLS
905 #undef TARGET_CANNOT_FORCE_CONST_MEM
906 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
908 #undef TARGET_ASM_FUNCTION_PROLOGUE
909 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
910 #undef TARGET_ASM_FUNCTION_EPILOGUE
911 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
913 #undef TARGET_SCHED_VARIABLE_ISSUE
914 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
916 #undef TARGET_SCHED_ISSUE_RATE
917 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
918 #undef TARGET_SCHED_ADJUST_COST
919 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
920 #undef TARGET_SCHED_ADJUST_PRIORITY
921 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
922 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
923 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
924 #undef TARGET_SCHED_FINISH
925 #define TARGET_SCHED_FINISH rs6000_sched_finish
927 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
928 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
930 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
931 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
933 #undef TARGET_INIT_BUILTINS
934 #define TARGET_INIT_BUILTINS rs6000_init_builtins
936 #undef TARGET_EXPAND_BUILTIN
937 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
939 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
940 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
942 #undef TARGET_INIT_LIBFUNCS
943 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
946 #undef TARGET_BINDS_LOCAL_P
947 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
950 #undef TARGET_ASM_OUTPUT_MI_THUNK
951 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
953 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
954 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
956 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
957 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
959 #undef TARGET_RTX_COSTS
960 #define TARGET_RTX_COSTS rs6000_rtx_costs
961 #undef TARGET_ADDRESS_COST
962 #define TARGET_ADDRESS_COST hook_int_rtx_0
964 #undef TARGET_VECTOR_OPAQUE_P
965 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
967 #undef TARGET_DWARF_REGISTER_SPAN
968 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
970 /* On rs6000, function arguments are promoted, as are function return
972 #undef TARGET_PROMOTE_FUNCTION_ARGS
973 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
974 #undef TARGET_PROMOTE_FUNCTION_RETURN
975 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
977 #undef TARGET_RETURN_IN_MEMORY
978 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
980 #undef TARGET_SETUP_INCOMING_VARARGS
981 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
983 /* Always strict argument naming on rs6000. */
984 #undef TARGET_STRICT_ARGUMENT_NAMING
985 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
986 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
987 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
988 #undef TARGET_SPLIT_COMPLEX_ARG
989 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
990 #undef TARGET_MUST_PASS_IN_STACK
991 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
992 #undef TARGET_PASS_BY_REFERENCE
993 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
995 #undef TARGET_BUILD_BUILTIN_VA_LIST
996 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
998 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
999 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1001 #undef TARGET_EH_RETURN_FILTER_MODE
1002 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1004 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1005 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1007 struct gcc_target targetm = TARGET_INITIALIZER;
1010 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1013 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1015 /* The GPRs can hold any mode, but values bigger than one register
1016 cannot go past R31. */
1017 if (INT_REGNO_P (regno))
1018 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1020 /* The float registers can only hold floating modes and DImode. */
1021 if (FP_REGNO_P (regno))
1023 (GET_MODE_CLASS (mode) == MODE_FLOAT
1024 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1025 || (GET_MODE_CLASS (mode) == MODE_INT
1026 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1028 /* The CR register can only hold CC modes. */
1029 if (CR_REGNO_P (regno))
1030 return GET_MODE_CLASS (mode) == MODE_CC;
1032 if (XER_REGNO_P (regno))
1033 return mode == PSImode;
1035 /* AltiVec only in AldyVec registers. */
1036 if (ALTIVEC_REGNO_P (regno))
1037 return ALTIVEC_VECTOR_MODE (mode);
1039 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1040 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1043 /* We cannot put TImode anywhere except general register and it must be
1044 able to fit within the register set. */
1046 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1049 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1051 rs6000_init_hard_regno_mode_ok (void)
1055 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1056 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1057 if (rs6000_hard_regno_mode_ok (r, m))
1058 rs6000_hard_regno_mode_ok_p[m][r] = true;
1061 /* If not otherwise specified by a target, make 'long double' equivalent to
1064 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1065 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1068 /* Override command line options. Mostly we process the processor
1069 type and sometimes adjust other TARGET_ options. */
1072 rs6000_override_options (const char *default_cpu)
1075 struct rs6000_cpu_select *ptr;
1078 /* Simplifications for entries below. */
1081 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1082 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1085 /* This table occasionally claims that a processor does not support
1086 a particular feature even though it does, but the feature is slower
1087 than the alternative. Thus, it shouldn't be relied on as a
1088 complete description of the processor's support.
1090 Please keep this list in order, and don't forget to update the
1091 documentation in invoke.texi when adding a new processor or
1095 const char *const name; /* Canonical processor name. */
1096 const enum processor_type processor; /* Processor type enum value. */
1097 const int target_enable; /* Target flags to enable. */
1098 } const processor_target_table[]
1099 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1100 {"403", PROCESSOR_PPC403,
1101 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1102 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1103 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1104 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1105 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1106 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1107 {"601", PROCESSOR_PPC601,
1108 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1109 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1110 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1111 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1112 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1113 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1114 {"620", PROCESSOR_PPC620,
1115 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1116 {"630", PROCESSOR_PPC630,
1117 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1118 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1119 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1120 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1121 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1122 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1123 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1124 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1125 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1126 /* 8548 has a dummy entry for now. */
1127 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1128 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1129 {"970", PROCESSOR_POWER4,
1130 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1131 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1132 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1133 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1134 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1135 {"G5", PROCESSOR_POWER4,
1136 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1137 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1138 {"power2", PROCESSOR_POWER,
1139 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1140 {"power3", PROCESSOR_PPC630,
1141 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1142 {"power4", PROCESSOR_POWER4,
1143 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1144 {"power5", PROCESSOR_POWER5,
1145 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1146 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1147 {"powerpc64", PROCESSOR_POWERPC64,
1148 POWERPC_BASE_MASK | MASK_POWERPC64},
1149 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1150 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1151 {"rios2", PROCESSOR_RIOS2,
1152 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1153 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1154 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1155 {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
1158 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1160 /* Some OSs don't support saving the high part of 64-bit registers on
1161 context switch. Other OSs don't support saving Altivec registers.
1162 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1163 settings; if the user wants either, the user must explicitly specify
1164 them and we won't interfere with the user's specification. */
1167 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1168 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1169 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1173 rs6000_init_hard_regno_mode_ok ();
1175 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1176 #ifdef OS_MISSING_POWERPC64
1177 if (OS_MISSING_POWERPC64)
1178 set_masks &= ~MASK_POWERPC64;
1180 #ifdef OS_MISSING_ALTIVEC
1181 if (OS_MISSING_ALTIVEC)
1182 set_masks &= ~MASK_ALTIVEC;
1185 /* Don't override these by the processor default if given explicitly. */
1186 set_masks &= ~(target_flags_explicit
1187 & (MASK_MULTIPLE | MASK_STRING | MASK_SOFT_FLOAT));
1189 /* Identify the processor type. */
1190 rs6000_select[0].string = default_cpu;
1191 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1193 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1195 ptr = &rs6000_select[i];
1196 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1198 for (j = 0; j < ptt_size; j++)
1199 if (! strcmp (ptr->string, processor_target_table[j].name))
1201 if (ptr->set_tune_p)
1202 rs6000_cpu = processor_target_table[j].processor;
1204 if (ptr->set_arch_p)
1206 target_flags &= ~set_masks;
1207 target_flags |= (processor_target_table[j].target_enable
1214 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1221 /* If we are optimizing big endian systems for space, use the load/store
1222 multiple and string instructions. */
1223 if (BYTES_BIG_ENDIAN && optimize_size)
1224 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1226 /* Don't allow -mmultiple or -mstring on little endian systems
1227 unless the cpu is a 750, because the hardware doesn't support the
1228 instructions used in little endian mode, and causes an alignment
1229 trap. The 750 does not cause an alignment trap (except when the
1230 target is unaligned). */
1232 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1234 if (TARGET_MULTIPLE)
1236 target_flags &= ~MASK_MULTIPLE;
1237 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1238 warning ("-mmultiple is not supported on little endian systems");
1243 target_flags &= ~MASK_STRING;
1244 if ((target_flags_explicit & MASK_STRING) != 0)
1245 warning ("-mstring is not supported on little endian systems");
1249 /* Set debug flags */
1250 if (rs6000_debug_name)
1252 if (! strcmp (rs6000_debug_name, "all"))
1253 rs6000_debug_stack = rs6000_debug_arg = 1;
1254 else if (! strcmp (rs6000_debug_name, "stack"))
1255 rs6000_debug_stack = 1;
1256 else if (! strcmp (rs6000_debug_name, "arg"))
1257 rs6000_debug_arg = 1;
1259 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1262 if (rs6000_traceback_name)
1264 if (! strncmp (rs6000_traceback_name, "full", 4))
1265 rs6000_traceback = traceback_full;
1266 else if (! strncmp (rs6000_traceback_name, "part", 4))
1267 rs6000_traceback = traceback_part;
1268 else if (! strncmp (rs6000_traceback_name, "no", 2))
1269 rs6000_traceback = traceback_none;
1271 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1272 rs6000_traceback_name);
1275 /* Set size of long double */
1276 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1277 if (rs6000_long_double_size_string)
1280 int size = strtol (rs6000_long_double_size_string, &tail, 10);
1281 if (*tail != '\0' || (size != 64 && size != 128))
1282 error ("Unknown switch -mlong-double-%s",
1283 rs6000_long_double_size_string);
1285 rs6000_long_double_type_size = size;
1288 /* Set Altivec ABI as default for powerpc64 linux. */
1289 if (TARGET_ELF && TARGET_64BIT)
1291 rs6000_altivec_abi = 1;
1292 rs6000_altivec_vrsave = 1;
1295 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1296 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1298 rs6000_darwin64_abi = 1;
1299 /* Setting to empty string is same as "-mone-byte-bool". */
1301 darwin_one_byte_bool = "";
1305 /* Handle -mabi= options. */
1306 rs6000_parse_abi_options ();
1308 /* Handle -malign-XXXXX option. */
1309 rs6000_parse_alignment_option ();
1311 rs6000_parse_float_gprs_option ();
1313 /* Handle generic -mFOO=YES/NO options. */
1314 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
1315 &rs6000_altivec_vrsave);
1316 rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
1318 rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
1320 /* Handle -mtls-size option. */
1321 rs6000_parse_tls_size_option ();
1323 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1324 SUBTARGET_OVERRIDE_OPTIONS;
1326 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1327 SUBSUBTARGET_OVERRIDE_OPTIONS;
1329 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1330 SUB3TARGET_OVERRIDE_OPTIONS;
1336 error ("AltiVec and E500 instructions cannot coexist");
1338 /* The e500 does not have string instructions, and we set
1339 MASK_STRING above when optimizing for size. */
1340 if ((target_flags & MASK_STRING) != 0)
1341 target_flags = target_flags & ~MASK_STRING;
1343 /* No SPE means 64-bit long doubles, even if an E500. */
1344 if (rs6000_spe_string != 0
1345 && !strcmp (rs6000_spe_string, "no"))
1346 rs6000_long_double_type_size = 64;
1348 else if (rs6000_select[1].string != NULL)
1350 /* For the powerpc-eabispe configuration, we set all these by
1351 default, so let's unset them if we manually set another
1352 CPU that is not the E500. */
1353 if (rs6000_abi_string == 0)
1355 if (rs6000_spe_string == 0)
1357 if (rs6000_float_gprs_string == 0)
1358 rs6000_float_gprs = 0;
1359 if (rs6000_isel_string == 0)
1361 if (rs6000_long_double_size_string == 0)
1362 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1365 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1366 && rs6000_cpu != PROCESSOR_POWER5);
1367 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1368 || rs6000_cpu == PROCESSOR_POWER5);
1370 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
1371 using TARGET_OPTIONS to handle a toggle switch, but we're out of
1372 bits in target_flags so TARGET_SWITCHES cannot be used.
1373 Assumption here is that rs6000_longcall_switch points into the
1374 text of the complete option, rather than being a copy, so we can
1375 scan back for the presence or absence of the no- modifier. */
1376 if (rs6000_longcall_switch)
1378 const char *base = rs6000_longcall_switch;
1379 while (base[-1] != 'm') base--;
1381 if (*rs6000_longcall_switch != '\0')
1382 error ("invalid option %qs", base);
1383 rs6000_default_long_calls = (base[0] != 'n');
1386 /* Handle -m(no-)warn-altivec-long similarly. */
1387 if (rs6000_warn_altivec_long_switch)
1389 const char *base = rs6000_warn_altivec_long_switch;
1390 while (base[-1] != 'm') base--;
1392 if (*rs6000_warn_altivec_long_switch != '\0')
1393 error ("invalid option %qs", base);
1394 rs6000_warn_altivec_long = (base[0] != 'n');
1397 /* Handle -mprioritize-restricted-insns option. */
1398 rs6000_sched_restricted_insns_priority
1399 = (rs6000_sched_groups ? 1 : 0);
1400 if (rs6000_sched_restricted_insns_priority_str)
1401 rs6000_sched_restricted_insns_priority =
1402 atoi (rs6000_sched_restricted_insns_priority_str);
1404 /* Handle -msched-costly-dep option. */
1405 rs6000_sched_costly_dep
1406 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1407 if (rs6000_sched_costly_dep_str)
1409 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1410 rs6000_sched_costly_dep = no_dep_costly;
1411 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1412 rs6000_sched_costly_dep = all_deps_costly;
1413 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1414 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1415 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1416 rs6000_sched_costly_dep = store_to_load_dep_costly;
1418 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1421 /* Handle -minsert-sched-nops option. */
1422 rs6000_sched_insert_nops
1423 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1424 if (rs6000_sched_insert_nops_str)
1426 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1427 rs6000_sched_insert_nops = sched_finish_none;
1428 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1429 rs6000_sched_insert_nops = sched_finish_pad_groups;
1430 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1431 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1433 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1436 #ifdef TARGET_REGNAMES
1437 /* If the user desires alternate register names, copy in the
1438 alternate names now. */
1439 if (TARGET_REGNAMES)
1440 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1443 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1444 If -maix-struct-return or -msvr4-struct-return was explicitly
1445 used, don't override with the ABI default. */
1446 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
1448 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
1449 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
1451 target_flags |= MASK_AIX_STRUCT_RET;
1454 if (TARGET_LONG_DOUBLE_128
1455 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1456 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1458 /* Allocate an alias set for register saves & restores from stack. */
1459 rs6000_sr_alias_set = new_alias_set ();
1462 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1464 /* We can only guarantee the availability of DI pseudo-ops when
1465 assembling for 64-bit targets. */
1468 targetm.asm_out.aligned_op.di = NULL;
1469 targetm.asm_out.unaligned_op.di = NULL;
1472 /* Set branch target alignment, if not optimizing for size. */
1475 if (rs6000_sched_groups)
1477 if (align_functions <= 0)
1478 align_functions = 16;
1479 if (align_jumps <= 0)
1481 if (align_loops <= 0)
1484 if (align_jumps_max_skip <= 0)
1485 align_jumps_max_skip = 15;
1486 if (align_loops_max_skip <= 0)
1487 align_loops_max_skip = 15;
1490 /* Arrange to save and restore machine status around nested functions. */
1491 init_machine_status = rs6000_init_machine_status;
1493 /* We should always be splitting complex arguments, but we can't break
1494 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1495 if (DEFAULT_ABI != ABI_AIX)
1496 targetm.calls.split_complex_arg = NULL;
1498 /* Initialize rs6000_cost with the appropriate target costs. */
1500 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1504 case PROCESSOR_RIOS1:
1505 rs6000_cost = &rios1_cost;
1508 case PROCESSOR_RIOS2:
1509 rs6000_cost = &rios2_cost;
1512 case PROCESSOR_RS64A:
1513 rs6000_cost = &rs64a_cost;
1516 case PROCESSOR_MPCCORE:
1517 rs6000_cost = &mpccore_cost;
1520 case PROCESSOR_PPC403:
1521 rs6000_cost = &ppc403_cost;
1524 case PROCESSOR_PPC405:
1525 rs6000_cost = &ppc405_cost;
1528 case PROCESSOR_PPC440:
1529 rs6000_cost = &ppc440_cost;
1532 case PROCESSOR_PPC601:
1533 rs6000_cost = &ppc601_cost;
1536 case PROCESSOR_PPC603:
1537 rs6000_cost = &ppc603_cost;
1540 case PROCESSOR_PPC604:
1541 rs6000_cost = &ppc604_cost;
1544 case PROCESSOR_PPC604e:
1545 rs6000_cost = &ppc604e_cost;
1548 case PROCESSOR_PPC620:
1549 rs6000_cost = &ppc620_cost;
1552 case PROCESSOR_PPC630:
1553 rs6000_cost = &ppc630_cost;
1556 case PROCESSOR_PPC750:
1557 case PROCESSOR_PPC7400:
1558 rs6000_cost = &ppc750_cost;
1561 case PROCESSOR_PPC7450:
1562 rs6000_cost = &ppc7450_cost;
1565 case PROCESSOR_PPC8540:
1566 rs6000_cost = &ppc8540_cost;
1569 case PROCESSOR_POWER4:
1570 case PROCESSOR_POWER5:
1571 rs6000_cost = &power4_cost;
1579 /* Implement targetm.vectorize.builtin_mask_for_load. */
1581 rs6000_builtin_mask_for_load (void)
1584 return altivec_builtin_mask_for_load;
1589 /* Handle generic options of the form -mfoo=yes/no.
1590 NAME is the option name.
1591 VALUE is the option value.
1592 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1593 whether the option value is 'yes' or 'no' respectively. */
1595 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1599 else if (!strcmp (value, "yes"))
1601 else if (!strcmp (value, "no"))
1604 error ("unknown -m%s= option specified: '%s'", name, value);
1607 /* Handle -mabi= options. */
1609 rs6000_parse_abi_options (void)
1611 if (rs6000_abi_string == 0)
1613 else if (! strcmp (rs6000_abi_string, "altivec"))
1615 rs6000_altivec_abi = 1;
1618 else if (! strcmp (rs6000_abi_string, "no-altivec"))
1619 rs6000_altivec_abi = 0;
1620 else if (! strcmp (rs6000_abi_string, "spe"))
1623 rs6000_altivec_abi = 0;
1624 if (!TARGET_SPE_ABI)
1625 error ("not configured for ABI: '%s'", rs6000_abi_string);
1628 /* These are here for testing during development only, do not
1629 document in the manual please. */
1630 else if (! strcmp (rs6000_abi_string, "d64"))
1632 rs6000_darwin64_abi = 1;
1633 warning ("Using darwin64 ABI");
1635 else if (! strcmp (rs6000_abi_string, "d32"))
1637 rs6000_darwin64_abi = 0;
1638 warning ("Using old darwin ABI");
1641 else if (! strcmp (rs6000_abi_string, "no-spe"))
1644 error ("unknown ABI specified: '%s'", rs6000_abi_string);
1647 /* Handle -mfloat-gprs= options. */
1649 rs6000_parse_float_gprs_option (void)
1651 if (rs6000_float_gprs_string == 0)
1653 else if (! strcmp (rs6000_float_gprs_string, "yes")
1654 || ! strcmp (rs6000_float_gprs_string, "single"))
1655 rs6000_float_gprs = 1;
1656 else if (! strcmp (rs6000_float_gprs_string, "double"))
1657 rs6000_float_gprs = 2;
1658 else if (! strcmp (rs6000_float_gprs_string, "no"))
1659 rs6000_float_gprs = 0;
1661 error ("invalid option for -mfloat-gprs");
1664 /* Handle -malign-XXXXXX options. */
1666 rs6000_parse_alignment_option (void)
1668 if (rs6000_alignment_string == 0)
1670 else if (! strcmp (rs6000_alignment_string, "power"))
1671 rs6000_alignment_flags = MASK_ALIGN_POWER;
1672 else if (! strcmp (rs6000_alignment_string, "natural"))
1673 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1675 error ("unknown -malign-XXXXX option specified: '%s'",
1676 rs6000_alignment_string);
1679 /* Validate and record the size specified with the -mtls-size option. */
1682 rs6000_parse_tls_size_option (void)
1684 if (rs6000_tls_size_string == 0)
1686 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1687 rs6000_tls_size = 16;
1688 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1689 rs6000_tls_size = 32;
1690 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1691 rs6000_tls_size = 64;
1693 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1697 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1701 /* Do anything needed at the start of the asm file. */
1704 rs6000_file_start (void)
1708 const char *start = buffer;
1709 struct rs6000_cpu_select *ptr;
1710 const char *default_cpu = TARGET_CPU_DEFAULT;
1711 FILE *file = asm_out_file;
1713 default_file_start ();
1715 #ifdef TARGET_BI_ARCH
1716 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1720 if (flag_verbose_asm)
1722 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1723 rs6000_select[0].string = default_cpu;
1725 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1727 ptr = &rs6000_select[i];
1728 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1730 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1735 #ifdef USING_ELFOS_H
1736 switch (rs6000_sdata)
1738 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1739 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1740 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1741 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1744 if (rs6000_sdata && g_switch_value)
1746 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1758 /* Return nonzero if this function is known to have a null epilogue. */
1761 direct_return (void)
1763 if (reload_completed)
1765 rs6000_stack_t *info = rs6000_stack_info ();
1767 if (info->first_gp_reg_save == 32
1768 && info->first_fp_reg_save == 64
1769 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1770 && ! info->lr_save_p
1771 && ! info->cr_save_p
1772 && info->vrsave_mask == 0
1780 /* Returns 1 always. */
1783 any_operand (rtx op ATTRIBUTE_UNUSED,
1784 enum machine_mode mode ATTRIBUTE_UNUSED)
1789 /* Returns 1 always. */
1792 any_parallel_operand (rtx op ATTRIBUTE_UNUSED,
1793 enum machine_mode mode ATTRIBUTE_UNUSED)
1798 /* Returns 1 if op is the count register. */
1801 count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1803 if (GET_CODE (op) != REG)
1806 if (REGNO (op) == COUNT_REGISTER_REGNUM)
1809 if (REGNO (op) > FIRST_PSEUDO_REGISTER)
1815 /* Returns 1 if op is an altivec register. */
1818 altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1820 return (register_operand (op, mode)
1821 && (GET_CODE (op) != REG
1822 || REGNO (op) > FIRST_PSEUDO_REGISTER
1823 || ALTIVEC_REGNO_P (REGNO (op))));
1827 xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1829 if (GET_CODE (op) != REG)
1832 if (XER_REGNO_P (REGNO (op)))
1838 /* Return 1 if OP is a signed 8-bit constant. Int multiplication
1839 by such constants completes more quickly. */
1842 s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1844 return (GET_CODE (op) == CONST_INT
1845 && (INTVAL (op) >= -128 && INTVAL (op) <= 127));
1848 /* Return 1 if OP is a constant that can fit in a D field. */
1851 short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1853 return (GET_CODE (op) == CONST_INT
1854 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
1857 /* Similar for an unsigned D field. */
1860 u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1862 return (GET_CODE (op) == CONST_INT
1863 && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K'));
1866 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
1869 non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1871 return (GET_CODE (op) == CONST_INT
1872 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
1875 /* Returns 1 if OP is a CONST_INT that is a positive value
1876 and an exact power of 2. */
1879 exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1881 return (GET_CODE (op) == CONST_INT
1883 && exact_log2 (INTVAL (op)) >= 0);
1886 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
1890 gpc_reg_operand (rtx op, enum machine_mode mode)
1892 return (register_operand (op, mode)
1893 && (GET_CODE (op) != REG
1894 || (REGNO (op) >= ARG_POINTER_REGNUM
1895 && !XER_REGNO_P (REGNO (op)))
1896 || REGNO (op) < MQ_REGNO));
1899 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1903 cc_reg_operand (rtx op, enum machine_mode mode)
1905 return (register_operand (op, mode)
1906 && (GET_CODE (op) != REG
1907 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1908 || CR_REGNO_P (REGNO (op))));
1911 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1912 CR field that isn't CR0. */
1915 cc_reg_not_cr0_operand (rtx op, enum machine_mode mode)
1917 return (register_operand (op, mode)
1918 && (GET_CODE (op) != REG
1919 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1920 || CR_REGNO_NOT_CR0_P (REGNO (op))));
1923 /* Returns 1 if OP is either a constant integer valid for a D-field or
1924 a non-special register. If a register, it must be in the proper
1925 mode unless MODE is VOIDmode. */
1928 reg_or_short_operand (rtx op, enum machine_mode mode)
1930 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1933 /* Similar, except check if the negation of the constant would be
1934 valid for a D-field. Don't allow a constant zero, since all the
1935 patterns that call this predicate use "addic r1,r2,-constant" on
1936 a constant value to set a carry when r2 is greater or equal to
1937 "constant". That doesn't work for zero. */
1940 reg_or_neg_short_operand (rtx op, enum machine_mode mode)
1942 if (GET_CODE (op) == CONST_INT)
1943 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P') && INTVAL (op) != 0;
1945 return gpc_reg_operand (op, mode);
1948 /* Returns 1 if OP is either a constant integer valid for a DS-field or
1949 a non-special register. If a register, it must be in the proper
1950 mode unless MODE is VOIDmode. */
1953 reg_or_aligned_short_operand (rtx op, enum machine_mode mode)
1955 if (gpc_reg_operand (op, mode))
1957 else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3))
1964 /* Return 1 if the operand is either a register or an integer whose
1965 high-order 16 bits are zero. */
1968 reg_or_u_short_operand (rtx op, enum machine_mode mode)
1970 return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1973 /* Return 1 is the operand is either a non-special register or ANY
1974 constant integer. */
1977 reg_or_cint_operand (rtx op, enum machine_mode mode)
1979 return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
1982 /* Return 1 is the operand is either a non-special register or ANY
1983 32-bit signed constant integer. */
1986 reg_or_arith_cint_operand (rtx op, enum machine_mode mode)
1988 return (gpc_reg_operand (op, mode)
1989 || (GET_CODE (op) == CONST_INT
1990 #if HOST_BITS_PER_WIDE_INT != 32
1991 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
1992 < (unsigned HOST_WIDE_INT) 0x100000000ll)
1997 /* Return 1 is the operand is either a non-special register or a 32-bit
1998 signed constant integer valid for 64-bit addition. */
2001 reg_or_add_cint64_operand (rtx op, enum machine_mode mode)
2003 return (gpc_reg_operand (op, mode)
2004 || (GET_CODE (op) == CONST_INT
2005 #if HOST_BITS_PER_WIDE_INT == 32
2006 && INTVAL (op) < 0x7fff8000
2008 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
2014 /* Return 1 is the operand is either a non-special register or a 32-bit
2015 signed constant integer valid for 64-bit subtraction. */
2018 reg_or_sub_cint64_operand (rtx op, enum machine_mode mode)
2020 return (gpc_reg_operand (op, mode)
2021 || (GET_CODE (op) == CONST_INT
2022 #if HOST_BITS_PER_WIDE_INT == 32
2023 && (- INTVAL (op)) < 0x7fff8000
2025 && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
2031 /* Return 1 is the operand is either a non-special register or ANY
2032 32-bit unsigned constant integer. */
2035 reg_or_logical_cint_operand (rtx op, enum machine_mode mode)
2037 if (GET_CODE (op) == CONST_INT)
2039 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
2041 if (GET_MODE_BITSIZE (mode) <= 32)
2044 if (INTVAL (op) < 0)
2048 return ((INTVAL (op) & GET_MODE_MASK (mode)
2049 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0);
2051 else if (GET_CODE (op) == CONST_DOUBLE)
2053 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2057 return CONST_DOUBLE_HIGH (op) == 0;
2060 return gpc_reg_operand (op, mode);
2063 /* Return 1 if the operand is an operand that can be loaded via the GOT. */
2066 got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2068 return (GET_CODE (op) == SYMBOL_REF
2069 || GET_CODE (op) == CONST
2070 || GET_CODE (op) == LABEL_REF);
2073 /* Return 1 if the operand is a simple references that can be loaded via
2074 the GOT (labels involving addition aren't allowed). */
2077 got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2079 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
2082 /* Return the number of instructions it takes to form a constant in an
2083 integer register. */
2086 num_insns_constant_wide (HOST_WIDE_INT value)
2088 /* signed constant loadable with {cal|addi} */
2089 if (CONST_OK_FOR_LETTER_P (value, 'I'))
2092 /* constant loadable with {cau|addis} */
2093 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
2096 #if HOST_BITS_PER_WIDE_INT == 64
2097 else if (TARGET_POWERPC64)
2099 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2100 HOST_WIDE_INT high = value >> 31;
2102 if (high == 0 || high == -1)
2108 return num_insns_constant_wide (high) + 1;
2110 return (num_insns_constant_wide (high)
2111 + num_insns_constant_wide (low) + 1);
2120 num_insns_constant (rtx op, enum machine_mode mode)
2122 if (GET_CODE (op) == CONST_INT)
2124 #if HOST_BITS_PER_WIDE_INT == 64
2125 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2126 && mask64_operand (op, mode))
2130 return num_insns_constant_wide (INTVAL (op));
2133 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
2138 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2139 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2140 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2143 else if (GET_CODE (op) == CONST_DOUBLE)
2149 int endian = (WORDS_BIG_ENDIAN == 0);
2151 if (mode == VOIDmode || mode == DImode)
2153 high = CONST_DOUBLE_HIGH (op);
2154 low = CONST_DOUBLE_LOW (op);
2158 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2159 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2161 low = l[1 - endian];
2165 return (num_insns_constant_wide (low)
2166 + num_insns_constant_wide (high));
2170 if (high == 0 && low >= 0)
2171 return num_insns_constant_wide (low);
2173 else if (high == -1 && low < 0)
2174 return num_insns_constant_wide (low);
2176 else if (mask64_operand (op, mode))
2180 return num_insns_constant_wide (high) + 1;
2183 return (num_insns_constant_wide (high)
2184 + num_insns_constant_wide (low) + 1);
2192 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
2193 register with one instruction per word. We only do this if we can
2194 safely read CONST_DOUBLE_{LOW,HIGH}. */
2197 easy_fp_constant (rtx op, enum machine_mode mode)
2199 if (GET_CODE (op) != CONST_DOUBLE
2200 || GET_MODE (op) != mode
2201 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
2204 /* Consider all constants with -msoft-float to be easy. */
2205 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
2209 /* If we are using V.4 style PIC, consider all constants to be hard. */
2210 if (flag_pic && DEFAULT_ABI == ABI_V4)
2213 #ifdef TARGET_RELOCATABLE
2214 /* Similarly if we are using -mrelocatable, consider all constants
2216 if (TARGET_RELOCATABLE)
2225 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2226 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
2228 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
2229 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
2230 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
2231 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
2234 else if (mode == DFmode)
2239 if (TARGET_E500_DOUBLE)
2242 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2243 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
2245 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
2246 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
2249 else if (mode == SFmode)
2254 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2255 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2257 return num_insns_constant_wide (l) == 1;
2260 else if (mode == DImode)
2261 return ((TARGET_POWERPC64
2262 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
2263 || (num_insns_constant (op, DImode) <= 2));
2265 else if (mode == SImode)
2271 /* Returns the constant for the splat instruction, if exists. */
2274 easy_vector_splat_const (int cst, enum machine_mode mode)
2279 if (EASY_VECTOR_15 (cst)
2280 || EASY_VECTOR_15_ADD_SELF (cst))
2282 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
2288 if (EASY_VECTOR_15 (cst)
2289 || EASY_VECTOR_15_ADD_SELF (cst))
2291 if ((cst & 0xff) != ((cst >> 8) & 0xff))
2297 if (EASY_VECTOR_15 (cst)
2298 || EASY_VECTOR_15_ADD_SELF (cst))
2307 /* Return nonzero if all elements of a vector have the same value. */
2310 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2314 units = CONST_VECTOR_NUNITS (op);
2316 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2317 for (i = 1; i < units; ++i)
2318 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
2320 if (i == units && easy_vector_splat_const (cst, mode))
2325 /* Return 1 if the operand is a CONST_INT and can be put into a
2326 register without using memory. */
2329 easy_vector_constant (rtx op, enum machine_mode mode)
2333 if (GET_CODE (op) != CONST_VECTOR
2338 if (zero_constant (op, mode)
2339 && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
2340 || (TARGET_SPE && SPE_VECTOR_MODE (mode))))
2343 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
2346 if (TARGET_SPE && mode == V1DImode)
2349 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2350 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
2352 /* Limit SPE vectors to 15 bits signed. These we can generate with:
2354 evmergelo r0, r0, r0
2357 I don't know how efficient it would be to allow bigger constants,
2358 considering we'll have an extra 'ori' for every 'li'. I doubt 5
2359 instructions is better than a 64-bit memory load, but I don't
2360 have the e500 timing specs. */
2361 if (TARGET_SPE && mode == V2SImode
2362 && cst >= -0x7fff && cst <= 0x7fff
2363 && cst2 >= -0x7fff && cst2 <= 0x7fff)
2367 && easy_vector_same (op, mode))
2369 cst = easy_vector_splat_const (cst, mode);
2370 if (EASY_VECTOR_15_ADD_SELF (cst)
2371 || EASY_VECTOR_15 (cst))
2377 /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */
2380 easy_vector_constant_add_self (rtx op, enum machine_mode mode)
2384 && GET_CODE (op) == CONST_VECTOR
2385 && easy_vector_same (op, mode))
2387 cst = easy_vector_splat_const (INTVAL (CONST_VECTOR_ELT (op, 0)), mode);
2388 if (EASY_VECTOR_15_ADD_SELF (cst))
2394 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
2397 gen_easy_vector_constant_add_self (rtx op)
2401 units = GET_MODE_NUNITS (GET_MODE (op));
2402 v = rtvec_alloc (units);
2404 for (i = 0; i < units; i++)
2406 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
2407 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
2411 output_vec_const_move (rtx *operands)
2414 enum machine_mode mode;
2420 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2421 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2422 mode = GET_MODE (dest);
2426 if (zero_constant (vec, mode))
2427 return "vxor %0,%0,%0";
2428 else if (easy_vector_constant (vec, mode))
2430 operands[1] = GEN_INT (cst);
2434 if (EASY_VECTOR_15 (cst))
2436 operands[1] = GEN_INT (cst);
2437 return "vspltisw %0,%1";
2439 else if (EASY_VECTOR_15_ADD_SELF (cst))
2445 if (EASY_VECTOR_15 (cst))
2447 operands[1] = GEN_INT (cst);
2448 return "vspltish %0,%1";
2450 else if (EASY_VECTOR_15_ADD_SELF (cst))
2456 if (EASY_VECTOR_15 (cst))
2458 operands[1] = GEN_INT (cst);
2459 return "vspltisb %0,%1";
2461 else if (EASY_VECTOR_15_ADD_SELF (cst))
2474 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2475 pattern of V1DI, V4HI, and V2SF.
2477 FIXME: We should probably return # and add post reload
2478 splitters for these, but this way is so easy ;-). */
2479 operands[1] = GEN_INT (cst);
2480 operands[2] = GEN_INT (cst2);
2482 return "li %0,%1\n\tevmergelo %0,%0,%0";
2484 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2490 /* Return 1 if the operand is the constant 0. This works for scalars
2491 as well as vectors. */
2493 zero_constant (rtx op, enum machine_mode mode)
2495 return op == CONST0_RTX (mode);
2498 /* Return 1 if the operand is 0.0. */
2500 zero_fp_constant (rtx op, enum machine_mode mode)
2502 return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
2505 /* Return 1 if the operand is in volatile memory. Note that during
2506 the RTL generation phase, memory_operand does not return TRUE for
2507 volatile memory references. So this function allows us to
2508 recognize volatile references where its safe. */
2511 volatile_mem_operand (rtx op, enum machine_mode mode)
2513 if (GET_CODE (op) != MEM)
2516 if (!MEM_VOLATILE_P (op))
2519 if (mode != GET_MODE (op))
2522 if (reload_completed)
2523 return memory_operand (op, mode);
2525 if (reload_in_progress)
2526 return strict_memory_address_p (mode, XEXP (op, 0));
2528 return memory_address_p (mode, XEXP (op, 0));
2531 /* Return 1 if the operand is an offsettable memory operand. */
2534 offsettable_mem_operand (rtx op, enum machine_mode mode)
2536 return ((GET_CODE (op) == MEM)
2537 && offsettable_address_p (reload_completed || reload_in_progress,
2538 mode, XEXP (op, 0)));
2541 /* Return 1 if the operand is either an easy FP constant (see above) or
2545 mem_or_easy_const_operand (rtx op, enum machine_mode mode)
2547 return memory_operand (op, mode) || easy_fp_constant (op, mode);
2550 /* Return 1 if the operand is either a non-special register or an item
2551 that can be used as the operand of a `mode' add insn. */
2554 add_operand (rtx op, enum machine_mode mode)
2556 if (GET_CODE (op) == CONST_INT)
2557 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
2558 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
2560 return gpc_reg_operand (op, mode);
2563 /* Return 1 if OP is a constant but not a valid add_operand. */
2566 non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2568 return (GET_CODE (op) == CONST_INT
2569 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
2570 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
2573 /* Return 1 if the operand is a non-special register or a constant that
2574 can be used as the operand of an OR or XOR insn on the RS/6000. */
2577 logical_operand (rtx op, enum machine_mode mode)
2579 HOST_WIDE_INT opl, oph;
2581 if (gpc_reg_operand (op, mode))
2584 if (GET_CODE (op) == CONST_INT)
2586 opl = INTVAL (op) & GET_MODE_MASK (mode);
2588 #if HOST_BITS_PER_WIDE_INT <= 32
2589 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
2593 else if (GET_CODE (op) == CONST_DOUBLE)
2595 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
2598 opl = CONST_DOUBLE_LOW (op);
2599 oph = CONST_DOUBLE_HIGH (op);
2606 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
2607 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
2610 /* Return 1 if C is a constant that is not a logical operand (as
2611 above), but could be split into one. */
2614 non_logical_cint_operand (rtx op, enum machine_mode mode)
2616 return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
2617 && ! logical_operand (op, mode)
2618 && reg_or_logical_cint_operand (op, mode));
2621 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
2622 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
2623 Reject all ones and all zeros, since these should have been optimized
2624 away and confuse the making of MB and ME. */
2627 mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2629 HOST_WIDE_INT c, lsb;
2631 if (GET_CODE (op) != CONST_INT)
2636 /* Fail in 64-bit mode if the mask wraps around because the upper
2637 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
2638 if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
2641 /* We don't change the number of transitions by inverting,
2642 so make sure we start with the LS bit zero. */
2646 /* Reject all zeros or all ones. */
2650 /* Find the first transition. */
2653 /* Invert to look for a second transition. */
2656 /* Erase first transition. */
2659 /* Find the second transition (if any). */
2662 /* Match if all the bits above are 1's (or c is zero). */
2666 /* Return 1 for the PowerPC64 rlwinm corner case. */
2669 mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2671 HOST_WIDE_INT c, lsb;
2673 if (GET_CODE (op) != CONST_INT)
2678 if ((c & 0x80000001) != 0x80000001)
2692 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
2693 It is if there are no more than one 1->0 or 0->1 transitions.
2694 Reject all zeros, since zero should have been optimized away and
2695 confuses the making of MB and ME. */
2698 mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2700 if (GET_CODE (op) == CONST_INT)
2702 HOST_WIDE_INT c, lsb;
2706 /* Reject all zeros. */
2710 /* We don't change the number of transitions by inverting,
2711 so make sure we start with the LS bit zero. */
2715 /* Find the transition, and check that all bits above are 1's. */
2718 /* Match if all the bits above are 1's (or c is zero). */
2725 mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED,
2728 if (GET_CODE (op) == CONST_INT)
2730 HOST_WIDE_INT c, lsb;
2735 /* Disallow all zeros. */
2739 /* We can use a single rlwinm insn if no upper bits of C are set
2740 AND there are zero, one or two transitions in the _whole_ of
2742 one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff);
2744 /* We don't change the number of transitions by inverting,
2745 so make sure we start with the LS bit zero. */
2749 /* Find the first transition. */
2752 /* Invert to look for a second transition. */
2755 /* Erase first transition. */
2758 /* Find the second transition. */
2761 /* Invert to look for a third transition. */
2764 /* Erase second transition. */
2767 if (one_ok && !(allow_one || c))
2770 /* Find the third transition (if any). */
2773 /* Match if all the bits above are 1's (or c is zero). */
2779 /* Like mask64_operand, but allow up to three transitions. This
2780 predicate is used by insn patterns that generate two rldicl or
2781 rldicr machine insns. */
2782 int mask64_2_operand (rtx op, enum machine_mode mode)
2784 return mask64_1or2_operand (op, mode, false);
2787 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2788 implement ANDing by the mask IN. */
2790 build_mask64_2_operands (rtx in, rtx *out)
2792 #if HOST_BITS_PER_WIDE_INT >= 64
2793 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2796 if (GET_CODE (in) != CONST_INT)
2802 /* Assume c initially something like 0x00fff000000fffff. The idea
2803 is to rotate the word so that the middle ^^^^^^ group of zeros
2804 is at the MS end and can be cleared with an rldicl mask. We then
2805 rotate back and clear off the MS ^^ group of zeros with a
2807 c = ~c; /* c == 0xff000ffffff00000 */
2808 lsb = c & -c; /* lsb == 0x0000000000100000 */
2809 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2810 c = ~c; /* c == 0x00fff000000fffff */
2811 c &= -lsb; /* c == 0x00fff00000000000 */
2812 lsb = c & -c; /* lsb == 0x0000100000000000 */
2813 c = ~c; /* c == 0xff000fffffffffff */
2814 c &= -lsb; /* c == 0xff00000000000000 */
2816 while ((lsb >>= 1) != 0)
2817 shift++; /* shift == 44 on exit from loop */
2818 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2819 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2820 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2824 /* Assume c initially something like 0xff000f0000000000. The idea
2825 is to rotate the word so that the ^^^ middle group of zeros
2826 is at the LS end and can be cleared with an rldicr mask. We then
2827 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2829 lsb = c & -c; /* lsb == 0x0000010000000000 */
2830 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2831 c = ~c; /* c == 0x00fff0ffffffffff */
2832 c &= -lsb; /* c == 0x00fff00000000000 */
2833 lsb = c & -c; /* lsb == 0x0000100000000000 */
2834 c = ~c; /* c == 0xff000fffffffffff */
2835 c &= -lsb; /* c == 0xff00000000000000 */
2837 while ((lsb >>= 1) != 0)
2838 shift++; /* shift == 44 on exit from loop */
2839 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2840 m1 >>= shift; /* m1 == 0x0000000000000fff */
2841 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2844 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2845 masks will be all 1's. We are guaranteed more than one transition. */
2846 out[0] = GEN_INT (64 - shift);
2847 out[1] = GEN_INT (m1);
2848 out[2] = GEN_INT (shift);
2849 out[3] = GEN_INT (m2);
2857 /* Return 1 if the operand is either a non-special register or a constant
2858 that can be used as the operand of a PowerPC64 logical AND insn. */
2861 and64_operand (rtx op, enum machine_mode mode)
2863 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2864 return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
2866 return (logical_operand (op, mode) || mask64_operand (op, mode));
2869 /* Like the above, but also match constants that can be implemented
2870 with two rldicl or rldicr insns. */
2873 and64_2_operand (rtx op, enum machine_mode mode)
2875 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2876 return gpc_reg_operand (op, mode) || mask64_1or2_operand (op, mode, true);
2878 return logical_operand (op, mode) || mask64_1or2_operand (op, mode, true);
2881 /* Return 1 if the operand is either a non-special register or a
2882 constant that can be used as the operand of an RS/6000 logical AND insn. */
2885 and_operand (rtx op, enum machine_mode mode)
2887 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2888 return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
2890 return (logical_operand (op, mode) || mask_operand (op, mode));
2893 /* Return 1 if the operand is a general register or memory operand. */
2896 reg_or_mem_operand (rtx op, enum machine_mode mode)
2898 return (gpc_reg_operand (op, mode)
2899 || memory_operand (op, mode)
2900 || macho_lo_sum_memory_operand (op, mode)
2901 || volatile_mem_operand (op, mode));
2904 /* Return 1 if the operand is a general register or memory operand without
2905 pre_inc or pre_dec which produces invalid form of PowerPC lwa
2909 lwa_operand (rtx op, enum machine_mode mode)
2913 if (reload_completed && GET_CODE (inner) == SUBREG)
2914 inner = SUBREG_REG (inner);
2916 return gpc_reg_operand (inner, mode)
2917 || (memory_operand (inner, mode)
2918 && GET_CODE (XEXP (inner, 0)) != PRE_INC
2919 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
2920 && (GET_CODE (XEXP (inner, 0)) != PLUS
2921 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
2922 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
2925 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */
2928 symbol_ref_operand (rtx op, enum machine_mode mode)
2930 if (mode != VOIDmode && GET_MODE (op) != mode)
2933 return (GET_CODE (op) == SYMBOL_REF
2934 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)));
2937 /* Return 1 if the operand, used inside a MEM, is a valid first argument
2938 to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */
2941 call_operand (rtx op, enum machine_mode mode)
2943 if (mode != VOIDmode && GET_MODE (op) != mode)
2946 return (GET_CODE (op) == SYMBOL_REF
2947 || (GET_CODE (op) == REG
2948 && (REGNO (op) == LINK_REGISTER_REGNUM
2949 || REGNO (op) == COUNT_REGISTER_REGNUM
2950 || REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2953 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
2957 current_file_function_operand (rtx op,
2958 enum machine_mode mode ATTRIBUTE_UNUSED)
2960 return (GET_CODE (op) == SYMBOL_REF
2961 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
2962 && (SYMBOL_REF_LOCAL_P (op)
2963 || (op == XEXP (DECL_RTL (current_function_decl), 0))));
2966 /* Return 1 if this operand is a valid input for a move insn. */
2969 input_operand (rtx op, enum machine_mode mode)
2971 /* Memory is always valid. */
2972 if (memory_operand (op, mode))
2975 /* For floating-point, easy constants are valid. */
2976 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2978 && easy_fp_constant (op, mode))
2981 /* Allow any integer constant. */
2982 if (GET_MODE_CLASS (mode) == MODE_INT
2983 && (GET_CODE (op) == CONST_INT
2984 || GET_CODE (op) == CONST_DOUBLE))
2987 /* Allow easy vector constants. */
2988 if (GET_CODE (op) == CONST_VECTOR
2989 && easy_vector_constant (op, mode))
2992 /* For floating-point or multi-word mode, the only remaining valid type
2994 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2995 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
2996 return register_operand (op, mode);
2998 /* The only cases left are integral modes one word or smaller (we
2999 do not get called for MODE_CC values). These can be in any
3001 if (register_operand (op, mode))
3004 /* A SYMBOL_REF referring to the TOC is valid. */
3005 if (legitimate_constant_pool_address_p (op))
3008 /* A constant pool expression (relative to the TOC) is valid */
3009 if (toc_relative_expr_p (op))
3012 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
3014 if (DEFAULT_ABI == ABI_V4
3015 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
3016 && small_data_operand (op, Pmode))
3023 /* Darwin, AIX increases natural record alignment to doubleword if the first
3024 field is an FP double while the FP fields remain word aligned. */
3027 rs6000_special_round_type_align (tree type, int computed, int specified)
3029 tree field = TYPE_FIELDS (type);
3031 /* Skip all the static variables only if ABI is greater than
3033 while (field != NULL && TREE_CODE (field) == VAR_DECL)
3034 field = TREE_CHAIN (field);
3036 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
3037 return MAX (computed, specified);
3039 return MAX (MAX (computed, specified), 64);
3042 /* Return 1 for an operand in small memory on V.4/eabi. */
3045 small_data_operand (rtx op ATTRIBUTE_UNUSED,
3046 enum machine_mode mode ATTRIBUTE_UNUSED)
3051 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
3054 if (DEFAULT_ABI != ABI_V4)
3057 if (GET_CODE (op) == SYMBOL_REF)
3060 else if (GET_CODE (op) != CONST
3061 || GET_CODE (XEXP (op, 0)) != PLUS
3062 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
3063 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
3068 rtx sum = XEXP (op, 0);
3069 HOST_WIDE_INT summand;
3071 /* We have to be careful here, because it is the referenced address
3072 that must be 32k from _SDA_BASE_, not just the symbol. */
3073 summand = INTVAL (XEXP (sum, 1));
3074 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
3077 sym_ref = XEXP (sum, 0);
3080 return SYMBOL_REF_SMALL_P (sym_ref);
3086 /* Return true, if operand is a memory operand and has a
3087 displacement divisible by 4. */
3090 word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3095 if (!memory_operand (op, mode))
3098 addr = XEXP (op, 0);
3099 if (GET_CODE (addr) == PLUS
3100 && GET_CODE (XEXP (addr, 0)) == REG
3101 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
3102 off = INTVAL (XEXP (addr, 1));
3104 return (off % 4) == 0;
3107 /* Return true if either operand is a general purpose register. */
3110 gpr_or_gpr_p (rtx op0, rtx op1)
3112 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
3113 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
3117 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3120 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
3122 switch (GET_CODE(op))
3125 if (RS6000_SYMBOL_REF_TLS_P (op))
3127 else if (CONSTANT_POOL_ADDRESS_P (op))
3129 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
3137 else if (! strcmp (XSTR (op, 0), toc_label_name))
3146 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
3147 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
3149 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
3158 constant_pool_expr_p (rtx op)
3162 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
3166 toc_relative_expr_p (rtx op)
3170 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3174 legitimate_constant_pool_address_p (rtx x)
3177 && GET_CODE (x) == PLUS
3178 && GET_CODE (XEXP (x, 0)) == REG
3179 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3180 && constant_pool_expr_p (XEXP (x, 1)));
3184 legitimate_small_data_p (enum machine_mode mode, rtx x)
3186 return (DEFAULT_ABI == ABI_V4
3187 && !flag_pic && !TARGET_TOC
3188 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3189 && small_data_operand (x, mode));
3192 /* SPE offset addressing is limited to 5-bits worth of double words. */
3193 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3196 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3198 unsigned HOST_WIDE_INT offset, extra;
3200 if (GET_CODE (x) != PLUS)
3202 if (GET_CODE (XEXP (x, 0)) != REG)
3204 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3206 if (legitimate_constant_pool_address_p (x))
3208 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3211 offset = INTVAL (XEXP (x, 1));
3219 /* AltiVec vector modes. Only reg+reg addressing is valid here,
3220 which leaves the only valid constant offset of zero, which by
3221 canonicalization rules is also invalid. */
3228 /* SPE vector modes. */
3229 return SPE_CONST_OFFSET_OK (offset);
3232 if (TARGET_E500_DOUBLE)
3233 return SPE_CONST_OFFSET_OK (offset);
3236 if (mode == DFmode || !TARGET_POWERPC64)
3238 else if (offset & 3)
3244 if (mode == TFmode || !TARGET_POWERPC64)
3246 else if (offset & 3)
3257 return (offset < 0x10000) && (offset + extra < 0x10000);
3261 legitimate_indexed_address_p (rtx x, int strict)
3265 if (GET_CODE (x) != PLUS)
3271 if (!REG_P (op0) || !REG_P (op1))
3274 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
3275 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3276 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3277 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
3281 legitimate_indirect_address_p (rtx x, int strict)
3283 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3287 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3289 if (!TARGET_MACHO || !flag_pic
3290 || mode != SImode || GET_CODE(x) != MEM)
3294 if (GET_CODE (x) != LO_SUM)
3296 if (GET_CODE (XEXP (x, 0)) != REG)
3298 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3302 return CONSTANT_P (x);
3306 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3308 if (GET_CODE (x) != LO_SUM)
3310 if (GET_CODE (XEXP (x, 0)) != REG)
3312 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3314 if (TARGET_E500_DOUBLE && mode == DFmode)
3318 if (TARGET_ELF || TARGET_MACHO)
3320 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3324 if (GET_MODE_NUNITS (mode) != 1)
3326 if (GET_MODE_BITSIZE (mode) > 64)
3329 return CONSTANT_P (x);
3336 /* Try machine-dependent ways of modifying an illegitimate address
3337 to be legitimate. If we find one, return the new, valid address.
3338 This is used from only one place: `memory_address' in explow.c.
3340 OLDX is the address as it was before break_out_memory_refs was
3341 called. In some cases it is useful to look at this to decide what
3344 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3346 It is always safe for this function to do nothing. It exists to
3347 recognize opportunities to optimize the output.
3349 On RS/6000, first check for the sum of a register with a constant
3350 integer that is out of range. If so, generate code to add the
3351 constant with the low-order 16 bits masked to the register and force
3352 this result into another register (this can be done with `cau').
3353 Then generate an address of REG+(CONST&0xffff), allowing for the
3354 possibility of bit 16 being a one.
3356 Then check for the sum of a register and something not constant, try to
3357 load the other things into a register and return the sum. */
3360 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3361 enum machine_mode mode)
3363 if (GET_CODE (x) == SYMBOL_REF)
3365 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3367 return rs6000_legitimize_tls_address (x, model);
3370 if (GET_CODE (x) == PLUS
3371 && GET_CODE (XEXP (x, 0)) == REG
3372 && GET_CODE (XEXP (x, 1)) == CONST_INT
3373 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
3375 HOST_WIDE_INT high_int, low_int;
3377 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3378 high_int = INTVAL (XEXP (x, 1)) - low_int;
3379 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3380 GEN_INT (high_int)), 0);
3381 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3383 else if (GET_CODE (x) == PLUS
3384 && GET_CODE (XEXP (x, 0)) == REG
3385 && GET_CODE (XEXP (x, 1)) != CONST_INT
3386 && GET_MODE_NUNITS (mode) == 1
3387 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3389 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3390 && (TARGET_POWERPC64 || mode != DImode)
3393 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3394 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3396 else if (ALTIVEC_VECTOR_MODE (mode))
3400 /* Make sure both operands are registers. */
3401 if (GET_CODE (x) == PLUS)
3402 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3403 force_reg (Pmode, XEXP (x, 1)));
3405 reg = force_reg (Pmode, x);
3408 else if (SPE_VECTOR_MODE (mode)
3409 || (TARGET_E500_DOUBLE && mode == DFmode))
3411 /* We accept [reg + reg] and [reg + OFFSET]. */
3413 if (GET_CODE (x) == PLUS)
3415 rtx op1 = XEXP (x, 0);
3416 rtx op2 = XEXP (x, 1);
3418 op1 = force_reg (Pmode, op1);
3420 if (GET_CODE (op2) != REG
3421 && (GET_CODE (op2) != CONST_INT
3422 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3423 op2 = force_reg (Pmode, op2);
3425 return gen_rtx_PLUS (Pmode, op1, op2);
3428 return force_reg (Pmode, x);
3434 && GET_CODE (x) != CONST_INT
3435 && GET_CODE (x) != CONST_DOUBLE
3437 && GET_MODE_NUNITS (mode) == 1
3438 && (GET_MODE_BITSIZE (mode) <= 32
3439 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3441 rtx reg = gen_reg_rtx (Pmode);
3442 emit_insn (gen_elf_high (reg, x));
3443 return gen_rtx_LO_SUM (Pmode, reg, x);
3445 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3448 && ! MACHO_DYNAMIC_NO_PIC_P
3450 && GET_CODE (x) != CONST_INT
3451 && GET_CODE (x) != CONST_DOUBLE
3453 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3457 rtx reg = gen_reg_rtx (Pmode);
3458 emit_insn (gen_macho_high (reg, x));
3459 return gen_rtx_LO_SUM (Pmode, reg, x);
3462 && constant_pool_expr_p (x)
3463 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3465 return create_TOC_reference (x);
3471 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
3472 We need to emit DTP-relative relocations. */
3475 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3480 fputs ("\t.long\t", file);
3483 fputs (DOUBLE_INT_ASM_OP, file);
3488 output_addr_const (file, x);
3489 fputs ("@dtprel+0x8000", file);
3492 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3494 static GTY(()) rtx rs6000_tls_symbol;
3496 rs6000_tls_get_addr (void)
3498 if (!rs6000_tls_symbol)
3499 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3501 return rs6000_tls_symbol;
3504 /* Construct the SYMBOL_REF for TLS GOT references. */
3506 static GTY(()) rtx rs6000_got_symbol;
3508 rs6000_got_sym (void)
3510 if (!rs6000_got_symbol)
3512 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3513 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3514 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3517 return rs6000_got_symbol;
3520 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3521 this (thread-local) address. */
3524 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3528 dest = gen_reg_rtx (Pmode);
3529 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3535 tlsreg = gen_rtx_REG (Pmode, 13);
3536 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3540 tlsreg = gen_rtx_REG (Pmode, 2);
3541 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3545 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3549 tmp = gen_reg_rtx (Pmode);
3552 tlsreg = gen_rtx_REG (Pmode, 13);
3553 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3557 tlsreg = gen_rtx_REG (Pmode, 2);
3558 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3562 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3564 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3569 rtx r3, got, tga, tmp1, tmp2, eqv;
3572 got = gen_rtx_REG (Pmode, TOC_REGISTER);
3576 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3579 rtx gsym = rs6000_got_sym ();
3580 got = gen_reg_rtx (Pmode);
3582 rs6000_emit_move (got, gsym, Pmode);
3586 static int tls_got_labelno = 0;
3587 rtx tempLR, lab, tmp3, mem;
3590 ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++);
3591 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
3592 tempLR = gen_reg_rtx (Pmode);
3593 tmp1 = gen_reg_rtx (Pmode);
3594 tmp2 = gen_reg_rtx (Pmode);
3595 tmp3 = gen_reg_rtx (Pmode);
3596 mem = gen_const_mem (Pmode, tmp1);
3598 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab,
3600 emit_move_insn (tmp1, tempLR);
3601 emit_move_insn (tmp2, mem);
3602 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3603 last = emit_move_insn (got, tmp3);
3604 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3606 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3608 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3614 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3616 r3 = gen_rtx_REG (Pmode, 3);
3618 insn = gen_tls_gd_64 (r3, got, addr);
3620 insn = gen_tls_gd_32 (r3, got, addr);
3623 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3624 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3625 insn = emit_call_insn (insn);
3626 CONST_OR_PURE_CALL_P (insn) = 1;
3627 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3628 insn = get_insns ();
3630 emit_libcall_block (insn, dest, r3, addr);
3632 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3634 r3 = gen_rtx_REG (Pmode, 3);
3636 insn = gen_tls_ld_64 (r3, got);
3638 insn = gen_tls_ld_32 (r3, got);
3641 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3642 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3643 insn = emit_call_insn (insn);
3644 CONST_OR_PURE_CALL_P (insn) = 1;
3645 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3646 insn = get_insns ();
3648 tmp1 = gen_reg_rtx (Pmode);
3649 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3651 emit_libcall_block (insn, tmp1, r3, eqv);
3652 if (rs6000_tls_size == 16)
3655 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3657 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3659 else if (rs6000_tls_size == 32)
3661 tmp2 = gen_reg_rtx (Pmode);
3663 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3665 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3668 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3670 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3674 tmp2 = gen_reg_rtx (Pmode);
3676 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3678 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3680 insn = gen_rtx_SET (Pmode, dest,
3681 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3687 /* IE, or 64 bit offset LE. */
3688 tmp2 = gen_reg_rtx (Pmode);
3690 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3692 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3695 insn = gen_tls_tls_64 (dest, tmp2, addr);
3697 insn = gen_tls_tls_32 (dest, tmp2, addr);
3705 /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in
3706 instruction definitions. */
3709 rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
3711 return RS6000_SYMBOL_REF_TLS_P (x);
3714 /* Return 1 if X contains a thread-local symbol. */
3717 rs6000_tls_referenced_p (rtx x)
3719 if (! TARGET_HAVE_TLS)
3722 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3725 /* Return 1 if *X is a thread-local symbol. This is the same as
3726 rs6000_tls_symbol_ref except for the type of the unused argument. */
3729 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3731 return RS6000_SYMBOL_REF_TLS_P (*x);
3734 /* The convention appears to be to define this wherever it is used.
3735 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3736 is now used here. */
3737 #ifndef REG_MODE_OK_FOR_BASE_P
3738 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3741 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3742 replace the input X, or the original X if no replacement is called for.
3743 The output parameter *WIN is 1 if the calling macro should goto WIN,
3746 For RS/6000, we wish to handle large displacements off a base
3747 register by splitting the addend across an addiu/addis and the mem insn.
3748 This cuts number of extra insns needed from 3 to 1.
3750 On Darwin, we use this to generate code for floating point constants.
3751 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3752 The Darwin code is inside #if TARGET_MACHO because only then is
3753 machopic_function_base_name() defined. */
3755 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3756 int opnum, int type,
3757 int ind_levels ATTRIBUTE_UNUSED, int *win)
3759 /* We must recognize output that we have already generated ourselves. */
3760 if (GET_CODE (x) == PLUS
3761 && GET_CODE (XEXP (x, 0)) == PLUS
3762 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3763 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3764 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3766 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3767 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3768 opnum, (enum reload_type)type);
3774 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3775 && GET_CODE (x) == LO_SUM
3776 && GET_CODE (XEXP (x, 0)) == PLUS
3777 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3778 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3779 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3780 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3781 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3782 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3783 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3785 /* Result of previous invocation of this function on Darwin
3786 floating point constant. */
3787 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3788 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3789 opnum, (enum reload_type)type);
3794 if (GET_CODE (x) == PLUS
3795 && GET_CODE (XEXP (x, 0)) == REG
3796 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3797 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3798 && GET_CODE (XEXP (x, 1)) == CONST_INT
3799 && !SPE_VECTOR_MODE (mode)
3800 && !(TARGET_E500_DOUBLE && mode == DFmode)
3801 && !ALTIVEC_VECTOR_MODE (mode))
3803 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3804 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3806 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3808 /* Check for 32-bit overflow. */
3809 if (high + low != val)
3815 /* Reload the high part into a base reg; leave the low part
3816 in the mem directly. */
3818 x = gen_rtx_PLUS (GET_MODE (x),
3819 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3823 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3824 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3825 opnum, (enum reload_type)type);
3830 if (GET_CODE (x) == SYMBOL_REF
3831 && DEFAULT_ABI == ABI_DARWIN
3832 && !ALTIVEC_VECTOR_MODE (mode)
3833 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3834 /* Don't do this for TFmode, since the result isn't offsettable. */
3839 rtx offset = gen_rtx_CONST (Pmode,
3840 gen_rtx_MINUS (Pmode, x,
3841 machopic_function_base_sym ()));
3842 x = gen_rtx_LO_SUM (GET_MODE (x),
3843 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3844 gen_rtx_HIGH (Pmode, offset)), offset);
3847 x = gen_rtx_LO_SUM (GET_MODE (x),
3848 gen_rtx_HIGH (Pmode, x), x);
3850 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3851 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3852 opnum, (enum reload_type)type);
3858 && constant_pool_expr_p (x)
3859 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3861 (x) = create_TOC_reference (x);
3869 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3870 that is a valid memory address for an instruction.
3871 The MODE argument is the machine mode for the MEM expression
3872 that wants to use this address.
3874 On the RS/6000, there are four valid address: a SYMBOL_REF that
3875 refers to a constant pool entry of an address (or the sum of it
3876 plus a constant), a short (16-bit signed) constant plus a register,
3877 the sum of two registers, or a register indirect, possibly with an
3878 auto-increment. For DFmode and DImode with a constant plus register,
3879 we must ensure that both words are addressable or PowerPC64 with offset
3882 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3883 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3884 adjacent memory cells are accessed by adding word-sized offsets
3885 during assembly output. */
3887 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3889 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3891 && ALTIVEC_VECTOR_MODE (mode)
3892 && GET_CODE (x) == AND
3893 && GET_CODE (XEXP (x, 1)) == CONST_INT
3894 && INTVAL (XEXP (x, 1)) == -16)
3897 if (RS6000_SYMBOL_REF_TLS_P (x))
3899 if (legitimate_indirect_address_p (x, reg_ok_strict))
3901 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3902 && !ALTIVEC_VECTOR_MODE (mode)
3903 && !SPE_VECTOR_MODE (mode)
3904 && !(TARGET_E500_DOUBLE && mode == DFmode)
3906 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3908 if (legitimate_small_data_p (mode, x))
3910 if (legitimate_constant_pool_address_p (x))
3912 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3914 && GET_CODE (x) == PLUS
3915 && GET_CODE (XEXP (x, 0)) == REG
3916 && (XEXP (x, 0) == virtual_stack_vars_rtx
3917 || XEXP (x, 0) == arg_pointer_rtx)
3918 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3920 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3924 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3926 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3927 && (TARGET_POWERPC64 || mode != DImode)
3928 && legitimate_indexed_address_p (x, reg_ok_strict))
3930 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3935 /* Go to LABEL if ADDR (a legitimate address expression)
3936 has an effect that depends on the machine mode it is used for.
3938 On the RS/6000 this is true of all integral offsets (since AltiVec
3939 modes don't allow them) or is a pre-increment or decrement.
3941 ??? Except that due to conceptual problems in offsettable_address_p
3942 we can't really report the problems of integral offsets. So leave
3943 this assuming that the adjustable offset must be valid for the
3944 sub-words of a TFmode operand, which is what we had before. */
3947 rs6000_mode_dependent_address (rtx addr)
3949 switch (GET_CODE (addr))
3952 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3954 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3955 return val + 12 + 0x8000 >= 0x10000;
3964 return TARGET_UPDATE;
3973 /* Return number of consecutive hard regs needed starting at reg REGNO
3974 to hold something of mode MODE.
3975 This is ordinarily the length in words of a value of mode MODE
3976 but can be less for certain modes in special long registers.
3978 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3979 scalar instructions. The upper 32 bits are only available to the
3982 POWER and PowerPC GPRs hold 32 bits worth;
3983 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3986 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3988 if (FP_REGNO_P (regno))
3989 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3991 if (TARGET_E500_DOUBLE && mode == DFmode)
3994 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3995 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3997 if (ALTIVEC_REGNO_P (regno))
3999 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
4001 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4004 /* Change register usage conditional on target flags. */
4006 rs6000_conditional_register_usage (void)
4010 /* Set MQ register fixed (already call_used) if not POWER
4011 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4016 /* 64-bit AIX reserves GPR13 for thread-private data. */
4018 fixed_regs[13] = call_used_regs[13]
4019 = call_really_used_regs[13] = 1;
4021 /* Conditionally disable FPRs. */
4022 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
4023 for (i = 32; i < 64; i++)
4024 fixed_regs[i] = call_used_regs[i]
4025 = call_really_used_regs[i] = 1;
4027 if (DEFAULT_ABI == ABI_V4
4028 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4030 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4032 if (DEFAULT_ABI == ABI_V4
4033 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4035 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4036 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4037 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4039 if (DEFAULT_ABI == ABI_DARWIN
4040 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
4041 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4042 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4043 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4044 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4046 if (TARGET_TOC && TARGET_MINIMAL_TOC)
4047 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4048 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4051 global_regs[VSCR_REGNO] = 1;
4055 global_regs[SPEFSCR_REGNO] = 1;
4056 fixed_regs[FIXED_SCRATCH]
4057 = call_used_regs[FIXED_SCRATCH]
4058 = call_really_used_regs[FIXED_SCRATCH] = 1;
4061 if (! TARGET_ALTIVEC)
4063 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4064 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4065 call_really_used_regs[VRSAVE_REGNO] = 1;
4068 if (TARGET_ALTIVEC_ABI)
4069 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4070 call_used_regs[i] = call_really_used_regs[i] = 1;
4073 /* Try to output insns to set TARGET equal to the constant C if it can
4074 be done in less than N insns. Do all computations in MODE.
4075 Returns the place where the output has been placed if it can be
4076 done and the insns have been emitted. If it would take more than N
4077 insns, zero is returned and no insns and emitted. */
4080 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4081 rtx source, int n ATTRIBUTE_UNUSED)
4083 rtx result, insn, set;
4084 HOST_WIDE_INT c0, c1;
4086 if (mode == QImode || mode == HImode)
4089 dest = gen_reg_rtx (mode);
4090 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4093 else if (mode == SImode)
4095 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
4097 emit_insn (gen_rtx_SET (VOIDmode, result,
4098 GEN_INT (INTVAL (source)
4099 & (~ (HOST_WIDE_INT) 0xffff))));
4100 emit_insn (gen_rtx_SET (VOIDmode, dest,
4101 gen_rtx_IOR (SImode, result,
4102 GEN_INT (INTVAL (source) & 0xffff))));
4105 else if (mode == DImode)
4107 if (GET_CODE (source) == CONST_INT)
4109 c0 = INTVAL (source);
4112 else if (GET_CODE (source) == CONST_DOUBLE)
4114 #if HOST_BITS_PER_WIDE_INT >= 64
4115 c0 = CONST_DOUBLE_LOW (source);
4118 c0 = CONST_DOUBLE_LOW (source);
4119 c1 = CONST_DOUBLE_HIGH (source);
4125 result = rs6000_emit_set_long_const (dest, c0, c1);
4130 insn = get_last_insn ();
4131 set = single_set (insn);
4132 if (! CONSTANT_P (SET_SRC (set)))
4133 set_unique_reg_note (insn, REG_EQUAL, source);
4138 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4139 fall back to a straight forward decomposition. We do this to avoid
4140 exponential run times encountered when looking for longer sequences
4141 with rs6000_emit_set_const. */
4143 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4145 if (!TARGET_POWERPC64)
4147 rtx operand1, operand2;
4149 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4151 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
4153 emit_move_insn (operand1, GEN_INT (c1));
4154 emit_move_insn (operand2, GEN_INT (c2));
4158 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4161 ud2 = (c1 & 0xffff0000) >> 16;
4162 #if HOST_BITS_PER_WIDE_INT >= 64
4166 ud4 = (c2 & 0xffff0000) >> 16;
4168 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4169 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4172 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4174 emit_move_insn (dest, GEN_INT (ud1));
4177 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4178 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4181 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4184 emit_move_insn (dest, GEN_INT (ud2 << 16));
4186 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4188 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4189 || (ud4 == 0 && ! (ud3 & 0x8000)))
4192 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4195 emit_move_insn (dest, GEN_INT (ud3 << 16));
4198 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
4199 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
4201 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4206 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4209 emit_move_insn (dest, GEN_INT (ud4 << 16));
4212 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
4214 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
4216 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
4217 GEN_INT (ud2 << 16)));
4219 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4225 /* Helper for the following. Get rid of [r+r] memory refs
4226 in cases where it won't work (TImode, TFmode). */
4229 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4231 if (GET_CODE (operands[0]) == MEM
4232 && GET_CODE (XEXP (operands[0], 0)) != REG
4233 && ! reload_in_progress)
4235 = replace_equiv_address (operands[0],
4236 copy_addr_to_reg (XEXP (operands[0], 0)));
4238 if (GET_CODE (operands[1]) == MEM
4239 && GET_CODE (XEXP (operands[1], 0)) != REG
4240 && ! reload_in_progress)
4242 = replace_equiv_address (operands[1],
4243 copy_addr_to_reg (XEXP (operands[1], 0)));
4246 /* Emit a move from SOURCE to DEST in mode MODE. */
4248 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4252 operands[1] = source;
4254 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4255 if (GET_CODE (operands[1]) == CONST_DOUBLE
4256 && ! FLOAT_MODE_P (mode)
4257 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4259 /* FIXME. This should never happen. */
4260 /* Since it seems that it does, do the safe thing and convert
4262 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4264 if (GET_CODE (operands[1]) == CONST_DOUBLE
4265 && ! FLOAT_MODE_P (mode)
4266 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
4267 && CONST_DOUBLE_LOW (operands[1]) >= 0)
4268 || (CONST_DOUBLE_HIGH (operands[1]) == -1
4269 && CONST_DOUBLE_LOW (operands[1]) < 0)))
4272 /* Check if GCC is setting up a block move that will end up using FP
4273 registers as temporaries. We must make sure this is acceptable. */
4274 if (GET_CODE (operands[0]) == MEM
4275 && GET_CODE (operands[1]) == MEM
4277 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4278 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4279 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4280 ? 32 : MEM_ALIGN (operands[0])))
4281 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4283 : MEM_ALIGN (operands[1]))))
4284 && ! MEM_VOLATILE_P (operands [0])
4285 && ! MEM_VOLATILE_P (operands [1]))
4287 emit_move_insn (adjust_address (operands[0], SImode, 0),
4288 adjust_address (operands[1], SImode, 0));
4289 emit_move_insn (adjust_address (operands[0], SImode, 4),
4290 adjust_address (operands[1], SImode, 4));
4294 if (!no_new_pseudos && GET_CODE (operands[0]) != REG
4295 && !gpc_reg_operand (operands[1], mode))
4296 operands[1] = force_reg (mode, operands[1]);
4298 if (mode == SFmode && ! TARGET_POWERPC
4299 && TARGET_HARD_FLOAT && TARGET_FPRS
4300 && GET_CODE (operands[0]) == MEM)
4304 if (reload_in_progress || reload_completed)
4305 regnum = true_regnum (operands[1]);
4306 else if (GET_CODE (operands[1]) == REG)
4307 regnum = REGNO (operands[1]);
4311 /* If operands[1] is a register, on POWER it may have
4312 double-precision data in it, so truncate it to single
4314 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4317 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
4318 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4319 operands[1] = newreg;
4323 /* Recognize the case where operand[1] is a reference to thread-local
4324 data and load its address to a register. */
4325 if (GET_CODE (operands[1]) == SYMBOL_REF)
4327 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
4329 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
4332 /* Handle the case where reload calls us with an invalid address. */
4333 if (reload_in_progress && mode == Pmode
4334 && (! general_operand (operands[1], mode)
4335 || ! nonimmediate_operand (operands[0], mode)))
4338 /* 128-bit constant floating-point values on Darwin should really be
4339 loaded as two parts. */
4340 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
4341 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
4342 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4344 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4345 know how to get a DFmode SUBREG of a TFmode. */
4346 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
4347 simplify_gen_subreg (DImode, operands[1], mode, 0),
4349 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
4350 GET_MODE_SIZE (DImode)),
4351 simplify_gen_subreg (DImode, operands[1], mode,
4352 GET_MODE_SIZE (DImode)),
4357 /* FIXME: In the long term, this switch statement should go away
4358 and be replaced by a sequence of tests based on things like
4364 if (CONSTANT_P (operands[1])
4365 && GET_CODE (operands[1]) != CONST_INT)
4366 operands[1] = force_const_mem (mode, operands[1]);
4370 rs6000_eliminate_indexed_memrefs (operands);
4375 if (CONSTANT_P (operands[1])
4376 && ! easy_fp_constant (operands[1], mode))
4377 operands[1] = force_const_mem (mode, operands[1]);
4388 if (CONSTANT_P (operands[1])
4389 && !easy_vector_constant (operands[1], mode))
4390 operands[1] = force_const_mem (mode, operands[1]);
4395 /* Use default pattern for address of ELF small data */
4398 && DEFAULT_ABI == ABI_V4
4399 && (GET_CODE (operands[1]) == SYMBOL_REF
4400 || GET_CODE (operands[1]) == CONST)
4401 && small_data_operand (operands[1], mode))
4403 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4407 if (DEFAULT_ABI == ABI_V4
4408 && mode == Pmode && mode == SImode
4409 && flag_pic == 1 && got_operand (operands[1], mode))
4411 emit_insn (gen_movsi_got (operands[0], operands[1]));
4415 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4419 && CONSTANT_P (operands[1])
4420 && GET_CODE (operands[1]) != HIGH
4421 && GET_CODE (operands[1]) != CONST_INT)
4423 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
4425 /* If this is a function address on -mcall-aixdesc,
4426 convert it to the address of the descriptor. */
4427 if (DEFAULT_ABI == ABI_AIX
4428 && GET_CODE (operands[1]) == SYMBOL_REF
4429 && XSTR (operands[1], 0)[0] == '.')
4431 const char *name = XSTR (operands[1], 0);
4433 while (*name == '.')
4435 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4436 CONSTANT_POOL_ADDRESS_P (new_ref)
4437 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4438 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4439 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4440 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
4441 operands[1] = new_ref;
4444 if (DEFAULT_ABI == ABI_DARWIN)
4447 if (MACHO_DYNAMIC_NO_PIC_P)
4449 /* Take care of any required data indirection. */
4450 operands[1] = rs6000_machopic_legitimize_pic_address (
4451 operands[1], mode, operands[0]);
4452 if (operands[0] != operands[1])
4453 emit_insn (gen_rtx_SET (VOIDmode,
4454 operands[0], operands[1]));
4458 emit_insn (gen_macho_high (target, operands[1]));
4459 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4463 emit_insn (gen_elf_high (target, operands[1]));
4464 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4468 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4469 and we have put it in the TOC, we just need to make a TOC-relative
4472 && GET_CODE (operands[1]) == SYMBOL_REF
4473 && constant_pool_expr_p (operands[1])
4474 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4475 get_pool_mode (operands[1])))
4477 operands[1] = create_TOC_reference (operands[1]);
4479 else if (mode == Pmode
4480 && CONSTANT_P (operands[1])
4481 && ((GET_CODE (operands[1]) != CONST_INT
4482 && ! easy_fp_constant (operands[1], mode))
4483 || (GET_CODE (operands[1]) == CONST_INT
4484 && num_insns_constant (operands[1], mode) > 2)
4485 || (GET_CODE (operands[0]) == REG
4486 && FP_REGNO_P (REGNO (operands[0]))))
4487 && GET_CODE (operands[1]) != HIGH
4488 && ! legitimate_constant_pool_address_p (operands[1])
4489 && ! toc_relative_expr_p (operands[1]))
4491 /* Emit a USE operation so that the constant isn't deleted if
4492 expensive optimizations are turned on because nobody
4493 references it. This should only be done for operands that
4494 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4495 This should not be done for operands that contain LABEL_REFs.
4496 For now, we just handle the obvious case. */
4497 if (GET_CODE (operands[1]) != LABEL_REF)
4498 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4501 /* Darwin uses a special PIC legitimizer. */
4502 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4505 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4507 if (operands[0] != operands[1])
4508 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4513 /* If we are to limit the number of things we put in the TOC and
4514 this is a symbol plus a constant we can add in one insn,
4515 just put the symbol in the TOC and add the constant. Don't do
4516 this if reload is in progress. */
4517 if (GET_CODE (operands[1]) == CONST
4518 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4519 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4520 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4521 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4522 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4523 && ! side_effects_p (operands[0]))
4526 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4527 rtx other = XEXP (XEXP (operands[1], 0), 1);
4529 sym = force_reg (mode, sym);
4531 emit_insn (gen_addsi3 (operands[0], sym, other));
4533 emit_insn (gen_adddi3 (operands[0], sym, other));
4537 operands[1] = force_const_mem (mode, operands[1]);
4540 && constant_pool_expr_p (XEXP (operands[1], 0))
4541 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4542 get_pool_constant (XEXP (operands[1], 0)),
4543 get_pool_mode (XEXP (operands[1], 0))))
4546 = gen_const_mem (mode,
4547 create_TOC_reference (XEXP (operands[1], 0)));
4548 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4554 rs6000_eliminate_indexed_memrefs (operands);
4558 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4560 gen_rtx_SET (VOIDmode,
4561 operands[0], operands[1]),
4562 gen_rtx_CLOBBER (VOIDmode,
4563 gen_rtx_SCRATCH (SImode)))));
4572 /* Above, we may have called force_const_mem which may have returned
4573 an invalid address. If we can, fix this up; otherwise, reload will
4574 have to deal with it. */
4575 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4576 operands[1] = validize_mem (operands[1]);
4579 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4582 /* Nonzero if we can use a floating-point register to pass this arg. */
4583 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4584 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
4585 && (CUM)->fregno <= FP_ARG_MAX_REG \
4586 && TARGET_HARD_FLOAT && TARGET_FPRS)
4588 /* Nonzero if we can use an AltiVec register to pass this arg. */
4589 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4590 (ALTIVEC_VECTOR_MODE (MODE) \
4591 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4592 && TARGET_ALTIVEC_ABI \
4595 /* Return a nonzero value to say to return the function value in
4596 memory, just as large structures are always returned. TYPE will be
4597 the data type of the value, and FNTYPE will be the type of the
4598 function doing the returning, or @code{NULL} for libcalls.
4600 The AIX ABI for the RS/6000 specifies that all structures are
4601 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4602 specifies that structures <= 8 bytes are returned in r3/r4, but a
4603 draft put them in memory, and GCC used to implement the draft
4604 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
4605 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4606 compatibility can change DRAFT_V4_STRUCT_RET to override the
4607 default, and -m switches get the final word. See
4608 rs6000_override_options for more details.
4610 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4611 long double support is enabled. These values are returned in memory.
4613 int_size_in_bytes returns -1 for variable size objects, which go in
4614 memory always. The cast to unsigned makes -1 > 8. */
4617 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4619 /* In the darwin64 abi, try to use registers for larger structs
4621 if (AGGREGATE_TYPE_P (type)
4622 && rs6000_darwin64_abi
4623 && TREE_CODE (type) == RECORD_TYPE
4624 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 32)
4625 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 0))
4628 if (AGGREGATE_TYPE_P (type)
4629 && (TARGET_AIX_STRUCT_RET
4630 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4633 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4634 modes only exist for GCC vector types if -maltivec. */
4635 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4636 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4639 /* Return synthetic vectors in memory. */
4640 if (TREE_CODE (type) == VECTOR_TYPE
4641 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4643 static bool warned_for_return_big_vectors = false;
4644 if (!warned_for_return_big_vectors)
4646 warning ("GCC vector returned by reference: "
4647 "non-standard ABI extension with no compatibility guarantee");
4648 warned_for_return_big_vectors = true;
4653 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
4659 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4660 for a call to a function whose data type is FNTYPE.
4661 For a library call, FNTYPE is 0.
4663 For incoming args we set the number of arguments in the prototype large
4664 so we never return a PARALLEL. */
4667 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4668 rtx libname ATTRIBUTE_UNUSED, int incoming,
4669 int libcall, int n_named_args)
4671 static CUMULATIVE_ARGS zero_cumulative;
4673 *cum = zero_cumulative;
4675 cum->fregno = FP_ARG_MIN_REG;
4676 cum->vregno = ALTIVEC_ARG_MIN_REG;
4677 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4678 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4679 ? CALL_LIBCALL : CALL_NORMAL);
4680 cum->sysv_gregno = GP_ARG_MIN_REG;
4681 cum->stdarg = fntype
4682 && (TYPE_ARG_TYPES (fntype) != 0
4683 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4684 != void_type_node));
4686 cum->nargs_prototype = 0;
4687 if (incoming || cum->prototype)
4688 cum->nargs_prototype = n_named_args;
4690 /* Check for a longcall attribute. */
4691 if ((!fntype && rs6000_default_long_calls)
4693 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4694 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4695 cum->call_cookie |= CALL_LONG;
4697 if (TARGET_DEBUG_ARG)
4699 fprintf (stderr, "\ninit_cumulative_args:");
4702 tree ret_type = TREE_TYPE (fntype);
4703 fprintf (stderr, " ret code = %s,",
4704 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4707 if (cum->call_cookie & CALL_LONG)
4708 fprintf (stderr, " longcall,");
4710 fprintf (stderr, " proto = %d, nargs = %d\n",
4711 cum->prototype, cum->nargs_prototype);
4716 && TARGET_ALTIVEC_ABI
4717 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4719 error ("Cannot return value in vector register because"
4720 " altivec instructions are disabled, use -maltivec"
4721 " to enable them.");
4725 /* Return true if TYPE must be passed on the stack and not in registers. */
4728 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4730 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4731 return must_pass_in_stack_var_size (mode, type);
4733 return must_pass_in_stack_var_size_or_pad (mode, type);
4736 /* If defined, a C expression which determines whether, and in which
4737 direction, to pad out an argument with extra space. The value
4738 should be of type `enum direction': either `upward' to pad above
4739 the argument, `downward' to pad below, or `none' to inhibit
4742 For the AIX ABI structs are always stored left shifted in their
4746 function_arg_padding (enum machine_mode mode, tree type)
4748 #ifndef AGGREGATE_PADDING_FIXED
4749 #define AGGREGATE_PADDING_FIXED 0
4751 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4752 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4755 if (!AGGREGATE_PADDING_FIXED)
4757 /* GCC used to pass structures of the same size as integer types as
4758 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4759 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4760 passed padded downward, except that -mstrict-align further
4761 muddied the water in that multi-component structures of 2 and 4
4762 bytes in size were passed padded upward.
4764 The following arranges for best compatibility with previous
4765 versions of gcc, but removes the -mstrict-align dependency. */
4766 if (BYTES_BIG_ENDIAN)
4768 HOST_WIDE_INT size = 0;
4770 if (mode == BLKmode)
4772 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4773 size = int_size_in_bytes (type);
4776 size = GET_MODE_SIZE (mode);
4778 if (size == 1 || size == 2 || size == 4)
4784 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4786 if (type != 0 && AGGREGATE_TYPE_P (type))
4790 /* Fall back to the default. */
4791 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4794 /* If defined, a C expression that gives the alignment boundary, in bits,
4795 of an argument with the specified mode and type. If it is not defined,
4796 PARM_BOUNDARY is used for all arguments.
4798 V.4 wants long longs to be double word aligned.
4799 Doubleword align SPE vectors.
4800 Quadword align Altivec vectors.
4801 Quadword align large synthetic vector types. */
4804 function_arg_boundary (enum machine_mode mode, tree type)
4806 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4808 else if (SPE_VECTOR_MODE (mode)
4809 || (type && TREE_CODE (type) == VECTOR_TYPE
4810 && int_size_in_bytes (type) >= 8
4811 && int_size_in_bytes (type) < 16))
4813 else if (ALTIVEC_VECTOR_MODE (mode)
4814 || (type && TREE_CODE (type) == VECTOR_TYPE
4815 && int_size_in_bytes (type) >= 16))
4818 return PARM_BOUNDARY;
4821 /* Compute the size (in words) of a function argument. */
4823 static unsigned long
4824 rs6000_arg_size (enum machine_mode mode, tree type)
4828 if (mode != BLKmode)
4829 size = GET_MODE_SIZE (mode);
4831 size = int_size_in_bytes (type);
4834 return (size + 3) >> 2;
4836 return (size + 7) >> 3;
4839 /* The darwin64 ABI calls for us to recurse down through structs,
4840 applying the same rules to struct elements as if a reference to
4841 each were being passed directly. */
4844 darwin64_function_arg_advance (CUMULATIVE_ARGS *cum, tree type,
4845 int named, int depth)
4850 switch (TREE_CODE (type))
4853 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4854 if (TREE_CODE (f) == FIELD_DECL)
4856 ftype = TREE_TYPE (f);
4857 function_arg_advance (cum, TYPE_MODE (ftype), ftype,
4863 tot = int_size_in_bytes (type);
4866 ftype = TREE_TYPE (type);
4867 tot /= int_size_in_bytes (ftype);
4869 for (i = 0; i < tot; ++i)
4871 function_arg_advance (cum, TYPE_MODE (ftype), ftype,
4881 /* Update the data in CUM to advance over an argument
4882 of mode MODE and data type TYPE.
4883 (TYPE is null for libcalls where that information may not be available.)
4885 Note that for args passed by reference, function_arg will be called
4886 with MODE and TYPE set to that of the pointer to the arg, not the arg
4890 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4891 tree type, int named, int depth)
4893 /* Only tick off an argument if we're not recursing. */
4895 cum->nargs_prototype--;
4897 if (TARGET_ALTIVEC_ABI
4898 && (ALTIVEC_VECTOR_MODE (mode)
4899 || (type && TREE_CODE (type) == VECTOR_TYPE
4900 && int_size_in_bytes (type) == 16)))
4904 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4907 if (!TARGET_ALTIVEC)
4908 error ("Cannot pass argument in vector register because"
4909 " altivec instructions are disabled, use -maltivec"
4910 " to enable them.");
4912 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4913 even if it is going to be passed in a vector register.
4914 Darwin does the same for variable-argument functions. */
4915 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4916 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4926 /* Vector parameters must be 16-byte aligned. This places
4927 them at 2 mod 4 in terms of words in 32-bit mode, since
4928 the parameter save area starts at offset 24 from the
4929 stack. In 64-bit mode, they just have to start on an
4930 even word, since the parameter save area is 16-byte
4931 aligned. Space for GPRs is reserved even if the argument
4932 will be passed in memory. */
4934 align = (2 - cum->words) & 3;
4936 align = cum->words & 1;
4937 cum->words += align + rs6000_arg_size (mode, type);
4939 if (TARGET_DEBUG_ARG)
4941 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4943 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4944 cum->nargs_prototype, cum->prototype,
4945 GET_MODE_NAME (mode));
4949 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4951 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4954 else if (rs6000_darwin64_abi
4956 && (TREE_CODE (type) == RECORD_TYPE
4957 || TREE_CODE (type) == ARRAY_TYPE))
4958 darwin64_function_arg_advance (cum, type, named, depth);
4960 else if (DEFAULT_ABI == ABI_V4)
4962 if (TARGET_HARD_FLOAT && TARGET_FPRS
4963 && (mode == SFmode || mode == DFmode))
4965 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4970 cum->words += cum->words & 1;
4971 cum->words += rs6000_arg_size (mode, type);
4976 int n_words = rs6000_arg_size (mode, type);
4977 int gregno = cum->sysv_gregno;
4979 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4980 (r7,r8) or (r9,r10). As does any other 2 word item such
4981 as complex int due to a historical mistake. */
4983 gregno += (1 - gregno) & 1;
4985 /* Multi-reg args are not split between registers and stack. */
4986 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4988 /* Long long and SPE vectors are aligned on the stack.
4989 So are other 2 word items such as complex int due to
4990 a historical mistake. */
4992 cum->words += cum->words & 1;
4993 cum->words += n_words;
4996 /* Note: continuing to accumulate gregno past when we've started
4997 spilling to the stack indicates the fact that we've started
4998 spilling to the stack to expand_builtin_saveregs. */
4999 cum->sysv_gregno = gregno + n_words;
5002 if (TARGET_DEBUG_ARG)
5004 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5005 cum->words, cum->fregno);
5006 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5007 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5008 fprintf (stderr, "mode = %4s, named = %d\n",
5009 GET_MODE_NAME (mode), named);
5014 int n_words = rs6000_arg_size (mode, type);
5015 int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5017 /* The simple alignment calculation here works because
5018 function_arg_boundary / PARM_BOUNDARY will only be 1 or 2.
5019 If we ever want to handle alignments larger than 8 bytes for
5020 32-bit or 16 bytes for 64-bit, then we'll need to take into
5021 account the offset to the start of the parm save area. */
5022 align &= cum->words;
5023 cum->words += align + n_words;
5025 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5026 && TARGET_HARD_FLOAT && TARGET_FPRS)
5027 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5029 if (TARGET_DEBUG_ARG)
5031 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5032 cum->words, cum->fregno);
5033 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5034 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5035 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5036 named, align, depth);
5042 spe_build_register_parallel (enum machine_mode mode, int gregno)
5045 enum machine_mode inner = SImode;
5049 r1 = gen_rtx_REG (inner, gregno);
5050 r1 = gen_rtx_EXPR_LIST (SImode, r1, const0_rtx);
5051 r2 = gen_rtx_REG (inner, gregno + 1);
5052 r2 = gen_rtx_EXPR_LIST (SImode, r2, GEN_INT (4));
5053 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5055 else if (mode == DCmode)
5057 r1 = gen_rtx_REG (inner, gregno);
5058 r1 = gen_rtx_EXPR_LIST (SImode, r1, const0_rtx);
5059 r2 = gen_rtx_REG (inner, gregno + 1);
5060 r2 = gen_rtx_EXPR_LIST (SImode, r2, GEN_INT (4));
5061 r3 = gen_rtx_REG (inner, gregno + 2);
5062 r3 = gen_rtx_EXPR_LIST (SImode, r3, GEN_INT (8));
5063 r4 = gen_rtx_REG (inner, gregno + 3);
5064 r4 = gen_rtx_EXPR_LIST (SImode, r4, GEN_INT (12));
5065 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r2, r3, r4));
5072 /* Determine where to put a SIMD argument on the SPE. */
5074 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5077 int gregno = cum->sysv_gregno;
5079 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5080 are passed and returned in a pair of GPRs for ABI compatibility. */
5081 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
5083 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5084 gregno += (1 - gregno) & 1;
5086 /* We do not split between registers and stack. */
5087 if (gregno + 1 > GP_ARG_MAX_REG)
5090 return spe_build_register_parallel (mode, gregno);
5094 int n_words = rs6000_arg_size (mode, type);
5096 /* SPE vectors are put in odd registers. */
5097 if (n_words == 2 && (gregno & 1) == 0)
5100 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5103 enum machine_mode m = SImode;
5105 r1 = gen_rtx_REG (m, gregno);
5106 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5107 r2 = gen_rtx_REG (m, gregno + 1);
5108 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5109 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5116 if (gregno <= GP_ARG_MAX_REG)
5117 return gen_rtx_REG (mode, gregno);
5123 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5124 the register(s) to be used for each field and subfield of a struct
5125 being passed by value, along with the offset of where the
5126 register's value may be found in the block. */
5129 rs6000_darwin64_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5130 tree type, int named)
5132 tree f, ftype, offset;
5133 rtx rvec[FIRST_PSEUDO_REGISTER], sub, suboff, roffset;
5134 int k = 0, i, j, bytepos, subbytepos, tot;
5135 CUMULATIVE_ARGS saved_cum = *cum;
5136 enum machine_mode submode;
5138 switch (TREE_CODE (type))
5141 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5142 if (TREE_CODE (f) == FIELD_DECL)
5144 ftype = TREE_TYPE (f);
5145 offset = DECL_FIELD_OFFSET (f);
5146 bytepos = int_bit_position (f) / BITS_PER_UNIT;
5147 /* Force substructs to be handled as BLKmode even if
5148 they're small enough to be recorded as DImode, so we
5149 drill through to non-record fields. */
5150 submode = TYPE_MODE (ftype);
5151 if (TREE_CODE (ftype) == RECORD_TYPE)
5153 sub = function_arg (cum, submode, ftype, named);
5154 if (sub == NULL_RTX)
5156 if (GET_CODE (sub) == PARALLEL)
5158 for (i = 0; i < XVECLEN (sub, 0); i++)
5160 rtx subsub = XVECEXP (sub, 0, i);
5161 suboff = XEXP (subsub, 1);
5162 subbytepos = INTVAL (suboff);
5163 subbytepos += bytepos;
5164 roffset = gen_rtx_CONST_INT (SImode, subbytepos);
5165 subsub = XEXP (subsub, 0);
5166 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset);
5171 roffset = gen_rtx_CONST_INT (SImode, bytepos);
5172 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
5174 /* Now do an arg advance to get all the cumulative arg
5175 stuff set correctly for the next subfield. Note that it
5176 has no lasting effect, because it is being done on a
5177 temporary copy of the cumulative arg data. */
5178 function_arg_advance (cum, submode, ftype, named, 1);
5183 tot = rs6000_arg_size (mode, type);
5188 for (j = 0; j < tot; ++j)
5190 sub = gen_rtx_REG ((TARGET_64BIT ? DImode : SImode), GP_ARG_MIN_REG + cum->words++);
5191 roffset = gen_rtx_CONST_INT (SImode, bytepos);
5192 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
5193 if (cum->words >= GP_ARG_NUM_REG)
5195 bytepos += (TARGET_64BIT ? 8 : 4);
5200 tot = int_size_in_bytes (type);
5203 ftype = TREE_TYPE (type);
5204 tot /= int_size_in_bytes (ftype);
5207 for (j = 0; j < tot; ++j)
5209 /* Force substructs to be handled as BLKmode even if
5210 they're small enough to be recorded as DImode, so we
5211 drill through to non-record fields. */
5212 submode = TYPE_MODE (ftype);
5213 if (TREE_CODE (ftype) == RECORD_TYPE)
5215 sub = function_arg (cum, submode, ftype, named);
5216 if (sub == NULL_RTX)
5218 if (GET_CODE (sub) == PARALLEL)
5220 for (i = 0; i < XVECLEN (sub, 0); i++)
5222 rtx subsub = XVECEXP (sub, 0, i);
5224 suboff = XEXP (subsub, 1);
5225 subbytepos = INTVAL (suboff);
5226 subbytepos += bytepos;
5227 roffset = gen_rtx_CONST_INT (SImode, subbytepos);
5228 subsub = XEXP (subsub, 0);
5229 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset);
5234 roffset = gen_rtx_CONST_INT (SImode, bytepos);
5235 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
5237 /* Now do an arg advance to get all the cumulative arg
5238 stuff set correctly for the next subfield. Note that it
5239 has no lasting effect, because it is being done on a
5240 temporary copy of the cumulative arg data. */
5241 function_arg_advance (cum, submode, ftype, named, 1);
5242 bytepos += int_size_in_bytes (ftype);
5252 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5257 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5260 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5264 rtx rvec[GP_ARG_NUM_REG + 1];
5266 if (align_words >= GP_ARG_NUM_REG)
5269 n_units = rs6000_arg_size (mode, type);
5271 /* Optimize the simple case where the arg fits in one gpr, except in
5272 the case of BLKmode due to assign_parms assuming that registers are
5273 BITS_PER_WORD wide. */
5275 || (n_units == 1 && mode != BLKmode))
5276 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5279 if (align_words + n_units > GP_ARG_NUM_REG)
5280 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5281 using a magic NULL_RTX component.
5282 FIXME: This is not strictly correct. Only some of the arg
5283 belongs in memory, not all of it. However, there isn't any way
5284 to do this currently, apart from building rtx descriptions for
5285 the pieces of memory we want stored. Due to bugs in the generic
5286 code we can't use the normal function_arg_partial_nregs scheme
5287 with the PARALLEL arg description we emit here.
5288 In any case, the code to store the whole arg to memory is often
5289 more efficient than code to store pieces, and we know that space
5290 is available in the right place for the whole arg. */
5291 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5296 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5297 rtx off = GEN_INT (i++ * 4);
5298 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5300 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5302 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5305 /* Determine where to put an argument to a function.
5306 Value is zero to push the argument on the stack,
5307 or a hard register in which to store the argument.
5309 MODE is the argument's machine mode.
5310 TYPE is the data type of the argument (as a tree).
5311 This is null for libcalls where that information may
5313 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5314 the preceding args and about the function being called.
5315 NAMED is nonzero if this argument is a named parameter
5316 (otherwise it is an extra parameter matching an ellipsis).
5318 On RS/6000 the first eight words of non-FP are normally in registers
5319 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5320 Under V.4, the first 8 FP args are in registers.
5322 If this is floating-point and no prototype is specified, we use
5323 both an FP and integer register (or possibly FP reg and stack). Library
5324 functions (when CALL_LIBCALL is set) always have the proper types for args,
5325 so we can pass the FP value just in one register. emit_library_function
5326 doesn't support PARALLEL anyway.
5328 Note that for args passed by reference, function_arg will be called
5329 with MODE and TYPE set to that of the pointer to the arg, not the arg
5333 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5334 tree type, int named)
5336 enum rs6000_abi abi = DEFAULT_ABI;
5338 /* Return a marker to indicate whether CR1 needs to set or clear the
5339 bit that V.4 uses to say fp args were passed in registers.
5340 Assume that we don't need the marker for software floating point,
5341 or compiler generated library calls. */
5342 if (mode == VOIDmode)
5345 && cum->nargs_prototype < 0
5346 && (cum->call_cookie & CALL_LIBCALL) == 0
5347 && (cum->prototype || TARGET_NO_PROTOTYPE))
5349 /* For the SPE, we need to crxor CR6 always. */
5351 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5352 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5353 return GEN_INT (cum->call_cookie
5354 | ((cum->fregno == FP_ARG_MIN_REG)
5355 ? CALL_V4_SET_FP_ARGS
5356 : CALL_V4_CLEAR_FP_ARGS));
5359 return GEN_INT (cum->call_cookie);
5363 && rs6000_darwin64_abi
5364 && (TREE_CODE (type) == RECORD_TYPE
5365 || TREE_CODE (type) == UNION_TYPE
5366 || TREE_CODE (type) == ARRAY_TYPE))
5368 rtx rslt = rs6000_darwin64_function_arg (cum, mode, type, named);
5369 if (rslt != NULL_RTX)
5371 /* Else fall through to usual handling. */
5374 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5375 if (TARGET_64BIT && ! cum->prototype)
5377 /* Vector parameters get passed in vector register
5378 and also in GPRs or memory, in absence of prototype. */
5381 align_words = (cum->words + 1) & ~1;
5383 if (align_words >= GP_ARG_NUM_REG)
5389 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5391 return gen_rtx_PARALLEL (mode,
5393 gen_rtx_EXPR_LIST (VOIDmode,
5395 gen_rtx_EXPR_LIST (VOIDmode,
5396 gen_rtx_REG (mode, cum->vregno),
5400 return gen_rtx_REG (mode, cum->vregno);
5401 else if (TARGET_ALTIVEC_ABI
5402 && (ALTIVEC_VECTOR_MODE (mode)
5403 || (type && TREE_CODE (type) == VECTOR_TYPE
5404 && int_size_in_bytes (type) == 16)))
5406 if (named || abi == ABI_V4)
5410 /* Vector parameters to varargs functions under AIX or Darwin
5411 get passed in memory and possibly also in GPRs. */
5412 int align, align_words, n_words;
5413 enum machine_mode part_mode;
5415 /* Vector parameters must be 16-byte aligned. This places them at
5416 2 mod 4 in terms of words in 32-bit mode, since the parameter
5417 save area starts at offset 24 from the stack. In 64-bit mode,
5418 they just have to start on an even word, since the parameter
5419 save area is 16-byte aligned. */
5421 align = (2 - cum->words) & 3;
5423 align = cum->words & 1;
5424 align_words = cum->words + align;
5426 /* Out of registers? Memory, then. */
5427 if (align_words >= GP_ARG_NUM_REG)
5430 if (TARGET_32BIT && TARGET_POWERPC64)
5431 return rs6000_mixed_function_arg (mode, type, align_words);
5433 /* The vector value goes in GPRs. Only the part of the
5434 value in GPRs is reported here. */
5436 n_words = rs6000_arg_size (mode, type);
5437 if (align_words + n_words > GP_ARG_NUM_REG)
5438 /* Fortunately, there are only two possibilities, the value
5439 is either wholly in GPRs or half in GPRs and half not. */
5442 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5445 else if (TARGET_SPE_ABI && TARGET_SPE
5446 && (SPE_VECTOR_MODE (mode)
5447 || (TARGET_E500_DOUBLE && (mode == DFmode
5448 || mode == DCmode))))
5449 return rs6000_spe_function_arg (cum, mode, type);
5451 else if (abi == ABI_V4)
5453 if (TARGET_HARD_FLOAT && TARGET_FPRS
5454 && (mode == SFmode || mode == DFmode))
5456 if (cum->fregno <= FP_ARG_V4_MAX_REG)
5457 return gen_rtx_REG (mode, cum->fregno);
5463 int n_words = rs6000_arg_size (mode, type);
5464 int gregno = cum->sysv_gregno;
5466 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5467 (r7,r8) or (r9,r10). As does any other 2 word item such
5468 as complex int due to a historical mistake. */
5470 gregno += (1 - gregno) & 1;
5472 /* Multi-reg args are not split between registers and stack. */
5473 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5476 if (TARGET_32BIT && TARGET_POWERPC64)
5477 return rs6000_mixed_function_arg (mode, type,
5478 gregno - GP_ARG_MIN_REG);
5479 return gen_rtx_REG (mode, gregno);
5484 int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5485 int align_words = cum->words + (cum->words & align);
5487 if (USE_FP_FOR_ARG_P (cum, mode, type))
5489 rtx rvec[GP_ARG_NUM_REG + 1];
5493 enum machine_mode fmode = mode;
5494 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5496 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5498 /* Currently, we only ever need one reg here because complex
5499 doubles are split. */
5500 if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode)
5503 /* Long double split over regs and memory. */
5507 /* Do we also need to pass this arg in the parameter save
5510 && (cum->nargs_prototype <= 0
5511 || (DEFAULT_ABI == ABI_AIX
5513 && align_words >= GP_ARG_NUM_REG)));
5515 if (!needs_psave && mode == fmode)
5516 return gen_rtx_REG (fmode, cum->fregno);
5521 /* Describe the part that goes in gprs or the stack.
5522 This piece must come first, before the fprs. */
5523 if (align_words < GP_ARG_NUM_REG)
5525 unsigned long n_words = rs6000_arg_size (mode, type);
5527 if (align_words + n_words > GP_ARG_NUM_REG
5528 || (TARGET_32BIT && TARGET_POWERPC64))
5530 /* If this is partially on the stack, then we only
5531 include the portion actually in registers here. */
5532 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5535 if (align_words + n_words > GP_ARG_NUM_REG
5536 && (TARGET_32BIT && TARGET_POWERPC64))
5537 /* Not all of the arg fits in gprs. Say that it
5538 goes in memory too, using a magic NULL_RTX
5539 component. Also see comment in
5540 rs6000_mixed_function_arg for why the normal
5541 function_arg_partial_nregs scheme doesn't work
5543 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5547 r = gen_rtx_REG (rmode,
5548 GP_ARG_MIN_REG + align_words);
5549 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5550 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5552 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5556 /* The whole arg fits in gprs. */
5557 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5558 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5562 /* It's entirely in memory. */
5563 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5566 /* Describe where this piece goes in the fprs. */
5567 r = gen_rtx_REG (fmode, cum->fregno);
5568 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5570 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5572 else if (align_words < GP_ARG_NUM_REG)
5574 if (TARGET_32BIT && TARGET_POWERPC64)
5575 return rs6000_mixed_function_arg (mode, type, align_words);
5577 if (mode == BLKmode)
5580 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5587 /* For an arg passed partly in registers and partly in memory, this is
5588 the number of registers used. For args passed entirely in registers
5589 or entirely in memory, zero. When an arg is described by a PARALLEL,
5590 perhaps using more than one register type, this function returns the
5591 number of registers used by the first element of the PARALLEL. */
5594 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5595 tree type, int named)
5602 if (DEFAULT_ABI == ABI_V4)
5605 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5606 && cum->nargs_prototype >= 0)
5609 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5610 parm_offset = TARGET_32BIT ? 2 : 0;
5611 align_words = cum->words + ((parm_offset - cum->words) & align);
5613 if (USE_FP_FOR_ARG_P (cum, mode, type)
5614 /* If we are passing this arg in gprs as well, then this function
5615 should return the number of gprs (or memory) partially passed,
5616 *not* the number of fprs. */
5618 && (cum->nargs_prototype <= 0
5619 || (DEFAULT_ABI == ABI_AIX
5621 && align_words >= GP_ARG_NUM_REG))))
5623 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
5624 ret = FP_ARG_MAX_REG + 1 - cum->fregno;
5625 else if (cum->nargs_prototype >= 0)
5629 if (align_words < GP_ARG_NUM_REG
5630 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5631 ret = GP_ARG_NUM_REG - align_words;
5633 if (ret != 0 && TARGET_DEBUG_ARG)
5634 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
5639 /* A C expression that indicates when an argument must be passed by
5640 reference. If nonzero for an argument, a copy of that argument is
5641 made in memory and a pointer to the argument is passed instead of
5642 the argument itself. The pointer is passed in whatever way is
5643 appropriate for passing a pointer to that type.
5645 Under V.4, aggregates and long double are passed by reference.
5647 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5648 reference unless the AltiVec vector extension ABI is in force.
5650 As an extension to all ABIs, variable sized types are passed by
5654 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5655 enum machine_mode mode, tree type,
5656 bool named ATTRIBUTE_UNUSED)
5658 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
5660 if (TARGET_DEBUG_ARG)
5661 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5668 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5670 if (TARGET_DEBUG_ARG)
5671 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5675 if (int_size_in_bytes (type) < 0)
5677 if (TARGET_DEBUG_ARG)
5678 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5682 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5683 modes only exist for GCC vector types if -maltivec. */
5684 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5686 if (TARGET_DEBUG_ARG)
5687 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5691 /* Pass synthetic vectors in memory. */
5692 if (TREE_CODE (type) == VECTOR_TYPE
5693 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5695 static bool warned_for_pass_big_vectors = false;
5696 if (TARGET_DEBUG_ARG)
5697 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5698 if (!warned_for_pass_big_vectors)
5700 warning ("GCC vector passed by reference: "
5701 "non-standard ABI extension with no compatibility guarantee");
5702 warned_for_pass_big_vectors = true;
5711 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5714 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5719 for (i = 0; i < nregs; i++)
5721 rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode));
5722 if (reload_completed)
5724 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5727 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5728 i * GET_MODE_SIZE(reg_mode));
5731 tem = replace_equiv_address (tem, XEXP (tem, 0));
5733 if (tem == NULL_RTX)
5736 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5740 /* Perform any needed actions needed for a function that is receiving a
5741 variable number of arguments.
5745 MODE and TYPE are the mode and type of the current parameter.
5747 PRETEND_SIZE is a variable that should be set to the amount of stack
5748 that must be pushed by the prolog to pretend that our caller pushed
5751 Normally, this macro will push all remaining incoming registers on the
5752 stack and set PRETEND_SIZE to the length of the registers pushed. */
5755 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5756 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5759 CUMULATIVE_ARGS next_cum;
5760 int reg_size = TARGET_32BIT ? 4 : 8;
5761 rtx save_area = NULL_RTX, mem;
5762 int first_reg_offset, set;
5764 /* Skip the last named argument. */
5766 function_arg_advance (&next_cum, mode, type, 1, 0);
5768 if (DEFAULT_ABI == ABI_V4)
5771 save_area = plus_constant (virtual_stack_vars_rtx,
5772 - RS6000_VARARGS_SIZE);
5774 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5778 first_reg_offset = next_cum.words;
5779 save_area = virtual_incoming_args_rtx;
5781 if (targetm.calls.must_pass_in_stack (mode, type))
5782 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5785 set = get_varargs_alias_set ();
5786 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
5788 mem = gen_rtx_MEM (BLKmode,
5789 plus_constant (save_area,
5790 first_reg_offset * reg_size)),
5791 set_mem_alias_set (mem, set);
5792 set_mem_align (mem, BITS_PER_WORD);
5794 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5795 GP_ARG_NUM_REG - first_reg_offset);
5798 /* Save FP registers if needed. */
5799 if (DEFAULT_ABI == ABI_V4
5800 && TARGET_HARD_FLOAT && TARGET_FPRS
5802 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
5804 int fregno = next_cum.fregno;
5805 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5806 rtx lab = gen_label_rtx ();
5807 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
5810 (gen_rtx_SET (VOIDmode,
5812 gen_rtx_IF_THEN_ELSE (VOIDmode,
5813 gen_rtx_NE (VOIDmode, cr1,
5815 gen_rtx_LABEL_REF (VOIDmode, lab),
5818 while (fregno <= FP_ARG_V4_MAX_REG)
5820 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5821 set_mem_alias_set (mem, set);
5822 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5823 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5832 /* Create the va_list data type. */
5835 rs6000_build_builtin_va_list (void)
5837 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5839 /* For AIX, prefer 'char *' because that's what the system
5840 header files like. */
5841 if (DEFAULT_ABI != ABI_V4)
5842 return build_pointer_type (char_type_node);
5844 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5845 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5847 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5848 unsigned_char_type_node);
5849 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5850 unsigned_char_type_node);
5851 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5853 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5854 short_unsigned_type_node);
5855 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5857 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5860 DECL_FIELD_CONTEXT (f_gpr) = record;
5861 DECL_FIELD_CONTEXT (f_fpr) = record;
5862 DECL_FIELD_CONTEXT (f_res) = record;
5863 DECL_FIELD_CONTEXT (f_ovf) = record;
5864 DECL_FIELD_CONTEXT (f_sav) = record;
5866 TREE_CHAIN (record) = type_decl;
5867 TYPE_NAME (record) = type_decl;
5868 TYPE_FIELDS (record) = f_gpr;
5869 TREE_CHAIN (f_gpr) = f_fpr;
5870 TREE_CHAIN (f_fpr) = f_res;
5871 TREE_CHAIN (f_res) = f_ovf;
5872 TREE_CHAIN (f_ovf) = f_sav;
5874 layout_type (record);
5876 /* The correct type is an array type of one element. */
5877 return build_array_type (record, build_index_type (size_zero_node));
5880 /* Implement va_start. */
5883 rs6000_va_start (tree valist, rtx nextarg)
5885 HOST_WIDE_INT words, n_gpr, n_fpr;
5886 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5887 tree gpr, fpr, ovf, sav, t;
5889 /* Only SVR4 needs something special. */
5890 if (DEFAULT_ABI != ABI_V4)
5892 std_expand_builtin_va_start (valist, nextarg);
5896 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5897 f_fpr = TREE_CHAIN (f_gpr);
5898 f_res = TREE_CHAIN (f_fpr);
5899 f_ovf = TREE_CHAIN (f_res);
5900 f_sav = TREE_CHAIN (f_ovf);
5902 valist = build_va_arg_indirect_ref (valist);
5903 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5904 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5905 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5906 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5908 /* Count number of gp and fp argument registers used. */
5909 words = current_function_args_info.words;
5910 n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG;
5911 n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG;
5913 if (TARGET_DEBUG_ARG)
5914 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5915 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5916 words, n_gpr, n_fpr);
5918 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5919 build_int_cst (NULL_TREE, n_gpr));
5920 TREE_SIDE_EFFECTS (t) = 1;
5921 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5923 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5924 build_int_cst (NULL_TREE, n_fpr));
5925 TREE_SIDE_EFFECTS (t) = 1;
5926 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5928 /* Find the overflow area. */
5929 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5931 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
5932 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5933 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5934 TREE_SIDE_EFFECTS (t) = 1;
5935 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5937 /* Find the register save area. */
5938 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5939 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
5940 build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE));
5941 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5942 TREE_SIDE_EFFECTS (t) = 1;
5943 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5946 /* Implement va_arg. */
5949 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5951 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5952 tree gpr, fpr, ovf, sav, reg, t, u;
5953 int size, rsize, n_reg, sav_ofs, sav_scale;
5954 tree lab_false, lab_over, addr;
5956 tree ptrtype = build_pointer_type (type);
5958 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5960 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5961 return build_va_arg_indirect_ref (t);
5964 if (DEFAULT_ABI != ABI_V4)
5966 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5968 tree elem_type = TREE_TYPE (type);
5969 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5970 int elem_size = GET_MODE_SIZE (elem_mode);
5972 if (elem_size < UNITS_PER_WORD)
5974 tree real_part, imag_part;
5975 tree post = NULL_TREE;
5977 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5979 /* Copy the value into a temporary, lest the formal temporary
5980 be reused out from under us. */
5981 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5982 append_to_statement_list (post, pre_p);
5984 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5987 return build (COMPLEX_EXPR, type, real_part, imag_part);
5991 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5994 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5995 f_fpr = TREE_CHAIN (f_gpr);
5996 f_res = TREE_CHAIN (f_fpr);
5997 f_ovf = TREE_CHAIN (f_res);
5998 f_sav = TREE_CHAIN (f_ovf);
6000 valist = build_va_arg_indirect_ref (valist);
6001 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6002 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6003 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6004 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6006 size = int_size_in_bytes (type);
6007 rsize = (size + 3) / 4;
6010 if (TARGET_HARD_FLOAT && TARGET_FPRS
6011 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
6013 /* FP args go in FP registers, if present. */
6018 if (TYPE_MODE (type) == DFmode)
6023 /* Otherwise into GP registers. */
6032 /* Pull the value out of the saved registers.... */
6035 addr = create_tmp_var (ptr_type_node, "addr");
6036 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6038 /* AltiVec vectors never go in registers when -mabi=altivec. */
6039 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6043 lab_false = create_artificial_label ();
6044 lab_over = create_artificial_label ();
6046 /* Long long and SPE vectors are aligned in the registers.
6047 As are any other 2 gpr item such as complex int due to a
6048 historical mistake. */
6052 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
6053 size_int (n_reg - 1));
6054 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
6057 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6058 t = build2 (GE_EXPR, boolean_type_node, u, t);
6059 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6060 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6061 gimplify_and_add (t, pre_p);
6065 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6067 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
6068 u = build1 (CONVERT_EXPR, integer_type_node, u);
6069 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
6070 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
6072 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
6073 gimplify_and_add (t, pre_p);
6075 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6076 gimplify_and_add (t, pre_p);
6078 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6079 append_to_statement_list (t, pre_p);
6083 /* Ensure that we don't find any more args in regs.
6084 Alignment has taken care of the n_reg == 2 case. */
6085 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
6086 gimplify_and_add (t, pre_p);
6090 /* ... otherwise out of the overflow area. */
6092 /* Care for on-stack alignment if needed. */
6096 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6097 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6098 build_int_cst (NULL_TREE, -align));
6100 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6102 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
6103 gimplify_and_add (u, pre_p);
6105 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6106 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
6107 gimplify_and_add (t, pre_p);
6111 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6112 append_to_statement_list (t, pre_p);
6115 addr = fold_convert (ptrtype, addr);
6116 return build_va_arg_indirect_ref (addr);
6121 #define def_builtin(MASK, NAME, TYPE, CODE) \
6123 if ((MASK) & target_flags) \
6124 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
6128 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6130 static const struct builtin_description bdesc_3arg[] =
6132 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6133 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6134 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6135 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6136 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6137 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6138 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6139 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6140 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6141 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6142 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6143 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6144 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6145 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6146 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6147 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6148 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6149 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6150 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6151 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6152 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6153 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6154 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6157 /* DST operations: void foo (void *, const int, const char). */
6159 static const struct builtin_description bdesc_dst[] =
6161 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6162 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6163 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6164 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
6167 /* Simple binary operations: VECc = foo (VECa, VECb). */
6169 static struct builtin_description bdesc_2arg[] =
6171 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6172 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6173 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6174 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6175 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6176 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6177 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6178 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6179 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6180 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6181 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6182 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6183 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6184 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6185 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6186 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6187 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6188 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6189 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6190 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6191 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6192 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6193 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6194 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6195 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6196 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6197 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6198 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6199 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6200 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6201 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6202 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6203 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6204 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6205 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6206 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6207 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6208 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6209 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6210 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6211 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6212 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6213 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6214 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6215 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6216 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6217 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6218 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6219 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6220 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6221 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6222 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6223 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6224 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6225 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6226 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6227 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6228 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6229 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6230 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6231 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6232 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6233 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6234 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6235 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6236 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6237 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6238 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6239 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6240 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
6241 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6242 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
6243 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6244 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6245 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6246 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6247 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6248 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6249 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6250 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6251 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6252 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6253 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6254 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6255 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6256 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6257 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6258 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6259 { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6260 { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6261 { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6262 { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6263 { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6264 { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6265 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6266 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6267 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6268 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6269 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6270 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6271 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6272 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6273 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6274 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6275 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6276 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6277 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6278 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6279 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6280 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6281 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6282 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6283 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6285 /* Place holder, leave as first spe builtin. */
6286 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6287 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6288 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6289 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6290 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6291 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6292 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6293 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6294 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6295 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6296 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6297 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6298 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6299 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6300 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6301 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6302 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6303 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6304 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6305 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6306 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6307 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6308 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6309 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6310 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6311 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6312 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6313 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6314 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6315 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6316 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6317 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6318 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6319 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6320 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6321 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6322 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6323 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6324 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6325 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6326 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6327 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6328 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6329 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6330 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6331 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6332 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6333 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6334 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6335 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6336 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6337 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6338 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6339 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6340 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6341 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6342 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6343 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6344 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6345 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6346 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6347 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6348 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6349 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6350 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6351 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6352 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6353 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6354 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6355 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6356 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6357 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6358 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6359 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6360 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6361 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6362 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6363 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6364 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6365 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6366 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6367 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6368 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6369 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6370 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6371 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6372 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6373 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6374 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6375 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6376 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6377 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6378 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6379 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6380 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6381 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6382 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6383 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6384 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6385 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6386 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6387 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6388 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6389 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6390 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6391 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6392 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6393 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6394 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6396 /* SPE binary operations expecting a 5-bit unsigned literal. */
6397 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6399 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6400 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6401 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6402 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6403 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6404 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6405 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6406 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6407 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6408 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6409 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6410 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6411 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6412 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6413 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6414 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6415 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6416 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6417 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6418 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6419 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6420 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6421 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6422 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6423 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6424 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6426 /* Place-holder. Leave as last binary SPE builtin. */
6427 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
6430 /* AltiVec predicates. */
6432 struct builtin_description_predicates
6434 const unsigned int mask;
6435 const enum insn_code icode;
6437 const char *const name;
6438 const enum rs6000_builtins code;
6441 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6443 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6444 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6445 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6446 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6447 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6448 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6449 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6450 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6451 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6452 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6453 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6454 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6455 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
6458 /* SPE predicates. */
6459 static struct builtin_description bdesc_spe_predicates[] =
6461 /* Place-holder. Leave as first. */
6462 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6463 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6464 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6465 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6466 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6467 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6468 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6469 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6470 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6471 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6472 /* Place-holder. Leave as last. */
6473 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6476 /* SPE evsel predicates. */
6477 static struct builtin_description bdesc_spe_evsel[] =
6479 /* Place-holder. Leave as first. */
6480 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6481 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6482 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6483 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6484 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6485 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6486 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6487 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6488 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6489 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6490 /* Place-holder. Leave as last. */
6491 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6494 /* ABS* operations. */
6496 static const struct builtin_description bdesc_abs[] =
6498 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6499 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6500 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6501 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6502 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6503 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6504 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6507 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6510 static struct builtin_description bdesc_1arg[] =
6512 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6513 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6514 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6515 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6516 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6517 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6518 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6519 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6520 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6521 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6522 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6523 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6524 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6525 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6526 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6527 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6528 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6530 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6531 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6532 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6533 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6534 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6535 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6536 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6537 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6538 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6539 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6540 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6541 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6542 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6543 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6544 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6545 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6546 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6547 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6548 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6549 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6550 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6551 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6552 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6553 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6554 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6555 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6556 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6557 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6558 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6559 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6561 /* Place-holder. Leave as last unary SPE builtin. */
6562 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
6566 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6569 tree arg0 = TREE_VALUE (arglist);
6570 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6571 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6572 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6574 if (icode == CODE_FOR_nothing)
6575 /* Builtin not supported on this processor. */
6578 /* If we got invalid arguments bail out before generating bad rtl. */
6579 if (arg0 == error_mark_node)
6582 if (icode == CODE_FOR_altivec_vspltisb
6583 || icode == CODE_FOR_altivec_vspltish
6584 || icode == CODE_FOR_altivec_vspltisw
6585 || icode == CODE_FOR_spe_evsplatfi
6586 || icode == CODE_FOR_spe_evsplati)
6588 /* Only allow 5-bit *signed* literals. */
6589 if (GET_CODE (op0) != CONST_INT
6590 || INTVAL (op0) > 0x1f
6591 || INTVAL (op0) < -0x1f)
6593 error ("argument 1 must be a 5-bit signed literal");
6599 || GET_MODE (target) != tmode
6600 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6601 target = gen_reg_rtx (tmode);
6603 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6604 op0 = copy_to_mode_reg (mode0, op0);
6606 pat = GEN_FCN (icode) (target, op0);
6615 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6617 rtx pat, scratch1, scratch2;
6618 tree arg0 = TREE_VALUE (arglist);
6619 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6620 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6621 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6623 /* If we have invalid arguments, bail out before generating bad rtl. */
6624 if (arg0 == error_mark_node)
6628 || GET_MODE (target) != tmode
6629 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6630 target = gen_reg_rtx (tmode);
6632 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6633 op0 = copy_to_mode_reg (mode0, op0);
6635 scratch1 = gen_reg_rtx (mode0);
6636 scratch2 = gen_reg_rtx (mode0);
6638 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6647 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6650 tree arg0 = TREE_VALUE (arglist);
6651 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6652 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6653 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6654 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6655 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6656 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6658 if (icode == CODE_FOR_nothing)
6659 /* Builtin not supported on this processor. */
6662 /* If we got invalid arguments bail out before generating bad rtl. */
6663 if (arg0 == error_mark_node || arg1 == error_mark_node)
6666 if (icode == CODE_FOR_altivec_vcfux
6667 || icode == CODE_FOR_altivec_vcfsx
6668 || icode == CODE_FOR_altivec_vctsxs
6669 || icode == CODE_FOR_altivec_vctuxs
6670 || icode == CODE_FOR_altivec_vspltb
6671 || icode == CODE_FOR_altivec_vsplth
6672 || icode == CODE_FOR_altivec_vspltw
6673 || icode == CODE_FOR_spe_evaddiw
6674 || icode == CODE_FOR_spe_evldd
6675 || icode == CODE_FOR_spe_evldh
6676 || icode == CODE_FOR_spe_evldw
6677 || icode == CODE_FOR_spe_evlhhesplat
6678 || icode == CODE_FOR_spe_evlhhossplat
6679 || icode == CODE_FOR_spe_evlhhousplat
6680 || icode == CODE_FOR_spe_evlwhe
6681 || icode == CODE_FOR_spe_evlwhos
6682 || icode == CODE_FOR_spe_evlwhou
6683 || icode == CODE_FOR_spe_evlwhsplat
6684 || icode == CODE_FOR_spe_evlwwsplat
6685 || icode == CODE_FOR_spe_evrlwi
6686 || icode == CODE_FOR_spe_evslwi
6687 || icode == CODE_FOR_spe_evsrwis
6688 || icode == CODE_FOR_spe_evsubifw
6689 || icode == CODE_FOR_spe_evsrwiu)
6691 /* Only allow 5-bit unsigned literals. */
6693 if (TREE_CODE (arg1) != INTEGER_CST
6694 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6696 error ("argument 2 must be a 5-bit unsigned literal");
6702 || GET_MODE (target) != tmode
6703 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6704 target = gen_reg_rtx (tmode);
6706 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6707 op0 = copy_to_mode_reg (mode0, op0);
6708 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6709 op1 = copy_to_mode_reg (mode1, op1);
6711 pat = GEN_FCN (icode) (target, op0, op1);
6720 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6721 tree arglist, rtx target)
6724 tree cr6_form = TREE_VALUE (arglist);
6725 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6726 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6727 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6728 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6729 enum machine_mode tmode = SImode;
6730 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6731 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6734 if (TREE_CODE (cr6_form) != INTEGER_CST)
6736 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6740 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6745 /* If we have invalid arguments, bail out before generating bad rtl. */
6746 if (arg0 == error_mark_node || arg1 == error_mark_node)
6750 || GET_MODE (target) != tmode
6751 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6752 target = gen_reg_rtx (tmode);
6754 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6755 op0 = copy_to_mode_reg (mode0, op0);
6756 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6757 op1 = copy_to_mode_reg (mode1, op1);
6759 scratch = gen_reg_rtx (mode0);
6761 pat = GEN_FCN (icode) (scratch, op0, op1,
6762 gen_rtx_SYMBOL_REF (Pmode, opcode));
6767 /* The vec_any* and vec_all* predicates use the same opcodes for two
6768 different operations, but the bits in CR6 will be different
6769 depending on what information we want. So we have to play tricks
6770 with CR6 to get the right bits out.
6772 If you think this is disgusting, look at the specs for the
6773 AltiVec predicates. */
6775 switch (cr6_form_int)
6778 emit_insn (gen_cr6_test_for_zero (target));
6781 emit_insn (gen_cr6_test_for_zero_reverse (target));
6784 emit_insn (gen_cr6_test_for_lt (target));
6787 emit_insn (gen_cr6_test_for_lt_reverse (target));
6790 error ("argument 1 of __builtin_altivec_predicate is out of range");
6798 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6801 tree arg0 = TREE_VALUE (arglist);
6802 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6803 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6804 enum machine_mode mode0 = Pmode;
6805 enum machine_mode mode1 = Pmode;
6806 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6807 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6809 if (icode == CODE_FOR_nothing)
6810 /* Builtin not supported on this processor. */
6813 /* If we got invalid arguments bail out before generating bad rtl. */
6814 if (arg0 == error_mark_node || arg1 == error_mark_node)
6818 || GET_MODE (target) != tmode
6819 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6820 target = gen_reg_rtx (tmode);
6822 op1 = copy_to_mode_reg (mode1, op1);
6824 if (op0 == const0_rtx)
6826 addr = gen_rtx_MEM (tmode, op1);
6830 op0 = copy_to_mode_reg (mode0, op0);
6831 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6834 pat = GEN_FCN (icode) (target, addr);
6844 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6846 tree arg0 = TREE_VALUE (arglist);
6847 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6848 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6849 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6850 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6851 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6853 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6854 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6855 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6857 /* Invalid arguments. Bail before doing anything stoopid! */
6858 if (arg0 == error_mark_node
6859 || arg1 == error_mark_node
6860 || arg2 == error_mark_node)
6863 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6864 op0 = copy_to_mode_reg (mode2, op0);
6865 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6866 op1 = copy_to_mode_reg (mode0, op1);
6867 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6868 op2 = copy_to_mode_reg (mode1, op2);
6870 pat = GEN_FCN (icode) (op1, op2, op0);
6877 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6879 tree arg0 = TREE_VALUE (arglist);
6880 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6881 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6882 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6883 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6884 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6886 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6887 enum machine_mode mode1 = Pmode;
6888 enum machine_mode mode2 = Pmode;
6890 /* Invalid arguments. Bail before doing anything stoopid! */
6891 if (arg0 == error_mark_node
6892 || arg1 == error_mark_node
6893 || arg2 == error_mark_node)
6896 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6897 op0 = copy_to_mode_reg (tmode, op0);
6899 op2 = copy_to_mode_reg (mode2, op2);
6901 if (op1 == const0_rtx)
6903 addr = gen_rtx_MEM (tmode, op2);
6907 op1 = copy_to_mode_reg (mode1, op1);
6908 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6911 pat = GEN_FCN (icode) (addr, op0);
6918 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6921 tree arg0 = TREE_VALUE (arglist);
6922 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6923 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6924 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6925 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6926 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6927 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6928 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6929 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6930 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6932 if (icode == CODE_FOR_nothing)
6933 /* Builtin not supported on this processor. */
6936 /* If we got invalid arguments bail out before generating bad rtl. */
6937 if (arg0 == error_mark_node
6938 || arg1 == error_mark_node
6939 || arg2 == error_mark_node)
6942 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6943 || icode == CODE_FOR_altivec_vsldoi_v4si
6944 || icode == CODE_FOR_altivec_vsldoi_v8hi
6945 || icode == CODE_FOR_altivec_vsldoi_v16qi)
6947 /* Only allow 4-bit unsigned literals. */
6949 if (TREE_CODE (arg2) != INTEGER_CST
6950 || TREE_INT_CST_LOW (arg2) & ~0xf)
6952 error ("argument 3 must be a 4-bit unsigned literal");
6958 || GET_MODE (target) != tmode
6959 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6960 target = gen_reg_rtx (tmode);
6962 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6963 op0 = copy_to_mode_reg (mode0, op0);
6964 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6965 op1 = copy_to_mode_reg (mode1, op1);
6966 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6967 op2 = copy_to_mode_reg (mode2, op2);
6969 pat = GEN_FCN (icode) (target, op0, op1, op2);
6977 /* Expand the lvx builtins. */
6979 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
6981 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6982 tree arglist = TREE_OPERAND (exp, 1);
6983 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6985 enum machine_mode tmode, mode0;
6987 enum insn_code icode;
6991 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
6992 icode = CODE_FOR_altivec_lvx_v16qi;
6994 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
6995 icode = CODE_FOR_altivec_lvx_v8hi;
6997 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
6998 icode = CODE_FOR_altivec_lvx_v4si;
7000 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7001 icode = CODE_FOR_altivec_lvx_v4sf;
7010 arg0 = TREE_VALUE (arglist);
7011 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7012 tmode = insn_data[icode].operand[0].mode;
7013 mode0 = insn_data[icode].operand[1].mode;
7016 || GET_MODE (target) != tmode
7017 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7018 target = gen_reg_rtx (tmode);
7020 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7021 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7023 pat = GEN_FCN (icode) (target, op0);
7030 /* Expand the stvx builtins. */
7032 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7035 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7036 tree arglist = TREE_OPERAND (exp, 1);
7037 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7039 enum machine_mode mode0, mode1;
7041 enum insn_code icode;
7045 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7046 icode = CODE_FOR_altivec_stvx_v16qi;
7048 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7049 icode = CODE_FOR_altivec_stvx_v8hi;
7051 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7052 icode = CODE_FOR_altivec_stvx_v4si;
7054 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7055 icode = CODE_FOR_altivec_stvx_v4sf;
7062 arg0 = TREE_VALUE (arglist);
7063 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7064 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7065 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7066 mode0 = insn_data[icode].operand[0].mode;
7067 mode1 = insn_data[icode].operand[1].mode;
7069 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7070 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7071 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7072 op1 = copy_to_mode_reg (mode1, op1);
7074 pat = GEN_FCN (icode) (op0, op1);
7082 /* Expand the dst builtins. */
7084 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7087 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7088 tree arglist = TREE_OPERAND (exp, 1);
7089 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7090 tree arg0, arg1, arg2;
7091 enum machine_mode mode0, mode1, mode2;
7092 rtx pat, op0, op1, op2;
7093 struct builtin_description *d;
7098 /* Handle DST variants. */
7099 d = (struct builtin_description *) bdesc_dst;
7100 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7101 if (d->code == fcode)
7103 arg0 = TREE_VALUE (arglist);
7104 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7105 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7106 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7107 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7108 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7109 mode0 = insn_data[d->icode].operand[0].mode;
7110 mode1 = insn_data[d->icode].operand[1].mode;
7111 mode2 = insn_data[d->icode].operand[2].mode;
7113 /* Invalid arguments, bail out before generating bad rtl. */
7114 if (arg0 == error_mark_node
7115 || arg1 == error_mark_node
7116 || arg2 == error_mark_node)
7121 if (TREE_CODE (arg2) != INTEGER_CST
7122 || TREE_INT_CST_LOW (arg2) & ~0x3)
7124 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7128 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7129 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7130 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7131 op1 = copy_to_mode_reg (mode1, op1);
7133 pat = GEN_FCN (d->icode) (op0, op1, op2);
7143 /* Expand the builtin in EXP and store the result in TARGET. Store
7144 true in *EXPANDEDP if we found a builtin to expand. */
7146 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7148 struct builtin_description *d;
7149 struct builtin_description_predicates *dp;
7151 enum insn_code icode;
7152 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7153 tree arglist = TREE_OPERAND (exp, 1);
7156 enum machine_mode tmode, mode0;
7157 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7159 target = altivec_expand_ld_builtin (exp, target, expandedp);
7163 target = altivec_expand_st_builtin (exp, target, expandedp);
7167 target = altivec_expand_dst_builtin (exp, target, expandedp);
7175 case ALTIVEC_BUILTIN_STVX:
7176 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
7177 case ALTIVEC_BUILTIN_STVEBX:
7178 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
7179 case ALTIVEC_BUILTIN_STVEHX:
7180 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
7181 case ALTIVEC_BUILTIN_STVEWX:
7182 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
7183 case ALTIVEC_BUILTIN_STVXL:
7184 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
7186 case ALTIVEC_BUILTIN_MFVSCR:
7187 icode = CODE_FOR_altivec_mfvscr;
7188 tmode = insn_data[icode].operand[0].mode;
7191 || GET_MODE (target) != tmode
7192 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7193 target = gen_reg_rtx (tmode);
7195 pat = GEN_FCN (icode) (target);
7201 case ALTIVEC_BUILTIN_MTVSCR:
7202 icode = CODE_FOR_altivec_mtvscr;
7203 arg0 = TREE_VALUE (arglist);
7204 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7205 mode0 = insn_data[icode].operand[0].mode;
7207 /* If we got invalid arguments bail out before generating bad rtl. */
7208 if (arg0 == error_mark_node)
7211 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7212 op0 = copy_to_mode_reg (mode0, op0);
7214 pat = GEN_FCN (icode) (op0);
7219 case ALTIVEC_BUILTIN_DSSALL:
7220 emit_insn (gen_altivec_dssall ());
7223 case ALTIVEC_BUILTIN_DSS:
7224 icode = CODE_FOR_altivec_dss;
7225 arg0 = TREE_VALUE (arglist);
7227 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7228 mode0 = insn_data[icode].operand[0].mode;
7230 /* If we got invalid arguments bail out before generating bad rtl. */
7231 if (arg0 == error_mark_node)
7234 if (TREE_CODE (arg0) != INTEGER_CST
7235 || TREE_INT_CST_LOW (arg0) & ~0x3)
7237 error ("argument to dss must be a 2-bit unsigned literal");
7241 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7242 op0 = copy_to_mode_reg (mode0, op0);
7244 emit_insn (gen_altivec_dss (op0));
7247 case ALTIVEC_BUILTIN_COMPILETIME_ERROR:
7248 arg0 = TREE_VALUE (arglist);
7249 while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR
7250 || TREE_CODE (arg0) == ARRAY_REF)
7251 arg0 = TREE_OPERAND (arg0, 0);
7252 error ("invalid parameter combination for %qs AltiVec intrinsic",
7253 TREE_STRING_POINTER (arg0));
7258 /* Expand abs* operations. */
7259 d = (struct builtin_description *) bdesc_abs;
7260 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7261 if (d->code == fcode)
7262 return altivec_expand_abs_builtin (d->icode, arglist, target);
7264 /* Expand the AltiVec predicates. */
7265 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7266 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7267 if (dp->code == fcode)
7268 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7271 /* LV* are funky. We initialized them differently. */
7274 case ALTIVEC_BUILTIN_LVSL:
7275 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7277 case ALTIVEC_BUILTIN_LVSR:
7278 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7280 case ALTIVEC_BUILTIN_LVEBX:
7281 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7283 case ALTIVEC_BUILTIN_LVEHX:
7284 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7286 case ALTIVEC_BUILTIN_LVEWX:
7287 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7289 case ALTIVEC_BUILTIN_LVXL:
7290 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7292 case ALTIVEC_BUILTIN_LVX:
7293 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7304 /* Binops that need to be initialized manually, but can be expanded
7305 automagically by rs6000_expand_binop_builtin. */
7306 static struct builtin_description bdesc_2arg_spe[] =
7308 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7309 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7310 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7311 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7312 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7313 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7314 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7315 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7316 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7317 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7318 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7319 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7320 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7321 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7322 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7323 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7324 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7325 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7326 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7327 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7328 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7329 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7332 /* Expand the builtin in EXP and store the result in TARGET. Store
7333 true in *EXPANDEDP if we found a builtin to expand.
7335 This expands the SPE builtins that are not simple unary and binary
7338 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7340 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7341 tree arglist = TREE_OPERAND (exp, 1);
7343 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7344 enum insn_code icode;
7345 enum machine_mode tmode, mode0;
7347 struct builtin_description *d;
7352 /* Syntax check for a 5-bit unsigned immediate. */
7355 case SPE_BUILTIN_EVSTDD:
7356 case SPE_BUILTIN_EVSTDH:
7357 case SPE_BUILTIN_EVSTDW:
7358 case SPE_BUILTIN_EVSTWHE:
7359 case SPE_BUILTIN_EVSTWHO:
7360 case SPE_BUILTIN_EVSTWWE:
7361 case SPE_BUILTIN_EVSTWWO:
7362 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7363 if (TREE_CODE (arg1) != INTEGER_CST
7364 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7366 error ("argument 2 must be a 5-bit unsigned literal");
7374 /* The evsplat*i instructions are not quite generic. */
7377 case SPE_BUILTIN_EVSPLATFI:
7378 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7380 case SPE_BUILTIN_EVSPLATI:
7381 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7387 d = (struct builtin_description *) bdesc_2arg_spe;
7388 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7389 if (d->code == fcode)
7390 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7392 d = (struct builtin_description *) bdesc_spe_predicates;
7393 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7394 if (d->code == fcode)
7395 return spe_expand_predicate_builtin (d->icode, arglist, target);
7397 d = (struct builtin_description *) bdesc_spe_evsel;
7398 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7399 if (d->code == fcode)
7400 return spe_expand_evsel_builtin (d->icode, arglist, target);
7404 case SPE_BUILTIN_EVSTDDX:
7405 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7406 case SPE_BUILTIN_EVSTDHX:
7407 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7408 case SPE_BUILTIN_EVSTDWX:
7409 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7410 case SPE_BUILTIN_EVSTWHEX:
7411 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7412 case SPE_BUILTIN_EVSTWHOX:
7413 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7414 case SPE_BUILTIN_EVSTWWEX:
7415 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7416 case SPE_BUILTIN_EVSTWWOX:
7417 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7418 case SPE_BUILTIN_EVSTDD:
7419 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7420 case SPE_BUILTIN_EVSTDH:
7421 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7422 case SPE_BUILTIN_EVSTDW:
7423 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7424 case SPE_BUILTIN_EVSTWHE:
7425 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7426 case SPE_BUILTIN_EVSTWHO:
7427 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7428 case SPE_BUILTIN_EVSTWWE:
7429 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7430 case SPE_BUILTIN_EVSTWWO:
7431 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7432 case SPE_BUILTIN_MFSPEFSCR:
7433 icode = CODE_FOR_spe_mfspefscr;
7434 tmode = insn_data[icode].operand[0].mode;
7437 || GET_MODE (target) != tmode
7438 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7439 target = gen_reg_rtx (tmode);
7441 pat = GEN_FCN (icode) (target);
7446 case SPE_BUILTIN_MTSPEFSCR:
7447 icode = CODE_FOR_spe_mtspefscr;
7448 arg0 = TREE_VALUE (arglist);
7449 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7450 mode0 = insn_data[icode].operand[0].mode;
7452 if (arg0 == error_mark_node)
7455 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7456 op0 = copy_to_mode_reg (mode0, op0);
7458 pat = GEN_FCN (icode) (op0);
7471 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7473 rtx pat, scratch, tmp;
7474 tree form = TREE_VALUE (arglist);
7475 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7476 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7477 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7478 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7479 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7480 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7484 if (TREE_CODE (form) != INTEGER_CST)
7486 error ("argument 1 of __builtin_spe_predicate must be a constant");
7490 form_int = TREE_INT_CST_LOW (form);
7495 if (arg0 == error_mark_node || arg1 == error_mark_node)
7499 || GET_MODE (target) != SImode
7500 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7501 target = gen_reg_rtx (SImode);
7503 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7504 op0 = copy_to_mode_reg (mode0, op0);
7505 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7506 op1 = copy_to_mode_reg (mode1, op1);
7508 scratch = gen_reg_rtx (CCmode);
7510 pat = GEN_FCN (icode) (scratch, op0, op1);
7515 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7516 _lower_. We use one compare, but look in different bits of the
7517 CR for each variant.
7519 There are 2 elements in each SPE simd type (upper/lower). The CR
7520 bits are set as follows:
7522 BIT0 | BIT 1 | BIT 2 | BIT 3
7523 U | L | (U | L) | (U & L)
7525 So, for an "all" relationship, BIT 3 would be set.
7526 For an "any" relationship, BIT 2 would be set. Etc.
7528 Following traditional nomenclature, these bits map to:
7530 BIT0 | BIT 1 | BIT 2 | BIT 3
7533 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7538 /* All variant. OV bit. */
7540 /* We need to get to the OV bit, which is the ORDERED bit. We
7541 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7542 that's ugly and will trigger a validate_condition_mode abort.
7543 So let's just use another pattern. */
7544 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7546 /* Any variant. EQ bit. */
7550 /* Upper variant. LT bit. */
7554 /* Lower variant. GT bit. */
7559 error ("argument 1 of __builtin_spe_predicate is out of range");
7563 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7564 emit_move_insn (target, tmp);
7569 /* The evsel builtins look like this:
7571 e = __builtin_spe_evsel_OP (a, b, c, d);
7575 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7576 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7580 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7583 tree arg0 = TREE_VALUE (arglist);
7584 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7585 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7586 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7587 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7588 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7589 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7590 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
7591 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7592 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7597 if (arg0 == error_mark_node || arg1 == error_mark_node
7598 || arg2 == error_mark_node || arg3 == error_mark_node)
7602 || GET_MODE (target) != mode0
7603 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7604 target = gen_reg_rtx (mode0);
7606 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7607 op0 = copy_to_mode_reg (mode0, op0);
7608 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7609 op1 = copy_to_mode_reg (mode0, op1);
7610 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7611 op2 = copy_to_mode_reg (mode0, op2);
7612 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7613 op3 = copy_to_mode_reg (mode0, op3);
7615 /* Generate the compare. */
7616 scratch = gen_reg_rtx (CCmode);
7617 pat = GEN_FCN (icode) (scratch, op0, op1);
7622 if (mode0 == V2SImode)
7623 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7625 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7630 /* Expand an expression EXP that calls a built-in function,
7631 with result going to TARGET if that's convenient
7632 (and in mode MODE if that's convenient).
7633 SUBTARGET may be used as the target for computing one of EXP's operands.
7634 IGNORE is nonzero if the value is to be ignored. */
7637 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7638 enum machine_mode mode ATTRIBUTE_UNUSED,
7639 int ignore ATTRIBUTE_UNUSED)
7641 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7642 tree arglist = TREE_OPERAND (exp, 1);
7643 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7644 struct builtin_description *d;
7649 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7650 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7652 int icode = (int) CODE_FOR_altivec_lvsr;
7653 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7654 enum machine_mode mode = insn_data[icode].operand[1].mode;
7658 if (!TARGET_ALTIVEC)
7661 arg = TREE_VALUE (arglist);
7662 if (TREE_CODE (TREE_TYPE (arg)) != POINTER_TYPE)
7664 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7665 addr = memory_address (mode, op);
7666 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7670 /* For the load case need to negate the address. */
7671 op = gen_reg_rtx (GET_MODE (addr));
7672 emit_insn (gen_rtx_SET (VOIDmode, op,
7673 gen_rtx_NEG (GET_MODE (addr), addr)));
7675 op = gen_rtx_MEM (mode, op);
7678 || GET_MODE (target) != tmode
7679 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7680 target = gen_reg_rtx (tmode);
7682 /*pat = gen_altivec_lvsr (target, op);*/
7683 pat = GEN_FCN (icode) (target, op);
7693 ret = altivec_expand_builtin (exp, target, &success);
7700 ret = spe_expand_builtin (exp, target, &success);
7706 if (TARGET_ALTIVEC || TARGET_SPE)
7708 /* Handle simple unary operations. */
7709 d = (struct builtin_description *) bdesc_1arg;
7710 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7711 if (d->code == fcode)
7712 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7714 /* Handle simple binary operations. */
7715 d = (struct builtin_description *) bdesc_2arg;
7716 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7717 if (d->code == fcode)
7718 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7720 /* Handle simple ternary operations. */
7721 d = (struct builtin_description *) bdesc_3arg;
7722 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7723 if (d->code == fcode)
7724 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7732 build_opaque_vector_type (tree node, int nunits)
7734 node = copy_node (node);
7735 TYPE_MAIN_VARIANT (node) = node;
7736 return build_vector_type (node, nunits);
7740 rs6000_init_builtins (void)
7742 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7743 V2SF_type_node = build_vector_type (float_type_node, 2);
7744 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7745 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7746 V4SF_type_node = build_vector_type (float_type_node, 4);
7747 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7748 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7750 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7751 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7752 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7754 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7755 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7756 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7758 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7759 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7760 'vector unsigned short'. */
7762 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7763 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7764 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7765 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7767 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7768 get_identifier ("__bool char"),
7769 bool_char_type_node));
7770 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7771 get_identifier ("__bool short"),
7772 bool_short_type_node));
7773 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7774 get_identifier ("__bool int"),
7775 bool_int_type_node));
7776 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7777 get_identifier ("__pixel"),
7780 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7781 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7782 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7783 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7785 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7786 get_identifier ("__vector unsigned char"),
7787 unsigned_V16QI_type_node));
7788 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7789 get_identifier ("__vector signed char"),
7791 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7792 get_identifier ("__vector __bool char"),
7793 bool_V16QI_type_node));
7795 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7796 get_identifier ("__vector unsigned short"),
7797 unsigned_V8HI_type_node));
7798 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7799 get_identifier ("__vector signed short"),
7801 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7802 get_identifier ("__vector __bool short"),
7803 bool_V8HI_type_node));
7805 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7806 get_identifier ("__vector unsigned int"),
7807 unsigned_V4SI_type_node));
7808 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7809 get_identifier ("__vector signed int"),
7811 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7812 get_identifier ("__vector __bool int"),
7813 bool_V4SI_type_node));
7815 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7816 get_identifier ("__vector float"),
7818 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7819 get_identifier ("__vector __pixel"),
7820 pixel_V8HI_type_node));
7823 spe_init_builtins ();
7825 altivec_init_builtins ();
7826 if (TARGET_ALTIVEC || TARGET_SPE)
7827 rs6000_common_init_builtins ();
7830 /* Search through a set of builtins and enable the mask bits.
7831 DESC is an array of builtins.
7832 SIZE is the total number of builtins.
7833 START is the builtin enum at which to start.
7834 END is the builtin enum at which to end. */
7836 enable_mask_for_builtins (struct builtin_description *desc, int size,
7837 enum rs6000_builtins start,
7838 enum rs6000_builtins end)
7842 for (i = 0; i < size; ++i)
7843 if (desc[i].code == start)
7849 for (; i < size; ++i)
7851 /* Flip all the bits on. */
7852 desc[i].mask = target_flags;
7853 if (desc[i].code == end)
7859 spe_init_builtins (void)
7861 tree endlink = void_list_node;
7862 tree puint_type_node = build_pointer_type (unsigned_type_node);
7863 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
7864 struct builtin_description *d;
7867 tree v2si_ftype_4_v2si
7868 = build_function_type
7869 (opaque_V2SI_type_node,
7870 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7871 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7872 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7873 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7876 tree v2sf_ftype_4_v2sf
7877 = build_function_type
7878 (opaque_V2SF_type_node,
7879 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7880 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7881 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7882 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7885 tree int_ftype_int_v2si_v2si
7886 = build_function_type
7888 tree_cons (NULL_TREE, integer_type_node,
7889 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7890 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7893 tree int_ftype_int_v2sf_v2sf
7894 = build_function_type
7896 tree_cons (NULL_TREE, integer_type_node,
7897 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7898 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7901 tree void_ftype_v2si_puint_int
7902 = build_function_type (void_type_node,
7903 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7904 tree_cons (NULL_TREE, puint_type_node,
7905 tree_cons (NULL_TREE,
7909 tree void_ftype_v2si_puint_char
7910 = build_function_type (void_type_node,
7911 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7912 tree_cons (NULL_TREE, puint_type_node,
7913 tree_cons (NULL_TREE,
7917 tree void_ftype_v2si_pv2si_int
7918 = build_function_type (void_type_node,
7919 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7920 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7921 tree_cons (NULL_TREE,
7925 tree void_ftype_v2si_pv2si_char
7926 = build_function_type (void_type_node,
7927 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7928 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7929 tree_cons (NULL_TREE,
7934 = build_function_type (void_type_node,
7935 tree_cons (NULL_TREE, integer_type_node, endlink));
7938 = build_function_type (integer_type_node, endlink);
7940 tree v2si_ftype_pv2si_int
7941 = build_function_type (opaque_V2SI_type_node,
7942 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7943 tree_cons (NULL_TREE, integer_type_node,
7946 tree v2si_ftype_puint_int
7947 = build_function_type (opaque_V2SI_type_node,
7948 tree_cons (NULL_TREE, puint_type_node,
7949 tree_cons (NULL_TREE, integer_type_node,
7952 tree v2si_ftype_pushort_int
7953 = build_function_type (opaque_V2SI_type_node,
7954 tree_cons (NULL_TREE, pushort_type_node,
7955 tree_cons (NULL_TREE, integer_type_node,
7958 tree v2si_ftype_signed_char
7959 = build_function_type (opaque_V2SI_type_node,
7960 tree_cons (NULL_TREE, signed_char_type_node,
7963 /* The initialization of the simple binary and unary builtins is
7964 done in rs6000_common_init_builtins, but we have to enable the
7965 mask bits here manually because we have run out of `target_flags'
7966 bits. We really need to redesign this mask business. */
7968 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
7969 ARRAY_SIZE (bdesc_2arg),
7972 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
7973 ARRAY_SIZE (bdesc_1arg),
7975 SPE_BUILTIN_EVSUBFUSIAAW);
7976 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
7977 ARRAY_SIZE (bdesc_spe_predicates),
7978 SPE_BUILTIN_EVCMPEQ,
7979 SPE_BUILTIN_EVFSTSTLT);
7980 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
7981 ARRAY_SIZE (bdesc_spe_evsel),
7982 SPE_BUILTIN_EVSEL_CMPGTS,
7983 SPE_BUILTIN_EVSEL_FSTSTEQ);
7985 (*lang_hooks.decls.pushdecl)
7986 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
7987 opaque_V2SI_type_node));
7989 /* Initialize irregular SPE builtins. */
7991 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
7992 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
7993 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
7994 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
7995 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
7996 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
7997 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
7998 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
7999 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8000 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8001 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8002 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8003 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8004 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8005 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8006 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8007 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8008 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8011 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8012 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8013 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8014 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8015 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8016 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8017 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8018 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8019 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8020 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8021 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8022 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8023 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8024 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8025 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8026 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8027 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8028 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8029 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8030 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8031 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8032 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8035 d = (struct builtin_description *) bdesc_spe_predicates;
8036 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8040 switch (insn_data[d->icode].operand[1].mode)
8043 type = int_ftype_int_v2si_v2si;
8046 type = int_ftype_int_v2sf_v2sf;
8052 def_builtin (d->mask, d->name, type, d->code);
8055 /* Evsel predicates. */
8056 d = (struct builtin_description *) bdesc_spe_evsel;
8057 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8061 switch (insn_data[d->icode].operand[1].mode)
8064 type = v2si_ftype_4_v2si;
8067 type = v2sf_ftype_4_v2sf;
8073 def_builtin (d->mask, d->name, type, d->code);
8078 altivec_init_builtins (void)
8080 struct builtin_description *d;
8081 struct builtin_description_predicates *dp;
8083 tree pfloat_type_node = build_pointer_type (float_type_node);
8084 tree pint_type_node = build_pointer_type (integer_type_node);
8085 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8086 tree pchar_type_node = build_pointer_type (char_type_node);
8088 tree pvoid_type_node = build_pointer_type (void_type_node);
8090 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8091 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8092 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8093 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8095 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8097 tree int_ftype_int_v4si_v4si
8098 = build_function_type_list (integer_type_node,
8099 integer_type_node, V4SI_type_node,
8100 V4SI_type_node, NULL_TREE);
8101 tree v4sf_ftype_pcfloat
8102 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8103 tree void_ftype_pfloat_v4sf
8104 = build_function_type_list (void_type_node,
8105 pfloat_type_node, V4SF_type_node, NULL_TREE);
8106 tree v4si_ftype_pcint
8107 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8108 tree void_ftype_pint_v4si
8109 = build_function_type_list (void_type_node,
8110 pint_type_node, V4SI_type_node, NULL_TREE);
8111 tree v8hi_ftype_pcshort
8112 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8113 tree void_ftype_pshort_v8hi
8114 = build_function_type_list (void_type_node,
8115 pshort_type_node, V8HI_type_node, NULL_TREE);
8116 tree v16qi_ftype_pcchar
8117 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8118 tree void_ftype_pchar_v16qi
8119 = build_function_type_list (void_type_node,
8120 pchar_type_node, V16QI_type_node, NULL_TREE);
8121 tree void_ftype_v4si
8122 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8123 tree v8hi_ftype_void
8124 = build_function_type (V8HI_type_node, void_list_node);
8125 tree void_ftype_void
8126 = build_function_type (void_type_node, void_list_node);
8128 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8130 tree v16qi_ftype_long_pcvoid
8131 = build_function_type_list (V16QI_type_node,
8132 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8133 tree v8hi_ftype_long_pcvoid
8134 = build_function_type_list (V8HI_type_node,
8135 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8136 tree v4si_ftype_long_pcvoid
8137 = build_function_type_list (V4SI_type_node,
8138 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8140 tree void_ftype_v4si_long_pvoid
8141 = build_function_type_list (void_type_node,
8142 V4SI_type_node, long_integer_type_node,
8143 pvoid_type_node, NULL_TREE);
8144 tree void_ftype_v16qi_long_pvoid
8145 = build_function_type_list (void_type_node,
8146 V16QI_type_node, long_integer_type_node,
8147 pvoid_type_node, NULL_TREE);
8148 tree void_ftype_v8hi_long_pvoid
8149 = build_function_type_list (void_type_node,
8150 V8HI_type_node, long_integer_type_node,
8151 pvoid_type_node, NULL_TREE);
8152 tree int_ftype_int_v8hi_v8hi
8153 = build_function_type_list (integer_type_node,
8154 integer_type_node, V8HI_type_node,
8155 V8HI_type_node, NULL_TREE);
8156 tree int_ftype_int_v16qi_v16qi
8157 = build_function_type_list (integer_type_node,
8158 integer_type_node, V16QI_type_node,
8159 V16QI_type_node, NULL_TREE);
8160 tree int_ftype_int_v4sf_v4sf
8161 = build_function_type_list (integer_type_node,
8162 integer_type_node, V4SF_type_node,
8163 V4SF_type_node, NULL_TREE);
8164 tree v4si_ftype_v4si
8165 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8166 tree v8hi_ftype_v8hi
8167 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8168 tree v16qi_ftype_v16qi
8169 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8170 tree v4sf_ftype_v4sf
8171 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8172 tree void_ftype_pcvoid_int_int
8173 = build_function_type_list (void_type_node,
8174 pcvoid_type_node, integer_type_node,
8175 integer_type_node, NULL_TREE);
8176 tree int_ftype_pcchar
8177 = build_function_type_list (integer_type_node,
8178 pcchar_type_node, NULL_TREE);
8180 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8181 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8182 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8183 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8184 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8185 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8186 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8187 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8188 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8189 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8190 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8191 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8192 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8193 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8194 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8195 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8196 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8197 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8198 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8199 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8200 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8201 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8202 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8203 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8204 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8205 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8206 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8207 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8208 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8209 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8210 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8211 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8213 /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */
8214 def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar,
8215 ALTIVEC_BUILTIN_COMPILETIME_ERROR);
8217 /* Add the DST variants. */
8218 d = (struct builtin_description *) bdesc_dst;
8219 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8220 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8222 /* Initialize the predicates. */
8223 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8224 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8226 enum machine_mode mode1;
8229 mode1 = insn_data[dp->icode].operand[1].mode;
8234 type = int_ftype_int_v4si_v4si;
8237 type = int_ftype_int_v8hi_v8hi;
8240 type = int_ftype_int_v16qi_v16qi;
8243 type = int_ftype_int_v4sf_v4sf;
8249 def_builtin (dp->mask, dp->name, type, dp->code);
8252 /* Initialize the abs* operators. */
8253 d = (struct builtin_description *) bdesc_abs;
8254 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8256 enum machine_mode mode0;
8259 mode0 = insn_data[d->icode].operand[0].mode;
8264 type = v4si_ftype_v4si;
8267 type = v8hi_ftype_v8hi;
8270 type = v16qi_ftype_v16qi;
8273 type = v4sf_ftype_v4sf;
8279 def_builtin (d->mask, d->name, type, d->code);
8286 /* Initialize target builtin that implements
8287 targetm.vectorize.builtin_mask_for_load. */
8289 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8290 v16qi_ftype_long_pcvoid,
8291 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8292 BUILT_IN_MD, NULL, NULL_TREE);
8293 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8294 altivec_builtin_mask_for_load = decl;
8299 rs6000_common_init_builtins (void)
8301 struct builtin_description *d;
8304 tree v4sf_ftype_v4sf_v4sf_v16qi
8305 = build_function_type_list (V4SF_type_node,
8306 V4SF_type_node, V4SF_type_node,
8307 V16QI_type_node, NULL_TREE);
8308 tree v4si_ftype_v4si_v4si_v16qi
8309 = build_function_type_list (V4SI_type_node,
8310 V4SI_type_node, V4SI_type_node,
8311 V16QI_type_node, NULL_TREE);
8312 tree v8hi_ftype_v8hi_v8hi_v16qi
8313 = build_function_type_list (V8HI_type_node,
8314 V8HI_type_node, V8HI_type_node,
8315 V16QI_type_node, NULL_TREE);
8316 tree v16qi_ftype_v16qi_v16qi_v16qi
8317 = build_function_type_list (V16QI_type_node,
8318 V16QI_type_node, V16QI_type_node,
8319 V16QI_type_node, NULL_TREE);
8321 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8323 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8324 tree v16qi_ftype_int
8325 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8326 tree v8hi_ftype_v16qi
8327 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8328 tree v4sf_ftype_v4sf
8329 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8331 tree v2si_ftype_v2si_v2si
8332 = build_function_type_list (opaque_V2SI_type_node,
8333 opaque_V2SI_type_node,
8334 opaque_V2SI_type_node, NULL_TREE);
8336 tree v2sf_ftype_v2sf_v2sf
8337 = build_function_type_list (opaque_V2SF_type_node,
8338 opaque_V2SF_type_node,
8339 opaque_V2SF_type_node, NULL_TREE);
8341 tree v2si_ftype_int_int
8342 = build_function_type_list (opaque_V2SI_type_node,
8343 integer_type_node, integer_type_node,
8346 tree v2si_ftype_v2si
8347 = build_function_type_list (opaque_V2SI_type_node,
8348 opaque_V2SI_type_node, NULL_TREE);
8350 tree v2sf_ftype_v2sf
8351 = build_function_type_list (opaque_V2SF_type_node,
8352 opaque_V2SF_type_node, NULL_TREE);
8354 tree v2sf_ftype_v2si
8355 = build_function_type_list (opaque_V2SF_type_node,
8356 opaque_V2SI_type_node, NULL_TREE);
8358 tree v2si_ftype_v2sf
8359 = build_function_type_list (opaque_V2SI_type_node,
8360 opaque_V2SF_type_node, NULL_TREE);
8362 tree v2si_ftype_v2si_char
8363 = build_function_type_list (opaque_V2SI_type_node,
8364 opaque_V2SI_type_node,
8365 char_type_node, NULL_TREE);
8367 tree v2si_ftype_int_char
8368 = build_function_type_list (opaque_V2SI_type_node,
8369 integer_type_node, char_type_node, NULL_TREE);
8371 tree v2si_ftype_char
8372 = build_function_type_list (opaque_V2SI_type_node,
8373 char_type_node, NULL_TREE);
8375 tree int_ftype_int_int
8376 = build_function_type_list (integer_type_node,
8377 integer_type_node, integer_type_node,
8380 tree v4si_ftype_v4si_v4si
8381 = build_function_type_list (V4SI_type_node,
8382 V4SI_type_node, V4SI_type_node, NULL_TREE);
8383 tree v4sf_ftype_v4si_int
8384 = build_function_type_list (V4SF_type_node,
8385 V4SI_type_node, integer_type_node, NULL_TREE);
8386 tree v4si_ftype_v4sf_int
8387 = build_function_type_list (V4SI_type_node,
8388 V4SF_type_node, integer_type_node, NULL_TREE);
8389 tree v4si_ftype_v4si_int
8390 = build_function_type_list (V4SI_type_node,
8391 V4SI_type_node, integer_type_node, NULL_TREE);
8392 tree v8hi_ftype_v8hi_int
8393 = build_function_type_list (V8HI_type_node,
8394 V8HI_type_node, integer_type_node, NULL_TREE);
8395 tree v16qi_ftype_v16qi_int
8396 = build_function_type_list (V16QI_type_node,
8397 V16QI_type_node, integer_type_node, NULL_TREE);
8398 tree v16qi_ftype_v16qi_v16qi_int
8399 = build_function_type_list (V16QI_type_node,
8400 V16QI_type_node, V16QI_type_node,
8401 integer_type_node, NULL_TREE);
8402 tree v8hi_ftype_v8hi_v8hi_int
8403 = build_function_type_list (V8HI_type_node,
8404 V8HI_type_node, V8HI_type_node,
8405 integer_type_node, NULL_TREE);
8406 tree v4si_ftype_v4si_v4si_int
8407 = build_function_type_list (V4SI_type_node,
8408 V4SI_type_node, V4SI_type_node,
8409 integer_type_node, NULL_TREE);
8410 tree v4sf_ftype_v4sf_v4sf_int
8411 = build_function_type_list (V4SF_type_node,
8412 V4SF_type_node, V4SF_type_node,
8413 integer_type_node, NULL_TREE);
8414 tree v4sf_ftype_v4sf_v4sf
8415 = build_function_type_list (V4SF_type_node,
8416 V4SF_type_node, V4SF_type_node, NULL_TREE);
8417 tree v4sf_ftype_v4sf_v4sf_v4si
8418 = build_function_type_list (V4SF_type_node,
8419 V4SF_type_node, V4SF_type_node,
8420 V4SI_type_node, NULL_TREE);
8421 tree v4sf_ftype_v4sf_v4sf_v4sf
8422 = build_function_type_list (V4SF_type_node,
8423 V4SF_type_node, V4SF_type_node,
8424 V4SF_type_node, NULL_TREE);
8425 tree v4si_ftype_v4si_v4si_v4si
8426 = build_function_type_list (V4SI_type_node,
8427 V4SI_type_node, V4SI_type_node,
8428 V4SI_type_node, NULL_TREE);
8429 tree v8hi_ftype_v8hi_v8hi
8430 = build_function_type_list (V8HI_type_node,
8431 V8HI_type_node, V8HI_type_node, NULL_TREE);
8432 tree v8hi_ftype_v8hi_v8hi_v8hi
8433 = build_function_type_list (V8HI_type_node,
8434 V8HI_type_node, V8HI_type_node,
8435 V8HI_type_node, NULL_TREE);
8436 tree v4si_ftype_v8hi_v8hi_v4si
8437 = build_function_type_list (V4SI_type_node,
8438 V8HI_type_node, V8HI_type_node,
8439 V4SI_type_node, NULL_TREE);
8440 tree v4si_ftype_v16qi_v16qi_v4si
8441 = build_function_type_list (V4SI_type_node,
8442 V16QI_type_node, V16QI_type_node,
8443 V4SI_type_node, NULL_TREE);
8444 tree v16qi_ftype_v16qi_v16qi
8445 = build_function_type_list (V16QI_type_node,
8446 V16QI_type_node, V16QI_type_node, NULL_TREE);
8447 tree v4si_ftype_v4sf_v4sf
8448 = build_function_type_list (V4SI_type_node,
8449 V4SF_type_node, V4SF_type_node, NULL_TREE);
8450 tree v8hi_ftype_v16qi_v16qi
8451 = build_function_type_list (V8HI_type_node,
8452 V16QI_type_node, V16QI_type_node, NULL_TREE);
8453 tree v4si_ftype_v8hi_v8hi
8454 = build_function_type_list (V4SI_type_node,
8455 V8HI_type_node, V8HI_type_node, NULL_TREE);
8456 tree v8hi_ftype_v4si_v4si
8457 = build_function_type_list (V8HI_type_node,
8458 V4SI_type_node, V4SI_type_node, NULL_TREE);
8459 tree v16qi_ftype_v8hi_v8hi
8460 = build_function_type_list (V16QI_type_node,
8461 V8HI_type_node, V8HI_type_node, NULL_TREE);
8462 tree v4si_ftype_v16qi_v4si
8463 = build_function_type_list (V4SI_type_node,
8464 V16QI_type_node, V4SI_type_node, NULL_TREE);
8465 tree v4si_ftype_v16qi_v16qi
8466 = build_function_type_list (V4SI_type_node,
8467 V16QI_type_node, V16QI_type_node, NULL_TREE);
8468 tree v4si_ftype_v8hi_v4si
8469 = build_function_type_list (V4SI_type_node,
8470 V8HI_type_node, V4SI_type_node, NULL_TREE);
8471 tree v4si_ftype_v8hi
8472 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8473 tree int_ftype_v4si_v4si
8474 = build_function_type_list (integer_type_node,
8475 V4SI_type_node, V4SI_type_node, NULL_TREE);
8476 tree int_ftype_v4sf_v4sf
8477 = build_function_type_list (integer_type_node,
8478 V4SF_type_node, V4SF_type_node, NULL_TREE);
8479 tree int_ftype_v16qi_v16qi
8480 = build_function_type_list (integer_type_node,
8481 V16QI_type_node, V16QI_type_node, NULL_TREE);
8482 tree int_ftype_v8hi_v8hi
8483 = build_function_type_list (integer_type_node,
8484 V8HI_type_node, V8HI_type_node, NULL_TREE);
8486 /* Add the simple ternary operators. */
8487 d = (struct builtin_description *) bdesc_3arg;
8488 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8491 enum machine_mode mode0, mode1, mode2, mode3;
8494 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8497 mode0 = insn_data[d->icode].operand[0].mode;
8498 mode1 = insn_data[d->icode].operand[1].mode;
8499 mode2 = insn_data[d->icode].operand[2].mode;
8500 mode3 = insn_data[d->icode].operand[3].mode;
8502 /* When all four are of the same mode. */
8503 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8508 type = v4si_ftype_v4si_v4si_v4si;
8511 type = v4sf_ftype_v4sf_v4sf_v4sf;
8514 type = v8hi_ftype_v8hi_v8hi_v8hi;
8517 type = v16qi_ftype_v16qi_v16qi_v16qi;
8523 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8528 type = v4si_ftype_v4si_v4si_v16qi;
8531 type = v4sf_ftype_v4sf_v4sf_v16qi;
8534 type = v8hi_ftype_v8hi_v8hi_v16qi;
8537 type = v16qi_ftype_v16qi_v16qi_v16qi;
8543 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8544 && mode3 == V4SImode)
8545 type = v4si_ftype_v16qi_v16qi_v4si;
8546 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8547 && mode3 == V4SImode)
8548 type = v4si_ftype_v8hi_v8hi_v4si;
8549 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8550 && mode3 == V4SImode)
8551 type = v4sf_ftype_v4sf_v4sf_v4si;
8553 /* vchar, vchar, vchar, 4 bit literal. */
8554 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8556 type = v16qi_ftype_v16qi_v16qi_int;
8558 /* vshort, vshort, vshort, 4 bit literal. */
8559 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8561 type = v8hi_ftype_v8hi_v8hi_int;
8563 /* vint, vint, vint, 4 bit literal. */
8564 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8566 type = v4si_ftype_v4si_v4si_int;
8568 /* vfloat, vfloat, vfloat, 4 bit literal. */
8569 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8571 type = v4sf_ftype_v4sf_v4sf_int;
8576 def_builtin (d->mask, d->name, type, d->code);
8579 /* Add the simple binary operators. */
8580 d = (struct builtin_description *) bdesc_2arg;
8581 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8583 enum machine_mode mode0, mode1, mode2;
8586 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8589 mode0 = insn_data[d->icode].operand[0].mode;
8590 mode1 = insn_data[d->icode].operand[1].mode;
8591 mode2 = insn_data[d->icode].operand[2].mode;
8593 /* When all three operands are of the same mode. */
8594 if (mode0 == mode1 && mode1 == mode2)
8599 type = v4sf_ftype_v4sf_v4sf;
8602 type = v4si_ftype_v4si_v4si;
8605 type = v16qi_ftype_v16qi_v16qi;
8608 type = v8hi_ftype_v8hi_v8hi;
8611 type = v2si_ftype_v2si_v2si;
8614 type = v2sf_ftype_v2sf_v2sf;
8617 type = int_ftype_int_int;
8624 /* A few other combos we really don't want to do manually. */
8626 /* vint, vfloat, vfloat. */
8627 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8628 type = v4si_ftype_v4sf_v4sf;
8630 /* vshort, vchar, vchar. */
8631 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8632 type = v8hi_ftype_v16qi_v16qi;
8634 /* vint, vshort, vshort. */
8635 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8636 type = v4si_ftype_v8hi_v8hi;
8638 /* vshort, vint, vint. */
8639 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8640 type = v8hi_ftype_v4si_v4si;
8642 /* vchar, vshort, vshort. */
8643 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8644 type = v16qi_ftype_v8hi_v8hi;
8646 /* vint, vchar, vint. */
8647 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8648 type = v4si_ftype_v16qi_v4si;
8650 /* vint, vchar, vchar. */
8651 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8652 type = v4si_ftype_v16qi_v16qi;
8654 /* vint, vshort, vint. */
8655 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8656 type = v4si_ftype_v8hi_v4si;
8658 /* vint, vint, 5 bit literal. */
8659 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
8660 type = v4si_ftype_v4si_int;
8662 /* vshort, vshort, 5 bit literal. */
8663 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8664 type = v8hi_ftype_v8hi_int;
8666 /* vchar, vchar, 5 bit literal. */
8667 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8668 type = v16qi_ftype_v16qi_int;
8670 /* vfloat, vint, 5 bit literal. */
8671 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8672 type = v4sf_ftype_v4si_int;
8674 /* vint, vfloat, 5 bit literal. */
8675 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
8676 type = v4si_ftype_v4sf_int;
8678 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8679 type = v2si_ftype_int_int;
8681 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8682 type = v2si_ftype_v2si_char;
8684 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8685 type = v2si_ftype_int_char;
8688 else if (mode0 == SImode)
8693 type = int_ftype_v4si_v4si;
8696 type = int_ftype_v4sf_v4sf;
8699 type = int_ftype_v16qi_v16qi;
8702 type = int_ftype_v8hi_v8hi;
8712 def_builtin (d->mask, d->name, type, d->code);
8715 /* Add the simple unary operators. */
8716 d = (struct builtin_description *) bdesc_1arg;
8717 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8719 enum machine_mode mode0, mode1;
8722 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8725 mode0 = insn_data[d->icode].operand[0].mode;
8726 mode1 = insn_data[d->icode].operand[1].mode;
8728 if (mode0 == V4SImode && mode1 == QImode)
8729 type = v4si_ftype_int;
8730 else if (mode0 == V8HImode && mode1 == QImode)
8731 type = v8hi_ftype_int;
8732 else if (mode0 == V16QImode && mode1 == QImode)
8733 type = v16qi_ftype_int;
8734 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8735 type = v4sf_ftype_v4sf;
8736 else if (mode0 == V8HImode && mode1 == V16QImode)
8737 type = v8hi_ftype_v16qi;
8738 else if (mode0 == V4SImode && mode1 == V8HImode)
8739 type = v4si_ftype_v8hi;
8740 else if (mode0 == V2SImode && mode1 == V2SImode)
8741 type = v2si_ftype_v2si;
8742 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8743 type = v2sf_ftype_v2sf;
8744 else if (mode0 == V2SFmode && mode1 == V2SImode)
8745 type = v2sf_ftype_v2si;
8746 else if (mode0 == V2SImode && mode1 == V2SFmode)
8747 type = v2si_ftype_v2sf;
8748 else if (mode0 == V2SImode && mode1 == QImode)
8749 type = v2si_ftype_char;
8753 def_builtin (d->mask, d->name, type, d->code);
8758 rs6000_init_libfuncs (void)
8760 if (!TARGET_HARD_FLOAT)
8763 if (DEFAULT_ABI != ABI_V4)
8765 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
8767 /* AIX library routines for float->int conversion. */
8768 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
8769 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
8770 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
8771 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
8774 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
8775 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
8776 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
8777 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
8778 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
8782 /* 32-bit SVR4 quad floating point routines. */
8784 set_optab_libfunc (add_optab, TFmode, "_q_add");
8785 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
8786 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
8787 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
8788 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
8789 if (TARGET_PPC_GPOPT || TARGET_POWER2)
8790 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
8792 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
8793 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
8794 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
8795 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
8796 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
8797 set_optab_libfunc (le_optab, TFmode, "_q_fle");
8799 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
8800 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
8801 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
8802 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
8803 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
8804 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
8805 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
8810 /* Expand a block clear operation, and return 1 if successful. Return 0
8811 if we should let the compiler generate normal code.
8813 operands[0] is the destination
8814 operands[1] is the length
8815 operands[2] is the alignment */
8818 expand_block_clear (rtx operands[])
8820 rtx orig_dest = operands[0];
8821 rtx bytes_rtx = operands[1];
8822 rtx align_rtx = operands[2];
8823 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
8824 HOST_WIDE_INT align;
8825 HOST_WIDE_INT bytes;
8830 /* If this is not a fixed size move, just call memcpy */
8834 /* If this is not a fixed size alignment, abort */
8835 if (GET_CODE (align_rtx) != CONST_INT)
8837 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8839 /* Anything to clear? */
8840 bytes = INTVAL (bytes_rtx);
8844 /* Use the builtin memset after a point, to avoid huge code bloat.
8845 When optimize_size, avoid any significant code bloat; calling
8846 memset is about 4 instructions, so allow for one instruction to
8847 load zero and three to do clearing. */
8848 if (TARGET_ALTIVEC && align >= 128)
8850 else if (TARGET_POWERPC64 && align >= 32)
8855 if (optimize_size && bytes > 3 * clear_step)
8857 if (! optimize_size && bytes > 8 * clear_step)
8860 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
8862 enum machine_mode mode = BLKmode;
8865 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
8870 else if (bytes >= 8 && TARGET_POWERPC64
8871 /* 64-bit loads and stores require word-aligned
8873 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8878 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
8879 { /* move 4 bytes */
8883 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
8884 { /* move 2 bytes */
8888 else /* move 1 byte at a time */
8894 dest = adjust_address (orig_dest, mode, offset);
8896 emit_move_insn (dest, CONST0_RTX (mode));
8903 /* Expand a block move operation, and return 1 if successful. Return 0
8904 if we should let the compiler generate normal code.
8906 operands[0] is the destination
8907 operands[1] is the source
8908 operands[2] is the length
8909 operands[3] is the alignment */
8911 #define MAX_MOVE_REG 4
8914 expand_block_move (rtx operands[])
8916 rtx orig_dest = operands[0];
8917 rtx orig_src = operands[1];
8918 rtx bytes_rtx = operands[2];
8919 rtx align_rtx = operands[3];
8920 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
8925 rtx stores[MAX_MOVE_REG];
8928 /* If this is not a fixed size move, just call memcpy */
8932 /* If this is not a fixed size alignment, abort */
8933 if (GET_CODE (align_rtx) != CONST_INT)
8935 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8937 /* Anything to move? */
8938 bytes = INTVAL (bytes_rtx);
8942 /* store_one_arg depends on expand_block_move to handle at least the size of
8943 reg_parm_stack_space. */
8944 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
8947 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
8950 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
8951 rtx (*mov) (rtx, rtx);
8953 enum machine_mode mode = BLKmode;
8956 /* Altivec first, since it will be faster than a string move
8957 when it applies, and usually not significantly larger. */
8958 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
8962 gen_func.mov = gen_movv4si;
8964 else if (TARGET_STRING
8965 && bytes > 24 /* move up to 32 bytes at a time */
8973 && ! fixed_regs[12])
8975 move_bytes = (bytes > 32) ? 32 : bytes;
8976 gen_func.movmemsi = gen_movmemsi_8reg;
8978 else if (TARGET_STRING
8979 && bytes > 16 /* move up to 24 bytes at a time */
8985 && ! fixed_regs[10])
8987 move_bytes = (bytes > 24) ? 24 : bytes;
8988 gen_func.movmemsi = gen_movmemsi_6reg;
8990 else if (TARGET_STRING
8991 && bytes > 8 /* move up to 16 bytes at a time */
8997 move_bytes = (bytes > 16) ? 16 : bytes;
8998 gen_func.movmemsi = gen_movmemsi_4reg;
9000 else if (bytes >= 8 && TARGET_POWERPC64
9001 /* 64-bit loads and stores require word-aligned
9003 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9007 gen_func.mov = gen_movdi;
9009 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9010 { /* move up to 8 bytes at a time */
9011 move_bytes = (bytes > 8) ? 8 : bytes;
9012 gen_func.movmemsi = gen_movmemsi_2reg;
9014 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9015 { /* move 4 bytes */
9018 gen_func.mov = gen_movsi;
9020 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
9021 { /* move 2 bytes */
9024 gen_func.mov = gen_movhi;
9026 else if (TARGET_STRING && bytes > 1)
9027 { /* move up to 4 bytes at a time */
9028 move_bytes = (bytes > 4) ? 4 : bytes;
9029 gen_func.movmemsi = gen_movmemsi_1reg;
9031 else /* move 1 byte at a time */
9035 gen_func.mov = gen_movqi;
9038 src = adjust_address (orig_src, mode, offset);
9039 dest = adjust_address (orig_dest, mode, offset);
9041 if (mode != BLKmode)
9043 rtx tmp_reg = gen_reg_rtx (mode);
9045 emit_insn ((*gen_func.mov) (tmp_reg, src));
9046 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9049 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9052 for (i = 0; i < num_reg; i++)
9053 emit_insn (stores[i]);
9057 if (mode == BLKmode)
9059 /* Move the address into scratch registers. The movmemsi
9060 patterns require zero offset. */
9061 if (!REG_P (XEXP (src, 0)))
9063 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9064 src = replace_equiv_address (src, src_reg);
9066 set_mem_size (src, GEN_INT (move_bytes));
9068 if (!REG_P (XEXP (dest, 0)))
9070 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9071 dest = replace_equiv_address (dest, dest_reg);
9073 set_mem_size (dest, GEN_INT (move_bytes));
9075 emit_insn ((*gen_func.movmemsi) (dest, src,
9076 GEN_INT (move_bytes & 31),
9085 /* Return 1 if OP is suitable for a save_world call in prologue. It is
9086 known to be a PARALLEL. */
9088 save_world_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9093 int count = XVECLEN (op, 0);
9099 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9100 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
9103 for (i=1; i <= 18; i++)
9105 elt = XVECEXP (op, 0, index++);
9106 if (GET_CODE (elt) != SET
9107 || GET_CODE (SET_DEST (elt)) != MEM
9108 || ! memory_operand (SET_DEST (elt), DFmode)
9109 || GET_CODE (SET_SRC (elt)) != REG
9110 || GET_MODE (SET_SRC (elt)) != DFmode)
9114 for (i=1; i <= 12; i++)
9116 elt = XVECEXP (op, 0, index++);
9117 if (GET_CODE (elt) != SET
9118 || GET_CODE (SET_DEST (elt)) != MEM
9119 || GET_CODE (SET_SRC (elt)) != REG
9120 || GET_MODE (SET_SRC (elt)) != V4SImode)
9124 for (i=1; i <= 19; i++)
9126 elt = XVECEXP (op, 0, index++);
9127 if (GET_CODE (elt) != SET
9128 || GET_CODE (SET_DEST (elt)) != MEM
9129 || ! memory_operand (SET_DEST (elt), Pmode)
9130 || GET_CODE (SET_SRC (elt)) != REG
9131 || GET_MODE (SET_SRC (elt)) != Pmode)
9135 elt = XVECEXP (op, 0, index++);
9136 if (GET_CODE (elt) != SET
9137 || GET_CODE (SET_DEST (elt)) != MEM
9138 || ! memory_operand (SET_DEST (elt), Pmode)
9139 || GET_CODE (SET_SRC (elt)) != REG
9140 || REGNO (SET_SRC (elt)) != CR2_REGNO
9141 || GET_MODE (SET_SRC (elt)) != Pmode)
9144 if (GET_CODE (XVECEXP (op, 0, index++)) != USE
9145 || GET_CODE (XVECEXP (op, 0, index++)) != USE
9146 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
9151 /* Return 1 if OP is suitable for a save_world call in prologue. It is
9152 known to be a PARALLEL. */
9154 restore_world_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9159 int count = XVECLEN (op, 0);
9165 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
9166 || GET_CODE (XVECEXP (op, 0, index++)) != USE
9167 || GET_CODE (XVECEXP (op, 0, index++)) != USE
9168 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
9171 elt = XVECEXP (op, 0, index++);
9172 if (GET_CODE (elt) != SET
9173 || GET_CODE (SET_SRC (elt)) != MEM
9174 || ! memory_operand (SET_SRC (elt), Pmode)
9175 || GET_CODE (SET_DEST (elt)) != REG
9176 || REGNO (SET_DEST (elt)) != CR2_REGNO
9177 || GET_MODE (SET_DEST (elt)) != Pmode)
9180 for (i=1; i <= 19; i++)
9182 elt = XVECEXP (op, 0, index++);
9183 if (GET_CODE (elt) != SET
9184 || GET_CODE (SET_SRC (elt)) != MEM
9185 || ! memory_operand (SET_SRC (elt), Pmode)
9186 || GET_CODE (SET_DEST (elt)) != REG
9187 || GET_MODE (SET_DEST (elt)) != Pmode)
9191 for (i=1; i <= 12; i++)
9193 elt = XVECEXP (op, 0, index++);
9194 if (GET_CODE (elt) != SET
9195 || GET_CODE (SET_SRC (elt)) != MEM
9196 || GET_CODE (SET_DEST (elt)) != REG
9197 || GET_MODE (SET_DEST (elt)) != V4SImode)
9201 for (i=1; i <= 18; i++)
9203 elt = XVECEXP (op, 0, index++);
9204 if (GET_CODE (elt) != SET
9205 || GET_CODE (SET_SRC (elt)) != MEM
9206 || ! memory_operand (SET_SRC (elt), DFmode)
9207 || GET_CODE (SET_DEST (elt)) != REG
9208 || GET_MODE (SET_DEST (elt)) != DFmode)
9212 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9213 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9214 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9215 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9216 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
9222 /* Return 1 if OP is a load multiple operation. It is known to be a
9223 PARALLEL and the first section will be tested. */
9226 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9228 int count = XVECLEN (op, 0);
9229 unsigned int dest_regno;
9233 /* Perform a quick check so we don't blow up below. */
9235 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9236 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
9237 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
9240 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
9241 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
9243 for (i = 1; i < count; i++)
9245 rtx elt = XVECEXP (op, 0, i);
9247 if (GET_CODE (elt) != SET
9248 || GET_CODE (SET_DEST (elt)) != REG
9249 || GET_MODE (SET_DEST (elt)) != SImode
9250 || REGNO (SET_DEST (elt)) != dest_regno + i
9251 || GET_CODE (SET_SRC (elt)) != MEM
9252 || GET_MODE (SET_SRC (elt)) != SImode
9253 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
9254 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
9255 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
9256 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
9263 /* Similar, but tests for store multiple. Here, the second vector element
9264 is a CLOBBER. It will be tested later. */
9267 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9269 int count = XVECLEN (op, 0) - 1;
9270 unsigned int src_regno;
9274 /* Perform a quick check so we don't blow up below. */
9276 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9277 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
9278 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
9281 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
9282 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
9284 for (i = 1; i < count; i++)
9286 rtx elt = XVECEXP (op, 0, i + 1);
9288 if (GET_CODE (elt) != SET
9289 || GET_CODE (SET_SRC (elt)) != REG
9290 || GET_MODE (SET_SRC (elt)) != SImode
9291 || REGNO (SET_SRC (elt)) != src_regno + i
9292 || GET_CODE (SET_DEST (elt)) != MEM
9293 || GET_MODE (SET_DEST (elt)) != SImode
9294 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
9295 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
9296 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
9297 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
9304 /* Return a string to perform a load_multiple operation.
9305 operands[0] is the vector.
9306 operands[1] is the source address.
9307 operands[2] is the first destination register. */
9310 rs6000_output_load_multiple (rtx operands[3])
9312 /* We have to handle the case where the pseudo used to contain the address
9313 is assigned to one of the output registers. */
9315 int words = XVECLEN (operands[0], 0);
9318 if (XVECLEN (operands[0], 0) == 1)
9319 return "{l|lwz} %2,0(%1)";
9321 for (i = 0; i < words; i++)
9322 if (refers_to_regno_p (REGNO (operands[2]) + i,
9323 REGNO (operands[2]) + i + 1, operands[1], 0))
9327 xop[0] = GEN_INT (4 * (words-1));
9328 xop[1] = operands[1];
9329 xop[2] = operands[2];
9330 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9335 xop[0] = GEN_INT (4 * (words-1));
9336 xop[1] = operands[1];
9337 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9338 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9343 for (j = 0; j < words; j++)
9346 xop[0] = GEN_INT (j * 4);
9347 xop[1] = operands[1];
9348 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9349 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9351 xop[0] = GEN_INT (i * 4);
9352 xop[1] = operands[1];
9353 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9358 return "{lsi|lswi} %2,%1,%N0";
9361 /* Return 1 for a parallel vrsave operation. */
9364 vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9366 int count = XVECLEN (op, 0);
9367 unsigned int dest_regno, src_regno;
9371 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9372 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
9373 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
9376 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
9377 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
9379 if (dest_regno != VRSAVE_REGNO
9380 && src_regno != VRSAVE_REGNO)
9383 for (i = 1; i < count; i++)
9385 rtx elt = XVECEXP (op, 0, i);
9387 if (GET_CODE (elt) != CLOBBER
9388 && GET_CODE (elt) != SET)
9395 /* Return 1 for an PARALLEL suitable for mfcr. */
9398 mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9400 int count = XVECLEN (op, 0);
9403 /* Perform a quick check so we don't blow up below. */
9405 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9406 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
9407 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
9410 for (i = 0; i < count; i++)
9412 rtx exp = XVECEXP (op, 0, i);
9417 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
9419 if (GET_CODE (src_reg) != REG
9420 || GET_MODE (src_reg) != CCmode
9421 || ! CR_REGNO_P (REGNO (src_reg)))
9424 if (GET_CODE (exp) != SET
9425 || GET_CODE (SET_DEST (exp)) != REG
9426 || GET_MODE (SET_DEST (exp)) != SImode
9427 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
9429 unspec = SET_SRC (exp);
9430 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
9432 if (GET_CODE (unspec) != UNSPEC
9433 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
9434 || XVECLEN (unspec, 0) != 2
9435 || XVECEXP (unspec, 0, 0) != src_reg
9436 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
9437 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
9443 /* Return 1 for an PARALLEL suitable for mtcrf. */
9446 mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9448 int count = XVECLEN (op, 0);
9452 /* Perform a quick check so we don't blow up below. */
9454 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9455 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
9456 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
9458 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
9460 if (GET_CODE (src_reg) != REG
9461 || GET_MODE (src_reg) != SImode
9462 || ! INT_REGNO_P (REGNO (src_reg)))
9465 for (i = 0; i < count; i++)
9467 rtx exp = XVECEXP (op, 0, i);
9471 if (GET_CODE (exp) != SET
9472 || GET_CODE (SET_DEST (exp)) != REG
9473 || GET_MODE (SET_DEST (exp)) != CCmode
9474 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
9476 unspec = SET_SRC (exp);
9477 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
9479 if (GET_CODE (unspec) != UNSPEC
9480 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
9481 || XVECLEN (unspec, 0) != 2
9482 || XVECEXP (unspec, 0, 0) != src_reg
9483 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
9484 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
9490 /* Return 1 for an PARALLEL suitable for lmw. */
9493 lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9495 int count = XVECLEN (op, 0);
9496 unsigned int dest_regno;
9498 unsigned int base_regno;
9499 HOST_WIDE_INT offset;
9502 /* Perform a quick check so we don't blow up below. */
9504 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9505 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
9506 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
9509 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
9510 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
9513 || count != 32 - (int) dest_regno)
9516 if (legitimate_indirect_address_p (src_addr, 0))
9519 base_regno = REGNO (src_addr);
9520 if (base_regno == 0)
9523 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
9525 offset = INTVAL (XEXP (src_addr, 1));
9526 base_regno = REGNO (XEXP (src_addr, 0));
9531 for (i = 0; i < count; i++)
9533 rtx elt = XVECEXP (op, 0, i);
9536 HOST_WIDE_INT newoffset;
9538 if (GET_CODE (elt) != SET
9539 || GET_CODE (SET_DEST (elt)) != REG
9540 || GET_MODE (SET_DEST (elt)) != SImode
9541 || REGNO (SET_DEST (elt)) != dest_regno + i
9542 || GET_CODE (SET_SRC (elt)) != MEM
9543 || GET_MODE (SET_SRC (elt)) != SImode)
9545 newaddr = XEXP (SET_SRC (elt), 0);
9546 if (legitimate_indirect_address_p (newaddr, 0))
9551 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
9553 addr_reg = XEXP (newaddr, 0);
9554 newoffset = INTVAL (XEXP (newaddr, 1));
9558 if (REGNO (addr_reg) != base_regno
9559 || newoffset != offset + 4 * i)
9566 /* Return 1 for an PARALLEL suitable for stmw. */
9569 stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9571 int count = XVECLEN (op, 0);
9572 unsigned int src_regno;
9574 unsigned int base_regno;
9575 HOST_WIDE_INT offset;
9578 /* Perform a quick check so we don't blow up below. */
9580 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9581 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
9582 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
9585 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
9586 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
9589 || count != 32 - (int) src_regno)
9592 if (legitimate_indirect_address_p (dest_addr, 0))
9595 base_regno = REGNO (dest_addr);
9596 if (base_regno == 0)
9599 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
9601 offset = INTVAL (XEXP (dest_addr, 1));
9602 base_regno = REGNO (XEXP (dest_addr, 0));
9607 for (i = 0; i < count; i++)
9609 rtx elt = XVECEXP (op, 0, i);
9612 HOST_WIDE_INT newoffset;
9614 if (GET_CODE (elt) != SET
9615 || GET_CODE (SET_SRC (elt)) != REG
9616 || GET_MODE (SET_SRC (elt)) != SImode
9617 || REGNO (SET_SRC (elt)) != src_regno + i
9618 || GET_CODE (SET_DEST (elt)) != MEM
9619 || GET_MODE (SET_DEST (elt)) != SImode)
9621 newaddr = XEXP (SET_DEST (elt), 0);
9622 if (legitimate_indirect_address_p (newaddr, 0))
9627 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
9629 addr_reg = XEXP (newaddr, 0);
9630 newoffset = INTVAL (XEXP (newaddr, 1));
9634 if (REGNO (addr_reg) != base_regno
9635 || newoffset != offset + 4 * i)
9642 /* A validation routine: say whether CODE, a condition code, and MODE
9643 match. The other alternatives either don't make sense or should
9644 never be generated. */
9647 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9649 if ((GET_RTX_CLASS (code) != RTX_COMPARE
9650 && GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
9651 || GET_MODE_CLASS (mode) != MODE_CC)
9654 /* These don't make sense. */
9655 if ((code == GT || code == LT || code == GE || code == LE)
9656 && mode == CCUNSmode)
9659 if ((code == GTU || code == LTU || code == GEU || code == LEU)
9660 && mode != CCUNSmode)
9663 if (mode != CCFPmode
9664 && (code == ORDERED || code == UNORDERED
9665 || code == UNEQ || code == LTGT
9666 || code == UNGT || code == UNLT
9667 || code == UNGE || code == UNLE))
9670 /* These should never be generated except for
9671 flag_finite_math_only. */
9672 if (mode == CCFPmode
9673 && ! flag_finite_math_only
9674 && (code == LE || code == GE
9675 || code == UNEQ || code == LTGT
9676 || code == UNGT || code == UNLT))
9679 /* These are invalid; the information is not there. */
9680 if (mode == CCEQmode
9681 && code != EQ && code != NE)
9685 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
9686 We only check the opcode against the mode of the CC value here. */
9689 branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9691 enum rtx_code code = GET_CODE (op);
9692 enum machine_mode cc_mode;
9694 if (!COMPARISON_P (op))
9697 cc_mode = GET_MODE (XEXP (op, 0));
9698 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
9701 validate_condition_mode (code, cc_mode);
9706 /* Return 1 if OP is a comparison operation that is valid for a branch
9707 insn and which is true if the corresponding bit in the CC register
9711 branch_positive_comparison_operator (rtx op, enum machine_mode mode)
9715 if (! branch_comparison_operator (op, mode))
9718 code = GET_CODE (op);
9719 return (code == EQ || code == LT || code == GT
9720 || code == LTU || code == GTU
9721 || code == UNORDERED);
9724 /* Return 1 if OP is a comparison operation that is valid for an scc
9725 insn: it must be a positive comparison. */
9728 scc_comparison_operator (rtx op, enum machine_mode mode)
9730 return branch_positive_comparison_operator (op, mode);
9734 trap_comparison_operator (rtx op, enum machine_mode mode)
9736 if (mode != VOIDmode && mode != GET_MODE (op))
9738 return COMPARISON_P (op);
9742 boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9744 enum rtx_code code = GET_CODE (op);
9745 return (code == AND || code == IOR || code == XOR);
9749 boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9751 enum rtx_code code = GET_CODE (op);
9752 return (code == IOR || code == XOR);
9756 min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9758 enum rtx_code code = GET_CODE (op);
9759 return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
9762 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9763 mask required to convert the result of a rotate insn into a shift
9764 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9767 includes_lshift_p (rtx shiftop, rtx andop)
9769 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9771 shift_mask <<= INTVAL (shiftop);
9773 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9776 /* Similar, but for right shift. */
9779 includes_rshift_p (rtx shiftop, rtx andop)
9781 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9783 shift_mask >>= INTVAL (shiftop);
9785 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9788 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9789 to perform a left shift. It must have exactly SHIFTOP least
9790 significant 0's, then one or more 1's, then zero or more 0's. */
9793 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9795 if (GET_CODE (andop) == CONST_INT)
9797 HOST_WIDE_INT c, lsb, shift_mask;
9800 if (c == 0 || c == ~0)
9804 shift_mask <<= INTVAL (shiftop);
9806 /* Find the least significant one bit. */
9809 /* It must coincide with the LSB of the shift mask. */
9810 if (-lsb != shift_mask)
9813 /* Invert to look for the next transition (if any). */
9816 /* Remove the low group of ones (originally low group of zeros). */
9819 /* Again find the lsb, and check we have all 1's above. */
9823 else if (GET_CODE (andop) == CONST_DOUBLE
9824 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9826 HOST_WIDE_INT low, high, lsb;
9827 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9829 low = CONST_DOUBLE_LOW (andop);
9830 if (HOST_BITS_PER_WIDE_INT < 64)
9831 high = CONST_DOUBLE_HIGH (andop);
9833 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9834 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9837 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9839 shift_mask_high = ~0;
9840 if (INTVAL (shiftop) > 32)
9841 shift_mask_high <<= INTVAL (shiftop) - 32;
9845 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9852 return high == -lsb;
9855 shift_mask_low = ~0;
9856 shift_mask_low <<= INTVAL (shiftop);
9860 if (-lsb != shift_mask_low)
9863 if (HOST_BITS_PER_WIDE_INT < 64)
9868 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9871 return high == -lsb;
9875 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9881 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9882 to perform a left shift. It must have SHIFTOP or more least
9883 significant 0's, with the remainder of the word 1's. */
9886 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9888 if (GET_CODE (andop) == CONST_INT)
9890 HOST_WIDE_INT c, lsb, shift_mask;
9893 shift_mask <<= INTVAL (shiftop);
9896 /* Find the least significant one bit. */
9899 /* It must be covered by the shift mask.
9900 This test also rejects c == 0. */
9901 if ((lsb & shift_mask) == 0)
9904 /* Check we have all 1's above the transition, and reject all 1's. */
9905 return c == -lsb && lsb != 1;
9907 else if (GET_CODE (andop) == CONST_DOUBLE
9908 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9910 HOST_WIDE_INT low, lsb, shift_mask_low;
9912 low = CONST_DOUBLE_LOW (andop);
9914 if (HOST_BITS_PER_WIDE_INT < 64)
9916 HOST_WIDE_INT high, shift_mask_high;
9918 high = CONST_DOUBLE_HIGH (andop);
9922 shift_mask_high = ~0;
9923 if (INTVAL (shiftop) > 32)
9924 shift_mask_high <<= INTVAL (shiftop) - 32;
9928 if ((lsb & shift_mask_high) == 0)
9931 return high == -lsb;
9937 shift_mask_low = ~0;
9938 shift_mask_low <<= INTVAL (shiftop);
9942 if ((lsb & shift_mask_low) == 0)
9945 return low == -lsb && lsb != 1;
9951 /* Return 1 if operands will generate a valid arguments to rlwimi
9952 instruction for insert with right shift in 64-bit mode. The mask may
9953 not start on the first bit or stop on the last bit because wrap-around
9954 effects of instruction do not correspond to semantics of RTL insn. */
9957 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9959 if (INTVAL (startop) < 64
9960 && INTVAL (startop) > 32
9961 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9962 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9963 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9964 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9965 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9971 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9972 for lfq and stfq insns iff the registers are hard registers. */
9975 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
9977 /* We might have been passed a SUBREG. */
9978 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
9981 /* We might have been passed non floating point registers. */
9982 if (!FP_REGNO_P (REGNO (reg1))
9983 || !FP_REGNO_P (REGNO (reg2)))
9986 return (REGNO (reg1) == REGNO (reg2) - 1);
9989 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9990 addr1 and addr2 must be in consecutive memory locations
9991 (addr2 == addr1 + 8). */
9994 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
10000 /* The mems cannot be volatile. */
10001 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
10004 addr1 = XEXP (mem1, 0);
10005 addr2 = XEXP (mem2, 0);
10007 /* Extract an offset (if used) from the first addr. */
10008 if (GET_CODE (addr1) == PLUS)
10010 /* If not a REG, return zero. */
10011 if (GET_CODE (XEXP (addr1, 0)) != REG)
10015 reg1 = REGNO (XEXP (addr1, 0));
10016 /* The offset must be constant! */
10017 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
10019 offset1 = INTVAL (XEXP (addr1, 1));
10022 else if (GET_CODE (addr1) != REG)
10026 reg1 = REGNO (addr1);
10027 /* This was a simple (mem (reg)) expression. Offset is 0. */
10031 /* Make sure the second address is a (mem (plus (reg) (const_int)))
10032 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
10033 register as addr1. */
10034 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
10036 if (GET_CODE (addr2) != PLUS)
10039 if (GET_CODE (XEXP (addr2, 0)) != REG
10040 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
10043 if (reg1 != REGNO (XEXP (addr2, 0)))
10046 /* The offset for the second addr must be 8 more than the first addr. */
10047 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
10050 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10055 /* Return the register class of a scratch register needed to copy IN into
10056 or out of a register in CLASS in MODE. If it can be done directly,
10057 NO_REGS is returned. */
10060 secondary_reload_class (enum reg_class class,
10061 enum machine_mode mode ATTRIBUTE_UNUSED,
10066 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
10068 && MACHOPIC_INDIRECT
10072 /* We cannot copy a symbolic operand directly into anything
10073 other than BASE_REGS for TARGET_ELF. So indicate that a
10074 register from BASE_REGS is needed as an intermediate
10077 On Darwin, pic addresses require a load from memory, which
10078 needs a base register. */
10079 if (class != BASE_REGS
10080 && (GET_CODE (in) == SYMBOL_REF
10081 || GET_CODE (in) == HIGH
10082 || GET_CODE (in) == LABEL_REF
10083 || GET_CODE (in) == CONST))
10087 if (GET_CODE (in) == REG)
10089 regno = REGNO (in);
10090 if (regno >= FIRST_PSEUDO_REGISTER)
10092 regno = true_regnum (in);
10093 if (regno >= FIRST_PSEUDO_REGISTER)
10097 else if (GET_CODE (in) == SUBREG)
10099 regno = true_regnum (in);
10100 if (regno >= FIRST_PSEUDO_REGISTER)
10106 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10108 if (class == GENERAL_REGS || class == BASE_REGS
10109 || (regno >= 0 && INT_REGNO_P (regno)))
10112 /* Constants, memory, and FP registers can go into FP registers. */
10113 if ((regno == -1 || FP_REGNO_P (regno))
10114 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
10117 /* Memory, and AltiVec registers can go into AltiVec registers. */
10118 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
10119 && class == ALTIVEC_REGS)
10122 /* We can copy among the CR registers. */
10123 if ((class == CR_REGS || class == CR0_REGS)
10124 && regno >= 0 && CR_REGNO_P (regno))
10127 /* Otherwise, we need GENERAL_REGS. */
10128 return GENERAL_REGS;
10131 /* Given a comparison operation, return the bit number in CCR to test. We
10132 know this is a valid comparison.
10134 SCC_P is 1 if this is for an scc. That means that %D will have been
10135 used instead of %C, so the bits will be in different places.
10137 Return -1 if OP isn't a valid comparison for some reason. */
10140 ccr_bit (rtx op, int scc_p)
10142 enum rtx_code code = GET_CODE (op);
10143 enum machine_mode cc_mode;
10148 if (!COMPARISON_P (op))
10151 reg = XEXP (op, 0);
10153 if (GET_CODE (reg) != REG
10154 || ! CR_REGNO_P (REGNO (reg)))
10157 cc_mode = GET_MODE (reg);
10158 cc_regnum = REGNO (reg);
10159 base_bit = 4 * (cc_regnum - CR0_REGNO);
10161 validate_condition_mode (code, cc_mode);
10163 /* When generating a sCOND operation, only positive conditions are
10165 if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
10166 && code != GTU && code != LTU)
10172 return scc_p ? base_bit + 3 : base_bit + 2;
10174 return base_bit + 2;
10175 case GT: case GTU: case UNLE:
10176 return base_bit + 1;
10177 case LT: case LTU: case UNGE:
10179 case ORDERED: case UNORDERED:
10180 return base_bit + 3;
10183 /* If scc, we will have done a cror to put the bit in the
10184 unordered position. So test that bit. For integer, this is ! LT
10185 unless this is an scc insn. */
10186 return scc_p ? base_bit + 3 : base_bit;
10189 return scc_p ? base_bit + 3 : base_bit + 1;
10196 /* Return the GOT register. */
10199 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10201 /* The second flow pass currently (June 1999) can't update
10202 regs_ever_live without disturbing other parts of the compiler, so
10203 update it here to make the prolog/epilogue code happy. */
10204 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
10205 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10207 current_function_uses_pic_offset_table = 1;
10209 return pic_offset_table_rtx;
10212 /* Function to init struct machine_function.
10213 This will be called, via a pointer variable,
10214 from push_function_context. */
10216 static struct machine_function *
10217 rs6000_init_machine_status (void)
10219 return ggc_alloc_cleared (sizeof (machine_function));
10222 /* These macros test for integers and extract the low-order bits. */
10224 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10225 && GET_MODE (X) == VOIDmode)
10227 #define INT_LOWPART(X) \
10228 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10231 extract_MB (rtx op)
10234 unsigned long val = INT_LOWPART (op);
10236 /* If the high bit is zero, the value is the first 1 bit we find
10238 if ((val & 0x80000000) == 0)
10240 if ((val & 0xffffffff) == 0)
10244 while (((val <<= 1) & 0x80000000) == 0)
10249 /* If the high bit is set and the low bit is not, or the mask is all
10250 1's, the value is zero. */
10251 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10254 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10257 while (((val >>= 1) & 1) != 0)
10264 extract_ME (rtx op)
10267 unsigned long val = INT_LOWPART (op);
10269 /* If the low bit is zero, the value is the first 1 bit we find from
10271 if ((val & 1) == 0)
10273 if ((val & 0xffffffff) == 0)
10277 while (((val >>= 1) & 1) == 0)
10283 /* If the low bit is set and the high bit is not, or the mask is all
10284 1's, the value is 31. */
10285 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10288 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10291 while (((val <<= 1) & 0x80000000) != 0)
10297 /* Locate some local-dynamic symbol still in use by this function
10298 so that we can print its name in some tls_ld pattern. */
10300 static const char *
10301 rs6000_get_some_local_dynamic_name (void)
10305 if (cfun->machine->some_ld_name)
10306 return cfun->machine->some_ld_name;
10308 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10310 && for_each_rtx (&PATTERN (insn),
10311 rs6000_get_some_local_dynamic_name_1, 0))
10312 return cfun->machine->some_ld_name;
10317 /* Helper function for rs6000_get_some_local_dynamic_name. */
10320 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10324 if (GET_CODE (x) == SYMBOL_REF)
10326 const char *str = XSTR (x, 0);
10327 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10329 cfun->machine->some_ld_name = str;
10337 /* Write out a function code label. */
10340 rs6000_output_function_entry (FILE *file, const char *fname)
10342 if (fname[0] != '.')
10344 switch (DEFAULT_ABI)
10353 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10362 RS6000_OUTPUT_BASENAME (file, fname);
10364 assemble_name (file, fname);
10367 /* Print an operand. Recognize special options, documented below. */
10370 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10371 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10373 #define SMALL_DATA_RELOC "sda21"
10374 #define SMALL_DATA_REG 0
10378 print_operand (FILE *file, rtx x, int code)
10382 unsigned HOST_WIDE_INT uval;
10387 /* Write out an instruction after the call which may be replaced
10388 with glue code by the loader. This depends on the AIX version. */
10389 asm_fprintf (file, RS6000_CALL_GLUE);
10392 /* %a is output_address. */
10395 /* If X is a constant integer whose low-order 5 bits are zero,
10396 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10397 in the AIX assembler where "sri" with a zero shift count
10398 writes a trash instruction. */
10399 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10406 /* If constant, low-order 16 bits of constant, unsigned.
10407 Otherwise, write normally. */
10409 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10411 print_operand (file, x, 0);
10415 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10416 for 64-bit mask direction. */
10417 putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
10420 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10424 /* X is a CR register. Print the number of the GT bit of the CR. */
10425 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10426 output_operand_lossage ("invalid %%E value");
10428 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10432 /* Like 'J' but get to the EQ bit. */
10433 if (GET_CODE (x) != REG)
10436 /* Bit 1 is EQ bit. */
10437 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
10439 /* If we want bit 31, write a shift count of zero, not 32. */
10440 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10444 /* X is a CR register. Print the number of the EQ bit of the CR */
10445 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10446 output_operand_lossage ("invalid %%E value");
10448 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10452 /* X is a CR register. Print the shift count needed to move it
10453 to the high-order four bits. */
10454 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10455 output_operand_lossage ("invalid %%f value");
10457 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10461 /* Similar, but print the count for the rotate in the opposite
10463 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10464 output_operand_lossage ("invalid %%F value");
10466 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10470 /* X is a constant integer. If it is negative, print "m",
10471 otherwise print "z". This is to make an aze or ame insn. */
10472 if (GET_CODE (x) != CONST_INT)
10473 output_operand_lossage ("invalid %%G value");
10474 else if (INTVAL (x) >= 0)
10481 /* If constant, output low-order five bits. Otherwise, write
10484 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10486 print_operand (file, x, 0);
10490 /* If constant, output low-order six bits. Otherwise, write
10493 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10495 print_operand (file, x, 0);
10499 /* Print `i' if this is a constant, else nothing. */
10505 /* Write the bit number in CCR for jump. */
10506 i = ccr_bit (x, 0);
10508 output_operand_lossage ("invalid %%j code");
10510 fprintf (file, "%d", i);
10514 /* Similar, but add one for shift count in rlinm for scc and pass
10515 scc flag to `ccr_bit'. */
10516 i = ccr_bit (x, 1);
10518 output_operand_lossage ("invalid %%J code");
10520 /* If we want bit 31, write a shift count of zero, not 32. */
10521 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10525 /* X must be a constant. Write the 1's complement of the
10528 output_operand_lossage ("invalid %%k value");
10530 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10534 /* X must be a symbolic constant on ELF. Write an
10535 expression suitable for an 'addi' that adds in the low 16
10536 bits of the MEM. */
10537 if (GET_CODE (x) != CONST)
10539 print_operand_address (file, x);
10540 fputs ("@l", file);
10544 if (GET_CODE (XEXP (x, 0)) != PLUS
10545 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10546 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10547 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10548 output_operand_lossage ("invalid %%K value");
10549 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10550 fputs ("@l", file);
10551 /* For GNU as, there must be a non-alphanumeric character
10552 between 'l' and the number. The '-' is added by
10553 print_operand() already. */
10554 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10556 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10560 /* %l is output_asm_label. */
10563 /* Write second word of DImode or DFmode reference. Works on register
10564 or non-indexed memory only. */
10565 if (GET_CODE (x) == REG)
10566 fputs (reg_names[REGNO (x) + 1], file);
10567 else if (GET_CODE (x) == MEM)
10569 /* Handle possible auto-increment. Since it is pre-increment and
10570 we have already done it, we can just use an offset of word. */
10571 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10572 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10573 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10576 output_address (XEXP (adjust_address_nv (x, SImode,
10580 if (small_data_operand (x, GET_MODE (x)))
10581 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10582 reg_names[SMALL_DATA_REG]);
10587 /* MB value for a mask operand. */
10588 if (! mask_operand (x, SImode))
10589 output_operand_lossage ("invalid %%m value");
10591 fprintf (file, "%d", extract_MB (x));
10595 /* ME value for a mask operand. */
10596 if (! mask_operand (x, SImode))
10597 output_operand_lossage ("invalid %%M value");
10599 fprintf (file, "%d", extract_ME (x));
10602 /* %n outputs the negative of its operand. */
10605 /* Write the number of elements in the vector times 4. */
10606 if (GET_CODE (x) != PARALLEL)
10607 output_operand_lossage ("invalid %%N value");
10609 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10613 /* Similar, but subtract 1 first. */
10614 if (GET_CODE (x) != PARALLEL)
10615 output_operand_lossage ("invalid %%O value");
10617 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10621 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10623 || INT_LOWPART (x) < 0
10624 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10625 output_operand_lossage ("invalid %%p value");
10627 fprintf (file, "%d", i);
10631 /* The operand must be an indirect memory reference. The result
10632 is the register name. */
10633 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10634 || REGNO (XEXP (x, 0)) >= 32)
10635 output_operand_lossage ("invalid %%P value");
10637 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10641 /* This outputs the logical code corresponding to a boolean
10642 expression. The expression may have one or both operands
10643 negated (if one, only the first one). For condition register
10644 logical operations, it will also treat the negated
10645 CR codes as NOTs, but not handle NOTs of them. */
10647 const char *const *t = 0;
10649 enum rtx_code code = GET_CODE (x);
10650 static const char * const tbl[3][3] = {
10651 { "and", "andc", "nor" },
10652 { "or", "orc", "nand" },
10653 { "xor", "eqv", "xor" } };
10657 else if (code == IOR)
10659 else if (code == XOR)
10662 output_operand_lossage ("invalid %%q value");
10664 if (GET_CODE (XEXP (x, 0)) != NOT)
10668 if (GET_CODE (XEXP (x, 1)) == NOT)
10686 /* X is a CR register. Print the mask for `mtcrf'. */
10687 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10688 output_operand_lossage ("invalid %%R value");
10690 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10694 /* Low 5 bits of 32 - value */
10696 output_operand_lossage ("invalid %%s value");
10698 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10702 /* PowerPC64 mask position. All 0's is excluded.
10703 CONST_INT 32-bit mask is considered sign-extended so any
10704 transition must occur within the CONST_INT, not on the boundary. */
10705 if (! mask64_operand (x, DImode))
10706 output_operand_lossage ("invalid %%S value");
10708 uval = INT_LOWPART (x);
10710 if (uval & 1) /* Clear Left */
10712 #if HOST_BITS_PER_WIDE_INT > 64
10713 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10717 else /* Clear Right */
10720 #if HOST_BITS_PER_WIDE_INT > 64
10721 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10729 fprintf (file, "%d", i);
10733 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10734 if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
10737 /* Bit 3 is OV bit. */
10738 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10740 /* If we want bit 31, write a shift count of zero, not 32. */
10741 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10745 /* Print the symbolic name of a branch target register. */
10746 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10747 && REGNO (x) != COUNT_REGISTER_REGNUM))
10748 output_operand_lossage ("invalid %%T value");
10749 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10750 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10752 fputs ("ctr", file);
10756 /* High-order 16 bits of constant for use in unsigned operand. */
10758 output_operand_lossage ("invalid %%u value");
10760 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10761 (INT_LOWPART (x) >> 16) & 0xffff);
10765 /* High-order 16 bits of constant for use in signed operand. */
10767 output_operand_lossage ("invalid %%v value");
10769 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10770 (INT_LOWPART (x) >> 16) & 0xffff);
10774 /* Print `u' if this has an auto-increment or auto-decrement. */
10775 if (GET_CODE (x) == MEM
10776 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10777 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10782 /* Print the trap code for this operand. */
10783 switch (GET_CODE (x))
10786 fputs ("eq", file); /* 4 */
10789 fputs ("ne", file); /* 24 */
10792 fputs ("lt", file); /* 16 */
10795 fputs ("le", file); /* 20 */
10798 fputs ("gt", file); /* 8 */
10801 fputs ("ge", file); /* 12 */
10804 fputs ("llt", file); /* 2 */
10807 fputs ("lle", file); /* 6 */
10810 fputs ("lgt", file); /* 1 */
10813 fputs ("lge", file); /* 5 */
10821 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10824 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10825 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10827 print_operand (file, x, 0);
10831 /* MB value for a PowerPC64 rldic operand. */
10832 val = (GET_CODE (x) == CONST_INT
10833 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10838 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10839 if ((val <<= 1) < 0)
10842 #if HOST_BITS_PER_WIDE_INT == 32
10843 if (GET_CODE (x) == CONST_INT && i >= 0)
10844 i += 32; /* zero-extend high-part was all 0's */
10845 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10847 val = CONST_DOUBLE_LOW (x);
10854 for ( ; i < 64; i++)
10855 if ((val <<= 1) < 0)
10860 fprintf (file, "%d", i + 1);
10864 if (GET_CODE (x) == MEM
10865 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10870 /* Like 'L', for third word of TImode */
10871 if (GET_CODE (x) == REG)
10872 fputs (reg_names[REGNO (x) + 2], file);
10873 else if (GET_CODE (x) == MEM)
10875 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10876 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10877 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10879 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10880 if (small_data_operand (x, GET_MODE (x)))
10881 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10882 reg_names[SMALL_DATA_REG]);
10887 /* X is a SYMBOL_REF. Write out the name preceded by a
10888 period and without any trailing data in brackets. Used for function
10889 names. If we are configured for System V (or the embedded ABI) on
10890 the PowerPC, do not emit the period, since those systems do not use
10891 TOCs and the like. */
10892 if (GET_CODE (x) != SYMBOL_REF)
10895 /* Mark the decl as referenced so that cgraph will output the
10897 if (SYMBOL_REF_DECL (x))
10898 mark_decl_referenced (SYMBOL_REF_DECL (x));
10900 /* For macho, check to see if we need a stub. */
10903 const char *name = XSTR (x, 0);
10905 if (MACHOPIC_INDIRECT
10906 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10907 name = machopic_indirection_name (x, /*stub_p=*/true);
10909 assemble_name (file, name);
10911 else if (!DOT_SYMBOLS)
10912 assemble_name (file, XSTR (x, 0));
10914 rs6000_output_function_entry (file, XSTR (x, 0));
10918 /* Like 'L', for last word of TImode. */
10919 if (GET_CODE (x) == REG)
10920 fputs (reg_names[REGNO (x) + 3], file);
10921 else if (GET_CODE (x) == MEM)
10923 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10924 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10925 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10927 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10928 if (small_data_operand (x, GET_MODE (x)))
10929 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10930 reg_names[SMALL_DATA_REG]);
10934 /* Print AltiVec or SPE memory operand. */
10939 if (GET_CODE (x) != MEM)
10946 /* Handle [reg]. */
10947 if (GET_CODE (tmp) == REG)
10949 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10952 /* Handle [reg+UIMM]. */
10953 else if (GET_CODE (tmp) == PLUS &&
10954 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10958 if (GET_CODE (XEXP (tmp, 0)) != REG)
10961 x = INTVAL (XEXP (tmp, 1));
10962 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10966 /* Fall through. Must be [reg+reg]. */
10969 && GET_CODE (tmp) == AND
10970 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10971 && INTVAL (XEXP (tmp, 1)) == -16)
10972 tmp = XEXP (tmp, 0);
10973 if (GET_CODE (tmp) == REG)
10974 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
10975 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
10977 if (REGNO (XEXP (tmp, 0)) == 0)
10978 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10979 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10981 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10982 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10990 if (GET_CODE (x) == REG)
10991 fprintf (file, "%s", reg_names[REGNO (x)]);
10992 else if (GET_CODE (x) == MEM)
10994 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10995 know the width from the mode. */
10996 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
10997 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10998 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10999 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
11000 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
11001 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11003 output_address (XEXP (x, 0));
11006 output_addr_const (file, x);
11010 assemble_name (file, rs6000_get_some_local_dynamic_name ());
11014 output_operand_lossage ("invalid %%xn code");
11018 /* Print the address of an operand. */
11021 print_operand_address (FILE *file, rtx x)
11023 if (GET_CODE (x) == REG)
11024 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
11025 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
11026 || GET_CODE (x) == LABEL_REF)
11028 output_addr_const (file, x);
11029 if (small_data_operand (x, GET_MODE (x)))
11030 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11031 reg_names[SMALL_DATA_REG]);
11032 else if (TARGET_TOC)
11035 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
11037 if (REGNO (XEXP (x, 0)) == 0)
11038 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
11039 reg_names[ REGNO (XEXP (x, 0)) ]);
11041 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
11042 reg_names[ REGNO (XEXP (x, 1)) ]);
11044 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
11045 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
11046 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
11048 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11049 && CONSTANT_P (XEXP (x, 1)))
11051 output_addr_const (file, XEXP (x, 1));
11052 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11056 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11057 && CONSTANT_P (XEXP (x, 1)))
11059 fprintf (file, "lo16(");
11060 output_addr_const (file, XEXP (x, 1));
11061 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11064 else if (legitimate_constant_pool_address_p (x))
11066 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
11068 rtx contains_minus = XEXP (x, 1);
11072 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11073 turn it into (sym) for output_addr_const. */
11074 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
11075 contains_minus = XEXP (contains_minus, 0);
11077 minus = XEXP (contains_minus, 0);
11078 symref = XEXP (minus, 0);
11079 XEXP (contains_minus, 0) = symref;
11084 name = XSTR (symref, 0);
11085 newname = alloca (strlen (name) + sizeof ("@toc"));
11086 strcpy (newname, name);
11087 strcat (newname, "@toc");
11088 XSTR (symref, 0) = newname;
11090 output_addr_const (file, XEXP (x, 1));
11092 XSTR (symref, 0) = name;
11093 XEXP (contains_minus, 0) = minus;
11096 output_addr_const (file, XEXP (x, 1));
11098 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
11104 /* Target hook for assembling integer objects. The PowerPC version has
11105 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11106 is defined. It also needs to handle DI-mode objects on 64-bit
11110 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
11112 #ifdef RELOCATABLE_NEEDS_FIXUP
11113 /* Special handling for SI values. */
11114 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
11116 extern int in_toc_section (void);
11117 static int recurse = 0;
11119 /* For -mrelocatable, we mark all addresses that need to be fixed up
11120 in the .fixup section. */
11121 if (TARGET_RELOCATABLE
11122 && !in_toc_section ()
11123 && !in_text_section ()
11124 && !in_unlikely_text_section ()
11126 && GET_CODE (x) != CONST_INT
11127 && GET_CODE (x) != CONST_DOUBLE
11133 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
11135 ASM_OUTPUT_LABEL (asm_out_file, buf);
11136 fprintf (asm_out_file, "\t.long\t(");
11137 output_addr_const (asm_out_file, x);
11138 fprintf (asm_out_file, ")@fixup\n");
11139 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
11140 ASM_OUTPUT_ALIGN (asm_out_file, 2);
11141 fprintf (asm_out_file, "\t.long\t");
11142 assemble_name (asm_out_file, buf);
11143 fprintf (asm_out_file, "\n\t.previous\n");
11147 /* Remove initial .'s to turn a -mcall-aixdesc function
11148 address into the address of the descriptor, not the function
11150 else if (GET_CODE (x) == SYMBOL_REF
11151 && XSTR (x, 0)[0] == '.'
11152 && DEFAULT_ABI == ABI_AIX)
11154 const char *name = XSTR (x, 0);
11155 while (*name == '.')
11158 fprintf (asm_out_file, "\t.long\t%s\n", name);
11162 #endif /* RELOCATABLE_NEEDS_FIXUP */
11163 return default_assemble_integer (x, size, aligned_p);
11166 #ifdef HAVE_GAS_HIDDEN
11167 /* Emit an assembler directive to set symbol visibility for DECL to
11168 VISIBILITY_TYPE. */
11171 rs6000_assemble_visibility (tree decl, int vis)
11173 /* Functions need to have their entry point symbol visibility set as
11174 well as their descriptor symbol visibility. */
11175 if (DEFAULT_ABI == ABI_AIX
11177 && TREE_CODE (decl) == FUNCTION_DECL)
11179 static const char * const visibility_types[] = {
11180 NULL, "internal", "hidden", "protected"
11183 const char *name, *type;
11185 name = ((* targetm.strip_name_encoding)
11186 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
11187 type = visibility_types[vis];
11189 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
11190 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
11193 default_assemble_visibility (decl, vis);
11198 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11200 /* Reversal of FP compares takes care -- an ordered compare
11201 becomes an unordered compare and vice versa. */
11202 if (mode == CCFPmode
11203 && (!flag_finite_math_only
11204 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11205 || code == UNEQ || code == LTGT))
11206 return reverse_condition_maybe_unordered (code);
11208 return reverse_condition (code);
11211 /* Generate a compare for CODE. Return a brand-new rtx that
11212 represents the result of the compare. */
11215 rs6000_generate_compare (enum rtx_code code)
11217 enum machine_mode comp_mode;
11218 rtx compare_result;
11220 if (rs6000_compare_fp_p)
11221 comp_mode = CCFPmode;
11222 else if (code == GTU || code == LTU
11223 || code == GEU || code == LEU)
11224 comp_mode = CCUNSmode;
11225 else if ((code == EQ || code == NE)
11226 && GET_CODE (rs6000_compare_op0) == SUBREG
11227 && GET_CODE (rs6000_compare_op1) == SUBREG
11228 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11229 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11230 /* These are unsigned values, perhaps there will be a later
11231 ordering compare that can be shared with this one.
11232 Unfortunately we cannot detect the signedness of the operands
11233 for non-subregs. */
11234 comp_mode = CCUNSmode;
11236 comp_mode = CCmode;
11238 /* First, the compare. */
11239 compare_result = gen_reg_rtx (comp_mode);
11241 /* SPE FP compare instructions on the GPRs. Yuck! */
11242 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11243 && rs6000_compare_fp_p)
11245 rtx cmp, or1, or2, or_result, compare_result2;
11246 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11248 if (op_mode == VOIDmode)
11249 op_mode = GET_MODE (rs6000_compare_op1);
11251 /* Note: The E500 comparison instructions set the GT bit (x +
11252 1), on success. This explains the mess. */
11256 case EQ: case UNEQ: case NE: case LTGT:
11257 if (op_mode == SFmode)
11258 cmp = flag_finite_math_only
11259 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11260 rs6000_compare_op1)
11261 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11262 rs6000_compare_op1);
11263 else if (op_mode == DFmode)
11264 cmp = flag_finite_math_only
11265 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11266 rs6000_compare_op1)
11267 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11268 rs6000_compare_op1);
11271 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11272 if (op_mode == SFmode)
11273 cmp = flag_finite_math_only
11274 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11275 rs6000_compare_op1)
11276 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11277 rs6000_compare_op1);
11278 else if (op_mode == DFmode)
11279 cmp = flag_finite_math_only
11280 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11281 rs6000_compare_op1)
11282 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11283 rs6000_compare_op1);
11286 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11287 if (op_mode == SFmode)
11288 cmp = flag_finite_math_only
11289 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11290 rs6000_compare_op1)
11291 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11292 rs6000_compare_op1);
11293 else if (op_mode == DFmode)
11294 cmp = flag_finite_math_only
11295 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11296 rs6000_compare_op1)
11297 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11298 rs6000_compare_op1);
11305 /* Synthesize LE and GE from LT/GT || EQ. */
11306 if (code == LE || code == GE || code == LEU || code == GEU)
11312 case LE: code = LT; break;
11313 case GE: code = GT; break;
11314 case LEU: code = LT; break;
11315 case GEU: code = GT; break;
11319 or1 = gen_reg_rtx (SImode);
11320 or2 = gen_reg_rtx (SImode);
11321 or_result = gen_reg_rtx (CCEQmode);
11322 compare_result2 = gen_reg_rtx (CCFPmode);
11325 if (op_mode == SFmode)
11326 cmp = flag_finite_math_only
11327 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11328 rs6000_compare_op1)
11329 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11330 rs6000_compare_op1);
11331 else if (op_mode == DFmode)
11332 cmp = flag_finite_math_only
11333 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11334 rs6000_compare_op1)
11335 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11336 rs6000_compare_op1);
11340 or1 = gen_rtx_GT (SImode, compare_result, const0_rtx);
11341 or2 = gen_rtx_GT (SImode, compare_result2, const0_rtx);
11343 /* OR them together. */
11344 cmp = gen_rtx_SET (VOIDmode, or_result,
11345 gen_rtx_COMPARE (CCEQmode,
11346 gen_rtx_IOR (SImode, or1, or2),
11348 compare_result = or_result;
11353 if (code == NE || code == LTGT)
11362 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11363 gen_rtx_COMPARE (comp_mode,
11364 rs6000_compare_op0,
11365 rs6000_compare_op1)));
11367 /* Some kinds of FP comparisons need an OR operation;
11368 under flag_finite_math_only we don't bother. */
11369 if (rs6000_compare_fp_p
11370 && ! flag_finite_math_only
11371 && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11372 && (code == LE || code == GE
11373 || code == UNEQ || code == LTGT
11374 || code == UNGT || code == UNLT))
11376 enum rtx_code or1, or2;
11377 rtx or1_rtx, or2_rtx, compare2_rtx;
11378 rtx or_result = gen_reg_rtx (CCEQmode);
11382 case LE: or1 = LT; or2 = EQ; break;
11383 case GE: or1 = GT; or2 = EQ; break;
11384 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11385 case LTGT: or1 = LT; or2 = GT; break;
11386 case UNGT: or1 = UNORDERED; or2 = GT; break;
11387 case UNLT: or1 = UNORDERED; or2 = LT; break;
11390 validate_condition_mode (or1, comp_mode);
11391 validate_condition_mode (or2, comp_mode);
11392 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11393 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11394 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11395 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11397 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11399 compare_result = or_result;
11403 validate_condition_mode (code, GET_MODE (compare_result));
11405 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11409 /* Emit the RTL for an sCOND pattern. */
11412 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11415 enum machine_mode op_mode;
11416 enum rtx_code cond_code;
11418 condition_rtx = rs6000_generate_compare (code);
11419 cond_code = GET_CODE (condition_rtx);
11421 if (TARGET_E500 && rs6000_compare_fp_p
11422 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11426 PUT_MODE (condition_rtx, SImode);
11427 t = XEXP (condition_rtx, 0);
11429 if (cond_code != NE && cond_code != EQ)
11432 if (cond_code == NE)
11433 emit_insn (gen_e500_flip_eq_bit (t, t));
11435 emit_insn (gen_move_from_CR_eq_bit (result, t));
11439 if (cond_code == NE
11440 || cond_code == GE || cond_code == LE
11441 || cond_code == GEU || cond_code == LEU
11442 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11444 rtx not_result = gen_reg_rtx (CCEQmode);
11445 rtx not_op, rev_cond_rtx;
11446 enum machine_mode cc_mode;
11448 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11450 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11451 SImode, XEXP (condition_rtx, 0), const0_rtx);
11452 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11453 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11454 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11457 op_mode = GET_MODE (rs6000_compare_op0);
11458 if (op_mode == VOIDmode)
11459 op_mode = GET_MODE (rs6000_compare_op1);
11461 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11463 PUT_MODE (condition_rtx, DImode);
11464 convert_move (result, condition_rtx, 0);
11468 PUT_MODE (condition_rtx, SImode);
11469 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11473 /* Emit a branch of kind CODE to location LOC. */
11476 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11478 rtx condition_rtx, loc_ref;
11480 condition_rtx = rs6000_generate_compare (code);
11481 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11482 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11483 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11484 loc_ref, pc_rtx)));
11487 /* Return the string to output a conditional branch to LABEL, which is
11488 the operand number of the label, or -1 if the branch is really a
11489 conditional return.
11491 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11492 condition code register and its mode specifies what kind of
11493 comparison we made.
11495 REVERSED is nonzero if we should reverse the sense of the comparison.
11497 INSN is the insn. */
11500 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11502 static char string[64];
11503 enum rtx_code code = GET_CODE (op);
11504 rtx cc_reg = XEXP (op, 0);
11505 enum machine_mode mode = GET_MODE (cc_reg);
11506 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11507 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11508 int really_reversed = reversed ^ need_longbranch;
11514 validate_condition_mode (code, mode);
11516 /* Work out which way this really branches. We could use
11517 reverse_condition_maybe_unordered here always but this
11518 makes the resulting assembler clearer. */
11519 if (really_reversed)
11521 /* Reversal of FP compares takes care -- an ordered compare
11522 becomes an unordered compare and vice versa. */
11523 if (mode == CCFPmode)
11524 code = reverse_condition_maybe_unordered (code);
11526 code = reverse_condition (code);
11529 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11531 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11534 /* Opposite of GT. */
11536 else if (code == NE)
11544 /* Not all of these are actually distinct opcodes, but
11545 we distinguish them for clarity of the resulting assembler. */
11546 case NE: case LTGT:
11547 ccode = "ne"; break;
11548 case EQ: case UNEQ:
11549 ccode = "eq"; break;
11551 ccode = "ge"; break;
11552 case GT: case GTU: case UNGT:
11553 ccode = "gt"; break;
11555 ccode = "le"; break;
11556 case LT: case LTU: case UNLT:
11557 ccode = "lt"; break;
11558 case UNORDERED: ccode = "un"; break;
11559 case ORDERED: ccode = "nu"; break;
11560 case UNGE: ccode = "nl"; break;
11561 case UNLE: ccode = "ng"; break;
11566 /* Maybe we have a guess as to how likely the branch is.
11567 The old mnemonics don't have a way to specify this information. */
11569 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11570 if (note != NULL_RTX)
11572 /* PROB is the difference from 50%. */
11573 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11575 /* Only hint for highly probable/improbable branches on newer
11576 cpus as static prediction overrides processor dynamic
11577 prediction. For older cpus we may as well always hint, but
11578 assume not taken for branches that are very close to 50% as a
11579 mispredicted taken branch is more expensive than a
11580 mispredicted not-taken branch. */
11581 if (rs6000_always_hint
11582 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
11584 if (abs (prob) > REG_BR_PROB_BASE / 20
11585 && ((prob > 0) ^ need_longbranch))
11593 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11595 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11597 /* We need to escape any '%' characters in the reg_names string.
11598 Assume they'd only be the first character.... */
11599 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11601 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11605 /* If the branch distance was too far, we may have to use an
11606 unconditional branch to go the distance. */
11607 if (need_longbranch)
11608 s += sprintf (s, ",$+8\n\tb %s", label);
11610 s += sprintf (s, ",%s", label);
11616 /* Return the string to flip the EQ bit on a CR. */
11618 output_e500_flip_eq_bit (rtx dst, rtx src)
11620 static char string[64];
11623 if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst))
11624 || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src)))
11628 a = 4 * (REGNO (dst) - CR0_REGNO) + 2;
11629 b = 4 * (REGNO (src) - CR0_REGNO) + 2;
11631 sprintf (string, "crnot %d,%d", a, b);
11635 /* Return insn index for the vector compare instruction for given CODE,
11636 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11640 get_vec_cmp_insn (enum rtx_code code,
11641 enum machine_mode dest_mode,
11642 enum machine_mode op_mode)
11644 if (!TARGET_ALTIVEC)
11645 return INSN_NOT_AVAILABLE;
11650 if (dest_mode == V16QImode && op_mode == V16QImode)
11651 return UNSPEC_VCMPEQUB;
11652 if (dest_mode == V8HImode && op_mode == V8HImode)
11653 return UNSPEC_VCMPEQUH;
11654 if (dest_mode == V4SImode && op_mode == V4SImode)
11655 return UNSPEC_VCMPEQUW;
11656 if (dest_mode == V4SImode && op_mode == V4SFmode)
11657 return UNSPEC_VCMPEQFP;
11660 if (dest_mode == V4SImode && op_mode == V4SFmode)
11661 return UNSPEC_VCMPGEFP;
11663 if (dest_mode == V16QImode && op_mode == V16QImode)
11664 return UNSPEC_VCMPGTSB;
11665 if (dest_mode == V8HImode && op_mode == V8HImode)
11666 return UNSPEC_VCMPGTSH;
11667 if (dest_mode == V4SImode && op_mode == V4SImode)
11668 return UNSPEC_VCMPGTSW;
11669 if (dest_mode == V4SImode && op_mode == V4SFmode)
11670 return UNSPEC_VCMPGTFP;
11673 if (dest_mode == V16QImode && op_mode == V16QImode)
11674 return UNSPEC_VCMPGTUB;
11675 if (dest_mode == V8HImode && op_mode == V8HImode)
11676 return UNSPEC_VCMPGTUH;
11677 if (dest_mode == V4SImode && op_mode == V4SImode)
11678 return UNSPEC_VCMPGTUW;
11683 return INSN_NOT_AVAILABLE;
11686 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11687 DMODE is expected destination mode. This is a recursive function. */
11690 rs6000_emit_vector_compare (enum rtx_code rcode,
11692 enum machine_mode dmode)
11696 enum machine_mode dest_mode;
11697 enum machine_mode op_mode = GET_MODE (op1);
11699 #ifdef ENABLE_CHECKING
11700 if (!TARGET_ALTIVEC)
11703 if (GET_MODE (op0) != GET_MODE (op1))
11707 /* Floating point vector compare instructions uses destination V4SImode.
11708 Move destination to appropriate mode later. */
11709 if (dmode == V4SFmode)
11710 dest_mode = V4SImode;
11714 mask = gen_reg_rtx (dest_mode);
11715 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11717 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11719 bool swap_operands = false;
11720 bool try_again = false;
11725 swap_operands = true;
11730 swap_operands = true;
11734 /* Treat A != B as ~(A==B). */
11736 enum insn_code nor_code;
11737 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11740 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11741 if (nor_code == CODE_FOR_nothing)
11743 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11745 if (dmode != dest_mode)
11747 rtx temp = gen_reg_rtx (dest_mode);
11748 convert_move (temp, mask, 0);
11758 /* Try GT/GTU/LT/LTU OR EQ */
11761 enum insn_code ior_code;
11762 enum rtx_code new_code;
11766 else if (rcode == GEU)
11768 else if (rcode == LE)
11770 else if (rcode == LEU)
11775 c_rtx = rs6000_emit_vector_compare (new_code,
11776 op0, op1, dest_mode);
11777 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11780 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11781 if (ior_code == CODE_FOR_nothing)
11783 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11784 if (dmode != dest_mode)
11786 rtx temp = gen_reg_rtx (dest_mode);
11787 convert_move (temp, mask, 0);
11799 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11800 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11801 /* You only get two chances. */
11814 emit_insn (gen_rtx_fmt_ee (SET,
11817 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
11818 gen_rtvec (2, op0, op1),
11820 if (dmode != dest_mode)
11822 rtx temp = gen_reg_rtx (dest_mode);
11823 convert_move (temp, mask, 0);
11829 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11830 valid insn doesn exist for given mode. */
11833 get_vsel_insn (enum machine_mode mode)
11838 return UNSPEC_VSEL4SI;
11841 return UNSPEC_VSEL4SF;
11844 return UNSPEC_VSEL8HI;
11847 return UNSPEC_VSEL16QI;
11850 return INSN_NOT_AVAILABLE;
11853 return INSN_NOT_AVAILABLE;
11856 /* Emit vector select insn where DEST is destination using
11857 operands OP1, OP2 and MASK. */
11860 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11863 enum machine_mode dest_mode = GET_MODE (dest);
11864 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11866 temp = gen_reg_rtx (dest_mode);
11868 t = gen_rtx_fmt_ee (SET, VOIDmode, temp,
11869 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
11870 gen_rtvec (3, op1, op2, mask),
11873 emit_move_insn (dest, temp);
11877 /* Emit vector conditional expression.
11878 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11879 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11882 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11883 rtx cond, rtx cc_op0, rtx cc_op1)
11885 enum machine_mode dest_mode = GET_MODE (dest);
11886 enum rtx_code rcode = GET_CODE (cond);
11889 if (!TARGET_ALTIVEC)
11892 /* Get the vector mask for the given relational operations. */
11893 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11895 rs6000_emit_vector_select (dest, op1, op2, mask);
11900 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11901 operands of the last comparison is nonzero/true, FALSE_COND if it
11902 is zero/false. Return 0 if the hardware has no such operation. */
11905 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11907 enum rtx_code code = GET_CODE (op);
11908 rtx op0 = rs6000_compare_op0;
11909 rtx op1 = rs6000_compare_op1;
11910 REAL_VALUE_TYPE c1;
11911 enum machine_mode compare_mode = GET_MODE (op0);
11912 enum machine_mode result_mode = GET_MODE (dest);
11914 bool is_against_zero;
11916 /* These modes should always match. */
11917 if (GET_MODE (op1) != compare_mode
11918 /* In the isel case however, we can use a compare immediate, so
11919 op1 may be a small constant. */
11920 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11922 if (GET_MODE (true_cond) != result_mode)
11924 if (GET_MODE (false_cond) != result_mode)
11927 /* First, work out if the hardware can do this at all, or
11928 if it's too slow.... */
11929 if (! rs6000_compare_fp_p)
11932 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11935 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11936 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
11939 is_against_zero = op1 == CONST0_RTX (compare_mode);
11941 /* A floating-point subtract might overflow, underflow, or produce
11942 an inexact result, thus changing the floating-point flags, so it
11943 can't be generated if we care about that. It's safe if one side
11944 of the construct is zero, since then no subtract will be
11946 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT
11947 && flag_trapping_math && ! is_against_zero)
11950 /* Eliminate half of the comparisons by switching operands, this
11951 makes the remaining code simpler. */
11952 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
11953 || code == LTGT || code == LT || code == UNLE)
11955 code = reverse_condition_maybe_unordered (code);
11957 true_cond = false_cond;
11961 /* UNEQ and LTGT take four instructions for a comparison with zero,
11962 it'll probably be faster to use a branch here too. */
11963 if (code == UNEQ && HONOR_NANS (compare_mode))
11966 if (GET_CODE (op1) == CONST_DOUBLE)
11967 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
11969 /* We're going to try to implement comparisons by performing
11970 a subtract, then comparing against zero. Unfortunately,
11971 Inf - Inf is NaN which is not zero, and so if we don't
11972 know that the operand is finite and the comparison
11973 would treat EQ different to UNORDERED, we can't do it. */
11974 if (HONOR_INFINITIES (compare_mode)
11975 && code != GT && code != UNGE
11976 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
11977 /* Constructs of the form (a OP b ? a : b) are safe. */
11978 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
11979 || (! rtx_equal_p (op0, true_cond)
11980 && ! rtx_equal_p (op1, true_cond))))
11983 /* At this point we know we can use fsel. */
11985 /* Reduce the comparison to a comparison against zero. */
11986 if (! is_against_zero)
11988 temp = gen_reg_rtx (compare_mode);
11989 emit_insn (gen_rtx_SET (VOIDmode, temp,
11990 gen_rtx_MINUS (compare_mode, op0, op1)));
11992 op1 = CONST0_RTX (compare_mode);
11995 /* If we don't care about NaNs we can reduce some of the comparisons
11996 down to faster ones. */
11997 if (! HONOR_NANS (compare_mode))
12003 true_cond = false_cond;
12016 /* Now, reduce everything down to a GE. */
12023 temp = gen_reg_rtx (compare_mode);
12024 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12029 temp = gen_reg_rtx (compare_mode);
12030 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
12035 temp = gen_reg_rtx (compare_mode);
12036 emit_insn (gen_rtx_SET (VOIDmode, temp,
12037 gen_rtx_NEG (compare_mode,
12038 gen_rtx_ABS (compare_mode, op0))));
12043 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12044 temp = gen_reg_rtx (result_mode);
12045 emit_insn (gen_rtx_SET (VOIDmode, temp,
12046 gen_rtx_IF_THEN_ELSE (result_mode,
12047 gen_rtx_GE (VOIDmode,
12049 true_cond, false_cond)));
12050 false_cond = true_cond;
12053 temp = gen_reg_rtx (compare_mode);
12054 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12059 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
12060 temp = gen_reg_rtx (result_mode);
12061 emit_insn (gen_rtx_SET (VOIDmode, temp,
12062 gen_rtx_IF_THEN_ELSE (result_mode,
12063 gen_rtx_GE (VOIDmode,
12065 true_cond, false_cond)));
12066 true_cond = false_cond;
12069 temp = gen_reg_rtx (compare_mode);
12070 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12078 emit_insn (gen_rtx_SET (VOIDmode, dest,
12079 gen_rtx_IF_THEN_ELSE (result_mode,
12080 gen_rtx_GE (VOIDmode,
12082 true_cond, false_cond)));
12086 /* Same as above, but for ints (isel). */
12089 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12091 rtx condition_rtx, cr;
12093 /* All isel implementations thus far are 32-bits. */
12094 if (GET_MODE (rs6000_compare_op0) != SImode)
12097 /* We still have to do the compare, because isel doesn't do a
12098 compare, it just looks at the CRx bits set by a previous compare
12100 condition_rtx = rs6000_generate_compare (GET_CODE (op));
12101 cr = XEXP (condition_rtx, 0);
12103 if (GET_MODE (cr) == CCmode)
12104 emit_insn (gen_isel_signed (dest, condition_rtx,
12105 true_cond, false_cond, cr));
12107 emit_insn (gen_isel_unsigned (dest, condition_rtx,
12108 true_cond, false_cond, cr));
12114 output_isel (rtx *operands)
12116 enum rtx_code code;
12118 code = GET_CODE (operands[1]);
12119 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
12121 PUT_CODE (operands[1], reverse_condition (code));
12122 return "isel %0,%3,%2,%j1";
12125 return "isel %0,%2,%3,%j1";
12129 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
12131 enum machine_mode mode = GET_MODE (op0);
12135 if (code == SMAX || code == SMIN)
12140 if (code == SMAX || code == UMAX)
12141 target = emit_conditional_move (dest, c, op0, op1, mode,
12142 op0, op1, mode, 0);
12144 target = emit_conditional_move (dest, c, op0, op1, mode,
12145 op1, op0, mode, 0);
12146 if (target == NULL_RTX)
12148 if (target != dest)
12149 emit_move_insn (dest, target);
12152 /* Emit instructions to move SRC to DST. Called by splitters for
12153 multi-register moves. It will emit at most one instruction for
12154 each register that is accessed; that is, it won't emit li/lis pairs
12155 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12159 rs6000_split_multireg_move (rtx dst, rtx src)
12161 /* The register number of the first register being moved. */
12163 /* The mode that is to be moved. */
12164 enum machine_mode mode;
12165 /* The mode that the move is being done in, and its size. */
12166 enum machine_mode reg_mode;
12168 /* The number of registers that will be moved. */
12171 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12172 mode = GET_MODE (dst);
12173 nregs = HARD_REGNO_NREGS (reg, mode);
12174 if (FP_REGNO_P (reg))
12176 else if (ALTIVEC_REGNO_P (reg))
12177 reg_mode = V16QImode;
12179 reg_mode = word_mode;
12180 reg_mode_size = GET_MODE_SIZE (reg_mode);
12182 if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
12185 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12187 /* Move register range backwards, if we might have destructive
12190 for (i = nregs - 1; i >= 0; i--)
12191 emit_insn (gen_rtx_SET (VOIDmode,
12192 simplify_gen_subreg (reg_mode, dst, mode,
12193 i * reg_mode_size),
12194 simplify_gen_subreg (reg_mode, src, mode,
12195 i * reg_mode_size)));
12201 bool used_update = false;
12203 if (MEM_P (src) && INT_REGNO_P (reg))
12207 if (GET_CODE (XEXP (src, 0)) == PRE_INC
12208 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
12211 breg = XEXP (XEXP (src, 0), 0);
12212 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
12213 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
12214 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
12215 emit_insn (TARGET_32BIT
12216 ? gen_addsi3 (breg, breg, delta_rtx)
12217 : gen_adddi3 (breg, breg, delta_rtx));
12218 src = gen_rtx_MEM (mode, breg);
12220 else if (! offsettable_memref_p (src))
12222 rtx newsrc, basereg;
12223 basereg = gen_rtx_REG (Pmode, reg);
12224 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
12225 newsrc = gen_rtx_MEM (GET_MODE (src), basereg);
12226 MEM_COPY_ATTRIBUTES (newsrc, src);
12230 breg = XEXP (src, 0);
12231 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
12232 breg = XEXP (breg, 0);
12234 /* If the base register we are using to address memory is
12235 also a destination reg, then change that register last. */
12237 && REGNO (breg) >= REGNO (dst)
12238 && REGNO (breg) < REGNO (dst) + nregs)
12239 j = REGNO (breg) - REGNO (dst);
12242 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
12246 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
12247 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
12250 breg = XEXP (XEXP (dst, 0), 0);
12251 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
12252 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
12253 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
12255 /* We have to update the breg before doing the store.
12256 Use store with update, if available. */
12260 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
12261 emit_insn (TARGET_32BIT
12262 ? (TARGET_POWERPC64
12263 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
12264 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
12265 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
12266 used_update = true;
12269 emit_insn (TARGET_32BIT
12270 ? gen_addsi3 (breg, breg, delta_rtx)
12271 : gen_adddi3 (breg, breg, delta_rtx));
12272 dst = gen_rtx_MEM (mode, breg);
12274 else if (! offsettable_memref_p (dst))
12278 for (i = 0; i < nregs; i++)
12280 /* Calculate index to next subword. */
12285 /* If compiler already emitted move of first word by
12286 store with update, no need to do anything. */
12287 if (j == 0 && used_update)
12290 emit_insn (gen_rtx_SET (VOIDmode,
12291 simplify_gen_subreg (reg_mode, dst, mode,
12292 j * reg_mode_size),
12293 simplify_gen_subreg (reg_mode, src, mode,
12294 j * reg_mode_size)));
12300 /* This page contains routines that are used to determine what the
12301 function prologue and epilogue code will do and write them out. */
12303 /* Return the first fixed-point register that is required to be
12304 saved. 32 if none. */
12307 first_reg_to_save (void)
12311 /* Find lowest numbered live register. */
12312 for (first_reg = 13; first_reg <= 31; first_reg++)
12313 if (regs_ever_live[first_reg]
12314 && (! call_used_regs[first_reg]
12315 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12316 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12317 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12318 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12323 && current_function_uses_pic_offset_table
12324 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12325 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12331 /* Similar, for FP regs. */
12334 first_fp_reg_to_save (void)
12338 /* Find lowest numbered live register. */
12339 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12340 if (regs_ever_live[first_reg])
12346 /* Similar, for AltiVec regs. */
12349 first_altivec_reg_to_save (void)
12353 /* Stack frame remains as is unless we are in AltiVec ABI. */
12354 if (! TARGET_ALTIVEC_ABI)
12355 return LAST_ALTIVEC_REGNO + 1;
12357 /* Find lowest numbered live register. */
12358 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12359 if (regs_ever_live[i])
12365 /* Return a 32-bit mask of the AltiVec registers we need to set in
12366 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12367 the 32-bit word is 0. */
12369 static unsigned int
12370 compute_vrsave_mask (void)
12372 unsigned int i, mask = 0;
12374 /* First, find out if we use _any_ altivec registers. */
12375 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12376 if (regs_ever_live[i])
12377 mask |= ALTIVEC_REG_BIT (i);
12382 /* Next, remove the argument registers from the set. These must
12383 be in the VRSAVE mask set by the caller, so we don't need to add
12384 them in again. More importantly, the mask we compute here is
12385 used to generate CLOBBERs in the set_vrsave insn, and we do not
12386 wish the argument registers to die. */
12387 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12388 mask &= ~ALTIVEC_REG_BIT (i);
12390 /* Similarly, remove the return value from the set. */
12393 diddle_return_value (is_altivec_return_reg, &yes);
12395 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12401 /* For a very restricted set of circumstances, we can cut down the
12402 size of prologues/epilogues by calling our own save/restore-the-world
12406 compute_save_world_info (rs6000_stack_t *info_ptr)
12408 info_ptr->world_save_p = 1;
12409 info_ptr->world_save_p
12410 = (WORLD_SAVE_P (info_ptr)
12411 && DEFAULT_ABI == ABI_DARWIN
12412 && ! (current_function_calls_setjmp && flag_exceptions)
12413 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12414 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12415 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12416 && info_ptr->cr_save_p);
12418 /* This will not work in conjunction with sibcalls. Make sure there
12419 are none. (This check is expensive, but seldom executed.) */
12420 if (WORLD_SAVE_P (info_ptr))
12423 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12424 if ( GET_CODE (insn) == CALL_INSN
12425 && SIBLING_CALL_P (insn))
12427 info_ptr->world_save_p = 0;
12432 if (WORLD_SAVE_P (info_ptr))
12434 /* Even if we're not touching VRsave, make sure there's room on the
12435 stack for it, if it looks like we're calling SAVE_WORLD, which
12436 will attempt to save it. */
12437 info_ptr->vrsave_size = 4;
12439 /* "Save" the VRsave register too if we're saving the world. */
12440 if (info_ptr->vrsave_mask == 0)
12441 info_ptr->vrsave_mask = compute_vrsave_mask ();
12443 /* Because the Darwin register save/restore routines only handle
12444 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12445 check and abort if there's something worng. */
12446 if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO
12447 || info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO)
12455 is_altivec_return_reg (rtx reg, void *xyes)
12457 bool *yes = (bool *) xyes;
12458 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
12463 /* Calculate the stack information for the current function. This is
12464 complicated by having two separate calling sequences, the AIX calling
12465 sequence and the V.4 calling sequence.
12467 AIX (and Darwin/Mac OS X) stack frames look like:
12469 SP----> +---------------------------------------+
12470 | back chain to caller | 0 0
12471 +---------------------------------------+
12472 | saved CR | 4 8 (8-11)
12473 +---------------------------------------+
12475 +---------------------------------------+
12476 | reserved for compilers | 12 24
12477 +---------------------------------------+
12478 | reserved for binders | 16 32
12479 +---------------------------------------+
12480 | saved TOC pointer | 20 40
12481 +---------------------------------------+
12482 | Parameter save area (P) | 24 48
12483 +---------------------------------------+
12484 | Alloca space (A) | 24+P etc.
12485 +---------------------------------------+
12486 | Local variable space (L) | 24+P+A
12487 +---------------------------------------+
12488 | Float/int conversion temporary (X) | 24+P+A+L
12489 +---------------------------------------+
12490 | Save area for AltiVec registers (W) | 24+P+A+L+X
12491 +---------------------------------------+
12492 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12493 +---------------------------------------+
12494 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12495 +---------------------------------------+
12496 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12497 +---------------------------------------+
12498 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12499 +---------------------------------------+
12500 old SP->| back chain to caller's caller |
12501 +---------------------------------------+
12503 The required alignment for AIX configurations is two words (i.e., 8
12507 V.4 stack frames look like:
12509 SP----> +---------------------------------------+
12510 | back chain to caller | 0
12511 +---------------------------------------+
12512 | caller's saved LR | 4
12513 +---------------------------------------+
12514 | Parameter save area (P) | 8
12515 +---------------------------------------+
12516 | Alloca space (A) | 8+P
12517 +---------------------------------------+
12518 | Varargs save area (V) | 8+P+A
12519 +---------------------------------------+
12520 | Local variable space (L) | 8+P+A+V
12521 +---------------------------------------+
12522 | Float/int conversion temporary (X) | 8+P+A+V+L
12523 +---------------------------------------+
12524 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12525 +---------------------------------------+
12526 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12527 +---------------------------------------+
12528 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12529 +---------------------------------------+
12530 | SPE: area for 64-bit GP registers |
12531 +---------------------------------------+
12532 | SPE alignment padding |
12533 +---------------------------------------+
12534 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12535 +---------------------------------------+
12536 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12537 +---------------------------------------+
12538 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12539 +---------------------------------------+
12540 old SP->| back chain to caller's caller |
12541 +---------------------------------------+
12543 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12544 given. (But note below and in sysv4.h that we require only 8 and
12545 may round up the size of our stack frame anyways. The historical
12546 reason is early versions of powerpc-linux which didn't properly
12547 align the stack at program startup. A happy side-effect is that
12548 -mno-eabi libraries can be used with -meabi programs.)
12550 The EABI configuration defaults to the V.4 layout. However,
12551 the stack alignment requirements may differ. If -mno-eabi is not
12552 given, the required stack alignment is 8 bytes; if -mno-eabi is
12553 given, the required alignment is 16 bytes. (But see V.4 comment
12556 #ifndef ABI_STACK_BOUNDARY
12557 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12560 static rs6000_stack_t *
12561 rs6000_stack_info (void)
12563 static rs6000_stack_t info, zero_info;
12564 rs6000_stack_t *info_ptr = &info;
12565 int reg_size = TARGET_32BIT ? 4 : 8;
12568 HOST_WIDE_INT non_fixed_size;
12570 /* Zero all fields portably. */
12575 /* Cache value so we don't rescan instruction chain over and over. */
12576 if (cfun->machine->insn_chain_scanned_p == 0)
12578 cfun->machine->insn_chain_scanned_p = 1;
12579 info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p ();
12583 /* Select which calling sequence. */
12584 info_ptr->abi = DEFAULT_ABI;
12586 /* Calculate which registers need to be saved & save area size. */
12587 info_ptr->first_gp_reg_save = first_reg_to_save ();
12588 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12589 even if it currently looks like we won't. */
12590 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
12591 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12592 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
12593 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12594 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
12596 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
12598 /* For the SPE, we have an additional upper 32-bits on each GPR.
12599 Ideally we should save the entire 64-bits only when the upper
12600 half is used in SIMD instructions. Since we only record
12601 registers live (not the size they are used in), this proves
12602 difficult because we'd have to traverse the instruction chain at
12603 the right time, taking reload into account. This is a real pain,
12604 so we opt to save the GPRs in 64-bits always if but one register
12605 gets used in 64-bits. Otherwise, all the registers in the frame
12606 get saved in 32-bits.
12608 So... since when we save all GPRs (except the SP) in 64-bits, the
12609 traditional GP save area will be empty. */
12610 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12611 info_ptr->gp_size = 0;
12613 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12614 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12616 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12617 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12618 - info_ptr->first_altivec_reg_save);
12620 /* Does this function call anything? */
12621 info_ptr->calls_p = (! current_function_is_leaf
12622 || cfun->machine->ra_needs_full_frame);
12624 /* Determine if we need to save the link register. */
12625 if (rs6000_ra_ever_killed ()
12626 || (DEFAULT_ABI == ABI_AIX
12627 && current_function_profile
12628 && !TARGET_PROFILE_KERNEL)
12629 #ifdef TARGET_RELOCATABLE
12630 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12632 || (info_ptr->first_fp_reg_save != 64
12633 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
12634 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
12635 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
12636 || (DEFAULT_ABI == ABI_DARWIN
12638 && current_function_uses_pic_offset_table)
12639 || info_ptr->calls_p)
12641 info_ptr->lr_save_p = 1;
12642 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
12645 /* Determine if we need to save the condition code registers. */
12646 if (regs_ever_live[CR2_REGNO]
12647 || regs_ever_live[CR3_REGNO]
12648 || regs_ever_live[CR4_REGNO])
12650 info_ptr->cr_save_p = 1;
12651 if (DEFAULT_ABI == ABI_V4)
12652 info_ptr->cr_size = reg_size;
12655 /* If the current function calls __builtin_eh_return, then we need
12656 to allocate stack space for registers that will hold data for
12657 the exception handler. */
12658 if (current_function_calls_eh_return)
12661 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12664 /* SPE saves EH registers in 64-bits. */
12665 ehrd_size = i * (TARGET_SPE_ABI
12666 && info_ptr->spe_64bit_regs_used != 0
12667 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
12672 /* Determine various sizes. */
12673 info_ptr->reg_size = reg_size;
12674 info_ptr->fixed_size = RS6000_SAVE_AREA;
12675 info_ptr->varargs_size = RS6000_VARARGS_AREA;
12676 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
12677 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
12678 TARGET_ALTIVEC ? 16 : 8);
12680 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12681 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12683 info_ptr->spe_gp_size = 0;
12685 if (TARGET_ALTIVEC_ABI)
12686 info_ptr->vrsave_mask = compute_vrsave_mask ();
12688 info_ptr->vrsave_mask = 0;
12690 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
12691 info_ptr->vrsave_size = 4;
12693 info_ptr->vrsave_size = 0;
12695 compute_save_world_info (info_ptr);
12697 /* Calculate the offsets. */
12698 switch (DEFAULT_ABI)
12706 info_ptr->fp_save_offset = - info_ptr->fp_size;
12707 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12709 if (TARGET_ALTIVEC_ABI)
12711 info_ptr->vrsave_save_offset
12712 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
12714 /* Align stack so vector save area is on a quadword boundary. */
12715 if (info_ptr->altivec_size != 0)
12716 info_ptr->altivec_padding_size
12717 = 16 - (-info_ptr->vrsave_save_offset % 16);
12719 info_ptr->altivec_padding_size = 0;
12721 info_ptr->altivec_save_offset
12722 = info_ptr->vrsave_save_offset
12723 - info_ptr->altivec_padding_size
12724 - info_ptr->altivec_size;
12726 /* Adjust for AltiVec case. */
12727 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
12730 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
12731 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
12732 info_ptr->lr_save_offset = 2*reg_size;
12736 info_ptr->fp_save_offset = - info_ptr->fp_size;
12737 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12738 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
12740 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12742 /* Align stack so SPE GPR save area is aligned on a
12743 double-word boundary. */
12744 if (info_ptr->spe_gp_size != 0)
12745 info_ptr->spe_padding_size
12746 = 8 - (-info_ptr->cr_save_offset % 8);
12748 info_ptr->spe_padding_size = 0;
12750 info_ptr->spe_gp_save_offset
12751 = info_ptr->cr_save_offset
12752 - info_ptr->spe_padding_size
12753 - info_ptr->spe_gp_size;
12755 /* Adjust for SPE case. */
12756 info_ptr->toc_save_offset
12757 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
12759 else if (TARGET_ALTIVEC_ABI)
12761 info_ptr->vrsave_save_offset
12762 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
12764 /* Align stack so vector save area is on a quadword boundary. */
12765 if (info_ptr->altivec_size != 0)
12766 info_ptr->altivec_padding_size
12767 = 16 - (-info_ptr->vrsave_save_offset % 16);
12769 info_ptr->altivec_padding_size = 0;
12771 info_ptr->altivec_save_offset
12772 = info_ptr->vrsave_save_offset
12773 - info_ptr->altivec_padding_size
12774 - info_ptr->altivec_size;
12776 /* Adjust for AltiVec case. */
12777 info_ptr->toc_save_offset
12778 = info_ptr->altivec_save_offset - info_ptr->toc_size;
12781 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
12782 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
12783 info_ptr->lr_save_offset = reg_size;
12787 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
12788 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
12789 + info_ptr->gp_size
12790 + info_ptr->altivec_size
12791 + info_ptr->altivec_padding_size
12792 + info_ptr->spe_gp_size
12793 + info_ptr->spe_padding_size
12795 + info_ptr->cr_size
12796 + info_ptr->lr_size
12797 + info_ptr->vrsave_size
12798 + info_ptr->toc_size,
12801 non_fixed_size = (info_ptr->vars_size
12802 + info_ptr->parm_size
12803 + info_ptr->save_size
12804 + info_ptr->varargs_size);
12806 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
12807 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
12809 /* Determine if we need to allocate any stack frame:
12811 For AIX we need to push the stack if a frame pointer is needed
12812 (because the stack might be dynamically adjusted), if we are
12813 debugging, if we make calls, or if the sum of fp_save, gp_save,
12814 and local variables are more than the space needed to save all
12815 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
12816 + 18*8 = 288 (GPR13 reserved).
12818 For V.4 we don't have the stack cushion that AIX uses, but assume
12819 that the debugger can handle stackless frames. */
12821 if (info_ptr->calls_p)
12822 info_ptr->push_p = 1;
12824 else if (DEFAULT_ABI == ABI_V4)
12825 info_ptr->push_p = non_fixed_size != 0;
12827 else if (frame_pointer_needed)
12828 info_ptr->push_p = 1;
12830 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
12831 info_ptr->push_p = 1;
12834 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
12836 /* Zero offsets if we're not saving those registers. */
12837 if (info_ptr->fp_size == 0)
12838 info_ptr->fp_save_offset = 0;
12840 if (info_ptr->gp_size == 0)
12841 info_ptr->gp_save_offset = 0;
12843 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
12844 info_ptr->altivec_save_offset = 0;
12846 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
12847 info_ptr->vrsave_save_offset = 0;
12849 if (! TARGET_SPE_ABI
12850 || info_ptr->spe_64bit_regs_used == 0
12851 || info_ptr->spe_gp_size == 0)
12852 info_ptr->spe_gp_save_offset = 0;
12854 if (! info_ptr->lr_save_p)
12855 info_ptr->lr_save_offset = 0;
12857 if (! info_ptr->cr_save_p)
12858 info_ptr->cr_save_offset = 0;
12860 if (! info_ptr->toc_save_p)
12861 info_ptr->toc_save_offset = 0;
12866 /* Return true if the current function uses any GPRs in 64-bit SIMD
12870 spe_func_has_64bit_regs_p (void)
12874 /* Functions that save and restore all the call-saved registers will
12875 need to save/restore the registers in 64-bits. */
12876 if (current_function_calls_eh_return
12877 || current_function_calls_setjmp
12878 || current_function_has_nonlocal_goto)
12881 insns = get_insns ();
12883 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
12889 i = PATTERN (insn);
12890 if (GET_CODE (i) == SET)
12892 enum machine_mode mode = GET_MODE (SET_SRC (i));
12894 if (SPE_VECTOR_MODE (mode))
12896 if (TARGET_E500_DOUBLE && mode == DFmode)
12906 debug_stack_info (rs6000_stack_t *info)
12908 const char *abi_string;
12911 info = rs6000_stack_info ();
12913 fprintf (stderr, "\nStack information for function %s:\n",
12914 ((current_function_decl && DECL_NAME (current_function_decl))
12915 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
12920 default: abi_string = "Unknown"; break;
12921 case ABI_NONE: abi_string = "NONE"; break;
12922 case ABI_AIX: abi_string = "AIX"; break;
12923 case ABI_DARWIN: abi_string = "Darwin"; break;
12924 case ABI_V4: abi_string = "V.4"; break;
12927 fprintf (stderr, "\tABI = %5s\n", abi_string);
12929 if (TARGET_ALTIVEC_ABI)
12930 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
12932 if (TARGET_SPE_ABI)
12933 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
12935 if (info->first_gp_reg_save != 32)
12936 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
12938 if (info->first_fp_reg_save != 64)
12939 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
12941 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
12942 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
12943 info->first_altivec_reg_save);
12945 if (info->lr_save_p)
12946 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
12948 if (info->cr_save_p)
12949 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
12951 if (info->toc_save_p)
12952 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
12954 if (info->vrsave_mask)
12955 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
12958 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
12961 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
12963 if (info->gp_save_offset)
12964 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
12966 if (info->fp_save_offset)
12967 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
12969 if (info->altivec_save_offset)
12970 fprintf (stderr, "\taltivec_save_offset = %5d\n",
12971 info->altivec_save_offset);
12973 if (info->spe_gp_save_offset)
12974 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
12975 info->spe_gp_save_offset);
12977 if (info->vrsave_save_offset)
12978 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
12979 info->vrsave_save_offset);
12981 if (info->lr_save_offset)
12982 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
12984 if (info->cr_save_offset)
12985 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
12987 if (info->toc_save_offset)
12988 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
12990 if (info->varargs_save_offset)
12991 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
12993 if (info->total_size)
12994 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
12997 if (info->varargs_size)
12998 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
13000 if (info->vars_size)
13001 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13004 if (info->parm_size)
13005 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13007 if (info->fixed_size)
13008 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13011 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13013 if (info->spe_gp_size)
13014 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13017 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13019 if (info->altivec_size)
13020 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13022 if (info->vrsave_size)
13023 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13025 if (info->altivec_padding_size)
13026 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13027 info->altivec_padding_size);
13029 if (info->spe_padding_size)
13030 fprintf (stderr, "\tspe_padding_size = %5d\n",
13031 info->spe_padding_size);
13034 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
13037 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13039 if (info->toc_size)
13040 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
13042 if (info->save_size)
13043 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13045 if (info->reg_size != 4)
13046 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13048 fprintf (stderr, "\n");
13052 rs6000_return_addr (int count, rtx frame)
13054 /* Currently we don't optimize very well between prolog and body
13055 code and for PIC code the code can be actually quite bad, so
13056 don't try to be too clever here. */
13057 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13059 cfun->machine->ra_needs_full_frame = 1;
13066 plus_constant (copy_to_reg
13067 (gen_rtx_MEM (Pmode,
13068 memory_address (Pmode, frame))),
13069 RETURN_ADDRESS_OFFSET)));
13072 cfun->machine->ra_need_lr = 1;
13073 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13076 /* Say whether a function is a candidate for sibcall handling or not.
13077 We do not allow indirect calls to be optimized into sibling calls.
13078 Also, we can't do it if there are any vector parameters; there's
13079 nowhere to put the VRsave code so it works; note that functions with
13080 vector parameters are required to have a prototype, so the argument
13081 type info must be available here. (The tail recursion case can work
13082 with vector parameters, but there's no way to distinguish here.) */
13084 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13089 if (TARGET_ALTIVEC_VRSAVE)
13091 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13092 type; type = TREE_CHAIN (type))
13094 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13098 if (DEFAULT_ABI == ABI_DARWIN
13099 || (*targetm.binds_local_p) (decl))
13101 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13103 if (!lookup_attribute ("longcall", attr_list)
13104 || lookup_attribute ("shortcall", attr_list))
13112 rs6000_ra_ever_killed (void)
13118 if (current_function_is_thunk)
13121 /* regs_ever_live has LR marked as used if any sibcalls are present,
13122 but this should not force saving and restoring in the
13123 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13124 clobbers LR, so that is inappropriate. */
13126 /* Also, the prologue can generate a store into LR that
13127 doesn't really count, like this:
13130 bcl to set PIC register
13134 When we're called from the epilogue, we need to avoid counting
13135 this as a store. */
13137 push_topmost_sequence ();
13138 top = get_insns ();
13139 pop_topmost_sequence ();
13140 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13142 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13146 if (FIND_REG_INC_NOTE (insn, reg))
13148 else if (GET_CODE (insn) == CALL_INSN
13149 && !SIBLING_CALL_P (insn))
13151 else if (set_of (reg, insn) != NULL_RTX
13152 && !prologue_epilogue_contains (insn))
13159 /* Add a REG_MAYBE_DEAD note to the insn. */
13161 rs6000_maybe_dead (rtx insn)
13163 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13168 /* Emit instructions needed to load the TOC register.
13169 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13170 a constant pool; or for SVR4 -fpic. */
13173 rs6000_emit_load_toc_table (int fromprolog)
13176 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13178 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
13180 rtx temp = (fromprolog
13181 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13182 : gen_reg_rtx (Pmode));
13183 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
13185 rs6000_maybe_dead (insn);
13186 insn = emit_move_insn (dest, temp);
13188 rs6000_maybe_dead (insn);
13190 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
13193 rtx tempLR = (fromprolog
13194 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13195 : gen_reg_rtx (Pmode));
13196 rtx temp0 = (fromprolog
13197 ? gen_rtx_REG (Pmode, 0)
13198 : gen_reg_rtx (Pmode));
13201 /* possibly create the toc section */
13202 if (! toc_initialized)
13205 function_section (current_function_decl);
13212 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13213 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13215 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
13216 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13218 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
13220 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
13221 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
13228 static int reload_toc_labelno = 0;
13230 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13232 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
13233 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13235 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
13236 emit_move_insn (dest, tempLR);
13237 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
13239 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
13241 rs6000_maybe_dead (insn);
13243 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
13245 /* This is for AIX code running in non-PIC ELF32. */
13248 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
13249 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13251 insn = emit_insn (gen_elf_high (dest, realsym));
13253 rs6000_maybe_dead (insn);
13254 insn = emit_insn (gen_elf_low (dest, dest, realsym));
13256 rs6000_maybe_dead (insn);
13258 else if (DEFAULT_ABI == ABI_AIX)
13261 insn = emit_insn (gen_load_toc_aix_si (dest));
13263 insn = emit_insn (gen_load_toc_aix_di (dest));
13265 rs6000_maybe_dead (insn);
13271 /* Emit instructions to restore the link register after determining where
13272 its value has been stored. */
13275 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
13277 rs6000_stack_t *info = rs6000_stack_info ();
13280 operands[0] = source;
13281 operands[1] = scratch;
13283 if (info->lr_save_p)
13285 rtx frame_rtx = stack_pointer_rtx;
13286 HOST_WIDE_INT sp_offset = 0;
13289 if (frame_pointer_needed
13290 || current_function_calls_alloca
13291 || info->total_size > 32767)
13293 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
13294 frame_rtx = operands[1];
13296 else if (info->push_p)
13297 sp_offset = info->total_size;
13299 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13300 tmp = gen_rtx_MEM (Pmode, tmp);
13301 emit_move_insn (tmp, operands[0]);
13304 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13307 static GTY(()) int set = -1;
13310 get_TOC_alias_set (void)
13313 set = new_alias_set ();
13317 /* This returns nonzero if the current function uses the TOC. This is
13318 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13319 is generated by the ABI_V4 load_toc_* patterns. */
13326 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13329 rtx pat = PATTERN (insn);
13332 if (GET_CODE (pat) == PARALLEL)
13333 for (i = 0; i < XVECLEN (pat, 0); i++)
13335 rtx sub = XVECEXP (pat, 0, i);
13336 if (GET_CODE (sub) == USE)
13338 sub = XEXP (sub, 0);
13339 if (GET_CODE (sub) == UNSPEC
13340 && XINT (sub, 1) == UNSPEC_TOC)
13350 create_TOC_reference (rtx symbol)
13352 return gen_rtx_PLUS (Pmode,
13353 gen_rtx_REG (Pmode, TOC_REGISTER),
13354 gen_rtx_CONST (Pmode,
13355 gen_rtx_MINUS (Pmode, symbol,
13356 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13359 /* If _Unwind_* has been called from within the same module,
13360 toc register is not guaranteed to be saved to 40(1) on function
13361 entry. Save it there in that case. */
13364 rs6000_aix_emit_builtin_unwind_init (void)
13367 rtx stack_top = gen_reg_rtx (Pmode);
13368 rtx opcode_addr = gen_reg_rtx (Pmode);
13369 rtx opcode = gen_reg_rtx (SImode);
13370 rtx tocompare = gen_reg_rtx (SImode);
13371 rtx no_toc_save_needed = gen_label_rtx ();
13373 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
13374 emit_move_insn (stack_top, mem);
13376 mem = gen_rtx_MEM (Pmode,
13377 gen_rtx_PLUS (Pmode, stack_top,
13378 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13379 emit_move_insn (opcode_addr, mem);
13380 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13381 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13382 : 0xE8410028, SImode));
13384 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13385 SImode, NULL_RTX, NULL_RTX,
13386 no_toc_save_needed);
13388 mem = gen_rtx_MEM (Pmode,
13389 gen_rtx_PLUS (Pmode, stack_top,
13390 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13391 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13392 emit_label (no_toc_save_needed);
13395 /* This ties together stack memory (MEM with an alias set of
13396 rs6000_sr_alias_set) and the change to the stack pointer. */
13399 rs6000_emit_stack_tie (void)
13401 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
13403 set_mem_alias_set (mem, rs6000_sr_alias_set);
13404 emit_insn (gen_stack_tie (mem));
13407 /* Emit the correct code for allocating stack space, as insns.
13408 If COPY_R12, make sure a copy of the old frame is left in r12.
13409 The generated code may use hard register 0 as a temporary. */
13412 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
13415 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13416 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
13417 rtx todec = gen_int_mode (-size, Pmode);
13419 if (INTVAL (todec) != -size)
13421 warning("stack frame too large");
13422 emit_insn (gen_trap ());
13426 if (current_function_limit_stack)
13428 if (REG_P (stack_limit_rtx)
13429 && REGNO (stack_limit_rtx) > 1
13430 && REGNO (stack_limit_rtx) <= 31)
13432 emit_insn (TARGET_32BIT
13433 ? gen_addsi3 (tmp_reg,
13436 : gen_adddi3 (tmp_reg,
13440 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13443 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
13445 && DEFAULT_ABI == ABI_V4)
13447 rtx toload = gen_rtx_CONST (VOIDmode,
13448 gen_rtx_PLUS (Pmode,
13452 emit_insn (gen_elf_high (tmp_reg, toload));
13453 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
13454 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13458 warning ("stack limit expression is not supported");
13461 if (copy_r12 || ! TARGET_UPDATE)
13462 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
13468 /* Need a note here so that try_split doesn't get confused. */
13469 if (get_last_insn() == NULL_RTX)
13470 emit_note (NOTE_INSN_DELETED);
13471 insn = emit_move_insn (tmp_reg, todec);
13472 try_split (PATTERN (insn), insn, 0);
13476 insn = emit_insn (TARGET_32BIT
13477 ? gen_movsi_update (stack_reg, stack_reg,
13479 : gen_movdi_di_update (stack_reg, stack_reg,
13480 todec, stack_reg));
13484 insn = emit_insn (TARGET_32BIT
13485 ? gen_addsi3 (stack_reg, stack_reg, todec)
13486 : gen_adddi3 (stack_reg, stack_reg, todec));
13487 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
13488 gen_rtx_REG (Pmode, 12));
13491 RTX_FRAME_RELATED_P (insn) = 1;
13493 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13494 gen_rtx_SET (VOIDmode, stack_reg,
13495 gen_rtx_PLUS (Pmode, stack_reg,
13500 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13501 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13502 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13503 deduce these equivalences by itself so it wasn't necessary to hold
13504 its hand so much. */
13507 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13508 rtx reg2, rtx rreg)
13512 /* copy_rtx will not make unique copies of registers, so we need to
13513 ensure we don't have unwanted sharing here. */
13515 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13518 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13520 real = copy_rtx (PATTERN (insn));
13522 if (reg2 != NULL_RTX)
13523 real = replace_rtx (real, reg2, rreg);
13525 real = replace_rtx (real, reg,
13526 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13527 STACK_POINTER_REGNUM),
13530 /* We expect that 'real' is either a SET or a PARALLEL containing
13531 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13532 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13534 if (GET_CODE (real) == SET)
13538 temp = simplify_rtx (SET_SRC (set));
13540 SET_SRC (set) = temp;
13541 temp = simplify_rtx (SET_DEST (set));
13543 SET_DEST (set) = temp;
13544 if (GET_CODE (SET_DEST (set)) == MEM)
13546 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13548 XEXP (SET_DEST (set), 0) = temp;
13551 else if (GET_CODE (real) == PARALLEL)
13554 for (i = 0; i < XVECLEN (real, 0); i++)
13555 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13557 rtx set = XVECEXP (real, 0, i);
13559 temp = simplify_rtx (SET_SRC (set));
13561 SET_SRC (set) = temp;
13562 temp = simplify_rtx (SET_DEST (set));
13564 SET_DEST (set) = temp;
13565 if (GET_CODE (SET_DEST (set)) == MEM)
13567 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13569 XEXP (SET_DEST (set), 0) = temp;
13571 RTX_FRAME_RELATED_P (set) = 1;
13578 real = spe_synthesize_frame_save (real);
13580 RTX_FRAME_RELATED_P (insn) = 1;
13581 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13586 /* Given an SPE frame note, return a PARALLEL of SETs with the
13587 original note, plus a synthetic register save. */
13590 spe_synthesize_frame_save (rtx real)
13592 rtx synth, offset, reg, real2;
13594 if (GET_CODE (real) != SET
13595 || GET_MODE (SET_SRC (real)) != V2SImode)
13598 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13599 frame related note. The parallel contains a set of the register
13600 being saved, and another set to a synthetic register (n+1200).
13601 This is so we can differentiate between 64-bit and 32-bit saves.
13602 Words cannot describe this nastiness. */
13604 if (GET_CODE (SET_DEST (real)) != MEM
13605 || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
13606 || GET_CODE (SET_SRC (real)) != REG)
13610 (set (mem (plus (reg x) (const y)))
13613 (set (mem (plus (reg x) (const y+4)))
13617 real2 = copy_rtx (real);
13618 PUT_MODE (SET_DEST (real2), SImode);
13619 reg = SET_SRC (real2);
13620 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
13621 synth = copy_rtx (real2);
13623 if (BYTES_BIG_ENDIAN)
13625 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
13626 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
13629 reg = SET_SRC (synth);
13631 synth = replace_rtx (synth, reg,
13632 gen_rtx_REG (SImode, REGNO (reg) + 1200));
13634 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
13635 synth = replace_rtx (synth, offset,
13636 GEN_INT (INTVAL (offset)
13637 + (BYTES_BIG_ENDIAN ? 0 : 4)));
13639 RTX_FRAME_RELATED_P (synth) = 1;
13640 RTX_FRAME_RELATED_P (real2) = 1;
13641 if (BYTES_BIG_ENDIAN)
13642 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
13644 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
13649 /* Returns an insn that has a vrsave set operation with the
13650 appropriate CLOBBERs. */
13653 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
13656 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
13657 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13660 = gen_rtx_SET (VOIDmode,
13662 gen_rtx_UNSPEC_VOLATILE (SImode,
13663 gen_rtvec (2, reg, vrsave),
13668 /* We need to clobber the registers in the mask so the scheduler
13669 does not move sets to VRSAVE before sets of AltiVec registers.
13671 However, if the function receives nonlocal gotos, reload will set
13672 all call saved registers live. We will end up with:
13674 (set (reg 999) (mem))
13675 (parallel [ (set (reg vrsave) (unspec blah))
13676 (clobber (reg 999))])
13678 The clobber will cause the store into reg 999 to be dead, and
13679 flow will attempt to delete an epilogue insn. In this case, we
13680 need an unspec use/set of the register. */
13682 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13683 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13685 if (!epiloguep || call_used_regs [i])
13686 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
13687 gen_rtx_REG (V4SImode, i));
13690 rtx reg = gen_rtx_REG (V4SImode, i);
13693 = gen_rtx_SET (VOIDmode,
13695 gen_rtx_UNSPEC (V4SImode,
13696 gen_rtvec (1, reg), 27));
13700 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
13702 for (i = 0; i < nclobs; ++i)
13703 XVECEXP (insn, 0, i) = clobs[i];
13708 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
13709 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
13712 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
13713 unsigned int regno, int offset, HOST_WIDE_INT total_size)
13715 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
13716 rtx replacea, replaceb;
13718 int_rtx = GEN_INT (offset);
13720 /* Some cases that need register indexed addressing. */
13721 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13722 || (TARGET_E500_DOUBLE && mode == DFmode)
13724 && SPE_VECTOR_MODE (mode)
13725 && !SPE_CONST_OFFSET_OK (offset)))
13727 /* Whomever calls us must make sure r11 is available in the
13728 flow path of instructions in the prologue. */
13729 offset_rtx = gen_rtx_REG (Pmode, 11);
13730 emit_move_insn (offset_rtx, int_rtx);
13732 replacea = offset_rtx;
13733 replaceb = int_rtx;
13737 offset_rtx = int_rtx;
13738 replacea = NULL_RTX;
13739 replaceb = NULL_RTX;
13742 reg = gen_rtx_REG (mode, regno);
13743 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
13744 mem = gen_rtx_MEM (mode, addr);
13745 set_mem_alias_set (mem, rs6000_sr_alias_set);
13747 insn = emit_move_insn (mem, reg);
13749 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
13752 /* Emit an offset memory reference suitable for a frame store, while
13753 converting to a valid addressing mode. */
13756 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
13758 rtx int_rtx, offset_rtx;
13760 int_rtx = GEN_INT (offset);
13762 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
13763 || (TARGET_E500_DOUBLE && mode == DFmode))
13765 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13766 emit_move_insn (offset_rtx, int_rtx);
13769 offset_rtx = int_rtx;
13771 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
13774 #ifndef TARGET_FIX_AND_CONTINUE
13775 #define TARGET_FIX_AND_CONTINUE 0
13778 /* Emit function prologue as insns. */
13781 rs6000_emit_prologue (void)
13783 rs6000_stack_t *info = rs6000_stack_info ();
13784 enum machine_mode reg_mode = Pmode;
13785 int reg_size = TARGET_32BIT ? 4 : 8;
13786 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13787 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
13788 rtx frame_reg_rtx = sp_reg_rtx;
13789 rtx cr_save_rtx = NULL_RTX;
13791 int saving_FPRs_inline;
13792 int using_store_multiple;
13793 HOST_WIDE_INT sp_offset = 0;
13795 if (TARGET_FIX_AND_CONTINUE)
13797 /* gdb on darwin arranges to forward a function from the old
13798 address by modifying the first 4 instructions of the function
13799 to branch to the overriding function. This is necessary to
13800 permit function pointers that point to the old function to
13801 actually forward to the new function. */
13802 emit_insn (gen_nop ());
13803 emit_insn (gen_nop ());
13804 emit_insn (gen_nop ());
13805 emit_insn (gen_nop ());
13808 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13810 reg_mode = V2SImode;
13814 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
13815 && (!TARGET_SPE_ABI
13816 || info->spe_64bit_regs_used == 0)
13817 && info->first_gp_reg_save < 31);
13818 saving_FPRs_inline = (info->first_fp_reg_save == 64
13819 || FP_SAVE_INLINE (info->first_fp_reg_save)
13820 || current_function_calls_eh_return
13821 || cfun->machine->ra_need_lr);
13823 /* For V.4, update stack before we do any saving and set back pointer. */
13825 && (DEFAULT_ABI == ABI_V4
13826 || current_function_calls_eh_return))
13828 if (info->total_size < 32767)
13829 sp_offset = info->total_size;
13831 frame_reg_rtx = frame_ptr_rtx;
13832 rs6000_emit_allocate_stack (info->total_size,
13833 (frame_reg_rtx != sp_reg_rtx
13834 && (info->cr_save_p
13836 || info->first_fp_reg_save < 64
13837 || info->first_gp_reg_save < 32
13839 if (frame_reg_rtx != sp_reg_rtx)
13840 rs6000_emit_stack_tie ();
13843 /* Handle world saves specially here. */
13844 if (WORLD_SAVE_P (info))
13850 /* save_world expects lr in r0. */
13851 if (info->lr_save_p)
13853 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
13854 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
13855 RTX_FRAME_RELATED_P (insn) = 1;
13858 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
13859 assumptions about the offsets of various bits of the stack
13860 frame. Abort if things aren't what they should be. */
13861 if (info->gp_save_offset != -220
13862 || info->fp_save_offset != -144
13863 || info->lr_save_offset != 8
13864 || info->cr_save_offset != 4
13866 || !info->lr_save_p
13867 || (current_function_calls_eh_return && info->ehrd_offset != -432)
13868 || (info->vrsave_save_offset != -224
13869 || info->altivec_save_offset != (-224 -16 -192)))
13872 treg = gen_rtx_REG (SImode, 11);
13873 emit_move_insn (treg, GEN_INT (-info->total_size));
13875 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
13876 in R11. It also clobbers R12, so beware! */
13878 /* Preserve CR2 for save_world prologues */
13880 sz += 32 - info->first_gp_reg_save;
13881 sz += 64 - info->first_fp_reg_save;
13882 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
13883 p = rtvec_alloc (sz);
13885 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
13886 gen_rtx_REG (Pmode,
13887 LINK_REGISTER_REGNUM));
13888 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
13889 gen_rtx_SYMBOL_REF (Pmode,
13891 /* We do floats first so that the instruction pattern matches
13893 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13895 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13896 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13897 GEN_INT (info->fp_save_offset
13898 + sp_offset + 8 * i));
13899 rtx mem = gen_rtx_MEM (DFmode, addr);
13900 set_mem_alias_set (mem, rs6000_sr_alias_set);
13902 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13904 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
13906 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13907 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13908 GEN_INT (info->altivec_save_offset
13909 + sp_offset + 16 * i));
13910 rtx mem = gen_rtx_MEM (V4SImode, addr);
13911 set_mem_alias_set (mem, rs6000_sr_alias_set);
13913 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13915 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13917 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13918 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13919 GEN_INT (info->gp_save_offset
13920 + sp_offset + reg_size * i));
13921 rtx mem = gen_rtx_MEM (reg_mode, addr);
13922 set_mem_alias_set (mem, rs6000_sr_alias_set);
13924 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13928 /* CR register traditionally saved as CR2. */
13929 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13930 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13931 GEN_INT (info->cr_save_offset
13933 rtx mem = gen_rtx_MEM (reg_mode, addr);
13934 set_mem_alias_set (mem, rs6000_sr_alias_set);
13936 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13938 /* Prevent any attempt to delete the setting of r0 and treg! */
13939 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
13940 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
13941 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
13943 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13944 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13945 NULL_RTX, NULL_RTX);
13947 if (current_function_calls_eh_return)
13952 unsigned int regno = EH_RETURN_DATA_REGNO (i);
13953 if (regno == INVALID_REGNUM)
13955 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13956 info->ehrd_offset + sp_offset
13957 + reg_size * (int) i,
13963 /* Save AltiVec registers if needed. */
13964 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
13968 /* There should be a non inline version of this, for when we
13969 are saving lots of vector registers. */
13970 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
13971 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13973 rtx areg, savereg, mem;
13976 offset = info->altivec_save_offset + sp_offset
13977 + 16 * (i - info->first_altivec_reg_save);
13979 savereg = gen_rtx_REG (V4SImode, i);
13981 areg = gen_rtx_REG (Pmode, 0);
13982 emit_move_insn (areg, GEN_INT (offset));
13984 /* AltiVec addressing mode is [reg+reg]. */
13985 mem = gen_rtx_MEM (V4SImode,
13986 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
13988 set_mem_alias_set (mem, rs6000_sr_alias_set);
13990 insn = emit_move_insn (mem, savereg);
13992 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13993 areg, GEN_INT (offset));
13997 /* VRSAVE is a bit vector representing which AltiVec registers
13998 are used. The OS uses this to determine which vector
13999 registers to save on a context switch. We need to save
14000 VRSAVE on the stack frame, add whatever AltiVec registers we
14001 used in this function, and do the corresponding magic in the
14004 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14005 && !WORLD_SAVE_P (info) && info->vrsave_mask != 0)
14007 rtx reg, mem, vrsave;
14010 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14011 as frame_reg_rtx and r11 as the static chain pointer for
14012 nested functions. */
14013 reg = gen_rtx_REG (SImode, 0);
14014 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14016 emit_insn (gen_get_vrsave_internal (reg));
14018 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14021 offset = info->vrsave_save_offset + sp_offset;
14023 = gen_rtx_MEM (SImode,
14024 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
14025 set_mem_alias_set (mem, rs6000_sr_alias_set);
14026 insn = emit_move_insn (mem, reg);
14028 /* Include the registers in the mask. */
14029 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14031 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14034 /* If we use the link register, get it into r0. */
14035 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14037 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14038 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14039 RTX_FRAME_RELATED_P (insn) = 1;
14042 /* If we need to save CR, put it into r12. */
14043 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14047 cr_save_rtx = gen_rtx_REG (SImode, 12);
14048 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14049 RTX_FRAME_RELATED_P (insn) = 1;
14050 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14051 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14052 But that's OK. All we have to do is specify that _one_ condition
14053 code register is saved in this stack slot. The thrower's epilogue
14054 will then restore all the call-saved registers.
14055 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14056 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14057 gen_rtx_REG (SImode, CR2_REGNO));
14058 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14063 /* Do any required saving of fpr's. If only one or two to save, do
14064 it ourselves. Otherwise, call function. */
14065 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14068 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14069 if ((regs_ever_live[info->first_fp_reg_save+i]
14070 && ! call_used_regs[info->first_fp_reg_save+i]))
14071 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14072 info->first_fp_reg_save + i,
14073 info->fp_save_offset + sp_offset + 8 * i,
14076 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14080 const char *alloc_rname;
14082 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14084 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14085 gen_rtx_REG (Pmode,
14086 LINK_REGISTER_REGNUM));
14087 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14088 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14089 alloc_rname = ggc_strdup (rname);
14090 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14091 gen_rtx_SYMBOL_REF (Pmode,
14093 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14095 rtx addr, reg, mem;
14096 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14097 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14098 GEN_INT (info->fp_save_offset
14099 + sp_offset + 8*i));
14100 mem = gen_rtx_MEM (DFmode, addr);
14101 set_mem_alias_set (mem, rs6000_sr_alias_set);
14103 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14105 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14106 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14107 NULL_RTX, NULL_RTX);
14110 /* Save GPRs. This is done as a PARALLEL if we are using
14111 the store-multiple instructions. */
14112 if (!WORLD_SAVE_P (info) && using_store_multiple)
14116 p = rtvec_alloc (32 - info->first_gp_reg_save);
14117 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14119 rtx addr, reg, mem;
14120 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14121 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14122 GEN_INT (info->gp_save_offset
14125 mem = gen_rtx_MEM (reg_mode, addr);
14126 set_mem_alias_set (mem, rs6000_sr_alias_set);
14128 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14130 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14131 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14132 NULL_RTX, NULL_RTX);
14134 else if (!WORLD_SAVE_P (info))
14137 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14138 if ((regs_ever_live[info->first_gp_reg_save+i]
14139 && (! call_used_regs[info->first_gp_reg_save+i]
14140 || (i+info->first_gp_reg_save
14141 == RS6000_PIC_OFFSET_TABLE_REGNUM
14142 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14143 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14144 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14145 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14147 rtx addr, reg, mem;
14148 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14150 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14152 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14155 if (!SPE_CONST_OFFSET_OK (offset))
14157 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14158 emit_move_insn (b, GEN_INT (offset));
14161 b = GEN_INT (offset);
14163 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14164 mem = gen_rtx_MEM (V2SImode, addr);
14165 set_mem_alias_set (mem, rs6000_sr_alias_set);
14166 insn = emit_move_insn (mem, reg);
14168 if (GET_CODE (b) == CONST_INT)
14169 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14170 NULL_RTX, NULL_RTX);
14172 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14173 b, GEN_INT (offset));
14177 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14178 GEN_INT (info->gp_save_offset
14181 mem = gen_rtx_MEM (reg_mode, addr);
14182 set_mem_alias_set (mem, rs6000_sr_alias_set);
14184 insn = emit_move_insn (mem, reg);
14185 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14186 NULL_RTX, NULL_RTX);
14191 /* ??? There's no need to emit actual instructions here, but it's the
14192 easiest way to get the frame unwind information emitted. */
14193 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
14195 unsigned int i, regno;
14197 /* In AIX ABI we need to pretend we save r2 here. */
14200 rtx addr, reg, mem;
14202 reg = gen_rtx_REG (reg_mode, 2);
14203 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14204 GEN_INT (sp_offset + 5 * reg_size));
14205 mem = gen_rtx_MEM (reg_mode, addr);
14206 set_mem_alias_set (mem, rs6000_sr_alias_set);
14208 insn = emit_move_insn (mem, reg);
14209 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14210 NULL_RTX, NULL_RTX);
14211 PATTERN (insn) = gen_blockage ();
14216 regno = EH_RETURN_DATA_REGNO (i);
14217 if (regno == INVALID_REGNUM)
14220 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14221 info->ehrd_offset + sp_offset
14222 + reg_size * (int) i,
14227 /* Save lr if we used it. */
14228 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14230 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14231 GEN_INT (info->lr_save_offset + sp_offset));
14232 rtx reg = gen_rtx_REG (Pmode, 0);
14233 rtx mem = gen_rtx_MEM (Pmode, addr);
14234 /* This should not be of rs6000_sr_alias_set, because of
14235 __builtin_return_address. */
14237 insn = emit_move_insn (mem, reg);
14238 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14239 NULL_RTX, NULL_RTX);
14242 /* Save CR if we use any that must be preserved. */
14243 if (!WORLD_SAVE_P (info) && info->cr_save_p)
14245 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14246 GEN_INT (info->cr_save_offset + sp_offset));
14247 rtx mem = gen_rtx_MEM (SImode, addr);
14248 /* See the large comment above about why CR2_REGNO is used. */
14249 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
14251 set_mem_alias_set (mem, rs6000_sr_alias_set);
14253 /* If r12 was used to hold the original sp, copy cr into r0 now
14255 if (REGNO (frame_reg_rtx) == 12)
14259 cr_save_rtx = gen_rtx_REG (SImode, 0);
14260 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14261 RTX_FRAME_RELATED_P (insn) = 1;
14262 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
14263 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14268 insn = emit_move_insn (mem, cr_save_rtx);
14270 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14271 NULL_RTX, NULL_RTX);
14274 /* Update stack and set back pointer unless this is V.4,
14275 for which it was done previously. */
14276 if (!WORLD_SAVE_P (info) && info->push_p
14277 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
14278 rs6000_emit_allocate_stack (info->total_size, FALSE);
14280 /* Set frame pointer, if needed. */
14281 if (frame_pointer_needed)
14283 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
14285 RTX_FRAME_RELATED_P (insn) = 1;
14288 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14289 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
14290 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
14291 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
14293 /* If emit_load_toc_table will use the link register, we need to save
14294 it. We use R12 for this purpose because emit_load_toc_table
14295 can use register 0. This allows us to use a plain 'blr' to return
14296 from the procedure more often. */
14297 int save_LR_around_toc_setup = (TARGET_ELF
14298 && DEFAULT_ABI != ABI_AIX
14300 && ! info->lr_save_p
14301 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
14302 if (save_LR_around_toc_setup)
14304 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14306 insn = emit_move_insn (frame_ptr_rtx, lr);
14307 rs6000_maybe_dead (insn);
14308 RTX_FRAME_RELATED_P (insn) = 1;
14310 rs6000_emit_load_toc_table (TRUE);
14312 insn = emit_move_insn (lr, frame_ptr_rtx);
14313 rs6000_maybe_dead (insn);
14314 RTX_FRAME_RELATED_P (insn) = 1;
14317 rs6000_emit_load_toc_table (TRUE);
14321 if (DEFAULT_ABI == ABI_DARWIN
14322 && flag_pic && current_function_uses_pic_offset_table)
14324 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14325 rtx src = machopic_function_base_sym ();
14327 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14329 insn = emit_move_insn (gen_rtx_REG (Pmode,
14330 RS6000_PIC_OFFSET_TABLE_REGNUM),
14332 rs6000_maybe_dead (insn);
14337 /* Write function prologue. */
14340 rs6000_output_function_prologue (FILE *file,
14341 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14343 rs6000_stack_t *info = rs6000_stack_info ();
14345 if (TARGET_DEBUG_STACK)
14346 debug_stack_info (info);
14348 /* Write .extern for any function we will call to save and restore
14350 if (info->first_fp_reg_save < 64
14351 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14352 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14353 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14354 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14355 RESTORE_FP_SUFFIX);
14357 /* Write .extern for AIX common mode routines, if needed. */
14358 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14360 fputs ("\t.extern __mulh\n", file);
14361 fputs ("\t.extern __mull\n", file);
14362 fputs ("\t.extern __divss\n", file);
14363 fputs ("\t.extern __divus\n", file);
14364 fputs ("\t.extern __quoss\n", file);
14365 fputs ("\t.extern __quous\n", file);
14366 common_mode_defined = 1;
14369 if (! HAVE_prologue)
14373 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14374 the "toplevel" insn chain. */
14375 emit_note (NOTE_INSN_DELETED);
14376 rs6000_emit_prologue ();
14377 emit_note (NOTE_INSN_DELETED);
14379 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14383 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14385 INSN_ADDRESSES_NEW (insn, addr);
14390 if (TARGET_DEBUG_STACK)
14391 debug_rtx_list (get_insns (), 100);
14392 final (get_insns (), file, FALSE, FALSE);
14396 rs6000_pic_labelno++;
14399 /* Emit function epilogue as insns.
14401 At present, dwarf2out_frame_debug_expr doesn't understand
14402 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14403 anywhere in the epilogue. Most of the insns below would in any case
14404 need special notes to explain where r11 is in relation to the stack. */
14407 rs6000_emit_epilogue (int sibcall)
14409 rs6000_stack_t *info;
14410 int restoring_FPRs_inline;
14411 int using_load_multiple;
14412 int using_mfcr_multiple;
14413 int use_backchain_to_restore_sp;
14415 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
14416 rtx frame_reg_rtx = sp_reg_rtx;
14417 enum machine_mode reg_mode = Pmode;
14418 int reg_size = TARGET_32BIT ? 4 : 8;
14421 info = rs6000_stack_info ();
14423 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14425 reg_mode = V2SImode;
14429 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14430 && (!TARGET_SPE_ABI
14431 || info->spe_64bit_regs_used == 0)
14432 && info->first_gp_reg_save < 31);
14433 restoring_FPRs_inline = (sibcall
14434 || current_function_calls_eh_return
14435 || info->first_fp_reg_save == 64
14436 || FP_SAVE_INLINE (info->first_fp_reg_save));
14437 use_backchain_to_restore_sp = (frame_pointer_needed
14438 || current_function_calls_alloca
14439 || info->total_size > 32767);
14440 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
14441 || rs6000_cpu == PROCESSOR_PPC603
14442 || rs6000_cpu == PROCESSOR_PPC750
14445 if (WORLD_SAVE_P (info))
14449 const char *alloc_rname;
14452 /* eh_rest_world_r10 will return to the location saved in the LR
14453 stack slot (which is not likely to be our caller.)
14454 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14455 rest_world is similar, except any R10 parameter is ignored.
14456 The exception-handling stuff that was here in 2.95 is no
14457 longer necessary. */
14461 + 32 - info->first_gp_reg_save
14462 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
14463 + 63 + 1 - info->first_fp_reg_save);
14465 strcpy (rname, ((current_function_calls_eh_return) ?
14466 "*eh_rest_world_r10" : "*rest_world"));
14467 alloc_rname = ggc_strdup (rname);
14470 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
14471 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14472 gen_rtx_REG (Pmode,
14473 LINK_REGISTER_REGNUM));
14475 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
14476 /* The instruction pattern requires a clobber here;
14477 it is shared with the restVEC helper. */
14479 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14482 /* CR register traditionally saved as CR2. */
14483 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14484 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14485 GEN_INT (info->cr_save_offset));
14486 rtx mem = gen_rtx_MEM (reg_mode, addr);
14487 set_mem_alias_set (mem, rs6000_sr_alias_set);
14489 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14492 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14494 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14495 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14496 GEN_INT (info->gp_save_offset
14498 rtx mem = gen_rtx_MEM (reg_mode, addr);
14499 set_mem_alias_set (mem, rs6000_sr_alias_set);
14501 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14503 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14505 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14506 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14507 GEN_INT (info->altivec_save_offset
14509 rtx mem = gen_rtx_MEM (V4SImode, addr);
14510 set_mem_alias_set (mem, rs6000_sr_alias_set);
14512 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14514 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14516 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14517 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14518 GEN_INT (info->fp_save_offset
14520 rtx mem = gen_rtx_MEM (DFmode, addr);
14521 set_mem_alias_set (mem, rs6000_sr_alias_set);
14523 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14526 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
14528 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
14530 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
14532 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
14534 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
14535 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14540 /* If we have a frame pointer, a call to alloca, or a large stack
14541 frame, restore the old stack pointer using the backchain. Otherwise,
14542 we know what size to update it with. */
14543 if (use_backchain_to_restore_sp)
14545 /* Under V.4, don't reset the stack pointer until after we're done
14546 loading the saved registers. */
14547 if (DEFAULT_ABI == ABI_V4)
14548 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
14550 emit_move_insn (frame_reg_rtx,
14551 gen_rtx_MEM (Pmode, sp_reg_rtx));
14554 else if (info->push_p)
14556 if (DEFAULT_ABI == ABI_V4
14557 || current_function_calls_eh_return)
14558 sp_offset = info->total_size;
14561 emit_insn (TARGET_32BIT
14562 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14563 GEN_INT (info->total_size))
14564 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14565 GEN_INT (info->total_size)));
14569 /* Restore AltiVec registers if needed. */
14570 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14574 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14575 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14577 rtx addr, areg, mem;
14579 areg = gen_rtx_REG (Pmode, 0);
14581 (areg, GEN_INT (info->altivec_save_offset
14583 + 16 * (i - info->first_altivec_reg_save)));
14585 /* AltiVec addressing mode is [reg+reg]. */
14586 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14587 mem = gen_rtx_MEM (V4SImode, addr);
14588 set_mem_alias_set (mem, rs6000_sr_alias_set);
14590 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14594 /* Restore VRSAVE if needed. */
14595 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14596 && info->vrsave_mask != 0)
14598 rtx addr, mem, reg;
14600 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14601 GEN_INT (info->vrsave_save_offset + sp_offset));
14602 mem = gen_rtx_MEM (SImode, addr);
14603 set_mem_alias_set (mem, rs6000_sr_alias_set);
14604 reg = gen_rtx_REG (SImode, 12);
14605 emit_move_insn (reg, mem);
14607 emit_insn (generate_set_vrsave (reg, info, 1));
14610 /* Get the old lr if we saved it. */
14611 if (info->lr_save_p)
14613 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
14614 info->lr_save_offset + sp_offset);
14616 set_mem_alias_set (mem, rs6000_sr_alias_set);
14618 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
14621 /* Get the old cr if we saved it. */
14622 if (info->cr_save_p)
14624 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14625 GEN_INT (info->cr_save_offset + sp_offset));
14626 rtx mem = gen_rtx_MEM (SImode, addr);
14628 set_mem_alias_set (mem, rs6000_sr_alias_set);
14630 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
14633 /* Set LR here to try to overlap restores below. */
14634 if (info->lr_save_p)
14635 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
14636 gen_rtx_REG (Pmode, 0));
14638 /* Load exception handler data registers, if needed. */
14639 if (current_function_calls_eh_return)
14641 unsigned int i, regno;
14645 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14646 GEN_INT (sp_offset + 5 * reg_size));
14647 rtx mem = gen_rtx_MEM (reg_mode, addr);
14649 set_mem_alias_set (mem, rs6000_sr_alias_set);
14651 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
14658 regno = EH_RETURN_DATA_REGNO (i);
14659 if (regno == INVALID_REGNUM)
14662 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
14663 info->ehrd_offset + sp_offset
14664 + reg_size * (int) i);
14665 set_mem_alias_set (mem, rs6000_sr_alias_set);
14667 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
14671 /* Restore GPRs. This is done as a PARALLEL if we are using
14672 the load-multiple instructions. */
14673 if (using_load_multiple)
14676 p = rtvec_alloc (32 - info->first_gp_reg_save);
14677 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14679 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14680 GEN_INT (info->gp_save_offset
14683 rtx mem = gen_rtx_MEM (reg_mode, addr);
14685 set_mem_alias_set (mem, rs6000_sr_alias_set);
14688 gen_rtx_SET (VOIDmode,
14689 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
14692 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14695 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14696 if ((regs_ever_live[info->first_gp_reg_save+i]
14697 && (! call_used_regs[info->first_gp_reg_save+i]
14698 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14699 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14700 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14701 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14702 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14704 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14705 GEN_INT (info->gp_save_offset
14708 rtx mem = gen_rtx_MEM (reg_mode, addr);
14710 /* Restore 64-bit quantities for SPE. */
14711 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14713 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14716 if (!SPE_CONST_OFFSET_OK (offset))
14718 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14719 emit_move_insn (b, GEN_INT (offset));
14722 b = GEN_INT (offset);
14724 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14725 mem = gen_rtx_MEM (V2SImode, addr);
14728 set_mem_alias_set (mem, rs6000_sr_alias_set);
14730 emit_move_insn (gen_rtx_REG (reg_mode,
14731 info->first_gp_reg_save + i), mem);
14734 /* Restore fpr's if we need to do it without calling a function. */
14735 if (restoring_FPRs_inline)
14736 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14737 if ((regs_ever_live[info->first_fp_reg_save+i]
14738 && ! call_used_regs[info->first_fp_reg_save+i]))
14741 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14742 GEN_INT (info->fp_save_offset
14745 mem = gen_rtx_MEM (DFmode, addr);
14746 set_mem_alias_set (mem, rs6000_sr_alias_set);
14748 emit_move_insn (gen_rtx_REG (DFmode,
14749 info->first_fp_reg_save + i),
14753 /* If we saved cr, restore it here. Just those that were used. */
14754 if (info->cr_save_p)
14756 rtx r12_rtx = gen_rtx_REG (SImode, 12);
14759 if (using_mfcr_multiple)
14761 for (i = 0; i < 8; i++)
14762 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14768 if (using_mfcr_multiple && count > 1)
14773 p = rtvec_alloc (count);
14776 for (i = 0; i < 8; i++)
14777 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14779 rtvec r = rtvec_alloc (2);
14780 RTVEC_ELT (r, 0) = r12_rtx;
14781 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
14782 RTVEC_ELT (p, ndx) =
14783 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
14784 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
14787 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14792 for (i = 0; i < 8; i++)
14793 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14795 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
14801 /* If this is V.4, unwind the stack pointer after all of the loads
14802 have been done. We need to emit a block here so that sched
14803 doesn't decide to move the sp change before the register restores
14804 (which may not have any obvious dependency on the stack). This
14805 doesn't hurt performance, because there is no scheduling that can
14806 be done after this point. */
14807 if (DEFAULT_ABI == ABI_V4
14808 || current_function_calls_eh_return)
14810 if (frame_reg_rtx != sp_reg_rtx)
14811 rs6000_emit_stack_tie ();
14813 if (use_backchain_to_restore_sp)
14815 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
14817 else if (sp_offset != 0)
14819 emit_insn (TARGET_32BIT
14820 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14821 GEN_INT (sp_offset))
14822 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14823 GEN_INT (sp_offset)));
14827 if (current_function_calls_eh_return)
14829 rtx sa = EH_RETURN_STACKADJ_RTX;
14830 emit_insn (TARGET_32BIT
14831 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
14832 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
14838 if (! restoring_FPRs_inline)
14839 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
14841 p = rtvec_alloc (2);
14843 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
14844 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14845 gen_rtx_REG (Pmode,
14846 LINK_REGISTER_REGNUM));
14848 /* If we have to restore more than two FP registers, branch to the
14849 restore function. It will return to our caller. */
14850 if (! restoring_FPRs_inline)
14854 const char *alloc_rname;
14856 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
14857 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
14858 alloc_rname = ggc_strdup (rname);
14859 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
14860 gen_rtx_SYMBOL_REF (Pmode,
14863 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14866 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
14867 GEN_INT (info->fp_save_offset + 8*i));
14868 mem = gen_rtx_MEM (DFmode, addr);
14869 set_mem_alias_set (mem, rs6000_sr_alias_set);
14871 RTVEC_ELT (p, i+3) =
14872 gen_rtx_SET (VOIDmode,
14873 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
14878 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14882 /* Write function epilogue. */
14885 rs6000_output_function_epilogue (FILE *file,
14886 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14888 rs6000_stack_t *info = rs6000_stack_info ();
14890 if (! HAVE_epilogue)
14892 rtx insn = get_last_insn ();
14893 /* If the last insn was a BARRIER, we don't have to write anything except
14894 the trace table. */
14895 if (GET_CODE (insn) == NOTE)
14896 insn = prev_nonnote_insn (insn);
14897 if (insn == 0 || GET_CODE (insn) != BARRIER)
14899 /* This is slightly ugly, but at least we don't have two
14900 copies of the epilogue-emitting code. */
14903 /* A NOTE_INSN_DELETED is supposed to be at the start
14904 and end of the "toplevel" insn chain. */
14905 emit_note (NOTE_INSN_DELETED);
14906 rs6000_emit_epilogue (FALSE);
14907 emit_note (NOTE_INSN_DELETED);
14909 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14913 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14915 INSN_ADDRESSES_NEW (insn, addr);
14920 if (TARGET_DEBUG_STACK)
14921 debug_rtx_list (get_insns (), 100);
14922 final (get_insns (), file, FALSE, FALSE);
14928 macho_branch_islands ();
14929 /* Mach-O doesn't support labels at the end of objects, so if
14930 it looks like we might want one, insert a NOP. */
14932 rtx insn = get_last_insn ();
14935 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
14936 insn = PREV_INSN (insn);
14940 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
14941 fputs ("\tnop\n", file);
14945 /* Output a traceback table here. See /usr/include/sys/debug.h for info
14948 We don't output a traceback table if -finhibit-size-directive was
14949 used. The documentation for -finhibit-size-directive reads
14950 ``don't output a @code{.size} assembler directive, or anything
14951 else that would cause trouble if the function is split in the
14952 middle, and the two halves are placed at locations far apart in
14953 memory.'' The traceback table has this property, since it
14954 includes the offset from the start of the function to the
14955 traceback table itself.
14957 System V.4 Powerpc's (and the embedded ABI derived from it) use a
14958 different traceback table. */
14959 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
14960 && rs6000_traceback != traceback_none)
14962 const char *fname = NULL;
14963 const char *language_string = lang_hooks.name;
14964 int fixed_parms = 0, float_parms = 0, parm_info = 0;
14966 int optional_tbtab;
14968 if (rs6000_traceback == traceback_full)
14969 optional_tbtab = 1;
14970 else if (rs6000_traceback == traceback_part)
14971 optional_tbtab = 0;
14973 optional_tbtab = !optimize_size && !TARGET_ELF;
14975 if (optional_tbtab)
14977 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
14978 while (*fname == '.') /* V.4 encodes . in the name */
14981 /* Need label immediately before tbtab, so we can compute
14982 its offset from the function start. */
14983 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
14984 ASM_OUTPUT_LABEL (file, fname);
14987 /* The .tbtab pseudo-op can only be used for the first eight
14988 expressions, since it can't handle the possibly variable
14989 length fields that follow. However, if you omit the optional
14990 fields, the assembler outputs zeros for all optional fields
14991 anyways, giving each variable length field is minimum length
14992 (as defined in sys/debug.h). Thus we can not use the .tbtab
14993 pseudo-op at all. */
14995 /* An all-zero word flags the start of the tbtab, for debuggers
14996 that have to find it by searching forward from the entry
14997 point or from the current pc. */
14998 fputs ("\t.long 0\n", file);
15000 /* Tbtab format type. Use format type 0. */
15001 fputs ("\t.byte 0,", file);
15003 /* Language type. Unfortunately, there does not seem to be any
15004 official way to discover the language being compiled, so we
15005 use language_string.
15006 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15007 Java is 13. Objective-C is 14. */
15008 if (! strcmp (language_string, "GNU C"))
15010 else if (! strcmp (language_string, "GNU F77")
15011 || ! strcmp (language_string, "GNU F95"))
15013 else if (! strcmp (language_string, "GNU Pascal"))
15015 else if (! strcmp (language_string, "GNU Ada"))
15017 else if (! strcmp (language_string, "GNU C++"))
15019 else if (! strcmp (language_string, "GNU Java"))
15021 else if (! strcmp (language_string, "GNU Objective-C"))
15025 fprintf (file, "%d,", i);
15027 /* 8 single bit fields: global linkage (not set for C extern linkage,
15028 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15029 from start of procedure stored in tbtab, internal function, function
15030 has controlled storage, function has no toc, function uses fp,
15031 function logs/aborts fp operations. */
15032 /* Assume that fp operations are used if any fp reg must be saved. */
15033 fprintf (file, "%d,",
15034 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15036 /* 6 bitfields: function is interrupt handler, name present in
15037 proc table, function calls alloca, on condition directives
15038 (controls stack walks, 3 bits), saves condition reg, saves
15040 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15041 set up as a frame pointer, even when there is no alloca call. */
15042 fprintf (file, "%d,",
15043 ((optional_tbtab << 6)
15044 | ((optional_tbtab & frame_pointer_needed) << 5)
15045 | (info->cr_save_p << 1)
15046 | (info->lr_save_p)));
15048 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15050 fprintf (file, "%d,",
15051 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15053 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15054 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15056 if (optional_tbtab)
15058 /* Compute the parameter info from the function decl argument
15061 int next_parm_info_bit = 31;
15063 for (decl = DECL_ARGUMENTS (current_function_decl);
15064 decl; decl = TREE_CHAIN (decl))
15066 rtx parameter = DECL_INCOMING_RTL (decl);
15067 enum machine_mode mode = GET_MODE (parameter);
15069 if (GET_CODE (parameter) == REG)
15071 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
15077 if (mode == SFmode)
15079 else if (mode == DFmode || mode == TFmode)
15084 /* If only one bit will fit, don't or in this entry. */
15085 if (next_parm_info_bit > 0)
15086 parm_info |= (bits << (next_parm_info_bit - 1));
15087 next_parm_info_bit -= 2;
15091 fixed_parms += ((GET_MODE_SIZE (mode)
15092 + (UNITS_PER_WORD - 1))
15094 next_parm_info_bit -= 1;
15100 /* Number of fixed point parameters. */
15101 /* This is actually the number of words of fixed point parameters; thus
15102 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15103 fprintf (file, "%d,", fixed_parms);
15105 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15107 /* This is actually the number of fp registers that hold parameters;
15108 and thus the maximum value is 13. */
15109 /* Set parameters on stack bit if parameters are not in their original
15110 registers, regardless of whether they are on the stack? Xlc
15111 seems to set the bit when not optimizing. */
15112 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15114 if (! optional_tbtab)
15117 /* Optional fields follow. Some are variable length. */
15119 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15120 11 double float. */
15121 /* There is an entry for each parameter in a register, in the order that
15122 they occur in the parameter list. Any intervening arguments on the
15123 stack are ignored. If the list overflows a long (max possible length
15124 34 bits) then completely leave off all elements that don't fit. */
15125 /* Only emit this long if there was at least one parameter. */
15126 if (fixed_parms || float_parms)
15127 fprintf (file, "\t.long %d\n", parm_info);
15129 /* Offset from start of code to tb table. */
15130 fputs ("\t.long ", file);
15131 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15133 RS6000_OUTPUT_BASENAME (file, fname);
15135 assemble_name (file, fname);
15137 rs6000_output_function_entry (file, fname);
15140 /* Interrupt handler mask. */
15141 /* Omit this long, since we never set the interrupt handler bit
15144 /* Number of CTL (controlled storage) anchors. */
15145 /* Omit this long, since the has_ctl bit is never set above. */
15147 /* Displacement into stack of each CTL anchor. */
15148 /* Omit this list of longs, because there are no CTL anchors. */
15150 /* Length of function name. */
15153 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15155 /* Function name. */
15156 assemble_string (fname, strlen (fname));
15158 /* Register for alloca automatic storage; this is always reg 31.
15159 Only emit this if the alloca bit was set above. */
15160 if (frame_pointer_needed)
15161 fputs ("\t.byte 31\n", file);
15163 fputs ("\t.align 2\n", file);
15167 /* A C compound statement that outputs the assembler code for a thunk
15168 function, used to implement C++ virtual function calls with
15169 multiple inheritance. The thunk acts as a wrapper around a virtual
15170 function, adjusting the implicit object parameter before handing
15171 control off to the real function.
15173 First, emit code to add the integer DELTA to the location that
15174 contains the incoming first argument. Assume that this argument
15175 contains a pointer, and is the one used to pass the `this' pointer
15176 in C++. This is the incoming argument *before* the function
15177 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15178 values of all other incoming arguments.
15180 After the addition, emit code to jump to FUNCTION, which is a
15181 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15182 not touch the return address. Hence returning from FUNCTION will
15183 return to whoever called the current `thunk'.
15185 The effect must be as if FUNCTION had been called directly with the
15186 adjusted first argument. This macro is responsible for emitting
15187 all of the code for a thunk function; output_function_prologue()
15188 and output_function_epilogue() are not invoked.
15190 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15191 been extracted from it.) It might possibly be useful on some
15192 targets, but probably not.
15194 If you do not define this macro, the target-independent code in the
15195 C++ frontend will generate a less efficient heavyweight thunk that
15196 calls FUNCTION instead of jumping to it. The generic approach does
15197 not support varargs. */
15200 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15201 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15204 rtx this, insn, funexp;
15206 reload_completed = 1;
15207 epilogue_completed = 1;
15208 no_new_pseudos = 1;
15209 reset_block_changes ();
15211 /* Mark the end of the (empty) prologue. */
15212 emit_note (NOTE_INSN_PROLOGUE_END);
15214 /* Find the "this" pointer. If the function returns a structure,
15215 the structure return pointer is in r3. */
15216 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15217 this = gen_rtx_REG (Pmode, 4);
15219 this = gen_rtx_REG (Pmode, 3);
15221 /* Apply the constant offset, if required. */
15224 rtx delta_rtx = GEN_INT (delta);
15225 emit_insn (TARGET_32BIT
15226 ? gen_addsi3 (this, this, delta_rtx)
15227 : gen_adddi3 (this, this, delta_rtx));
15230 /* Apply the offset from the vtable, if required. */
15233 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15234 rtx tmp = gen_rtx_REG (Pmode, 12);
15236 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
15237 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15239 emit_insn (TARGET_32BIT
15240 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
15241 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
15242 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15246 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15248 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15250 emit_insn (TARGET_32BIT
15251 ? gen_addsi3 (this, this, tmp)
15252 : gen_adddi3 (this, this, tmp));
15255 /* Generate a tail call to the target function. */
15256 if (!TREE_USED (function))
15258 assemble_external (function);
15259 TREE_USED (function) = 1;
15261 funexp = XEXP (DECL_RTL (function), 0);
15262 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15265 if (MACHOPIC_INDIRECT)
15266 funexp = machopic_indirect_call_target (funexp);
15269 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15270 generate sibcall RTL explicitly to avoid constraint abort. */
15271 insn = emit_call_insn (
15272 gen_rtx_PARALLEL (VOIDmode,
15274 gen_rtx_CALL (VOIDmode,
15275 funexp, const0_rtx),
15276 gen_rtx_USE (VOIDmode, const0_rtx),
15277 gen_rtx_USE (VOIDmode,
15278 gen_rtx_REG (SImode,
15279 LINK_REGISTER_REGNUM)),
15280 gen_rtx_RETURN (VOIDmode))));
15281 SIBLING_CALL_P (insn) = 1;
15284 /* Run just enough of rest_of_compilation to get the insns emitted.
15285 There's not really enough bulk here to make other passes such as
15286 instruction scheduling worth while. Note that use_thunk calls
15287 assemble_start_function and assemble_end_function. */
15288 insn = get_insns ();
15289 insn_locators_initialize ();
15290 shorten_branches (insn);
15291 final_start_function (insn, file, 1);
15292 final (insn, file, 1, 0);
15293 final_end_function ();
15295 reload_completed = 0;
15296 epilogue_completed = 0;
15297 no_new_pseudos = 0;
15300 /* A quick summary of the various types of 'constant-pool tables'
15303 Target Flags Name One table per
15304 AIX (none) AIX TOC object file
15305 AIX -mfull-toc AIX TOC object file
15306 AIX -mminimal-toc AIX minimal TOC translation unit
15307 SVR4/EABI (none) SVR4 SDATA object file
15308 SVR4/EABI -fpic SVR4 pic object file
15309 SVR4/EABI -fPIC SVR4 PIC translation unit
15310 SVR4/EABI -mrelocatable EABI TOC function
15311 SVR4/EABI -maix AIX TOC object file
15312 SVR4/EABI -maix -mminimal-toc
15313 AIX minimal TOC translation unit
15315 Name Reg. Set by entries contains:
15316 made by addrs? fp? sum?
15318 AIX TOC 2 crt0 as Y option option
15319 AIX minimal TOC 30 prolog gcc Y Y option
15320 SVR4 SDATA 13 crt0 gcc N Y N
15321 SVR4 pic 30 prolog ld Y not yet N
15322 SVR4 PIC 30 prolog gcc Y option option
15323 EABI TOC 30 prolog gcc Y option option
15327 /* Hash functions for the hash table. */
15330 rs6000_hash_constant (rtx k)
15332 enum rtx_code code = GET_CODE (k);
15333 enum machine_mode mode = GET_MODE (k);
15334 unsigned result = (code << 3) ^ mode;
15335 const char *format;
15338 format = GET_RTX_FORMAT (code);
15339 flen = strlen (format);
15345 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15348 if (mode != VOIDmode)
15349 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15361 for (; fidx < flen; fidx++)
15362 switch (format[fidx])
15367 const char *str = XSTR (k, fidx);
15368 len = strlen (str);
15369 result = result * 613 + len;
15370 for (i = 0; i < len; i++)
15371 result = result * 613 + (unsigned) str[i];
15376 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15380 result = result * 613 + (unsigned) XINT (k, fidx);
15383 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15384 result = result * 613 + (unsigned) XWINT (k, fidx);
15388 for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
15389 result = result * 613 + (unsigned) (XWINT (k, fidx)
15403 toc_hash_function (const void *hash_entry)
15405 const struct toc_hash_struct *thc =
15406 (const struct toc_hash_struct *) hash_entry;
15407 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15410 /* Compare H1 and H2 for equivalence. */
15413 toc_hash_eq (const void *h1, const void *h2)
15415 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
15416 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
15418 if (((const struct toc_hash_struct *) h1)->key_mode
15419 != ((const struct toc_hash_struct *) h2)->key_mode)
15422 return rtx_equal_p (r1, r2);
15425 /* These are the names given by the C++ front-end to vtables, and
15426 vtable-like objects. Ideally, this logic should not be here;
15427 instead, there should be some programmatic way of inquiring as
15428 to whether or not an object is a vtable. */
15430 #define VTABLE_NAME_P(NAME) \
15431 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
15432 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15433 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15434 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15435 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15438 rs6000_output_symbol_ref (FILE *file, rtx x)
15440 /* Currently C++ toc references to vtables can be emitted before it
15441 is decided whether the vtable is public or private. If this is
15442 the case, then the linker will eventually complain that there is
15443 a reference to an unknown section. Thus, for vtables only,
15444 we emit the TOC reference to reference the symbol and not the
15446 const char *name = XSTR (x, 0);
15448 if (VTABLE_NAME_P (name))
15450 RS6000_OUTPUT_BASENAME (file, name);
15453 assemble_name (file, name);
15456 /* Output a TOC entry. We derive the entry name from what is being
15460 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
15463 const char *name = buf;
15464 const char *real_name;
15471 /* When the linker won't eliminate them, don't output duplicate
15472 TOC entries (this happens on AIX if there is any kind of TOC,
15473 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15475 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15477 struct toc_hash_struct *h;
15480 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15481 time because GGC is not initialized at that point. */
15482 if (toc_hash_table == NULL)
15483 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15484 toc_hash_eq, NULL);
15486 h = ggc_alloc (sizeof (*h));
15488 h->key_mode = mode;
15489 h->labelno = labelno;
15491 found = htab_find_slot (toc_hash_table, h, 1);
15492 if (*found == NULL)
15494 else /* This is indeed a duplicate.
15495 Set this label equal to that label. */
15497 fputs ("\t.set ", file);
15498 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15499 fprintf (file, "%d,", labelno);
15500 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15501 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15507 /* If we're going to put a double constant in the TOC, make sure it's
15508 aligned properly when strict alignment is on. */
15509 if (GET_CODE (x) == CONST_DOUBLE
15510 && STRICT_ALIGNMENT
15511 && GET_MODE_BITSIZE (mode) >= 64
15512 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15513 ASM_OUTPUT_ALIGN (file, 3);
15516 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15518 /* Handle FP constants specially. Note that if we have a minimal
15519 TOC, things we put here aren't actually in the TOC, so we can allow
15521 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
15523 REAL_VALUE_TYPE rv;
15526 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15527 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15531 if (TARGET_MINIMAL_TOC)
15532 fputs (DOUBLE_INT_ASM_OP, file);
15534 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15535 k[0] & 0xffffffff, k[1] & 0xffffffff,
15536 k[2] & 0xffffffff, k[3] & 0xffffffff);
15537 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15538 k[0] & 0xffffffff, k[1] & 0xffffffff,
15539 k[2] & 0xffffffff, k[3] & 0xffffffff);
15544 if (TARGET_MINIMAL_TOC)
15545 fputs ("\t.long ", file);
15547 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15548 k[0] & 0xffffffff, k[1] & 0xffffffff,
15549 k[2] & 0xffffffff, k[3] & 0xffffffff);
15550 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15551 k[0] & 0xffffffff, k[1] & 0xffffffff,
15552 k[2] & 0xffffffff, k[3] & 0xffffffff);
15556 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
15558 REAL_VALUE_TYPE rv;
15561 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15562 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
15566 if (TARGET_MINIMAL_TOC)
15567 fputs (DOUBLE_INT_ASM_OP, file);
15569 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15570 k[0] & 0xffffffff, k[1] & 0xffffffff);
15571 fprintf (file, "0x%lx%08lx\n",
15572 k[0] & 0xffffffff, k[1] & 0xffffffff);
15577 if (TARGET_MINIMAL_TOC)
15578 fputs ("\t.long ", file);
15580 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15581 k[0] & 0xffffffff, k[1] & 0xffffffff);
15582 fprintf (file, "0x%lx,0x%lx\n",
15583 k[0] & 0xffffffff, k[1] & 0xffffffff);
15587 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
15589 REAL_VALUE_TYPE rv;
15592 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15593 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15597 if (TARGET_MINIMAL_TOC)
15598 fputs (DOUBLE_INT_ASM_OP, file);
15600 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15601 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
15606 if (TARGET_MINIMAL_TOC)
15607 fputs ("\t.long ", file);
15609 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15610 fprintf (file, "0x%lx\n", l & 0xffffffff);
15614 else if (GET_MODE (x) == VOIDmode
15615 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
15617 unsigned HOST_WIDE_INT low;
15618 HOST_WIDE_INT high;
15620 if (GET_CODE (x) == CONST_DOUBLE)
15622 low = CONST_DOUBLE_LOW (x);
15623 high = CONST_DOUBLE_HIGH (x);
15626 #if HOST_BITS_PER_WIDE_INT == 32
15629 high = (low & 0x80000000) ? ~0 : 0;
15633 low = INTVAL (x) & 0xffffffff;
15634 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
15638 /* TOC entries are always Pmode-sized, but since this
15639 is a bigendian machine then if we're putting smaller
15640 integer constants in the TOC we have to pad them.
15641 (This is still a win over putting the constants in
15642 a separate constant pool, because then we'd have
15643 to have both a TOC entry _and_ the actual constant.)
15645 For a 32-bit target, CONST_INT values are loaded and shifted
15646 entirely within `low' and can be stored in one TOC entry. */
15648 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
15649 abort ();/* It would be easy to make this work, but it doesn't now. */
15651 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
15653 #if HOST_BITS_PER_WIDE_INT == 32
15654 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15655 POINTER_SIZE, &low, &high, 0);
15658 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
15659 high = (HOST_WIDE_INT) low >> 32;
15666 if (TARGET_MINIMAL_TOC)
15667 fputs (DOUBLE_INT_ASM_OP, file);
15669 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15670 (long) high & 0xffffffff, (long) low & 0xffffffff);
15671 fprintf (file, "0x%lx%08lx\n",
15672 (long) high & 0xffffffff, (long) low & 0xffffffff);
15677 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
15679 if (TARGET_MINIMAL_TOC)
15680 fputs ("\t.long ", file);
15682 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15683 (long) high & 0xffffffff, (long) low & 0xffffffff);
15684 fprintf (file, "0x%lx,0x%lx\n",
15685 (long) high & 0xffffffff, (long) low & 0xffffffff);
15689 if (TARGET_MINIMAL_TOC)
15690 fputs ("\t.long ", file);
15692 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
15693 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
15699 if (GET_CODE (x) == CONST)
15701 if (GET_CODE (XEXP (x, 0)) != PLUS)
15704 base = XEXP (XEXP (x, 0), 0);
15705 offset = INTVAL (XEXP (XEXP (x, 0), 1));
15708 if (GET_CODE (base) == SYMBOL_REF)
15709 name = XSTR (base, 0);
15710 else if (GET_CODE (base) == LABEL_REF)
15711 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
15712 else if (GET_CODE (base) == CODE_LABEL)
15713 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
15717 real_name = (*targetm.strip_name_encoding) (name);
15718 if (TARGET_MINIMAL_TOC)
15719 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
15722 fprintf (file, "\t.tc %s", real_name);
15725 fprintf (file, ".N%d", - offset);
15727 fprintf (file, ".P%d", offset);
15729 fputs ("[TC],", file);
15732 /* Currently C++ toc references to vtables can be emitted before it
15733 is decided whether the vtable is public or private. If this is
15734 the case, then the linker will eventually complain that there is
15735 a TOC reference to an unknown section. Thus, for vtables only,
15736 we emit the TOC reference to reference the symbol and not the
15738 if (VTABLE_NAME_P (name))
15740 RS6000_OUTPUT_BASENAME (file, name);
15742 fprintf (file, "%d", offset);
15743 else if (offset > 0)
15744 fprintf (file, "+%d", offset);
15747 output_addr_const (file, x);
15751 /* Output an assembler pseudo-op to write an ASCII string of N characters
15752 starting at P to FILE.
15754 On the RS/6000, we have to do this using the .byte operation and
15755 write out special characters outside the quoted string.
15756 Also, the assembler is broken; very long strings are truncated,
15757 so we must artificially break them up early. */
15760 output_ascii (FILE *file, const char *p, int n)
15763 int i, count_string;
15764 const char *for_string = "\t.byte \"";
15765 const char *for_decimal = "\t.byte ";
15766 const char *to_close = NULL;
15769 for (i = 0; i < n; i++)
15772 if (c >= ' ' && c < 0177)
15775 fputs (for_string, file);
15778 /* Write two quotes to get one. */
15786 for_decimal = "\"\n\t.byte ";
15790 if (count_string >= 512)
15792 fputs (to_close, file);
15794 for_string = "\t.byte \"";
15795 for_decimal = "\t.byte ";
15803 fputs (for_decimal, file);
15804 fprintf (file, "%d", c);
15806 for_string = "\n\t.byte \"";
15807 for_decimal = ", ";
15813 /* Now close the string if we have written one. Then end the line. */
15815 fputs (to_close, file);
15818 /* Generate a unique section name for FILENAME for a section type
15819 represented by SECTION_DESC. Output goes into BUF.
15821 SECTION_DESC can be any string, as long as it is different for each
15822 possible section type.
15824 We name the section in the same manner as xlc. The name begins with an
15825 underscore followed by the filename (after stripping any leading directory
15826 names) with the last period replaced by the string SECTION_DESC. If
15827 FILENAME does not contain a period, SECTION_DESC is appended to the end of
15831 rs6000_gen_section_name (char **buf, const char *filename,
15832 const char *section_desc)
15834 const char *q, *after_last_slash, *last_period = 0;
15838 after_last_slash = filename;
15839 for (q = filename; *q; q++)
15842 after_last_slash = q + 1;
15843 else if (*q == '.')
15847 len = strlen (after_last_slash) + strlen (section_desc) + 2;
15848 *buf = (char *) xmalloc (len);
15853 for (q = after_last_slash; *q; q++)
15855 if (q == last_period)
15857 strcpy (p, section_desc);
15858 p += strlen (section_desc);
15862 else if (ISALNUM (*q))
15866 if (last_period == 0)
15867 strcpy (p, section_desc);
15872 /* Emit profile function. */
15875 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
15877 if (TARGET_PROFILE_KERNEL)
15880 if (DEFAULT_ABI == ABI_AIX)
15882 #ifndef NO_PROFILE_COUNTERS
15883 # define NO_PROFILE_COUNTERS 0
15885 if (NO_PROFILE_COUNTERS)
15886 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
15890 const char *label_name;
15893 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
15894 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
15895 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
15897 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
15901 else if (DEFAULT_ABI == ABI_DARWIN)
15903 const char *mcount_name = RS6000_MCOUNT;
15904 int caller_addr_regno = LINK_REGISTER_REGNUM;
15906 /* Be conservative and always set this, at least for now. */
15907 current_function_uses_pic_offset_table = 1;
15910 /* For PIC code, set up a stub and collect the caller's address
15911 from r0, which is where the prologue puts it. */
15912 if (MACHOPIC_INDIRECT
15913 && current_function_uses_pic_offset_table)
15914 caller_addr_regno = 0;
15916 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
15918 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
15922 /* Write function profiler code. */
15925 output_function_profiler (FILE *file, int labelno)
15930 switch (DEFAULT_ABI)
15939 warning ("no profiling of 64-bit code for this ABI");
15942 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
15943 fprintf (file, "\tmflr %s\n", reg_names[0]);
15946 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
15947 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15948 reg_names[0], save_lr, reg_names[1]);
15949 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
15950 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
15951 assemble_name (file, buf);
15952 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
15954 else if (flag_pic > 1)
15956 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15957 reg_names[0], save_lr, reg_names[1]);
15958 /* Now, we need to get the address of the label. */
15959 fputs ("\tbl 1f\n\t.long ", file);
15960 assemble_name (file, buf);
15961 fputs ("-.\n1:", file);
15962 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
15963 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
15964 reg_names[0], reg_names[11]);
15965 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
15966 reg_names[0], reg_names[0], reg_names[11]);
15970 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
15971 assemble_name (file, buf);
15972 fputs ("@ha\n", file);
15973 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15974 reg_names[0], save_lr, reg_names[1]);
15975 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
15976 assemble_name (file, buf);
15977 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
15980 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
15981 fprintf (file, "\tbl %s%s\n",
15982 RS6000_MCOUNT, flag_pic ? "@plt" : "");
15987 if (!TARGET_PROFILE_KERNEL)
15989 /* Don't do anything, done in output_profile_hook (). */
15996 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
15997 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
15999 if (cfun->static_chain_decl != NULL)
16001 asm_fprintf (file, "\tstd %s,24(%s)\n",
16002 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16003 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16004 asm_fprintf (file, "\tld %s,24(%s)\n",
16005 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16008 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16015 /* Power4 load update and store update instructions are cracked into a
16016 load or store and an integer insn which are executed in the same cycle.
16017 Branches have their own dispatch slot which does not count against the
16018 GCC issue rate, but it changes the program flow so there are no other
16019 instructions to issue in this cycle. */
16022 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16023 int verbose ATTRIBUTE_UNUSED,
16024 rtx insn, int more)
16026 if (GET_CODE (PATTERN (insn)) == USE
16027 || GET_CODE (PATTERN (insn)) == CLOBBER)
16030 if (rs6000_sched_groups)
16032 if (is_microcoded_insn (insn))
16034 else if (is_cracked_insn (insn))
16035 return more > 2 ? more - 2 : 0;
16041 /* Adjust the cost of a scheduling dependency. Return the new cost of
16042 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16045 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16047 if (! recog_memoized (insn))
16050 if (REG_NOTE_KIND (link) != 0)
16053 if (REG_NOTE_KIND (link) == 0)
16055 /* Data dependency; DEP_INSN writes a register that INSN reads
16056 some cycles later. */
16058 /* Separate a load from a narrower, dependent store. */
16059 if (rs6000_sched_groups
16060 && GET_CODE (PATTERN (insn)) == SET
16061 && GET_CODE (PATTERN (dep_insn)) == SET
16062 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16063 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16064 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16065 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16068 switch (get_attr_type (insn))
16071 /* Tell the first scheduling pass about the latency between
16072 a mtctr and bctr (and mtlr and br/blr). The first
16073 scheduling pass will not know about this latency since
16074 the mtctr instruction, which has the latency associated
16075 to it, will be generated by reload. */
16076 return TARGET_POWER ? 5 : 4;
16078 /* Leave some extra cycles between a compare and its
16079 dependent branch, to inhibit expensive mispredicts. */
16080 if ((rs6000_cpu_attr == CPU_PPC603
16081 || rs6000_cpu_attr == CPU_PPC604
16082 || rs6000_cpu_attr == CPU_PPC604E
16083 || rs6000_cpu_attr == CPU_PPC620
16084 || rs6000_cpu_attr == CPU_PPC630
16085 || rs6000_cpu_attr == CPU_PPC750
16086 || rs6000_cpu_attr == CPU_PPC7400
16087 || rs6000_cpu_attr == CPU_PPC7450
16088 || rs6000_cpu_attr == CPU_POWER4
16089 || rs6000_cpu_attr == CPU_POWER5)
16090 && recog_memoized (dep_insn)
16091 && (INSN_CODE (dep_insn) >= 0)
16092 && (get_attr_type (dep_insn) == TYPE_CMP
16093 || get_attr_type (dep_insn) == TYPE_COMPARE
16094 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
16095 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
16096 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
16097 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
16098 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
16099 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
16104 /* Fall out to return default cost. */
16110 /* The function returns a true if INSN is microcoded.
16111 Return false otherwise. */
16114 is_microcoded_insn (rtx insn)
16116 if (!insn || !INSN_P (insn)
16117 || GET_CODE (PATTERN (insn)) == USE
16118 || GET_CODE (PATTERN (insn)) == CLOBBER)
16121 if (rs6000_sched_groups)
16123 enum attr_type type = get_attr_type (insn);
16124 if (type == TYPE_LOAD_EXT_U
16125 || type == TYPE_LOAD_EXT_UX
16126 || type == TYPE_LOAD_UX
16127 || type == TYPE_STORE_UX
16128 || type == TYPE_MFCR)
16135 /* The function returns a nonzero value if INSN can be scheduled only
16136 as the first insn in a dispatch group ("dispatch-slot restricted").
16137 In this case, the returned value indicates how many dispatch slots
16138 the insn occupies (at the beginning of the group).
16139 Return 0 otherwise. */
16142 is_dispatch_slot_restricted (rtx insn)
16144 enum attr_type type;
16146 if (!rs6000_sched_groups)
16150 || insn == NULL_RTX
16151 || GET_CODE (insn) == NOTE
16152 || GET_CODE (PATTERN (insn)) == USE
16153 || GET_CODE (PATTERN (insn)) == CLOBBER)
16156 type = get_attr_type (insn);
16163 case TYPE_DELAYED_CR:
16164 case TYPE_CR_LOGICAL:
16172 if (rs6000_cpu == PROCESSOR_POWER5
16173 && is_cracked_insn (insn))
16179 /* The function returns true if INSN is cracked into 2 instructions
16180 by the processor (and therefore occupies 2 issue slots). */
16183 is_cracked_insn (rtx insn)
16185 if (!insn || !INSN_P (insn)
16186 || GET_CODE (PATTERN (insn)) == USE
16187 || GET_CODE (PATTERN (insn)) == CLOBBER)
16190 if (rs6000_sched_groups)
16192 enum attr_type type = get_attr_type (insn);
16193 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
16194 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
16195 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
16196 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
16197 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
16198 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
16199 || type == TYPE_IDIV || type == TYPE_LDIV
16200 || type == TYPE_INSERT_WORD)
16207 /* The function returns true if INSN can be issued only from
16208 the branch slot. */
16211 is_branch_slot_insn (rtx insn)
16213 if (!insn || !INSN_P (insn)
16214 || GET_CODE (PATTERN (insn)) == USE
16215 || GET_CODE (PATTERN (insn)) == CLOBBER)
16218 if (rs6000_sched_groups)
16220 enum attr_type type = get_attr_type (insn);
16221 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
16229 /* A C statement (sans semicolon) to update the integer scheduling
16230 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16231 INSN earlier, reduce the priority to execute INSN later. Do not
16232 define this macro if you do not need to adjust the scheduling
16233 priorities of insns. */
16236 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
16238 /* On machines (like the 750) which have asymmetric integer units,
16239 where one integer unit can do multiply and divides and the other
16240 can't, reduce the priority of multiply/divide so it is scheduled
16241 before other integer operations. */
16244 if (! INSN_P (insn))
16247 if (GET_CODE (PATTERN (insn)) == USE)
16250 switch (rs6000_cpu_attr) {
16252 switch (get_attr_type (insn))
16259 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
16260 priority, priority);
16261 if (priority >= 0 && priority < 0x01000000)
16268 if (is_dispatch_slot_restricted (insn)
16269 && reload_completed
16270 && current_sched_info->sched_max_insns_priority
16271 && rs6000_sched_restricted_insns_priority)
16274 /* Prioritize insns that can be dispatched only in the first
16276 if (rs6000_sched_restricted_insns_priority == 1)
16277 /* Attach highest priority to insn. This means that in
16278 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16279 precede 'priority' (critical path) considerations. */
16280 return current_sched_info->sched_max_insns_priority;
16281 else if (rs6000_sched_restricted_insns_priority == 2)
16282 /* Increase priority of insn by a minimal amount. This means that in
16283 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16284 considerations precede dispatch-slot restriction considerations. */
16285 return (priority + 1);
16291 /* Return how many instructions the machine can issue per cycle. */
16294 rs6000_issue_rate (void)
16296 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16297 if (!reload_completed)
16300 switch (rs6000_cpu_attr) {
16301 case CPU_RIOS1: /* ? */
16303 case CPU_PPC601: /* ? */
16326 /* Return how many instructions to look ahead for better insn
16330 rs6000_use_sched_lookahead (void)
16332 if (rs6000_cpu_attr == CPU_PPC8540)
16337 /* Determine is PAT refers to memory. */
16340 is_mem_ref (rtx pat)
16346 if (GET_CODE (pat) == MEM)
16349 /* Recursively process the pattern. */
16350 fmt = GET_RTX_FORMAT (GET_CODE (pat));
16352 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
16355 ret |= is_mem_ref (XEXP (pat, i));
16356 else if (fmt[i] == 'E')
16357 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
16358 ret |= is_mem_ref (XVECEXP (pat, i, j));
16364 /* Determine if PAT is a PATTERN of a load insn. */
16367 is_load_insn1 (rtx pat)
16369 if (!pat || pat == NULL_RTX)
16372 if (GET_CODE (pat) == SET)
16373 return is_mem_ref (SET_SRC (pat));
16375 if (GET_CODE (pat) == PARALLEL)
16379 for (i = 0; i < XVECLEN (pat, 0); i++)
16380 if (is_load_insn1 (XVECEXP (pat, 0, i)))
16387 /* Determine if INSN loads from memory. */
16390 is_load_insn (rtx insn)
16392 if (!insn || !INSN_P (insn))
16395 if (GET_CODE (insn) == CALL_INSN)
16398 return is_load_insn1 (PATTERN (insn));
16401 /* Determine if PAT is a PATTERN of a store insn. */
16404 is_store_insn1 (rtx pat)
16406 if (!pat || pat == NULL_RTX)
16409 if (GET_CODE (pat) == SET)
16410 return is_mem_ref (SET_DEST (pat));
16412 if (GET_CODE (pat) == PARALLEL)
16416 for (i = 0; i < XVECLEN (pat, 0); i++)
16417 if (is_store_insn1 (XVECEXP (pat, 0, i)))
16424 /* Determine if INSN stores to memory. */
16427 is_store_insn (rtx insn)
16429 if (!insn || !INSN_P (insn))
16432 return is_store_insn1 (PATTERN (insn));
16435 /* Returns whether the dependence between INSN and NEXT is considered
16436 costly by the given target. */
16439 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
16442 /* If the flag is not enbled - no dependence is considered costly;
16443 allow all dependent insns in the same group.
16444 This is the most aggressive option. */
16445 if (rs6000_sched_costly_dep == no_dep_costly)
16448 /* If the flag is set to 1 - a dependence is always considered costly;
16449 do not allow dependent instructions in the same group.
16450 This is the most conservative option. */
16451 if (rs6000_sched_costly_dep == all_deps_costly)
16454 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16455 && is_load_insn (next)
16456 && is_store_insn (insn))
16457 /* Prevent load after store in the same group. */
16460 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16461 && is_load_insn (next)
16462 && is_store_insn (insn)
16463 && (!link || (int) REG_NOTE_KIND (link) == 0))
16464 /* Prevent load after store in the same group if it is a true
16468 /* The flag is set to X; dependences with latency >= X are considered costly,
16469 and will not be scheduled in the same group. */
16470 if (rs6000_sched_costly_dep <= max_dep_latency
16471 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16477 /* Return the next insn after INSN that is found before TAIL is reached,
16478 skipping any "non-active" insns - insns that will not actually occupy
16479 an issue slot. Return NULL_RTX if such an insn is not found. */
16482 get_next_active_insn (rtx insn, rtx tail)
16486 if (!insn || insn == tail)
16489 next_insn = NEXT_INSN (insn);
16492 && next_insn != tail
16493 && (GET_CODE(next_insn) == NOTE
16494 || GET_CODE (PATTERN (next_insn)) == USE
16495 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
16497 next_insn = NEXT_INSN (next_insn);
16500 if (!next_insn || next_insn == tail)
16506 /* Return whether the presence of INSN causes a dispatch group termination
16507 of group WHICH_GROUP.
16509 If WHICH_GROUP == current_group, this function will return true if INSN
16510 causes the termination of the current group (i.e, the dispatch group to
16511 which INSN belongs). This means that INSN will be the last insn in the
16512 group it belongs to.
16514 If WHICH_GROUP == previous_group, this function will return true if INSN
16515 causes the termination of the previous group (i.e, the dispatch group that
16516 precedes the group to which INSN belongs). This means that INSN will be
16517 the first insn in the group it belongs to). */
16520 insn_terminates_group_p (rtx insn, enum group_termination which_group)
16522 enum attr_type type;
16527 type = get_attr_type (insn);
16529 if (is_microcoded_insn (insn))
16532 if (which_group == current_group)
16534 if (is_branch_slot_insn (insn))
16538 else if (which_group == previous_group)
16540 if (is_dispatch_slot_restricted (insn))
16548 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16549 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16552 is_costly_group (rtx *group_insns, rtx next_insn)
16557 int issue_rate = rs6000_issue_rate ();
16559 for (i = 0; i < issue_rate; i++)
16561 rtx insn = group_insns[i];
16564 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
16566 rtx next = XEXP (link, 0);
16567 if (next == next_insn)
16569 cost = insn_cost (insn, link, next_insn);
16570 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
16579 /* Utility of the function redefine_groups.
16580 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16581 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16582 to keep it "far" (in a separate group) from GROUP_INSNS, following
16583 one of the following schemes, depending on the value of the flag
16584 -minsert_sched_nops = X:
16585 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16586 in order to force NEXT_INSN into a separate group.
16587 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16588 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16589 insertion (has a group just ended, how many vacant issue slots remain in the
16590 last group, and how many dispatch groups were encountered so far). */
16593 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
16594 rtx next_insn, bool *group_end, int can_issue_more,
16599 int issue_rate = rs6000_issue_rate ();
16600 bool end = *group_end;
16603 if (next_insn == NULL_RTX)
16604 return can_issue_more;
16606 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
16607 return can_issue_more;
16609 force = is_costly_group (group_insns, next_insn);
16611 return can_issue_more;
16613 if (sched_verbose > 6)
16614 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
16615 *group_count ,can_issue_more);
16617 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
16620 can_issue_more = 0;
16622 /* Since only a branch can be issued in the last issue_slot, it is
16623 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16624 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16625 in this case the last nop will start a new group and the branch
16626 will be forced to the new group. */
16627 if (can_issue_more && !is_branch_slot_insn (next_insn))
16630 while (can_issue_more > 0)
16633 emit_insn_before (nop, next_insn);
16641 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
16643 int n_nops = rs6000_sched_insert_nops;
16645 /* Nops can't be issued from the branch slot, so the effective
16646 issue_rate for nops is 'issue_rate - 1'. */
16647 if (can_issue_more == 0)
16648 can_issue_more = issue_rate;
16650 if (can_issue_more == 0)
16652 can_issue_more = issue_rate - 1;
16655 for (i = 0; i < issue_rate; i++)
16657 group_insns[i] = 0;
16664 emit_insn_before (nop, next_insn);
16665 if (can_issue_more == issue_rate - 1) /* new group begins */
16668 if (can_issue_more == 0)
16670 can_issue_more = issue_rate - 1;
16673 for (i = 0; i < issue_rate; i++)
16675 group_insns[i] = 0;
16681 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
16684 /* Is next_insn going to start a new group? */
16687 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16688 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16689 || (can_issue_more < issue_rate &&
16690 insn_terminates_group_p (next_insn, previous_group)));
16691 if (*group_end && end)
16694 if (sched_verbose > 6)
16695 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
16696 *group_count, can_issue_more);
16697 return can_issue_more;
16700 return can_issue_more;
16703 /* This function tries to synch the dispatch groups that the compiler "sees"
16704 with the dispatch groups that the processor dispatcher is expected to
16705 form in practice. It tries to achieve this synchronization by forcing the
16706 estimated processor grouping on the compiler (as opposed to the function
16707 'pad_goups' which tries to force the scheduler's grouping on the processor).
16709 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
16710 examines the (estimated) dispatch groups that will be formed by the processor
16711 dispatcher. It marks these group boundaries to reflect the estimated
16712 processor grouping, overriding the grouping that the scheduler had marked.
16713 Depending on the value of the flag '-minsert-sched-nops' this function can
16714 force certain insns into separate groups or force a certain distance between
16715 them by inserting nops, for example, if there exists a "costly dependence"
16718 The function estimates the group boundaries that the processor will form as
16719 folllows: It keeps track of how many vacant issue slots are available after
16720 each insn. A subsequent insn will start a new group if one of the following
16722 - no more vacant issue slots remain in the current dispatch group.
16723 - only the last issue slot, which is the branch slot, is vacant, but the next
16724 insn is not a branch.
16725 - only the last 2 or less issue slots, including the branch slot, are vacant,
16726 which means that a cracked insn (which occupies two issue slots) can't be
16727 issued in this group.
16728 - less than 'issue_rate' slots are vacant, and the next insn always needs to
16729 start a new group. */
16732 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16734 rtx insn, next_insn;
16736 int can_issue_more;
16739 int group_count = 0;
16743 issue_rate = rs6000_issue_rate ();
16744 group_insns = alloca (issue_rate * sizeof (rtx));
16745 for (i = 0; i < issue_rate; i++)
16747 group_insns[i] = 0;
16749 can_issue_more = issue_rate;
16751 insn = get_next_active_insn (prev_head_insn, tail);
16754 while (insn != NULL_RTX)
16756 slot = (issue_rate - can_issue_more);
16757 group_insns[slot] = insn;
16759 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16760 if (insn_terminates_group_p (insn, current_group))
16761 can_issue_more = 0;
16763 next_insn = get_next_active_insn (insn, tail);
16764 if (next_insn == NULL_RTX)
16765 return group_count + 1;
16767 /* Is next_insn going to start a new group? */
16769 = (can_issue_more == 0
16770 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16771 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16772 || (can_issue_more < issue_rate &&
16773 insn_terminates_group_p (next_insn, previous_group)));
16775 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
16776 next_insn, &group_end, can_issue_more,
16782 can_issue_more = 0;
16783 for (i = 0; i < issue_rate; i++)
16785 group_insns[i] = 0;
16789 if (GET_MODE (next_insn) == TImode && can_issue_more)
16790 PUT_MODE(next_insn, VOIDmode);
16791 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
16792 PUT_MODE (next_insn, TImode);
16795 if (can_issue_more == 0)
16796 can_issue_more = issue_rate;
16799 return group_count;
16802 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
16803 dispatch group boundaries that the scheduler had marked. Pad with nops
16804 any dispatch groups which have vacant issue slots, in order to force the
16805 scheduler's grouping on the processor dispatcher. The function
16806 returns the number of dispatch groups found. */
16809 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16811 rtx insn, next_insn;
16814 int can_issue_more;
16816 int group_count = 0;
16818 /* Initialize issue_rate. */
16819 issue_rate = rs6000_issue_rate ();
16820 can_issue_more = issue_rate;
16822 insn = get_next_active_insn (prev_head_insn, tail);
16823 next_insn = get_next_active_insn (insn, tail);
16825 while (insn != NULL_RTX)
16828 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16830 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
16832 if (next_insn == NULL_RTX)
16837 /* If the scheduler had marked group termination at this location
16838 (between insn and next_indn), and neither insn nor next_insn will
16839 force group termination, pad the group with nops to force group
16842 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
16843 && !insn_terminates_group_p (insn, current_group)
16844 && !insn_terminates_group_p (next_insn, previous_group))
16846 if (!is_branch_slot_insn(next_insn))
16849 while (can_issue_more)
16852 emit_insn_before (nop, next_insn);
16857 can_issue_more = issue_rate;
16862 next_insn = get_next_active_insn (insn, tail);
16865 return group_count;
16868 /* The following function is called at the end of scheduling BB.
16869 After reload, it inserts nops at insn group bundling. */
16872 rs6000_sched_finish (FILE *dump, int sched_verbose)
16877 fprintf (dump, "=== Finishing schedule.\n");
16879 if (reload_completed && rs6000_sched_groups)
16881 if (rs6000_sched_insert_nops == sched_finish_none)
16884 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
16885 n_groups = pad_groups (dump, sched_verbose,
16886 current_sched_info->prev_head,
16887 current_sched_info->next_tail);
16889 n_groups = redefine_groups (dump, sched_verbose,
16890 current_sched_info->prev_head,
16891 current_sched_info->next_tail);
16893 if (sched_verbose >= 6)
16895 fprintf (dump, "ngroups = %d\n", n_groups);
16896 print_rtl (dump, current_sched_info->prev_head);
16897 fprintf (dump, "Done finish_sched\n");
16902 /* Length in units of the trampoline for entering a nested function. */
16905 rs6000_trampoline_size (void)
16909 switch (DEFAULT_ABI)
16915 ret = (TARGET_32BIT) ? 12 : 24;
16920 ret = (TARGET_32BIT) ? 40 : 48;
16927 /* Emit RTL insns to initialize the variable parts of a trampoline.
16928 FNADDR is an RTX for the address of the function's pure code.
16929 CXT is an RTX for the static chain value for the function. */
16932 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
16934 enum machine_mode pmode = Pmode;
16935 int regsize = (TARGET_32BIT) ? 4 : 8;
16936 rtx ctx_reg = force_reg (pmode, cxt);
16938 switch (DEFAULT_ABI)
16943 /* Macros to shorten the code expansions below. */
16944 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
16945 #define MEM_PLUS(addr,offset) \
16946 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
16948 /* Under AIX, just build the 3 word function descriptor */
16951 rtx fn_reg = gen_reg_rtx (pmode);
16952 rtx toc_reg = gen_reg_rtx (pmode);
16953 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
16954 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
16955 emit_move_insn (MEM_DEREF (addr), fn_reg);
16956 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
16957 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
16961 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
16964 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
16965 FALSE, VOIDmode, 4,
16967 GEN_INT (rs6000_trampoline_size ()), SImode,
16977 /* Table of valid machine attributes. */
16979 const struct attribute_spec rs6000_attribute_table[] =
16981 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
16982 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
16983 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
16984 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
16985 #ifdef SUBTARGET_ATTRIBUTE_TABLE
16986 SUBTARGET_ATTRIBUTE_TABLE,
16988 { NULL, 0, 0, false, false, false, NULL }
16991 /* Handle the "altivec" attribute. The attribute may have
16992 arguments as follows:
16994 __attribute__((altivec(vector__)))
16995 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
16996 __attribute__((altivec(bool__))) (always followed by 'unsigned')
16998 and may appear more than once (e.g., 'vector bool char') in a
16999 given declaration. */
17002 rs6000_handle_altivec_attribute (tree *node, tree name, tree args,
17003 int flags ATTRIBUTE_UNUSED,
17004 bool *no_add_attrs)
17006 tree type = *node, result = NULL_TREE;
17007 enum machine_mode mode;
17010 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
17011 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
17012 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
17015 while (POINTER_TYPE_P (type)
17016 || TREE_CODE (type) == FUNCTION_TYPE
17017 || TREE_CODE (type) == METHOD_TYPE
17018 || TREE_CODE (type) == ARRAY_TYPE)
17019 type = TREE_TYPE (type);
17021 mode = TYPE_MODE (type);
17023 if (rs6000_warn_altivec_long
17024 && (type == long_unsigned_type_node || type == long_integer_type_node))
17025 warning ("use of 'long' in AltiVec types is deprecated; use 'int'");
17027 switch (altivec_type)
17030 unsigned_p = TYPE_UNSIGNED (type);
17034 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
17037 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
17040 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
17042 case SFmode: result = V4SF_type_node; break;
17043 /* If the user says 'vector int bool', we may be handed the 'bool'
17044 attribute _before_ the 'vector' attribute, and so select the
17045 proper type in the 'b' case below. */
17046 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
17054 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
17055 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
17056 case QImode: case V16QImode: result = bool_V16QI_type_node;
17063 case V8HImode: result = pixel_V8HI_type_node;
17069 if (result && result != type && TYPE_READONLY (type))
17070 result = build_qualified_type (result, TYPE_QUAL_CONST);
17072 *no_add_attrs = true; /* No need to hang on to the attribute. */
17075 warning ("%qs attribute ignored", IDENTIFIER_POINTER (name));
17077 *node = reconstruct_complex_type (*node, result);
17082 /* AltiVec defines four built-in scalar types that serve as vector
17083 elements; we must teach the compiler how to mangle them. */
17085 static const char *
17086 rs6000_mangle_fundamental_type (tree type)
17088 if (type == bool_char_type_node) return "U6__boolc";
17089 if (type == bool_short_type_node) return "U6__bools";
17090 if (type == pixel_type_node) return "u7__pixel";
17091 if (type == bool_int_type_node) return "U6__booli";
17093 /* For all other types, use normal C++ mangling. */
17097 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17098 struct attribute_spec.handler. */
17101 rs6000_handle_longcall_attribute (tree *node, tree name,
17102 tree args ATTRIBUTE_UNUSED,
17103 int flags ATTRIBUTE_UNUSED,
17104 bool *no_add_attrs)
17106 if (TREE_CODE (*node) != FUNCTION_TYPE
17107 && TREE_CODE (*node) != FIELD_DECL
17108 && TREE_CODE (*node) != TYPE_DECL)
17110 warning ("%qs attribute only applies to functions",
17111 IDENTIFIER_POINTER (name));
17112 *no_add_attrs = true;
17118 /* Set longcall attributes on all functions declared when
17119 rs6000_default_long_calls is true. */
17121 rs6000_set_default_type_attributes (tree type)
17123 if (rs6000_default_long_calls
17124 && (TREE_CODE (type) == FUNCTION_TYPE
17125 || TREE_CODE (type) == METHOD_TYPE))
17126 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
17128 TYPE_ATTRIBUTES (type));
17131 /* Return a reference suitable for calling a function with the
17132 longcall attribute. */
17135 rs6000_longcall_ref (rtx call_ref)
17137 const char *call_name;
17140 if (GET_CODE (call_ref) != SYMBOL_REF)
17143 /* System V adds '.' to the internal name, so skip them. */
17144 call_name = XSTR (call_ref, 0);
17145 if (*call_name == '.')
17147 while (*call_name == '.')
17150 node = get_identifier (call_name);
17151 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
17154 return force_reg (Pmode, call_ref);
17157 #ifdef USING_ELFOS_H
17159 /* A C statement or statements to switch to the appropriate section
17160 for output of RTX in mode MODE. You can assume that RTX is some
17161 kind of constant in RTL. The argument MODE is redundant except in
17162 the case of a `const_int' rtx. Select the section by calling
17163 `text_section' or one of the alternatives for other sections.
17165 Do not define this macro if you put all constants in the read-only
17169 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
17170 unsigned HOST_WIDE_INT align)
17172 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17175 default_elf_select_rtx_section (mode, x, align);
17178 /* A C statement or statements to switch to the appropriate
17179 section for output of DECL. DECL is either a `VAR_DECL' node
17180 or a constant of some sort. RELOC indicates whether forming
17181 the initial value of DECL requires link-time relocations. */
17184 rs6000_elf_select_section (tree decl, int reloc,
17185 unsigned HOST_WIDE_INT align)
17187 /* Pretend that we're always building for a shared library when
17188 ABI_AIX, because otherwise we end up with dynamic relocations
17189 in read-only sections. This happens for function pointers,
17190 references to vtables in typeinfo, and probably other cases. */
17191 default_elf_select_section_1 (decl, reloc, align,
17192 flag_pic || DEFAULT_ABI == ABI_AIX);
17195 /* A C statement to build up a unique section name, expressed as a
17196 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17197 RELOC indicates whether the initial value of EXP requires
17198 link-time relocations. If you do not define this macro, GCC will use
17199 the symbol name prefixed by `.' as the section name. Note - this
17200 macro can now be called for uninitialized data items as well as
17201 initialized data and functions. */
17204 rs6000_elf_unique_section (tree decl, int reloc)
17206 /* As above, pretend that we're always building for a shared library
17207 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
17208 default_unique_section_1 (decl, reloc,
17209 flag_pic || DEFAULT_ABI == ABI_AIX);
17212 /* For a SYMBOL_REF, set generic flags and then perform some
17213 target-specific processing.
17215 When the AIX ABI is requested on a non-AIX system, replace the
17216 function name with the real name (with a leading .) rather than the
17217 function descriptor name. This saves a lot of overriding code to
17218 read the prefixes. */
17221 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
17223 default_encode_section_info (decl, rtl, first);
17226 && TREE_CODE (decl) == FUNCTION_DECL
17228 && DEFAULT_ABI == ABI_AIX)
17230 rtx sym_ref = XEXP (rtl, 0);
17231 size_t len = strlen (XSTR (sym_ref, 0));
17232 char *str = alloca (len + 2);
17234 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
17235 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
17240 rs6000_elf_in_small_data_p (tree decl)
17242 if (rs6000_sdata == SDATA_NONE)
17245 /* We want to merge strings, so we never consider them small data. */
17246 if (TREE_CODE (decl) == STRING_CST)
17249 /* Functions are never in the small data area. */
17250 if (TREE_CODE (decl) == FUNCTION_DECL)
17253 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
17255 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
17256 if (strcmp (section, ".sdata") == 0
17257 || strcmp (section, ".sdata2") == 0
17258 || strcmp (section, ".sbss") == 0
17259 || strcmp (section, ".sbss2") == 0
17260 || strcmp (section, ".PPC.EMB.sdata0") == 0
17261 || strcmp (section, ".PPC.EMB.sbss0") == 0)
17266 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
17269 && (unsigned HOST_WIDE_INT) size <= g_switch_value
17270 /* If it's not public, and we're not going to reference it there,
17271 there's no need to put it in the small data section. */
17272 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
17279 #endif /* USING_ELFOS_H */
17282 /* Return a REG that occurs in ADDR with coefficient 1.
17283 ADDR can be effectively incremented by incrementing REG.
17285 r0 is special and we must not select it as an address
17286 register by this routine since our caller will try to
17287 increment the returned register via an "la" instruction. */
17290 find_addr_reg (rtx addr)
17292 while (GET_CODE (addr) == PLUS)
17294 if (GET_CODE (XEXP (addr, 0)) == REG
17295 && REGNO (XEXP (addr, 0)) != 0)
17296 addr = XEXP (addr, 0);
17297 else if (GET_CODE (XEXP (addr, 1)) == REG
17298 && REGNO (XEXP (addr, 1)) != 0)
17299 addr = XEXP (addr, 1);
17300 else if (CONSTANT_P (XEXP (addr, 0)))
17301 addr = XEXP (addr, 1);
17302 else if (CONSTANT_P (XEXP (addr, 1)))
17303 addr = XEXP (addr, 0);
17307 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
17313 rs6000_fatal_bad_address (rtx op)
17315 fatal_insn ("bad address", op);
17320 static tree branch_island_list = 0;
17322 /* Remember to generate a branch island for far calls to the given
17326 add_compiler_branch_island (tree label_name, tree function_name,
17329 tree branch_island = build_tree_list (function_name, label_name);
17330 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
17331 TREE_CHAIN (branch_island) = branch_island_list;
17332 branch_island_list = branch_island;
17335 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17336 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17337 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17338 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17340 /* Generate far-jump branch islands for everything on the
17341 branch_island_list. Invoked immediately after the last instruction
17342 of the epilogue has been emitted; the branch-islands must be
17343 appended to, and contiguous with, the function body. Mach-O stubs
17344 are generated in machopic_output_stub(). */
17347 macho_branch_islands (void)
17350 tree branch_island;
17352 for (branch_island = branch_island_list;
17354 branch_island = TREE_CHAIN (branch_island))
17356 const char *label =
17357 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
17359 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
17360 char name_buf[512];
17361 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17362 if (name[0] == '*' || name[0] == '&')
17363 strcpy (name_buf, name+1);
17367 strcpy (name_buf+1, name);
17369 strcpy (tmp_buf, "\n");
17370 strcat (tmp_buf, label);
17371 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17372 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17373 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17374 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17377 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
17378 strcat (tmp_buf, label);
17379 strcat (tmp_buf, "_pic\n");
17380 strcat (tmp_buf, label);
17381 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
17383 strcat (tmp_buf, "\taddis r11,r11,ha16(");
17384 strcat (tmp_buf, name_buf);
17385 strcat (tmp_buf, " - ");
17386 strcat (tmp_buf, label);
17387 strcat (tmp_buf, "_pic)\n");
17389 strcat (tmp_buf, "\tmtlr r0\n");
17391 strcat (tmp_buf, "\taddi r12,r11,lo16(");
17392 strcat (tmp_buf, name_buf);
17393 strcat (tmp_buf, " - ");
17394 strcat (tmp_buf, label);
17395 strcat (tmp_buf, "_pic)\n");
17397 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
17401 strcat (tmp_buf, ":\nlis r12,hi16(");
17402 strcat (tmp_buf, name_buf);
17403 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
17404 strcat (tmp_buf, name_buf);
17405 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
17407 output_asm_insn (tmp_buf, 0);
17408 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17409 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17410 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17411 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17414 branch_island_list = 0;
17417 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17418 already there or not. */
17421 no_previous_def (tree function_name)
17423 tree branch_island;
17424 for (branch_island = branch_island_list;
17426 branch_island = TREE_CHAIN (branch_island))
17427 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17432 /* GET_PREV_LABEL gets the label name from the previous definition of
17436 get_prev_label (tree function_name)
17438 tree branch_island;
17439 for (branch_island = branch_island_list;
17441 branch_island = TREE_CHAIN (branch_island))
17442 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17443 return BRANCH_ISLAND_LABEL_NAME (branch_island);
17447 /* INSN is either a function call or a millicode call. It may have an
17448 unconditional jump in its delay slot.
17450 CALL_DEST is the routine we are calling. */
17453 output_call (rtx insn, rtx *operands, int dest_operand_number,
17454 int cookie_operand_number)
17456 static char buf[256];
17457 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
17458 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
17461 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
17463 if (no_previous_def (funname))
17465 int line_number = 0;
17466 rtx label_rtx = gen_label_rtx ();
17467 char *label_buf, temp_buf[256];
17468 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
17469 CODE_LABEL_NUMBER (label_rtx));
17470 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
17471 labelname = get_identifier (label_buf);
17472 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
17474 line_number = NOTE_LINE_NUMBER (insn);
17475 add_compiler_branch_island (labelname, funname, line_number);
17478 labelname = get_prev_label (funname);
17480 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17481 instruction will reach 'foo', otherwise link as 'bl L42'".
17482 "L42" should be a 'branch island', that will do a far jump to
17483 'foo'. Branch islands are generated in
17484 macho_branch_islands(). */
17485 sprintf (buf, "jbsr %%z%d,%.246s",
17486 dest_operand_number, IDENTIFIER_POINTER (labelname));
17489 sprintf (buf, "bl %%z%d", dest_operand_number);
17493 /* Generate PIC and indirect symbol stubs. */
17496 machopic_output_stub (FILE *file, const char *symb, const char *stub)
17498 unsigned int length;
17499 char *symbol_name, *lazy_ptr_name;
17500 char *local_label_0;
17501 static int label = 0;
17503 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17504 symb = (*targetm.strip_name_encoding) (symb);
17507 length = strlen (symb);
17508 symbol_name = alloca (length + 32);
17509 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17511 lazy_ptr_name = alloca (length + 32);
17512 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
17515 machopic_picsymbol_stub1_section ();
17517 machopic_symbol_stub1_section ();
17521 fprintf (file, "\t.align 5\n");
17523 fprintf (file, "%s:\n", stub);
17524 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17527 local_label_0 = alloca (sizeof("\"L0000000000$spb\""));
17528 sprintf (local_label_0, "\"L%011d$spb\"", label);
17530 fprintf (file, "\tmflr r0\n");
17531 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
17532 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
17533 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
17534 lazy_ptr_name, local_label_0);
17535 fprintf (file, "\tmtlr r0\n");
17536 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
17537 (TARGET_64BIT ? "ldu" : "lwzu"),
17538 lazy_ptr_name, local_label_0);
17539 fprintf (file, "\tmtctr r12\n");
17540 fprintf (file, "\tbctr\n");
17544 fprintf (file, "\t.align 4\n");
17546 fprintf (file, "%s:\n", stub);
17547 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17549 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
17550 fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name);
17551 fprintf (file, "\tmtctr r12\n");
17552 fprintf (file, "\tbctr\n");
17555 machopic_lazy_symbol_ptr_section ();
17556 fprintf (file, "%s:\n", lazy_ptr_name);
17557 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17558 fprintf (file, "%sdyld_stub_binding_helper\n",
17559 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
17562 /* Legitimize PIC addresses. If the address is already
17563 position-independent, we return ORIG. Newly generated
17564 position-independent addresses go into a reg. This is REG if non
17565 zero, otherwise we allocate register(s) as necessary. */
17567 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
17570 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
17575 if (reg == NULL && ! reload_in_progress && ! reload_completed)
17576 reg = gen_reg_rtx (Pmode);
17578 if (GET_CODE (orig) == CONST)
17580 if (GET_CODE (XEXP (orig, 0)) == PLUS
17581 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
17584 if (GET_CODE (XEXP (orig, 0)) == PLUS)
17586 /* Use a different reg for the intermediate value, as
17587 it will be marked UNCHANGING. */
17588 rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
17591 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
17594 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
17600 if (GET_CODE (offset) == CONST_INT)
17602 if (SMALL_INT (offset))
17603 return plus_constant (base, INTVAL (offset));
17604 else if (! reload_in_progress && ! reload_completed)
17605 offset = force_reg (Pmode, offset);
17608 rtx mem = force_const_mem (Pmode, orig);
17609 return machopic_legitimize_pic_address (mem, Pmode, reg);
17612 return gen_rtx_PLUS (Pmode, base, offset);
17615 /* Fall back on generic machopic code. */
17616 return machopic_legitimize_pic_address (orig, mode, reg);
17619 /* This is just a placeholder to make linking work without having to
17620 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
17621 ever needed for Darwin (not too likely!) this would have to get a
17622 real definition. */
17629 /* Output a .machine directive for the Darwin assembler, and call
17630 the generic start_file routine. */
17633 rs6000_darwin_file_start (void)
17635 static const struct
17641 { "ppc64", "ppc64", MASK_64BIT },
17642 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
17643 { "power4", "ppc970", 0 },
17644 { "G5", "ppc970", 0 },
17645 { "7450", "ppc7450", 0 },
17646 { "7400", "ppc7400", MASK_ALTIVEC },
17647 { "G4", "ppc7400", 0 },
17648 { "750", "ppc750", 0 },
17649 { "740", "ppc750", 0 },
17650 { "G3", "ppc750", 0 },
17651 { "604e", "ppc604e", 0 },
17652 { "604", "ppc604", 0 },
17653 { "603e", "ppc603", 0 },
17654 { "603", "ppc603", 0 },
17655 { "601", "ppc601", 0 },
17656 { NULL, "ppc", 0 } };
17657 const char *cpu_id = "";
17660 rs6000_file_start();
17662 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
17663 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
17664 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
17665 && rs6000_select[i].string[0] != '\0')
17666 cpu_id = rs6000_select[i].string;
17668 /* Look through the mapping array. Pick the first name that either
17669 matches the argument, has a bit set in IF_SET that is also set
17670 in the target flags, or has a NULL name. */
17673 while (mapping[i].arg != NULL
17674 && strcmp (mapping[i].arg, cpu_id) != 0
17675 && (mapping[i].if_set & target_flags) == 0)
17678 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
17681 #endif /* TARGET_MACHO */
17684 static unsigned int
17685 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
17687 return default_section_type_flags_1 (decl, name, reloc,
17688 flag_pic || DEFAULT_ABI == ABI_AIX);
17691 /* Record an element in the table of global constructors. SYMBOL is
17692 a SYMBOL_REF of the function to be called; PRIORITY is a number
17693 between 0 and MAX_INIT_PRIORITY.
17695 This differs from default_named_section_asm_out_constructor in
17696 that we have special handling for -mrelocatable. */
17699 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
17701 const char *section = ".ctors";
17704 if (priority != DEFAULT_INIT_PRIORITY)
17706 sprintf (buf, ".ctors.%.5u",
17707 /* Invert the numbering so the linker puts us in the proper
17708 order; constructors are run from right to left, and the
17709 linker sorts in increasing order. */
17710 MAX_INIT_PRIORITY - priority);
17714 named_section_flags (section, SECTION_WRITE);
17715 assemble_align (POINTER_SIZE);
17717 if (TARGET_RELOCATABLE)
17719 fputs ("\t.long (", asm_out_file);
17720 output_addr_const (asm_out_file, symbol);
17721 fputs (")@fixup\n", asm_out_file);
17724 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17728 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
17730 const char *section = ".dtors";
17733 if (priority != DEFAULT_INIT_PRIORITY)
17735 sprintf (buf, ".dtors.%.5u",
17736 /* Invert the numbering so the linker puts us in the proper
17737 order; constructors are run from right to left, and the
17738 linker sorts in increasing order. */
17739 MAX_INIT_PRIORITY - priority);
17743 named_section_flags (section, SECTION_WRITE);
17744 assemble_align (POINTER_SIZE);
17746 if (TARGET_RELOCATABLE)
17748 fputs ("\t.long (", asm_out_file);
17749 output_addr_const (asm_out_file, symbol);
17750 fputs (")@fixup\n", asm_out_file);
17753 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17757 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
17761 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
17762 ASM_OUTPUT_LABEL (file, name);
17763 fputs (DOUBLE_INT_ASM_OP, file);
17764 rs6000_output_function_entry (file, name);
17765 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
17768 fputs ("\t.size\t", file);
17769 assemble_name (file, name);
17770 fputs (",24\n\t.type\t.", file);
17771 assemble_name (file, name);
17772 fputs (",@function\n", file);
17773 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
17775 fputs ("\t.globl\t.", file);
17776 assemble_name (file, name);
17781 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17782 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17783 rs6000_output_function_entry (file, name);
17784 fputs (":\n", file);
17788 if (TARGET_RELOCATABLE
17789 && (get_pool_size () != 0 || current_function_profile)
17794 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
17796 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
17797 fprintf (file, "\t.long ");
17798 assemble_name (file, buf);
17800 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
17801 assemble_name (file, buf);
17805 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17806 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17808 if (DEFAULT_ABI == ABI_AIX)
17810 const char *desc_name, *orig_name;
17812 orig_name = (*targetm.strip_name_encoding) (name);
17813 desc_name = orig_name;
17814 while (*desc_name == '.')
17817 if (TREE_PUBLIC (decl))
17818 fprintf (file, "\t.globl %s\n", desc_name);
17820 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17821 fprintf (file, "%s:\n", desc_name);
17822 fprintf (file, "\t.long %s\n", orig_name);
17823 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
17824 if (DEFAULT_ABI == ABI_AIX)
17825 fputs ("\t.long 0\n", file);
17826 fprintf (file, "\t.previous\n");
17828 ASM_OUTPUT_LABEL (file, name);
17834 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
17836 fputs (GLOBAL_ASM_OP, stream);
17837 RS6000_OUTPUT_BASENAME (stream, name);
17838 putc ('\n', stream);
17842 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
17843 tree decl ATTRIBUTE_UNUSED)
17846 static const char * const suffix[3] = { "PR", "RO", "RW" };
17848 if (flags & SECTION_CODE)
17850 else if (flags & SECTION_WRITE)
17855 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
17856 (flags & SECTION_CODE) ? "." : "",
17857 name, suffix[smclass], flags & SECTION_ENTSIZE);
17861 rs6000_xcoff_select_section (tree decl, int reloc,
17862 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
17864 if (decl_readonly_section_1 (decl, reloc, 1))
17866 if (TREE_PUBLIC (decl))
17867 read_only_data_section ();
17869 read_only_private_data_section ();
17873 if (TREE_PUBLIC (decl))
17876 private_data_section ();
17881 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
17885 /* Use select_section for private and uninitialized data. */
17886 if (!TREE_PUBLIC (decl)
17887 || DECL_COMMON (decl)
17888 || DECL_INITIAL (decl) == NULL_TREE
17889 || DECL_INITIAL (decl) == error_mark_node
17890 || (flag_zero_initialized_in_bss
17891 && initializer_zerop (DECL_INITIAL (decl))))
17894 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
17895 name = (*targetm.strip_name_encoding) (name);
17896 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
17899 /* Select section for constant in constant pool.
17901 On RS/6000, all constants are in the private read-only data area.
17902 However, if this is being placed in the TOC it must be output as a
17906 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
17907 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
17909 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17912 read_only_private_data_section ();
17915 /* Remove any trailing [DS] or the like from the symbol name. */
17917 static const char *
17918 rs6000_xcoff_strip_name_encoding (const char *name)
17923 len = strlen (name);
17924 if (name[len - 1] == ']')
17925 return ggc_alloc_string (name, len - 4);
17930 /* Section attributes. AIX is always PIC. */
17932 static unsigned int
17933 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
17935 unsigned int align;
17936 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
17938 /* Align to at least UNIT size. */
17939 if (flags & SECTION_CODE)
17940 align = MIN_UNITS_PER_WORD;
17942 /* Increase alignment of large objects if not already stricter. */
17943 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
17944 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
17945 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
17947 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
17950 /* Output at beginning of assembler file.
17952 Initialize the section names for the RS/6000 at this point.
17954 Specify filename, including full path, to assembler.
17956 We want to go into the TOC section so at least one .toc will be emitted.
17957 Also, in order to output proper .bs/.es pairs, we need at least one static
17958 [RW] section emitted.
17960 Finally, declare mcount when profiling to make the assembler happy. */
17963 rs6000_xcoff_file_start (void)
17965 rs6000_gen_section_name (&xcoff_bss_section_name,
17966 main_input_filename, ".bss_");
17967 rs6000_gen_section_name (&xcoff_private_data_section_name,
17968 main_input_filename, ".rw_");
17969 rs6000_gen_section_name (&xcoff_read_only_section_name,
17970 main_input_filename, ".ro_");
17972 fputs ("\t.file\t", asm_out_file);
17973 output_quoted_string (asm_out_file, main_input_filename);
17974 fputc ('\n', asm_out_file);
17976 if (write_symbols != NO_DEBUG)
17977 private_data_section ();
17980 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
17981 rs6000_file_start ();
17984 /* Output at end of assembler file.
17985 On the RS/6000, referencing data should automatically pull in text. */
17988 rs6000_xcoff_file_end (void)
17991 fputs ("_section_.text:\n", asm_out_file);
17993 fputs (TARGET_32BIT
17994 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
17997 #endif /* TARGET_XCOFF */
18000 /* Cross-module name binding. Darwin does not support overriding
18001 functions at dynamic-link time. */
18004 rs6000_binds_local_p (tree decl)
18006 return default_binds_local_p_1 (decl, 0);
18010 /* Compute a (partial) cost for rtx X. Return true if the complete
18011 cost has been computed, and false if subexpressions should be
18012 scanned. In either case, *TOTAL contains the cost result. */
18015 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
18017 enum machine_mode mode = GET_MODE (x);
18021 /* On the RS/6000, if it is valid in the insn, it is free. */
18023 if (((outer_code == SET
18024 || outer_code == PLUS
18025 || outer_code == MINUS)
18026 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18027 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
18028 || (outer_code == AND
18029 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18030 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18031 mode == SImode ? 'L' : 'J'))
18032 || mask_operand (x, VOIDmode)))
18033 || ((outer_code == IOR || outer_code == XOR)
18034 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18035 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18036 mode == SImode ? 'L' : 'J'))))
18037 || outer_code == ASHIFT
18038 || outer_code == ASHIFTRT
18039 || outer_code == LSHIFTRT
18040 || outer_code == ROTATE
18041 || outer_code == ROTATERT
18042 || outer_code == ZERO_EXTRACT
18043 || (outer_code == MULT
18044 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18045 || ((outer_code == DIV || outer_code == UDIV
18046 || outer_code == MOD || outer_code == UMOD)
18047 && exact_log2 (INTVAL (x)) >= 0)
18048 || (outer_code == COMPARE
18049 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18050 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
18051 || (outer_code == EQ
18052 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18053 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18054 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18055 mode == SImode ? 'L' : 'J'))))
18056 || (outer_code == GTU
18057 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18058 || (outer_code == LTU
18059 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
18064 else if ((outer_code == PLUS
18065 && reg_or_add_cint64_operand (x, VOIDmode))
18066 || (outer_code == MINUS
18067 && reg_or_sub_cint64_operand (x, VOIDmode))
18068 || ((outer_code == SET
18069 || outer_code == IOR
18070 || outer_code == XOR)
18072 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
18074 *total = COSTS_N_INSNS (1);
18081 && ((outer_code == AND
18082 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18083 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
18084 || mask64_operand (x, DImode)))
18085 || ((outer_code == IOR || outer_code == XOR)
18086 && CONST_DOUBLE_HIGH (x) == 0
18087 && (CONST_DOUBLE_LOW (x)
18088 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
18093 else if (mode == DImode
18094 && (outer_code == SET
18095 || outer_code == IOR
18096 || outer_code == XOR)
18097 && CONST_DOUBLE_HIGH (x) == 0)
18099 *total = COSTS_N_INSNS (1);
18108 /* When optimizing for size, MEM should be slightly more expensive
18109 than generating address, e.g., (plus (reg) (const)).
18110 L1 cache latency is about two instructions. */
18111 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18119 if (mode == DFmode)
18121 if (GET_CODE (XEXP (x, 0)) == MULT)
18123 /* FNMA accounted in outer NEG. */
18124 if (outer_code == NEG)
18125 *total = rs6000_cost->dmul - rs6000_cost->fp;
18127 *total = rs6000_cost->dmul;
18130 *total = rs6000_cost->fp;
18132 else if (mode == SFmode)
18134 /* FNMA accounted in outer NEG. */
18135 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18138 *total = rs6000_cost->fp;
18140 else if (GET_CODE (XEXP (x, 0)) == MULT)
18142 /* The rs6000 doesn't have shift-and-add instructions. */
18143 rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total);
18144 *total += COSTS_N_INSNS (1);
18147 *total = COSTS_N_INSNS (1);
18151 if (mode == DFmode)
18153 if (GET_CODE (XEXP (x, 0)) == MULT)
18155 /* FNMA accounted in outer NEG. */
18156 if (outer_code == NEG)
18159 *total = rs6000_cost->dmul;
18162 *total = rs6000_cost->fp;
18164 else if (mode == SFmode)
18166 /* FNMA accounted in outer NEG. */
18167 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18170 *total = rs6000_cost->fp;
18172 else if (GET_CODE (XEXP (x, 0)) == MULT)
18174 /* The rs6000 doesn't have shift-and-sub instructions. */
18175 rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total);
18176 *total += COSTS_N_INSNS (1);
18179 *total = COSTS_N_INSNS (1);
18183 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18184 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
18186 if (INTVAL (XEXP (x, 1)) >= -256
18187 && INTVAL (XEXP (x, 1)) <= 255)
18188 *total = rs6000_cost->mulsi_const9;
18190 *total = rs6000_cost->mulsi_const;
18192 /* FMA accounted in outer PLUS/MINUS. */
18193 else if ((mode == DFmode || mode == SFmode)
18194 && (outer_code == PLUS || outer_code == MINUS))
18196 else if (mode == DFmode)
18197 *total = rs6000_cost->dmul;
18198 else if (mode == SFmode)
18199 *total = rs6000_cost->fp;
18200 else if (mode == DImode)
18201 *total = rs6000_cost->muldi;
18203 *total = rs6000_cost->mulsi;
18208 if (FLOAT_MODE_P (mode))
18210 *total = mode == DFmode ? rs6000_cost->ddiv
18211 : rs6000_cost->sdiv;
18218 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18219 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
18221 if (code == DIV || code == MOD)
18223 *total = COSTS_N_INSNS (2);
18226 *total = COSTS_N_INSNS (1);
18230 if (GET_MODE (XEXP (x, 1)) == DImode)
18231 *total = rs6000_cost->divdi;
18233 *total = rs6000_cost->divsi;
18235 /* Add in shift and subtract for MOD. */
18236 if (code == MOD || code == UMOD)
18237 *total += COSTS_N_INSNS (2);
18241 *total = COSTS_N_INSNS (4);
18245 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
18256 *total = COSTS_N_INSNS (1);
18264 /* Handle mul_highpart. */
18265 if (outer_code == TRUNCATE
18266 && GET_CODE (XEXP (x, 0)) == MULT)
18268 if (mode == DImode)
18269 *total = rs6000_cost->muldi;
18271 *total = rs6000_cost->mulsi;
18274 else if (outer_code == AND)
18277 *total = COSTS_N_INSNS (1);
18282 if (GET_CODE (XEXP (x, 0)) == MEM)
18285 *total = COSTS_N_INSNS (1);
18291 if (!FLOAT_MODE_P (mode))
18293 *total = COSTS_N_INSNS (1);
18299 case UNSIGNED_FLOAT:
18303 case FLOAT_TRUNCATE:
18304 *total = rs6000_cost->fp;
18308 switch (XINT (x, 1))
18311 *total = rs6000_cost->fp;
18323 *total = COSTS_N_INSNS (1);
18326 else if (FLOAT_MODE_P (mode)
18327 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
18329 *total = rs6000_cost->fp;
18337 /* Carry bit requires mode == Pmode.
18338 NEG or PLUS already counted so only add one. */
18340 && (outer_code == NEG || outer_code == PLUS))
18342 *total = COSTS_N_INSNS (1);
18345 if (outer_code == SET)
18347 if (XEXP (x, 1) == const0_rtx)
18349 *total = COSTS_N_INSNS (2);
18352 else if (mode == Pmode)
18354 *total = COSTS_N_INSNS (3);
18363 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
18365 *total = COSTS_N_INSNS (2);
18369 if (outer_code == COMPARE)
18383 /* A C expression returning the cost of moving data from a register of class
18384 CLASS1 to one of CLASS2. */
18387 rs6000_register_move_cost (enum machine_mode mode,
18388 enum reg_class from, enum reg_class to)
18390 /* Moves from/to GENERAL_REGS. */
18391 if (reg_classes_intersect_p (to, GENERAL_REGS)
18392 || reg_classes_intersect_p (from, GENERAL_REGS))
18394 if (! reg_classes_intersect_p (to, GENERAL_REGS))
18397 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
18398 return (rs6000_memory_move_cost (mode, from, 0)
18399 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
18401 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18403 else if (from == CR_REGS)
18407 /* A move will cost one instruction per GPR moved. */
18408 return 2 * HARD_REGNO_NREGS (0, mode);
18411 /* Moving between two similar registers is just one instruction. */
18412 else if (reg_classes_intersect_p (to, from))
18413 return mode == TFmode ? 4 : 2;
18415 /* Everything else has to go through GENERAL_REGS. */
18417 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
18418 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
18421 /* A C expressions returning the cost of moving data of MODE from a register to
18425 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
18426 int in ATTRIBUTE_UNUSED)
18428 if (reg_classes_intersect_p (class, GENERAL_REGS))
18429 return 4 * HARD_REGNO_NREGS (0, mode);
18430 else if (reg_classes_intersect_p (class, FLOAT_REGS))
18431 return 4 * HARD_REGNO_NREGS (32, mode);
18432 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
18433 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
18435 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
18438 /* Return an RTX representing where to find the function value of a
18439 function returning MODE. */
18441 rs6000_complex_function_value (enum machine_mode mode)
18443 unsigned int regno;
18445 enum machine_mode inner = GET_MODE_INNER (mode);
18446 unsigned int inner_bytes = GET_MODE_SIZE (inner);
18448 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
18449 regno = FP_ARG_RETURN;
18452 regno = GP_ARG_RETURN;
18454 /* 32-bit is OK since it'll go in r3/r4. */
18455 if (TARGET_32BIT && inner_bytes >= 4)
18456 return gen_rtx_REG (mode, regno);
18459 if (inner_bytes >= 8)
18460 return gen_rtx_REG (mode, regno);
18462 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
18464 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
18465 GEN_INT (inner_bytes));
18466 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
18469 /* Compose a PARALLEL for a darwin64 struct being returned by
18473 rs6000_darwin64_function_value (CUMULATIVE_ARGS *cum, tree valtype)
18476 rtx rvec[FIRST_PSEUDO_REGISTER], sub, roffset, suboff;
18477 int k = 0, bytepos, tot, elt, i, subbytepos;
18478 enum machine_mode fmode;
18480 switch (TREE_CODE (valtype))
18483 for (f = TYPE_FIELDS (valtype); f ; f = TREE_CHAIN (f))
18484 if (TREE_CODE (f) == FIELD_DECL)
18486 ftype = TREE_TYPE (f);
18487 fmode = TYPE_MODE (ftype);
18488 bytepos = int_bit_position (f) / BITS_PER_UNIT;
18489 if (USE_FP_FOR_ARG_P (cum, fmode, ftype))
18491 sub = gen_rtx_REG (fmode, cum->fregno++);
18492 cum->sysv_gregno++;
18494 else if (USE_ALTIVEC_FOR_ARG_P (cum, fmode, ftype, 1))
18496 sub = gen_rtx_REG (fmode, cum->vregno++);
18497 cum->sysv_gregno++;
18499 else if (fmode == BLKmode
18500 && (TREE_CODE (ftype) == RECORD_TYPE
18501 || TREE_CODE (ftype) == ARRAY_TYPE))
18502 sub = rs6000_darwin64_function_value (cum, ftype);
18504 sub = gen_rtx_REG (fmode, cum->sysv_gregno++);
18505 if (sub == NULL_RTX)
18507 else if (GET_CODE (sub) == PARALLEL)
18509 for (i = 0; i < XVECLEN (sub, 0); i++)
18511 rtx subsub = XVECEXP (sub, 0, i);
18513 suboff = XEXP (subsub, 1);
18514 subbytepos = INTVAL (suboff);
18515 subbytepos += bytepos;
18516 roffset = gen_rtx_CONST_INT (SImode, subbytepos);
18517 subsub = XEXP (subsub, 0);
18518 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset);
18523 roffset = gen_rtx_CONST_INT (SImode, bytepos);
18524 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
18528 return gen_rtx_PARALLEL (TYPE_MODE (valtype), gen_rtvec_v (k, rvec));
18533 /* If passing by value won't work, give up. */
18534 if (int_size_in_bytes (valtype) <= 0)
18536 ftype = TREE_TYPE (valtype);
18537 fmode = TYPE_MODE (ftype);
18538 tot = int_size_in_bytes (valtype) / int_size_in_bytes (ftype);
18540 for (elt = 0; elt < tot; ++elt)
18542 if (USE_FP_FOR_ARG_P (cum, fmode, ftype))
18544 sub = gen_rtx_REG (fmode, cum->fregno++);
18545 cum->sysv_gregno++;
18547 else if (USE_ALTIVEC_FOR_ARG_P (cum, fmode, ftype, 1))
18549 sub = gen_rtx_REG (fmode, cum->vregno++);
18550 cum->sysv_gregno++;
18552 else if (fmode == BLKmode
18553 && (TREE_CODE (ftype) == RECORD_TYPE
18554 || TREE_CODE (ftype) == ARRAY_TYPE))
18555 sub = rs6000_darwin64_function_value (cum, ftype);
18557 sub = gen_rtx_REG (fmode, cum->sysv_gregno++);
18558 if (sub == NULL_RTX)
18560 else if (GET_CODE (sub) == PARALLEL)
18562 for (i = 0; i < XVECLEN (sub, 0); i++)
18564 rtx subsub = XVECEXP (sub, 0, i);
18566 suboff = XEXP (subsub, 1);
18567 subbytepos = INTVAL (suboff);
18568 subbytepos += bytepos;
18569 roffset = gen_rtx_CONST_INT (SImode, subbytepos);
18570 subsub = XEXP (subsub, 0);
18571 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset);
18576 roffset = gen_rtx_CONST_INT (SImode, bytepos);
18577 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
18579 bytepos += int_size_in_bytes (ftype);
18582 return gen_rtx_PARALLEL (TYPE_MODE (valtype), gen_rtvec_v (k, rvec));
18591 /* Define how to find the value returned by a function.
18592 VALTYPE is the data type of the value (as a tree).
18593 If the precise function being called is known, FUNC is its FUNCTION_DECL;
18594 otherwise, FUNC is 0.
18596 On the SPE, both FPs and vectors are returned in r3.
18598 On RS/6000 an integer value is in r3 and a floating-point value is in
18599 fp1, unless -msoft-float. */
18602 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
18604 enum machine_mode mode;
18605 unsigned int regno;
18607 /* Special handling for structs in darwin64. */
18608 if (rs6000_darwin64_abi
18609 && TYPE_MODE (valtype) == BLKmode
18610 && (TREE_CODE (valtype) == RECORD_TYPE
18611 || TREE_CODE (valtype) == ARRAY_TYPE))
18613 CUMULATIVE_ARGS valcum;
18616 valcum.sysv_gregno = GP_ARG_RETURN;
18617 valcum.fregno = FP_ARG_MIN_REG;
18618 valcum.vregno = ALTIVEC_ARG_MIN_REG;
18619 valret = rs6000_darwin64_function_value (&valcum, valtype);
18622 /* Otherwise fall through to standard ABI rules. */
18625 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
18627 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18628 return gen_rtx_PARALLEL (DImode,
18630 gen_rtx_EXPR_LIST (VOIDmode,
18631 gen_rtx_REG (SImode, GP_ARG_RETURN),
18633 gen_rtx_EXPR_LIST (VOIDmode,
18634 gen_rtx_REG (SImode,
18635 GP_ARG_RETURN + 1),
18639 if ((INTEGRAL_TYPE_P (valtype)
18640 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
18641 || POINTER_TYPE_P (valtype))
18642 mode = TARGET_32BIT ? SImode : DImode;
18644 mode = TYPE_MODE (valtype);
18646 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
18647 regno = FP_ARG_RETURN;
18648 else if (TREE_CODE (valtype) == COMPLEX_TYPE
18649 && targetm.calls.split_complex_arg)
18650 return rs6000_complex_function_value (mode);
18651 else if (TREE_CODE (valtype) == VECTOR_TYPE
18652 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
18653 && ALTIVEC_VECTOR_MODE (mode))
18654 regno = ALTIVEC_ARG_RETURN;
18655 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18656 && (mode == DFmode || mode == DCmode))
18657 return spe_build_register_parallel (mode, GP_ARG_RETURN);
18659 regno = GP_ARG_RETURN;
18661 return gen_rtx_REG (mode, regno);
18664 /* Define how to find the value returned by a library function
18665 assuming the value has mode MODE. */
18667 rs6000_libcall_value (enum machine_mode mode)
18669 unsigned int regno;
18671 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
18673 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18674 return gen_rtx_PARALLEL (DImode,
18676 gen_rtx_EXPR_LIST (VOIDmode,
18677 gen_rtx_REG (SImode, GP_ARG_RETURN),
18679 gen_rtx_EXPR_LIST (VOIDmode,
18680 gen_rtx_REG (SImode,
18681 GP_ARG_RETURN + 1),
18685 if (GET_MODE_CLASS (mode) == MODE_FLOAT
18686 && TARGET_HARD_FLOAT && TARGET_FPRS)
18687 regno = FP_ARG_RETURN;
18688 else if (ALTIVEC_VECTOR_MODE (mode)
18689 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
18690 regno = ALTIVEC_ARG_RETURN;
18691 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
18692 return rs6000_complex_function_value (mode);
18693 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18694 && (mode == DFmode || mode == DCmode))
18695 return spe_build_register_parallel (mode, GP_ARG_RETURN);
18697 regno = GP_ARG_RETURN;
18699 return gen_rtx_REG (mode, regno);
18702 /* Define the offset between two registers, FROM to be eliminated and its
18703 replacement TO, at the start of a routine. */
18705 rs6000_initial_elimination_offset (int from, int to)
18707 rs6000_stack_t *info = rs6000_stack_info ();
18708 HOST_WIDE_INT offset;
18710 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18711 offset = info->push_p ? 0 : -info->total_size;
18712 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
18713 offset = info->total_size;
18714 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18715 offset = info->push_p ? info->total_size : 0;
18716 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
18724 /* Return true if TYPE is of type __ev64_opaque__. */
18727 is_ev64_opaque_type (tree type)
18730 && (type == opaque_V2SI_type_node
18731 || type == opaque_V2SF_type_node
18732 || type == opaque_p_V2SI_type_node));
18736 rs6000_dwarf_register_span (rtx reg)
18741 && (SPE_VECTOR_MODE (GET_MODE (reg))
18742 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
18747 regno = REGNO (reg);
18749 /* The duality of the SPE register size wreaks all kinds of havoc.
18750 This is a way of distinguishing r0 in 32-bits from r0 in
18753 gen_rtx_PARALLEL (VOIDmode,
18756 gen_rtx_REG (SImode, regno + 1200),
18757 gen_rtx_REG (SImode, regno))
18759 gen_rtx_REG (SImode, regno),
18760 gen_rtx_REG (SImode, regno + 1200)));
18763 /* Map internal gcc register numbers to DWARF2 register numbers. */
18766 rs6000_dbx_register_number (unsigned int regno)
18768 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
18770 if (regno == MQ_REGNO)
18772 if (regno == LINK_REGISTER_REGNUM)
18774 if (regno == COUNT_REGISTER_REGNUM)
18776 if (CR_REGNO_P (regno))
18777 return regno - CR0_REGNO + 86;
18778 if (regno == XER_REGNO)
18780 if (ALTIVEC_REGNO_P (regno))
18781 return regno - FIRST_ALTIVEC_REGNO + 1124;
18782 if (regno == VRSAVE_REGNO)
18784 if (regno == VSCR_REGNO)
18786 if (regno == SPE_ACC_REGNO)
18788 if (regno == SPEFSCR_REGNO)
18790 /* SPE high reg number. We get these values of regno from
18791 rs6000_dwarf_register_span. */
18792 if (regno >= 1200 && regno < 1232)
18798 /* target hook eh_return_filter_mode */
18799 static enum machine_mode
18800 rs6000_eh_return_filter_mode (void)
18802 return TARGET_32BIT ? SImode : word_mode;
18805 /* Target hook for vector_mode_supported_p. */
18807 rs6000_vector_mode_supported_p (enum machine_mode mode)
18810 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
18813 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
18820 #include "gt-rs6000.h"