1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
45 #include "integrate.h"
51 #include "target-def.h"
52 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
56 #include "tree-gimple.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack {
76 int first_gp_reg_save; /* first callee saved GP register used */
77 int first_fp_reg_save; /* first callee saved FP register used */
78 int first_altivec_reg_save; /* first callee saved AltiVec register used */
79 int lr_save_p; /* true if the link reg needs to be saved */
80 int cr_save_p; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask; /* mask of vec registers to save */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset; /* offset to save the varargs registers */
95 int ehrd_offset; /* offset to EH return data */
96 int reg_size; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
111 int spe_64bit_regs_used;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct machine_function GTY(())
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset;
131 /* Target cpu type */
133 enum processor_type rs6000_cpu;
134 struct rs6000_cpu_select rs6000_select[3] =
136 /* switch name, tune arch */
137 { (const char *)0, "--with-cpu=", 1, 1 },
138 { (const char *)0, "-mcpu=", 1, 1 },
139 { (const char *)0, "-mtune=", 1, 0 },
142 /* Always emit branch hint bits. */
143 static GTY(()) bool rs6000_always_hint;
145 /* Schedule instructions for group formation. */
146 static GTY(()) bool rs6000_sched_groups;
148 /* Support for -msched-costly-dep option. */
149 const char *rs6000_sched_costly_dep_str;
150 enum rs6000_dependence_cost rs6000_sched_costly_dep;
152 /* Support for -minsert-sched-nops option. */
153 const char *rs6000_sched_insert_nops_str;
154 enum rs6000_nop_insertion rs6000_sched_insert_nops;
156 /* Support targetm.vectorize.builtin_mask_for_load. */
157 static GTY(()) tree altivec_builtin_mask_for_load;
159 /* Size of long double. */
160 int rs6000_long_double_type_size;
162 /* IEEE quad extended precision long double. */
165 /* Whether -mabi=altivec has appeared. */
166 int rs6000_altivec_abi;
168 /* Nonzero if we want SPE ABI extensions. */
171 /* Nonzero if floating point operations are done in the GPRs. */
172 int rs6000_float_gprs = 0;
174 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
175 int rs6000_darwin64_abi;
177 /* Set to nonzero once AIX common-mode calls have been defined. */
178 static GTY(()) int common_mode_defined;
180 /* Save information from a "cmpxx" operation until the branch or scc is
182 rtx rs6000_compare_op0, rs6000_compare_op1;
183 int rs6000_compare_fp_p;
185 /* Label number of label created for -mrelocatable, to call to so we can
186 get the address of the GOT section */
187 int rs6000_pic_labelno;
190 /* Which abi to adhere to */
191 const char *rs6000_abi_name;
193 /* Semantics of the small data area */
194 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
196 /* Which small data model to use */
197 const char *rs6000_sdata_name = (char *)0;
199 /* Counter for labels which are to be placed in .fixup. */
200 int fixuplabelno = 0;
203 /* Bit size of immediate TLS offsets and string from which it is decoded. */
204 int rs6000_tls_size = 32;
205 const char *rs6000_tls_size_string;
207 /* ABI enumeration available for subtarget to use. */
208 enum rs6000_abi rs6000_current_abi;
210 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
214 const char *rs6000_debug_name;
215 int rs6000_debug_stack; /* debug stack applications */
216 int rs6000_debug_arg; /* debug argument handling */
218 /* Value is TRUE if register/mode pair is acceptable. */
219 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
221 /* Built in types. */
223 tree rs6000_builtin_types[RS6000_BTI_MAX];
224 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
226 const char *rs6000_traceback_name;
228 traceback_default = 0,
234 /* Flag to say the TOC is initialized */
236 char toc_label_name[10];
238 static GTY(()) section *read_only_data_section;
239 static GTY(()) section *private_data_section;
240 static GTY(()) section *read_only_private_data_section;
241 static GTY(()) section *sdata2_section;
242 static GTY(()) section *toc_section;
244 /* Control alignment for fields within structures. */
245 /* String from -malign-XXXXX. */
246 int rs6000_alignment_flags;
248 /* True for any options that were explicitly set. */
250 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
251 bool alignment; /* True if -malign- was used. */
252 bool abi; /* True if -mabi=spe/nospe was used. */
253 bool spe; /* True if -mspe= was used. */
254 bool float_gprs; /* True if -mfloat-gprs= was used. */
255 bool isel; /* True if -misel was used. */
256 bool long_double; /* True if -mlong-double- was used. */
257 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
258 } rs6000_explicit_options;
260 struct builtin_description
262 /* mask is not const because we're going to alter it below. This
263 nonsense will go away when we rewrite the -march infrastructure
264 to give us more target flag bits. */
266 const enum insn_code icode;
267 const char *const name;
268 const enum rs6000_builtins code;
271 /* Target cpu costs. */
273 struct processor_costs {
274 const int mulsi; /* cost of SImode multiplication. */
275 const int mulsi_const; /* cost of SImode multiplication by constant. */
276 const int mulsi_const9; /* cost of SImode mult by short constant. */
277 const int muldi; /* cost of DImode multiplication. */
278 const int divsi; /* cost of SImode division. */
279 const int divdi; /* cost of DImode division. */
280 const int fp; /* cost of simple SFmode and DFmode insns. */
281 const int dmul; /* cost of DFmode multiplication (and fmadd). */
282 const int sdiv; /* cost of SFmode division (fdivs). */
283 const int ddiv; /* cost of DFmode division (fdiv). */
286 const struct processor_costs *rs6000_cost;
288 /* Processor costs (relative to an add) */
290 /* Instruction size costs on 32bit processors. */
292 struct processor_costs size32_cost = {
293 COSTS_N_INSNS (1), /* mulsi */
294 COSTS_N_INSNS (1), /* mulsi_const */
295 COSTS_N_INSNS (1), /* mulsi_const9 */
296 COSTS_N_INSNS (1), /* muldi */
297 COSTS_N_INSNS (1), /* divsi */
298 COSTS_N_INSNS (1), /* divdi */
299 COSTS_N_INSNS (1), /* fp */
300 COSTS_N_INSNS (1), /* dmul */
301 COSTS_N_INSNS (1), /* sdiv */
302 COSTS_N_INSNS (1), /* ddiv */
305 /* Instruction size costs on 64bit processors. */
307 struct processor_costs size64_cost = {
308 COSTS_N_INSNS (1), /* mulsi */
309 COSTS_N_INSNS (1), /* mulsi_const */
310 COSTS_N_INSNS (1), /* mulsi_const9 */
311 COSTS_N_INSNS (1), /* muldi */
312 COSTS_N_INSNS (1), /* divsi */
313 COSTS_N_INSNS (1), /* divdi */
314 COSTS_N_INSNS (1), /* fp */
315 COSTS_N_INSNS (1), /* dmul */
316 COSTS_N_INSNS (1), /* sdiv */
317 COSTS_N_INSNS (1), /* ddiv */
320 /* Instruction costs on RIOS1 processors. */
322 struct processor_costs rios1_cost = {
323 COSTS_N_INSNS (5), /* mulsi */
324 COSTS_N_INSNS (4), /* mulsi_const */
325 COSTS_N_INSNS (3), /* mulsi_const9 */
326 COSTS_N_INSNS (5), /* muldi */
327 COSTS_N_INSNS (19), /* divsi */
328 COSTS_N_INSNS (19), /* divdi */
329 COSTS_N_INSNS (2), /* fp */
330 COSTS_N_INSNS (2), /* dmul */
331 COSTS_N_INSNS (19), /* sdiv */
332 COSTS_N_INSNS (19), /* ddiv */
335 /* Instruction costs on RIOS2 processors. */
337 struct processor_costs rios2_cost = {
338 COSTS_N_INSNS (2), /* mulsi */
339 COSTS_N_INSNS (2), /* mulsi_const */
340 COSTS_N_INSNS (2), /* mulsi_const9 */
341 COSTS_N_INSNS (2), /* muldi */
342 COSTS_N_INSNS (13), /* divsi */
343 COSTS_N_INSNS (13), /* divdi */
344 COSTS_N_INSNS (2), /* fp */
345 COSTS_N_INSNS (2), /* dmul */
346 COSTS_N_INSNS (17), /* sdiv */
347 COSTS_N_INSNS (17), /* ddiv */
350 /* Instruction costs on RS64A processors. */
352 struct processor_costs rs64a_cost = {
353 COSTS_N_INSNS (20), /* mulsi */
354 COSTS_N_INSNS (12), /* mulsi_const */
355 COSTS_N_INSNS (8), /* mulsi_const9 */
356 COSTS_N_INSNS (34), /* muldi */
357 COSTS_N_INSNS (65), /* divsi */
358 COSTS_N_INSNS (67), /* divdi */
359 COSTS_N_INSNS (4), /* fp */
360 COSTS_N_INSNS (4), /* dmul */
361 COSTS_N_INSNS (31), /* sdiv */
362 COSTS_N_INSNS (31), /* ddiv */
365 /* Instruction costs on MPCCORE processors. */
367 struct processor_costs mpccore_cost = {
368 COSTS_N_INSNS (2), /* mulsi */
369 COSTS_N_INSNS (2), /* mulsi_const */
370 COSTS_N_INSNS (2), /* mulsi_const9 */
371 COSTS_N_INSNS (2), /* muldi */
372 COSTS_N_INSNS (6), /* divsi */
373 COSTS_N_INSNS (6), /* divdi */
374 COSTS_N_INSNS (4), /* fp */
375 COSTS_N_INSNS (5), /* dmul */
376 COSTS_N_INSNS (10), /* sdiv */
377 COSTS_N_INSNS (17), /* ddiv */
380 /* Instruction costs on PPC403 processors. */
382 struct processor_costs ppc403_cost = {
383 COSTS_N_INSNS (4), /* mulsi */
384 COSTS_N_INSNS (4), /* mulsi_const */
385 COSTS_N_INSNS (4), /* mulsi_const9 */
386 COSTS_N_INSNS (4), /* muldi */
387 COSTS_N_INSNS (33), /* divsi */
388 COSTS_N_INSNS (33), /* divdi */
389 COSTS_N_INSNS (11), /* fp */
390 COSTS_N_INSNS (11), /* dmul */
391 COSTS_N_INSNS (11), /* sdiv */
392 COSTS_N_INSNS (11), /* ddiv */
395 /* Instruction costs on PPC405 processors. */
397 struct processor_costs ppc405_cost = {
398 COSTS_N_INSNS (5), /* mulsi */
399 COSTS_N_INSNS (4), /* mulsi_const */
400 COSTS_N_INSNS (3), /* mulsi_const9 */
401 COSTS_N_INSNS (5), /* muldi */
402 COSTS_N_INSNS (35), /* divsi */
403 COSTS_N_INSNS (35), /* divdi */
404 COSTS_N_INSNS (11), /* fp */
405 COSTS_N_INSNS (11), /* dmul */
406 COSTS_N_INSNS (11), /* sdiv */
407 COSTS_N_INSNS (11), /* ddiv */
410 /* Instruction costs on PPC440 processors. */
412 struct processor_costs ppc440_cost = {
413 COSTS_N_INSNS (3), /* mulsi */
414 COSTS_N_INSNS (2), /* mulsi_const */
415 COSTS_N_INSNS (2), /* mulsi_const9 */
416 COSTS_N_INSNS (3), /* muldi */
417 COSTS_N_INSNS (34), /* divsi */
418 COSTS_N_INSNS (34), /* divdi */
419 COSTS_N_INSNS (5), /* fp */
420 COSTS_N_INSNS (5), /* dmul */
421 COSTS_N_INSNS (19), /* sdiv */
422 COSTS_N_INSNS (33), /* ddiv */
425 /* Instruction costs on PPC601 processors. */
427 struct processor_costs ppc601_cost = {
428 COSTS_N_INSNS (5), /* mulsi */
429 COSTS_N_INSNS (5), /* mulsi_const */
430 COSTS_N_INSNS (5), /* mulsi_const9 */
431 COSTS_N_INSNS (5), /* muldi */
432 COSTS_N_INSNS (36), /* divsi */
433 COSTS_N_INSNS (36), /* divdi */
434 COSTS_N_INSNS (4), /* fp */
435 COSTS_N_INSNS (5), /* dmul */
436 COSTS_N_INSNS (17), /* sdiv */
437 COSTS_N_INSNS (31), /* ddiv */
440 /* Instruction costs on PPC603 processors. */
442 struct processor_costs ppc603_cost = {
443 COSTS_N_INSNS (5), /* mulsi */
444 COSTS_N_INSNS (3), /* mulsi_const */
445 COSTS_N_INSNS (2), /* mulsi_const9 */
446 COSTS_N_INSNS (5), /* muldi */
447 COSTS_N_INSNS (37), /* divsi */
448 COSTS_N_INSNS (37), /* divdi */
449 COSTS_N_INSNS (3), /* fp */
450 COSTS_N_INSNS (4), /* dmul */
451 COSTS_N_INSNS (18), /* sdiv */
452 COSTS_N_INSNS (33), /* ddiv */
455 /* Instruction costs on PPC604 processors. */
457 struct processor_costs ppc604_cost = {
458 COSTS_N_INSNS (4), /* mulsi */
459 COSTS_N_INSNS (4), /* mulsi_const */
460 COSTS_N_INSNS (4), /* mulsi_const9 */
461 COSTS_N_INSNS (4), /* muldi */
462 COSTS_N_INSNS (20), /* divsi */
463 COSTS_N_INSNS (20), /* divdi */
464 COSTS_N_INSNS (3), /* fp */
465 COSTS_N_INSNS (3), /* dmul */
466 COSTS_N_INSNS (18), /* sdiv */
467 COSTS_N_INSNS (32), /* ddiv */
470 /* Instruction costs on PPC604e processors. */
472 struct processor_costs ppc604e_cost = {
473 COSTS_N_INSNS (2), /* mulsi */
474 COSTS_N_INSNS (2), /* mulsi_const */
475 COSTS_N_INSNS (2), /* mulsi_const9 */
476 COSTS_N_INSNS (2), /* muldi */
477 COSTS_N_INSNS (20), /* divsi */
478 COSTS_N_INSNS (20), /* divdi */
479 COSTS_N_INSNS (3), /* fp */
480 COSTS_N_INSNS (3), /* dmul */
481 COSTS_N_INSNS (18), /* sdiv */
482 COSTS_N_INSNS (32), /* ddiv */
485 /* Instruction costs on PPC620 processors. */
487 struct processor_costs ppc620_cost = {
488 COSTS_N_INSNS (5), /* mulsi */
489 COSTS_N_INSNS (4), /* mulsi_const */
490 COSTS_N_INSNS (3), /* mulsi_const9 */
491 COSTS_N_INSNS (7), /* muldi */
492 COSTS_N_INSNS (21), /* divsi */
493 COSTS_N_INSNS (37), /* divdi */
494 COSTS_N_INSNS (3), /* fp */
495 COSTS_N_INSNS (3), /* dmul */
496 COSTS_N_INSNS (18), /* sdiv */
497 COSTS_N_INSNS (32), /* ddiv */
500 /* Instruction costs on PPC630 processors. */
502 struct processor_costs ppc630_cost = {
503 COSTS_N_INSNS (5), /* mulsi */
504 COSTS_N_INSNS (4), /* mulsi_const */
505 COSTS_N_INSNS (3), /* mulsi_const9 */
506 COSTS_N_INSNS (7), /* muldi */
507 COSTS_N_INSNS (21), /* divsi */
508 COSTS_N_INSNS (37), /* divdi */
509 COSTS_N_INSNS (3), /* fp */
510 COSTS_N_INSNS (3), /* dmul */
511 COSTS_N_INSNS (17), /* sdiv */
512 COSTS_N_INSNS (21), /* ddiv */
515 /* Instruction costs on PPC750 and PPC7400 processors. */
517 struct processor_costs ppc750_cost = {
518 COSTS_N_INSNS (5), /* mulsi */
519 COSTS_N_INSNS (3), /* mulsi_const */
520 COSTS_N_INSNS (2), /* mulsi_const9 */
521 COSTS_N_INSNS (5), /* muldi */
522 COSTS_N_INSNS (17), /* divsi */
523 COSTS_N_INSNS (17), /* divdi */
524 COSTS_N_INSNS (3), /* fp */
525 COSTS_N_INSNS (3), /* dmul */
526 COSTS_N_INSNS (17), /* sdiv */
527 COSTS_N_INSNS (31), /* ddiv */
530 /* Instruction costs on PPC7450 processors. */
532 struct processor_costs ppc7450_cost = {
533 COSTS_N_INSNS (4), /* mulsi */
534 COSTS_N_INSNS (3), /* mulsi_const */
535 COSTS_N_INSNS (3), /* mulsi_const9 */
536 COSTS_N_INSNS (4), /* muldi */
537 COSTS_N_INSNS (23), /* divsi */
538 COSTS_N_INSNS (23), /* divdi */
539 COSTS_N_INSNS (5), /* fp */
540 COSTS_N_INSNS (5), /* dmul */
541 COSTS_N_INSNS (21), /* sdiv */
542 COSTS_N_INSNS (35), /* ddiv */
545 /* Instruction costs on PPC8540 processors. */
547 struct processor_costs ppc8540_cost = {
548 COSTS_N_INSNS (4), /* mulsi */
549 COSTS_N_INSNS (4), /* mulsi_const */
550 COSTS_N_INSNS (4), /* mulsi_const9 */
551 COSTS_N_INSNS (4), /* muldi */
552 COSTS_N_INSNS (19), /* divsi */
553 COSTS_N_INSNS (19), /* divdi */
554 COSTS_N_INSNS (4), /* fp */
555 COSTS_N_INSNS (4), /* dmul */
556 COSTS_N_INSNS (29), /* sdiv */
557 COSTS_N_INSNS (29), /* ddiv */
560 /* Instruction costs on POWER4 and POWER5 processors. */
562 struct processor_costs power4_cost = {
563 COSTS_N_INSNS (3), /* mulsi */
564 COSTS_N_INSNS (2), /* mulsi_const */
565 COSTS_N_INSNS (2), /* mulsi_const9 */
566 COSTS_N_INSNS (4), /* muldi */
567 COSTS_N_INSNS (18), /* divsi */
568 COSTS_N_INSNS (34), /* divdi */
569 COSTS_N_INSNS (3), /* fp */
570 COSTS_N_INSNS (3), /* dmul */
571 COSTS_N_INSNS (17), /* sdiv */
572 COSTS_N_INSNS (17), /* ddiv */
576 static bool rs6000_function_ok_for_sibcall (tree, tree);
577 static const char *rs6000_invalid_within_doloop (rtx);
578 static rtx rs6000_generate_compare (enum rtx_code);
579 static void rs6000_maybe_dead (rtx);
580 static void rs6000_emit_stack_tie (void);
581 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
582 static rtx spe_synthesize_frame_save (rtx);
583 static bool spe_func_has_64bit_regs_p (void);
584 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
586 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
587 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
588 static unsigned rs6000_hash_constant (rtx);
589 static unsigned toc_hash_function (const void *);
590 static int toc_hash_eq (const void *, const void *);
591 static int constant_pool_expr_1 (rtx, int *, int *);
592 static bool constant_pool_expr_p (rtx);
593 static bool legitimate_small_data_p (enum machine_mode, rtx);
594 static bool legitimate_indexed_address_p (rtx, int);
595 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
596 static struct machine_function * rs6000_init_machine_status (void);
597 static bool rs6000_assemble_integer (rtx, unsigned int, int);
598 static bool no_global_regs_above (int);
599 #ifdef HAVE_GAS_HIDDEN
600 static void rs6000_assemble_visibility (tree, int);
602 static int rs6000_ra_ever_killed (void);
603 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
604 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
605 static bool rs6000_ms_bitfield_layout_p (tree);
606 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
607 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
608 static const char *rs6000_mangle_fundamental_type (tree);
609 extern const struct attribute_spec rs6000_attribute_table[];
610 static void rs6000_set_default_type_attributes (tree);
611 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
612 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
613 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
615 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
616 static bool rs6000_return_in_memory (tree, tree);
617 static void rs6000_file_start (void);
619 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
620 static void rs6000_elf_asm_out_constructor (rtx, int);
621 static void rs6000_elf_asm_out_destructor (rtx, int);
622 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
623 static void rs6000_elf_asm_init_sections (void);
624 static section *rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
625 static void rs6000_elf_unique_section (tree, int);
626 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
627 unsigned HOST_WIDE_INT);
628 static void rs6000_elf_encode_section_info (tree, rtx, int)
631 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, rtx);
633 static void rs6000_xcoff_asm_output_anchor (rtx);
634 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
635 static void rs6000_xcoff_asm_init_sections (void);
636 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
637 static section *rs6000_xcoff_select_section (tree, int,
638 unsigned HOST_WIDE_INT);
639 static void rs6000_xcoff_unique_section (tree, int);
640 static section *rs6000_xcoff_select_rtx_section
641 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
642 static const char * rs6000_xcoff_strip_name_encoding (const char *);
643 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
644 static void rs6000_xcoff_file_start (void);
645 static void rs6000_xcoff_file_end (void);
647 static int rs6000_variable_issue (FILE *, int, rtx, int);
648 static bool rs6000_rtx_costs (rtx, int, int, int *);
649 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
650 static bool is_microcoded_insn (rtx);
651 static int is_dispatch_slot_restricted (rtx);
652 static bool is_cracked_insn (rtx);
653 static bool is_branch_slot_insn (rtx);
654 static int rs6000_adjust_priority (rtx, int);
655 static int rs6000_issue_rate (void);
656 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
657 static rtx get_next_active_insn (rtx, rtx);
658 static bool insn_terminates_group_p (rtx , enum group_termination);
659 static bool is_costly_group (rtx *, rtx);
660 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
661 static int redefine_groups (FILE *, int, rtx, rtx);
662 static int pad_groups (FILE *, int, rtx, rtx);
663 static void rs6000_sched_finish (FILE *, int);
664 static int rs6000_use_sched_lookahead (void);
665 static tree rs6000_builtin_mask_for_load (void);
667 static void def_builtin (int, const char *, tree, int);
668 static void rs6000_init_builtins (void);
669 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
670 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
671 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
672 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
673 static void altivec_init_builtins (void);
674 static void rs6000_common_init_builtins (void);
675 static void rs6000_init_libfuncs (void);
677 static void enable_mask_for_builtins (struct builtin_description *, int,
678 enum rs6000_builtins,
679 enum rs6000_builtins);
680 static tree build_opaque_vector_type (tree, int);
681 static void spe_init_builtins (void);
682 static rtx spe_expand_builtin (tree, rtx, bool *);
683 static rtx spe_expand_stv_builtin (enum insn_code, tree);
684 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
685 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
686 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
687 static rs6000_stack_t *rs6000_stack_info (void);
688 static void debug_stack_info (rs6000_stack_t *);
690 static rtx altivec_expand_builtin (tree, rtx, bool *);
691 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
692 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
693 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
694 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
695 static rtx altivec_expand_predicate_builtin (enum insn_code,
696 const char *, tree, rtx);
697 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
698 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
699 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
700 static rtx altivec_expand_vec_set_builtin (tree);
701 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
702 static int get_element_number (tree, tree);
703 static bool rs6000_handle_option (size_t, const char *, int);
704 static void rs6000_parse_tls_size_option (void);
705 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
706 static int first_altivec_reg_to_save (void);
707 static unsigned int compute_vrsave_mask (void);
708 static void compute_save_world_info (rs6000_stack_t *info_ptr);
709 static void is_altivec_return_reg (rtx, void *);
710 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
711 int easy_vector_constant (rtx, enum machine_mode);
712 static bool rs6000_is_opaque_type (tree);
713 static rtx rs6000_dwarf_register_span (rtx);
714 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
715 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
716 static rtx rs6000_tls_get_addr (void);
717 static rtx rs6000_got_sym (void);
718 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
719 static const char *rs6000_get_some_local_dynamic_name (void);
720 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
721 static rtx rs6000_complex_function_value (enum machine_mode);
722 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
723 enum machine_mode, tree);
724 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
726 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
727 tree, HOST_WIDE_INT);
728 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
731 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
734 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
735 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
736 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
737 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
738 enum machine_mode, tree,
740 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
742 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
744 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
746 static void macho_branch_islands (void);
747 static void add_compiler_branch_island (tree, tree, int);
748 static int no_previous_def (tree function_name);
749 static tree get_prev_label (tree function_name);
750 static void rs6000_darwin_file_start (void);
753 static tree rs6000_build_builtin_va_list (void);
754 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
755 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
756 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
757 static bool rs6000_vector_mode_supported_p (enum machine_mode);
758 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
760 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
762 static int get_vsel_insn (enum machine_mode);
763 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
764 static tree rs6000_stack_protect_fail (void);
766 const int INSN_NOT_AVAILABLE = -1;
767 static enum machine_mode rs6000_eh_return_filter_mode (void);
769 /* Hash table stuff for keeping track of TOC entries. */
771 struct toc_hash_struct GTY(())
773 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
774 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
776 enum machine_mode key_mode;
780 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
782 /* Default register names. */
783 char rs6000_reg_names[][8] =
785 "0", "1", "2", "3", "4", "5", "6", "7",
786 "8", "9", "10", "11", "12", "13", "14", "15",
787 "16", "17", "18", "19", "20", "21", "22", "23",
788 "24", "25", "26", "27", "28", "29", "30", "31",
789 "0", "1", "2", "3", "4", "5", "6", "7",
790 "8", "9", "10", "11", "12", "13", "14", "15",
791 "16", "17", "18", "19", "20", "21", "22", "23",
792 "24", "25", "26", "27", "28", "29", "30", "31",
793 "mq", "lr", "ctr","ap",
794 "0", "1", "2", "3", "4", "5", "6", "7",
796 /* AltiVec registers. */
797 "0", "1", "2", "3", "4", "5", "6", "7",
798 "8", "9", "10", "11", "12", "13", "14", "15",
799 "16", "17", "18", "19", "20", "21", "22", "23",
800 "24", "25", "26", "27", "28", "29", "30", "31",
803 "spe_acc", "spefscr",
804 /* Soft frame pointer. */
808 #ifdef TARGET_REGNAMES
809 static const char alt_reg_names[][8] =
811 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
812 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
813 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
814 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
815 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
816 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
817 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
818 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
819 "mq", "lr", "ctr", "ap",
820 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
822 /* AltiVec registers. */
823 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
824 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
825 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
826 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
829 "spe_acc", "spefscr",
830 /* Soft frame pointer. */
835 #ifndef MASK_STRICT_ALIGN
836 #define MASK_STRICT_ALIGN 0
838 #ifndef TARGET_PROFILE_KERNEL
839 #define TARGET_PROFILE_KERNEL 0
842 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
843 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
845 /* Initialize the GCC target structure. */
846 #undef TARGET_ATTRIBUTE_TABLE
847 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
848 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
849 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
851 #undef TARGET_ASM_ALIGNED_DI_OP
852 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
854 /* Default unaligned ops are only provided for ELF. Find the ops needed
855 for non-ELF systems. */
856 #ifndef OBJECT_FORMAT_ELF
858 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
860 #undef TARGET_ASM_UNALIGNED_HI_OP
861 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
862 #undef TARGET_ASM_UNALIGNED_SI_OP
863 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
864 #undef TARGET_ASM_UNALIGNED_DI_OP
865 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
868 #undef TARGET_ASM_UNALIGNED_HI_OP
869 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
870 #undef TARGET_ASM_UNALIGNED_SI_OP
871 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
872 #undef TARGET_ASM_UNALIGNED_DI_OP
873 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
874 #undef TARGET_ASM_ALIGNED_DI_OP
875 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
879 /* This hook deals with fixups for relocatable code and DI-mode objects
881 #undef TARGET_ASM_INTEGER
882 #define TARGET_ASM_INTEGER rs6000_assemble_integer
884 #ifdef HAVE_GAS_HIDDEN
885 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
886 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
889 #undef TARGET_HAVE_TLS
890 #define TARGET_HAVE_TLS HAVE_AS_TLS
892 #undef TARGET_CANNOT_FORCE_CONST_MEM
893 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
895 #undef TARGET_ASM_FUNCTION_PROLOGUE
896 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
897 #undef TARGET_ASM_FUNCTION_EPILOGUE
898 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
900 #undef TARGET_SCHED_VARIABLE_ISSUE
901 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
903 #undef TARGET_SCHED_ISSUE_RATE
904 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
905 #undef TARGET_SCHED_ADJUST_COST
906 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
907 #undef TARGET_SCHED_ADJUST_PRIORITY
908 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
909 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
910 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
911 #undef TARGET_SCHED_FINISH
912 #define TARGET_SCHED_FINISH rs6000_sched_finish
914 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
915 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
917 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
918 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
920 #undef TARGET_INIT_BUILTINS
921 #define TARGET_INIT_BUILTINS rs6000_init_builtins
923 #undef TARGET_EXPAND_BUILTIN
924 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
926 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
927 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
929 #undef TARGET_INIT_LIBFUNCS
930 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
933 #undef TARGET_BINDS_LOCAL_P
934 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
937 #undef TARGET_MS_BITFIELD_LAYOUT_P
938 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
940 #undef TARGET_ASM_OUTPUT_MI_THUNK
941 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
943 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
944 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
946 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
947 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
949 #undef TARGET_INVALID_WITHIN_DOLOOP
950 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
952 #undef TARGET_RTX_COSTS
953 #define TARGET_RTX_COSTS rs6000_rtx_costs
954 #undef TARGET_ADDRESS_COST
955 #define TARGET_ADDRESS_COST hook_int_rtx_0
957 #undef TARGET_VECTOR_OPAQUE_P
958 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
960 #undef TARGET_DWARF_REGISTER_SPAN
961 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
963 /* On rs6000, function arguments are promoted, as are function return
965 #undef TARGET_PROMOTE_FUNCTION_ARGS
966 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
967 #undef TARGET_PROMOTE_FUNCTION_RETURN
968 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
970 #undef TARGET_RETURN_IN_MEMORY
971 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
973 #undef TARGET_SETUP_INCOMING_VARARGS
974 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
976 /* Always strict argument naming on rs6000. */
977 #undef TARGET_STRICT_ARGUMENT_NAMING
978 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
979 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
980 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
981 #undef TARGET_SPLIT_COMPLEX_ARG
982 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
983 #undef TARGET_MUST_PASS_IN_STACK
984 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
985 #undef TARGET_PASS_BY_REFERENCE
986 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
987 #undef TARGET_ARG_PARTIAL_BYTES
988 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
990 #undef TARGET_BUILD_BUILTIN_VA_LIST
991 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
993 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
994 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
996 #undef TARGET_EH_RETURN_FILTER_MODE
997 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
999 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1000 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1002 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1003 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1005 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1006 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1008 #undef TARGET_HANDLE_OPTION
1009 #define TARGET_HANDLE_OPTION rs6000_handle_option
1011 #undef TARGET_DEFAULT_TARGET_FLAGS
1012 #define TARGET_DEFAULT_TARGET_FLAGS \
1015 #undef TARGET_STACK_PROTECT_FAIL
1016 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1018 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1019 The PowerPC architecture requires only weak consistency among
1020 processors--that is, memory accesses between processors need not be
1021 sequentially consistent and memory accesses among processors can occur
1022 in any order. The ability to order memory accesses weakly provides
1023 opportunities for more efficient use of the system bus. Unless a
1024 dependency exists, the 604e allows read operations to precede store
1026 #undef TARGET_RELAXED_ORDERING
1027 #define TARGET_RELAXED_ORDERING true
1030 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1031 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1034 /* Use a 32-bit anchor range. This leads to sequences like:
1036 addis tmp,anchor,high
1039 where tmp itself acts as an anchor, and can be shared between
1040 accesses to the same 64k page. */
1041 #undef TARGET_MIN_ANCHOR_OFFSET
1042 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1043 #undef TARGET_MAX_ANCHOR_OFFSET
1044 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1045 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1046 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1048 struct gcc_target targetm = TARGET_INITIALIZER;
1051 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1054 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1056 /* The GPRs can hold any mode, but values bigger than one register
1057 cannot go past R31. */
1058 if (INT_REGNO_P (regno))
1059 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1061 /* The float registers can only hold floating modes and DImode.
1062 This also excludes decimal float modes. */
1063 if (FP_REGNO_P (regno))
1065 (SCALAR_FLOAT_MODE_P (mode)
1066 && !DECIMAL_FLOAT_MODE_P (mode)
1067 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1068 || (GET_MODE_CLASS (mode) == MODE_INT
1069 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1071 /* The CR register can only hold CC modes. */
1072 if (CR_REGNO_P (regno))
1073 return GET_MODE_CLASS (mode) == MODE_CC;
1075 if (XER_REGNO_P (regno))
1076 return mode == PSImode;
1078 /* AltiVec only in AldyVec registers. */
1079 if (ALTIVEC_REGNO_P (regno))
1080 return ALTIVEC_VECTOR_MODE (mode);
1082 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1083 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1086 /* We cannot put TImode anywhere except general register and it must be
1087 able to fit within the register set. */
1089 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1092 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1094 rs6000_init_hard_regno_mode_ok (void)
1098 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1099 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1100 if (rs6000_hard_regno_mode_ok (r, m))
1101 rs6000_hard_regno_mode_ok_p[m][r] = true;
1104 /* If not otherwise specified by a target, make 'long double' equivalent to
1107 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1108 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1111 /* Override command line options. Mostly we process the processor
1112 type and sometimes adjust other TARGET_ options. */
1115 rs6000_override_options (const char *default_cpu)
1118 struct rs6000_cpu_select *ptr;
1121 /* Simplifications for entries below. */
1124 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1125 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1128 /* This table occasionally claims that a processor does not support
1129 a particular feature even though it does, but the feature is slower
1130 than the alternative. Thus, it shouldn't be relied on as a
1131 complete description of the processor's support.
1133 Please keep this list in order, and don't forget to update the
1134 documentation in invoke.texi when adding a new processor or
1138 const char *const name; /* Canonical processor name. */
1139 const enum processor_type processor; /* Processor type enum value. */
1140 const int target_enable; /* Target flags to enable. */
1141 } const processor_target_table[]
1142 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1143 {"403", PROCESSOR_PPC403,
1144 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1145 {"405", PROCESSOR_PPC405,
1146 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1147 {"405fp", PROCESSOR_PPC405,
1148 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1149 {"440", PROCESSOR_PPC440,
1150 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1151 {"440fp", PROCESSOR_PPC440,
1152 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1153 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1154 {"601", PROCESSOR_PPC601,
1155 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1156 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1157 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1158 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1159 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1160 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1161 {"620", PROCESSOR_PPC620,
1162 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1163 {"630", PROCESSOR_PPC630,
1164 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1165 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1166 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1167 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1168 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1169 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1170 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1171 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1172 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1173 /* 8548 has a dummy entry for now. */
1174 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1175 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1176 {"970", PROCESSOR_POWER4,
1177 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1178 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1179 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1180 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1181 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1182 {"G5", PROCESSOR_POWER4,
1183 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1184 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1185 {"power2", PROCESSOR_POWER,
1186 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1187 {"power3", PROCESSOR_PPC630,
1188 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1189 {"power4", PROCESSOR_POWER4,
1190 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1191 {"power5", PROCESSOR_POWER5,
1192 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1193 | MASK_MFCRF | MASK_POPCNTB},
1194 {"power5+", PROCESSOR_POWER5,
1195 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1196 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1197 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1198 {"powerpc64", PROCESSOR_POWERPC64,
1199 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1200 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1201 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1202 {"rios2", PROCESSOR_RIOS2,
1203 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1204 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1205 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1206 {"rs64", PROCESSOR_RS64A,
1207 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1210 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1212 /* Some OSs don't support saving the high part of 64-bit registers on
1213 context switch. Other OSs don't support saving Altivec registers.
1214 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1215 settings; if the user wants either, the user must explicitly specify
1216 them and we won't interfere with the user's specification. */
1219 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1220 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1221 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1222 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1226 rs6000_init_hard_regno_mode_ok ();
1228 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1229 #ifdef OS_MISSING_POWERPC64
1230 if (OS_MISSING_POWERPC64)
1231 set_masks &= ~MASK_POWERPC64;
1233 #ifdef OS_MISSING_ALTIVEC
1234 if (OS_MISSING_ALTIVEC)
1235 set_masks &= ~MASK_ALTIVEC;
1238 /* Don't override by the processor default if given explicitly. */
1239 set_masks &= ~target_flags_explicit;
1241 /* Identify the processor type. */
1242 rs6000_select[0].string = default_cpu;
1243 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1245 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1247 ptr = &rs6000_select[i];
1248 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1250 for (j = 0; j < ptt_size; j++)
1251 if (! strcmp (ptr->string, processor_target_table[j].name))
1253 if (ptr->set_tune_p)
1254 rs6000_cpu = processor_target_table[j].processor;
1256 if (ptr->set_arch_p)
1258 target_flags &= ~set_masks;
1259 target_flags |= (processor_target_table[j].target_enable
1266 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1273 /* If we are optimizing big endian systems for space, use the load/store
1274 multiple and string instructions. */
1275 if (BYTES_BIG_ENDIAN && optimize_size)
1276 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1278 /* Don't allow -mmultiple or -mstring on little endian systems
1279 unless the cpu is a 750, because the hardware doesn't support the
1280 instructions used in little endian mode, and causes an alignment
1281 trap. The 750 does not cause an alignment trap (except when the
1282 target is unaligned). */
1284 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1286 if (TARGET_MULTIPLE)
1288 target_flags &= ~MASK_MULTIPLE;
1289 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1290 warning (0, "-mmultiple is not supported on little endian systems");
1295 target_flags &= ~MASK_STRING;
1296 if ((target_flags_explicit & MASK_STRING) != 0)
1297 warning (0, "-mstring is not supported on little endian systems");
1301 /* Set debug flags */
1302 if (rs6000_debug_name)
1304 if (! strcmp (rs6000_debug_name, "all"))
1305 rs6000_debug_stack = rs6000_debug_arg = 1;
1306 else if (! strcmp (rs6000_debug_name, "stack"))
1307 rs6000_debug_stack = 1;
1308 else if (! strcmp (rs6000_debug_name, "arg"))
1309 rs6000_debug_arg = 1;
1311 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1314 if (rs6000_traceback_name)
1316 if (! strncmp (rs6000_traceback_name, "full", 4))
1317 rs6000_traceback = traceback_full;
1318 else if (! strncmp (rs6000_traceback_name, "part", 4))
1319 rs6000_traceback = traceback_part;
1320 else if (! strncmp (rs6000_traceback_name, "no", 2))
1321 rs6000_traceback = traceback_none;
1323 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1324 rs6000_traceback_name);
1327 if (!rs6000_explicit_options.long_double)
1328 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1330 #ifndef POWERPC_LINUX
1331 if (!rs6000_explicit_options.ieee)
1332 rs6000_ieeequad = 1;
1335 /* Set Altivec ABI as default for powerpc64 linux. */
1336 if (TARGET_ELF && TARGET_64BIT)
1338 rs6000_altivec_abi = 1;
1339 TARGET_ALTIVEC_VRSAVE = 1;
1342 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1343 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1345 rs6000_darwin64_abi = 1;
1347 darwin_one_byte_bool = 1;
1349 /* Default to natural alignment, for better performance. */
1350 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1353 /* Handle -mtls-size option. */
1354 rs6000_parse_tls_size_option ();
1356 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1357 SUBTARGET_OVERRIDE_OPTIONS;
1359 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1360 SUBSUBTARGET_OVERRIDE_OPTIONS;
1362 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1363 SUB3TARGET_OVERRIDE_OPTIONS;
1369 error ("AltiVec and E500 instructions cannot coexist");
1371 /* The e500 does not have string instructions, and we set
1372 MASK_STRING above when optimizing for size. */
1373 if ((target_flags & MASK_STRING) != 0)
1374 target_flags = target_flags & ~MASK_STRING;
1376 else if (rs6000_select[1].string != NULL)
1378 /* For the powerpc-eabispe configuration, we set all these by
1379 default, so let's unset them if we manually set another
1380 CPU that is not the E500. */
1381 if (!rs6000_explicit_options.abi)
1383 if (!rs6000_explicit_options.spe)
1385 if (!rs6000_explicit_options.float_gprs)
1386 rs6000_float_gprs = 0;
1387 if (!rs6000_explicit_options.isel)
1389 if (!rs6000_explicit_options.long_double)
1390 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1393 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1394 && rs6000_cpu != PROCESSOR_POWER5);
1395 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1396 || rs6000_cpu == PROCESSOR_POWER5);
1398 rs6000_sched_restricted_insns_priority
1399 = (rs6000_sched_groups ? 1 : 0);
1401 /* Handle -msched-costly-dep option. */
1402 rs6000_sched_costly_dep
1403 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1405 if (rs6000_sched_costly_dep_str)
1407 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1408 rs6000_sched_costly_dep = no_dep_costly;
1409 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1410 rs6000_sched_costly_dep = all_deps_costly;
1411 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1412 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1413 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1414 rs6000_sched_costly_dep = store_to_load_dep_costly;
1416 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1419 /* Handle -minsert-sched-nops option. */
1420 rs6000_sched_insert_nops
1421 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1423 if (rs6000_sched_insert_nops_str)
1425 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1426 rs6000_sched_insert_nops = sched_finish_none;
1427 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1428 rs6000_sched_insert_nops = sched_finish_pad_groups;
1429 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1430 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1432 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1435 #ifdef TARGET_REGNAMES
1436 /* If the user desires alternate register names, copy in the
1437 alternate names now. */
1438 if (TARGET_REGNAMES)
1439 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1442 /* Set aix_struct_return last, after the ABI is determined.
1443 If -maix-struct-return or -msvr4-struct-return was explicitly
1444 used, don't override with the ABI default. */
1445 if (!rs6000_explicit_options.aix_struct_ret)
1446 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1448 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1449 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1452 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1454 /* We can only guarantee the availability of DI pseudo-ops when
1455 assembling for 64-bit targets. */
1458 targetm.asm_out.aligned_op.di = NULL;
1459 targetm.asm_out.unaligned_op.di = NULL;
1462 /* Set branch target alignment, if not optimizing for size. */
1465 if (rs6000_sched_groups)
1467 if (align_functions <= 0)
1468 align_functions = 16;
1469 if (align_jumps <= 0)
1471 if (align_loops <= 0)
1474 if (align_jumps_max_skip <= 0)
1475 align_jumps_max_skip = 15;
1476 if (align_loops_max_skip <= 0)
1477 align_loops_max_skip = 15;
1480 /* Arrange to save and restore machine status around nested functions. */
1481 init_machine_status = rs6000_init_machine_status;
1483 /* We should always be splitting complex arguments, but we can't break
1484 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1485 if (DEFAULT_ABI != ABI_AIX)
1486 targetm.calls.split_complex_arg = NULL;
1488 /* Initialize rs6000_cost with the appropriate target costs. */
1490 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1494 case PROCESSOR_RIOS1:
1495 rs6000_cost = &rios1_cost;
1498 case PROCESSOR_RIOS2:
1499 rs6000_cost = &rios2_cost;
1502 case PROCESSOR_RS64A:
1503 rs6000_cost = &rs64a_cost;
1506 case PROCESSOR_MPCCORE:
1507 rs6000_cost = &mpccore_cost;
1510 case PROCESSOR_PPC403:
1511 rs6000_cost = &ppc403_cost;
1514 case PROCESSOR_PPC405:
1515 rs6000_cost = &ppc405_cost;
1518 case PROCESSOR_PPC440:
1519 rs6000_cost = &ppc440_cost;
1522 case PROCESSOR_PPC601:
1523 rs6000_cost = &ppc601_cost;
1526 case PROCESSOR_PPC603:
1527 rs6000_cost = &ppc603_cost;
1530 case PROCESSOR_PPC604:
1531 rs6000_cost = &ppc604_cost;
1534 case PROCESSOR_PPC604e:
1535 rs6000_cost = &ppc604e_cost;
1538 case PROCESSOR_PPC620:
1539 rs6000_cost = &ppc620_cost;
1542 case PROCESSOR_PPC630:
1543 rs6000_cost = &ppc630_cost;
1546 case PROCESSOR_PPC750:
1547 case PROCESSOR_PPC7400:
1548 rs6000_cost = &ppc750_cost;
1551 case PROCESSOR_PPC7450:
1552 rs6000_cost = &ppc7450_cost;
1555 case PROCESSOR_PPC8540:
1556 rs6000_cost = &ppc8540_cost;
1559 case PROCESSOR_POWER4:
1560 case PROCESSOR_POWER5:
1561 rs6000_cost = &power4_cost;
1569 /* Implement targetm.vectorize.builtin_mask_for_load. */
1571 rs6000_builtin_mask_for_load (void)
1574 return altivec_builtin_mask_for_load;
1579 /* Handle generic options of the form -mfoo=yes/no.
1580 NAME is the option name.
1581 VALUE is the option value.
1582 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1583 whether the option value is 'yes' or 'no' respectively. */
1585 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1589 else if (!strcmp (value, "yes"))
1591 else if (!strcmp (value, "no"))
1594 error ("unknown -m%s= option specified: '%s'", name, value);
1597 /* Validate and record the size specified with the -mtls-size option. */
1600 rs6000_parse_tls_size_option (void)
1602 if (rs6000_tls_size_string == 0)
1604 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1605 rs6000_tls_size = 16;
1606 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1607 rs6000_tls_size = 32;
1608 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1609 rs6000_tls_size = 64;
1611 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1615 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1617 if (DEFAULT_ABI == ABI_DARWIN)
1618 /* The Darwin libraries never set errno, so we might as well
1619 avoid calling them when that's the only reason we would. */
1620 flag_errno_math = 0;
1622 /* Double growth factor to counter reduced min jump length. */
1623 set_param_value ("max-grow-copy-bb-insns", 16);
1626 /* Implement TARGET_HANDLE_OPTION. */
1629 rs6000_handle_option (size_t code, const char *arg, int value)
1634 target_flags &= ~(MASK_POWER | MASK_POWER2
1635 | MASK_MULTIPLE | MASK_STRING);
1636 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1637 | MASK_MULTIPLE | MASK_STRING);
1639 case OPT_mno_powerpc:
1640 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1641 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1642 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1643 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1646 target_flags &= ~MASK_MINIMAL_TOC;
1647 TARGET_NO_FP_IN_TOC = 0;
1648 TARGET_NO_SUM_IN_TOC = 0;
1649 target_flags_explicit |= MASK_MINIMAL_TOC;
1650 #ifdef TARGET_USES_SYSV4_OPT
1651 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1652 just the same as -mminimal-toc. */
1653 target_flags |= MASK_MINIMAL_TOC;
1654 target_flags_explicit |= MASK_MINIMAL_TOC;
1658 #ifdef TARGET_USES_SYSV4_OPT
1660 /* Make -mtoc behave like -mminimal-toc. */
1661 target_flags |= MASK_MINIMAL_TOC;
1662 target_flags_explicit |= MASK_MINIMAL_TOC;
1666 #ifdef TARGET_USES_AIX64_OPT
1671 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
1672 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
1673 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
1676 #ifdef TARGET_USES_AIX64_OPT
1681 target_flags &= ~MASK_POWERPC64;
1682 target_flags_explicit |= MASK_POWERPC64;
1685 case OPT_minsert_sched_nops_:
1686 rs6000_sched_insert_nops_str = arg;
1689 case OPT_mminimal_toc:
1692 TARGET_NO_FP_IN_TOC = 0;
1693 TARGET_NO_SUM_IN_TOC = 0;
1700 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1701 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1708 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1709 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1713 case OPT_mpowerpc_gpopt:
1714 case OPT_mpowerpc_gfxopt:
1717 target_flags |= MASK_POWERPC;
1718 target_flags_explicit |= MASK_POWERPC;
1722 case OPT_maix_struct_return:
1723 case OPT_msvr4_struct_return:
1724 rs6000_explicit_options.aix_struct_ret = true;
1728 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1732 rs6000_explicit_options.isel = true;
1733 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1737 rs6000_explicit_options.spe = true;
1738 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1739 /* No SPE means 64-bit long doubles, even if an E500. */
1741 rs6000_long_double_type_size = 64;
1745 rs6000_debug_name = arg;
1748 #ifdef TARGET_USES_SYSV4_OPT
1750 rs6000_abi_name = arg;
1754 rs6000_sdata_name = arg;
1757 case OPT_mtls_size_:
1758 rs6000_tls_size_string = arg;
1761 case OPT_mrelocatable:
1764 target_flags |= MASK_MINIMAL_TOC;
1765 target_flags_explicit |= MASK_MINIMAL_TOC;
1766 TARGET_NO_FP_IN_TOC = 1;
1770 case OPT_mrelocatable_lib:
1773 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
1774 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
1775 TARGET_NO_FP_IN_TOC = 1;
1779 target_flags &= ~MASK_RELOCATABLE;
1780 target_flags_explicit |= MASK_RELOCATABLE;
1786 if (!strcmp (arg, "altivec"))
1788 rs6000_explicit_options.abi = true;
1789 rs6000_altivec_abi = 1;
1792 else if (! strcmp (arg, "no-altivec"))
1794 /* ??? Don't set rs6000_explicit_options.abi here, to allow
1795 the default for rs6000_spe_abi to be chosen later. */
1796 rs6000_altivec_abi = 0;
1798 else if (! strcmp (arg, "spe"))
1800 rs6000_explicit_options.abi = true;
1802 rs6000_altivec_abi = 0;
1803 if (!TARGET_SPE_ABI)
1804 error ("not configured for ABI: '%s'", arg);
1806 else if (! strcmp (arg, "no-spe"))
1808 rs6000_explicit_options.abi = true;
1812 /* These are here for testing during development only, do not
1813 document in the manual please. */
1814 else if (! strcmp (arg, "d64"))
1816 rs6000_darwin64_abi = 1;
1817 warning (0, "Using darwin64 ABI");
1819 else if (! strcmp (arg, "d32"))
1821 rs6000_darwin64_abi = 0;
1822 warning (0, "Using old darwin ABI");
1825 else if (! strcmp (arg, "ibmlongdouble"))
1827 rs6000_explicit_options.ieee = true;
1828 rs6000_ieeequad = 0;
1829 warning (0, "Using IBM extended precision long double");
1831 else if (! strcmp (arg, "ieeelongdouble"))
1833 rs6000_explicit_options.ieee = true;
1834 rs6000_ieeequad = 1;
1835 warning (0, "Using IEEE extended precision long double");
1840 error ("unknown ABI specified: '%s'", arg);
1846 rs6000_select[1].string = arg;
1850 rs6000_select[2].string = arg;
1853 case OPT_mtraceback_:
1854 rs6000_traceback_name = arg;
1857 case OPT_mfloat_gprs_:
1858 rs6000_explicit_options.float_gprs = true;
1859 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
1860 rs6000_float_gprs = 1;
1861 else if (! strcmp (arg, "double"))
1862 rs6000_float_gprs = 2;
1863 else if (! strcmp (arg, "no"))
1864 rs6000_float_gprs = 0;
1867 error ("invalid option for -mfloat-gprs: '%s'", arg);
1872 case OPT_mlong_double_:
1873 rs6000_explicit_options.long_double = true;
1874 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1875 if (value != 64 && value != 128)
1877 error ("Unknown switch -mlong-double-%s", arg);
1878 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1882 rs6000_long_double_type_size = value;
1885 case OPT_msched_costly_dep_:
1886 rs6000_sched_costly_dep_str = arg;
1890 rs6000_explicit_options.alignment = true;
1891 if (! strcmp (arg, "power"))
1893 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1894 some C library functions, so warn about it. The flag may be
1895 useful for performance studies from time to time though, so
1896 don't disable it entirely. */
1897 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1898 warning (0, "-malign-power is not supported for 64-bit Darwin;"
1899 " it is incompatible with the installed C and C++ libraries");
1900 rs6000_alignment_flags = MASK_ALIGN_POWER;
1902 else if (! strcmp (arg, "natural"))
1903 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1906 error ("unknown -malign-XXXXX option specified: '%s'", arg);
1914 /* Do anything needed at the start of the asm file. */
1917 rs6000_file_start (void)
1921 const char *start = buffer;
1922 struct rs6000_cpu_select *ptr;
1923 const char *default_cpu = TARGET_CPU_DEFAULT;
1924 FILE *file = asm_out_file;
1926 default_file_start ();
1928 #ifdef TARGET_BI_ARCH
1929 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1933 if (flag_verbose_asm)
1935 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1936 rs6000_select[0].string = default_cpu;
1938 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1940 ptr = &rs6000_select[i];
1941 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1943 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1948 if (PPC405_ERRATUM77)
1950 fprintf (file, "%s PPC405CR_ERRATUM77", start);
1954 #ifdef USING_ELFOS_H
1955 switch (rs6000_sdata)
1957 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1958 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1959 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1960 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1963 if (rs6000_sdata && g_switch_value)
1965 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1975 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1977 switch_to_section (toc_section);
1978 switch_to_section (text_section);
1983 /* Return nonzero if this function is known to have a null epilogue. */
1986 direct_return (void)
1988 if (reload_completed)
1990 rs6000_stack_t *info = rs6000_stack_info ();
1992 if (info->first_gp_reg_save == 32
1993 && info->first_fp_reg_save == 64
1994 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1995 && ! info->lr_save_p
1996 && ! info->cr_save_p
1997 && info->vrsave_mask == 0
2005 /* Return the number of instructions it takes to form a constant in an
2006 integer register. */
2009 num_insns_constant_wide (HOST_WIDE_INT value)
2011 /* signed constant loadable with {cal|addi} */
2012 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2015 /* constant loadable with {cau|addis} */
2016 else if ((value & 0xffff) == 0
2017 && (value >> 31 == -1 || value >> 31 == 0))
2020 #if HOST_BITS_PER_WIDE_INT == 64
2021 else if (TARGET_POWERPC64)
2023 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2024 HOST_WIDE_INT high = value >> 31;
2026 if (high == 0 || high == -1)
2032 return num_insns_constant_wide (high) + 1;
2034 return (num_insns_constant_wide (high)
2035 + num_insns_constant_wide (low) + 1);
2044 num_insns_constant (rtx op, enum machine_mode mode)
2046 HOST_WIDE_INT low, high;
2048 switch (GET_CODE (op))
2051 #if HOST_BITS_PER_WIDE_INT == 64
2052 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2053 && mask64_operand (op, mode))
2057 return num_insns_constant_wide (INTVAL (op));
2065 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2066 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2067 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2070 if (mode == VOIDmode || mode == DImode)
2072 high = CONST_DOUBLE_HIGH (op);
2073 low = CONST_DOUBLE_LOW (op);
2080 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2081 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2082 high = l[WORDS_BIG_ENDIAN == 0];
2083 low = l[WORDS_BIG_ENDIAN != 0];
2087 return (num_insns_constant_wide (low)
2088 + num_insns_constant_wide (high));
2091 if ((high == 0 && low >= 0)
2092 || (high == -1 && low < 0))
2093 return num_insns_constant_wide (low);
2095 else if (mask64_operand (op, mode))
2099 return num_insns_constant_wide (high) + 1;
2102 return (num_insns_constant_wide (high)
2103 + num_insns_constant_wide (low) + 1);
2112 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2113 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2114 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2115 all items are set to the same value and contain COPIES replicas of the
2116 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2117 operand and the others are set to the value of the operand's msb. */
2120 vspltis_constant (rtx op, unsigned step, unsigned copies)
2122 enum machine_mode mode = GET_MODE (op);
2123 enum machine_mode inner = GET_MODE_INNER (mode);
2126 unsigned nunits = GET_MODE_NUNITS (mode);
2127 unsigned bitsize = GET_MODE_BITSIZE (inner);
2128 unsigned mask = GET_MODE_MASK (inner);
2130 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2131 HOST_WIDE_INT val = INTVAL (last);
2132 HOST_WIDE_INT splat_val = val;
2133 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2135 /* Construct the value to be splatted, if possible. If not, return 0. */
2136 for (i = 2; i <= copies; i *= 2)
2138 HOST_WIDE_INT small_val;
2140 small_val = splat_val >> bitsize;
2142 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2144 splat_val = small_val;
2147 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2148 if (EASY_VECTOR_15 (splat_val))
2151 /* Also check if we can splat, and then add the result to itself. Do so if
2152 the value is positive, of if the splat instruction is using OP's mode;
2153 for splat_val < 0, the splat and the add should use the same mode. */
2154 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2155 && (splat_val >= 0 || (step == 1 && copies == 1)))
2161 /* Check if VAL is present in every STEP-th element, and the
2162 other elements are filled with its most significant bit. */
2163 for (i = 0; i < nunits - 1; ++i)
2165 HOST_WIDE_INT desired_val;
2166 if (((i + 1) & (step - 1)) == 0)
2169 desired_val = msb_val;
2171 if (desired_val != INTVAL (CONST_VECTOR_ELT (op, i)))
2179 /* Return true if OP is of the given MODE and can be synthesized
2180 with a vspltisb, vspltish or vspltisw. */
2183 easy_altivec_constant (rtx op, enum machine_mode mode)
2185 unsigned step, copies;
2187 if (mode == VOIDmode)
2188 mode = GET_MODE (op);
2189 else if (mode != GET_MODE (op))
2192 /* Start with a vspltisw. */
2193 step = GET_MODE_NUNITS (mode) / 4;
2196 if (vspltis_constant (op, step, copies))
2199 /* Then try with a vspltish. */
2205 if (vspltis_constant (op, step, copies))
2208 /* And finally a vspltisb. */
2214 if (vspltis_constant (op, step, copies))
2220 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2221 result is OP. Abort if it is not possible. */
2224 gen_easy_altivec_constant (rtx op)
2226 enum machine_mode mode = GET_MODE (op);
2227 int nunits = GET_MODE_NUNITS (mode);
2228 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2229 unsigned step = nunits / 4;
2230 unsigned copies = 1;
2232 /* Start with a vspltisw. */
2233 if (vspltis_constant (op, step, copies))
2234 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2236 /* Then try with a vspltish. */
2242 if (vspltis_constant (op, step, copies))
2243 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2245 /* And finally a vspltisb. */
2251 if (vspltis_constant (op, step, copies))
2252 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2258 output_vec_const_move (rtx *operands)
2261 enum machine_mode mode;
2266 mode = GET_MODE (dest);
2271 if (zero_constant (vec, mode))
2272 return "vxor %0,%0,%0";
2274 splat_vec = gen_easy_altivec_constant (vec);
2275 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2276 operands[1] = XEXP (splat_vec, 0);
2277 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2280 switch (GET_MODE (splat_vec))
2283 return "vspltisw %0,%1";
2286 return "vspltish %0,%1";
2289 return "vspltisb %0,%1";
2296 gcc_assert (TARGET_SPE);
2298 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2299 pattern of V1DI, V4HI, and V2SF.
2301 FIXME: We should probably return # and add post reload
2302 splitters for these, but this way is so easy ;-). */
2303 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2304 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2305 operands[1] = CONST_VECTOR_ELT (vec, 0);
2306 operands[2] = CONST_VECTOR_ELT (vec, 1);
2308 return "li %0,%1\n\tevmergelo %0,%0,%0";
2310 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2313 /* Initialize vector TARGET to VALS. */
2316 rs6000_expand_vector_init (rtx target, rtx vals)
2318 enum machine_mode mode = GET_MODE (target);
2319 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2320 int n_elts = GET_MODE_NUNITS (mode);
2321 int n_var = 0, one_var = -1;
2322 bool all_same = true, all_const_zero = true;
2326 for (i = 0; i < n_elts; ++i)
2328 x = XVECEXP (vals, 0, i);
2329 if (!CONSTANT_P (x))
2330 ++n_var, one_var = i;
2331 else if (x != CONST0_RTX (inner_mode))
2332 all_const_zero = false;
2334 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2340 if (mode != V4SFmode && all_const_zero)
2342 /* Zero register. */
2343 emit_insn (gen_rtx_SET (VOIDmode, target,
2344 gen_rtx_XOR (mode, target, target)));
2347 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2349 /* Splat immediate. */
2350 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2354 ; /* Splat vector element. */
2357 /* Load from constant pool. */
2358 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2363 /* Store value to stack temp. Load vector element. Splat. */
2366 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2367 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2368 XVECEXP (vals, 0, 0));
2369 x = gen_rtx_UNSPEC (VOIDmode,
2370 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2371 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2373 gen_rtx_SET (VOIDmode,
2376 x = gen_rtx_VEC_SELECT (inner_mode, target,
2377 gen_rtx_PARALLEL (VOIDmode,
2378 gen_rtvec (1, const0_rtx)));
2379 emit_insn (gen_rtx_SET (VOIDmode, target,
2380 gen_rtx_VEC_DUPLICATE (mode, x)));
2384 /* One field is non-constant. Load constant then overwrite
2388 rtx copy = copy_rtx (vals);
2390 /* Load constant part of vector, substitute neighboring value for
2392 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2393 rs6000_expand_vector_init (target, copy);
2395 /* Insert variable. */
2396 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2400 /* Construct the vector in memory one field at a time
2401 and load the whole vector. */
2402 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2403 for (i = 0; i < n_elts; i++)
2404 emit_move_insn (adjust_address_nv (mem, inner_mode,
2405 i * GET_MODE_SIZE (inner_mode)),
2406 XVECEXP (vals, 0, i));
2407 emit_move_insn (target, mem);
2410 /* Set field ELT of TARGET to VAL. */
2413 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2415 enum machine_mode mode = GET_MODE (target);
2416 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2417 rtx reg = gen_reg_rtx (mode);
2419 int width = GET_MODE_SIZE (inner_mode);
2422 /* Load single variable value. */
2423 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2424 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2425 x = gen_rtx_UNSPEC (VOIDmode,
2426 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2427 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2429 gen_rtx_SET (VOIDmode,
2433 /* Linear sequence. */
2434 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2435 for (i = 0; i < 16; ++i)
2436 XVECEXP (mask, 0, i) = GEN_INT (i);
2438 /* Set permute mask to insert element into target. */
2439 for (i = 0; i < width; ++i)
2440 XVECEXP (mask, 0, elt*width + i)
2441 = GEN_INT (i + 0x10);
2442 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2443 x = gen_rtx_UNSPEC (mode,
2444 gen_rtvec (3, target, reg,
2445 force_reg (V16QImode, x)),
2447 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2450 /* Extract field ELT from VEC into TARGET. */
2453 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2455 enum machine_mode mode = GET_MODE (vec);
2456 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2459 /* Allocate mode-sized buffer. */
2460 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2462 /* Add offset to field within buffer matching vector element. */
2463 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2465 /* Store single field into mode-sized buffer. */
2466 x = gen_rtx_UNSPEC (VOIDmode,
2467 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2468 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2470 gen_rtx_SET (VOIDmode,
2473 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2476 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2477 implement ANDing by the mask IN. */
2479 build_mask64_2_operands (rtx in, rtx *out)
2481 #if HOST_BITS_PER_WIDE_INT >= 64
2482 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2485 gcc_assert (GET_CODE (in) == CONST_INT);
2490 /* Assume c initially something like 0x00fff000000fffff. The idea
2491 is to rotate the word so that the middle ^^^^^^ group of zeros
2492 is at the MS end and can be cleared with an rldicl mask. We then
2493 rotate back and clear off the MS ^^ group of zeros with a
2495 c = ~c; /* c == 0xff000ffffff00000 */
2496 lsb = c & -c; /* lsb == 0x0000000000100000 */
2497 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2498 c = ~c; /* c == 0x00fff000000fffff */
2499 c &= -lsb; /* c == 0x00fff00000000000 */
2500 lsb = c & -c; /* lsb == 0x0000100000000000 */
2501 c = ~c; /* c == 0xff000fffffffffff */
2502 c &= -lsb; /* c == 0xff00000000000000 */
2504 while ((lsb >>= 1) != 0)
2505 shift++; /* shift == 44 on exit from loop */
2506 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2507 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2508 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2512 /* Assume c initially something like 0xff000f0000000000. The idea
2513 is to rotate the word so that the ^^^ middle group of zeros
2514 is at the LS end and can be cleared with an rldicr mask. We then
2515 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2517 lsb = c & -c; /* lsb == 0x0000010000000000 */
2518 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2519 c = ~c; /* c == 0x00fff0ffffffffff */
2520 c &= -lsb; /* c == 0x00fff00000000000 */
2521 lsb = c & -c; /* lsb == 0x0000100000000000 */
2522 c = ~c; /* c == 0xff000fffffffffff */
2523 c &= -lsb; /* c == 0xff00000000000000 */
2525 while ((lsb >>= 1) != 0)
2526 shift++; /* shift == 44 on exit from loop */
2527 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2528 m1 >>= shift; /* m1 == 0x0000000000000fff */
2529 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2532 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2533 masks will be all 1's. We are guaranteed more than one transition. */
2534 out[0] = GEN_INT (64 - shift);
2535 out[1] = GEN_INT (m1);
2536 out[2] = GEN_INT (shift);
2537 out[3] = GEN_INT (m2);
2545 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2548 invalid_e500_subreg (rtx op, enum machine_mode mode)
2550 /* Reject (subreg:SI (reg:DF)). */
2551 if (GET_CODE (op) == SUBREG
2553 && REG_P (SUBREG_REG (op))
2554 && GET_MODE (SUBREG_REG (op)) == DFmode)
2557 /* Reject (subreg:DF (reg:DI)). */
2558 if (GET_CODE (op) == SUBREG
2560 && REG_P (SUBREG_REG (op))
2561 && GET_MODE (SUBREG_REG (op)) == DImode)
2567 /* Darwin, AIX increases natural record alignment to doubleword if the first
2568 field is an FP double while the FP fields remain word aligned. */
2571 rs6000_special_round_type_align (tree type, unsigned int computed,
2572 unsigned int specified)
2574 unsigned int align = MAX (computed, specified);
2575 tree field = TYPE_FIELDS (type);
2577 /* Skip all non field decls */
2578 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2579 field = TREE_CHAIN (field);
2581 if (field != NULL && field != type)
2583 type = TREE_TYPE (field);
2584 while (TREE_CODE (type) == ARRAY_TYPE)
2585 type = TREE_TYPE (type);
2587 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2588 align = MAX (align, 64);
2594 /* Return 1 for an operand in small memory on V.4/eabi. */
2597 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2598 enum machine_mode mode ATTRIBUTE_UNUSED)
2603 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2606 if (DEFAULT_ABI != ABI_V4)
2609 if (GET_CODE (op) == SYMBOL_REF)
2612 else if (GET_CODE (op) != CONST
2613 || GET_CODE (XEXP (op, 0)) != PLUS
2614 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2615 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2620 rtx sum = XEXP (op, 0);
2621 HOST_WIDE_INT summand;
2623 /* We have to be careful here, because it is the referenced address
2624 that must be 32k from _SDA_BASE_, not just the symbol. */
2625 summand = INTVAL (XEXP (sum, 1));
2626 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2629 sym_ref = XEXP (sum, 0);
2632 return SYMBOL_REF_SMALL_P (sym_ref);
2638 /* Return true if either operand is a general purpose register. */
2641 gpr_or_gpr_p (rtx op0, rtx op1)
2643 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2644 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2648 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2651 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2653 switch (GET_CODE (op))
2656 if (RS6000_SYMBOL_REF_TLS_P (op))
2658 else if (CONSTANT_POOL_ADDRESS_P (op))
2660 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2668 else if (! strcmp (XSTR (op, 0), toc_label_name))
2677 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2678 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2680 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2689 constant_pool_expr_p (rtx op)
2693 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2697 toc_relative_expr_p (rtx op)
2701 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2705 legitimate_constant_pool_address_p (rtx x)
2708 && GET_CODE (x) == PLUS
2709 && GET_CODE (XEXP (x, 0)) == REG
2710 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2711 && constant_pool_expr_p (XEXP (x, 1)));
2715 legitimate_small_data_p (enum machine_mode mode, rtx x)
2717 return (DEFAULT_ABI == ABI_V4
2718 && !flag_pic && !TARGET_TOC
2719 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2720 && small_data_operand (x, mode));
2723 /* SPE offset addressing is limited to 5-bits worth of double words. */
2724 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2727 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2729 unsigned HOST_WIDE_INT offset, extra;
2731 if (GET_CODE (x) != PLUS)
2733 if (GET_CODE (XEXP (x, 0)) != REG)
2735 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2737 if (legitimate_constant_pool_address_p (x))
2739 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2742 offset = INTVAL (XEXP (x, 1));
2750 /* AltiVec vector modes. Only reg+reg addressing is valid and
2751 constant offset zero should not occur due to canonicalization.
2752 Allow any offset when not strict before reload. */
2759 /* SPE vector modes. */
2760 return SPE_CONST_OFFSET_OK (offset);
2763 if (TARGET_E500_DOUBLE)
2764 return SPE_CONST_OFFSET_OK (offset);
2767 /* On e500v2, we may have:
2769 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2771 Which gets addressed with evldd instructions. */
2772 if (TARGET_E500_DOUBLE)
2773 return SPE_CONST_OFFSET_OK (offset);
2775 if (mode == DFmode || !TARGET_POWERPC64)
2777 else if (offset & 3)
2783 if (mode == TFmode || !TARGET_POWERPC64)
2785 else if (offset & 3)
2796 return (offset < 0x10000) && (offset + extra < 0x10000);
2800 legitimate_indexed_address_p (rtx x, int strict)
2804 if (GET_CODE (x) != PLUS)
2810 /* Recognize the rtl generated by reload which we know will later be
2811 replaced with proper base and index regs. */
2813 && reload_in_progress
2814 && (REG_P (op0) || GET_CODE (op0) == PLUS)
2818 return (REG_P (op0) && REG_P (op1)
2819 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
2820 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2821 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2822 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
2826 legitimate_indirect_address_p (rtx x, int strict)
2828 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2832 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2834 if (!TARGET_MACHO || !flag_pic
2835 || mode != SImode || GET_CODE (x) != MEM)
2839 if (GET_CODE (x) != LO_SUM)
2841 if (GET_CODE (XEXP (x, 0)) != REG)
2843 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2847 return CONSTANT_P (x);
2851 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2853 if (GET_CODE (x) != LO_SUM)
2855 if (GET_CODE (XEXP (x, 0)) != REG)
2857 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2859 /* Restrict addressing for DI because of our SUBREG hackery. */
2860 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
2864 if (TARGET_ELF || TARGET_MACHO)
2866 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2870 if (GET_MODE_NUNITS (mode) != 1)
2872 if (GET_MODE_BITSIZE (mode) > 64
2873 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2874 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
2877 return CONSTANT_P (x);
2884 /* Try machine-dependent ways of modifying an illegitimate address
2885 to be legitimate. If we find one, return the new, valid address.
2886 This is used from only one place: `memory_address' in explow.c.
2888 OLDX is the address as it was before break_out_memory_refs was
2889 called. In some cases it is useful to look at this to decide what
2892 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2894 It is always safe for this function to do nothing. It exists to
2895 recognize opportunities to optimize the output.
2897 On RS/6000, first check for the sum of a register with a constant
2898 integer that is out of range. If so, generate code to add the
2899 constant with the low-order 16 bits masked to the register and force
2900 this result into another register (this can be done with `cau').
2901 Then generate an address of REG+(CONST&0xffff), allowing for the
2902 possibility of bit 16 being a one.
2904 Then check for the sum of a register and something not constant, try to
2905 load the other things into a register and return the sum. */
2908 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2909 enum machine_mode mode)
2911 if (GET_CODE (x) == SYMBOL_REF)
2913 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2915 return rs6000_legitimize_tls_address (x, model);
2918 if (GET_CODE (x) == PLUS
2919 && GET_CODE (XEXP (x, 0)) == REG
2920 && GET_CODE (XEXP (x, 1)) == CONST_INT
2921 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2923 HOST_WIDE_INT high_int, low_int;
2925 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2926 high_int = INTVAL (XEXP (x, 1)) - low_int;
2927 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2928 GEN_INT (high_int)), 0);
2929 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2931 else if (GET_CODE (x) == PLUS
2932 && GET_CODE (XEXP (x, 0)) == REG
2933 && GET_CODE (XEXP (x, 1)) != CONST_INT
2934 && GET_MODE_NUNITS (mode) == 1
2935 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2937 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2939 && (TARGET_POWERPC64 || mode != DImode)
2942 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2943 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2945 else if (ALTIVEC_VECTOR_MODE (mode))
2949 /* Make sure both operands are registers. */
2950 if (GET_CODE (x) == PLUS)
2951 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2952 force_reg (Pmode, XEXP (x, 1)));
2954 reg = force_reg (Pmode, x);
2957 else if (SPE_VECTOR_MODE (mode)
2958 || (TARGET_E500_DOUBLE && (mode == DFmode
2959 || mode == DImode)))
2963 /* We accept [reg + reg] and [reg + OFFSET]. */
2965 if (GET_CODE (x) == PLUS)
2967 rtx op1 = XEXP (x, 0);
2968 rtx op2 = XEXP (x, 1);
2970 op1 = force_reg (Pmode, op1);
2972 if (GET_CODE (op2) != REG
2973 && (GET_CODE (op2) != CONST_INT
2974 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2975 op2 = force_reg (Pmode, op2);
2977 return gen_rtx_PLUS (Pmode, op1, op2);
2980 return force_reg (Pmode, x);
2986 && GET_CODE (x) != CONST_INT
2987 && GET_CODE (x) != CONST_DOUBLE
2989 && GET_MODE_NUNITS (mode) == 1
2990 && (GET_MODE_BITSIZE (mode) <= 32
2991 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2993 rtx reg = gen_reg_rtx (Pmode);
2994 emit_insn (gen_elf_high (reg, x));
2995 return gen_rtx_LO_SUM (Pmode, reg, x);
2997 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3000 && ! MACHO_DYNAMIC_NO_PIC_P
3002 && GET_CODE (x) != CONST_INT
3003 && GET_CODE (x) != CONST_DOUBLE
3005 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3009 rtx reg = gen_reg_rtx (Pmode);
3010 emit_insn (gen_macho_high (reg, x));
3011 return gen_rtx_LO_SUM (Pmode, reg, x);
3014 && constant_pool_expr_p (x)
3015 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3017 return create_TOC_reference (x);
3023 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3024 We need to emit DTP-relative relocations. */
3027 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3032 fputs ("\t.long\t", file);
3035 fputs (DOUBLE_INT_ASM_OP, file);
3040 output_addr_const (file, x);
3041 fputs ("@dtprel+0x8000", file);
3044 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3046 static GTY(()) rtx rs6000_tls_symbol;
3048 rs6000_tls_get_addr (void)
3050 if (!rs6000_tls_symbol)
3051 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3053 return rs6000_tls_symbol;
3056 /* Construct the SYMBOL_REF for TLS GOT references. */
3058 static GTY(()) rtx rs6000_got_symbol;
3060 rs6000_got_sym (void)
3062 if (!rs6000_got_symbol)
3064 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3065 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3066 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3069 return rs6000_got_symbol;
3072 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3073 this (thread-local) address. */
3076 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3080 dest = gen_reg_rtx (Pmode);
3081 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3087 tlsreg = gen_rtx_REG (Pmode, 13);
3088 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3092 tlsreg = gen_rtx_REG (Pmode, 2);
3093 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3097 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3101 tmp = gen_reg_rtx (Pmode);
3104 tlsreg = gen_rtx_REG (Pmode, 13);
3105 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3109 tlsreg = gen_rtx_REG (Pmode, 2);
3110 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3114 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3116 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3121 rtx r3, got, tga, tmp1, tmp2, eqv;
3123 /* We currently use relocations like @got@tlsgd for tls, which
3124 means the linker will handle allocation of tls entries, placing
3125 them in the .got section. So use a pointer to the .got section,
3126 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3127 or to secondary GOT sections used by 32-bit -fPIC. */
3129 got = gen_rtx_REG (Pmode, 2);
3133 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3136 rtx gsym = rs6000_got_sym ();
3137 got = gen_reg_rtx (Pmode);
3139 rs6000_emit_move (got, gsym, Pmode);
3142 rtx tempLR, tmp3, mem;
3145 tempLR = gen_reg_rtx (Pmode);
3146 tmp1 = gen_reg_rtx (Pmode);
3147 tmp2 = gen_reg_rtx (Pmode);
3148 tmp3 = gen_reg_rtx (Pmode);
3149 mem = gen_const_mem (Pmode, tmp1);
3151 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
3152 emit_move_insn (tmp1, tempLR);
3153 emit_move_insn (tmp2, mem);
3154 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3155 last = emit_move_insn (got, tmp3);
3156 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3158 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3160 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3166 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3168 r3 = gen_rtx_REG (Pmode, 3);
3170 insn = gen_tls_gd_64 (r3, got, addr);
3172 insn = gen_tls_gd_32 (r3, got, addr);
3175 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3176 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3177 insn = emit_call_insn (insn);
3178 CONST_OR_PURE_CALL_P (insn) = 1;
3179 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3180 insn = get_insns ();
3182 emit_libcall_block (insn, dest, r3, addr);
3184 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3186 r3 = gen_rtx_REG (Pmode, 3);
3188 insn = gen_tls_ld_64 (r3, got);
3190 insn = gen_tls_ld_32 (r3, got);
3193 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3194 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3195 insn = emit_call_insn (insn);
3196 CONST_OR_PURE_CALL_P (insn) = 1;
3197 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3198 insn = get_insns ();
3200 tmp1 = gen_reg_rtx (Pmode);
3201 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3203 emit_libcall_block (insn, tmp1, r3, eqv);
3204 if (rs6000_tls_size == 16)
3207 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3209 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3211 else if (rs6000_tls_size == 32)
3213 tmp2 = gen_reg_rtx (Pmode);
3215 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3217 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3220 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3222 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3226 tmp2 = gen_reg_rtx (Pmode);
3228 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3230 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3232 insn = gen_rtx_SET (Pmode, dest,
3233 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3239 /* IE, or 64 bit offset LE. */
3240 tmp2 = gen_reg_rtx (Pmode);
3242 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3244 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3247 insn = gen_tls_tls_64 (dest, tmp2, addr);
3249 insn = gen_tls_tls_32 (dest, tmp2, addr);
3257 /* Return 1 if X contains a thread-local symbol. */
3260 rs6000_tls_referenced_p (rtx x)
3262 if (! TARGET_HAVE_TLS)
3265 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3268 /* Return 1 if *X is a thread-local symbol. This is the same as
3269 rs6000_tls_symbol_ref except for the type of the unused argument. */
3272 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3274 return RS6000_SYMBOL_REF_TLS_P (*x);
3277 /* The convention appears to be to define this wherever it is used.
3278 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3279 is now used here. */
3280 #ifndef REG_MODE_OK_FOR_BASE_P
3281 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3284 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3285 replace the input X, or the original X if no replacement is called for.
3286 The output parameter *WIN is 1 if the calling macro should goto WIN,
3289 For RS/6000, we wish to handle large displacements off a base
3290 register by splitting the addend across an addiu/addis and the mem insn.
3291 This cuts number of extra insns needed from 3 to 1.
3293 On Darwin, we use this to generate code for floating point constants.
3294 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3295 The Darwin code is inside #if TARGET_MACHO because only then is
3296 machopic_function_base_name() defined. */
3298 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3299 int opnum, int type,
3300 int ind_levels ATTRIBUTE_UNUSED, int *win)
3302 /* We must recognize output that we have already generated ourselves. */
3303 if (GET_CODE (x) == PLUS
3304 && GET_CODE (XEXP (x, 0)) == PLUS
3305 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3306 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3307 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3309 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3310 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3311 opnum, (enum reload_type)type);
3317 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3318 && GET_CODE (x) == LO_SUM
3319 && GET_CODE (XEXP (x, 0)) == PLUS
3320 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3321 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3322 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3323 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3324 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3325 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3326 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3328 /* Result of previous invocation of this function on Darwin
3329 floating point constant. */
3330 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3331 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3332 opnum, (enum reload_type)type);
3338 /* Force ld/std non-word aligned offset into base register by wrapping
3340 if (GET_CODE (x) == PLUS
3341 && GET_CODE (XEXP (x, 0)) == REG
3342 && REGNO (XEXP (x, 0)) < 32
3343 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3344 && GET_CODE (XEXP (x, 1)) == CONST_INT
3345 && (INTVAL (XEXP (x, 1)) & 3) != 0
3346 && !ALTIVEC_VECTOR_MODE (mode)
3347 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3348 && TARGET_POWERPC64)
3350 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3351 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3352 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3353 opnum, (enum reload_type) type);
3358 if (GET_CODE (x) == PLUS
3359 && GET_CODE (XEXP (x, 0)) == REG
3360 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3361 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3362 && GET_CODE (XEXP (x, 1)) == CONST_INT
3363 && !SPE_VECTOR_MODE (mode)
3364 && !(TARGET_E500_DOUBLE && (mode == DFmode
3366 && !ALTIVEC_VECTOR_MODE (mode))
3368 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3369 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3371 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3373 /* Check for 32-bit overflow. */
3374 if (high + low != val)
3380 /* Reload the high part into a base reg; leave the low part
3381 in the mem directly. */
3383 x = gen_rtx_PLUS (GET_MODE (x),
3384 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3388 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3389 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3390 opnum, (enum reload_type)type);
3395 if (GET_CODE (x) == SYMBOL_REF
3396 && !ALTIVEC_VECTOR_MODE (mode)
3398 && DEFAULT_ABI == ABI_DARWIN
3399 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3401 && DEFAULT_ABI == ABI_V4
3404 /* Don't do this for TFmode, since the result isn't offsettable.
3405 The same goes for DImode without 64-bit gprs and DFmode
3408 && (mode != DImode || TARGET_POWERPC64)
3409 && (mode != DFmode || TARGET_POWERPC64
3410 || (TARGET_FPRS && TARGET_HARD_FLOAT)))
3415 rtx offset = gen_rtx_CONST (Pmode,
3416 gen_rtx_MINUS (Pmode, x,
3417 machopic_function_base_sym ()));
3418 x = gen_rtx_LO_SUM (GET_MODE (x),
3419 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3420 gen_rtx_HIGH (Pmode, offset)), offset);
3424 x = gen_rtx_LO_SUM (GET_MODE (x),
3425 gen_rtx_HIGH (Pmode, x), x);
3427 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3428 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3429 opnum, (enum reload_type)type);
3434 /* Reload an offset address wrapped by an AND that represents the
3435 masking of the lower bits. Strip the outer AND and let reload
3436 convert the offset address into an indirect address. */
3438 && ALTIVEC_VECTOR_MODE (mode)
3439 && GET_CODE (x) == AND
3440 && GET_CODE (XEXP (x, 0)) == PLUS
3441 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3442 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3443 && GET_CODE (XEXP (x, 1)) == CONST_INT
3444 && INTVAL (XEXP (x, 1)) == -16)
3452 && constant_pool_expr_p (x)
3453 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3455 (x) = create_TOC_reference (x);
3463 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3464 that is a valid memory address for an instruction.
3465 The MODE argument is the machine mode for the MEM expression
3466 that wants to use this address.
3468 On the RS/6000, there are four valid address: a SYMBOL_REF that
3469 refers to a constant pool entry of an address (or the sum of it
3470 plus a constant), a short (16-bit signed) constant plus a register,
3471 the sum of two registers, or a register indirect, possibly with an
3472 auto-increment. For DFmode and DImode with a constant plus register,
3473 we must ensure that both words are addressable or PowerPC64 with offset
3476 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3477 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3478 adjacent memory cells are accessed by adding word-sized offsets
3479 during assembly output. */
3481 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3483 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3485 && ALTIVEC_VECTOR_MODE (mode)
3486 && GET_CODE (x) == AND
3487 && GET_CODE (XEXP (x, 1)) == CONST_INT
3488 && INTVAL (XEXP (x, 1)) == -16)
3491 if (RS6000_SYMBOL_REF_TLS_P (x))
3493 if (legitimate_indirect_address_p (x, reg_ok_strict))
3495 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3496 && !ALTIVEC_VECTOR_MODE (mode)
3497 && !SPE_VECTOR_MODE (mode)
3498 /* Restrict addressing for DI because of our SUBREG hackery. */
3499 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3501 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3503 if (legitimate_small_data_p (mode, x))
3505 if (legitimate_constant_pool_address_p (x))
3507 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3509 && GET_CODE (x) == PLUS
3510 && GET_CODE (XEXP (x, 0)) == REG
3511 && (XEXP (x, 0) == virtual_stack_vars_rtx
3512 || XEXP (x, 0) == arg_pointer_rtx)
3513 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3515 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3519 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3521 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3522 && (TARGET_POWERPC64 || mode != DImode)
3523 && legitimate_indexed_address_p (x, reg_ok_strict))
3525 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3530 /* Go to LABEL if ADDR (a legitimate address expression)
3531 has an effect that depends on the machine mode it is used for.
3533 On the RS/6000 this is true of all integral offsets (since AltiVec
3534 modes don't allow them) or is a pre-increment or decrement.
3536 ??? Except that due to conceptual problems in offsettable_address_p
3537 we can't really report the problems of integral offsets. So leave
3538 this assuming that the adjustable offset must be valid for the
3539 sub-words of a TFmode operand, which is what we had before. */
3542 rs6000_mode_dependent_address (rtx addr)
3544 switch (GET_CODE (addr))
3547 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3549 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3550 return val + 12 + 0x8000 >= 0x10000;
3559 return TARGET_UPDATE;
3568 /* More elaborate version of recog's offsettable_memref_p predicate
3569 that works around the ??? note of rs6000_mode_dependent_address.
3570 In particular it accepts
3572 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
3574 in 32-bit mode, that the recog predicate rejects. */
3577 rs6000_offsettable_memref_p (rtx op)
3582 /* First mimic offsettable_memref_p. */
3583 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
3586 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
3587 the latter predicate knows nothing about the mode of the memory
3588 reference and, therefore, assumes that it is the largest supported
3589 mode (TFmode). As a consequence, legitimate offsettable memory
3590 references are rejected. rs6000_legitimate_offset_address_p contains
3591 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
3592 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
3595 /* Return number of consecutive hard regs needed starting at reg REGNO
3596 to hold something of mode MODE.
3597 This is ordinarily the length in words of a value of mode MODE
3598 but can be less for certain modes in special long registers.
3600 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3601 scalar instructions. The upper 32 bits are only available to the
3604 POWER and PowerPC GPRs hold 32 bits worth;
3605 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3608 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3610 if (FP_REGNO_P (regno))
3611 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3613 if (TARGET_E500_DOUBLE && mode == DFmode)
3616 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3617 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3619 if (ALTIVEC_REGNO_P (regno))
3621 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3623 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3626 /* Change register usage conditional on target flags. */
3628 rs6000_conditional_register_usage (void)
3632 /* Set MQ register fixed (already call_used) if not POWER
3633 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3638 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3640 fixed_regs[13] = call_used_regs[13]
3641 = call_really_used_regs[13] = 1;
3643 /* Conditionally disable FPRs. */
3644 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3645 for (i = 32; i < 64; i++)
3646 fixed_regs[i] = call_used_regs[i]
3647 = call_really_used_regs[i] = 1;
3649 /* The TOC register is not killed across calls in a way that is
3650 visible to the compiler. */
3651 if (DEFAULT_ABI == ABI_AIX)
3652 call_really_used_regs[2] = 0;
3654 if (DEFAULT_ABI == ABI_V4
3655 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3657 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3659 if (DEFAULT_ABI == ABI_V4
3660 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3662 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3663 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3664 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3666 if (DEFAULT_ABI == ABI_DARWIN
3667 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3668 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3669 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3670 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3672 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3673 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3674 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3677 global_regs[VSCR_REGNO] = 1;
3681 global_regs[SPEFSCR_REGNO] = 1;
3682 fixed_regs[FIXED_SCRATCH]
3683 = call_used_regs[FIXED_SCRATCH]
3684 = call_really_used_regs[FIXED_SCRATCH] = 1;
3687 if (! TARGET_ALTIVEC)
3689 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3690 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3691 call_really_used_regs[VRSAVE_REGNO] = 1;
3694 if (TARGET_ALTIVEC_ABI)
3695 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3696 call_used_regs[i] = call_really_used_regs[i] = 1;
3699 /* Try to output insns to set TARGET equal to the constant C if it can
3700 be done in less than N insns. Do all computations in MODE.
3701 Returns the place where the output has been placed if it can be
3702 done and the insns have been emitted. If it would take more than N
3703 insns, zero is returned and no insns and emitted. */
3706 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3707 rtx source, int n ATTRIBUTE_UNUSED)
3709 rtx result, insn, set;
3710 HOST_WIDE_INT c0, c1;
3717 dest = gen_reg_rtx (mode);
3718 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3722 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3724 emit_insn (gen_rtx_SET (VOIDmode, result,
3725 GEN_INT (INTVAL (source)
3726 & (~ (HOST_WIDE_INT) 0xffff))));
3727 emit_insn (gen_rtx_SET (VOIDmode, dest,
3728 gen_rtx_IOR (SImode, result,
3729 GEN_INT (INTVAL (source) & 0xffff))));
3734 switch (GET_CODE (source))
3737 c0 = INTVAL (source);
3742 #if HOST_BITS_PER_WIDE_INT >= 64
3743 c0 = CONST_DOUBLE_LOW (source);
3746 c0 = CONST_DOUBLE_LOW (source);
3747 c1 = CONST_DOUBLE_HIGH (source);
3755 result = rs6000_emit_set_long_const (dest, c0, c1);
3762 insn = get_last_insn ();
3763 set = single_set (insn);
3764 if (! CONSTANT_P (SET_SRC (set)))
3765 set_unique_reg_note (insn, REG_EQUAL, source);
3770 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3771 fall back to a straight forward decomposition. We do this to avoid
3772 exponential run times encountered when looking for longer sequences
3773 with rs6000_emit_set_const. */
3775 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3777 if (!TARGET_POWERPC64)
3779 rtx operand1, operand2;
3781 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3783 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3785 emit_move_insn (operand1, GEN_INT (c1));
3786 emit_move_insn (operand2, GEN_INT (c2));
3790 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3793 ud2 = (c1 & 0xffff0000) >> 16;
3794 #if HOST_BITS_PER_WIDE_INT >= 64
3798 ud4 = (c2 & 0xffff0000) >> 16;
3800 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3801 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3804 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3806 emit_move_insn (dest, GEN_INT (ud1));
3809 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3810 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3813 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3816 emit_move_insn (dest, GEN_INT (ud2 << 16));
3818 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3820 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3821 || (ud4 == 0 && ! (ud3 & 0x8000)))
3824 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3827 emit_move_insn (dest, GEN_INT (ud3 << 16));
3830 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3831 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3833 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3838 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3841 emit_move_insn (dest, GEN_INT (ud4 << 16));
3844 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3846 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3848 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3849 GEN_INT (ud2 << 16)));
3851 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3857 /* Helper for the following. Get rid of [r+r] memory refs
3858 in cases where it won't work (TImode, TFmode). */
3861 rs6000_eliminate_indexed_memrefs (rtx operands[2])
3863 if (GET_CODE (operands[0]) == MEM
3864 && GET_CODE (XEXP (operands[0], 0)) != REG
3865 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
3866 && ! reload_in_progress)
3868 = replace_equiv_address (operands[0],
3869 copy_addr_to_reg (XEXP (operands[0], 0)));
3871 if (GET_CODE (operands[1]) == MEM
3872 && GET_CODE (XEXP (operands[1], 0)) != REG
3873 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
3874 && ! reload_in_progress)
3876 = replace_equiv_address (operands[1],
3877 copy_addr_to_reg (XEXP (operands[1], 0)));
3880 /* Emit a move from SOURCE to DEST in mode MODE. */
3882 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3886 operands[1] = source;
3888 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3889 if (GET_CODE (operands[1]) == CONST_DOUBLE
3890 && ! FLOAT_MODE_P (mode)
3891 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3893 /* FIXME. This should never happen. */
3894 /* Since it seems that it does, do the safe thing and convert
3896 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3898 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
3899 || FLOAT_MODE_P (mode)
3900 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
3901 || CONST_DOUBLE_LOW (operands[1]) < 0)
3902 && (CONST_DOUBLE_HIGH (operands[1]) != -1
3903 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
3905 /* Check if GCC is setting up a block move that will end up using FP
3906 registers as temporaries. We must make sure this is acceptable. */
3907 if (GET_CODE (operands[0]) == MEM
3908 && GET_CODE (operands[1]) == MEM
3910 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3911 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3912 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3913 ? 32 : MEM_ALIGN (operands[0])))
3914 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3916 : MEM_ALIGN (operands[1]))))
3917 && ! MEM_VOLATILE_P (operands [0])
3918 && ! MEM_VOLATILE_P (operands [1]))
3920 emit_move_insn (adjust_address (operands[0], SImode, 0),
3921 adjust_address (operands[1], SImode, 0));
3922 emit_move_insn (adjust_address (operands[0], SImode, 4),
3923 adjust_address (operands[1], SImode, 4));
3927 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
3928 && !gpc_reg_operand (operands[1], mode))
3929 operands[1] = force_reg (mode, operands[1]);
3931 if (mode == SFmode && ! TARGET_POWERPC
3932 && TARGET_HARD_FLOAT && TARGET_FPRS
3933 && GET_CODE (operands[0]) == MEM)
3937 if (reload_in_progress || reload_completed)
3938 regnum = true_regnum (operands[1]);
3939 else if (GET_CODE (operands[1]) == REG)
3940 regnum = REGNO (operands[1]);
3944 /* If operands[1] is a register, on POWER it may have
3945 double-precision data in it, so truncate it to single
3947 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3950 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3951 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3952 operands[1] = newreg;
3956 /* Recognize the case where operand[1] is a reference to thread-local
3957 data and load its address to a register. */
3958 if (rs6000_tls_referenced_p (operands[1]))
3960 enum tls_model model;
3961 rtx tmp = operands[1];
3964 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
3966 addend = XEXP (XEXP (tmp, 0), 1);
3967 tmp = XEXP (XEXP (tmp, 0), 0);
3970 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
3971 model = SYMBOL_REF_TLS_MODEL (tmp);
3972 gcc_assert (model != 0);
3974 tmp = rs6000_legitimize_tls_address (tmp, model);
3977 tmp = gen_rtx_PLUS (mode, tmp, addend);
3978 tmp = force_operand (tmp, operands[0]);
3983 /* Handle the case where reload calls us with an invalid address. */
3984 if (reload_in_progress && mode == Pmode
3985 && (! general_operand (operands[1], mode)
3986 || ! nonimmediate_operand (operands[0], mode)))
3989 /* 128-bit constant floating-point values on Darwin should really be
3990 loaded as two parts. */
3991 if (!TARGET_IEEEQUAD
3992 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3993 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3995 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3996 know how to get a DFmode SUBREG of a TFmode. */
3997 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3998 simplify_gen_subreg (DImode, operands[1], mode, 0),
4000 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
4001 GET_MODE_SIZE (DImode)),
4002 simplify_gen_subreg (DImode, operands[1], mode,
4003 GET_MODE_SIZE (DImode)),
4008 /* FIXME: In the long term, this switch statement should go away
4009 and be replaced by a sequence of tests based on things like
4015 if (CONSTANT_P (operands[1])
4016 && GET_CODE (operands[1]) != CONST_INT)
4017 operands[1] = force_const_mem (mode, operands[1]);
4021 rs6000_eliminate_indexed_memrefs (operands);
4026 if (CONSTANT_P (operands[1])
4027 && ! easy_fp_constant (operands[1], mode))
4028 operands[1] = force_const_mem (mode, operands[1]);
4039 if (CONSTANT_P (operands[1])
4040 && !easy_vector_constant (operands[1], mode))
4041 operands[1] = force_const_mem (mode, operands[1]);
4046 /* Use default pattern for address of ELF small data */
4049 && DEFAULT_ABI == ABI_V4
4050 && (GET_CODE (operands[1]) == SYMBOL_REF
4051 || GET_CODE (operands[1]) == CONST)
4052 && small_data_operand (operands[1], mode))
4054 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4058 if (DEFAULT_ABI == ABI_V4
4059 && mode == Pmode && mode == SImode
4060 && flag_pic == 1 && got_operand (operands[1], mode))
4062 emit_insn (gen_movsi_got (operands[0], operands[1]));
4066 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4070 && CONSTANT_P (operands[1])
4071 && GET_CODE (operands[1]) != HIGH
4072 && GET_CODE (operands[1]) != CONST_INT)
4074 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
4076 /* If this is a function address on -mcall-aixdesc,
4077 convert it to the address of the descriptor. */
4078 if (DEFAULT_ABI == ABI_AIX
4079 && GET_CODE (operands[1]) == SYMBOL_REF
4080 && XSTR (operands[1], 0)[0] == '.')
4082 const char *name = XSTR (operands[1], 0);
4084 while (*name == '.')
4086 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4087 CONSTANT_POOL_ADDRESS_P (new_ref)
4088 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4089 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4090 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4091 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4092 operands[1] = new_ref;
4095 if (DEFAULT_ABI == ABI_DARWIN)
4098 if (MACHO_DYNAMIC_NO_PIC_P)
4100 /* Take care of any required data indirection. */
4101 operands[1] = rs6000_machopic_legitimize_pic_address (
4102 operands[1], mode, operands[0]);
4103 if (operands[0] != operands[1])
4104 emit_insn (gen_rtx_SET (VOIDmode,
4105 operands[0], operands[1]));
4109 emit_insn (gen_macho_high (target, operands[1]));
4110 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4114 emit_insn (gen_elf_high (target, operands[1]));
4115 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4119 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4120 and we have put it in the TOC, we just need to make a TOC-relative
4123 && GET_CODE (operands[1]) == SYMBOL_REF
4124 && constant_pool_expr_p (operands[1])
4125 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4126 get_pool_mode (operands[1])))
4128 operands[1] = create_TOC_reference (operands[1]);
4130 else if (mode == Pmode
4131 && CONSTANT_P (operands[1])
4132 && ((GET_CODE (operands[1]) != CONST_INT
4133 && ! easy_fp_constant (operands[1], mode))
4134 || (GET_CODE (operands[1]) == CONST_INT
4135 && num_insns_constant (operands[1], mode) > 2)
4136 || (GET_CODE (operands[0]) == REG
4137 && FP_REGNO_P (REGNO (operands[0]))))
4138 && GET_CODE (operands[1]) != HIGH
4139 && ! legitimate_constant_pool_address_p (operands[1])
4140 && ! toc_relative_expr_p (operands[1]))
4142 /* Emit a USE operation so that the constant isn't deleted if
4143 expensive optimizations are turned on because nobody
4144 references it. This should only be done for operands that
4145 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4146 This should not be done for operands that contain LABEL_REFs.
4147 For now, we just handle the obvious case. */
4148 if (GET_CODE (operands[1]) != LABEL_REF)
4149 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4152 /* Darwin uses a special PIC legitimizer. */
4153 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4156 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4158 if (operands[0] != operands[1])
4159 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4164 /* If we are to limit the number of things we put in the TOC and
4165 this is a symbol plus a constant we can add in one insn,
4166 just put the symbol in the TOC and add the constant. Don't do
4167 this if reload is in progress. */
4168 if (GET_CODE (operands[1]) == CONST
4169 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4170 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4171 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4172 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4173 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4174 && ! side_effects_p (operands[0]))
4177 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4178 rtx other = XEXP (XEXP (operands[1], 0), 1);
4180 sym = force_reg (mode, sym);
4182 emit_insn (gen_addsi3 (operands[0], sym, other));
4184 emit_insn (gen_adddi3 (operands[0], sym, other));
4188 operands[1] = force_const_mem (mode, operands[1]);
4191 && constant_pool_expr_p (XEXP (operands[1], 0))
4192 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4193 get_pool_constant (XEXP (operands[1], 0)),
4194 get_pool_mode (XEXP (operands[1], 0))))
4197 = gen_const_mem (mode,
4198 create_TOC_reference (XEXP (operands[1], 0)));
4199 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4205 rs6000_eliminate_indexed_memrefs (operands);
4209 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4211 gen_rtx_SET (VOIDmode,
4212 operands[0], operands[1]),
4213 gen_rtx_CLOBBER (VOIDmode,
4214 gen_rtx_SCRATCH (SImode)))));
4223 /* Above, we may have called force_const_mem which may have returned
4224 an invalid address. If we can, fix this up; otherwise, reload will
4225 have to deal with it. */
4226 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4227 operands[1] = validize_mem (operands[1]);
4230 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4233 /* Nonzero if we can use a floating-point register to pass this arg. */
4234 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4235 (SCALAR_FLOAT_MODE_P (MODE) \
4236 && !DECIMAL_FLOAT_MODE_P (MODE) \
4237 && (CUM)->fregno <= FP_ARG_MAX_REG \
4238 && TARGET_HARD_FLOAT && TARGET_FPRS)
4240 /* Nonzero if we can use an AltiVec register to pass this arg. */
4241 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4242 (ALTIVEC_VECTOR_MODE (MODE) \
4243 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4244 && TARGET_ALTIVEC_ABI \
4247 /* Return a nonzero value to say to return the function value in
4248 memory, just as large structures are always returned. TYPE will be
4249 the data type of the value, and FNTYPE will be the type of the
4250 function doing the returning, or @code{NULL} for libcalls.
4252 The AIX ABI for the RS/6000 specifies that all structures are
4253 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4254 specifies that structures <= 8 bytes are returned in r3/r4, but a
4255 draft put them in memory, and GCC used to implement the draft
4256 instead of the final standard. Therefore, aix_struct_return
4257 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4258 compatibility can change DRAFT_V4_STRUCT_RET to override the
4259 default, and -m switches get the final word. See
4260 rs6000_override_options for more details.
4262 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4263 long double support is enabled. These values are returned in memory.
4265 int_size_in_bytes returns -1 for variable size objects, which go in
4266 memory always. The cast to unsigned makes -1 > 8. */
4269 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4271 /* In the darwin64 abi, try to use registers for larger structs
4273 if (rs6000_darwin64_abi
4274 && TREE_CODE (type) == RECORD_TYPE
4275 && int_size_in_bytes (type) > 0)
4277 CUMULATIVE_ARGS valcum;
4281 valcum.fregno = FP_ARG_MIN_REG;
4282 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4283 /* Do a trial code generation as if this were going to be passed
4284 as an argument; if any part goes in memory, we return NULL. */
4285 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4288 /* Otherwise fall through to more conventional ABI rules. */
4291 if (AGGREGATE_TYPE_P (type)
4292 && (aix_struct_return
4293 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4296 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4297 modes only exist for GCC vector types if -maltivec. */
4298 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4299 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4302 /* Return synthetic vectors in memory. */
4303 if (TREE_CODE (type) == VECTOR_TYPE
4304 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4306 static bool warned_for_return_big_vectors = false;
4307 if (!warned_for_return_big_vectors)
4309 warning (0, "GCC vector returned by reference: "
4310 "non-standard ABI extension with no compatibility guarantee");
4311 warned_for_return_big_vectors = true;
4316 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4322 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4323 for a call to a function whose data type is FNTYPE.
4324 For a library call, FNTYPE is 0.
4326 For incoming args we set the number of arguments in the prototype large
4327 so we never return a PARALLEL. */
4330 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4331 rtx libname ATTRIBUTE_UNUSED, int incoming,
4332 int libcall, int n_named_args)
4334 static CUMULATIVE_ARGS zero_cumulative;
4336 *cum = zero_cumulative;
4338 cum->fregno = FP_ARG_MIN_REG;
4339 cum->vregno = ALTIVEC_ARG_MIN_REG;
4340 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4341 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4342 ? CALL_LIBCALL : CALL_NORMAL);
4343 cum->sysv_gregno = GP_ARG_MIN_REG;
4344 cum->stdarg = fntype
4345 && (TYPE_ARG_TYPES (fntype) != 0
4346 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4347 != void_type_node));
4349 cum->nargs_prototype = 0;
4350 if (incoming || cum->prototype)
4351 cum->nargs_prototype = n_named_args;
4353 /* Check for a longcall attribute. */
4354 if ((!fntype && rs6000_default_long_calls)
4356 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4357 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4358 cum->call_cookie |= CALL_LONG;
4360 if (TARGET_DEBUG_ARG)
4362 fprintf (stderr, "\ninit_cumulative_args:");
4365 tree ret_type = TREE_TYPE (fntype);
4366 fprintf (stderr, " ret code = %s,",
4367 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4370 if (cum->call_cookie & CALL_LONG)
4371 fprintf (stderr, " longcall,");
4373 fprintf (stderr, " proto = %d, nargs = %d\n",
4374 cum->prototype, cum->nargs_prototype);
4379 && TARGET_ALTIVEC_ABI
4380 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4382 error ("cannot return value in vector register because"
4383 " altivec instructions are disabled, use -maltivec"
4388 /* Return true if TYPE must be passed on the stack and not in registers. */
4391 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4393 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4394 return must_pass_in_stack_var_size (mode, type);
4396 return must_pass_in_stack_var_size_or_pad (mode, type);
4399 /* If defined, a C expression which determines whether, and in which
4400 direction, to pad out an argument with extra space. The value
4401 should be of type `enum direction': either `upward' to pad above
4402 the argument, `downward' to pad below, or `none' to inhibit
4405 For the AIX ABI structs are always stored left shifted in their
4409 function_arg_padding (enum machine_mode mode, tree type)
4411 #ifndef AGGREGATE_PADDING_FIXED
4412 #define AGGREGATE_PADDING_FIXED 0
4414 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4415 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4418 if (!AGGREGATE_PADDING_FIXED)
4420 /* GCC used to pass structures of the same size as integer types as
4421 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4422 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4423 passed padded downward, except that -mstrict-align further
4424 muddied the water in that multi-component structures of 2 and 4
4425 bytes in size were passed padded upward.
4427 The following arranges for best compatibility with previous
4428 versions of gcc, but removes the -mstrict-align dependency. */
4429 if (BYTES_BIG_ENDIAN)
4431 HOST_WIDE_INT size = 0;
4433 if (mode == BLKmode)
4435 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4436 size = int_size_in_bytes (type);
4439 size = GET_MODE_SIZE (mode);
4441 if (size == 1 || size == 2 || size == 4)
4447 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4449 if (type != 0 && AGGREGATE_TYPE_P (type))
4453 /* Fall back to the default. */
4454 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4457 /* If defined, a C expression that gives the alignment boundary, in bits,
4458 of an argument with the specified mode and type. If it is not defined,
4459 PARM_BOUNDARY is used for all arguments.
4461 V.4 wants long longs to be double word aligned.
4462 Doubleword align SPE vectors.
4463 Quadword align Altivec vectors.
4464 Quadword align large synthetic vector types. */
4467 function_arg_boundary (enum machine_mode mode, tree type)
4469 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4471 else if (SPE_VECTOR_MODE (mode)
4472 || (type && TREE_CODE (type) == VECTOR_TYPE
4473 && int_size_in_bytes (type) >= 8
4474 && int_size_in_bytes (type) < 16))
4476 else if (ALTIVEC_VECTOR_MODE (mode)
4477 || (type && TREE_CODE (type) == VECTOR_TYPE
4478 && int_size_in_bytes (type) >= 16))
4480 else if (rs6000_darwin64_abi && mode == BLKmode
4481 && type && TYPE_ALIGN (type) > 64)
4484 return PARM_BOUNDARY;
4487 /* For a function parm of MODE and TYPE, return the starting word in
4488 the parameter area. NWORDS of the parameter area are already used. */
4491 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4494 unsigned int parm_offset;
4496 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4497 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4498 return nwords + (-(parm_offset + nwords) & align);
4501 /* Compute the size (in words) of a function argument. */
4503 static unsigned long
4504 rs6000_arg_size (enum machine_mode mode, tree type)
4508 if (mode != BLKmode)
4509 size = GET_MODE_SIZE (mode);
4511 size = int_size_in_bytes (type);
4514 return (size + 3) >> 2;
4516 return (size + 7) >> 3;
4519 /* Use this to flush pending int fields. */
4522 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4523 HOST_WIDE_INT bitpos)
4525 unsigned int startbit, endbit;
4526 int intregs, intoffset;
4527 enum machine_mode mode;
4529 if (cum->intoffset == -1)
4532 intoffset = cum->intoffset;
4533 cum->intoffset = -1;
4535 if (intoffset % BITS_PER_WORD != 0)
4537 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4539 if (mode == BLKmode)
4541 /* We couldn't find an appropriate mode, which happens,
4542 e.g., in packed structs when there are 3 bytes to load.
4543 Back intoffset back to the beginning of the word in this
4545 intoffset = intoffset & -BITS_PER_WORD;
4549 startbit = intoffset & -BITS_PER_WORD;
4550 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4551 intregs = (endbit - startbit) / BITS_PER_WORD;
4552 cum->words += intregs;
4555 /* The darwin64 ABI calls for us to recurse down through structs,
4556 looking for elements passed in registers. Unfortunately, we have
4557 to track int register count here also because of misalignments
4558 in powerpc alignment mode. */
4561 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4563 HOST_WIDE_INT startbitpos)
4567 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4568 if (TREE_CODE (f) == FIELD_DECL)
4570 HOST_WIDE_INT bitpos = startbitpos;
4571 tree ftype = TREE_TYPE (f);
4572 enum machine_mode mode = TYPE_MODE (ftype);
4574 if (DECL_SIZE (f) != 0
4575 && host_integerp (bit_position (f), 1))
4576 bitpos += int_bit_position (f);
4578 /* ??? FIXME: else assume zero offset. */
4580 if (TREE_CODE (ftype) == RECORD_TYPE)
4581 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4582 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4584 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4585 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4586 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4588 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4590 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4594 else if (cum->intoffset == -1)
4595 cum->intoffset = bitpos;
4599 /* Update the data in CUM to advance over an argument
4600 of mode MODE and data type TYPE.
4601 (TYPE is null for libcalls where that information may not be available.)
4603 Note that for args passed by reference, function_arg will be called
4604 with MODE and TYPE set to that of the pointer to the arg, not the arg
4608 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4609 tree type, int named, int depth)
4613 /* Only tick off an argument if we're not recursing. */
4615 cum->nargs_prototype--;
4617 if (TARGET_ALTIVEC_ABI
4618 && (ALTIVEC_VECTOR_MODE (mode)
4619 || (type && TREE_CODE (type) == VECTOR_TYPE
4620 && int_size_in_bytes (type) == 16)))
4624 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4627 if (!TARGET_ALTIVEC)
4628 error ("cannot pass argument in vector register because"
4629 " altivec instructions are disabled, use -maltivec"
4632 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4633 even if it is going to be passed in a vector register.
4634 Darwin does the same for variable-argument functions. */
4635 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4636 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4646 /* Vector parameters must be 16-byte aligned. This places
4647 them at 2 mod 4 in terms of words in 32-bit mode, since
4648 the parameter save area starts at offset 24 from the
4649 stack. In 64-bit mode, they just have to start on an
4650 even word, since the parameter save area is 16-byte
4651 aligned. Space for GPRs is reserved even if the argument
4652 will be passed in memory. */
4654 align = (2 - cum->words) & 3;
4656 align = cum->words & 1;
4657 cum->words += align + rs6000_arg_size (mode, type);
4659 if (TARGET_DEBUG_ARG)
4661 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4663 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4664 cum->nargs_prototype, cum->prototype,
4665 GET_MODE_NAME (mode));
4669 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4671 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4674 else if (rs6000_darwin64_abi
4676 && TREE_CODE (type) == RECORD_TYPE
4677 && (size = int_size_in_bytes (type)) > 0)
4679 /* Variable sized types have size == -1 and are
4680 treated as if consisting entirely of ints.
4681 Pad to 16 byte boundary if needed. */
4682 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4683 && (cum->words % 2) != 0)
4685 /* For varargs, we can just go up by the size of the struct. */
4687 cum->words += (size + 7) / 8;
4690 /* It is tempting to say int register count just goes up by
4691 sizeof(type)/8, but this is wrong in a case such as
4692 { int; double; int; } [powerpc alignment]. We have to
4693 grovel through the fields for these too. */
4695 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4696 rs6000_darwin64_record_arg_advance_flush (cum,
4697 size * BITS_PER_UNIT);
4700 else if (DEFAULT_ABI == ABI_V4)
4702 if (TARGET_HARD_FLOAT && TARGET_FPRS
4703 && (mode == SFmode || mode == DFmode
4704 || (mode == TFmode && !TARGET_IEEEQUAD)))
4706 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
4707 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4710 cum->fregno = FP_ARG_V4_MAX_REG + 1;
4711 if (mode == DFmode || mode == TFmode)
4712 cum->words += cum->words & 1;
4713 cum->words += rs6000_arg_size (mode, type);
4718 int n_words = rs6000_arg_size (mode, type);
4719 int gregno = cum->sysv_gregno;
4721 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4722 (r7,r8) or (r9,r10). As does any other 2 word item such
4723 as complex int due to a historical mistake. */
4725 gregno += (1 - gregno) & 1;
4727 /* Multi-reg args are not split between registers and stack. */
4728 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4730 /* Long long and SPE vectors are aligned on the stack.
4731 So are other 2 word items such as complex int due to
4732 a historical mistake. */
4734 cum->words += cum->words & 1;
4735 cum->words += n_words;
4738 /* Note: continuing to accumulate gregno past when we've started
4739 spilling to the stack indicates the fact that we've started
4740 spilling to the stack to expand_builtin_saveregs. */
4741 cum->sysv_gregno = gregno + n_words;
4744 if (TARGET_DEBUG_ARG)
4746 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4747 cum->words, cum->fregno);
4748 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4749 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4750 fprintf (stderr, "mode = %4s, named = %d\n",
4751 GET_MODE_NAME (mode), named);
4756 int n_words = rs6000_arg_size (mode, type);
4757 int start_words = cum->words;
4758 int align_words = rs6000_parm_start (mode, type, start_words);
4760 cum->words = align_words + n_words;
4762 if (SCALAR_FLOAT_MODE_P (mode)
4763 && !DECIMAL_FLOAT_MODE_P (mode)
4764 && TARGET_HARD_FLOAT && TARGET_FPRS)
4765 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4767 if (TARGET_DEBUG_ARG)
4769 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4770 cum->words, cum->fregno);
4771 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4772 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4773 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
4774 named, align_words - start_words, depth);
4780 spe_build_register_parallel (enum machine_mode mode, int gregno)
4787 r1 = gen_rtx_REG (DImode, gregno);
4788 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4789 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
4792 r1 = gen_rtx_REG (DImode, gregno);
4793 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4794 r3 = gen_rtx_REG (DImode, gregno + 2);
4795 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4796 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
4803 /* Determine where to put a SIMD argument on the SPE. */
4805 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4808 int gregno = cum->sysv_gregno;
4810 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4811 are passed and returned in a pair of GPRs for ABI compatibility. */
4812 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
4814 int n_words = rs6000_arg_size (mode, type);
4816 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4818 gregno += (1 - gregno) & 1;
4820 /* Multi-reg args are not split between registers and stack. */
4821 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4824 return spe_build_register_parallel (mode, gregno);
4828 int n_words = rs6000_arg_size (mode, type);
4830 /* SPE vectors are put in odd registers. */
4831 if (n_words == 2 && (gregno & 1) == 0)
4834 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4837 enum machine_mode m = SImode;
4839 r1 = gen_rtx_REG (m, gregno);
4840 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4841 r2 = gen_rtx_REG (m, gregno + 1);
4842 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4843 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4850 if (gregno <= GP_ARG_MAX_REG)
4851 return gen_rtx_REG (mode, gregno);
4857 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4858 structure between cum->intoffset and bitpos to integer registers. */
4861 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4862 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
4864 enum machine_mode mode;
4866 unsigned int startbit, endbit;
4867 int this_regno, intregs, intoffset;
4870 if (cum->intoffset == -1)
4873 intoffset = cum->intoffset;
4874 cum->intoffset = -1;
4876 /* If this is the trailing part of a word, try to only load that
4877 much into the register. Otherwise load the whole register. Note
4878 that in the latter case we may pick up unwanted bits. It's not a
4879 problem at the moment but may wish to revisit. */
4881 if (intoffset % BITS_PER_WORD != 0)
4883 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4885 if (mode == BLKmode)
4887 /* We couldn't find an appropriate mode, which happens,
4888 e.g., in packed structs when there are 3 bytes to load.
4889 Back intoffset back to the beginning of the word in this
4891 intoffset = intoffset & -BITS_PER_WORD;
4898 startbit = intoffset & -BITS_PER_WORD;
4899 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4900 intregs = (endbit - startbit) / BITS_PER_WORD;
4901 this_regno = cum->words + intoffset / BITS_PER_WORD;
4903 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4906 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4910 intoffset /= BITS_PER_UNIT;
4913 regno = GP_ARG_MIN_REG + this_regno;
4914 reg = gen_rtx_REG (mode, regno);
4916 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4919 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4923 while (intregs > 0);
4926 /* Recursive workhorse for the following. */
4929 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4930 HOST_WIDE_INT startbitpos, rtx rvec[],
4935 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4936 if (TREE_CODE (f) == FIELD_DECL)
4938 HOST_WIDE_INT bitpos = startbitpos;
4939 tree ftype = TREE_TYPE (f);
4940 enum machine_mode mode = TYPE_MODE (ftype);
4942 if (DECL_SIZE (f) != 0
4943 && host_integerp (bit_position (f), 1))
4944 bitpos += int_bit_position (f);
4946 /* ??? FIXME: else assume zero offset. */
4948 if (TREE_CODE (ftype) == RECORD_TYPE)
4949 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4950 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
4955 case SCmode: mode = SFmode; break;
4956 case DCmode: mode = DFmode; break;
4957 case TCmode: mode = TFmode; break;
4961 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4963 = gen_rtx_EXPR_LIST (VOIDmode,
4964 gen_rtx_REG (mode, cum->fregno++),
4965 GEN_INT (bitpos / BITS_PER_UNIT));
4969 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4971 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4973 = gen_rtx_EXPR_LIST (VOIDmode,
4974 gen_rtx_REG (mode, cum->vregno++),
4975 GEN_INT (bitpos / BITS_PER_UNIT));
4977 else if (cum->intoffset == -1)
4978 cum->intoffset = bitpos;
4982 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4983 the register(s) to be used for each field and subfield of a struct
4984 being passed by value, along with the offset of where the
4985 register's value may be found in the block. FP fields go in FP
4986 register, vector fields go in vector registers, and everything
4987 else goes in int registers, packed as in memory.
4989 This code is also used for function return values. RETVAL indicates
4990 whether this is the case.
4992 Much of this is taken from the SPARC V9 port, which has a similar
4993 calling convention. */
4996 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4997 int named, bool retval)
4999 rtx rvec[FIRST_PSEUDO_REGISTER];
5000 int k = 1, kbase = 1;
5001 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5002 /* This is a copy; modifications are not visible to our caller. */
5003 CUMULATIVE_ARGS copy_cum = *orig_cum;
5004 CUMULATIVE_ARGS *cum = ©_cum;
5006 /* Pad to 16 byte boundary if needed. */
5007 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5008 && (cum->words % 2) != 0)
5015 /* Put entries into rvec[] for individual FP and vector fields, and
5016 for the chunks of memory that go in int regs. Note we start at
5017 element 1; 0 is reserved for an indication of using memory, and
5018 may or may not be filled in below. */
5019 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5020 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5022 /* If any part of the struct went on the stack put all of it there.
5023 This hack is because the generic code for
5024 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5025 parts of the struct are not at the beginning. */
5029 return NULL_RTX; /* doesn't go in registers at all */
5031 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5033 if (k > 1 || cum->use_stack)
5034 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5039 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5042 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5046 rtx rvec[GP_ARG_NUM_REG + 1];
5048 if (align_words >= GP_ARG_NUM_REG)
5051 n_units = rs6000_arg_size (mode, type);
5053 /* Optimize the simple case where the arg fits in one gpr, except in
5054 the case of BLKmode due to assign_parms assuming that registers are
5055 BITS_PER_WORD wide. */
5057 || (n_units == 1 && mode != BLKmode))
5058 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5061 if (align_words + n_units > GP_ARG_NUM_REG)
5062 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5063 using a magic NULL_RTX component.
5064 This is not strictly correct. Only some of the arg belongs in
5065 memory, not all of it. However, the normal scheme using
5066 function_arg_partial_nregs can result in unusual subregs, eg.
5067 (subreg:SI (reg:DF) 4), which are not handled well. The code to
5068 store the whole arg to memory is often more efficient than code
5069 to store pieces, and we know that space is available in the right
5070 place for the whole arg. */
5071 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5076 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5077 rtx off = GEN_INT (i++ * 4);
5078 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5080 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5082 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5085 /* Determine where to put an argument to a function.
5086 Value is zero to push the argument on the stack,
5087 or a hard register in which to store the argument.
5089 MODE is the argument's machine mode.
5090 TYPE is the data type of the argument (as a tree).
5091 This is null for libcalls where that information may
5093 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5094 the preceding args and about the function being called. It is
5095 not modified in this routine.
5096 NAMED is nonzero if this argument is a named parameter
5097 (otherwise it is an extra parameter matching an ellipsis).
5099 On RS/6000 the first eight words of non-FP are normally in registers
5100 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5101 Under V.4, the first 8 FP args are in registers.
5103 If this is floating-point and no prototype is specified, we use
5104 both an FP and integer register (or possibly FP reg and stack). Library
5105 functions (when CALL_LIBCALL is set) always have the proper types for args,
5106 so we can pass the FP value just in one register. emit_library_function
5107 doesn't support PARALLEL anyway.
5109 Note that for args passed by reference, function_arg will be called
5110 with MODE and TYPE set to that of the pointer to the arg, not the arg
5114 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5115 tree type, int named)
5117 enum rs6000_abi abi = DEFAULT_ABI;
5119 /* Return a marker to indicate whether CR1 needs to set or clear the
5120 bit that V.4 uses to say fp args were passed in registers.
5121 Assume that we don't need the marker for software floating point,
5122 or compiler generated library calls. */
5123 if (mode == VOIDmode)
5126 && (cum->call_cookie & CALL_LIBCALL) == 0
5128 || (cum->nargs_prototype < 0
5129 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5131 /* For the SPE, we need to crxor CR6 always. */
5133 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5134 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5135 return GEN_INT (cum->call_cookie
5136 | ((cum->fregno == FP_ARG_MIN_REG)
5137 ? CALL_V4_SET_FP_ARGS
5138 : CALL_V4_CLEAR_FP_ARGS));
5141 return GEN_INT (cum->call_cookie);
5144 if (rs6000_darwin64_abi && mode == BLKmode
5145 && TREE_CODE (type) == RECORD_TYPE)
5147 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5148 if (rslt != NULL_RTX)
5150 /* Else fall through to usual handling. */
5153 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5154 if (TARGET_64BIT && ! cum->prototype)
5156 /* Vector parameters get passed in vector register
5157 and also in GPRs or memory, in absence of prototype. */
5160 align_words = (cum->words + 1) & ~1;
5162 if (align_words >= GP_ARG_NUM_REG)
5168 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5170 return gen_rtx_PARALLEL (mode,
5172 gen_rtx_EXPR_LIST (VOIDmode,
5174 gen_rtx_EXPR_LIST (VOIDmode,
5175 gen_rtx_REG (mode, cum->vregno),
5179 return gen_rtx_REG (mode, cum->vregno);
5180 else if (TARGET_ALTIVEC_ABI
5181 && (ALTIVEC_VECTOR_MODE (mode)
5182 || (type && TREE_CODE (type) == VECTOR_TYPE
5183 && int_size_in_bytes (type) == 16)))
5185 if (named || abi == ABI_V4)
5189 /* Vector parameters to varargs functions under AIX or Darwin
5190 get passed in memory and possibly also in GPRs. */
5191 int align, align_words, n_words;
5192 enum machine_mode part_mode;
5194 /* Vector parameters must be 16-byte aligned. This places them at
5195 2 mod 4 in terms of words in 32-bit mode, since the parameter
5196 save area starts at offset 24 from the stack. In 64-bit mode,
5197 they just have to start on an even word, since the parameter
5198 save area is 16-byte aligned. */
5200 align = (2 - cum->words) & 3;
5202 align = cum->words & 1;
5203 align_words = cum->words + align;
5205 /* Out of registers? Memory, then. */
5206 if (align_words >= GP_ARG_NUM_REG)
5209 if (TARGET_32BIT && TARGET_POWERPC64)
5210 return rs6000_mixed_function_arg (mode, type, align_words);
5212 /* The vector value goes in GPRs. Only the part of the
5213 value in GPRs is reported here. */
5215 n_words = rs6000_arg_size (mode, type);
5216 if (align_words + n_words > GP_ARG_NUM_REG)
5217 /* Fortunately, there are only two possibilities, the value
5218 is either wholly in GPRs or half in GPRs and half not. */
5221 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5224 else if (TARGET_SPE_ABI && TARGET_SPE
5225 && (SPE_VECTOR_MODE (mode)
5226 || (TARGET_E500_DOUBLE && (mode == DFmode
5227 || mode == DCmode))))
5228 return rs6000_spe_function_arg (cum, mode, type);
5230 else if (abi == ABI_V4)
5232 if (TARGET_HARD_FLOAT && TARGET_FPRS
5233 && (mode == SFmode || mode == DFmode
5234 || (mode == TFmode && !TARGET_IEEEQUAD)))
5236 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
5237 return gen_rtx_REG (mode, cum->fregno);
5243 int n_words = rs6000_arg_size (mode, type);
5244 int gregno = cum->sysv_gregno;
5246 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5247 (r7,r8) or (r9,r10). As does any other 2 word item such
5248 as complex int due to a historical mistake. */
5250 gregno += (1 - gregno) & 1;
5252 /* Multi-reg args are not split between registers and stack. */
5253 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5256 if (TARGET_32BIT && TARGET_POWERPC64)
5257 return rs6000_mixed_function_arg (mode, type,
5258 gregno - GP_ARG_MIN_REG);
5259 return gen_rtx_REG (mode, gregno);
5264 int align_words = rs6000_parm_start (mode, type, cum->words);
5266 if (USE_FP_FOR_ARG_P (cum, mode, type))
5268 rtx rvec[GP_ARG_NUM_REG + 1];
5272 enum machine_mode fmode = mode;
5273 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5275 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5277 /* Currently, we only ever need one reg here because complex
5278 doubles are split. */
5279 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);
5281 /* Long double split over regs and memory. */
5285 /* Do we also need to pass this arg in the parameter save
5288 && (cum->nargs_prototype <= 0
5289 || (DEFAULT_ABI == ABI_AIX
5291 && align_words >= GP_ARG_NUM_REG)));
5293 if (!needs_psave && mode == fmode)
5294 return gen_rtx_REG (fmode, cum->fregno);
5299 /* Describe the part that goes in gprs or the stack.
5300 This piece must come first, before the fprs. */
5301 if (align_words < GP_ARG_NUM_REG)
5303 unsigned long n_words = rs6000_arg_size (mode, type);
5305 if (align_words + n_words > GP_ARG_NUM_REG
5306 || (TARGET_32BIT && TARGET_POWERPC64))
5308 /* If this is partially on the stack, then we only
5309 include the portion actually in registers here. */
5310 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5313 if (align_words + n_words > GP_ARG_NUM_REG)
5314 /* Not all of the arg fits in gprs. Say that it
5315 goes in memory too, using a magic NULL_RTX
5316 component. Also see comment in
5317 rs6000_mixed_function_arg for why the normal
5318 function_arg_partial_nregs scheme doesn't work
5320 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5324 r = gen_rtx_REG (rmode,
5325 GP_ARG_MIN_REG + align_words);
5326 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5327 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5329 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5333 /* The whole arg fits in gprs. */
5334 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5335 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5339 /* It's entirely in memory. */
5340 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5343 /* Describe where this piece goes in the fprs. */
5344 r = gen_rtx_REG (fmode, cum->fregno);
5345 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5347 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5349 else if (align_words < GP_ARG_NUM_REG)
5351 if (TARGET_32BIT && TARGET_POWERPC64)
5352 return rs6000_mixed_function_arg (mode, type, align_words);
5354 if (mode == BLKmode)
5357 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5364 /* For an arg passed partly in registers and partly in memory, this is
5365 the number of bytes passed in registers. For args passed entirely in
5366 registers or entirely in memory, zero. When an arg is described by a
5367 PARALLEL, perhaps using more than one register type, this function
5368 returns the number of bytes used by the first element of the PARALLEL. */
5371 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5372 tree type, bool named)
5377 if (DEFAULT_ABI == ABI_V4)
5380 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5381 && cum->nargs_prototype >= 0)
5384 /* In this complicated case we just disable the partial_nregs code. */
5385 if (rs6000_darwin64_abi && mode == BLKmode
5386 && TREE_CODE (type) == RECORD_TYPE
5387 && int_size_in_bytes (type) > 0)
5390 align_words = rs6000_parm_start (mode, type, cum->words);
5392 if (USE_FP_FOR_ARG_P (cum, mode, type))
5394 /* If we are passing this arg in the fixed parameter save area
5395 (gprs or memory) as well as fprs, then this function should
5396 return the number of partial bytes passed in the parameter
5397 save area rather than partial bytes passed in fprs. */
5399 && (cum->nargs_prototype <= 0
5400 || (DEFAULT_ABI == ABI_AIX
5402 && align_words >= GP_ARG_NUM_REG)))
5404 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
5405 > FP_ARG_MAX_REG + 1)
5406 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5407 else if (cum->nargs_prototype >= 0)
5411 if (align_words < GP_ARG_NUM_REG
5412 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5413 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5415 if (ret != 0 && TARGET_DEBUG_ARG)
5416 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5421 /* A C expression that indicates when an argument must be passed by
5422 reference. If nonzero for an argument, a copy of that argument is
5423 made in memory and a pointer to the argument is passed instead of
5424 the argument itself. The pointer is passed in whatever way is
5425 appropriate for passing a pointer to that type.
5427 Under V.4, aggregates and long double are passed by reference.
5429 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5430 reference unless the AltiVec vector extension ABI is in force.
5432 As an extension to all ABIs, variable sized types are passed by
5436 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5437 enum machine_mode mode, tree type,
5438 bool named ATTRIBUTE_UNUSED)
5440 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
5442 if (TARGET_DEBUG_ARG)
5443 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5450 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5452 if (TARGET_DEBUG_ARG)
5453 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5457 if (int_size_in_bytes (type) < 0)
5459 if (TARGET_DEBUG_ARG)
5460 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5464 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5465 modes only exist for GCC vector types if -maltivec. */
5466 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5468 if (TARGET_DEBUG_ARG)
5469 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5473 /* Pass synthetic vectors in memory. */
5474 if (TREE_CODE (type) == VECTOR_TYPE
5475 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5477 static bool warned_for_pass_big_vectors = false;
5478 if (TARGET_DEBUG_ARG)
5479 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5480 if (!warned_for_pass_big_vectors)
5482 warning (0, "GCC vector passed by reference: "
5483 "non-standard ABI extension with no compatibility guarantee");
5484 warned_for_pass_big_vectors = true;
5493 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5496 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5501 for (i = 0; i < nregs; i++)
5503 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5504 if (reload_completed)
5506 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5509 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5510 i * GET_MODE_SIZE (reg_mode));
5513 tem = replace_equiv_address (tem, XEXP (tem, 0));
5517 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5521 /* Perform any needed actions needed for a function that is receiving a
5522 variable number of arguments.
5526 MODE and TYPE are the mode and type of the current parameter.
5528 PRETEND_SIZE is a variable that should be set to the amount of stack
5529 that must be pushed by the prolog to pretend that our caller pushed
5532 Normally, this macro will push all remaining incoming registers on the
5533 stack and set PRETEND_SIZE to the length of the registers pushed. */
5536 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5537 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5540 CUMULATIVE_ARGS next_cum;
5541 int reg_size = TARGET_32BIT ? 4 : 8;
5542 rtx save_area = NULL_RTX, mem;
5543 int first_reg_offset, set;
5545 /* Skip the last named argument. */
5547 function_arg_advance (&next_cum, mode, type, 1, 0);
5549 if (DEFAULT_ABI == ABI_V4)
5551 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5555 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
5556 HOST_WIDE_INT offset = 0;
5558 /* Try to optimize the size of the varargs save area.
5559 The ABI requires that ap.reg_save_area is doubleword
5560 aligned, but we don't need to allocate space for all
5561 the bytes, only those to which we actually will save
5563 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
5564 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
5565 if (TARGET_HARD_FLOAT && TARGET_FPRS
5566 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5567 && cfun->va_list_fpr_size)
5570 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
5571 * UNITS_PER_FP_WORD;
5572 if (cfun->va_list_fpr_size
5573 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5574 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
5576 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5577 * UNITS_PER_FP_WORD;
5581 offset = -((first_reg_offset * reg_size) & ~7);
5582 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
5584 gpr_reg_num = cfun->va_list_gpr_size;
5585 if (reg_size == 4 && (first_reg_offset & 1))
5588 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
5591 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
5593 - (int) (GP_ARG_NUM_REG * reg_size);
5595 if (gpr_size + fpr_size)
5598 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
5599 gcc_assert (GET_CODE (reg_save_area) == MEM);
5600 reg_save_area = XEXP (reg_save_area, 0);
5601 if (GET_CODE (reg_save_area) == PLUS)
5603 gcc_assert (XEXP (reg_save_area, 0)
5604 == virtual_stack_vars_rtx);
5605 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
5606 offset += INTVAL (XEXP (reg_save_area, 1));
5609 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
5612 cfun->machine->varargs_save_offset = offset;
5613 save_area = plus_constant (virtual_stack_vars_rtx, offset);
5618 first_reg_offset = next_cum.words;
5619 save_area = virtual_incoming_args_rtx;
5621 if (targetm.calls.must_pass_in_stack (mode, type))
5622 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5625 set = get_varargs_alias_set ();
5626 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5627 && cfun->va_list_gpr_size)
5629 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5631 if (va_list_gpr_counter_field)
5633 /* V4 va_list_gpr_size counts number of registers needed. */
5634 if (nregs > cfun->va_list_gpr_size)
5635 nregs = cfun->va_list_gpr_size;
5639 /* char * va_list instead counts number of bytes needed. */
5640 if (nregs > cfun->va_list_gpr_size / reg_size)
5641 nregs = cfun->va_list_gpr_size / reg_size;
5644 mem = gen_rtx_MEM (BLKmode,
5645 plus_constant (save_area,
5646 first_reg_offset * reg_size));
5647 MEM_NOTRAP_P (mem) = 1;
5648 set_mem_alias_set (mem, set);
5649 set_mem_align (mem, BITS_PER_WORD);
5651 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5655 /* Save FP registers if needed. */
5656 if (DEFAULT_ABI == ABI_V4
5657 && TARGET_HARD_FLOAT && TARGET_FPRS
5659 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5660 && cfun->va_list_fpr_size)
5662 int fregno = next_cum.fregno, nregs;
5663 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5664 rtx lab = gen_label_rtx ();
5665 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
5666 * UNITS_PER_FP_WORD);
5669 (gen_rtx_SET (VOIDmode,
5671 gen_rtx_IF_THEN_ELSE (VOIDmode,
5672 gen_rtx_NE (VOIDmode, cr1,
5674 gen_rtx_LABEL_REF (VOIDmode, lab),
5678 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
5679 fregno++, off += UNITS_PER_FP_WORD, nregs++)
5681 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5682 MEM_NOTRAP_P (mem) = 1;
5683 set_mem_alias_set (mem, set);
5684 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5685 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5692 /* Create the va_list data type. */
5695 rs6000_build_builtin_va_list (void)
5697 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5699 /* For AIX, prefer 'char *' because that's what the system
5700 header files like. */
5701 if (DEFAULT_ABI != ABI_V4)
5702 return build_pointer_type (char_type_node);
5704 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5705 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5707 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5708 unsigned_char_type_node);
5709 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5710 unsigned_char_type_node);
5711 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5713 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5714 short_unsigned_type_node);
5715 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5717 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5720 va_list_gpr_counter_field = f_gpr;
5721 va_list_fpr_counter_field = f_fpr;
5723 DECL_FIELD_CONTEXT (f_gpr) = record;
5724 DECL_FIELD_CONTEXT (f_fpr) = record;
5725 DECL_FIELD_CONTEXT (f_res) = record;
5726 DECL_FIELD_CONTEXT (f_ovf) = record;
5727 DECL_FIELD_CONTEXT (f_sav) = record;
5729 TREE_CHAIN (record) = type_decl;
5730 TYPE_NAME (record) = type_decl;
5731 TYPE_FIELDS (record) = f_gpr;
5732 TREE_CHAIN (f_gpr) = f_fpr;
5733 TREE_CHAIN (f_fpr) = f_res;
5734 TREE_CHAIN (f_res) = f_ovf;
5735 TREE_CHAIN (f_ovf) = f_sav;
5737 layout_type (record);
5739 /* The correct type is an array type of one element. */
5740 return build_array_type (record, build_index_type (size_zero_node));
5743 /* Implement va_start. */
5746 rs6000_va_start (tree valist, rtx nextarg)
5748 HOST_WIDE_INT words, n_gpr, n_fpr;
5749 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5750 tree gpr, fpr, ovf, sav, t;
5752 /* Only SVR4 needs something special. */
5753 if (DEFAULT_ABI != ABI_V4)
5755 std_expand_builtin_va_start (valist, nextarg);
5759 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5760 f_fpr = TREE_CHAIN (f_gpr);
5761 f_res = TREE_CHAIN (f_fpr);
5762 f_ovf = TREE_CHAIN (f_res);
5763 f_sav = TREE_CHAIN (f_ovf);
5765 valist = build_va_arg_indirect_ref (valist);
5766 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5767 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5768 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5769 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5771 /* Count number of gp and fp argument registers used. */
5772 words = current_function_args_info.words;
5773 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5775 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5778 if (TARGET_DEBUG_ARG)
5779 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5780 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5781 words, n_gpr, n_fpr);
5783 if (cfun->va_list_gpr_size)
5785 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5786 build_int_cst (NULL_TREE, n_gpr));
5787 TREE_SIDE_EFFECTS (t) = 1;
5788 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5791 if (cfun->va_list_fpr_size)
5793 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5794 build_int_cst (NULL_TREE, n_fpr));
5795 TREE_SIDE_EFFECTS (t) = 1;
5796 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5799 /* Find the overflow area. */
5800 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5802 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t,
5803 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5804 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5805 TREE_SIDE_EFFECTS (t) = 1;
5806 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5808 /* If there were no va_arg invocations, don't set up the register
5810 if (!cfun->va_list_gpr_size
5811 && !cfun->va_list_fpr_size
5812 && n_gpr < GP_ARG_NUM_REG
5813 && n_fpr < FP_ARG_V4_MAX_REG)
5816 /* Find the register save area. */
5817 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5818 if (cfun->machine->varargs_save_offset)
5819 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
5820 build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset));
5821 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5822 TREE_SIDE_EFFECTS (t) = 1;
5823 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5826 /* Implement va_arg. */
5829 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5831 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5832 tree gpr, fpr, ovf, sav, reg, t, u;
5833 int size, rsize, n_reg, sav_ofs, sav_scale;
5834 tree lab_false, lab_over, addr;
5836 tree ptrtype = build_pointer_type (type);
5838 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5840 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5841 return build_va_arg_indirect_ref (t);
5844 if (DEFAULT_ABI != ABI_V4)
5846 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5848 tree elem_type = TREE_TYPE (type);
5849 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5850 int elem_size = GET_MODE_SIZE (elem_mode);
5852 if (elem_size < UNITS_PER_WORD)
5854 tree real_part, imag_part;
5855 tree post = NULL_TREE;
5857 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5859 /* Copy the value into a temporary, lest the formal temporary
5860 be reused out from under us. */
5861 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5862 append_to_statement_list (post, pre_p);
5864 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5867 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
5871 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5874 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5875 f_fpr = TREE_CHAIN (f_gpr);
5876 f_res = TREE_CHAIN (f_fpr);
5877 f_ovf = TREE_CHAIN (f_res);
5878 f_sav = TREE_CHAIN (f_ovf);
5880 valist = build_va_arg_indirect_ref (valist);
5881 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5882 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5883 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5884 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5886 size = int_size_in_bytes (type);
5887 rsize = (size + 3) / 4;
5890 if (TARGET_HARD_FLOAT && TARGET_FPRS
5891 && (TYPE_MODE (type) == SFmode
5892 || TYPE_MODE (type) == DFmode
5893 || TYPE_MODE (type) == TFmode))
5895 /* FP args go in FP registers, if present. */
5897 n_reg = (size + 7) / 8;
5900 if (TYPE_MODE (type) != SFmode)
5905 /* Otherwise into GP registers. */
5914 /* Pull the value out of the saved registers.... */
5917 addr = create_tmp_var (ptr_type_node, "addr");
5918 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5920 /* AltiVec vectors never go in registers when -mabi=altivec. */
5921 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5925 lab_false = create_artificial_label ();
5926 lab_over = create_artificial_label ();
5928 /* Long long and SPE vectors are aligned in the registers.
5929 As are any other 2 gpr item such as complex int due to a
5930 historical mistake. */
5932 if (n_reg == 2 && reg == gpr)
5934 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5935 size_int (n_reg - 1));
5936 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5939 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5940 t = build2 (GE_EXPR, boolean_type_node, u, t);
5941 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5942 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5943 gimplify_and_add (t, pre_p);
5947 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5949 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5950 u = build1 (CONVERT_EXPR, integer_type_node, u);
5951 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5952 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5954 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5955 gimplify_and_add (t, pre_p);
5957 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5958 gimplify_and_add (t, pre_p);
5960 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5961 append_to_statement_list (t, pre_p);
5963 if ((n_reg == 2 && reg != gpr) || n_reg > 2)
5965 /* Ensure that we don't find any more args in regs.
5966 Alignment has taken care of the n_reg == 2 gpr case. */
5967 t = build2 (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
5968 gimplify_and_add (t, pre_p);
5972 /* ... otherwise out of the overflow area. */
5974 /* Care for on-stack alignment if needed. */
5978 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
5979 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5980 build_int_cst (NULL_TREE, -align));
5982 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5984 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5985 gimplify_and_add (u, pre_p);
5987 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
5988 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5989 gimplify_and_add (t, pre_p);
5993 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5994 append_to_statement_list (t, pre_p);
5997 addr = fold_convert (ptrtype, addr);
5998 return build_va_arg_indirect_ref (addr);
6004 def_builtin (int mask, const char *name, tree type, int code)
6006 if (mask & target_flags)
6008 if (rs6000_builtin_decls[code])
6011 rs6000_builtin_decls[code] =
6012 lang_hooks.builtin_function (name, type, code, BUILT_IN_MD,
6017 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6019 static const struct builtin_description bdesc_3arg[] =
6021 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6022 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6023 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6024 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6025 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6026 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6027 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6028 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6029 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6030 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6031 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6032 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6033 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6034 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6035 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6036 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6037 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6038 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6039 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6040 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6041 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6042 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6043 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6045 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6046 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6047 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6048 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6049 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6050 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6051 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6052 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6053 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6054 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6055 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6056 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6057 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6058 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6059 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6062 /* DST operations: void foo (void *, const int, const char). */
6064 static const struct builtin_description bdesc_dst[] =
6066 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6067 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6068 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6069 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6071 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6072 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6073 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6074 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6077 /* Simple binary operations: VECc = foo (VECa, VECb). */
6079 static struct builtin_description bdesc_2arg[] =
6081 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6082 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6083 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6084 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6085 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6086 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6087 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6088 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6089 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6090 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6091 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6092 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6093 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6094 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6095 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6096 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6097 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6098 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6099 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6100 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6101 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6102 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6103 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6104 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6105 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6106 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6107 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6108 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6109 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6110 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6111 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6112 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6113 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6114 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6115 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6116 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6117 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6118 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6119 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6120 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6121 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6122 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6123 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6124 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6125 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6126 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6127 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6128 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6129 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6130 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6131 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6132 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6133 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6134 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6135 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6136 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6137 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6138 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6139 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6140 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6141 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6142 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6143 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6144 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6145 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6146 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6147 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6148 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6149 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6150 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6151 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6152 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6153 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6154 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6155 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6156 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6157 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6158 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6159 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6160 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6161 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6162 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6163 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6164 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6165 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6166 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6167 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6168 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6169 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6170 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6171 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6172 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6173 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6174 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6175 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6176 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6177 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6178 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6179 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6180 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6181 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6182 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6183 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6184 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6185 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6186 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6187 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6188 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6189 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6190 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6191 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6193 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6194 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6195 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6196 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6197 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6198 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6199 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6200 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6201 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6202 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6203 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6204 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6205 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6206 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6207 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6208 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6209 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6210 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6211 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6212 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6213 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6214 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6215 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6216 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6217 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6218 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6219 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6220 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6221 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6222 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6223 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6224 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6225 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6226 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6227 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6228 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6229 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6230 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6231 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6232 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6233 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6234 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6235 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6236 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6237 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6238 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6239 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6240 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6241 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6242 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6243 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6244 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6245 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6246 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6247 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6248 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6249 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6250 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6251 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6252 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6253 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6254 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6255 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6256 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6257 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6258 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6259 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6260 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6261 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6262 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6263 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6264 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6265 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6266 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6267 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6268 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6269 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6270 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6271 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6272 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6273 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6274 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6275 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6276 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6277 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6278 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6279 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6280 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6281 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6282 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6283 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6284 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6285 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6286 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6287 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6288 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6289 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6290 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6291 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6292 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6293 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6294 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6295 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6296 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6297 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6298 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6299 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6300 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6301 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6302 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6303 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6304 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6305 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6306 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6307 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6308 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6309 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6310 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6311 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6312 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6313 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6314 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6315 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6316 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6317 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6318 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6319 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6321 /* Place holder, leave as first spe builtin. */
6322 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6323 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6324 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6325 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6326 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6327 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6328 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6329 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6330 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6331 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6332 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6333 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6334 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6335 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6336 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6337 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6338 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6339 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6340 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6341 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6342 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6343 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6344 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6345 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6346 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6347 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6348 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6349 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6350 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6351 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6352 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6353 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6354 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6355 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6356 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6357 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6358 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6359 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6360 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6361 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6362 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6363 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6364 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6365 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6366 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6367 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6368 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6369 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6370 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6371 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6372 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6373 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6374 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6375 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6376 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6377 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6378 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6379 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6380 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6381 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6382 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6383 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6384 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6385 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6386 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6387 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6388 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6389 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6390 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6391 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6392 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6393 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6394 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6395 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6396 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6397 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6398 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6399 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6400 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6401 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6402 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6403 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6404 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6405 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6406 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6407 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6408 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6409 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6410 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6411 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6412 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6413 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6414 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6415 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6416 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6417 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6418 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6419 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6420 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6421 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6422 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6423 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6424 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6425 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6426 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6427 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6428 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6429 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6430 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6432 /* SPE binary operations expecting a 5-bit unsigned literal. */
6433 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6435 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6436 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6437 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6438 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6439 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6440 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6441 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6442 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6443 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6444 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6445 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6446 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6447 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6448 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6449 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6450 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6451 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6452 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6453 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6454 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6455 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6456 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6457 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6458 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6459 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6460 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6462 /* Place-holder. Leave as last binary SPE builtin. */
6463 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6466 /* AltiVec predicates. */
6468 struct builtin_description_predicates
6470 const unsigned int mask;
6471 const enum insn_code icode;
6473 const char *const name;
6474 const enum rs6000_builtins code;
6477 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6479 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6480 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6481 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6482 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6483 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6484 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6485 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6486 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6487 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6488 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6489 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6490 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6491 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6493 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6494 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6495 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6498 /* SPE predicates. */
6499 static struct builtin_description bdesc_spe_predicates[] =
6501 /* Place-holder. Leave as first. */
6502 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6503 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6504 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6505 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6506 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6507 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6508 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6509 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6510 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6511 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6512 /* Place-holder. Leave as last. */
6513 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6516 /* SPE evsel predicates. */
6517 static struct builtin_description bdesc_spe_evsel[] =
6519 /* Place-holder. Leave as first. */
6520 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6521 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6522 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6523 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6524 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6525 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6526 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6527 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6528 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6529 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6530 /* Place-holder. Leave as last. */
6531 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6534 /* ABS* operations. */
6536 static const struct builtin_description bdesc_abs[] =
6538 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6539 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6540 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6541 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6542 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6543 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6544 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6547 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6550 static struct builtin_description bdesc_1arg[] =
6552 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6553 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6554 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6555 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6556 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6557 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6558 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6559 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6560 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6561 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6562 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6563 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6564 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6565 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6566 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6567 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6568 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6570 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6571 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6572 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6573 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6574 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6575 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6576 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6577 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6578 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6579 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6580 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
6581 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
6582 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
6583 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
6584 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
6585 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
6586 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
6587 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
6588 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
6590 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6591 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6592 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6593 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6594 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6595 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6596 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6597 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6598 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6599 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6600 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6601 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6602 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6603 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6604 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6605 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6606 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6607 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6608 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6609 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6610 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6611 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6612 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6613 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6614 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6615 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6616 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6617 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6618 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6619 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6621 /* Place-holder. Leave as last unary SPE builtin. */
6622 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
6626 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6629 tree arg0 = TREE_VALUE (arglist);
6630 rtx op0 = expand_normal (arg0);
6631 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6632 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6634 if (icode == CODE_FOR_nothing)
6635 /* Builtin not supported on this processor. */
6638 /* If we got invalid arguments bail out before generating bad rtl. */
6639 if (arg0 == error_mark_node)
6642 if (icode == CODE_FOR_altivec_vspltisb
6643 || icode == CODE_FOR_altivec_vspltish
6644 || icode == CODE_FOR_altivec_vspltisw
6645 || icode == CODE_FOR_spe_evsplatfi
6646 || icode == CODE_FOR_spe_evsplati)
6648 /* Only allow 5-bit *signed* literals. */
6649 if (GET_CODE (op0) != CONST_INT
6650 || INTVAL (op0) > 15
6651 || INTVAL (op0) < -16)
6653 error ("argument 1 must be a 5-bit signed literal");
6659 || GET_MODE (target) != tmode
6660 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6661 target = gen_reg_rtx (tmode);
6663 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6664 op0 = copy_to_mode_reg (mode0, op0);
6666 pat = GEN_FCN (icode) (target, op0);
6675 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6677 rtx pat, scratch1, scratch2;
6678 tree arg0 = TREE_VALUE (arglist);
6679 rtx op0 = expand_normal (arg0);
6680 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6681 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6683 /* If we have invalid arguments, bail out before generating bad rtl. */
6684 if (arg0 == error_mark_node)
6688 || GET_MODE (target) != tmode
6689 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6690 target = gen_reg_rtx (tmode);
6692 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6693 op0 = copy_to_mode_reg (mode0, op0);
6695 scratch1 = gen_reg_rtx (mode0);
6696 scratch2 = gen_reg_rtx (mode0);
6698 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6707 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6710 tree arg0 = TREE_VALUE (arglist);
6711 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6712 rtx op0 = expand_normal (arg0);
6713 rtx op1 = expand_normal (arg1);
6714 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6715 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6716 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6718 if (icode == CODE_FOR_nothing)
6719 /* Builtin not supported on this processor. */
6722 /* If we got invalid arguments bail out before generating bad rtl. */
6723 if (arg0 == error_mark_node || arg1 == error_mark_node)
6726 if (icode == CODE_FOR_altivec_vcfux
6727 || icode == CODE_FOR_altivec_vcfsx
6728 || icode == CODE_FOR_altivec_vctsxs
6729 || icode == CODE_FOR_altivec_vctuxs
6730 || icode == CODE_FOR_altivec_vspltb
6731 || icode == CODE_FOR_altivec_vsplth
6732 || icode == CODE_FOR_altivec_vspltw
6733 || icode == CODE_FOR_spe_evaddiw
6734 || icode == CODE_FOR_spe_evldd
6735 || icode == CODE_FOR_spe_evldh
6736 || icode == CODE_FOR_spe_evldw
6737 || icode == CODE_FOR_spe_evlhhesplat
6738 || icode == CODE_FOR_spe_evlhhossplat
6739 || icode == CODE_FOR_spe_evlhhousplat
6740 || icode == CODE_FOR_spe_evlwhe
6741 || icode == CODE_FOR_spe_evlwhos
6742 || icode == CODE_FOR_spe_evlwhou
6743 || icode == CODE_FOR_spe_evlwhsplat
6744 || icode == CODE_FOR_spe_evlwwsplat
6745 || icode == CODE_FOR_spe_evrlwi
6746 || icode == CODE_FOR_spe_evslwi
6747 || icode == CODE_FOR_spe_evsrwis
6748 || icode == CODE_FOR_spe_evsubifw
6749 || icode == CODE_FOR_spe_evsrwiu)
6751 /* Only allow 5-bit unsigned literals. */
6753 if (TREE_CODE (arg1) != INTEGER_CST
6754 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6756 error ("argument 2 must be a 5-bit unsigned literal");
6762 || GET_MODE (target) != tmode
6763 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6764 target = gen_reg_rtx (tmode);
6766 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6767 op0 = copy_to_mode_reg (mode0, op0);
6768 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6769 op1 = copy_to_mode_reg (mode1, op1);
6771 pat = GEN_FCN (icode) (target, op0, op1);
6780 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6781 tree arglist, rtx target)
6784 tree cr6_form = TREE_VALUE (arglist);
6785 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6786 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6787 rtx op0 = expand_normal (arg0);
6788 rtx op1 = expand_normal (arg1);
6789 enum machine_mode tmode = SImode;
6790 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6791 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6794 if (TREE_CODE (cr6_form) != INTEGER_CST)
6796 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6800 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6802 gcc_assert (mode0 == mode1);
6804 /* If we have invalid arguments, bail out before generating bad rtl. */
6805 if (arg0 == error_mark_node || arg1 == error_mark_node)
6809 || GET_MODE (target) != tmode
6810 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6811 target = gen_reg_rtx (tmode);
6813 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6814 op0 = copy_to_mode_reg (mode0, op0);
6815 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6816 op1 = copy_to_mode_reg (mode1, op1);
6818 scratch = gen_reg_rtx (mode0);
6820 pat = GEN_FCN (icode) (scratch, op0, op1,
6821 gen_rtx_SYMBOL_REF (Pmode, opcode));
6826 /* The vec_any* and vec_all* predicates use the same opcodes for two
6827 different operations, but the bits in CR6 will be different
6828 depending on what information we want. So we have to play tricks
6829 with CR6 to get the right bits out.
6831 If you think this is disgusting, look at the specs for the
6832 AltiVec predicates. */
6834 switch (cr6_form_int)
6837 emit_insn (gen_cr6_test_for_zero (target));
6840 emit_insn (gen_cr6_test_for_zero_reverse (target));
6843 emit_insn (gen_cr6_test_for_lt (target));
6846 emit_insn (gen_cr6_test_for_lt_reverse (target));
6849 error ("argument 1 of __builtin_altivec_predicate is out of range");
6857 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6860 tree arg0 = TREE_VALUE (arglist);
6861 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6862 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6863 enum machine_mode mode0 = Pmode;
6864 enum machine_mode mode1 = Pmode;
6865 rtx op0 = expand_normal (arg0);
6866 rtx op1 = expand_normal (arg1);
6868 if (icode == CODE_FOR_nothing)
6869 /* Builtin not supported on this processor. */
6872 /* If we got invalid arguments bail out before generating bad rtl. */
6873 if (arg0 == error_mark_node || arg1 == error_mark_node)
6877 || GET_MODE (target) != tmode
6878 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6879 target = gen_reg_rtx (tmode);
6881 op1 = copy_to_mode_reg (mode1, op1);
6883 if (op0 == const0_rtx)
6885 addr = gen_rtx_MEM (tmode, op1);
6889 op0 = copy_to_mode_reg (mode0, op0);
6890 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6893 pat = GEN_FCN (icode) (target, addr);
6903 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6905 tree arg0 = TREE_VALUE (arglist);
6906 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6907 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6908 rtx op0 = expand_normal (arg0);
6909 rtx op1 = expand_normal (arg1);
6910 rtx op2 = expand_normal (arg2);
6912 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6913 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6914 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6916 /* Invalid arguments. Bail before doing anything stoopid! */
6917 if (arg0 == error_mark_node
6918 || arg1 == error_mark_node
6919 || arg2 == error_mark_node)
6922 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6923 op0 = copy_to_mode_reg (mode2, op0);
6924 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6925 op1 = copy_to_mode_reg (mode0, op1);
6926 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6927 op2 = copy_to_mode_reg (mode1, op2);
6929 pat = GEN_FCN (icode) (op1, op2, op0);
6936 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6938 tree arg0 = TREE_VALUE (arglist);
6939 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6940 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6941 rtx op0 = expand_normal (arg0);
6942 rtx op1 = expand_normal (arg1);
6943 rtx op2 = expand_normal (arg2);
6945 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6946 enum machine_mode mode1 = Pmode;
6947 enum machine_mode mode2 = Pmode;
6949 /* Invalid arguments. Bail before doing anything stoopid! */
6950 if (arg0 == error_mark_node
6951 || arg1 == error_mark_node
6952 || arg2 == error_mark_node)
6955 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6956 op0 = copy_to_mode_reg (tmode, op0);
6958 op2 = copy_to_mode_reg (mode2, op2);
6960 if (op1 == const0_rtx)
6962 addr = gen_rtx_MEM (tmode, op2);
6966 op1 = copy_to_mode_reg (mode1, op1);
6967 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6970 pat = GEN_FCN (icode) (addr, op0);
6977 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6980 tree arg0 = TREE_VALUE (arglist);
6981 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6982 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6983 rtx op0 = expand_normal (arg0);
6984 rtx op1 = expand_normal (arg1);
6985 rtx op2 = expand_normal (arg2);
6986 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6987 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6988 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6989 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6991 if (icode == CODE_FOR_nothing)
6992 /* Builtin not supported on this processor. */
6995 /* If we got invalid arguments bail out before generating bad rtl. */
6996 if (arg0 == error_mark_node
6997 || arg1 == error_mark_node
6998 || arg2 == error_mark_node)
7001 if (icode == CODE_FOR_altivec_vsldoi_v4sf
7002 || icode == CODE_FOR_altivec_vsldoi_v4si
7003 || icode == CODE_FOR_altivec_vsldoi_v8hi
7004 || icode == CODE_FOR_altivec_vsldoi_v16qi)
7006 /* Only allow 4-bit unsigned literals. */
7008 if (TREE_CODE (arg2) != INTEGER_CST
7009 || TREE_INT_CST_LOW (arg2) & ~0xf)
7011 error ("argument 3 must be a 4-bit unsigned literal");
7017 || GET_MODE (target) != tmode
7018 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7019 target = gen_reg_rtx (tmode);
7021 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7022 op0 = copy_to_mode_reg (mode0, op0);
7023 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7024 op1 = copy_to_mode_reg (mode1, op1);
7025 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7026 op2 = copy_to_mode_reg (mode2, op2);
7028 pat = GEN_FCN (icode) (target, op0, op1, op2);
7036 /* Expand the lvx builtins. */
7038 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7040 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7041 tree arglist = TREE_OPERAND (exp, 1);
7042 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7044 enum machine_mode tmode, mode0;
7046 enum insn_code icode;
7050 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7051 icode = CODE_FOR_altivec_lvx_v16qi;
7053 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7054 icode = CODE_FOR_altivec_lvx_v8hi;
7056 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7057 icode = CODE_FOR_altivec_lvx_v4si;
7059 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7060 icode = CODE_FOR_altivec_lvx_v4sf;
7069 arg0 = TREE_VALUE (arglist);
7070 op0 = expand_normal (arg0);
7071 tmode = insn_data[icode].operand[0].mode;
7072 mode0 = insn_data[icode].operand[1].mode;
7075 || GET_MODE (target) != tmode
7076 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7077 target = gen_reg_rtx (tmode);
7079 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7080 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7082 pat = GEN_FCN (icode) (target, op0);
7089 /* Expand the stvx builtins. */
7091 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7094 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7095 tree arglist = TREE_OPERAND (exp, 1);
7096 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7098 enum machine_mode mode0, mode1;
7100 enum insn_code icode;
7104 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7105 icode = CODE_FOR_altivec_stvx_v16qi;
7107 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7108 icode = CODE_FOR_altivec_stvx_v8hi;
7110 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7111 icode = CODE_FOR_altivec_stvx_v4si;
7113 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7114 icode = CODE_FOR_altivec_stvx_v4sf;
7121 arg0 = TREE_VALUE (arglist);
7122 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7123 op0 = expand_normal (arg0);
7124 op1 = expand_normal (arg1);
7125 mode0 = insn_data[icode].operand[0].mode;
7126 mode1 = insn_data[icode].operand[1].mode;
7128 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7129 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7130 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7131 op1 = copy_to_mode_reg (mode1, op1);
7133 pat = GEN_FCN (icode) (op0, op1);
7141 /* Expand the dst builtins. */
7143 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7146 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7147 tree arglist = TREE_OPERAND (exp, 1);
7148 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7149 tree arg0, arg1, arg2;
7150 enum machine_mode mode0, mode1, mode2;
7151 rtx pat, op0, op1, op2;
7152 struct builtin_description *d;
7157 /* Handle DST variants. */
7158 d = (struct builtin_description *) bdesc_dst;
7159 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7160 if (d->code == fcode)
7162 arg0 = TREE_VALUE (arglist);
7163 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7164 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7165 op0 = expand_normal (arg0);
7166 op1 = expand_normal (arg1);
7167 op2 = expand_normal (arg2);
7168 mode0 = insn_data[d->icode].operand[0].mode;
7169 mode1 = insn_data[d->icode].operand[1].mode;
7170 mode2 = insn_data[d->icode].operand[2].mode;
7172 /* Invalid arguments, bail out before generating bad rtl. */
7173 if (arg0 == error_mark_node
7174 || arg1 == error_mark_node
7175 || arg2 == error_mark_node)
7180 if (TREE_CODE (arg2) != INTEGER_CST
7181 || TREE_INT_CST_LOW (arg2) & ~0x3)
7183 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7187 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7188 op0 = copy_to_mode_reg (Pmode, op0);
7189 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7190 op1 = copy_to_mode_reg (mode1, op1);
7192 pat = GEN_FCN (d->icode) (op0, op1, op2);
7202 /* Expand vec_init builtin. */
7204 altivec_expand_vec_init_builtin (tree type, tree arglist, rtx target)
7206 enum machine_mode tmode = TYPE_MODE (type);
7207 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7208 int i, n_elt = GET_MODE_NUNITS (tmode);
7209 rtvec v = rtvec_alloc (n_elt);
7211 gcc_assert (VECTOR_MODE_P (tmode));
7213 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
7215 rtx x = expand_normal (TREE_VALUE (arglist));
7216 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7219 gcc_assert (arglist == NULL);
7221 if (!target || !register_operand (target, tmode))
7222 target = gen_reg_rtx (tmode);
7224 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7228 /* Return the integer constant in ARG. Constrain it to be in the range
7229 of the subparts of VEC_TYPE; issue an error if not. */
7232 get_element_number (tree vec_type, tree arg)
7234 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7236 if (!host_integerp (arg, 1)
7237 || (elt = tree_low_cst (arg, 1), elt > max))
7239 error ("selector must be an integer constant in the range 0..%wi", max);
7246 /* Expand vec_set builtin. */
7248 altivec_expand_vec_set_builtin (tree arglist)
7250 enum machine_mode tmode, mode1;
7251 tree arg0, arg1, arg2;
7255 arg0 = TREE_VALUE (arglist);
7256 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7257 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7259 tmode = TYPE_MODE (TREE_TYPE (arg0));
7260 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7261 gcc_assert (VECTOR_MODE_P (tmode));
7263 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7264 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7265 elt = get_element_number (TREE_TYPE (arg0), arg2);
7267 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7268 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7270 op0 = force_reg (tmode, op0);
7271 op1 = force_reg (mode1, op1);
7273 rs6000_expand_vector_set (op0, op1, elt);
7278 /* Expand vec_ext builtin. */
7280 altivec_expand_vec_ext_builtin (tree arglist, rtx target)
7282 enum machine_mode tmode, mode0;
7287 arg0 = TREE_VALUE (arglist);
7288 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7290 op0 = expand_normal (arg0);
7291 elt = get_element_number (TREE_TYPE (arg0), arg1);
7293 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7294 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7295 gcc_assert (VECTOR_MODE_P (mode0));
7297 op0 = force_reg (mode0, op0);
7299 if (optimize || !target || !register_operand (target, tmode))
7300 target = gen_reg_rtx (tmode);
7302 rs6000_expand_vector_extract (target, op0, elt);
7307 /* Expand the builtin in EXP and store the result in TARGET. Store
7308 true in *EXPANDEDP if we found a builtin to expand. */
7310 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7312 struct builtin_description *d;
7313 struct builtin_description_predicates *dp;
7315 enum insn_code icode;
7316 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7317 tree arglist = TREE_OPERAND (exp, 1);
7320 enum machine_mode tmode, mode0;
7321 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7323 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7324 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7327 error ("unresolved overload for Altivec builtin %qF", fndecl);
7331 target = altivec_expand_ld_builtin (exp, target, expandedp);
7335 target = altivec_expand_st_builtin (exp, target, expandedp);
7339 target = altivec_expand_dst_builtin (exp, target, expandedp);
7347 case ALTIVEC_BUILTIN_STVX:
7348 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
7349 case ALTIVEC_BUILTIN_STVEBX:
7350 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
7351 case ALTIVEC_BUILTIN_STVEHX:
7352 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
7353 case ALTIVEC_BUILTIN_STVEWX:
7354 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
7355 case ALTIVEC_BUILTIN_STVXL:
7356 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
7358 case ALTIVEC_BUILTIN_MFVSCR:
7359 icode = CODE_FOR_altivec_mfvscr;
7360 tmode = insn_data[icode].operand[0].mode;
7363 || GET_MODE (target) != tmode
7364 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7365 target = gen_reg_rtx (tmode);
7367 pat = GEN_FCN (icode) (target);
7373 case ALTIVEC_BUILTIN_MTVSCR:
7374 icode = CODE_FOR_altivec_mtvscr;
7375 arg0 = TREE_VALUE (arglist);
7376 op0 = expand_normal (arg0);
7377 mode0 = insn_data[icode].operand[0].mode;
7379 /* If we got invalid arguments bail out before generating bad rtl. */
7380 if (arg0 == error_mark_node)
7383 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7384 op0 = copy_to_mode_reg (mode0, op0);
7386 pat = GEN_FCN (icode) (op0);
7391 case ALTIVEC_BUILTIN_DSSALL:
7392 emit_insn (gen_altivec_dssall ());
7395 case ALTIVEC_BUILTIN_DSS:
7396 icode = CODE_FOR_altivec_dss;
7397 arg0 = TREE_VALUE (arglist);
7399 op0 = expand_normal (arg0);
7400 mode0 = insn_data[icode].operand[0].mode;
7402 /* If we got invalid arguments bail out before generating bad rtl. */
7403 if (arg0 == error_mark_node)
7406 if (TREE_CODE (arg0) != INTEGER_CST
7407 || TREE_INT_CST_LOW (arg0) & ~0x3)
7409 error ("argument to dss must be a 2-bit unsigned literal");
7413 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7414 op0 = copy_to_mode_reg (mode0, op0);
7416 emit_insn (gen_altivec_dss (op0));
7419 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7420 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7421 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7422 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7423 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
7425 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7426 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7427 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7428 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7429 return altivec_expand_vec_set_builtin (arglist);
7431 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7432 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7433 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7434 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7435 return altivec_expand_vec_ext_builtin (arglist, target);
7442 /* Expand abs* operations. */
7443 d = (struct builtin_description *) bdesc_abs;
7444 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7445 if (d->code == fcode)
7446 return altivec_expand_abs_builtin (d->icode, arglist, target);
7448 /* Expand the AltiVec predicates. */
7449 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7450 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7451 if (dp->code == fcode)
7452 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7455 /* LV* are funky. We initialized them differently. */
7458 case ALTIVEC_BUILTIN_LVSL:
7459 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7461 case ALTIVEC_BUILTIN_LVSR:
7462 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7464 case ALTIVEC_BUILTIN_LVEBX:
7465 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7467 case ALTIVEC_BUILTIN_LVEHX:
7468 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7470 case ALTIVEC_BUILTIN_LVEWX:
7471 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7473 case ALTIVEC_BUILTIN_LVXL:
7474 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7476 case ALTIVEC_BUILTIN_LVX:
7477 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7488 /* Binops that need to be initialized manually, but can be expanded
7489 automagically by rs6000_expand_binop_builtin. */
7490 static struct builtin_description bdesc_2arg_spe[] =
7492 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7493 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7494 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7495 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7496 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7497 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7498 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7499 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7500 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7501 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7502 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7503 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7504 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7505 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7506 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7507 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7508 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7509 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7510 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7511 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7512 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7513 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7516 /* Expand the builtin in EXP and store the result in TARGET. Store
7517 true in *EXPANDEDP if we found a builtin to expand.
7519 This expands the SPE builtins that are not simple unary and binary
7522 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7524 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7525 tree arglist = TREE_OPERAND (exp, 1);
7527 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7528 enum insn_code icode;
7529 enum machine_mode tmode, mode0;
7531 struct builtin_description *d;
7536 /* Syntax check for a 5-bit unsigned immediate. */
7539 case SPE_BUILTIN_EVSTDD:
7540 case SPE_BUILTIN_EVSTDH:
7541 case SPE_BUILTIN_EVSTDW:
7542 case SPE_BUILTIN_EVSTWHE:
7543 case SPE_BUILTIN_EVSTWHO:
7544 case SPE_BUILTIN_EVSTWWE:
7545 case SPE_BUILTIN_EVSTWWO:
7546 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7547 if (TREE_CODE (arg1) != INTEGER_CST
7548 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7550 error ("argument 2 must be a 5-bit unsigned literal");
7558 /* The evsplat*i instructions are not quite generic. */
7561 case SPE_BUILTIN_EVSPLATFI:
7562 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7564 case SPE_BUILTIN_EVSPLATI:
7565 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7571 d = (struct builtin_description *) bdesc_2arg_spe;
7572 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7573 if (d->code == fcode)
7574 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7576 d = (struct builtin_description *) bdesc_spe_predicates;
7577 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7578 if (d->code == fcode)
7579 return spe_expand_predicate_builtin (d->icode, arglist, target);
7581 d = (struct builtin_description *) bdesc_spe_evsel;
7582 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7583 if (d->code == fcode)
7584 return spe_expand_evsel_builtin (d->icode, arglist, target);
7588 case SPE_BUILTIN_EVSTDDX:
7589 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7590 case SPE_BUILTIN_EVSTDHX:
7591 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7592 case SPE_BUILTIN_EVSTDWX:
7593 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7594 case SPE_BUILTIN_EVSTWHEX:
7595 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7596 case SPE_BUILTIN_EVSTWHOX:
7597 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7598 case SPE_BUILTIN_EVSTWWEX:
7599 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7600 case SPE_BUILTIN_EVSTWWOX:
7601 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7602 case SPE_BUILTIN_EVSTDD:
7603 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7604 case SPE_BUILTIN_EVSTDH:
7605 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7606 case SPE_BUILTIN_EVSTDW:
7607 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7608 case SPE_BUILTIN_EVSTWHE:
7609 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7610 case SPE_BUILTIN_EVSTWHO:
7611 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7612 case SPE_BUILTIN_EVSTWWE:
7613 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7614 case SPE_BUILTIN_EVSTWWO:
7615 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7616 case SPE_BUILTIN_MFSPEFSCR:
7617 icode = CODE_FOR_spe_mfspefscr;
7618 tmode = insn_data[icode].operand[0].mode;
7621 || GET_MODE (target) != tmode
7622 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7623 target = gen_reg_rtx (tmode);
7625 pat = GEN_FCN (icode) (target);
7630 case SPE_BUILTIN_MTSPEFSCR:
7631 icode = CODE_FOR_spe_mtspefscr;
7632 arg0 = TREE_VALUE (arglist);
7633 op0 = expand_normal (arg0);
7634 mode0 = insn_data[icode].operand[0].mode;
7636 if (arg0 == error_mark_node)
7639 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7640 op0 = copy_to_mode_reg (mode0, op0);
7642 pat = GEN_FCN (icode) (op0);
7655 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7657 rtx pat, scratch, tmp;
7658 tree form = TREE_VALUE (arglist);
7659 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7660 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7661 rtx op0 = expand_normal (arg0);
7662 rtx op1 = expand_normal (arg1);
7663 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7664 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7668 if (TREE_CODE (form) != INTEGER_CST)
7670 error ("argument 1 of __builtin_spe_predicate must be a constant");
7674 form_int = TREE_INT_CST_LOW (form);
7676 gcc_assert (mode0 == mode1);
7678 if (arg0 == error_mark_node || arg1 == error_mark_node)
7682 || GET_MODE (target) != SImode
7683 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7684 target = gen_reg_rtx (SImode);
7686 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7687 op0 = copy_to_mode_reg (mode0, op0);
7688 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7689 op1 = copy_to_mode_reg (mode1, op1);
7691 scratch = gen_reg_rtx (CCmode);
7693 pat = GEN_FCN (icode) (scratch, op0, op1);
7698 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7699 _lower_. We use one compare, but look in different bits of the
7700 CR for each variant.
7702 There are 2 elements in each SPE simd type (upper/lower). The CR
7703 bits are set as follows:
7705 BIT0 | BIT 1 | BIT 2 | BIT 3
7706 U | L | (U | L) | (U & L)
7708 So, for an "all" relationship, BIT 3 would be set.
7709 For an "any" relationship, BIT 2 would be set. Etc.
7711 Following traditional nomenclature, these bits map to:
7713 BIT0 | BIT 1 | BIT 2 | BIT 3
7716 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7721 /* All variant. OV bit. */
7723 /* We need to get to the OV bit, which is the ORDERED bit. We
7724 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7725 that's ugly and will make validate_condition_mode die.
7726 So let's just use another pattern. */
7727 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7729 /* Any variant. EQ bit. */
7733 /* Upper variant. LT bit. */
7737 /* Lower variant. GT bit. */
7742 error ("argument 1 of __builtin_spe_predicate is out of range");
7746 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7747 emit_move_insn (target, tmp);
7752 /* The evsel builtins look like this:
7754 e = __builtin_spe_evsel_OP (a, b, c, d);
7758 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7759 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7763 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7766 tree arg0 = TREE_VALUE (arglist);
7767 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7768 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7769 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7770 rtx op0 = expand_normal (arg0);
7771 rtx op1 = expand_normal (arg1);
7772 rtx op2 = expand_normal (arg2);
7773 rtx op3 = expand_normal (arg3);
7774 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7775 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7777 gcc_assert (mode0 == mode1);
7779 if (arg0 == error_mark_node || arg1 == error_mark_node
7780 || arg2 == error_mark_node || arg3 == error_mark_node)
7784 || GET_MODE (target) != mode0
7785 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7786 target = gen_reg_rtx (mode0);
7788 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7789 op0 = copy_to_mode_reg (mode0, op0);
7790 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7791 op1 = copy_to_mode_reg (mode0, op1);
7792 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7793 op2 = copy_to_mode_reg (mode0, op2);
7794 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7795 op3 = copy_to_mode_reg (mode0, op3);
7797 /* Generate the compare. */
7798 scratch = gen_reg_rtx (CCmode);
7799 pat = GEN_FCN (icode) (scratch, op0, op1);
7804 if (mode0 == V2SImode)
7805 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7807 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7812 /* Expand an expression EXP that calls a built-in function,
7813 with result going to TARGET if that's convenient
7814 (and in mode MODE if that's convenient).
7815 SUBTARGET may be used as the target for computing one of EXP's operands.
7816 IGNORE is nonzero if the value is to be ignored. */
7819 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7820 enum machine_mode mode ATTRIBUTE_UNUSED,
7821 int ignore ATTRIBUTE_UNUSED)
7823 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7824 tree arglist = TREE_OPERAND (exp, 1);
7825 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7826 struct builtin_description *d;
7831 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7832 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7834 int icode = (int) CODE_FOR_altivec_lvsr;
7835 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7836 enum machine_mode mode = insn_data[icode].operand[1].mode;
7840 gcc_assert (TARGET_ALTIVEC);
7842 arg = TREE_VALUE (arglist);
7843 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
7844 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7845 addr = memory_address (mode, op);
7846 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7850 /* For the load case need to negate the address. */
7851 op = gen_reg_rtx (GET_MODE (addr));
7852 emit_insn (gen_rtx_SET (VOIDmode, op,
7853 gen_rtx_NEG (GET_MODE (addr), addr)));
7855 op = gen_rtx_MEM (mode, op);
7858 || GET_MODE (target) != tmode
7859 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7860 target = gen_reg_rtx (tmode);
7862 /*pat = gen_altivec_lvsr (target, op);*/
7863 pat = GEN_FCN (icode) (target, op);
7873 ret = altivec_expand_builtin (exp, target, &success);
7880 ret = spe_expand_builtin (exp, target, &success);
7886 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
7888 /* Handle simple unary operations. */
7889 d = (struct builtin_description *) bdesc_1arg;
7890 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7891 if (d->code == fcode)
7892 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7894 /* Handle simple binary operations. */
7895 d = (struct builtin_description *) bdesc_2arg;
7896 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7897 if (d->code == fcode)
7898 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7900 /* Handle simple ternary operations. */
7901 d = (struct builtin_description *) bdesc_3arg;
7902 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7903 if (d->code == fcode)
7904 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7910 build_opaque_vector_type (tree node, int nunits)
7912 node = copy_node (node);
7913 TYPE_MAIN_VARIANT (node) = node;
7914 return build_vector_type (node, nunits);
7918 rs6000_init_builtins (void)
7920 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7921 V2SF_type_node = build_vector_type (float_type_node, 2);
7922 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7923 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7924 V4SF_type_node = build_vector_type (float_type_node, 4);
7925 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7926 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7928 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7929 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7930 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7932 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7933 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7934 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7935 opaque_V4SI_type_node = copy_node (V4SI_type_node);
7937 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7938 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7939 'vector unsigned short'. */
7941 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7942 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7943 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7944 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7946 long_integer_type_internal_node = long_integer_type_node;
7947 long_unsigned_type_internal_node = long_unsigned_type_node;
7948 intQI_type_internal_node = intQI_type_node;
7949 uintQI_type_internal_node = unsigned_intQI_type_node;
7950 intHI_type_internal_node = intHI_type_node;
7951 uintHI_type_internal_node = unsigned_intHI_type_node;
7952 intSI_type_internal_node = intSI_type_node;
7953 uintSI_type_internal_node = unsigned_intSI_type_node;
7954 float_type_internal_node = float_type_node;
7955 void_type_internal_node = void_type_node;
7957 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7958 get_identifier ("__bool char"),
7959 bool_char_type_node));
7960 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7961 get_identifier ("__bool short"),
7962 bool_short_type_node));
7963 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7964 get_identifier ("__bool int"),
7965 bool_int_type_node));
7966 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7967 get_identifier ("__pixel"),
7970 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7971 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7972 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7973 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7975 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7976 get_identifier ("__vector unsigned char"),
7977 unsigned_V16QI_type_node));
7978 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7979 get_identifier ("__vector signed char"),
7981 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7982 get_identifier ("__vector __bool char"),
7983 bool_V16QI_type_node));
7985 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7986 get_identifier ("__vector unsigned short"),
7987 unsigned_V8HI_type_node));
7988 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7989 get_identifier ("__vector signed short"),
7991 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7992 get_identifier ("__vector __bool short"),
7993 bool_V8HI_type_node));
7995 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7996 get_identifier ("__vector unsigned int"),
7997 unsigned_V4SI_type_node));
7998 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7999 get_identifier ("__vector signed int"),
8001 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8002 get_identifier ("__vector __bool int"),
8003 bool_V4SI_type_node));
8005 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8006 get_identifier ("__vector float"),
8008 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8009 get_identifier ("__vector __pixel"),
8010 pixel_V8HI_type_node));
8013 spe_init_builtins ();
8015 altivec_init_builtins ();
8016 if (TARGET_ALTIVEC || TARGET_SPE)
8017 rs6000_common_init_builtins ();
8020 /* AIX libm provides clog as __clog. */
8021 if (built_in_decls [BUILT_IN_CLOG])
8022 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
8026 /* Search through a set of builtins and enable the mask bits.
8027 DESC is an array of builtins.
8028 SIZE is the total number of builtins.
8029 START is the builtin enum at which to start.
8030 END is the builtin enum at which to end. */
8032 enable_mask_for_builtins (struct builtin_description *desc, int size,
8033 enum rs6000_builtins start,
8034 enum rs6000_builtins end)
8038 for (i = 0; i < size; ++i)
8039 if (desc[i].code == start)
8045 for (; i < size; ++i)
8047 /* Flip all the bits on. */
8048 desc[i].mask = target_flags;
8049 if (desc[i].code == end)
8055 spe_init_builtins (void)
8057 tree endlink = void_list_node;
8058 tree puint_type_node = build_pointer_type (unsigned_type_node);
8059 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
8060 struct builtin_description *d;
8063 tree v2si_ftype_4_v2si
8064 = build_function_type
8065 (opaque_V2SI_type_node,
8066 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8067 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8068 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8069 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8072 tree v2sf_ftype_4_v2sf
8073 = build_function_type
8074 (opaque_V2SF_type_node,
8075 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8076 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8077 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8078 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8081 tree int_ftype_int_v2si_v2si
8082 = build_function_type
8084 tree_cons (NULL_TREE, integer_type_node,
8085 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8086 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8089 tree int_ftype_int_v2sf_v2sf
8090 = build_function_type
8092 tree_cons (NULL_TREE, integer_type_node,
8093 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8094 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8097 tree void_ftype_v2si_puint_int
8098 = build_function_type (void_type_node,
8099 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8100 tree_cons (NULL_TREE, puint_type_node,
8101 tree_cons (NULL_TREE,
8105 tree void_ftype_v2si_puint_char
8106 = build_function_type (void_type_node,
8107 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8108 tree_cons (NULL_TREE, puint_type_node,
8109 tree_cons (NULL_TREE,
8113 tree void_ftype_v2si_pv2si_int
8114 = build_function_type (void_type_node,
8115 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8116 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8117 tree_cons (NULL_TREE,
8121 tree void_ftype_v2si_pv2si_char
8122 = build_function_type (void_type_node,
8123 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8124 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8125 tree_cons (NULL_TREE,
8130 = build_function_type (void_type_node,
8131 tree_cons (NULL_TREE, integer_type_node, endlink));
8134 = build_function_type (integer_type_node, endlink);
8136 tree v2si_ftype_pv2si_int
8137 = build_function_type (opaque_V2SI_type_node,
8138 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8139 tree_cons (NULL_TREE, integer_type_node,
8142 tree v2si_ftype_puint_int
8143 = build_function_type (opaque_V2SI_type_node,
8144 tree_cons (NULL_TREE, puint_type_node,
8145 tree_cons (NULL_TREE, integer_type_node,
8148 tree v2si_ftype_pushort_int
8149 = build_function_type (opaque_V2SI_type_node,
8150 tree_cons (NULL_TREE, pushort_type_node,
8151 tree_cons (NULL_TREE, integer_type_node,
8154 tree v2si_ftype_signed_char
8155 = build_function_type (opaque_V2SI_type_node,
8156 tree_cons (NULL_TREE, signed_char_type_node,
8159 /* The initialization of the simple binary and unary builtins is
8160 done in rs6000_common_init_builtins, but we have to enable the
8161 mask bits here manually because we have run out of `target_flags'
8162 bits. We really need to redesign this mask business. */
8164 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8165 ARRAY_SIZE (bdesc_2arg),
8168 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8169 ARRAY_SIZE (bdesc_1arg),
8171 SPE_BUILTIN_EVSUBFUSIAAW);
8172 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8173 ARRAY_SIZE (bdesc_spe_predicates),
8174 SPE_BUILTIN_EVCMPEQ,
8175 SPE_BUILTIN_EVFSTSTLT);
8176 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8177 ARRAY_SIZE (bdesc_spe_evsel),
8178 SPE_BUILTIN_EVSEL_CMPGTS,
8179 SPE_BUILTIN_EVSEL_FSTSTEQ);
8181 (*lang_hooks.decls.pushdecl)
8182 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8183 opaque_V2SI_type_node));
8185 /* Initialize irregular SPE builtins. */
8187 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8188 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8189 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8190 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8191 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8192 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8193 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8194 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8195 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8196 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8197 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8198 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8199 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8200 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8201 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8202 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8203 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8204 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8207 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8208 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8209 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8210 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8211 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8212 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8213 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8214 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8215 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8216 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8217 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8218 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8219 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8220 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8221 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8222 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8223 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8224 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8225 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8226 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8227 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8228 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8231 d = (struct builtin_description *) bdesc_spe_predicates;
8232 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8236 switch (insn_data[d->icode].operand[1].mode)
8239 type = int_ftype_int_v2si_v2si;
8242 type = int_ftype_int_v2sf_v2sf;
8248 def_builtin (d->mask, d->name, type, d->code);
8251 /* Evsel predicates. */
8252 d = (struct builtin_description *) bdesc_spe_evsel;
8253 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8257 switch (insn_data[d->icode].operand[1].mode)
8260 type = v2si_ftype_4_v2si;
8263 type = v2sf_ftype_4_v2sf;
8269 def_builtin (d->mask, d->name, type, d->code);
8274 altivec_init_builtins (void)
8276 struct builtin_description *d;
8277 struct builtin_description_predicates *dp;
8281 tree pfloat_type_node = build_pointer_type (float_type_node);
8282 tree pint_type_node = build_pointer_type (integer_type_node);
8283 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8284 tree pchar_type_node = build_pointer_type (char_type_node);
8286 tree pvoid_type_node = build_pointer_type (void_type_node);
8288 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8289 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8290 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8291 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8293 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8295 tree int_ftype_opaque
8296 = build_function_type_list (integer_type_node,
8297 opaque_V4SI_type_node, NULL_TREE);
8299 tree opaque_ftype_opaque_int
8300 = build_function_type_list (opaque_V4SI_type_node,
8301 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8302 tree opaque_ftype_opaque_opaque_int
8303 = build_function_type_list (opaque_V4SI_type_node,
8304 opaque_V4SI_type_node, opaque_V4SI_type_node,
8305 integer_type_node, NULL_TREE);
8306 tree int_ftype_int_opaque_opaque
8307 = build_function_type_list (integer_type_node,
8308 integer_type_node, opaque_V4SI_type_node,
8309 opaque_V4SI_type_node, NULL_TREE);
8310 tree int_ftype_int_v4si_v4si
8311 = build_function_type_list (integer_type_node,
8312 integer_type_node, V4SI_type_node,
8313 V4SI_type_node, NULL_TREE);
8314 tree v4sf_ftype_pcfloat
8315 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8316 tree void_ftype_pfloat_v4sf
8317 = build_function_type_list (void_type_node,
8318 pfloat_type_node, V4SF_type_node, NULL_TREE);
8319 tree v4si_ftype_pcint
8320 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8321 tree void_ftype_pint_v4si
8322 = build_function_type_list (void_type_node,
8323 pint_type_node, V4SI_type_node, NULL_TREE);
8324 tree v8hi_ftype_pcshort
8325 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8326 tree void_ftype_pshort_v8hi
8327 = build_function_type_list (void_type_node,
8328 pshort_type_node, V8HI_type_node, NULL_TREE);
8329 tree v16qi_ftype_pcchar
8330 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8331 tree void_ftype_pchar_v16qi
8332 = build_function_type_list (void_type_node,
8333 pchar_type_node, V16QI_type_node, NULL_TREE);
8334 tree void_ftype_v4si
8335 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8336 tree v8hi_ftype_void
8337 = build_function_type (V8HI_type_node, void_list_node);
8338 tree void_ftype_void
8339 = build_function_type (void_type_node, void_list_node);
8341 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8343 tree opaque_ftype_long_pcvoid
8344 = build_function_type_list (opaque_V4SI_type_node,
8345 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8346 tree v16qi_ftype_long_pcvoid
8347 = build_function_type_list (V16QI_type_node,
8348 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8349 tree v8hi_ftype_long_pcvoid
8350 = build_function_type_list (V8HI_type_node,
8351 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8352 tree v4si_ftype_long_pcvoid
8353 = build_function_type_list (V4SI_type_node,
8354 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8356 tree void_ftype_opaque_long_pvoid
8357 = build_function_type_list (void_type_node,
8358 opaque_V4SI_type_node, long_integer_type_node,
8359 pvoid_type_node, NULL_TREE);
8360 tree void_ftype_v4si_long_pvoid
8361 = build_function_type_list (void_type_node,
8362 V4SI_type_node, long_integer_type_node,
8363 pvoid_type_node, NULL_TREE);
8364 tree void_ftype_v16qi_long_pvoid
8365 = build_function_type_list (void_type_node,
8366 V16QI_type_node, long_integer_type_node,
8367 pvoid_type_node, NULL_TREE);
8368 tree void_ftype_v8hi_long_pvoid
8369 = build_function_type_list (void_type_node,
8370 V8HI_type_node, long_integer_type_node,
8371 pvoid_type_node, NULL_TREE);
8372 tree int_ftype_int_v8hi_v8hi
8373 = build_function_type_list (integer_type_node,
8374 integer_type_node, V8HI_type_node,
8375 V8HI_type_node, NULL_TREE);
8376 tree int_ftype_int_v16qi_v16qi
8377 = build_function_type_list (integer_type_node,
8378 integer_type_node, V16QI_type_node,
8379 V16QI_type_node, NULL_TREE);
8380 tree int_ftype_int_v4sf_v4sf
8381 = build_function_type_list (integer_type_node,
8382 integer_type_node, V4SF_type_node,
8383 V4SF_type_node, NULL_TREE);
8384 tree v4si_ftype_v4si
8385 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8386 tree v8hi_ftype_v8hi
8387 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8388 tree v16qi_ftype_v16qi
8389 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8390 tree v4sf_ftype_v4sf
8391 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8392 tree void_ftype_pcvoid_int_int
8393 = build_function_type_list (void_type_node,
8394 pcvoid_type_node, integer_type_node,
8395 integer_type_node, NULL_TREE);
8397 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8398 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8399 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8400 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8401 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8402 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8403 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8404 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8405 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8406 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8407 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8408 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8409 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8410 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8411 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8412 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8413 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8414 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8415 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8416 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8417 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8418 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8419 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8420 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8421 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8422 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8423 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8424 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8425 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8426 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8427 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8428 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8429 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8430 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8431 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8432 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8433 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8434 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8435 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8436 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
8437 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
8438 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
8439 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
8440 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
8441 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
8442 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
8444 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
8446 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
8447 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
8448 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
8449 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
8450 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
8451 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
8452 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
8453 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
8454 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
8455 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8457 /* Add the DST variants. */
8458 d = (struct builtin_description *) bdesc_dst;
8459 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8460 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8462 /* Initialize the predicates. */
8463 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8464 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8466 enum machine_mode mode1;
8468 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8469 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8474 mode1 = insn_data[dp->icode].operand[1].mode;
8479 type = int_ftype_int_opaque_opaque;
8482 type = int_ftype_int_v4si_v4si;
8485 type = int_ftype_int_v8hi_v8hi;
8488 type = int_ftype_int_v16qi_v16qi;
8491 type = int_ftype_int_v4sf_v4sf;
8497 def_builtin (dp->mask, dp->name, type, dp->code);
8500 /* Initialize the abs* operators. */
8501 d = (struct builtin_description *) bdesc_abs;
8502 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8504 enum machine_mode mode0;
8507 mode0 = insn_data[d->icode].operand[0].mode;
8512 type = v4si_ftype_v4si;
8515 type = v8hi_ftype_v8hi;
8518 type = v16qi_ftype_v16qi;
8521 type = v4sf_ftype_v4sf;
8527 def_builtin (d->mask, d->name, type, d->code);
8534 /* Initialize target builtin that implements
8535 targetm.vectorize.builtin_mask_for_load. */
8537 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8538 v16qi_ftype_long_pcvoid,
8539 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8541 tree_cons (get_identifier ("const"),
8542 NULL_TREE, NULL_TREE));
8543 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8544 altivec_builtin_mask_for_load = decl;
8547 /* Access to the vec_init patterns. */
8548 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
8549 integer_type_node, integer_type_node,
8550 integer_type_node, NULL_TREE);
8551 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
8552 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
8554 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
8555 short_integer_type_node,
8556 short_integer_type_node,
8557 short_integer_type_node,
8558 short_integer_type_node,
8559 short_integer_type_node,
8560 short_integer_type_node,
8561 short_integer_type_node, NULL_TREE);
8562 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
8563 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
8565 ftype = build_function_type_list (V16QI_type_node, char_type_node,
8566 char_type_node, char_type_node,
8567 char_type_node, char_type_node,
8568 char_type_node, char_type_node,
8569 char_type_node, char_type_node,
8570 char_type_node, char_type_node,
8571 char_type_node, char_type_node,
8572 char_type_node, char_type_node,
8573 char_type_node, NULL_TREE);
8574 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
8575 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
8577 ftype = build_function_type_list (V4SF_type_node, float_type_node,
8578 float_type_node, float_type_node,
8579 float_type_node, NULL_TREE);
8580 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
8581 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
8583 /* Access to the vec_set patterns. */
8584 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
8586 integer_type_node, NULL_TREE);
8587 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
8588 ALTIVEC_BUILTIN_VEC_SET_V4SI);
8590 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
8592 integer_type_node, NULL_TREE);
8593 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
8594 ALTIVEC_BUILTIN_VEC_SET_V8HI);
8596 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
8598 integer_type_node, NULL_TREE);
8599 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
8600 ALTIVEC_BUILTIN_VEC_SET_V16QI);
8602 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
8604 integer_type_node, NULL_TREE);
8605 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
8606 ALTIVEC_BUILTIN_VEC_SET_V4SF);
8608 /* Access to the vec_extract patterns. */
8609 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
8610 integer_type_node, NULL_TREE);
8611 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
8612 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
8614 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
8615 integer_type_node, NULL_TREE);
8616 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
8617 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
8619 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
8620 integer_type_node, NULL_TREE);
8621 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
8622 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
8624 ftype = build_function_type_list (float_type_node, V4SF_type_node,
8625 integer_type_node, NULL_TREE);
8626 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
8627 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
8631 rs6000_common_init_builtins (void)
8633 struct builtin_description *d;
8636 tree v4sf_ftype_v4sf_v4sf_v16qi
8637 = build_function_type_list (V4SF_type_node,
8638 V4SF_type_node, V4SF_type_node,
8639 V16QI_type_node, NULL_TREE);
8640 tree v4si_ftype_v4si_v4si_v16qi
8641 = build_function_type_list (V4SI_type_node,
8642 V4SI_type_node, V4SI_type_node,
8643 V16QI_type_node, NULL_TREE);
8644 tree v8hi_ftype_v8hi_v8hi_v16qi
8645 = build_function_type_list (V8HI_type_node,
8646 V8HI_type_node, V8HI_type_node,
8647 V16QI_type_node, NULL_TREE);
8648 tree v16qi_ftype_v16qi_v16qi_v16qi
8649 = build_function_type_list (V16QI_type_node,
8650 V16QI_type_node, V16QI_type_node,
8651 V16QI_type_node, NULL_TREE);
8653 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8655 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8656 tree v16qi_ftype_int
8657 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8658 tree v8hi_ftype_v16qi
8659 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8660 tree v4sf_ftype_v4sf
8661 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8663 tree v2si_ftype_v2si_v2si
8664 = build_function_type_list (opaque_V2SI_type_node,
8665 opaque_V2SI_type_node,
8666 opaque_V2SI_type_node, NULL_TREE);
8668 tree v2sf_ftype_v2sf_v2sf
8669 = build_function_type_list (opaque_V2SF_type_node,
8670 opaque_V2SF_type_node,
8671 opaque_V2SF_type_node, NULL_TREE);
8673 tree v2si_ftype_int_int
8674 = build_function_type_list (opaque_V2SI_type_node,
8675 integer_type_node, integer_type_node,
8678 tree opaque_ftype_opaque
8679 = build_function_type_list (opaque_V4SI_type_node,
8680 opaque_V4SI_type_node, NULL_TREE);
8682 tree v2si_ftype_v2si
8683 = build_function_type_list (opaque_V2SI_type_node,
8684 opaque_V2SI_type_node, NULL_TREE);
8686 tree v2sf_ftype_v2sf
8687 = build_function_type_list (opaque_V2SF_type_node,
8688 opaque_V2SF_type_node, NULL_TREE);
8690 tree v2sf_ftype_v2si
8691 = build_function_type_list (opaque_V2SF_type_node,
8692 opaque_V2SI_type_node, NULL_TREE);
8694 tree v2si_ftype_v2sf
8695 = build_function_type_list (opaque_V2SI_type_node,
8696 opaque_V2SF_type_node, NULL_TREE);
8698 tree v2si_ftype_v2si_char
8699 = build_function_type_list (opaque_V2SI_type_node,
8700 opaque_V2SI_type_node,
8701 char_type_node, NULL_TREE);
8703 tree v2si_ftype_int_char
8704 = build_function_type_list (opaque_V2SI_type_node,
8705 integer_type_node, char_type_node, NULL_TREE);
8707 tree v2si_ftype_char
8708 = build_function_type_list (opaque_V2SI_type_node,
8709 char_type_node, NULL_TREE);
8711 tree int_ftype_int_int
8712 = build_function_type_list (integer_type_node,
8713 integer_type_node, integer_type_node,
8716 tree opaque_ftype_opaque_opaque
8717 = build_function_type_list (opaque_V4SI_type_node,
8718 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
8719 tree v4si_ftype_v4si_v4si
8720 = build_function_type_list (V4SI_type_node,
8721 V4SI_type_node, V4SI_type_node, NULL_TREE);
8722 tree v4sf_ftype_v4si_int
8723 = build_function_type_list (V4SF_type_node,
8724 V4SI_type_node, integer_type_node, NULL_TREE);
8725 tree v4si_ftype_v4sf_int
8726 = build_function_type_list (V4SI_type_node,
8727 V4SF_type_node, integer_type_node, NULL_TREE);
8728 tree v4si_ftype_v4si_int
8729 = build_function_type_list (V4SI_type_node,
8730 V4SI_type_node, integer_type_node, NULL_TREE);
8731 tree v8hi_ftype_v8hi_int
8732 = build_function_type_list (V8HI_type_node,
8733 V8HI_type_node, integer_type_node, NULL_TREE);
8734 tree v16qi_ftype_v16qi_int
8735 = build_function_type_list (V16QI_type_node,
8736 V16QI_type_node, integer_type_node, NULL_TREE);
8737 tree v16qi_ftype_v16qi_v16qi_int
8738 = build_function_type_list (V16QI_type_node,
8739 V16QI_type_node, V16QI_type_node,
8740 integer_type_node, NULL_TREE);
8741 tree v8hi_ftype_v8hi_v8hi_int
8742 = build_function_type_list (V8HI_type_node,
8743 V8HI_type_node, V8HI_type_node,
8744 integer_type_node, NULL_TREE);
8745 tree v4si_ftype_v4si_v4si_int
8746 = build_function_type_list (V4SI_type_node,
8747 V4SI_type_node, V4SI_type_node,
8748 integer_type_node, NULL_TREE);
8749 tree v4sf_ftype_v4sf_v4sf_int
8750 = build_function_type_list (V4SF_type_node,
8751 V4SF_type_node, V4SF_type_node,
8752 integer_type_node, NULL_TREE);
8753 tree v4sf_ftype_v4sf_v4sf
8754 = build_function_type_list (V4SF_type_node,
8755 V4SF_type_node, V4SF_type_node, NULL_TREE);
8756 tree opaque_ftype_opaque_opaque_opaque
8757 = build_function_type_list (opaque_V4SI_type_node,
8758 opaque_V4SI_type_node, opaque_V4SI_type_node,
8759 opaque_V4SI_type_node, NULL_TREE);
8760 tree v4sf_ftype_v4sf_v4sf_v4si
8761 = build_function_type_list (V4SF_type_node,
8762 V4SF_type_node, V4SF_type_node,
8763 V4SI_type_node, NULL_TREE);
8764 tree v4sf_ftype_v4sf_v4sf_v4sf
8765 = build_function_type_list (V4SF_type_node,
8766 V4SF_type_node, V4SF_type_node,
8767 V4SF_type_node, NULL_TREE);
8768 tree v4si_ftype_v4si_v4si_v4si
8769 = build_function_type_list (V4SI_type_node,
8770 V4SI_type_node, V4SI_type_node,
8771 V4SI_type_node, NULL_TREE);
8772 tree v8hi_ftype_v8hi_v8hi
8773 = build_function_type_list (V8HI_type_node,
8774 V8HI_type_node, V8HI_type_node, NULL_TREE);
8775 tree v8hi_ftype_v8hi_v8hi_v8hi
8776 = build_function_type_list (V8HI_type_node,
8777 V8HI_type_node, V8HI_type_node,
8778 V8HI_type_node, NULL_TREE);
8779 tree v4si_ftype_v8hi_v8hi_v4si
8780 = build_function_type_list (V4SI_type_node,
8781 V8HI_type_node, V8HI_type_node,
8782 V4SI_type_node, NULL_TREE);
8783 tree v4si_ftype_v16qi_v16qi_v4si
8784 = build_function_type_list (V4SI_type_node,
8785 V16QI_type_node, V16QI_type_node,
8786 V4SI_type_node, NULL_TREE);
8787 tree v16qi_ftype_v16qi_v16qi
8788 = build_function_type_list (V16QI_type_node,
8789 V16QI_type_node, V16QI_type_node, NULL_TREE);
8790 tree v4si_ftype_v4sf_v4sf
8791 = build_function_type_list (V4SI_type_node,
8792 V4SF_type_node, V4SF_type_node, NULL_TREE);
8793 tree v8hi_ftype_v16qi_v16qi
8794 = build_function_type_list (V8HI_type_node,
8795 V16QI_type_node, V16QI_type_node, NULL_TREE);
8796 tree v4si_ftype_v8hi_v8hi
8797 = build_function_type_list (V4SI_type_node,
8798 V8HI_type_node, V8HI_type_node, NULL_TREE);
8799 tree v8hi_ftype_v4si_v4si
8800 = build_function_type_list (V8HI_type_node,
8801 V4SI_type_node, V4SI_type_node, NULL_TREE);
8802 tree v16qi_ftype_v8hi_v8hi
8803 = build_function_type_list (V16QI_type_node,
8804 V8HI_type_node, V8HI_type_node, NULL_TREE);
8805 tree v4si_ftype_v16qi_v4si
8806 = build_function_type_list (V4SI_type_node,
8807 V16QI_type_node, V4SI_type_node, NULL_TREE);
8808 tree v4si_ftype_v16qi_v16qi
8809 = build_function_type_list (V4SI_type_node,
8810 V16QI_type_node, V16QI_type_node, NULL_TREE);
8811 tree v4si_ftype_v8hi_v4si
8812 = build_function_type_list (V4SI_type_node,
8813 V8HI_type_node, V4SI_type_node, NULL_TREE);
8814 tree v4si_ftype_v8hi
8815 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8816 tree int_ftype_v4si_v4si
8817 = build_function_type_list (integer_type_node,
8818 V4SI_type_node, V4SI_type_node, NULL_TREE);
8819 tree int_ftype_v4sf_v4sf
8820 = build_function_type_list (integer_type_node,
8821 V4SF_type_node, V4SF_type_node, NULL_TREE);
8822 tree int_ftype_v16qi_v16qi
8823 = build_function_type_list (integer_type_node,
8824 V16QI_type_node, V16QI_type_node, NULL_TREE);
8825 tree int_ftype_v8hi_v8hi
8826 = build_function_type_list (integer_type_node,
8827 V8HI_type_node, V8HI_type_node, NULL_TREE);
8829 /* Add the simple ternary operators. */
8830 d = (struct builtin_description *) bdesc_3arg;
8831 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8833 enum machine_mode mode0, mode1, mode2, mode3;
8835 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8836 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8847 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8850 mode0 = insn_data[d->icode].operand[0].mode;
8851 mode1 = insn_data[d->icode].operand[1].mode;
8852 mode2 = insn_data[d->icode].operand[2].mode;
8853 mode3 = insn_data[d->icode].operand[3].mode;
8856 /* When all four are of the same mode. */
8857 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8862 type = opaque_ftype_opaque_opaque_opaque;
8865 type = v4si_ftype_v4si_v4si_v4si;
8868 type = v4sf_ftype_v4sf_v4sf_v4sf;
8871 type = v8hi_ftype_v8hi_v8hi_v8hi;
8874 type = v16qi_ftype_v16qi_v16qi_v16qi;
8880 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8885 type = v4si_ftype_v4si_v4si_v16qi;
8888 type = v4sf_ftype_v4sf_v4sf_v16qi;
8891 type = v8hi_ftype_v8hi_v8hi_v16qi;
8894 type = v16qi_ftype_v16qi_v16qi_v16qi;
8900 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8901 && mode3 == V4SImode)
8902 type = v4si_ftype_v16qi_v16qi_v4si;
8903 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8904 && mode3 == V4SImode)
8905 type = v4si_ftype_v8hi_v8hi_v4si;
8906 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8907 && mode3 == V4SImode)
8908 type = v4sf_ftype_v4sf_v4sf_v4si;
8910 /* vchar, vchar, vchar, 4 bit literal. */
8911 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8913 type = v16qi_ftype_v16qi_v16qi_int;
8915 /* vshort, vshort, vshort, 4 bit literal. */
8916 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8918 type = v8hi_ftype_v8hi_v8hi_int;
8920 /* vint, vint, vint, 4 bit literal. */
8921 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8923 type = v4si_ftype_v4si_v4si_int;
8925 /* vfloat, vfloat, vfloat, 4 bit literal. */
8926 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8928 type = v4sf_ftype_v4sf_v4sf_int;
8933 def_builtin (d->mask, d->name, type, d->code);
8936 /* Add the simple binary operators. */
8937 d = (struct builtin_description *) bdesc_2arg;
8938 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8940 enum machine_mode mode0, mode1, mode2;
8942 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8943 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8953 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8956 mode0 = insn_data[d->icode].operand[0].mode;
8957 mode1 = insn_data[d->icode].operand[1].mode;
8958 mode2 = insn_data[d->icode].operand[2].mode;
8961 /* When all three operands are of the same mode. */
8962 if (mode0 == mode1 && mode1 == mode2)
8967 type = opaque_ftype_opaque_opaque;
8970 type = v4sf_ftype_v4sf_v4sf;
8973 type = v4si_ftype_v4si_v4si;
8976 type = v16qi_ftype_v16qi_v16qi;
8979 type = v8hi_ftype_v8hi_v8hi;
8982 type = v2si_ftype_v2si_v2si;
8985 type = v2sf_ftype_v2sf_v2sf;
8988 type = int_ftype_int_int;
8995 /* A few other combos we really don't want to do manually. */
8997 /* vint, vfloat, vfloat. */
8998 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8999 type = v4si_ftype_v4sf_v4sf;
9001 /* vshort, vchar, vchar. */
9002 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
9003 type = v8hi_ftype_v16qi_v16qi;
9005 /* vint, vshort, vshort. */
9006 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
9007 type = v4si_ftype_v8hi_v8hi;
9009 /* vshort, vint, vint. */
9010 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
9011 type = v8hi_ftype_v4si_v4si;
9013 /* vchar, vshort, vshort. */
9014 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
9015 type = v16qi_ftype_v8hi_v8hi;
9017 /* vint, vchar, vint. */
9018 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
9019 type = v4si_ftype_v16qi_v4si;
9021 /* vint, vchar, vchar. */
9022 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
9023 type = v4si_ftype_v16qi_v16qi;
9025 /* vint, vshort, vint. */
9026 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
9027 type = v4si_ftype_v8hi_v4si;
9029 /* vint, vint, 5 bit literal. */
9030 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
9031 type = v4si_ftype_v4si_int;
9033 /* vshort, vshort, 5 bit literal. */
9034 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
9035 type = v8hi_ftype_v8hi_int;
9037 /* vchar, vchar, 5 bit literal. */
9038 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
9039 type = v16qi_ftype_v16qi_int;
9041 /* vfloat, vint, 5 bit literal. */
9042 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
9043 type = v4sf_ftype_v4si_int;
9045 /* vint, vfloat, 5 bit literal. */
9046 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
9047 type = v4si_ftype_v4sf_int;
9049 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
9050 type = v2si_ftype_int_int;
9052 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
9053 type = v2si_ftype_v2si_char;
9055 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
9056 type = v2si_ftype_int_char;
9061 gcc_assert (mode0 == SImode);
9065 type = int_ftype_v4si_v4si;
9068 type = int_ftype_v4sf_v4sf;
9071 type = int_ftype_v16qi_v16qi;
9074 type = int_ftype_v8hi_v8hi;
9081 def_builtin (d->mask, d->name, type, d->code);
9084 /* Add the simple unary operators. */
9085 d = (struct builtin_description *) bdesc_1arg;
9086 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9088 enum machine_mode mode0, mode1;
9090 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9091 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9100 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9103 mode0 = insn_data[d->icode].operand[0].mode;
9104 mode1 = insn_data[d->icode].operand[1].mode;
9107 if (mode0 == V4SImode && mode1 == QImode)
9108 type = v4si_ftype_int;
9109 else if (mode0 == V8HImode && mode1 == QImode)
9110 type = v8hi_ftype_int;
9111 else if (mode0 == V16QImode && mode1 == QImode)
9112 type = v16qi_ftype_int;
9113 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9114 type = opaque_ftype_opaque;
9115 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9116 type = v4sf_ftype_v4sf;
9117 else if (mode0 == V8HImode && mode1 == V16QImode)
9118 type = v8hi_ftype_v16qi;
9119 else if (mode0 == V4SImode && mode1 == V8HImode)
9120 type = v4si_ftype_v8hi;
9121 else if (mode0 == V2SImode && mode1 == V2SImode)
9122 type = v2si_ftype_v2si;
9123 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9124 type = v2sf_ftype_v2sf;
9125 else if (mode0 == V2SFmode && mode1 == V2SImode)
9126 type = v2sf_ftype_v2si;
9127 else if (mode0 == V2SImode && mode1 == V2SFmode)
9128 type = v2si_ftype_v2sf;
9129 else if (mode0 == V2SImode && mode1 == QImode)
9130 type = v2si_ftype_char;
9134 def_builtin (d->mask, d->name, type, d->code);
9139 rs6000_init_libfuncs (void)
9141 if (!TARGET_HARD_FLOAT)
9144 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
9145 && !TARGET_POWER2 && !TARGET_POWERPC)
9147 /* AIX library routines for float->int conversion. */
9148 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9149 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9150 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9151 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9154 if (!TARGET_IEEEQUAD)
9155 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9156 if (!TARGET_XL_COMPAT)
9158 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9159 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9160 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9161 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9165 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9166 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9167 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9168 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9172 /* 32-bit SVR4 quad floating point routines. */
9174 set_optab_libfunc (add_optab, TFmode, "_q_add");
9175 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9176 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9177 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9178 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9179 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9180 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9182 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9183 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9184 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9185 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9186 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9187 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9189 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9190 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9191 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9192 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9193 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9194 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9195 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9196 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9201 /* Expand a block clear operation, and return 1 if successful. Return 0
9202 if we should let the compiler generate normal code.
9204 operands[0] is the destination
9205 operands[1] is the length
9206 operands[3] is the alignment */
9209 expand_block_clear (rtx operands[])
9211 rtx orig_dest = operands[0];
9212 rtx bytes_rtx = operands[1];
9213 rtx align_rtx = operands[3];
9214 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9215 HOST_WIDE_INT align;
9216 HOST_WIDE_INT bytes;
9221 /* If this is not a fixed size move, just call memcpy */
9225 /* This must be a fixed size alignment */
9226 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9227 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9229 /* Anything to clear? */
9230 bytes = INTVAL (bytes_rtx);
9234 /* Use the builtin memset after a point, to avoid huge code bloat.
9235 When optimize_size, avoid any significant code bloat; calling
9236 memset is about 4 instructions, so allow for one instruction to
9237 load zero and three to do clearing. */
9238 if (TARGET_ALTIVEC && align >= 128)
9240 else if (TARGET_POWERPC64 && align >= 32)
9245 if (optimize_size && bytes > 3 * clear_step)
9247 if (! optimize_size && bytes > 8 * clear_step)
9250 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9252 enum machine_mode mode = BLKmode;
9255 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9260 else if (bytes >= 8 && TARGET_POWERPC64
9261 /* 64-bit loads and stores require word-aligned
9263 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9268 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9269 { /* move 4 bytes */
9273 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9274 { /* move 2 bytes */
9278 else /* move 1 byte at a time */
9284 dest = adjust_address (orig_dest, mode, offset);
9286 emit_move_insn (dest, CONST0_RTX (mode));
9293 /* Expand a block move operation, and return 1 if successful. Return 0
9294 if we should let the compiler generate normal code.
9296 operands[0] is the destination
9297 operands[1] is the source
9298 operands[2] is the length
9299 operands[3] is the alignment */
9301 #define MAX_MOVE_REG 4
9304 expand_block_move (rtx operands[])
9306 rtx orig_dest = operands[0];
9307 rtx orig_src = operands[1];
9308 rtx bytes_rtx = operands[2];
9309 rtx align_rtx = operands[3];
9310 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9315 rtx stores[MAX_MOVE_REG];
9318 /* If this is not a fixed size move, just call memcpy */
9322 /* This must be a fixed size alignment */
9323 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9324 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9326 /* Anything to move? */
9327 bytes = INTVAL (bytes_rtx);
9331 /* store_one_arg depends on expand_block_move to handle at least the size of
9332 reg_parm_stack_space. */
9333 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9336 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9339 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9340 rtx (*mov) (rtx, rtx);
9342 enum machine_mode mode = BLKmode;
9345 /* Altivec first, since it will be faster than a string move
9346 when it applies, and usually not significantly larger. */
9347 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9351 gen_func.mov = gen_movv4si;
9353 else if (TARGET_STRING
9354 && bytes > 24 /* move up to 32 bytes at a time */
9362 && ! fixed_regs[12])
9364 move_bytes = (bytes > 32) ? 32 : bytes;
9365 gen_func.movmemsi = gen_movmemsi_8reg;
9367 else if (TARGET_STRING
9368 && bytes > 16 /* move up to 24 bytes at a time */
9374 && ! fixed_regs[10])
9376 move_bytes = (bytes > 24) ? 24 : bytes;
9377 gen_func.movmemsi = gen_movmemsi_6reg;
9379 else if (TARGET_STRING
9380 && bytes > 8 /* move up to 16 bytes at a time */
9386 move_bytes = (bytes > 16) ? 16 : bytes;
9387 gen_func.movmemsi = gen_movmemsi_4reg;
9389 else if (bytes >= 8 && TARGET_POWERPC64
9390 /* 64-bit loads and stores require word-aligned
9392 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9396 gen_func.mov = gen_movdi;
9398 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9399 { /* move up to 8 bytes at a time */
9400 move_bytes = (bytes > 8) ? 8 : bytes;
9401 gen_func.movmemsi = gen_movmemsi_2reg;
9403 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9404 { /* move 4 bytes */
9407 gen_func.mov = gen_movsi;
9409 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9410 { /* move 2 bytes */
9413 gen_func.mov = gen_movhi;
9415 else if (TARGET_STRING && bytes > 1)
9416 { /* move up to 4 bytes at a time */
9417 move_bytes = (bytes > 4) ? 4 : bytes;
9418 gen_func.movmemsi = gen_movmemsi_1reg;
9420 else /* move 1 byte at a time */
9424 gen_func.mov = gen_movqi;
9427 src = adjust_address (orig_src, mode, offset);
9428 dest = adjust_address (orig_dest, mode, offset);
9430 if (mode != BLKmode)
9432 rtx tmp_reg = gen_reg_rtx (mode);
9434 emit_insn ((*gen_func.mov) (tmp_reg, src));
9435 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9438 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9441 for (i = 0; i < num_reg; i++)
9442 emit_insn (stores[i]);
9446 if (mode == BLKmode)
9448 /* Move the address into scratch registers. The movmemsi
9449 patterns require zero offset. */
9450 if (!REG_P (XEXP (src, 0)))
9452 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9453 src = replace_equiv_address (src, src_reg);
9455 set_mem_size (src, GEN_INT (move_bytes));
9457 if (!REG_P (XEXP (dest, 0)))
9459 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9460 dest = replace_equiv_address (dest, dest_reg);
9462 set_mem_size (dest, GEN_INT (move_bytes));
9464 emit_insn ((*gen_func.movmemsi) (dest, src,
9465 GEN_INT (move_bytes & 31),
9474 /* Return a string to perform a load_multiple operation.
9475 operands[0] is the vector.
9476 operands[1] is the source address.
9477 operands[2] is the first destination register. */
9480 rs6000_output_load_multiple (rtx operands[3])
9482 /* We have to handle the case where the pseudo used to contain the address
9483 is assigned to one of the output registers. */
9485 int words = XVECLEN (operands[0], 0);
9488 if (XVECLEN (operands[0], 0) == 1)
9489 return "{l|lwz} %2,0(%1)";
9491 for (i = 0; i < words; i++)
9492 if (refers_to_regno_p (REGNO (operands[2]) + i,
9493 REGNO (operands[2]) + i + 1, operands[1], 0))
9497 xop[0] = GEN_INT (4 * (words-1));
9498 xop[1] = operands[1];
9499 xop[2] = operands[2];
9500 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9505 xop[0] = GEN_INT (4 * (words-1));
9506 xop[1] = operands[1];
9507 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9508 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9513 for (j = 0; j < words; j++)
9516 xop[0] = GEN_INT (j * 4);
9517 xop[1] = operands[1];
9518 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9519 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9521 xop[0] = GEN_INT (i * 4);
9522 xop[1] = operands[1];
9523 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9528 return "{lsi|lswi} %2,%1,%N0";
9532 /* A validation routine: say whether CODE, a condition code, and MODE
9533 match. The other alternatives either don't make sense or should
9534 never be generated. */
9537 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9539 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
9540 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9541 && GET_MODE_CLASS (mode) == MODE_CC);
9543 /* These don't make sense. */
9544 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
9545 || mode != CCUNSmode);
9547 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
9548 || mode == CCUNSmode);
9550 gcc_assert (mode == CCFPmode
9551 || (code != ORDERED && code != UNORDERED
9552 && code != UNEQ && code != LTGT
9553 && code != UNGT && code != UNLT
9554 && code != UNGE && code != UNLE));
9556 /* These should never be generated except for
9557 flag_finite_math_only. */
9558 gcc_assert (mode != CCFPmode
9559 || flag_finite_math_only
9560 || (code != LE && code != GE
9561 && code != UNEQ && code != LTGT
9562 && code != UNGT && code != UNLT));
9564 /* These are invalid; the information is not there. */
9565 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
9569 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9570 mask required to convert the result of a rotate insn into a shift
9571 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9574 includes_lshift_p (rtx shiftop, rtx andop)
9576 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9578 shift_mask <<= INTVAL (shiftop);
9580 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9583 /* Similar, but for right shift. */
9586 includes_rshift_p (rtx shiftop, rtx andop)
9588 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9590 shift_mask >>= INTVAL (shiftop);
9592 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9595 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9596 to perform a left shift. It must have exactly SHIFTOP least
9597 significant 0's, then one or more 1's, then zero or more 0's. */
9600 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9602 if (GET_CODE (andop) == CONST_INT)
9604 HOST_WIDE_INT c, lsb, shift_mask;
9607 if (c == 0 || c == ~0)
9611 shift_mask <<= INTVAL (shiftop);
9613 /* Find the least significant one bit. */
9616 /* It must coincide with the LSB of the shift mask. */
9617 if (-lsb != shift_mask)
9620 /* Invert to look for the next transition (if any). */
9623 /* Remove the low group of ones (originally low group of zeros). */
9626 /* Again find the lsb, and check we have all 1's above. */
9630 else if (GET_CODE (andop) == CONST_DOUBLE
9631 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9633 HOST_WIDE_INT low, high, lsb;
9634 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9636 low = CONST_DOUBLE_LOW (andop);
9637 if (HOST_BITS_PER_WIDE_INT < 64)
9638 high = CONST_DOUBLE_HIGH (andop);
9640 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9641 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9644 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9646 shift_mask_high = ~0;
9647 if (INTVAL (shiftop) > 32)
9648 shift_mask_high <<= INTVAL (shiftop) - 32;
9652 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9659 return high == -lsb;
9662 shift_mask_low = ~0;
9663 shift_mask_low <<= INTVAL (shiftop);
9667 if (-lsb != shift_mask_low)
9670 if (HOST_BITS_PER_WIDE_INT < 64)
9675 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9678 return high == -lsb;
9682 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9688 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9689 to perform a left shift. It must have SHIFTOP or more least
9690 significant 0's, with the remainder of the word 1's. */
9693 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9695 if (GET_CODE (andop) == CONST_INT)
9697 HOST_WIDE_INT c, lsb, shift_mask;
9700 shift_mask <<= INTVAL (shiftop);
9703 /* Find the least significant one bit. */
9706 /* It must be covered by the shift mask.
9707 This test also rejects c == 0. */
9708 if ((lsb & shift_mask) == 0)
9711 /* Check we have all 1's above the transition, and reject all 1's. */
9712 return c == -lsb && lsb != 1;
9714 else if (GET_CODE (andop) == CONST_DOUBLE
9715 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9717 HOST_WIDE_INT low, lsb, shift_mask_low;
9719 low = CONST_DOUBLE_LOW (andop);
9721 if (HOST_BITS_PER_WIDE_INT < 64)
9723 HOST_WIDE_INT high, shift_mask_high;
9725 high = CONST_DOUBLE_HIGH (andop);
9729 shift_mask_high = ~0;
9730 if (INTVAL (shiftop) > 32)
9731 shift_mask_high <<= INTVAL (shiftop) - 32;
9735 if ((lsb & shift_mask_high) == 0)
9738 return high == -lsb;
9744 shift_mask_low = ~0;
9745 shift_mask_low <<= INTVAL (shiftop);
9749 if ((lsb & shift_mask_low) == 0)
9752 return low == -lsb && lsb != 1;
9758 /* Return 1 if operands will generate a valid arguments to rlwimi
9759 instruction for insert with right shift in 64-bit mode. The mask may
9760 not start on the first bit or stop on the last bit because wrap-around
9761 effects of instruction do not correspond to semantics of RTL insn. */
9764 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9766 if (INTVAL (startop) < 64
9767 && INTVAL (startop) > 32
9768 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9769 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9770 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9771 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9772 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9778 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9779 for lfq and stfq insns iff the registers are hard registers. */
9782 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
9784 /* We might have been passed a SUBREG. */
9785 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
9788 /* We might have been passed non floating point registers. */
9789 if (!FP_REGNO_P (REGNO (reg1))
9790 || !FP_REGNO_P (REGNO (reg2)))
9793 return (REGNO (reg1) == REGNO (reg2) - 1);
9796 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9797 addr1 and addr2 must be in consecutive memory locations
9798 (addr2 == addr1 + 8). */
9801 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
9804 unsigned int reg1, reg2;
9805 int offset1, offset2;
9807 /* The mems cannot be volatile. */
9808 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9811 addr1 = XEXP (mem1, 0);
9812 addr2 = XEXP (mem2, 0);
9814 /* Extract an offset (if used) from the first addr. */
9815 if (GET_CODE (addr1) == PLUS)
9817 /* If not a REG, return zero. */
9818 if (GET_CODE (XEXP (addr1, 0)) != REG)
9822 reg1 = REGNO (XEXP (addr1, 0));
9823 /* The offset must be constant! */
9824 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
9826 offset1 = INTVAL (XEXP (addr1, 1));
9829 else if (GET_CODE (addr1) != REG)
9833 reg1 = REGNO (addr1);
9834 /* This was a simple (mem (reg)) expression. Offset is 0. */
9838 /* And now for the second addr. */
9839 if (GET_CODE (addr2) == PLUS)
9841 /* If not a REG, return zero. */
9842 if (GET_CODE (XEXP (addr2, 0)) != REG)
9846 reg2 = REGNO (XEXP (addr2, 0));
9847 /* The offset must be constant. */
9848 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9850 offset2 = INTVAL (XEXP (addr2, 1));
9853 else if (GET_CODE (addr2) != REG)
9857 reg2 = REGNO (addr2);
9858 /* This was a simple (mem (reg)) expression. Offset is 0. */
9862 /* Both of these must have the same base register. */
9866 /* The offset for the second addr must be 8 more than the first addr. */
9867 if (offset2 != offset1 + 8)
9870 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9875 /* Return the register class of a scratch register needed to copy IN into
9876 or out of a register in CLASS in MODE. If it can be done directly,
9877 NO_REGS is returned. */
9880 rs6000_secondary_reload_class (enum reg_class class,
9881 enum machine_mode mode ATTRIBUTE_UNUSED,
9886 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9888 && MACHOPIC_INDIRECT
9892 /* We cannot copy a symbolic operand directly into anything
9893 other than BASE_REGS for TARGET_ELF. So indicate that a
9894 register from BASE_REGS is needed as an intermediate
9897 On Darwin, pic addresses require a load from memory, which
9898 needs a base register. */
9899 if (class != BASE_REGS
9900 && (GET_CODE (in) == SYMBOL_REF
9901 || GET_CODE (in) == HIGH
9902 || GET_CODE (in) == LABEL_REF
9903 || GET_CODE (in) == CONST))
9907 if (GET_CODE (in) == REG)
9910 if (regno >= FIRST_PSEUDO_REGISTER)
9912 regno = true_regnum (in);
9913 if (regno >= FIRST_PSEUDO_REGISTER)
9917 else if (GET_CODE (in) == SUBREG)
9919 regno = true_regnum (in);
9920 if (regno >= FIRST_PSEUDO_REGISTER)
9926 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9928 if (class == GENERAL_REGS || class == BASE_REGS
9929 || (regno >= 0 && INT_REGNO_P (regno)))
9932 /* Constants, memory, and FP registers can go into FP registers. */
9933 if ((regno == -1 || FP_REGNO_P (regno))
9934 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
9937 /* Memory, and AltiVec registers can go into AltiVec registers. */
9938 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
9939 && class == ALTIVEC_REGS)
9942 /* We can copy among the CR registers. */
9943 if ((class == CR_REGS || class == CR0_REGS)
9944 && regno >= 0 && CR_REGNO_P (regno))
9947 /* Otherwise, we need GENERAL_REGS. */
9948 return GENERAL_REGS;
9951 /* Given a comparison operation, return the bit number in CCR to test. We
9952 know this is a valid comparison.
9954 SCC_P is 1 if this is for an scc. That means that %D will have been
9955 used instead of %C, so the bits will be in different places.
9957 Return -1 if OP isn't a valid comparison for some reason. */
9960 ccr_bit (rtx op, int scc_p)
9962 enum rtx_code code = GET_CODE (op);
9963 enum machine_mode cc_mode;
9968 if (!COMPARISON_P (op))
9973 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
9975 cc_mode = GET_MODE (reg);
9976 cc_regnum = REGNO (reg);
9977 base_bit = 4 * (cc_regnum - CR0_REGNO);
9979 validate_condition_mode (code, cc_mode);
9981 /* When generating a sCOND operation, only positive conditions are
9984 || code == EQ || code == GT || code == LT || code == UNORDERED
9985 || code == GTU || code == LTU);
9990 return scc_p ? base_bit + 3 : base_bit + 2;
9992 return base_bit + 2;
9993 case GT: case GTU: case UNLE:
9994 return base_bit + 1;
9995 case LT: case LTU: case UNGE:
9997 case ORDERED: case UNORDERED:
9998 return base_bit + 3;
10001 /* If scc, we will have done a cror to put the bit in the
10002 unordered position. So test that bit. For integer, this is ! LT
10003 unless this is an scc insn. */
10004 return scc_p ? base_bit + 3 : base_bit;
10007 return scc_p ? base_bit + 3 : base_bit + 1;
10010 gcc_unreachable ();
10014 /* Return the GOT register. */
10017 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10019 /* The second flow pass currently (June 1999) can't update
10020 regs_ever_live without disturbing other parts of the compiler, so
10021 update it here to make the prolog/epilogue code happy. */
10022 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
10023 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10025 current_function_uses_pic_offset_table = 1;
10027 return pic_offset_table_rtx;
10030 /* Function to init struct machine_function.
10031 This will be called, via a pointer variable,
10032 from push_function_context. */
10034 static struct machine_function *
10035 rs6000_init_machine_status (void)
10037 return ggc_alloc_cleared (sizeof (machine_function));
10040 /* These macros test for integers and extract the low-order bits. */
10042 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10043 && GET_MODE (X) == VOIDmode)
10045 #define INT_LOWPART(X) \
10046 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10049 extract_MB (rtx op)
10052 unsigned long val = INT_LOWPART (op);
10054 /* If the high bit is zero, the value is the first 1 bit we find
10056 if ((val & 0x80000000) == 0)
10058 gcc_assert (val & 0xffffffff);
10061 while (((val <<= 1) & 0x80000000) == 0)
10066 /* If the high bit is set and the low bit is not, or the mask is all
10067 1's, the value is zero. */
10068 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10071 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10074 while (((val >>= 1) & 1) != 0)
10081 extract_ME (rtx op)
10084 unsigned long val = INT_LOWPART (op);
10086 /* If the low bit is zero, the value is the first 1 bit we find from
10088 if ((val & 1) == 0)
10090 gcc_assert (val & 0xffffffff);
10093 while (((val >>= 1) & 1) == 0)
10099 /* If the low bit is set and the high bit is not, or the mask is all
10100 1's, the value is 31. */
10101 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10104 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10107 while (((val <<= 1) & 0x80000000) != 0)
10113 /* Locate some local-dynamic symbol still in use by this function
10114 so that we can print its name in some tls_ld pattern. */
10116 static const char *
10117 rs6000_get_some_local_dynamic_name (void)
10121 if (cfun->machine->some_ld_name)
10122 return cfun->machine->some_ld_name;
10124 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10126 && for_each_rtx (&PATTERN (insn),
10127 rs6000_get_some_local_dynamic_name_1, 0))
10128 return cfun->machine->some_ld_name;
10130 gcc_unreachable ();
10133 /* Helper function for rs6000_get_some_local_dynamic_name. */
10136 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10140 if (GET_CODE (x) == SYMBOL_REF)
10142 const char *str = XSTR (x, 0);
10143 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10145 cfun->machine->some_ld_name = str;
10153 /* Write out a function code label. */
10156 rs6000_output_function_entry (FILE *file, const char *fname)
10158 if (fname[0] != '.')
10160 switch (DEFAULT_ABI)
10163 gcc_unreachable ();
10169 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10178 RS6000_OUTPUT_BASENAME (file, fname);
10180 assemble_name (file, fname);
10183 /* Print an operand. Recognize special options, documented below. */
10186 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10187 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10189 #define SMALL_DATA_RELOC "sda21"
10190 #define SMALL_DATA_REG 0
10194 print_operand (FILE *file, rtx x, int code)
10198 unsigned HOST_WIDE_INT uval;
10203 /* Write out an instruction after the call which may be replaced
10204 with glue code by the loader. This depends on the AIX version. */
10205 asm_fprintf (file, RS6000_CALL_GLUE);
10208 /* %a is output_address. */
10211 /* If X is a constant integer whose low-order 5 bits are zero,
10212 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10213 in the AIX assembler where "sri" with a zero shift count
10214 writes a trash instruction. */
10215 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10222 /* If constant, low-order 16 bits of constant, unsigned.
10223 Otherwise, write normally. */
10225 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10227 print_operand (file, x, 0);
10231 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10232 for 64-bit mask direction. */
10233 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10236 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10240 /* X is a CR register. Print the number of the GT bit of the CR. */
10241 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10242 output_operand_lossage ("invalid %%E value");
10244 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10248 /* Like 'J' but get to the EQ bit. */
10249 gcc_assert (GET_CODE (x) == REG);
10251 /* Bit 1 is EQ bit. */
10252 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
10254 fprintf (file, "%d", i);
10258 /* X is a CR register. Print the number of the EQ bit of the CR */
10259 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10260 output_operand_lossage ("invalid %%E value");
10262 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10266 /* X is a CR register. Print the shift count needed to move it
10267 to the high-order four bits. */
10268 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10269 output_operand_lossage ("invalid %%f value");
10271 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10275 /* Similar, but print the count for the rotate in the opposite
10277 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10278 output_operand_lossage ("invalid %%F value");
10280 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10284 /* X is a constant integer. If it is negative, print "m",
10285 otherwise print "z". This is to make an aze or ame insn. */
10286 if (GET_CODE (x) != CONST_INT)
10287 output_operand_lossage ("invalid %%G value");
10288 else if (INTVAL (x) >= 0)
10295 /* If constant, output low-order five bits. Otherwise, write
10298 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10300 print_operand (file, x, 0);
10304 /* If constant, output low-order six bits. Otherwise, write
10307 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10309 print_operand (file, x, 0);
10313 /* Print `i' if this is a constant, else nothing. */
10319 /* Write the bit number in CCR for jump. */
10320 i = ccr_bit (x, 0);
10322 output_operand_lossage ("invalid %%j code");
10324 fprintf (file, "%d", i);
10328 /* Similar, but add one for shift count in rlinm for scc and pass
10329 scc flag to `ccr_bit'. */
10330 i = ccr_bit (x, 1);
10332 output_operand_lossage ("invalid %%J code");
10334 /* If we want bit 31, write a shift count of zero, not 32. */
10335 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10339 /* X must be a constant. Write the 1's complement of the
10342 output_operand_lossage ("invalid %%k value");
10344 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10348 /* X must be a symbolic constant on ELF. Write an
10349 expression suitable for an 'addi' that adds in the low 16
10350 bits of the MEM. */
10351 if (GET_CODE (x) != CONST)
10353 print_operand_address (file, x);
10354 fputs ("@l", file);
10358 if (GET_CODE (XEXP (x, 0)) != PLUS
10359 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10360 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10361 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10362 output_operand_lossage ("invalid %%K value");
10363 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10364 fputs ("@l", file);
10365 /* For GNU as, there must be a non-alphanumeric character
10366 between 'l' and the number. The '-' is added by
10367 print_operand() already. */
10368 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10370 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10374 /* %l is output_asm_label. */
10377 /* Write second word of DImode or DFmode reference. Works on register
10378 or non-indexed memory only. */
10379 if (GET_CODE (x) == REG)
10380 fputs (reg_names[REGNO (x) + 1], file);
10381 else if (GET_CODE (x) == MEM)
10383 /* Handle possible auto-increment. Since it is pre-increment and
10384 we have already done it, we can just use an offset of word. */
10385 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10386 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10387 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10390 output_address (XEXP (adjust_address_nv (x, SImode,
10394 if (small_data_operand (x, GET_MODE (x)))
10395 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10396 reg_names[SMALL_DATA_REG]);
10401 /* MB value for a mask operand. */
10402 if (! mask_operand (x, SImode))
10403 output_operand_lossage ("invalid %%m value");
10405 fprintf (file, "%d", extract_MB (x));
10409 /* ME value for a mask operand. */
10410 if (! mask_operand (x, SImode))
10411 output_operand_lossage ("invalid %%M value");
10413 fprintf (file, "%d", extract_ME (x));
10416 /* %n outputs the negative of its operand. */
10419 /* Write the number of elements in the vector times 4. */
10420 if (GET_CODE (x) != PARALLEL)
10421 output_operand_lossage ("invalid %%N value");
10423 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10427 /* Similar, but subtract 1 first. */
10428 if (GET_CODE (x) != PARALLEL)
10429 output_operand_lossage ("invalid %%O value");
10431 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10435 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10437 || INT_LOWPART (x) < 0
10438 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10439 output_operand_lossage ("invalid %%p value");
10441 fprintf (file, "%d", i);
10445 /* The operand must be an indirect memory reference. The result
10446 is the register name. */
10447 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10448 || REGNO (XEXP (x, 0)) >= 32)
10449 output_operand_lossage ("invalid %%P value");
10451 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10455 /* This outputs the logical code corresponding to a boolean
10456 expression. The expression may have one or both operands
10457 negated (if one, only the first one). For condition register
10458 logical operations, it will also treat the negated
10459 CR codes as NOTs, but not handle NOTs of them. */
10461 const char *const *t = 0;
10463 enum rtx_code code = GET_CODE (x);
10464 static const char * const tbl[3][3] = {
10465 { "and", "andc", "nor" },
10466 { "or", "orc", "nand" },
10467 { "xor", "eqv", "xor" } };
10471 else if (code == IOR)
10473 else if (code == XOR)
10476 output_operand_lossage ("invalid %%q value");
10478 if (GET_CODE (XEXP (x, 0)) != NOT)
10482 if (GET_CODE (XEXP (x, 1)) == NOT)
10500 /* X is a CR register. Print the mask for `mtcrf'. */
10501 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10502 output_operand_lossage ("invalid %%R value");
10504 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10508 /* Low 5 bits of 32 - value */
10510 output_operand_lossage ("invalid %%s value");
10512 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10516 /* PowerPC64 mask position. All 0's is excluded.
10517 CONST_INT 32-bit mask is considered sign-extended so any
10518 transition must occur within the CONST_INT, not on the boundary. */
10519 if (! mask64_operand (x, DImode))
10520 output_operand_lossage ("invalid %%S value");
10522 uval = INT_LOWPART (x);
10524 if (uval & 1) /* Clear Left */
10526 #if HOST_BITS_PER_WIDE_INT > 64
10527 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10531 else /* Clear Right */
10534 #if HOST_BITS_PER_WIDE_INT > 64
10535 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10541 gcc_assert (i >= 0);
10542 fprintf (file, "%d", i);
10546 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10547 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
10549 /* Bit 3 is OV bit. */
10550 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10552 /* If we want bit 31, write a shift count of zero, not 32. */
10553 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10557 /* Print the symbolic name of a branch target register. */
10558 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10559 && REGNO (x) != COUNT_REGISTER_REGNUM))
10560 output_operand_lossage ("invalid %%T value");
10561 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10562 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10564 fputs ("ctr", file);
10568 /* High-order 16 bits of constant for use in unsigned operand. */
10570 output_operand_lossage ("invalid %%u value");
10572 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10573 (INT_LOWPART (x) >> 16) & 0xffff);
10577 /* High-order 16 bits of constant for use in signed operand. */
10579 output_operand_lossage ("invalid %%v value");
10581 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10582 (INT_LOWPART (x) >> 16) & 0xffff);
10586 /* Print `u' if this has an auto-increment or auto-decrement. */
10587 if (GET_CODE (x) == MEM
10588 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10589 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10594 /* Print the trap code for this operand. */
10595 switch (GET_CODE (x))
10598 fputs ("eq", file); /* 4 */
10601 fputs ("ne", file); /* 24 */
10604 fputs ("lt", file); /* 16 */
10607 fputs ("le", file); /* 20 */
10610 fputs ("gt", file); /* 8 */
10613 fputs ("ge", file); /* 12 */
10616 fputs ("llt", file); /* 2 */
10619 fputs ("lle", file); /* 6 */
10622 fputs ("lgt", file); /* 1 */
10625 fputs ("lge", file); /* 5 */
10628 gcc_unreachable ();
10633 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10636 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10637 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10639 print_operand (file, x, 0);
10643 /* MB value for a PowerPC64 rldic operand. */
10644 val = (GET_CODE (x) == CONST_INT
10645 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10650 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10651 if ((val <<= 1) < 0)
10654 #if HOST_BITS_PER_WIDE_INT == 32
10655 if (GET_CODE (x) == CONST_INT && i >= 0)
10656 i += 32; /* zero-extend high-part was all 0's */
10657 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10659 val = CONST_DOUBLE_LOW (x);
10665 for ( ; i < 64; i++)
10666 if ((val <<= 1) < 0)
10671 fprintf (file, "%d", i + 1);
10675 if (GET_CODE (x) == MEM
10676 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10681 /* Like 'L', for third word of TImode */
10682 if (GET_CODE (x) == REG)
10683 fputs (reg_names[REGNO (x) + 2], file);
10684 else if (GET_CODE (x) == MEM)
10686 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10687 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10688 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10690 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10691 if (small_data_operand (x, GET_MODE (x)))
10692 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10693 reg_names[SMALL_DATA_REG]);
10698 /* X is a SYMBOL_REF. Write out the name preceded by a
10699 period and without any trailing data in brackets. Used for function
10700 names. If we are configured for System V (or the embedded ABI) on
10701 the PowerPC, do not emit the period, since those systems do not use
10702 TOCs and the like. */
10703 gcc_assert (GET_CODE (x) == SYMBOL_REF);
10705 /* Mark the decl as referenced so that cgraph will output the
10707 if (SYMBOL_REF_DECL (x))
10708 mark_decl_referenced (SYMBOL_REF_DECL (x));
10710 /* For macho, check to see if we need a stub. */
10713 const char *name = XSTR (x, 0);
10715 if (MACHOPIC_INDIRECT
10716 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10717 name = machopic_indirection_name (x, /*stub_p=*/true);
10719 assemble_name (file, name);
10721 else if (!DOT_SYMBOLS)
10722 assemble_name (file, XSTR (x, 0));
10724 rs6000_output_function_entry (file, XSTR (x, 0));
10728 /* Like 'L', for last word of TImode. */
10729 if (GET_CODE (x) == REG)
10730 fputs (reg_names[REGNO (x) + 3], file);
10731 else if (GET_CODE (x) == MEM)
10733 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10734 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10735 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10737 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10738 if (small_data_operand (x, GET_MODE (x)))
10739 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10740 reg_names[SMALL_DATA_REG]);
10744 /* Print AltiVec or SPE memory operand. */
10749 gcc_assert (GET_CODE (x) == MEM);
10755 /* Handle [reg]. */
10756 if (GET_CODE (tmp) == REG)
10758 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10761 /* Handle [reg+UIMM]. */
10762 else if (GET_CODE (tmp) == PLUS &&
10763 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10767 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
10769 x = INTVAL (XEXP (tmp, 1));
10770 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10774 /* Fall through. Must be [reg+reg]. */
10777 && GET_CODE (tmp) == AND
10778 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10779 && INTVAL (XEXP (tmp, 1)) == -16)
10780 tmp = XEXP (tmp, 0);
10781 if (GET_CODE (tmp) == REG)
10782 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
10785 gcc_assert (GET_CODE (tmp) == PLUS
10786 && REG_P (XEXP (tmp, 0))
10787 && REG_P (XEXP (tmp, 1)));
10789 if (REGNO (XEXP (tmp, 0)) == 0)
10790 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10791 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10793 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10794 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10800 if (GET_CODE (x) == REG)
10801 fprintf (file, "%s", reg_names[REGNO (x)]);
10802 else if (GET_CODE (x) == MEM)
10804 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10805 know the width from the mode. */
10806 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
10807 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10808 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10809 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
10810 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10811 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10813 output_address (XEXP (x, 0));
10816 output_addr_const (file, x);
10820 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10824 output_operand_lossage ("invalid %%xn code");
10828 /* Print the address of an operand. */
10831 print_operand_address (FILE *file, rtx x)
10833 if (GET_CODE (x) == REG)
10834 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
10835 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10836 || GET_CODE (x) == LABEL_REF)
10838 output_addr_const (file, x);
10839 if (small_data_operand (x, GET_MODE (x)))
10840 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10841 reg_names[SMALL_DATA_REG]);
10843 gcc_assert (!TARGET_TOC);
10845 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10847 gcc_assert (REG_P (XEXP (x, 0)));
10848 if (REGNO (XEXP (x, 0)) == 0)
10849 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10850 reg_names[ REGNO (XEXP (x, 0)) ]);
10852 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10853 reg_names[ REGNO (XEXP (x, 1)) ]);
10855 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
10856 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10857 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
10859 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10860 && CONSTANT_P (XEXP (x, 1)))
10862 output_addr_const (file, XEXP (x, 1));
10863 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10867 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10868 && CONSTANT_P (XEXP (x, 1)))
10870 fprintf (file, "lo16(");
10871 output_addr_const (file, XEXP (x, 1));
10872 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10875 else if (legitimate_constant_pool_address_p (x))
10877 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
10879 rtx contains_minus = XEXP (x, 1);
10883 /* Find the (minus (sym) (toc)) buried in X, and temporarily
10884 turn it into (sym) for output_addr_const. */
10885 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10886 contains_minus = XEXP (contains_minus, 0);
10888 minus = XEXP (contains_minus, 0);
10889 symref = XEXP (minus, 0);
10890 XEXP (contains_minus, 0) = symref;
10895 name = XSTR (symref, 0);
10896 newname = alloca (strlen (name) + sizeof ("@toc"));
10897 strcpy (newname, name);
10898 strcat (newname, "@toc");
10899 XSTR (symref, 0) = newname;
10901 output_addr_const (file, XEXP (x, 1));
10903 XSTR (symref, 0) = name;
10904 XEXP (contains_minus, 0) = minus;
10907 output_addr_const (file, XEXP (x, 1));
10909 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
10912 gcc_unreachable ();
10915 /* Target hook for assembling integer objects. The PowerPC version has
10916 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10917 is defined. It also needs to handle DI-mode objects on 64-bit
10921 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
10923 #ifdef RELOCATABLE_NEEDS_FIXUP
10924 /* Special handling for SI values. */
10925 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
10927 static int recurse = 0;
10929 /* For -mrelocatable, we mark all addresses that need to be fixed up
10930 in the .fixup section. */
10931 if (TARGET_RELOCATABLE
10932 && in_section != toc_section
10933 && in_section != text_section
10934 && !unlikely_text_section_p (in_section)
10936 && GET_CODE (x) != CONST_INT
10937 && GET_CODE (x) != CONST_DOUBLE
10943 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
10945 ASM_OUTPUT_LABEL (asm_out_file, buf);
10946 fprintf (asm_out_file, "\t.long\t(");
10947 output_addr_const (asm_out_file, x);
10948 fprintf (asm_out_file, ")@fixup\n");
10949 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
10950 ASM_OUTPUT_ALIGN (asm_out_file, 2);
10951 fprintf (asm_out_file, "\t.long\t");
10952 assemble_name (asm_out_file, buf);
10953 fprintf (asm_out_file, "\n\t.previous\n");
10957 /* Remove initial .'s to turn a -mcall-aixdesc function
10958 address into the address of the descriptor, not the function
10960 else if (GET_CODE (x) == SYMBOL_REF
10961 && XSTR (x, 0)[0] == '.'
10962 && DEFAULT_ABI == ABI_AIX)
10964 const char *name = XSTR (x, 0);
10965 while (*name == '.')
10968 fprintf (asm_out_file, "\t.long\t%s\n", name);
10972 #endif /* RELOCATABLE_NEEDS_FIXUP */
10973 return default_assemble_integer (x, size, aligned_p);
10976 #ifdef HAVE_GAS_HIDDEN
10977 /* Emit an assembler directive to set symbol visibility for DECL to
10978 VISIBILITY_TYPE. */
10981 rs6000_assemble_visibility (tree decl, int vis)
10983 /* Functions need to have their entry point symbol visibility set as
10984 well as their descriptor symbol visibility. */
10985 if (DEFAULT_ABI == ABI_AIX
10987 && TREE_CODE (decl) == FUNCTION_DECL)
10989 static const char * const visibility_types[] = {
10990 NULL, "internal", "hidden", "protected"
10993 const char *name, *type;
10995 name = ((* targetm.strip_name_encoding)
10996 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
10997 type = visibility_types[vis];
10999 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
11000 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
11003 default_assemble_visibility (decl, vis);
11008 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11010 /* Reversal of FP compares takes care -- an ordered compare
11011 becomes an unordered compare and vice versa. */
11012 if (mode == CCFPmode
11013 && (!flag_finite_math_only
11014 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11015 || code == UNEQ || code == LTGT))
11016 return reverse_condition_maybe_unordered (code);
11018 return reverse_condition (code);
11021 /* Generate a compare for CODE. Return a brand-new rtx that
11022 represents the result of the compare. */
11025 rs6000_generate_compare (enum rtx_code code)
11027 enum machine_mode comp_mode;
11028 rtx compare_result;
11030 if (rs6000_compare_fp_p)
11031 comp_mode = CCFPmode;
11032 else if (code == GTU || code == LTU
11033 || code == GEU || code == LEU)
11034 comp_mode = CCUNSmode;
11035 else if ((code == EQ || code == NE)
11036 && GET_CODE (rs6000_compare_op0) == SUBREG
11037 && GET_CODE (rs6000_compare_op1) == SUBREG
11038 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11039 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11040 /* These are unsigned values, perhaps there will be a later
11041 ordering compare that can be shared with this one.
11042 Unfortunately we cannot detect the signedness of the operands
11043 for non-subregs. */
11044 comp_mode = CCUNSmode;
11046 comp_mode = CCmode;
11048 /* First, the compare. */
11049 compare_result = gen_reg_rtx (comp_mode);
11051 /* SPE FP compare instructions on the GPRs. Yuck! */
11052 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11053 && rs6000_compare_fp_p)
11055 rtx cmp, or_result, compare_result2;
11056 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11058 if (op_mode == VOIDmode)
11059 op_mode = GET_MODE (rs6000_compare_op1);
11061 /* Note: The E500 comparison instructions set the GT bit (x +
11062 1), on success. This explains the mess. */
11066 case EQ: case UNEQ: case NE: case LTGT:
11070 cmp = flag_unsafe_math_optimizations
11071 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11072 rs6000_compare_op1)
11073 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11074 rs6000_compare_op1);
11078 cmp = flag_unsafe_math_optimizations
11079 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11080 rs6000_compare_op1)
11081 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11082 rs6000_compare_op1);
11086 gcc_unreachable ();
11090 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11094 cmp = flag_unsafe_math_optimizations
11095 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11096 rs6000_compare_op1)
11097 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11098 rs6000_compare_op1);
11102 cmp = flag_unsafe_math_optimizations
11103 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11104 rs6000_compare_op1)
11105 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11106 rs6000_compare_op1);
11110 gcc_unreachable ();
11114 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11118 cmp = flag_unsafe_math_optimizations
11119 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11120 rs6000_compare_op1)
11121 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11122 rs6000_compare_op1);
11126 cmp = flag_unsafe_math_optimizations
11127 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11128 rs6000_compare_op1)
11129 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11130 rs6000_compare_op1);
11134 gcc_unreachable ();
11138 gcc_unreachable ();
11141 /* Synthesize LE and GE from LT/GT || EQ. */
11142 if (code == LE || code == GE || code == LEU || code == GEU)
11148 case LE: code = LT; break;
11149 case GE: code = GT; break;
11150 case LEU: code = LT; break;
11151 case GEU: code = GT; break;
11152 default: gcc_unreachable ();
11155 compare_result2 = gen_reg_rtx (CCFPmode);
11161 cmp = flag_unsafe_math_optimizations
11162 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11163 rs6000_compare_op1)
11164 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11165 rs6000_compare_op1);
11169 cmp = flag_unsafe_math_optimizations
11170 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11171 rs6000_compare_op1)
11172 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11173 rs6000_compare_op1);
11177 gcc_unreachable ();
11181 /* OR them together. */
11182 or_result = gen_reg_rtx (CCFPmode);
11183 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11185 compare_result = or_result;
11190 if (code == NE || code == LTGT)
11200 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11201 CLOBBERs to match cmptf_internal2 pattern. */
11202 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11203 && GET_MODE (rs6000_compare_op0) == TFmode
11204 && !TARGET_IEEEQUAD
11205 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11206 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11208 gen_rtx_SET (VOIDmode,
11210 gen_rtx_COMPARE (comp_mode,
11211 rs6000_compare_op0,
11212 rs6000_compare_op1)),
11213 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11214 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11215 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11216 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11217 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11218 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11219 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11220 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11221 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11222 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11224 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11225 comp_mode = CCEQmode;
11226 compare_result = gen_reg_rtx (CCEQmode);
11228 emit_insn (gen_stack_protect_testdi (compare_result,
11229 rs6000_compare_op0, op1));
11231 emit_insn (gen_stack_protect_testsi (compare_result,
11232 rs6000_compare_op0, op1));
11235 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11236 gen_rtx_COMPARE (comp_mode,
11237 rs6000_compare_op0,
11238 rs6000_compare_op1)));
11241 /* Some kinds of FP comparisons need an OR operation;
11242 under flag_finite_math_only we don't bother. */
11243 if (rs6000_compare_fp_p
11244 && !flag_finite_math_only
11245 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11246 && (code == LE || code == GE
11247 || code == UNEQ || code == LTGT
11248 || code == UNGT || code == UNLT))
11250 enum rtx_code or1, or2;
11251 rtx or1_rtx, or2_rtx, compare2_rtx;
11252 rtx or_result = gen_reg_rtx (CCEQmode);
11256 case LE: or1 = LT; or2 = EQ; break;
11257 case GE: or1 = GT; or2 = EQ; break;
11258 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11259 case LTGT: or1 = LT; or2 = GT; break;
11260 case UNGT: or1 = UNORDERED; or2 = GT; break;
11261 case UNLT: or1 = UNORDERED; or2 = LT; break;
11262 default: gcc_unreachable ();
11264 validate_condition_mode (or1, comp_mode);
11265 validate_condition_mode (or2, comp_mode);
11266 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11267 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11268 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11269 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11271 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11273 compare_result = or_result;
11277 validate_condition_mode (code, GET_MODE (compare_result));
11279 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11283 /* Emit the RTL for an sCOND pattern. */
11286 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11289 enum machine_mode op_mode;
11290 enum rtx_code cond_code;
11292 condition_rtx = rs6000_generate_compare (code);
11293 cond_code = GET_CODE (condition_rtx);
11295 if (TARGET_E500 && rs6000_compare_fp_p
11296 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11300 PUT_MODE (condition_rtx, SImode);
11301 t = XEXP (condition_rtx, 0);
11303 gcc_assert (cond_code == NE || cond_code == EQ);
11305 if (cond_code == NE)
11306 emit_insn (gen_e500_flip_gt_bit (t, t));
11308 emit_insn (gen_move_from_CR_gt_bit (result, t));
11312 if (cond_code == NE
11313 || cond_code == GE || cond_code == LE
11314 || cond_code == GEU || cond_code == LEU
11315 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11317 rtx not_result = gen_reg_rtx (CCEQmode);
11318 rtx not_op, rev_cond_rtx;
11319 enum machine_mode cc_mode;
11321 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11323 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11324 SImode, XEXP (condition_rtx, 0), const0_rtx);
11325 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11326 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11327 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11330 op_mode = GET_MODE (rs6000_compare_op0);
11331 if (op_mode == VOIDmode)
11332 op_mode = GET_MODE (rs6000_compare_op1);
11334 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11336 PUT_MODE (condition_rtx, DImode);
11337 convert_move (result, condition_rtx, 0);
11341 PUT_MODE (condition_rtx, SImode);
11342 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11346 /* Emit a branch of kind CODE to location LOC. */
11349 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11351 rtx condition_rtx, loc_ref;
11353 condition_rtx = rs6000_generate_compare (code);
11354 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11355 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11356 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11357 loc_ref, pc_rtx)));
11360 /* Return the string to output a conditional branch to LABEL, which is
11361 the operand number of the label, or -1 if the branch is really a
11362 conditional return.
11364 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11365 condition code register and its mode specifies what kind of
11366 comparison we made.
11368 REVERSED is nonzero if we should reverse the sense of the comparison.
11370 INSN is the insn. */
11373 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11375 static char string[64];
11376 enum rtx_code code = GET_CODE (op);
11377 rtx cc_reg = XEXP (op, 0);
11378 enum machine_mode mode = GET_MODE (cc_reg);
11379 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11380 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11381 int really_reversed = reversed ^ need_longbranch;
11387 validate_condition_mode (code, mode);
11389 /* Work out which way this really branches. We could use
11390 reverse_condition_maybe_unordered here always but this
11391 makes the resulting assembler clearer. */
11392 if (really_reversed)
11394 /* Reversal of FP compares takes care -- an ordered compare
11395 becomes an unordered compare and vice versa. */
11396 if (mode == CCFPmode)
11397 code = reverse_condition_maybe_unordered (code);
11399 code = reverse_condition (code);
11402 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11404 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11409 /* Opposite of GT. */
11418 gcc_unreachable ();
11424 /* Not all of these are actually distinct opcodes, but
11425 we distinguish them for clarity of the resulting assembler. */
11426 case NE: case LTGT:
11427 ccode = "ne"; break;
11428 case EQ: case UNEQ:
11429 ccode = "eq"; break;
11431 ccode = "ge"; break;
11432 case GT: case GTU: case UNGT:
11433 ccode = "gt"; break;
11435 ccode = "le"; break;
11436 case LT: case LTU: case UNLT:
11437 ccode = "lt"; break;
11438 case UNORDERED: ccode = "un"; break;
11439 case ORDERED: ccode = "nu"; break;
11440 case UNGE: ccode = "nl"; break;
11441 case UNLE: ccode = "ng"; break;
11443 gcc_unreachable ();
11446 /* Maybe we have a guess as to how likely the branch is.
11447 The old mnemonics don't have a way to specify this information. */
11449 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11450 if (note != NULL_RTX)
11452 /* PROB is the difference from 50%. */
11453 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11455 /* Only hint for highly probable/improbable branches on newer
11456 cpus as static prediction overrides processor dynamic
11457 prediction. For older cpus we may as well always hint, but
11458 assume not taken for branches that are very close to 50% as a
11459 mispredicted taken branch is more expensive than a
11460 mispredicted not-taken branch. */
11461 if (rs6000_always_hint
11462 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
11464 if (abs (prob) > REG_BR_PROB_BASE / 20
11465 && ((prob > 0) ^ need_longbranch))
11473 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11475 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11477 /* We need to escape any '%' characters in the reg_names string.
11478 Assume they'd only be the first character.... */
11479 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11481 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11485 /* If the branch distance was too far, we may have to use an
11486 unconditional branch to go the distance. */
11487 if (need_longbranch)
11488 s += sprintf (s, ",$+8\n\tb %s", label);
11490 s += sprintf (s, ",%s", label);
11496 /* Return the string to flip the GT bit on a CR. */
11498 output_e500_flip_gt_bit (rtx dst, rtx src)
11500 static char string[64];
11503 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
11504 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
11507 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
11508 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
11510 sprintf (string, "crnot %d,%d", a, b);
11514 /* Return insn index for the vector compare instruction for given CODE,
11515 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11519 get_vec_cmp_insn (enum rtx_code code,
11520 enum machine_mode dest_mode,
11521 enum machine_mode op_mode)
11523 if (!TARGET_ALTIVEC)
11524 return INSN_NOT_AVAILABLE;
11529 if (dest_mode == V16QImode && op_mode == V16QImode)
11530 return UNSPEC_VCMPEQUB;
11531 if (dest_mode == V8HImode && op_mode == V8HImode)
11532 return UNSPEC_VCMPEQUH;
11533 if (dest_mode == V4SImode && op_mode == V4SImode)
11534 return UNSPEC_VCMPEQUW;
11535 if (dest_mode == V4SImode && op_mode == V4SFmode)
11536 return UNSPEC_VCMPEQFP;
11539 if (dest_mode == V4SImode && op_mode == V4SFmode)
11540 return UNSPEC_VCMPGEFP;
11542 if (dest_mode == V16QImode && op_mode == V16QImode)
11543 return UNSPEC_VCMPGTSB;
11544 if (dest_mode == V8HImode && op_mode == V8HImode)
11545 return UNSPEC_VCMPGTSH;
11546 if (dest_mode == V4SImode && op_mode == V4SImode)
11547 return UNSPEC_VCMPGTSW;
11548 if (dest_mode == V4SImode && op_mode == V4SFmode)
11549 return UNSPEC_VCMPGTFP;
11552 if (dest_mode == V16QImode && op_mode == V16QImode)
11553 return UNSPEC_VCMPGTUB;
11554 if (dest_mode == V8HImode && op_mode == V8HImode)
11555 return UNSPEC_VCMPGTUH;
11556 if (dest_mode == V4SImode && op_mode == V4SImode)
11557 return UNSPEC_VCMPGTUW;
11562 return INSN_NOT_AVAILABLE;
11565 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11566 DMODE is expected destination mode. This is a recursive function. */
11569 rs6000_emit_vector_compare (enum rtx_code rcode,
11571 enum machine_mode dmode)
11575 enum machine_mode dest_mode;
11576 enum machine_mode op_mode = GET_MODE (op1);
11578 gcc_assert (TARGET_ALTIVEC);
11579 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
11581 /* Floating point vector compare instructions uses destination V4SImode.
11582 Move destination to appropriate mode later. */
11583 if (dmode == V4SFmode)
11584 dest_mode = V4SImode;
11588 mask = gen_reg_rtx (dest_mode);
11589 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11591 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11593 bool swap_operands = false;
11594 bool try_again = false;
11599 swap_operands = true;
11604 swap_operands = true;
11608 /* Treat A != B as ~(A==B). */
11610 enum insn_code nor_code;
11611 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11614 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11615 gcc_assert (nor_code != CODE_FOR_nothing);
11616 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11618 if (dmode != dest_mode)
11620 rtx temp = gen_reg_rtx (dest_mode);
11621 convert_move (temp, mask, 0);
11631 /* Try GT/GTU/LT/LTU OR EQ */
11634 enum insn_code ior_code;
11635 enum rtx_code new_code;
11656 gcc_unreachable ();
11659 c_rtx = rs6000_emit_vector_compare (new_code,
11660 op0, op1, dest_mode);
11661 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11664 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11665 gcc_assert (ior_code != CODE_FOR_nothing);
11666 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11667 if (dmode != dest_mode)
11669 rtx temp = gen_reg_rtx (dest_mode);
11670 convert_move (temp, mask, 0);
11677 gcc_unreachable ();
11682 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11683 /* You only get two chances. */
11684 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
11696 emit_insn (gen_rtx_SET (VOIDmode, mask,
11697 gen_rtx_UNSPEC (dest_mode,
11698 gen_rtvec (2, op0, op1),
11700 if (dmode != dest_mode)
11702 rtx temp = gen_reg_rtx (dest_mode);
11703 convert_move (temp, mask, 0);
11709 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11710 valid insn doesn exist for given mode. */
11713 get_vsel_insn (enum machine_mode mode)
11718 return UNSPEC_VSEL4SI;
11721 return UNSPEC_VSEL4SF;
11724 return UNSPEC_VSEL8HI;
11727 return UNSPEC_VSEL16QI;
11730 return INSN_NOT_AVAILABLE;
11733 return INSN_NOT_AVAILABLE;
11736 /* Emit vector select insn where DEST is destination using
11737 operands OP1, OP2 and MASK. */
11740 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11743 enum machine_mode dest_mode = GET_MODE (dest);
11744 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11746 temp = gen_reg_rtx (dest_mode);
11748 /* For each vector element, select op1 when mask is 1 otherwise
11750 t = gen_rtx_SET (VOIDmode, temp,
11751 gen_rtx_UNSPEC (dest_mode,
11752 gen_rtvec (3, op2, op1, mask),
11755 emit_move_insn (dest, temp);
11759 /* Emit vector conditional expression.
11760 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11761 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11764 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11765 rtx cond, rtx cc_op0, rtx cc_op1)
11767 enum machine_mode dest_mode = GET_MODE (dest);
11768 enum rtx_code rcode = GET_CODE (cond);
11771 if (!TARGET_ALTIVEC)
11774 /* Get the vector mask for the given relational operations. */
11775 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11777 rs6000_emit_vector_select (dest, op1, op2, mask);
11782 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11783 operands of the last comparison is nonzero/true, FALSE_COND if it
11784 is zero/false. Return 0 if the hardware has no such operation. */
11787 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11789 enum rtx_code code = GET_CODE (op);
11790 rtx op0 = rs6000_compare_op0;
11791 rtx op1 = rs6000_compare_op1;
11792 REAL_VALUE_TYPE c1;
11793 enum machine_mode compare_mode = GET_MODE (op0);
11794 enum machine_mode result_mode = GET_MODE (dest);
11796 bool is_against_zero;
11798 /* These modes should always match. */
11799 if (GET_MODE (op1) != compare_mode
11800 /* In the isel case however, we can use a compare immediate, so
11801 op1 may be a small constant. */
11802 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11804 if (GET_MODE (true_cond) != result_mode)
11806 if (GET_MODE (false_cond) != result_mode)
11809 /* First, work out if the hardware can do this at all, or
11810 if it's too slow.... */
11811 if (! rs6000_compare_fp_p)
11814 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11817 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11818 && SCALAR_FLOAT_MODE_P (compare_mode))
11821 is_against_zero = op1 == CONST0_RTX (compare_mode);
11823 /* A floating-point subtract might overflow, underflow, or produce
11824 an inexact result, thus changing the floating-point flags, so it
11825 can't be generated if we care about that. It's safe if one side
11826 of the construct is zero, since then no subtract will be
11828 if (SCALAR_FLOAT_MODE_P (compare_mode)
11829 && flag_trapping_math && ! is_against_zero)
11832 /* Eliminate half of the comparisons by switching operands, this
11833 makes the remaining code simpler. */
11834 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
11835 || code == LTGT || code == LT || code == UNLE)
11837 code = reverse_condition_maybe_unordered (code);
11839 true_cond = false_cond;
11843 /* UNEQ and LTGT take four instructions for a comparison with zero,
11844 it'll probably be faster to use a branch here too. */
11845 if (code == UNEQ && HONOR_NANS (compare_mode))
11848 if (GET_CODE (op1) == CONST_DOUBLE)
11849 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
11851 /* We're going to try to implement comparisons by performing
11852 a subtract, then comparing against zero. Unfortunately,
11853 Inf - Inf is NaN which is not zero, and so if we don't
11854 know that the operand is finite and the comparison
11855 would treat EQ different to UNORDERED, we can't do it. */
11856 if (HONOR_INFINITIES (compare_mode)
11857 && code != GT && code != UNGE
11858 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
11859 /* Constructs of the form (a OP b ? a : b) are safe. */
11860 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
11861 || (! rtx_equal_p (op0, true_cond)
11862 && ! rtx_equal_p (op1, true_cond))))
11865 /* At this point we know we can use fsel. */
11867 /* Reduce the comparison to a comparison against zero. */
11868 if (! is_against_zero)
11870 temp = gen_reg_rtx (compare_mode);
11871 emit_insn (gen_rtx_SET (VOIDmode, temp,
11872 gen_rtx_MINUS (compare_mode, op0, op1)));
11874 op1 = CONST0_RTX (compare_mode);
11877 /* If we don't care about NaNs we can reduce some of the comparisons
11878 down to faster ones. */
11879 if (! HONOR_NANS (compare_mode))
11885 true_cond = false_cond;
11898 /* Now, reduce everything down to a GE. */
11905 temp = gen_reg_rtx (compare_mode);
11906 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11911 temp = gen_reg_rtx (compare_mode);
11912 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
11917 temp = gen_reg_rtx (compare_mode);
11918 emit_insn (gen_rtx_SET (VOIDmode, temp,
11919 gen_rtx_NEG (compare_mode,
11920 gen_rtx_ABS (compare_mode, op0))));
11925 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
11926 temp = gen_reg_rtx (result_mode);
11927 emit_insn (gen_rtx_SET (VOIDmode, temp,
11928 gen_rtx_IF_THEN_ELSE (result_mode,
11929 gen_rtx_GE (VOIDmode,
11931 true_cond, false_cond)));
11932 false_cond = true_cond;
11935 temp = gen_reg_rtx (compare_mode);
11936 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11941 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
11942 temp = gen_reg_rtx (result_mode);
11943 emit_insn (gen_rtx_SET (VOIDmode, temp,
11944 gen_rtx_IF_THEN_ELSE (result_mode,
11945 gen_rtx_GE (VOIDmode,
11947 true_cond, false_cond)));
11948 true_cond = false_cond;
11951 temp = gen_reg_rtx (compare_mode);
11952 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11957 gcc_unreachable ();
11960 emit_insn (gen_rtx_SET (VOIDmode, dest,
11961 gen_rtx_IF_THEN_ELSE (result_mode,
11962 gen_rtx_GE (VOIDmode,
11964 true_cond, false_cond)));
11968 /* Same as above, but for ints (isel). */
11971 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11973 rtx condition_rtx, cr;
11975 /* All isel implementations thus far are 32-bits. */
11976 if (GET_MODE (rs6000_compare_op0) != SImode)
11979 /* We still have to do the compare, because isel doesn't do a
11980 compare, it just looks at the CRx bits set by a previous compare
11982 condition_rtx = rs6000_generate_compare (GET_CODE (op));
11983 cr = XEXP (condition_rtx, 0);
11985 if (GET_MODE (cr) == CCmode)
11986 emit_insn (gen_isel_signed (dest, condition_rtx,
11987 true_cond, false_cond, cr));
11989 emit_insn (gen_isel_unsigned (dest, condition_rtx,
11990 true_cond, false_cond, cr));
11996 output_isel (rtx *operands)
11998 enum rtx_code code;
12000 code = GET_CODE (operands[1]);
12001 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
12003 PUT_CODE (operands[1], reverse_condition (code));
12004 return "isel %0,%3,%2,%j1";
12007 return "isel %0,%2,%3,%j1";
12011 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
12013 enum machine_mode mode = GET_MODE (op0);
12017 if (code == SMAX || code == SMIN)
12022 if (code == SMAX || code == UMAX)
12023 target = emit_conditional_move (dest, c, op0, op1, mode,
12024 op0, op1, mode, 0);
12026 target = emit_conditional_move (dest, c, op0, op1, mode,
12027 op1, op0, mode, 0);
12028 gcc_assert (target);
12029 if (target != dest)
12030 emit_move_insn (dest, target);
12033 /* Emit instructions to perform a load-reserved/store-conditional operation.
12034 The operation performed is an atomic
12035 (set M (CODE:MODE M OP))
12036 If not NULL, BEFORE is atomically set to M before the operation, and
12037 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
12038 If SYNC_P then a memory barrier is emitted before the operation.
12039 Either OP or M may be wrapped in a NOT operation. */
12042 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
12043 rtx m, rtx op, rtx before_param, rtx after_param,
12046 enum machine_mode used_mode;
12047 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
12050 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12051 rtx shift = NULL_RTX;
12054 emit_insn (gen_memory_barrier ());
12056 if (GET_CODE (m) == NOT)
12057 used_m = XEXP (m, 0);
12061 /* If this is smaller than SImode, we'll have to use SImode with
12063 if (mode == QImode || mode == HImode)
12067 if (MEM_ALIGN (used_m) >= 32)
12070 if (BYTES_BIG_ENDIAN)
12071 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
12073 shift = GEN_INT (ishift);
12077 rtx addrSI, aligned_addr;
12078 int shift_mask = mode == QImode ? 0x18 : 0x10;
12080 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
12081 XEXP (used_m, 0)));
12082 shift = gen_reg_rtx (SImode);
12084 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12085 GEN_INT (shift_mask)));
12086 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12088 aligned_addr = expand_binop (Pmode, and_optab,
12090 GEN_INT (-4), NULL_RTX,
12091 1, OPTAB_LIB_WIDEN);
12092 used_m = change_address (used_m, SImode, aligned_addr);
12093 set_mem_align (used_m, 32);
12094 /* It's safe to keep the old alias set of USED_M, because
12095 the operation is atomic and only affects the original
12097 if (GET_CODE (m) == NOT)
12098 m = gen_rtx_NOT (SImode, used_m);
12103 if (GET_CODE (op) == NOT)
12105 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12106 oldop = gen_rtx_NOT (SImode, oldop);
12109 oldop = lowpart_subreg (SImode, op, mode);
12115 newop = expand_binop (SImode, and_optab,
12116 oldop, GEN_INT (imask), NULL_RTX,
12117 1, OPTAB_LIB_WIDEN);
12118 emit_insn (gen_ashlsi3 (newop, newop, shift));
12122 newop = expand_binop (SImode, ior_optab,
12123 oldop, GEN_INT (~imask), NULL_RTX,
12124 1, OPTAB_LIB_WIDEN);
12125 emit_insn (gen_rotlsi3 (newop, newop, shift));
12133 newop = expand_binop (SImode, and_optab,
12134 oldop, GEN_INT (imask), NULL_RTX,
12135 1, OPTAB_LIB_WIDEN);
12136 emit_insn (gen_ashlsi3 (newop, newop, shift));
12138 mask = gen_reg_rtx (SImode);
12139 emit_move_insn (mask, GEN_INT (imask));
12140 emit_insn (gen_ashlsi3 (mask, mask, shift));
12143 newop = gen_rtx_PLUS (SImode, m, newop);
12145 newop = gen_rtx_MINUS (SImode, m, newop);
12146 newop = gen_rtx_AND (SImode, newop, mask);
12147 newop = gen_rtx_IOR (SImode, newop,
12148 gen_rtx_AND (SImode,
12149 gen_rtx_NOT (SImode, mask),
12155 gcc_unreachable ();
12158 if (GET_CODE (m) == NOT)
12162 mask = gen_reg_rtx (SImode);
12163 emit_move_insn (mask, GEN_INT (imask));
12164 emit_insn (gen_ashlsi3 (mask, mask, shift));
12166 xorm = gen_rtx_XOR (SImode, used_m, mask);
12167 /* Depending on the value of 'op', the XOR or the operation might
12168 be able to be simplified away. */
12169 newop = simplify_gen_binary (code, SImode, xorm, newop);
12172 used_mode = SImode;
12173 before = gen_reg_rtx (used_mode);
12174 after = gen_reg_rtx (used_mode);
12179 before = before_param;
12180 after = after_param;
12182 if (before == NULL_RTX)
12183 before = gen_reg_rtx (used_mode);
12184 if (after == NULL_RTX)
12185 after = gen_reg_rtx (used_mode);
12188 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12189 && used_mode != mode)
12190 the_op = op; /* Computed above. */
12191 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12192 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12194 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12196 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12197 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12198 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12199 gen_rtx_UNSPEC (used_mode,
12200 gen_rtvec (1, the_op),
12202 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12204 if ((code == PLUS || code == MINUS) && used_mode != mode)
12205 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12206 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12208 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12209 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12211 /* Shift and mask the return values properly. */
12212 if (used_mode != mode && before_param)
12214 emit_insn (gen_lshrsi3 (before, before, shift));
12215 convert_move (before_param, before, 1);
12218 if (used_mode != mode && after_param)
12220 emit_insn (gen_lshrsi3 (after, after, shift));
12221 convert_move (after_param, after, 1);
12224 /* The previous sequence will end with a branch that's dependent on
12225 the conditional store, so placing an isync will ensure that no
12226 other instructions (especially, no load or store instructions)
12227 can start before the atomic operation completes. */
12229 emit_insn (gen_isync ());
12232 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12233 COND is true. Mark the jump as unlikely to be taken. */
12236 emit_unlikely_jump (rtx cond, rtx label)
12238 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12241 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12242 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12243 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12246 /* A subroutine of the atomic operation splitters. Emit a load-locked
12247 instruction in MODE. */
12250 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12252 rtx (*fn) (rtx, rtx) = NULL;
12253 if (mode == SImode)
12254 fn = gen_load_locked_si;
12255 else if (mode == DImode)
12256 fn = gen_load_locked_di;
12257 emit_insn (fn (reg, mem));
12260 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12261 instruction in MODE. */
12264 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12266 rtx (*fn) (rtx, rtx, rtx) = NULL;
12267 if (mode == SImode)
12268 fn = gen_store_conditional_si;
12269 else if (mode == DImode)
12270 fn = gen_store_conditional_di;
12272 /* Emit sync before stwcx. to address PPC405 Erratum. */
12273 if (PPC405_ERRATUM77)
12274 emit_insn (gen_memory_barrier ());
12276 emit_insn (fn (res, mem, val));
12279 /* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation
12280 to perform. MEM is the memory on which to operate. VAL is the second
12281 operand of the binary operator. BEFORE and AFTER are optional locations to
12282 return the value of MEM either before of after the operation. SCRATCH is
12283 a scratch register. */
12286 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12287 rtx before, rtx after, rtx scratch)
12289 enum machine_mode mode = GET_MODE (mem);
12290 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12292 emit_insn (gen_memory_barrier ());
12294 label = gen_label_rtx ();
12295 emit_label (label);
12296 label = gen_rtx_LABEL_REF (VOIDmode, label);
12298 if (before == NULL_RTX)
12300 emit_load_locked (mode, before, mem);
12303 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12304 else if (code == AND)
12305 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12307 x = gen_rtx_fmt_ee (code, mode, before, val);
12309 if (after != NULL_RTX)
12310 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12311 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12313 emit_store_conditional (mode, cond, mem, scratch);
12315 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12316 emit_unlikely_jump (x, label);
12318 emit_insn (gen_isync ());
12321 /* Expand an atomic compare and swap operation. MEM is the memory on which
12322 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12323 value to be stored. SCRATCH is a scratch GPR. */
12326 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12329 enum machine_mode mode = GET_MODE (mem);
12330 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12332 emit_insn (gen_memory_barrier ());
12334 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12335 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12336 emit_label (XEXP (label1, 0));
12338 emit_load_locked (mode, retval, mem);
12340 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12341 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12343 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12344 emit_unlikely_jump (x, label2);
12346 emit_move_insn (scratch, newval);
12347 emit_store_conditional (mode, cond, mem, scratch);
12349 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12350 emit_unlikely_jump (x, label1);
12352 emit_insn (gen_isync ());
12353 emit_label (XEXP (label2, 0));
12356 /* Expand an atomic test and set operation. MEM is the memory on which
12357 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12360 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
12362 enum machine_mode mode = GET_MODE (mem);
12363 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12365 emit_insn (gen_memory_barrier ());
12367 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12368 emit_label (XEXP (label, 0));
12370 emit_load_locked (mode, retval, mem);
12371 emit_move_insn (scratch, val);
12372 emit_store_conditional (mode, cond, mem, scratch);
12374 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12375 emit_unlikely_jump (x, label);
12377 emit_insn (gen_isync ());
12381 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
12383 enum machine_mode mode = GET_MODE (mem);
12384 rtx addrSI, align, wdst, shift, mask;
12385 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
12386 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12388 /* Shift amount for subword relative to aligned word. */
12389 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
12390 shift = gen_reg_rtx (SImode);
12391 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12392 GEN_INT (shift_mask)));
12393 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12395 /* Shift and mask old value into position within word. */
12396 oldval = convert_modes (SImode, mode, oldval, 1);
12397 oldval = expand_binop (SImode, and_optab,
12398 oldval, GEN_INT (imask), NULL_RTX,
12399 1, OPTAB_LIB_WIDEN);
12400 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
12402 /* Shift and mask new value into position within word. */
12403 newval = convert_modes (SImode, mode, newval, 1);
12404 newval = expand_binop (SImode, and_optab,
12405 newval, GEN_INT (imask), NULL_RTX,
12406 1, OPTAB_LIB_WIDEN);
12407 emit_insn (gen_ashlsi3 (newval, newval, shift));
12409 /* Mask for insertion. */
12410 mask = gen_reg_rtx (SImode);
12411 emit_move_insn (mask, GEN_INT (imask));
12412 emit_insn (gen_ashlsi3 (mask, mask, shift));
12414 /* Address of aligned word containing subword. */
12415 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
12416 NULL_RTX, 1, OPTAB_LIB_WIDEN);
12417 mem = change_address (mem, SImode, align);
12418 set_mem_align (mem, 32);
12419 MEM_VOLATILE_P (mem) = 1;
12421 wdst = gen_reg_rtx (SImode);
12422 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
12423 oldval, newval, mem));
12425 emit_move_insn (dst, gen_lowpart (mode, wdst));
12429 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
12430 rtx oldval, rtx newval, rtx mem,
12433 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12435 emit_insn (gen_memory_barrier ());
12436 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12437 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12438 emit_label (XEXP (label1, 0));
12440 emit_load_locked (SImode, scratch, mem);
12442 /* Mask subword within loaded value for comparison with oldval.
12443 Use UNSPEC_AND to avoid clobber.*/
12444 emit_insn (gen_rtx_SET (SImode, dest,
12445 gen_rtx_UNSPEC (SImode,
12446 gen_rtvec (2, scratch, mask),
12449 x = gen_rtx_COMPARE (CCmode, dest, oldval);
12450 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12452 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12453 emit_unlikely_jump (x, label2);
12455 /* Clear subword within loaded value for insertion of new value. */
12456 emit_insn (gen_rtx_SET (SImode, scratch,
12457 gen_rtx_AND (SImode,
12458 gen_rtx_NOT (SImode, mask), scratch)));
12459 emit_insn (gen_iorsi3 (scratch, scratch, newval));
12460 emit_store_conditional (SImode, cond, mem, scratch);
12462 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12463 emit_unlikely_jump (x, label1);
12465 emit_insn (gen_isync ());
12466 emit_label (XEXP (label2, 0));
12470 /* Emit instructions to move SRC to DST. Called by splitters for
12471 multi-register moves. It will emit at most one instruction for
12472 each register that is accessed; that is, it won't emit li/lis pairs
12473 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12477 rs6000_split_multireg_move (rtx dst, rtx src)
12479 /* The register number of the first register being moved. */
12481 /* The mode that is to be moved. */
12482 enum machine_mode mode;
12483 /* The mode that the move is being done in, and its size. */
12484 enum machine_mode reg_mode;
12486 /* The number of registers that will be moved. */
12489 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12490 mode = GET_MODE (dst);
12491 nregs = hard_regno_nregs[reg][mode];
12492 if (FP_REGNO_P (reg))
12494 else if (ALTIVEC_REGNO_P (reg))
12495 reg_mode = V16QImode;
12497 reg_mode = word_mode;
12498 reg_mode_size = GET_MODE_SIZE (reg_mode);
12500 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
12502 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12504 /* Move register range backwards, if we might have destructive
12507 for (i = nregs - 1; i >= 0; i--)
12508 emit_insn (gen_rtx_SET (VOIDmode,
12509 simplify_gen_subreg (reg_mode, dst, mode,
12510 i * reg_mode_size),
12511 simplify_gen_subreg (reg_mode, src, mode,
12512 i * reg_mode_size)));
12518 bool used_update = false;
12520 if (MEM_P (src) && INT_REGNO_P (reg))
12524 if (GET_CODE (XEXP (src, 0)) == PRE_INC
12525 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
12528 breg = XEXP (XEXP (src, 0), 0);
12529 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
12530 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
12531 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
12532 emit_insn (TARGET_32BIT
12533 ? gen_addsi3 (breg, breg, delta_rtx)
12534 : gen_adddi3 (breg, breg, delta_rtx));
12535 src = replace_equiv_address (src, breg);
12537 else if (! rs6000_offsettable_memref_p (src))
12540 basereg = gen_rtx_REG (Pmode, reg);
12541 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
12542 src = replace_equiv_address (src, basereg);
12545 breg = XEXP (src, 0);
12546 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
12547 breg = XEXP (breg, 0);
12549 /* If the base register we are using to address memory is
12550 also a destination reg, then change that register last. */
12552 && REGNO (breg) >= REGNO (dst)
12553 && REGNO (breg) < REGNO (dst) + nregs)
12554 j = REGNO (breg) - REGNO (dst);
12557 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
12561 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
12562 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
12565 breg = XEXP (XEXP (dst, 0), 0);
12566 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
12567 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
12568 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
12570 /* We have to update the breg before doing the store.
12571 Use store with update, if available. */
12575 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
12576 emit_insn (TARGET_32BIT
12577 ? (TARGET_POWERPC64
12578 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
12579 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
12580 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
12581 used_update = true;
12584 emit_insn (TARGET_32BIT
12585 ? gen_addsi3 (breg, breg, delta_rtx)
12586 : gen_adddi3 (breg, breg, delta_rtx));
12587 dst = replace_equiv_address (dst, breg);
12590 gcc_assert (rs6000_offsettable_memref_p (dst));
12593 for (i = 0; i < nregs; i++)
12595 /* Calculate index to next subword. */
12600 /* If compiler already emitted move of first word by
12601 store with update, no need to do anything. */
12602 if (j == 0 && used_update)
12605 emit_insn (gen_rtx_SET (VOIDmode,
12606 simplify_gen_subreg (reg_mode, dst, mode,
12607 j * reg_mode_size),
12608 simplify_gen_subreg (reg_mode, src, mode,
12609 j * reg_mode_size)));
12615 /* This page contains routines that are used to determine what the
12616 function prologue and epilogue code will do and write them out. */
12618 /* Return the first fixed-point register that is required to be
12619 saved. 32 if none. */
12622 first_reg_to_save (void)
12626 /* Find lowest numbered live register. */
12627 for (first_reg = 13; first_reg <= 31; first_reg++)
12628 if (regs_ever_live[first_reg]
12629 && (! call_used_regs[first_reg]
12630 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12631 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12632 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12633 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12638 && current_function_uses_pic_offset_table
12639 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12640 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12646 /* Similar, for FP regs. */
12649 first_fp_reg_to_save (void)
12653 /* Find lowest numbered live register. */
12654 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12655 if (regs_ever_live[first_reg])
12661 /* Similar, for AltiVec regs. */
12664 first_altivec_reg_to_save (void)
12668 /* Stack frame remains as is unless we are in AltiVec ABI. */
12669 if (! TARGET_ALTIVEC_ABI)
12670 return LAST_ALTIVEC_REGNO + 1;
12672 /* Find lowest numbered live register. */
12673 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12674 if (regs_ever_live[i])
12680 /* Return a 32-bit mask of the AltiVec registers we need to set in
12681 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12682 the 32-bit word is 0. */
12684 static unsigned int
12685 compute_vrsave_mask (void)
12687 unsigned int i, mask = 0;
12689 /* First, find out if we use _any_ altivec registers. */
12690 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12691 if (regs_ever_live[i])
12692 mask |= ALTIVEC_REG_BIT (i);
12697 /* Next, remove the argument registers from the set. These must
12698 be in the VRSAVE mask set by the caller, so we don't need to add
12699 them in again. More importantly, the mask we compute here is
12700 used to generate CLOBBERs in the set_vrsave insn, and we do not
12701 wish the argument registers to die. */
12702 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12703 mask &= ~ALTIVEC_REG_BIT (i);
12705 /* Similarly, remove the return value from the set. */
12708 diddle_return_value (is_altivec_return_reg, &yes);
12710 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12716 /* For a very restricted set of circumstances, we can cut down the
12717 size of prologues/epilogues by calling our own save/restore-the-world
12721 compute_save_world_info (rs6000_stack_t *info_ptr)
12723 info_ptr->world_save_p = 1;
12724 info_ptr->world_save_p
12725 = (WORLD_SAVE_P (info_ptr)
12726 && DEFAULT_ABI == ABI_DARWIN
12727 && ! (current_function_calls_setjmp && flag_exceptions)
12728 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12729 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12730 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12731 && info_ptr->cr_save_p);
12733 /* This will not work in conjunction with sibcalls. Make sure there
12734 are none. (This check is expensive, but seldom executed.) */
12735 if (WORLD_SAVE_P (info_ptr))
12738 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12739 if ( GET_CODE (insn) == CALL_INSN
12740 && SIBLING_CALL_P (insn))
12742 info_ptr->world_save_p = 0;
12747 if (WORLD_SAVE_P (info_ptr))
12749 /* Even if we're not touching VRsave, make sure there's room on the
12750 stack for it, if it looks like we're calling SAVE_WORLD, which
12751 will attempt to save it. */
12752 info_ptr->vrsave_size = 4;
12754 /* "Save" the VRsave register too if we're saving the world. */
12755 if (info_ptr->vrsave_mask == 0)
12756 info_ptr->vrsave_mask = compute_vrsave_mask ();
12758 /* Because the Darwin register save/restore routines only handle
12759 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12761 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
12762 && (info_ptr->first_altivec_reg_save
12763 >= FIRST_SAVED_ALTIVEC_REGNO));
12770 is_altivec_return_reg (rtx reg, void *xyes)
12772 bool *yes = (bool *) xyes;
12773 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
12778 /* Calculate the stack information for the current function. This is
12779 complicated by having two separate calling sequences, the AIX calling
12780 sequence and the V.4 calling sequence.
12782 AIX (and Darwin/Mac OS X) stack frames look like:
12784 SP----> +---------------------------------------+
12785 | back chain to caller | 0 0
12786 +---------------------------------------+
12787 | saved CR | 4 8 (8-11)
12788 +---------------------------------------+
12790 +---------------------------------------+
12791 | reserved for compilers | 12 24
12792 +---------------------------------------+
12793 | reserved for binders | 16 32
12794 +---------------------------------------+
12795 | saved TOC pointer | 20 40
12796 +---------------------------------------+
12797 | Parameter save area (P) | 24 48
12798 +---------------------------------------+
12799 | Alloca space (A) | 24+P etc.
12800 +---------------------------------------+
12801 | Local variable space (L) | 24+P+A
12802 +---------------------------------------+
12803 | Float/int conversion temporary (X) | 24+P+A+L
12804 +---------------------------------------+
12805 | Save area for AltiVec registers (W) | 24+P+A+L+X
12806 +---------------------------------------+
12807 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12808 +---------------------------------------+
12809 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12810 +---------------------------------------+
12811 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12812 +---------------------------------------+
12813 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12814 +---------------------------------------+
12815 old SP->| back chain to caller's caller |
12816 +---------------------------------------+
12818 The required alignment for AIX configurations is two words (i.e., 8
12822 V.4 stack frames look like:
12824 SP----> +---------------------------------------+
12825 | back chain to caller | 0
12826 +---------------------------------------+
12827 | caller's saved LR | 4
12828 +---------------------------------------+
12829 | Parameter save area (P) | 8
12830 +---------------------------------------+
12831 | Alloca space (A) | 8+P
12832 +---------------------------------------+
12833 | Varargs save area (V) | 8+P+A
12834 +---------------------------------------+
12835 | Local variable space (L) | 8+P+A+V
12836 +---------------------------------------+
12837 | Float/int conversion temporary (X) | 8+P+A+V+L
12838 +---------------------------------------+
12839 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12840 +---------------------------------------+
12841 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12842 +---------------------------------------+
12843 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12844 +---------------------------------------+
12845 | SPE: area for 64-bit GP registers |
12846 +---------------------------------------+
12847 | SPE alignment padding |
12848 +---------------------------------------+
12849 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12850 +---------------------------------------+
12851 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12852 +---------------------------------------+
12853 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12854 +---------------------------------------+
12855 old SP->| back chain to caller's caller |
12856 +---------------------------------------+
12858 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12859 given. (But note below and in sysv4.h that we require only 8 and
12860 may round up the size of our stack frame anyways. The historical
12861 reason is early versions of powerpc-linux which didn't properly
12862 align the stack at program startup. A happy side-effect is that
12863 -mno-eabi libraries can be used with -meabi programs.)
12865 The EABI configuration defaults to the V.4 layout. However,
12866 the stack alignment requirements may differ. If -mno-eabi is not
12867 given, the required stack alignment is 8 bytes; if -mno-eabi is
12868 given, the required alignment is 16 bytes. (But see V.4 comment
12871 #ifndef ABI_STACK_BOUNDARY
12872 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12875 static rs6000_stack_t *
12876 rs6000_stack_info (void)
12878 static rs6000_stack_t info;
12879 rs6000_stack_t *info_ptr = &info;
12880 int reg_size = TARGET_32BIT ? 4 : 8;
12883 HOST_WIDE_INT non_fixed_size;
12885 memset (&info, 0, sizeof (info));
12889 /* Cache value so we don't rescan instruction chain over and over. */
12890 if (cfun->machine->insn_chain_scanned_p == 0)
12891 cfun->machine->insn_chain_scanned_p
12892 = spe_func_has_64bit_regs_p () + 1;
12893 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
12896 /* Select which calling sequence. */
12897 info_ptr->abi = DEFAULT_ABI;
12899 /* Calculate which registers need to be saved & save area size. */
12900 info_ptr->first_gp_reg_save = first_reg_to_save ();
12901 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12902 even if it currently looks like we won't. */
12903 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
12904 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12905 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
12906 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12907 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
12909 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
12911 /* For the SPE, we have an additional upper 32-bits on each GPR.
12912 Ideally we should save the entire 64-bits only when the upper
12913 half is used in SIMD instructions. Since we only record
12914 registers live (not the size they are used in), this proves
12915 difficult because we'd have to traverse the instruction chain at
12916 the right time, taking reload into account. This is a real pain,
12917 so we opt to save the GPRs in 64-bits always if but one register
12918 gets used in 64-bits. Otherwise, all the registers in the frame
12919 get saved in 32-bits.
12921 So... since when we save all GPRs (except the SP) in 64-bits, the
12922 traditional GP save area will be empty. */
12923 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12924 info_ptr->gp_size = 0;
12926 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12927 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12929 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12930 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12931 - info_ptr->first_altivec_reg_save);
12933 /* Does this function call anything? */
12934 info_ptr->calls_p = (! current_function_is_leaf
12935 || cfun->machine->ra_needs_full_frame);
12937 /* Determine if we need to save the link register. */
12938 if ((DEFAULT_ABI == ABI_AIX
12939 && current_function_profile
12940 && !TARGET_PROFILE_KERNEL)
12941 #ifdef TARGET_RELOCATABLE
12942 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12944 || (info_ptr->first_fp_reg_save != 64
12945 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
12946 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
12947 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
12948 || info_ptr->calls_p
12949 || rs6000_ra_ever_killed ())
12951 info_ptr->lr_save_p = 1;
12952 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
12955 /* Determine if we need to save the condition code registers. */
12956 if (regs_ever_live[CR2_REGNO]
12957 || regs_ever_live[CR3_REGNO]
12958 || regs_ever_live[CR4_REGNO])
12960 info_ptr->cr_save_p = 1;
12961 if (DEFAULT_ABI == ABI_V4)
12962 info_ptr->cr_size = reg_size;
12965 /* If the current function calls __builtin_eh_return, then we need
12966 to allocate stack space for registers that will hold data for
12967 the exception handler. */
12968 if (current_function_calls_eh_return)
12971 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12974 /* SPE saves EH registers in 64-bits. */
12975 ehrd_size = i * (TARGET_SPE_ABI
12976 && info_ptr->spe_64bit_regs_used != 0
12977 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
12982 /* Determine various sizes. */
12983 info_ptr->reg_size = reg_size;
12984 info_ptr->fixed_size = RS6000_SAVE_AREA;
12985 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
12986 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
12987 TARGET_ALTIVEC ? 16 : 8);
12988 if (FRAME_GROWS_DOWNWARD)
12989 info_ptr->vars_size
12990 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
12991 + info_ptr->parm_size,
12992 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
12993 - (info_ptr->fixed_size + info_ptr->vars_size
12994 + info_ptr->parm_size);
12996 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12997 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12999 info_ptr->spe_gp_size = 0;
13001 if (TARGET_ALTIVEC_ABI)
13002 info_ptr->vrsave_mask = compute_vrsave_mask ();
13004 info_ptr->vrsave_mask = 0;
13006 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
13007 info_ptr->vrsave_size = 4;
13009 info_ptr->vrsave_size = 0;
13011 compute_save_world_info (info_ptr);
13013 /* Calculate the offsets. */
13014 switch (DEFAULT_ABI)
13018 gcc_unreachable ();
13022 info_ptr->fp_save_offset = - info_ptr->fp_size;
13023 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13025 if (TARGET_ALTIVEC_ABI)
13027 info_ptr->vrsave_save_offset
13028 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
13030 /* Align stack so vector save area is on a quadword boundary. */
13031 if (info_ptr->altivec_size != 0)
13032 info_ptr->altivec_padding_size
13033 = 16 - (-info_ptr->vrsave_save_offset % 16);
13035 info_ptr->altivec_padding_size = 0;
13037 info_ptr->altivec_save_offset
13038 = info_ptr->vrsave_save_offset
13039 - info_ptr->altivec_padding_size
13040 - info_ptr->altivec_size;
13042 /* Adjust for AltiVec case. */
13043 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
13046 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
13047 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
13048 info_ptr->lr_save_offset = 2*reg_size;
13052 info_ptr->fp_save_offset = - info_ptr->fp_size;
13053 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13054 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
13056 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13058 /* Align stack so SPE GPR save area is aligned on a
13059 double-word boundary. */
13060 if (info_ptr->spe_gp_size != 0)
13061 info_ptr->spe_padding_size
13062 = 8 - (-info_ptr->cr_save_offset % 8);
13064 info_ptr->spe_padding_size = 0;
13066 info_ptr->spe_gp_save_offset
13067 = info_ptr->cr_save_offset
13068 - info_ptr->spe_padding_size
13069 - info_ptr->spe_gp_size;
13071 /* Adjust for SPE case. */
13072 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
13074 else if (TARGET_ALTIVEC_ABI)
13076 info_ptr->vrsave_save_offset
13077 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
13079 /* Align stack so vector save area is on a quadword boundary. */
13080 if (info_ptr->altivec_size != 0)
13081 info_ptr->altivec_padding_size
13082 = 16 - (-info_ptr->vrsave_save_offset % 16);
13084 info_ptr->altivec_padding_size = 0;
13086 info_ptr->altivec_save_offset
13087 = info_ptr->vrsave_save_offset
13088 - info_ptr->altivec_padding_size
13089 - info_ptr->altivec_size;
13091 /* Adjust for AltiVec case. */
13092 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
13095 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
13096 info_ptr->ehrd_offset -= ehrd_size;
13097 info_ptr->lr_save_offset = reg_size;
13101 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
13102 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
13103 + info_ptr->gp_size
13104 + info_ptr->altivec_size
13105 + info_ptr->altivec_padding_size
13106 + info_ptr->spe_gp_size
13107 + info_ptr->spe_padding_size
13109 + info_ptr->cr_size
13110 + info_ptr->vrsave_size,
13113 non_fixed_size = (info_ptr->vars_size
13114 + info_ptr->parm_size
13115 + info_ptr->save_size);
13117 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
13118 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
13120 /* Determine if we need to allocate any stack frame:
13122 For AIX we need to push the stack if a frame pointer is needed
13123 (because the stack might be dynamically adjusted), if we are
13124 debugging, if we make calls, or if the sum of fp_save, gp_save,
13125 and local variables are more than the space needed to save all
13126 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
13127 + 18*8 = 288 (GPR13 reserved).
13129 For V.4 we don't have the stack cushion that AIX uses, but assume
13130 that the debugger can handle stackless frames. */
13132 if (info_ptr->calls_p)
13133 info_ptr->push_p = 1;
13135 else if (DEFAULT_ABI == ABI_V4)
13136 info_ptr->push_p = non_fixed_size != 0;
13138 else if (frame_pointer_needed)
13139 info_ptr->push_p = 1;
13141 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
13142 info_ptr->push_p = 1;
13145 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
13147 /* Zero offsets if we're not saving those registers. */
13148 if (info_ptr->fp_size == 0)
13149 info_ptr->fp_save_offset = 0;
13151 if (info_ptr->gp_size == 0)
13152 info_ptr->gp_save_offset = 0;
13154 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
13155 info_ptr->altivec_save_offset = 0;
13157 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
13158 info_ptr->vrsave_save_offset = 0;
13160 if (! TARGET_SPE_ABI
13161 || info_ptr->spe_64bit_regs_used == 0
13162 || info_ptr->spe_gp_size == 0)
13163 info_ptr->spe_gp_save_offset = 0;
13165 if (! info_ptr->lr_save_p)
13166 info_ptr->lr_save_offset = 0;
13168 if (! info_ptr->cr_save_p)
13169 info_ptr->cr_save_offset = 0;
13174 /* Return true if the current function uses any GPRs in 64-bit SIMD
13178 spe_func_has_64bit_regs_p (void)
13182 /* Functions that save and restore all the call-saved registers will
13183 need to save/restore the registers in 64-bits. */
13184 if (current_function_calls_eh_return
13185 || current_function_calls_setjmp
13186 || current_function_has_nonlocal_goto)
13189 insns = get_insns ();
13191 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13197 /* FIXME: This should be implemented with attributes...
13199 (set_attr "spe64" "true")....then,
13200 if (get_spe64(insn)) return true;
13202 It's the only reliable way to do the stuff below. */
13204 i = PATTERN (insn);
13205 if (GET_CODE (i) == SET)
13207 enum machine_mode mode = GET_MODE (SET_SRC (i));
13209 if (SPE_VECTOR_MODE (mode))
13211 if (TARGET_E500_DOUBLE && mode == DFmode)
13221 debug_stack_info (rs6000_stack_t *info)
13223 const char *abi_string;
13226 info = rs6000_stack_info ();
13228 fprintf (stderr, "\nStack information for function %s:\n",
13229 ((current_function_decl && DECL_NAME (current_function_decl))
13230 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13235 default: abi_string = "Unknown"; break;
13236 case ABI_NONE: abi_string = "NONE"; break;
13237 case ABI_AIX: abi_string = "AIX"; break;
13238 case ABI_DARWIN: abi_string = "Darwin"; break;
13239 case ABI_V4: abi_string = "V.4"; break;
13242 fprintf (stderr, "\tABI = %5s\n", abi_string);
13244 if (TARGET_ALTIVEC_ABI)
13245 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13247 if (TARGET_SPE_ABI)
13248 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13250 if (info->first_gp_reg_save != 32)
13251 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13253 if (info->first_fp_reg_save != 64)
13254 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13256 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13257 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13258 info->first_altivec_reg_save);
13260 if (info->lr_save_p)
13261 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13263 if (info->cr_save_p)
13264 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13266 if (info->vrsave_mask)
13267 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13270 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13273 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13275 if (info->gp_save_offset)
13276 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13278 if (info->fp_save_offset)
13279 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13281 if (info->altivec_save_offset)
13282 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13283 info->altivec_save_offset);
13285 if (info->spe_gp_save_offset)
13286 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13287 info->spe_gp_save_offset);
13289 if (info->vrsave_save_offset)
13290 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13291 info->vrsave_save_offset);
13293 if (info->lr_save_offset)
13294 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13296 if (info->cr_save_offset)
13297 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13299 if (info->varargs_save_offset)
13300 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13302 if (info->total_size)
13303 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13306 if (info->vars_size)
13307 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13310 if (info->parm_size)
13311 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13313 if (info->fixed_size)
13314 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13317 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13319 if (info->spe_gp_size)
13320 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13323 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13325 if (info->altivec_size)
13326 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13328 if (info->vrsave_size)
13329 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13331 if (info->altivec_padding_size)
13332 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13333 info->altivec_padding_size);
13335 if (info->spe_padding_size)
13336 fprintf (stderr, "\tspe_padding_size = %5d\n",
13337 info->spe_padding_size);
13340 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13342 if (info->save_size)
13343 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13345 if (info->reg_size != 4)
13346 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13348 fprintf (stderr, "\n");
13352 rs6000_return_addr (int count, rtx frame)
13354 /* Currently we don't optimize very well between prolog and body
13355 code and for PIC code the code can be actually quite bad, so
13356 don't try to be too clever here. */
13357 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13359 cfun->machine->ra_needs_full_frame = 1;
13366 plus_constant (copy_to_reg
13367 (gen_rtx_MEM (Pmode,
13368 memory_address (Pmode, frame))),
13369 RETURN_ADDRESS_OFFSET)));
13372 cfun->machine->ra_need_lr = 1;
13373 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13376 /* Say whether a function is a candidate for sibcall handling or not.
13377 We do not allow indirect calls to be optimized into sibling calls.
13378 Also, we can't do it if there are any vector parameters; there's
13379 nowhere to put the VRsave code so it works; note that functions with
13380 vector parameters are required to have a prototype, so the argument
13381 type info must be available here. (The tail recursion case can work
13382 with vector parameters, but there's no way to distinguish here.) */
13384 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13389 if (TARGET_ALTIVEC_VRSAVE)
13391 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13392 type; type = TREE_CHAIN (type))
13394 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13398 if (DEFAULT_ABI == ABI_DARWIN
13399 || (*targetm.binds_local_p) (decl))
13401 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13403 if (!lookup_attribute ("longcall", attr_list)
13404 || lookup_attribute ("shortcall", attr_list))
13411 /* NULL if INSN insn is valid within a low-overhead loop.
13412 Otherwise return why doloop cannot be applied.
13413 PowerPC uses the COUNT register for branch on table instructions. */
13415 static const char *
13416 rs6000_invalid_within_doloop (rtx insn)
13419 return "Function call in the loop.";
13422 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
13423 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
13424 return "Computed branch in the loop.";
13430 rs6000_ra_ever_killed (void)
13436 if (current_function_is_thunk)
13439 /* regs_ever_live has LR marked as used if any sibcalls are present,
13440 but this should not force saving and restoring in the
13441 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13442 clobbers LR, so that is inappropriate. */
13444 /* Also, the prologue can generate a store into LR that
13445 doesn't really count, like this:
13448 bcl to set PIC register
13452 When we're called from the epilogue, we need to avoid counting
13453 this as a store. */
13455 push_topmost_sequence ();
13456 top = get_insns ();
13457 pop_topmost_sequence ();
13458 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13460 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13466 if (!SIBLING_CALL_P (insn))
13469 else if (find_regno_note (insn, REG_INC, LINK_REGISTER_REGNUM))
13471 else if (set_of (reg, insn) != NULL_RTX
13472 && !prologue_epilogue_contains (insn))
13479 /* Add a REG_MAYBE_DEAD note to the insn. */
13481 rs6000_maybe_dead (rtx insn)
13483 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13488 /* Emit instructions needed to load the TOC register.
13489 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13490 a constant pool; or for SVR4 -fpic. */
13493 rs6000_emit_load_toc_table (int fromprolog)
13496 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13498 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
13501 rtx lab, tmp1, tmp2, got, tempLR;
13503 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13504 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13506 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13508 got = rs6000_got_sym ();
13509 tmp1 = tmp2 = dest;
13512 tmp1 = gen_reg_rtx (Pmode);
13513 tmp2 = gen_reg_rtx (Pmode);
13515 tempLR = (fromprolog
13516 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13517 : gen_reg_rtx (Pmode));
13518 insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab));
13520 rs6000_maybe_dead (insn);
13521 insn = emit_move_insn (tmp1, tempLR);
13523 rs6000_maybe_dead (insn);
13524 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
13526 rs6000_maybe_dead (insn);
13527 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
13529 rs6000_maybe_dead (insn);
13531 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
13533 rtx tempLR = (fromprolog
13534 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13535 : gen_reg_rtx (Pmode));
13537 insn = emit_insn (gen_load_toc_v4_pic_si (tempLR));
13539 rs6000_maybe_dead (insn);
13540 insn = emit_move_insn (dest, tempLR);
13542 rs6000_maybe_dead (insn);
13544 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
13547 rtx tempLR = (fromprolog
13548 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13549 : gen_reg_rtx (Pmode));
13550 rtx temp0 = (fromprolog
13551 ? gen_rtx_REG (Pmode, 0)
13552 : gen_reg_rtx (Pmode));
13558 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13559 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13561 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
13562 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13564 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
13566 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
13567 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
13575 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13576 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
13577 emit_move_insn (dest, tempLR);
13578 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
13580 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
13582 rs6000_maybe_dead (insn);
13584 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
13586 /* This is for AIX code running in non-PIC ELF32. */
13589 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
13590 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13592 insn = emit_insn (gen_elf_high (dest, realsym));
13594 rs6000_maybe_dead (insn);
13595 insn = emit_insn (gen_elf_low (dest, dest, realsym));
13597 rs6000_maybe_dead (insn);
13601 gcc_assert (DEFAULT_ABI == ABI_AIX);
13604 insn = emit_insn (gen_load_toc_aix_si (dest));
13606 insn = emit_insn (gen_load_toc_aix_di (dest));
13608 rs6000_maybe_dead (insn);
13612 /* Emit instructions to restore the link register after determining where
13613 its value has been stored. */
13616 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
13618 rs6000_stack_t *info = rs6000_stack_info ();
13621 operands[0] = source;
13622 operands[1] = scratch;
13624 if (info->lr_save_p)
13626 rtx frame_rtx = stack_pointer_rtx;
13627 HOST_WIDE_INT sp_offset = 0;
13630 if (frame_pointer_needed
13631 || current_function_calls_alloca
13632 || info->total_size > 32767)
13634 tmp = gen_frame_mem (Pmode, frame_rtx);
13635 emit_move_insn (operands[1], tmp);
13636 frame_rtx = operands[1];
13638 else if (info->push_p)
13639 sp_offset = info->total_size;
13641 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13642 tmp = gen_frame_mem (Pmode, tmp);
13643 emit_move_insn (tmp, operands[0]);
13646 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13649 static GTY(()) int set = -1;
13652 get_TOC_alias_set (void)
13655 set = new_alias_set ();
13659 /* This returns nonzero if the current function uses the TOC. This is
13660 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13661 is generated by the ABI_V4 load_toc_* patterns. */
13668 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13671 rtx pat = PATTERN (insn);
13674 if (GET_CODE (pat) == PARALLEL)
13675 for (i = 0; i < XVECLEN (pat, 0); i++)
13677 rtx sub = XVECEXP (pat, 0, i);
13678 if (GET_CODE (sub) == USE)
13680 sub = XEXP (sub, 0);
13681 if (GET_CODE (sub) == UNSPEC
13682 && XINT (sub, 1) == UNSPEC_TOC)
13692 create_TOC_reference (rtx symbol)
13694 if (no_new_pseudos)
13695 regs_ever_live[TOC_REGISTER] = 1;
13696 return gen_rtx_PLUS (Pmode,
13697 gen_rtx_REG (Pmode, TOC_REGISTER),
13698 gen_rtx_CONST (Pmode,
13699 gen_rtx_MINUS (Pmode, symbol,
13700 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13703 /* If _Unwind_* has been called from within the same module,
13704 toc register is not guaranteed to be saved to 40(1) on function
13705 entry. Save it there in that case. */
13708 rs6000_aix_emit_builtin_unwind_init (void)
13711 rtx stack_top = gen_reg_rtx (Pmode);
13712 rtx opcode_addr = gen_reg_rtx (Pmode);
13713 rtx opcode = gen_reg_rtx (SImode);
13714 rtx tocompare = gen_reg_rtx (SImode);
13715 rtx no_toc_save_needed = gen_label_rtx ();
13717 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
13718 emit_move_insn (stack_top, mem);
13720 mem = gen_frame_mem (Pmode,
13721 gen_rtx_PLUS (Pmode, stack_top,
13722 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13723 emit_move_insn (opcode_addr, mem);
13724 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13725 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13726 : 0xE8410028, SImode));
13728 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13729 SImode, NULL_RTX, NULL_RTX,
13730 no_toc_save_needed);
13732 mem = gen_frame_mem (Pmode,
13733 gen_rtx_PLUS (Pmode, stack_top,
13734 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13735 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13736 emit_label (no_toc_save_needed);
13739 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
13740 and the change to the stack pointer. */
13743 rs6000_emit_stack_tie (void)
13745 rtx mem = gen_frame_mem (BLKmode,
13746 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
13748 emit_insn (gen_stack_tie (mem));
13751 /* Emit the correct code for allocating stack space, as insns.
13752 If COPY_R12, make sure a copy of the old frame is left in r12.
13753 The generated code may use hard register 0 as a temporary. */
13756 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
13759 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13760 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
13761 rtx todec = gen_int_mode (-size, Pmode);
13763 if (INTVAL (todec) != -size)
13765 warning (0, "stack frame too large");
13766 emit_insn (gen_trap ());
13770 if (current_function_limit_stack)
13772 if (REG_P (stack_limit_rtx)
13773 && REGNO (stack_limit_rtx) > 1
13774 && REGNO (stack_limit_rtx) <= 31)
13776 emit_insn (TARGET_32BIT
13777 ? gen_addsi3 (tmp_reg,
13780 : gen_adddi3 (tmp_reg,
13784 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13787 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
13789 && DEFAULT_ABI == ABI_V4)
13791 rtx toload = gen_rtx_CONST (VOIDmode,
13792 gen_rtx_PLUS (Pmode,
13796 emit_insn (gen_elf_high (tmp_reg, toload));
13797 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
13798 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13802 warning (0, "stack limit expression is not supported");
13805 if (copy_r12 || ! TARGET_UPDATE)
13806 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
13812 /* Need a note here so that try_split doesn't get confused. */
13813 if (get_last_insn () == NULL_RTX)
13814 emit_note (NOTE_INSN_DELETED);
13815 insn = emit_move_insn (tmp_reg, todec);
13816 try_split (PATTERN (insn), insn, 0);
13820 insn = emit_insn (TARGET_32BIT
13821 ? gen_movsi_update (stack_reg, stack_reg,
13823 : gen_movdi_di_update (stack_reg, stack_reg,
13824 todec, stack_reg));
13828 insn = emit_insn (TARGET_32BIT
13829 ? gen_addsi3 (stack_reg, stack_reg, todec)
13830 : gen_adddi3 (stack_reg, stack_reg, todec));
13831 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
13832 gen_rtx_REG (Pmode, 12));
13835 RTX_FRAME_RELATED_P (insn) = 1;
13837 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13838 gen_rtx_SET (VOIDmode, stack_reg,
13839 gen_rtx_PLUS (Pmode, stack_reg,
13844 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13845 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13846 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13847 deduce these equivalences by itself so it wasn't necessary to hold
13848 its hand so much. */
13851 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13852 rtx reg2, rtx rreg)
13856 /* copy_rtx will not make unique copies of registers, so we need to
13857 ensure we don't have unwanted sharing here. */
13859 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13862 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13864 real = copy_rtx (PATTERN (insn));
13866 if (reg2 != NULL_RTX)
13867 real = replace_rtx (real, reg2, rreg);
13869 real = replace_rtx (real, reg,
13870 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13871 STACK_POINTER_REGNUM),
13874 /* We expect that 'real' is either a SET or a PARALLEL containing
13875 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13876 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13878 if (GET_CODE (real) == SET)
13882 temp = simplify_rtx (SET_SRC (set));
13884 SET_SRC (set) = temp;
13885 temp = simplify_rtx (SET_DEST (set));
13887 SET_DEST (set) = temp;
13888 if (GET_CODE (SET_DEST (set)) == MEM)
13890 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13892 XEXP (SET_DEST (set), 0) = temp;
13899 gcc_assert (GET_CODE (real) == PARALLEL);
13900 for (i = 0; i < XVECLEN (real, 0); i++)
13901 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13903 rtx set = XVECEXP (real, 0, i);
13905 temp = simplify_rtx (SET_SRC (set));
13907 SET_SRC (set) = temp;
13908 temp = simplify_rtx (SET_DEST (set));
13910 SET_DEST (set) = temp;
13911 if (GET_CODE (SET_DEST (set)) == MEM)
13913 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13915 XEXP (SET_DEST (set), 0) = temp;
13917 RTX_FRAME_RELATED_P (set) = 1;
13922 real = spe_synthesize_frame_save (real);
13924 RTX_FRAME_RELATED_P (insn) = 1;
13925 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13930 /* Given an SPE frame note, return a PARALLEL of SETs with the
13931 original note, plus a synthetic register save. */
13934 spe_synthesize_frame_save (rtx real)
13936 rtx synth, offset, reg, real2;
13938 if (GET_CODE (real) != SET
13939 || GET_MODE (SET_SRC (real)) != V2SImode)
13942 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13943 frame related note. The parallel contains a set of the register
13944 being saved, and another set to a synthetic register (n+1200).
13945 This is so we can differentiate between 64-bit and 32-bit saves.
13946 Words cannot describe this nastiness. */
13948 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
13949 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
13950 && GET_CODE (SET_SRC (real)) == REG);
13953 (set (mem (plus (reg x) (const y)))
13956 (set (mem (plus (reg x) (const y+4)))
13960 real2 = copy_rtx (real);
13961 PUT_MODE (SET_DEST (real2), SImode);
13962 reg = SET_SRC (real2);
13963 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
13964 synth = copy_rtx (real2);
13966 if (BYTES_BIG_ENDIAN)
13968 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
13969 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
13972 reg = SET_SRC (synth);
13974 synth = replace_rtx (synth, reg,
13975 gen_rtx_REG (SImode, REGNO (reg) + 1200));
13977 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
13978 synth = replace_rtx (synth, offset,
13979 GEN_INT (INTVAL (offset)
13980 + (BYTES_BIG_ENDIAN ? 0 : 4)));
13982 RTX_FRAME_RELATED_P (synth) = 1;
13983 RTX_FRAME_RELATED_P (real2) = 1;
13984 if (BYTES_BIG_ENDIAN)
13985 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
13987 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
13992 /* Returns an insn that has a vrsave set operation with the
13993 appropriate CLOBBERs. */
13996 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
13999 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
14000 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14003 = gen_rtx_SET (VOIDmode,
14005 gen_rtx_UNSPEC_VOLATILE (SImode,
14006 gen_rtvec (2, reg, vrsave),
14007 UNSPECV_SET_VRSAVE));
14011 /* We need to clobber the registers in the mask so the scheduler
14012 does not move sets to VRSAVE before sets of AltiVec registers.
14014 However, if the function receives nonlocal gotos, reload will set
14015 all call saved registers live. We will end up with:
14017 (set (reg 999) (mem))
14018 (parallel [ (set (reg vrsave) (unspec blah))
14019 (clobber (reg 999))])
14021 The clobber will cause the store into reg 999 to be dead, and
14022 flow will attempt to delete an epilogue insn. In this case, we
14023 need an unspec use/set of the register. */
14025 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14026 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14028 if (!epiloguep || call_used_regs [i])
14029 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
14030 gen_rtx_REG (V4SImode, i));
14033 rtx reg = gen_rtx_REG (V4SImode, i);
14036 = gen_rtx_SET (VOIDmode,
14038 gen_rtx_UNSPEC (V4SImode,
14039 gen_rtvec (1, reg), 27));
14043 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
14045 for (i = 0; i < nclobs; ++i)
14046 XVECEXP (insn, 0, i) = clobs[i];
14051 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
14052 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
14055 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
14056 unsigned int regno, int offset, HOST_WIDE_INT total_size)
14058 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
14059 rtx replacea, replaceb;
14061 int_rtx = GEN_INT (offset);
14063 /* Some cases that need register indexed addressing. */
14064 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
14065 || (TARGET_E500_DOUBLE && mode == DFmode)
14067 && SPE_VECTOR_MODE (mode)
14068 && !SPE_CONST_OFFSET_OK (offset)))
14070 /* Whomever calls us must make sure r11 is available in the
14071 flow path of instructions in the prologue. */
14072 offset_rtx = gen_rtx_REG (Pmode, 11);
14073 emit_move_insn (offset_rtx, int_rtx);
14075 replacea = offset_rtx;
14076 replaceb = int_rtx;
14080 offset_rtx = int_rtx;
14081 replacea = NULL_RTX;
14082 replaceb = NULL_RTX;
14085 reg = gen_rtx_REG (mode, regno);
14086 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
14087 mem = gen_frame_mem (mode, addr);
14089 insn = emit_move_insn (mem, reg);
14091 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
14094 /* Emit an offset memory reference suitable for a frame store, while
14095 converting to a valid addressing mode. */
14098 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
14100 rtx int_rtx, offset_rtx;
14102 int_rtx = GEN_INT (offset);
14104 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
14105 || (TARGET_E500_DOUBLE && mode == DFmode))
14107 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14108 emit_move_insn (offset_rtx, int_rtx);
14111 offset_rtx = int_rtx;
14113 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
14116 /* Look for user-defined global regs. We should not save and restore these,
14117 and cannot use stmw/lmw if there are any in its range. */
14120 no_global_regs_above (int first_greg)
14123 for (i = 0; i < 32 - first_greg; i++)
14124 if (global_regs[first_greg + i])
14129 #ifndef TARGET_FIX_AND_CONTINUE
14130 #define TARGET_FIX_AND_CONTINUE 0
14133 /* Emit function prologue as insns. */
14136 rs6000_emit_prologue (void)
14138 rs6000_stack_t *info = rs6000_stack_info ();
14139 enum machine_mode reg_mode = Pmode;
14140 int reg_size = TARGET_32BIT ? 4 : 8;
14141 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14142 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
14143 rtx frame_reg_rtx = sp_reg_rtx;
14144 rtx cr_save_rtx = NULL_RTX;
14146 int saving_FPRs_inline;
14147 int using_store_multiple;
14148 HOST_WIDE_INT sp_offset = 0;
14150 if (TARGET_FIX_AND_CONTINUE)
14152 /* gdb on darwin arranges to forward a function from the old
14153 address by modifying the first 5 instructions of the function
14154 to branch to the overriding function. This is necessary to
14155 permit function pointers that point to the old function to
14156 actually forward to the new function. */
14157 emit_insn (gen_nop ());
14158 emit_insn (gen_nop ());
14159 emit_insn (gen_nop ());
14160 emit_insn (gen_nop ());
14161 emit_insn (gen_nop ());
14164 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14166 reg_mode = V2SImode;
14170 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14171 && (!TARGET_SPE_ABI
14172 || info->spe_64bit_regs_used == 0)
14173 && info->first_gp_reg_save < 31
14174 && no_global_regs_above (info->first_gp_reg_save));
14175 saving_FPRs_inline = (info->first_fp_reg_save == 64
14176 || FP_SAVE_INLINE (info->first_fp_reg_save)
14177 || current_function_calls_eh_return
14178 || cfun->machine->ra_need_lr);
14180 /* For V.4, update stack before we do any saving and set back pointer. */
14182 && (DEFAULT_ABI == ABI_V4
14183 || current_function_calls_eh_return))
14185 if (info->total_size < 32767)
14186 sp_offset = info->total_size;
14188 frame_reg_rtx = frame_ptr_rtx;
14189 rs6000_emit_allocate_stack (info->total_size,
14190 (frame_reg_rtx != sp_reg_rtx
14191 && (info->cr_save_p
14193 || info->first_fp_reg_save < 64
14194 || info->first_gp_reg_save < 32
14196 if (frame_reg_rtx != sp_reg_rtx)
14197 rs6000_emit_stack_tie ();
14200 /* Handle world saves specially here. */
14201 if (WORLD_SAVE_P (info))
14207 /* save_world expects lr in r0. */
14208 if (info->lr_save_p)
14210 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14211 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14212 RTX_FRAME_RELATED_P (insn) = 1;
14215 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14216 assumptions about the offsets of various bits of the stack
14218 gcc_assert (info->gp_save_offset == -220
14219 && info->fp_save_offset == -144
14220 && info->lr_save_offset == 8
14221 && info->cr_save_offset == 4
14224 && (!current_function_calls_eh_return
14225 || info->ehrd_offset == -432)
14226 && info->vrsave_save_offset == -224
14227 && info->altivec_save_offset == (-224 -16 -192));
14229 treg = gen_rtx_REG (SImode, 11);
14230 emit_move_insn (treg, GEN_INT (-info->total_size));
14232 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14233 in R11. It also clobbers R12, so beware! */
14235 /* Preserve CR2 for save_world prologues */
14237 sz += 32 - info->first_gp_reg_save;
14238 sz += 64 - info->first_fp_reg_save;
14239 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14240 p = rtvec_alloc (sz);
14242 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14243 gen_rtx_REG (Pmode,
14244 LINK_REGISTER_REGNUM));
14245 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14246 gen_rtx_SYMBOL_REF (Pmode,
14248 /* We do floats first so that the instruction pattern matches
14250 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14252 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14253 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14254 GEN_INT (info->fp_save_offset
14255 + sp_offset + 8 * i));
14256 rtx mem = gen_frame_mem (DFmode, addr);
14258 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14260 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14262 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14263 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14264 GEN_INT (info->altivec_save_offset
14265 + sp_offset + 16 * i));
14266 rtx mem = gen_frame_mem (V4SImode, addr);
14268 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14270 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14272 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14273 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14274 GEN_INT (info->gp_save_offset
14275 + sp_offset + reg_size * i));
14276 rtx mem = gen_frame_mem (reg_mode, addr);
14278 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14282 /* CR register traditionally saved as CR2. */
14283 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14284 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14285 GEN_INT (info->cr_save_offset
14287 rtx mem = gen_frame_mem (reg_mode, addr);
14289 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14291 /* Prevent any attempt to delete the setting of r0 and treg! */
14292 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
14293 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
14294 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
14296 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14297 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14298 NULL_RTX, NULL_RTX);
14300 if (current_function_calls_eh_return)
14305 unsigned int regno = EH_RETURN_DATA_REGNO (i);
14306 if (regno == INVALID_REGNUM)
14308 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14309 info->ehrd_offset + sp_offset
14310 + reg_size * (int) i,
14316 /* Save AltiVec registers if needed. */
14317 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14321 /* There should be a non inline version of this, for when we
14322 are saving lots of vector registers. */
14323 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14324 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14326 rtx areg, savereg, mem;
14329 offset = info->altivec_save_offset + sp_offset
14330 + 16 * (i - info->first_altivec_reg_save);
14332 savereg = gen_rtx_REG (V4SImode, i);
14334 areg = gen_rtx_REG (Pmode, 0);
14335 emit_move_insn (areg, GEN_INT (offset));
14337 /* AltiVec addressing mode is [reg+reg]. */
14338 mem = gen_frame_mem (V4SImode,
14339 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
14341 insn = emit_move_insn (mem, savereg);
14343 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14344 areg, GEN_INT (offset));
14348 /* VRSAVE is a bit vector representing which AltiVec registers
14349 are used. The OS uses this to determine which vector
14350 registers to save on a context switch. We need to save
14351 VRSAVE on the stack frame, add whatever AltiVec registers we
14352 used in this function, and do the corresponding magic in the
14355 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14356 && info->vrsave_mask != 0)
14358 rtx reg, mem, vrsave;
14361 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14362 as frame_reg_rtx and r11 as the static chain pointer for
14363 nested functions. */
14364 reg = gen_rtx_REG (SImode, 0);
14365 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14367 emit_insn (gen_get_vrsave_internal (reg));
14369 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14371 if (!WORLD_SAVE_P (info))
14374 offset = info->vrsave_save_offset + sp_offset;
14375 mem = gen_frame_mem (SImode,
14376 gen_rtx_PLUS (Pmode, frame_reg_rtx,
14377 GEN_INT (offset)));
14378 insn = emit_move_insn (mem, reg);
14381 /* Include the registers in the mask. */
14382 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14384 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14387 /* If we use the link register, get it into r0. */
14388 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14390 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14391 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14392 RTX_FRAME_RELATED_P (insn) = 1;
14395 /* If we need to save CR, put it into r12. */
14396 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14400 cr_save_rtx = gen_rtx_REG (SImode, 12);
14401 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14402 RTX_FRAME_RELATED_P (insn) = 1;
14403 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14404 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14405 But that's OK. All we have to do is specify that _one_ condition
14406 code register is saved in this stack slot. The thrower's epilogue
14407 will then restore all the call-saved registers.
14408 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14409 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14410 gen_rtx_REG (SImode, CR2_REGNO));
14411 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14416 /* Do any required saving of fpr's. If only one or two to save, do
14417 it ourselves. Otherwise, call function. */
14418 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14421 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14422 if ((regs_ever_live[info->first_fp_reg_save+i]
14423 && ! call_used_regs[info->first_fp_reg_save+i]))
14424 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14425 info->first_fp_reg_save + i,
14426 info->fp_save_offset + sp_offset + 8 * i,
14429 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14433 const char *alloc_rname;
14435 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14437 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14438 gen_rtx_REG (Pmode,
14439 LINK_REGISTER_REGNUM));
14440 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14441 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14442 alloc_rname = ggc_strdup (rname);
14443 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14444 gen_rtx_SYMBOL_REF (Pmode,
14446 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14448 rtx addr, reg, mem;
14449 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14450 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14451 GEN_INT (info->fp_save_offset
14452 + sp_offset + 8*i));
14453 mem = gen_frame_mem (DFmode, addr);
14455 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14457 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14458 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14459 NULL_RTX, NULL_RTX);
14462 /* Save GPRs. This is done as a PARALLEL if we are using
14463 the store-multiple instructions. */
14464 if (!WORLD_SAVE_P (info) && using_store_multiple)
14468 p = rtvec_alloc (32 - info->first_gp_reg_save);
14469 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14471 rtx addr, reg, mem;
14472 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14473 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14474 GEN_INT (info->gp_save_offset
14477 mem = gen_frame_mem (reg_mode, addr);
14479 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14481 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14482 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14483 NULL_RTX, NULL_RTX);
14485 else if (!WORLD_SAVE_P (info))
14488 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14489 if ((regs_ever_live[info->first_gp_reg_save + i]
14490 && (!call_used_regs[info->first_gp_reg_save + i]
14491 || (i + info->first_gp_reg_save
14492 == RS6000_PIC_OFFSET_TABLE_REGNUM
14493 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14494 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14495 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14496 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14498 rtx addr, reg, mem;
14499 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14501 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14503 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14506 if (!SPE_CONST_OFFSET_OK (offset))
14508 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14509 emit_move_insn (b, GEN_INT (offset));
14512 b = GEN_INT (offset);
14514 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14515 mem = gen_frame_mem (V2SImode, addr);
14516 insn = emit_move_insn (mem, reg);
14518 if (GET_CODE (b) == CONST_INT)
14519 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14520 NULL_RTX, NULL_RTX);
14522 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14523 b, GEN_INT (offset));
14527 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14528 GEN_INT (info->gp_save_offset
14531 mem = gen_frame_mem (reg_mode, addr);
14533 insn = emit_move_insn (mem, reg);
14534 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14535 NULL_RTX, NULL_RTX);
14540 /* ??? There's no need to emit actual instructions here, but it's the
14541 easiest way to get the frame unwind information emitted. */
14542 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
14544 unsigned int i, regno;
14546 /* In AIX ABI we need to pretend we save r2 here. */
14549 rtx addr, reg, mem;
14551 reg = gen_rtx_REG (reg_mode, 2);
14552 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14553 GEN_INT (sp_offset + 5 * reg_size));
14554 mem = gen_frame_mem (reg_mode, addr);
14556 insn = emit_move_insn (mem, reg);
14557 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14558 NULL_RTX, NULL_RTX);
14559 PATTERN (insn) = gen_blockage ();
14564 regno = EH_RETURN_DATA_REGNO (i);
14565 if (regno == INVALID_REGNUM)
14568 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14569 info->ehrd_offset + sp_offset
14570 + reg_size * (int) i,
14575 /* Save lr if we used it. */
14576 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14578 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14579 GEN_INT (info->lr_save_offset + sp_offset));
14580 rtx reg = gen_rtx_REG (Pmode, 0);
14581 rtx mem = gen_rtx_MEM (Pmode, addr);
14582 /* This should not be of frame_alias_set, because of
14583 __builtin_return_address. */
14585 insn = emit_move_insn (mem, reg);
14586 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14587 NULL_RTX, NULL_RTX);
14590 /* Save CR if we use any that must be preserved. */
14591 if (!WORLD_SAVE_P (info) && info->cr_save_p)
14593 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14594 GEN_INT (info->cr_save_offset + sp_offset));
14595 rtx mem = gen_frame_mem (SImode, addr);
14596 /* See the large comment above about why CR2_REGNO is used. */
14597 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
14599 /* If r12 was used to hold the original sp, copy cr into r0 now
14601 if (REGNO (frame_reg_rtx) == 12)
14605 cr_save_rtx = gen_rtx_REG (SImode, 0);
14606 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14607 RTX_FRAME_RELATED_P (insn) = 1;
14608 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
14609 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14614 insn = emit_move_insn (mem, cr_save_rtx);
14616 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14617 NULL_RTX, NULL_RTX);
14620 /* Update stack and set back pointer unless this is V.4,
14621 for which it was done previously. */
14622 if (!WORLD_SAVE_P (info) && info->push_p
14623 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
14624 rs6000_emit_allocate_stack (info->total_size, FALSE);
14626 /* Set frame pointer, if needed. */
14627 if (frame_pointer_needed)
14629 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
14631 RTX_FRAME_RELATED_P (insn) = 1;
14634 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14635 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
14636 || (DEFAULT_ABI == ABI_V4
14637 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
14638 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
14640 /* If emit_load_toc_table will use the link register, we need to save
14641 it. We use R12 for this purpose because emit_load_toc_table
14642 can use register 0. This allows us to use a plain 'blr' to return
14643 from the procedure more often. */
14644 int save_LR_around_toc_setup = (TARGET_ELF
14645 && DEFAULT_ABI != ABI_AIX
14647 && ! info->lr_save_p
14648 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
14649 if (save_LR_around_toc_setup)
14651 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14653 insn = emit_move_insn (frame_ptr_rtx, lr);
14654 rs6000_maybe_dead (insn);
14655 RTX_FRAME_RELATED_P (insn) = 1;
14657 rs6000_emit_load_toc_table (TRUE);
14659 insn = emit_move_insn (lr, frame_ptr_rtx);
14660 rs6000_maybe_dead (insn);
14661 RTX_FRAME_RELATED_P (insn) = 1;
14664 rs6000_emit_load_toc_table (TRUE);
14668 if (DEFAULT_ABI == ABI_DARWIN
14669 && flag_pic && current_function_uses_pic_offset_table)
14671 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14672 rtx src = machopic_function_base_sym ();
14674 /* Save and restore LR locally around this call (in R0). */
14675 if (!info->lr_save_p)
14676 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr));
14678 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14680 insn = emit_move_insn (gen_rtx_REG (Pmode,
14681 RS6000_PIC_OFFSET_TABLE_REGNUM),
14683 rs6000_maybe_dead (insn);
14685 if (!info->lr_save_p)
14686 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0)));
14691 /* Write function prologue. */
14694 rs6000_output_function_prologue (FILE *file,
14695 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14697 rs6000_stack_t *info = rs6000_stack_info ();
14699 if (TARGET_DEBUG_STACK)
14700 debug_stack_info (info);
14702 /* Write .extern for any function we will call to save and restore
14704 if (info->first_fp_reg_save < 64
14705 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14706 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14707 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14708 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14709 RESTORE_FP_SUFFIX);
14711 /* Write .extern for AIX common mode routines, if needed. */
14712 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14714 fputs ("\t.extern __mulh\n", file);
14715 fputs ("\t.extern __mull\n", file);
14716 fputs ("\t.extern __divss\n", file);
14717 fputs ("\t.extern __divus\n", file);
14718 fputs ("\t.extern __quoss\n", file);
14719 fputs ("\t.extern __quous\n", file);
14720 common_mode_defined = 1;
14723 if (! HAVE_prologue)
14727 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14728 the "toplevel" insn chain. */
14729 emit_note (NOTE_INSN_DELETED);
14730 rs6000_emit_prologue ();
14731 emit_note (NOTE_INSN_DELETED);
14733 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14737 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14739 INSN_ADDRESSES_NEW (insn, addr);
14744 if (TARGET_DEBUG_STACK)
14745 debug_rtx_list (get_insns (), 100);
14746 final (get_insns (), file, FALSE);
14750 rs6000_pic_labelno++;
14753 /* Emit function epilogue as insns.
14755 At present, dwarf2out_frame_debug_expr doesn't understand
14756 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14757 anywhere in the epilogue. Most of the insns below would in any case
14758 need special notes to explain where r11 is in relation to the stack. */
14761 rs6000_emit_epilogue (int sibcall)
14763 rs6000_stack_t *info;
14764 int restoring_FPRs_inline;
14765 int using_load_multiple;
14766 int using_mfcr_multiple;
14767 int use_backchain_to_restore_sp;
14769 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
14770 rtx frame_reg_rtx = sp_reg_rtx;
14771 enum machine_mode reg_mode = Pmode;
14772 int reg_size = TARGET_32BIT ? 4 : 8;
14775 info = rs6000_stack_info ();
14777 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14779 reg_mode = V2SImode;
14783 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14784 && (!TARGET_SPE_ABI
14785 || info->spe_64bit_regs_used == 0)
14786 && info->first_gp_reg_save < 31
14787 && no_global_regs_above (info->first_gp_reg_save));
14788 restoring_FPRs_inline = (sibcall
14789 || current_function_calls_eh_return
14790 || info->first_fp_reg_save == 64
14791 || FP_SAVE_INLINE (info->first_fp_reg_save));
14792 use_backchain_to_restore_sp = (frame_pointer_needed
14793 || current_function_calls_alloca
14794 || info->total_size > 32767);
14795 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
14796 || rs6000_cpu == PROCESSOR_PPC603
14797 || rs6000_cpu == PROCESSOR_PPC750
14800 if (WORLD_SAVE_P (info))
14804 const char *alloc_rname;
14807 /* eh_rest_world_r10 will return to the location saved in the LR
14808 stack slot (which is not likely to be our caller.)
14809 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14810 rest_world is similar, except any R10 parameter is ignored.
14811 The exception-handling stuff that was here in 2.95 is no
14812 longer necessary. */
14816 + 32 - info->first_gp_reg_save
14817 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
14818 + 63 + 1 - info->first_fp_reg_save);
14820 strcpy (rname, ((current_function_calls_eh_return) ?
14821 "*eh_rest_world_r10" : "*rest_world"));
14822 alloc_rname = ggc_strdup (rname);
14825 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
14826 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14827 gen_rtx_REG (Pmode,
14828 LINK_REGISTER_REGNUM));
14830 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
14831 /* The instruction pattern requires a clobber here;
14832 it is shared with the restVEC helper. */
14834 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14837 /* CR register traditionally saved as CR2. */
14838 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14839 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14840 GEN_INT (info->cr_save_offset));
14841 rtx mem = gen_frame_mem (reg_mode, addr);
14843 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14846 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14848 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14849 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14850 GEN_INT (info->gp_save_offset
14852 rtx mem = gen_frame_mem (reg_mode, addr);
14854 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14856 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14858 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14859 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14860 GEN_INT (info->altivec_save_offset
14862 rtx mem = gen_frame_mem (V4SImode, addr);
14864 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14866 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14868 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14869 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14870 GEN_INT (info->fp_save_offset
14872 rtx mem = gen_frame_mem (DFmode, addr);
14874 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14877 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
14879 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
14881 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
14883 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
14885 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
14886 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14891 /* If we have a frame pointer, a call to alloca, or a large stack
14892 frame, restore the old stack pointer using the backchain. Otherwise,
14893 we know what size to update it with. */
14894 if (use_backchain_to_restore_sp)
14896 /* Under V.4, don't reset the stack pointer until after we're done
14897 loading the saved registers. */
14898 if (DEFAULT_ABI == ABI_V4)
14899 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
14901 emit_move_insn (frame_reg_rtx,
14902 gen_rtx_MEM (Pmode, sp_reg_rtx));
14904 else if (info->push_p)
14906 if (DEFAULT_ABI == ABI_V4
14907 || current_function_calls_eh_return)
14908 sp_offset = info->total_size;
14911 emit_insn (TARGET_32BIT
14912 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14913 GEN_INT (info->total_size))
14914 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14915 GEN_INT (info->total_size)));
14919 /* Restore AltiVec registers if needed. */
14920 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14924 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14925 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14927 rtx addr, areg, mem;
14929 areg = gen_rtx_REG (Pmode, 0);
14931 (areg, GEN_INT (info->altivec_save_offset
14933 + 16 * (i - info->first_altivec_reg_save)));
14935 /* AltiVec addressing mode is [reg+reg]. */
14936 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14937 mem = gen_frame_mem (V4SImode, addr);
14939 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14943 /* Restore VRSAVE if needed. */
14944 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14945 && info->vrsave_mask != 0)
14947 rtx addr, mem, reg;
14949 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14950 GEN_INT (info->vrsave_save_offset + sp_offset));
14951 mem = gen_frame_mem (SImode, addr);
14952 reg = gen_rtx_REG (SImode, 12);
14953 emit_move_insn (reg, mem);
14955 emit_insn (generate_set_vrsave (reg, info, 1));
14958 /* Get the old lr if we saved it. */
14959 if (info->lr_save_p)
14961 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
14962 info->lr_save_offset + sp_offset);
14964 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
14967 /* Get the old cr if we saved it. */
14968 if (info->cr_save_p)
14970 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14971 GEN_INT (info->cr_save_offset + sp_offset));
14972 rtx mem = gen_frame_mem (SImode, addr);
14974 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
14977 /* Set LR here to try to overlap restores below. */
14978 if (info->lr_save_p)
14979 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
14980 gen_rtx_REG (Pmode, 0));
14982 /* Load exception handler data registers, if needed. */
14983 if (current_function_calls_eh_return)
14985 unsigned int i, regno;
14989 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14990 GEN_INT (sp_offset + 5 * reg_size));
14991 rtx mem = gen_frame_mem (reg_mode, addr);
14993 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
15000 regno = EH_RETURN_DATA_REGNO (i);
15001 if (regno == INVALID_REGNUM)
15004 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
15005 info->ehrd_offset + sp_offset
15006 + reg_size * (int) i);
15008 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
15012 /* Restore GPRs. This is done as a PARALLEL if we are using
15013 the load-multiple instructions. */
15014 if (using_load_multiple)
15017 p = rtvec_alloc (32 - info->first_gp_reg_save);
15018 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15020 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15021 GEN_INT (info->gp_save_offset
15024 rtx mem = gen_frame_mem (reg_mode, addr);
15027 gen_rtx_SET (VOIDmode,
15028 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15031 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15034 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15035 if ((regs_ever_live[info->first_gp_reg_save + i]
15036 && (!call_used_regs[info->first_gp_reg_save + i]
15037 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
15038 && TARGET_TOC && TARGET_MINIMAL_TOC)))
15039 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
15040 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
15041 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
15043 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15044 GEN_INT (info->gp_save_offset
15047 rtx mem = gen_frame_mem (reg_mode, addr);
15049 /* Restore 64-bit quantities for SPE. */
15050 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15052 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
15055 if (!SPE_CONST_OFFSET_OK (offset))
15057 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
15058 emit_move_insn (b, GEN_INT (offset));
15061 b = GEN_INT (offset);
15063 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
15064 mem = gen_frame_mem (V2SImode, addr);
15067 emit_move_insn (gen_rtx_REG (reg_mode,
15068 info->first_gp_reg_save + i), mem);
15071 /* Restore fpr's if we need to do it without calling a function. */
15072 if (restoring_FPRs_inline)
15073 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15074 if ((regs_ever_live[info->first_fp_reg_save+i]
15075 && ! call_used_regs[info->first_fp_reg_save+i]))
15078 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15079 GEN_INT (info->fp_save_offset
15082 mem = gen_frame_mem (DFmode, addr);
15084 emit_move_insn (gen_rtx_REG (DFmode,
15085 info->first_fp_reg_save + i),
15089 /* If we saved cr, restore it here. Just those that were used. */
15090 if (info->cr_save_p)
15092 rtx r12_rtx = gen_rtx_REG (SImode, 12);
15095 if (using_mfcr_multiple)
15097 for (i = 0; i < 8; i++)
15098 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15100 gcc_assert (count);
15103 if (using_mfcr_multiple && count > 1)
15108 p = rtvec_alloc (count);
15111 for (i = 0; i < 8; i++)
15112 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15114 rtvec r = rtvec_alloc (2);
15115 RTVEC_ELT (r, 0) = r12_rtx;
15116 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
15117 RTVEC_ELT (p, ndx) =
15118 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
15119 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
15122 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15123 gcc_assert (ndx == count);
15126 for (i = 0; i < 8; i++)
15127 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15129 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
15135 /* If this is V.4, unwind the stack pointer after all of the loads
15137 if (frame_reg_rtx != sp_reg_rtx)
15139 /* This blockage is needed so that sched doesn't decide to move
15140 the sp change before the register restores. */
15141 rs6000_emit_stack_tie ();
15142 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15144 else if (sp_offset != 0)
15145 emit_insn (TARGET_32BIT
15146 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15147 GEN_INT (sp_offset))
15148 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15149 GEN_INT (sp_offset)));
15151 if (current_function_calls_eh_return)
15153 rtx sa = EH_RETURN_STACKADJ_RTX;
15154 emit_insn (TARGET_32BIT
15155 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
15156 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
15162 if (! restoring_FPRs_inline)
15163 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
15165 p = rtvec_alloc (2);
15167 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15168 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15169 gen_rtx_REG (Pmode,
15170 LINK_REGISTER_REGNUM));
15172 /* If we have to restore more than two FP registers, branch to the
15173 restore function. It will return to our caller. */
15174 if (! restoring_FPRs_inline)
15178 const char *alloc_rname;
15180 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15181 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15182 alloc_rname = ggc_strdup (rname);
15183 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15184 gen_rtx_SYMBOL_REF (Pmode,
15187 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15190 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15191 GEN_INT (info->fp_save_offset + 8*i));
15192 mem = gen_frame_mem (DFmode, addr);
15194 RTVEC_ELT (p, i+3) =
15195 gen_rtx_SET (VOIDmode,
15196 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15201 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15205 /* Write function epilogue. */
15208 rs6000_output_function_epilogue (FILE *file,
15209 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15211 if (! HAVE_epilogue)
15213 rtx insn = get_last_insn ();
15214 /* If the last insn was a BARRIER, we don't have to write anything except
15215 the trace table. */
15216 if (GET_CODE (insn) == NOTE)
15217 insn = prev_nonnote_insn (insn);
15218 if (insn == 0 || GET_CODE (insn) != BARRIER)
15220 /* This is slightly ugly, but at least we don't have two
15221 copies of the epilogue-emitting code. */
15224 /* A NOTE_INSN_DELETED is supposed to be at the start
15225 and end of the "toplevel" insn chain. */
15226 emit_note (NOTE_INSN_DELETED);
15227 rs6000_emit_epilogue (FALSE);
15228 emit_note (NOTE_INSN_DELETED);
15230 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15234 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15236 INSN_ADDRESSES_NEW (insn, addr);
15241 if (TARGET_DEBUG_STACK)
15242 debug_rtx_list (get_insns (), 100);
15243 final (get_insns (), file, FALSE);
15249 macho_branch_islands ();
15250 /* Mach-O doesn't support labels at the end of objects, so if
15251 it looks like we might want one, insert a NOP. */
15253 rtx insn = get_last_insn ();
15256 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
15257 insn = PREV_INSN (insn);
15261 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
15262 fputs ("\tnop\n", file);
15266 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15269 We don't output a traceback table if -finhibit-size-directive was
15270 used. The documentation for -finhibit-size-directive reads
15271 ``don't output a @code{.size} assembler directive, or anything
15272 else that would cause trouble if the function is split in the
15273 middle, and the two halves are placed at locations far apart in
15274 memory.'' The traceback table has this property, since it
15275 includes the offset from the start of the function to the
15276 traceback table itself.
15278 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15279 different traceback table. */
15280 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15281 && rs6000_traceback != traceback_none && !current_function_is_thunk)
15283 const char *fname = NULL;
15284 const char *language_string = lang_hooks.name;
15285 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15287 int optional_tbtab;
15288 rs6000_stack_t *info = rs6000_stack_info ();
15290 if (rs6000_traceback == traceback_full)
15291 optional_tbtab = 1;
15292 else if (rs6000_traceback == traceback_part)
15293 optional_tbtab = 0;
15295 optional_tbtab = !optimize_size && !TARGET_ELF;
15297 if (optional_tbtab)
15299 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15300 while (*fname == '.') /* V.4 encodes . in the name */
15303 /* Need label immediately before tbtab, so we can compute
15304 its offset from the function start. */
15305 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15306 ASM_OUTPUT_LABEL (file, fname);
15309 /* The .tbtab pseudo-op can only be used for the first eight
15310 expressions, since it can't handle the possibly variable
15311 length fields that follow. However, if you omit the optional
15312 fields, the assembler outputs zeros for all optional fields
15313 anyways, giving each variable length field is minimum length
15314 (as defined in sys/debug.h). Thus we can not use the .tbtab
15315 pseudo-op at all. */
15317 /* An all-zero word flags the start of the tbtab, for debuggers
15318 that have to find it by searching forward from the entry
15319 point or from the current pc. */
15320 fputs ("\t.long 0\n", file);
15322 /* Tbtab format type. Use format type 0. */
15323 fputs ("\t.byte 0,", file);
15325 /* Language type. Unfortunately, there does not seem to be any
15326 official way to discover the language being compiled, so we
15327 use language_string.
15328 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15329 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
15330 a number, so for now use 9. */
15331 if (! strcmp (language_string, "GNU C"))
15333 else if (! strcmp (language_string, "GNU F77")
15334 || ! strcmp (language_string, "GNU F95"))
15336 else if (! strcmp (language_string, "GNU Pascal"))
15338 else if (! strcmp (language_string, "GNU Ada"))
15340 else if (! strcmp (language_string, "GNU C++")
15341 || ! strcmp (language_string, "GNU Objective-C++"))
15343 else if (! strcmp (language_string, "GNU Java"))
15345 else if (! strcmp (language_string, "GNU Objective-C"))
15348 gcc_unreachable ();
15349 fprintf (file, "%d,", i);
15351 /* 8 single bit fields: global linkage (not set for C extern linkage,
15352 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15353 from start of procedure stored in tbtab, internal function, function
15354 has controlled storage, function has no toc, function uses fp,
15355 function logs/aborts fp operations. */
15356 /* Assume that fp operations are used if any fp reg must be saved. */
15357 fprintf (file, "%d,",
15358 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15360 /* 6 bitfields: function is interrupt handler, name present in
15361 proc table, function calls alloca, on condition directives
15362 (controls stack walks, 3 bits), saves condition reg, saves
15364 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15365 set up as a frame pointer, even when there is no alloca call. */
15366 fprintf (file, "%d,",
15367 ((optional_tbtab << 6)
15368 | ((optional_tbtab & frame_pointer_needed) << 5)
15369 | (info->cr_save_p << 1)
15370 | (info->lr_save_p)));
15372 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15374 fprintf (file, "%d,",
15375 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15377 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15378 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15380 if (optional_tbtab)
15382 /* Compute the parameter info from the function decl argument
15385 int next_parm_info_bit = 31;
15387 for (decl = DECL_ARGUMENTS (current_function_decl);
15388 decl; decl = TREE_CHAIN (decl))
15390 rtx parameter = DECL_INCOMING_RTL (decl);
15391 enum machine_mode mode = GET_MODE (parameter);
15393 if (GET_CODE (parameter) == REG)
15395 if (SCALAR_FLOAT_MODE_P (mode))
15413 gcc_unreachable ();
15416 /* If only one bit will fit, don't or in this entry. */
15417 if (next_parm_info_bit > 0)
15418 parm_info |= (bits << (next_parm_info_bit - 1));
15419 next_parm_info_bit -= 2;
15423 fixed_parms += ((GET_MODE_SIZE (mode)
15424 + (UNITS_PER_WORD - 1))
15426 next_parm_info_bit -= 1;
15432 /* Number of fixed point parameters. */
15433 /* This is actually the number of words of fixed point parameters; thus
15434 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15435 fprintf (file, "%d,", fixed_parms);
15437 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15439 /* This is actually the number of fp registers that hold parameters;
15440 and thus the maximum value is 13. */
15441 /* Set parameters on stack bit if parameters are not in their original
15442 registers, regardless of whether they are on the stack? Xlc
15443 seems to set the bit when not optimizing. */
15444 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15446 if (! optional_tbtab)
15449 /* Optional fields follow. Some are variable length. */
15451 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15452 11 double float. */
15453 /* There is an entry for each parameter in a register, in the order that
15454 they occur in the parameter list. Any intervening arguments on the
15455 stack are ignored. If the list overflows a long (max possible length
15456 34 bits) then completely leave off all elements that don't fit. */
15457 /* Only emit this long if there was at least one parameter. */
15458 if (fixed_parms || float_parms)
15459 fprintf (file, "\t.long %d\n", parm_info);
15461 /* Offset from start of code to tb table. */
15462 fputs ("\t.long ", file);
15463 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15465 RS6000_OUTPUT_BASENAME (file, fname);
15467 assemble_name (file, fname);
15469 rs6000_output_function_entry (file, fname);
15472 /* Interrupt handler mask. */
15473 /* Omit this long, since we never set the interrupt handler bit
15476 /* Number of CTL (controlled storage) anchors. */
15477 /* Omit this long, since the has_ctl bit is never set above. */
15479 /* Displacement into stack of each CTL anchor. */
15480 /* Omit this list of longs, because there are no CTL anchors. */
15482 /* Length of function name. */
15485 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15487 /* Function name. */
15488 assemble_string (fname, strlen (fname));
15490 /* Register for alloca automatic storage; this is always reg 31.
15491 Only emit this if the alloca bit was set above. */
15492 if (frame_pointer_needed)
15493 fputs ("\t.byte 31\n", file);
15495 fputs ("\t.align 2\n", file);
15499 /* A C compound statement that outputs the assembler code for a thunk
15500 function, used to implement C++ virtual function calls with
15501 multiple inheritance. The thunk acts as a wrapper around a virtual
15502 function, adjusting the implicit object parameter before handing
15503 control off to the real function.
15505 First, emit code to add the integer DELTA to the location that
15506 contains the incoming first argument. Assume that this argument
15507 contains a pointer, and is the one used to pass the `this' pointer
15508 in C++. This is the incoming argument *before* the function
15509 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15510 values of all other incoming arguments.
15512 After the addition, emit code to jump to FUNCTION, which is a
15513 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15514 not touch the return address. Hence returning from FUNCTION will
15515 return to whoever called the current `thunk'.
15517 The effect must be as if FUNCTION had been called directly with the
15518 adjusted first argument. This macro is responsible for emitting
15519 all of the code for a thunk function; output_function_prologue()
15520 and output_function_epilogue() are not invoked.
15522 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15523 been extracted from it.) It might possibly be useful on some
15524 targets, but probably not.
15526 If you do not define this macro, the target-independent code in the
15527 C++ frontend will generate a less efficient heavyweight thunk that
15528 calls FUNCTION instead of jumping to it. The generic approach does
15529 not support varargs. */
15532 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15533 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15536 rtx this, insn, funexp;
15538 reload_completed = 1;
15539 epilogue_completed = 1;
15540 no_new_pseudos = 1;
15541 reset_block_changes ();
15543 /* Mark the end of the (empty) prologue. */
15544 emit_note (NOTE_INSN_PROLOGUE_END);
15546 /* Find the "this" pointer. If the function returns a structure,
15547 the structure return pointer is in r3. */
15548 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15549 this = gen_rtx_REG (Pmode, 4);
15551 this = gen_rtx_REG (Pmode, 3);
15553 /* Apply the constant offset, if required. */
15556 rtx delta_rtx = GEN_INT (delta);
15557 emit_insn (TARGET_32BIT
15558 ? gen_addsi3 (this, this, delta_rtx)
15559 : gen_adddi3 (this, this, delta_rtx));
15562 /* Apply the offset from the vtable, if required. */
15565 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15566 rtx tmp = gen_rtx_REG (Pmode, 12);
15568 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
15569 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15571 emit_insn (TARGET_32BIT
15572 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
15573 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
15574 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15578 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15580 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15582 emit_insn (TARGET_32BIT
15583 ? gen_addsi3 (this, this, tmp)
15584 : gen_adddi3 (this, this, tmp));
15587 /* Generate a tail call to the target function. */
15588 if (!TREE_USED (function))
15590 assemble_external (function);
15591 TREE_USED (function) = 1;
15593 funexp = XEXP (DECL_RTL (function), 0);
15594 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15597 if (MACHOPIC_INDIRECT)
15598 funexp = machopic_indirect_call_target (funexp);
15601 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15602 generate sibcall RTL explicitly. */
15603 insn = emit_call_insn (
15604 gen_rtx_PARALLEL (VOIDmode,
15606 gen_rtx_CALL (VOIDmode,
15607 funexp, const0_rtx),
15608 gen_rtx_USE (VOIDmode, const0_rtx),
15609 gen_rtx_USE (VOIDmode,
15610 gen_rtx_REG (SImode,
15611 LINK_REGISTER_REGNUM)),
15612 gen_rtx_RETURN (VOIDmode))));
15613 SIBLING_CALL_P (insn) = 1;
15616 /* Run just enough of rest_of_compilation to get the insns emitted.
15617 There's not really enough bulk here to make other passes such as
15618 instruction scheduling worth while. Note that use_thunk calls
15619 assemble_start_function and assemble_end_function. */
15620 insn = get_insns ();
15621 insn_locators_initialize ();
15622 shorten_branches (insn);
15623 final_start_function (insn, file, 1);
15624 final (insn, file, 1);
15625 final_end_function ();
15627 reload_completed = 0;
15628 epilogue_completed = 0;
15629 no_new_pseudos = 0;
15632 /* A quick summary of the various types of 'constant-pool tables'
15635 Target Flags Name One table per
15636 AIX (none) AIX TOC object file
15637 AIX -mfull-toc AIX TOC object file
15638 AIX -mminimal-toc AIX minimal TOC translation unit
15639 SVR4/EABI (none) SVR4 SDATA object file
15640 SVR4/EABI -fpic SVR4 pic object file
15641 SVR4/EABI -fPIC SVR4 PIC translation unit
15642 SVR4/EABI -mrelocatable EABI TOC function
15643 SVR4/EABI -maix AIX TOC object file
15644 SVR4/EABI -maix -mminimal-toc
15645 AIX minimal TOC translation unit
15647 Name Reg. Set by entries contains:
15648 made by addrs? fp? sum?
15650 AIX TOC 2 crt0 as Y option option
15651 AIX minimal TOC 30 prolog gcc Y Y option
15652 SVR4 SDATA 13 crt0 gcc N Y N
15653 SVR4 pic 30 prolog ld Y not yet N
15654 SVR4 PIC 30 prolog gcc Y option option
15655 EABI TOC 30 prolog gcc Y option option
15659 /* Hash functions for the hash table. */
15662 rs6000_hash_constant (rtx k)
15664 enum rtx_code code = GET_CODE (k);
15665 enum machine_mode mode = GET_MODE (k);
15666 unsigned result = (code << 3) ^ mode;
15667 const char *format;
15670 format = GET_RTX_FORMAT (code);
15671 flen = strlen (format);
15677 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15680 if (mode != VOIDmode)
15681 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15693 for (; fidx < flen; fidx++)
15694 switch (format[fidx])
15699 const char *str = XSTR (k, fidx);
15700 len = strlen (str);
15701 result = result * 613 + len;
15702 for (i = 0; i < len; i++)
15703 result = result * 613 + (unsigned) str[i];
15708 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15712 result = result * 613 + (unsigned) XINT (k, fidx);
15715 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15716 result = result * 613 + (unsigned) XWINT (k, fidx);
15720 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
15721 result = result * 613 + (unsigned) (XWINT (k, fidx)
15728 gcc_unreachable ();
15735 toc_hash_function (const void *hash_entry)
15737 const struct toc_hash_struct *thc =
15738 (const struct toc_hash_struct *) hash_entry;
15739 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15742 /* Compare H1 and H2 for equivalence. */
15745 toc_hash_eq (const void *h1, const void *h2)
15747 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
15748 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
15750 if (((const struct toc_hash_struct *) h1)->key_mode
15751 != ((const struct toc_hash_struct *) h2)->key_mode)
15754 return rtx_equal_p (r1, r2);
15757 /* These are the names given by the C++ front-end to vtables, and
15758 vtable-like objects. Ideally, this logic should not be here;
15759 instead, there should be some programmatic way of inquiring as
15760 to whether or not an object is a vtable. */
15762 #define VTABLE_NAME_P(NAME) \
15763 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
15764 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15765 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15766 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15767 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15770 rs6000_output_symbol_ref (FILE *file, rtx x)
15772 /* Currently C++ toc references to vtables can be emitted before it
15773 is decided whether the vtable is public or private. If this is
15774 the case, then the linker will eventually complain that there is
15775 a reference to an unknown section. Thus, for vtables only,
15776 we emit the TOC reference to reference the symbol and not the
15778 const char *name = XSTR (x, 0);
15780 if (VTABLE_NAME_P (name))
15782 RS6000_OUTPUT_BASENAME (file, name);
15785 assemble_name (file, name);
15788 /* Output a TOC entry. We derive the entry name from what is being
15792 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
15795 const char *name = buf;
15796 const char *real_name;
15798 HOST_WIDE_INT offset = 0;
15800 gcc_assert (!TARGET_NO_TOC);
15802 /* When the linker won't eliminate them, don't output duplicate
15803 TOC entries (this happens on AIX if there is any kind of TOC,
15804 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15806 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15808 struct toc_hash_struct *h;
15811 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15812 time because GGC is not initialized at that point. */
15813 if (toc_hash_table == NULL)
15814 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15815 toc_hash_eq, NULL);
15817 h = ggc_alloc (sizeof (*h));
15819 h->key_mode = mode;
15820 h->labelno = labelno;
15822 found = htab_find_slot (toc_hash_table, h, 1);
15823 if (*found == NULL)
15825 else /* This is indeed a duplicate.
15826 Set this label equal to that label. */
15828 fputs ("\t.set ", file);
15829 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15830 fprintf (file, "%d,", labelno);
15831 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15832 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15838 /* If we're going to put a double constant in the TOC, make sure it's
15839 aligned properly when strict alignment is on. */
15840 if (GET_CODE (x) == CONST_DOUBLE
15841 && STRICT_ALIGNMENT
15842 && GET_MODE_BITSIZE (mode) >= 64
15843 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15844 ASM_OUTPUT_ALIGN (file, 3);
15847 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15849 /* Handle FP constants specially. Note that if we have a minimal
15850 TOC, things we put here aren't actually in the TOC, so we can allow
15852 if (GET_CODE (x) == CONST_DOUBLE &&
15853 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
15855 REAL_VALUE_TYPE rv;
15858 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15859 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15860 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
15862 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15866 if (TARGET_MINIMAL_TOC)
15867 fputs (DOUBLE_INT_ASM_OP, file);
15869 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15870 k[0] & 0xffffffff, k[1] & 0xffffffff,
15871 k[2] & 0xffffffff, k[3] & 0xffffffff);
15872 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15873 k[0] & 0xffffffff, k[1] & 0xffffffff,
15874 k[2] & 0xffffffff, k[3] & 0xffffffff);
15879 if (TARGET_MINIMAL_TOC)
15880 fputs ("\t.long ", file);
15882 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15883 k[0] & 0xffffffff, k[1] & 0xffffffff,
15884 k[2] & 0xffffffff, k[3] & 0xffffffff);
15885 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15886 k[0] & 0xffffffff, k[1] & 0xffffffff,
15887 k[2] & 0xffffffff, k[3] & 0xffffffff);
15891 else if (GET_CODE (x) == CONST_DOUBLE &&
15892 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
15894 REAL_VALUE_TYPE rv;
15897 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15899 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15900 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
15902 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
15906 if (TARGET_MINIMAL_TOC)
15907 fputs (DOUBLE_INT_ASM_OP, file);
15909 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15910 k[0] & 0xffffffff, k[1] & 0xffffffff);
15911 fprintf (file, "0x%lx%08lx\n",
15912 k[0] & 0xffffffff, k[1] & 0xffffffff);
15917 if (TARGET_MINIMAL_TOC)
15918 fputs ("\t.long ", file);
15920 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15921 k[0] & 0xffffffff, k[1] & 0xffffffff);
15922 fprintf (file, "0x%lx,0x%lx\n",
15923 k[0] & 0xffffffff, k[1] & 0xffffffff);
15927 else if (GET_CODE (x) == CONST_DOUBLE &&
15928 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
15930 REAL_VALUE_TYPE rv;
15933 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15934 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15935 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
15937 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15941 if (TARGET_MINIMAL_TOC)
15942 fputs (DOUBLE_INT_ASM_OP, file);
15944 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15945 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
15950 if (TARGET_MINIMAL_TOC)
15951 fputs ("\t.long ", file);
15953 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15954 fprintf (file, "0x%lx\n", l & 0xffffffff);
15958 else if (GET_MODE (x) == VOIDmode
15959 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
15961 unsigned HOST_WIDE_INT low;
15962 HOST_WIDE_INT high;
15964 if (GET_CODE (x) == CONST_DOUBLE)
15966 low = CONST_DOUBLE_LOW (x);
15967 high = CONST_DOUBLE_HIGH (x);
15970 #if HOST_BITS_PER_WIDE_INT == 32
15973 high = (low & 0x80000000) ? ~0 : 0;
15977 low = INTVAL (x) & 0xffffffff;
15978 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
15982 /* TOC entries are always Pmode-sized, but since this
15983 is a bigendian machine then if we're putting smaller
15984 integer constants in the TOC we have to pad them.
15985 (This is still a win over putting the constants in
15986 a separate constant pool, because then we'd have
15987 to have both a TOC entry _and_ the actual constant.)
15989 For a 32-bit target, CONST_INT values are loaded and shifted
15990 entirely within `low' and can be stored in one TOC entry. */
15992 /* It would be easy to make this work, but it doesn't now. */
15993 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
15995 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
15997 #if HOST_BITS_PER_WIDE_INT == 32
15998 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15999 POINTER_SIZE, &low, &high, 0);
16002 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
16003 high = (HOST_WIDE_INT) low >> 32;
16010 if (TARGET_MINIMAL_TOC)
16011 fputs (DOUBLE_INT_ASM_OP, file);
16013 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16014 (long) high & 0xffffffff, (long) low & 0xffffffff);
16015 fprintf (file, "0x%lx%08lx\n",
16016 (long) high & 0xffffffff, (long) low & 0xffffffff);
16021 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
16023 if (TARGET_MINIMAL_TOC)
16024 fputs ("\t.long ", file);
16026 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16027 (long) high & 0xffffffff, (long) low & 0xffffffff);
16028 fprintf (file, "0x%lx,0x%lx\n",
16029 (long) high & 0xffffffff, (long) low & 0xffffffff);
16033 if (TARGET_MINIMAL_TOC)
16034 fputs ("\t.long ", file);
16036 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
16037 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
16043 if (GET_CODE (x) == CONST)
16045 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
16047 base = XEXP (XEXP (x, 0), 0);
16048 offset = INTVAL (XEXP (XEXP (x, 0), 1));
16051 switch (GET_CODE (base))
16054 name = XSTR (base, 0);
16058 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
16059 CODE_LABEL_NUMBER (XEXP (base, 0)));
16063 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
16067 gcc_unreachable ();
16070 real_name = (*targetm.strip_name_encoding) (name);
16071 if (TARGET_MINIMAL_TOC)
16072 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
16075 fprintf (file, "\t.tc %s", real_name);
16078 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
16080 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
16082 fputs ("[TC],", file);
16085 /* Currently C++ toc references to vtables can be emitted before it
16086 is decided whether the vtable is public or private. If this is
16087 the case, then the linker will eventually complain that there is
16088 a TOC reference to an unknown section. Thus, for vtables only,
16089 we emit the TOC reference to reference the symbol and not the
16091 if (VTABLE_NAME_P (name))
16093 RS6000_OUTPUT_BASENAME (file, name);
16095 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16096 else if (offset > 0)
16097 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
16100 output_addr_const (file, x);
16104 /* Output an assembler pseudo-op to write an ASCII string of N characters
16105 starting at P to FILE.
16107 On the RS/6000, we have to do this using the .byte operation and
16108 write out special characters outside the quoted string.
16109 Also, the assembler is broken; very long strings are truncated,
16110 so we must artificially break them up early. */
16113 output_ascii (FILE *file, const char *p, int n)
16116 int i, count_string;
16117 const char *for_string = "\t.byte \"";
16118 const char *for_decimal = "\t.byte ";
16119 const char *to_close = NULL;
16122 for (i = 0; i < n; i++)
16125 if (c >= ' ' && c < 0177)
16128 fputs (for_string, file);
16131 /* Write two quotes to get one. */
16139 for_decimal = "\"\n\t.byte ";
16143 if (count_string >= 512)
16145 fputs (to_close, file);
16147 for_string = "\t.byte \"";
16148 for_decimal = "\t.byte ";
16156 fputs (for_decimal, file);
16157 fprintf (file, "%d", c);
16159 for_string = "\n\t.byte \"";
16160 for_decimal = ", ";
16166 /* Now close the string if we have written one. Then end the line. */
16168 fputs (to_close, file);
16171 /* Generate a unique section name for FILENAME for a section type
16172 represented by SECTION_DESC. Output goes into BUF.
16174 SECTION_DESC can be any string, as long as it is different for each
16175 possible section type.
16177 We name the section in the same manner as xlc. The name begins with an
16178 underscore followed by the filename (after stripping any leading directory
16179 names) with the last period replaced by the string SECTION_DESC. If
16180 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16184 rs6000_gen_section_name (char **buf, const char *filename,
16185 const char *section_desc)
16187 const char *q, *after_last_slash, *last_period = 0;
16191 after_last_slash = filename;
16192 for (q = filename; *q; q++)
16195 after_last_slash = q + 1;
16196 else if (*q == '.')
16200 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16201 *buf = (char *) xmalloc (len);
16206 for (q = after_last_slash; *q; q++)
16208 if (q == last_period)
16210 strcpy (p, section_desc);
16211 p += strlen (section_desc);
16215 else if (ISALNUM (*q))
16219 if (last_period == 0)
16220 strcpy (p, section_desc);
16225 /* Emit profile function. */
16228 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16230 /* Non-standard profiling for kernels, which just saves LR then calls
16231 _mcount without worrying about arg saves. The idea is to change
16232 the function prologue as little as possible as it isn't easy to
16233 account for arg save/restore code added just for _mcount. */
16234 if (TARGET_PROFILE_KERNEL)
16237 if (DEFAULT_ABI == ABI_AIX)
16239 #ifndef NO_PROFILE_COUNTERS
16240 # define NO_PROFILE_COUNTERS 0
16242 if (NO_PROFILE_COUNTERS)
16243 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16247 const char *label_name;
16250 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16251 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16252 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16254 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16258 else if (DEFAULT_ABI == ABI_DARWIN)
16260 const char *mcount_name = RS6000_MCOUNT;
16261 int caller_addr_regno = LINK_REGISTER_REGNUM;
16263 /* Be conservative and always set this, at least for now. */
16264 current_function_uses_pic_offset_table = 1;
16267 /* For PIC code, set up a stub and collect the caller's address
16268 from r0, which is where the prologue puts it. */
16269 if (MACHOPIC_INDIRECT
16270 && current_function_uses_pic_offset_table)
16271 caller_addr_regno = 0;
16273 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16275 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16279 /* Write function profiler code. */
16282 output_function_profiler (FILE *file, int labelno)
16286 switch (DEFAULT_ABI)
16289 gcc_unreachable ();
16294 warning (0, "no profiling of 64-bit code for this ABI");
16297 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16298 fprintf (file, "\tmflr %s\n", reg_names[0]);
16299 if (NO_PROFILE_COUNTERS)
16301 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16302 reg_names[0], reg_names[1]);
16304 else if (TARGET_SECURE_PLT && flag_pic)
16306 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16307 reg_names[0], reg_names[1]);
16308 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16309 asm_fprintf (file, "\t{cau|addis} %s,%s,",
16310 reg_names[12], reg_names[12]);
16311 assemble_name (file, buf);
16312 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
16313 assemble_name (file, buf);
16314 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
16316 else if (flag_pic == 1)
16318 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16319 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16320 reg_names[0], reg_names[1]);
16321 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16322 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16323 assemble_name (file, buf);
16324 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16326 else if (flag_pic > 1)
16328 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16329 reg_names[0], reg_names[1]);
16330 /* Now, we need to get the address of the label. */
16331 fputs ("\tbcl 20,31,1f\n\t.long ", file);
16332 assemble_name (file, buf);
16333 fputs ("-.\n1:", file);
16334 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16335 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16336 reg_names[0], reg_names[11]);
16337 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16338 reg_names[0], reg_names[0], reg_names[11]);
16342 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16343 assemble_name (file, buf);
16344 fputs ("@ha\n", file);
16345 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16346 reg_names[0], reg_names[1]);
16347 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16348 assemble_name (file, buf);
16349 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16352 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16353 fprintf (file, "\tbl %s%s\n",
16354 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16359 if (!TARGET_PROFILE_KERNEL)
16361 /* Don't do anything, done in output_profile_hook (). */
16365 gcc_assert (!TARGET_32BIT);
16367 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16368 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16370 if (cfun->static_chain_decl != NULL)
16372 asm_fprintf (file, "\tstd %s,24(%s)\n",
16373 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16374 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16375 asm_fprintf (file, "\tld %s,24(%s)\n",
16376 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16379 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16386 /* Power4 load update and store update instructions are cracked into a
16387 load or store and an integer insn which are executed in the same cycle.
16388 Branches have their own dispatch slot which does not count against the
16389 GCC issue rate, but it changes the program flow so there are no other
16390 instructions to issue in this cycle. */
16393 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16394 int verbose ATTRIBUTE_UNUSED,
16395 rtx insn, int more)
16397 if (GET_CODE (PATTERN (insn)) == USE
16398 || GET_CODE (PATTERN (insn)) == CLOBBER)
16401 if (rs6000_sched_groups)
16403 if (is_microcoded_insn (insn))
16405 else if (is_cracked_insn (insn))
16406 return more > 2 ? more - 2 : 0;
16412 /* Adjust the cost of a scheduling dependency. Return the new cost of
16413 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16416 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16418 if (! recog_memoized (insn))
16421 if (REG_NOTE_KIND (link) != 0)
16424 if (REG_NOTE_KIND (link) == 0)
16426 /* Data dependency; DEP_INSN writes a register that INSN reads
16427 some cycles later. */
16429 /* Separate a load from a narrower, dependent store. */
16430 if (rs6000_sched_groups
16431 && GET_CODE (PATTERN (insn)) == SET
16432 && GET_CODE (PATTERN (dep_insn)) == SET
16433 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16434 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16435 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16436 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16439 switch (get_attr_type (insn))
16442 /* Tell the first scheduling pass about the latency between
16443 a mtctr and bctr (and mtlr and br/blr). The first
16444 scheduling pass will not know about this latency since
16445 the mtctr instruction, which has the latency associated
16446 to it, will be generated by reload. */
16447 return TARGET_POWER ? 5 : 4;
16449 /* Leave some extra cycles between a compare and its
16450 dependent branch, to inhibit expensive mispredicts. */
16451 if ((rs6000_cpu_attr == CPU_PPC603
16452 || rs6000_cpu_attr == CPU_PPC604
16453 || rs6000_cpu_attr == CPU_PPC604E
16454 || rs6000_cpu_attr == CPU_PPC620
16455 || rs6000_cpu_attr == CPU_PPC630
16456 || rs6000_cpu_attr == CPU_PPC750
16457 || rs6000_cpu_attr == CPU_PPC7400
16458 || rs6000_cpu_attr == CPU_PPC7450
16459 || rs6000_cpu_attr == CPU_POWER4
16460 || rs6000_cpu_attr == CPU_POWER5)
16461 && recog_memoized (dep_insn)
16462 && (INSN_CODE (dep_insn) >= 0)
16463 && (get_attr_type (dep_insn) == TYPE_CMP
16464 || get_attr_type (dep_insn) == TYPE_COMPARE
16465 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
16466 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
16467 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
16468 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
16469 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
16470 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
16475 /* Fall out to return default cost. */
16481 /* The function returns a true if INSN is microcoded.
16482 Return false otherwise. */
16485 is_microcoded_insn (rtx insn)
16487 if (!insn || !INSN_P (insn)
16488 || GET_CODE (PATTERN (insn)) == USE
16489 || GET_CODE (PATTERN (insn)) == CLOBBER)
16492 if (rs6000_sched_groups)
16494 enum attr_type type = get_attr_type (insn);
16495 if (type == TYPE_LOAD_EXT_U
16496 || type == TYPE_LOAD_EXT_UX
16497 || type == TYPE_LOAD_UX
16498 || type == TYPE_STORE_UX
16499 || type == TYPE_MFCR)
16506 /* The function returns a nonzero value if INSN can be scheduled only
16507 as the first insn in a dispatch group ("dispatch-slot restricted").
16508 In this case, the returned value indicates how many dispatch slots
16509 the insn occupies (at the beginning of the group).
16510 Return 0 otherwise. */
16513 is_dispatch_slot_restricted (rtx insn)
16515 enum attr_type type;
16517 if (!rs6000_sched_groups)
16521 || insn == NULL_RTX
16522 || GET_CODE (insn) == NOTE
16523 || GET_CODE (PATTERN (insn)) == USE
16524 || GET_CODE (PATTERN (insn)) == CLOBBER)
16527 type = get_attr_type (insn);
16534 case TYPE_DELAYED_CR:
16535 case TYPE_CR_LOGICAL:
16548 if (rs6000_cpu == PROCESSOR_POWER5
16549 && is_cracked_insn (insn))
16555 /* The function returns true if INSN is cracked into 2 instructions
16556 by the processor (and therefore occupies 2 issue slots). */
16559 is_cracked_insn (rtx insn)
16561 if (!insn || !INSN_P (insn)
16562 || GET_CODE (PATTERN (insn)) == USE
16563 || GET_CODE (PATTERN (insn)) == CLOBBER)
16566 if (rs6000_sched_groups)
16568 enum attr_type type = get_attr_type (insn);
16569 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
16570 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
16571 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
16572 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
16573 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
16574 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
16575 || type == TYPE_IDIV || type == TYPE_LDIV
16576 || type == TYPE_INSERT_WORD)
16583 /* The function returns true if INSN can be issued only from
16584 the branch slot. */
16587 is_branch_slot_insn (rtx insn)
16589 if (!insn || !INSN_P (insn)
16590 || GET_CODE (PATTERN (insn)) == USE
16591 || GET_CODE (PATTERN (insn)) == CLOBBER)
16594 if (rs6000_sched_groups)
16596 enum attr_type type = get_attr_type (insn);
16597 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
16605 /* A C statement (sans semicolon) to update the integer scheduling
16606 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16607 INSN earlier, reduce the priority to execute INSN later. Do not
16608 define this macro if you do not need to adjust the scheduling
16609 priorities of insns. */
16612 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
16614 /* On machines (like the 750) which have asymmetric integer units,
16615 where one integer unit can do multiply and divides and the other
16616 can't, reduce the priority of multiply/divide so it is scheduled
16617 before other integer operations. */
16620 if (! INSN_P (insn))
16623 if (GET_CODE (PATTERN (insn)) == USE)
16626 switch (rs6000_cpu_attr) {
16628 switch (get_attr_type (insn))
16635 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
16636 priority, priority);
16637 if (priority >= 0 && priority < 0x01000000)
16644 if (is_dispatch_slot_restricted (insn)
16645 && reload_completed
16646 && current_sched_info->sched_max_insns_priority
16647 && rs6000_sched_restricted_insns_priority)
16650 /* Prioritize insns that can be dispatched only in the first
16652 if (rs6000_sched_restricted_insns_priority == 1)
16653 /* Attach highest priority to insn. This means that in
16654 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16655 precede 'priority' (critical path) considerations. */
16656 return current_sched_info->sched_max_insns_priority;
16657 else if (rs6000_sched_restricted_insns_priority == 2)
16658 /* Increase priority of insn by a minimal amount. This means that in
16659 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16660 considerations precede dispatch-slot restriction considerations. */
16661 return (priority + 1);
16667 /* Return how many instructions the machine can issue per cycle. */
16670 rs6000_issue_rate (void)
16672 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16673 if (!reload_completed)
16676 switch (rs6000_cpu_attr) {
16677 case CPU_RIOS1: /* ? */
16679 case CPU_PPC601: /* ? */
16702 /* Return how many instructions to look ahead for better insn
16706 rs6000_use_sched_lookahead (void)
16708 if (rs6000_cpu_attr == CPU_PPC8540)
16713 /* Determine is PAT refers to memory. */
16716 is_mem_ref (rtx pat)
16722 if (GET_CODE (pat) == MEM)
16725 /* Recursively process the pattern. */
16726 fmt = GET_RTX_FORMAT (GET_CODE (pat));
16728 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
16731 ret |= is_mem_ref (XEXP (pat, i));
16732 else if (fmt[i] == 'E')
16733 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
16734 ret |= is_mem_ref (XVECEXP (pat, i, j));
16740 /* Determine if PAT is a PATTERN of a load insn. */
16743 is_load_insn1 (rtx pat)
16745 if (!pat || pat == NULL_RTX)
16748 if (GET_CODE (pat) == SET)
16749 return is_mem_ref (SET_SRC (pat));
16751 if (GET_CODE (pat) == PARALLEL)
16755 for (i = 0; i < XVECLEN (pat, 0); i++)
16756 if (is_load_insn1 (XVECEXP (pat, 0, i)))
16763 /* Determine if INSN loads from memory. */
16766 is_load_insn (rtx insn)
16768 if (!insn || !INSN_P (insn))
16771 if (GET_CODE (insn) == CALL_INSN)
16774 return is_load_insn1 (PATTERN (insn));
16777 /* Determine if PAT is a PATTERN of a store insn. */
16780 is_store_insn1 (rtx pat)
16782 if (!pat || pat == NULL_RTX)
16785 if (GET_CODE (pat) == SET)
16786 return is_mem_ref (SET_DEST (pat));
16788 if (GET_CODE (pat) == PARALLEL)
16792 for (i = 0; i < XVECLEN (pat, 0); i++)
16793 if (is_store_insn1 (XVECEXP (pat, 0, i)))
16800 /* Determine if INSN stores to memory. */
16803 is_store_insn (rtx insn)
16805 if (!insn || !INSN_P (insn))
16808 return is_store_insn1 (PATTERN (insn));
16811 /* Returns whether the dependence between INSN and NEXT is considered
16812 costly by the given target. */
16815 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
16818 /* If the flag is not enabled - no dependence is considered costly;
16819 allow all dependent insns in the same group.
16820 This is the most aggressive option. */
16821 if (rs6000_sched_costly_dep == no_dep_costly)
16824 /* If the flag is set to 1 - a dependence is always considered costly;
16825 do not allow dependent instructions in the same group.
16826 This is the most conservative option. */
16827 if (rs6000_sched_costly_dep == all_deps_costly)
16830 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16831 && is_load_insn (next)
16832 && is_store_insn (insn))
16833 /* Prevent load after store in the same group. */
16836 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16837 && is_load_insn (next)
16838 && is_store_insn (insn)
16839 && (!link || (int) REG_NOTE_KIND (link) == 0))
16840 /* Prevent load after store in the same group if it is a true
16844 /* The flag is set to X; dependences with latency >= X are considered costly,
16845 and will not be scheduled in the same group. */
16846 if (rs6000_sched_costly_dep <= max_dep_latency
16847 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16853 /* Return the next insn after INSN that is found before TAIL is reached,
16854 skipping any "non-active" insns - insns that will not actually occupy
16855 an issue slot. Return NULL_RTX if such an insn is not found. */
16858 get_next_active_insn (rtx insn, rtx tail)
16860 if (insn == NULL_RTX || insn == tail)
16865 insn = NEXT_INSN (insn);
16866 if (insn == NULL_RTX || insn == tail)
16871 || (NONJUMP_INSN_P (insn)
16872 && GET_CODE (PATTERN (insn)) != USE
16873 && GET_CODE (PATTERN (insn)) != CLOBBER
16874 && INSN_CODE (insn) != CODE_FOR_stack_tie))
16880 /* Return whether the presence of INSN causes a dispatch group termination
16881 of group WHICH_GROUP.
16883 If WHICH_GROUP == current_group, this function will return true if INSN
16884 causes the termination of the current group (i.e, the dispatch group to
16885 which INSN belongs). This means that INSN will be the last insn in the
16886 group it belongs to.
16888 If WHICH_GROUP == previous_group, this function will return true if INSN
16889 causes the termination of the previous group (i.e, the dispatch group that
16890 precedes the group to which INSN belongs). This means that INSN will be
16891 the first insn in the group it belongs to). */
16894 insn_terminates_group_p (rtx insn, enum group_termination which_group)
16896 enum attr_type type;
16901 type = get_attr_type (insn);
16903 if (is_microcoded_insn (insn))
16906 if (which_group == current_group)
16908 if (is_branch_slot_insn (insn))
16912 else if (which_group == previous_group)
16914 if (is_dispatch_slot_restricted (insn))
16922 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16923 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16926 is_costly_group (rtx *group_insns, rtx next_insn)
16931 int issue_rate = rs6000_issue_rate ();
16933 for (i = 0; i < issue_rate; i++)
16935 rtx insn = group_insns[i];
16938 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
16940 rtx next = XEXP (link, 0);
16941 if (next == next_insn)
16943 cost = insn_cost (insn, link, next_insn);
16944 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
16953 /* Utility of the function redefine_groups.
16954 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16955 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16956 to keep it "far" (in a separate group) from GROUP_INSNS, following
16957 one of the following schemes, depending on the value of the flag
16958 -minsert_sched_nops = X:
16959 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16960 in order to force NEXT_INSN into a separate group.
16961 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16962 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16963 insertion (has a group just ended, how many vacant issue slots remain in the
16964 last group, and how many dispatch groups were encountered so far). */
16967 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
16968 rtx next_insn, bool *group_end, int can_issue_more,
16973 int issue_rate = rs6000_issue_rate ();
16974 bool end = *group_end;
16977 if (next_insn == NULL_RTX)
16978 return can_issue_more;
16980 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
16981 return can_issue_more;
16983 force = is_costly_group (group_insns, next_insn);
16985 return can_issue_more;
16987 if (sched_verbose > 6)
16988 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
16989 *group_count ,can_issue_more);
16991 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
16994 can_issue_more = 0;
16996 /* Since only a branch can be issued in the last issue_slot, it is
16997 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16998 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16999 in this case the last nop will start a new group and the branch
17000 will be forced to the new group. */
17001 if (can_issue_more && !is_branch_slot_insn (next_insn))
17004 while (can_issue_more > 0)
17007 emit_insn_before (nop, next_insn);
17015 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
17017 int n_nops = rs6000_sched_insert_nops;
17019 /* Nops can't be issued from the branch slot, so the effective
17020 issue_rate for nops is 'issue_rate - 1'. */
17021 if (can_issue_more == 0)
17022 can_issue_more = issue_rate;
17024 if (can_issue_more == 0)
17026 can_issue_more = issue_rate - 1;
17029 for (i = 0; i < issue_rate; i++)
17031 group_insns[i] = 0;
17038 emit_insn_before (nop, next_insn);
17039 if (can_issue_more == issue_rate - 1) /* new group begins */
17042 if (can_issue_more == 0)
17044 can_issue_more = issue_rate - 1;
17047 for (i = 0; i < issue_rate; i++)
17049 group_insns[i] = 0;
17055 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
17058 /* Is next_insn going to start a new group? */
17061 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
17062 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
17063 || (can_issue_more < issue_rate &&
17064 insn_terminates_group_p (next_insn, previous_group)));
17065 if (*group_end && end)
17068 if (sched_verbose > 6)
17069 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
17070 *group_count, can_issue_more);
17071 return can_issue_more;
17074 return can_issue_more;
17077 /* This function tries to synch the dispatch groups that the compiler "sees"
17078 with the dispatch groups that the processor dispatcher is expected to
17079 form in practice. It tries to achieve this synchronization by forcing the
17080 estimated processor grouping on the compiler (as opposed to the function
17081 'pad_goups' which tries to force the scheduler's grouping on the processor).
17083 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
17084 examines the (estimated) dispatch groups that will be formed by the processor
17085 dispatcher. It marks these group boundaries to reflect the estimated
17086 processor grouping, overriding the grouping that the scheduler had marked.
17087 Depending on the value of the flag '-minsert-sched-nops' this function can
17088 force certain insns into separate groups or force a certain distance between
17089 them by inserting nops, for example, if there exists a "costly dependence"
17092 The function estimates the group boundaries that the processor will form as
17093 follows: It keeps track of how many vacant issue slots are available after
17094 each insn. A subsequent insn will start a new group if one of the following
17096 - no more vacant issue slots remain in the current dispatch group.
17097 - only the last issue slot, which is the branch slot, is vacant, but the next
17098 insn is not a branch.
17099 - only the last 2 or less issue slots, including the branch slot, are vacant,
17100 which means that a cracked insn (which occupies two issue slots) can't be
17101 issued in this group.
17102 - less than 'issue_rate' slots are vacant, and the next insn always needs to
17103 start a new group. */
17106 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
17108 rtx insn, next_insn;
17110 int can_issue_more;
17113 int group_count = 0;
17117 issue_rate = rs6000_issue_rate ();
17118 group_insns = alloca (issue_rate * sizeof (rtx));
17119 for (i = 0; i < issue_rate; i++)
17121 group_insns[i] = 0;
17123 can_issue_more = issue_rate;
17125 insn = get_next_active_insn (prev_head_insn, tail);
17128 while (insn != NULL_RTX)
17130 slot = (issue_rate - can_issue_more);
17131 group_insns[slot] = insn;
17133 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
17134 if (insn_terminates_group_p (insn, current_group))
17135 can_issue_more = 0;
17137 next_insn = get_next_active_insn (insn, tail);
17138 if (next_insn == NULL_RTX)
17139 return group_count + 1;
17141 /* Is next_insn going to start a new group? */
17143 = (can_issue_more == 0
17144 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
17145 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
17146 || (can_issue_more < issue_rate &&
17147 insn_terminates_group_p (next_insn, previous_group)));
17149 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
17150 next_insn, &group_end, can_issue_more,
17156 can_issue_more = 0;
17157 for (i = 0; i < issue_rate; i++)
17159 group_insns[i] = 0;
17163 if (GET_MODE (next_insn) == TImode && can_issue_more)
17164 PUT_MODE (next_insn, VOIDmode);
17165 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
17166 PUT_MODE (next_insn, TImode);
17169 if (can_issue_more == 0)
17170 can_issue_more = issue_rate;
17173 return group_count;
17176 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
17177 dispatch group boundaries that the scheduler had marked. Pad with nops
17178 any dispatch groups which have vacant issue slots, in order to force the
17179 scheduler's grouping on the processor dispatcher. The function
17180 returns the number of dispatch groups found. */
17183 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
17185 rtx insn, next_insn;
17188 int can_issue_more;
17190 int group_count = 0;
17192 /* Initialize issue_rate. */
17193 issue_rate = rs6000_issue_rate ();
17194 can_issue_more = issue_rate;
17196 insn = get_next_active_insn (prev_head_insn, tail);
17197 next_insn = get_next_active_insn (insn, tail);
17199 while (insn != NULL_RTX)
17202 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
17204 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
17206 if (next_insn == NULL_RTX)
17211 /* If the scheduler had marked group termination at this location
17212 (between insn and next_indn), and neither insn nor next_insn will
17213 force group termination, pad the group with nops to force group
17216 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
17217 && !insn_terminates_group_p (insn, current_group)
17218 && !insn_terminates_group_p (next_insn, previous_group))
17220 if (!is_branch_slot_insn (next_insn))
17223 while (can_issue_more)
17226 emit_insn_before (nop, next_insn);
17231 can_issue_more = issue_rate;
17236 next_insn = get_next_active_insn (insn, tail);
17239 return group_count;
17242 /* The following function is called at the end of scheduling BB.
17243 After reload, it inserts nops at insn group bundling. */
17246 rs6000_sched_finish (FILE *dump, int sched_verbose)
17251 fprintf (dump, "=== Finishing schedule.\n");
17253 if (reload_completed && rs6000_sched_groups)
17255 if (rs6000_sched_insert_nops == sched_finish_none)
17258 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
17259 n_groups = pad_groups (dump, sched_verbose,
17260 current_sched_info->prev_head,
17261 current_sched_info->next_tail);
17263 n_groups = redefine_groups (dump, sched_verbose,
17264 current_sched_info->prev_head,
17265 current_sched_info->next_tail);
17267 if (sched_verbose >= 6)
17269 fprintf (dump, "ngroups = %d\n", n_groups);
17270 print_rtl (dump, current_sched_info->prev_head);
17271 fprintf (dump, "Done finish_sched\n");
17276 /* Length in units of the trampoline for entering a nested function. */
17279 rs6000_trampoline_size (void)
17283 switch (DEFAULT_ABI)
17286 gcc_unreachable ();
17289 ret = (TARGET_32BIT) ? 12 : 24;
17294 ret = (TARGET_32BIT) ? 40 : 48;
17301 /* Emit RTL insns to initialize the variable parts of a trampoline.
17302 FNADDR is an RTX for the address of the function's pure code.
17303 CXT is an RTX for the static chain value for the function. */
17306 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
17308 int regsize = (TARGET_32BIT) ? 4 : 8;
17309 rtx ctx_reg = force_reg (Pmode, cxt);
17311 switch (DEFAULT_ABI)
17314 gcc_unreachable ();
17316 /* Macros to shorten the code expansions below. */
17317 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
17318 #define MEM_PLUS(addr,offset) \
17319 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
17321 /* Under AIX, just build the 3 word function descriptor */
17324 rtx fn_reg = gen_reg_rtx (Pmode);
17325 rtx toc_reg = gen_reg_rtx (Pmode);
17326 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
17327 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
17328 emit_move_insn (MEM_DEREF (addr), fn_reg);
17329 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
17330 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
17334 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
17337 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
17338 FALSE, VOIDmode, 4,
17340 GEN_INT (rs6000_trampoline_size ()), SImode,
17350 /* Table of valid machine attributes. */
17352 const struct attribute_spec rs6000_attribute_table[] =
17354 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
17355 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
17356 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17357 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17358 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
17359 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
17360 #ifdef SUBTARGET_ATTRIBUTE_TABLE
17361 SUBTARGET_ATTRIBUTE_TABLE,
17363 { NULL, 0, 0, false, false, false, NULL }
17366 /* Handle the "altivec" attribute. The attribute may have
17367 arguments as follows:
17369 __attribute__((altivec(vector__)))
17370 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
17371 __attribute__((altivec(bool__))) (always followed by 'unsigned')
17373 and may appear more than once (e.g., 'vector bool char') in a
17374 given declaration. */
17377 rs6000_handle_altivec_attribute (tree *node,
17378 tree name ATTRIBUTE_UNUSED,
17380 int flags ATTRIBUTE_UNUSED,
17381 bool *no_add_attrs)
17383 tree type = *node, result = NULL_TREE;
17384 enum machine_mode mode;
17387 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
17388 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
17389 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
17392 while (POINTER_TYPE_P (type)
17393 || TREE_CODE (type) == FUNCTION_TYPE
17394 || TREE_CODE (type) == METHOD_TYPE
17395 || TREE_CODE (type) == ARRAY_TYPE)
17396 type = TREE_TYPE (type);
17398 mode = TYPE_MODE (type);
17400 /* Check for invalid AltiVec type qualifiers. */
17401 if (type == long_unsigned_type_node || type == long_integer_type_node)
17404 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
17405 else if (rs6000_warn_altivec_long)
17406 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
17408 else if (type == long_long_unsigned_type_node
17409 || type == long_long_integer_type_node)
17410 error ("use of %<long long%> in AltiVec types is invalid");
17411 else if (type == double_type_node)
17412 error ("use of %<double%> in AltiVec types is invalid");
17413 else if (type == long_double_type_node)
17414 error ("use of %<long double%> in AltiVec types is invalid");
17415 else if (type == boolean_type_node)
17416 error ("use of boolean types in AltiVec types is invalid");
17417 else if (TREE_CODE (type) == COMPLEX_TYPE)
17418 error ("use of %<complex%> in AltiVec types is invalid");
17419 else if (DECIMAL_FLOAT_MODE_P (mode))
17420 error ("use of decimal floating point types in AltiVec types is invalid");
17422 switch (altivec_type)
17425 unsigned_p = TYPE_UNSIGNED (type);
17429 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
17432 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
17435 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
17437 case SFmode: result = V4SF_type_node; break;
17438 /* If the user says 'vector int bool', we may be handed the 'bool'
17439 attribute _before_ the 'vector' attribute, and so select the
17440 proper type in the 'b' case below. */
17441 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
17449 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
17450 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
17451 case QImode: case V16QImode: result = bool_V16QI_type_node;
17458 case V8HImode: result = pixel_V8HI_type_node;
17464 if (result && result != type && TYPE_READONLY (type))
17465 result = build_qualified_type (result, TYPE_QUAL_CONST);
17467 *no_add_attrs = true; /* No need to hang on to the attribute. */
17470 *node = reconstruct_complex_type (*node, result);
17475 /* AltiVec defines four built-in scalar types that serve as vector
17476 elements; we must teach the compiler how to mangle them. */
17478 static const char *
17479 rs6000_mangle_fundamental_type (tree type)
17481 if (type == bool_char_type_node) return "U6__boolc";
17482 if (type == bool_short_type_node) return "U6__bools";
17483 if (type == pixel_type_node) return "u7__pixel";
17484 if (type == bool_int_type_node) return "U6__booli";
17486 /* Mangle IBM extended float long double as `g' (__float128) on
17487 powerpc*-linux where long-double-64 previously was the default. */
17488 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
17490 && TARGET_LONG_DOUBLE_128
17491 && !TARGET_IEEEQUAD)
17494 /* For all other types, use normal C++ mangling. */
17498 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17499 struct attribute_spec.handler. */
17502 rs6000_handle_longcall_attribute (tree *node, tree name,
17503 tree args ATTRIBUTE_UNUSED,
17504 int flags ATTRIBUTE_UNUSED,
17505 bool *no_add_attrs)
17507 if (TREE_CODE (*node) != FUNCTION_TYPE
17508 && TREE_CODE (*node) != FIELD_DECL
17509 && TREE_CODE (*node) != TYPE_DECL)
17511 warning (OPT_Wattributes, "%qs attribute only applies to functions",
17512 IDENTIFIER_POINTER (name));
17513 *no_add_attrs = true;
17519 /* Set longcall attributes on all functions declared when
17520 rs6000_default_long_calls is true. */
17522 rs6000_set_default_type_attributes (tree type)
17524 if (rs6000_default_long_calls
17525 && (TREE_CODE (type) == FUNCTION_TYPE
17526 || TREE_CODE (type) == METHOD_TYPE))
17527 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
17529 TYPE_ATTRIBUTES (type));
17532 darwin_set_default_type_attributes (type);
17536 /* Return a reference suitable for calling a function with the
17537 longcall attribute. */
17540 rs6000_longcall_ref (rtx call_ref)
17542 const char *call_name;
17545 if (GET_CODE (call_ref) != SYMBOL_REF)
17548 /* System V adds '.' to the internal name, so skip them. */
17549 call_name = XSTR (call_ref, 0);
17550 if (*call_name == '.')
17552 while (*call_name == '.')
17555 node = get_identifier (call_name);
17556 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
17559 return force_reg (Pmode, call_ref);
17562 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
17563 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
17566 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
17567 struct attribute_spec.handler. */
17569 rs6000_handle_struct_attribute (tree *node, tree name,
17570 tree args ATTRIBUTE_UNUSED,
17571 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
17574 if (DECL_P (*node))
17576 if (TREE_CODE (*node) == TYPE_DECL)
17577 type = &TREE_TYPE (*node);
17582 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
17583 || TREE_CODE (*type) == UNION_TYPE)))
17585 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
17586 *no_add_attrs = true;
17589 else if ((is_attribute_p ("ms_struct", name)
17590 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
17591 || ((is_attribute_p ("gcc_struct", name)
17592 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
17594 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
17595 IDENTIFIER_POINTER (name));
17596 *no_add_attrs = true;
17603 rs6000_ms_bitfield_layout_p (tree record_type)
17605 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
17606 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
17607 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
17610 #ifdef USING_ELFOS_H
17612 /* A get_unnamed_section callback, used for switching to toc_section. */
17615 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
17617 if (DEFAULT_ABI == ABI_AIX
17618 && TARGET_MINIMAL_TOC
17619 && !TARGET_RELOCATABLE)
17621 if (!toc_initialized)
17623 toc_initialized = 1;
17624 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17625 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
17626 fprintf (asm_out_file, "\t.tc ");
17627 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
17628 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17629 fprintf (asm_out_file, "\n");
17631 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17632 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17633 fprintf (asm_out_file, " = .+32768\n");
17636 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17638 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
17639 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17642 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17643 if (!toc_initialized)
17645 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17646 fprintf (asm_out_file, " = .+32768\n");
17647 toc_initialized = 1;
17652 /* Implement TARGET_ASM_INIT_SECTIONS. */
17655 rs6000_elf_asm_init_sections (void)
17658 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
17661 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
17662 SDATA2_SECTION_ASM_OP);
17665 /* Implement TARGET_SELECT_RTX_SECTION. */
17668 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
17669 unsigned HOST_WIDE_INT align)
17671 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17672 return toc_section;
17674 return default_elf_select_rtx_section (mode, x, align);
17677 /* Implement TARGET_ASM_SELECT_SECTION for ELF targets. */
17680 rs6000_elf_select_section (tree decl, int reloc,
17681 unsigned HOST_WIDE_INT align)
17683 /* Pretend that we're always building for a shared library when
17684 ABI_AIX, because otherwise we end up with dynamic relocations
17685 in read-only sections. This happens for function pointers,
17686 references to vtables in typeinfo, and probably other cases. */
17687 return default_elf_select_section_1 (decl, reloc, align,
17688 flag_pic || DEFAULT_ABI == ABI_AIX);
17691 /* A C statement to build up a unique section name, expressed as a
17692 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17693 RELOC indicates whether the initial value of EXP requires
17694 link-time relocations. If you do not define this macro, GCC will use
17695 the symbol name prefixed by `.' as the section name. Note - this
17696 macro can now be called for uninitialized data items as well as
17697 initialized data and functions. */
17700 rs6000_elf_unique_section (tree decl, int reloc)
17702 /* As above, pretend that we're always building for a shared library
17703 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
17704 default_unique_section_1 (decl, reloc,
17705 flag_pic || DEFAULT_ABI == ABI_AIX);
17708 /* For a SYMBOL_REF, set generic flags and then perform some
17709 target-specific processing.
17711 When the AIX ABI is requested on a non-AIX system, replace the
17712 function name with the real name (with a leading .) rather than the
17713 function descriptor name. This saves a lot of overriding code to
17714 read the prefixes. */
17717 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
17719 default_encode_section_info (decl, rtl, first);
17722 && TREE_CODE (decl) == FUNCTION_DECL
17724 && DEFAULT_ABI == ABI_AIX)
17726 rtx sym_ref = XEXP (rtl, 0);
17727 size_t len = strlen (XSTR (sym_ref, 0));
17728 char *str = alloca (len + 2);
17730 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
17731 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
17736 rs6000_elf_in_small_data_p (tree decl)
17738 if (rs6000_sdata == SDATA_NONE)
17741 /* We want to merge strings, so we never consider them small data. */
17742 if (TREE_CODE (decl) == STRING_CST)
17745 /* Functions are never in the small data area. */
17746 if (TREE_CODE (decl) == FUNCTION_DECL)
17749 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
17751 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
17752 if (strcmp (section, ".sdata") == 0
17753 || strcmp (section, ".sdata2") == 0
17754 || strcmp (section, ".sbss") == 0
17755 || strcmp (section, ".sbss2") == 0
17756 || strcmp (section, ".PPC.EMB.sdata0") == 0
17757 || strcmp (section, ".PPC.EMB.sbss0") == 0)
17762 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
17765 && (unsigned HOST_WIDE_INT) size <= g_switch_value
17766 /* If it's not public, and we're not going to reference it there,
17767 there's no need to put it in the small data section. */
17768 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
17775 #endif /* USING_ELFOS_H */
17777 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
17780 rs6000_use_blocks_for_constant_p (enum machine_mode mode, rtx x)
17782 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
17785 /* Return a REG that occurs in ADDR with coefficient 1.
17786 ADDR can be effectively incremented by incrementing REG.
17788 r0 is special and we must not select it as an address
17789 register by this routine since our caller will try to
17790 increment the returned register via an "la" instruction. */
17793 find_addr_reg (rtx addr)
17795 while (GET_CODE (addr) == PLUS)
17797 if (GET_CODE (XEXP (addr, 0)) == REG
17798 && REGNO (XEXP (addr, 0)) != 0)
17799 addr = XEXP (addr, 0);
17800 else if (GET_CODE (XEXP (addr, 1)) == REG
17801 && REGNO (XEXP (addr, 1)) != 0)
17802 addr = XEXP (addr, 1);
17803 else if (CONSTANT_P (XEXP (addr, 0)))
17804 addr = XEXP (addr, 1);
17805 else if (CONSTANT_P (XEXP (addr, 1)))
17806 addr = XEXP (addr, 0);
17808 gcc_unreachable ();
17810 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
17815 rs6000_fatal_bad_address (rtx op)
17817 fatal_insn ("bad address", op);
17822 static tree branch_island_list = 0;
17824 /* Remember to generate a branch island for far calls to the given
17828 add_compiler_branch_island (tree label_name, tree function_name,
17831 tree branch_island = build_tree_list (function_name, label_name);
17832 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
17833 TREE_CHAIN (branch_island) = branch_island_list;
17834 branch_island_list = branch_island;
17837 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17838 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17839 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17840 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17842 /* Generate far-jump branch islands for everything on the
17843 branch_island_list. Invoked immediately after the last instruction
17844 of the epilogue has been emitted; the branch-islands must be
17845 appended to, and contiguous with, the function body. Mach-O stubs
17846 are generated in machopic_output_stub(). */
17849 macho_branch_islands (void)
17852 tree branch_island;
17854 for (branch_island = branch_island_list;
17856 branch_island = TREE_CHAIN (branch_island))
17858 const char *label =
17859 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
17861 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
17862 char name_buf[512];
17863 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17864 if (name[0] == '*' || name[0] == '&')
17865 strcpy (name_buf, name+1);
17869 strcpy (name_buf+1, name);
17871 strcpy (tmp_buf, "\n");
17872 strcat (tmp_buf, label);
17873 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17874 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17875 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17876 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17879 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
17880 strcat (tmp_buf, label);
17881 strcat (tmp_buf, "_pic\n");
17882 strcat (tmp_buf, label);
17883 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
17885 strcat (tmp_buf, "\taddis r11,r11,ha16(");
17886 strcat (tmp_buf, name_buf);
17887 strcat (tmp_buf, " - ");
17888 strcat (tmp_buf, label);
17889 strcat (tmp_buf, "_pic)\n");
17891 strcat (tmp_buf, "\tmtlr r0\n");
17893 strcat (tmp_buf, "\taddi r12,r11,lo16(");
17894 strcat (tmp_buf, name_buf);
17895 strcat (tmp_buf, " - ");
17896 strcat (tmp_buf, label);
17897 strcat (tmp_buf, "_pic)\n");
17899 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
17903 strcat (tmp_buf, ":\nlis r12,hi16(");
17904 strcat (tmp_buf, name_buf);
17905 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
17906 strcat (tmp_buf, name_buf);
17907 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
17909 output_asm_insn (tmp_buf, 0);
17910 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17911 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17912 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17913 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17916 branch_island_list = 0;
17919 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17920 already there or not. */
17923 no_previous_def (tree function_name)
17925 tree branch_island;
17926 for (branch_island = branch_island_list;
17928 branch_island = TREE_CHAIN (branch_island))
17929 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17934 /* GET_PREV_LABEL gets the label name from the previous definition of
17938 get_prev_label (tree function_name)
17940 tree branch_island;
17941 for (branch_island = branch_island_list;
17943 branch_island = TREE_CHAIN (branch_island))
17944 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17945 return BRANCH_ISLAND_LABEL_NAME (branch_island);
17949 /* INSN is either a function call or a millicode call. It may have an
17950 unconditional jump in its delay slot.
17952 CALL_DEST is the routine we are calling. */
17955 output_call (rtx insn, rtx *operands, int dest_operand_number,
17956 int cookie_operand_number)
17958 static char buf[256];
17959 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
17960 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
17963 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
17965 if (no_previous_def (funname))
17967 int line_number = 0;
17968 rtx label_rtx = gen_label_rtx ();
17969 char *label_buf, temp_buf[256];
17970 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
17971 CODE_LABEL_NUMBER (label_rtx));
17972 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
17973 labelname = get_identifier (label_buf);
17974 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
17976 line_number = NOTE_LINE_NUMBER (insn);
17977 add_compiler_branch_island (labelname, funname, line_number);
17980 labelname = get_prev_label (funname);
17982 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17983 instruction will reach 'foo', otherwise link as 'bl L42'".
17984 "L42" should be a 'branch island', that will do a far jump to
17985 'foo'. Branch islands are generated in
17986 macho_branch_islands(). */
17987 sprintf (buf, "jbsr %%z%d,%.246s",
17988 dest_operand_number, IDENTIFIER_POINTER (labelname));
17991 sprintf (buf, "bl %%z%d", dest_operand_number);
17995 /* Generate PIC and indirect symbol stubs. */
17998 machopic_output_stub (FILE *file, const char *symb, const char *stub)
18000 unsigned int length;
18001 char *symbol_name, *lazy_ptr_name;
18002 char *local_label_0;
18003 static int label = 0;
18005 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
18006 symb = (*targetm.strip_name_encoding) (symb);
18009 length = strlen (symb);
18010 symbol_name = alloca (length + 32);
18011 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
18013 lazy_ptr_name = alloca (length + 32);
18014 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
18017 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
18019 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
18023 fprintf (file, "\t.align 5\n");
18025 fprintf (file, "%s:\n", stub);
18026 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
18029 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
18030 sprintf (local_label_0, "\"L%011d$spb\"", label);
18032 fprintf (file, "\tmflr r0\n");
18033 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
18034 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
18035 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
18036 lazy_ptr_name, local_label_0);
18037 fprintf (file, "\tmtlr r0\n");
18038 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
18039 (TARGET_64BIT ? "ldu" : "lwzu"),
18040 lazy_ptr_name, local_label_0);
18041 fprintf (file, "\tmtctr r12\n");
18042 fprintf (file, "\tbctr\n");
18046 fprintf (file, "\t.align 4\n");
18048 fprintf (file, "%s:\n", stub);
18049 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
18051 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
18052 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
18053 (TARGET_64BIT ? "ldu" : "lwzu"),
18055 fprintf (file, "\tmtctr r12\n");
18056 fprintf (file, "\tbctr\n");
18059 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
18060 fprintf (file, "%s:\n", lazy_ptr_name);
18061 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
18062 fprintf (file, "%sdyld_stub_binding_helper\n",
18063 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
18066 /* Legitimize PIC addresses. If the address is already
18067 position-independent, we return ORIG. Newly generated
18068 position-independent addresses go into a reg. This is REG if non
18069 zero, otherwise we allocate register(s) as necessary. */
18071 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
18074 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
18079 if (reg == NULL && ! reload_in_progress && ! reload_completed)
18080 reg = gen_reg_rtx (Pmode);
18082 if (GET_CODE (orig) == CONST)
18086 if (GET_CODE (XEXP (orig, 0)) == PLUS
18087 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
18090 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
18092 /* Use a different reg for the intermediate value, as
18093 it will be marked UNCHANGING. */
18094 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
18095 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
18098 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
18101 if (GET_CODE (offset) == CONST_INT)
18103 if (SMALL_INT (offset))
18104 return plus_constant (base, INTVAL (offset));
18105 else if (! reload_in_progress && ! reload_completed)
18106 offset = force_reg (Pmode, offset);
18109 rtx mem = force_const_mem (Pmode, orig);
18110 return machopic_legitimize_pic_address (mem, Pmode, reg);
18113 return gen_rtx_PLUS (Pmode, base, offset);
18116 /* Fall back on generic machopic code. */
18117 return machopic_legitimize_pic_address (orig, mode, reg);
18120 /* Output a .machine directive for the Darwin assembler, and call
18121 the generic start_file routine. */
18124 rs6000_darwin_file_start (void)
18126 static const struct
18132 { "ppc64", "ppc64", MASK_64BIT },
18133 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
18134 { "power4", "ppc970", 0 },
18135 { "G5", "ppc970", 0 },
18136 { "7450", "ppc7450", 0 },
18137 { "7400", "ppc7400", MASK_ALTIVEC },
18138 { "G4", "ppc7400", 0 },
18139 { "750", "ppc750", 0 },
18140 { "740", "ppc750", 0 },
18141 { "G3", "ppc750", 0 },
18142 { "604e", "ppc604e", 0 },
18143 { "604", "ppc604", 0 },
18144 { "603e", "ppc603", 0 },
18145 { "603", "ppc603", 0 },
18146 { "601", "ppc601", 0 },
18147 { NULL, "ppc", 0 } };
18148 const char *cpu_id = "";
18151 rs6000_file_start ();
18152 darwin_file_start ();
18154 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
18155 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
18156 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
18157 && rs6000_select[i].string[0] != '\0')
18158 cpu_id = rs6000_select[i].string;
18160 /* Look through the mapping array. Pick the first name that either
18161 matches the argument, has a bit set in IF_SET that is also set
18162 in the target flags, or has a NULL name. */
18165 while (mapping[i].arg != NULL
18166 && strcmp (mapping[i].arg, cpu_id) != 0
18167 && (mapping[i].if_set & target_flags) == 0)
18170 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
18173 #endif /* TARGET_MACHO */
18176 static unsigned int
18177 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
18179 return default_section_type_flags_1 (decl, name, reloc,
18180 flag_pic || DEFAULT_ABI == ABI_AIX);
18183 /* Record an element in the table of global constructors. SYMBOL is
18184 a SYMBOL_REF of the function to be called; PRIORITY is a number
18185 between 0 and MAX_INIT_PRIORITY.
18187 This differs from default_named_section_asm_out_constructor in
18188 that we have special handling for -mrelocatable. */
18191 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
18193 const char *section = ".ctors";
18196 if (priority != DEFAULT_INIT_PRIORITY)
18198 sprintf (buf, ".ctors.%.5u",
18199 /* Invert the numbering so the linker puts us in the proper
18200 order; constructors are run from right to left, and the
18201 linker sorts in increasing order. */
18202 MAX_INIT_PRIORITY - priority);
18206 switch_to_section (get_section (section, SECTION_WRITE, NULL));
18207 assemble_align (POINTER_SIZE);
18209 if (TARGET_RELOCATABLE)
18211 fputs ("\t.long (", asm_out_file);
18212 output_addr_const (asm_out_file, symbol);
18213 fputs (")@fixup\n", asm_out_file);
18216 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
18220 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
18222 const char *section = ".dtors";
18225 if (priority != DEFAULT_INIT_PRIORITY)
18227 sprintf (buf, ".dtors.%.5u",
18228 /* Invert the numbering so the linker puts us in the proper
18229 order; constructors are run from right to left, and the
18230 linker sorts in increasing order. */
18231 MAX_INIT_PRIORITY - priority);
18235 switch_to_section (get_section (section, SECTION_WRITE, NULL));
18236 assemble_align (POINTER_SIZE);
18238 if (TARGET_RELOCATABLE)
18240 fputs ("\t.long (", asm_out_file);
18241 output_addr_const (asm_out_file, symbol);
18242 fputs (")@fixup\n", asm_out_file);
18245 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
18249 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
18253 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
18254 ASM_OUTPUT_LABEL (file, name);
18255 fputs (DOUBLE_INT_ASM_OP, file);
18256 rs6000_output_function_entry (file, name);
18257 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
18260 fputs ("\t.size\t", file);
18261 assemble_name (file, name);
18262 fputs (",24\n\t.type\t.", file);
18263 assemble_name (file, name);
18264 fputs (",@function\n", file);
18265 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
18267 fputs ("\t.globl\t.", file);
18268 assemble_name (file, name);
18273 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18274 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18275 rs6000_output_function_entry (file, name);
18276 fputs (":\n", file);
18280 if (TARGET_RELOCATABLE
18281 && !TARGET_SECURE_PLT
18282 && (get_pool_size () != 0 || current_function_profile)
18287 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
18289 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
18290 fprintf (file, "\t.long ");
18291 assemble_name (file, buf);
18293 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
18294 assemble_name (file, buf);
18298 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18299 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18301 if (DEFAULT_ABI == ABI_AIX)
18303 const char *desc_name, *orig_name;
18305 orig_name = (*targetm.strip_name_encoding) (name);
18306 desc_name = orig_name;
18307 while (*desc_name == '.')
18310 if (TREE_PUBLIC (decl))
18311 fprintf (file, "\t.globl %s\n", desc_name);
18313 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18314 fprintf (file, "%s:\n", desc_name);
18315 fprintf (file, "\t.long %s\n", orig_name);
18316 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
18317 if (DEFAULT_ABI == ABI_AIX)
18318 fputs ("\t.long 0\n", file);
18319 fprintf (file, "\t.previous\n");
18321 ASM_OUTPUT_LABEL (file, name);
18325 rs6000_elf_end_indicate_exec_stack (void)
18328 file_end_indicate_exec_stack ();
18334 rs6000_xcoff_asm_output_anchor (rtx symbol)
18338 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
18339 SYMBOL_REF_BLOCK_OFFSET (symbol));
18340 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
18344 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
18346 fputs (GLOBAL_ASM_OP, stream);
18347 RS6000_OUTPUT_BASENAME (stream, name);
18348 putc ('\n', stream);
18351 /* A get_unnamed_decl callback, used for read-only sections. PTR
18352 points to the section string variable. */
18355 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
18357 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
18358 *(const char *const *) directive);
18361 /* Likewise for read-write sections. */
18364 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
18366 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
18367 *(const char *const *) directive);
18370 /* A get_unnamed_section callback, used for switching to toc_section. */
18373 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
18375 if (TARGET_MINIMAL_TOC)
18377 /* toc_section is always selected at least once from
18378 rs6000_xcoff_file_start, so this is guaranteed to
18379 always be defined once and only once in each file. */
18380 if (!toc_initialized)
18382 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
18383 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
18384 toc_initialized = 1;
18386 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
18387 (TARGET_32BIT ? "" : ",3"));
18390 fputs ("\t.toc\n", asm_out_file);
18393 /* Implement TARGET_ASM_INIT_SECTIONS. */
18396 rs6000_xcoff_asm_init_sections (void)
18398 read_only_data_section
18399 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18400 &xcoff_read_only_section_name);
18402 private_data_section
18403 = get_unnamed_section (SECTION_WRITE,
18404 rs6000_xcoff_output_readwrite_section_asm_op,
18405 &xcoff_private_data_section_name);
18407 read_only_private_data_section
18408 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18409 &xcoff_private_data_section_name);
18412 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
18414 readonly_data_section = read_only_data_section;
18415 exception_section = data_section;
18419 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
18420 tree decl ATTRIBUTE_UNUSED)
18423 static const char * const suffix[3] = { "PR", "RO", "RW" };
18425 if (flags & SECTION_CODE)
18427 else if (flags & SECTION_WRITE)
18432 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
18433 (flags & SECTION_CODE) ? "." : "",
18434 name, suffix[smclass], flags & SECTION_ENTSIZE);
18438 rs6000_xcoff_select_section (tree decl, int reloc,
18439 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18441 if (decl_readonly_section_1 (decl, reloc, 1))
18443 if (TREE_PUBLIC (decl))
18444 return read_only_data_section;
18446 return read_only_private_data_section;
18450 if (TREE_PUBLIC (decl))
18451 return data_section;
18453 return private_data_section;
18458 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
18462 /* Use select_section for private and uninitialized data. */
18463 if (!TREE_PUBLIC (decl)
18464 || DECL_COMMON (decl)
18465 || DECL_INITIAL (decl) == NULL_TREE
18466 || DECL_INITIAL (decl) == error_mark_node
18467 || (flag_zero_initialized_in_bss
18468 && initializer_zerop (DECL_INITIAL (decl))))
18471 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
18472 name = (*targetm.strip_name_encoding) (name);
18473 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
18476 /* Select section for constant in constant pool.
18478 On RS/6000, all constants are in the private read-only data area.
18479 However, if this is being placed in the TOC it must be output as a
18483 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
18484 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18486 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
18487 return toc_section;
18489 return read_only_private_data_section;
18492 /* Remove any trailing [DS] or the like from the symbol name. */
18494 static const char *
18495 rs6000_xcoff_strip_name_encoding (const char *name)
18500 len = strlen (name);
18501 if (name[len - 1] == ']')
18502 return ggc_alloc_string (name, len - 4);
18507 /* Section attributes. AIX is always PIC. */
18509 static unsigned int
18510 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
18512 unsigned int align;
18513 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
18515 /* Align to at least UNIT size. */
18516 if (flags & SECTION_CODE)
18517 align = MIN_UNITS_PER_WORD;
18519 /* Increase alignment of large objects if not already stricter. */
18520 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
18521 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
18522 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
18524 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
18527 /* Output at beginning of assembler file.
18529 Initialize the section names for the RS/6000 at this point.
18531 Specify filename, including full path, to assembler.
18533 We want to go into the TOC section so at least one .toc will be emitted.
18534 Also, in order to output proper .bs/.es pairs, we need at least one static
18535 [RW] section emitted.
18537 Finally, declare mcount when profiling to make the assembler happy. */
18540 rs6000_xcoff_file_start (void)
18542 rs6000_gen_section_name (&xcoff_bss_section_name,
18543 main_input_filename, ".bss_");
18544 rs6000_gen_section_name (&xcoff_private_data_section_name,
18545 main_input_filename, ".rw_");
18546 rs6000_gen_section_name (&xcoff_read_only_section_name,
18547 main_input_filename, ".ro_");
18549 fputs ("\t.file\t", asm_out_file);
18550 output_quoted_string (asm_out_file, main_input_filename);
18551 fputc ('\n', asm_out_file);
18552 if (write_symbols != NO_DEBUG)
18553 switch_to_section (private_data_section);
18554 switch_to_section (text_section);
18556 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
18557 rs6000_file_start ();
18560 /* Output at end of assembler file.
18561 On the RS/6000, referencing data should automatically pull in text. */
18564 rs6000_xcoff_file_end (void)
18566 switch_to_section (text_section);
18567 fputs ("_section_.text:\n", asm_out_file);
18568 switch_to_section (data_section);
18569 fputs (TARGET_32BIT
18570 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
18573 #endif /* TARGET_XCOFF */
18575 /* Compute a (partial) cost for rtx X. Return true if the complete
18576 cost has been computed, and false if subexpressions should be
18577 scanned. In either case, *TOTAL contains the cost result. */
18580 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
18582 enum machine_mode mode = GET_MODE (x);
18586 /* On the RS/6000, if it is valid in the insn, it is free. */
18588 if (((outer_code == SET
18589 || outer_code == PLUS
18590 || outer_code == MINUS)
18591 && (satisfies_constraint_I (x)
18592 || satisfies_constraint_L (x)))
18593 || (outer_code == AND
18594 && (satisfies_constraint_K (x)
18596 ? satisfies_constraint_L (x)
18597 : satisfies_constraint_J (x))
18598 || mask_operand (x, mode)
18600 && mask64_operand (x, DImode))))
18601 || ((outer_code == IOR || outer_code == XOR)
18602 && (satisfies_constraint_K (x)
18604 ? satisfies_constraint_L (x)
18605 : satisfies_constraint_J (x))))
18606 || outer_code == ASHIFT
18607 || outer_code == ASHIFTRT
18608 || outer_code == LSHIFTRT
18609 || outer_code == ROTATE
18610 || outer_code == ROTATERT
18611 || outer_code == ZERO_EXTRACT
18612 || (outer_code == MULT
18613 && satisfies_constraint_I (x))
18614 || ((outer_code == DIV || outer_code == UDIV
18615 || outer_code == MOD || outer_code == UMOD)
18616 && exact_log2 (INTVAL (x)) >= 0)
18617 || (outer_code == COMPARE
18618 && (satisfies_constraint_I (x)
18619 || satisfies_constraint_K (x)))
18620 || (outer_code == EQ
18621 && (satisfies_constraint_I (x)
18622 || satisfies_constraint_K (x)
18624 ? satisfies_constraint_L (x)
18625 : satisfies_constraint_J (x))))
18626 || (outer_code == GTU
18627 && satisfies_constraint_I (x))
18628 || (outer_code == LTU
18629 && satisfies_constraint_P (x)))
18634 else if ((outer_code == PLUS
18635 && reg_or_add_cint_operand (x, VOIDmode))
18636 || (outer_code == MINUS
18637 && reg_or_sub_cint_operand (x, VOIDmode))
18638 || ((outer_code == SET
18639 || outer_code == IOR
18640 || outer_code == XOR)
18642 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
18644 *total = COSTS_N_INSNS (1);
18650 if (mode == DImode && code == CONST_DOUBLE)
18652 if ((outer_code == IOR || outer_code == XOR)
18653 && CONST_DOUBLE_HIGH (x) == 0
18654 && (CONST_DOUBLE_LOW (x)
18655 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
18660 else if ((outer_code == AND && and64_2_operand (x, DImode))
18661 || ((outer_code == SET
18662 || outer_code == IOR
18663 || outer_code == XOR)
18664 && CONST_DOUBLE_HIGH (x) == 0))
18666 *total = COSTS_N_INSNS (1);
18676 /* When optimizing for size, MEM should be slightly more expensive
18677 than generating address, e.g., (plus (reg) (const)).
18678 L1 cache latency is about two instructions. */
18679 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18687 if (mode == DFmode)
18689 if (GET_CODE (XEXP (x, 0)) == MULT)
18691 /* FNMA accounted in outer NEG. */
18692 if (outer_code == NEG)
18693 *total = rs6000_cost->dmul - rs6000_cost->fp;
18695 *total = rs6000_cost->dmul;
18698 *total = rs6000_cost->fp;
18700 else if (mode == SFmode)
18702 /* FNMA accounted in outer NEG. */
18703 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18706 *total = rs6000_cost->fp;
18709 *total = COSTS_N_INSNS (1);
18713 if (mode == DFmode)
18715 if (GET_CODE (XEXP (x, 0)) == MULT)
18717 /* FNMA accounted in outer NEG. */
18718 if (outer_code == NEG)
18721 *total = rs6000_cost->dmul;
18724 *total = rs6000_cost->fp;
18726 else if (mode == SFmode)
18728 /* FNMA accounted in outer NEG. */
18729 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18732 *total = rs6000_cost->fp;
18735 *total = COSTS_N_INSNS (1);
18739 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18740 && satisfies_constraint_I (XEXP (x, 1)))
18742 if (INTVAL (XEXP (x, 1)) >= -256
18743 && INTVAL (XEXP (x, 1)) <= 255)
18744 *total = rs6000_cost->mulsi_const9;
18746 *total = rs6000_cost->mulsi_const;
18748 /* FMA accounted in outer PLUS/MINUS. */
18749 else if ((mode == DFmode || mode == SFmode)
18750 && (outer_code == PLUS || outer_code == MINUS))
18752 else if (mode == DFmode)
18753 *total = rs6000_cost->dmul;
18754 else if (mode == SFmode)
18755 *total = rs6000_cost->fp;
18756 else if (mode == DImode)
18757 *total = rs6000_cost->muldi;
18759 *total = rs6000_cost->mulsi;
18764 if (FLOAT_MODE_P (mode))
18766 *total = mode == DFmode ? rs6000_cost->ddiv
18767 : rs6000_cost->sdiv;
18774 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18775 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
18777 if (code == DIV || code == MOD)
18779 *total = COSTS_N_INSNS (2);
18782 *total = COSTS_N_INSNS (1);
18786 if (GET_MODE (XEXP (x, 1)) == DImode)
18787 *total = rs6000_cost->divdi;
18789 *total = rs6000_cost->divsi;
18791 /* Add in shift and subtract for MOD. */
18792 if (code == MOD || code == UMOD)
18793 *total += COSTS_N_INSNS (2);
18797 *total = COSTS_N_INSNS (4);
18801 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
18812 *total = COSTS_N_INSNS (1);
18820 /* Handle mul_highpart. */
18821 if (outer_code == TRUNCATE
18822 && GET_CODE (XEXP (x, 0)) == MULT)
18824 if (mode == DImode)
18825 *total = rs6000_cost->muldi;
18827 *total = rs6000_cost->mulsi;
18830 else if (outer_code == AND)
18833 *total = COSTS_N_INSNS (1);
18838 if (GET_CODE (XEXP (x, 0)) == MEM)
18841 *total = COSTS_N_INSNS (1);
18847 if (!FLOAT_MODE_P (mode))
18849 *total = COSTS_N_INSNS (1);
18855 case UNSIGNED_FLOAT:
18858 case FLOAT_TRUNCATE:
18859 *total = rs6000_cost->fp;
18863 if (mode == DFmode)
18866 *total = rs6000_cost->fp;
18870 switch (XINT (x, 1))
18873 *total = rs6000_cost->fp;
18885 *total = COSTS_N_INSNS (1);
18888 else if (FLOAT_MODE_P (mode)
18889 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
18891 *total = rs6000_cost->fp;
18899 /* Carry bit requires mode == Pmode.
18900 NEG or PLUS already counted so only add one. */
18902 && (outer_code == NEG || outer_code == PLUS))
18904 *total = COSTS_N_INSNS (1);
18907 if (outer_code == SET)
18909 if (XEXP (x, 1) == const0_rtx)
18911 *total = COSTS_N_INSNS (2);
18914 else if (mode == Pmode)
18916 *total = COSTS_N_INSNS (3);
18925 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
18927 *total = COSTS_N_INSNS (2);
18931 if (outer_code == COMPARE)
18945 /* A C expression returning the cost of moving data from a register of class
18946 CLASS1 to one of CLASS2. */
18949 rs6000_register_move_cost (enum machine_mode mode,
18950 enum reg_class from, enum reg_class to)
18952 /* Moves from/to GENERAL_REGS. */
18953 if (reg_classes_intersect_p (to, GENERAL_REGS)
18954 || reg_classes_intersect_p (from, GENERAL_REGS))
18956 if (! reg_classes_intersect_p (to, GENERAL_REGS))
18959 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
18960 return (rs6000_memory_move_cost (mode, from, 0)
18961 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
18963 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18965 else if (from == CR_REGS)
18969 /* A move will cost one instruction per GPR moved. */
18970 return 2 * hard_regno_nregs[0][mode];
18973 /* Moving between two similar registers is just one instruction. */
18974 else if (reg_classes_intersect_p (to, from))
18975 return mode == TFmode ? 4 : 2;
18977 /* Everything else has to go through GENERAL_REGS. */
18979 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
18980 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
18983 /* A C expressions returning the cost of moving data of MODE from a register to
18987 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
18988 int in ATTRIBUTE_UNUSED)
18990 if (reg_classes_intersect_p (class, GENERAL_REGS))
18991 return 4 * hard_regno_nregs[0][mode];
18992 else if (reg_classes_intersect_p (class, FLOAT_REGS))
18993 return 4 * hard_regno_nregs[32][mode];
18994 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
18995 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
18997 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
19000 /* Newton-Raphson approximation of single-precision floating point divide n/d.
19001 Assumes no trapping math and finite arguments. */
19004 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
19006 rtx x0, e0, e1, y1, u0, v0, one;
19008 x0 = gen_reg_rtx (SFmode);
19009 e0 = gen_reg_rtx (SFmode);
19010 e1 = gen_reg_rtx (SFmode);
19011 y1 = gen_reg_rtx (SFmode);
19012 u0 = gen_reg_rtx (SFmode);
19013 v0 = gen_reg_rtx (SFmode);
19014 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
19016 /* x0 = 1./d estimate */
19017 emit_insn (gen_rtx_SET (VOIDmode, x0,
19018 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
19020 /* e0 = 1. - d * x0 */
19021 emit_insn (gen_rtx_SET (VOIDmode, e0,
19022 gen_rtx_MINUS (SFmode, one,
19023 gen_rtx_MULT (SFmode, d, x0))));
19024 /* e1 = e0 + e0 * e0 */
19025 emit_insn (gen_rtx_SET (VOIDmode, e1,
19026 gen_rtx_PLUS (SFmode,
19027 gen_rtx_MULT (SFmode, e0, e0), e0)));
19028 /* y1 = x0 + e1 * x0 */
19029 emit_insn (gen_rtx_SET (VOIDmode, y1,
19030 gen_rtx_PLUS (SFmode,
19031 gen_rtx_MULT (SFmode, e1, x0), x0)));
19033 emit_insn (gen_rtx_SET (VOIDmode, u0,
19034 gen_rtx_MULT (SFmode, n, y1)));
19035 /* v0 = n - d * u0 */
19036 emit_insn (gen_rtx_SET (VOIDmode, v0,
19037 gen_rtx_MINUS (SFmode, n,
19038 gen_rtx_MULT (SFmode, d, u0))));
19039 /* res = u0 + v0 * y1 */
19040 emit_insn (gen_rtx_SET (VOIDmode, res,
19041 gen_rtx_PLUS (SFmode,
19042 gen_rtx_MULT (SFmode, v0, y1), u0)));
19045 /* Newton-Raphson approximation of double-precision floating point divide n/d.
19046 Assumes no trapping math and finite arguments. */
19049 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
19051 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
19053 x0 = gen_reg_rtx (DFmode);
19054 e0 = gen_reg_rtx (DFmode);
19055 e1 = gen_reg_rtx (DFmode);
19056 e2 = gen_reg_rtx (DFmode);
19057 y1 = gen_reg_rtx (DFmode);
19058 y2 = gen_reg_rtx (DFmode);
19059 y3 = gen_reg_rtx (DFmode);
19060 u0 = gen_reg_rtx (DFmode);
19061 v0 = gen_reg_rtx (DFmode);
19062 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
19064 /* x0 = 1./d estimate */
19065 emit_insn (gen_rtx_SET (VOIDmode, x0,
19066 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
19068 /* e0 = 1. - d * x0 */
19069 emit_insn (gen_rtx_SET (VOIDmode, e0,
19070 gen_rtx_MINUS (DFmode, one,
19071 gen_rtx_MULT (SFmode, d, x0))));
19072 /* y1 = x0 + e0 * x0 */
19073 emit_insn (gen_rtx_SET (VOIDmode, y1,
19074 gen_rtx_PLUS (DFmode,
19075 gen_rtx_MULT (DFmode, e0, x0), x0)));
19077 emit_insn (gen_rtx_SET (VOIDmode, e1,
19078 gen_rtx_MULT (DFmode, e0, e0)));
19079 /* y2 = y1 + e1 * y1 */
19080 emit_insn (gen_rtx_SET (VOIDmode, y2,
19081 gen_rtx_PLUS (DFmode,
19082 gen_rtx_MULT (DFmode, e1, y1), y1)));
19084 emit_insn (gen_rtx_SET (VOIDmode, e2,
19085 gen_rtx_MULT (DFmode, e1, e1)));
19086 /* y3 = y2 + e2 * y2 */
19087 emit_insn (gen_rtx_SET (VOIDmode, y3,
19088 gen_rtx_PLUS (DFmode,
19089 gen_rtx_MULT (DFmode, e2, y2), y2)));
19091 emit_insn (gen_rtx_SET (VOIDmode, u0,
19092 gen_rtx_MULT (DFmode, n, y3)));
19093 /* v0 = n - d * u0 */
19094 emit_insn (gen_rtx_SET (VOIDmode, v0,
19095 gen_rtx_MINUS (DFmode, n,
19096 gen_rtx_MULT (DFmode, d, u0))));
19097 /* res = u0 + v0 * y3 */
19098 emit_insn (gen_rtx_SET (VOIDmode, res,
19099 gen_rtx_PLUS (DFmode,
19100 gen_rtx_MULT (DFmode, v0, y3), u0)));
19103 /* Return an RTX representing where to find the function value of a
19104 function returning MODE. */
19106 rs6000_complex_function_value (enum machine_mode mode)
19108 unsigned int regno;
19110 enum machine_mode inner = GET_MODE_INNER (mode);
19111 unsigned int inner_bytes = GET_MODE_SIZE (inner);
19113 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
19114 regno = FP_ARG_RETURN;
19117 regno = GP_ARG_RETURN;
19119 /* 32-bit is OK since it'll go in r3/r4. */
19120 if (TARGET_32BIT && inner_bytes >= 4)
19121 return gen_rtx_REG (mode, regno);
19124 if (inner_bytes >= 8)
19125 return gen_rtx_REG (mode, regno);
19127 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
19129 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
19130 GEN_INT (inner_bytes));
19131 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
19134 /* Define how to find the value returned by a function.
19135 VALTYPE is the data type of the value (as a tree).
19136 If the precise function being called is known, FUNC is its FUNCTION_DECL;
19137 otherwise, FUNC is 0.
19139 On the SPE, both FPs and vectors are returned in r3.
19141 On RS/6000 an integer value is in r3 and a floating-point value is in
19142 fp1, unless -msoft-float. */
19145 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
19147 enum machine_mode mode;
19148 unsigned int regno;
19150 /* Special handling for structs in darwin64. */
19151 if (rs6000_darwin64_abi
19152 && TYPE_MODE (valtype) == BLKmode
19153 && TREE_CODE (valtype) == RECORD_TYPE
19154 && int_size_in_bytes (valtype) > 0)
19156 CUMULATIVE_ARGS valcum;
19160 valcum.fregno = FP_ARG_MIN_REG;
19161 valcum.vregno = ALTIVEC_ARG_MIN_REG;
19162 /* Do a trial code generation as if this were going to be passed as
19163 an argument; if any part goes in memory, we return NULL. */
19164 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
19167 /* Otherwise fall through to standard ABI rules. */
19170 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
19172 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
19173 return gen_rtx_PARALLEL (DImode,
19175 gen_rtx_EXPR_LIST (VOIDmode,
19176 gen_rtx_REG (SImode, GP_ARG_RETURN),
19178 gen_rtx_EXPR_LIST (VOIDmode,
19179 gen_rtx_REG (SImode,
19180 GP_ARG_RETURN + 1),
19183 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
19185 return gen_rtx_PARALLEL (DCmode,
19187 gen_rtx_EXPR_LIST (VOIDmode,
19188 gen_rtx_REG (SImode, GP_ARG_RETURN),
19190 gen_rtx_EXPR_LIST (VOIDmode,
19191 gen_rtx_REG (SImode,
19192 GP_ARG_RETURN + 1),
19194 gen_rtx_EXPR_LIST (VOIDmode,
19195 gen_rtx_REG (SImode,
19196 GP_ARG_RETURN + 2),
19198 gen_rtx_EXPR_LIST (VOIDmode,
19199 gen_rtx_REG (SImode,
19200 GP_ARG_RETURN + 3),
19204 if ((INTEGRAL_TYPE_P (valtype)
19205 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
19206 || POINTER_TYPE_P (valtype))
19207 mode = TARGET_32BIT ? SImode : DImode;
19209 mode = TYPE_MODE (valtype);
19211 if (DECIMAL_FLOAT_MODE_P (mode))
19212 regno = GP_ARG_RETURN;
19213 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
19214 regno = FP_ARG_RETURN;
19215 else if (TREE_CODE (valtype) == COMPLEX_TYPE
19216 && targetm.calls.split_complex_arg)
19217 return rs6000_complex_function_value (mode);
19218 else if (TREE_CODE (valtype) == VECTOR_TYPE
19219 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
19220 && ALTIVEC_VECTOR_MODE (mode))
19221 regno = ALTIVEC_ARG_RETURN;
19222 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
19223 && (mode == DFmode || mode == DCmode))
19224 return spe_build_register_parallel (mode, GP_ARG_RETURN);
19226 regno = GP_ARG_RETURN;
19228 return gen_rtx_REG (mode, regno);
19231 /* Define how to find the value returned by a library function
19232 assuming the value has mode MODE. */
19234 rs6000_libcall_value (enum machine_mode mode)
19236 unsigned int regno;
19238 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
19240 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
19241 return gen_rtx_PARALLEL (DImode,
19243 gen_rtx_EXPR_LIST (VOIDmode,
19244 gen_rtx_REG (SImode, GP_ARG_RETURN),
19246 gen_rtx_EXPR_LIST (VOIDmode,
19247 gen_rtx_REG (SImode,
19248 GP_ARG_RETURN + 1),
19252 if (DECIMAL_FLOAT_MODE_P (mode))
19253 regno = GP_ARG_RETURN;
19254 else if (SCALAR_FLOAT_MODE_P (mode)
19255 && TARGET_HARD_FLOAT && TARGET_FPRS)
19256 regno = FP_ARG_RETURN;
19257 else if (ALTIVEC_VECTOR_MODE (mode)
19258 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
19259 regno = ALTIVEC_ARG_RETURN;
19260 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
19261 return rs6000_complex_function_value (mode);
19262 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
19263 && (mode == DFmode || mode == DCmode))
19264 return spe_build_register_parallel (mode, GP_ARG_RETURN);
19266 regno = GP_ARG_RETURN;
19268 return gen_rtx_REG (mode, regno);
19271 /* Define the offset between two registers, FROM to be eliminated and its
19272 replacement TO, at the start of a routine. */
19274 rs6000_initial_elimination_offset (int from, int to)
19276 rs6000_stack_t *info = rs6000_stack_info ();
19277 HOST_WIDE_INT offset;
19279 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19280 offset = info->push_p ? 0 : -info->total_size;
19281 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19283 offset = info->push_p ? 0 : -info->total_size;
19284 if (FRAME_GROWS_DOWNWARD)
19285 offset += info->fixed_size + info->vars_size + info->parm_size;
19287 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
19288 offset = FRAME_GROWS_DOWNWARD
19289 ? info->fixed_size + info->vars_size + info->parm_size
19291 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
19292 offset = info->total_size;
19293 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19294 offset = info->push_p ? info->total_size : 0;
19295 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
19298 gcc_unreachable ();
19303 /* Return true if TYPE is a SPE or AltiVec opaque type. */
19306 rs6000_is_opaque_type (tree type)
19308 return (type == opaque_V2SI_type_node
19309 || type == opaque_V2SF_type_node
19310 || type == opaque_p_V2SI_type_node
19311 || type == opaque_V4SI_type_node);
19315 rs6000_dwarf_register_span (rtx reg)
19320 && (SPE_VECTOR_MODE (GET_MODE (reg))
19321 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
19326 regno = REGNO (reg);
19328 /* The duality of the SPE register size wreaks all kinds of havoc.
19329 This is a way of distinguishing r0 in 32-bits from r0 in
19332 gen_rtx_PARALLEL (VOIDmode,
19335 gen_rtx_REG (SImode, regno + 1200),
19336 gen_rtx_REG (SImode, regno))
19338 gen_rtx_REG (SImode, regno),
19339 gen_rtx_REG (SImode, regno + 1200)));
19342 /* Map internal gcc register numbers to DWARF2 register numbers. */
19345 rs6000_dbx_register_number (unsigned int regno)
19347 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
19349 if (regno == MQ_REGNO)
19351 if (regno == LINK_REGISTER_REGNUM)
19353 if (regno == COUNT_REGISTER_REGNUM)
19355 if (CR_REGNO_P (regno))
19356 return regno - CR0_REGNO + 86;
19357 if (regno == XER_REGNO)
19359 if (ALTIVEC_REGNO_P (regno))
19360 return regno - FIRST_ALTIVEC_REGNO + 1124;
19361 if (regno == VRSAVE_REGNO)
19363 if (regno == VSCR_REGNO)
19365 if (regno == SPE_ACC_REGNO)
19367 if (regno == SPEFSCR_REGNO)
19369 /* SPE high reg number. We get these values of regno from
19370 rs6000_dwarf_register_span. */
19371 gcc_assert (regno >= 1200 && regno < 1232);
19375 /* target hook eh_return_filter_mode */
19376 static enum machine_mode
19377 rs6000_eh_return_filter_mode (void)
19379 return TARGET_32BIT ? SImode : word_mode;
19382 /* Target hook for scalar_mode_supported_p. */
19384 rs6000_scalar_mode_supported_p (enum machine_mode mode)
19386 if (DECIMAL_FLOAT_MODE_P (mode))
19389 return default_scalar_mode_supported_p (mode);
19392 /* Target hook for vector_mode_supported_p. */
19394 rs6000_vector_mode_supported_p (enum machine_mode mode)
19397 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
19400 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
19407 /* Target hook for invalid_arg_for_unprototyped_fn. */
19408 static const char *
19409 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
19411 return (!rs6000_darwin64_abi
19413 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
19414 && (funcdecl == NULL_TREE
19415 || (TREE_CODE (funcdecl) == FUNCTION_DECL
19416 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
19417 ? N_("AltiVec argument passed to unprototyped function")
19421 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
19422 setup by using __stack_chk_fail_local hidden function instead of
19423 calling __stack_chk_fail directly. Otherwise it is better to call
19424 __stack_chk_fail directly. */
19427 rs6000_stack_protect_fail (void)
19429 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
19430 ? default_hidden_stack_protect_fail ()
19431 : default_external_stack_protect_fail ();
19434 #include "gt-rs6000.h"