1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
40 extern char *language_string;
41 extern int profile_block_flag;
43 #define min(A,B) ((A) < (B) ? (A) : (B))
44 #define max(A,B) ((A) > (B) ? (A) : (B))
48 enum processor_type rs6000_cpu;
49 char *rs6000_cpu_string;
51 /* Set to non-zero by "fix" operation to indicate that itrunc and
52 uitrunc must be defined. */
54 int rs6000_trunc_used;
56 /* Set to non-zero once they have been defined. */
58 static int trunc_defined;
60 /* Set to non-zero once AIX common-mode calls have been defined. */
61 static int common_mode_defined;
62 /* Save information from a "cmpxx" operation until the branch or scc is
65 rtx rs6000_compare_op0, rs6000_compare_op1;
66 int rs6000_compare_fp_p;
69 /* Label number of label created for -mrelocatable, to call to so we can
70 get the address of the GOT section */
71 int rs6000_pic_labelno;
74 /* Override command line options. Mostly we process the processor
75 type and sometimes adjust other TARGET_ options. */
78 rs6000_override_options ()
82 /* Simplify the entries below by making a mask for any POWER
83 variant and any PowerPC variant. */
85 #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING)
86 #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \
87 | MASK_PPC_GFXOPT | MASK_POWERPC64)
88 #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT)
92 char *name; /* Canonical processor name. */
93 enum processor_type processor; /* Processor type enum value. */
94 int target_enable; /* Target flags to enable. */
95 int target_disable; /* Target flags to disable. */
96 } processor_target_table[]
97 = {{"common", PROCESSOR_COMMON, 0, POWER_MASKS | POWERPC_MASKS},
98 {"power", PROCESSOR_POWER,
99 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
100 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
101 {"powerpc", PROCESSOR_POWERPC,
102 MASK_POWERPC | MASK_NEW_MNEMONICS,
103 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
104 {"rios", PROCESSOR_RIOS1,
105 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
106 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
107 {"rios1", PROCESSOR_RIOS1,
108 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
109 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
110 {"rsc", PROCESSOR_PPC601,
111 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
112 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
113 {"rsc1", PROCESSOR_PPC601,
114 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
115 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
116 {"rios2", PROCESSOR_RIOS2,
117 MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2,
118 POWERPC_MASKS | MASK_NEW_MNEMONICS},
119 {"403", PROCESSOR_PPC403,
120 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
121 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
122 {"601", PROCESSOR_PPC601,
123 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING,
124 MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
125 {"603", PROCESSOR_PPC603,
126 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
127 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
128 {"604", PROCESSOR_PPC604,
129 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
130 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}};
132 int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
134 int multiple = TARGET_MULTIPLE; /* save current -mmultiple/-mno-multiple status */
135 int string = TARGET_STRING; /* save current -mstring/-mno-string status */
137 profile_block_flag = 0;
139 /* Identify the processor type */
140 if (rs6000_cpu_string == 0)
141 rs6000_cpu = PROCESSOR_DEFAULT;
144 for (i = 0; i < ptt_size; i++)
145 if (! strcmp (rs6000_cpu_string, processor_target_table[i].name))
147 rs6000_cpu = processor_target_table[i].processor;
148 target_flags |= processor_target_table[i].target_enable;
149 target_flags &= ~processor_target_table[i].target_disable;
155 error ("bad value (%s) for -mcpu= switch", rs6000_cpu_string);
156 rs6000_cpu_string = "default";
157 rs6000_cpu = PROCESSOR_DEFAULT;
161 /* If -mmultiple or -mno-multiple was explicitly used, don't
162 override with the processor default */
163 if (TARGET_MULTIPLE_SET)
164 target_flags = (target_flags & ~MASK_MULTIPLE) | multiple;
166 /* If -mstring or -mno-string was explicitly used, don't
167 override with the processor default */
168 if (TARGET_STRING_SET)
169 target_flags = (target_flags & ~MASK_STRING) | string;
171 /* Don't allow -mmultiple or -mstring on little endian systems, because the
172 hardware doesn't support the instructions used in little endian mode */
173 if (!BYTES_BIG_ENDIAN)
177 target_flags &= ~MASK_MULTIPLE;
178 if (TARGET_MULTIPLE_SET)
179 warning ("-mmultiple is not supported on little endian systems");
184 target_flags &= ~MASK_STRING;
185 if (TARGET_STRING_SET)
186 warning ("-mstring is not supported on little endian systems");
190 #ifdef SUBTARGET_OVERRIDE_OPTIONS
191 SUBTARGET_OVERRIDE_OPTIONS;
195 /* Create a CONST_DOUBLE like immed_double_const, except reverse the
196 two parts of the constant if the target is little endian. */
198 struct rtx_def *rs6000_immed_double_const (i0, i1, mode)
199 HOST_WIDE_INT i0, i1;
200 enum machine_mode mode;
202 if (! WORDS_BIG_ENDIAN)
203 return immed_double_const (i1, i0, mode);
205 return immed_double_const (i0, i1, mode);
209 /* Return non-zero if this function is known to have a null epilogue. */
214 return (reload_completed
215 && first_reg_to_save () == 32
216 && first_fp_reg_to_save () == 64
217 && ! regs_ever_live[65]
218 && ! rs6000_pushes_stack ());
221 /* Returns 1 always. */
224 any_operand (op, mode)
226 enum machine_mode mode;
231 /* Return 1 if OP is a constant that can fit in a D field. */
234 short_cint_operand (op, mode)
236 enum machine_mode mode;
238 return (GET_CODE (op) == CONST_INT
239 && (unsigned) (INTVAL (op) + 0x8000) < 0x10000);
242 /* Similar for a unsigned D field. */
245 u_short_cint_operand (op, mode)
247 enum machine_mode mode;
249 return (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0);
252 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
255 non_short_cint_operand (op, mode)
257 enum machine_mode mode;
259 return (GET_CODE (op) == CONST_INT
260 && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000);
263 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
267 gpc_reg_operand (op, mode)
269 enum machine_mode mode;
271 return (register_operand (op, mode)
272 && (GET_CODE (op) != REG || REGNO (op) >= 67 || REGNO (op) < 64));
275 /* Returns 1 if OP is either a pseudo-register or a register denoting a
279 cc_reg_operand (op, mode)
281 enum machine_mode mode;
283 return (register_operand (op, mode)
284 && (GET_CODE (op) != REG
285 || REGNO (op) >= FIRST_PSEUDO_REGISTER
286 || CR_REGNO_P (REGNO (op))));
289 /* Returns 1 if OP is either a constant integer valid for a D-field or a
290 non-special register. If a register, it must be in the proper mode unless
294 reg_or_short_operand (op, mode)
296 enum machine_mode mode;
298 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
301 /* Similar, except check if the negation of the constant would be valid for
305 reg_or_neg_short_operand (op, mode)
307 enum machine_mode mode;
309 if (GET_CODE (op) == CONST_INT)
310 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
312 return gpc_reg_operand (op, mode);
315 /* Return 1 if the operand is either a register or an integer whose high-order
319 reg_or_u_short_operand (op, mode)
321 enum machine_mode mode;
323 if (GET_CODE (op) == CONST_INT
324 && (INTVAL (op) & 0xffff0000) == 0)
327 return gpc_reg_operand (op, mode);
330 /* Return 1 is the operand is either a non-special register or ANY
334 reg_or_cint_operand (op, mode)
336 enum machine_mode mode;
338 return GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode);
341 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register
342 with one instruction per word. We only do this if we can safely read
343 CONST_DOUBLE_{LOW,HIGH}. */
346 easy_fp_constant (op, mode)
348 register enum machine_mode mode;
352 if (GET_CODE (op) != CONST_DOUBLE
353 || GET_MODE (op) != mode
354 || GET_MODE_CLASS (mode) != MODE_FLOAT)
357 high = operand_subword (op, 0, 0, mode);
358 low = operand_subword (op, 1, 0, mode);
360 if (high == 0 || ! input_operand (high, word_mode))
363 return (mode == SFmode
364 || (low != 0 && input_operand (low, word_mode)));
367 /* Return 1 if the operand is a constant whose low-order 32 bits are
371 low_32_bit_operand (op, mode)
373 enum machine_mode mode;
377 if (GET_CODE (op) != CONST_DOUBLE && GET_CODE (op) != CONST_INT)
380 low = operand_subword (op, 1, 0, mode);
381 return low != 0 && GET_CODE (low) == CONST_INT && INTVAL (low) == 0;
384 /* Return 1 if the operand is either a floating-point register, a pseudo
385 register, or memory. */
388 fp_reg_or_mem_operand (op, mode)
390 enum machine_mode mode;
392 return (memory_operand (op, mode)
393 || (register_operand (op, mode)
394 && (GET_CODE (op) != REG
395 || REGNO (op) >= FIRST_PSEUDO_REGISTER
396 || FP_REGNO_P (REGNO (op)))));
399 /* Return 1 if the operand is either an easy FP constant (see above) or
403 mem_or_easy_const_operand (op, mode)
405 enum machine_mode mode;
407 return memory_operand (op, mode) || easy_fp_constant (op, mode);
410 /* Return 1 if the operand is either a non-special register or an item
411 that can be used as the operand of an SI add insn. */
414 add_operand (op, mode)
416 enum machine_mode mode;
418 return (reg_or_short_operand (op, mode)
419 || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0));
422 /* Return 1 if OP is a constant but not a valid add_operand. */
425 non_add_cint_operand (op, mode)
427 enum machine_mode mode;
429 return (GET_CODE (op) == CONST_INT
430 && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000
431 && (INTVAL (op) & 0xffff) != 0);
434 /* Return 1 if the operand is a non-special register or a constant that
435 can be used as the operand of an OR or XOR insn on the RS/6000. */
438 logical_operand (op, mode)
440 enum machine_mode mode;
442 return (gpc_reg_operand (op, mode)
443 || (GET_CODE (op) == CONST_INT
444 && ((INTVAL (op) & 0xffff0000) == 0
445 || (INTVAL (op) & 0xffff) == 0)));
448 /* Return 1 if C is a constant that is not a logical operand (as
452 non_logical_cint_operand (op, mode)
454 enum machine_mode mode;
456 return (GET_CODE (op) == CONST_INT
457 && (INTVAL (op) & 0xffff0000) != 0
458 && (INTVAL (op) & 0xffff) != 0);
461 /* Return 1 if C is a constant that can be encoded in a mask on the
462 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
463 Reject all ones and all zeros, since these should have been optimized
464 away and confuse the making of MB and ME. */
474 if (c == 0 || c == ~0)
477 last_bit_value = c & 1;
479 for (i = 1; i < 32; i++)
480 if (((c >>= 1) & 1) != last_bit_value)
481 last_bit_value ^= 1, transitions++;
483 return transitions <= 2;
486 /* Return 1 if the operand is a constant that is a mask on the RS/6000. */
489 mask_operand (op, mode)
491 enum machine_mode mode;
493 return GET_CODE (op) == CONST_INT && mask_constant (INTVAL (op));
496 /* Return 1 if the operand is either a non-special register or a
497 constant that can be used as the operand of an RS/6000 logical AND insn. */
500 and_operand (op, mode)
502 enum machine_mode mode;
504 return (reg_or_short_operand (op, mode)
505 || logical_operand (op, mode)
506 || mask_operand (op, mode));
509 /* Return 1 if the operand is a constant but not a valid operand for an AND
513 non_and_cint_operand (op, mode)
515 enum machine_mode mode;
517 return GET_CODE (op) == CONST_INT && ! and_operand (op, mode);
520 /* Return 1 if the operand is a general register or memory operand. */
523 reg_or_mem_operand (op, mode)
525 register enum machine_mode mode;
527 return gpc_reg_operand (op, mode) || memory_operand (op, mode);
530 /* Return 1 if the operand is a general register or memory operand without
531 pre-inc or pre_dec which produces invalid form of PowerPC lwa
535 lwa_operand (op, mode)
537 register enum machine_mode mode;
541 if (reload_completed && GET_CODE (inner) == SUBREG)
542 inner = SUBREG_REG (inner);
544 return gpc_reg_operand (inner, mode)
545 || (memory_operand (inner, mode)
546 && GET_CODE (XEXP (inner, 0)) != PRE_INC
547 && GET_CODE (XEXP (inner, 0)) != PRE_DEC);
550 /* Return 1 if the operand, used inside a MEM, is a valid first argument
551 to CALL. This is a SYMBOL_REF or a pseudo-register, which will be
555 call_operand (op, mode)
557 enum machine_mode mode;
559 if (mode != VOIDmode && GET_MODE (op) != mode)
562 return (GET_CODE (op) == SYMBOL_REF
563 || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER));
567 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
571 current_file_function_operand (op, mode)
573 enum machine_mode mode;
575 return (GET_CODE (op) == SYMBOL_REF
576 && (SYMBOL_REF_FLAG (op)
577 || op == XEXP (DECL_RTL (current_function_decl), 0)));
581 /* Return 1 if this operand is a valid input for a move insn. */
584 input_operand (op, mode)
586 enum machine_mode mode;
588 /* Memory is always valid. */
589 if (memory_operand (op, mode))
592 /* For floating-point, easy constants are valid. */
593 if (GET_MODE_CLASS (mode) == MODE_FLOAT
595 && easy_fp_constant (op, mode))
598 /* For floating-point or multi-word mode, the only remaining valid type
600 if (GET_MODE_CLASS (mode) == MODE_FLOAT
601 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
602 return register_operand (op, mode);
604 /* The only cases left are integral modes one word or smaller (we
605 do not get called for MODE_CC values). These can be in any
607 if (register_operand (op, mode))
610 /* For HImode and QImode, any constant is valid. */
611 if ((mode == HImode || mode == QImode)
612 && GET_CODE (op) == CONST_INT)
615 /* A SYMBOL_REF referring to the TOC is valid. */
616 if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op))
619 /* Otherwise, we will be doing this SET with an add, so anything valid
620 for an add will be valid. */
621 return add_operand (op, mode);
624 /* Expand a block move operation, and return 1 if successful. Return 0
625 if we should let the compiler generate normal code.
627 operands[0] is the destination
628 operands[1] is the source
629 operands[2] is the length
630 operands[3] is the alignment */
632 #define MAX_MOVE_REG 4
635 expand_block_move (operands)
638 rtx bytes_rtx = operands[2];
639 rtx align_rtx = operands[3];
640 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
641 int align = XINT (align_rtx, 0);
651 rtx stores[MAX_MOVE_REG];
654 /* If this is not a fixed size move, just call memcpy */
658 /* Anything to move? */
659 bytes = INTVAL (bytes_rtx);
663 /* Don't support real large moves. If string instructions are not used,
664 then don't generate more than 8 loads. */
670 else if (!STRICT_ALIGNMENT)
675 else if (bytes > 8*align)
678 /* Move the address into scratch registers. */
679 dest_reg = copy_addr_to_reg (XEXP (operands[0], 0));
680 src_reg = copy_addr_to_reg (XEXP (operands[1], 0));
682 if (TARGET_STRING) /* string instructions are available */
684 for ( ; bytes > 0; bytes -= move_bytes)
687 /* XXX Don't move so many bytes right now, it causes the compiler to not bootstrap */
688 if (bytes > 24 /* move up to 32 bytes at a time */
698 move_bytes = (bytes > 32) ? 32 : bytes;
699 emit_insn (gen_movstrsi_8reg (dest_reg,
701 GEN_INT ((move_bytes == 32) ? 0 : move_bytes),
704 else if (bytes > 16 /* move up to 24 bytes at a time */
712 move_bytes = (bytes > 24) ? 24 : bytes;
713 emit_insn (gen_movstrsi_6reg (dest_reg,
715 GEN_INT (move_bytes),
718 else if (bytes > 8 /* move up to 16 bytes at a time */
724 move_bytes = (bytes > 16) ? 16 : bytes;
725 emit_insn (gen_movstrsi_4reg (dest_reg,
727 GEN_INT (move_bytes),
732 if (bytes > 4 && !TARGET_64BIT)
733 { /* move up to 8 bytes at a time */
734 move_bytes = (bytes > 8) ? 8 : bytes;
735 emit_insn (gen_movstrsi_2reg (dest_reg,
737 GEN_INT (move_bytes),
740 else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT))
743 tmp_reg = gen_reg_rtx (SImode);
744 emit_move_insn (tmp_reg, gen_rtx (MEM, SImode, src_reg));
745 emit_move_insn (gen_rtx (MEM, SImode, dest_reg), tmp_reg);
747 else if (bytes == 2 && (align >= 2 || !STRICT_ALIGNMENT))
750 tmp_reg = gen_reg_rtx (HImode);
751 emit_move_insn (tmp_reg, gen_rtx (MEM, HImode, src_reg));
752 emit_move_insn (gen_rtx (MEM, HImode, dest_reg), tmp_reg);
754 else if (bytes == 1) /* move 1 byte */
757 tmp_reg = gen_reg_rtx (QImode);
758 emit_move_insn (tmp_reg, gen_rtx (MEM, QImode, src_reg));
759 emit_move_insn (gen_rtx (MEM, QImode, dest_reg), tmp_reg);
762 { /* move up to 4 bytes at a time */
763 move_bytes = (bytes > 4) ? 4 : bytes;
764 emit_insn (gen_movstrsi_1reg (dest_reg,
766 GEN_INT (move_bytes),
770 if (bytes > move_bytes)
772 emit_insn (gen_addsi3 (src_reg, src_reg, GEN_INT (move_bytes)));
773 emit_insn (gen_addsi3 (dest_reg, dest_reg, GEN_INT (move_bytes)));
778 else /* string instructions not available */
780 num_reg = offset = 0;
781 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
783 /* Calculate the correct offset for src/dest */
787 dest_addr = dest_reg;
791 src_addr = gen_rtx (PLUS, Pmode, src_reg, GEN_INT (offset));
792 dest_addr = gen_rtx (PLUS, Pmode, dest_reg, GEN_INT (offset));
795 /* Generate the appropriate load and store, saving the stores for later */
796 if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT))
799 tmp_reg = gen_reg_rtx (SImode);
800 emit_insn (gen_movsi (tmp_reg, gen_rtx (MEM, SImode, src_addr)));
801 stores[ num_reg++ ] = gen_movsi (gen_rtx (MEM, SImode, dest_addr), tmp_reg);
803 else if (bytes >= 2 && (align >= 2 || !STRICT_ALIGNMENT))
806 tmp_reg = gen_reg_rtx (HImode);
807 emit_insn (gen_movhi (tmp_reg, gen_rtx (MEM, HImode, src_addr)));
808 stores[ num_reg++ ] = gen_movhi (gen_rtx (MEM, HImode, dest_addr), tmp_reg);
813 tmp_reg = gen_reg_rtx (QImode);
814 emit_insn (gen_movqi (tmp_reg, gen_rtx (MEM, QImode, src_addr)));
815 stores[ num_reg++ ] = gen_movqi (gen_rtx (MEM, QImode, dest_addr), tmp_reg);
818 if (num_reg >= MAX_MOVE_REG)
820 for (i = 0; i < num_reg; i++)
821 emit_insn (stores[i]);
828 for (i = 0; i < num_reg; i++)
829 emit_insn (stores[i]);
837 /* Return 1 if OP is a load multiple operation. It is known to be a
838 PARALLEL and the first section will be tested. */
841 load_multiple_operation (op, mode)
843 enum machine_mode mode;
845 int count = XVECLEN (op, 0);
850 /* Perform a quick check so we don't blow up below. */
852 || GET_CODE (XVECEXP (op, 0, 0)) != SET
853 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
854 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
857 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
858 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
860 for (i = 1; i < count; i++)
862 rtx elt = XVECEXP (op, 0, i);
864 if (GET_CODE (elt) != SET
865 || GET_CODE (SET_DEST (elt)) != REG
866 || GET_MODE (SET_DEST (elt)) != SImode
867 || REGNO (SET_DEST (elt)) != dest_regno + i
868 || GET_CODE (SET_SRC (elt)) != MEM
869 || GET_MODE (SET_SRC (elt)) != SImode
870 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
871 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
872 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
873 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
880 /* Similar, but tests for store multiple. Here, the second vector element
881 is a CLOBBER. It will be tested later. */
884 store_multiple_operation (op, mode)
886 enum machine_mode mode;
888 int count = XVECLEN (op, 0) - 1;
893 /* Perform a quick check so we don't blow up below. */
895 || GET_CODE (XVECEXP (op, 0, 0)) != SET
896 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
897 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
900 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
901 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
903 for (i = 1; i < count; i++)
905 rtx elt = XVECEXP (op, 0, i + 1);
907 if (GET_CODE (elt) != SET
908 || GET_CODE (SET_SRC (elt)) != REG
909 || GET_MODE (SET_SRC (elt)) != SImode
910 || REGNO (SET_SRC (elt)) != src_regno + i
911 || GET_CODE (SET_DEST (elt)) != MEM
912 || GET_MODE (SET_DEST (elt)) != SImode
913 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
914 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
915 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
916 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
923 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
924 We only check the opcode against the mode of the CC value here. */
927 branch_comparison_operator (op, mode)
929 enum machine_mode mode;
931 enum rtx_code code = GET_CODE (op);
932 enum machine_mode cc_mode;
934 if (GET_RTX_CLASS (code) != '<')
937 cc_mode = GET_MODE (XEXP (op, 0));
938 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
941 if ((code == GT || code == LT || code == GE || code == LE)
942 && cc_mode == CCUNSmode)
945 if ((code == GTU || code == LTU || code == GEU || code == LEU)
946 && (cc_mode != CCUNSmode))
952 /* Return 1 if OP is a comparison operation that is valid for an scc insn.
953 We check the opcode against the mode of the CC value and disallow EQ or
954 NE comparisons for integers. */
957 scc_comparison_operator (op, mode)
959 enum machine_mode mode;
961 enum rtx_code code = GET_CODE (op);
962 enum machine_mode cc_mode;
964 if (GET_MODE (op) != mode && mode != VOIDmode)
967 if (GET_RTX_CLASS (code) != '<')
970 cc_mode = GET_MODE (XEXP (op, 0));
971 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
974 if (code == NE && cc_mode != CCFPmode)
977 if ((code == GT || code == LT || code == GE || code == LE)
978 && cc_mode == CCUNSmode)
981 if ((code == GTU || code == LTU || code == GEU || code == LEU)
982 && (cc_mode != CCUNSmode))
985 if (cc_mode == CCEQmode && code != EQ && code != NE)
991 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
992 mask required to convert the result of a rotate insn into a shift
993 left insn of SHIFTOP bits. Both are known to be CONST_INT. */
996 includes_lshift_p (shiftop, andop)
997 register rtx shiftop;
1000 int shift_mask = (~0 << INTVAL (shiftop));
1002 return (INTVAL (andop) & ~shift_mask) == 0;
1005 /* Similar, but for right shift. */
1008 includes_rshift_p (shiftop, andop)
1009 register rtx shiftop;
1012 unsigned shift_mask = ~0;
1014 shift_mask >>= INTVAL (shiftop);
1016 return (INTVAL (andop) & ~ shift_mask) == 0;
1019 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
1020 for lfq and stfq insns.
1022 Note reg1 and reg2 *must* be hard registers. To be sure we will
1023 abort if we are passed pseudo registers. */
1026 registers_ok_for_quad_peep (reg1, reg2)
1029 /* We might have been passed a SUBREG. */
1030 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
1033 return (REGNO (reg1) == REGNO (reg2) - 1);
1036 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. addr1 and
1037 addr2 must be in consecutive memory locations (addr2 == addr1 + 8). */
1040 addrs_ok_for_quad_peep (addr1, addr2)
1047 /* Extract an offset (if used) from the first addr. */
1048 if (GET_CODE (addr1) == PLUS)
1050 /* If not a REG, return zero. */
1051 if (GET_CODE (XEXP (addr1, 0)) != REG)
1055 reg1 = REGNO (XEXP (addr1, 0));
1056 /* The offset must be constant! */
1057 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
1059 offset1 = INTVAL (XEXP (addr1, 1));
1062 else if (GET_CODE (addr1) != REG)
1066 reg1 = REGNO (addr1);
1067 /* This was a simple (mem (reg)) expression. Offset is 0. */
1071 /* Make sure the second address is a (mem (plus (reg) (const_int). */
1072 if (GET_CODE (addr2) != PLUS)
1075 if (GET_CODE (XEXP (addr2, 0)) != REG
1076 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
1079 if (reg1 != REGNO (XEXP (addr2, 0)))
1082 /* The offset for the second addr must be 8 more than the first addr. */
1083 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
1086 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
1091 /* Return the register class of a scratch register needed to copy IN into
1092 or out of a register in CLASS in MODE. If it can be done directly,
1093 NO_REGS is returned. */
1096 secondary_reload_class (class, mode, in)
1097 enum reg_class class;
1098 enum machine_mode mode;
1101 int regno = true_regnum (in);
1103 if (regno >= FIRST_PSEUDO_REGISTER)
1106 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
1108 if (class == GENERAL_REGS || class == BASE_REGS
1109 || (regno >= 0 && INT_REGNO_P (regno)))
1112 /* Constants, memory, and FP registers can go into FP registers. */
1113 if ((regno == -1 || FP_REGNO_P (regno))
1114 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
1117 /* We can copy among the CR registers. */
1118 if ((class == CR_REGS || class == CR0_REGS)
1119 && regno >= 0 && CR_REGNO_P (regno))
1122 /* Otherwise, we need GENERAL_REGS. */
1123 return GENERAL_REGS;
1126 /* Given a comparison operation, return the bit number in CCR to test. We
1127 know this is a valid comparison.
1129 SCC_P is 1 if this is for an scc. That means that %D will have been
1130 used instead of %C, so the bits will be in different places.
1132 Return -1 if OP isn't a valid comparison for some reason. */
1139 enum rtx_code code = GET_CODE (op);
1140 enum machine_mode cc_mode;
1144 if (GET_RTX_CLASS (code) != '<')
1147 cc_mode = GET_MODE (XEXP (op, 0));
1148 cc_regnum = REGNO (XEXP (op, 0));
1149 base_bit = 4 * (cc_regnum - 68);
1151 /* In CCEQmode cases we have made sure that the result is always in the
1152 third bit of the CR field. */
1154 if (cc_mode == CCEQmode)
1155 return base_bit + 3;
1160 return scc_p ? base_bit + 3 : base_bit + 2;
1162 return base_bit + 2;
1164 return base_bit + 1;
1169 /* If floating-point, we will have done a cror to put the bit in the
1170 unordered position. So test that bit. For integer, this is ! LT
1171 unless this is an scc insn. */
1172 return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit;
1175 return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit + 1;
1182 /* Print an operand. Recognize special options, documented below. */
1185 print_operand (file, x, code)
1193 /* These macros test for integers and extract the low-order bits. */
1195 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
1196 && GET_MODE (X) == VOIDmode)
1198 #define INT_LOWPART(X) \
1199 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
1204 /* Write out an instruction after the call which may be replaced
1205 with glue code by the loader. This depends on the AIX version. */
1206 asm_fprintf (file, RS6000_CALL_GLUE);
1210 /* Write the register number of the TOC register. */
1211 fputs (TARGET_MINIMAL_TOC ? "30" : "2", file);
1215 /* If X is a constant integer whose low-order 5 bits are zero,
1216 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
1217 in the AIX assembler where "sri" with a zero shift count
1218 write a trash instruction. */
1219 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
1226 /* Low-order 16 bits of constant, unsigned. */
1228 output_operand_lossage ("invalid %%b value");
1230 fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
1234 /* This is an optional cror needed for LE or GE floating-point
1235 comparisons. Otherwise write nothing. */
1236 if ((GET_CODE (x) == LE || GET_CODE (x) == GE)
1237 && GET_MODE (XEXP (x, 0)) == CCFPmode)
1239 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
1241 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
1242 base_bit + 2, base_bit + (GET_CODE (x) == GE));
1247 /* Similar, except that this is for an scc, so we must be able to
1248 encode the test in a single bit that is one. We do the above
1249 for any LE, GE, GEU, or LEU and invert the bit for NE. */
1250 if (GET_CODE (x) == LE || GET_CODE (x) == GE
1251 || GET_CODE (x) == LEU || GET_CODE (x) == GEU)
1253 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
1255 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
1257 base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU));
1260 else if (GET_CODE (x) == NE)
1262 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
1264 fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
1265 base_bit + 2, base_bit + 2);
1270 /* X is a CR register. Print the number of the third bit of the CR */
1271 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1272 output_operand_lossage ("invalid %%E value");
1274 fprintf(file, "%d", 4 * (REGNO (x) - 68) + 3);
1278 /* X is a CR register. Print the shift count needed to move it
1279 to the high-order four bits. */
1280 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1281 output_operand_lossage ("invalid %%f value");
1283 fprintf (file, "%d", 4 * (REGNO (x) - 68));
1287 /* Similar, but print the count for the rotate in the opposite
1289 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1290 output_operand_lossage ("invalid %%F value");
1292 fprintf (file, "%d", 32 - 4 * (REGNO (x) - 68));
1296 /* X is a constant integer. If it is negative, print "m",
1297 otherwise print "z". This is to make a aze or ame insn. */
1298 if (GET_CODE (x) != CONST_INT)
1299 output_operand_lossage ("invalid %%G value");
1300 else if (INTVAL (x) >= 0)
1307 /* If constant, output low-order five bits. Otherwise,
1310 fprintf (file, "%d", INT_LOWPART (x) & 31);
1312 print_operand (file, x, 0);
1316 /* Print `i' if this is a constant, else nothing. */
1322 /* Write the bit number in CCR for jump. */
1325 output_operand_lossage ("invalid %%j code");
1327 fprintf (file, "%d", i);
1331 /* Similar, but add one for shift count in rlinm for scc and pass
1332 scc flag to `ccr_bit'. */
1335 output_operand_lossage ("invalid %%J code");
1337 /* If we want bit 31, write a shift count of zero, not 32. */
1338 fprintf (file, "%d", i == 31 ? 0 : i + 1);
1342 /* X must be a constant. Write the 1's complement of the
1345 output_operand_lossage ("invalid %%k value");
1347 fprintf (file, "%d", ~ INT_LOWPART (x));
1351 /* Write second word of DImode or DFmode reference. Works on register
1352 or non-indexed memory only. */
1353 if (GET_CODE (x) == REG)
1354 fprintf (file, "%d", REGNO (x) + 1);
1355 else if (GET_CODE (x) == MEM)
1357 /* Handle possible auto-increment. Since it is pre-increment and
1358 we have already done it, we can just use an offset of four. */
1359 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1360 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1361 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
1363 output_address (plus_constant (XEXP (x, 0), 4));
1368 /* MB value for a mask operand. */
1369 if (! mask_operand (x, VOIDmode))
1370 output_operand_lossage ("invalid %%m value");
1372 val = INT_LOWPART (x);
1374 /* If the high bit is set and the low bit is not, the value is zero.
1375 If the high bit is zero, the value is the first 1 bit we find from
1377 if (val < 0 && (val & 1) == 0)
1379 fprintf (file, "0");
1384 for (i = 1; i < 32; i++)
1385 if ((val <<= 1) < 0)
1387 fprintf (file, "%d", i);
1391 /* Otherwise, look for the first 0 bit from the right. The result is its
1392 number plus 1. We know the low-order bit is one. */
1393 for (i = 0; i < 32; i++)
1394 if (((val >>= 1) & 1) == 0)
1397 /* If we ended in ...01, I would be 0. The correct value is 31, so
1399 fprintf (file, "%d", 31 - i);
1403 /* ME value for a mask operand. */
1404 if (! mask_operand (x, VOIDmode))
1405 output_operand_lossage ("invalid %%m value");
1407 val = INT_LOWPART (x);
1409 /* If the low bit is set and the high bit is not, the value is 31.
1410 If the low bit is zero, the value is the first 1 bit we find from
1412 if ((val & 1) && val >= 0)
1417 else if ((val & 1) == 0)
1419 for (i = 0; i < 32; i++)
1420 if ((val >>= 1) & 1)
1423 /* If we had ....10, I would be 0. The result should be
1424 30, so we need 30 - i. */
1425 fprintf (file, "%d", 30 - i);
1429 /* Otherwise, look for the first 0 bit from the left. The result is its
1430 number minus 1. We know the high-order bit is one. */
1431 for (i = 0; i < 32; i++)
1432 if ((val <<= 1) >= 0)
1435 fprintf (file, "%d", i);
1439 /* Write the number of elements in the vector times 4. */
1440 if (GET_CODE (x) != PARALLEL)
1441 output_operand_lossage ("invalid %%N value");
1443 fprintf (file, "%d", XVECLEN (x, 0) * 4);
1447 /* Similar, but subtract 1 first. */
1448 if (GET_CODE (x) != PARALLEL)
1449 output_operand_lossage ("invalid %%N value");
1451 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
1455 /* X is a CONST_INT that is a power of two. Output the logarithm. */
1457 || (i = exact_log2 (INT_LOWPART (x))) < 0)
1458 output_operand_lossage ("invalid %%p value");
1460 fprintf (file, "%d", i);
1464 /* The operand must be an indirect memory reference. The result
1465 is the register number. */
1466 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
1467 || REGNO (XEXP (x, 0)) >= 32)
1468 output_operand_lossage ("invalid %%P value");
1470 fprintf (file, "%d", REGNO (XEXP (x, 0)));
1474 /* X is a CR register. Print the mask for `mtcrf'. */
1475 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1476 output_operand_lossage ("invalid %%R value");
1478 fprintf (file, "%d", 128 >> (REGNO (x) - 68));
1482 /* Low 5 bits of 32 - value */
1484 output_operand_lossage ("invalid %%s value");
1486 fprintf (file, "%d", (32 - INT_LOWPART (x)) & 31);
1490 /* Write 12 if this jump operation will branch if true, 4 otherwise.
1491 All floating-point operations except NE branch true and integer
1492 EQ, LT, GT, LTU and GTU also branch true. */
1493 if (GET_RTX_CLASS (GET_CODE (x)) != '<')
1494 output_operand_lossage ("invalid %%t value");
1496 else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
1497 && GET_CODE (x) != NE)
1498 || GET_CODE (x) == EQ
1499 || GET_CODE (x) == LT || GET_CODE (x) == GT
1500 || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
1507 /* Opposite of 't': write 4 if this jump operation will branch if true,
1509 if (GET_RTX_CLASS (GET_CODE (x)) != '<')
1510 output_operand_lossage ("invalid %%t value");
1512 else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
1513 && GET_CODE (x) != NE)
1514 || GET_CODE (x) == EQ
1515 || GET_CODE (x) == LT || GET_CODE (x) == GT
1516 || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
1523 /* High-order 16 bits of constant. */
1525 output_operand_lossage ("invalid %%u value");
1527 fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff);
1531 /* Print `u' if this has an auto-increment or auto-decrement. */
1532 if (GET_CODE (x) == MEM
1533 && (GET_CODE (XEXP (x, 0)) == PRE_INC
1534 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
1539 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
1542 fprintf (file, "%d",
1543 (INT_LOWPART (x) & 0xffff) - 2 * (INT_LOWPART (x) & 0x8000));
1545 print_operand (file, x, 0);
1549 /* If constant, low-order 16 bits of constant, unsigned.
1550 Otherwise, write normally. */
1552 fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
1554 print_operand (file, x, 0);
1558 if (GET_CODE (x) == MEM
1559 && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0)))
1564 /* Like 'L', for third word of TImode */
1565 if (GET_CODE (x) == REG)
1566 fprintf (file, "%d", REGNO (x) + 2);
1567 else if (GET_CODE (x) == MEM)
1569 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1570 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1571 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
1573 output_address (plus_constant (XEXP (x, 0), 8));
1578 /* X is a SYMBOL_REF. Write out the name preceded by a
1579 period and without any trailing data in brackets. Used for function
1580 names. If we are configured for System V (or the embedded ABI) on
1581 the PowerPC, do not emit the period, since those systems do not use
1582 TOCs and the like. */
1583 if (GET_CODE (x) != SYMBOL_REF)
1586 #ifndef USING_SVR4_H
1589 RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
1593 /* Like 'L', for last word of TImode. */
1594 if (GET_CODE (x) == REG)
1595 fprintf (file, "%d", REGNO (x) + 3);
1596 else if (GET_CODE (x) == MEM)
1598 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1599 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1600 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
1602 output_address (plus_constant (XEXP (x, 0), 12));
1607 if (GET_CODE (x) == REG)
1608 fprintf (file, "%s", reg_names[REGNO (x)]);
1609 else if (GET_CODE (x) == MEM)
1611 /* We need to handle PRE_INC and PRE_DEC here, since we need to
1612 know the width from the mode. */
1613 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
1614 fprintf (file, "%d(%d)", GET_MODE_SIZE (GET_MODE (x)),
1615 REGNO (XEXP (XEXP (x, 0), 0)));
1616 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
1617 fprintf (file, "%d(%d)", - GET_MODE_SIZE (GET_MODE (x)),
1618 REGNO (XEXP (XEXP (x, 0), 0)));
1620 output_address (XEXP (x, 0));
1623 output_addr_const (file, x);
1627 output_operand_lossage ("invalid %%xn code");
1631 /* Print the address of an operand. */
1634 print_operand_address (file, x)
1638 if (GET_CODE (x) == REG)
1639 fprintf (file, "0(%d)", REGNO (x));
1640 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
1642 output_addr_const (file, x);
1643 /* When TARGET_MINIMAL_TOC, use the indirected toc table pointer instead
1644 of the toc pointer. */
1645 if (TARGET_MINIMAL_TOC)
1646 fprintf (file, "(30)");
1648 fprintf (file, "(2)");
1650 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
1652 if (REGNO (XEXP (x, 0)) == 0)
1653 fprintf (file, "%d,%d", REGNO (XEXP (x, 1)), REGNO (XEXP (x, 0)));
1655 fprintf (file, "%d,%d", REGNO (XEXP (x, 0)), REGNO (XEXP (x, 1)));
1657 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1658 fprintf (file, "%d(%d)", INTVAL (XEXP (x, 1)), REGNO (XEXP (x, 0)));
1663 /* This page contains routines that are used to determine what the function
1664 prologue and epilogue code will do and write them out. */
1666 /* Return the first fixed-point register that is required to be saved. 32 if
1670 first_reg_to_save ()
1674 /* Find lowest numbered live register. */
1675 for (first_reg = 13; first_reg <= 31; first_reg++)
1676 if (regs_ever_live[first_reg])
1679 /* If profiling, then we must save/restore every register that contains
1680 a parameter before/after the .mcount call. Use registers from 30 down
1681 to 23 to do this. Don't use the frame pointer in reg 31.
1683 For now, save enough room for all of the parameter registers. */
1691 /* Similar, for FP regs. */
1694 first_fp_reg_to_save ()
1698 /* Find lowest numbered live register. */
1699 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
1700 if (regs_ever_live[first_reg])
1706 /* Return 1 if we need to save CR. */
1711 return regs_ever_live[70] || regs_ever_live[71] || regs_ever_live[72];
1714 /* Compute the size of the save area in the stack, including the space for
1722 /* We have the six fixed words, plus the size of the register save
1723 areas, rounded to a double-word. */
1724 size = 6 + (32 - first_reg_to_save ()) + (64 - first_fp_reg_to_save ()) * 2;
1731 /* Return non-zero if this function makes calls. */
1734 rs6000_makes_calls ()
1738 /* If we are profiling, we will be making a call to mcount. */
1742 for (insn = get_insns (); insn; insn = next_insn (insn))
1743 if (GET_CODE (insn) == CALL_INSN)
1749 /* Return non-zero if this function needs to push space on the stack. */
1752 rs6000_pushes_stack ()
1754 int total_size = (rs6000_sa_size () + get_frame_size ()
1755 + current_function_outgoing_args_size);
1757 /* We need to push the stack if a frame pointer is needed (because the
1758 stack might be dynamically adjusted), if we are debugging, if the
1759 total stack size is more than 220 bytes, or if we make calls. */
1761 return (frame_pointer_needed || write_symbols != NO_DEBUG
1763 || rs6000_makes_calls ());
1767 /* Write out a System V.4 style traceback table before the prologue
1769 At present, only emit the basic tag table (ie, do not emit tag_types other
1770 than 0, which might use more than 1 tag word).
1772 The first tag word looks like:
1775 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
1776 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1777 | 0 |ver| tag |e|s| alloca | # fprs | # gprs |s|l|c|f|
1778 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1783 svr4_traceback (file, name, decl)
1788 int first_reg = first_reg_to_save ();
1789 int first_fp_reg = first_fp_reg_to_save ();
1790 int pushes_stack = rs6000_pushes_stack ();
1792 long version = 0; /* version number */
1793 long tag_type = 0; /* function type */
1794 long extended_tag = 0; /* additional tag words needed */
1795 long spare = 0; /* reserved for future use */
1796 long alloca_reg; /* stack/frame register */
1797 long fpr_max = 64 - first_fp_reg; /* # of floating point registers saved */
1798 long gpr_max = 32 - first_reg; /* # of general purpose registers saved */
1799 long sp_max; /* 1 if the function acquires a stack frame */
1800 long lr_max; /* 1 if the function stores the link register */
1801 long cr_max; /* 1 if the function has a CR save word */
1802 long fpscr_max = 0; /* 1 if the function has a FPSCR save word */
1804 if (frame_pointer_needed)
1807 else if (pushes_stack != 0)
1813 lr_max = (regs_ever_live[65] || first_fp_reg < 62 || profile_flag);
1814 cr_max = (must_save_cr () != 0);
1815 sp_max = (pushes_stack != 0);
1817 tag = (((version & 3) << 24)
1818 | ((tag_type & 7) << 21)
1819 | ((extended_tag & 1) << 20)
1820 | ((spare & 1) << 19)
1821 | ((alloca_reg & 0x1f) << 14)
1822 | ((fpr_max & 0x1f) << 9)
1823 | ((gpr_max & 0x1f) << 4)
1824 | ((sp_max & 1) << 3)
1825 | ((lr_max & 1) << 2)
1826 | ((cr_max & 1) << 1)
1827 | ((fpscr_max & 1) << 0));
1829 fprintf (file, "\t.long 0x%lx\n", tag);
1832 #endif /* USING_SVR4_H */
1834 /* Write function prologue. */
1837 output_prolog (file, size)
1841 int first_reg = first_reg_to_save ();
1842 int must_push = rs6000_pushes_stack ();
1843 int first_fp_reg = first_fp_reg_to_save ();
1844 int basic_size = rs6000_sa_size ();
1845 int total_size = (basic_size + size + current_function_outgoing_args_size);
1848 /* Round size to multiple of 8 bytes. */
1849 total_size = (total_size + 7) & ~7;
1851 /* Write .extern for any function we will call to save and restore fp
1853 #ifndef USING_SVR4_H
1854 if (first_fp_reg < 62)
1855 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
1856 SAVE_FP_PREFIX, first_fp_reg - 32, SAVE_FP_SUFFIX,
1857 RESTORE_FP_PREFIX, first_fp_reg - 32, RESTORE_FP_SUFFIX);
1860 /* Write .extern for truncation routines, if needed. */
1861 if (rs6000_trunc_used && ! trunc_defined)
1863 fprintf (file, "\t.extern .%s\n\t.extern .%s\n",
1864 RS6000_ITRUNC, RS6000_UITRUNC);
1867 /* Write .extern for AIX common mode routines, if needed. */
1868 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
1870 fputs ("\t.extern __mulh\n", file);
1871 fputs ("\t.extern __mull\n", file);
1872 fputs ("\t.extern __divss\n", file);
1873 fputs ("\t.extern __divus\n", file);
1874 fputs ("\t.extern __quoss\n", file);
1875 fputs ("\t.extern __quous\n", file);
1876 common_mode_defined = 1;
1880 /* If we have a relocatable GOT section, we need to save the LR. */
1881 if (TARGET_RELOCATABLE && get_pool_size () != 0)
1882 regs_ever_live[65] = 1;
1885 /* If we have to call a function to save fpr's, or if we are doing profiling,
1886 then we will be using LR. */
1888 regs_ever_live[65] = 1;
1890 #ifndef USING_SVR4_H
1891 if (first_fp_reg < 62)
1892 regs_ever_live[65] = 1;
1895 /* If we use the link register, get it into r0. */
1896 if (regs_ever_live[65])
1897 asm_fprintf (file, "\tmflr 0\n");
1899 /* If we need to save CR, put it into r12. */
1900 if (must_save_cr ())
1901 asm_fprintf (file, "\tmfcr 12\n");
1903 /* Do any required saving of fpr's. If only one or two to save, do it
1904 ourself. Otherwise, call function. Note that since they are statically
1905 linked, we do not need a nop following them. */
1906 if (first_fp_reg == 62)
1907 asm_fprintf (file, "\tstfd 30,-16(1)\n\tstfd 31,-8(1)\n");
1908 else if (first_fp_reg == 63)
1909 asm_fprintf (file, "\tstfd 31,-8(1)\n");
1910 else if (first_fp_reg != 64)
1912 #ifndef USING_SVR4_H
1913 asm_fprintf (file, "\tbl %s%d%s\n", SAVE_FP_PREFIX, first_fp_reg - 32, SAVE_FP_SUFFIX);
1917 for (regno = first_fp_reg,
1918 loc = - (64 - first_fp_reg) * 8;
1921 asm_fprintf (file, "\tstfd %d,%d(1)\n", regno - 32, loc);
1925 /* Now save gpr's. */
1926 if (! TARGET_MULTIPLE || first_reg == 31)
1930 for (regno = first_reg,
1931 loc = - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8;
1934 asm_fprintf (file, "\t{st|stw} %d,%d(1)\n", regno, loc);
1937 else if (first_reg != 32)
1938 asm_fprintf (file, "\t{stm|stmw} %d,%d(1)\n", first_reg,
1939 - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8);
1941 /* Save lr if we used it. */
1942 if (regs_ever_live[65])
1943 asm_fprintf (file, "\t{st|stw} 0,8(1)\n");
1945 /* Save CR if we use any that must be preserved. */
1946 if (must_save_cr ())
1947 asm_fprintf (file, "\t{st|stw} 12,4(1)\n");
1949 /* Update stack and set back pointer. */
1952 if (total_size < 32767)
1953 asm_fprintf (file, "\t{stu|stwu} 1,%d(1)\n", - total_size);
1956 asm_fprintf (file, "\t{liu|lis} 0,%d\n\t{oril|ori} 0,0,%d\n",
1957 (total_size >> 16) & 0xffff, total_size & 0xffff);
1959 asm_fprintf (file, "\tsubf 12,0,1\n");
1961 asm_fprintf (file, "\t{sf|subfc} 12,0,1\n");
1962 asm_fprintf (file, "\t{st|stw} 1,0(12)\n\tmr 1,12\n");
1966 /* Set frame pointer, if needed. */
1967 if (frame_pointer_needed)
1968 asm_fprintf (file, "\tmr 31,1\n");
1970 /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the
1971 TOC_TABLE address into register 30. */
1972 if (TARGET_MINIMAL_TOC && get_pool_size () != 0)
1977 if (TARGET_RELOCATABLE)
1979 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
1980 fprintf (file, "\tbl ");
1981 assemble_name (file, buf);
1982 fprintf (file, "\n");
1984 ASM_OUTPUT_INTERNAL_LABEL (file, "LCF", rs6000_pic_labelno);
1985 fprintf (file, "\tmflr 30\n");
1987 if (TARGET_POWERPC64)
1988 fprintf (file, "\tld 0,");
1989 else if (TARGET_NEW_MNEMONICS)
1990 fprintf (file, "\tlwz 0,");
1992 fprintf (file, "\tl 0,");
1994 fprintf (file, "(");
1995 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
1996 assemble_name (file, buf);
1997 fprintf (file, "-");
1998 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
1999 assemble_name (file, buf);
2000 fprintf (file, ")(30)\n");
2001 asm_fprintf (file, "\t{cax|add} 30,0,30\n");
2002 rs6000_pic_labelno++;
2004 else if (TARGET_NO_TOC)
2006 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
2007 asm_fprintf (file, "\t{cau|addis} 30,0,");
2008 assemble_name (file, buf);
2009 asm_fprintf (file, "@ha\n");
2010 asm_fprintf (file, "\t{cal|addi} 30,30,");
2011 assemble_name (file, buf);
2012 asm_fprintf (file, "@l\n");
2015 #endif /* USING_SVR4_H */
2017 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 0);
2018 asm_fprintf (file, "\t{l|lwz} 30,");
2019 assemble_name (file, buf);
2020 asm_fprintf (file, "(2)\n");
2025 /* Write function epilogue. */
2028 output_epilog (file, size)
2032 int first_reg = first_reg_to_save ();
2033 int must_push = rs6000_pushes_stack ();
2034 int first_fp_reg = first_fp_reg_to_save ();
2035 int basic_size = rs6000_sa_size ();
2036 int total_size = (basic_size + size + current_function_outgoing_args_size);
2037 rtx insn = get_last_insn ();
2039 /* Round size to multiple of 8 bytes. */
2040 total_size = (total_size + 7) & ~7;
2042 /* If the last insn was a BARRIER, we don't have to write anything except
2044 if (GET_CODE (insn) == NOTE)
2045 insn = prev_nonnote_insn (insn);
2046 if (insn == 0 || GET_CODE (insn) != BARRIER)
2048 /* If we have a frame pointer, a call to alloca, or a large stack
2049 frame, restore the old stack pointer using the backchain. Otherwise,
2050 we know what size to update it with. */
2051 if (frame_pointer_needed || current_function_calls_alloca
2052 || total_size > 32767)
2053 asm_fprintf (file, "\t{l|lwz} 1,0(1)\n");
2055 asm_fprintf (file, "\t{cal 1,%d(1)|addi 1,1,%d}\n", total_size);
2057 /* Get the old lr if we saved it. */
2058 if (regs_ever_live[65])
2059 asm_fprintf (file, "\t{l|lwz} 0,8(1)\n");
2061 /* Get the old cr if we saved it. */
2062 if (must_save_cr ())
2063 asm_fprintf (file, "\t{l|lwz} 12,4(1)\n");
2065 /* Set LR here to try to overlap restores below. */
2066 if (regs_ever_live[65])
2067 asm_fprintf (file, "\tmtlr 0\n");
2069 /* Restore gpr's. */
2070 if (! TARGET_MULTIPLE || first_reg == 31)
2074 for (regno = first_reg,
2075 loc = - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8;
2078 asm_fprintf (file, "\t{l|lwz} %d,%d(1)\n", regno, loc);
2081 else if (first_reg != 32)
2082 asm_fprintf (file, "\t{lm|lmw} %d,%d(1)\n", first_reg,
2083 - (32 - first_reg) * 4 - (64 - first_fp_reg) * 8);
2085 /* Restore fpr's if we can do it without calling a function. */
2086 if (first_fp_reg == 62)
2087 asm_fprintf (file, "\tlfd 30,-16(1)\n\tlfd 31,-8(1)\n");
2088 else if (first_fp_reg == 63)
2089 asm_fprintf (file, "\tlfd 31,-8(1)\n");
2091 /* If we saved cr, restore it here. Just those of cr2, cr3, and cr4
2093 if (must_save_cr ())
2094 asm_fprintf (file, "\tmtcrf %d,12\n",
2095 (regs_ever_live[70] != 0) * 0x20
2096 + (regs_ever_live[71] != 0) * 0x10
2097 + (regs_ever_live[72] != 0) * 0x8);
2099 /* If we have to restore more than two FP registers, branch to the
2100 restore function. It will return to our caller. */
2101 if (first_fp_reg < 62)
2103 #ifndef USING_SVR4_H
2104 asm_fprintf (file, "\tb %s%d%s\n", RESTORE_FP_PREFIX, first_fp_reg - 32, RESTORE_FP_SUFFIX);
2108 for (regno = first_fp_reg,
2109 loc = - (64 - first_fp_reg) * 8;
2112 asm_fprintf (file, "\tlfd %d,%d(1)\n", regno - 32, loc);
2114 asm_fprintf (file, "\t{br|blr}\n");
2118 asm_fprintf (file, "\t{br|blr}\n");
2121 /* Output a traceback table here. See /usr/include/sys/debug.h for info
2124 We don't output a traceback table if -finhibit-size-directive was
2125 used. The documentation for -finhibit-size-directive reads
2126 ``don't output a @code{.size} assembler directive, or anything
2127 else that would cause trouble if the function is split in the
2128 middle, and the two halves are placed at locations far apart in
2129 memory.'' The traceback table has this property, since it
2130 includes the offset from the start of the function to the
2131 traceback table itself.
2133 System V.4 Powerpc's (and the embedded ABI derived from it) use a
2134 different traceback table located before the prologue. */
2135 #ifndef USING_SVR4_H
2136 if (! flag_inhibit_size_directive)
2138 char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
2139 int fixed_parms, float_parms, parm_info;
2142 /* Need label immediately before tbtab, so we can compute its offset
2143 from the function start. */
2146 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
2147 ASM_OUTPUT_LABEL (file, fname);
2149 /* The .tbtab pseudo-op can only be used for the first eight
2150 expressions, since it can't handle the possibly variable
2151 length fields that follow. However, if you omit the optional
2152 fields, the assembler outputs zeros for all optional fields
2153 anyways, giving each variable length field is minimum length
2154 (as defined in sys/debug.h). Thus we can not use the .tbtab
2155 pseudo-op at all. */
2157 /* An all-zero word flags the start of the tbtab, for debuggers
2158 that have to find it by searching forward from the entry
2159 point or from the current pc. */
2160 fprintf (file, "\t.long 0\n");
2162 /* Tbtab format type. Use format type 0. */
2163 fprintf (file, "\t.byte 0,");
2165 /* Language type. Unfortunately, there doesn't seem to be any
2166 official way to get this info, so we use language_string. C
2167 is 0. C++ is 9. No number defined for Obj-C, so use the
2168 value for C for now. */
2169 if (! strcmp (language_string, "GNU C")
2170 || ! strcmp (language_string, "GNU Obj-C"))
2172 else if (! strcmp (language_string, "GNU F77"))
2174 else if (! strcmp (language_string, "GNU Ada"))
2176 else if (! strcmp (language_string, "GNU PASCAL"))
2178 else if (! strcmp (language_string, "GNU C++"))
2182 fprintf (file, "%d,", i);
2184 /* 8 single bit fields: global linkage (not set for C extern linkage,
2185 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
2186 from start of procedure stored in tbtab, internal function, function
2187 has controlled storage, function has no toc, function uses fp,
2188 function logs/aborts fp operations. */
2189 /* Assume that fp operations are used if any fp reg must be saved. */
2190 fprintf (file, "%d,", (1 << 5) | ((first_fp_reg != 64) << 1));
2192 /* 6 bitfields: function is interrupt handler, name present in
2193 proc table, function calls alloca, on condition directives
2194 (controls stack walks, 3 bits), saves condition reg, saves
2196 /* The `function calls alloca' bit seems to be set whenever reg 31 is
2197 set up as a frame pointer, even when there is no alloca call. */
2198 fprintf (file, "%d,",
2199 ((1 << 6) | (frame_pointer_needed << 5)
2200 | (must_save_cr () << 1) | (regs_ever_live[65])));
2202 /* 3 bitfields: saves backchain, spare bit, number of fpr saved
2204 fprintf (file, "%d,",
2205 (must_push << 7) | (64 - first_fp_reg_to_save ()));
2207 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
2208 fprintf (file, "%d,", (32 - first_reg_to_save ()));
2211 /* Compute the parameter info from the function decl argument
2214 int next_parm_info_bit;
2216 next_parm_info_bit = 31;
2221 for (decl = DECL_ARGUMENTS (current_function_decl);
2222 decl; decl = TREE_CHAIN (decl))
2224 rtx parameter = DECL_INCOMING_RTL (decl);
2225 enum machine_mode mode = GET_MODE (parameter);
2227 if (GET_CODE (parameter) == REG)
2229 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2237 else if (mode == DFmode)
2242 /* If only one bit will fit, don't or in this entry. */
2243 if (next_parm_info_bit > 0)
2244 parm_info |= (bits << (next_parm_info_bit - 1));
2245 next_parm_info_bit -= 2;
2249 fixed_parms += ((GET_MODE_SIZE (mode)
2250 + (UNITS_PER_WORD - 1))
2252 next_parm_info_bit -= 1;
2258 /* Number of fixed point parameters. */
2259 /* This is actually the number of words of fixed point parameters; thus
2260 an 8 byte struct counts as 2; and thus the maximum value is 8. */
2261 fprintf (file, "%d,", fixed_parms);
2263 /* 2 bitfields: number of floating point parameters (7 bits), parameters
2265 /* This is actually the number of fp registers that hold parameters;
2266 and thus the maximum value is 13. */
2267 /* Set parameters on stack bit if parameters are not in their original
2268 registers, regardless of whether they are on the stack? Xlc
2269 seems to set the bit when not optimizing. */
2270 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
2272 /* Optional fields follow. Some are variable length. */
2274 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
2276 /* There is an entry for each parameter in a register, in the order that
2277 they occur in the parameter list. Any intervening arguments on the
2278 stack are ignored. If the list overflows a long (max possible length
2279 34 bits) then completely leave off all elements that don't fit. */
2280 /* Only emit this long if there was at least one parameter. */
2281 if (fixed_parms || float_parms)
2282 fprintf (file, "\t.long %d\n", parm_info);
2284 /* Offset from start of code to tb table. */
2285 fprintf (file, "\t.long ");
2286 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
2287 RS6000_OUTPUT_BASENAME (file, fname);
2288 fprintf (file, "-.");
2289 RS6000_OUTPUT_BASENAME (file, fname);
2290 fprintf (file, "\n");
2292 /* Interrupt handler mask. */
2293 /* Omit this long, since we never set the interrupt handler bit
2296 /* Number of CTL (controlled storage) anchors. */
2297 /* Omit this long, since the has_ctl bit is never set above. */
2299 /* Displacement into stack of each CTL anchor. */
2300 /* Omit this list of longs, because there are no CTL anchors. */
2302 /* Length of function name. */
2303 fprintf (file, "\t.short %d\n", strlen (fname));
2305 /* Function name. */
2306 assemble_string (fname, strlen (fname));
2308 /* Register for alloca automatic storage; this is always reg 31.
2309 Only emit this if the alloca bit was set above. */
2310 if (frame_pointer_needed)
2311 fprintf (file, "\t.byte 31\n");
2313 #endif /* !USING_SVR4_H */
2316 /* Output a TOC entry. We derive the entry name from what is
2320 output_toc (file, x, labelno)
2331 if (TARGET_MINIMAL_TOC)
2333 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
2334 fprintf (file, "%d = .-", labelno);
2335 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCTOC");
2336 fprintf (file, "1\n");
2339 #endif /* USING_SVR4_H */
2340 ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno);
2342 /* Handle FP constants specially. Note that if we have a minimal
2343 TOC, things we put here aren't actually in the TOC, so we can allow
2345 if (GET_CODE (x) == CONST_DOUBLE
2346 && GET_MODE (x) == DFmode
2347 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
2352 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2353 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
2354 if (TARGET_MINIMAL_TOC)
2355 fprintf (file, "\t.long %ld\n\t.long %ld\n", l[0], l[1]);
2357 fprintf (file, "\t.tc FD_%lx_%lx[TC],%ld,%ld\n",
2358 l[0], l[1], l[0], l[1]);
2361 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode
2362 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
2364 rtx val = operand_subword (x, 0, 0, SFmode);
2366 if (val == 0 || GET_CODE (val) != CONST_INT)
2369 if (TARGET_MINIMAL_TOC)
2370 fprintf (file, "\t.long %d\n", INTVAL (val));
2372 fprintf (file, "\t.tc FS_%x[TC],%d\n", INTVAL (val), INTVAL (val));
2376 if (GET_CODE (x) == CONST)
2378 base = XEXP (XEXP (x, 0), 0);
2379 offset = INTVAL (XEXP (XEXP (x, 0), 1));
2382 if (GET_CODE (base) == SYMBOL_REF)
2383 name = XSTR (base, 0);
2384 else if (GET_CODE (base) == LABEL_REF)
2385 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
2386 else if (GET_CODE (base) == CODE_LABEL)
2387 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
2391 if (TARGET_MINIMAL_TOC)
2392 fprintf (file, "\t.long ");
2395 fprintf (file, "\t.tc ");
2396 RS6000_OUTPUT_BASENAME (file, name);
2399 fprintf (file, ".N%d", - offset);
2401 fprintf (file, ".P%d", offset);
2403 fprintf (file, "[TC],");
2405 output_addr_const (file, x);
2406 fprintf (file, "\n");
2409 /* Output an assembler pseudo-op to write an ASCII string of N characters
2410 starting at P to FILE.
2412 On the RS/6000, we have to do this using the .byte operation and
2413 write out special characters outside the quoted string.
2414 Also, the assembler is broken; very long strings are truncated,
2415 so we must artificially break them up early. */
2418 output_ascii (file, p, n)
2424 int i, count_string;
2425 char *for_string = "\t.byte \"";
2426 char *for_decimal = "\t.byte ";
2427 char *to_close = NULL;
2430 for (i = 0; i < n; i++)
2433 if (c >= ' ' && c < 0177)
2436 fputs (for_string, file);
2439 /* Write two quotes to get one. */
2447 for_decimal = "\"\n\t.byte ";
2451 if (count_string >= 512)
2453 fputs (to_close, file);
2455 for_string = "\t.byte \"";
2456 for_decimal = "\t.byte ";
2464 fputs (for_decimal, file);
2465 fprintf (file, "%d", c);
2467 for_string = "\n\t.byte \"";
2474 /* Now close the string if we have written one. Then end the line. */
2476 fprintf (file, to_close);
2479 /* Generate a unique section name for FILENAME for a section type
2480 represented by SECTION_DESC. Output goes into BUF.
2482 SECTION_DESC can be any string, as long as it is different for each
2483 possible section type.
2485 We name the section in the same manner as xlc. The name begins with an
2486 underscore followed by the filename (after stripping any leading directory
2487 names) with the last period replaced by the string SECTION_DESC. If
2488 FILENAME does not contain a period, SECTION_DESC is appended to the end of
2492 rs6000_gen_section_name (buf, filename, section_desc)
2497 char *q, *after_last_slash, *last_period;
2501 after_last_slash = filename;
2502 for (q = filename; *q; q++)
2505 after_last_slash = q + 1;
2510 len = strlen (after_last_slash) + strlen (section_desc) + 2;
2511 *buf = (char *) permalloc (len);
2516 for (q = after_last_slash; *q; q++)
2518 if (q == last_period)
2520 strcpy (p, section_desc);
2521 p += strlen (section_desc);
2524 else if (isalnum (*q))
2528 if (last_period == 0)
2529 strcpy (p, section_desc);
2534 /* Write function profiler code. */
2537 output_function_profiler (file, labelno)
2544 /* The last used parameter register. */
2549 /* Set up a TOC entry for the profiler label. */
2551 ASM_OUTPUT_INTERNAL_LABEL (file, "LPC", labelno);
2552 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
2553 if (TARGET_MINIMAL_TOC)
2555 fprintf (file, "\t.long ");
2556 assemble_name (file, buf);
2557 fprintf (file, "\n");
2561 fprintf (file, "\t.tc\t");
2562 assemble_name (file, buf);
2563 fprintf (file, "[TC],");
2564 assemble_name (file, buf);
2565 fprintf (file, "\n");
2569 /* Figure out last used parameter register. The proper thing to do is
2570 to walk incoming args of the function. A function might have live
2571 parameter registers even if it has no incoming args. */
2573 for (last_parm_reg = 10;
2574 last_parm_reg > 2 && ! regs_ever_live [last_parm_reg];
2578 /* Save parameter registers in regs 23-30. Don't overwrite reg 31, since
2579 it might be set up as the frame pointer. */
2581 for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
2582 fprintf (file, "\tai %d,%d,0\n", j, i);
2584 /* Load location address into r3, and call mcount. */
2586 ASM_GENERATE_INTERNAL_LABEL (buf, "LPC", labelno);
2587 fprintf (file, "\tl 3,");
2588 assemble_name (file, buf);
2589 fprintf (file, "(2)\n\tbl .mcount\n");
2591 /* Restore parameter registers. */
2593 for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
2594 fprintf (file, "\tai %d,%d,0\n", i, j);
2598 /* Adjust the cost of a scheduling dependency. Return the new cost of
2599 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
2602 rs6000_adjust_cost (insn, link, dep_insn, cost)
2608 if (! recog_memoized (insn))
2611 if (REG_NOTE_KIND (link) != 0)
2614 if (REG_NOTE_KIND (link) == 0)
2616 /* Data dependency; DEP_INSN writes a register that INSN reads some
2619 /* Tell the first scheduling pass about the latency between a mtctr
2620 and bctr (and mtlr and br/blr). The first scheduling pass will not
2621 know about this latency since the mtctr instruction, which has the
2622 latency associated to it, will be generated by reload. */
2623 if (get_attr_type (insn) == TYPE_JMPREG)
2624 return TARGET_POWER ? 5 : 4;
2626 /* Fall out to return default cost. */