1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
57 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
60 #include "gstab.h" /* for N_SLINE */
63 #ifndef TARGET_NO_PROTOTYPE
64 #define TARGET_NO_PROTOTYPE 0
67 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
68 #define EASY_VECTOR_15_ADD_SELF(n) ((n) >= 0x10 && (n) <= 0x1e && !((n) & 1))
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack {
75 int first_gp_reg_save; /* first callee saved GP register used */
76 int first_fp_reg_save; /* first callee saved FP register used */
77 int first_altivec_reg_save; /* first callee saved AltiVec register used */
78 int lr_save_p; /* true if the link reg needs to be saved */
79 int cr_save_p; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask; /* mask of vec registers to save */
81 int toc_save_p; /* true if the TOC needs to be saved */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int toc_save_offset; /* offset to save the TOC pointer */
95 int varargs_save_offset; /* offset to save the varargs registers */
96 int ehrd_offset; /* offset to EH return data */
97 int reg_size; /* register size (4 or 8) */
98 int varargs_size; /* size to hold V.4 args passed in regs */
99 HOST_WIDE_INT vars_size; /* variable save area size */
100 int parm_size; /* outgoing parameter size */
101 int save_size; /* save area size */
102 int fixed_size; /* fixed size of stack frame */
103 int gp_size; /* size of saved GP registers */
104 int fp_size; /* size of saved FP registers */
105 int altivec_size; /* size of saved AltiVec registers */
106 int cr_size; /* size to hold CR if not in save_size */
107 int lr_size; /* size to hold LR if not in save_size */
108 int vrsave_size; /* size to hold VRSAVE if not in save_size */
109 int altivec_padding_size; /* size of altivec alignment padding if
111 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
112 int spe_padding_size;
113 int toc_size; /* size to hold TOC if not in save_size */
114 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
115 int spe_64bit_regs_used;
118 /* Target cpu type */
120 enum processor_type rs6000_cpu;
121 struct rs6000_cpu_select rs6000_select[3] =
123 /* switch name, tune arch */
124 { (const char *)0, "--with-cpu=", 1, 1 },
125 { (const char *)0, "-mcpu=", 1, 1 },
126 { (const char *)0, "-mtune=", 1, 0 },
129 /* Always emit branch hint bits. */
130 static GTY(()) bool rs6000_always_hint;
132 /* Schedule instructions for group formation. */
133 static GTY(()) bool rs6000_sched_groups;
135 /* Support adjust_priority scheduler hook
136 and -mprioritize-restricted-insns= option. */
137 const char *rs6000_sched_restricted_insns_priority_str;
138 int rs6000_sched_restricted_insns_priority;
140 /* Support for -msched-costly-dep option. */
141 const char *rs6000_sched_costly_dep_str;
142 enum rs6000_dependence_cost rs6000_sched_costly_dep;
144 /* Support for -minsert-sched-nops option. */
145 const char *rs6000_sched_insert_nops_str;
146 enum rs6000_nop_insertion rs6000_sched_insert_nops;
148 /* Support targetm.vectorize.builtin_mask_for_load. */
149 static GTY(()) tree altivec_builtin_mask_for_load;
150 /* Support targetm.vectorize.builtin_mask_for_store. */
151 static GTY(()) tree altivec_builtin_mask_for_store;
153 /* Size of long double */
154 const char *rs6000_long_double_size_string;
155 int rs6000_long_double_type_size;
157 /* Whether -mabi=altivec has appeared */
158 int rs6000_altivec_abi;
160 /* Whether VRSAVE instructions should be generated. */
161 int rs6000_altivec_vrsave;
163 /* String from -mvrsave= option. */
164 const char *rs6000_altivec_vrsave_string;
166 /* Nonzero if we want SPE ABI extensions. */
169 /* Whether isel instructions should be generated. */
172 /* Whether SPE simd instructions should be generated. */
175 /* Nonzero if floating point operations are done in the GPRs. */
176 int rs6000_float_gprs = 0;
178 /* String from -mfloat-gprs=. */
179 const char *rs6000_float_gprs_string;
181 /* String from -misel=. */
182 const char *rs6000_isel_string;
184 /* String from -mspe=. */
185 const char *rs6000_spe_string;
187 /* Set to nonzero once AIX common-mode calls have been defined. */
188 static GTY(()) int common_mode_defined;
190 /* Save information from a "cmpxx" operation until the branch or scc is
192 rtx rs6000_compare_op0, rs6000_compare_op1;
193 int rs6000_compare_fp_p;
195 /* Label number of label created for -mrelocatable, to call to so we can
196 get the address of the GOT section */
197 int rs6000_pic_labelno;
200 /* Which abi to adhere to */
201 const char *rs6000_abi_name;
203 /* Semantics of the small data area */
204 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
206 /* Which small data model to use */
207 const char *rs6000_sdata_name = (char *)0;
209 /* Counter for labels which are to be placed in .fixup. */
210 int fixuplabelno = 0;
213 /* Bit size of immediate TLS offsets and string from which it is decoded. */
214 int rs6000_tls_size = 32;
215 const char *rs6000_tls_size_string;
217 /* ABI enumeration available for subtarget to use. */
218 enum rs6000_abi rs6000_current_abi;
220 /* ABI string from -mabi= option. */
221 const char *rs6000_abi_string;
223 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
227 const char *rs6000_debug_name;
228 int rs6000_debug_stack; /* debug stack applications */
229 int rs6000_debug_arg; /* debug argument handling */
231 /* Value is TRUE if register/mode pair is accepatable. */
232 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
235 static GTY(()) tree opaque_V2SI_type_node;
236 static GTY(()) tree opaque_V2SF_type_node;
237 static GTY(()) tree opaque_p_V2SI_type_node;
238 static GTY(()) tree V16QI_type_node;
239 static GTY(()) tree V2SI_type_node;
240 static GTY(()) tree V2SF_type_node;
241 static GTY(()) tree V4HI_type_node;
242 static GTY(()) tree V4SI_type_node;
243 static GTY(()) tree V4SF_type_node;
244 static GTY(()) tree V8HI_type_node;
245 static GTY(()) tree unsigned_V16QI_type_node;
246 static GTY(()) tree unsigned_V8HI_type_node;
247 static GTY(()) tree unsigned_V4SI_type_node;
248 static GTY(()) tree bool_char_type_node; /* __bool char */
249 static GTY(()) tree bool_short_type_node; /* __bool short */
250 static GTY(()) tree bool_int_type_node; /* __bool int */
251 static GTY(()) tree pixel_type_node; /* __pixel */
252 static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */
253 static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */
254 static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */
255 static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */
257 int rs6000_warn_altivec_long = 1; /* On by default. */
258 const char *rs6000_warn_altivec_long_switch;
260 const char *rs6000_traceback_name;
262 traceback_default = 0,
268 /* Flag to say the TOC is initialized */
270 char toc_label_name[10];
272 /* Alias set for saves and restores from the rs6000 stack. */
273 static GTY(()) int rs6000_sr_alias_set;
275 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
276 The only place that looks at this is rs6000_set_default_type_attributes;
277 everywhere else should rely on the presence or absence of a longcall
278 attribute on the function declaration. */
279 int rs6000_default_long_calls;
280 const char *rs6000_longcall_switch;
282 /* Control alignment for fields within structures. */
283 /* String from -malign-XXXXX. */
284 const char *rs6000_alignment_string;
285 int rs6000_alignment_flags;
287 struct builtin_description
289 /* mask is not const because we're going to alter it below. This
290 nonsense will go away when we rewrite the -march infrastructure
291 to give us more target flag bits. */
293 const enum insn_code icode;
294 const char *const name;
295 const enum rs6000_builtins code;
298 /* Target cpu costs. */
300 struct processor_costs {
301 const int mulsi; /* cost of SImode multiplication. */
302 const int mulsi_const; /* cost of SImode multiplication by constant. */
303 const int mulsi_const9; /* cost of SImode mult by short constant. */
304 const int muldi; /* cost of DImode multiplication. */
305 const int divsi; /* cost of SImode division. */
306 const int divdi; /* cost of DImode division. */
307 const int fp; /* cost of simple SFmode and DFmode insns. */
308 const int dmul; /* cost of DFmode multiplication (and fmadd). */
309 const int sdiv; /* cost of SFmode division (fdivs). */
310 const int ddiv; /* cost of DFmode division (fdiv). */
313 const struct processor_costs *rs6000_cost;
315 /* Processor costs (relative to an add) */
317 /* Instruction size costs on 32bit processors. */
319 struct processor_costs size32_cost = {
320 COSTS_N_INSNS (1), /* mulsi */
321 COSTS_N_INSNS (1), /* mulsi_const */
322 COSTS_N_INSNS (1), /* mulsi_const9 */
323 COSTS_N_INSNS (1), /* muldi */
324 COSTS_N_INSNS (1), /* divsi */
325 COSTS_N_INSNS (1), /* divdi */
326 COSTS_N_INSNS (1), /* fp */
327 COSTS_N_INSNS (1), /* dmul */
328 COSTS_N_INSNS (1), /* sdiv */
329 COSTS_N_INSNS (1), /* ddiv */
332 /* Instruction size costs on 64bit processors. */
334 struct processor_costs size64_cost = {
335 COSTS_N_INSNS (1), /* mulsi */
336 COSTS_N_INSNS (1), /* mulsi_const */
337 COSTS_N_INSNS (1), /* mulsi_const9 */
338 COSTS_N_INSNS (1), /* muldi */
339 COSTS_N_INSNS (1), /* divsi */
340 COSTS_N_INSNS (1), /* divdi */
341 COSTS_N_INSNS (1), /* fp */
342 COSTS_N_INSNS (1), /* dmul */
343 COSTS_N_INSNS (1), /* sdiv */
344 COSTS_N_INSNS (1), /* ddiv */
347 /* Instruction costs on RIOS1 processors. */
349 struct processor_costs rios1_cost = {
350 COSTS_N_INSNS (5), /* mulsi */
351 COSTS_N_INSNS (4), /* mulsi_const */
352 COSTS_N_INSNS (3), /* mulsi_const9 */
353 COSTS_N_INSNS (5), /* muldi */
354 COSTS_N_INSNS (19), /* divsi */
355 COSTS_N_INSNS (19), /* divdi */
356 COSTS_N_INSNS (2), /* fp */
357 COSTS_N_INSNS (2), /* dmul */
358 COSTS_N_INSNS (19), /* sdiv */
359 COSTS_N_INSNS (19), /* ddiv */
362 /* Instruction costs on RIOS2 processors. */
364 struct processor_costs rios2_cost = {
365 COSTS_N_INSNS (2), /* mulsi */
366 COSTS_N_INSNS (2), /* mulsi_const */
367 COSTS_N_INSNS (2), /* mulsi_const9 */
368 COSTS_N_INSNS (2), /* muldi */
369 COSTS_N_INSNS (13), /* divsi */
370 COSTS_N_INSNS (13), /* divdi */
371 COSTS_N_INSNS (2), /* fp */
372 COSTS_N_INSNS (2), /* dmul */
373 COSTS_N_INSNS (17), /* sdiv */
374 COSTS_N_INSNS (17), /* ddiv */
377 /* Instruction costs on RS64A processors. */
379 struct processor_costs rs64a_cost = {
380 COSTS_N_INSNS (20), /* mulsi */
381 COSTS_N_INSNS (12), /* mulsi_const */
382 COSTS_N_INSNS (8), /* mulsi_const9 */
383 COSTS_N_INSNS (34), /* muldi */
384 COSTS_N_INSNS (65), /* divsi */
385 COSTS_N_INSNS (67), /* divdi */
386 COSTS_N_INSNS (4), /* fp */
387 COSTS_N_INSNS (4), /* dmul */
388 COSTS_N_INSNS (31), /* sdiv */
389 COSTS_N_INSNS (31), /* ddiv */
392 /* Instruction costs on MPCCORE processors. */
394 struct processor_costs mpccore_cost = {
395 COSTS_N_INSNS (2), /* mulsi */
396 COSTS_N_INSNS (2), /* mulsi_const */
397 COSTS_N_INSNS (2), /* mulsi_const9 */
398 COSTS_N_INSNS (2), /* muldi */
399 COSTS_N_INSNS (6), /* divsi */
400 COSTS_N_INSNS (6), /* divdi */
401 COSTS_N_INSNS (4), /* fp */
402 COSTS_N_INSNS (5), /* dmul */
403 COSTS_N_INSNS (10), /* sdiv */
404 COSTS_N_INSNS (17), /* ddiv */
407 /* Instruction costs on PPC403 processors. */
409 struct processor_costs ppc403_cost = {
410 COSTS_N_INSNS (4), /* mulsi */
411 COSTS_N_INSNS (4), /* mulsi_const */
412 COSTS_N_INSNS (4), /* mulsi_const9 */
413 COSTS_N_INSNS (4), /* muldi */
414 COSTS_N_INSNS (33), /* divsi */
415 COSTS_N_INSNS (33), /* divdi */
416 COSTS_N_INSNS (11), /* fp */
417 COSTS_N_INSNS (11), /* dmul */
418 COSTS_N_INSNS (11), /* sdiv */
419 COSTS_N_INSNS (11), /* ddiv */
422 /* Instruction costs on PPC405 processors. */
424 struct processor_costs ppc405_cost = {
425 COSTS_N_INSNS (5), /* mulsi */
426 COSTS_N_INSNS (4), /* mulsi_const */
427 COSTS_N_INSNS (3), /* mulsi_const9 */
428 COSTS_N_INSNS (5), /* muldi */
429 COSTS_N_INSNS (35), /* divsi */
430 COSTS_N_INSNS (35), /* divdi */
431 COSTS_N_INSNS (11), /* fp */
432 COSTS_N_INSNS (11), /* dmul */
433 COSTS_N_INSNS (11), /* sdiv */
434 COSTS_N_INSNS (11), /* ddiv */
437 /* Instruction costs on PPC440 processors. */
439 struct processor_costs ppc440_cost = {
440 COSTS_N_INSNS (3), /* mulsi */
441 COSTS_N_INSNS (2), /* mulsi_const */
442 COSTS_N_INSNS (2), /* mulsi_const9 */
443 COSTS_N_INSNS (3), /* muldi */
444 COSTS_N_INSNS (34), /* divsi */
445 COSTS_N_INSNS (34), /* divdi */
446 COSTS_N_INSNS (5), /* fp */
447 COSTS_N_INSNS (5), /* dmul */
448 COSTS_N_INSNS (19), /* sdiv */
449 COSTS_N_INSNS (33), /* ddiv */
452 /* Instruction costs on PPC601 processors. */
454 struct processor_costs ppc601_cost = {
455 COSTS_N_INSNS (5), /* mulsi */
456 COSTS_N_INSNS (5), /* mulsi_const */
457 COSTS_N_INSNS (5), /* mulsi_const9 */
458 COSTS_N_INSNS (5), /* muldi */
459 COSTS_N_INSNS (36), /* divsi */
460 COSTS_N_INSNS (36), /* divdi */
461 COSTS_N_INSNS (4), /* fp */
462 COSTS_N_INSNS (5), /* dmul */
463 COSTS_N_INSNS (17), /* sdiv */
464 COSTS_N_INSNS (31), /* ddiv */
467 /* Instruction costs on PPC603 processors. */
469 struct processor_costs ppc603_cost = {
470 COSTS_N_INSNS (5), /* mulsi */
471 COSTS_N_INSNS (3), /* mulsi_const */
472 COSTS_N_INSNS (2), /* mulsi_const9 */
473 COSTS_N_INSNS (5), /* muldi */
474 COSTS_N_INSNS (37), /* divsi */
475 COSTS_N_INSNS (37), /* divdi */
476 COSTS_N_INSNS (3), /* fp */
477 COSTS_N_INSNS (4), /* dmul */
478 COSTS_N_INSNS (18), /* sdiv */
479 COSTS_N_INSNS (33), /* ddiv */
482 /* Instruction costs on PPC604 processors. */
484 struct processor_costs ppc604_cost = {
485 COSTS_N_INSNS (4), /* mulsi */
486 COSTS_N_INSNS (4), /* mulsi_const */
487 COSTS_N_INSNS (4), /* mulsi_const9 */
488 COSTS_N_INSNS (4), /* muldi */
489 COSTS_N_INSNS (20), /* divsi */
490 COSTS_N_INSNS (20), /* divdi */
491 COSTS_N_INSNS (3), /* fp */
492 COSTS_N_INSNS (3), /* dmul */
493 COSTS_N_INSNS (18), /* sdiv */
494 COSTS_N_INSNS (32), /* ddiv */
497 /* Instruction costs on PPC604e processors. */
499 struct processor_costs ppc604e_cost = {
500 COSTS_N_INSNS (2), /* mulsi */
501 COSTS_N_INSNS (2), /* mulsi_const */
502 COSTS_N_INSNS (2), /* mulsi_const9 */
503 COSTS_N_INSNS (2), /* muldi */
504 COSTS_N_INSNS (20), /* divsi */
505 COSTS_N_INSNS (20), /* divdi */
506 COSTS_N_INSNS (3), /* fp */
507 COSTS_N_INSNS (3), /* dmul */
508 COSTS_N_INSNS (18), /* sdiv */
509 COSTS_N_INSNS (32), /* ddiv */
512 /* Instruction costs on PPC620 processors. */
514 struct processor_costs ppc620_cost = {
515 COSTS_N_INSNS (5), /* mulsi */
516 COSTS_N_INSNS (4), /* mulsi_const */
517 COSTS_N_INSNS (3), /* mulsi_const9 */
518 COSTS_N_INSNS (7), /* muldi */
519 COSTS_N_INSNS (21), /* divsi */
520 COSTS_N_INSNS (37), /* divdi */
521 COSTS_N_INSNS (3), /* fp */
522 COSTS_N_INSNS (3), /* dmul */
523 COSTS_N_INSNS (18), /* sdiv */
524 COSTS_N_INSNS (32), /* ddiv */
527 /* Instruction costs on PPC630 processors. */
529 struct processor_costs ppc630_cost = {
530 COSTS_N_INSNS (5), /* mulsi */
531 COSTS_N_INSNS (4), /* mulsi_const */
532 COSTS_N_INSNS (3), /* mulsi_const9 */
533 COSTS_N_INSNS (7), /* muldi */
534 COSTS_N_INSNS (21), /* divsi */
535 COSTS_N_INSNS (37), /* divdi */
536 COSTS_N_INSNS (3), /* fp */
537 COSTS_N_INSNS (3), /* dmul */
538 COSTS_N_INSNS (17), /* sdiv */
539 COSTS_N_INSNS (21), /* ddiv */
542 /* Instruction costs on PPC750 and PPC7400 processors. */
544 struct processor_costs ppc750_cost = {
545 COSTS_N_INSNS (5), /* mulsi */
546 COSTS_N_INSNS (3), /* mulsi_const */
547 COSTS_N_INSNS (2), /* mulsi_const9 */
548 COSTS_N_INSNS (5), /* muldi */
549 COSTS_N_INSNS (17), /* divsi */
550 COSTS_N_INSNS (17), /* divdi */
551 COSTS_N_INSNS (3), /* fp */
552 COSTS_N_INSNS (3), /* dmul */
553 COSTS_N_INSNS (17), /* sdiv */
554 COSTS_N_INSNS (31), /* ddiv */
557 /* Instruction costs on PPC7450 processors. */
559 struct processor_costs ppc7450_cost = {
560 COSTS_N_INSNS (4), /* mulsi */
561 COSTS_N_INSNS (3), /* mulsi_const */
562 COSTS_N_INSNS (3), /* mulsi_const9 */
563 COSTS_N_INSNS (4), /* muldi */
564 COSTS_N_INSNS (23), /* divsi */
565 COSTS_N_INSNS (23), /* divdi */
566 COSTS_N_INSNS (5), /* fp */
567 COSTS_N_INSNS (5), /* dmul */
568 COSTS_N_INSNS (21), /* sdiv */
569 COSTS_N_INSNS (35), /* ddiv */
572 /* Instruction costs on PPC8540 processors. */
574 struct processor_costs ppc8540_cost = {
575 COSTS_N_INSNS (4), /* mulsi */
576 COSTS_N_INSNS (4), /* mulsi_const */
577 COSTS_N_INSNS (4), /* mulsi_const9 */
578 COSTS_N_INSNS (4), /* muldi */
579 COSTS_N_INSNS (19), /* divsi */
580 COSTS_N_INSNS (19), /* divdi */
581 COSTS_N_INSNS (4), /* fp */
582 COSTS_N_INSNS (4), /* dmul */
583 COSTS_N_INSNS (29), /* sdiv */
584 COSTS_N_INSNS (29), /* ddiv */
587 /* Instruction costs on POWER4 and POWER5 processors. */
589 struct processor_costs power4_cost = {
590 COSTS_N_INSNS (3), /* mulsi */
591 COSTS_N_INSNS (2), /* mulsi_const */
592 COSTS_N_INSNS (2), /* mulsi_const9 */
593 COSTS_N_INSNS (4), /* muldi */
594 COSTS_N_INSNS (18), /* divsi */
595 COSTS_N_INSNS (34), /* divdi */
596 COSTS_N_INSNS (3), /* fp */
597 COSTS_N_INSNS (3), /* dmul */
598 COSTS_N_INSNS (17), /* sdiv */
599 COSTS_N_INSNS (17), /* ddiv */
603 static bool rs6000_function_ok_for_sibcall (tree, tree);
604 static int num_insns_constant_wide (HOST_WIDE_INT);
605 static void validate_condition_mode (enum rtx_code, enum machine_mode);
606 static rtx rs6000_generate_compare (enum rtx_code);
607 static void rs6000_maybe_dead (rtx);
608 static void rs6000_emit_stack_tie (void);
609 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
610 static rtx spe_synthesize_frame_save (rtx);
611 static bool spe_func_has_64bit_regs_p (void);
612 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
614 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
615 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
616 static unsigned rs6000_hash_constant (rtx);
617 static unsigned toc_hash_function (const void *);
618 static int toc_hash_eq (const void *, const void *);
619 static int constant_pool_expr_1 (rtx, int *, int *);
620 static bool constant_pool_expr_p (rtx);
621 static bool toc_relative_expr_p (rtx);
622 static bool legitimate_small_data_p (enum machine_mode, rtx);
623 static bool legitimate_indexed_address_p (rtx, int);
624 static bool legitimate_indirect_address_p (rtx, int);
625 static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode);
626 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
627 static struct machine_function * rs6000_init_machine_status (void);
628 static bool rs6000_assemble_integer (rtx, unsigned int, int);
629 #ifdef HAVE_GAS_HIDDEN
630 static void rs6000_assemble_visibility (tree, int);
632 static int rs6000_ra_ever_killed (void);
633 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
634 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
635 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
636 static const char *rs6000_mangle_fundamental_type (tree);
637 extern const struct attribute_spec rs6000_attribute_table[];
638 static void rs6000_set_default_type_attributes (tree);
639 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
640 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
641 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
643 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
644 static bool rs6000_return_in_memory (tree, tree);
645 static void rs6000_file_start (void);
647 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
648 static void rs6000_elf_asm_out_constructor (rtx, int);
649 static void rs6000_elf_asm_out_destructor (rtx, int);
650 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
651 static void rs6000_elf_unique_section (tree, int);
652 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
653 unsigned HOST_WIDE_INT);
654 static void rs6000_elf_encode_section_info (tree, rtx, int)
656 static bool rs6000_elf_in_small_data_p (tree);
659 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
660 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
661 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
662 static void rs6000_xcoff_unique_section (tree, int);
663 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
664 unsigned HOST_WIDE_INT);
665 static const char * rs6000_xcoff_strip_name_encoding (const char *);
666 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
667 static void rs6000_xcoff_file_start (void);
668 static void rs6000_xcoff_file_end (void);
671 static bool rs6000_binds_local_p (tree);
673 static int rs6000_variable_issue (FILE *, int, rtx, int);
674 static bool rs6000_rtx_costs (rtx, int, int, int *);
675 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
676 static bool is_microcoded_insn (rtx);
677 static int is_dispatch_slot_restricted (rtx);
678 static bool is_cracked_insn (rtx);
679 static bool is_branch_slot_insn (rtx);
680 static int rs6000_adjust_priority (rtx, int);
681 static int rs6000_issue_rate (void);
682 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
683 static rtx get_next_active_insn (rtx, rtx);
684 static bool insn_terminates_group_p (rtx , enum group_termination);
685 static bool is_costly_group (rtx *, rtx);
686 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
687 static int redefine_groups (FILE *, int, rtx, rtx);
688 static int pad_groups (FILE *, int, rtx, rtx);
689 static void rs6000_sched_finish (FILE *, int);
690 static int rs6000_use_sched_lookahead (void);
691 static tree rs6000_builtin_mask_for_load (void);
692 static tree rs6000_builtin_mask_for_store (void);
694 static void rs6000_init_builtins (void);
695 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
696 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
697 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
698 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
699 static void altivec_init_builtins (void);
700 static void rs6000_common_init_builtins (void);
701 static void rs6000_init_libfuncs (void);
703 static void enable_mask_for_builtins (struct builtin_description *, int,
704 enum rs6000_builtins,
705 enum rs6000_builtins);
706 static tree build_opaque_vector_type (tree, int);
707 static void spe_init_builtins (void);
708 static rtx spe_expand_builtin (tree, rtx, bool *);
709 static rtx spe_expand_stv_builtin (enum insn_code, tree);
710 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
711 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
712 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
713 static rs6000_stack_t *rs6000_stack_info (void);
714 static void debug_stack_info (rs6000_stack_t *);
716 static rtx altivec_expand_builtin (tree, rtx, bool *);
717 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
718 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
719 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
720 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
721 static rtx altivec_expand_predicate_builtin (enum insn_code,
722 const char *, tree, rtx);
723 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
724 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
725 static void rs6000_parse_abi_options (void);
726 static void rs6000_parse_alignment_option (void);
727 static void rs6000_parse_tls_size_option (void);
728 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
729 static void rs6000_parse_float_gprs_option (void);
730 static int first_altivec_reg_to_save (void);
731 static unsigned int compute_vrsave_mask (void);
732 static void compute_save_world_info(rs6000_stack_t *info_ptr);
733 static void is_altivec_return_reg (rtx, void *);
734 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
735 int easy_vector_constant (rtx, enum machine_mode);
736 static int easy_vector_same (rtx, enum machine_mode);
737 static int easy_vector_splat_const (int, enum machine_mode);
738 static bool is_ev64_opaque_type (tree);
739 static rtx rs6000_dwarf_register_span (rtx);
740 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
741 static rtx rs6000_tls_get_addr (void);
742 static rtx rs6000_got_sym (void);
743 static inline int rs6000_tls_symbol_ref_1 (rtx *, void *);
744 static const char *rs6000_get_some_local_dynamic_name (void);
745 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
746 static rtx rs6000_complex_function_value (enum machine_mode);
747 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
748 enum machine_mode, tree);
749 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
750 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
751 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
752 enum machine_mode, tree,
754 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
757 static void macho_branch_islands (void);
758 static void add_compiler_branch_island (tree, tree, int);
759 static int no_previous_def (tree function_name);
760 static tree get_prev_label (tree function_name);
761 static void rs6000_darwin_file_start (void);
764 static tree rs6000_build_builtin_va_list (void);
765 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
766 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
767 static bool rs6000_vector_mode_supported_p (enum machine_mode);
768 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
770 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
772 static int get_vsel_insn (enum machine_mode);
773 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
776 const int INSN_NOT_AVAILABLE = -1;
777 static enum machine_mode rs6000_eh_return_filter_mode (void);
779 /* Hash table stuff for keeping track of TOC entries. */
781 struct toc_hash_struct GTY(())
783 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
784 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
786 enum machine_mode key_mode;
790 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
792 /* Default register names. */
793 char rs6000_reg_names[][8] =
795 "0", "1", "2", "3", "4", "5", "6", "7",
796 "8", "9", "10", "11", "12", "13", "14", "15",
797 "16", "17", "18", "19", "20", "21", "22", "23",
798 "24", "25", "26", "27", "28", "29", "30", "31",
799 "0", "1", "2", "3", "4", "5", "6", "7",
800 "8", "9", "10", "11", "12", "13", "14", "15",
801 "16", "17", "18", "19", "20", "21", "22", "23",
802 "24", "25", "26", "27", "28", "29", "30", "31",
803 "mq", "lr", "ctr","ap",
804 "0", "1", "2", "3", "4", "5", "6", "7",
806 /* AltiVec registers. */
807 "0", "1", "2", "3", "4", "5", "6", "7",
808 "8", "9", "10", "11", "12", "13", "14", "15",
809 "16", "17", "18", "19", "20", "21", "22", "23",
810 "24", "25", "26", "27", "28", "29", "30", "31",
816 #ifdef TARGET_REGNAMES
817 static const char alt_reg_names[][8] =
819 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
820 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
821 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
822 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
823 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
824 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
825 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
826 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
827 "mq", "lr", "ctr", "ap",
828 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
830 /* AltiVec registers. */
831 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
832 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
833 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
834 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
841 #ifndef MASK_STRICT_ALIGN
842 #define MASK_STRICT_ALIGN 0
844 #ifndef TARGET_PROFILE_KERNEL
845 #define TARGET_PROFILE_KERNEL 0
848 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
849 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
851 /* Return 1 for a symbol ref for a thread-local storage symbol. */
852 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
853 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
855 /* Initialize the GCC target structure. */
856 #undef TARGET_ATTRIBUTE_TABLE
857 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
858 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
859 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
861 #undef TARGET_ASM_ALIGNED_DI_OP
862 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
864 /* Default unaligned ops are only provided for ELF. Find the ops needed
865 for non-ELF systems. */
866 #ifndef OBJECT_FORMAT_ELF
868 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
870 #undef TARGET_ASM_UNALIGNED_HI_OP
871 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
872 #undef TARGET_ASM_UNALIGNED_SI_OP
873 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
874 #undef TARGET_ASM_UNALIGNED_DI_OP
875 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
878 #undef TARGET_ASM_UNALIGNED_HI_OP
879 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
880 #undef TARGET_ASM_UNALIGNED_SI_OP
881 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
882 #undef TARGET_ASM_UNALIGNED_DI_OP
883 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
884 #undef TARGET_ASM_ALIGNED_DI_OP
885 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
889 /* This hook deals with fixups for relocatable code and DI-mode objects
891 #undef TARGET_ASM_INTEGER
892 #define TARGET_ASM_INTEGER rs6000_assemble_integer
894 #ifdef HAVE_GAS_HIDDEN
895 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
896 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
899 #undef TARGET_HAVE_TLS
900 #define TARGET_HAVE_TLS HAVE_AS_TLS
902 #undef TARGET_CANNOT_FORCE_CONST_MEM
903 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
905 #undef TARGET_ASM_FUNCTION_PROLOGUE
906 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
907 #undef TARGET_ASM_FUNCTION_EPILOGUE
908 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
910 #undef TARGET_SCHED_VARIABLE_ISSUE
911 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
913 #undef TARGET_SCHED_ISSUE_RATE
914 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
915 #undef TARGET_SCHED_ADJUST_COST
916 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
917 #undef TARGET_SCHED_ADJUST_PRIORITY
918 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
919 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
920 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
921 #undef TARGET_SCHED_FINISH
922 #define TARGET_SCHED_FINISH rs6000_sched_finish
924 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
925 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
927 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
928 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
930 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_STORE
931 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_STORE rs6000_builtin_mask_for_store
933 #undef TARGET_INIT_BUILTINS
934 #define TARGET_INIT_BUILTINS rs6000_init_builtins
936 #undef TARGET_EXPAND_BUILTIN
937 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
939 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
940 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
942 #undef TARGET_INIT_LIBFUNCS
943 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
946 #undef TARGET_BINDS_LOCAL_P
947 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
950 #undef TARGET_ASM_OUTPUT_MI_THUNK
951 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
953 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
954 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
956 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
957 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
959 #undef TARGET_RTX_COSTS
960 #define TARGET_RTX_COSTS rs6000_rtx_costs
961 #undef TARGET_ADDRESS_COST
962 #define TARGET_ADDRESS_COST hook_int_rtx_0
964 #undef TARGET_VECTOR_OPAQUE_P
965 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
967 #undef TARGET_DWARF_REGISTER_SPAN
968 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
970 /* On rs6000, function arguments are promoted, as are function return
972 #undef TARGET_PROMOTE_FUNCTION_ARGS
973 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
974 #undef TARGET_PROMOTE_FUNCTION_RETURN
975 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
977 #undef TARGET_RETURN_IN_MEMORY
978 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
980 #undef TARGET_SETUP_INCOMING_VARARGS
981 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
983 /* Always strict argument naming on rs6000. */
984 #undef TARGET_STRICT_ARGUMENT_NAMING
985 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
986 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
987 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
988 #undef TARGET_SPLIT_COMPLEX_ARG
989 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
990 #undef TARGET_MUST_PASS_IN_STACK
991 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
992 #undef TARGET_PASS_BY_REFERENCE
993 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
995 #undef TARGET_BUILD_BUILTIN_VA_LIST
996 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
998 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
999 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1001 #undef TARGET_EH_RETURN_FILTER_MODE
1002 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1004 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1005 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1007 struct gcc_target targetm = TARGET_INITIALIZER;
1010 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1013 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1015 /* The GPRs can hold any mode, but values bigger than one register
1016 cannot go past R31. */
1017 if (INT_REGNO_P (regno))
1018 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1020 /* The float registers can only hold floating modes and DImode. */
1021 if (FP_REGNO_P (regno))
1023 (GET_MODE_CLASS (mode) == MODE_FLOAT
1024 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1025 || (GET_MODE_CLASS (mode) == MODE_INT
1026 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1028 /* The CR register can only hold CC modes. */
1029 if (CR_REGNO_P (regno))
1030 return GET_MODE_CLASS (mode) == MODE_CC;
1032 if (XER_REGNO_P (regno))
1033 return mode == PSImode;
1035 /* AltiVec only in AldyVec registers. */
1036 if (ALTIVEC_REGNO_P (regno))
1037 return ALTIVEC_VECTOR_MODE (mode);
1039 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1040 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1043 /* We cannot put TImode anywhere except general register and it must be
1044 able to fit within the register set. */
1046 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1049 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1051 rs6000_init_hard_regno_mode_ok (void)
1055 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1056 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1057 if (rs6000_hard_regno_mode_ok (r, m))
1058 rs6000_hard_regno_mode_ok_p[m][r] = true;
1061 /* If not otherwise specified by a target, make 'long double' equivalent to
1064 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1065 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1068 /* Override command line options. Mostly we process the processor
1069 type and sometimes adjust other TARGET_ options. */
1072 rs6000_override_options (const char *default_cpu)
1075 struct rs6000_cpu_select *ptr;
1078 /* Simplifications for entries below. */
1081 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1082 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1085 /* This table occasionally claims that a processor does not support
1086 a particular feature even though it does, but the feature is slower
1087 than the alternative. Thus, it shouldn't be relied on as a
1088 complete description of the processor's support.
1090 Please keep this list in order, and don't forget to update the
1091 documentation in invoke.texi when adding a new processor or
1095 const char *const name; /* Canonical processor name. */
1096 const enum processor_type processor; /* Processor type enum value. */
1097 const int target_enable; /* Target flags to enable. */
1098 } const processor_target_table[]
1099 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1100 {"403", PROCESSOR_PPC403,
1101 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1102 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1103 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1104 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1105 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1106 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1107 {"601", PROCESSOR_PPC601,
1108 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1109 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1110 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1111 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1112 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1113 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1114 {"620", PROCESSOR_PPC620,
1115 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1116 {"630", PROCESSOR_PPC630,
1117 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1118 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1119 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1120 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1121 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1122 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1123 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1124 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1125 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1126 /* 8548 has a dummy entry for now. */
1127 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1128 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1129 {"970", PROCESSOR_POWER4,
1130 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1131 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1132 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1133 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1134 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1135 {"G5", PROCESSOR_POWER4,
1136 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1137 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1138 {"power2", PROCESSOR_POWER,
1139 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1140 {"power3", PROCESSOR_PPC630,
1141 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1142 {"power4", PROCESSOR_POWER4,
1143 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1144 {"power5", PROCESSOR_POWER5,
1145 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1146 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1147 {"powerpc64", PROCESSOR_POWERPC64,
1148 POWERPC_BASE_MASK | MASK_POWERPC64},
1149 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1150 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1151 {"rios2", PROCESSOR_RIOS2,
1152 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1153 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1154 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1155 {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
1158 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1160 /* Some OSs don't support saving the high part of 64-bit registers on
1161 context switch. Other OSs don't support saving Altivec registers.
1162 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1163 settings; if the user wants either, the user must explicitly specify
1164 them and we won't interfere with the user's specification. */
1167 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1168 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1169 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1173 rs6000_init_hard_regno_mode_ok ();
1175 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1176 #ifdef OS_MISSING_POWERPC64
1177 if (OS_MISSING_POWERPC64)
1178 set_masks &= ~MASK_POWERPC64;
1180 #ifdef OS_MISSING_ALTIVEC
1181 if (OS_MISSING_ALTIVEC)
1182 set_masks &= ~MASK_ALTIVEC;
1185 /* Don't override these by the processor default if given explicitly. */
1186 set_masks &= ~(target_flags_explicit
1187 & (MASK_MULTIPLE | MASK_STRING | MASK_SOFT_FLOAT));
1189 /* Identify the processor type. */
1190 rs6000_select[0].string = default_cpu;
1191 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1193 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1195 ptr = &rs6000_select[i];
1196 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1198 for (j = 0; j < ptt_size; j++)
1199 if (! strcmp (ptr->string, processor_target_table[j].name))
1201 if (ptr->set_tune_p)
1202 rs6000_cpu = processor_target_table[j].processor;
1204 if (ptr->set_arch_p)
1206 target_flags &= ~set_masks;
1207 target_flags |= (processor_target_table[j].target_enable
1214 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1221 /* If we are optimizing big endian systems for space, use the load/store
1222 multiple and string instructions. */
1223 if (BYTES_BIG_ENDIAN && optimize_size)
1224 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1226 /* Don't allow -mmultiple or -mstring on little endian systems
1227 unless the cpu is a 750, because the hardware doesn't support the
1228 instructions used in little endian mode, and causes an alignment
1229 trap. The 750 does not cause an alignment trap (except when the
1230 target is unaligned). */
1232 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1234 if (TARGET_MULTIPLE)
1236 target_flags &= ~MASK_MULTIPLE;
1237 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1238 warning ("-mmultiple is not supported on little endian systems");
1243 target_flags &= ~MASK_STRING;
1244 if ((target_flags_explicit & MASK_STRING) != 0)
1245 warning ("-mstring is not supported on little endian systems");
1249 /* Set debug flags */
1250 if (rs6000_debug_name)
1252 if (! strcmp (rs6000_debug_name, "all"))
1253 rs6000_debug_stack = rs6000_debug_arg = 1;
1254 else if (! strcmp (rs6000_debug_name, "stack"))
1255 rs6000_debug_stack = 1;
1256 else if (! strcmp (rs6000_debug_name, "arg"))
1257 rs6000_debug_arg = 1;
1259 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1262 if (rs6000_traceback_name)
1264 if (! strncmp (rs6000_traceback_name, "full", 4))
1265 rs6000_traceback = traceback_full;
1266 else if (! strncmp (rs6000_traceback_name, "part", 4))
1267 rs6000_traceback = traceback_part;
1268 else if (! strncmp (rs6000_traceback_name, "no", 2))
1269 rs6000_traceback = traceback_none;
1271 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1272 rs6000_traceback_name);
1275 /* Set size of long double */
1276 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1277 if (rs6000_long_double_size_string)
1280 int size = strtol (rs6000_long_double_size_string, &tail, 10);
1281 if (*tail != '\0' || (size != 64 && size != 128))
1282 error ("Unknown switch -mlong-double-%s",
1283 rs6000_long_double_size_string);
1285 rs6000_long_double_type_size = size;
1288 /* Set Altivec ABI as default for powerpc64 linux. */
1289 if (TARGET_ELF && TARGET_64BIT)
1291 rs6000_altivec_abi = 1;
1292 rs6000_altivec_vrsave = 1;
1295 /* Handle -mabi= options. */
1296 rs6000_parse_abi_options ();
1298 /* Handle -malign-XXXXX option. */
1299 rs6000_parse_alignment_option ();
1301 rs6000_parse_float_gprs_option ();
1303 /* Handle generic -mFOO=YES/NO options. */
1304 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
1305 &rs6000_altivec_vrsave);
1306 rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
1308 rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
1310 /* Handle -mtls-size option. */
1311 rs6000_parse_tls_size_option ();
1313 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1314 SUBTARGET_OVERRIDE_OPTIONS;
1316 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1317 SUBSUBTARGET_OVERRIDE_OPTIONS;
1319 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1320 SUB3TARGET_OVERRIDE_OPTIONS;
1326 error ("AltiVec and E500 instructions cannot coexist");
1328 /* The e500 does not have string instructions, and we set
1329 MASK_STRING above when optimizing for size. */
1330 if ((target_flags & MASK_STRING) != 0)
1331 target_flags = target_flags & ~MASK_STRING;
1333 /* No SPE means 64-bit long doubles, even if an E500. */
1334 if (rs6000_spe_string != 0
1335 && !strcmp (rs6000_spe_string, "no"))
1336 rs6000_long_double_type_size = 64;
1338 else if (rs6000_select[1].string != NULL)
1340 /* For the powerpc-eabispe configuration, we set all these by
1341 default, so let's unset them if we manually set another
1342 CPU that is not the E500. */
1343 if (rs6000_abi_string == 0)
1345 if (rs6000_spe_string == 0)
1347 if (rs6000_float_gprs_string == 0)
1348 rs6000_float_gprs = 0;
1349 if (rs6000_isel_string == 0)
1351 if (rs6000_long_double_size_string == 0)
1352 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1355 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1356 && rs6000_cpu != PROCESSOR_POWER5);
1357 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1358 || rs6000_cpu == PROCESSOR_POWER5);
1360 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
1361 using TARGET_OPTIONS to handle a toggle switch, but we're out of
1362 bits in target_flags so TARGET_SWITCHES cannot be used.
1363 Assumption here is that rs6000_longcall_switch points into the
1364 text of the complete option, rather than being a copy, so we can
1365 scan back for the presence or absence of the no- modifier. */
1366 if (rs6000_longcall_switch)
1368 const char *base = rs6000_longcall_switch;
1369 while (base[-1] != 'm') base--;
1371 if (*rs6000_longcall_switch != '\0')
1372 error ("invalid option %qs", base);
1373 rs6000_default_long_calls = (base[0] != 'n');
1376 /* Handle -m(no-)warn-altivec-long similarly. */
1377 if (rs6000_warn_altivec_long_switch)
1379 const char *base = rs6000_warn_altivec_long_switch;
1380 while (base[-1] != 'm') base--;
1382 if (*rs6000_warn_altivec_long_switch != '\0')
1383 error ("invalid option %qs", base);
1384 rs6000_warn_altivec_long = (base[0] != 'n');
1387 /* Handle -mprioritize-restricted-insns option. */
1388 rs6000_sched_restricted_insns_priority
1389 = (rs6000_sched_groups ? 1 : 0);
1390 if (rs6000_sched_restricted_insns_priority_str)
1391 rs6000_sched_restricted_insns_priority =
1392 atoi (rs6000_sched_restricted_insns_priority_str);
1394 /* Handle -msched-costly-dep option. */
1395 rs6000_sched_costly_dep
1396 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1397 if (rs6000_sched_costly_dep_str)
1399 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1400 rs6000_sched_costly_dep = no_dep_costly;
1401 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1402 rs6000_sched_costly_dep = all_deps_costly;
1403 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1404 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1405 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1406 rs6000_sched_costly_dep = store_to_load_dep_costly;
1408 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1411 /* Handle -minsert-sched-nops option. */
1412 rs6000_sched_insert_nops
1413 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1414 if (rs6000_sched_insert_nops_str)
1416 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1417 rs6000_sched_insert_nops = sched_finish_none;
1418 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1419 rs6000_sched_insert_nops = sched_finish_pad_groups;
1420 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1421 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1423 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1426 #ifdef TARGET_REGNAMES
1427 /* If the user desires alternate register names, copy in the
1428 alternate names now. */
1429 if (TARGET_REGNAMES)
1430 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1433 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1434 If -maix-struct-return or -msvr4-struct-return was explicitly
1435 used, don't override with the ABI default. */
1436 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
1438 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
1439 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
1441 target_flags |= MASK_AIX_STRUCT_RET;
1444 if (TARGET_LONG_DOUBLE_128
1445 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1446 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1448 /* Allocate an alias set for register saves & restores from stack. */
1449 rs6000_sr_alias_set = new_alias_set ();
1452 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1454 /* We can only guarantee the availability of DI pseudo-ops when
1455 assembling for 64-bit targets. */
1458 targetm.asm_out.aligned_op.di = NULL;
1459 targetm.asm_out.unaligned_op.di = NULL;
1462 /* Set branch target alignment, if not optimizing for size. */
1465 if (rs6000_sched_groups)
1467 if (align_functions <= 0)
1468 align_functions = 16;
1469 if (align_jumps <= 0)
1471 if (align_loops <= 0)
1474 if (align_jumps_max_skip <= 0)
1475 align_jumps_max_skip = 15;
1476 if (align_loops_max_skip <= 0)
1477 align_loops_max_skip = 15;
1480 /* Arrange to save and restore machine status around nested functions. */
1481 init_machine_status = rs6000_init_machine_status;
1483 /* We should always be splitting complex arguments, but we can't break
1484 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1485 if (DEFAULT_ABI != ABI_AIX)
1486 targetm.calls.split_complex_arg = NULL;
1488 /* Initialize rs6000_cost with the appropriate target costs. */
1490 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1494 case PROCESSOR_RIOS1:
1495 rs6000_cost = &rios1_cost;
1498 case PROCESSOR_RIOS2:
1499 rs6000_cost = &rios2_cost;
1502 case PROCESSOR_RS64A:
1503 rs6000_cost = &rs64a_cost;
1506 case PROCESSOR_MPCCORE:
1507 rs6000_cost = &mpccore_cost;
1510 case PROCESSOR_PPC403:
1511 rs6000_cost = &ppc403_cost;
1514 case PROCESSOR_PPC405:
1515 rs6000_cost = &ppc405_cost;
1518 case PROCESSOR_PPC440:
1519 rs6000_cost = &ppc440_cost;
1522 case PROCESSOR_PPC601:
1523 rs6000_cost = &ppc601_cost;
1526 case PROCESSOR_PPC603:
1527 rs6000_cost = &ppc603_cost;
1530 case PROCESSOR_PPC604:
1531 rs6000_cost = &ppc604_cost;
1534 case PROCESSOR_PPC604e:
1535 rs6000_cost = &ppc604e_cost;
1538 case PROCESSOR_PPC620:
1539 rs6000_cost = &ppc620_cost;
1542 case PROCESSOR_PPC630:
1543 rs6000_cost = &ppc630_cost;
1546 case PROCESSOR_PPC750:
1547 case PROCESSOR_PPC7400:
1548 rs6000_cost = &ppc750_cost;
1551 case PROCESSOR_PPC7450:
1552 rs6000_cost = &ppc7450_cost;
1555 case PROCESSOR_PPC8540:
1556 rs6000_cost = &ppc8540_cost;
1559 case PROCESSOR_POWER4:
1560 case PROCESSOR_POWER5:
1561 rs6000_cost = &power4_cost;
1569 /* Implement targetm.vectorize.builtin_mask_for_load. */
1571 rs6000_builtin_mask_for_load (void)
1574 return altivec_builtin_mask_for_load;
1579 /* Implement targetm.vectorize.builtin_mask_for_store. */
1581 rs6000_builtin_mask_for_store (void)
1584 return altivec_builtin_mask_for_store;
1589 /* Handle generic options of the form -mfoo=yes/no.
1590 NAME is the option name.
1591 VALUE is the option value.
1592 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1593 whether the option value is 'yes' or 'no' respectively. */
1595 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1599 else if (!strcmp (value, "yes"))
1601 else if (!strcmp (value, "no"))
1604 error ("unknown -m%s= option specified: '%s'", name, value);
1607 /* Handle -mabi= options. */
1609 rs6000_parse_abi_options (void)
1611 if (rs6000_abi_string == 0)
1613 else if (! strcmp (rs6000_abi_string, "altivec"))
1615 rs6000_altivec_abi = 1;
1618 else if (! strcmp (rs6000_abi_string, "no-altivec"))
1619 rs6000_altivec_abi = 0;
1620 else if (! strcmp (rs6000_abi_string, "spe"))
1623 rs6000_altivec_abi = 0;
1624 if (!TARGET_SPE_ABI)
1625 error ("not configured for ABI: '%s'", rs6000_abi_string);
1628 else if (! strcmp (rs6000_abi_string, "no-spe"))
1631 error ("unknown ABI specified: '%s'", rs6000_abi_string);
1634 /* Handle -mfloat-gprs= options. */
1636 rs6000_parse_float_gprs_option (void)
1638 if (rs6000_float_gprs_string == 0)
1640 else if (! strcmp (rs6000_float_gprs_string, "yes")
1641 || ! strcmp (rs6000_float_gprs_string, "single"))
1642 rs6000_float_gprs = 1;
1643 else if (! strcmp (rs6000_float_gprs_string, "double"))
1644 rs6000_float_gprs = 2;
1645 else if (! strcmp (rs6000_float_gprs_string, "no"))
1646 rs6000_float_gprs = 0;
1648 error ("invalid option for -mfloat-gprs");
1651 /* Handle -malign-XXXXXX options. */
1653 rs6000_parse_alignment_option (void)
1655 if (rs6000_alignment_string == 0)
1657 else if (! strcmp (rs6000_alignment_string, "power"))
1658 rs6000_alignment_flags = MASK_ALIGN_POWER;
1659 else if (! strcmp (rs6000_alignment_string, "natural"))
1660 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1662 error ("unknown -malign-XXXXX option specified: '%s'",
1663 rs6000_alignment_string);
1666 /* Validate and record the size specified with the -mtls-size option. */
1669 rs6000_parse_tls_size_option (void)
1671 if (rs6000_tls_size_string == 0)
1673 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1674 rs6000_tls_size = 16;
1675 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1676 rs6000_tls_size = 32;
1677 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1678 rs6000_tls_size = 64;
1680 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1684 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1688 /* Do anything needed at the start of the asm file. */
1691 rs6000_file_start (void)
1695 const char *start = buffer;
1696 struct rs6000_cpu_select *ptr;
1697 const char *default_cpu = TARGET_CPU_DEFAULT;
1698 FILE *file = asm_out_file;
1700 default_file_start ();
1702 #ifdef TARGET_BI_ARCH
1703 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1707 if (flag_verbose_asm)
1709 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1710 rs6000_select[0].string = default_cpu;
1712 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1714 ptr = &rs6000_select[i];
1715 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1717 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1722 #ifdef USING_ELFOS_H
1723 switch (rs6000_sdata)
1725 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1726 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1727 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1728 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1731 if (rs6000_sdata && g_switch_value)
1733 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1745 /* Return nonzero if this function is known to have a null epilogue. */
1748 direct_return (void)
1750 if (reload_completed)
1752 rs6000_stack_t *info = rs6000_stack_info ();
1754 if (info->first_gp_reg_save == 32
1755 && info->first_fp_reg_save == 64
1756 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1757 && ! info->lr_save_p
1758 && ! info->cr_save_p
1759 && info->vrsave_mask == 0
1767 /* Returns 1 always. */
1770 any_operand (rtx op ATTRIBUTE_UNUSED,
1771 enum machine_mode mode ATTRIBUTE_UNUSED)
1776 /* Returns 1 always. */
1779 any_parallel_operand (rtx op ATTRIBUTE_UNUSED,
1780 enum machine_mode mode ATTRIBUTE_UNUSED)
1785 /* Returns 1 if op is the count register. */
1788 count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1790 if (GET_CODE (op) != REG)
1793 if (REGNO (op) == COUNT_REGISTER_REGNUM)
1796 if (REGNO (op) > FIRST_PSEUDO_REGISTER)
1802 /* Returns 1 if op is an altivec register. */
1805 altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1807 return (register_operand (op, mode)
1808 && (GET_CODE (op) != REG
1809 || REGNO (op) > FIRST_PSEUDO_REGISTER
1810 || ALTIVEC_REGNO_P (REGNO (op))));
1814 xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1816 if (GET_CODE (op) != REG)
1819 if (XER_REGNO_P (REGNO (op)))
1825 /* Return 1 if OP is a signed 8-bit constant. Int multiplication
1826 by such constants completes more quickly. */
1829 s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1831 return (GET_CODE (op) == CONST_INT
1832 && (INTVAL (op) >= -128 && INTVAL (op) <= 127));
1835 /* Return 1 if OP is a constant that can fit in a D field. */
1838 short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1840 return (GET_CODE (op) == CONST_INT
1841 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
1844 /* Similar for an unsigned D field. */
1847 u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1849 return (GET_CODE (op) == CONST_INT
1850 && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K'));
1853 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
1856 non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1858 return (GET_CODE (op) == CONST_INT
1859 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
1862 /* Returns 1 if OP is a CONST_INT that is a positive value
1863 and an exact power of 2. */
1866 exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1868 return (GET_CODE (op) == CONST_INT
1870 && exact_log2 (INTVAL (op)) >= 0);
1873 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
1877 gpc_reg_operand (rtx op, enum machine_mode mode)
1879 return (register_operand (op, mode)
1880 && (GET_CODE (op) != REG
1881 || (REGNO (op) >= ARG_POINTER_REGNUM
1882 && !XER_REGNO_P (REGNO (op)))
1883 || REGNO (op) < MQ_REGNO));
1886 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1890 cc_reg_operand (rtx op, enum machine_mode mode)
1892 return (register_operand (op, mode)
1893 && (GET_CODE (op) != REG
1894 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1895 || CR_REGNO_P (REGNO (op))));
1898 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1899 CR field that isn't CR0. */
1902 cc_reg_not_cr0_operand (rtx op, enum machine_mode mode)
1904 return (register_operand (op, mode)
1905 && (GET_CODE (op) != REG
1906 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1907 || CR_REGNO_NOT_CR0_P (REGNO (op))));
1910 /* Returns 1 if OP is either a constant integer valid for a D-field or
1911 a non-special register. If a register, it must be in the proper
1912 mode unless MODE is VOIDmode. */
1915 reg_or_short_operand (rtx op, enum machine_mode mode)
1917 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1920 /* Similar, except check if the negation of the constant would be
1921 valid for a D-field. Don't allow a constant zero, since all the
1922 patterns that call this predicate use "addic r1,r2,-constant" on
1923 a constant value to set a carry when r2 is greater or equal to
1924 "constant". That doesn't work for zero. */
1927 reg_or_neg_short_operand (rtx op, enum machine_mode mode)
1929 if (GET_CODE (op) == CONST_INT)
1930 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P') && INTVAL (op) != 0;
1932 return gpc_reg_operand (op, mode);
1935 /* Returns 1 if OP is either a constant integer valid for a DS-field or
1936 a non-special register. If a register, it must be in the proper
1937 mode unless MODE is VOIDmode. */
1940 reg_or_aligned_short_operand (rtx op, enum machine_mode mode)
1942 if (gpc_reg_operand (op, mode))
1944 else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3))
1951 /* Return 1 if the operand is either a register or an integer whose
1952 high-order 16 bits are zero. */
1955 reg_or_u_short_operand (rtx op, enum machine_mode mode)
1957 return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1960 /* Return 1 is the operand is either a non-special register or ANY
1961 constant integer. */
1964 reg_or_cint_operand (rtx op, enum machine_mode mode)
1966 return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
1969 /* Return 1 is the operand is either a non-special register or ANY
1970 32-bit signed constant integer. */
1973 reg_or_arith_cint_operand (rtx op, enum machine_mode mode)
1975 return (gpc_reg_operand (op, mode)
1976 || (GET_CODE (op) == CONST_INT
1977 #if HOST_BITS_PER_WIDE_INT != 32
1978 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
1979 < (unsigned HOST_WIDE_INT) 0x100000000ll)
1984 /* Return 1 is the operand is either a non-special register or a 32-bit
1985 signed constant integer valid for 64-bit addition. */
1988 reg_or_add_cint64_operand (rtx op, enum machine_mode mode)
1990 return (gpc_reg_operand (op, mode)
1991 || (GET_CODE (op) == CONST_INT
1992 #if HOST_BITS_PER_WIDE_INT == 32
1993 && INTVAL (op) < 0x7fff8000
1995 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
2001 /* Return 1 is the operand is either a non-special register or a 32-bit
2002 signed constant integer valid for 64-bit subtraction. */
2005 reg_or_sub_cint64_operand (rtx op, enum machine_mode mode)
2007 return (gpc_reg_operand (op, mode)
2008 || (GET_CODE (op) == CONST_INT
2009 #if HOST_BITS_PER_WIDE_INT == 32
2010 && (- INTVAL (op)) < 0x7fff8000
2012 && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
2018 /* Return 1 is the operand is either a non-special register or ANY
2019 32-bit unsigned constant integer. */
2022 reg_or_logical_cint_operand (rtx op, enum machine_mode mode)
2024 if (GET_CODE (op) == CONST_INT)
2026 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
2028 if (GET_MODE_BITSIZE (mode) <= 32)
2031 if (INTVAL (op) < 0)
2035 return ((INTVAL (op) & GET_MODE_MASK (mode)
2036 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0);
2038 else if (GET_CODE (op) == CONST_DOUBLE)
2040 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2044 return CONST_DOUBLE_HIGH (op) == 0;
2047 return gpc_reg_operand (op, mode);
2050 /* Return 1 if the operand is an operand that can be loaded via the GOT. */
2053 got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2055 return (GET_CODE (op) == SYMBOL_REF
2056 || GET_CODE (op) == CONST
2057 || GET_CODE (op) == LABEL_REF);
2060 /* Return 1 if the operand is a simple references that can be loaded via
2061 the GOT (labels involving addition aren't allowed). */
2064 got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2066 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
2069 /* Return the number of instructions it takes to form a constant in an
2070 integer register. */
2073 num_insns_constant_wide (HOST_WIDE_INT value)
2075 /* signed constant loadable with {cal|addi} */
2076 if (CONST_OK_FOR_LETTER_P (value, 'I'))
2079 /* constant loadable with {cau|addis} */
2080 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
2083 #if HOST_BITS_PER_WIDE_INT == 64
2084 else if (TARGET_POWERPC64)
2086 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2087 HOST_WIDE_INT high = value >> 31;
2089 if (high == 0 || high == -1)
2095 return num_insns_constant_wide (high) + 1;
2097 return (num_insns_constant_wide (high)
2098 + num_insns_constant_wide (low) + 1);
2107 num_insns_constant (rtx op, enum machine_mode mode)
2109 if (GET_CODE (op) == CONST_INT)
2111 #if HOST_BITS_PER_WIDE_INT == 64
2112 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2113 && mask64_operand (op, mode))
2117 return num_insns_constant_wide (INTVAL (op));
2120 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
2125 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2126 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2127 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2130 else if (GET_CODE (op) == CONST_DOUBLE)
2136 int endian = (WORDS_BIG_ENDIAN == 0);
2138 if (mode == VOIDmode || mode == DImode)
2140 high = CONST_DOUBLE_HIGH (op);
2141 low = CONST_DOUBLE_LOW (op);
2145 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2146 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2148 low = l[1 - endian];
2152 return (num_insns_constant_wide (low)
2153 + num_insns_constant_wide (high));
2157 if (high == 0 && low >= 0)
2158 return num_insns_constant_wide (low);
2160 else if (high == -1 && low < 0)
2161 return num_insns_constant_wide (low);
2163 else if (mask64_operand (op, mode))
2167 return num_insns_constant_wide (high) + 1;
2170 return (num_insns_constant_wide (high)
2171 + num_insns_constant_wide (low) + 1);
2179 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
2180 register with one instruction per word. We only do this if we can
2181 safely read CONST_DOUBLE_{LOW,HIGH}. */
2184 easy_fp_constant (rtx op, enum machine_mode mode)
2186 if (GET_CODE (op) != CONST_DOUBLE
2187 || GET_MODE (op) != mode
2188 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
2191 /* Consider all constants with -msoft-float to be easy. */
2192 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
2196 /* If we are using V.4 style PIC, consider all constants to be hard. */
2197 if (flag_pic && DEFAULT_ABI == ABI_V4)
2200 #ifdef TARGET_RELOCATABLE
2201 /* Similarly if we are using -mrelocatable, consider all constants
2203 if (TARGET_RELOCATABLE)
2212 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2213 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
2215 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
2216 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
2217 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
2218 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
2221 else if (mode == DFmode)
2226 if (TARGET_E500_DOUBLE)
2229 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2230 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
2232 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
2233 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
2236 else if (mode == SFmode)
2241 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2242 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2244 return num_insns_constant_wide (l) == 1;
2247 else if (mode == DImode)
2248 return ((TARGET_POWERPC64
2249 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
2250 || (num_insns_constant (op, DImode) <= 2));
2252 else if (mode == SImode)
2258 /* Returns the constant for the splat instruction, if exists. */
2261 easy_vector_splat_const (int cst, enum machine_mode mode)
2266 if (EASY_VECTOR_15 (cst)
2267 || EASY_VECTOR_15_ADD_SELF (cst))
2269 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
2275 if (EASY_VECTOR_15 (cst)
2276 || EASY_VECTOR_15_ADD_SELF (cst))
2278 if ((cst & 0xff) != ((cst >> 8) & 0xff))
2284 if (EASY_VECTOR_15 (cst)
2285 || EASY_VECTOR_15_ADD_SELF (cst))
2294 /* Return nonzero if all elements of a vector have the same value. */
2297 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2301 units = CONST_VECTOR_NUNITS (op);
2303 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2304 for (i = 1; i < units; ++i)
2305 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
2307 if (i == units && easy_vector_splat_const (cst, mode))
2312 /* Return 1 if the operand is a CONST_INT and can be put into a
2313 register without using memory. */
2316 easy_vector_constant (rtx op, enum machine_mode mode)
2320 if (GET_CODE (op) != CONST_VECTOR
2325 if (zero_constant (op, mode)
2326 && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
2327 || (TARGET_SPE && SPE_VECTOR_MODE (mode))))
2330 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
2333 if (TARGET_SPE && mode == V1DImode)
2336 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2337 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
2339 /* Limit SPE vectors to 15 bits signed. These we can generate with:
2341 evmergelo r0, r0, r0
2344 I don't know how efficient it would be to allow bigger constants,
2345 considering we'll have an extra 'ori' for every 'li'. I doubt 5
2346 instructions is better than a 64-bit memory load, but I don't
2347 have the e500 timing specs. */
2348 if (TARGET_SPE && mode == V2SImode
2349 && cst >= -0x7fff && cst <= 0x7fff
2350 && cst2 >= -0x7fff && cst2 <= 0x7fff)
2354 && easy_vector_same (op, mode))
2356 cst = easy_vector_splat_const (cst, mode);
2357 if (EASY_VECTOR_15_ADD_SELF (cst)
2358 || EASY_VECTOR_15 (cst))
2364 /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */
2367 easy_vector_constant_add_self (rtx op, enum machine_mode mode)
2371 && GET_CODE (op) == CONST_VECTOR
2372 && easy_vector_same (op, mode))
2374 cst = easy_vector_splat_const (INTVAL (CONST_VECTOR_ELT (op, 0)), mode);
2375 if (EASY_VECTOR_15_ADD_SELF (cst))
2381 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
2384 gen_easy_vector_constant_add_self (rtx op)
2388 units = GET_MODE_NUNITS (GET_MODE (op));
2389 v = rtvec_alloc (units);
2391 for (i = 0; i < units; i++)
2393 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
2394 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
2398 output_vec_const_move (rtx *operands)
2401 enum machine_mode mode;
2407 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2408 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2409 mode = GET_MODE (dest);
2413 if (zero_constant (vec, mode))
2414 return "vxor %0,%0,%0";
2415 else if (easy_vector_constant (vec, mode))
2417 operands[1] = GEN_INT (cst);
2421 if (EASY_VECTOR_15 (cst))
2423 operands[1] = GEN_INT (cst);
2424 return "vspltisw %0,%1";
2426 else if (EASY_VECTOR_15_ADD_SELF (cst))
2432 if (EASY_VECTOR_15 (cst))
2434 operands[1] = GEN_INT (cst);
2435 return "vspltish %0,%1";
2437 else if (EASY_VECTOR_15_ADD_SELF (cst))
2443 if (EASY_VECTOR_15 (cst))
2445 operands[1] = GEN_INT (cst);
2446 return "vspltisb %0,%1";
2448 else if (EASY_VECTOR_15_ADD_SELF (cst))
2461 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2462 pattern of V1DI, V4HI, and V2SF.
2464 FIXME: We should probably return # and add post reload
2465 splitters for these, but this way is so easy ;-). */
2466 operands[1] = GEN_INT (cst);
2467 operands[2] = GEN_INT (cst2);
2469 return "li %0,%1\n\tevmergelo %0,%0,%0";
2471 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2477 /* Return 1 if the operand is the constant 0. This works for scalars
2478 as well as vectors. */
2480 zero_constant (rtx op, enum machine_mode mode)
2482 return op == CONST0_RTX (mode);
2485 /* Return 1 if the operand is 0.0. */
2487 zero_fp_constant (rtx op, enum machine_mode mode)
2489 return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
2492 /* Return 1 if the operand is in volatile memory. Note that during
2493 the RTL generation phase, memory_operand does not return TRUE for
2494 volatile memory references. So this function allows us to
2495 recognize volatile references where its safe. */
2498 volatile_mem_operand (rtx op, enum machine_mode mode)
2500 if (GET_CODE (op) != MEM)
2503 if (!MEM_VOLATILE_P (op))
2506 if (mode != GET_MODE (op))
2509 if (reload_completed)
2510 return memory_operand (op, mode);
2512 if (reload_in_progress)
2513 return strict_memory_address_p (mode, XEXP (op, 0));
2515 return memory_address_p (mode, XEXP (op, 0));
2518 /* Return 1 if the operand is an offsettable memory operand. */
2521 offsettable_mem_operand (rtx op, enum machine_mode mode)
2523 return ((GET_CODE (op) == MEM)
2524 && offsettable_address_p (reload_completed || reload_in_progress,
2525 mode, XEXP (op, 0)));
2528 /* Return 1 if the operand is either an easy FP constant (see above) or
2532 mem_or_easy_const_operand (rtx op, enum machine_mode mode)
2534 return memory_operand (op, mode) || easy_fp_constant (op, mode);
2537 /* Return 1 if the operand is either a non-special register or an item
2538 that can be used as the operand of a `mode' add insn. */
2541 add_operand (rtx op, enum machine_mode mode)
2543 if (GET_CODE (op) == CONST_INT)
2544 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
2545 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
2547 return gpc_reg_operand (op, mode);
2550 /* Return 1 if OP is a constant but not a valid add_operand. */
2553 non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2555 return (GET_CODE (op) == CONST_INT
2556 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
2557 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
2560 /* Return 1 if the operand is a non-special register or a constant that
2561 can be used as the operand of an OR or XOR insn on the RS/6000. */
2564 logical_operand (rtx op, enum machine_mode mode)
2566 HOST_WIDE_INT opl, oph;
2568 if (gpc_reg_operand (op, mode))
2571 if (GET_CODE (op) == CONST_INT)
2573 opl = INTVAL (op) & GET_MODE_MASK (mode);
2575 #if HOST_BITS_PER_WIDE_INT <= 32
2576 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
2580 else if (GET_CODE (op) == CONST_DOUBLE)
2582 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
2585 opl = CONST_DOUBLE_LOW (op);
2586 oph = CONST_DOUBLE_HIGH (op);
2593 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
2594 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
2597 /* Return 1 if C is a constant that is not a logical operand (as
2598 above), but could be split into one. */
2601 non_logical_cint_operand (rtx op, enum machine_mode mode)
2603 return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
2604 && ! logical_operand (op, mode)
2605 && reg_or_logical_cint_operand (op, mode));
2608 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
2609 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
2610 Reject all ones and all zeros, since these should have been optimized
2611 away and confuse the making of MB and ME. */
2614 mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2616 HOST_WIDE_INT c, lsb;
2618 if (GET_CODE (op) != CONST_INT)
2623 /* Fail in 64-bit mode if the mask wraps around because the upper
2624 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
2625 if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
2628 /* We don't change the number of transitions by inverting,
2629 so make sure we start with the LS bit zero. */
2633 /* Reject all zeros or all ones. */
2637 /* Find the first transition. */
2640 /* Invert to look for a second transition. */
2643 /* Erase first transition. */
2646 /* Find the second transition (if any). */
2649 /* Match if all the bits above are 1's (or c is zero). */
2653 /* Return 1 for the PowerPC64 rlwinm corner case. */
2656 mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2658 HOST_WIDE_INT c, lsb;
2660 if (GET_CODE (op) != CONST_INT)
2665 if ((c & 0x80000001) != 0x80000001)
2679 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
2680 It is if there are no more than one 1->0 or 0->1 transitions.
2681 Reject all zeros, since zero should have been optimized away and
2682 confuses the making of MB and ME. */
2685 mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2687 if (GET_CODE (op) == CONST_INT)
2689 HOST_WIDE_INT c, lsb;
2693 /* Reject all zeros. */
2697 /* We don't change the number of transitions by inverting,
2698 so make sure we start with the LS bit zero. */
2702 /* Find the transition, and check that all bits above are 1's. */
2705 /* Match if all the bits above are 1's (or c is zero). */
2712 mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED,
2715 if (GET_CODE (op) == CONST_INT)
2717 HOST_WIDE_INT c, lsb;
2722 /* Disallow all zeros. */
2726 /* We can use a single rlwinm insn if no upper bits of C are set
2727 AND there are zero, one or two transitions in the _whole_ of
2729 one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff);
2731 /* We don't change the number of transitions by inverting,
2732 so make sure we start with the LS bit zero. */
2736 /* Find the first transition. */
2739 /* Invert to look for a second transition. */
2742 /* Erase first transition. */
2745 /* Find the second transition. */
2748 /* Invert to look for a third transition. */
2751 /* Erase second transition. */
2754 if (one_ok && !(allow_one || c))
2757 /* Find the third transition (if any). */
2760 /* Match if all the bits above are 1's (or c is zero). */
2766 /* Like mask64_operand, but allow up to three transitions. This
2767 predicate is used by insn patterns that generate two rldicl or
2768 rldicr machine insns. */
2769 int mask64_2_operand (rtx op, enum machine_mode mode)
2771 return mask64_1or2_operand (op, mode, false);
2774 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2775 implement ANDing by the mask IN. */
2777 build_mask64_2_operands (rtx in, rtx *out)
2779 #if HOST_BITS_PER_WIDE_INT >= 64
2780 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2783 if (GET_CODE (in) != CONST_INT)
2789 /* Assume c initially something like 0x00fff000000fffff. The idea
2790 is to rotate the word so that the middle ^^^^^^ group of zeros
2791 is at the MS end and can be cleared with an rldicl mask. We then
2792 rotate back and clear off the MS ^^ group of zeros with a
2794 c = ~c; /* c == 0xff000ffffff00000 */
2795 lsb = c & -c; /* lsb == 0x0000000000100000 */
2796 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2797 c = ~c; /* c == 0x00fff000000fffff */
2798 c &= -lsb; /* c == 0x00fff00000000000 */
2799 lsb = c & -c; /* lsb == 0x0000100000000000 */
2800 c = ~c; /* c == 0xff000fffffffffff */
2801 c &= -lsb; /* c == 0xff00000000000000 */
2803 while ((lsb >>= 1) != 0)
2804 shift++; /* shift == 44 on exit from loop */
2805 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2806 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2807 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2811 /* Assume c initially something like 0xff000f0000000000. The idea
2812 is to rotate the word so that the ^^^ middle group of zeros
2813 is at the LS end and can be cleared with an rldicr mask. We then
2814 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2816 lsb = c & -c; /* lsb == 0x0000010000000000 */
2817 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2818 c = ~c; /* c == 0x00fff0ffffffffff */
2819 c &= -lsb; /* c == 0x00fff00000000000 */
2820 lsb = c & -c; /* lsb == 0x0000100000000000 */
2821 c = ~c; /* c == 0xff000fffffffffff */
2822 c &= -lsb; /* c == 0xff00000000000000 */
2824 while ((lsb >>= 1) != 0)
2825 shift++; /* shift == 44 on exit from loop */
2826 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2827 m1 >>= shift; /* m1 == 0x0000000000000fff */
2828 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2831 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2832 masks will be all 1's. We are guaranteed more than one transition. */
2833 out[0] = GEN_INT (64 - shift);
2834 out[1] = GEN_INT (m1);
2835 out[2] = GEN_INT (shift);
2836 out[3] = GEN_INT (m2);
2844 /* Return 1 if the operand is either a non-special register or a constant
2845 that can be used as the operand of a PowerPC64 logical AND insn. */
2848 and64_operand (rtx op, enum machine_mode mode)
2850 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2851 return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
2853 return (logical_operand (op, mode) || mask64_operand (op, mode));
2856 /* Like the above, but also match constants that can be implemented
2857 with two rldicl or rldicr insns. */
2860 and64_2_operand (rtx op, enum machine_mode mode)
2862 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2863 return gpc_reg_operand (op, mode) || mask64_1or2_operand (op, mode, true);
2865 return logical_operand (op, mode) || mask64_1or2_operand (op, mode, true);
2868 /* Return 1 if the operand is either a non-special register or a
2869 constant that can be used as the operand of an RS/6000 logical AND insn. */
2872 and_operand (rtx op, enum machine_mode mode)
2874 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2875 return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
2877 return (logical_operand (op, mode) || mask_operand (op, mode));
2880 /* Return 1 if the operand is a general register or memory operand. */
2883 reg_or_mem_operand (rtx op, enum machine_mode mode)
2885 return (gpc_reg_operand (op, mode)
2886 || memory_operand (op, mode)
2887 || macho_lo_sum_memory_operand (op, mode)
2888 || volatile_mem_operand (op, mode));
2891 /* Return 1 if the operand is a general register or memory operand without
2892 pre_inc or pre_dec which produces invalid form of PowerPC lwa
2896 lwa_operand (rtx op, enum machine_mode mode)
2900 if (reload_completed && GET_CODE (inner) == SUBREG)
2901 inner = SUBREG_REG (inner);
2903 return gpc_reg_operand (inner, mode)
2904 || (memory_operand (inner, mode)
2905 && GET_CODE (XEXP (inner, 0)) != PRE_INC
2906 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
2907 && (GET_CODE (XEXP (inner, 0)) != PLUS
2908 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
2909 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
2912 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */
2915 symbol_ref_operand (rtx op, enum machine_mode mode)
2917 if (mode != VOIDmode && GET_MODE (op) != mode)
2920 return (GET_CODE (op) == SYMBOL_REF
2921 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)));
2924 /* Return 1 if the operand, used inside a MEM, is a valid first argument
2925 to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */
2928 call_operand (rtx op, enum machine_mode mode)
2930 if (mode != VOIDmode && GET_MODE (op) != mode)
2933 return (GET_CODE (op) == SYMBOL_REF
2934 || (GET_CODE (op) == REG
2935 && (REGNO (op) == LINK_REGISTER_REGNUM
2936 || REGNO (op) == COUNT_REGISTER_REGNUM
2937 || REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2940 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
2944 current_file_function_operand (rtx op,
2945 enum machine_mode mode ATTRIBUTE_UNUSED)
2947 return (GET_CODE (op) == SYMBOL_REF
2948 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
2949 && (SYMBOL_REF_LOCAL_P (op)
2950 || (op == XEXP (DECL_RTL (current_function_decl), 0))));
2953 /* Return 1 if this operand is a valid input for a move insn. */
2956 input_operand (rtx op, enum machine_mode mode)
2958 /* Memory is always valid. */
2959 if (memory_operand (op, mode))
2962 /* For floating-point, easy constants are valid. */
2963 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2965 && easy_fp_constant (op, mode))
2968 /* Allow any integer constant. */
2969 if (GET_MODE_CLASS (mode) == MODE_INT
2970 && (GET_CODE (op) == CONST_INT
2971 || GET_CODE (op) == CONST_DOUBLE))
2974 /* Allow easy vector constants. */
2975 if (GET_CODE (op) == CONST_VECTOR
2976 && easy_vector_constant (op, mode))
2979 /* For floating-point or multi-word mode, the only remaining valid type
2981 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2982 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
2983 return register_operand (op, mode);
2985 /* The only cases left are integral modes one word or smaller (we
2986 do not get called for MODE_CC values). These can be in any
2988 if (register_operand (op, mode))
2991 /* A SYMBOL_REF referring to the TOC is valid. */
2992 if (legitimate_constant_pool_address_p (op))
2995 /* A constant pool expression (relative to the TOC) is valid */
2996 if (toc_relative_expr_p (op))
2999 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
3001 if (DEFAULT_ABI == ABI_V4
3002 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
3003 && small_data_operand (op, Pmode))
3010 /* Darwin, AIX increases natural record alignment to doubleword if the first
3011 field is an FP double while the FP fields remain word aligned. */
3014 rs6000_special_round_type_align (tree type, int computed, int specified)
3016 tree field = TYPE_FIELDS (type);
3018 /* Skip all the static variables only if ABI is greater than
3020 while (field != NULL && TREE_CODE (field) == VAR_DECL)
3021 field = TREE_CHAIN (field);
3023 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
3024 return MAX (computed, specified);
3026 return MAX (MAX (computed, specified), 64);
3029 /* Return 1 for an operand in small memory on V.4/eabi. */
3032 small_data_operand (rtx op ATTRIBUTE_UNUSED,
3033 enum machine_mode mode ATTRIBUTE_UNUSED)
3038 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
3041 if (DEFAULT_ABI != ABI_V4)
3044 if (GET_CODE (op) == SYMBOL_REF)
3047 else if (GET_CODE (op) != CONST
3048 || GET_CODE (XEXP (op, 0)) != PLUS
3049 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
3050 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
3055 rtx sum = XEXP (op, 0);
3056 HOST_WIDE_INT summand;
3058 /* We have to be careful here, because it is the referenced address
3059 that must be 32k from _SDA_BASE_, not just the symbol. */
3060 summand = INTVAL (XEXP (sum, 1));
3061 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
3064 sym_ref = XEXP (sum, 0);
3067 return SYMBOL_REF_SMALL_P (sym_ref);
3073 /* Return true, if operand is a memory operand and has a
3074 displacement divisible by 4. */
3077 word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3082 if (!memory_operand (op, mode))
3085 addr = XEXP (op, 0);
3086 if (GET_CODE (addr) == PLUS
3087 && GET_CODE (XEXP (addr, 0)) == REG
3088 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
3089 off = INTVAL (XEXP (addr, 1));
3091 return (off % 4) == 0;
3094 /* Return true if either operand is a general purpose register. */
3097 gpr_or_gpr_p (rtx op0, rtx op1)
3099 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
3100 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
3104 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3107 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
3109 switch (GET_CODE(op))
3112 if (RS6000_SYMBOL_REF_TLS_P (op))
3114 else if (CONSTANT_POOL_ADDRESS_P (op))
3116 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
3124 else if (! strcmp (XSTR (op, 0), toc_label_name))
3133 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
3134 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
3136 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
3145 constant_pool_expr_p (rtx op)
3149 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
3153 toc_relative_expr_p (rtx op)
3157 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3161 legitimate_constant_pool_address_p (rtx x)
3164 && GET_CODE (x) == PLUS
3165 && GET_CODE (XEXP (x, 0)) == REG
3166 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3167 && constant_pool_expr_p (XEXP (x, 1)));
3171 legitimate_small_data_p (enum machine_mode mode, rtx x)
3173 return (DEFAULT_ABI == ABI_V4
3174 && !flag_pic && !TARGET_TOC
3175 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3176 && small_data_operand (x, mode));
3179 /* SPE offset addressing is limited to 5-bits worth of double words. */
3180 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3183 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3185 unsigned HOST_WIDE_INT offset, extra;
3187 if (GET_CODE (x) != PLUS)
3189 if (GET_CODE (XEXP (x, 0)) != REG)
3191 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3193 if (legitimate_constant_pool_address_p (x))
3195 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3198 offset = INTVAL (XEXP (x, 1));
3206 /* AltiVec vector modes. Only reg+reg addressing is valid here,
3207 which leaves the only valid constant offset of zero, which by
3208 canonicalization rules is also invalid. */
3215 /* SPE vector modes. */
3216 return SPE_CONST_OFFSET_OK (offset);
3219 if (TARGET_E500_DOUBLE)
3220 return SPE_CONST_OFFSET_OK (offset);
3223 if (mode == DFmode || !TARGET_POWERPC64)
3225 else if (offset & 3)
3231 if (mode == TFmode || !TARGET_POWERPC64)
3233 else if (offset & 3)
3244 return (offset < 0x10000) && (offset + extra < 0x10000);
3248 legitimate_indexed_address_p (rtx x, int strict)
3252 if (GET_CODE (x) != PLUS)
3258 if (!REG_P (op0) || !REG_P (op1))
3261 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
3262 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3263 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3264 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
3268 legitimate_indirect_address_p (rtx x, int strict)
3270 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3274 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3276 if (!TARGET_MACHO || !flag_pic
3277 || mode != SImode || GET_CODE(x) != MEM)
3281 if (GET_CODE (x) != LO_SUM)
3283 if (GET_CODE (XEXP (x, 0)) != REG)
3285 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3289 return CONSTANT_P (x);
3293 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3295 if (GET_CODE (x) != LO_SUM)
3297 if (GET_CODE (XEXP (x, 0)) != REG)
3299 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3301 if (TARGET_E500_DOUBLE && mode == DFmode)
3305 if (TARGET_ELF || TARGET_MACHO)
3307 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3311 if (GET_MODE_NUNITS (mode) != 1)
3313 if (GET_MODE_BITSIZE (mode) > 64)
3316 return CONSTANT_P (x);
3323 /* Try machine-dependent ways of modifying an illegitimate address
3324 to be legitimate. If we find one, return the new, valid address.
3325 This is used from only one place: `memory_address' in explow.c.
3327 OLDX is the address as it was before break_out_memory_refs was
3328 called. In some cases it is useful to look at this to decide what
3331 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3333 It is always safe for this function to do nothing. It exists to
3334 recognize opportunities to optimize the output.
3336 On RS/6000, first check for the sum of a register with a constant
3337 integer that is out of range. If so, generate code to add the
3338 constant with the low-order 16 bits masked to the register and force
3339 this result into another register (this can be done with `cau').
3340 Then generate an address of REG+(CONST&0xffff), allowing for the
3341 possibility of bit 16 being a one.
3343 Then check for the sum of a register and something not constant, try to
3344 load the other things into a register and return the sum. */
3347 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3348 enum machine_mode mode)
3350 if (GET_CODE (x) == SYMBOL_REF)
3352 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3354 return rs6000_legitimize_tls_address (x, model);
3357 if (GET_CODE (x) == PLUS
3358 && GET_CODE (XEXP (x, 0)) == REG
3359 && GET_CODE (XEXP (x, 1)) == CONST_INT
3360 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
3362 HOST_WIDE_INT high_int, low_int;
3364 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3365 high_int = INTVAL (XEXP (x, 1)) - low_int;
3366 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3367 GEN_INT (high_int)), 0);
3368 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3370 else if (GET_CODE (x) == PLUS
3371 && GET_CODE (XEXP (x, 0)) == REG
3372 && GET_CODE (XEXP (x, 1)) != CONST_INT
3373 && GET_MODE_NUNITS (mode) == 1
3374 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3376 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3377 && (TARGET_POWERPC64 || mode != DImode)
3380 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3381 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3383 else if (ALTIVEC_VECTOR_MODE (mode))
3387 /* Make sure both operands are registers. */
3388 if (GET_CODE (x) == PLUS)
3389 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3390 force_reg (Pmode, XEXP (x, 1)));
3392 reg = force_reg (Pmode, x);
3395 else if (SPE_VECTOR_MODE (mode)
3396 || (TARGET_E500_DOUBLE && mode == DFmode))
3398 /* We accept [reg + reg] and [reg + OFFSET]. */
3400 if (GET_CODE (x) == PLUS)
3402 rtx op1 = XEXP (x, 0);
3403 rtx op2 = XEXP (x, 1);
3405 op1 = force_reg (Pmode, op1);
3407 if (GET_CODE (op2) != REG
3408 && (GET_CODE (op2) != CONST_INT
3409 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3410 op2 = force_reg (Pmode, op2);
3412 return gen_rtx_PLUS (Pmode, op1, op2);
3415 return force_reg (Pmode, x);
3421 && GET_CODE (x) != CONST_INT
3422 && GET_CODE (x) != CONST_DOUBLE
3424 && GET_MODE_NUNITS (mode) == 1
3425 && (GET_MODE_BITSIZE (mode) <= 32
3426 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3428 rtx reg = gen_reg_rtx (Pmode);
3429 emit_insn (gen_elf_high (reg, x));
3430 return gen_rtx_LO_SUM (Pmode, reg, x);
3432 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3435 && ! MACHO_DYNAMIC_NO_PIC_P
3437 && GET_CODE (x) != CONST_INT
3438 && GET_CODE (x) != CONST_DOUBLE
3440 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3444 rtx reg = gen_reg_rtx (Pmode);
3445 emit_insn (gen_macho_high (reg, x));
3446 return gen_rtx_LO_SUM (Pmode, reg, x);
3449 && constant_pool_expr_p (x)
3450 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3452 return create_TOC_reference (x);
3458 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
3459 We need to emit DTP-relative relocations. */
3462 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3467 fputs ("\t.long\t", file);
3470 fputs (DOUBLE_INT_ASM_OP, file);
3475 output_addr_const (file, x);
3476 fputs ("@dtprel+0x8000", file);
3479 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3481 static GTY(()) rtx rs6000_tls_symbol;
3483 rs6000_tls_get_addr (void)
3485 if (!rs6000_tls_symbol)
3486 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3488 return rs6000_tls_symbol;
3491 /* Construct the SYMBOL_REF for TLS GOT references. */
3493 static GTY(()) rtx rs6000_got_symbol;
3495 rs6000_got_sym (void)
3497 if (!rs6000_got_symbol)
3499 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3500 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3501 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3504 return rs6000_got_symbol;
3507 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3508 this (thread-local) address. */
3511 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3515 dest = gen_reg_rtx (Pmode);
3516 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3522 tlsreg = gen_rtx_REG (Pmode, 13);
3523 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3527 tlsreg = gen_rtx_REG (Pmode, 2);
3528 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3532 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3536 tmp = gen_reg_rtx (Pmode);
3539 tlsreg = gen_rtx_REG (Pmode, 13);
3540 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3544 tlsreg = gen_rtx_REG (Pmode, 2);
3545 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3549 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3551 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3556 rtx r3, got, tga, tmp1, tmp2, eqv;
3559 got = gen_rtx_REG (Pmode, TOC_REGISTER);
3563 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3566 rtx gsym = rs6000_got_sym ();
3567 got = gen_reg_rtx (Pmode);
3569 rs6000_emit_move (got, gsym, Pmode);
3573 static int tls_got_labelno = 0;
3574 rtx tempLR, lab, tmp3, mem;
3577 ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++);
3578 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
3579 tempLR = gen_reg_rtx (Pmode);
3580 tmp1 = gen_reg_rtx (Pmode);
3581 tmp2 = gen_reg_rtx (Pmode);
3582 tmp3 = gen_reg_rtx (Pmode);
3583 mem = gen_const_mem (Pmode, tmp1);
3585 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab,
3587 emit_move_insn (tmp1, tempLR);
3588 emit_move_insn (tmp2, mem);
3589 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3590 last = emit_move_insn (got, tmp3);
3591 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3593 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3595 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3601 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3603 r3 = gen_rtx_REG (Pmode, 3);
3605 insn = gen_tls_gd_64 (r3, got, addr);
3607 insn = gen_tls_gd_32 (r3, got, addr);
3610 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3611 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3612 insn = emit_call_insn (insn);
3613 CONST_OR_PURE_CALL_P (insn) = 1;
3614 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3615 insn = get_insns ();
3617 emit_libcall_block (insn, dest, r3, addr);
3619 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3621 r3 = gen_rtx_REG (Pmode, 3);
3623 insn = gen_tls_ld_64 (r3, got);
3625 insn = gen_tls_ld_32 (r3, got);
3628 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3629 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3630 insn = emit_call_insn (insn);
3631 CONST_OR_PURE_CALL_P (insn) = 1;
3632 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3633 insn = get_insns ();
3635 tmp1 = gen_reg_rtx (Pmode);
3636 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3638 emit_libcall_block (insn, tmp1, r3, eqv);
3639 if (rs6000_tls_size == 16)
3642 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3644 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3646 else if (rs6000_tls_size == 32)
3648 tmp2 = gen_reg_rtx (Pmode);
3650 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3652 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3655 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3657 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3661 tmp2 = gen_reg_rtx (Pmode);
3663 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3665 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3667 insn = gen_rtx_SET (Pmode, dest,
3668 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3674 /* IE, or 64 bit offset LE. */
3675 tmp2 = gen_reg_rtx (Pmode);
3677 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3679 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3682 insn = gen_tls_tls_64 (dest, tmp2, addr);
3684 insn = gen_tls_tls_32 (dest, tmp2, addr);
3692 /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in
3693 instruction definitions. */
3696 rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
3698 return RS6000_SYMBOL_REF_TLS_P (x);
3701 /* Return 1 if X contains a thread-local symbol. */
3704 rs6000_tls_referenced_p (rtx x)
3706 if (! TARGET_HAVE_TLS)
3709 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3712 /* Return 1 if *X is a thread-local symbol. This is the same as
3713 rs6000_tls_symbol_ref except for the type of the unused argument. */
3716 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3718 return RS6000_SYMBOL_REF_TLS_P (*x);
3721 /* The convention appears to be to define this wherever it is used.
3722 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3723 is now used here. */
3724 #ifndef REG_MODE_OK_FOR_BASE_P
3725 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3728 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3729 replace the input X, or the original X if no replacement is called for.
3730 The output parameter *WIN is 1 if the calling macro should goto WIN,
3733 For RS/6000, we wish to handle large displacements off a base
3734 register by splitting the addend across an addiu/addis and the mem insn.
3735 This cuts number of extra insns needed from 3 to 1.
3737 On Darwin, we use this to generate code for floating point constants.
3738 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3739 The Darwin code is inside #if TARGET_MACHO because only then is
3740 machopic_function_base_name() defined. */
3742 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3743 int opnum, int type,
3744 int ind_levels ATTRIBUTE_UNUSED, int *win)
3746 /* We must recognize output that we have already generated ourselves. */
3747 if (GET_CODE (x) == PLUS
3748 && GET_CODE (XEXP (x, 0)) == PLUS
3749 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3750 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3751 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3753 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3754 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3755 opnum, (enum reload_type)type);
3761 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3762 && GET_CODE (x) == LO_SUM
3763 && GET_CODE (XEXP (x, 0)) == PLUS
3764 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3765 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3766 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3767 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3768 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3769 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3770 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3772 /* Result of previous invocation of this function on Darwin
3773 floating point constant. */
3774 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3775 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3776 opnum, (enum reload_type)type);
3781 if (GET_CODE (x) == PLUS
3782 && GET_CODE (XEXP (x, 0)) == REG
3783 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3784 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3785 && GET_CODE (XEXP (x, 1)) == CONST_INT
3786 && !SPE_VECTOR_MODE (mode)
3787 && !(TARGET_E500_DOUBLE && mode == DFmode)
3788 && !ALTIVEC_VECTOR_MODE (mode))
3790 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3791 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3793 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3795 /* Check for 32-bit overflow. */
3796 if (high + low != val)
3802 /* Reload the high part into a base reg; leave the low part
3803 in the mem directly. */
3805 x = gen_rtx_PLUS (GET_MODE (x),
3806 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3810 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3811 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3812 opnum, (enum reload_type)type);
3817 if (GET_CODE (x) == SYMBOL_REF
3818 && DEFAULT_ABI == ABI_DARWIN
3819 && !ALTIVEC_VECTOR_MODE (mode)
3820 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3821 /* Don't do this for TFmode, since the result isn't offsettable. */
3826 rtx offset = gen_rtx_CONST (Pmode,
3827 gen_rtx_MINUS (Pmode, x,
3828 machopic_function_base_sym ()));
3829 x = gen_rtx_LO_SUM (GET_MODE (x),
3830 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3831 gen_rtx_HIGH (Pmode, offset)), offset);
3834 x = gen_rtx_LO_SUM (GET_MODE (x),
3835 gen_rtx_HIGH (Pmode, x), x);
3837 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3838 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3839 opnum, (enum reload_type)type);
3845 && constant_pool_expr_p (x)
3846 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3848 (x) = create_TOC_reference (x);
3856 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3857 that is a valid memory address for an instruction.
3858 The MODE argument is the machine mode for the MEM expression
3859 that wants to use this address.
3861 On the RS/6000, there are four valid address: a SYMBOL_REF that
3862 refers to a constant pool entry of an address (or the sum of it
3863 plus a constant), a short (16-bit signed) constant plus a register,
3864 the sum of two registers, or a register indirect, possibly with an
3865 auto-increment. For DFmode and DImode with a constant plus register,
3866 we must ensure that both words are addressable or PowerPC64 with offset
3869 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3870 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3871 adjacent memory cells are accessed by adding word-sized offsets
3872 during assembly output. */
3874 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3876 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3878 && ALTIVEC_VECTOR_MODE (mode)
3879 && GET_CODE (x) == AND
3880 && GET_CODE (XEXP (x, 1)) == CONST_INT
3881 && INTVAL (XEXP (x, 1)) == -16)
3884 if (RS6000_SYMBOL_REF_TLS_P (x))
3886 if (legitimate_indirect_address_p (x, reg_ok_strict))
3888 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3889 && !ALTIVEC_VECTOR_MODE (mode)
3890 && !SPE_VECTOR_MODE (mode)
3891 && !(TARGET_E500_DOUBLE && mode == DFmode)
3893 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3895 if (legitimate_small_data_p (mode, x))
3897 if (legitimate_constant_pool_address_p (x))
3899 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3901 && GET_CODE (x) == PLUS
3902 && GET_CODE (XEXP (x, 0)) == REG
3903 && (XEXP (x, 0) == virtual_stack_vars_rtx
3904 || XEXP (x, 0) == arg_pointer_rtx)
3905 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3907 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3911 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3913 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3914 && (TARGET_POWERPC64 || mode != DImode)
3915 && legitimate_indexed_address_p (x, reg_ok_strict))
3917 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3922 /* Go to LABEL if ADDR (a legitimate address expression)
3923 has an effect that depends on the machine mode it is used for.
3925 On the RS/6000 this is true of all integral offsets (since AltiVec
3926 modes don't allow them) or is a pre-increment or decrement.
3928 ??? Except that due to conceptual problems in offsettable_address_p
3929 we can't really report the problems of integral offsets. So leave
3930 this assuming that the adjustable offset must be valid for the
3931 sub-words of a TFmode operand, which is what we had before. */
3934 rs6000_mode_dependent_address (rtx addr)
3936 switch (GET_CODE (addr))
3939 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3941 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3942 return val + 12 + 0x8000 >= 0x10000;
3951 return TARGET_UPDATE;
3960 /* Return number of consecutive hard regs needed starting at reg REGNO
3961 to hold something of mode MODE.
3962 This is ordinarily the length in words of a value of mode MODE
3963 but can be less for certain modes in special long registers.
3965 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3966 scalar instructions. The upper 32 bits are only available to the
3969 POWER and PowerPC GPRs hold 32 bits worth;
3970 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3973 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3975 if (FP_REGNO_P (regno))
3976 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3978 if (TARGET_E500_DOUBLE && mode == DFmode)
3981 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3982 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3984 if (ALTIVEC_REGNO_P (regno))
3986 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3988 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3991 /* Change register usage conditional on target flags. */
3993 rs6000_conditional_register_usage (void)
3997 /* Set MQ register fixed (already call_used) if not POWER
3998 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4003 /* 64-bit AIX reserves GPR13 for thread-private data. */
4005 fixed_regs[13] = call_used_regs[13]
4006 = call_really_used_regs[13] = 1;
4008 /* Conditionally disable FPRs. */
4009 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
4010 for (i = 32; i < 64; i++)
4011 fixed_regs[i] = call_used_regs[i]
4012 = call_really_used_regs[i] = 1;
4014 if (DEFAULT_ABI == ABI_V4
4015 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4017 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4019 if (DEFAULT_ABI == ABI_V4
4020 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4022 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4023 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4024 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4026 if (DEFAULT_ABI == ABI_DARWIN
4027 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
4028 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4029 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4030 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4031 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4033 if (TARGET_TOC && TARGET_MINIMAL_TOC)
4034 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4035 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4038 global_regs[VSCR_REGNO] = 1;
4042 global_regs[SPEFSCR_REGNO] = 1;
4043 fixed_regs[FIXED_SCRATCH]
4044 = call_used_regs[FIXED_SCRATCH]
4045 = call_really_used_regs[FIXED_SCRATCH] = 1;
4048 if (! TARGET_ALTIVEC)
4050 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4051 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4052 call_really_used_regs[VRSAVE_REGNO] = 1;
4055 if (TARGET_ALTIVEC_ABI)
4056 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4057 call_used_regs[i] = call_really_used_regs[i] = 1;
4060 /* Try to output insns to set TARGET equal to the constant C if it can
4061 be done in less than N insns. Do all computations in MODE.
4062 Returns the place where the output has been placed if it can be
4063 done and the insns have been emitted. If it would take more than N
4064 insns, zero is returned and no insns and emitted. */
4067 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4068 rtx source, int n ATTRIBUTE_UNUSED)
4070 rtx result, insn, set;
4071 HOST_WIDE_INT c0, c1;
4073 if (mode == QImode || mode == HImode)
4076 dest = gen_reg_rtx (mode);
4077 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4080 else if (mode == SImode)
4082 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
4084 emit_insn (gen_rtx_SET (VOIDmode, result,
4085 GEN_INT (INTVAL (source)
4086 & (~ (HOST_WIDE_INT) 0xffff))));
4087 emit_insn (gen_rtx_SET (VOIDmode, dest,
4088 gen_rtx_IOR (SImode, result,
4089 GEN_INT (INTVAL (source) & 0xffff))));
4092 else if (mode == DImode)
4094 if (GET_CODE (source) == CONST_INT)
4096 c0 = INTVAL (source);
4099 else if (GET_CODE (source) == CONST_DOUBLE)
4101 #if HOST_BITS_PER_WIDE_INT >= 64
4102 c0 = CONST_DOUBLE_LOW (source);
4105 c0 = CONST_DOUBLE_LOW (source);
4106 c1 = CONST_DOUBLE_HIGH (source);
4112 result = rs6000_emit_set_long_const (dest, c0, c1);
4117 insn = get_last_insn ();
4118 set = single_set (insn);
4119 if (! CONSTANT_P (SET_SRC (set)))
4120 set_unique_reg_note (insn, REG_EQUAL, source);
4125 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4126 fall back to a straight forward decomposition. We do this to avoid
4127 exponential run times encountered when looking for longer sequences
4128 with rs6000_emit_set_const. */
4130 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4132 if (!TARGET_POWERPC64)
4134 rtx operand1, operand2;
4136 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4138 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
4140 emit_move_insn (operand1, GEN_INT (c1));
4141 emit_move_insn (operand2, GEN_INT (c2));
4145 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4148 ud2 = (c1 & 0xffff0000) >> 16;
4149 #if HOST_BITS_PER_WIDE_INT >= 64
4153 ud4 = (c2 & 0xffff0000) >> 16;
4155 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4156 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4159 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4161 emit_move_insn (dest, GEN_INT (ud1));
4164 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4165 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4168 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4171 emit_move_insn (dest, GEN_INT (ud2 << 16));
4173 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4175 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4176 || (ud4 == 0 && ! (ud3 & 0x8000)))
4179 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4182 emit_move_insn (dest, GEN_INT (ud3 << 16));
4185 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
4186 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
4188 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4193 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4196 emit_move_insn (dest, GEN_INT (ud4 << 16));
4199 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
4201 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
4203 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
4204 GEN_INT (ud2 << 16)));
4206 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4212 /* Helper for the following. Get rid of [r+r] memory refs
4213 in cases where it won't work (TImode, TFmode). */
4216 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4218 if (GET_CODE (operands[0]) == MEM
4219 && GET_CODE (XEXP (operands[0], 0)) != REG
4220 && ! reload_in_progress)
4222 = replace_equiv_address (operands[0],
4223 copy_addr_to_reg (XEXP (operands[0], 0)));
4225 if (GET_CODE (operands[1]) == MEM
4226 && GET_CODE (XEXP (operands[1], 0)) != REG
4227 && ! reload_in_progress)
4229 = replace_equiv_address (operands[1],
4230 copy_addr_to_reg (XEXP (operands[1], 0)));
4233 /* Emit a move from SOURCE to DEST in mode MODE. */
4235 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4239 operands[1] = source;
4241 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4242 if (GET_CODE (operands[1]) == CONST_DOUBLE
4243 && ! FLOAT_MODE_P (mode)
4244 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4246 /* FIXME. This should never happen. */
4247 /* Since it seems that it does, do the safe thing and convert
4249 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4251 if (GET_CODE (operands[1]) == CONST_DOUBLE
4252 && ! FLOAT_MODE_P (mode)
4253 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
4254 && CONST_DOUBLE_LOW (operands[1]) >= 0)
4255 || (CONST_DOUBLE_HIGH (operands[1]) == -1
4256 && CONST_DOUBLE_LOW (operands[1]) < 0)))
4259 /* Check if GCC is setting up a block move that will end up using FP
4260 registers as temporaries. We must make sure this is acceptable. */
4261 if (GET_CODE (operands[0]) == MEM
4262 && GET_CODE (operands[1]) == MEM
4264 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4265 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4266 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4267 ? 32 : MEM_ALIGN (operands[0])))
4268 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4270 : MEM_ALIGN (operands[1]))))
4271 && ! MEM_VOLATILE_P (operands [0])
4272 && ! MEM_VOLATILE_P (operands [1]))
4274 emit_move_insn (adjust_address (operands[0], SImode, 0),
4275 adjust_address (operands[1], SImode, 0));
4276 emit_move_insn (adjust_address (operands[0], SImode, 4),
4277 adjust_address (operands[1], SImode, 4));
4281 if (!no_new_pseudos && GET_CODE (operands[0]) != REG
4282 && !gpc_reg_operand (operands[1], mode))
4283 operands[1] = force_reg (mode, operands[1]);
4285 if (mode == SFmode && ! TARGET_POWERPC
4286 && TARGET_HARD_FLOAT && TARGET_FPRS
4287 && GET_CODE (operands[0]) == MEM)
4291 if (reload_in_progress || reload_completed)
4292 regnum = true_regnum (operands[1]);
4293 else if (GET_CODE (operands[1]) == REG)
4294 regnum = REGNO (operands[1]);
4298 /* If operands[1] is a register, on POWER it may have
4299 double-precision data in it, so truncate it to single
4301 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4304 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
4305 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4306 operands[1] = newreg;
4310 /* Recognize the case where operand[1] is a reference to thread-local
4311 data and load its address to a register. */
4312 if (GET_CODE (operands[1]) == SYMBOL_REF)
4314 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
4316 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
4319 /* Handle the case where reload calls us with an invalid address. */
4320 if (reload_in_progress && mode == Pmode
4321 && (! general_operand (operands[1], mode)
4322 || ! nonimmediate_operand (operands[0], mode)))
4325 /* 128-bit constant floating-point values on Darwin should really be
4326 loaded as two parts. */
4327 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
4328 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
4329 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4331 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4332 know how to get a DFmode SUBREG of a TFmode. */
4333 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
4334 simplify_gen_subreg (DImode, operands[1], mode, 0),
4336 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
4337 GET_MODE_SIZE (DImode)),
4338 simplify_gen_subreg (DImode, operands[1], mode,
4339 GET_MODE_SIZE (DImode)),
4344 /* FIXME: In the long term, this switch statement should go away
4345 and be replaced by a sequence of tests based on things like
4351 if (CONSTANT_P (operands[1])
4352 && GET_CODE (operands[1]) != CONST_INT)
4353 operands[1] = force_const_mem (mode, operands[1]);
4357 rs6000_eliminate_indexed_memrefs (operands);
4362 if (CONSTANT_P (operands[1])
4363 && ! easy_fp_constant (operands[1], mode))
4364 operands[1] = force_const_mem (mode, operands[1]);
4375 if (CONSTANT_P (operands[1])
4376 && !easy_vector_constant (operands[1], mode))
4377 operands[1] = force_const_mem (mode, operands[1]);
4382 /* Use default pattern for address of ELF small data */
4385 && DEFAULT_ABI == ABI_V4
4386 && (GET_CODE (operands[1]) == SYMBOL_REF
4387 || GET_CODE (operands[1]) == CONST)
4388 && small_data_operand (operands[1], mode))
4390 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4394 if (DEFAULT_ABI == ABI_V4
4395 && mode == Pmode && mode == SImode
4396 && flag_pic == 1 && got_operand (operands[1], mode))
4398 emit_insn (gen_movsi_got (operands[0], operands[1]));
4402 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4406 && CONSTANT_P (operands[1])
4407 && GET_CODE (operands[1]) != HIGH
4408 && GET_CODE (operands[1]) != CONST_INT)
4410 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
4412 /* If this is a function address on -mcall-aixdesc,
4413 convert it to the address of the descriptor. */
4414 if (DEFAULT_ABI == ABI_AIX
4415 && GET_CODE (operands[1]) == SYMBOL_REF
4416 && XSTR (operands[1], 0)[0] == '.')
4418 const char *name = XSTR (operands[1], 0);
4420 while (*name == '.')
4422 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4423 CONSTANT_POOL_ADDRESS_P (new_ref)
4424 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4425 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4426 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4427 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
4428 operands[1] = new_ref;
4431 if (DEFAULT_ABI == ABI_DARWIN)
4434 if (MACHO_DYNAMIC_NO_PIC_P)
4436 /* Take care of any required data indirection. */
4437 operands[1] = rs6000_machopic_legitimize_pic_address (
4438 operands[1], mode, operands[0]);
4439 if (operands[0] != operands[1])
4440 emit_insn (gen_rtx_SET (VOIDmode,
4441 operands[0], operands[1]));
4445 emit_insn (gen_macho_high (target, operands[1]));
4446 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4450 emit_insn (gen_elf_high (target, operands[1]));
4451 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4455 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4456 and we have put it in the TOC, we just need to make a TOC-relative
4459 && GET_CODE (operands[1]) == SYMBOL_REF
4460 && constant_pool_expr_p (operands[1])
4461 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4462 get_pool_mode (operands[1])))
4464 operands[1] = create_TOC_reference (operands[1]);
4466 else if (mode == Pmode
4467 && CONSTANT_P (operands[1])
4468 && ((GET_CODE (operands[1]) != CONST_INT
4469 && ! easy_fp_constant (operands[1], mode))
4470 || (GET_CODE (operands[1]) == CONST_INT
4471 && num_insns_constant (operands[1], mode) > 2)
4472 || (GET_CODE (operands[0]) == REG
4473 && FP_REGNO_P (REGNO (operands[0]))))
4474 && GET_CODE (operands[1]) != HIGH
4475 && ! legitimate_constant_pool_address_p (operands[1])
4476 && ! toc_relative_expr_p (operands[1]))
4478 /* Emit a USE operation so that the constant isn't deleted if
4479 expensive optimizations are turned on because nobody
4480 references it. This should only be done for operands that
4481 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4482 This should not be done for operands that contain LABEL_REFs.
4483 For now, we just handle the obvious case. */
4484 if (GET_CODE (operands[1]) != LABEL_REF)
4485 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4488 /* Darwin uses a special PIC legitimizer. */
4489 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4492 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4494 if (operands[0] != operands[1])
4495 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4500 /* If we are to limit the number of things we put in the TOC and
4501 this is a symbol plus a constant we can add in one insn,
4502 just put the symbol in the TOC and add the constant. Don't do
4503 this if reload is in progress. */
4504 if (GET_CODE (operands[1]) == CONST
4505 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4506 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4507 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4508 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4509 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4510 && ! side_effects_p (operands[0]))
4513 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4514 rtx other = XEXP (XEXP (operands[1], 0), 1);
4516 sym = force_reg (mode, sym);
4518 emit_insn (gen_addsi3 (operands[0], sym, other));
4520 emit_insn (gen_adddi3 (operands[0], sym, other));
4524 operands[1] = force_const_mem (mode, operands[1]);
4527 && constant_pool_expr_p (XEXP (operands[1], 0))
4528 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4529 get_pool_constant (XEXP (operands[1], 0)),
4530 get_pool_mode (XEXP (operands[1], 0))))
4533 = gen_const_mem (mode,
4534 create_TOC_reference (XEXP (operands[1], 0)));
4535 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4541 rs6000_eliminate_indexed_memrefs (operands);
4545 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4547 gen_rtx_SET (VOIDmode,
4548 operands[0], operands[1]),
4549 gen_rtx_CLOBBER (VOIDmode,
4550 gen_rtx_SCRATCH (SImode)))));
4559 /* Above, we may have called force_const_mem which may have returned
4560 an invalid address. If we can, fix this up; otherwise, reload will
4561 have to deal with it. */
4562 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4563 operands[1] = validize_mem (operands[1]);
4566 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4569 /* Nonzero if we can use a floating-point register to pass this arg. */
4570 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4571 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
4572 && (CUM)->fregno <= FP_ARG_MAX_REG \
4573 && TARGET_HARD_FLOAT && TARGET_FPRS)
4575 /* Nonzero if we can use an AltiVec register to pass this arg. */
4576 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4577 (ALTIVEC_VECTOR_MODE (MODE) \
4578 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4579 && TARGET_ALTIVEC_ABI \
4582 /* Return a nonzero value to say to return the function value in
4583 memory, just as large structures are always returned. TYPE will be
4584 the data type of the value, and FNTYPE will be the type of the
4585 function doing the returning, or @code{NULL} for libcalls.
4587 The AIX ABI for the RS/6000 specifies that all structures are
4588 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4589 specifies that structures <= 8 bytes are returned in r3/r4, but a
4590 draft put them in memory, and GCC used to implement the draft
4591 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
4592 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4593 compatibility can change DRAFT_V4_STRUCT_RET to override the
4594 default, and -m switches get the final word. See
4595 rs6000_override_options for more details.
4597 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4598 long double support is enabled. These values are returned in memory.
4600 int_size_in_bytes returns -1 for variable size objects, which go in
4601 memory always. The cast to unsigned makes -1 > 8. */
4604 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4606 if (AGGREGATE_TYPE_P (type)
4607 && (TARGET_AIX_STRUCT_RET
4608 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4610 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
4615 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4616 for a call to a function whose data type is FNTYPE.
4617 For a library call, FNTYPE is 0.
4619 For incoming args we set the number of arguments in the prototype large
4620 so we never return a PARALLEL. */
4623 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4624 rtx libname ATTRIBUTE_UNUSED, int incoming,
4625 int libcall, int n_named_args)
4627 static CUMULATIVE_ARGS zero_cumulative;
4629 *cum = zero_cumulative;
4631 cum->fregno = FP_ARG_MIN_REG;
4632 cum->vregno = ALTIVEC_ARG_MIN_REG;
4633 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4634 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4635 ? CALL_LIBCALL : CALL_NORMAL);
4636 cum->sysv_gregno = GP_ARG_MIN_REG;
4637 cum->stdarg = fntype
4638 && (TYPE_ARG_TYPES (fntype) != 0
4639 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4640 != void_type_node));
4642 cum->nargs_prototype = 0;
4643 if (incoming || cum->prototype)
4644 cum->nargs_prototype = n_named_args;
4646 /* Check for a longcall attribute. */
4648 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4649 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))
4650 cum->call_cookie = CALL_LONG;
4652 if (TARGET_DEBUG_ARG)
4654 fprintf (stderr, "\ninit_cumulative_args:");
4657 tree ret_type = TREE_TYPE (fntype);
4658 fprintf (stderr, " ret code = %s,",
4659 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4662 if (cum->call_cookie & CALL_LONG)
4663 fprintf (stderr, " longcall,");
4665 fprintf (stderr, " proto = %d, nargs = %d\n",
4666 cum->prototype, cum->nargs_prototype);
4671 && TARGET_ALTIVEC_ABI
4672 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4674 error ("Cannot return value in vector register because"
4675 " altivec instructions are disabled, use -maltivec"
4676 " to enable them.");
4680 /* Return true if TYPE must be passed on the stack and not in registers. */
4683 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4685 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4686 return must_pass_in_stack_var_size (mode, type);
4688 return must_pass_in_stack_var_size_or_pad (mode, type);
4691 /* If defined, a C expression which determines whether, and in which
4692 direction, to pad out an argument with extra space. The value
4693 should be of type `enum direction': either `upward' to pad above
4694 the argument, `downward' to pad below, or `none' to inhibit
4697 For the AIX ABI structs are always stored left shifted in their
4701 function_arg_padding (enum machine_mode mode, tree type)
4703 #ifndef AGGREGATE_PADDING_FIXED
4704 #define AGGREGATE_PADDING_FIXED 0
4706 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4707 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4710 if (!AGGREGATE_PADDING_FIXED)
4712 /* GCC used to pass structures of the same size as integer types as
4713 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4714 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4715 passed padded downward, except that -mstrict-align further
4716 muddied the water in that multi-component structures of 2 and 4
4717 bytes in size were passed padded upward.
4719 The following arranges for best compatibility with previous
4720 versions of gcc, but removes the -mstrict-align dependency. */
4721 if (BYTES_BIG_ENDIAN)
4723 HOST_WIDE_INT size = 0;
4725 if (mode == BLKmode)
4727 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4728 size = int_size_in_bytes (type);
4731 size = GET_MODE_SIZE (mode);
4733 if (size == 1 || size == 2 || size == 4)
4739 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4741 if (type != 0 && AGGREGATE_TYPE_P (type))
4745 /* Fall back to the default. */
4746 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4749 /* If defined, a C expression that gives the alignment boundary, in bits,
4750 of an argument with the specified mode and type. If it is not defined,
4751 PARM_BOUNDARY is used for all arguments.
4753 V.4 wants long longs to be double word aligned. */
4756 function_arg_boundary (enum machine_mode mode, tree type ATTRIBUTE_UNUSED)
4758 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4760 else if (SPE_VECTOR_MODE (mode))
4762 else if (ALTIVEC_VECTOR_MODE (mode))
4765 return PARM_BOUNDARY;
4768 /* Compute the size (in words) of a function argument. */
4770 static unsigned long
4771 rs6000_arg_size (enum machine_mode mode, tree type)
4775 if (mode != BLKmode)
4776 size = GET_MODE_SIZE (mode);
4778 size = int_size_in_bytes (type);
4781 return (size + 3) >> 2;
4783 return (size + 7) >> 3;
4786 /* Update the data in CUM to advance over an argument
4787 of mode MODE and data type TYPE.
4788 (TYPE is null for libcalls where that information may not be available.)
4790 Note that for args passed by reference, function_arg will be called
4791 with MODE and TYPE set to that of the pointer to the arg, not the arg
4795 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4796 tree type, int named)
4798 cum->nargs_prototype--;
4800 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4804 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4807 if (!TARGET_ALTIVEC)
4808 error ("Cannot pass argument in vector register because"
4809 " altivec instructions are disabled, use -maltivec"
4810 " to enable them.");
4812 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4813 even if it is going to be passed in a vector register.
4814 Darwin does the same for variable-argument functions. */
4815 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4816 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4826 /* Vector parameters must be 16-byte aligned. This places
4827 them at 2 mod 4 in terms of words in 32-bit mode, since
4828 the parameter save area starts at offset 24 from the
4829 stack. In 64-bit mode, they just have to start on an
4830 even word, since the parameter save area is 16-byte
4831 aligned. Space for GPRs is reserved even if the argument
4832 will be passed in memory. */
4834 align = (2 - cum->words) & 3;
4836 align = cum->words & 1;
4837 cum->words += align + rs6000_arg_size (mode, type);
4839 if (TARGET_DEBUG_ARG)
4841 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4843 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4844 cum->nargs_prototype, cum->prototype,
4845 GET_MODE_NAME (mode));
4849 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4851 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4853 else if (DEFAULT_ABI == ABI_V4)
4855 if (TARGET_HARD_FLOAT && TARGET_FPRS
4856 && (mode == SFmode || mode == DFmode))
4858 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4863 cum->words += cum->words & 1;
4864 cum->words += rs6000_arg_size (mode, type);
4869 int n_words = rs6000_arg_size (mode, type);
4870 int gregno = cum->sysv_gregno;
4872 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4873 (r7,r8) or (r9,r10). As does any other 2 word item such
4874 as complex int due to a historical mistake. */
4876 gregno += (1 - gregno) & 1;
4878 /* Multi-reg args are not split between registers and stack. */
4879 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4881 /* Long long and SPE vectors are aligned on the stack.
4882 So are other 2 word items such as complex int due to
4883 a historical mistake. */
4885 cum->words += cum->words & 1;
4886 cum->words += n_words;
4889 /* Note: continuing to accumulate gregno past when we've started
4890 spilling to the stack indicates the fact that we've started
4891 spilling to the stack to expand_builtin_saveregs. */
4892 cum->sysv_gregno = gregno + n_words;
4895 if (TARGET_DEBUG_ARG)
4897 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4898 cum->words, cum->fregno);
4899 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4900 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4901 fprintf (stderr, "mode = %4s, named = %d\n",
4902 GET_MODE_NAME (mode), named);
4907 int n_words = rs6000_arg_size (mode, type);
4908 int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4910 /* The simple alignment calculation here works because
4911 function_arg_boundary / PARM_BOUNDARY will only be 1 or 2.
4912 If we ever want to handle alignments larger than 8 bytes for
4913 32-bit or 16 bytes for 64-bit, then we'll need to take into
4914 account the offset to the start of the parm save area. */
4915 align &= cum->words;
4916 cum->words += align + n_words;
4918 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4919 && TARGET_HARD_FLOAT && TARGET_FPRS)
4920 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4922 if (TARGET_DEBUG_ARG)
4924 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4925 cum->words, cum->fregno);
4926 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4927 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4928 fprintf (stderr, "named = %d, align = %d\n", named, align);
4934 spe_build_register_parallel (enum machine_mode mode, int gregno)
4937 enum machine_mode inner;
4938 unsigned int inner_bytes;
4948 r1 = gen_rtx_REG (inner, gregno);
4949 r1 = gen_rtx_EXPR_LIST (SImode, r1, const0_rtx);
4950 r2 = gen_rtx_REG (inner, gregno + 1);
4951 r2 = gen_rtx_EXPR_LIST (SImode, r2, GEN_INT (inner_bytes));
4952 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4955 /* Determine where to put a SIMD argument on the SPE. */
4957 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4960 int gregno = cum->sysv_gregno;
4962 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4963 are passed and returned in a pair of GPRs for ABI compatibility. */
4964 if (TARGET_E500_DOUBLE && mode == DFmode)
4966 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4967 gregno += (1 - gregno) & 1;
4969 /* We do not split between registers and stack. */
4970 if (gregno + 1 > GP_ARG_MAX_REG)
4973 return spe_build_register_parallel (mode, gregno);
4977 int n_words = rs6000_arg_size (mode, type);
4979 /* SPE vectors are put in odd registers. */
4980 if (n_words == 2 && (gregno & 1) == 0)
4983 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4986 enum machine_mode m = SImode;
4988 r1 = gen_rtx_REG (m, gregno);
4989 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4990 r2 = gen_rtx_REG (m, gregno + 1);
4991 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4992 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4999 if (gregno <= GP_ARG_MAX_REG)
5000 return gen_rtx_REG (mode, gregno);
5006 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5009 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5013 rtx rvec[GP_ARG_NUM_REG + 1];
5015 if (align_words >= GP_ARG_NUM_REG)
5018 n_units = rs6000_arg_size (mode, type);
5020 /* Optimize the simple case where the arg fits in one gpr, except in
5021 the case of BLKmode due to assign_parms assuming that registers are
5022 BITS_PER_WORD wide. */
5024 || (n_units == 1 && mode != BLKmode))
5025 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5028 if (align_words + n_units > GP_ARG_NUM_REG)
5029 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5030 using a magic NULL_RTX component.
5031 FIXME: This is not strictly correct. Only some of the arg
5032 belongs in memory, not all of it. However, there isn't any way
5033 to do this currently, apart from building rtx descriptions for
5034 the pieces of memory we want stored. Due to bugs in the generic
5035 code we can't use the normal function_arg_partial_nregs scheme
5036 with the PARALLEL arg description we emit here.
5037 In any case, the code to store the whole arg to memory is often
5038 more efficient than code to store pieces, and we know that space
5039 is available in the right place for the whole arg. */
5040 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5045 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5046 rtx off = GEN_INT (i++ * 4);
5047 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5049 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5051 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5054 /* Determine where to put an argument to a function.
5055 Value is zero to push the argument on the stack,
5056 or a hard register in which to store the argument.
5058 MODE is the argument's machine mode.
5059 TYPE is the data type of the argument (as a tree).
5060 This is null for libcalls where that information may
5062 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5063 the preceding args and about the function being called.
5064 NAMED is nonzero if this argument is a named parameter
5065 (otherwise it is an extra parameter matching an ellipsis).
5067 On RS/6000 the first eight words of non-FP are normally in registers
5068 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5069 Under V.4, the first 8 FP args are in registers.
5071 If this is floating-point and no prototype is specified, we use
5072 both an FP and integer register (or possibly FP reg and stack). Library
5073 functions (when CALL_LIBCALL is set) always have the proper types for args,
5074 so we can pass the FP value just in one register. emit_library_function
5075 doesn't support PARALLEL anyway.
5077 Note that for args passed by reference, function_arg will be called
5078 with MODE and TYPE set to that of the pointer to the arg, not the arg
5082 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5083 tree type, int named)
5085 enum rs6000_abi abi = DEFAULT_ABI;
5087 /* Return a marker to indicate whether CR1 needs to set or clear the
5088 bit that V.4 uses to say fp args were passed in registers.
5089 Assume that we don't need the marker for software floating point,
5090 or compiler generated library calls. */
5091 if (mode == VOIDmode)
5094 && cum->nargs_prototype < 0
5095 && (cum->call_cookie & CALL_LIBCALL) == 0
5096 && (cum->prototype || TARGET_NO_PROTOTYPE))
5098 /* For the SPE, we need to crxor CR6 always. */
5100 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5101 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5102 return GEN_INT (cum->call_cookie
5103 | ((cum->fregno == FP_ARG_MIN_REG)
5104 ? CALL_V4_SET_FP_ARGS
5105 : CALL_V4_CLEAR_FP_ARGS));
5108 return GEN_INT (cum->call_cookie);
5111 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5112 if (TARGET_64BIT && ! cum->prototype)
5114 /* Vector parameters get passed in vector register
5115 and also in GPRs or memory, in absence of prototype. */
5118 align_words = (cum->words + 1) & ~1;
5120 if (align_words >= GP_ARG_NUM_REG)
5126 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5128 return gen_rtx_PARALLEL (mode,
5130 gen_rtx_EXPR_LIST (VOIDmode,
5132 gen_rtx_EXPR_LIST (VOIDmode,
5133 gen_rtx_REG (mode, cum->vregno),
5137 return gen_rtx_REG (mode, cum->vregno);
5138 else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5140 if (named || abi == ABI_V4)
5144 /* Vector parameters to varargs functions under AIX or Darwin
5145 get passed in memory and possibly also in GPRs. */
5146 int align, align_words, n_words;
5147 enum machine_mode part_mode;
5149 /* Vector parameters must be 16-byte aligned. This places them at
5150 2 mod 4 in terms of words in 32-bit mode, since the parameter
5151 save area starts at offset 24 from the stack. In 64-bit mode,
5152 they just have to start on an even word, since the parameter
5153 save area is 16-byte aligned. */
5155 align = (2 - cum->words) & 3;
5157 align = cum->words & 1;
5158 align_words = cum->words + align;
5160 /* Out of registers? Memory, then. */
5161 if (align_words >= GP_ARG_NUM_REG)
5164 if (TARGET_32BIT && TARGET_POWERPC64)
5165 return rs6000_mixed_function_arg (mode, type, align_words);
5167 /* The vector value goes in GPRs. Only the part of the
5168 value in GPRs is reported here. */
5170 n_words = rs6000_arg_size (mode, type);
5171 if (align_words + n_words > GP_ARG_NUM_REG)
5172 /* Fortunately, there are only two possibilities, the value
5173 is either wholly in GPRs or half in GPRs and half not. */
5176 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5179 else if (TARGET_SPE_ABI && TARGET_SPE
5180 && (SPE_VECTOR_MODE (mode)
5181 || (TARGET_E500_DOUBLE && mode == DFmode)))
5182 return rs6000_spe_function_arg (cum, mode, type);
5183 else if (abi == ABI_V4)
5185 if (TARGET_HARD_FLOAT && TARGET_FPRS
5186 && (mode == SFmode || mode == DFmode))
5188 if (cum->fregno <= FP_ARG_V4_MAX_REG)
5189 return gen_rtx_REG (mode, cum->fregno);
5195 int n_words = rs6000_arg_size (mode, type);
5196 int gregno = cum->sysv_gregno;
5198 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5199 (r7,r8) or (r9,r10). As does any other 2 word item such
5200 as complex int due to a historical mistake. */
5202 gregno += (1 - gregno) & 1;
5204 /* Multi-reg args are not split between registers and stack. */
5205 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5208 if (TARGET_32BIT && TARGET_POWERPC64)
5209 return rs6000_mixed_function_arg (mode, type,
5210 gregno - GP_ARG_MIN_REG);
5211 return gen_rtx_REG (mode, gregno);
5216 int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5217 int align_words = cum->words + (cum->words & align);
5219 if (USE_FP_FOR_ARG_P (cum, mode, type))
5221 rtx rvec[GP_ARG_NUM_REG + 1];
5225 enum machine_mode fmode = mode;
5226 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5228 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5230 /* Currently, we only ever need one reg here because complex
5231 doubles are split. */
5232 if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode)
5235 /* Long double split over regs and memory. */
5239 /* Do we also need to pass this arg in the parameter save
5242 && (cum->nargs_prototype <= 0
5243 || (DEFAULT_ABI == ABI_AIX
5245 && align_words >= GP_ARG_NUM_REG)));
5247 if (!needs_psave && mode == fmode)
5248 return gen_rtx_REG (fmode, cum->fregno);
5253 /* Describe the part that goes in gprs or the stack.
5254 This piece must come first, before the fprs. */
5255 if (align_words < GP_ARG_NUM_REG)
5257 unsigned long n_words = rs6000_arg_size (mode, type);
5259 if (align_words + n_words > GP_ARG_NUM_REG
5260 || (TARGET_32BIT && TARGET_POWERPC64))
5262 /* If this is partially on the stack, then we only
5263 include the portion actually in registers here. */
5264 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5267 if (align_words + n_words > GP_ARG_NUM_REG
5268 && (TARGET_32BIT && TARGET_POWERPC64))
5269 /* Not all of the arg fits in gprs. Say that it
5270 goes in memory too, using a magic NULL_RTX
5271 component. Also see comment in
5272 rs6000_mixed_function_arg for why the normal
5273 function_arg_partial_nregs scheme doesn't work
5275 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5279 r = gen_rtx_REG (rmode,
5280 GP_ARG_MIN_REG + align_words);
5281 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5282 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5284 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5288 /* The whole arg fits in gprs. */
5289 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5290 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5294 /* It's entirely in memory. */
5295 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5298 /* Describe where this piece goes in the fprs. */
5299 r = gen_rtx_REG (fmode, cum->fregno);
5300 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5302 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5304 else if (align_words < GP_ARG_NUM_REG)
5306 if (TARGET_32BIT && TARGET_POWERPC64)
5307 return rs6000_mixed_function_arg (mode, type, align_words);
5309 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5316 /* For an arg passed partly in registers and partly in memory, this is
5317 the number of registers used. For args passed entirely in registers
5318 or entirely in memory, zero. When an arg is described by a PARALLEL,
5319 perhaps using more than one register type, this function returns the
5320 number of registers used by the first element of the PARALLEL. */
5323 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5324 tree type, int named)
5331 if (DEFAULT_ABI == ABI_V4)
5334 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5335 && cum->nargs_prototype >= 0)
5338 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5339 parm_offset = TARGET_32BIT ? 2 : 0;
5340 align_words = cum->words + ((parm_offset - cum->words) & align);
5342 if (USE_FP_FOR_ARG_P (cum, mode, type)
5343 /* If we are passing this arg in gprs as well, then this function
5344 should return the number of gprs (or memory) partially passed,
5345 *not* the number of fprs. */
5347 && (cum->nargs_prototype <= 0
5348 || (DEFAULT_ABI == ABI_AIX
5350 && align_words >= GP_ARG_NUM_REG))))
5352 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
5353 ret = FP_ARG_MAX_REG + 1 - cum->fregno;
5354 else if (cum->nargs_prototype >= 0)
5358 if (align_words < GP_ARG_NUM_REG
5359 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5360 ret = GP_ARG_NUM_REG - align_words;
5362 if (ret != 0 && TARGET_DEBUG_ARG)
5363 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
5368 /* A C expression that indicates when an argument must be passed by
5369 reference. If nonzero for an argument, a copy of that argument is
5370 made in memory and a pointer to the argument is passed instead of
5371 the argument itself. The pointer is passed in whatever way is
5372 appropriate for passing a pointer to that type.
5374 Under V.4, aggregates and long double are passed by reference.
5376 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5377 reference unless the AltiVec vector extension ABI is in force.
5379 As an extension to all ABIs, variable sized types are passed by
5383 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5384 enum machine_mode mode ATTRIBUTE_UNUSED,
5385 tree type, bool named ATTRIBUTE_UNUSED)
5387 if ((DEFAULT_ABI == ABI_V4
5388 && ((type && AGGREGATE_TYPE_P (type))
5390 || (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5391 || (type && int_size_in_bytes (type) < 0))
5393 if (TARGET_DEBUG_ARG)
5394 fprintf (stderr, "function_arg_pass_by_reference\n");
5402 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5405 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5410 for (i = 0; i < nregs; i++)
5412 rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode));
5413 if (reload_completed)
5415 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5418 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5419 i * GET_MODE_SIZE(reg_mode));
5422 tem = replace_equiv_address (tem, XEXP (tem, 0));
5424 if (tem == NULL_RTX)
5427 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5431 /* Perform any needed actions needed for a function that is receiving a
5432 variable number of arguments.
5436 MODE and TYPE are the mode and type of the current parameter.
5438 PRETEND_SIZE is a variable that should be set to the amount of stack
5439 that must be pushed by the prolog to pretend that our caller pushed
5442 Normally, this macro will push all remaining incoming registers on the
5443 stack and set PRETEND_SIZE to the length of the registers pushed. */
5446 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5447 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5450 CUMULATIVE_ARGS next_cum;
5451 int reg_size = TARGET_32BIT ? 4 : 8;
5452 rtx save_area = NULL_RTX, mem;
5453 int first_reg_offset, set;
5455 /* Skip the last named argument. */
5457 function_arg_advance (&next_cum, mode, type, 1);
5459 if (DEFAULT_ABI == ABI_V4)
5462 save_area = plus_constant (virtual_stack_vars_rtx,
5463 - RS6000_VARARGS_SIZE);
5465 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5469 first_reg_offset = next_cum.words;
5470 save_area = virtual_incoming_args_rtx;
5472 if (targetm.calls.must_pass_in_stack (mode, type))
5473 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5476 set = get_varargs_alias_set ();
5477 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
5479 mem = gen_rtx_MEM (BLKmode,
5480 plus_constant (save_area,
5481 first_reg_offset * reg_size)),
5482 set_mem_alias_set (mem, set);
5483 set_mem_align (mem, BITS_PER_WORD);
5485 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5486 GP_ARG_NUM_REG - first_reg_offset);
5489 /* Save FP registers if needed. */
5490 if (DEFAULT_ABI == ABI_V4
5491 && TARGET_HARD_FLOAT && TARGET_FPRS
5493 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
5495 int fregno = next_cum.fregno;
5496 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5497 rtx lab = gen_label_rtx ();
5498 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
5501 (gen_rtx_SET (VOIDmode,
5503 gen_rtx_IF_THEN_ELSE (VOIDmode,
5504 gen_rtx_NE (VOIDmode, cr1,
5506 gen_rtx_LABEL_REF (VOIDmode, lab),
5509 while (fregno <= FP_ARG_V4_MAX_REG)
5511 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5512 set_mem_alias_set (mem, set);
5513 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5514 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5523 /* Create the va_list data type. */
5526 rs6000_build_builtin_va_list (void)
5528 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5530 /* For AIX, prefer 'char *' because that's what the system
5531 header files like. */
5532 if (DEFAULT_ABI != ABI_V4)
5533 return build_pointer_type (char_type_node);
5535 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5536 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5538 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5539 unsigned_char_type_node);
5540 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5541 unsigned_char_type_node);
5542 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5544 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5545 short_unsigned_type_node);
5546 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5548 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5551 DECL_FIELD_CONTEXT (f_gpr) = record;
5552 DECL_FIELD_CONTEXT (f_fpr) = record;
5553 DECL_FIELD_CONTEXT (f_res) = record;
5554 DECL_FIELD_CONTEXT (f_ovf) = record;
5555 DECL_FIELD_CONTEXT (f_sav) = record;
5557 TREE_CHAIN (record) = type_decl;
5558 TYPE_NAME (record) = type_decl;
5559 TYPE_FIELDS (record) = f_gpr;
5560 TREE_CHAIN (f_gpr) = f_fpr;
5561 TREE_CHAIN (f_fpr) = f_res;
5562 TREE_CHAIN (f_res) = f_ovf;
5563 TREE_CHAIN (f_ovf) = f_sav;
5565 layout_type (record);
5567 /* The correct type is an array type of one element. */
5568 return build_array_type (record, build_index_type (size_zero_node));
5571 /* Implement va_start. */
5574 rs6000_va_start (tree valist, rtx nextarg)
5576 HOST_WIDE_INT words, n_gpr, n_fpr;
5577 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5578 tree gpr, fpr, ovf, sav, t;
5580 /* Only SVR4 needs something special. */
5581 if (DEFAULT_ABI != ABI_V4)
5583 std_expand_builtin_va_start (valist, nextarg);
5587 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5588 f_fpr = TREE_CHAIN (f_gpr);
5589 f_res = TREE_CHAIN (f_fpr);
5590 f_ovf = TREE_CHAIN (f_res);
5591 f_sav = TREE_CHAIN (f_ovf);
5593 valist = build_va_arg_indirect_ref (valist);
5594 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5595 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5596 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5597 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5599 /* Count number of gp and fp argument registers used. */
5600 words = current_function_args_info.words;
5601 n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG;
5602 n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG;
5604 if (TARGET_DEBUG_ARG)
5605 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5606 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5607 words, n_gpr, n_fpr);
5609 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5610 build_int_cst (NULL_TREE, n_gpr));
5611 TREE_SIDE_EFFECTS (t) = 1;
5612 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5614 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5615 build_int_cst (NULL_TREE, n_fpr));
5616 TREE_SIDE_EFFECTS (t) = 1;
5617 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5619 /* Find the overflow area. */
5620 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5622 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
5623 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5624 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5625 TREE_SIDE_EFFECTS (t) = 1;
5626 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5628 /* Find the register save area. */
5629 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5630 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
5631 build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE));
5632 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5633 TREE_SIDE_EFFECTS (t) = 1;
5634 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5637 /* Implement va_arg. */
5640 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5642 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5643 tree gpr, fpr, ovf, sav, reg, t, u;
5644 int size, rsize, n_reg, sav_ofs, sav_scale;
5645 tree lab_false, lab_over, addr;
5647 tree ptrtype = build_pointer_type (type);
5649 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5651 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5652 return build_va_arg_indirect_ref (t);
5655 if (DEFAULT_ABI != ABI_V4)
5657 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5659 tree elem_type = TREE_TYPE (type);
5660 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5661 int elem_size = GET_MODE_SIZE (elem_mode);
5663 if (elem_size < UNITS_PER_WORD)
5665 tree real_part, imag_part;
5666 tree post = NULL_TREE;
5668 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5670 /* Copy the value into a temporary, lest the formal temporary
5671 be reused out from under us. */
5672 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5673 append_to_statement_list (post, pre_p);
5675 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5678 return build (COMPLEX_EXPR, type, real_part, imag_part);
5682 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5685 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5686 f_fpr = TREE_CHAIN (f_gpr);
5687 f_res = TREE_CHAIN (f_fpr);
5688 f_ovf = TREE_CHAIN (f_res);
5689 f_sav = TREE_CHAIN (f_ovf);
5691 valist = build_va_arg_indirect_ref (valist);
5692 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5693 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5694 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5695 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5697 size = int_size_in_bytes (type);
5698 rsize = (size + 3) / 4;
5701 if (TARGET_HARD_FLOAT && TARGET_FPRS
5702 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
5704 /* FP args go in FP registers, if present. */
5709 if (TYPE_MODE (type) == DFmode)
5714 /* Otherwise into GP registers. */
5723 /* Pull the value out of the saved registers.... */
5726 addr = create_tmp_var (ptr_type_node, "addr");
5727 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5729 /* AltiVec vectors never go in registers when -mabi=altivec. */
5730 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5734 lab_false = create_artificial_label ();
5735 lab_over = create_artificial_label ();
5737 /* Long long and SPE vectors are aligned in the registers.
5738 As are any other 2 gpr item such as complex int due to a
5739 historical mistake. */
5743 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5744 size_int (n_reg - 1));
5745 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5748 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5749 t = build2 (GE_EXPR, boolean_type_node, u, t);
5750 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5751 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5752 gimplify_and_add (t, pre_p);
5756 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5758 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5759 u = build1 (CONVERT_EXPR, integer_type_node, u);
5760 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5761 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5763 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5764 gimplify_and_add (t, pre_p);
5766 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5767 gimplify_and_add (t, pre_p);
5769 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5770 append_to_statement_list (t, pre_p);
5774 /* Ensure that we don't find any more args in regs.
5775 Alignment has taken care of the n_reg == 2 case. */
5776 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
5777 gimplify_and_add (t, pre_p);
5781 /* ... otherwise out of the overflow area. */
5783 /* Care for on-stack alignment if needed. */
5787 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
5788 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5789 build_int_cst (NULL_TREE, -align));
5791 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5793 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5794 gimplify_and_add (u, pre_p);
5796 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
5797 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5798 gimplify_and_add (t, pre_p);
5802 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5803 append_to_statement_list (t, pre_p);
5806 addr = fold_convert (ptrtype, addr);
5807 return build_va_arg_indirect_ref (addr);
5812 #define def_builtin(MASK, NAME, TYPE, CODE) \
5814 if ((MASK) & target_flags) \
5815 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
5819 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5821 static const struct builtin_description bdesc_3arg[] =
5823 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5824 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5825 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5826 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5827 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5828 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5829 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5830 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5831 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5832 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
5833 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
5834 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5835 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5836 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5837 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5838 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5839 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5840 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5841 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5842 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5843 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5844 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5845 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
5848 /* DST operations: void foo (void *, const int, const char). */
5850 static const struct builtin_description bdesc_dst[] =
5852 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5853 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5854 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
5855 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
5858 /* Simple binary operations: VECc = foo (VECa, VECb). */
5860 static struct builtin_description bdesc_2arg[] =
5862 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5863 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5864 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5865 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
5866 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5867 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5868 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5869 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5870 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5871 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5872 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
5873 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
5874 { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
5875 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5876 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5877 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5878 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5879 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5880 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
5881 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5882 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
5883 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
5884 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
5885 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
5886 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
5887 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
5888 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
5889 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
5890 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
5891 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
5892 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
5893 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
5894 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
5895 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
5896 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
5897 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
5898 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
5899 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
5900 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
5901 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
5902 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
5903 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
5904 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
5905 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
5906 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
5907 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
5908 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
5909 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
5910 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
5911 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
5912 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
5913 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
5914 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
5915 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
5916 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
5917 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
5918 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
5919 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
5920 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
5921 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
5922 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
5923 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
5924 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
5925 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
5926 { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
5927 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
5928 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
5929 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
5930 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
5931 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
5932 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
5933 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
5934 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
5935 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
5936 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
5937 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
5938 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
5939 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
5940 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
5941 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
5942 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
5943 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
5944 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
5945 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
5946 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
5947 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
5948 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
5949 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
5950 { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
5951 { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
5952 { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
5953 { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
5954 { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
5955 { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
5956 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
5957 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
5958 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
5959 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
5960 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
5961 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
5962 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
5963 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
5964 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
5965 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
5966 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
5967 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
5968 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
5969 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
5970 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
5971 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
5972 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
5973 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
5974 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
5976 /* Place holder, leave as first spe builtin. */
5977 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
5978 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
5979 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
5980 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
5981 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
5982 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
5983 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
5984 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
5985 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
5986 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
5987 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
5988 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
5989 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
5990 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
5991 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
5992 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
5993 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
5994 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
5995 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
5996 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
5997 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
5998 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
5999 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6000 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6001 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6002 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6003 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6004 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6005 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6006 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6007 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6008 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6009 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6010 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6011 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6012 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6013 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6014 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6015 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6016 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6017 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6018 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6019 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6020 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6021 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6022 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6023 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6024 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6025 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6026 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6027 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6028 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6029 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6030 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6031 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6032 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6033 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6034 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6035 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6036 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6037 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6038 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6039 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6040 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6041 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6042 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6043 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6044 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6045 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6046 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6047 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6048 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6049 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6050 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6051 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6052 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6053 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6054 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6055 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6056 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6057 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6058 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6059 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6060 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6061 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6062 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6063 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6064 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6065 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6066 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6067 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6068 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6069 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6070 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6071 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6072 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6073 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6074 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6075 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6076 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6077 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6078 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6079 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6080 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6081 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6082 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6083 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6084 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6085 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6087 /* SPE binary operations expecting a 5-bit unsigned literal. */
6088 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6090 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6091 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6092 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6093 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6094 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6095 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6096 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6097 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6098 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6099 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6100 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6101 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6102 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6103 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6104 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6105 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6106 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6107 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6108 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6109 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6110 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6111 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6112 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6113 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6114 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6115 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6117 /* Place-holder. Leave as last binary SPE builtin. */
6118 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
6121 /* AltiVec predicates. */
6123 struct builtin_description_predicates
6125 const unsigned int mask;
6126 const enum insn_code icode;
6128 const char *const name;
6129 const enum rs6000_builtins code;
6132 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6134 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6135 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6136 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6137 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6138 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6139 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6140 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6141 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6142 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6143 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6144 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6145 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6146 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
6149 /* SPE predicates. */
6150 static struct builtin_description bdesc_spe_predicates[] =
6152 /* Place-holder. Leave as first. */
6153 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6154 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6155 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6156 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6157 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6158 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6159 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6160 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6161 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6162 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6163 /* Place-holder. Leave as last. */
6164 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6167 /* SPE evsel predicates. */
6168 static struct builtin_description bdesc_spe_evsel[] =
6170 /* Place-holder. Leave as first. */
6171 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6172 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6173 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6174 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6175 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6176 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6177 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6178 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6179 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6180 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6181 /* Place-holder. Leave as last. */
6182 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6185 /* ABS* operations. */
6187 static const struct builtin_description bdesc_abs[] =
6189 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6190 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6191 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6192 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6193 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6194 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6195 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6198 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6201 static struct builtin_description bdesc_1arg[] =
6203 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6204 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6205 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6206 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6207 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6208 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6209 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6210 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6211 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6212 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6213 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6214 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6215 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6216 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6217 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6218 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6219 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6221 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6222 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6223 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6224 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6225 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6226 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6227 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6228 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6229 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6230 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6231 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6232 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6233 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6234 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6235 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6236 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6237 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6238 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6239 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6240 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6241 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6242 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6243 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6244 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6245 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6246 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6247 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6248 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6249 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6250 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6252 /* Place-holder. Leave as last unary SPE builtin. */
6253 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
6257 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6260 tree arg0 = TREE_VALUE (arglist);
6261 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6262 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6263 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6265 if (icode == CODE_FOR_nothing)
6266 /* Builtin not supported on this processor. */
6269 /* If we got invalid arguments bail out before generating bad rtl. */
6270 if (arg0 == error_mark_node)
6273 if (icode == CODE_FOR_altivec_vspltisb
6274 || icode == CODE_FOR_altivec_vspltish
6275 || icode == CODE_FOR_altivec_vspltisw
6276 || icode == CODE_FOR_spe_evsplatfi
6277 || icode == CODE_FOR_spe_evsplati)
6279 /* Only allow 5-bit *signed* literals. */
6280 if (GET_CODE (op0) != CONST_INT
6281 || INTVAL (op0) > 0x1f
6282 || INTVAL (op0) < -0x1f)
6284 error ("argument 1 must be a 5-bit signed literal");
6290 || GET_MODE (target) != tmode
6291 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6292 target = gen_reg_rtx (tmode);
6294 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6295 op0 = copy_to_mode_reg (mode0, op0);
6297 pat = GEN_FCN (icode) (target, op0);
6306 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6308 rtx pat, scratch1, scratch2;
6309 tree arg0 = TREE_VALUE (arglist);
6310 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6311 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6312 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6314 /* If we have invalid arguments, bail out before generating bad rtl. */
6315 if (arg0 == error_mark_node)
6319 || GET_MODE (target) != tmode
6320 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6321 target = gen_reg_rtx (tmode);
6323 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6324 op0 = copy_to_mode_reg (mode0, op0);
6326 scratch1 = gen_reg_rtx (mode0);
6327 scratch2 = gen_reg_rtx (mode0);
6329 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6338 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6341 tree arg0 = TREE_VALUE (arglist);
6342 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6343 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6344 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6345 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6346 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6347 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6349 if (icode == CODE_FOR_nothing)
6350 /* Builtin not supported on this processor. */
6353 /* If we got invalid arguments bail out before generating bad rtl. */
6354 if (arg0 == error_mark_node || arg1 == error_mark_node)
6357 if (icode == CODE_FOR_altivec_vcfux
6358 || icode == CODE_FOR_altivec_vcfsx
6359 || icode == CODE_FOR_altivec_vctsxs
6360 || icode == CODE_FOR_altivec_vctuxs
6361 || icode == CODE_FOR_altivec_vspltb
6362 || icode == CODE_FOR_altivec_vsplth
6363 || icode == CODE_FOR_altivec_vspltw
6364 || icode == CODE_FOR_spe_evaddiw
6365 || icode == CODE_FOR_spe_evldd
6366 || icode == CODE_FOR_spe_evldh
6367 || icode == CODE_FOR_spe_evldw
6368 || icode == CODE_FOR_spe_evlhhesplat
6369 || icode == CODE_FOR_spe_evlhhossplat
6370 || icode == CODE_FOR_spe_evlhhousplat
6371 || icode == CODE_FOR_spe_evlwhe
6372 || icode == CODE_FOR_spe_evlwhos
6373 || icode == CODE_FOR_spe_evlwhou
6374 || icode == CODE_FOR_spe_evlwhsplat
6375 || icode == CODE_FOR_spe_evlwwsplat
6376 || icode == CODE_FOR_spe_evrlwi
6377 || icode == CODE_FOR_spe_evslwi
6378 || icode == CODE_FOR_spe_evsrwis
6379 || icode == CODE_FOR_spe_evsubifw
6380 || icode == CODE_FOR_spe_evsrwiu)
6382 /* Only allow 5-bit unsigned literals. */
6384 if (TREE_CODE (arg1) != INTEGER_CST
6385 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6387 error ("argument 2 must be a 5-bit unsigned literal");
6393 || GET_MODE (target) != tmode
6394 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6395 target = gen_reg_rtx (tmode);
6397 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6398 op0 = copy_to_mode_reg (mode0, op0);
6399 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6400 op1 = copy_to_mode_reg (mode1, op1);
6402 pat = GEN_FCN (icode) (target, op0, op1);
6411 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6412 tree arglist, rtx target)
6415 tree cr6_form = TREE_VALUE (arglist);
6416 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6417 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6418 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6419 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6420 enum machine_mode tmode = SImode;
6421 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6422 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6425 if (TREE_CODE (cr6_form) != INTEGER_CST)
6427 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6431 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6436 /* If we have invalid arguments, bail out before generating bad rtl. */
6437 if (arg0 == error_mark_node || arg1 == error_mark_node)
6441 || GET_MODE (target) != tmode
6442 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6443 target = gen_reg_rtx (tmode);
6445 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6446 op0 = copy_to_mode_reg (mode0, op0);
6447 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6448 op1 = copy_to_mode_reg (mode1, op1);
6450 scratch = gen_reg_rtx (mode0);
6452 pat = GEN_FCN (icode) (scratch, op0, op1,
6453 gen_rtx_SYMBOL_REF (Pmode, opcode));
6458 /* The vec_any* and vec_all* predicates use the same opcodes for two
6459 different operations, but the bits in CR6 will be different
6460 depending on what information we want. So we have to play tricks
6461 with CR6 to get the right bits out.
6463 If you think this is disgusting, look at the specs for the
6464 AltiVec predicates. */
6466 switch (cr6_form_int)
6469 emit_insn (gen_cr6_test_for_zero (target));
6472 emit_insn (gen_cr6_test_for_zero_reverse (target));
6475 emit_insn (gen_cr6_test_for_lt (target));
6478 emit_insn (gen_cr6_test_for_lt_reverse (target));
6481 error ("argument 1 of __builtin_altivec_predicate is out of range");
6489 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6492 tree arg0 = TREE_VALUE (arglist);
6493 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6494 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6495 enum machine_mode mode0 = Pmode;
6496 enum machine_mode mode1 = Pmode;
6497 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6498 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6500 if (icode == CODE_FOR_nothing)
6501 /* Builtin not supported on this processor. */
6504 /* If we got invalid arguments bail out before generating bad rtl. */
6505 if (arg0 == error_mark_node || arg1 == error_mark_node)
6509 || GET_MODE (target) != tmode
6510 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6511 target = gen_reg_rtx (tmode);
6513 op1 = copy_to_mode_reg (mode1, op1);
6515 if (op0 == const0_rtx)
6517 addr = gen_rtx_MEM (tmode, op1);
6521 op0 = copy_to_mode_reg (mode0, op0);
6522 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6525 pat = GEN_FCN (icode) (target, addr);
6535 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6537 tree arg0 = TREE_VALUE (arglist);
6538 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6539 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6540 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6541 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6542 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6544 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6545 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6546 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6548 /* Invalid arguments. Bail before doing anything stoopid! */
6549 if (arg0 == error_mark_node
6550 || arg1 == error_mark_node
6551 || arg2 == error_mark_node)
6554 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6555 op0 = copy_to_mode_reg (mode2, op0);
6556 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6557 op1 = copy_to_mode_reg (mode0, op1);
6558 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6559 op2 = copy_to_mode_reg (mode1, op2);
6561 pat = GEN_FCN (icode) (op1, op2, op0);
6568 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6570 tree arg0 = TREE_VALUE (arglist);
6571 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6572 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6573 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6574 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6575 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6577 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6578 enum machine_mode mode1 = Pmode;
6579 enum machine_mode mode2 = Pmode;
6581 /* Invalid arguments. Bail before doing anything stoopid! */
6582 if (arg0 == error_mark_node
6583 || arg1 == error_mark_node
6584 || arg2 == error_mark_node)
6587 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6588 op0 = copy_to_mode_reg (tmode, op0);
6590 op2 = copy_to_mode_reg (mode2, op2);
6592 if (op1 == const0_rtx)
6594 addr = gen_rtx_MEM (tmode, op2);
6598 op1 = copy_to_mode_reg (mode1, op1);
6599 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6602 pat = GEN_FCN (icode) (addr, op0);
6609 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6612 tree arg0 = TREE_VALUE (arglist);
6613 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6614 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6615 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6616 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6617 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6618 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6619 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6620 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6621 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6623 if (icode == CODE_FOR_nothing)
6624 /* Builtin not supported on this processor. */
6627 /* If we got invalid arguments bail out before generating bad rtl. */
6628 if (arg0 == error_mark_node
6629 || arg1 == error_mark_node
6630 || arg2 == error_mark_node)
6633 if (icode == CODE_FOR_altivec_vsldoi_4sf
6634 || icode == CODE_FOR_altivec_vsldoi_4si
6635 || icode == CODE_FOR_altivec_vsldoi_8hi
6636 || icode == CODE_FOR_altivec_vsldoi_16qi)
6638 /* Only allow 4-bit unsigned literals. */
6640 if (TREE_CODE (arg2) != INTEGER_CST
6641 || TREE_INT_CST_LOW (arg2) & ~0xf)
6643 error ("argument 3 must be a 4-bit unsigned literal");
6649 || GET_MODE (target) != tmode
6650 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6651 target = gen_reg_rtx (tmode);
6653 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6654 op0 = copy_to_mode_reg (mode0, op0);
6655 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6656 op1 = copy_to_mode_reg (mode1, op1);
6657 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6658 op2 = copy_to_mode_reg (mode2, op2);
6660 pat = GEN_FCN (icode) (target, op0, op1, op2);
6668 /* Expand the lvx builtins. */
6670 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
6672 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6673 tree arglist = TREE_OPERAND (exp, 1);
6674 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6676 enum machine_mode tmode, mode0;
6678 enum insn_code icode;
6682 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
6683 icode = CODE_FOR_altivec_lvx_16qi;
6685 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
6686 icode = CODE_FOR_altivec_lvx_8hi;
6688 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
6689 icode = CODE_FOR_altivec_lvx_4si;
6691 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
6692 icode = CODE_FOR_altivec_lvx_4sf;
6701 arg0 = TREE_VALUE (arglist);
6702 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6703 tmode = insn_data[icode].operand[0].mode;
6704 mode0 = insn_data[icode].operand[1].mode;
6707 || GET_MODE (target) != tmode
6708 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6709 target = gen_reg_rtx (tmode);
6711 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6712 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6714 pat = GEN_FCN (icode) (target, op0);
6721 /* Expand the stvx builtins. */
6723 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6726 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6727 tree arglist = TREE_OPERAND (exp, 1);
6728 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6730 enum machine_mode mode0, mode1;
6732 enum insn_code icode;
6736 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
6737 icode = CODE_FOR_altivec_stvx_16qi;
6739 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
6740 icode = CODE_FOR_altivec_stvx_8hi;
6742 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
6743 icode = CODE_FOR_altivec_stvx_4si;
6745 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
6746 icode = CODE_FOR_altivec_stvx_4sf;
6753 arg0 = TREE_VALUE (arglist);
6754 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6755 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6756 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6757 mode0 = insn_data[icode].operand[0].mode;
6758 mode1 = insn_data[icode].operand[1].mode;
6760 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6761 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6762 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6763 op1 = copy_to_mode_reg (mode1, op1);
6765 pat = GEN_FCN (icode) (op0, op1);
6773 /* Expand the dst builtins. */
6775 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6778 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6779 tree arglist = TREE_OPERAND (exp, 1);
6780 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6781 tree arg0, arg1, arg2;
6782 enum machine_mode mode0, mode1, mode2;
6783 rtx pat, op0, op1, op2;
6784 struct builtin_description *d;
6789 /* Handle DST variants. */
6790 d = (struct builtin_description *) bdesc_dst;
6791 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6792 if (d->code == fcode)
6794 arg0 = TREE_VALUE (arglist);
6795 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6796 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6797 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6798 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6799 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6800 mode0 = insn_data[d->icode].operand[0].mode;
6801 mode1 = insn_data[d->icode].operand[1].mode;
6802 mode2 = insn_data[d->icode].operand[2].mode;
6804 /* Invalid arguments, bail out before generating bad rtl. */
6805 if (arg0 == error_mark_node
6806 || arg1 == error_mark_node
6807 || arg2 == error_mark_node)
6812 if (TREE_CODE (arg2) != INTEGER_CST
6813 || TREE_INT_CST_LOW (arg2) & ~0x3)
6815 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
6819 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
6820 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6821 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
6822 op1 = copy_to_mode_reg (mode1, op1);
6824 pat = GEN_FCN (d->icode) (op0, op1, op2);
6834 /* Expand the builtin in EXP and store the result in TARGET. Store
6835 true in *EXPANDEDP if we found a builtin to expand. */
6837 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
6839 struct builtin_description *d;
6840 struct builtin_description_predicates *dp;
6842 enum insn_code icode;
6843 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6844 tree arglist = TREE_OPERAND (exp, 1);
6847 enum machine_mode tmode, mode0;
6848 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6850 target = altivec_expand_ld_builtin (exp, target, expandedp);
6854 target = altivec_expand_st_builtin (exp, target, expandedp);
6858 target = altivec_expand_dst_builtin (exp, target, expandedp);
6866 case ALTIVEC_BUILTIN_STVX:
6867 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
6868 case ALTIVEC_BUILTIN_STVEBX:
6869 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
6870 case ALTIVEC_BUILTIN_STVEHX:
6871 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
6872 case ALTIVEC_BUILTIN_STVEWX:
6873 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
6874 case ALTIVEC_BUILTIN_STVXL:
6875 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
6877 case ALTIVEC_BUILTIN_MFVSCR:
6878 icode = CODE_FOR_altivec_mfvscr;
6879 tmode = insn_data[icode].operand[0].mode;
6882 || GET_MODE (target) != tmode
6883 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6884 target = gen_reg_rtx (tmode);
6886 pat = GEN_FCN (icode) (target);
6892 case ALTIVEC_BUILTIN_MTVSCR:
6893 icode = CODE_FOR_altivec_mtvscr;
6894 arg0 = TREE_VALUE (arglist);
6895 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6896 mode0 = insn_data[icode].operand[0].mode;
6898 /* If we got invalid arguments bail out before generating bad rtl. */
6899 if (arg0 == error_mark_node)
6902 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6903 op0 = copy_to_mode_reg (mode0, op0);
6905 pat = GEN_FCN (icode) (op0);
6910 case ALTIVEC_BUILTIN_DSSALL:
6911 emit_insn (gen_altivec_dssall ());
6914 case ALTIVEC_BUILTIN_DSS:
6915 icode = CODE_FOR_altivec_dss;
6916 arg0 = TREE_VALUE (arglist);
6918 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6919 mode0 = insn_data[icode].operand[0].mode;
6921 /* If we got invalid arguments bail out before generating bad rtl. */
6922 if (arg0 == error_mark_node)
6925 if (TREE_CODE (arg0) != INTEGER_CST
6926 || TREE_INT_CST_LOW (arg0) & ~0x3)
6928 error ("argument to dss must be a 2-bit unsigned literal");
6932 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6933 op0 = copy_to_mode_reg (mode0, op0);
6935 emit_insn (gen_altivec_dss (op0));
6938 case ALTIVEC_BUILTIN_COMPILETIME_ERROR:
6939 arg0 = TREE_VALUE (arglist);
6940 while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR
6941 || TREE_CODE (arg0) == ARRAY_REF)
6942 arg0 = TREE_OPERAND (arg0, 0);
6943 error ("invalid parameter combination for %qs AltiVec intrinsic",
6944 TREE_STRING_POINTER (arg0));
6949 /* Expand abs* operations. */
6950 d = (struct builtin_description *) bdesc_abs;
6951 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
6952 if (d->code == fcode)
6953 return altivec_expand_abs_builtin (d->icode, arglist, target);
6955 /* Expand the AltiVec predicates. */
6956 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
6957 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
6958 if (dp->code == fcode)
6959 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
6962 /* LV* are funky. We initialized them differently. */
6965 case ALTIVEC_BUILTIN_LVSL:
6966 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
6968 case ALTIVEC_BUILTIN_LVSR:
6969 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
6971 case ALTIVEC_BUILTIN_LVEBX:
6972 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
6974 case ALTIVEC_BUILTIN_LVEHX:
6975 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
6977 case ALTIVEC_BUILTIN_LVEWX:
6978 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
6980 case ALTIVEC_BUILTIN_LVXL:
6981 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
6983 case ALTIVEC_BUILTIN_LVX:
6984 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
6995 /* Binops that need to be initialized manually, but can be expanded
6996 automagically by rs6000_expand_binop_builtin. */
6997 static struct builtin_description bdesc_2arg_spe[] =
6999 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7000 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7001 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7002 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7003 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7004 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7005 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7006 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7007 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7008 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7009 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7010 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7011 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7012 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7013 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7014 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7015 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7016 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7017 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7018 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7019 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7020 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7023 /* Expand the builtin in EXP and store the result in TARGET. Store
7024 true in *EXPANDEDP if we found a builtin to expand.
7026 This expands the SPE builtins that are not simple unary and binary
7029 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7031 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7032 tree arglist = TREE_OPERAND (exp, 1);
7034 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7035 enum insn_code icode;
7036 enum machine_mode tmode, mode0;
7038 struct builtin_description *d;
7043 /* Syntax check for a 5-bit unsigned immediate. */
7046 case SPE_BUILTIN_EVSTDD:
7047 case SPE_BUILTIN_EVSTDH:
7048 case SPE_BUILTIN_EVSTDW:
7049 case SPE_BUILTIN_EVSTWHE:
7050 case SPE_BUILTIN_EVSTWHO:
7051 case SPE_BUILTIN_EVSTWWE:
7052 case SPE_BUILTIN_EVSTWWO:
7053 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7054 if (TREE_CODE (arg1) != INTEGER_CST
7055 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7057 error ("argument 2 must be a 5-bit unsigned literal");
7065 /* The evsplat*i instructions are not quite generic. */
7068 case SPE_BUILTIN_EVSPLATFI:
7069 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7071 case SPE_BUILTIN_EVSPLATI:
7072 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7078 d = (struct builtin_description *) bdesc_2arg_spe;
7079 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7080 if (d->code == fcode)
7081 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7083 d = (struct builtin_description *) bdesc_spe_predicates;
7084 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7085 if (d->code == fcode)
7086 return spe_expand_predicate_builtin (d->icode, arglist, target);
7088 d = (struct builtin_description *) bdesc_spe_evsel;
7089 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7090 if (d->code == fcode)
7091 return spe_expand_evsel_builtin (d->icode, arglist, target);
7095 case SPE_BUILTIN_EVSTDDX:
7096 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7097 case SPE_BUILTIN_EVSTDHX:
7098 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7099 case SPE_BUILTIN_EVSTDWX:
7100 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7101 case SPE_BUILTIN_EVSTWHEX:
7102 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7103 case SPE_BUILTIN_EVSTWHOX:
7104 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7105 case SPE_BUILTIN_EVSTWWEX:
7106 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7107 case SPE_BUILTIN_EVSTWWOX:
7108 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7109 case SPE_BUILTIN_EVSTDD:
7110 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7111 case SPE_BUILTIN_EVSTDH:
7112 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7113 case SPE_BUILTIN_EVSTDW:
7114 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7115 case SPE_BUILTIN_EVSTWHE:
7116 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7117 case SPE_BUILTIN_EVSTWHO:
7118 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7119 case SPE_BUILTIN_EVSTWWE:
7120 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7121 case SPE_BUILTIN_EVSTWWO:
7122 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7123 case SPE_BUILTIN_MFSPEFSCR:
7124 icode = CODE_FOR_spe_mfspefscr;
7125 tmode = insn_data[icode].operand[0].mode;
7128 || GET_MODE (target) != tmode
7129 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7130 target = gen_reg_rtx (tmode);
7132 pat = GEN_FCN (icode) (target);
7137 case SPE_BUILTIN_MTSPEFSCR:
7138 icode = CODE_FOR_spe_mtspefscr;
7139 arg0 = TREE_VALUE (arglist);
7140 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7141 mode0 = insn_data[icode].operand[0].mode;
7143 if (arg0 == error_mark_node)
7146 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7147 op0 = copy_to_mode_reg (mode0, op0);
7149 pat = GEN_FCN (icode) (op0);
7162 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7164 rtx pat, scratch, tmp;
7165 tree form = TREE_VALUE (arglist);
7166 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7167 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7168 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7169 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7170 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7171 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7175 if (TREE_CODE (form) != INTEGER_CST)
7177 error ("argument 1 of __builtin_spe_predicate must be a constant");
7181 form_int = TREE_INT_CST_LOW (form);
7186 if (arg0 == error_mark_node || arg1 == error_mark_node)
7190 || GET_MODE (target) != SImode
7191 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7192 target = gen_reg_rtx (SImode);
7194 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7195 op0 = copy_to_mode_reg (mode0, op0);
7196 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7197 op1 = copy_to_mode_reg (mode1, op1);
7199 scratch = gen_reg_rtx (CCmode);
7201 pat = GEN_FCN (icode) (scratch, op0, op1);
7206 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7207 _lower_. We use one compare, but look in different bits of the
7208 CR for each variant.
7210 There are 2 elements in each SPE simd type (upper/lower). The CR
7211 bits are set as follows:
7213 BIT0 | BIT 1 | BIT 2 | BIT 3
7214 U | L | (U | L) | (U & L)
7216 So, for an "all" relationship, BIT 3 would be set.
7217 For an "any" relationship, BIT 2 would be set. Etc.
7219 Following traditional nomenclature, these bits map to:
7221 BIT0 | BIT 1 | BIT 2 | BIT 3
7224 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7229 /* All variant. OV bit. */
7231 /* We need to get to the OV bit, which is the ORDERED bit. We
7232 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7233 that's ugly and will trigger a validate_condition_mode abort.
7234 So let's just use another pattern. */
7235 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7237 /* Any variant. EQ bit. */
7241 /* Upper variant. LT bit. */
7245 /* Lower variant. GT bit. */
7250 error ("argument 1 of __builtin_spe_predicate is out of range");
7254 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7255 emit_move_insn (target, tmp);
7260 /* The evsel builtins look like this:
7262 e = __builtin_spe_evsel_OP (a, b, c, d);
7266 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7267 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7271 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7274 tree arg0 = TREE_VALUE (arglist);
7275 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7276 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7277 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7278 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7279 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7280 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7281 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
7282 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7283 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7288 if (arg0 == error_mark_node || arg1 == error_mark_node
7289 || arg2 == error_mark_node || arg3 == error_mark_node)
7293 || GET_MODE (target) != mode0
7294 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7295 target = gen_reg_rtx (mode0);
7297 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7298 op0 = copy_to_mode_reg (mode0, op0);
7299 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7300 op1 = copy_to_mode_reg (mode0, op1);
7301 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7302 op2 = copy_to_mode_reg (mode0, op2);
7303 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7304 op3 = copy_to_mode_reg (mode0, op3);
7306 /* Generate the compare. */
7307 scratch = gen_reg_rtx (CCmode);
7308 pat = GEN_FCN (icode) (scratch, op0, op1);
7313 if (mode0 == V2SImode)
7314 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7316 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7321 /* Expand an expression EXP that calls a built-in function,
7322 with result going to TARGET if that's convenient
7323 (and in mode MODE if that's convenient).
7324 SUBTARGET may be used as the target for computing one of EXP's operands.
7325 IGNORE is nonzero if the value is to be ignored. */
7328 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7329 enum machine_mode mode ATTRIBUTE_UNUSED,
7330 int ignore ATTRIBUTE_UNUSED)
7332 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7333 tree arglist = TREE_OPERAND (exp, 1);
7334 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7335 struct builtin_description *d;
7340 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7341 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7343 int icode = (int) CODE_FOR_altivec_lvsr;
7344 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7345 enum machine_mode mode = insn_data[icode].operand[1].mode;
7349 if (!TARGET_ALTIVEC)
7352 arg = TREE_VALUE (arglist);
7353 if (TREE_CODE (TREE_TYPE (arg)) != POINTER_TYPE)
7355 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7356 addr = memory_address (mode, op);
7357 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7361 /* For the load case need to negate the address. */
7362 op = gen_reg_rtx (GET_MODE (addr));
7363 emit_insn (gen_rtx_SET (VOIDmode, op,
7364 gen_rtx_NEG (GET_MODE (addr), addr)));
7366 op = gen_rtx_MEM (mode, op);
7369 || GET_MODE (target) != tmode
7370 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7371 target = gen_reg_rtx (tmode);
7373 /*pat = gen_altivec_lvsr (target, op);*/
7374 pat = GEN_FCN (icode) (target, op);
7384 ret = altivec_expand_builtin (exp, target, &success);
7391 ret = spe_expand_builtin (exp, target, &success);
7397 if (TARGET_ALTIVEC || TARGET_SPE)
7399 /* Handle simple unary operations. */
7400 d = (struct builtin_description *) bdesc_1arg;
7401 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7402 if (d->code == fcode)
7403 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7405 /* Handle simple binary operations. */
7406 d = (struct builtin_description *) bdesc_2arg;
7407 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7408 if (d->code == fcode)
7409 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7411 /* Handle simple ternary operations. */
7412 d = (struct builtin_description *) bdesc_3arg;
7413 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7414 if (d->code == fcode)
7415 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7423 build_opaque_vector_type (tree node, int nunits)
7425 node = copy_node (node);
7426 TYPE_MAIN_VARIANT (node) = node;
7427 return build_vector_type (node, nunits);
7431 rs6000_init_builtins (void)
7433 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7434 V2SF_type_node = build_vector_type (float_type_node, 2);
7435 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7436 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7437 V4SF_type_node = build_vector_type (float_type_node, 4);
7438 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7439 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7441 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7442 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7443 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7445 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7446 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7447 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7449 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7450 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7451 'vector unsigned short'. */
7453 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7454 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7455 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7456 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7458 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7459 get_identifier ("__bool char"),
7460 bool_char_type_node));
7461 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7462 get_identifier ("__bool short"),
7463 bool_short_type_node));
7464 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7465 get_identifier ("__bool int"),
7466 bool_int_type_node));
7467 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7468 get_identifier ("__pixel"),
7471 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7472 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7473 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7474 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7476 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7477 get_identifier ("__vector unsigned char"),
7478 unsigned_V16QI_type_node));
7479 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7480 get_identifier ("__vector signed char"),
7482 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7483 get_identifier ("__vector __bool char"),
7484 bool_V16QI_type_node));
7486 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7487 get_identifier ("__vector unsigned short"),
7488 unsigned_V8HI_type_node));
7489 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7490 get_identifier ("__vector signed short"),
7492 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7493 get_identifier ("__vector __bool short"),
7494 bool_V8HI_type_node));
7496 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7497 get_identifier ("__vector unsigned int"),
7498 unsigned_V4SI_type_node));
7499 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7500 get_identifier ("__vector signed int"),
7502 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7503 get_identifier ("__vector __bool int"),
7504 bool_V4SI_type_node));
7506 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7507 get_identifier ("__vector float"),
7509 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7510 get_identifier ("__vector __pixel"),
7511 pixel_V8HI_type_node));
7514 spe_init_builtins ();
7516 altivec_init_builtins ();
7517 if (TARGET_ALTIVEC || TARGET_SPE)
7518 rs6000_common_init_builtins ();
7521 /* Search through a set of builtins and enable the mask bits.
7522 DESC is an array of builtins.
7523 SIZE is the total number of builtins.
7524 START is the builtin enum at which to start.
7525 END is the builtin enum at which to end. */
7527 enable_mask_for_builtins (struct builtin_description *desc, int size,
7528 enum rs6000_builtins start,
7529 enum rs6000_builtins end)
7533 for (i = 0; i < size; ++i)
7534 if (desc[i].code == start)
7540 for (; i < size; ++i)
7542 /* Flip all the bits on. */
7543 desc[i].mask = target_flags;
7544 if (desc[i].code == end)
7550 spe_init_builtins (void)
7552 tree endlink = void_list_node;
7553 tree puint_type_node = build_pointer_type (unsigned_type_node);
7554 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
7555 struct builtin_description *d;
7558 tree v2si_ftype_4_v2si
7559 = build_function_type
7560 (opaque_V2SI_type_node,
7561 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7562 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7563 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7564 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7567 tree v2sf_ftype_4_v2sf
7568 = build_function_type
7569 (opaque_V2SF_type_node,
7570 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7571 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7572 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7573 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7576 tree int_ftype_int_v2si_v2si
7577 = build_function_type
7579 tree_cons (NULL_TREE, integer_type_node,
7580 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7581 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7584 tree int_ftype_int_v2sf_v2sf
7585 = build_function_type
7587 tree_cons (NULL_TREE, integer_type_node,
7588 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7589 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7592 tree void_ftype_v2si_puint_int
7593 = build_function_type (void_type_node,
7594 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7595 tree_cons (NULL_TREE, puint_type_node,
7596 tree_cons (NULL_TREE,
7600 tree void_ftype_v2si_puint_char
7601 = build_function_type (void_type_node,
7602 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7603 tree_cons (NULL_TREE, puint_type_node,
7604 tree_cons (NULL_TREE,
7608 tree void_ftype_v2si_pv2si_int
7609 = build_function_type (void_type_node,
7610 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7611 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7612 tree_cons (NULL_TREE,
7616 tree void_ftype_v2si_pv2si_char
7617 = build_function_type (void_type_node,
7618 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7619 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7620 tree_cons (NULL_TREE,
7625 = build_function_type (void_type_node,
7626 tree_cons (NULL_TREE, integer_type_node, endlink));
7629 = build_function_type (integer_type_node, endlink);
7631 tree v2si_ftype_pv2si_int
7632 = build_function_type (opaque_V2SI_type_node,
7633 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7634 tree_cons (NULL_TREE, integer_type_node,
7637 tree v2si_ftype_puint_int
7638 = build_function_type (opaque_V2SI_type_node,
7639 tree_cons (NULL_TREE, puint_type_node,
7640 tree_cons (NULL_TREE, integer_type_node,
7643 tree v2si_ftype_pushort_int
7644 = build_function_type (opaque_V2SI_type_node,
7645 tree_cons (NULL_TREE, pushort_type_node,
7646 tree_cons (NULL_TREE, integer_type_node,
7649 tree v2si_ftype_signed_char
7650 = build_function_type (opaque_V2SI_type_node,
7651 tree_cons (NULL_TREE, signed_char_type_node,
7654 /* The initialization of the simple binary and unary builtins is
7655 done in rs6000_common_init_builtins, but we have to enable the
7656 mask bits here manually because we have run out of `target_flags'
7657 bits. We really need to redesign this mask business. */
7659 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
7660 ARRAY_SIZE (bdesc_2arg),
7663 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
7664 ARRAY_SIZE (bdesc_1arg),
7666 SPE_BUILTIN_EVSUBFUSIAAW);
7667 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
7668 ARRAY_SIZE (bdesc_spe_predicates),
7669 SPE_BUILTIN_EVCMPEQ,
7670 SPE_BUILTIN_EVFSTSTLT);
7671 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
7672 ARRAY_SIZE (bdesc_spe_evsel),
7673 SPE_BUILTIN_EVSEL_CMPGTS,
7674 SPE_BUILTIN_EVSEL_FSTSTEQ);
7676 (*lang_hooks.decls.pushdecl)
7677 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
7678 opaque_V2SI_type_node));
7680 /* Initialize irregular SPE builtins. */
7682 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
7683 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
7684 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
7685 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
7686 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
7687 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
7688 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
7689 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
7690 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
7691 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
7692 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
7693 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
7694 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
7695 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
7696 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
7697 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
7698 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
7699 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
7702 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
7703 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
7704 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
7705 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
7706 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
7707 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
7708 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
7709 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
7710 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
7711 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
7712 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
7713 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
7714 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
7715 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
7716 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
7717 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
7718 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
7719 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
7720 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
7721 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
7722 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
7723 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
7726 d = (struct builtin_description *) bdesc_spe_predicates;
7727 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
7731 switch (insn_data[d->icode].operand[1].mode)
7734 type = int_ftype_int_v2si_v2si;
7737 type = int_ftype_int_v2sf_v2sf;
7743 def_builtin (d->mask, d->name, type, d->code);
7746 /* Evsel predicates. */
7747 d = (struct builtin_description *) bdesc_spe_evsel;
7748 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
7752 switch (insn_data[d->icode].operand[1].mode)
7755 type = v2si_ftype_4_v2si;
7758 type = v2sf_ftype_4_v2sf;
7764 def_builtin (d->mask, d->name, type, d->code);
7769 altivec_init_builtins (void)
7771 struct builtin_description *d;
7772 struct builtin_description_predicates *dp;
7774 tree pfloat_type_node = build_pointer_type (float_type_node);
7775 tree pint_type_node = build_pointer_type (integer_type_node);
7776 tree pshort_type_node = build_pointer_type (short_integer_type_node);
7777 tree pchar_type_node = build_pointer_type (char_type_node);
7779 tree pvoid_type_node = build_pointer_type (void_type_node);
7781 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
7782 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
7783 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
7784 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
7786 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
7788 tree int_ftype_int_v4si_v4si
7789 = build_function_type_list (integer_type_node,
7790 integer_type_node, V4SI_type_node,
7791 V4SI_type_node, NULL_TREE);
7792 tree v4sf_ftype_pcfloat
7793 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
7794 tree void_ftype_pfloat_v4sf
7795 = build_function_type_list (void_type_node,
7796 pfloat_type_node, V4SF_type_node, NULL_TREE);
7797 tree v4si_ftype_pcint
7798 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
7799 tree void_ftype_pint_v4si
7800 = build_function_type_list (void_type_node,
7801 pint_type_node, V4SI_type_node, NULL_TREE);
7802 tree v8hi_ftype_pcshort
7803 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
7804 tree void_ftype_pshort_v8hi
7805 = build_function_type_list (void_type_node,
7806 pshort_type_node, V8HI_type_node, NULL_TREE);
7807 tree v16qi_ftype_pcchar
7808 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
7809 tree void_ftype_pchar_v16qi
7810 = build_function_type_list (void_type_node,
7811 pchar_type_node, V16QI_type_node, NULL_TREE);
7812 tree void_ftype_v4si
7813 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
7814 tree v8hi_ftype_void
7815 = build_function_type (V8HI_type_node, void_list_node);
7816 tree void_ftype_void
7817 = build_function_type (void_type_node, void_list_node);
7819 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
7821 tree v16qi_ftype_long_pcvoid
7822 = build_function_type_list (V16QI_type_node,
7823 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7824 tree v8hi_ftype_long_pcvoid
7825 = build_function_type_list (V8HI_type_node,
7826 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7827 tree v4si_ftype_long_pcvoid
7828 = build_function_type_list (V4SI_type_node,
7829 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7831 tree void_ftype_v4si_long_pvoid
7832 = build_function_type_list (void_type_node,
7833 V4SI_type_node, long_integer_type_node,
7834 pvoid_type_node, NULL_TREE);
7835 tree void_ftype_v16qi_long_pvoid
7836 = build_function_type_list (void_type_node,
7837 V16QI_type_node, long_integer_type_node,
7838 pvoid_type_node, NULL_TREE);
7839 tree void_ftype_v8hi_long_pvoid
7840 = build_function_type_list (void_type_node,
7841 V8HI_type_node, long_integer_type_node,
7842 pvoid_type_node, NULL_TREE);
7843 tree int_ftype_int_v8hi_v8hi
7844 = build_function_type_list (integer_type_node,
7845 integer_type_node, V8HI_type_node,
7846 V8HI_type_node, NULL_TREE);
7847 tree int_ftype_int_v16qi_v16qi
7848 = build_function_type_list (integer_type_node,
7849 integer_type_node, V16QI_type_node,
7850 V16QI_type_node, NULL_TREE);
7851 tree int_ftype_int_v4sf_v4sf
7852 = build_function_type_list (integer_type_node,
7853 integer_type_node, V4SF_type_node,
7854 V4SF_type_node, NULL_TREE);
7855 tree v4si_ftype_v4si
7856 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
7857 tree v8hi_ftype_v8hi
7858 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
7859 tree v16qi_ftype_v16qi
7860 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
7861 tree v4sf_ftype_v4sf
7862 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7863 tree void_ftype_pcvoid_int_int
7864 = build_function_type_list (void_type_node,
7865 pcvoid_type_node, integer_type_node,
7866 integer_type_node, NULL_TREE);
7867 tree int_ftype_pcchar
7868 = build_function_type_list (integer_type_node,
7869 pcchar_type_node, NULL_TREE);
7871 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
7872 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
7873 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
7874 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
7875 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
7876 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
7877 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
7878 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
7879 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
7880 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
7881 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
7882 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
7883 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
7884 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
7885 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
7886 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
7887 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
7888 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
7889 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
7890 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
7891 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
7892 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
7893 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
7894 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
7895 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
7896 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
7897 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
7898 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
7899 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
7900 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
7901 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
7902 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
7904 /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */
7905 def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar,
7906 ALTIVEC_BUILTIN_COMPILETIME_ERROR);
7908 /* Add the DST variants. */
7909 d = (struct builtin_description *) bdesc_dst;
7910 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7911 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
7913 /* Initialize the predicates. */
7914 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7915 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7917 enum machine_mode mode1;
7920 mode1 = insn_data[dp->icode].operand[1].mode;
7925 type = int_ftype_int_v4si_v4si;
7928 type = int_ftype_int_v8hi_v8hi;
7931 type = int_ftype_int_v16qi_v16qi;
7934 type = int_ftype_int_v4sf_v4sf;
7940 def_builtin (dp->mask, dp->name, type, dp->code);
7943 /* Initialize the abs* operators. */
7944 d = (struct builtin_description *) bdesc_abs;
7945 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7947 enum machine_mode mode0;
7950 mode0 = insn_data[d->icode].operand[0].mode;
7955 type = v4si_ftype_v4si;
7958 type = v8hi_ftype_v8hi;
7961 type = v16qi_ftype_v16qi;
7964 type = v4sf_ftype_v4sf;
7970 def_builtin (d->mask, d->name, type, d->code);
7977 /* Initialize target builtin that implements
7978 targetm.vectorize.builtin_mask_for_load. */
7980 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
7981 v16qi_ftype_long_pcvoid,
7982 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
7983 BUILT_IN_MD, NULL, NULL_TREE);
7984 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
7985 altivec_builtin_mask_for_load = decl;
7988 /* Initialize target builtin that implements
7989 targetm.vectorize.builtin_mask_for_store. */
7991 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_store",
7992 v16qi_ftype_long_pcvoid,
7993 ALTIVEC_BUILTIN_MASK_FOR_STORE,
7994 BUILT_IN_MD, NULL, NULL_TREE);
7995 /* Record the decl. Will be used by rs6000_builtin_mask_for_store. */
7996 altivec_builtin_mask_for_store = decl;
8001 rs6000_common_init_builtins (void)
8003 struct builtin_description *d;
8006 tree v4sf_ftype_v4sf_v4sf_v16qi
8007 = build_function_type_list (V4SF_type_node,
8008 V4SF_type_node, V4SF_type_node,
8009 V16QI_type_node, NULL_TREE);
8010 tree v4si_ftype_v4si_v4si_v16qi
8011 = build_function_type_list (V4SI_type_node,
8012 V4SI_type_node, V4SI_type_node,
8013 V16QI_type_node, NULL_TREE);
8014 tree v8hi_ftype_v8hi_v8hi_v16qi
8015 = build_function_type_list (V8HI_type_node,
8016 V8HI_type_node, V8HI_type_node,
8017 V16QI_type_node, NULL_TREE);
8018 tree v16qi_ftype_v16qi_v16qi_v16qi
8019 = build_function_type_list (V16QI_type_node,
8020 V16QI_type_node, V16QI_type_node,
8021 V16QI_type_node, NULL_TREE);
8023 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8025 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8026 tree v16qi_ftype_int
8027 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8028 tree v8hi_ftype_v16qi
8029 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8030 tree v4sf_ftype_v4sf
8031 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8033 tree v2si_ftype_v2si_v2si
8034 = build_function_type_list (opaque_V2SI_type_node,
8035 opaque_V2SI_type_node,
8036 opaque_V2SI_type_node, NULL_TREE);
8038 tree v2sf_ftype_v2sf_v2sf
8039 = build_function_type_list (opaque_V2SF_type_node,
8040 opaque_V2SF_type_node,
8041 opaque_V2SF_type_node, NULL_TREE);
8043 tree v2si_ftype_int_int
8044 = build_function_type_list (opaque_V2SI_type_node,
8045 integer_type_node, integer_type_node,
8048 tree v2si_ftype_v2si
8049 = build_function_type_list (opaque_V2SI_type_node,
8050 opaque_V2SI_type_node, NULL_TREE);
8052 tree v2sf_ftype_v2sf
8053 = build_function_type_list (opaque_V2SF_type_node,
8054 opaque_V2SF_type_node, NULL_TREE);
8056 tree v2sf_ftype_v2si
8057 = build_function_type_list (opaque_V2SF_type_node,
8058 opaque_V2SI_type_node, NULL_TREE);
8060 tree v2si_ftype_v2sf
8061 = build_function_type_list (opaque_V2SI_type_node,
8062 opaque_V2SF_type_node, NULL_TREE);
8064 tree v2si_ftype_v2si_char
8065 = build_function_type_list (opaque_V2SI_type_node,
8066 opaque_V2SI_type_node,
8067 char_type_node, NULL_TREE);
8069 tree v2si_ftype_int_char
8070 = build_function_type_list (opaque_V2SI_type_node,
8071 integer_type_node, char_type_node, NULL_TREE);
8073 tree v2si_ftype_char
8074 = build_function_type_list (opaque_V2SI_type_node,
8075 char_type_node, NULL_TREE);
8077 tree int_ftype_int_int
8078 = build_function_type_list (integer_type_node,
8079 integer_type_node, integer_type_node,
8082 tree v4si_ftype_v4si_v4si
8083 = build_function_type_list (V4SI_type_node,
8084 V4SI_type_node, V4SI_type_node, NULL_TREE);
8085 tree v4sf_ftype_v4si_int
8086 = build_function_type_list (V4SF_type_node,
8087 V4SI_type_node, integer_type_node, NULL_TREE);
8088 tree v4si_ftype_v4sf_int
8089 = build_function_type_list (V4SI_type_node,
8090 V4SF_type_node, integer_type_node, NULL_TREE);
8091 tree v4si_ftype_v4si_int
8092 = build_function_type_list (V4SI_type_node,
8093 V4SI_type_node, integer_type_node, NULL_TREE);
8094 tree v8hi_ftype_v8hi_int
8095 = build_function_type_list (V8HI_type_node,
8096 V8HI_type_node, integer_type_node, NULL_TREE);
8097 tree v16qi_ftype_v16qi_int
8098 = build_function_type_list (V16QI_type_node,
8099 V16QI_type_node, integer_type_node, NULL_TREE);
8100 tree v16qi_ftype_v16qi_v16qi_int
8101 = build_function_type_list (V16QI_type_node,
8102 V16QI_type_node, V16QI_type_node,
8103 integer_type_node, NULL_TREE);
8104 tree v8hi_ftype_v8hi_v8hi_int
8105 = build_function_type_list (V8HI_type_node,
8106 V8HI_type_node, V8HI_type_node,
8107 integer_type_node, NULL_TREE);
8108 tree v4si_ftype_v4si_v4si_int
8109 = build_function_type_list (V4SI_type_node,
8110 V4SI_type_node, V4SI_type_node,
8111 integer_type_node, NULL_TREE);
8112 tree v4sf_ftype_v4sf_v4sf_int
8113 = build_function_type_list (V4SF_type_node,
8114 V4SF_type_node, V4SF_type_node,
8115 integer_type_node, NULL_TREE);
8116 tree v4sf_ftype_v4sf_v4sf
8117 = build_function_type_list (V4SF_type_node,
8118 V4SF_type_node, V4SF_type_node, NULL_TREE);
8119 tree v4sf_ftype_v4sf_v4sf_v4si
8120 = build_function_type_list (V4SF_type_node,
8121 V4SF_type_node, V4SF_type_node,
8122 V4SI_type_node, NULL_TREE);
8123 tree v4sf_ftype_v4sf_v4sf_v4sf
8124 = build_function_type_list (V4SF_type_node,
8125 V4SF_type_node, V4SF_type_node,
8126 V4SF_type_node, NULL_TREE);
8127 tree v4si_ftype_v4si_v4si_v4si
8128 = build_function_type_list (V4SI_type_node,
8129 V4SI_type_node, V4SI_type_node,
8130 V4SI_type_node, NULL_TREE);
8131 tree v8hi_ftype_v8hi_v8hi
8132 = build_function_type_list (V8HI_type_node,
8133 V8HI_type_node, V8HI_type_node, NULL_TREE);
8134 tree v8hi_ftype_v8hi_v8hi_v8hi
8135 = build_function_type_list (V8HI_type_node,
8136 V8HI_type_node, V8HI_type_node,
8137 V8HI_type_node, NULL_TREE);
8138 tree v4si_ftype_v8hi_v8hi_v4si
8139 = build_function_type_list (V4SI_type_node,
8140 V8HI_type_node, V8HI_type_node,
8141 V4SI_type_node, NULL_TREE);
8142 tree v4si_ftype_v16qi_v16qi_v4si
8143 = build_function_type_list (V4SI_type_node,
8144 V16QI_type_node, V16QI_type_node,
8145 V4SI_type_node, NULL_TREE);
8146 tree v16qi_ftype_v16qi_v16qi
8147 = build_function_type_list (V16QI_type_node,
8148 V16QI_type_node, V16QI_type_node, NULL_TREE);
8149 tree v4si_ftype_v4sf_v4sf
8150 = build_function_type_list (V4SI_type_node,
8151 V4SF_type_node, V4SF_type_node, NULL_TREE);
8152 tree v8hi_ftype_v16qi_v16qi
8153 = build_function_type_list (V8HI_type_node,
8154 V16QI_type_node, V16QI_type_node, NULL_TREE);
8155 tree v4si_ftype_v8hi_v8hi
8156 = build_function_type_list (V4SI_type_node,
8157 V8HI_type_node, V8HI_type_node, NULL_TREE);
8158 tree v8hi_ftype_v4si_v4si
8159 = build_function_type_list (V8HI_type_node,
8160 V4SI_type_node, V4SI_type_node, NULL_TREE);
8161 tree v16qi_ftype_v8hi_v8hi
8162 = build_function_type_list (V16QI_type_node,
8163 V8HI_type_node, V8HI_type_node, NULL_TREE);
8164 tree v4si_ftype_v16qi_v4si
8165 = build_function_type_list (V4SI_type_node,
8166 V16QI_type_node, V4SI_type_node, NULL_TREE);
8167 tree v4si_ftype_v16qi_v16qi
8168 = build_function_type_list (V4SI_type_node,
8169 V16QI_type_node, V16QI_type_node, NULL_TREE);
8170 tree v4si_ftype_v8hi_v4si
8171 = build_function_type_list (V4SI_type_node,
8172 V8HI_type_node, V4SI_type_node, NULL_TREE);
8173 tree v4si_ftype_v8hi
8174 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8175 tree int_ftype_v4si_v4si
8176 = build_function_type_list (integer_type_node,
8177 V4SI_type_node, V4SI_type_node, NULL_TREE);
8178 tree int_ftype_v4sf_v4sf
8179 = build_function_type_list (integer_type_node,
8180 V4SF_type_node, V4SF_type_node, NULL_TREE);
8181 tree int_ftype_v16qi_v16qi
8182 = build_function_type_list (integer_type_node,
8183 V16QI_type_node, V16QI_type_node, NULL_TREE);
8184 tree int_ftype_v8hi_v8hi
8185 = build_function_type_list (integer_type_node,
8186 V8HI_type_node, V8HI_type_node, NULL_TREE);
8188 /* Add the simple ternary operators. */
8189 d = (struct builtin_description *) bdesc_3arg;
8190 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8193 enum machine_mode mode0, mode1, mode2, mode3;
8196 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8199 mode0 = insn_data[d->icode].operand[0].mode;
8200 mode1 = insn_data[d->icode].operand[1].mode;
8201 mode2 = insn_data[d->icode].operand[2].mode;
8202 mode3 = insn_data[d->icode].operand[3].mode;
8204 /* When all four are of the same mode. */
8205 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8210 type = v4si_ftype_v4si_v4si_v4si;
8213 type = v4sf_ftype_v4sf_v4sf_v4sf;
8216 type = v8hi_ftype_v8hi_v8hi_v8hi;
8219 type = v16qi_ftype_v16qi_v16qi_v16qi;
8225 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8230 type = v4si_ftype_v4si_v4si_v16qi;
8233 type = v4sf_ftype_v4sf_v4sf_v16qi;
8236 type = v8hi_ftype_v8hi_v8hi_v16qi;
8239 type = v16qi_ftype_v16qi_v16qi_v16qi;
8245 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8246 && mode3 == V4SImode)
8247 type = v4si_ftype_v16qi_v16qi_v4si;
8248 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8249 && mode3 == V4SImode)
8250 type = v4si_ftype_v8hi_v8hi_v4si;
8251 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8252 && mode3 == V4SImode)
8253 type = v4sf_ftype_v4sf_v4sf_v4si;
8255 /* vchar, vchar, vchar, 4 bit literal. */
8256 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8258 type = v16qi_ftype_v16qi_v16qi_int;
8260 /* vshort, vshort, vshort, 4 bit literal. */
8261 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8263 type = v8hi_ftype_v8hi_v8hi_int;
8265 /* vint, vint, vint, 4 bit literal. */
8266 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8268 type = v4si_ftype_v4si_v4si_int;
8270 /* vfloat, vfloat, vfloat, 4 bit literal. */
8271 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8273 type = v4sf_ftype_v4sf_v4sf_int;
8278 def_builtin (d->mask, d->name, type, d->code);
8281 /* Add the simple binary operators. */
8282 d = (struct builtin_description *) bdesc_2arg;
8283 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8285 enum machine_mode mode0, mode1, mode2;
8288 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8291 mode0 = insn_data[d->icode].operand[0].mode;
8292 mode1 = insn_data[d->icode].operand[1].mode;
8293 mode2 = insn_data[d->icode].operand[2].mode;
8295 /* When all three operands are of the same mode. */
8296 if (mode0 == mode1 && mode1 == mode2)
8301 type = v4sf_ftype_v4sf_v4sf;
8304 type = v4si_ftype_v4si_v4si;
8307 type = v16qi_ftype_v16qi_v16qi;
8310 type = v8hi_ftype_v8hi_v8hi;
8313 type = v2si_ftype_v2si_v2si;
8316 type = v2sf_ftype_v2sf_v2sf;
8319 type = int_ftype_int_int;
8326 /* A few other combos we really don't want to do manually. */
8328 /* vint, vfloat, vfloat. */
8329 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8330 type = v4si_ftype_v4sf_v4sf;
8332 /* vshort, vchar, vchar. */
8333 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8334 type = v8hi_ftype_v16qi_v16qi;
8336 /* vint, vshort, vshort. */
8337 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8338 type = v4si_ftype_v8hi_v8hi;
8340 /* vshort, vint, vint. */
8341 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8342 type = v8hi_ftype_v4si_v4si;
8344 /* vchar, vshort, vshort. */
8345 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8346 type = v16qi_ftype_v8hi_v8hi;
8348 /* vint, vchar, vint. */
8349 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8350 type = v4si_ftype_v16qi_v4si;
8352 /* vint, vchar, vchar. */
8353 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8354 type = v4si_ftype_v16qi_v16qi;
8356 /* vint, vshort, vint. */
8357 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8358 type = v4si_ftype_v8hi_v4si;
8360 /* vint, vint, 5 bit literal. */
8361 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
8362 type = v4si_ftype_v4si_int;
8364 /* vshort, vshort, 5 bit literal. */
8365 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8366 type = v8hi_ftype_v8hi_int;
8368 /* vchar, vchar, 5 bit literal. */
8369 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8370 type = v16qi_ftype_v16qi_int;
8372 /* vfloat, vint, 5 bit literal. */
8373 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8374 type = v4sf_ftype_v4si_int;
8376 /* vint, vfloat, 5 bit literal. */
8377 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
8378 type = v4si_ftype_v4sf_int;
8380 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8381 type = v2si_ftype_int_int;
8383 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8384 type = v2si_ftype_v2si_char;
8386 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8387 type = v2si_ftype_int_char;
8390 else if (mode0 == SImode)
8395 type = int_ftype_v4si_v4si;
8398 type = int_ftype_v4sf_v4sf;
8401 type = int_ftype_v16qi_v16qi;
8404 type = int_ftype_v8hi_v8hi;
8414 def_builtin (d->mask, d->name, type, d->code);
8417 /* Add the simple unary operators. */
8418 d = (struct builtin_description *) bdesc_1arg;
8419 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8421 enum machine_mode mode0, mode1;
8424 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8427 mode0 = insn_data[d->icode].operand[0].mode;
8428 mode1 = insn_data[d->icode].operand[1].mode;
8430 if (mode0 == V4SImode && mode1 == QImode)
8431 type = v4si_ftype_int;
8432 else if (mode0 == V8HImode && mode1 == QImode)
8433 type = v8hi_ftype_int;
8434 else if (mode0 == V16QImode && mode1 == QImode)
8435 type = v16qi_ftype_int;
8436 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8437 type = v4sf_ftype_v4sf;
8438 else if (mode0 == V8HImode && mode1 == V16QImode)
8439 type = v8hi_ftype_v16qi;
8440 else if (mode0 == V4SImode && mode1 == V8HImode)
8441 type = v4si_ftype_v8hi;
8442 else if (mode0 == V2SImode && mode1 == V2SImode)
8443 type = v2si_ftype_v2si;
8444 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8445 type = v2sf_ftype_v2sf;
8446 else if (mode0 == V2SFmode && mode1 == V2SImode)
8447 type = v2sf_ftype_v2si;
8448 else if (mode0 == V2SImode && mode1 == V2SFmode)
8449 type = v2si_ftype_v2sf;
8450 else if (mode0 == V2SImode && mode1 == QImode)
8451 type = v2si_ftype_char;
8455 def_builtin (d->mask, d->name, type, d->code);
8460 rs6000_init_libfuncs (void)
8462 if (!TARGET_HARD_FLOAT)
8465 if (DEFAULT_ABI != ABI_V4)
8467 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
8469 /* AIX library routines for float->int conversion. */
8470 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
8471 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
8472 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
8473 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
8476 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
8477 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
8478 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
8479 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
8480 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
8484 /* 32-bit SVR4 quad floating point routines. */
8486 set_optab_libfunc (add_optab, TFmode, "_q_add");
8487 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
8488 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
8489 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
8490 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
8491 if (TARGET_PPC_GPOPT || TARGET_POWER2)
8492 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
8494 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
8495 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
8496 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
8497 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
8498 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
8499 set_optab_libfunc (le_optab, TFmode, "_q_fle");
8501 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
8502 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
8503 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
8504 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
8505 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
8506 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
8507 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
8512 /* Expand a block clear operation, and return 1 if successful. Return 0
8513 if we should let the compiler generate normal code.
8515 operands[0] is the destination
8516 operands[1] is the length
8517 operands[2] is the alignment */
8520 expand_block_clear (rtx operands[])
8522 rtx orig_dest = operands[0];
8523 rtx bytes_rtx = operands[1];
8524 rtx align_rtx = operands[2];
8525 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
8526 HOST_WIDE_INT align;
8527 HOST_WIDE_INT bytes;
8532 /* If this is not a fixed size move, just call memcpy */
8536 /* If this is not a fixed size alignment, abort */
8537 if (GET_CODE (align_rtx) != CONST_INT)
8539 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8541 /* Anything to clear? */
8542 bytes = INTVAL (bytes_rtx);
8546 /* Use the builtin memset after a point, to avoid huge code bloat.
8547 When optimize_size, avoid any significant code bloat; calling
8548 memset is about 4 instructions, so allow for one instruction to
8549 load zero and three to do clearing. */
8550 if (TARGET_ALTIVEC && align >= 128)
8552 else if (TARGET_POWERPC64 && align >= 32)
8557 if (optimize_size && bytes > 3 * clear_step)
8559 if (! optimize_size && bytes > 8 * clear_step)
8562 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
8564 enum machine_mode mode = BLKmode;
8567 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
8572 else if (bytes >= 8 && TARGET_POWERPC64
8573 /* 64-bit loads and stores require word-aligned
8575 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8580 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
8581 { /* move 4 bytes */
8585 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
8586 { /* move 2 bytes */
8590 else /* move 1 byte at a time */
8596 dest = adjust_address (orig_dest, mode, offset);
8598 emit_move_insn (dest, CONST0_RTX (mode));
8605 /* Expand a block move operation, and return 1 if successful. Return 0
8606 if we should let the compiler generate normal code.
8608 operands[0] is the destination
8609 operands[1] is the source
8610 operands[2] is the length
8611 operands[3] is the alignment */
8613 #define MAX_MOVE_REG 4
8616 expand_block_move (rtx operands[])
8618 rtx orig_dest = operands[0];
8619 rtx orig_src = operands[1];
8620 rtx bytes_rtx = operands[2];
8621 rtx align_rtx = operands[3];
8622 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
8627 rtx stores[MAX_MOVE_REG];
8630 /* If this is not a fixed size move, just call memcpy */
8634 /* If this is not a fixed size alignment, abort */
8635 if (GET_CODE (align_rtx) != CONST_INT)
8637 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8639 /* Anything to move? */
8640 bytes = INTVAL (bytes_rtx);
8644 /* store_one_arg depends on expand_block_move to handle at least the size of
8645 reg_parm_stack_space. */
8646 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
8649 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
8652 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
8653 rtx (*mov) (rtx, rtx);
8655 enum machine_mode mode = BLKmode;
8658 /* Altivec first, since it will be faster than a string move
8659 when it applies, and usually not significantly larger. */
8660 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
8664 gen_func.mov = gen_movv4si;
8666 else if (TARGET_STRING
8667 && bytes > 24 /* move up to 32 bytes at a time */
8675 && ! fixed_regs[12])
8677 move_bytes = (bytes > 32) ? 32 : bytes;
8678 gen_func.movmemsi = gen_movmemsi_8reg;
8680 else if (TARGET_STRING
8681 && bytes > 16 /* move up to 24 bytes at a time */
8687 && ! fixed_regs[10])
8689 move_bytes = (bytes > 24) ? 24 : bytes;
8690 gen_func.movmemsi = gen_movmemsi_6reg;
8692 else if (TARGET_STRING
8693 && bytes > 8 /* move up to 16 bytes at a time */
8699 move_bytes = (bytes > 16) ? 16 : bytes;
8700 gen_func.movmemsi = gen_movmemsi_4reg;
8702 else if (bytes >= 8 && TARGET_POWERPC64
8703 /* 64-bit loads and stores require word-aligned
8705 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8709 gen_func.mov = gen_movdi;
8711 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
8712 { /* move up to 8 bytes at a time */
8713 move_bytes = (bytes > 8) ? 8 : bytes;
8714 gen_func.movmemsi = gen_movmemsi_2reg;
8716 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
8717 { /* move 4 bytes */
8720 gen_func.mov = gen_movsi;
8722 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
8723 { /* move 2 bytes */
8726 gen_func.mov = gen_movhi;
8728 else if (TARGET_STRING && bytes > 1)
8729 { /* move up to 4 bytes at a time */
8730 move_bytes = (bytes > 4) ? 4 : bytes;
8731 gen_func.movmemsi = gen_movmemsi_1reg;
8733 else /* move 1 byte at a time */
8737 gen_func.mov = gen_movqi;
8740 src = adjust_address (orig_src, mode, offset);
8741 dest = adjust_address (orig_dest, mode, offset);
8743 if (mode != BLKmode)
8745 rtx tmp_reg = gen_reg_rtx (mode);
8747 emit_insn ((*gen_func.mov) (tmp_reg, src));
8748 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
8751 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
8754 for (i = 0; i < num_reg; i++)
8755 emit_insn (stores[i]);
8759 if (mode == BLKmode)
8761 /* Move the address into scratch registers. The movmemsi
8762 patterns require zero offset. */
8763 if (!REG_P (XEXP (src, 0)))
8765 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
8766 src = replace_equiv_address (src, src_reg);
8768 set_mem_size (src, GEN_INT (move_bytes));
8770 if (!REG_P (XEXP (dest, 0)))
8772 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
8773 dest = replace_equiv_address (dest, dest_reg);
8775 set_mem_size (dest, GEN_INT (move_bytes));
8777 emit_insn ((*gen_func.movmemsi) (dest, src,
8778 GEN_INT (move_bytes & 31),
8787 /* Return 1 if OP is suitable for a save_world call in prologue. It is
8788 known to be a PARALLEL. */
8790 save_world_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8795 int count = XVECLEN (op, 0);
8801 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
8802 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
8805 for (i=1; i <= 18; i++)
8807 elt = XVECEXP (op, 0, index++);
8808 if (GET_CODE (elt) != SET
8809 || GET_CODE (SET_DEST (elt)) != MEM
8810 || ! memory_operand (SET_DEST (elt), DFmode)
8811 || GET_CODE (SET_SRC (elt)) != REG
8812 || GET_MODE (SET_SRC (elt)) != DFmode)
8816 for (i=1; i <= 12; i++)
8818 elt = XVECEXP (op, 0, index++);
8819 if (GET_CODE (elt) != SET
8820 || GET_CODE (SET_DEST (elt)) != MEM
8821 || GET_CODE (SET_SRC (elt)) != REG
8822 || GET_MODE (SET_SRC (elt)) != V4SImode)
8826 for (i=1; i <= 19; i++)
8828 elt = XVECEXP (op, 0, index++);
8829 if (GET_CODE (elt) != SET
8830 || GET_CODE (SET_DEST (elt)) != MEM
8831 || ! memory_operand (SET_DEST (elt), Pmode)
8832 || GET_CODE (SET_SRC (elt)) != REG
8833 || GET_MODE (SET_SRC (elt)) != Pmode)
8837 elt = XVECEXP (op, 0, index++);
8838 if (GET_CODE (elt) != SET
8839 || GET_CODE (SET_DEST (elt)) != MEM
8840 || ! memory_operand (SET_DEST (elt), Pmode)
8841 || GET_CODE (SET_SRC (elt)) != REG
8842 || REGNO (SET_SRC (elt)) != CR2_REGNO
8843 || GET_MODE (SET_SRC (elt)) != Pmode)
8846 if (GET_CODE (XVECEXP (op, 0, index++)) != USE
8847 || GET_CODE (XVECEXP (op, 0, index++)) != USE
8848 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
8853 /* Return 1 if OP is suitable for a save_world call in prologue. It is
8854 known to be a PARALLEL. */
8856 restore_world_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8861 int count = XVECLEN (op, 0);
8867 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
8868 || GET_CODE (XVECEXP (op, 0, index++)) != USE
8869 || GET_CODE (XVECEXP (op, 0, index++)) != USE
8870 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
8873 elt = XVECEXP (op, 0, index++);
8874 if (GET_CODE (elt) != SET
8875 || GET_CODE (SET_SRC (elt)) != MEM
8876 || ! memory_operand (SET_SRC (elt), Pmode)
8877 || GET_CODE (SET_DEST (elt)) != REG
8878 || REGNO (SET_DEST (elt)) != CR2_REGNO
8879 || GET_MODE (SET_DEST (elt)) != Pmode)
8882 for (i=1; i <= 19; i++)
8884 elt = XVECEXP (op, 0, index++);
8885 if (GET_CODE (elt) != SET
8886 || GET_CODE (SET_SRC (elt)) != MEM
8887 || ! memory_operand (SET_SRC (elt), Pmode)
8888 || GET_CODE (SET_DEST (elt)) != REG
8889 || GET_MODE (SET_DEST (elt)) != Pmode)
8893 for (i=1; i <= 12; i++)
8895 elt = XVECEXP (op, 0, index++);
8896 if (GET_CODE (elt) != SET
8897 || GET_CODE (SET_SRC (elt)) != MEM
8898 || GET_CODE (SET_DEST (elt)) != REG
8899 || GET_MODE (SET_DEST (elt)) != V4SImode)
8903 for (i=1; i <= 18; i++)
8905 elt = XVECEXP (op, 0, index++);
8906 if (GET_CODE (elt) != SET
8907 || GET_CODE (SET_SRC (elt)) != MEM
8908 || ! memory_operand (SET_SRC (elt), DFmode)
8909 || GET_CODE (SET_DEST (elt)) != REG
8910 || GET_MODE (SET_DEST (elt)) != DFmode)
8914 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
8915 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
8916 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
8917 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
8918 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
8924 /* Return 1 if OP is a load multiple operation. It is known to be a
8925 PARALLEL and the first section will be tested. */
8928 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8930 int count = XVECLEN (op, 0);
8931 unsigned int dest_regno;
8935 /* Perform a quick check so we don't blow up below. */
8937 || GET_CODE (XVECEXP (op, 0, 0)) != SET
8938 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
8939 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
8942 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
8943 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
8945 for (i = 1; i < count; i++)
8947 rtx elt = XVECEXP (op, 0, i);
8949 if (GET_CODE (elt) != SET
8950 || GET_CODE (SET_DEST (elt)) != REG
8951 || GET_MODE (SET_DEST (elt)) != SImode
8952 || REGNO (SET_DEST (elt)) != dest_regno + i
8953 || GET_CODE (SET_SRC (elt)) != MEM
8954 || GET_MODE (SET_SRC (elt)) != SImode
8955 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
8956 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
8957 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
8958 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
8965 /* Similar, but tests for store multiple. Here, the second vector element
8966 is a CLOBBER. It will be tested later. */
8969 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8971 int count = XVECLEN (op, 0) - 1;
8972 unsigned int src_regno;
8976 /* Perform a quick check so we don't blow up below. */
8978 || GET_CODE (XVECEXP (op, 0, 0)) != SET
8979 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
8980 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
8983 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
8984 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
8986 for (i = 1; i < count; i++)
8988 rtx elt = XVECEXP (op, 0, i + 1);
8990 if (GET_CODE (elt) != SET
8991 || GET_CODE (SET_SRC (elt)) != REG
8992 || GET_MODE (SET_SRC (elt)) != SImode
8993 || REGNO (SET_SRC (elt)) != src_regno + i
8994 || GET_CODE (SET_DEST (elt)) != MEM
8995 || GET_MODE (SET_DEST (elt)) != SImode
8996 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
8997 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
8998 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
8999 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
9006 /* Return a string to perform a load_multiple operation.
9007 operands[0] is the vector.
9008 operands[1] is the source address.
9009 operands[2] is the first destination register. */
9012 rs6000_output_load_multiple (rtx operands[3])
9014 /* We have to handle the case where the pseudo used to contain the address
9015 is assigned to one of the output registers. */
9017 int words = XVECLEN (operands[0], 0);
9020 if (XVECLEN (operands[0], 0) == 1)
9021 return "{l|lwz} %2,0(%1)";
9023 for (i = 0; i < words; i++)
9024 if (refers_to_regno_p (REGNO (operands[2]) + i,
9025 REGNO (operands[2]) + i + 1, operands[1], 0))
9029 xop[0] = GEN_INT (4 * (words-1));
9030 xop[1] = operands[1];
9031 xop[2] = operands[2];
9032 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9037 xop[0] = GEN_INT (4 * (words-1));
9038 xop[1] = operands[1];
9039 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9040 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9045 for (j = 0; j < words; j++)
9048 xop[0] = GEN_INT (j * 4);
9049 xop[1] = operands[1];
9050 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9051 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9053 xop[0] = GEN_INT (i * 4);
9054 xop[1] = operands[1];
9055 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9060 return "{lsi|lswi} %2,%1,%N0";
9063 /* Return 1 for a parallel vrsave operation. */
9066 vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9068 int count = XVECLEN (op, 0);
9069 unsigned int dest_regno, src_regno;
9073 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9074 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
9075 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
9078 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
9079 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
9081 if (dest_regno != VRSAVE_REGNO
9082 && src_regno != VRSAVE_REGNO)
9085 for (i = 1; i < count; i++)
9087 rtx elt = XVECEXP (op, 0, i);
9089 if (GET_CODE (elt) != CLOBBER
9090 && GET_CODE (elt) != SET)
9097 /* Return 1 for an PARALLEL suitable for mfcr. */
9100 mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9102 int count = XVECLEN (op, 0);
9105 /* Perform a quick check so we don't blow up below. */
9107 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9108 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
9109 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
9112 for (i = 0; i < count; i++)
9114 rtx exp = XVECEXP (op, 0, i);
9119 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
9121 if (GET_CODE (src_reg) != REG
9122 || GET_MODE (src_reg) != CCmode
9123 || ! CR_REGNO_P (REGNO (src_reg)))
9126 if (GET_CODE (exp) != SET
9127 || GET_CODE (SET_DEST (exp)) != REG
9128 || GET_MODE (SET_DEST (exp)) != SImode
9129 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
9131 unspec = SET_SRC (exp);
9132 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
9134 if (GET_CODE (unspec) != UNSPEC
9135 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
9136 || XVECLEN (unspec, 0) != 2
9137 || XVECEXP (unspec, 0, 0) != src_reg
9138 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
9139 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
9145 /* Return 1 for an PARALLEL suitable for mtcrf. */
9148 mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9150 int count = XVECLEN (op, 0);
9154 /* Perform a quick check so we don't blow up below. */
9156 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9157 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
9158 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
9160 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
9162 if (GET_CODE (src_reg) != REG
9163 || GET_MODE (src_reg) != SImode
9164 || ! INT_REGNO_P (REGNO (src_reg)))
9167 for (i = 0; i < count; i++)
9169 rtx exp = XVECEXP (op, 0, i);
9173 if (GET_CODE (exp) != SET
9174 || GET_CODE (SET_DEST (exp)) != REG
9175 || GET_MODE (SET_DEST (exp)) != CCmode
9176 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
9178 unspec = SET_SRC (exp);
9179 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
9181 if (GET_CODE (unspec) != UNSPEC
9182 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
9183 || XVECLEN (unspec, 0) != 2
9184 || XVECEXP (unspec, 0, 0) != src_reg
9185 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
9186 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
9192 /* Return 1 for an PARALLEL suitable for lmw. */
9195 lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9197 int count = XVECLEN (op, 0);
9198 unsigned int dest_regno;
9200 unsigned int base_regno;
9201 HOST_WIDE_INT offset;
9204 /* Perform a quick check so we don't blow up below. */
9206 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9207 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
9208 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
9211 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
9212 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
9215 || count != 32 - (int) dest_regno)
9218 if (legitimate_indirect_address_p (src_addr, 0))
9221 base_regno = REGNO (src_addr);
9222 if (base_regno == 0)
9225 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
9227 offset = INTVAL (XEXP (src_addr, 1));
9228 base_regno = REGNO (XEXP (src_addr, 0));
9233 for (i = 0; i < count; i++)
9235 rtx elt = XVECEXP (op, 0, i);
9238 HOST_WIDE_INT newoffset;
9240 if (GET_CODE (elt) != SET
9241 || GET_CODE (SET_DEST (elt)) != REG
9242 || GET_MODE (SET_DEST (elt)) != SImode
9243 || REGNO (SET_DEST (elt)) != dest_regno + i
9244 || GET_CODE (SET_SRC (elt)) != MEM
9245 || GET_MODE (SET_SRC (elt)) != SImode)
9247 newaddr = XEXP (SET_SRC (elt), 0);
9248 if (legitimate_indirect_address_p (newaddr, 0))
9253 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
9255 addr_reg = XEXP (newaddr, 0);
9256 newoffset = INTVAL (XEXP (newaddr, 1));
9260 if (REGNO (addr_reg) != base_regno
9261 || newoffset != offset + 4 * i)
9268 /* Return 1 for an PARALLEL suitable for stmw. */
9271 stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9273 int count = XVECLEN (op, 0);
9274 unsigned int src_regno;
9276 unsigned int base_regno;
9277 HOST_WIDE_INT offset;
9280 /* Perform a quick check so we don't blow up below. */
9282 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9283 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
9284 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
9287 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
9288 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
9291 || count != 32 - (int) src_regno)
9294 if (legitimate_indirect_address_p (dest_addr, 0))
9297 base_regno = REGNO (dest_addr);
9298 if (base_regno == 0)
9301 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
9303 offset = INTVAL (XEXP (dest_addr, 1));
9304 base_regno = REGNO (XEXP (dest_addr, 0));
9309 for (i = 0; i < count; i++)
9311 rtx elt = XVECEXP (op, 0, i);
9314 HOST_WIDE_INT newoffset;
9316 if (GET_CODE (elt) != SET
9317 || GET_CODE (SET_SRC (elt)) != REG
9318 || GET_MODE (SET_SRC (elt)) != SImode
9319 || REGNO (SET_SRC (elt)) != src_regno + i
9320 || GET_CODE (SET_DEST (elt)) != MEM
9321 || GET_MODE (SET_DEST (elt)) != SImode)
9323 newaddr = XEXP (SET_DEST (elt), 0);
9324 if (legitimate_indirect_address_p (newaddr, 0))
9329 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
9331 addr_reg = XEXP (newaddr, 0);
9332 newoffset = INTVAL (XEXP (newaddr, 1));
9336 if (REGNO (addr_reg) != base_regno
9337 || newoffset != offset + 4 * i)
9344 /* A validation routine: say whether CODE, a condition code, and MODE
9345 match. The other alternatives either don't make sense or should
9346 never be generated. */
9349 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9351 if ((GET_RTX_CLASS (code) != RTX_COMPARE
9352 && GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
9353 || GET_MODE_CLASS (mode) != MODE_CC)
9356 /* These don't make sense. */
9357 if ((code == GT || code == LT || code == GE || code == LE)
9358 && mode == CCUNSmode)
9361 if ((code == GTU || code == LTU || code == GEU || code == LEU)
9362 && mode != CCUNSmode)
9365 if (mode != CCFPmode
9366 && (code == ORDERED || code == UNORDERED
9367 || code == UNEQ || code == LTGT
9368 || code == UNGT || code == UNLT
9369 || code == UNGE || code == UNLE))
9372 /* These should never be generated except for
9373 flag_finite_math_only. */
9374 if (mode == CCFPmode
9375 && ! flag_finite_math_only
9376 && (code == LE || code == GE
9377 || code == UNEQ || code == LTGT
9378 || code == UNGT || code == UNLT))
9381 /* These are invalid; the information is not there. */
9382 if (mode == CCEQmode
9383 && code != EQ && code != NE)
9387 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
9388 We only check the opcode against the mode of the CC value here. */
9391 branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9393 enum rtx_code code = GET_CODE (op);
9394 enum machine_mode cc_mode;
9396 if (!COMPARISON_P (op))
9399 cc_mode = GET_MODE (XEXP (op, 0));
9400 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
9403 validate_condition_mode (code, cc_mode);
9408 /* Return 1 if OP is a comparison operation that is valid for a branch
9409 insn and which is true if the corresponding bit in the CC register
9413 branch_positive_comparison_operator (rtx op, enum machine_mode mode)
9417 if (! branch_comparison_operator (op, mode))
9420 code = GET_CODE (op);
9421 return (code == EQ || code == LT || code == GT
9422 || code == LTU || code == GTU
9423 || code == UNORDERED);
9426 /* Return 1 if OP is a comparison operation that is valid for an scc
9427 insn: it must be a positive comparison. */
9430 scc_comparison_operator (rtx op, enum machine_mode mode)
9432 return branch_positive_comparison_operator (op, mode);
9436 trap_comparison_operator (rtx op, enum machine_mode mode)
9438 if (mode != VOIDmode && mode != GET_MODE (op))
9440 return COMPARISON_P (op);
9444 boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9446 enum rtx_code code = GET_CODE (op);
9447 return (code == AND || code == IOR || code == XOR);
9451 boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9453 enum rtx_code code = GET_CODE (op);
9454 return (code == IOR || code == XOR);
9458 min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9460 enum rtx_code code = GET_CODE (op);
9461 return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
9464 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9465 mask required to convert the result of a rotate insn into a shift
9466 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9469 includes_lshift_p (rtx shiftop, rtx andop)
9471 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9473 shift_mask <<= INTVAL (shiftop);
9475 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9478 /* Similar, but for right shift. */
9481 includes_rshift_p (rtx shiftop, rtx andop)
9483 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9485 shift_mask >>= INTVAL (shiftop);
9487 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9490 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9491 to perform a left shift. It must have exactly SHIFTOP least
9492 significant 0's, then one or more 1's, then zero or more 0's. */
9495 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9497 if (GET_CODE (andop) == CONST_INT)
9499 HOST_WIDE_INT c, lsb, shift_mask;
9502 if (c == 0 || c == ~0)
9506 shift_mask <<= INTVAL (shiftop);
9508 /* Find the least significant one bit. */
9511 /* It must coincide with the LSB of the shift mask. */
9512 if (-lsb != shift_mask)
9515 /* Invert to look for the next transition (if any). */
9518 /* Remove the low group of ones (originally low group of zeros). */
9521 /* Again find the lsb, and check we have all 1's above. */
9525 else if (GET_CODE (andop) == CONST_DOUBLE
9526 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9528 HOST_WIDE_INT low, high, lsb;
9529 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9531 low = CONST_DOUBLE_LOW (andop);
9532 if (HOST_BITS_PER_WIDE_INT < 64)
9533 high = CONST_DOUBLE_HIGH (andop);
9535 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9536 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9539 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9541 shift_mask_high = ~0;
9542 if (INTVAL (shiftop) > 32)
9543 shift_mask_high <<= INTVAL (shiftop) - 32;
9547 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9554 return high == -lsb;
9557 shift_mask_low = ~0;
9558 shift_mask_low <<= INTVAL (shiftop);
9562 if (-lsb != shift_mask_low)
9565 if (HOST_BITS_PER_WIDE_INT < 64)
9570 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9573 return high == -lsb;
9577 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9583 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9584 to perform a left shift. It must have SHIFTOP or more least
9585 significant 0's, with the remainder of the word 1's. */
9588 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9590 if (GET_CODE (andop) == CONST_INT)
9592 HOST_WIDE_INT c, lsb, shift_mask;
9595 shift_mask <<= INTVAL (shiftop);
9598 /* Find the least significant one bit. */
9601 /* It must be covered by the shift mask.
9602 This test also rejects c == 0. */
9603 if ((lsb & shift_mask) == 0)
9606 /* Check we have all 1's above the transition, and reject all 1's. */
9607 return c == -lsb && lsb != 1;
9609 else if (GET_CODE (andop) == CONST_DOUBLE
9610 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9612 HOST_WIDE_INT low, lsb, shift_mask_low;
9614 low = CONST_DOUBLE_LOW (andop);
9616 if (HOST_BITS_PER_WIDE_INT < 64)
9618 HOST_WIDE_INT high, shift_mask_high;
9620 high = CONST_DOUBLE_HIGH (andop);
9624 shift_mask_high = ~0;
9625 if (INTVAL (shiftop) > 32)
9626 shift_mask_high <<= INTVAL (shiftop) - 32;
9630 if ((lsb & shift_mask_high) == 0)
9633 return high == -lsb;
9639 shift_mask_low = ~0;
9640 shift_mask_low <<= INTVAL (shiftop);
9644 if ((lsb & shift_mask_low) == 0)
9647 return low == -lsb && lsb != 1;
9653 /* Return 1 if operands will generate a valid arguments to rlwimi
9654 instruction for insert with right shift in 64-bit mode. The mask may
9655 not start on the first bit or stop on the last bit because wrap-around
9656 effects of instruction do not correspond to semantics of RTL insn. */
9659 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9661 if (INTVAL (startop) < 64
9662 && INTVAL (startop) > 32
9663 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9664 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9665 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9666 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9667 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9673 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9674 for lfq and stfq insns iff the registers are hard registers. */
9677 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
9679 /* We might have been passed a SUBREG. */
9680 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
9683 /* We might have been passed non floating point registers. */
9684 if (!FP_REGNO_P (REGNO (reg1))
9685 || !FP_REGNO_P (REGNO (reg2)))
9688 return (REGNO (reg1) == REGNO (reg2) - 1);
9691 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9692 addr1 and addr2 must be in consecutive memory locations
9693 (addr2 == addr1 + 8). */
9696 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
9702 /* The mems cannot be volatile. */
9703 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9706 addr1 = XEXP (mem1, 0);
9707 addr2 = XEXP (mem2, 0);
9709 /* Extract an offset (if used) from the first addr. */
9710 if (GET_CODE (addr1) == PLUS)
9712 /* If not a REG, return zero. */
9713 if (GET_CODE (XEXP (addr1, 0)) != REG)
9717 reg1 = REGNO (XEXP (addr1, 0));
9718 /* The offset must be constant! */
9719 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
9721 offset1 = INTVAL (XEXP (addr1, 1));
9724 else if (GET_CODE (addr1) != REG)
9728 reg1 = REGNO (addr1);
9729 /* This was a simple (mem (reg)) expression. Offset is 0. */
9733 /* Make sure the second address is a (mem (plus (reg) (const_int)))
9734 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
9735 register as addr1. */
9736 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
9738 if (GET_CODE (addr2) != PLUS)
9741 if (GET_CODE (XEXP (addr2, 0)) != REG
9742 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9745 if (reg1 != REGNO (XEXP (addr2, 0)))
9748 /* The offset for the second addr must be 8 more than the first addr. */
9749 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
9752 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9757 /* Return the register class of a scratch register needed to copy IN into
9758 or out of a register in CLASS in MODE. If it can be done directly,
9759 NO_REGS is returned. */
9762 secondary_reload_class (enum reg_class class,
9763 enum machine_mode mode ATTRIBUTE_UNUSED,
9768 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9770 && MACHOPIC_INDIRECT
9774 /* We cannot copy a symbolic operand directly into anything
9775 other than BASE_REGS for TARGET_ELF. So indicate that a
9776 register from BASE_REGS is needed as an intermediate
9779 On Darwin, pic addresses require a load from memory, which
9780 needs a base register. */
9781 if (class != BASE_REGS
9782 && (GET_CODE (in) == SYMBOL_REF
9783 || GET_CODE (in) == HIGH
9784 || GET_CODE (in) == LABEL_REF
9785 || GET_CODE (in) == CONST))
9789 if (GET_CODE (in) == REG)
9792 if (regno >= FIRST_PSEUDO_REGISTER)
9794 regno = true_regnum (in);
9795 if (regno >= FIRST_PSEUDO_REGISTER)
9799 else if (GET_CODE (in) == SUBREG)
9801 regno = true_regnum (in);
9802 if (regno >= FIRST_PSEUDO_REGISTER)
9808 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9810 if (class == GENERAL_REGS || class == BASE_REGS
9811 || (regno >= 0 && INT_REGNO_P (regno)))
9814 /* Constants, memory, and FP registers can go into FP registers. */
9815 if ((regno == -1 || FP_REGNO_P (regno))
9816 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
9819 /* Memory, and AltiVec registers can go into AltiVec registers. */
9820 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
9821 && class == ALTIVEC_REGS)
9824 /* We can copy among the CR registers. */
9825 if ((class == CR_REGS || class == CR0_REGS)
9826 && regno >= 0 && CR_REGNO_P (regno))
9829 /* Otherwise, we need GENERAL_REGS. */
9830 return GENERAL_REGS;
9833 /* Given a comparison operation, return the bit number in CCR to test. We
9834 know this is a valid comparison.
9836 SCC_P is 1 if this is for an scc. That means that %D will have been
9837 used instead of %C, so the bits will be in different places.
9839 Return -1 if OP isn't a valid comparison for some reason. */
9842 ccr_bit (rtx op, int scc_p)
9844 enum rtx_code code = GET_CODE (op);
9845 enum machine_mode cc_mode;
9850 if (!COMPARISON_P (op))
9855 if (GET_CODE (reg) != REG
9856 || ! CR_REGNO_P (REGNO (reg)))
9859 cc_mode = GET_MODE (reg);
9860 cc_regnum = REGNO (reg);
9861 base_bit = 4 * (cc_regnum - CR0_REGNO);
9863 validate_condition_mode (code, cc_mode);
9865 /* When generating a sCOND operation, only positive conditions are
9867 if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
9868 && code != GTU && code != LTU)
9874 return scc_p ? base_bit + 3 : base_bit + 2;
9876 return base_bit + 2;
9877 case GT: case GTU: case UNLE:
9878 return base_bit + 1;
9879 case LT: case LTU: case UNGE:
9881 case ORDERED: case UNORDERED:
9882 return base_bit + 3;
9885 /* If scc, we will have done a cror to put the bit in the
9886 unordered position. So test that bit. For integer, this is ! LT
9887 unless this is an scc insn. */
9888 return scc_p ? base_bit + 3 : base_bit;
9891 return scc_p ? base_bit + 3 : base_bit + 1;
9898 /* Return the GOT register. */
9901 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
9903 /* The second flow pass currently (June 1999) can't update
9904 regs_ever_live without disturbing other parts of the compiler, so
9905 update it here to make the prolog/epilogue code happy. */
9906 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
9907 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9909 current_function_uses_pic_offset_table = 1;
9911 return pic_offset_table_rtx;
9914 /* Function to init struct machine_function.
9915 This will be called, via a pointer variable,
9916 from push_function_context. */
9918 static struct machine_function *
9919 rs6000_init_machine_status (void)
9921 return ggc_alloc_cleared (sizeof (machine_function));
9924 /* These macros test for integers and extract the low-order bits. */
9926 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9927 && GET_MODE (X) == VOIDmode)
9929 #define INT_LOWPART(X) \
9930 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9936 unsigned long val = INT_LOWPART (op);
9938 /* If the high bit is zero, the value is the first 1 bit we find
9940 if ((val & 0x80000000) == 0)
9942 if ((val & 0xffffffff) == 0)
9946 while (((val <<= 1) & 0x80000000) == 0)
9951 /* If the high bit is set and the low bit is not, or the mask is all
9952 1's, the value is zero. */
9953 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
9956 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9959 while (((val >>= 1) & 1) != 0)
9969 unsigned long val = INT_LOWPART (op);
9971 /* If the low bit is zero, the value is the first 1 bit we find from
9975 if ((val & 0xffffffff) == 0)
9979 while (((val >>= 1) & 1) == 0)
9985 /* If the low bit is set and the high bit is not, or the mask is all
9986 1's, the value is 31. */
9987 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
9990 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9993 while (((val <<= 1) & 0x80000000) != 0)
9999 /* Locate some local-dynamic symbol still in use by this function
10000 so that we can print its name in some tls_ld pattern. */
10002 static const char *
10003 rs6000_get_some_local_dynamic_name (void)
10007 if (cfun->machine->some_ld_name)
10008 return cfun->machine->some_ld_name;
10010 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10012 && for_each_rtx (&PATTERN (insn),
10013 rs6000_get_some_local_dynamic_name_1, 0))
10014 return cfun->machine->some_ld_name;
10019 /* Helper function for rs6000_get_some_local_dynamic_name. */
10022 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10026 if (GET_CODE (x) == SYMBOL_REF)
10028 const char *str = XSTR (x, 0);
10029 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10031 cfun->machine->some_ld_name = str;
10039 /* Write out a function code label. */
10042 rs6000_output_function_entry (FILE *file, const char *fname)
10044 if (fname[0] != '.')
10046 switch (DEFAULT_ABI)
10055 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10064 RS6000_OUTPUT_BASENAME (file, fname);
10066 assemble_name (file, fname);
10069 /* Print an operand. Recognize special options, documented below. */
10072 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10073 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10075 #define SMALL_DATA_RELOC "sda21"
10076 #define SMALL_DATA_REG 0
10080 print_operand (FILE *file, rtx x, int code)
10084 unsigned HOST_WIDE_INT uval;
10089 /* Write out an instruction after the call which may be replaced
10090 with glue code by the loader. This depends on the AIX version. */
10091 asm_fprintf (file, RS6000_CALL_GLUE);
10094 /* %a is output_address. */
10097 /* If X is a constant integer whose low-order 5 bits are zero,
10098 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10099 in the AIX assembler where "sri" with a zero shift count
10100 writes a trash instruction. */
10101 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10108 /* If constant, low-order 16 bits of constant, unsigned.
10109 Otherwise, write normally. */
10111 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10113 print_operand (file, x, 0);
10117 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10118 for 64-bit mask direction. */
10119 putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
10122 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10126 /* X is a CR register. Print the number of the GT bit of the CR. */
10127 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10128 output_operand_lossage ("invalid %%E value");
10130 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10134 /* Like 'J' but get to the EQ bit. */
10135 if (GET_CODE (x) != REG)
10138 /* Bit 1 is EQ bit. */
10139 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
10141 /* If we want bit 31, write a shift count of zero, not 32. */
10142 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10146 /* X is a CR register. Print the number of the EQ bit of the CR */
10147 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10148 output_operand_lossage ("invalid %%E value");
10150 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10154 /* X is a CR register. Print the shift count needed to move it
10155 to the high-order four bits. */
10156 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10157 output_operand_lossage ("invalid %%f value");
10159 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10163 /* Similar, but print the count for the rotate in the opposite
10165 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10166 output_operand_lossage ("invalid %%F value");
10168 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10172 /* X is a constant integer. If it is negative, print "m",
10173 otherwise print "z". This is to make an aze or ame insn. */
10174 if (GET_CODE (x) != CONST_INT)
10175 output_operand_lossage ("invalid %%G value");
10176 else if (INTVAL (x) >= 0)
10183 /* If constant, output low-order five bits. Otherwise, write
10186 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10188 print_operand (file, x, 0);
10192 /* If constant, output low-order six bits. Otherwise, write
10195 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10197 print_operand (file, x, 0);
10201 /* Print `i' if this is a constant, else nothing. */
10207 /* Write the bit number in CCR for jump. */
10208 i = ccr_bit (x, 0);
10210 output_operand_lossage ("invalid %%j code");
10212 fprintf (file, "%d", i);
10216 /* Similar, but add one for shift count in rlinm for scc and pass
10217 scc flag to `ccr_bit'. */
10218 i = ccr_bit (x, 1);
10220 output_operand_lossage ("invalid %%J code");
10222 /* If we want bit 31, write a shift count of zero, not 32. */
10223 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10227 /* X must be a constant. Write the 1's complement of the
10230 output_operand_lossage ("invalid %%k value");
10232 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10236 /* X must be a symbolic constant on ELF. Write an
10237 expression suitable for an 'addi' that adds in the low 16
10238 bits of the MEM. */
10239 if (GET_CODE (x) != CONST)
10241 print_operand_address (file, x);
10242 fputs ("@l", file);
10246 if (GET_CODE (XEXP (x, 0)) != PLUS
10247 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10248 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10249 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10250 output_operand_lossage ("invalid %%K value");
10251 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10252 fputs ("@l", file);
10253 /* For GNU as, there must be a non-alphanumeric character
10254 between 'l' and the number. The '-' is added by
10255 print_operand() already. */
10256 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10258 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10262 /* %l is output_asm_label. */
10265 /* Write second word of DImode or DFmode reference. Works on register
10266 or non-indexed memory only. */
10267 if (GET_CODE (x) == REG)
10268 fputs (reg_names[REGNO (x) + 1], file);
10269 else if (GET_CODE (x) == MEM)
10271 /* Handle possible auto-increment. Since it is pre-increment and
10272 we have already done it, we can just use an offset of word. */
10273 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10274 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10275 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10278 output_address (XEXP (adjust_address_nv (x, SImode,
10282 if (small_data_operand (x, GET_MODE (x)))
10283 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10284 reg_names[SMALL_DATA_REG]);
10289 /* MB value for a mask operand. */
10290 if (! mask_operand (x, SImode))
10291 output_operand_lossage ("invalid %%m value");
10293 fprintf (file, "%d", extract_MB (x));
10297 /* ME value for a mask operand. */
10298 if (! mask_operand (x, SImode))
10299 output_operand_lossage ("invalid %%M value");
10301 fprintf (file, "%d", extract_ME (x));
10304 /* %n outputs the negative of its operand. */
10307 /* Write the number of elements in the vector times 4. */
10308 if (GET_CODE (x) != PARALLEL)
10309 output_operand_lossage ("invalid %%N value");
10311 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10315 /* Similar, but subtract 1 first. */
10316 if (GET_CODE (x) != PARALLEL)
10317 output_operand_lossage ("invalid %%O value");
10319 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10323 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10325 || INT_LOWPART (x) < 0
10326 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10327 output_operand_lossage ("invalid %%p value");
10329 fprintf (file, "%d", i);
10333 /* The operand must be an indirect memory reference. The result
10334 is the register name. */
10335 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10336 || REGNO (XEXP (x, 0)) >= 32)
10337 output_operand_lossage ("invalid %%P value");
10339 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10343 /* This outputs the logical code corresponding to a boolean
10344 expression. The expression may have one or both operands
10345 negated (if one, only the first one). For condition register
10346 logical operations, it will also treat the negated
10347 CR codes as NOTs, but not handle NOTs of them. */
10349 const char *const *t = 0;
10351 enum rtx_code code = GET_CODE (x);
10352 static const char * const tbl[3][3] = {
10353 { "and", "andc", "nor" },
10354 { "or", "orc", "nand" },
10355 { "xor", "eqv", "xor" } };
10359 else if (code == IOR)
10361 else if (code == XOR)
10364 output_operand_lossage ("invalid %%q value");
10366 if (GET_CODE (XEXP (x, 0)) != NOT)
10370 if (GET_CODE (XEXP (x, 1)) == NOT)
10388 /* X is a CR register. Print the mask for `mtcrf'. */
10389 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10390 output_operand_lossage ("invalid %%R value");
10392 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10396 /* Low 5 bits of 32 - value */
10398 output_operand_lossage ("invalid %%s value");
10400 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10404 /* PowerPC64 mask position. All 0's is excluded.
10405 CONST_INT 32-bit mask is considered sign-extended so any
10406 transition must occur within the CONST_INT, not on the boundary. */
10407 if (! mask64_operand (x, DImode))
10408 output_operand_lossage ("invalid %%S value");
10410 uval = INT_LOWPART (x);
10412 if (uval & 1) /* Clear Left */
10414 #if HOST_BITS_PER_WIDE_INT > 64
10415 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10419 else /* Clear Right */
10422 #if HOST_BITS_PER_WIDE_INT > 64
10423 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10431 fprintf (file, "%d", i);
10435 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10436 if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
10439 /* Bit 3 is OV bit. */
10440 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10442 /* If we want bit 31, write a shift count of zero, not 32. */
10443 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10447 /* Print the symbolic name of a branch target register. */
10448 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10449 && REGNO (x) != COUNT_REGISTER_REGNUM))
10450 output_operand_lossage ("invalid %%T value");
10451 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10452 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10454 fputs ("ctr", file);
10458 /* High-order 16 bits of constant for use in unsigned operand. */
10460 output_operand_lossage ("invalid %%u value");
10462 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10463 (INT_LOWPART (x) >> 16) & 0xffff);
10467 /* High-order 16 bits of constant for use in signed operand. */
10469 output_operand_lossage ("invalid %%v value");
10471 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10472 (INT_LOWPART (x) >> 16) & 0xffff);
10476 /* Print `u' if this has an auto-increment or auto-decrement. */
10477 if (GET_CODE (x) == MEM
10478 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10479 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10484 /* Print the trap code for this operand. */
10485 switch (GET_CODE (x))
10488 fputs ("eq", file); /* 4 */
10491 fputs ("ne", file); /* 24 */
10494 fputs ("lt", file); /* 16 */
10497 fputs ("le", file); /* 20 */
10500 fputs ("gt", file); /* 8 */
10503 fputs ("ge", file); /* 12 */
10506 fputs ("llt", file); /* 2 */
10509 fputs ("lle", file); /* 6 */
10512 fputs ("lgt", file); /* 1 */
10515 fputs ("lge", file); /* 5 */
10523 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10526 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10527 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10529 print_operand (file, x, 0);
10533 /* MB value for a PowerPC64 rldic operand. */
10534 val = (GET_CODE (x) == CONST_INT
10535 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10540 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10541 if ((val <<= 1) < 0)
10544 #if HOST_BITS_PER_WIDE_INT == 32
10545 if (GET_CODE (x) == CONST_INT && i >= 0)
10546 i += 32; /* zero-extend high-part was all 0's */
10547 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10549 val = CONST_DOUBLE_LOW (x);
10556 for ( ; i < 64; i++)
10557 if ((val <<= 1) < 0)
10562 fprintf (file, "%d", i + 1);
10566 if (GET_CODE (x) == MEM
10567 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10572 /* Like 'L', for third word of TImode */
10573 if (GET_CODE (x) == REG)
10574 fputs (reg_names[REGNO (x) + 2], file);
10575 else if (GET_CODE (x) == MEM)
10577 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10578 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10579 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10581 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10582 if (small_data_operand (x, GET_MODE (x)))
10583 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10584 reg_names[SMALL_DATA_REG]);
10589 /* X is a SYMBOL_REF. Write out the name preceded by a
10590 period and without any trailing data in brackets. Used for function
10591 names. If we are configured for System V (or the embedded ABI) on
10592 the PowerPC, do not emit the period, since those systems do not use
10593 TOCs and the like. */
10594 if (GET_CODE (x) != SYMBOL_REF)
10597 /* Mark the decl as referenced so that cgraph will output the
10599 if (SYMBOL_REF_DECL (x))
10600 mark_decl_referenced (SYMBOL_REF_DECL (x));
10602 /* For macho, check to see if we need a stub. */
10605 const char *name = XSTR (x, 0);
10607 if (MACHOPIC_INDIRECT
10608 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10609 name = machopic_indirection_name (x, /*stub_p=*/true);
10611 assemble_name (file, name);
10613 else if (!DOT_SYMBOLS)
10614 assemble_name (file, XSTR (x, 0));
10616 rs6000_output_function_entry (file, XSTR (x, 0));
10620 /* Like 'L', for last word of TImode. */
10621 if (GET_CODE (x) == REG)
10622 fputs (reg_names[REGNO (x) + 3], file);
10623 else if (GET_CODE (x) == MEM)
10625 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10626 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10627 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10629 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10630 if (small_data_operand (x, GET_MODE (x)))
10631 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10632 reg_names[SMALL_DATA_REG]);
10636 /* Print AltiVec or SPE memory operand. */
10641 if (GET_CODE (x) != MEM)
10648 /* Handle [reg]. */
10649 if (GET_CODE (tmp) == REG)
10651 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10654 /* Handle [reg+UIMM]. */
10655 else if (GET_CODE (tmp) == PLUS &&
10656 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10660 if (GET_CODE (XEXP (tmp, 0)) != REG)
10663 x = INTVAL (XEXP (tmp, 1));
10664 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10668 /* Fall through. Must be [reg+reg]. */
10671 && GET_CODE (tmp) == AND
10672 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10673 && INTVAL (XEXP (tmp, 1)) == -16)
10674 tmp = XEXP (tmp, 0);
10675 if (GET_CODE (tmp) == REG)
10676 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
10677 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
10679 if (REGNO (XEXP (tmp, 0)) == 0)
10680 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10681 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10683 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10684 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10692 if (GET_CODE (x) == REG)
10693 fprintf (file, "%s", reg_names[REGNO (x)]);
10694 else if (GET_CODE (x) == MEM)
10696 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10697 know the width from the mode. */
10698 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
10699 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10700 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10701 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
10702 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10703 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10705 output_address (XEXP (x, 0));
10708 output_addr_const (file, x);
10712 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10716 output_operand_lossage ("invalid %%xn code");
10720 /* Print the address of an operand. */
10723 print_operand_address (FILE *file, rtx x)
10725 if (GET_CODE (x) == REG)
10726 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
10727 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10728 || GET_CODE (x) == LABEL_REF)
10730 output_addr_const (file, x);
10731 if (small_data_operand (x, GET_MODE (x)))
10732 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10733 reg_names[SMALL_DATA_REG]);
10734 else if (TARGET_TOC)
10737 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10739 if (REGNO (XEXP (x, 0)) == 0)
10740 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10741 reg_names[ REGNO (XEXP (x, 0)) ]);
10743 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10744 reg_names[ REGNO (XEXP (x, 1)) ]);
10746 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
10747 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10748 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
10750 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10751 && CONSTANT_P (XEXP (x, 1)))
10753 output_addr_const (file, XEXP (x, 1));
10754 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10758 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10759 && CONSTANT_P (XEXP (x, 1)))
10761 fprintf (file, "lo16(");
10762 output_addr_const (file, XEXP (x, 1));
10763 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10766 else if (legitimate_constant_pool_address_p (x))
10768 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
10770 rtx contains_minus = XEXP (x, 1);
10774 /* Find the (minus (sym) (toc)) buried in X, and temporarily
10775 turn it into (sym) for output_addr_const. */
10776 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10777 contains_minus = XEXP (contains_minus, 0);
10779 minus = XEXP (contains_minus, 0);
10780 symref = XEXP (minus, 0);
10781 XEXP (contains_minus, 0) = symref;
10786 name = XSTR (symref, 0);
10787 newname = alloca (strlen (name) + sizeof ("@toc"));
10788 strcpy (newname, name);
10789 strcat (newname, "@toc");
10790 XSTR (symref, 0) = newname;
10792 output_addr_const (file, XEXP (x, 1));
10794 XSTR (symref, 0) = name;
10795 XEXP (contains_minus, 0) = minus;
10798 output_addr_const (file, XEXP (x, 1));
10800 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
10806 /* Target hook for assembling integer objects. The PowerPC version has
10807 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10808 is defined. It also needs to handle DI-mode objects on 64-bit
10812 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
10814 #ifdef RELOCATABLE_NEEDS_FIXUP
10815 /* Special handling for SI values. */
10816 if (size == 4 && aligned_p)
10818 extern int in_toc_section (void);
10819 static int recurse = 0;
10821 /* For -mrelocatable, we mark all addresses that need to be fixed up
10822 in the .fixup section. */
10823 if (TARGET_RELOCATABLE
10824 && !in_toc_section ()
10825 && !in_text_section ()
10826 && !in_unlikely_text_section ()
10828 && GET_CODE (x) != CONST_INT
10829 && GET_CODE (x) != CONST_DOUBLE
10835 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
10837 ASM_OUTPUT_LABEL (asm_out_file, buf);
10838 fprintf (asm_out_file, "\t.long\t(");
10839 output_addr_const (asm_out_file, x);
10840 fprintf (asm_out_file, ")@fixup\n");
10841 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
10842 ASM_OUTPUT_ALIGN (asm_out_file, 2);
10843 fprintf (asm_out_file, "\t.long\t");
10844 assemble_name (asm_out_file, buf);
10845 fprintf (asm_out_file, "\n\t.previous\n");
10849 /* Remove initial .'s to turn a -mcall-aixdesc function
10850 address into the address of the descriptor, not the function
10852 else if (GET_CODE (x) == SYMBOL_REF
10853 && XSTR (x, 0)[0] == '.'
10854 && DEFAULT_ABI == ABI_AIX)
10856 const char *name = XSTR (x, 0);
10857 while (*name == '.')
10860 fprintf (asm_out_file, "\t.long\t%s\n", name);
10864 #endif /* RELOCATABLE_NEEDS_FIXUP */
10865 return default_assemble_integer (x, size, aligned_p);
10868 #ifdef HAVE_GAS_HIDDEN
10869 /* Emit an assembler directive to set symbol visibility for DECL to
10870 VISIBILITY_TYPE. */
10873 rs6000_assemble_visibility (tree decl, int vis)
10875 /* Functions need to have their entry point symbol visibility set as
10876 well as their descriptor symbol visibility. */
10877 if (DEFAULT_ABI == ABI_AIX
10879 && TREE_CODE (decl) == FUNCTION_DECL)
10881 static const char * const visibility_types[] = {
10882 NULL, "internal", "hidden", "protected"
10885 const char *name, *type;
10887 name = ((* targetm.strip_name_encoding)
10888 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
10889 type = visibility_types[vis];
10891 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
10892 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
10895 default_assemble_visibility (decl, vis);
10900 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
10902 /* Reversal of FP compares takes care -- an ordered compare
10903 becomes an unordered compare and vice versa. */
10904 if (mode == CCFPmode
10905 && (!flag_finite_math_only
10906 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
10907 || code == UNEQ || code == LTGT))
10908 return reverse_condition_maybe_unordered (code);
10910 return reverse_condition (code);
10913 /* Generate a compare for CODE. Return a brand-new rtx that
10914 represents the result of the compare. */
10917 rs6000_generate_compare (enum rtx_code code)
10919 enum machine_mode comp_mode;
10920 rtx compare_result;
10922 if (rs6000_compare_fp_p)
10923 comp_mode = CCFPmode;
10924 else if (code == GTU || code == LTU
10925 || code == GEU || code == LEU)
10926 comp_mode = CCUNSmode;
10927 else if ((code == EQ || code == NE)
10928 && GET_CODE (rs6000_compare_op0) == SUBREG
10929 && GET_CODE (rs6000_compare_op1) == SUBREG
10930 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
10931 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
10932 /* These are unsigned values, perhaps there will be a later
10933 ordering compare that can be shared with this one.
10934 Unfortunately we cannot detect the signedness of the operands
10935 for non-subregs. */
10936 comp_mode = CCUNSmode;
10938 comp_mode = CCmode;
10940 /* First, the compare. */
10941 compare_result = gen_reg_rtx (comp_mode);
10943 /* SPE FP compare instructions on the GPRs. Yuck! */
10944 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10945 && rs6000_compare_fp_p)
10947 rtx cmp, or1, or2, or_result, compare_result2;
10948 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
10950 if (op_mode == VOIDmode)
10951 op_mode = GET_MODE (rs6000_compare_op1);
10953 /* Note: The E500 comparison instructions set the GT bit (x +
10954 1), on success. This explains the mess. */
10958 case EQ: case UNEQ: case NE: case LTGT:
10959 if (op_mode == SFmode)
10960 cmp = flag_finite_math_only
10961 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
10962 rs6000_compare_op1)
10963 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
10964 rs6000_compare_op1);
10965 else if (op_mode == DFmode)
10966 cmp = flag_finite_math_only
10967 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
10968 rs6000_compare_op1)
10969 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
10970 rs6000_compare_op1);
10973 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
10974 if (op_mode == SFmode)
10975 cmp = flag_finite_math_only
10976 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
10977 rs6000_compare_op1)
10978 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
10979 rs6000_compare_op1);
10980 else if (op_mode == DFmode)
10981 cmp = flag_finite_math_only
10982 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
10983 rs6000_compare_op1)
10984 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
10985 rs6000_compare_op1);
10988 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
10989 if (op_mode == SFmode)
10990 cmp = flag_finite_math_only
10991 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
10992 rs6000_compare_op1)
10993 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
10994 rs6000_compare_op1);
10995 else if (op_mode == DFmode)
10996 cmp = flag_finite_math_only
10997 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
10998 rs6000_compare_op1)
10999 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11000 rs6000_compare_op1);
11007 /* Synthesize LE and GE from LT/GT || EQ. */
11008 if (code == LE || code == GE || code == LEU || code == GEU)
11014 case LE: code = LT; break;
11015 case GE: code = GT; break;
11016 case LEU: code = LT; break;
11017 case GEU: code = GT; break;
11021 or1 = gen_reg_rtx (SImode);
11022 or2 = gen_reg_rtx (SImode);
11023 or_result = gen_reg_rtx (CCEQmode);
11024 compare_result2 = gen_reg_rtx (CCFPmode);
11027 if (op_mode == SFmode)
11028 cmp = flag_finite_math_only
11029 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11030 rs6000_compare_op1)
11031 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11032 rs6000_compare_op1);
11033 else if (op_mode == DFmode)
11034 cmp = flag_finite_math_only
11035 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11036 rs6000_compare_op1)
11037 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11038 rs6000_compare_op1);
11042 or1 = gen_rtx_GT (SImode, compare_result, const0_rtx);
11043 or2 = gen_rtx_GT (SImode, compare_result2, const0_rtx);
11045 /* OR them together. */
11046 cmp = gen_rtx_SET (VOIDmode, or_result,
11047 gen_rtx_COMPARE (CCEQmode,
11048 gen_rtx_IOR (SImode, or1, or2),
11050 compare_result = or_result;
11055 if (code == NE || code == LTGT)
11064 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11065 gen_rtx_COMPARE (comp_mode,
11066 rs6000_compare_op0,
11067 rs6000_compare_op1)));
11069 /* Some kinds of FP comparisons need an OR operation;
11070 under flag_finite_math_only we don't bother. */
11071 if (rs6000_compare_fp_p
11072 && ! flag_finite_math_only
11073 && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11074 && (code == LE || code == GE
11075 || code == UNEQ || code == LTGT
11076 || code == UNGT || code == UNLT))
11078 enum rtx_code or1, or2;
11079 rtx or1_rtx, or2_rtx, compare2_rtx;
11080 rtx or_result = gen_reg_rtx (CCEQmode);
11084 case LE: or1 = LT; or2 = EQ; break;
11085 case GE: or1 = GT; or2 = EQ; break;
11086 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11087 case LTGT: or1 = LT; or2 = GT; break;
11088 case UNGT: or1 = UNORDERED; or2 = GT; break;
11089 case UNLT: or1 = UNORDERED; or2 = LT; break;
11092 validate_condition_mode (or1, comp_mode);
11093 validate_condition_mode (or2, comp_mode);
11094 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11095 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11096 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11097 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11099 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11101 compare_result = or_result;
11105 validate_condition_mode (code, GET_MODE (compare_result));
11107 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11111 /* Emit the RTL for an sCOND pattern. */
11114 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11117 enum machine_mode op_mode;
11118 enum rtx_code cond_code;
11120 condition_rtx = rs6000_generate_compare (code);
11121 cond_code = GET_CODE (condition_rtx);
11123 if (TARGET_E500 && rs6000_compare_fp_p
11124 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11128 PUT_MODE (condition_rtx, SImode);
11129 t = XEXP (condition_rtx, 0);
11131 if (cond_code != NE && cond_code != EQ)
11134 if (cond_code == NE)
11135 emit_insn (gen_e500_flip_eq_bit (t, t));
11137 emit_insn (gen_move_from_CR_eq_bit (result, t));
11141 if (cond_code == NE
11142 || cond_code == GE || cond_code == LE
11143 || cond_code == GEU || cond_code == LEU
11144 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11146 rtx not_result = gen_reg_rtx (CCEQmode);
11147 rtx not_op, rev_cond_rtx;
11148 enum machine_mode cc_mode;
11150 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11152 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11153 SImode, XEXP (condition_rtx, 0), const0_rtx);
11154 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11155 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11156 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11159 op_mode = GET_MODE (rs6000_compare_op0);
11160 if (op_mode == VOIDmode)
11161 op_mode = GET_MODE (rs6000_compare_op1);
11163 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11165 PUT_MODE (condition_rtx, DImode);
11166 convert_move (result, condition_rtx, 0);
11170 PUT_MODE (condition_rtx, SImode);
11171 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11175 /* Emit a branch of kind CODE to location LOC. */
11178 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11180 rtx condition_rtx, loc_ref;
11182 condition_rtx = rs6000_generate_compare (code);
11183 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11184 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11185 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11186 loc_ref, pc_rtx)));
11189 /* Return the string to output a conditional branch to LABEL, which is
11190 the operand number of the label, or -1 if the branch is really a
11191 conditional return.
11193 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11194 condition code register and its mode specifies what kind of
11195 comparison we made.
11197 REVERSED is nonzero if we should reverse the sense of the comparison.
11199 INSN is the insn. */
11202 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11204 static char string[64];
11205 enum rtx_code code = GET_CODE (op);
11206 rtx cc_reg = XEXP (op, 0);
11207 enum machine_mode mode = GET_MODE (cc_reg);
11208 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11209 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11210 int really_reversed = reversed ^ need_longbranch;
11216 validate_condition_mode (code, mode);
11218 /* Work out which way this really branches. We could use
11219 reverse_condition_maybe_unordered here always but this
11220 makes the resulting assembler clearer. */
11221 if (really_reversed)
11223 /* Reversal of FP compares takes care -- an ordered compare
11224 becomes an unordered compare and vice versa. */
11225 if (mode == CCFPmode)
11226 code = reverse_condition_maybe_unordered (code);
11228 code = reverse_condition (code);
11231 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11233 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11236 /* Opposite of GT. */
11238 else if (code == NE)
11246 /* Not all of these are actually distinct opcodes, but
11247 we distinguish them for clarity of the resulting assembler. */
11248 case NE: case LTGT:
11249 ccode = "ne"; break;
11250 case EQ: case UNEQ:
11251 ccode = "eq"; break;
11253 ccode = "ge"; break;
11254 case GT: case GTU: case UNGT:
11255 ccode = "gt"; break;
11257 ccode = "le"; break;
11258 case LT: case LTU: case UNLT:
11259 ccode = "lt"; break;
11260 case UNORDERED: ccode = "un"; break;
11261 case ORDERED: ccode = "nu"; break;
11262 case UNGE: ccode = "nl"; break;
11263 case UNLE: ccode = "ng"; break;
11268 /* Maybe we have a guess as to how likely the branch is.
11269 The old mnemonics don't have a way to specify this information. */
11271 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11272 if (note != NULL_RTX)
11274 /* PROB is the difference from 50%. */
11275 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11277 /* Only hint for highly probable/improbable branches on newer
11278 cpus as static prediction overrides processor dynamic
11279 prediction. For older cpus we may as well always hint, but
11280 assume not taken for branches that are very close to 50% as a
11281 mispredicted taken branch is more expensive than a
11282 mispredicted not-taken branch. */
11283 if (rs6000_always_hint
11284 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
11286 if (abs (prob) > REG_BR_PROB_BASE / 20
11287 && ((prob > 0) ^ need_longbranch))
11295 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11297 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11299 /* We need to escape any '%' characters in the reg_names string.
11300 Assume they'd only be the first character.... */
11301 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11303 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11307 /* If the branch distance was too far, we may have to use an
11308 unconditional branch to go the distance. */
11309 if (need_longbranch)
11310 s += sprintf (s, ",$+8\n\tb %s", label);
11312 s += sprintf (s, ",%s", label);
11318 /* Return the string to flip the EQ bit on a CR. */
11320 output_e500_flip_eq_bit (rtx dst, rtx src)
11322 static char string[64];
11325 if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst))
11326 || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src)))
11330 a = 4 * (REGNO (dst) - CR0_REGNO) + 2;
11331 b = 4 * (REGNO (src) - CR0_REGNO) + 2;
11333 sprintf (string, "crnot %d,%d", a, b);
11337 /* Return insn index for the vector compare instruction for given CODE,
11338 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11342 get_vec_cmp_insn (enum rtx_code code,
11343 enum machine_mode dest_mode,
11344 enum machine_mode op_mode)
11346 if (!TARGET_ALTIVEC)
11347 return INSN_NOT_AVAILABLE;
11352 if (dest_mode == V16QImode && op_mode == V16QImode)
11353 return UNSPEC_VCMPEQUB;
11354 if (dest_mode == V8HImode && op_mode == V8HImode)
11355 return UNSPEC_VCMPEQUH;
11356 if (dest_mode == V4SImode && op_mode == V4SImode)
11357 return UNSPEC_VCMPEQUW;
11358 if (dest_mode == V4SImode && op_mode == V4SFmode)
11359 return UNSPEC_VCMPEQFP;
11362 if (dest_mode == V4SImode && op_mode == V4SFmode)
11363 return UNSPEC_VCMPGEFP;
11365 if (dest_mode == V16QImode && op_mode == V16QImode)
11366 return UNSPEC_VCMPGTSB;
11367 if (dest_mode == V8HImode && op_mode == V8HImode)
11368 return UNSPEC_VCMPGTSH;
11369 if (dest_mode == V4SImode && op_mode == V4SImode)
11370 return UNSPEC_VCMPGTSW;
11371 if (dest_mode == V4SImode && op_mode == V4SFmode)
11372 return UNSPEC_VCMPGTFP;
11375 if (dest_mode == V16QImode && op_mode == V16QImode)
11376 return UNSPEC_VCMPGTUB;
11377 if (dest_mode == V8HImode && op_mode == V8HImode)
11378 return UNSPEC_VCMPGTUH;
11379 if (dest_mode == V4SImode && op_mode == V4SImode)
11380 return UNSPEC_VCMPGTUW;
11385 return INSN_NOT_AVAILABLE;
11388 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11389 DMODE is expected destination mode. This is a recursive function. */
11392 rs6000_emit_vector_compare (enum rtx_code rcode,
11394 enum machine_mode dmode)
11398 enum machine_mode dest_mode;
11399 enum machine_mode op_mode = GET_MODE (op1);
11401 #ifdef ENABLE_CHECKING
11402 if (!TARGET_ALTIVEC)
11405 if (GET_MODE (op0) != GET_MODE (op1))
11409 /* Floating point vector compare instructions uses destination V4SImode.
11410 Move destination to appropriate mode later. */
11411 if (dmode == V4SFmode)
11412 dest_mode = V4SImode;
11416 mask = gen_reg_rtx (dest_mode);
11417 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11419 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11421 bool swap_operands = false;
11422 bool try_again = false;
11427 swap_operands = true;
11432 swap_operands = true;
11436 /* Treat A != B as ~(A==B). */
11438 enum insn_code nor_code;
11439 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11442 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11443 if (nor_code == CODE_FOR_nothing)
11445 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11447 if (dmode != dest_mode)
11449 rtx temp = gen_reg_rtx (dest_mode);
11450 convert_move (temp, mask, 0);
11460 /* Try GT/GTU/LT/LTU OR EQ */
11463 enum insn_code ior_code;
11464 enum rtx_code new_code;
11468 else if (rcode == GEU)
11470 else if (rcode == LE)
11472 else if (rcode == LEU)
11477 c_rtx = rs6000_emit_vector_compare (new_code,
11478 op0, op1, dest_mode);
11479 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11482 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11483 if (ior_code == CODE_FOR_nothing)
11485 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11486 if (dmode != dest_mode)
11488 rtx temp = gen_reg_rtx (dest_mode);
11489 convert_move (temp, mask, 0);
11501 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11502 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11503 /* You only get two chances. */
11516 emit_insn (gen_rtx_fmt_ee (SET,
11519 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
11520 gen_rtvec (2, op0, op1),
11522 if (dmode != dest_mode)
11524 rtx temp = gen_reg_rtx (dest_mode);
11525 convert_move (temp, mask, 0);
11531 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11532 valid insn doesn exist for given mode. */
11535 get_vsel_insn (enum machine_mode mode)
11540 return UNSPEC_VSEL4SI;
11543 return UNSPEC_VSEL4SF;
11546 return UNSPEC_VSEL8HI;
11549 return UNSPEC_VSEL16QI;
11552 return INSN_NOT_AVAILABLE;
11555 return INSN_NOT_AVAILABLE;
11558 /* Emit vector select insn where DEST is destination using
11559 operands OP1, OP2 and MASK. */
11562 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11565 enum machine_mode dest_mode = GET_MODE (dest);
11566 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11568 temp = gen_reg_rtx (dest_mode);
11570 t = gen_rtx_fmt_ee (SET, VOIDmode, temp,
11571 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
11572 gen_rtvec (3, op1, op2, mask),
11575 emit_move_insn (dest, temp);
11579 /* Emit vector conditional expression.
11580 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11581 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11584 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11585 rtx cond, rtx cc_op0, rtx cc_op1)
11587 enum machine_mode dest_mode = GET_MODE (dest);
11588 enum rtx_code rcode = GET_CODE (cond);
11591 if (!TARGET_ALTIVEC)
11594 /* Get the vector mask for the given relational operations. */
11595 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11597 rs6000_emit_vector_select (dest, op1, op2, mask);
11602 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11603 operands of the last comparison is nonzero/true, FALSE_COND if it
11604 is zero/false. Return 0 if the hardware has no such operation. */
11607 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11609 enum rtx_code code = GET_CODE (op);
11610 rtx op0 = rs6000_compare_op0;
11611 rtx op1 = rs6000_compare_op1;
11612 REAL_VALUE_TYPE c1;
11613 enum machine_mode compare_mode = GET_MODE (op0);
11614 enum machine_mode result_mode = GET_MODE (dest);
11616 bool is_against_zero;
11618 /* These modes should always match. */
11619 if (GET_MODE (op1) != compare_mode
11620 /* In the isel case however, we can use a compare immediate, so
11621 op1 may be a small constant. */
11622 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11624 if (GET_MODE (true_cond) != result_mode)
11626 if (GET_MODE (false_cond) != result_mode)
11629 /* First, work out if the hardware can do this at all, or
11630 if it's too slow.... */
11631 if (! rs6000_compare_fp_p)
11634 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11637 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11638 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
11641 is_against_zero = op1 == CONST0_RTX (compare_mode);
11643 /* A floating-point subtract might overflow, underflow, or produce
11644 an inexact result, thus changing the floating-point flags, so it
11645 can't be generated if we care about that. It's safe if one side
11646 of the construct is zero, since then no subtract will be
11648 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT
11649 && flag_trapping_math && ! is_against_zero)
11652 /* Eliminate half of the comparisons by switching operands, this
11653 makes the remaining code simpler. */
11654 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
11655 || code == LTGT || code == LT || code == UNLE)
11657 code = reverse_condition_maybe_unordered (code);
11659 true_cond = false_cond;
11663 /* UNEQ and LTGT take four instructions for a comparison with zero,
11664 it'll probably be faster to use a branch here too. */
11665 if (code == UNEQ && HONOR_NANS (compare_mode))
11668 if (GET_CODE (op1) == CONST_DOUBLE)
11669 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
11671 /* We're going to try to implement comparisons by performing
11672 a subtract, then comparing against zero. Unfortunately,
11673 Inf - Inf is NaN which is not zero, and so if we don't
11674 know that the operand is finite and the comparison
11675 would treat EQ different to UNORDERED, we can't do it. */
11676 if (HONOR_INFINITIES (compare_mode)
11677 && code != GT && code != UNGE
11678 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
11679 /* Constructs of the form (a OP b ? a : b) are safe. */
11680 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
11681 || (! rtx_equal_p (op0, true_cond)
11682 && ! rtx_equal_p (op1, true_cond))))
11685 /* At this point we know we can use fsel. */
11687 /* Reduce the comparison to a comparison against zero. */
11688 if (! is_against_zero)
11690 temp = gen_reg_rtx (compare_mode);
11691 emit_insn (gen_rtx_SET (VOIDmode, temp,
11692 gen_rtx_MINUS (compare_mode, op0, op1)));
11694 op1 = CONST0_RTX (compare_mode);
11697 /* If we don't care about NaNs we can reduce some of the comparisons
11698 down to faster ones. */
11699 if (! HONOR_NANS (compare_mode))
11705 true_cond = false_cond;
11718 /* Now, reduce everything down to a GE. */
11725 temp = gen_reg_rtx (compare_mode);
11726 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11731 temp = gen_reg_rtx (compare_mode);
11732 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
11737 temp = gen_reg_rtx (compare_mode);
11738 emit_insn (gen_rtx_SET (VOIDmode, temp,
11739 gen_rtx_NEG (compare_mode,
11740 gen_rtx_ABS (compare_mode, op0))));
11745 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
11746 temp = gen_reg_rtx (result_mode);
11747 emit_insn (gen_rtx_SET (VOIDmode, temp,
11748 gen_rtx_IF_THEN_ELSE (result_mode,
11749 gen_rtx_GE (VOIDmode,
11751 true_cond, false_cond)));
11752 false_cond = true_cond;
11755 temp = gen_reg_rtx (compare_mode);
11756 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11761 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
11762 temp = gen_reg_rtx (result_mode);
11763 emit_insn (gen_rtx_SET (VOIDmode, temp,
11764 gen_rtx_IF_THEN_ELSE (result_mode,
11765 gen_rtx_GE (VOIDmode,
11767 true_cond, false_cond)));
11768 true_cond = false_cond;
11771 temp = gen_reg_rtx (compare_mode);
11772 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11780 emit_insn (gen_rtx_SET (VOIDmode, dest,
11781 gen_rtx_IF_THEN_ELSE (result_mode,
11782 gen_rtx_GE (VOIDmode,
11784 true_cond, false_cond)));
11788 /* Same as above, but for ints (isel). */
11791 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11793 rtx condition_rtx, cr;
11795 /* All isel implementations thus far are 32-bits. */
11796 if (GET_MODE (rs6000_compare_op0) != SImode)
11799 /* We still have to do the compare, because isel doesn't do a
11800 compare, it just looks at the CRx bits set by a previous compare
11802 condition_rtx = rs6000_generate_compare (GET_CODE (op));
11803 cr = XEXP (condition_rtx, 0);
11805 if (GET_MODE (cr) == CCmode)
11806 emit_insn (gen_isel_signed (dest, condition_rtx,
11807 true_cond, false_cond, cr));
11809 emit_insn (gen_isel_unsigned (dest, condition_rtx,
11810 true_cond, false_cond, cr));
11816 output_isel (rtx *operands)
11818 enum rtx_code code;
11820 code = GET_CODE (operands[1]);
11821 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
11823 PUT_CODE (operands[1], reverse_condition (code));
11824 return "isel %0,%3,%2,%j1";
11827 return "isel %0,%2,%3,%j1";
11831 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
11833 enum machine_mode mode = GET_MODE (op0);
11837 if (code == SMAX || code == SMIN)
11842 if (code == SMAX || code == UMAX)
11843 target = emit_conditional_move (dest, c, op0, op1, mode,
11844 op0, op1, mode, 0);
11846 target = emit_conditional_move (dest, c, op0, op1, mode,
11847 op1, op0, mode, 0);
11848 if (target == NULL_RTX)
11850 if (target != dest)
11851 emit_move_insn (dest, target);
11854 /* Emit instructions to move SRC to DST. Called by splitters for
11855 multi-register moves. It will emit at most one instruction for
11856 each register that is accessed; that is, it won't emit li/lis pairs
11857 (or equivalent for 64-bit code). One of SRC or DST must be a hard
11861 rs6000_split_multireg_move (rtx dst, rtx src)
11863 /* The register number of the first register being moved. */
11865 /* The mode that is to be moved. */
11866 enum machine_mode mode;
11867 /* The mode that the move is being done in, and its size. */
11868 enum machine_mode reg_mode;
11870 /* The number of registers that will be moved. */
11873 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
11874 mode = GET_MODE (dst);
11875 nregs = HARD_REGNO_NREGS (reg, mode);
11876 if (FP_REGNO_P (reg))
11878 else if (ALTIVEC_REGNO_P (reg))
11879 reg_mode = V16QImode;
11881 reg_mode = word_mode;
11882 reg_mode_size = GET_MODE_SIZE (reg_mode);
11884 if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
11887 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
11889 /* Move register range backwards, if we might have destructive
11892 for (i = nregs - 1; i >= 0; i--)
11893 emit_insn (gen_rtx_SET (VOIDmode,
11894 simplify_gen_subreg (reg_mode, dst, mode,
11895 i * reg_mode_size),
11896 simplify_gen_subreg (reg_mode, src, mode,
11897 i * reg_mode_size)));
11903 bool used_update = false;
11905 if (MEM_P (src) && INT_REGNO_P (reg))
11909 if (GET_CODE (XEXP (src, 0)) == PRE_INC
11910 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
11913 breg = XEXP (XEXP (src, 0), 0);
11914 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
11915 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
11916 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
11917 emit_insn (TARGET_32BIT
11918 ? gen_addsi3 (breg, breg, delta_rtx)
11919 : gen_adddi3 (breg, breg, delta_rtx));
11920 src = gen_rtx_MEM (mode, breg);
11922 else if (! offsettable_memref_p (src))
11924 rtx newsrc, basereg;
11925 basereg = gen_rtx_REG (Pmode, reg);
11926 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
11927 newsrc = gen_rtx_MEM (GET_MODE (src), basereg);
11928 MEM_COPY_ATTRIBUTES (newsrc, src);
11932 breg = XEXP (src, 0);
11933 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
11934 breg = XEXP (breg, 0);
11936 /* If the base register we are using to address memory is
11937 also a destination reg, then change that register last. */
11939 && REGNO (breg) >= REGNO (dst)
11940 && REGNO (breg) < REGNO (dst) + nregs)
11941 j = REGNO (breg) - REGNO (dst);
11944 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
11948 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
11949 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
11952 breg = XEXP (XEXP (dst, 0), 0);
11953 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
11954 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
11955 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
11957 /* We have to update the breg before doing the store.
11958 Use store with update, if available. */
11962 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
11963 emit_insn (TARGET_32BIT
11964 ? (TARGET_POWERPC64
11965 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
11966 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
11967 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
11968 used_update = true;
11971 emit_insn (TARGET_32BIT
11972 ? gen_addsi3 (breg, breg, delta_rtx)
11973 : gen_adddi3 (breg, breg, delta_rtx));
11974 dst = gen_rtx_MEM (mode, breg);
11976 else if (! offsettable_memref_p (dst))
11980 for (i = 0; i < nregs; i++)
11982 /* Calculate index to next subword. */
11987 /* If compiler already emitted move of first word by
11988 store with update, no need to do anything. */
11989 if (j == 0 && used_update)
11992 emit_insn (gen_rtx_SET (VOIDmode,
11993 simplify_gen_subreg (reg_mode, dst, mode,
11994 j * reg_mode_size),
11995 simplify_gen_subreg (reg_mode, src, mode,
11996 j * reg_mode_size)));
12002 /* This page contains routines that are used to determine what the
12003 function prologue and epilogue code will do and write them out. */
12005 /* Return the first fixed-point register that is required to be
12006 saved. 32 if none. */
12009 first_reg_to_save (void)
12013 /* Find lowest numbered live register. */
12014 for (first_reg = 13; first_reg <= 31; first_reg++)
12015 if (regs_ever_live[first_reg]
12016 && (! call_used_regs[first_reg]
12017 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12018 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12019 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12020 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12025 && current_function_uses_pic_offset_table
12026 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12027 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12033 /* Similar, for FP regs. */
12036 first_fp_reg_to_save (void)
12040 /* Find lowest numbered live register. */
12041 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12042 if (regs_ever_live[first_reg])
12048 /* Similar, for AltiVec regs. */
12051 first_altivec_reg_to_save (void)
12055 /* Stack frame remains as is unless we are in AltiVec ABI. */
12056 if (! TARGET_ALTIVEC_ABI)
12057 return LAST_ALTIVEC_REGNO + 1;
12059 /* Find lowest numbered live register. */
12060 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12061 if (regs_ever_live[i])
12067 /* Return a 32-bit mask of the AltiVec registers we need to set in
12068 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12069 the 32-bit word is 0. */
12071 static unsigned int
12072 compute_vrsave_mask (void)
12074 unsigned int i, mask = 0;
12076 /* First, find out if we use _any_ altivec registers. */
12077 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12078 if (regs_ever_live[i])
12079 mask |= ALTIVEC_REG_BIT (i);
12084 /* Next, remove the argument registers from the set. These must
12085 be in the VRSAVE mask set by the caller, so we don't need to add
12086 them in again. More importantly, the mask we compute here is
12087 used to generate CLOBBERs in the set_vrsave insn, and we do not
12088 wish the argument registers to die. */
12089 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12090 mask &= ~ALTIVEC_REG_BIT (i);
12092 /* Similarly, remove the return value from the set. */
12095 diddle_return_value (is_altivec_return_reg, &yes);
12097 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12103 /* For a very restricted set of circumstances, we can cut down the
12104 size of prologs/epilogs by calling our own save/restore-the-world
12108 compute_save_world_info(rs6000_stack_t *info_ptr)
12110 info_ptr->world_save_p =
12111 (DEFAULT_ABI == ABI_DARWIN)
12112 && ! (current_function_calls_setjmp && flag_exceptions)
12113 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12114 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12115 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12116 && info_ptr->cr_save_p;
12118 /* This will not work in conjunction with sibcalls. Make sure there
12119 are none. (This check is expensive, but seldom executed.) */
12120 if ( info_ptr->world_save_p )
12123 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12124 if ( GET_CODE (insn) == CALL_INSN
12125 && SIBLING_CALL_P (insn))
12127 info_ptr->world_save_p = 0;
12132 if (info_ptr->world_save_p)
12134 /* Even if we're not touching VRsave, make sure there's room on the
12135 stack for it, if it looks like we're calling SAVE_WORLD, which
12136 will attempt to save it. */
12137 info_ptr->vrsave_size = 4;
12139 /* "Save" the VRsave register too if we're saving the world. */
12140 if (info_ptr->vrsave_mask == 0)
12141 info_ptr->vrsave_mask = compute_vrsave_mask ();
12143 /* Because the Darwin register save/restore routines only handle
12144 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12145 check and abort if there's something worng. */
12146 if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO
12147 || info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO)
12155 is_altivec_return_reg (rtx reg, void *xyes)
12157 bool *yes = (bool *) xyes;
12158 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
12163 /* Calculate the stack information for the current function. This is
12164 complicated by having two separate calling sequences, the AIX calling
12165 sequence and the V.4 calling sequence.
12167 AIX (and Darwin/Mac OS X) stack frames look like:
12169 SP----> +---------------------------------------+
12170 | back chain to caller | 0 0
12171 +---------------------------------------+
12172 | saved CR | 4 8 (8-11)
12173 +---------------------------------------+
12175 +---------------------------------------+
12176 | reserved for compilers | 12 24
12177 +---------------------------------------+
12178 | reserved for binders | 16 32
12179 +---------------------------------------+
12180 | saved TOC pointer | 20 40
12181 +---------------------------------------+
12182 | Parameter save area (P) | 24 48
12183 +---------------------------------------+
12184 | Alloca space (A) | 24+P etc.
12185 +---------------------------------------+
12186 | Local variable space (L) | 24+P+A
12187 +---------------------------------------+
12188 | Float/int conversion temporary (X) | 24+P+A+L
12189 +---------------------------------------+
12190 | Save area for AltiVec registers (W) | 24+P+A+L+X
12191 +---------------------------------------+
12192 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12193 +---------------------------------------+
12194 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12195 +---------------------------------------+
12196 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12197 +---------------------------------------+
12198 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12199 +---------------------------------------+
12200 old SP->| back chain to caller's caller |
12201 +---------------------------------------+
12203 The required alignment for AIX configurations is two words (i.e., 8
12207 V.4 stack frames look like:
12209 SP----> +---------------------------------------+
12210 | back chain to caller | 0
12211 +---------------------------------------+
12212 | caller's saved LR | 4
12213 +---------------------------------------+
12214 | Parameter save area (P) | 8
12215 +---------------------------------------+
12216 | Alloca space (A) | 8+P
12217 +---------------------------------------+
12218 | Varargs save area (V) | 8+P+A
12219 +---------------------------------------+
12220 | Local variable space (L) | 8+P+A+V
12221 +---------------------------------------+
12222 | Float/int conversion temporary (X) | 8+P+A+V+L
12223 +---------------------------------------+
12224 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12225 +---------------------------------------+
12226 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12227 +---------------------------------------+
12228 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12229 +---------------------------------------+
12230 | SPE: area for 64-bit GP registers |
12231 +---------------------------------------+
12232 | SPE alignment padding |
12233 +---------------------------------------+
12234 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12235 +---------------------------------------+
12236 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12237 +---------------------------------------+
12238 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12239 +---------------------------------------+
12240 old SP->| back chain to caller's caller |
12241 +---------------------------------------+
12243 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12244 given. (But note below and in sysv4.h that we require only 8 and
12245 may round up the size of our stack frame anyways. The historical
12246 reason is early versions of powerpc-linux which didn't properly
12247 align the stack at program startup. A happy side-effect is that
12248 -mno-eabi libraries can be used with -meabi programs.)
12250 The EABI configuration defaults to the V.4 layout. However,
12251 the stack alignment requirements may differ. If -mno-eabi is not
12252 given, the required stack alignment is 8 bytes; if -mno-eabi is
12253 given, the required alignment is 16 bytes. (But see V.4 comment
12256 #ifndef ABI_STACK_BOUNDARY
12257 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12260 static rs6000_stack_t *
12261 rs6000_stack_info (void)
12263 static rs6000_stack_t info, zero_info;
12264 rs6000_stack_t *info_ptr = &info;
12265 int reg_size = TARGET_32BIT ? 4 : 8;
12268 HOST_WIDE_INT non_fixed_size;
12270 /* Zero all fields portably. */
12275 /* Cache value so we don't rescan instruction chain over and over. */
12276 if (cfun->machine->insn_chain_scanned_p == 0)
12278 cfun->machine->insn_chain_scanned_p = 1;
12279 info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p ();
12283 /* Select which calling sequence. */
12284 info_ptr->abi = DEFAULT_ABI;
12286 /* Calculate which registers need to be saved & save area size. */
12287 info_ptr->first_gp_reg_save = first_reg_to_save ();
12288 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12289 even if it currently looks like we won't. */
12290 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
12291 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12292 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
12293 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12294 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
12296 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
12298 /* For the SPE, we have an additional upper 32-bits on each GPR.
12299 Ideally we should save the entire 64-bits only when the upper
12300 half is used in SIMD instructions. Since we only record
12301 registers live (not the size they are used in), this proves
12302 difficult because we'd have to traverse the instruction chain at
12303 the right time, taking reload into account. This is a real pain,
12304 so we opt to save the GPRs in 64-bits always if but one register
12305 gets used in 64-bits. Otherwise, all the registers in the frame
12306 get saved in 32-bits.
12308 So... since when we save all GPRs (except the SP) in 64-bits, the
12309 traditional GP save area will be empty. */
12310 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12311 info_ptr->gp_size = 0;
12313 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12314 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12316 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12317 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12318 - info_ptr->first_altivec_reg_save);
12320 /* Does this function call anything? */
12321 info_ptr->calls_p = (! current_function_is_leaf
12322 || cfun->machine->ra_needs_full_frame);
12324 /* Determine if we need to save the link register. */
12325 if (rs6000_ra_ever_killed ()
12326 || (DEFAULT_ABI == ABI_AIX
12327 && current_function_profile
12328 && !TARGET_PROFILE_KERNEL)
12329 #ifdef TARGET_RELOCATABLE
12330 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12332 || (info_ptr->first_fp_reg_save != 64
12333 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
12334 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
12335 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
12336 || (DEFAULT_ABI == ABI_DARWIN
12338 && current_function_uses_pic_offset_table)
12339 || info_ptr->calls_p)
12341 info_ptr->lr_save_p = 1;
12342 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
12345 /* Determine if we need to save the condition code registers. */
12346 if (regs_ever_live[CR2_REGNO]
12347 || regs_ever_live[CR3_REGNO]
12348 || regs_ever_live[CR4_REGNO])
12350 info_ptr->cr_save_p = 1;
12351 if (DEFAULT_ABI == ABI_V4)
12352 info_ptr->cr_size = reg_size;
12355 /* If the current function calls __builtin_eh_return, then we need
12356 to allocate stack space for registers that will hold data for
12357 the exception handler. */
12358 if (current_function_calls_eh_return)
12361 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12364 /* SPE saves EH registers in 64-bits. */
12365 ehrd_size = i * (TARGET_SPE_ABI
12366 && info_ptr->spe_64bit_regs_used != 0
12367 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
12372 /* Determine various sizes. */
12373 info_ptr->reg_size = reg_size;
12374 info_ptr->fixed_size = RS6000_SAVE_AREA;
12375 info_ptr->varargs_size = RS6000_VARARGS_AREA;
12376 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
12377 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
12378 TARGET_ALTIVEC ? 16 : 8);
12380 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12381 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12383 info_ptr->spe_gp_size = 0;
12385 if (TARGET_ALTIVEC_ABI)
12386 info_ptr->vrsave_mask = compute_vrsave_mask ();
12388 info_ptr->vrsave_mask = 0;
12390 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
12391 info_ptr->vrsave_size = 4;
12393 info_ptr->vrsave_size = 0;
12395 compute_save_world_info (info_ptr);
12397 /* Calculate the offsets. */
12398 switch (DEFAULT_ABI)
12406 info_ptr->fp_save_offset = - info_ptr->fp_size;
12407 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12409 if (TARGET_ALTIVEC_ABI)
12411 info_ptr->vrsave_save_offset
12412 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
12414 /* Align stack so vector save area is on a quadword boundary. */
12415 if (info_ptr->altivec_size != 0)
12416 info_ptr->altivec_padding_size
12417 = 16 - (-info_ptr->vrsave_save_offset % 16);
12419 info_ptr->altivec_padding_size = 0;
12421 info_ptr->altivec_save_offset
12422 = info_ptr->vrsave_save_offset
12423 - info_ptr->altivec_padding_size
12424 - info_ptr->altivec_size;
12426 /* Adjust for AltiVec case. */
12427 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
12430 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
12431 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
12432 info_ptr->lr_save_offset = 2*reg_size;
12436 info_ptr->fp_save_offset = - info_ptr->fp_size;
12437 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12438 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
12440 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12442 /* Align stack so SPE GPR save area is aligned on a
12443 double-word boundary. */
12444 if (info_ptr->spe_gp_size != 0)
12445 info_ptr->spe_padding_size
12446 = 8 - (-info_ptr->cr_save_offset % 8);
12448 info_ptr->spe_padding_size = 0;
12450 info_ptr->spe_gp_save_offset
12451 = info_ptr->cr_save_offset
12452 - info_ptr->spe_padding_size
12453 - info_ptr->spe_gp_size;
12455 /* Adjust for SPE case. */
12456 info_ptr->toc_save_offset
12457 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
12459 else if (TARGET_ALTIVEC_ABI)
12461 info_ptr->vrsave_save_offset
12462 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
12464 /* Align stack so vector save area is on a quadword boundary. */
12465 if (info_ptr->altivec_size != 0)
12466 info_ptr->altivec_padding_size
12467 = 16 - (-info_ptr->vrsave_save_offset % 16);
12469 info_ptr->altivec_padding_size = 0;
12471 info_ptr->altivec_save_offset
12472 = info_ptr->vrsave_save_offset
12473 - info_ptr->altivec_padding_size
12474 - info_ptr->altivec_size;
12476 /* Adjust for AltiVec case. */
12477 info_ptr->toc_save_offset
12478 = info_ptr->altivec_save_offset - info_ptr->toc_size;
12481 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
12482 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
12483 info_ptr->lr_save_offset = reg_size;
12487 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
12488 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
12489 + info_ptr->gp_size
12490 + info_ptr->altivec_size
12491 + info_ptr->altivec_padding_size
12492 + info_ptr->spe_gp_size
12493 + info_ptr->spe_padding_size
12495 + info_ptr->cr_size
12496 + info_ptr->lr_size
12497 + info_ptr->vrsave_size
12498 + info_ptr->toc_size,
12501 non_fixed_size = (info_ptr->vars_size
12502 + info_ptr->parm_size
12503 + info_ptr->save_size
12504 + info_ptr->varargs_size);
12506 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
12507 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
12509 /* Determine if we need to allocate any stack frame:
12511 For AIX we need to push the stack if a frame pointer is needed
12512 (because the stack might be dynamically adjusted), if we are
12513 debugging, if we make calls, or if the sum of fp_save, gp_save,
12514 and local variables are more than the space needed to save all
12515 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
12516 + 18*8 = 288 (GPR13 reserved).
12518 For V.4 we don't have the stack cushion that AIX uses, but assume
12519 that the debugger can handle stackless frames. */
12521 if (info_ptr->calls_p)
12522 info_ptr->push_p = 1;
12524 else if (DEFAULT_ABI == ABI_V4)
12525 info_ptr->push_p = non_fixed_size != 0;
12527 else if (frame_pointer_needed)
12528 info_ptr->push_p = 1;
12530 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
12531 info_ptr->push_p = 1;
12534 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
12536 /* Zero offsets if we're not saving those registers. */
12537 if (info_ptr->fp_size == 0)
12538 info_ptr->fp_save_offset = 0;
12540 if (info_ptr->gp_size == 0)
12541 info_ptr->gp_save_offset = 0;
12543 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
12544 info_ptr->altivec_save_offset = 0;
12546 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
12547 info_ptr->vrsave_save_offset = 0;
12549 if (! TARGET_SPE_ABI
12550 || info_ptr->spe_64bit_regs_used == 0
12551 || info_ptr->spe_gp_size == 0)
12552 info_ptr->spe_gp_save_offset = 0;
12554 if (! info_ptr->lr_save_p)
12555 info_ptr->lr_save_offset = 0;
12557 if (! info_ptr->cr_save_p)
12558 info_ptr->cr_save_offset = 0;
12560 if (! info_ptr->toc_save_p)
12561 info_ptr->toc_save_offset = 0;
12566 /* Return true if the current function uses any GPRs in 64-bit SIMD
12570 spe_func_has_64bit_regs_p (void)
12574 /* Functions that save and restore all the call-saved registers will
12575 need to save/restore the registers in 64-bits. */
12576 if (current_function_calls_eh_return
12577 || current_function_calls_setjmp
12578 || current_function_has_nonlocal_goto)
12581 insns = get_insns ();
12583 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
12589 i = PATTERN (insn);
12590 if (GET_CODE (i) == SET)
12592 enum machine_mode mode = GET_MODE (SET_SRC (i));
12594 if (SPE_VECTOR_MODE (mode))
12596 if (TARGET_E500_DOUBLE && mode == DFmode)
12606 debug_stack_info (rs6000_stack_t *info)
12608 const char *abi_string;
12611 info = rs6000_stack_info ();
12613 fprintf (stderr, "\nStack information for function %s:\n",
12614 ((current_function_decl && DECL_NAME (current_function_decl))
12615 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
12620 default: abi_string = "Unknown"; break;
12621 case ABI_NONE: abi_string = "NONE"; break;
12622 case ABI_AIX: abi_string = "AIX"; break;
12623 case ABI_DARWIN: abi_string = "Darwin"; break;
12624 case ABI_V4: abi_string = "V.4"; break;
12627 fprintf (stderr, "\tABI = %5s\n", abi_string);
12629 if (TARGET_ALTIVEC_ABI)
12630 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
12632 if (TARGET_SPE_ABI)
12633 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
12635 if (info->first_gp_reg_save != 32)
12636 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
12638 if (info->first_fp_reg_save != 64)
12639 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
12641 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
12642 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
12643 info->first_altivec_reg_save);
12645 if (info->lr_save_p)
12646 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
12648 if (info->cr_save_p)
12649 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
12651 if (info->toc_save_p)
12652 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
12654 if (info->vrsave_mask)
12655 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
12658 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
12661 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
12663 if (info->gp_save_offset)
12664 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
12666 if (info->fp_save_offset)
12667 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
12669 if (info->altivec_save_offset)
12670 fprintf (stderr, "\taltivec_save_offset = %5d\n",
12671 info->altivec_save_offset);
12673 if (info->spe_gp_save_offset)
12674 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
12675 info->spe_gp_save_offset);
12677 if (info->vrsave_save_offset)
12678 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
12679 info->vrsave_save_offset);
12681 if (info->lr_save_offset)
12682 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
12684 if (info->cr_save_offset)
12685 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
12687 if (info->toc_save_offset)
12688 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
12690 if (info->varargs_save_offset)
12691 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
12693 if (info->total_size)
12694 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
12697 if (info->varargs_size)
12698 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
12700 if (info->vars_size)
12701 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
12704 if (info->parm_size)
12705 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
12707 if (info->fixed_size)
12708 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
12711 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
12713 if (info->spe_gp_size)
12714 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
12717 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
12719 if (info->altivec_size)
12720 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
12722 if (info->vrsave_size)
12723 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
12725 if (info->altivec_padding_size)
12726 fprintf (stderr, "\taltivec_padding_size= %5d\n",
12727 info->altivec_padding_size);
12729 if (info->spe_padding_size)
12730 fprintf (stderr, "\tspe_padding_size = %5d\n",
12731 info->spe_padding_size);
12734 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
12737 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
12739 if (info->toc_size)
12740 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
12742 if (info->save_size)
12743 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
12745 if (info->reg_size != 4)
12746 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
12748 fprintf (stderr, "\n");
12752 rs6000_return_addr (int count, rtx frame)
12754 /* Currently we don't optimize very well between prolog and body
12755 code and for PIC code the code can be actually quite bad, so
12756 don't try to be too clever here. */
12757 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
12759 cfun->machine->ra_needs_full_frame = 1;
12766 plus_constant (copy_to_reg
12767 (gen_rtx_MEM (Pmode,
12768 memory_address (Pmode, frame))),
12769 RETURN_ADDRESS_OFFSET)));
12772 cfun->machine->ra_need_lr = 1;
12773 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
12776 /* Say whether a function is a candidate for sibcall handling or not.
12777 We do not allow indirect calls to be optimized into sibling calls.
12778 Also, we can't do it if there are any vector parameters; there's
12779 nowhere to put the VRsave code so it works; note that functions with
12780 vector parameters are required to have a prototype, so the argument
12781 type info must be available here. (The tail recursion case can work
12782 with vector parameters, but there's no way to distinguish here.) */
12784 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
12789 if (TARGET_ALTIVEC_VRSAVE)
12791 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
12792 type; type = TREE_CHAIN (type))
12794 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
12798 if (DEFAULT_ABI == ABI_DARWIN
12799 || (*targetm.binds_local_p) (decl))
12801 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
12803 if (!lookup_attribute ("longcall", attr_list)
12804 || lookup_attribute ("shortcall", attr_list))
12812 rs6000_ra_ever_killed (void)
12818 if (current_function_is_thunk)
12821 /* regs_ever_live has LR marked as used if any sibcalls are present,
12822 but this should not force saving and restoring in the
12823 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
12824 clobbers LR, so that is inappropriate. */
12826 /* Also, the prologue can generate a store into LR that
12827 doesn't really count, like this:
12830 bcl to set PIC register
12834 When we're called from the epilogue, we need to avoid counting
12835 this as a store. */
12837 push_topmost_sequence ();
12838 top = get_insns ();
12839 pop_topmost_sequence ();
12840 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
12842 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
12846 if (FIND_REG_INC_NOTE (insn, reg))
12848 else if (GET_CODE (insn) == CALL_INSN
12849 && !SIBLING_CALL_P (insn))
12851 else if (set_of (reg, insn) != NULL_RTX
12852 && !prologue_epilogue_contains (insn))
12859 /* Add a REG_MAYBE_DEAD note to the insn. */
12861 rs6000_maybe_dead (rtx insn)
12863 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
12868 /* Emit instructions needed to load the TOC register.
12869 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
12870 a constant pool; or for SVR4 -fpic. */
12873 rs6000_emit_load_toc_table (int fromprolog)
12876 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
12878 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
12880 rtx temp = (fromprolog
12881 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12882 : gen_reg_rtx (Pmode));
12883 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
12885 rs6000_maybe_dead (insn);
12886 insn = emit_move_insn (dest, temp);
12888 rs6000_maybe_dead (insn);
12890 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
12893 rtx tempLR = (fromprolog
12894 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12895 : gen_reg_rtx (Pmode));
12896 rtx temp0 = (fromprolog
12897 ? gen_rtx_REG (Pmode, 0)
12898 : gen_reg_rtx (Pmode));
12901 /* possibly create the toc section */
12902 if (! toc_initialized)
12905 function_section (current_function_decl);
12912 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
12913 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12915 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
12916 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12918 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
12920 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
12921 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
12928 static int reload_toc_labelno = 0;
12930 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
12932 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
12933 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12935 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
12936 emit_move_insn (dest, tempLR);
12937 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
12939 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
12941 rs6000_maybe_dead (insn);
12943 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
12945 /* This is for AIX code running in non-PIC ELF32. */
12948 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
12949 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12951 insn = emit_insn (gen_elf_high (dest, realsym));
12953 rs6000_maybe_dead (insn);
12954 insn = emit_insn (gen_elf_low (dest, dest, realsym));
12956 rs6000_maybe_dead (insn);
12958 else if (DEFAULT_ABI == ABI_AIX)
12961 insn = emit_insn (gen_load_toc_aix_si (dest));
12963 insn = emit_insn (gen_load_toc_aix_di (dest));
12965 rs6000_maybe_dead (insn);
12971 /* Emit instructions to restore the link register after determining where
12972 its value has been stored. */
12975 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
12977 rs6000_stack_t *info = rs6000_stack_info ();
12980 operands[0] = source;
12981 operands[1] = scratch;
12983 if (info->lr_save_p)
12985 rtx frame_rtx = stack_pointer_rtx;
12986 HOST_WIDE_INT sp_offset = 0;
12989 if (frame_pointer_needed
12990 || current_function_calls_alloca
12991 || info->total_size > 32767)
12993 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
12994 frame_rtx = operands[1];
12996 else if (info->push_p)
12997 sp_offset = info->total_size;
12999 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13000 tmp = gen_rtx_MEM (Pmode, tmp);
13001 emit_move_insn (tmp, operands[0]);
13004 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13007 static GTY(()) int set = -1;
13010 get_TOC_alias_set (void)
13013 set = new_alias_set ();
13017 /* This returns nonzero if the current function uses the TOC. This is
13018 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13019 is generated by the ABI_V4 load_toc_* patterns. */
13026 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13029 rtx pat = PATTERN (insn);
13032 if (GET_CODE (pat) == PARALLEL)
13033 for (i = 0; i < XVECLEN (pat, 0); i++)
13035 rtx sub = XVECEXP (pat, 0, i);
13036 if (GET_CODE (sub) == USE)
13038 sub = XEXP (sub, 0);
13039 if (GET_CODE (sub) == UNSPEC
13040 && XINT (sub, 1) == UNSPEC_TOC)
13050 create_TOC_reference (rtx symbol)
13052 return gen_rtx_PLUS (Pmode,
13053 gen_rtx_REG (Pmode, TOC_REGISTER),
13054 gen_rtx_CONST (Pmode,
13055 gen_rtx_MINUS (Pmode, symbol,
13056 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13059 /* If _Unwind_* has been called from within the same module,
13060 toc register is not guaranteed to be saved to 40(1) on function
13061 entry. Save it there in that case. */
13064 rs6000_aix_emit_builtin_unwind_init (void)
13067 rtx stack_top = gen_reg_rtx (Pmode);
13068 rtx opcode_addr = gen_reg_rtx (Pmode);
13069 rtx opcode = gen_reg_rtx (SImode);
13070 rtx tocompare = gen_reg_rtx (SImode);
13071 rtx no_toc_save_needed = gen_label_rtx ();
13073 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
13074 emit_move_insn (stack_top, mem);
13076 mem = gen_rtx_MEM (Pmode,
13077 gen_rtx_PLUS (Pmode, stack_top,
13078 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13079 emit_move_insn (opcode_addr, mem);
13080 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13081 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13082 : 0xE8410028, SImode));
13084 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13085 SImode, NULL_RTX, NULL_RTX,
13086 no_toc_save_needed);
13088 mem = gen_rtx_MEM (Pmode,
13089 gen_rtx_PLUS (Pmode, stack_top,
13090 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13091 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13092 emit_label (no_toc_save_needed);
13095 /* This ties together stack memory (MEM with an alias set of
13096 rs6000_sr_alias_set) and the change to the stack pointer. */
13099 rs6000_emit_stack_tie (void)
13101 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
13103 set_mem_alias_set (mem, rs6000_sr_alias_set);
13104 emit_insn (gen_stack_tie (mem));
13107 /* Emit the correct code for allocating stack space, as insns.
13108 If COPY_R12, make sure a copy of the old frame is left in r12.
13109 The generated code may use hard register 0 as a temporary. */
13112 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
13115 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13116 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
13117 rtx todec = gen_int_mode (-size, Pmode);
13119 if (INTVAL (todec) != -size)
13121 warning("stack frame too large");
13122 emit_insn (gen_trap ());
13126 if (current_function_limit_stack)
13128 if (REG_P (stack_limit_rtx)
13129 && REGNO (stack_limit_rtx) > 1
13130 && REGNO (stack_limit_rtx) <= 31)
13132 emit_insn (TARGET_32BIT
13133 ? gen_addsi3 (tmp_reg,
13136 : gen_adddi3 (tmp_reg,
13140 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13143 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
13145 && DEFAULT_ABI == ABI_V4)
13147 rtx toload = gen_rtx_CONST (VOIDmode,
13148 gen_rtx_PLUS (Pmode,
13152 emit_insn (gen_elf_high (tmp_reg, toload));
13153 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
13154 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13158 warning ("stack limit expression is not supported");
13161 if (copy_r12 || ! TARGET_UPDATE)
13162 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
13168 /* Need a note here so that try_split doesn't get confused. */
13169 if (get_last_insn() == NULL_RTX)
13170 emit_note (NOTE_INSN_DELETED);
13171 insn = emit_move_insn (tmp_reg, todec);
13172 try_split (PATTERN (insn), insn, 0);
13176 insn = emit_insn (TARGET_32BIT
13177 ? gen_movsi_update (stack_reg, stack_reg,
13179 : gen_movdi_di_update (stack_reg, stack_reg,
13180 todec, stack_reg));
13184 insn = emit_insn (TARGET_32BIT
13185 ? gen_addsi3 (stack_reg, stack_reg, todec)
13186 : gen_adddi3 (stack_reg, stack_reg, todec));
13187 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
13188 gen_rtx_REG (Pmode, 12));
13191 RTX_FRAME_RELATED_P (insn) = 1;
13193 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13194 gen_rtx_SET (VOIDmode, stack_reg,
13195 gen_rtx_PLUS (Pmode, stack_reg,
13200 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13201 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13202 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13203 deduce these equivalences by itself so it wasn't necessary to hold
13204 its hand so much. */
13207 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13208 rtx reg2, rtx rreg)
13212 /* copy_rtx will not make unique copies of registers, so we need to
13213 ensure we don't have unwanted sharing here. */
13215 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13218 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13220 real = copy_rtx (PATTERN (insn));
13222 if (reg2 != NULL_RTX)
13223 real = replace_rtx (real, reg2, rreg);
13225 real = replace_rtx (real, reg,
13226 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13227 STACK_POINTER_REGNUM),
13230 /* We expect that 'real' is either a SET or a PARALLEL containing
13231 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13232 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13234 if (GET_CODE (real) == SET)
13238 temp = simplify_rtx (SET_SRC (set));
13240 SET_SRC (set) = temp;
13241 temp = simplify_rtx (SET_DEST (set));
13243 SET_DEST (set) = temp;
13244 if (GET_CODE (SET_DEST (set)) == MEM)
13246 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13248 XEXP (SET_DEST (set), 0) = temp;
13251 else if (GET_CODE (real) == PARALLEL)
13254 for (i = 0; i < XVECLEN (real, 0); i++)
13255 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13257 rtx set = XVECEXP (real, 0, i);
13259 temp = simplify_rtx (SET_SRC (set));
13261 SET_SRC (set) = temp;
13262 temp = simplify_rtx (SET_DEST (set));
13264 SET_DEST (set) = temp;
13265 if (GET_CODE (SET_DEST (set)) == MEM)
13267 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13269 XEXP (SET_DEST (set), 0) = temp;
13271 RTX_FRAME_RELATED_P (set) = 1;
13278 real = spe_synthesize_frame_save (real);
13280 RTX_FRAME_RELATED_P (insn) = 1;
13281 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13286 /* Given an SPE frame note, return a PARALLEL of SETs with the
13287 original note, plus a synthetic register save. */
13290 spe_synthesize_frame_save (rtx real)
13292 rtx synth, offset, reg, real2;
13294 if (GET_CODE (real) != SET
13295 || GET_MODE (SET_SRC (real)) != V2SImode)
13298 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13299 frame related note. The parallel contains a set of the register
13300 being saved, and another set to a synthetic register (n+1200).
13301 This is so we can differentiate between 64-bit and 32-bit saves.
13302 Words cannot describe this nastiness. */
13304 if (GET_CODE (SET_DEST (real)) != MEM
13305 || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
13306 || GET_CODE (SET_SRC (real)) != REG)
13310 (set (mem (plus (reg x) (const y)))
13313 (set (mem (plus (reg x) (const y+4)))
13317 real2 = copy_rtx (real);
13318 PUT_MODE (SET_DEST (real2), SImode);
13319 reg = SET_SRC (real2);
13320 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
13321 synth = copy_rtx (real2);
13323 if (BYTES_BIG_ENDIAN)
13325 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
13326 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
13329 reg = SET_SRC (synth);
13331 synth = replace_rtx (synth, reg,
13332 gen_rtx_REG (SImode, REGNO (reg) + 1200));
13334 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
13335 synth = replace_rtx (synth, offset,
13336 GEN_INT (INTVAL (offset)
13337 + (BYTES_BIG_ENDIAN ? 0 : 4)));
13339 RTX_FRAME_RELATED_P (synth) = 1;
13340 RTX_FRAME_RELATED_P (real2) = 1;
13341 if (BYTES_BIG_ENDIAN)
13342 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
13344 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
13349 /* Returns an insn that has a vrsave set operation with the
13350 appropriate CLOBBERs. */
13353 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
13356 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
13357 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13360 = gen_rtx_SET (VOIDmode,
13362 gen_rtx_UNSPEC_VOLATILE (SImode,
13363 gen_rtvec (2, reg, vrsave),
13368 /* We need to clobber the registers in the mask so the scheduler
13369 does not move sets to VRSAVE before sets of AltiVec registers.
13371 However, if the function receives nonlocal gotos, reload will set
13372 all call saved registers live. We will end up with:
13374 (set (reg 999) (mem))
13375 (parallel [ (set (reg vrsave) (unspec blah))
13376 (clobber (reg 999))])
13378 The clobber will cause the store into reg 999 to be dead, and
13379 flow will attempt to delete an epilogue insn. In this case, we
13380 need an unspec use/set of the register. */
13382 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13383 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13385 if (!epiloguep || call_used_regs [i])
13386 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
13387 gen_rtx_REG (V4SImode, i));
13390 rtx reg = gen_rtx_REG (V4SImode, i);
13393 = gen_rtx_SET (VOIDmode,
13395 gen_rtx_UNSPEC (V4SImode,
13396 gen_rtvec (1, reg), 27));
13400 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
13402 for (i = 0; i < nclobs; ++i)
13403 XVECEXP (insn, 0, i) = clobs[i];
13408 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
13409 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
13412 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
13413 unsigned int regno, int offset, HOST_WIDE_INT total_size)
13415 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
13416 rtx replacea, replaceb;
13418 int_rtx = GEN_INT (offset);
13420 /* Some cases that need register indexed addressing. */
13421 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13422 || (TARGET_E500_DOUBLE && mode == DFmode)
13424 && SPE_VECTOR_MODE (mode)
13425 && !SPE_CONST_OFFSET_OK (offset)))
13427 /* Whomever calls us must make sure r11 is available in the
13428 flow path of instructions in the prologue. */
13429 offset_rtx = gen_rtx_REG (Pmode, 11);
13430 emit_move_insn (offset_rtx, int_rtx);
13432 replacea = offset_rtx;
13433 replaceb = int_rtx;
13437 offset_rtx = int_rtx;
13438 replacea = NULL_RTX;
13439 replaceb = NULL_RTX;
13442 reg = gen_rtx_REG (mode, regno);
13443 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
13444 mem = gen_rtx_MEM (mode, addr);
13445 set_mem_alias_set (mem, rs6000_sr_alias_set);
13447 insn = emit_move_insn (mem, reg);
13449 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
13452 /* Emit an offset memory reference suitable for a frame store, while
13453 converting to a valid addressing mode. */
13456 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
13458 rtx int_rtx, offset_rtx;
13460 int_rtx = GEN_INT (offset);
13462 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
13463 || (TARGET_E500_DOUBLE && mode == DFmode))
13465 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13466 emit_move_insn (offset_rtx, int_rtx);
13469 offset_rtx = int_rtx;
13471 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
13474 #ifndef TARGET_FIX_AND_CONTINUE
13475 #define TARGET_FIX_AND_CONTINUE 0
13478 /* Emit function prologue as insns. */
13481 rs6000_emit_prologue (void)
13483 rs6000_stack_t *info = rs6000_stack_info ();
13484 enum machine_mode reg_mode = Pmode;
13485 int reg_size = TARGET_32BIT ? 4 : 8;
13486 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13487 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
13488 rtx frame_reg_rtx = sp_reg_rtx;
13489 rtx cr_save_rtx = NULL_RTX;
13491 int saving_FPRs_inline;
13492 int using_store_multiple;
13493 HOST_WIDE_INT sp_offset = 0;
13495 if (TARGET_FIX_AND_CONTINUE)
13497 /* gdb on darwin arranges to forward a function from the old
13498 address by modifying the first 4 instructions of the function
13499 to branch to the overriding function. This is necessary to
13500 permit function pointers that point to the old function to
13501 actually forward to the new function. */
13502 emit_insn (gen_nop ());
13503 emit_insn (gen_nop ());
13504 emit_insn (gen_nop ());
13505 emit_insn (gen_nop ());
13508 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13510 reg_mode = V2SImode;
13514 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
13515 && (!TARGET_SPE_ABI
13516 || info->spe_64bit_regs_used == 0)
13517 && info->first_gp_reg_save < 31);
13518 saving_FPRs_inline = (info->first_fp_reg_save == 64
13519 || FP_SAVE_INLINE (info->first_fp_reg_save)
13520 || current_function_calls_eh_return
13521 || cfun->machine->ra_need_lr);
13523 /* For V.4, update stack before we do any saving and set back pointer. */
13525 && (DEFAULT_ABI == ABI_V4
13526 || current_function_calls_eh_return))
13528 if (info->total_size < 32767)
13529 sp_offset = info->total_size;
13531 frame_reg_rtx = frame_ptr_rtx;
13532 rs6000_emit_allocate_stack (info->total_size,
13533 (frame_reg_rtx != sp_reg_rtx
13534 && (info->cr_save_p
13536 || info->first_fp_reg_save < 64
13537 || info->first_gp_reg_save < 32
13539 if (frame_reg_rtx != sp_reg_rtx)
13540 rs6000_emit_stack_tie ();
13543 /* Handle world saves specially here. */
13544 if (info->world_save_p)
13550 /* save_world expects lr in r0. */
13551 if (info->lr_save_p)
13553 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
13554 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
13555 RTX_FRAME_RELATED_P (insn) = 1;
13558 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
13559 assumptions about the offsets of various bits of the stack
13560 frame. Abort if things aren't what they should be. */
13561 if (info->gp_save_offset != -220
13562 || info->fp_save_offset != -144
13563 || info->lr_save_offset != 8
13564 || info->cr_save_offset != 4
13566 || !info->lr_save_p
13567 || (current_function_calls_eh_return && info->ehrd_offset != -432)
13568 || (info->vrsave_save_offset != -224
13569 || info->altivec_save_offset != (-224 -16 -192)))
13572 treg = gen_rtx_REG (SImode, 11);
13573 emit_move_insn (treg, GEN_INT (-info->total_size));
13575 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
13576 in R11. It also clobbers R12, so beware! */
13578 /* Preserve CR2 for save_world prologues */
13580 sz += 32 - info->first_gp_reg_save;
13581 sz += 64 - info->first_fp_reg_save;
13582 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
13583 p = rtvec_alloc (sz);
13585 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
13586 gen_rtx_REG (Pmode,
13587 LINK_REGISTER_REGNUM));
13588 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
13589 gen_rtx_SYMBOL_REF (Pmode,
13591 /* We do floats first so that the instruction pattern matches
13593 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13595 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13596 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13597 GEN_INT (info->fp_save_offset
13598 + sp_offset + 8 * i));
13599 rtx mem = gen_rtx_MEM (DFmode, addr);
13600 set_mem_alias_set (mem, rs6000_sr_alias_set);
13602 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13604 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
13606 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13607 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13608 GEN_INT (info->altivec_save_offset
13609 + sp_offset + 16 * i));
13610 rtx mem = gen_rtx_MEM (V4SImode, addr);
13611 set_mem_alias_set (mem, rs6000_sr_alias_set);
13613 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13615 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13617 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13618 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13619 GEN_INT (info->gp_save_offset
13620 + sp_offset + reg_size * i));
13621 rtx mem = gen_rtx_MEM (reg_mode, addr);
13622 set_mem_alias_set (mem, rs6000_sr_alias_set);
13624 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13628 /* CR register traditionally saved as CR2. */
13629 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13630 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13631 GEN_INT (info->cr_save_offset
13633 rtx mem = gen_rtx_MEM (reg_mode, addr);
13634 set_mem_alias_set (mem, rs6000_sr_alias_set);
13636 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13638 /* Prevent any attempt to delete the setting of r0 and treg! */
13639 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
13640 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
13641 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
13643 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13644 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13645 NULL_RTX, NULL_RTX);
13647 if (current_function_calls_eh_return)
13652 unsigned int regno = EH_RETURN_DATA_REGNO (i);
13653 if (regno == INVALID_REGNUM)
13655 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13656 info->ehrd_offset + sp_offset
13657 + reg_size * (int) i,
13663 /* Save AltiVec registers if needed. */
13664 if (! info->world_save_p && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
13668 /* There should be a non inline version of this, for when we
13669 are saving lots of vector registers. */
13670 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
13671 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13673 rtx areg, savereg, mem;
13676 offset = info->altivec_save_offset + sp_offset
13677 + 16 * (i - info->first_altivec_reg_save);
13679 savereg = gen_rtx_REG (V4SImode, i);
13681 areg = gen_rtx_REG (Pmode, 0);
13682 emit_move_insn (areg, GEN_INT (offset));
13684 /* AltiVec addressing mode is [reg+reg]. */
13685 mem = gen_rtx_MEM (V4SImode,
13686 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
13688 set_mem_alias_set (mem, rs6000_sr_alias_set);
13690 insn = emit_move_insn (mem, savereg);
13692 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13693 areg, GEN_INT (offset));
13697 /* VRSAVE is a bit vector representing which AltiVec registers
13698 are used. The OS uses this to determine which vector
13699 registers to save on a context switch. We need to save
13700 VRSAVE on the stack frame, add whatever AltiVec registers we
13701 used in this function, and do the corresponding magic in the
13704 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
13705 && ! info->world_save_p && info->vrsave_mask != 0)
13707 rtx reg, mem, vrsave;
13710 /* Get VRSAVE onto a GPR. */
13711 reg = gen_rtx_REG (SImode, 12);
13712 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13714 emit_insn (gen_get_vrsave_internal (reg));
13716 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
13719 offset = info->vrsave_save_offset + sp_offset;
13721 = gen_rtx_MEM (SImode,
13722 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
13723 set_mem_alias_set (mem, rs6000_sr_alias_set);
13724 insn = emit_move_insn (mem, reg);
13726 /* Include the registers in the mask. */
13727 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
13729 insn = emit_insn (generate_set_vrsave (reg, info, 0));
13732 /* If we use the link register, get it into r0. */
13733 if (! info->world_save_p && info->lr_save_p)
13735 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
13736 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
13737 RTX_FRAME_RELATED_P (insn) = 1;
13740 /* If we need to save CR, put it into r12. */
13741 if (! info->world_save_p && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
13745 cr_save_rtx = gen_rtx_REG (SImode, 12);
13746 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13747 RTX_FRAME_RELATED_P (insn) = 1;
13748 /* Now, there's no way that dwarf2out_frame_debug_expr is going
13749 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
13750 But that's OK. All we have to do is specify that _one_ condition
13751 code register is saved in this stack slot. The thrower's epilogue
13752 will then restore all the call-saved registers.
13753 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
13754 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
13755 gen_rtx_REG (SImode, CR2_REGNO));
13756 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13761 /* Do any required saving of fpr's. If only one or two to save, do
13762 it ourselves. Otherwise, call function. */
13763 if (! info->world_save_p && saving_FPRs_inline)
13766 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13767 if ((regs_ever_live[info->first_fp_reg_save+i]
13768 && ! call_used_regs[info->first_fp_reg_save+i]))
13769 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
13770 info->first_fp_reg_save + i,
13771 info->fp_save_offset + sp_offset + 8 * i,
13774 else if (! info->world_save_p && info->first_fp_reg_save != 64)
13778 const char *alloc_rname;
13780 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
13782 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
13783 gen_rtx_REG (Pmode,
13784 LINK_REGISTER_REGNUM));
13785 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
13786 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
13787 alloc_rname = ggc_strdup (rname);
13788 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
13789 gen_rtx_SYMBOL_REF (Pmode,
13791 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13793 rtx addr, reg, mem;
13794 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13795 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13796 GEN_INT (info->fp_save_offset
13797 + sp_offset + 8*i));
13798 mem = gen_rtx_MEM (DFmode, addr);
13799 set_mem_alias_set (mem, rs6000_sr_alias_set);
13801 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
13803 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13804 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13805 NULL_RTX, NULL_RTX);
13808 /* Save GPRs. This is done as a PARALLEL if we are using
13809 the store-multiple instructions. */
13810 if (! info->world_save_p && using_store_multiple)
13814 p = rtvec_alloc (32 - info->first_gp_reg_save);
13815 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13817 rtx addr, reg, mem;
13818 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13819 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13820 GEN_INT (info->gp_save_offset
13823 mem = gen_rtx_MEM (reg_mode, addr);
13824 set_mem_alias_set (mem, rs6000_sr_alias_set);
13826 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
13828 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13829 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13830 NULL_RTX, NULL_RTX);
13832 else if (! info->world_save_p)
13835 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13836 if ((regs_ever_live[info->first_gp_reg_save+i]
13837 && (! call_used_regs[info->first_gp_reg_save+i]
13838 || (i+info->first_gp_reg_save
13839 == RS6000_PIC_OFFSET_TABLE_REGNUM
13840 && TARGET_TOC && TARGET_MINIMAL_TOC)))
13841 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
13842 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13843 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
13845 rtx addr, reg, mem;
13846 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13848 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13850 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
13853 if (!SPE_CONST_OFFSET_OK (offset))
13855 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13856 emit_move_insn (b, GEN_INT (offset));
13859 b = GEN_INT (offset);
13861 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
13862 mem = gen_rtx_MEM (V2SImode, addr);
13863 set_mem_alias_set (mem, rs6000_sr_alias_set);
13864 insn = emit_move_insn (mem, reg);
13866 if (GET_CODE (b) == CONST_INT)
13867 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13868 NULL_RTX, NULL_RTX);
13870 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13871 b, GEN_INT (offset));
13875 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13876 GEN_INT (info->gp_save_offset
13879 mem = gen_rtx_MEM (reg_mode, addr);
13880 set_mem_alias_set (mem, rs6000_sr_alias_set);
13882 insn = emit_move_insn (mem, reg);
13883 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13884 NULL_RTX, NULL_RTX);
13889 /* ??? There's no need to emit actual instructions here, but it's the
13890 easiest way to get the frame unwind information emitted. */
13891 if (! info->world_save_p && current_function_calls_eh_return)
13893 unsigned int i, regno;
13895 /* In AIX ABI we need to pretend we save r2 here. */
13898 rtx addr, reg, mem;
13900 reg = gen_rtx_REG (reg_mode, 2);
13901 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13902 GEN_INT (sp_offset + 5 * reg_size));
13903 mem = gen_rtx_MEM (reg_mode, addr);
13904 set_mem_alias_set (mem, rs6000_sr_alias_set);
13906 insn = emit_move_insn (mem, reg);
13907 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13908 NULL_RTX, NULL_RTX);
13909 PATTERN (insn) = gen_blockage ();
13914 regno = EH_RETURN_DATA_REGNO (i);
13915 if (regno == INVALID_REGNUM)
13918 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13919 info->ehrd_offset + sp_offset
13920 + reg_size * (int) i,
13925 /* Save lr if we used it. */
13926 if (! info->world_save_p && info->lr_save_p)
13928 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13929 GEN_INT (info->lr_save_offset + sp_offset));
13930 rtx reg = gen_rtx_REG (Pmode, 0);
13931 rtx mem = gen_rtx_MEM (Pmode, addr);
13932 /* This should not be of rs6000_sr_alias_set, because of
13933 __builtin_return_address. */
13935 insn = emit_move_insn (mem, reg);
13936 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13937 NULL_RTX, NULL_RTX);
13940 /* Save CR if we use any that must be preserved. */
13941 if (! info->world_save_p && info->cr_save_p)
13943 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13944 GEN_INT (info->cr_save_offset + sp_offset));
13945 rtx mem = gen_rtx_MEM (SImode, addr);
13946 /* See the large comment above about why CR2_REGNO is used. */
13947 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
13949 set_mem_alias_set (mem, rs6000_sr_alias_set);
13951 /* If r12 was used to hold the original sp, copy cr into r0 now
13953 if (REGNO (frame_reg_rtx) == 12)
13957 cr_save_rtx = gen_rtx_REG (SImode, 0);
13958 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13959 RTX_FRAME_RELATED_P (insn) = 1;
13960 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
13961 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13966 insn = emit_move_insn (mem, cr_save_rtx);
13968 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13969 NULL_RTX, NULL_RTX);
13972 /* Update stack and set back pointer unless this is V.4,
13973 for which it was done previously. */
13974 if (! info->world_save_p && info->push_p
13975 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
13976 rs6000_emit_allocate_stack (info->total_size, FALSE);
13978 /* Set frame pointer, if needed. */
13979 if (frame_pointer_needed)
13981 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
13983 RTX_FRAME_RELATED_P (insn) = 1;
13986 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
13987 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
13988 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
13989 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
13991 /* If emit_load_toc_table will use the link register, we need to save
13992 it. We use R12 for this purpose because emit_load_toc_table
13993 can use register 0. This allows us to use a plain 'blr' to return
13994 from the procedure more often. */
13995 int save_LR_around_toc_setup = (TARGET_ELF
13996 && DEFAULT_ABI != ABI_AIX
13998 && ! info->lr_save_p
13999 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
14000 if (save_LR_around_toc_setup)
14002 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14004 insn = emit_move_insn (frame_ptr_rtx, lr);
14005 rs6000_maybe_dead (insn);
14006 RTX_FRAME_RELATED_P (insn) = 1;
14008 rs6000_emit_load_toc_table (TRUE);
14010 insn = emit_move_insn (lr, frame_ptr_rtx);
14011 rs6000_maybe_dead (insn);
14012 RTX_FRAME_RELATED_P (insn) = 1;
14015 rs6000_emit_load_toc_table (TRUE);
14019 if (DEFAULT_ABI == ABI_DARWIN
14020 && flag_pic && current_function_uses_pic_offset_table)
14022 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14023 rtx src = machopic_function_base_sym ();
14025 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14027 insn = emit_move_insn (gen_rtx_REG (Pmode,
14028 RS6000_PIC_OFFSET_TABLE_REGNUM),
14030 rs6000_maybe_dead (insn);
14035 /* Write function prologue. */
14038 rs6000_output_function_prologue (FILE *file,
14039 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14041 rs6000_stack_t *info = rs6000_stack_info ();
14043 if (TARGET_DEBUG_STACK)
14044 debug_stack_info (info);
14046 /* Write .extern for any function we will call to save and restore
14048 if (info->first_fp_reg_save < 64
14049 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14050 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14051 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14052 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14053 RESTORE_FP_SUFFIX);
14055 /* Write .extern for AIX common mode routines, if needed. */
14056 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14058 fputs ("\t.extern __mulh\n", file);
14059 fputs ("\t.extern __mull\n", file);
14060 fputs ("\t.extern __divss\n", file);
14061 fputs ("\t.extern __divus\n", file);
14062 fputs ("\t.extern __quoss\n", file);
14063 fputs ("\t.extern __quous\n", file);
14064 common_mode_defined = 1;
14067 if (! HAVE_prologue)
14071 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14072 the "toplevel" insn chain. */
14073 emit_note (NOTE_INSN_DELETED);
14074 rs6000_emit_prologue ();
14075 emit_note (NOTE_INSN_DELETED);
14077 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14081 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14083 INSN_ADDRESSES_NEW (insn, addr);
14088 if (TARGET_DEBUG_STACK)
14089 debug_rtx_list (get_insns (), 100);
14090 final (get_insns (), file, FALSE, FALSE);
14094 rs6000_pic_labelno++;
14097 /* Emit function epilogue as insns.
14099 At present, dwarf2out_frame_debug_expr doesn't understand
14100 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14101 anywhere in the epilogue. Most of the insns below would in any case
14102 need special notes to explain where r11 is in relation to the stack. */
14105 rs6000_emit_epilogue (int sibcall)
14107 rs6000_stack_t *info;
14108 int restoring_FPRs_inline;
14109 int using_load_multiple;
14110 int using_mfcr_multiple;
14111 int use_backchain_to_restore_sp;
14113 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
14114 rtx frame_reg_rtx = sp_reg_rtx;
14115 enum machine_mode reg_mode = Pmode;
14116 int reg_size = TARGET_32BIT ? 4 : 8;
14119 info = rs6000_stack_info ();
14121 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14123 reg_mode = V2SImode;
14127 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14128 && (!TARGET_SPE_ABI
14129 || info->spe_64bit_regs_used == 0)
14130 && info->first_gp_reg_save < 31);
14131 restoring_FPRs_inline = (sibcall
14132 || current_function_calls_eh_return
14133 || info->first_fp_reg_save == 64
14134 || FP_SAVE_INLINE (info->first_fp_reg_save));
14135 use_backchain_to_restore_sp = (frame_pointer_needed
14136 || current_function_calls_alloca
14137 || info->total_size > 32767);
14138 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
14139 || rs6000_cpu == PROCESSOR_PPC603
14140 || rs6000_cpu == PROCESSOR_PPC750
14143 if (info->world_save_p)
14147 const char *alloc_rname;
14150 /* eh_rest_world_r10 will return to the location saved in the LR
14151 stack slot (which is not likely to be our caller.)
14152 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14153 rest_world is similar, except any R10 parameter is ignored.
14154 The exception-handling stuff that was here in 2.95 is no
14155 longer necessary. */
14159 + 32 - info->first_gp_reg_save
14160 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
14161 + 63 + 1 - info->first_fp_reg_save);
14163 strcpy (rname, ((current_function_calls_eh_return) ?
14164 "*eh_rest_world_r10" : "*rest_world"));
14165 alloc_rname = ggc_strdup (rname);
14168 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
14169 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14170 gen_rtx_REG (Pmode,
14171 LINK_REGISTER_REGNUM));
14173 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
14174 /* The instruction pattern requires a clobber here;
14175 it is shared with the restVEC helper. */
14177 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14180 /* CR register traditionally saved as CR2. */
14181 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14182 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14183 GEN_INT (info->cr_save_offset));
14184 rtx mem = gen_rtx_MEM (reg_mode, addr);
14185 set_mem_alias_set (mem, rs6000_sr_alias_set);
14187 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14190 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14192 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14193 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14194 GEN_INT (info->gp_save_offset
14196 rtx mem = gen_rtx_MEM (reg_mode, addr);
14197 set_mem_alias_set (mem, rs6000_sr_alias_set);
14199 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14201 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14203 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14204 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14205 GEN_INT (info->altivec_save_offset
14207 rtx mem = gen_rtx_MEM (V4SImode, addr);
14208 set_mem_alias_set (mem, rs6000_sr_alias_set);
14210 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14212 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14214 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14215 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14216 GEN_INT (info->fp_save_offset
14218 rtx mem = gen_rtx_MEM (DFmode, addr);
14219 set_mem_alias_set (mem, rs6000_sr_alias_set);
14221 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14224 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
14226 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
14228 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
14230 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
14232 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
14233 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14238 /* If we have a frame pointer, a call to alloca, or a large stack
14239 frame, restore the old stack pointer using the backchain. Otherwise,
14240 we know what size to update it with. */
14241 if (use_backchain_to_restore_sp)
14243 /* Under V.4, don't reset the stack pointer until after we're done
14244 loading the saved registers. */
14245 if (DEFAULT_ABI == ABI_V4)
14246 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
14248 emit_move_insn (frame_reg_rtx,
14249 gen_rtx_MEM (Pmode, sp_reg_rtx));
14252 else if (info->push_p)
14254 if (DEFAULT_ABI == ABI_V4
14255 || current_function_calls_eh_return)
14256 sp_offset = info->total_size;
14259 emit_insn (TARGET_32BIT
14260 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14261 GEN_INT (info->total_size))
14262 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14263 GEN_INT (info->total_size)));
14267 /* Restore AltiVec registers if needed. */
14268 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14272 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14273 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14275 rtx addr, areg, mem;
14277 areg = gen_rtx_REG (Pmode, 0);
14279 (areg, GEN_INT (info->altivec_save_offset
14281 + 16 * (i - info->first_altivec_reg_save)));
14283 /* AltiVec addressing mode is [reg+reg]. */
14284 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14285 mem = gen_rtx_MEM (V4SImode, addr);
14286 set_mem_alias_set (mem, rs6000_sr_alias_set);
14288 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14292 /* Restore VRSAVE if needed. */
14293 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14294 && info->vrsave_mask != 0)
14296 rtx addr, mem, reg;
14298 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14299 GEN_INT (info->vrsave_save_offset + sp_offset));
14300 mem = gen_rtx_MEM (SImode, addr);
14301 set_mem_alias_set (mem, rs6000_sr_alias_set);
14302 reg = gen_rtx_REG (SImode, 12);
14303 emit_move_insn (reg, mem);
14305 emit_insn (generate_set_vrsave (reg, info, 1));
14308 /* Get the old lr if we saved it. */
14309 if (info->lr_save_p)
14311 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
14312 info->lr_save_offset + sp_offset);
14314 set_mem_alias_set (mem, rs6000_sr_alias_set);
14316 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
14319 /* Get the old cr if we saved it. */
14320 if (info->cr_save_p)
14322 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14323 GEN_INT (info->cr_save_offset + sp_offset));
14324 rtx mem = gen_rtx_MEM (SImode, addr);
14326 set_mem_alias_set (mem, rs6000_sr_alias_set);
14328 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
14331 /* Set LR here to try to overlap restores below. */
14332 if (info->lr_save_p)
14333 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
14334 gen_rtx_REG (Pmode, 0));
14336 /* Load exception handler data registers, if needed. */
14337 if (current_function_calls_eh_return)
14339 unsigned int i, regno;
14343 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14344 GEN_INT (sp_offset + 5 * reg_size));
14345 rtx mem = gen_rtx_MEM (reg_mode, addr);
14347 set_mem_alias_set (mem, rs6000_sr_alias_set);
14349 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
14356 regno = EH_RETURN_DATA_REGNO (i);
14357 if (regno == INVALID_REGNUM)
14360 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
14361 info->ehrd_offset + sp_offset
14362 + reg_size * (int) i);
14363 set_mem_alias_set (mem, rs6000_sr_alias_set);
14365 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
14369 /* Restore GPRs. This is done as a PARALLEL if we are using
14370 the load-multiple instructions. */
14371 if (using_load_multiple)
14374 p = rtvec_alloc (32 - info->first_gp_reg_save);
14375 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14377 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14378 GEN_INT (info->gp_save_offset
14381 rtx mem = gen_rtx_MEM (reg_mode, addr);
14383 set_mem_alias_set (mem, rs6000_sr_alias_set);
14386 gen_rtx_SET (VOIDmode,
14387 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
14390 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14393 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14394 if ((regs_ever_live[info->first_gp_reg_save+i]
14395 && (! call_used_regs[info->first_gp_reg_save+i]
14396 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14397 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14398 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14399 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14400 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14402 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14403 GEN_INT (info->gp_save_offset
14406 rtx mem = gen_rtx_MEM (reg_mode, addr);
14408 /* Restore 64-bit quantities for SPE. */
14409 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14411 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14414 if (!SPE_CONST_OFFSET_OK (offset))
14416 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14417 emit_move_insn (b, GEN_INT (offset));
14420 b = GEN_INT (offset);
14422 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14423 mem = gen_rtx_MEM (V2SImode, addr);
14426 set_mem_alias_set (mem, rs6000_sr_alias_set);
14428 emit_move_insn (gen_rtx_REG (reg_mode,
14429 info->first_gp_reg_save + i), mem);
14432 /* Restore fpr's if we need to do it without calling a function. */
14433 if (restoring_FPRs_inline)
14434 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14435 if ((regs_ever_live[info->first_fp_reg_save+i]
14436 && ! call_used_regs[info->first_fp_reg_save+i]))
14439 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14440 GEN_INT (info->fp_save_offset
14443 mem = gen_rtx_MEM (DFmode, addr);
14444 set_mem_alias_set (mem, rs6000_sr_alias_set);
14446 emit_move_insn (gen_rtx_REG (DFmode,
14447 info->first_fp_reg_save + i),
14451 /* If we saved cr, restore it here. Just those that were used. */
14452 if (info->cr_save_p)
14454 rtx r12_rtx = gen_rtx_REG (SImode, 12);
14457 if (using_mfcr_multiple)
14459 for (i = 0; i < 8; i++)
14460 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14466 if (using_mfcr_multiple && count > 1)
14471 p = rtvec_alloc (count);
14474 for (i = 0; i < 8; i++)
14475 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14477 rtvec r = rtvec_alloc (2);
14478 RTVEC_ELT (r, 0) = r12_rtx;
14479 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
14480 RTVEC_ELT (p, ndx) =
14481 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
14482 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
14485 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14490 for (i = 0; i < 8; i++)
14491 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14493 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
14499 /* If this is V.4, unwind the stack pointer after all of the loads
14500 have been done. We need to emit a block here so that sched
14501 doesn't decide to move the sp change before the register restores
14502 (which may not have any obvious dependency on the stack). This
14503 doesn't hurt performance, because there is no scheduling that can
14504 be done after this point. */
14505 if (DEFAULT_ABI == ABI_V4
14506 || current_function_calls_eh_return)
14508 if (frame_reg_rtx != sp_reg_rtx)
14509 rs6000_emit_stack_tie ();
14511 if (use_backchain_to_restore_sp)
14513 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
14515 else if (sp_offset != 0)
14517 emit_insn (TARGET_32BIT
14518 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14519 GEN_INT (sp_offset))
14520 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14521 GEN_INT (sp_offset)));
14525 if (current_function_calls_eh_return)
14527 rtx sa = EH_RETURN_STACKADJ_RTX;
14528 emit_insn (TARGET_32BIT
14529 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
14530 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
14536 if (! restoring_FPRs_inline)
14537 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
14539 p = rtvec_alloc (2);
14541 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
14542 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14543 gen_rtx_REG (Pmode,
14544 LINK_REGISTER_REGNUM));
14546 /* If we have to restore more than two FP registers, branch to the
14547 restore function. It will return to our caller. */
14548 if (! restoring_FPRs_inline)
14552 const char *alloc_rname;
14554 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
14555 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
14556 alloc_rname = ggc_strdup (rname);
14557 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
14558 gen_rtx_SYMBOL_REF (Pmode,
14561 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14564 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
14565 GEN_INT (info->fp_save_offset + 8*i));
14566 mem = gen_rtx_MEM (DFmode, addr);
14567 set_mem_alias_set (mem, rs6000_sr_alias_set);
14569 RTVEC_ELT (p, i+3) =
14570 gen_rtx_SET (VOIDmode,
14571 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
14576 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14580 /* Write function epilogue. */
14583 rs6000_output_function_epilogue (FILE *file,
14584 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14586 rs6000_stack_t *info = rs6000_stack_info ();
14588 if (! HAVE_epilogue)
14590 rtx insn = get_last_insn ();
14591 /* If the last insn was a BARRIER, we don't have to write anything except
14592 the trace table. */
14593 if (GET_CODE (insn) == NOTE)
14594 insn = prev_nonnote_insn (insn);
14595 if (insn == 0 || GET_CODE (insn) != BARRIER)
14597 /* This is slightly ugly, but at least we don't have two
14598 copies of the epilogue-emitting code. */
14601 /* A NOTE_INSN_DELETED is supposed to be at the start
14602 and end of the "toplevel" insn chain. */
14603 emit_note (NOTE_INSN_DELETED);
14604 rs6000_emit_epilogue (FALSE);
14605 emit_note (NOTE_INSN_DELETED);
14607 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14611 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14613 INSN_ADDRESSES_NEW (insn, addr);
14618 if (TARGET_DEBUG_STACK)
14619 debug_rtx_list (get_insns (), 100);
14620 final (get_insns (), file, FALSE, FALSE);
14626 macho_branch_islands ();
14627 /* Mach-O doesn't support labels at the end of objects, so if
14628 it looks like we might want one, insert a NOP. */
14630 rtx insn = get_last_insn ();
14633 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
14634 insn = PREV_INSN (insn);
14638 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
14639 fputs ("\tnop\n", file);
14643 /* Output a traceback table here. See /usr/include/sys/debug.h for info
14646 We don't output a traceback table if -finhibit-size-directive was
14647 used. The documentation for -finhibit-size-directive reads
14648 ``don't output a @code{.size} assembler directive, or anything
14649 else that would cause trouble if the function is split in the
14650 middle, and the two halves are placed at locations far apart in
14651 memory.'' The traceback table has this property, since it
14652 includes the offset from the start of the function to the
14653 traceback table itself.
14655 System V.4 Powerpc's (and the embedded ABI derived from it) use a
14656 different traceback table. */
14657 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
14658 && rs6000_traceback != traceback_none)
14660 const char *fname = NULL;
14661 const char *language_string = lang_hooks.name;
14662 int fixed_parms = 0, float_parms = 0, parm_info = 0;
14664 int optional_tbtab;
14666 if (rs6000_traceback == traceback_full)
14667 optional_tbtab = 1;
14668 else if (rs6000_traceback == traceback_part)
14669 optional_tbtab = 0;
14671 optional_tbtab = !optimize_size && !TARGET_ELF;
14673 if (optional_tbtab)
14675 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
14676 while (*fname == '.') /* V.4 encodes . in the name */
14679 /* Need label immediately before tbtab, so we can compute
14680 its offset from the function start. */
14681 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
14682 ASM_OUTPUT_LABEL (file, fname);
14685 /* The .tbtab pseudo-op can only be used for the first eight
14686 expressions, since it can't handle the possibly variable
14687 length fields that follow. However, if you omit the optional
14688 fields, the assembler outputs zeros for all optional fields
14689 anyways, giving each variable length field is minimum length
14690 (as defined in sys/debug.h). Thus we can not use the .tbtab
14691 pseudo-op at all. */
14693 /* An all-zero word flags the start of the tbtab, for debuggers
14694 that have to find it by searching forward from the entry
14695 point or from the current pc. */
14696 fputs ("\t.long 0\n", file);
14698 /* Tbtab format type. Use format type 0. */
14699 fputs ("\t.byte 0,", file);
14701 /* Language type. Unfortunately, there does not seem to be any
14702 official way to discover the language being compiled, so we
14703 use language_string.
14704 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
14705 Java is 13. Objective-C is 14. */
14706 if (! strcmp (language_string, "GNU C"))
14708 else if (! strcmp (language_string, "GNU F77")
14709 || ! strcmp (language_string, "GNU F95"))
14711 else if (! strcmp (language_string, "GNU Pascal"))
14713 else if (! strcmp (language_string, "GNU Ada"))
14715 else if (! strcmp (language_string, "GNU C++"))
14717 else if (! strcmp (language_string, "GNU Java"))
14719 else if (! strcmp (language_string, "GNU Objective-C"))
14723 fprintf (file, "%d,", i);
14725 /* 8 single bit fields: global linkage (not set for C extern linkage,
14726 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
14727 from start of procedure stored in tbtab, internal function, function
14728 has controlled storage, function has no toc, function uses fp,
14729 function logs/aborts fp operations. */
14730 /* Assume that fp operations are used if any fp reg must be saved. */
14731 fprintf (file, "%d,",
14732 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
14734 /* 6 bitfields: function is interrupt handler, name present in
14735 proc table, function calls alloca, on condition directives
14736 (controls stack walks, 3 bits), saves condition reg, saves
14738 /* The `function calls alloca' bit seems to be set whenever reg 31 is
14739 set up as a frame pointer, even when there is no alloca call. */
14740 fprintf (file, "%d,",
14741 ((optional_tbtab << 6)
14742 | ((optional_tbtab & frame_pointer_needed) << 5)
14743 | (info->cr_save_p << 1)
14744 | (info->lr_save_p)));
14746 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
14748 fprintf (file, "%d,",
14749 (info->push_p << 7) | (64 - info->first_fp_reg_save));
14751 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
14752 fprintf (file, "%d,", (32 - first_reg_to_save ()));
14754 if (optional_tbtab)
14756 /* Compute the parameter info from the function decl argument
14759 int next_parm_info_bit = 31;
14761 for (decl = DECL_ARGUMENTS (current_function_decl);
14762 decl; decl = TREE_CHAIN (decl))
14764 rtx parameter = DECL_INCOMING_RTL (decl);
14765 enum machine_mode mode = GET_MODE (parameter);
14767 if (GET_CODE (parameter) == REG)
14769 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
14775 if (mode == SFmode)
14777 else if (mode == DFmode || mode == TFmode)
14782 /* If only one bit will fit, don't or in this entry. */
14783 if (next_parm_info_bit > 0)
14784 parm_info |= (bits << (next_parm_info_bit - 1));
14785 next_parm_info_bit -= 2;
14789 fixed_parms += ((GET_MODE_SIZE (mode)
14790 + (UNITS_PER_WORD - 1))
14792 next_parm_info_bit -= 1;
14798 /* Number of fixed point parameters. */
14799 /* This is actually the number of words of fixed point parameters; thus
14800 an 8 byte struct counts as 2; and thus the maximum value is 8. */
14801 fprintf (file, "%d,", fixed_parms);
14803 /* 2 bitfields: number of floating point parameters (7 bits), parameters
14805 /* This is actually the number of fp registers that hold parameters;
14806 and thus the maximum value is 13. */
14807 /* Set parameters on stack bit if parameters are not in their original
14808 registers, regardless of whether they are on the stack? Xlc
14809 seems to set the bit when not optimizing. */
14810 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
14812 if (! optional_tbtab)
14815 /* Optional fields follow. Some are variable length. */
14817 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
14818 11 double float. */
14819 /* There is an entry for each parameter in a register, in the order that
14820 they occur in the parameter list. Any intervening arguments on the
14821 stack are ignored. If the list overflows a long (max possible length
14822 34 bits) then completely leave off all elements that don't fit. */
14823 /* Only emit this long if there was at least one parameter. */
14824 if (fixed_parms || float_parms)
14825 fprintf (file, "\t.long %d\n", parm_info);
14827 /* Offset from start of code to tb table. */
14828 fputs ("\t.long ", file);
14829 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
14831 RS6000_OUTPUT_BASENAME (file, fname);
14833 assemble_name (file, fname);
14835 rs6000_output_function_entry (file, fname);
14838 /* Interrupt handler mask. */
14839 /* Omit this long, since we never set the interrupt handler bit
14842 /* Number of CTL (controlled storage) anchors. */
14843 /* Omit this long, since the has_ctl bit is never set above. */
14845 /* Displacement into stack of each CTL anchor. */
14846 /* Omit this list of longs, because there are no CTL anchors. */
14848 /* Length of function name. */
14851 fprintf (file, "\t.short %d\n", (int) strlen (fname));
14853 /* Function name. */
14854 assemble_string (fname, strlen (fname));
14856 /* Register for alloca automatic storage; this is always reg 31.
14857 Only emit this if the alloca bit was set above. */
14858 if (frame_pointer_needed)
14859 fputs ("\t.byte 31\n", file);
14861 fputs ("\t.align 2\n", file);
14865 /* A C compound statement that outputs the assembler code for a thunk
14866 function, used to implement C++ virtual function calls with
14867 multiple inheritance. The thunk acts as a wrapper around a virtual
14868 function, adjusting the implicit object parameter before handing
14869 control off to the real function.
14871 First, emit code to add the integer DELTA to the location that
14872 contains the incoming first argument. Assume that this argument
14873 contains a pointer, and is the one used to pass the `this' pointer
14874 in C++. This is the incoming argument *before* the function
14875 prologue, e.g. `%o0' on a sparc. The addition must preserve the
14876 values of all other incoming arguments.
14878 After the addition, emit code to jump to FUNCTION, which is a
14879 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
14880 not touch the return address. Hence returning from FUNCTION will
14881 return to whoever called the current `thunk'.
14883 The effect must be as if FUNCTION had been called directly with the
14884 adjusted first argument. This macro is responsible for emitting
14885 all of the code for a thunk function; output_function_prologue()
14886 and output_function_epilogue() are not invoked.
14888 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
14889 been extracted from it.) It might possibly be useful on some
14890 targets, but probably not.
14892 If you do not define this macro, the target-independent code in the
14893 C++ frontend will generate a less efficient heavyweight thunk that
14894 calls FUNCTION instead of jumping to it. The generic approach does
14895 not support varargs. */
14898 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
14899 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
14902 rtx this, insn, funexp;
14904 reload_completed = 1;
14905 epilogue_completed = 1;
14906 no_new_pseudos = 1;
14907 reset_block_changes ();
14909 /* Mark the end of the (empty) prologue. */
14910 emit_note (NOTE_INSN_PROLOGUE_END);
14912 /* Find the "this" pointer. If the function returns a structure,
14913 the structure return pointer is in r3. */
14914 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
14915 this = gen_rtx_REG (Pmode, 4);
14917 this = gen_rtx_REG (Pmode, 3);
14919 /* Apply the constant offset, if required. */
14922 rtx delta_rtx = GEN_INT (delta);
14923 emit_insn (TARGET_32BIT
14924 ? gen_addsi3 (this, this, delta_rtx)
14925 : gen_adddi3 (this, this, delta_rtx));
14928 /* Apply the offset from the vtable, if required. */
14931 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
14932 rtx tmp = gen_rtx_REG (Pmode, 12);
14934 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
14935 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
14937 emit_insn (TARGET_32BIT
14938 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
14939 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
14940 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
14944 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
14946 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
14948 emit_insn (TARGET_32BIT
14949 ? gen_addsi3 (this, this, tmp)
14950 : gen_adddi3 (this, this, tmp));
14953 /* Generate a tail call to the target function. */
14954 if (!TREE_USED (function))
14956 assemble_external (function);
14957 TREE_USED (function) = 1;
14959 funexp = XEXP (DECL_RTL (function), 0);
14960 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
14963 if (MACHOPIC_INDIRECT)
14964 funexp = machopic_indirect_call_target (funexp);
14967 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
14968 generate sibcall RTL explicitly to avoid constraint abort. */
14969 insn = emit_call_insn (
14970 gen_rtx_PARALLEL (VOIDmode,
14972 gen_rtx_CALL (VOIDmode,
14973 funexp, const0_rtx),
14974 gen_rtx_USE (VOIDmode, const0_rtx),
14975 gen_rtx_USE (VOIDmode,
14976 gen_rtx_REG (SImode,
14977 LINK_REGISTER_REGNUM)),
14978 gen_rtx_RETURN (VOIDmode))));
14979 SIBLING_CALL_P (insn) = 1;
14982 /* Run just enough of rest_of_compilation to get the insns emitted.
14983 There's not really enough bulk here to make other passes such as
14984 instruction scheduling worth while. Note that use_thunk calls
14985 assemble_start_function and assemble_end_function. */
14986 insn = get_insns ();
14987 insn_locators_initialize ();
14988 shorten_branches (insn);
14989 final_start_function (insn, file, 1);
14990 final (insn, file, 1, 0);
14991 final_end_function ();
14993 reload_completed = 0;
14994 epilogue_completed = 0;
14995 no_new_pseudos = 0;
14998 /* A quick summary of the various types of 'constant-pool tables'
15001 Target Flags Name One table per
15002 AIX (none) AIX TOC object file
15003 AIX -mfull-toc AIX TOC object file
15004 AIX -mminimal-toc AIX minimal TOC translation unit
15005 SVR4/EABI (none) SVR4 SDATA object file
15006 SVR4/EABI -fpic SVR4 pic object file
15007 SVR4/EABI -fPIC SVR4 PIC translation unit
15008 SVR4/EABI -mrelocatable EABI TOC function
15009 SVR4/EABI -maix AIX TOC object file
15010 SVR4/EABI -maix -mminimal-toc
15011 AIX minimal TOC translation unit
15013 Name Reg. Set by entries contains:
15014 made by addrs? fp? sum?
15016 AIX TOC 2 crt0 as Y option option
15017 AIX minimal TOC 30 prolog gcc Y Y option
15018 SVR4 SDATA 13 crt0 gcc N Y N
15019 SVR4 pic 30 prolog ld Y not yet N
15020 SVR4 PIC 30 prolog gcc Y option option
15021 EABI TOC 30 prolog gcc Y option option
15025 /* Hash functions for the hash table. */
15028 rs6000_hash_constant (rtx k)
15030 enum rtx_code code = GET_CODE (k);
15031 enum machine_mode mode = GET_MODE (k);
15032 unsigned result = (code << 3) ^ mode;
15033 const char *format;
15036 format = GET_RTX_FORMAT (code);
15037 flen = strlen (format);
15043 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15046 if (mode != VOIDmode)
15047 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15059 for (; fidx < flen; fidx++)
15060 switch (format[fidx])
15065 const char *str = XSTR (k, fidx);
15066 len = strlen (str);
15067 result = result * 613 + len;
15068 for (i = 0; i < len; i++)
15069 result = result * 613 + (unsigned) str[i];
15074 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15078 result = result * 613 + (unsigned) XINT (k, fidx);
15081 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15082 result = result * 613 + (unsigned) XWINT (k, fidx);
15086 for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
15087 result = result * 613 + (unsigned) (XWINT (k, fidx)
15101 toc_hash_function (const void *hash_entry)
15103 const struct toc_hash_struct *thc =
15104 (const struct toc_hash_struct *) hash_entry;
15105 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15108 /* Compare H1 and H2 for equivalence. */
15111 toc_hash_eq (const void *h1, const void *h2)
15113 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
15114 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
15116 if (((const struct toc_hash_struct *) h1)->key_mode
15117 != ((const struct toc_hash_struct *) h2)->key_mode)
15120 return rtx_equal_p (r1, r2);
15123 /* These are the names given by the C++ front-end to vtables, and
15124 vtable-like objects. Ideally, this logic should not be here;
15125 instead, there should be some programmatic way of inquiring as
15126 to whether or not an object is a vtable. */
15128 #define VTABLE_NAME_P(NAME) \
15129 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
15130 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15131 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15132 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15133 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15136 rs6000_output_symbol_ref (FILE *file, rtx x)
15138 /* Currently C++ toc references to vtables can be emitted before it
15139 is decided whether the vtable is public or private. If this is
15140 the case, then the linker will eventually complain that there is
15141 a reference to an unknown section. Thus, for vtables only,
15142 we emit the TOC reference to reference the symbol and not the
15144 const char *name = XSTR (x, 0);
15146 if (VTABLE_NAME_P (name))
15148 RS6000_OUTPUT_BASENAME (file, name);
15151 assemble_name (file, name);
15154 /* Output a TOC entry. We derive the entry name from what is being
15158 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
15161 const char *name = buf;
15162 const char *real_name;
15169 /* When the linker won't eliminate them, don't output duplicate
15170 TOC entries (this happens on AIX if there is any kind of TOC,
15171 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15173 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15175 struct toc_hash_struct *h;
15178 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15179 time because GGC is not initialized at that point. */
15180 if (toc_hash_table == NULL)
15181 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15182 toc_hash_eq, NULL);
15184 h = ggc_alloc (sizeof (*h));
15186 h->key_mode = mode;
15187 h->labelno = labelno;
15189 found = htab_find_slot (toc_hash_table, h, 1);
15190 if (*found == NULL)
15192 else /* This is indeed a duplicate.
15193 Set this label equal to that label. */
15195 fputs ("\t.set ", file);
15196 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15197 fprintf (file, "%d,", labelno);
15198 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15199 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15205 /* If we're going to put a double constant in the TOC, make sure it's
15206 aligned properly when strict alignment is on. */
15207 if (GET_CODE (x) == CONST_DOUBLE
15208 && STRICT_ALIGNMENT
15209 && GET_MODE_BITSIZE (mode) >= 64
15210 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15211 ASM_OUTPUT_ALIGN (file, 3);
15214 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15216 /* Handle FP constants specially. Note that if we have a minimal
15217 TOC, things we put here aren't actually in the TOC, so we can allow
15219 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
15221 REAL_VALUE_TYPE rv;
15224 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15225 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15229 if (TARGET_MINIMAL_TOC)
15230 fputs (DOUBLE_INT_ASM_OP, file);
15232 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15233 k[0] & 0xffffffff, k[1] & 0xffffffff,
15234 k[2] & 0xffffffff, k[3] & 0xffffffff);
15235 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15236 k[0] & 0xffffffff, k[1] & 0xffffffff,
15237 k[2] & 0xffffffff, k[3] & 0xffffffff);
15242 if (TARGET_MINIMAL_TOC)
15243 fputs ("\t.long ", file);
15245 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15246 k[0] & 0xffffffff, k[1] & 0xffffffff,
15247 k[2] & 0xffffffff, k[3] & 0xffffffff);
15248 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15249 k[0] & 0xffffffff, k[1] & 0xffffffff,
15250 k[2] & 0xffffffff, k[3] & 0xffffffff);
15254 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
15256 REAL_VALUE_TYPE rv;
15259 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15260 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
15264 if (TARGET_MINIMAL_TOC)
15265 fputs (DOUBLE_INT_ASM_OP, file);
15267 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15268 k[0] & 0xffffffff, k[1] & 0xffffffff);
15269 fprintf (file, "0x%lx%08lx\n",
15270 k[0] & 0xffffffff, k[1] & 0xffffffff);
15275 if (TARGET_MINIMAL_TOC)
15276 fputs ("\t.long ", file);
15278 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15279 k[0] & 0xffffffff, k[1] & 0xffffffff);
15280 fprintf (file, "0x%lx,0x%lx\n",
15281 k[0] & 0xffffffff, k[1] & 0xffffffff);
15285 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
15287 REAL_VALUE_TYPE rv;
15290 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15291 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15295 if (TARGET_MINIMAL_TOC)
15296 fputs (DOUBLE_INT_ASM_OP, file);
15298 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15299 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
15304 if (TARGET_MINIMAL_TOC)
15305 fputs ("\t.long ", file);
15307 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15308 fprintf (file, "0x%lx\n", l & 0xffffffff);
15312 else if (GET_MODE (x) == VOIDmode
15313 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
15315 unsigned HOST_WIDE_INT low;
15316 HOST_WIDE_INT high;
15318 if (GET_CODE (x) == CONST_DOUBLE)
15320 low = CONST_DOUBLE_LOW (x);
15321 high = CONST_DOUBLE_HIGH (x);
15324 #if HOST_BITS_PER_WIDE_INT == 32
15327 high = (low & 0x80000000) ? ~0 : 0;
15331 low = INTVAL (x) & 0xffffffff;
15332 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
15336 /* TOC entries are always Pmode-sized, but since this
15337 is a bigendian machine then if we're putting smaller
15338 integer constants in the TOC we have to pad them.
15339 (This is still a win over putting the constants in
15340 a separate constant pool, because then we'd have
15341 to have both a TOC entry _and_ the actual constant.)
15343 For a 32-bit target, CONST_INT values are loaded and shifted
15344 entirely within `low' and can be stored in one TOC entry. */
15346 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
15347 abort ();/* It would be easy to make this work, but it doesn't now. */
15349 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
15351 #if HOST_BITS_PER_WIDE_INT == 32
15352 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15353 POINTER_SIZE, &low, &high, 0);
15356 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
15357 high = (HOST_WIDE_INT) low >> 32;
15364 if (TARGET_MINIMAL_TOC)
15365 fputs (DOUBLE_INT_ASM_OP, file);
15367 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15368 (long) high & 0xffffffff, (long) low & 0xffffffff);
15369 fprintf (file, "0x%lx%08lx\n",
15370 (long) high & 0xffffffff, (long) low & 0xffffffff);
15375 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
15377 if (TARGET_MINIMAL_TOC)
15378 fputs ("\t.long ", file);
15380 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15381 (long) high & 0xffffffff, (long) low & 0xffffffff);
15382 fprintf (file, "0x%lx,0x%lx\n",
15383 (long) high & 0xffffffff, (long) low & 0xffffffff);
15387 if (TARGET_MINIMAL_TOC)
15388 fputs ("\t.long ", file);
15390 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
15391 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
15397 if (GET_CODE (x) == CONST)
15399 if (GET_CODE (XEXP (x, 0)) != PLUS)
15402 base = XEXP (XEXP (x, 0), 0);
15403 offset = INTVAL (XEXP (XEXP (x, 0), 1));
15406 if (GET_CODE (base) == SYMBOL_REF)
15407 name = XSTR (base, 0);
15408 else if (GET_CODE (base) == LABEL_REF)
15409 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
15410 else if (GET_CODE (base) == CODE_LABEL)
15411 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
15415 real_name = (*targetm.strip_name_encoding) (name);
15416 if (TARGET_MINIMAL_TOC)
15417 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
15420 fprintf (file, "\t.tc %s", real_name);
15423 fprintf (file, ".N%d", - offset);
15425 fprintf (file, ".P%d", offset);
15427 fputs ("[TC],", file);
15430 /* Currently C++ toc references to vtables can be emitted before it
15431 is decided whether the vtable is public or private. If this is
15432 the case, then the linker will eventually complain that there is
15433 a TOC reference to an unknown section. Thus, for vtables only,
15434 we emit the TOC reference to reference the symbol and not the
15436 if (VTABLE_NAME_P (name))
15438 RS6000_OUTPUT_BASENAME (file, name);
15440 fprintf (file, "%d", offset);
15441 else if (offset > 0)
15442 fprintf (file, "+%d", offset);
15445 output_addr_const (file, x);
15449 /* Output an assembler pseudo-op to write an ASCII string of N characters
15450 starting at P to FILE.
15452 On the RS/6000, we have to do this using the .byte operation and
15453 write out special characters outside the quoted string.
15454 Also, the assembler is broken; very long strings are truncated,
15455 so we must artificially break them up early. */
15458 output_ascii (FILE *file, const char *p, int n)
15461 int i, count_string;
15462 const char *for_string = "\t.byte \"";
15463 const char *for_decimal = "\t.byte ";
15464 const char *to_close = NULL;
15467 for (i = 0; i < n; i++)
15470 if (c >= ' ' && c < 0177)
15473 fputs (for_string, file);
15476 /* Write two quotes to get one. */
15484 for_decimal = "\"\n\t.byte ";
15488 if (count_string >= 512)
15490 fputs (to_close, file);
15492 for_string = "\t.byte \"";
15493 for_decimal = "\t.byte ";
15501 fputs (for_decimal, file);
15502 fprintf (file, "%d", c);
15504 for_string = "\n\t.byte \"";
15505 for_decimal = ", ";
15511 /* Now close the string if we have written one. Then end the line. */
15513 fputs (to_close, file);
15516 /* Generate a unique section name for FILENAME for a section type
15517 represented by SECTION_DESC. Output goes into BUF.
15519 SECTION_DESC can be any string, as long as it is different for each
15520 possible section type.
15522 We name the section in the same manner as xlc. The name begins with an
15523 underscore followed by the filename (after stripping any leading directory
15524 names) with the last period replaced by the string SECTION_DESC. If
15525 FILENAME does not contain a period, SECTION_DESC is appended to the end of
15529 rs6000_gen_section_name (char **buf, const char *filename,
15530 const char *section_desc)
15532 const char *q, *after_last_slash, *last_period = 0;
15536 after_last_slash = filename;
15537 for (q = filename; *q; q++)
15540 after_last_slash = q + 1;
15541 else if (*q == '.')
15545 len = strlen (after_last_slash) + strlen (section_desc) + 2;
15546 *buf = (char *) xmalloc (len);
15551 for (q = after_last_slash; *q; q++)
15553 if (q == last_period)
15555 strcpy (p, section_desc);
15556 p += strlen (section_desc);
15560 else if (ISALNUM (*q))
15564 if (last_period == 0)
15565 strcpy (p, section_desc);
15570 /* Emit profile function. */
15573 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
15575 if (TARGET_PROFILE_KERNEL)
15578 if (DEFAULT_ABI == ABI_AIX)
15580 #ifndef NO_PROFILE_COUNTERS
15581 # define NO_PROFILE_COUNTERS 0
15583 if (NO_PROFILE_COUNTERS)
15584 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
15588 const char *label_name;
15591 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
15592 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
15593 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
15595 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
15599 else if (DEFAULT_ABI == ABI_DARWIN)
15601 const char *mcount_name = RS6000_MCOUNT;
15602 int caller_addr_regno = LINK_REGISTER_REGNUM;
15604 /* Be conservative and always set this, at least for now. */
15605 current_function_uses_pic_offset_table = 1;
15608 /* For PIC code, set up a stub and collect the caller's address
15609 from r0, which is where the prologue puts it. */
15610 if (MACHOPIC_INDIRECT
15611 && current_function_uses_pic_offset_table)
15612 caller_addr_regno = 0;
15614 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
15616 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
15620 /* Write function profiler code. */
15623 output_function_profiler (FILE *file, int labelno)
15628 switch (DEFAULT_ABI)
15637 warning ("no profiling of 64-bit code for this ABI");
15640 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
15641 fprintf (file, "\tmflr %s\n", reg_names[0]);
15644 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
15645 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15646 reg_names[0], save_lr, reg_names[1]);
15647 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
15648 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
15649 assemble_name (file, buf);
15650 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
15652 else if (flag_pic > 1)
15654 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15655 reg_names[0], save_lr, reg_names[1]);
15656 /* Now, we need to get the address of the label. */
15657 fputs ("\tbl 1f\n\t.long ", file);
15658 assemble_name (file, buf);
15659 fputs ("-.\n1:", file);
15660 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
15661 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
15662 reg_names[0], reg_names[11]);
15663 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
15664 reg_names[0], reg_names[0], reg_names[11]);
15668 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
15669 assemble_name (file, buf);
15670 fputs ("@ha\n", file);
15671 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15672 reg_names[0], save_lr, reg_names[1]);
15673 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
15674 assemble_name (file, buf);
15675 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
15678 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
15679 fprintf (file, "\tbl %s%s\n",
15680 RS6000_MCOUNT, flag_pic ? "@plt" : "");
15685 if (!TARGET_PROFILE_KERNEL)
15687 /* Don't do anything, done in output_profile_hook (). */
15694 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
15695 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
15697 if (cfun->static_chain_decl != NULL)
15699 asm_fprintf (file, "\tstd %s,24(%s)\n",
15700 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
15701 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
15702 asm_fprintf (file, "\tld %s,24(%s)\n",
15703 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
15706 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
15713 /* Power4 load update and store update instructions are cracked into a
15714 load or store and an integer insn which are executed in the same cycle.
15715 Branches have their own dispatch slot which does not count against the
15716 GCC issue rate, but it changes the program flow so there are no other
15717 instructions to issue in this cycle. */
15720 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
15721 int verbose ATTRIBUTE_UNUSED,
15722 rtx insn, int more)
15724 if (GET_CODE (PATTERN (insn)) == USE
15725 || GET_CODE (PATTERN (insn)) == CLOBBER)
15728 if (rs6000_sched_groups)
15730 if (is_microcoded_insn (insn))
15732 else if (is_cracked_insn (insn))
15733 return more > 2 ? more - 2 : 0;
15739 /* Adjust the cost of a scheduling dependency. Return the new cost of
15740 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
15743 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
15745 if (! recog_memoized (insn))
15748 if (REG_NOTE_KIND (link) != 0)
15751 if (REG_NOTE_KIND (link) == 0)
15753 /* Data dependency; DEP_INSN writes a register that INSN reads
15754 some cycles later. */
15756 /* Separate a load from a narrower, dependent store. */
15757 if (rs6000_sched_groups
15758 && GET_CODE (PATTERN (insn)) == SET
15759 && GET_CODE (PATTERN (dep_insn)) == SET
15760 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
15761 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
15762 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
15763 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
15766 switch (get_attr_type (insn))
15769 /* Tell the first scheduling pass about the latency between
15770 a mtctr and bctr (and mtlr and br/blr). The first
15771 scheduling pass will not know about this latency since
15772 the mtctr instruction, which has the latency associated
15773 to it, will be generated by reload. */
15774 return TARGET_POWER ? 5 : 4;
15776 /* Leave some extra cycles between a compare and its
15777 dependent branch, to inhibit expensive mispredicts. */
15778 if ((rs6000_cpu_attr == CPU_PPC603
15779 || rs6000_cpu_attr == CPU_PPC604
15780 || rs6000_cpu_attr == CPU_PPC604E
15781 || rs6000_cpu_attr == CPU_PPC620
15782 || rs6000_cpu_attr == CPU_PPC630
15783 || rs6000_cpu_attr == CPU_PPC750
15784 || rs6000_cpu_attr == CPU_PPC7400
15785 || rs6000_cpu_attr == CPU_PPC7450
15786 || rs6000_cpu_attr == CPU_POWER4
15787 || rs6000_cpu_attr == CPU_POWER5)
15788 && recog_memoized (dep_insn)
15789 && (INSN_CODE (dep_insn) >= 0)
15790 && (get_attr_type (dep_insn) == TYPE_CMP
15791 || get_attr_type (dep_insn) == TYPE_COMPARE
15792 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
15793 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
15794 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
15795 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
15796 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
15797 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
15802 /* Fall out to return default cost. */
15808 /* The function returns a true if INSN is microcoded.
15809 Return false otherwise. */
15812 is_microcoded_insn (rtx insn)
15814 if (!insn || !INSN_P (insn)
15815 || GET_CODE (PATTERN (insn)) == USE
15816 || GET_CODE (PATTERN (insn)) == CLOBBER)
15819 if (rs6000_sched_groups)
15821 enum attr_type type = get_attr_type (insn);
15822 if (type == TYPE_LOAD_EXT_U
15823 || type == TYPE_LOAD_EXT_UX
15824 || type == TYPE_LOAD_UX
15825 || type == TYPE_STORE_UX
15826 || type == TYPE_MFCR)
15833 /* The function returns a nonzero value if INSN can be scheduled only
15834 as the first insn in a dispatch group ("dispatch-slot restricted").
15835 In this case, the returned value indicates how many dispatch slots
15836 the insn occupies (at the beginning of the group).
15837 Return 0 otherwise. */
15840 is_dispatch_slot_restricted (rtx insn)
15842 enum attr_type type;
15844 if (!rs6000_sched_groups)
15848 || insn == NULL_RTX
15849 || GET_CODE (insn) == NOTE
15850 || GET_CODE (PATTERN (insn)) == USE
15851 || GET_CODE (PATTERN (insn)) == CLOBBER)
15854 type = get_attr_type (insn);
15861 case TYPE_DELAYED_CR:
15862 case TYPE_CR_LOGICAL:
15870 if (rs6000_cpu == PROCESSOR_POWER5
15871 && is_cracked_insn (insn))
15877 /* The function returns true if INSN is cracked into 2 instructions
15878 by the processor (and therefore occupies 2 issue slots). */
15881 is_cracked_insn (rtx insn)
15883 if (!insn || !INSN_P (insn)
15884 || GET_CODE (PATTERN (insn)) == USE
15885 || GET_CODE (PATTERN (insn)) == CLOBBER)
15888 if (rs6000_sched_groups)
15890 enum attr_type type = get_attr_type (insn);
15891 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
15892 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
15893 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
15894 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
15895 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
15896 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
15897 || type == TYPE_IDIV || type == TYPE_LDIV
15898 || type == TYPE_INSERT_WORD)
15905 /* The function returns true if INSN can be issued only from
15906 the branch slot. */
15909 is_branch_slot_insn (rtx insn)
15911 if (!insn || !INSN_P (insn)
15912 || GET_CODE (PATTERN (insn)) == USE
15913 || GET_CODE (PATTERN (insn)) == CLOBBER)
15916 if (rs6000_sched_groups)
15918 enum attr_type type = get_attr_type (insn);
15919 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
15927 /* A C statement (sans semicolon) to update the integer scheduling
15928 priority INSN_PRIORITY (INSN). Increase the priority to execute the
15929 INSN earlier, reduce the priority to execute INSN later. Do not
15930 define this macro if you do not need to adjust the scheduling
15931 priorities of insns. */
15934 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
15936 /* On machines (like the 750) which have asymmetric integer units,
15937 where one integer unit can do multiply and divides and the other
15938 can't, reduce the priority of multiply/divide so it is scheduled
15939 before other integer operations. */
15942 if (! INSN_P (insn))
15945 if (GET_CODE (PATTERN (insn)) == USE)
15948 switch (rs6000_cpu_attr) {
15950 switch (get_attr_type (insn))
15957 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
15958 priority, priority);
15959 if (priority >= 0 && priority < 0x01000000)
15966 if (is_dispatch_slot_restricted (insn)
15967 && reload_completed
15968 && current_sched_info->sched_max_insns_priority
15969 && rs6000_sched_restricted_insns_priority)
15972 /* Prioritize insns that can be dispatched only in the first
15974 if (rs6000_sched_restricted_insns_priority == 1)
15975 /* Attach highest priority to insn. This means that in
15976 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
15977 precede 'priority' (critical path) considerations. */
15978 return current_sched_info->sched_max_insns_priority;
15979 else if (rs6000_sched_restricted_insns_priority == 2)
15980 /* Increase priority of insn by a minimal amount. This means that in
15981 haifa-sched.c:ready_sort(), only 'priority' (critical path)
15982 considerations precede dispatch-slot restriction considerations. */
15983 return (priority + 1);
15989 /* Return how many instructions the machine can issue per cycle. */
15992 rs6000_issue_rate (void)
15994 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
15995 if (!reload_completed)
15998 switch (rs6000_cpu_attr) {
15999 case CPU_RIOS1: /* ? */
16001 case CPU_PPC601: /* ? */
16024 /* Return how many instructions to look ahead for better insn
16028 rs6000_use_sched_lookahead (void)
16030 if (rs6000_cpu_attr == CPU_PPC8540)
16035 /* Determine is PAT refers to memory. */
16038 is_mem_ref (rtx pat)
16044 if (GET_CODE (pat) == MEM)
16047 /* Recursively process the pattern. */
16048 fmt = GET_RTX_FORMAT (GET_CODE (pat));
16050 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
16053 ret |= is_mem_ref (XEXP (pat, i));
16054 else if (fmt[i] == 'E')
16055 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
16056 ret |= is_mem_ref (XVECEXP (pat, i, j));
16062 /* Determine if PAT is a PATTERN of a load insn. */
16065 is_load_insn1 (rtx pat)
16067 if (!pat || pat == NULL_RTX)
16070 if (GET_CODE (pat) == SET)
16071 return is_mem_ref (SET_SRC (pat));
16073 if (GET_CODE (pat) == PARALLEL)
16077 for (i = 0; i < XVECLEN (pat, 0); i++)
16078 if (is_load_insn1 (XVECEXP (pat, 0, i)))
16085 /* Determine if INSN loads from memory. */
16088 is_load_insn (rtx insn)
16090 if (!insn || !INSN_P (insn))
16093 if (GET_CODE (insn) == CALL_INSN)
16096 return is_load_insn1 (PATTERN (insn));
16099 /* Determine if PAT is a PATTERN of a store insn. */
16102 is_store_insn1 (rtx pat)
16104 if (!pat || pat == NULL_RTX)
16107 if (GET_CODE (pat) == SET)
16108 return is_mem_ref (SET_DEST (pat));
16110 if (GET_CODE (pat) == PARALLEL)
16114 for (i = 0; i < XVECLEN (pat, 0); i++)
16115 if (is_store_insn1 (XVECEXP (pat, 0, i)))
16122 /* Determine if INSN stores to memory. */
16125 is_store_insn (rtx insn)
16127 if (!insn || !INSN_P (insn))
16130 return is_store_insn1 (PATTERN (insn));
16133 /* Returns whether the dependence between INSN and NEXT is considered
16134 costly by the given target. */
16137 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
16140 /* If the flag is not enbled - no dependence is considered costly;
16141 allow all dependent insns in the same group.
16142 This is the most aggressive option. */
16143 if (rs6000_sched_costly_dep == no_dep_costly)
16146 /* If the flag is set to 1 - a dependence is always considered costly;
16147 do not allow dependent instructions in the same group.
16148 This is the most conservative option. */
16149 if (rs6000_sched_costly_dep == all_deps_costly)
16152 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16153 && is_load_insn (next)
16154 && is_store_insn (insn))
16155 /* Prevent load after store in the same group. */
16158 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16159 && is_load_insn (next)
16160 && is_store_insn (insn)
16161 && (!link || (int) REG_NOTE_KIND (link) == 0))
16162 /* Prevent load after store in the same group if it is a true
16166 /* The flag is set to X; dependences with latency >= X are considered costly,
16167 and will not be scheduled in the same group. */
16168 if (rs6000_sched_costly_dep <= max_dep_latency
16169 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16175 /* Return the next insn after INSN that is found before TAIL is reached,
16176 skipping any "non-active" insns - insns that will not actually occupy
16177 an issue slot. Return NULL_RTX if such an insn is not found. */
16180 get_next_active_insn (rtx insn, rtx tail)
16184 if (!insn || insn == tail)
16187 next_insn = NEXT_INSN (insn);
16190 && next_insn != tail
16191 && (GET_CODE(next_insn) == NOTE
16192 || GET_CODE (PATTERN (next_insn)) == USE
16193 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
16195 next_insn = NEXT_INSN (next_insn);
16198 if (!next_insn || next_insn == tail)
16204 /* Return whether the presence of INSN causes a dispatch group termination
16205 of group WHICH_GROUP.
16207 If WHICH_GROUP == current_group, this function will return true if INSN
16208 causes the termination of the current group (i.e, the dispatch group to
16209 which INSN belongs). This means that INSN will be the last insn in the
16210 group it belongs to.
16212 If WHICH_GROUP == previous_group, this function will return true if INSN
16213 causes the termination of the previous group (i.e, the dispatch group that
16214 precedes the group to which INSN belongs). This means that INSN will be
16215 the first insn in the group it belongs to). */
16218 insn_terminates_group_p (rtx insn, enum group_termination which_group)
16220 enum attr_type type;
16225 type = get_attr_type (insn);
16227 if (is_microcoded_insn (insn))
16230 if (which_group == current_group)
16232 if (is_branch_slot_insn (insn))
16236 else if (which_group == previous_group)
16238 if (is_dispatch_slot_restricted (insn))
16246 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16247 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16250 is_costly_group (rtx *group_insns, rtx next_insn)
16255 int issue_rate = rs6000_issue_rate ();
16257 for (i = 0; i < issue_rate; i++)
16259 rtx insn = group_insns[i];
16262 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
16264 rtx next = XEXP (link, 0);
16265 if (next == next_insn)
16267 cost = insn_cost (insn, link, next_insn);
16268 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
16277 /* Utility of the function redefine_groups.
16278 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16279 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16280 to keep it "far" (in a separate group) from GROUP_INSNS, following
16281 one of the following schemes, depending on the value of the flag
16282 -minsert_sched_nops = X:
16283 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16284 in order to force NEXT_INSN into a separate group.
16285 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16286 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16287 insertion (has a group just ended, how many vacant issue slots remain in the
16288 last group, and how many dispatch groups were encountered so far). */
16291 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
16292 rtx next_insn, bool *group_end, int can_issue_more,
16297 int issue_rate = rs6000_issue_rate ();
16298 bool end = *group_end;
16301 if (next_insn == NULL_RTX)
16302 return can_issue_more;
16304 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
16305 return can_issue_more;
16307 force = is_costly_group (group_insns, next_insn);
16309 return can_issue_more;
16311 if (sched_verbose > 6)
16312 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
16313 *group_count ,can_issue_more);
16315 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
16318 can_issue_more = 0;
16320 /* Since only a branch can be issued in the last issue_slot, it is
16321 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16322 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16323 in this case the last nop will start a new group and the branch
16324 will be forced to the new group. */
16325 if (can_issue_more && !is_branch_slot_insn (next_insn))
16328 while (can_issue_more > 0)
16331 emit_insn_before (nop, next_insn);
16339 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
16341 int n_nops = rs6000_sched_insert_nops;
16343 /* Nops can't be issued from the branch slot, so the effective
16344 issue_rate for nops is 'issue_rate - 1'. */
16345 if (can_issue_more == 0)
16346 can_issue_more = issue_rate;
16348 if (can_issue_more == 0)
16350 can_issue_more = issue_rate - 1;
16353 for (i = 0; i < issue_rate; i++)
16355 group_insns[i] = 0;
16362 emit_insn_before (nop, next_insn);
16363 if (can_issue_more == issue_rate - 1) /* new group begins */
16366 if (can_issue_more == 0)
16368 can_issue_more = issue_rate - 1;
16371 for (i = 0; i < issue_rate; i++)
16373 group_insns[i] = 0;
16379 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
16382 /* Is next_insn going to start a new group? */
16385 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16386 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16387 || (can_issue_more < issue_rate &&
16388 insn_terminates_group_p (next_insn, previous_group)));
16389 if (*group_end && end)
16392 if (sched_verbose > 6)
16393 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
16394 *group_count, can_issue_more);
16395 return can_issue_more;
16398 return can_issue_more;
16401 /* This function tries to synch the dispatch groups that the compiler "sees"
16402 with the dispatch groups that the processor dispatcher is expected to
16403 form in practice. It tries to achieve this synchronization by forcing the
16404 estimated processor grouping on the compiler (as opposed to the function
16405 'pad_goups' which tries to force the scheduler's grouping on the processor).
16407 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
16408 examines the (estimated) dispatch groups that will be formed by the processor
16409 dispatcher. It marks these group boundaries to reflect the estimated
16410 processor grouping, overriding the grouping that the scheduler had marked.
16411 Depending on the value of the flag '-minsert-sched-nops' this function can
16412 force certain insns into separate groups or force a certain distance between
16413 them by inserting nops, for example, if there exists a "costly dependence"
16416 The function estimates the group boundaries that the processor will form as
16417 folllows: It keeps track of how many vacant issue slots are available after
16418 each insn. A subsequent insn will start a new group if one of the following
16420 - no more vacant issue slots remain in the current dispatch group.
16421 - only the last issue slot, which is the branch slot, is vacant, but the next
16422 insn is not a branch.
16423 - only the last 2 or less issue slots, including the branch slot, are vacant,
16424 which means that a cracked insn (which occupies two issue slots) can't be
16425 issued in this group.
16426 - less than 'issue_rate' slots are vacant, and the next insn always needs to
16427 start a new group. */
16430 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16432 rtx insn, next_insn;
16434 int can_issue_more;
16437 int group_count = 0;
16441 issue_rate = rs6000_issue_rate ();
16442 group_insns = alloca (issue_rate * sizeof (rtx));
16443 for (i = 0; i < issue_rate; i++)
16445 group_insns[i] = 0;
16447 can_issue_more = issue_rate;
16449 insn = get_next_active_insn (prev_head_insn, tail);
16452 while (insn != NULL_RTX)
16454 slot = (issue_rate - can_issue_more);
16455 group_insns[slot] = insn;
16457 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16458 if (insn_terminates_group_p (insn, current_group))
16459 can_issue_more = 0;
16461 next_insn = get_next_active_insn (insn, tail);
16462 if (next_insn == NULL_RTX)
16463 return group_count + 1;
16465 /* Is next_insn going to start a new group? */
16467 = (can_issue_more == 0
16468 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16469 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16470 || (can_issue_more < issue_rate &&
16471 insn_terminates_group_p (next_insn, previous_group)));
16473 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
16474 next_insn, &group_end, can_issue_more,
16480 can_issue_more = 0;
16481 for (i = 0; i < issue_rate; i++)
16483 group_insns[i] = 0;
16487 if (GET_MODE (next_insn) == TImode && can_issue_more)
16488 PUT_MODE(next_insn, VOIDmode);
16489 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
16490 PUT_MODE (next_insn, TImode);
16493 if (can_issue_more == 0)
16494 can_issue_more = issue_rate;
16497 return group_count;
16500 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
16501 dispatch group boundaries that the scheduler had marked. Pad with nops
16502 any dispatch groups which have vacant issue slots, in order to force the
16503 scheduler's grouping on the processor dispatcher. The function
16504 returns the number of dispatch groups found. */
16507 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16509 rtx insn, next_insn;
16512 int can_issue_more;
16514 int group_count = 0;
16516 /* Initialize issue_rate. */
16517 issue_rate = rs6000_issue_rate ();
16518 can_issue_more = issue_rate;
16520 insn = get_next_active_insn (prev_head_insn, tail);
16521 next_insn = get_next_active_insn (insn, tail);
16523 while (insn != NULL_RTX)
16526 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16528 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
16530 if (next_insn == NULL_RTX)
16535 /* If the scheduler had marked group termination at this location
16536 (between insn and next_indn), and neither insn nor next_insn will
16537 force group termination, pad the group with nops to force group
16540 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
16541 && !insn_terminates_group_p (insn, current_group)
16542 && !insn_terminates_group_p (next_insn, previous_group))
16544 if (!is_branch_slot_insn(next_insn))
16547 while (can_issue_more)
16550 emit_insn_before (nop, next_insn);
16555 can_issue_more = issue_rate;
16560 next_insn = get_next_active_insn (insn, tail);
16563 return group_count;
16566 /* The following function is called at the end of scheduling BB.
16567 After reload, it inserts nops at insn group bundling. */
16570 rs6000_sched_finish (FILE *dump, int sched_verbose)
16575 fprintf (dump, "=== Finishing schedule.\n");
16577 if (reload_completed && rs6000_sched_groups)
16579 if (rs6000_sched_insert_nops == sched_finish_none)
16582 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
16583 n_groups = pad_groups (dump, sched_verbose,
16584 current_sched_info->prev_head,
16585 current_sched_info->next_tail);
16587 n_groups = redefine_groups (dump, sched_verbose,
16588 current_sched_info->prev_head,
16589 current_sched_info->next_tail);
16591 if (sched_verbose >= 6)
16593 fprintf (dump, "ngroups = %d\n", n_groups);
16594 print_rtl (dump, current_sched_info->prev_head);
16595 fprintf (dump, "Done finish_sched\n");
16600 /* Length in units of the trampoline for entering a nested function. */
16603 rs6000_trampoline_size (void)
16607 switch (DEFAULT_ABI)
16613 ret = (TARGET_32BIT) ? 12 : 24;
16618 ret = (TARGET_32BIT) ? 40 : 48;
16625 /* Emit RTL insns to initialize the variable parts of a trampoline.
16626 FNADDR is an RTX for the address of the function's pure code.
16627 CXT is an RTX for the static chain value for the function. */
16630 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
16632 enum machine_mode pmode = Pmode;
16633 int regsize = (TARGET_32BIT) ? 4 : 8;
16634 rtx ctx_reg = force_reg (pmode, cxt);
16636 switch (DEFAULT_ABI)
16641 /* Macros to shorten the code expansions below. */
16642 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
16643 #define MEM_PLUS(addr,offset) \
16644 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
16646 /* Under AIX, just build the 3 word function descriptor */
16649 rtx fn_reg = gen_reg_rtx (pmode);
16650 rtx toc_reg = gen_reg_rtx (pmode);
16651 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
16652 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
16653 emit_move_insn (MEM_DEREF (addr), fn_reg);
16654 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
16655 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
16659 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
16662 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
16663 FALSE, VOIDmode, 4,
16665 GEN_INT (rs6000_trampoline_size ()), SImode,
16675 /* Table of valid machine attributes. */
16677 const struct attribute_spec rs6000_attribute_table[] =
16679 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
16680 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
16681 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
16682 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
16683 #ifdef SUBTARGET_ATTRIBUTE_TABLE
16684 SUBTARGET_ATTRIBUTE_TABLE,
16686 { NULL, 0, 0, false, false, false, NULL }
16689 /* Handle the "altivec" attribute. The attribute may have
16690 arguments as follows:
16692 __attribute__((altivec(vector__)))
16693 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
16694 __attribute__((altivec(bool__))) (always followed by 'unsigned')
16696 and may appear more than once (e.g., 'vector bool char') in a
16697 given declaration. */
16700 rs6000_handle_altivec_attribute (tree *node, tree name, tree args,
16701 int flags ATTRIBUTE_UNUSED,
16702 bool *no_add_attrs)
16704 tree type = *node, result = NULL_TREE;
16705 enum machine_mode mode;
16708 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
16709 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
16710 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
16713 while (POINTER_TYPE_P (type)
16714 || TREE_CODE (type) == FUNCTION_TYPE
16715 || TREE_CODE (type) == METHOD_TYPE
16716 || TREE_CODE (type) == ARRAY_TYPE)
16717 type = TREE_TYPE (type);
16719 mode = TYPE_MODE (type);
16721 if (rs6000_warn_altivec_long
16722 && (type == long_unsigned_type_node || type == long_integer_type_node))
16723 warning ("use of 'long' in AltiVec types is deprecated; use 'int'");
16725 switch (altivec_type)
16728 unsigned_p = TYPE_UNSIGNED (type);
16732 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
16735 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
16738 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
16740 case SFmode: result = V4SF_type_node; break;
16741 /* If the user says 'vector int bool', we may be handed the 'bool'
16742 attribute _before_ the 'vector' attribute, and so select the
16743 proper type in the 'b' case below. */
16744 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
16752 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
16753 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
16754 case QImode: case V16QImode: result = bool_V16QI_type_node;
16761 case V8HImode: result = pixel_V8HI_type_node;
16767 if (result && result != type && TYPE_READONLY (type))
16768 result = build_qualified_type (result, TYPE_QUAL_CONST);
16770 *no_add_attrs = true; /* No need to hang on to the attribute. */
16773 warning ("%qs attribute ignored", IDENTIFIER_POINTER (name));
16775 *node = reconstruct_complex_type (*node, result);
16780 /* AltiVec defines four built-in scalar types that serve as vector
16781 elements; we must teach the compiler how to mangle them. */
16783 static const char *
16784 rs6000_mangle_fundamental_type (tree type)
16786 if (type == bool_char_type_node) return "U6__boolc";
16787 if (type == bool_short_type_node) return "U6__bools";
16788 if (type == pixel_type_node) return "u7__pixel";
16789 if (type == bool_int_type_node) return "U6__booli";
16791 /* For all other types, use normal C++ mangling. */
16795 /* Handle a "longcall" or "shortcall" attribute; arguments as in
16796 struct attribute_spec.handler. */
16799 rs6000_handle_longcall_attribute (tree *node, tree name,
16800 tree args ATTRIBUTE_UNUSED,
16801 int flags ATTRIBUTE_UNUSED,
16802 bool *no_add_attrs)
16804 if (TREE_CODE (*node) != FUNCTION_TYPE
16805 && TREE_CODE (*node) != FIELD_DECL
16806 && TREE_CODE (*node) != TYPE_DECL)
16808 warning ("%qs attribute only applies to functions",
16809 IDENTIFIER_POINTER (name));
16810 *no_add_attrs = true;
16816 /* Set longcall attributes on all functions declared when
16817 rs6000_default_long_calls is true. */
16819 rs6000_set_default_type_attributes (tree type)
16821 if (rs6000_default_long_calls
16822 && (TREE_CODE (type) == FUNCTION_TYPE
16823 || TREE_CODE (type) == METHOD_TYPE))
16824 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
16826 TYPE_ATTRIBUTES (type));
16829 /* Return a reference suitable for calling a function with the
16830 longcall attribute. */
16833 rs6000_longcall_ref (rtx call_ref)
16835 const char *call_name;
16838 if (GET_CODE (call_ref) != SYMBOL_REF)
16841 /* System V adds '.' to the internal name, so skip them. */
16842 call_name = XSTR (call_ref, 0);
16843 if (*call_name == '.')
16845 while (*call_name == '.')
16848 node = get_identifier (call_name);
16849 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
16852 return force_reg (Pmode, call_ref);
16855 #ifdef USING_ELFOS_H
16857 /* A C statement or statements to switch to the appropriate section
16858 for output of RTX in mode MODE. You can assume that RTX is some
16859 kind of constant in RTL. The argument MODE is redundant except in
16860 the case of a `const_int' rtx. Select the section by calling
16861 `text_section' or one of the alternatives for other sections.
16863 Do not define this macro if you put all constants in the read-only
16867 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
16868 unsigned HOST_WIDE_INT align)
16870 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
16873 default_elf_select_rtx_section (mode, x, align);
16876 /* A C statement or statements to switch to the appropriate
16877 section for output of DECL. DECL is either a `VAR_DECL' node
16878 or a constant of some sort. RELOC indicates whether forming
16879 the initial value of DECL requires link-time relocations. */
16882 rs6000_elf_select_section (tree decl, int reloc,
16883 unsigned HOST_WIDE_INT align)
16885 /* Pretend that we're always building for a shared library when
16886 ABI_AIX, because otherwise we end up with dynamic relocations
16887 in read-only sections. This happens for function pointers,
16888 references to vtables in typeinfo, and probably other cases. */
16889 default_elf_select_section_1 (decl, reloc, align,
16890 flag_pic || DEFAULT_ABI == ABI_AIX);
16893 /* A C statement to build up a unique section name, expressed as a
16894 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
16895 RELOC indicates whether the initial value of EXP requires
16896 link-time relocations. If you do not define this macro, GCC will use
16897 the symbol name prefixed by `.' as the section name. Note - this
16898 macro can now be called for uninitialized data items as well as
16899 initialized data and functions. */
16902 rs6000_elf_unique_section (tree decl, int reloc)
16904 /* As above, pretend that we're always building for a shared library
16905 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
16906 default_unique_section_1 (decl, reloc,
16907 flag_pic || DEFAULT_ABI == ABI_AIX);
16910 /* For a SYMBOL_REF, set generic flags and then perform some
16911 target-specific processing.
16913 When the AIX ABI is requested on a non-AIX system, replace the
16914 function name with the real name (with a leading .) rather than the
16915 function descriptor name. This saves a lot of overriding code to
16916 read the prefixes. */
16919 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
16921 default_encode_section_info (decl, rtl, first);
16924 && TREE_CODE (decl) == FUNCTION_DECL
16926 && DEFAULT_ABI == ABI_AIX)
16928 rtx sym_ref = XEXP (rtl, 0);
16929 size_t len = strlen (XSTR (sym_ref, 0));
16930 char *str = alloca (len + 2);
16932 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
16933 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
16938 rs6000_elf_in_small_data_p (tree decl)
16940 if (rs6000_sdata == SDATA_NONE)
16943 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
16945 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
16946 if (strcmp (section, ".sdata") == 0
16947 || strcmp (section, ".sdata2") == 0
16948 || strcmp (section, ".sbss") == 0
16949 || strcmp (section, ".sbss2") == 0
16950 || strcmp (section, ".PPC.EMB.sdata0") == 0
16951 || strcmp (section, ".PPC.EMB.sbss0") == 0)
16956 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
16959 && (unsigned HOST_WIDE_INT) size <= g_switch_value
16960 /* If it's not public, and we're not going to reference it there,
16961 there's no need to put it in the small data section. */
16962 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
16969 #endif /* USING_ELFOS_H */
16972 /* Return a REG that occurs in ADDR with coefficient 1.
16973 ADDR can be effectively incremented by incrementing REG.
16975 r0 is special and we must not select it as an address
16976 register by this routine since our caller will try to
16977 increment the returned register via an "la" instruction. */
16980 find_addr_reg (rtx addr)
16982 while (GET_CODE (addr) == PLUS)
16984 if (GET_CODE (XEXP (addr, 0)) == REG
16985 && REGNO (XEXP (addr, 0)) != 0)
16986 addr = XEXP (addr, 0);
16987 else if (GET_CODE (XEXP (addr, 1)) == REG
16988 && REGNO (XEXP (addr, 1)) != 0)
16989 addr = XEXP (addr, 1);
16990 else if (CONSTANT_P (XEXP (addr, 0)))
16991 addr = XEXP (addr, 1);
16992 else if (CONSTANT_P (XEXP (addr, 1)))
16993 addr = XEXP (addr, 0);
16997 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
17003 rs6000_fatal_bad_address (rtx op)
17005 fatal_insn ("bad address", op);
17010 static tree branch_island_list = 0;
17012 /* Remember to generate a branch island for far calls to the given
17016 add_compiler_branch_island (tree label_name, tree function_name,
17019 tree branch_island = build_tree_list (function_name, label_name);
17020 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
17021 TREE_CHAIN (branch_island) = branch_island_list;
17022 branch_island_list = branch_island;
17025 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17026 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17027 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17028 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17030 /* Generate far-jump branch islands for everything on the
17031 branch_island_list. Invoked immediately after the last instruction
17032 of the epilogue has been emitted; the branch-islands must be
17033 appended to, and contiguous with, the function body. Mach-O stubs
17034 are generated in machopic_output_stub(). */
17037 macho_branch_islands (void)
17040 tree branch_island;
17042 for (branch_island = branch_island_list;
17044 branch_island = TREE_CHAIN (branch_island))
17046 const char *label =
17047 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
17049 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
17050 char name_buf[512];
17051 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17052 if (name[0] == '*' || name[0] == '&')
17053 strcpy (name_buf, name+1);
17057 strcpy (name_buf+1, name);
17059 strcpy (tmp_buf, "\n");
17060 strcat (tmp_buf, label);
17061 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17062 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17063 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17064 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17067 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
17068 strcat (tmp_buf, label);
17069 strcat (tmp_buf, "_pic\n");
17070 strcat (tmp_buf, label);
17071 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
17073 strcat (tmp_buf, "\taddis r11,r11,ha16(");
17074 strcat (tmp_buf, name_buf);
17075 strcat (tmp_buf, " - ");
17076 strcat (tmp_buf, label);
17077 strcat (tmp_buf, "_pic)\n");
17079 strcat (tmp_buf, "\tmtlr r0\n");
17081 strcat (tmp_buf, "\taddi r12,r11,lo16(");
17082 strcat (tmp_buf, name_buf);
17083 strcat (tmp_buf, " - ");
17084 strcat (tmp_buf, label);
17085 strcat (tmp_buf, "_pic)\n");
17087 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
17091 strcat (tmp_buf, ":\nlis r12,hi16(");
17092 strcat (tmp_buf, name_buf);
17093 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
17094 strcat (tmp_buf, name_buf);
17095 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
17097 output_asm_insn (tmp_buf, 0);
17098 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17099 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17100 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17101 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17104 branch_island_list = 0;
17107 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17108 already there or not. */
17111 no_previous_def (tree function_name)
17113 tree branch_island;
17114 for (branch_island = branch_island_list;
17116 branch_island = TREE_CHAIN (branch_island))
17117 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17122 /* GET_PREV_LABEL gets the label name from the previous definition of
17126 get_prev_label (tree function_name)
17128 tree branch_island;
17129 for (branch_island = branch_island_list;
17131 branch_island = TREE_CHAIN (branch_island))
17132 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17133 return BRANCH_ISLAND_LABEL_NAME (branch_island);
17137 /* INSN is either a function call or a millicode call. It may have an
17138 unconditional jump in its delay slot.
17140 CALL_DEST is the routine we are calling. */
17143 output_call (rtx insn, rtx *operands, int dest_operand_number,
17144 int cookie_operand_number)
17146 static char buf[256];
17147 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
17148 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
17151 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
17153 if (no_previous_def (funname))
17155 int line_number = 0;
17156 rtx label_rtx = gen_label_rtx ();
17157 char *label_buf, temp_buf[256];
17158 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
17159 CODE_LABEL_NUMBER (label_rtx));
17160 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
17161 labelname = get_identifier (label_buf);
17162 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
17164 line_number = NOTE_LINE_NUMBER (insn);
17165 add_compiler_branch_island (labelname, funname, line_number);
17168 labelname = get_prev_label (funname);
17170 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17171 instruction will reach 'foo', otherwise link as 'bl L42'".
17172 "L42" should be a 'branch island', that will do a far jump to
17173 'foo'. Branch islands are generated in
17174 macho_branch_islands(). */
17175 sprintf (buf, "jbsr %%z%d,%.246s",
17176 dest_operand_number, IDENTIFIER_POINTER (labelname));
17179 sprintf (buf, "bl %%z%d", dest_operand_number);
17183 /* Generate PIC and indirect symbol stubs. */
17186 machopic_output_stub (FILE *file, const char *symb, const char *stub)
17188 unsigned int length;
17189 char *symbol_name, *lazy_ptr_name;
17190 char *local_label_0;
17191 static int label = 0;
17193 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17194 symb = (*targetm.strip_name_encoding) (symb);
17197 length = strlen (symb);
17198 symbol_name = alloca (length + 32);
17199 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17201 lazy_ptr_name = alloca (length + 32);
17202 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
17205 machopic_picsymbol_stub1_section ();
17207 machopic_symbol_stub1_section ();
17211 fprintf (file, "\t.align 5\n");
17213 fprintf (file, "%s:\n", stub);
17214 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17217 local_label_0 = alloca (sizeof("\"L0000000000$spb\""));
17218 sprintf (local_label_0, "\"L%011d$spb\"", label);
17220 fprintf (file, "\tmflr r0\n");
17221 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
17222 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
17223 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
17224 lazy_ptr_name, local_label_0);
17225 fprintf (file, "\tmtlr r0\n");
17226 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
17227 (TARGET_64BIT ? "ldu" : "lwzu"),
17228 lazy_ptr_name, local_label_0);
17229 fprintf (file, "\tmtctr r12\n");
17230 fprintf (file, "\tbctr\n");
17234 fprintf (file, "\t.align 4\n");
17236 fprintf (file, "%s:\n", stub);
17237 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17239 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
17240 fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name);
17241 fprintf (file, "\tmtctr r12\n");
17242 fprintf (file, "\tbctr\n");
17245 machopic_lazy_symbol_ptr_section ();
17246 fprintf (file, "%s:\n", lazy_ptr_name);
17247 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17248 fprintf (file, "%sdyld_stub_binding_helper\n",
17249 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
17252 /* Legitimize PIC addresses. If the address is already
17253 position-independent, we return ORIG. Newly generated
17254 position-independent addresses go into a reg. This is REG if non
17255 zero, otherwise we allocate register(s) as necessary. */
17257 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
17260 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
17265 if (reg == NULL && ! reload_in_progress && ! reload_completed)
17266 reg = gen_reg_rtx (Pmode);
17268 if (GET_CODE (orig) == CONST)
17270 if (GET_CODE (XEXP (orig, 0)) == PLUS
17271 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
17274 if (GET_CODE (XEXP (orig, 0)) == PLUS)
17276 /* Use a different reg for the intermediate value, as
17277 it will be marked UNCHANGING. */
17278 rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
17281 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
17284 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
17290 if (GET_CODE (offset) == CONST_INT)
17292 if (SMALL_INT (offset))
17293 return plus_constant (base, INTVAL (offset));
17294 else if (! reload_in_progress && ! reload_completed)
17295 offset = force_reg (Pmode, offset);
17298 rtx mem = force_const_mem (Pmode, orig);
17299 return machopic_legitimize_pic_address (mem, Pmode, reg);
17302 return gen_rtx_PLUS (Pmode, base, offset);
17305 /* Fall back on generic machopic code. */
17306 return machopic_legitimize_pic_address (orig, mode, reg);
17309 /* This is just a placeholder to make linking work without having to
17310 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
17311 ever needed for Darwin (not too likely!) this would have to get a
17312 real definition. */
17319 /* Output a .machine directive for the Darwin assembler, and call
17320 the generic start_file routine. */
17323 rs6000_darwin_file_start (void)
17325 static const struct
17331 { "ppc64", "ppc64", MASK_64BIT },
17332 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
17333 { "power4", "ppc970", 0 },
17334 { "G5", "ppc970", 0 },
17335 { "7450", "ppc7450", 0 },
17336 { "7400", "ppc7400", MASK_ALTIVEC },
17337 { "G4", "ppc7400", 0 },
17338 { "750", "ppc750", 0 },
17339 { "740", "ppc750", 0 },
17340 { "G3", "ppc750", 0 },
17341 { "604e", "ppc604e", 0 },
17342 { "604", "ppc604", 0 },
17343 { "603e", "ppc603", 0 },
17344 { "603", "ppc603", 0 },
17345 { "601", "ppc601", 0 },
17346 { NULL, "ppc", 0 } };
17347 const char *cpu_id = "";
17350 rs6000_file_start();
17352 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
17353 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
17354 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
17355 && rs6000_select[i].string[0] != '\0')
17356 cpu_id = rs6000_select[i].string;
17358 /* Look through the mapping array. Pick the first name that either
17359 matches the argument, has a bit set in IF_SET that is also set
17360 in the target flags, or has a NULL name. */
17363 while (mapping[i].arg != NULL
17364 && strcmp (mapping[i].arg, cpu_id) != 0
17365 && (mapping[i].if_set & target_flags) == 0)
17368 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
17371 #endif /* TARGET_MACHO */
17374 static unsigned int
17375 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
17377 return default_section_type_flags_1 (decl, name, reloc,
17378 flag_pic || DEFAULT_ABI == ABI_AIX);
17381 /* Record an element in the table of global constructors. SYMBOL is
17382 a SYMBOL_REF of the function to be called; PRIORITY is a number
17383 between 0 and MAX_INIT_PRIORITY.
17385 This differs from default_named_section_asm_out_constructor in
17386 that we have special handling for -mrelocatable. */
17389 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
17391 const char *section = ".ctors";
17394 if (priority != DEFAULT_INIT_PRIORITY)
17396 sprintf (buf, ".ctors.%.5u",
17397 /* Invert the numbering so the linker puts us in the proper
17398 order; constructors are run from right to left, and the
17399 linker sorts in increasing order. */
17400 MAX_INIT_PRIORITY - priority);
17404 named_section_flags (section, SECTION_WRITE);
17405 assemble_align (POINTER_SIZE);
17407 if (TARGET_RELOCATABLE)
17409 fputs ("\t.long (", asm_out_file);
17410 output_addr_const (asm_out_file, symbol);
17411 fputs (")@fixup\n", asm_out_file);
17414 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17418 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
17420 const char *section = ".dtors";
17423 if (priority != DEFAULT_INIT_PRIORITY)
17425 sprintf (buf, ".dtors.%.5u",
17426 /* Invert the numbering so the linker puts us in the proper
17427 order; constructors are run from right to left, and the
17428 linker sorts in increasing order. */
17429 MAX_INIT_PRIORITY - priority);
17433 named_section_flags (section, SECTION_WRITE);
17434 assemble_align (POINTER_SIZE);
17436 if (TARGET_RELOCATABLE)
17438 fputs ("\t.long (", asm_out_file);
17439 output_addr_const (asm_out_file, symbol);
17440 fputs (")@fixup\n", asm_out_file);
17443 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17447 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
17451 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
17452 ASM_OUTPUT_LABEL (file, name);
17453 fputs (DOUBLE_INT_ASM_OP, file);
17454 rs6000_output_function_entry (file, name);
17455 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
17458 fputs ("\t.size\t", file);
17459 assemble_name (file, name);
17460 fputs (",24\n\t.type\t.", file);
17461 assemble_name (file, name);
17462 fputs (",@function\n", file);
17463 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
17465 fputs ("\t.globl\t.", file);
17466 assemble_name (file, name);
17471 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17472 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17473 rs6000_output_function_entry (file, name);
17474 fputs (":\n", file);
17478 if (TARGET_RELOCATABLE
17479 && (get_pool_size () != 0 || current_function_profile)
17484 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
17486 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
17487 fprintf (file, "\t.long ");
17488 assemble_name (file, buf);
17490 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
17491 assemble_name (file, buf);
17495 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17496 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17498 if (DEFAULT_ABI == ABI_AIX)
17500 const char *desc_name, *orig_name;
17502 orig_name = (*targetm.strip_name_encoding) (name);
17503 desc_name = orig_name;
17504 while (*desc_name == '.')
17507 if (TREE_PUBLIC (decl))
17508 fprintf (file, "\t.globl %s\n", desc_name);
17510 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17511 fprintf (file, "%s:\n", desc_name);
17512 fprintf (file, "\t.long %s\n", orig_name);
17513 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
17514 if (DEFAULT_ABI == ABI_AIX)
17515 fputs ("\t.long 0\n", file);
17516 fprintf (file, "\t.previous\n");
17518 ASM_OUTPUT_LABEL (file, name);
17524 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
17526 fputs (GLOBAL_ASM_OP, stream);
17527 RS6000_OUTPUT_BASENAME (stream, name);
17528 putc ('\n', stream);
17532 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
17533 tree decl ATTRIBUTE_UNUSED)
17536 static const char * const suffix[3] = { "PR", "RO", "RW" };
17538 if (flags & SECTION_CODE)
17540 else if (flags & SECTION_WRITE)
17545 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
17546 (flags & SECTION_CODE) ? "." : "",
17547 name, suffix[smclass], flags & SECTION_ENTSIZE);
17551 rs6000_xcoff_select_section (tree decl, int reloc,
17552 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
17554 if (decl_readonly_section_1 (decl, reloc, 1))
17556 if (TREE_PUBLIC (decl))
17557 read_only_data_section ();
17559 read_only_private_data_section ();
17563 if (TREE_PUBLIC (decl))
17566 private_data_section ();
17571 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
17575 /* Use select_section for private and uninitialized data. */
17576 if (!TREE_PUBLIC (decl)
17577 || DECL_COMMON (decl)
17578 || DECL_INITIAL (decl) == NULL_TREE
17579 || DECL_INITIAL (decl) == error_mark_node
17580 || (flag_zero_initialized_in_bss
17581 && initializer_zerop (DECL_INITIAL (decl))))
17584 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
17585 name = (*targetm.strip_name_encoding) (name);
17586 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
17589 /* Select section for constant in constant pool.
17591 On RS/6000, all constants are in the private read-only data area.
17592 However, if this is being placed in the TOC it must be output as a
17596 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
17597 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
17599 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17602 read_only_private_data_section ();
17605 /* Remove any trailing [DS] or the like from the symbol name. */
17607 static const char *
17608 rs6000_xcoff_strip_name_encoding (const char *name)
17613 len = strlen (name);
17614 if (name[len - 1] == ']')
17615 return ggc_alloc_string (name, len - 4);
17620 /* Section attributes. AIX is always PIC. */
17622 static unsigned int
17623 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
17625 unsigned int align;
17626 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
17628 /* Align to at least UNIT size. */
17629 if (flags & SECTION_CODE)
17630 align = MIN_UNITS_PER_WORD;
17632 /* Increase alignment of large objects if not already stricter. */
17633 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
17634 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
17635 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
17637 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
17640 /* Output at beginning of assembler file.
17642 Initialize the section names for the RS/6000 at this point.
17644 Specify filename, including full path, to assembler.
17646 We want to go into the TOC section so at least one .toc will be emitted.
17647 Also, in order to output proper .bs/.es pairs, we need at least one static
17648 [RW] section emitted.
17650 Finally, declare mcount when profiling to make the assembler happy. */
17653 rs6000_xcoff_file_start (void)
17655 rs6000_gen_section_name (&xcoff_bss_section_name,
17656 main_input_filename, ".bss_");
17657 rs6000_gen_section_name (&xcoff_private_data_section_name,
17658 main_input_filename, ".rw_");
17659 rs6000_gen_section_name (&xcoff_read_only_section_name,
17660 main_input_filename, ".ro_");
17662 fputs ("\t.file\t", asm_out_file);
17663 output_quoted_string (asm_out_file, main_input_filename);
17664 fputc ('\n', asm_out_file);
17666 if (write_symbols != NO_DEBUG)
17667 private_data_section ();
17670 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
17671 rs6000_file_start ();
17674 /* Output at end of assembler file.
17675 On the RS/6000, referencing data should automatically pull in text. */
17678 rs6000_xcoff_file_end (void)
17681 fputs ("_section_.text:\n", asm_out_file);
17683 fputs (TARGET_32BIT
17684 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
17687 #endif /* TARGET_XCOFF */
17690 /* Cross-module name binding. Darwin does not support overriding
17691 functions at dynamic-link time. */
17694 rs6000_binds_local_p (tree decl)
17696 return default_binds_local_p_1 (decl, 0);
17700 /* Compute a (partial) cost for rtx X. Return true if the complete
17701 cost has been computed, and false if subexpressions should be
17702 scanned. In either case, *TOTAL contains the cost result. */
17705 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
17707 enum machine_mode mode = GET_MODE (x);
17711 /* On the RS/6000, if it is valid in the insn, it is free. */
17713 if (((outer_code == SET
17714 || outer_code == PLUS
17715 || outer_code == MINUS)
17716 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
17717 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
17718 || ((outer_code == IOR || outer_code == XOR)
17719 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17720 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
17721 || ((outer_code == DIV || outer_code == UDIV
17722 || outer_code == MOD || outer_code == UMOD)
17723 && exact_log2 (INTVAL (x)) >= 0)
17724 || (outer_code == AND
17725 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17726 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
17727 || mask_operand (x, VOIDmode)))
17728 || outer_code == ASHIFT
17729 || outer_code == ASHIFTRT
17730 || outer_code == LSHIFTRT
17731 || outer_code == ROTATE
17732 || outer_code == ROTATERT
17733 || outer_code == ZERO_EXTRACT
17734 || (outer_code == MULT
17735 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
17736 || (outer_code == COMPARE
17737 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
17738 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K'))))
17743 else if ((outer_code == PLUS
17744 && reg_or_add_cint64_operand (x, VOIDmode))
17745 || (outer_code == MINUS
17746 && reg_or_sub_cint64_operand (x, VOIDmode))
17747 || ((outer_code == SET
17748 || outer_code == IOR
17749 || outer_code == XOR)
17751 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
17753 *total = COSTS_N_INSNS (1);
17760 && ((outer_code == AND
17761 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17762 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
17763 || mask64_operand (x, DImode)))
17764 || ((outer_code == IOR || outer_code == XOR)
17765 && CONST_DOUBLE_HIGH (x) == 0
17766 && (CONST_DOUBLE_LOW (x)
17767 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
17772 else if (mode == DImode
17773 && (outer_code == SET
17774 || outer_code == IOR
17775 || outer_code == XOR)
17776 && CONST_DOUBLE_HIGH (x) == 0)
17778 *total = COSTS_N_INSNS (1);
17787 /* When optimizing for size, MEM should be slightly more expensive
17788 than generating address, e.g., (plus (reg) (const)).
17789 L1 cache latency is about two instructions. */
17790 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
17798 if (mode == DFmode)
17800 if (GET_CODE (XEXP (x, 0)) == MULT)
17802 /* FNMA accounted in outer NEG. */
17803 if (outer_code == NEG)
17804 *total = rs6000_cost->dmul - rs6000_cost->fp;
17806 *total = rs6000_cost->dmul;
17809 *total = rs6000_cost->fp;
17811 else if (mode == SFmode)
17813 /* FNMA accounted in outer NEG. */
17814 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
17817 *total = rs6000_cost->fp;
17819 else if (GET_CODE (XEXP (x, 0)) == MULT)
17821 /* The rs6000 doesn't have shift-and-add instructions. */
17822 rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total);
17823 *total += COSTS_N_INSNS (1);
17826 *total = COSTS_N_INSNS (1);
17830 if (mode == DFmode)
17832 if (GET_CODE (XEXP (x, 0)) == MULT)
17834 /* FNMA accounted in outer NEG. */
17835 if (outer_code == NEG)
17838 *total = rs6000_cost->dmul;
17841 *total = rs6000_cost->fp;
17843 else if (mode == SFmode)
17845 /* FNMA accounted in outer NEG. */
17846 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
17849 *total = rs6000_cost->fp;
17851 else if (GET_CODE (XEXP (x, 0)) == MULT)
17853 /* The rs6000 doesn't have shift-and-sub instructions. */
17854 rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total);
17855 *total += COSTS_N_INSNS (1);
17858 *total = COSTS_N_INSNS (1);
17862 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17863 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
17865 if (INTVAL (XEXP (x, 1)) >= -256
17866 && INTVAL (XEXP (x, 1)) <= 255)
17867 *total = rs6000_cost->mulsi_const9;
17869 *total = rs6000_cost->mulsi_const;
17871 /* FMA accounted in outer PLUS/MINUS. */
17872 else if ((mode == DFmode || mode == SFmode)
17873 && (outer_code == PLUS || outer_code == MINUS))
17875 else if (mode == DFmode)
17876 *total = rs6000_cost->dmul;
17877 else if (mode == SFmode)
17878 *total = rs6000_cost->fp;
17879 else if (mode == DImode)
17880 *total = rs6000_cost->muldi;
17882 *total = rs6000_cost->mulsi;
17887 if (FLOAT_MODE_P (mode))
17889 *total = mode == DFmode ? rs6000_cost->ddiv
17890 : rs6000_cost->sdiv;
17897 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17898 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
17900 if (code == DIV || code == MOD)
17902 *total = COSTS_N_INSNS (2);
17905 *total = COSTS_N_INSNS (1);
17909 if (GET_MODE (XEXP (x, 1)) == DImode)
17910 *total = rs6000_cost->divdi;
17912 *total = rs6000_cost->divsi;
17914 /* Add in shift and subtract for MOD. */
17915 if (code == MOD || code == UMOD)
17916 *total += COSTS_N_INSNS (2);
17920 *total = COSTS_N_INSNS (4);
17924 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
17935 *total = COSTS_N_INSNS (1);
17943 /* Handle mul_highpart. */
17944 if (outer_code == TRUNCATE
17945 && GET_CODE (XEXP (x, 0)) == MULT)
17947 if (mode == DImode)
17948 *total = rs6000_cost->muldi;
17950 *total = rs6000_cost->mulsi;
17953 else if (outer_code == AND)
17956 *total = COSTS_N_INSNS (1);
17961 if (GET_CODE (XEXP (x, 0)) == MEM)
17964 *total = COSTS_N_INSNS (1);
17970 if (!FLOAT_MODE_P (mode))
17972 *total = COSTS_N_INSNS (1);
17978 case UNSIGNED_FLOAT:
17982 case FLOAT_TRUNCATE:
17983 *total = rs6000_cost->fp;
17987 switch (XINT (x, 1))
17990 *total = rs6000_cost->fp;
18002 *total = COSTS_N_INSNS (1);
18005 else if (FLOAT_MODE_P (mode)
18006 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
18008 *total = rs6000_cost->fp;
18018 switch (outer_code)
18022 /* PLUS or NEG already counted so only add one more. */
18023 *total = COSTS_N_INSNS (1);
18026 *total = COSTS_N_INSNS (3);
18044 /* A C expression returning the cost of moving data from a register of class
18045 CLASS1 to one of CLASS2. */
18048 rs6000_register_move_cost (enum machine_mode mode,
18049 enum reg_class from, enum reg_class to)
18051 /* Moves from/to GENERAL_REGS. */
18052 if (reg_classes_intersect_p (to, GENERAL_REGS)
18053 || reg_classes_intersect_p (from, GENERAL_REGS))
18055 if (! reg_classes_intersect_p (to, GENERAL_REGS))
18058 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
18059 return (rs6000_memory_move_cost (mode, from, 0)
18060 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
18062 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18064 else if (from == CR_REGS)
18068 /* A move will cost one instruction per GPR moved. */
18069 return 2 * HARD_REGNO_NREGS (0, mode);
18072 /* Moving between two similar registers is just one instruction. */
18073 else if (reg_classes_intersect_p (to, from))
18074 return mode == TFmode ? 4 : 2;
18076 /* Everything else has to go through GENERAL_REGS. */
18078 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
18079 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
18082 /* A C expressions returning the cost of moving data of MODE from a register to
18086 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
18087 int in ATTRIBUTE_UNUSED)
18089 if (reg_classes_intersect_p (class, GENERAL_REGS))
18090 return 4 * HARD_REGNO_NREGS (0, mode);
18091 else if (reg_classes_intersect_p (class, FLOAT_REGS))
18092 return 4 * HARD_REGNO_NREGS (32, mode);
18093 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
18094 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
18096 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
18099 /* Return an RTX representing where to find the function value of a
18100 function returning MODE. */
18102 rs6000_complex_function_value (enum machine_mode mode)
18104 unsigned int regno;
18106 enum machine_mode inner = GET_MODE_INNER (mode);
18107 unsigned int inner_bytes = GET_MODE_SIZE (inner);
18109 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
18110 regno = FP_ARG_RETURN;
18113 regno = GP_ARG_RETURN;
18115 /* 32-bit is OK since it'll go in r3/r4. */
18116 if (TARGET_32BIT && inner_bytes >= 4)
18117 return gen_rtx_REG (mode, regno);
18120 if (inner_bytes >= 8)
18121 return gen_rtx_REG (mode, regno);
18123 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
18125 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
18126 GEN_INT (inner_bytes));
18127 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
18130 /* Define how to find the value returned by a function.
18131 VALTYPE is the data type of the value (as a tree).
18132 If the precise function being called is known, FUNC is its FUNCTION_DECL;
18133 otherwise, FUNC is 0.
18135 On the SPE, both FPs and vectors are returned in r3.
18137 On RS/6000 an integer value is in r3 and a floating-point value is in
18138 fp1, unless -msoft-float. */
18141 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
18143 enum machine_mode mode;
18144 unsigned int regno;
18146 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
18148 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18149 return gen_rtx_PARALLEL (DImode,
18151 gen_rtx_EXPR_LIST (VOIDmode,
18152 gen_rtx_REG (SImode, GP_ARG_RETURN),
18154 gen_rtx_EXPR_LIST (VOIDmode,
18155 gen_rtx_REG (SImode,
18156 GP_ARG_RETURN + 1),
18160 if ((INTEGRAL_TYPE_P (valtype)
18161 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
18162 || POINTER_TYPE_P (valtype))
18163 mode = TARGET_32BIT ? SImode : DImode;
18165 mode = TYPE_MODE (valtype);
18167 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
18168 regno = FP_ARG_RETURN;
18169 else if (TREE_CODE (valtype) == COMPLEX_TYPE
18170 && targetm.calls.split_complex_arg)
18171 return rs6000_complex_function_value (mode);
18172 else if (TREE_CODE (valtype) == VECTOR_TYPE
18173 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
18174 && ALTIVEC_VECTOR_MODE(mode))
18175 regno = ALTIVEC_ARG_RETURN;
18176 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && mode == DFmode)
18177 return spe_build_register_parallel (DFmode, GP_ARG_RETURN);
18179 regno = GP_ARG_RETURN;
18181 return gen_rtx_REG (mode, regno);
18184 /* Define how to find the value returned by a library function
18185 assuming the value has mode MODE. */
18187 rs6000_libcall_value (enum machine_mode mode)
18189 unsigned int regno;
18191 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
18193 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18194 return gen_rtx_PARALLEL (DImode,
18196 gen_rtx_EXPR_LIST (VOIDmode,
18197 gen_rtx_REG (SImode, GP_ARG_RETURN),
18199 gen_rtx_EXPR_LIST (VOIDmode,
18200 gen_rtx_REG (SImode,
18201 GP_ARG_RETURN + 1),
18205 if (GET_MODE_CLASS (mode) == MODE_FLOAT
18206 && TARGET_HARD_FLOAT && TARGET_FPRS)
18207 regno = FP_ARG_RETURN;
18208 else if (ALTIVEC_VECTOR_MODE (mode)
18209 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
18210 regno = ALTIVEC_ARG_RETURN;
18211 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
18212 return rs6000_complex_function_value (mode);
18213 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT && mode == DFmode)
18214 return spe_build_register_parallel (DFmode, GP_ARG_RETURN);
18216 regno = GP_ARG_RETURN;
18218 return gen_rtx_REG (mode, regno);
18221 /* Define the offset between two registers, FROM to be eliminated and its
18222 replacement TO, at the start of a routine. */
18224 rs6000_initial_elimination_offset (int from, int to)
18226 rs6000_stack_t *info = rs6000_stack_info ();
18227 HOST_WIDE_INT offset;
18229 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18230 offset = info->push_p ? 0 : -info->total_size;
18231 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
18232 offset = info->total_size;
18233 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18234 offset = info->push_p ? info->total_size : 0;
18235 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
18243 /* Return true if TYPE is of type __ev64_opaque__. */
18246 is_ev64_opaque_type (tree type)
18249 && (type == opaque_V2SI_type_node
18250 || type == opaque_V2SF_type_node
18251 || type == opaque_p_V2SI_type_node));
18255 rs6000_dwarf_register_span (rtx reg)
18260 && (SPE_VECTOR_MODE (GET_MODE (reg))
18261 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
18266 regno = REGNO (reg);
18268 /* The duality of the SPE register size wreaks all kinds of havoc.
18269 This is a way of distinguishing r0 in 32-bits from r0 in
18272 gen_rtx_PARALLEL (VOIDmode,
18275 gen_rtx_REG (SImode, regno + 1200),
18276 gen_rtx_REG (SImode, regno))
18278 gen_rtx_REG (SImode, regno),
18279 gen_rtx_REG (SImode, regno + 1200)));
18282 /* Map internal gcc register numbers to DWARF2 register numbers. */
18285 rs6000_dbx_register_number (unsigned int regno)
18287 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
18289 if (regno == MQ_REGNO)
18291 if (regno == LINK_REGISTER_REGNUM)
18293 if (regno == COUNT_REGISTER_REGNUM)
18295 if (CR_REGNO_P (regno))
18296 return regno - CR0_REGNO + 86;
18297 if (regno == XER_REGNO)
18299 if (ALTIVEC_REGNO_P (regno))
18300 return regno - FIRST_ALTIVEC_REGNO + 1124;
18301 if (regno == VRSAVE_REGNO)
18303 if (regno == VSCR_REGNO)
18305 if (regno == SPE_ACC_REGNO)
18307 if (regno == SPEFSCR_REGNO)
18309 /* SPE high reg number. We get these values of regno from
18310 rs6000_dwarf_register_span. */
18311 if (regno >= 1200 && regno < 1232)
18317 /* target hook eh_return_filter_mode */
18318 static enum machine_mode
18319 rs6000_eh_return_filter_mode (void)
18321 return TARGET_32BIT ? SImode : word_mode;
18324 /* Target hook for vector_mode_supported_p. */
18326 rs6000_vector_mode_supported_p (enum machine_mode mode)
18329 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
18332 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
18339 #include "gt-rs6000.h"