1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
40 extern char *language_string;
41 extern int profile_block_flag;
43 #define min(A,B) ((A) < (B) ? (A) : (B))
44 #define max(A,B) ((A) > (B) ? (A) : (B))
48 enum processor_type rs6000_cpu;
49 char *rs6000_cpu_string;
51 /* Set to non-zero by "fix" operation to indicate that itrunc and
52 uitrunc must be defined. */
54 int rs6000_trunc_used;
56 /* Set to non-zero once they have been defined. */
58 static int trunc_defined;
60 /* Set to non-zero once AIX common-mode calls have been defined. */
61 static int common_mode_defined;
62 /* Save information from a "cmpxx" operation until the branch or scc is
65 rtx rs6000_compare_op0, rs6000_compare_op1;
66 int rs6000_compare_fp_p;
69 /* Label number of label created for -mrelocatable, to call to so we can
70 get the address of the GOT section */
71 int rs6000_pic_labelno;
74 /* Whether a System V.4 varargs area was created. */
75 int rs6000_sysv_varargs_p;
77 /* Override command line options. Mostly we process the processor
78 type and sometimes adjust other TARGET_ options. */
81 rs6000_override_options ()
85 /* Simplify the entries below by making a mask for any POWER
86 variant and any PowerPC variant. */
88 #define POWER_MASKS (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING)
89 #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \
90 | MASK_PPC_GFXOPT | MASK_POWERPC64)
91 #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT)
95 char *name; /* Canonical processor name. */
96 enum processor_type processor; /* Processor type enum value. */
97 int target_enable; /* Target flags to enable. */
98 int target_disable; /* Target flags to disable. */
99 } processor_target_table[]
100 = {{"common", PROCESSOR_COMMON, 0, POWER_MASKS | POWERPC_MASKS},
101 {"power", PROCESSOR_POWER,
102 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
103 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
104 {"powerpc", PROCESSOR_POWERPC,
105 MASK_POWERPC | MASK_NEW_MNEMONICS,
106 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
107 {"rios", PROCESSOR_RIOS1,
108 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
109 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
110 {"rios1", PROCESSOR_RIOS1,
111 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
112 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
113 {"rsc", PROCESSOR_PPC601,
114 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
115 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
116 {"rsc1", PROCESSOR_PPC601,
117 MASK_POWER | MASK_MULTIPLE | MASK_STRING,
118 MASK_POWER2 | POWERPC_MASKS | MASK_NEW_MNEMONICS},
119 {"rios2", PROCESSOR_RIOS2,
120 MASK_POWER | MASK_MULTIPLE | MASK_STRING | MASK_POWER2,
121 POWERPC_MASKS | MASK_NEW_MNEMONICS},
122 {"403", PROCESSOR_PPC403,
123 MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
124 POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
125 {"601", PROCESSOR_PPC601,
126 MASK_POWER | MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_MULTIPLE | MASK_STRING,
127 MASK_POWER2 | POWERPC_OPT_MASKS | MASK_POWERPC64},
128 {"603", PROCESSOR_PPC603,
129 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
130 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64},
131 {"604", PROCESSOR_PPC604,
132 MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
133 POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}};
135 int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
137 int multiple = TARGET_MULTIPLE; /* save current -mmultiple/-mno-multiple status */
138 int string = TARGET_STRING; /* save current -mstring/-mno-string status */
140 profile_block_flag = 0;
142 /* Identify the processor type */
143 if (rs6000_cpu_string == 0)
144 rs6000_cpu = PROCESSOR_DEFAULT;
147 for (i = 0; i < ptt_size; i++)
148 if (! strcmp (rs6000_cpu_string, processor_target_table[i].name))
150 rs6000_cpu = processor_target_table[i].processor;
151 target_flags |= processor_target_table[i].target_enable;
152 target_flags &= ~processor_target_table[i].target_disable;
158 error ("bad value (%s) for -mcpu= switch", rs6000_cpu_string);
159 rs6000_cpu_string = "default";
160 rs6000_cpu = PROCESSOR_DEFAULT;
164 /* If -mmultiple or -mno-multiple was explicitly used, don't
165 override with the processor default */
166 if (TARGET_MULTIPLE_SET)
167 target_flags = (target_flags & ~MASK_MULTIPLE) | multiple;
169 /* If -mstring or -mno-string was explicitly used, don't
170 override with the processor default */
171 if (TARGET_STRING_SET)
172 target_flags = (target_flags & ~MASK_STRING) | string;
174 /* Don't allow -mmultiple or -mstring on little endian systems, because the
175 hardware doesn't support the instructions used in little endian mode */
176 if (!BYTES_BIG_ENDIAN)
180 target_flags &= ~MASK_MULTIPLE;
181 if (TARGET_MULTIPLE_SET)
182 warning ("-mmultiple is not supported on little endian systems");
187 target_flags &= ~MASK_STRING;
188 if (TARGET_STRING_SET)
189 warning ("-mstring is not supported on little endian systems");
193 #ifdef SUBTARGET_OVERRIDE_OPTIONS
194 SUBTARGET_OVERRIDE_OPTIONS;
198 /* Create a CONST_DOUBLE like immed_double_const, except reverse the
199 two parts of the constant if the target is little endian. */
202 rs6000_immed_double_const (i0, i1, mode)
203 HOST_WIDE_INT i0, i1;
204 enum machine_mode mode;
206 if (! WORDS_BIG_ENDIAN)
207 return immed_double_const (i1, i0, mode);
209 return immed_double_const (i0, i1, mode);
213 /* Return non-zero if this function is known to have a null epilogue. */
218 if (reload_completed)
220 rs6000_stack_t *info = rs6000_stack_info ();
222 if (info->first_gp_reg_save == 32
223 && info->first_fp_reg_save == 64
233 /* Returns 1 always. */
236 any_operand (op, mode)
238 enum machine_mode mode;
243 /* Return 1 if OP is a constant that can fit in a D field. */
246 short_cint_operand (op, mode)
248 enum machine_mode mode;
250 return (GET_CODE (op) == CONST_INT
251 && (unsigned) (INTVAL (op) + 0x8000) < 0x10000);
254 /* Similar for a unsigned D field. */
257 u_short_cint_operand (op, mode)
259 enum machine_mode mode;
261 return (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0);
264 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
267 non_short_cint_operand (op, mode)
269 enum machine_mode mode;
271 return (GET_CODE (op) == CONST_INT
272 && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000);
275 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
279 gpc_reg_operand (op, mode)
281 enum machine_mode mode;
283 return (register_operand (op, mode)
284 && (GET_CODE (op) != REG || REGNO (op) >= 67 || REGNO (op) < 64));
287 /* Returns 1 if OP is either a pseudo-register or a register denoting a
291 cc_reg_operand (op, mode)
293 enum machine_mode mode;
295 return (register_operand (op, mode)
296 && (GET_CODE (op) != REG
297 || REGNO (op) >= FIRST_PSEUDO_REGISTER
298 || CR_REGNO_P (REGNO (op))));
301 /* Returns 1 if OP is either a constant integer valid for a D-field or a
302 non-special register. If a register, it must be in the proper mode unless
306 reg_or_short_operand (op, mode)
308 enum machine_mode mode;
310 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
313 /* Similar, except check if the negation of the constant would be valid for
317 reg_or_neg_short_operand (op, mode)
319 enum machine_mode mode;
321 if (GET_CODE (op) == CONST_INT)
322 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
324 return gpc_reg_operand (op, mode);
327 /* Return 1 if the operand is either a register or an integer whose high-order
331 reg_or_u_short_operand (op, mode)
333 enum machine_mode mode;
335 if (GET_CODE (op) == CONST_INT
336 && (INTVAL (op) & 0xffff0000) == 0)
339 return gpc_reg_operand (op, mode);
342 /* Return 1 is the operand is either a non-special register or ANY
346 reg_or_cint_operand (op, mode)
348 enum machine_mode mode;
350 return GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode);
353 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register
354 with one instruction per word. We only do this if we can safely read
355 CONST_DOUBLE_{LOW,HIGH}. */
358 easy_fp_constant (op, mode)
360 register enum machine_mode mode;
364 if (GET_CODE (op) != CONST_DOUBLE
365 || GET_MODE (op) != mode
366 || GET_MODE_CLASS (mode) != MODE_FLOAT)
369 high = operand_subword (op, 0, 0, mode);
370 low = operand_subword (op, 1, 0, mode);
372 if (high == 0 || ! input_operand (high, word_mode))
375 return (mode == SFmode
376 || (low != 0 && input_operand (low, word_mode)));
379 /* Return 1 if the operand is a constant whose low-order 32 bits are
383 low_32_bit_operand (op, mode)
385 enum machine_mode mode;
389 if (GET_CODE (op) != CONST_DOUBLE && GET_CODE (op) != CONST_INT)
392 low = operand_subword (op, 1, 0, mode);
393 return low != 0 && GET_CODE (low) == CONST_INT && INTVAL (low) == 0;
396 /* Return 1 if the operand is either a floating-point register, a pseudo
397 register, or memory. */
400 fp_reg_or_mem_operand (op, mode)
402 enum machine_mode mode;
404 return (memory_operand (op, mode)
405 || (register_operand (op, mode)
406 && (GET_CODE (op) != REG
407 || REGNO (op) >= FIRST_PSEUDO_REGISTER
408 || FP_REGNO_P (REGNO (op)))));
411 /* Return 1 if the operand is either an easy FP constant (see above) or
415 mem_or_easy_const_operand (op, mode)
417 enum machine_mode mode;
419 return memory_operand (op, mode) || easy_fp_constant (op, mode);
422 /* Return 1 if the operand is either a non-special register or an item
423 that can be used as the operand of an SI add insn. */
426 add_operand (op, mode)
428 enum machine_mode mode;
430 return (reg_or_short_operand (op, mode)
431 || (GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff) == 0));
434 /* Return 1 if OP is a constant but not a valid add_operand. */
437 non_add_cint_operand (op, mode)
439 enum machine_mode mode;
441 return (GET_CODE (op) == CONST_INT
442 && (unsigned) (INTVAL (op) + 0x8000) >= 0x10000
443 && (INTVAL (op) & 0xffff) != 0);
446 /* Return 1 if the operand is a non-special register or a constant that
447 can be used as the operand of an OR or XOR insn on the RS/6000. */
450 logical_operand (op, mode)
452 enum machine_mode mode;
454 return (gpc_reg_operand (op, mode)
455 || (GET_CODE (op) == CONST_INT
456 && ((INTVAL (op) & 0xffff0000) == 0
457 || (INTVAL (op) & 0xffff) == 0)));
460 /* Return 1 if C is a constant that is not a logical operand (as
464 non_logical_cint_operand (op, mode)
466 enum machine_mode mode;
468 return (GET_CODE (op) == CONST_INT
469 && (INTVAL (op) & 0xffff0000) != 0
470 && (INTVAL (op) & 0xffff) != 0);
473 /* Return 1 if C is a constant that can be encoded in a mask on the
474 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
475 Reject all ones and all zeros, since these should have been optimized
476 away and confuse the making of MB and ME. */
486 if (c == 0 || c == ~0)
489 last_bit_value = c & 1;
491 for (i = 1; i < 32; i++)
492 if (((c >>= 1) & 1) != last_bit_value)
493 last_bit_value ^= 1, transitions++;
495 return transitions <= 2;
498 /* Return 1 if the operand is a constant that is a mask on the RS/6000. */
501 mask_operand (op, mode)
503 enum machine_mode mode;
505 return GET_CODE (op) == CONST_INT && mask_constant (INTVAL (op));
508 /* Return 1 if the operand is either a non-special register or a
509 constant that can be used as the operand of an RS/6000 logical AND insn. */
512 and_operand (op, mode)
514 enum machine_mode mode;
516 return (reg_or_short_operand (op, mode)
517 || logical_operand (op, mode)
518 || mask_operand (op, mode));
521 /* Return 1 if the operand is a constant but not a valid operand for an AND
525 non_and_cint_operand (op, mode)
527 enum machine_mode mode;
529 return GET_CODE (op) == CONST_INT && ! and_operand (op, mode);
532 /* Return 1 if the operand is a general register or memory operand. */
535 reg_or_mem_operand (op, mode)
537 register enum machine_mode mode;
539 return gpc_reg_operand (op, mode) || memory_operand (op, mode);
542 /* Return 1 if the operand is a general register or memory operand without
543 pre-inc or pre_dec which produces invalid form of PowerPC lwa
547 lwa_operand (op, mode)
549 register enum machine_mode mode;
553 if (reload_completed && GET_CODE (inner) == SUBREG)
554 inner = SUBREG_REG (inner);
556 return gpc_reg_operand (inner, mode)
557 || (memory_operand (inner, mode)
558 && GET_CODE (XEXP (inner, 0)) != PRE_INC
559 && GET_CODE (XEXP (inner, 0)) != PRE_DEC);
562 /* Return 1 if the operand, used inside a MEM, is a valid first argument
563 to CALL. This is a SYMBOL_REF or a pseudo-register, which will be
567 call_operand (op, mode)
569 enum machine_mode mode;
571 if (mode != VOIDmode && GET_MODE (op) != mode)
574 return (GET_CODE (op) == SYMBOL_REF
575 || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER));
579 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
583 current_file_function_operand (op, mode)
585 enum machine_mode mode;
587 return (GET_CODE (op) == SYMBOL_REF
588 && (SYMBOL_REF_FLAG (op)
589 || op == XEXP (DECL_RTL (current_function_decl), 0)));
593 /* Return 1 if this operand is a valid input for a move insn. */
596 input_operand (op, mode)
598 enum machine_mode mode;
600 /* Memory is always valid. */
601 if (memory_operand (op, mode))
604 /* For floating-point, easy constants are valid. */
605 if (GET_MODE_CLASS (mode) == MODE_FLOAT
607 && easy_fp_constant (op, mode))
610 /* For floating-point or multi-word mode, the only remaining valid type
612 if (GET_MODE_CLASS (mode) == MODE_FLOAT
613 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
614 return register_operand (op, mode);
616 /* The only cases left are integral modes one word or smaller (we
617 do not get called for MODE_CC values). These can be in any
619 if (register_operand (op, mode))
622 /* For HImode and QImode, any constant is valid. */
623 if ((mode == HImode || mode == QImode)
624 && GET_CODE (op) == CONST_INT)
627 /* A SYMBOL_REF referring to the TOC is valid. */
628 if (LEGITIMATE_CONSTANT_POOL_ADDRESS_P (op))
631 /* Otherwise, we will be doing this SET with an add, so anything valid
632 for an add will be valid. */
633 return add_operand (op, mode);
636 /* Initialize a variable CUM of type CUMULATIVE_ARGS
637 for a call to a function whose data type is FNTYPE.
638 For a library call, FNTYPE is 0.
640 For incoming args we set the number of arguments in the prototype large
641 so we never return an EXPR_LIST. */
644 init_cumulative_args (cum, fntype, libname, incoming)
645 CUMULATIVE_ARGS *cum;
650 static CUMULATIVE_ARGS zero_cumulative;
652 *cum = zero_cumulative;
654 cum->fregno = FP_ARG_MIN_REG;
655 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
659 cum->nargs_prototype = 1000; /* don't return an EXPR_LIST */
660 #ifdef TARGET_V4_CALLS
662 cum->varargs_offset = RS6000_VARARGS_OFFSET;
666 else if (cum->prototype)
667 cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1
668 + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
669 || RETURN_IN_MEMORY (TREE_TYPE (fntype))));
672 cum->nargs_prototype = 0;
674 cum->orig_nargs = cum->nargs_prototype;
675 if (TARGET_DEBUG_ARG)
677 fprintf (stderr, "\ninit_cumulative_args:");
680 tree ret_type = TREE_TYPE (fntype);
681 fprintf (stderr, " ret code = %s,",
682 tree_code_name[ (int)TREE_CODE (ret_type) ]);
685 #ifdef TARGET_V4_CALLS
686 if (TARGET_V4_CALLS && incoming)
687 fprintf (stderr, " varargs = %d, ", cum->varargs_offset);
690 fprintf (stderr, " proto = %d, nargs = %d\n",
691 cum->prototype, cum->nargs_prototype);
695 /* Update the data in CUM to advance over an argument
696 of mode MODE and data type TYPE.
697 (TYPE is null for libcalls where that information may not be available.) */
700 function_arg_advance (cum, mode, type, named)
701 CUMULATIVE_ARGS *cum;
702 enum machine_mode mode;
706 cum->nargs_prototype--;
708 #ifdef TARGET_V4_CALLS
711 /* Long longs must not be split between registers and stack */
712 if ((GET_MODE_CLASS (mode) != MODE_FLOAT || TARGET_SOFT_FLOAT)
713 && type && !AGGREGATE_TYPE_P (type)
714 && cum->words < GP_ARG_NUM_REG
715 && cum->words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG)
717 cum->words = GP_ARG_NUM_REG;
720 /* Aggregates get passed as pointers */
721 if (type && AGGREGATE_TYPE_P (type))
724 /* Floats go in registers, & don't occupy space in the GP registers
725 like they do for AIX unless software floating point. */
726 else if (GET_MODE_CLASS (mode) == MODE_FLOAT
728 && cum->fregno <= FP_ARG_V4_MAX_REG)
732 cum->words += RS6000_ARG_SIZE (mode, type, 1);
738 cum->words += RS6000_ARG_SIZE (mode, type, named);
739 if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT)
743 if (TARGET_DEBUG_ARG)
745 "function_adv: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, named = %d\n",
746 cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), named);
749 /* Determine where to put an argument to a function.
750 Value is zero to push the argument on the stack,
751 or a hard register in which to store the argument.
753 MODE is the argument's machine mode.
754 TYPE is the data type of the argument (as a tree).
755 This is null for libcalls where that information may
757 CUM is a variable of type CUMULATIVE_ARGS which gives info about
758 the preceding args and about the function being called.
759 NAMED is nonzero if this argument is a named parameter
760 (otherwise it is an extra parameter matching an ellipsis).
762 On RS/6000 the first eight words of non-FP are normally in registers
763 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
764 Under V.4, the first 8 FP args are in registers.
766 If this is floating-point and no prototype is specified, we use
767 both an FP and integer register (or possibly FP reg and stack). Library
768 functions (when TYPE is zero) always have the proper types for args,
769 so we can pass the FP value just in one register. emit_library_function
770 doesn't support EXPR_LIST anyway. */
773 function_arg (cum, mode, type, named)
774 CUMULATIVE_ARGS *cum;
775 enum machine_mode mode;
779 if (TARGET_DEBUG_ARG)
781 "function_arg: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, named = %d\n",
782 cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), named);
784 /* Return a marker to indicate whether CR1 needs to set or clear the bit that V.4
785 uses to say fp args were passed in registers. Assume that we don't need the
786 marker for software floating point, or compiler generated library calls. */
787 if (mode == VOIDmode)
789 #ifdef TARGET_V4_CALLS
790 if (TARGET_V4_CALLS && TARGET_HARD_FLOAT && cum->nargs_prototype < 0
791 && type && (cum->prototype || TARGET_NO_PROTOTYPE))
792 return GEN_INT ((cum->fregno == FP_ARG_MIN_REG) ? -1 : 1);
800 #ifdef TARGET_V4_CALLS
801 if (!TARGET_V4_CALLS)
806 if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
809 if (USE_FP_FOR_ARG_P (*cum, mode, type))
811 if ((cum->nargs_prototype > 0)
812 #ifdef TARGET_V4_CALLS
813 || TARGET_V4_CALLS /* V.4 never passes FP values in GP registers */
816 return gen_rtx (REG, mode, cum->fregno);
818 return gen_rtx (EXPR_LIST, VOIDmode,
819 ((cum->words < GP_ARG_NUM_REG)
820 ? gen_rtx (REG, mode, GP_ARG_MIN_REG + cum->words)
822 gen_rtx (REG, mode, cum->fregno));
825 #ifdef TARGET_V4_CALLS
826 /* Long longs won't be split between register and stack */
827 else if (TARGET_V4_CALLS &&
828 cum->words + RS6000_ARG_SIZE (mode, type, named) > GP_ARG_NUM_REG)
834 else if (cum->words < GP_ARG_NUM_REG)
835 return gen_rtx (REG, mode, GP_ARG_MIN_REG + cum->words);
840 /* For an arg passed partly in registers and partly in memory,
841 this is the number of registers used.
842 For args passed entirely in registers or entirely in memory, zero. */
845 function_arg_partial_nregs (cum, mode, type, named)
846 CUMULATIVE_ARGS *cum;
847 enum machine_mode mode;
854 #ifdef TARGET_V4_CALLS
859 if (USE_FP_FOR_ARG_P (*cum, mode, type))
861 if (cum->nargs_prototype >= 0)
865 if (cum->words < GP_ARG_NUM_REG
866 && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type, named)))
868 int ret = GP_ARG_NUM_REG - cum->words;
869 if (ret && TARGET_DEBUG_ARG)
870 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
878 /* A C expression that indicates when an argument must be passed by
879 reference. If nonzero for an argument, a copy of that argument is
880 made in memory and a pointer to the argument is passed instead of
881 the argument itself. The pointer is passed in whatever way is
882 appropriate for passing a pointer to that type.
884 Under V.4, structures and unions are passed by reference. */
887 function_arg_pass_by_reference (cum, mode, type, named)
888 CUMULATIVE_ARGS *cum;
889 enum machine_mode mode;
893 #ifdef TARGET_V4_CALLS
894 if (TARGET_V4_CALLS && type && AGGREGATE_TYPE_P (type))
896 if (TARGET_DEBUG_ARG)
897 fprintf (stderr, "function_arg_pass_by_reference: aggregate\n");
907 /* Perform any needed actions needed for a function that is receiving a
908 variable number of arguments.
912 MODE and TYPE are the mode and type of the current parameter.
914 PRETEND_SIZE is a variable that should be set to the amount of stack
915 that must be pushed by the prolog to pretend that our caller pushed
918 Normally, this macro will push all remaining incoming registers on the
919 stack and set PRETEND_SIZE to the length of the registers pushed. */
922 setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
923 CUMULATIVE_ARGS *cum;
924 enum machine_mode mode;
930 rtx save_area = virtual_incoming_args_rtx;
931 int reg_size = (TARGET_64BIT) ? 8 : 4;
933 if (TARGET_DEBUG_ARG)
935 "setup_vararg: words = %2d, fregno = %2d, nargs = %4d, proto = %d, mode = %4s, no_rtl= %d\n",
936 cum->words, cum->fregno, cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode), no_rtl);
938 #ifdef TARGET_V4_CALLS
939 if (TARGET_V4_CALLS && !no_rtl)
941 rs6000_sysv_varargs_p = 1;
942 save_area = plus_constant (frame_pointer_rtx, RS6000_VARARGS_OFFSET);
948 int first_reg_offset = cum->words;
950 if (MUST_PASS_IN_STACK (mode, type))
951 first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type, 1);
953 if (first_reg_offset > GP_ARG_NUM_REG)
954 first_reg_offset = GP_ARG_NUM_REG;
956 if (!no_rtl && first_reg_offset != GP_ARG_NUM_REG)
958 (GP_ARG_MIN_REG + first_reg_offset,
959 gen_rtx (MEM, BLKmode,
960 plus_constant (save_area, first_reg_offset * reg_size)),
961 GP_ARG_NUM_REG - first_reg_offset,
962 (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD);
964 *pretend_size = (GP_ARG_NUM_REG - first_reg_offset) * UNITS_PER_WORD;
967 #ifdef TARGET_V4_CALLS
968 /* Save FP registers if needed. */
969 if (TARGET_V4_CALLS && TARGET_HARD_FLOAT && !no_rtl)
971 int fregno = cum->fregno;
972 int num_fp_reg = FP_ARG_V4_MAX_REG + 1 - fregno;
976 rtx cr1 = gen_rtx (REG, CCmode, 69);
977 rtx lab = gen_label_rtx ();
978 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
980 emit_jump_insn (gen_rtx (SET, VOIDmode,
982 gen_rtx (IF_THEN_ELSE, VOIDmode,
983 gen_rtx (NE, VOIDmode, cr1, const0_rtx),
984 gen_rtx (LABEL_REF, VOIDmode, lab),
987 while ( num_fp_reg-- >= 0)
989 emit_move_insn (gen_rtx (MEM, DFmode, plus_constant (save_area, off)),
990 gen_rtx (REG, DFmode, fregno++));
1000 /* If defined, is a C expression that produces the machine-specific
1001 code for a call to `__builtin_saveregs'. This code will be moved
1002 to the very beginning of the function, before any parameter access
1003 are made. The return value of this function should be an RTX that
1004 contains the value to use as the return of `__builtin_saveregs'.
1006 The argument ARGS is a `tree_list' containing the arguments that
1007 were passed to `__builtin_saveregs'.
1009 If this macro is not defined, the compiler will output an ordinary
1010 call to the library function `__builtin_saveregs'.
1012 On the Power/PowerPC return the address of the area on the stack
1013 used to hold arguments. Under AIX, this includes the 8 word register
1014 save area. Under V.4 this does not. */
1017 expand_builtin_saveregs (args)
1020 return virtual_incoming_args_rtx;
1024 /* Expand a block move operation, and return 1 if successful. Return 0
1025 if we should let the compiler generate normal code.
1027 operands[0] is the destination
1028 operands[1] is the source
1029 operands[2] is the length
1030 operands[3] is the alignment */
1032 #define MAX_MOVE_REG 4
1035 expand_block_move (operands)
1038 rtx bytes_rtx = operands[2];
1039 rtx align_rtx = operands[3];
1040 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
1041 int align = XINT (align_rtx, 0);
1051 rtx stores[MAX_MOVE_REG];
1054 /* If this is not a fixed size move, just call memcpy */
1058 /* Anything to move? */
1059 bytes = INTVAL (bytes_rtx);
1063 /* Don't support real large moves. If string instructions are not used,
1064 then don't generate more than 8 loads. */
1070 else if (!STRICT_ALIGNMENT)
1075 else if (bytes > 8*align)
1078 /* Move the address into scratch registers. */
1079 dest_reg = copy_addr_to_reg (XEXP (operands[0], 0));
1080 src_reg = copy_addr_to_reg (XEXP (operands[1], 0));
1082 if (TARGET_STRING) /* string instructions are available */
1084 for ( ; bytes > 0; bytes -= move_bytes)
1086 if (bytes > 24 /* move up to 32 bytes at a time */
1096 move_bytes = (bytes > 32) ? 32 : bytes;
1097 emit_insn (gen_movstrsi_8reg (dest_reg,
1099 GEN_INT ((move_bytes == 32) ? 0 : move_bytes),
1102 else if (bytes > 16 /* move up to 24 bytes at a time */
1110 move_bytes = (bytes > 24) ? 24 : bytes;
1111 emit_insn (gen_movstrsi_6reg (dest_reg,
1113 GEN_INT (move_bytes),
1116 else if (bytes > 8 /* move up to 16 bytes at a time */
1122 move_bytes = (bytes > 16) ? 16 : bytes;
1123 emit_insn (gen_movstrsi_4reg (dest_reg,
1125 GEN_INT (move_bytes),
1128 else if (bytes > 4 && !TARGET_64BIT)
1129 { /* move up to 8 bytes at a time */
1130 move_bytes = (bytes > 8) ? 8 : bytes;
1131 emit_insn (gen_movstrsi_2reg (dest_reg,
1133 GEN_INT (move_bytes),
1136 else if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT))
1137 { /* move 4 bytes */
1139 tmp_reg = gen_reg_rtx (SImode);
1140 emit_move_insn (tmp_reg, gen_rtx (MEM, SImode, src_reg));
1141 emit_move_insn (gen_rtx (MEM, SImode, dest_reg), tmp_reg);
1143 else if (bytes == 2 && (align >= 2 || !STRICT_ALIGNMENT))
1144 { /* move 2 bytes */
1146 tmp_reg = gen_reg_rtx (HImode);
1147 emit_move_insn (tmp_reg, gen_rtx (MEM, HImode, src_reg));
1148 emit_move_insn (gen_rtx (MEM, HImode, dest_reg), tmp_reg);
1150 else if (bytes == 1) /* move 1 byte */
1153 tmp_reg = gen_reg_rtx (QImode);
1154 emit_move_insn (tmp_reg, gen_rtx (MEM, QImode, src_reg));
1155 emit_move_insn (gen_rtx (MEM, QImode, dest_reg), tmp_reg);
1158 { /* move up to 4 bytes at a time */
1159 move_bytes = (bytes > 4) ? 4 : bytes;
1160 emit_insn (gen_movstrsi_1reg (dest_reg,
1162 GEN_INT (move_bytes),
1166 if (bytes > move_bytes)
1168 emit_insn (gen_addsi3 (src_reg, src_reg, GEN_INT (move_bytes)));
1169 emit_insn (gen_addsi3 (dest_reg, dest_reg, GEN_INT (move_bytes)));
1174 else /* string instructions not available */
1176 num_reg = offset = 0;
1177 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
1179 /* Calculate the correct offset for src/dest */
1183 dest_addr = dest_reg;
1187 src_addr = gen_rtx (PLUS, Pmode, src_reg, GEN_INT (offset));
1188 dest_addr = gen_rtx (PLUS, Pmode, dest_reg, GEN_INT (offset));
1191 /* Generate the appropriate load and store, saving the stores for later */
1192 if (bytes >= 4 && (align >= 4 || !STRICT_ALIGNMENT))
1195 tmp_reg = gen_reg_rtx (SImode);
1196 emit_insn (gen_movsi (tmp_reg, gen_rtx (MEM, SImode, src_addr)));
1197 stores[ num_reg++ ] = gen_movsi (gen_rtx (MEM, SImode, dest_addr), tmp_reg);
1199 else if (bytes >= 2 && (align >= 2 || !STRICT_ALIGNMENT))
1202 tmp_reg = gen_reg_rtx (HImode);
1203 emit_insn (gen_movhi (tmp_reg, gen_rtx (MEM, HImode, src_addr)));
1204 stores[ num_reg++ ] = gen_movhi (gen_rtx (MEM, HImode, dest_addr), tmp_reg);
1209 tmp_reg = gen_reg_rtx (QImode);
1210 emit_insn (gen_movqi (tmp_reg, gen_rtx (MEM, QImode, src_addr)));
1211 stores[ num_reg++ ] = gen_movqi (gen_rtx (MEM, QImode, dest_addr), tmp_reg);
1214 if (num_reg >= MAX_MOVE_REG)
1216 for (i = 0; i < num_reg; i++)
1217 emit_insn (stores[i]);
1224 for (i = 0; i < num_reg; i++)
1225 emit_insn (stores[i]);
1233 /* Return 1 if OP is a load multiple operation. It is known to be a
1234 PARALLEL and the first section will be tested. */
1237 load_multiple_operation (op, mode)
1239 enum machine_mode mode;
1241 int count = XVECLEN (op, 0);
1246 /* Perform a quick check so we don't blow up below. */
1248 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1249 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1250 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1253 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1254 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1256 for (i = 1; i < count; i++)
1258 rtx elt = XVECEXP (op, 0, i);
1260 if (GET_CODE (elt) != SET
1261 || GET_CODE (SET_DEST (elt)) != REG
1262 || GET_MODE (SET_DEST (elt)) != SImode
1263 || REGNO (SET_DEST (elt)) != dest_regno + i
1264 || GET_CODE (SET_SRC (elt)) != MEM
1265 || GET_MODE (SET_SRC (elt)) != SImode
1266 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1267 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1268 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1269 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1276 /* Similar, but tests for store multiple. Here, the second vector element
1277 is a CLOBBER. It will be tested later. */
1280 store_multiple_operation (op, mode)
1282 enum machine_mode mode;
1284 int count = XVECLEN (op, 0) - 1;
1289 /* Perform a quick check so we don't blow up below. */
1291 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1292 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1293 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1296 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1297 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1299 for (i = 1; i < count; i++)
1301 rtx elt = XVECEXP (op, 0, i + 1);
1303 if (GET_CODE (elt) != SET
1304 || GET_CODE (SET_SRC (elt)) != REG
1305 || GET_MODE (SET_SRC (elt)) != SImode
1306 || REGNO (SET_SRC (elt)) != src_regno + i
1307 || GET_CODE (SET_DEST (elt)) != MEM
1308 || GET_MODE (SET_DEST (elt)) != SImode
1309 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1310 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1311 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1312 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1319 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
1320 We only check the opcode against the mode of the CC value here. */
1323 branch_comparison_operator (op, mode)
1325 enum machine_mode mode;
1327 enum rtx_code code = GET_CODE (op);
1328 enum machine_mode cc_mode;
1330 if (GET_RTX_CLASS (code) != '<')
1333 cc_mode = GET_MODE (XEXP (op, 0));
1334 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
1337 if ((code == GT || code == LT || code == GE || code == LE)
1338 && cc_mode == CCUNSmode)
1341 if ((code == GTU || code == LTU || code == GEU || code == LEU)
1342 && (cc_mode != CCUNSmode))
1348 /* Return 1 if OP is a comparison operation that is valid for an scc insn.
1349 We check the opcode against the mode of the CC value and disallow EQ or
1350 NE comparisons for integers. */
1353 scc_comparison_operator (op, mode)
1355 enum machine_mode mode;
1357 enum rtx_code code = GET_CODE (op);
1358 enum machine_mode cc_mode;
1360 if (GET_MODE (op) != mode && mode != VOIDmode)
1363 if (GET_RTX_CLASS (code) != '<')
1366 cc_mode = GET_MODE (XEXP (op, 0));
1367 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
1370 if (code == NE && cc_mode != CCFPmode)
1373 if ((code == GT || code == LT || code == GE || code == LE)
1374 && cc_mode == CCUNSmode)
1377 if ((code == GTU || code == LTU || code == GEU || code == LEU)
1378 && (cc_mode != CCUNSmode))
1381 if (cc_mode == CCEQmode && code != EQ && code != NE)
1387 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
1388 mask required to convert the result of a rotate insn into a shift
1389 left insn of SHIFTOP bits. Both are known to be CONST_INT. */
1392 includes_lshift_p (shiftop, andop)
1393 register rtx shiftop;
1396 int shift_mask = (~0 << INTVAL (shiftop));
1398 return (INTVAL (andop) & ~shift_mask) == 0;
1401 /* Similar, but for right shift. */
1404 includes_rshift_p (shiftop, andop)
1405 register rtx shiftop;
1408 unsigned shift_mask = ~0;
1410 shift_mask >>= INTVAL (shiftop);
1412 return (INTVAL (andop) & ~ shift_mask) == 0;
1415 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
1416 for lfq and stfq insns.
1418 Note reg1 and reg2 *must* be hard registers. To be sure we will
1419 abort if we are passed pseudo registers. */
1422 registers_ok_for_quad_peep (reg1, reg2)
1425 /* We might have been passed a SUBREG. */
1426 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
1429 return (REGNO (reg1) == REGNO (reg2) - 1);
1432 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn. addr1 and
1433 addr2 must be in consecutive memory locations (addr2 == addr1 + 8). */
1436 addrs_ok_for_quad_peep (addr1, addr2)
1443 /* Extract an offset (if used) from the first addr. */
1444 if (GET_CODE (addr1) == PLUS)
1446 /* If not a REG, return zero. */
1447 if (GET_CODE (XEXP (addr1, 0)) != REG)
1451 reg1 = REGNO (XEXP (addr1, 0));
1452 /* The offset must be constant! */
1453 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
1455 offset1 = INTVAL (XEXP (addr1, 1));
1458 else if (GET_CODE (addr1) != REG)
1462 reg1 = REGNO (addr1);
1463 /* This was a simple (mem (reg)) expression. Offset is 0. */
1467 /* Make sure the second address is a (mem (plus (reg) (const_int). */
1468 if (GET_CODE (addr2) != PLUS)
1471 if (GET_CODE (XEXP (addr2, 0)) != REG
1472 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
1475 if (reg1 != REGNO (XEXP (addr2, 0)))
1478 /* The offset for the second addr must be 8 more than the first addr. */
1479 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
1482 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
1487 /* Return the register class of a scratch register needed to copy IN into
1488 or out of a register in CLASS in MODE. If it can be done directly,
1489 NO_REGS is returned. */
1492 secondary_reload_class (class, mode, in)
1493 enum reg_class class;
1494 enum machine_mode mode;
1497 int regno = true_regnum (in);
1499 if (regno >= FIRST_PSEUDO_REGISTER)
1502 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
1504 if (class == GENERAL_REGS || class == BASE_REGS
1505 || (regno >= 0 && INT_REGNO_P (regno)))
1508 /* Constants, memory, and FP registers can go into FP registers. */
1509 if ((regno == -1 || FP_REGNO_P (regno))
1510 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
1513 /* We can copy among the CR registers. */
1514 if ((class == CR_REGS || class == CR0_REGS)
1515 && regno >= 0 && CR_REGNO_P (regno))
1518 /* Otherwise, we need GENERAL_REGS. */
1519 return GENERAL_REGS;
1522 /* Given a comparison operation, return the bit number in CCR to test. We
1523 know this is a valid comparison.
1525 SCC_P is 1 if this is for an scc. That means that %D will have been
1526 used instead of %C, so the bits will be in different places.
1528 Return -1 if OP isn't a valid comparison for some reason. */
1535 enum rtx_code code = GET_CODE (op);
1536 enum machine_mode cc_mode;
1540 if (GET_RTX_CLASS (code) != '<')
1543 cc_mode = GET_MODE (XEXP (op, 0));
1544 cc_regnum = REGNO (XEXP (op, 0));
1545 base_bit = 4 * (cc_regnum - 68);
1547 /* In CCEQmode cases we have made sure that the result is always in the
1548 third bit of the CR field. */
1550 if (cc_mode == CCEQmode)
1551 return base_bit + 3;
1556 return scc_p ? base_bit + 3 : base_bit + 2;
1558 return base_bit + 2;
1560 return base_bit + 1;
1565 /* If floating-point, we will have done a cror to put the bit in the
1566 unordered position. So test that bit. For integer, this is ! LT
1567 unless this is an scc insn. */
1568 return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit;
1571 return cc_mode == CCFPmode || scc_p ? base_bit + 3 : base_bit + 1;
1578 /* Print an operand. Recognize special options, documented below. */
1581 print_operand (file, x, code)
1589 /* These macros test for integers and extract the low-order bits. */
1591 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
1592 && GET_MODE (X) == VOIDmode)
1594 #define INT_LOWPART(X) \
1595 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
1600 /* Write out an instruction after the call which may be replaced
1601 with glue code by the loader. This depends on the AIX version. */
1602 asm_fprintf (file, RS6000_CALL_GLUE);
1606 /* Write the register number of the TOC register. */
1607 fputs (TARGET_MINIMAL_TOC ? reg_names[30] : reg_names[2], file);
1611 /* If X is a constant integer whose low-order 5 bits are zero,
1612 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
1613 in the AIX assembler where "sri" with a zero shift count
1614 write a trash instruction. */
1615 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
1622 /* Low-order 16 bits of constant, unsigned. */
1624 output_operand_lossage ("invalid %%b value");
1626 fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
1630 /* This is an optional cror needed for LE or GE floating-point
1631 comparisons. Otherwise write nothing. */
1632 if ((GET_CODE (x) == LE || GET_CODE (x) == GE)
1633 && GET_MODE (XEXP (x, 0)) == CCFPmode)
1635 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
1637 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
1638 base_bit + 2, base_bit + (GET_CODE (x) == GE));
1643 /* Similar, except that this is for an scc, so we must be able to
1644 encode the test in a single bit that is one. We do the above
1645 for any LE, GE, GEU, or LEU and invert the bit for NE. */
1646 if (GET_CODE (x) == LE || GET_CODE (x) == GE
1647 || GET_CODE (x) == LEU || GET_CODE (x) == GEU)
1649 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
1651 fprintf (file, "cror %d,%d,%d\n\t", base_bit + 3,
1653 base_bit + (GET_CODE (x) == GE || GET_CODE (x) == GEU));
1656 else if (GET_CODE (x) == NE)
1658 int base_bit = 4 * (REGNO (XEXP (x, 0)) - 68);
1660 fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
1661 base_bit + 2, base_bit + 2);
1666 /* X is a CR register. Print the number of the third bit of the CR */
1667 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1668 output_operand_lossage ("invalid %%E value");
1670 fprintf(file, "%d", 4 * (REGNO (x) - 68) + 3);
1674 /* X is a CR register. Print the shift count needed to move it
1675 to the high-order four bits. */
1676 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1677 output_operand_lossage ("invalid %%f value");
1679 fprintf (file, "%d", 4 * (REGNO (x) - 68));
1683 /* Similar, but print the count for the rotate in the opposite
1685 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1686 output_operand_lossage ("invalid %%F value");
1688 fprintf (file, "%d", 32 - 4 * (REGNO (x) - 68));
1692 /* X is a constant integer. If it is negative, print "m",
1693 otherwise print "z". This is to make a aze or ame insn. */
1694 if (GET_CODE (x) != CONST_INT)
1695 output_operand_lossage ("invalid %%G value");
1696 else if (INTVAL (x) >= 0)
1703 /* If constant, output low-order five bits. Otherwise,
1706 fprintf (file, "%d", INT_LOWPART (x) & 31);
1708 print_operand (file, x, 0);
1712 /* Print `i' if this is a constant, else nothing. */
1718 /* Write the bit number in CCR for jump. */
1721 output_operand_lossage ("invalid %%j code");
1723 fprintf (file, "%d", i);
1727 /* Similar, but add one for shift count in rlinm for scc and pass
1728 scc flag to `ccr_bit'. */
1731 output_operand_lossage ("invalid %%J code");
1733 /* If we want bit 31, write a shift count of zero, not 32. */
1734 fprintf (file, "%d", i == 31 ? 0 : i + 1);
1738 /* X must be a constant. Write the 1's complement of the
1741 output_operand_lossage ("invalid %%k value");
1743 fprintf (file, "%d", ~ INT_LOWPART (x));
1747 /* Write second word of DImode or DFmode reference. Works on register
1748 or non-indexed memory only. */
1749 if (GET_CODE (x) == REG)
1750 fprintf (file, "%d", REGNO (x) + 1);
1751 else if (GET_CODE (x) == MEM)
1753 /* Handle possible auto-increment. Since it is pre-increment and
1754 we have already done it, we can just use an offset of four. */
1755 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1756 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1757 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
1759 output_address (plus_constant (XEXP (x, 0), 4));
1764 /* MB value for a mask operand. */
1765 if (! mask_operand (x, VOIDmode))
1766 output_operand_lossage ("invalid %%m value");
1768 val = INT_LOWPART (x);
1770 /* If the high bit is set and the low bit is not, the value is zero.
1771 If the high bit is zero, the value is the first 1 bit we find from
1773 if (val < 0 && (val & 1) == 0)
1775 fprintf (file, "0");
1780 for (i = 1; i < 32; i++)
1781 if ((val <<= 1) < 0)
1783 fprintf (file, "%d", i);
1787 /* Otherwise, look for the first 0 bit from the right. The result is its
1788 number plus 1. We know the low-order bit is one. */
1789 for (i = 0; i < 32; i++)
1790 if (((val >>= 1) & 1) == 0)
1793 /* If we ended in ...01, I would be 0. The correct value is 31, so
1795 fprintf (file, "%d", 31 - i);
1799 /* ME value for a mask operand. */
1800 if (! mask_operand (x, VOIDmode))
1801 output_operand_lossage ("invalid %%m value");
1803 val = INT_LOWPART (x);
1805 /* If the low bit is set and the high bit is not, the value is 31.
1806 If the low bit is zero, the value is the first 1 bit we find from
1808 if ((val & 1) && val >= 0)
1813 else if ((val & 1) == 0)
1815 for (i = 0; i < 32; i++)
1816 if ((val >>= 1) & 1)
1819 /* If we had ....10, I would be 0. The result should be
1820 30, so we need 30 - i. */
1821 fprintf (file, "%d", 30 - i);
1825 /* Otherwise, look for the first 0 bit from the left. The result is its
1826 number minus 1. We know the high-order bit is one. */
1827 for (i = 0; i < 32; i++)
1828 if ((val <<= 1) >= 0)
1831 fprintf (file, "%d", i);
1835 /* Write the number of elements in the vector times 4. */
1836 if (GET_CODE (x) != PARALLEL)
1837 output_operand_lossage ("invalid %%N value");
1839 fprintf (file, "%d", XVECLEN (x, 0) * 4);
1843 /* Similar, but subtract 1 first. */
1844 if (GET_CODE (x) != PARALLEL)
1845 output_operand_lossage ("invalid %%N value");
1847 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
1851 /* X is a CONST_INT that is a power of two. Output the logarithm. */
1853 || (i = exact_log2 (INT_LOWPART (x))) < 0)
1854 output_operand_lossage ("invalid %%p value");
1856 fprintf (file, "%d", i);
1860 /* The operand must be an indirect memory reference. The result
1861 is the register number. */
1862 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
1863 || REGNO (XEXP (x, 0)) >= 32)
1864 output_operand_lossage ("invalid %%P value");
1866 fprintf (file, "%d", REGNO (XEXP (x, 0)));
1870 /* X is a CR register. Print the mask for `mtcrf'. */
1871 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
1872 output_operand_lossage ("invalid %%R value");
1874 fprintf (file, "%d", 128 >> (REGNO (x) - 68));
1878 /* Low 5 bits of 32 - value */
1880 output_operand_lossage ("invalid %%s value");
1882 fprintf (file, "%d", (32 - INT_LOWPART (x)) & 31);
1886 /* Write 12 if this jump operation will branch if true, 4 otherwise.
1887 All floating-point operations except NE branch true and integer
1888 EQ, LT, GT, LTU and GTU also branch true. */
1889 if (GET_RTX_CLASS (GET_CODE (x)) != '<')
1890 output_operand_lossage ("invalid %%t value");
1892 else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
1893 && GET_CODE (x) != NE)
1894 || GET_CODE (x) == EQ
1895 || GET_CODE (x) == LT || GET_CODE (x) == GT
1896 || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
1903 /* Opposite of 't': write 4 if this jump operation will branch if true,
1905 if (GET_RTX_CLASS (GET_CODE (x)) != '<')
1906 output_operand_lossage ("invalid %%t value");
1908 else if ((GET_MODE (XEXP (x, 0)) == CCFPmode
1909 && GET_CODE (x) != NE)
1910 || GET_CODE (x) == EQ
1911 || GET_CODE (x) == LT || GET_CODE (x) == GT
1912 || GET_CODE (x) == LTU || GET_CODE (x) == GTU)
1919 /* High-order 16 bits of constant. */
1921 output_operand_lossage ("invalid %%u value");
1923 fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff);
1927 /* Print `u' if this has an auto-increment or auto-decrement. */
1928 if (GET_CODE (x) == MEM
1929 && (GET_CODE (XEXP (x, 0)) == PRE_INC
1930 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
1935 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
1938 fprintf (file, "%d",
1939 (INT_LOWPART (x) & 0xffff) - 2 * (INT_LOWPART (x) & 0x8000));
1941 print_operand (file, x, 0);
1945 /* If constant, low-order 16 bits of constant, unsigned.
1946 Otherwise, write normally. */
1948 fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
1950 print_operand (file, x, 0);
1954 if (GET_CODE (x) == MEM
1955 && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x, 0)))
1960 /* Like 'L', for third word of TImode */
1961 if (GET_CODE (x) == REG)
1962 fprintf (file, "%d", REGNO (x) + 2);
1963 else if (GET_CODE (x) == MEM)
1965 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1966 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1967 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
1969 output_address (plus_constant (XEXP (x, 0), 8));
1974 /* X is a SYMBOL_REF. Write out the name preceded by a
1975 period and without any trailing data in brackets. Used for function
1976 names. If we are configured for System V (or the embedded ABI) on
1977 the PowerPC, do not emit the period, since those systems do not use
1978 TOCs and the like. */
1979 if (GET_CODE (x) != SYMBOL_REF)
1982 #ifndef USING_SVR4_H
1985 RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
1989 /* Like 'L', for last word of TImode. */
1990 if (GET_CODE (x) == REG)
1991 fprintf (file, "%d", REGNO (x) + 3);
1992 else if (GET_CODE (x) == MEM)
1994 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1995 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1996 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
1998 output_address (plus_constant (XEXP (x, 0), 12));
2003 if (GET_CODE (x) == REG)
2004 fprintf (file, "%s", reg_names[REGNO (x)]);
2005 else if (GET_CODE (x) == MEM)
2007 /* We need to handle PRE_INC and PRE_DEC here, since we need to
2008 know the width from the mode. */
2009 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
2010 fprintf (file, "%d(%d)", GET_MODE_SIZE (GET_MODE (x)),
2011 REGNO (XEXP (XEXP (x, 0), 0)));
2012 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
2013 fprintf (file, "%d(%d)", - GET_MODE_SIZE (GET_MODE (x)),
2014 REGNO (XEXP (XEXP (x, 0), 0)));
2016 output_address (XEXP (x, 0));
2019 output_addr_const (file, x);
2023 output_operand_lossage ("invalid %%xn code");
2027 /* Print the address of an operand. */
2030 print_operand_address (file, x)
2034 if (GET_CODE (x) == REG)
2035 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
2036 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2038 output_addr_const (file, x);
2039 /* When TARGET_MINIMAL_TOC, use the indirected toc table pointer instead
2040 of the toc pointer. */
2041 #ifdef TARGET_NO_TOC
2046 fprintf (file, "(%s)", reg_names[ TARGET_MINIMAL_TOC ? 30 : 2 ]);
2048 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
2050 if (REGNO (XEXP (x, 0)) == 0)
2051 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
2052 reg_names[ REGNO (XEXP (x, 0)) ]);
2054 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
2055 reg_names[ REGNO (XEXP (x, 1)) ]);
2057 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
2058 fprintf (file, "%d(%s)", INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
2059 else if (TARGET_ELF && !TARGET_64BIT && GET_CODE (x) == LO_SUM
2060 && GET_CODE (XEXP (x, 0)) == REG && CONSTANT_P (XEXP (x, 1)))
2062 output_addr_const (file, XEXP (x, 1));
2063 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
2069 /* This page contains routines that are used to determine what the function
2070 prologue and epilogue code will do and write them out. */
2072 /* Return the first fixed-point register that is required to be saved. 32 if
2076 first_reg_to_save ()
2080 /* Find lowest numbered live register. */
2081 for (first_reg = 13; first_reg <= 31; first_reg++)
2082 if (regs_ever_live[first_reg])
2085 /* If profiling, then we must save/restore every register that contains
2086 a parameter before/after the .mcount call. Use registers from 30 down
2087 to 23 to do this. Don't use the frame pointer in reg 31.
2089 For now, save enough room for all of the parameter registers. */
2090 #ifndef USING_SVR4_H
2099 /* Similar, for FP regs. */
2102 first_fp_reg_to_save ()
2106 /* Find lowest numbered live register. */
2107 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
2108 if (regs_ever_live[first_reg])
2114 /* Return non-zero if this function makes calls. */
2117 rs6000_makes_calls ()
2121 /* If we are profiling, we will be making a call to mcount. */
2125 for (insn = get_insns (); insn; insn = next_insn (insn))
2126 if (GET_CODE (insn) == CALL_INSN)
2133 /* Calculate the stack information for the current function. This is
2134 complicated by having two separate calling sequences, the AIX calling
2135 sequence and the V.4 calling sequence.
2137 AIX stack frames look like:
2139 SP----> +---------------------------------------+
2140 | back chain to caller | 0
2141 +---------------------------------------+
2143 +---------------------------------------+
2145 +---------------------------------------+
2146 | reserved for compilers | 12
2147 +---------------------------------------+
2148 | reserved for binders | 16
2149 +---------------------------------------+
2150 | saved TOC pointer | 20
2151 +---------------------------------------+
2152 | Parameter save area (P) | 24
2153 +---------------------------------------+
2154 | Alloca space (A) | 24+P
2155 +---------------------------------------+
2156 | Local variable space (L) | 24+P+A
2157 +---------------------------------------+
2158 | Save area for GP registers (G) | 24+P+A+L
2159 +---------------------------------------+
2160 | Save area for FP registers (F) | 24+P+A+L+G
2161 +---------------------------------------+
2162 old SP->| back chain to caller's caller |
2163 +---------------------------------------+
2165 V.4 stack frames look like:
2167 SP----> +---------------------------------------+
2168 | back chain to caller | 0
2169 +---------------------------------------+
2170 | caller's saved LR | 4
2171 +---------------------------------------+
2172 | Parameter save area (P) | 8
2173 +---------------------------------------+
2174 | Alloca space (A) | 8+P
2175 +---------------------------------------+
2176 | Varargs save area (V) | 8+P+A
2177 +---------------------------------------+
2178 | Local variable space (L) | 8+P+A+V
2179 +---------------------------------------+
2180 | saved CR (C) | 8+P+A+V+L
2181 +---------------------------------------+
2182 | Save area for GP registers (G) | 8+P+A+V+L+C
2183 +---------------------------------------+
2184 | Save area for FP registers (F) | 8+P+A+V+L+C+G
2185 +---------------------------------------+
2186 old SP->| back chain to caller's caller |
2187 +---------------------------------------+
2191 rs6000_stack_info ()
2193 static rs6000_stack_t info, zero_info;
2194 rs6000_stack_t *info_ptr = &info;
2195 int reg_size = TARGET_64BIT ? 8 : 4;
2198 /* Zero all fields portably */
2201 /* Select which calling sequence */
2202 #ifdef TARGET_V4_CALLS
2203 if (TARGET_V4_CALLS)
2204 info_ptr->v4_call_p = v4_call_p = 1;
2207 /* Calculate which registers need to be saved & save area size */
2208 info_ptr->first_gp_reg_save = first_reg_to_save ();
2209 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
2211 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
2212 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
2214 /* Does this function call anything? */
2215 info_ptr->calls_p = rs6000_makes_calls ();
2217 /* Determine if we need to save the link register */
2218 if (regs_ever_live[65] || profile_flag
2219 #ifdef TARGET_RELOCATABLE
2220 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
2222 || (info_ptr->first_fp_reg_save != 64
2223 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
2224 || (v4_call_p && current_function_calls_alloca)
2225 || info_ptr->calls_p)
2227 info_ptr->lr_save_p = 1;
2228 regs_ever_live[65] = 1;
2231 /* Determine if we need to save the condition code registers */
2232 if (regs_ever_live[70] || regs_ever_live[71] || regs_ever_live[72])
2234 info_ptr->cr_save_p = 1;
2236 info_ptr->cr_size = reg_size;
2239 /* Determine various sizes */
2240 info_ptr->reg_size = reg_size;
2241 info_ptr->fixed_size = RS6000_SAVE_AREA;
2242 info_ptr->varargs_size = RS6000_VARARGS_AREA;
2243 info_ptr->vars_size = ALIGN (get_frame_size (), 8);
2244 info_ptr->parm_size = ALIGN (current_function_outgoing_args_size, 8);
2245 info_ptr->save_size = ALIGN (info_ptr->fp_size + info_ptr->gp_size + info_ptr->cr_size, 8);
2246 info_ptr->total_size = ALIGN (info_ptr->vars_size
2247 + info_ptr->parm_size
2248 + info_ptr->save_size
2249 + info_ptr->varargs_size
2250 + info_ptr->fixed_size, STACK_BOUNDARY / BITS_PER_UNIT);
2252 /* Determine if we need to allocate any stack frame.
2253 For AIX We need to push the stack if a frame pointer is needed (because
2254 the stack might be dynamically adjusted), if we are debugging, if the
2255 total stack size is more than 220 bytes, or if we make calls.
2257 For V.4 we don't have the stack cushion that AIX uses, but assume that
2258 the debugger can handle stackless frames. */
2260 if (info_ptr->calls_p)
2261 info_ptr->push_p = 1;
2264 info_ptr->push_p = (info_ptr->total_size > info_ptr->fixed_size
2265 || info_ptr->lr_save_p);
2268 info_ptr->push_p = (frame_pointer_needed
2269 || write_symbols != NO_DEBUG
2270 || info_ptr->total_size > 220);
2272 /* Calculate the offsets */
2273 info_ptr->fp_save_offset = - info_ptr->fp_size;
2274 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
2277 info_ptr->cr_save_offset = info_ptr->gp_save_offset - reg_size;
2278 info_ptr->lr_save_offset = reg_size;
2282 info_ptr->cr_save_offset = 4;
2283 info_ptr->lr_save_offset = 8;
2286 /* Zero offsets if we're not saving those registers */
2287 if (!info_ptr->fp_size)
2288 info_ptr->fp_save_offset = 0;
2290 if (!info_ptr->gp_size)
2291 info_ptr->gp_save_offset = 0;
2293 if (!info_ptr->lr_save_p)
2294 info_ptr->lr_save_offset = 0;
2296 if (!info_ptr->cr_save_p)
2297 info_ptr->cr_save_offset = 0;
2303 debug_stack_info (info)
2304 rs6000_stack_t *info;
2307 info = rs6000_stack_info ();
2309 fprintf (stderr, "\nStack information for function %s:\n",
2310 ((current_function_decl && DECL_NAME (current_function_decl))
2311 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
2314 if (info->first_gp_reg_save != 32)
2315 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
2317 if (info->first_fp_reg_save != 64)
2318 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
2320 if (info->lr_save_p)
2321 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
2323 if (info->cr_save_p)
2324 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
2327 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
2330 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
2332 if (info->v4_call_p)
2333 fprintf (stderr, "\tv4_call_p = %5d\n", info->v4_call_p);
2335 if (info->gp_save_offset)
2336 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
2338 if (info->fp_save_offset)
2339 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
2341 if (info->lr_save_offset)
2342 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
2344 if (info->cr_save_offset)
2345 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
2347 if (info->varargs_save_offset)
2348 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
2350 if (info->total_size)
2351 fprintf (stderr, "\ttotal_size = %5d\n", info->total_size);
2353 if (info->varargs_size)
2354 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
2356 if (info->vars_size)
2357 fprintf (stderr, "\tvars_size = %5d\n", info->vars_size);
2359 if (info->parm_size)
2360 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
2362 if (info->fixed_size)
2363 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
2366 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
2369 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
2372 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
2374 if (info->save_size)
2375 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
2377 if (info->reg_size != 4)
2378 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
2380 fprintf (stderr, "\n");
2386 /* Write out a System V.4 style traceback table before the prologue
2388 At present, only emit the basic tag table (ie, do not emit tag_types other
2389 than 0, which might use more than 1 tag word).
2391 The first tag word looks like:
2394 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
2395 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2396 | 0 |ver| tag |e|s| alloca | # fprs | # gprs |s|l|c|f|
2397 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
2402 svr4_traceback (file, name, decl)
2406 rs6000_stack_t *info = rs6000_stack_info ();
2408 long version = 0; /* version number */
2409 long tag_type = 0; /* function type */
2410 long extended_tag = 0; /* additional tag words needed */
2411 long spare = 0; /* reserved for future use */
2412 long fpscr_max = 0; /* 1 if the function has a FPSCR save word */
2413 long fpr_max = 64 - info->first_fp_reg_save; /* # of floating point registers saved */
2414 long gpr_max = 32 - info->first_gp_reg_save; /* # of general purpose registers saved */
2415 long alloca_reg; /* stack/frame register */
2417 if (frame_pointer_needed)
2420 else if (info->push_p != 0)
2426 tag = ((version << 24)
2428 | (extended_tag << 20)
2430 | (alloca_reg << 14)
2433 | (info->push_p << 3)
2434 | (info->lr_save_p << 2)
2435 | (info->cr_save_p << 1)
2436 | (fpscr_max << 0));
2438 fprintf (file, "\t.long 0x%lx\n", tag);
2441 #endif /* USING_SVR4_H */
2443 /* Write function prologue. */
2445 output_prolog (file, size)
2449 rs6000_stack_t *info = rs6000_stack_info ();
2450 char *store_reg = (TARGET_64BIT) ? "\tstd %s,%d(%s)" : "\t{st|stw} %s,%d(%s)\n";
2452 if (TARGET_DEBUG_STACK)
2453 debug_stack_info (info);
2455 /* Write .extern for any function we will call to save and restore fp
2457 #ifndef USING_SVR4_H
2458 if (info->first_fp_reg_save < 62)
2459 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
2460 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
2461 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
2464 /* Write .extern for truncation routines, if needed. */
2465 if (rs6000_trunc_used && ! trunc_defined)
2467 fprintf (file, "\t.extern .%s\n\t.extern .%s\n",
2468 RS6000_ITRUNC, RS6000_UITRUNC);
2472 /* Write .extern for AIX common mode routines, if needed. */
2473 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
2475 fputs ("\t.extern __mulh\n", file);
2476 fputs ("\t.extern __mull\n", file);
2477 fputs ("\t.extern __divss\n", file);
2478 fputs ("\t.extern __divus\n", file);
2479 fputs ("\t.extern __quoss\n", file);
2480 fputs ("\t.extern __quous\n", file);
2481 common_mode_defined = 1;
2484 /* If we use the link register, get it into r0. */
2485 if (info->lr_save_p)
2486 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
2488 /* If we need to save CR, put it into r12. */
2489 if (info->cr_save_p)
2490 asm_fprintf (file, "\tmfcr %s\n", reg_names[12]);
2492 /* Do any required saving of fpr's. If only one or two to save, do it
2493 ourself. Otherwise, call function. Note that since they are statically
2494 linked, we do not need a nop following them. */
2495 if (FP_SAVE_INLINE (info->first_fp_reg_save))
2497 int regno = info->first_fp_reg_save;
2498 int loc = info->fp_save_offset;
2500 for ( ; regno < 64; regno++, loc += 8)
2501 asm_fprintf (file, "\tstfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[1]);
2503 else if (info->first_fp_reg_save != 64)
2504 asm_fprintf (file, "\tbl %s%d%s\n", SAVE_FP_PREFIX,
2505 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
2507 /* Now save gpr's. */
2508 if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT)
2510 int regno = info->first_gp_reg_save;
2511 int loc = info->gp_save_offset;
2512 int reg_size = (TARGET_64BIT) ? 8 : 4;
2514 for ( ; regno < 32; regno++, loc += reg_size)
2515 asm_fprintf (file, store_reg, reg_names[regno], loc, reg_names[1]);
2518 else if (info->first_gp_reg_save != 32)
2519 asm_fprintf (file, "\t{stm|stmw} %s,%d(%s)\n",
2520 reg_names[info->first_gp_reg_save],
2521 info->gp_save_offset,
2524 /* Save lr if we used it. */
2525 if (info->lr_save_p)
2526 asm_fprintf (file, store_reg, reg_names[0], info->lr_save_offset, reg_names[1]);
2528 /* Save CR if we use any that must be preserved. */
2529 if (info->cr_save_p)
2530 asm_fprintf (file, store_reg, reg_names[12], info->cr_save_offset, reg_names[1]);
2532 /* Update stack and set back pointer. */
2535 if (info->total_size < 32767)
2537 (TARGET_64BIT) ? "\tstdu %s,%d(%s)\n" : "\t{stu|stwu} %s,%d(%s)\n",
2538 reg_names[1], - info->total_size, reg_names[1]);
2541 int neg_size = - info->total_size;
2542 asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
2543 reg_names[0], (neg_size >> 16) & 0xffff,
2544 reg_names[0], reg_names[0], neg_size & 0xffff);
2546 (TARGET_64BIT) ? "\tstdux %s,%s,%s\n" : "\t{stux|stwux} %s,%s,%s\n",
2547 reg_names[1], reg_names[1], reg_names[0]);
2551 /* Set frame pointer, if needed. */
2552 if (frame_pointer_needed)
2553 asm_fprintf (file, "\tmr %s,%s\n", reg_names[31], reg_names[1]);
2555 /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the
2556 TOC_TABLE address into register 30. */
2557 if (TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
2562 if (TARGET_RELOCATABLE)
2564 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
2565 fprintf (file, "\tbl ");
2566 assemble_name (file, buf);
2567 fprintf (file, "\n");
2569 ASM_OUTPUT_INTERNAL_LABEL (file, "LCF", rs6000_pic_labelno);
2570 fprintf (file, "\tmflr %s\n", reg_names[30]);
2572 if (TARGET_POWERPC64)
2573 fprintf (file, "\tld");
2574 else if (TARGET_NEW_MNEMONICS)
2575 fprintf (file, "\tlwz");
2577 fprintf (file, "\tl");
2579 fprintf (file, " %s,(", reg_names[0]);
2580 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
2581 assemble_name (file, buf);
2582 fprintf (file, "-");
2583 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
2584 assemble_name (file, buf);
2585 fprintf (file, ")(%s)\n", reg_names[30]);
2586 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
2587 reg_names[30], reg_names[0], reg_names[30]);
2588 rs6000_pic_labelno++;
2590 else if (!TARGET_64BIT)
2592 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
2593 asm_fprintf (file, "\t{cau|addis} %s,%s,", reg_names[30], reg_names[0]);
2594 assemble_name (file, buf);
2595 asm_fprintf (file, "@ha\n");
2596 if (TARGET_NEW_MNEMONICS)
2598 asm_fprintf (file, "\taddi %s,%s,", reg_names[30], reg_names[30]);
2599 assemble_name (file, buf);
2600 asm_fprintf (file, "@l\n");
2604 asm_fprintf (file, "\tcal %s,", reg_names[30]);
2605 assemble_name (file, buf);
2606 asm_fprintf (file, "@l(%s)\n", reg_names[30]);
2612 #else /* !USING_SVR4_H */
2613 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 0);
2614 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[30]);
2615 assemble_name (file, buf);
2616 asm_fprintf (file, "(%s)\n", reg_names[2]);
2617 #endif /* USING_SVR4_H */
2621 /* Write function epilogue. */
2624 output_epilog (file, size)
2628 rs6000_stack_t *info = rs6000_stack_info ();
2629 char *load_reg = (TARGET_64BIT) ? "\tld %s,%d(%s)" : "\t{l|lwz} %s,%d(%s)\n";
2630 rtx insn = get_last_insn ();
2632 /* If the last insn was a BARRIER, we don't have to write anything except
2634 if (GET_CODE (insn) == NOTE)
2635 insn = prev_nonnote_insn (insn);
2636 if (insn == 0 || GET_CODE (insn) != BARRIER)
2638 /* If we have a frame pointer, a call to alloca, or a large stack
2639 frame, restore the old stack pointer using the backchain. Otherwise,
2640 we know what size to update it with. */
2641 if (frame_pointer_needed || current_function_calls_alloca
2642 || info->total_size > 32767)
2643 asm_fprintf (file, load_reg, reg_names[1], 0, reg_names[1]);
2644 else if (info->push_p)
2646 if (TARGET_NEW_MNEMONICS)
2647 asm_fprintf (file, "\taddi %s,%s,%d\n", reg_names[1], reg_names[1], info->total_size);
2649 asm_fprintf (file, "\tcal %s,%d(%s)\n", reg_names[1], info->total_size, reg_names[1]);
2652 /* Get the old lr if we saved it. */
2653 if (info->lr_save_p)
2654 asm_fprintf (file, load_reg, reg_names[0], info->lr_save_offset, reg_names[1]);
2656 /* Get the old cr if we saved it. */
2657 if (info->cr_save_p)
2658 asm_fprintf (file, load_reg, reg_names[12], info->cr_save_offset, reg_names[1]);
2660 /* Set LR here to try to overlap restores below. */
2661 if (info->lr_save_p)
2662 asm_fprintf (file, "\tmtlr %s\n", reg_names[0]);
2664 /* Restore gpr's. */
2665 if (! TARGET_MULTIPLE || info->first_gp_reg_save == 31 || TARGET_64BIT)
2667 int regno = info->first_gp_reg_save;
2668 int loc = info->gp_save_offset;
2669 int reg_size = (TARGET_64BIT) ? 8 : 4;
2671 for ( ; regno < 32; regno++, loc += reg_size)
2672 asm_fprintf (file, load_reg, reg_names[regno], loc, reg_names[1]);
2675 else if (info->first_gp_reg_save != 32)
2676 asm_fprintf (file, "\t{lm|lmw} %s,%d(%s)\n",
2677 reg_names[info->first_gp_reg_save],
2678 info->gp_save_offset,
2681 /* Restore fpr's if we can do it without calling a function. */
2682 if (FP_SAVE_INLINE (info->first_fp_reg_save))
2684 int regno = info->first_fp_reg_save;
2685 int loc = info->fp_save_offset;
2687 for ( ; regno < 64; regno++, loc += 8)
2688 asm_fprintf (file, "\tlfd %s,%d(%s)\n", reg_names[regno], loc, reg_names[1]);
2691 /* If we saved cr, restore it here. Just those of cr2, cr3, and cr4
2693 if (info->cr_save_p)
2694 asm_fprintf (file, "\tmtcrf %d,%s\n",
2695 (regs_ever_live[70] != 0) * 0x20
2696 + (regs_ever_live[71] != 0) * 0x10
2697 + (regs_ever_live[72] != 0) * 0x8, reg_names[12]);
2699 /* If we have to restore more than two FP registers, branch to the
2700 restore function. It will return to our caller. */
2701 if (info->first_fp_reg_save != 64 && !FP_SAVE_INLINE (info->first_fp_reg_save))
2702 asm_fprintf (file, "\tb %s%d%s\n", RESTORE_FP_PREFIX,
2703 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
2705 asm_fprintf (file, "\t{br|blr}\n");
2708 /* Output a traceback table here. See /usr/include/sys/debug.h for info
2711 We don't output a traceback table if -finhibit-size-directive was
2712 used. The documentation for -finhibit-size-directive reads
2713 ``don't output a @code{.size} assembler directive, or anything
2714 else that would cause trouble if the function is split in the
2715 middle, and the two halves are placed at locations far apart in
2716 memory.'' The traceback table has this property, since it
2717 includes the offset from the start of the function to the
2718 traceback table itself.
2720 System V.4 Powerpc's (and the embedded ABI derived from it) use a
2721 different traceback table located before the prologue. */
2722 #ifndef USING_SVR4_H
2723 if (! flag_inhibit_size_directive)
2725 char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
2726 int fixed_parms, float_parms, parm_info;
2729 /* Need label immediately before tbtab, so we can compute its offset
2730 from the function start. */
2733 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
2734 ASM_OUTPUT_LABEL (file, fname);
2736 /* The .tbtab pseudo-op can only be used for the first eight
2737 expressions, since it can't handle the possibly variable
2738 length fields that follow. However, if you omit the optional
2739 fields, the assembler outputs zeros for all optional fields
2740 anyways, giving each variable length field is minimum length
2741 (as defined in sys/debug.h). Thus we can not use the .tbtab
2742 pseudo-op at all. */
2744 /* An all-zero word flags the start of the tbtab, for debuggers
2745 that have to find it by searching forward from the entry
2746 point or from the current pc. */
2747 fprintf (file, "\t.long 0\n");
2749 /* Tbtab format type. Use format type 0. */
2750 fprintf (file, "\t.byte 0,");
2752 /* Language type. Unfortunately, there doesn't seem to be any
2753 official way to get this info, so we use language_string. C
2754 is 0. C++ is 9. No number defined for Obj-C, so use the
2755 value for C for now. */
2756 if (! strcmp (language_string, "GNU C")
2757 || ! strcmp (language_string, "GNU Obj-C"))
2759 else if (! strcmp (language_string, "GNU F77"))
2761 else if (! strcmp (language_string, "GNU Ada"))
2763 else if (! strcmp (language_string, "GNU PASCAL"))
2765 else if (! strcmp (language_string, "GNU C++"))
2769 fprintf (file, "%d,", i);
2771 /* 8 single bit fields: global linkage (not set for C extern linkage,
2772 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
2773 from start of procedure stored in tbtab, internal function, function
2774 has controlled storage, function has no toc, function uses fp,
2775 function logs/aborts fp operations. */
2776 /* Assume that fp operations are used if any fp reg must be saved. */
2777 fprintf (file, "%d,", (1 << 5) | ((info->first_fp_reg_save != 64) << 1));
2779 /* 6 bitfields: function is interrupt handler, name present in
2780 proc table, function calls alloca, on condition directives
2781 (controls stack walks, 3 bits), saves condition reg, saves
2783 /* The `function calls alloca' bit seems to be set whenever reg 31 is
2784 set up as a frame pointer, even when there is no alloca call. */
2785 fprintf (file, "%d,",
2786 ((1 << 6) | (frame_pointer_needed << 5)
2787 | (info->cr_save_p << 1) | (info->lr_save_p)));
2789 /* 3 bitfields: saves backchain, spare bit, number of fpr saved
2791 fprintf (file, "%d,",
2792 (info->push_p << 7) | (64 - info->first_fp_reg_save));
2794 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
2795 fprintf (file, "%d,", (32 - first_reg_to_save ()));
2798 /* Compute the parameter info from the function decl argument
2801 int next_parm_info_bit;
2803 next_parm_info_bit = 31;
2808 for (decl = DECL_ARGUMENTS (current_function_decl);
2809 decl; decl = TREE_CHAIN (decl))
2811 rtx parameter = DECL_INCOMING_RTL (decl);
2812 enum machine_mode mode = GET_MODE (parameter);
2814 if (GET_CODE (parameter) == REG)
2816 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2824 else if (mode == DFmode)
2829 /* If only one bit will fit, don't or in this entry. */
2830 if (next_parm_info_bit > 0)
2831 parm_info |= (bits << (next_parm_info_bit - 1));
2832 next_parm_info_bit -= 2;
2836 fixed_parms += ((GET_MODE_SIZE (mode)
2837 + (UNITS_PER_WORD - 1))
2839 next_parm_info_bit -= 1;
2845 /* Number of fixed point parameters. */
2846 /* This is actually the number of words of fixed point parameters; thus
2847 an 8 byte struct counts as 2; and thus the maximum value is 8. */
2848 fprintf (file, "%d,", fixed_parms);
2850 /* 2 bitfields: number of floating point parameters (7 bits), parameters
2852 /* This is actually the number of fp registers that hold parameters;
2853 and thus the maximum value is 13. */
2854 /* Set parameters on stack bit if parameters are not in their original
2855 registers, regardless of whether they are on the stack? Xlc
2856 seems to set the bit when not optimizing. */
2857 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
2859 /* Optional fields follow. Some are variable length. */
2861 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
2863 /* There is an entry for each parameter in a register, in the order that
2864 they occur in the parameter list. Any intervening arguments on the
2865 stack are ignored. If the list overflows a long (max possible length
2866 34 bits) then completely leave off all elements that don't fit. */
2867 /* Only emit this long if there was at least one parameter. */
2868 if (fixed_parms || float_parms)
2869 fprintf (file, "\t.long %d\n", parm_info);
2871 /* Offset from start of code to tb table. */
2872 fprintf (file, "\t.long ");
2873 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
2874 RS6000_OUTPUT_BASENAME (file, fname);
2875 fprintf (file, "-.");
2876 RS6000_OUTPUT_BASENAME (file, fname);
2877 fprintf (file, "\n");
2879 /* Interrupt handler mask. */
2880 /* Omit this long, since we never set the interrupt handler bit
2883 /* Number of CTL (controlled storage) anchors. */
2884 /* Omit this long, since the has_ctl bit is never set above. */
2886 /* Displacement into stack of each CTL anchor. */
2887 /* Omit this list of longs, because there are no CTL anchors. */
2889 /* Length of function name. */
2890 fprintf (file, "\t.short %d\n", strlen (fname));
2892 /* Function name. */
2893 assemble_string (fname, strlen (fname));
2895 /* Register for alloca automatic storage; this is always reg 31.
2896 Only emit this if the alloca bit was set above. */
2897 if (frame_pointer_needed)
2898 fprintf (file, "\t.byte 31\n");
2900 #endif /* !USING_SVR4_H */
2902 /* Reset varargs indicator */
2903 rs6000_sysv_varargs_p = 0;
2906 /* Output a TOC entry. We derive the entry name from what is
2910 output_toc (file, x, labelno)
2924 if (TARGET_MINIMAL_TOC)
2926 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
2927 fprintf (file, "%d = .-", labelno);
2928 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCTOC");
2929 fprintf (file, "1\n");
2932 #endif /* USING_SVR4_H */
2933 ASM_OUTPUT_INTERNAL_LABEL (file, "LC", labelno);
2935 /* Handle FP constants specially. Note that if we have a minimal
2936 TOC, things we put here aren't actually in the TOC, so we can allow
2938 if (GET_CODE (x) == CONST_DOUBLE
2939 && GET_MODE (x) == DFmode
2940 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
2945 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2946 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
2947 if (TARGET_MINIMAL_TOC)
2948 fprintf (file, "\t.long %ld\n\t.long %ld\n", l[0], l[1]);
2950 fprintf (file, "\t.tc FD_%lx_%lx[TC],%ld,%ld\n",
2951 l[0], l[1], l[0], l[1]);
2954 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode
2955 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC))
2957 rtx val = operand_subword (x, 0, 0, SFmode);
2959 if (val == 0 || GET_CODE (val) != CONST_INT)
2962 if (TARGET_MINIMAL_TOC)
2963 fprintf (file, "\t.long %d\n", INTVAL (val));
2965 fprintf (file, "\t.tc FS_%x[TC],%d\n", INTVAL (val), INTVAL (val));
2969 if (GET_CODE (x) == CONST)
2971 base = XEXP (XEXP (x, 0), 0);
2972 offset = INTVAL (XEXP (XEXP (x, 0), 1));
2975 if (GET_CODE (base) == SYMBOL_REF)
2976 name = XSTR (base, 0);
2977 else if (GET_CODE (base) == LABEL_REF)
2978 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
2979 else if (GET_CODE (base) == CODE_LABEL)
2980 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
2984 if (TARGET_MINIMAL_TOC)
2985 fprintf (file, "\t.long ");
2988 fprintf (file, "\t.tc ");
2989 RS6000_OUTPUT_BASENAME (file, name);
2992 fprintf (file, ".N%d", - offset);
2994 fprintf (file, ".P%d", offset);
2996 fprintf (file, "[TC],");
2998 output_addr_const (file, x);
2999 fprintf (file, "\n");
3002 /* Output an assembler pseudo-op to write an ASCII string of N characters
3003 starting at P to FILE.
3005 On the RS/6000, we have to do this using the .byte operation and
3006 write out special characters outside the quoted string.
3007 Also, the assembler is broken; very long strings are truncated,
3008 so we must artificially break them up early. */
3011 output_ascii (file, p, n)
3017 int i, count_string;
3018 char *for_string = "\t.byte \"";
3019 char *for_decimal = "\t.byte ";
3020 char *to_close = NULL;
3023 for (i = 0; i < n; i++)
3026 if (c >= ' ' && c < 0177)
3029 fputs (for_string, file);
3032 /* Write two quotes to get one. */
3040 for_decimal = "\"\n\t.byte ";
3044 if (count_string >= 512)
3046 fputs (to_close, file);
3048 for_string = "\t.byte \"";
3049 for_decimal = "\t.byte ";
3057 fputs (for_decimal, file);
3058 fprintf (file, "%d", c);
3060 for_string = "\n\t.byte \"";
3067 /* Now close the string if we have written one. Then end the line. */
3069 fprintf (file, to_close);
3072 /* Generate a unique section name for FILENAME for a section type
3073 represented by SECTION_DESC. Output goes into BUF.
3075 SECTION_DESC can be any string, as long as it is different for each
3076 possible section type.
3078 We name the section in the same manner as xlc. The name begins with an
3079 underscore followed by the filename (after stripping any leading directory
3080 names) with the last period replaced by the string SECTION_DESC. If
3081 FILENAME does not contain a period, SECTION_DESC is appended to the end of
3085 rs6000_gen_section_name (buf, filename, section_desc)
3090 char *q, *after_last_slash, *last_period;
3094 after_last_slash = filename;
3095 for (q = filename; *q; q++)
3098 after_last_slash = q + 1;
3103 len = strlen (after_last_slash) + strlen (section_desc) + 2;
3104 *buf = (char *) permalloc (len);
3109 for (q = after_last_slash; *q; q++)
3111 if (q == last_period)
3113 strcpy (p, section_desc);
3114 p += strlen (section_desc);
3117 else if (isalnum (*q))
3121 if (last_period == 0)
3122 strcpy (p, section_desc);
3127 /* Write function profiler code. */
3130 output_function_profiler (file, labelno)
3137 /* The last used parameter register. */
3142 /* Set up a TOC entry for the profiler label. */
3144 ASM_OUTPUT_INTERNAL_LABEL (file, "LPC", labelno);
3145 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
3146 if (TARGET_MINIMAL_TOC)
3148 fprintf (file, "\t.long ");
3149 assemble_name (file, buf);
3150 fprintf (file, "\n");
3154 fprintf (file, "\t.tc\t");
3155 assemble_name (file, buf);
3156 fprintf (file, "[TC],");
3157 assemble_name (file, buf);
3158 fprintf (file, "\n");
3162 /* Figure out last used parameter register. The proper thing to do is
3163 to walk incoming args of the function. A function might have live
3164 parameter registers even if it has no incoming args. */
3166 for (last_parm_reg = 10;
3167 last_parm_reg > 2 && ! regs_ever_live [last_parm_reg];
3171 /* Save parameter registers in regs 23-30. Don't overwrite reg 31, since
3172 it might be set up as the frame pointer. */
3174 for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
3175 fprintf (file, "\tai %d,%d,0\n", j, i);
3177 /* Load location address into r3, and call mcount. */
3179 ASM_GENERATE_INTERNAL_LABEL (buf, "LPC", labelno);
3180 fprintf (file, "\tl 3,");
3181 assemble_name (file, buf);
3182 fprintf (file, "(2)\n\tbl .mcount\n");
3184 /* Restore parameter registers. */
3186 for (i = 3, j = 30; i <= last_parm_reg; i++, j--)
3187 fprintf (file, "\tai %d,%d,0\n", i, j);
3191 /* Adjust the cost of a scheduling dependency. Return the new cost of
3192 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3195 rs6000_adjust_cost (insn, link, dep_insn, cost)
3201 if (! recog_memoized (insn))
3204 if (REG_NOTE_KIND (link) != 0)
3207 if (REG_NOTE_KIND (link) == 0)
3209 /* Data dependency; DEP_INSN writes a register that INSN reads some
3212 /* Tell the first scheduling pass about the latency between a mtctr
3213 and bctr (and mtlr and br/blr). The first scheduling pass will not
3214 know about this latency since the mtctr instruction, which has the
3215 latency associated to it, will be generated by reload. */
3216 if (get_attr_type (insn) == TYPE_JMPREG)
3217 return TARGET_POWER ? 5 : 4;
3219 /* Fall out to return default cost. */