1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
45 #include "integrate.h"
51 #include "target-def.h"
52 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
56 #include "tree-gimple.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack {
76 int first_gp_reg_save; /* first callee saved GP register used */
77 int first_fp_reg_save; /* first callee saved FP register used */
78 int first_altivec_reg_save; /* first callee saved AltiVec register used */
79 int lr_save_p; /* true if the link reg needs to be saved */
80 int cr_save_p; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask; /* mask of vec registers to save */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset; /* offset to save the varargs registers */
95 int ehrd_offset; /* offset to EH return data */
96 int reg_size; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
111 int spe_64bit_regs_used;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct machine_function GTY(())
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset;
131 /* Target cpu type */
133 enum processor_type rs6000_cpu;
134 struct rs6000_cpu_select rs6000_select[3] =
136 /* switch name, tune arch */
137 { (const char *)0, "--with-cpu=", 1, 1 },
138 { (const char *)0, "-mcpu=", 1, 1 },
139 { (const char *)0, "-mtune=", 1, 0 },
142 static GTY(()) bool rs6000_cell_dont_microcode;
144 /* Always emit branch hint bits. */
145 static GTY(()) bool rs6000_always_hint;
147 /* Schedule instructions for group formation. */
148 static GTY(()) bool rs6000_sched_groups;
150 /* Align branch targets. */
151 static GTY(()) bool rs6000_align_branch_targets;
153 /* Support for -msched-costly-dep option. */
154 const char *rs6000_sched_costly_dep_str;
155 enum rs6000_dependence_cost rs6000_sched_costly_dep;
157 /* Support for -minsert-sched-nops option. */
158 const char *rs6000_sched_insert_nops_str;
159 enum rs6000_nop_insertion rs6000_sched_insert_nops;
161 /* Support targetm.vectorize.builtin_mask_for_load. */
162 static GTY(()) tree altivec_builtin_mask_for_load;
164 /* Size of long double. */
165 int rs6000_long_double_type_size;
167 /* IEEE quad extended precision long double. */
170 /* Whether -mabi=altivec has appeared. */
171 int rs6000_altivec_abi;
173 /* Nonzero if we want SPE ABI extensions. */
176 /* Nonzero if floating point operations are done in the GPRs. */
177 int rs6000_float_gprs = 0;
179 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
180 int rs6000_darwin64_abi;
182 /* Set to nonzero once AIX common-mode calls have been defined. */
183 static GTY(()) int common_mode_defined;
185 /* Save information from a "cmpxx" operation until the branch or scc is
187 rtx rs6000_compare_op0, rs6000_compare_op1;
188 int rs6000_compare_fp_p;
190 /* Label number of label created for -mrelocatable, to call to so we can
191 get the address of the GOT section */
192 int rs6000_pic_labelno;
195 /* Which abi to adhere to */
196 const char *rs6000_abi_name;
198 /* Semantics of the small data area */
199 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
201 /* Which small data model to use */
202 const char *rs6000_sdata_name = (char *)0;
204 /* Counter for labels which are to be placed in .fixup. */
205 int fixuplabelno = 0;
208 /* Bit size of immediate TLS offsets and string from which it is decoded. */
209 int rs6000_tls_size = 32;
210 const char *rs6000_tls_size_string;
212 /* ABI enumeration available for subtarget to use. */
213 enum rs6000_abi rs6000_current_abi;
215 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
219 const char *rs6000_debug_name;
220 int rs6000_debug_stack; /* debug stack applications */
221 int rs6000_debug_arg; /* debug argument handling */
223 /* Value is TRUE if register/mode pair is acceptable. */
224 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
226 /* Built in types. */
228 tree rs6000_builtin_types[RS6000_BTI_MAX];
229 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
231 const char *rs6000_traceback_name;
233 traceback_default = 0,
239 /* Flag to say the TOC is initialized */
241 char toc_label_name[10];
243 /* Cached value of rs6000_variable_issue. This is cached in
244 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
245 static short cached_can_issue_more;
247 static GTY(()) section *read_only_data_section;
248 static GTY(()) section *private_data_section;
249 static GTY(()) section *read_only_private_data_section;
250 static GTY(()) section *sdata2_section;
251 static GTY(()) section *toc_section;
253 /* Control alignment for fields within structures. */
254 /* String from -malign-XXXXX. */
255 int rs6000_alignment_flags;
257 /* True for any options that were explicitly set. */
259 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
260 bool alignment; /* True if -malign- was used. */
261 bool abi; /* True if -mabi=spe/nospe was used. */
262 bool spe; /* True if -mspe= was used. */
263 bool float_gprs; /* True if -mfloat-gprs= was used. */
264 bool isel; /* True if -misel was used. */
265 bool long_double; /* True if -mlong-double- was used. */
266 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
267 } rs6000_explicit_options;
269 struct builtin_description
271 /* mask is not const because we're going to alter it below. This
272 nonsense will go away when we rewrite the -march infrastructure
273 to give us more target flag bits. */
275 const enum insn_code icode;
276 const char *const name;
277 const enum rs6000_builtins code;
280 /* Target cpu costs. */
282 struct processor_costs {
283 const int mulsi; /* cost of SImode multiplication. */
284 const int mulsi_const; /* cost of SImode multiplication by constant. */
285 const int mulsi_const9; /* cost of SImode mult by short constant. */
286 const int muldi; /* cost of DImode multiplication. */
287 const int divsi; /* cost of SImode division. */
288 const int divdi; /* cost of DImode division. */
289 const int fp; /* cost of simple SFmode and DFmode insns. */
290 const int dmul; /* cost of DFmode multiplication (and fmadd). */
291 const int sdiv; /* cost of SFmode division (fdivs). */
292 const int ddiv; /* cost of DFmode division (fdiv). */
295 const struct processor_costs *rs6000_cost;
297 /* Processor costs (relative to an add) */
299 /* Instruction size costs on 32bit processors. */
301 struct processor_costs size32_cost = {
302 COSTS_N_INSNS (1), /* mulsi */
303 COSTS_N_INSNS (1), /* mulsi_const */
304 COSTS_N_INSNS (1), /* mulsi_const9 */
305 COSTS_N_INSNS (1), /* muldi */
306 COSTS_N_INSNS (1), /* divsi */
307 COSTS_N_INSNS (1), /* divdi */
308 COSTS_N_INSNS (1), /* fp */
309 COSTS_N_INSNS (1), /* dmul */
310 COSTS_N_INSNS (1), /* sdiv */
311 COSTS_N_INSNS (1), /* ddiv */
314 /* Instruction size costs on 64bit processors. */
316 struct processor_costs size64_cost = {
317 COSTS_N_INSNS (1), /* mulsi */
318 COSTS_N_INSNS (1), /* mulsi_const */
319 COSTS_N_INSNS (1), /* mulsi_const9 */
320 COSTS_N_INSNS (1), /* muldi */
321 COSTS_N_INSNS (1), /* divsi */
322 COSTS_N_INSNS (1), /* divdi */
323 COSTS_N_INSNS (1), /* fp */
324 COSTS_N_INSNS (1), /* dmul */
325 COSTS_N_INSNS (1), /* sdiv */
326 COSTS_N_INSNS (1), /* ddiv */
329 /* Instruction costs on RIOS1 processors. */
331 struct processor_costs rios1_cost = {
332 COSTS_N_INSNS (5), /* mulsi */
333 COSTS_N_INSNS (4), /* mulsi_const */
334 COSTS_N_INSNS (3), /* mulsi_const9 */
335 COSTS_N_INSNS (5), /* muldi */
336 COSTS_N_INSNS (19), /* divsi */
337 COSTS_N_INSNS (19), /* divdi */
338 COSTS_N_INSNS (2), /* fp */
339 COSTS_N_INSNS (2), /* dmul */
340 COSTS_N_INSNS (19), /* sdiv */
341 COSTS_N_INSNS (19), /* ddiv */
344 /* Instruction costs on RIOS2 processors. */
346 struct processor_costs rios2_cost = {
347 COSTS_N_INSNS (2), /* mulsi */
348 COSTS_N_INSNS (2), /* mulsi_const */
349 COSTS_N_INSNS (2), /* mulsi_const9 */
350 COSTS_N_INSNS (2), /* muldi */
351 COSTS_N_INSNS (13), /* divsi */
352 COSTS_N_INSNS (13), /* divdi */
353 COSTS_N_INSNS (2), /* fp */
354 COSTS_N_INSNS (2), /* dmul */
355 COSTS_N_INSNS (17), /* sdiv */
356 COSTS_N_INSNS (17), /* ddiv */
359 /* Instruction costs on RS64A processors. */
361 struct processor_costs rs64a_cost = {
362 COSTS_N_INSNS (20), /* mulsi */
363 COSTS_N_INSNS (12), /* mulsi_const */
364 COSTS_N_INSNS (8), /* mulsi_const9 */
365 COSTS_N_INSNS (34), /* muldi */
366 COSTS_N_INSNS (65), /* divsi */
367 COSTS_N_INSNS (67), /* divdi */
368 COSTS_N_INSNS (4), /* fp */
369 COSTS_N_INSNS (4), /* dmul */
370 COSTS_N_INSNS (31), /* sdiv */
371 COSTS_N_INSNS (31), /* ddiv */
374 /* Instruction costs on MPCCORE processors. */
376 struct processor_costs mpccore_cost = {
377 COSTS_N_INSNS (2), /* mulsi */
378 COSTS_N_INSNS (2), /* mulsi_const */
379 COSTS_N_INSNS (2), /* mulsi_const9 */
380 COSTS_N_INSNS (2), /* muldi */
381 COSTS_N_INSNS (6), /* divsi */
382 COSTS_N_INSNS (6), /* divdi */
383 COSTS_N_INSNS (4), /* fp */
384 COSTS_N_INSNS (5), /* dmul */
385 COSTS_N_INSNS (10), /* sdiv */
386 COSTS_N_INSNS (17), /* ddiv */
389 /* Instruction costs on PPC403 processors. */
391 struct processor_costs ppc403_cost = {
392 COSTS_N_INSNS (4), /* mulsi */
393 COSTS_N_INSNS (4), /* mulsi_const */
394 COSTS_N_INSNS (4), /* mulsi_const9 */
395 COSTS_N_INSNS (4), /* muldi */
396 COSTS_N_INSNS (33), /* divsi */
397 COSTS_N_INSNS (33), /* divdi */
398 COSTS_N_INSNS (11), /* fp */
399 COSTS_N_INSNS (11), /* dmul */
400 COSTS_N_INSNS (11), /* sdiv */
401 COSTS_N_INSNS (11), /* ddiv */
404 /* Instruction costs on PPC405 processors. */
406 struct processor_costs ppc405_cost = {
407 COSTS_N_INSNS (5), /* mulsi */
408 COSTS_N_INSNS (4), /* mulsi_const */
409 COSTS_N_INSNS (3), /* mulsi_const9 */
410 COSTS_N_INSNS (5), /* muldi */
411 COSTS_N_INSNS (35), /* divsi */
412 COSTS_N_INSNS (35), /* divdi */
413 COSTS_N_INSNS (11), /* fp */
414 COSTS_N_INSNS (11), /* dmul */
415 COSTS_N_INSNS (11), /* sdiv */
416 COSTS_N_INSNS (11), /* ddiv */
419 /* Instruction costs on PPC440 processors. */
421 struct processor_costs ppc440_cost = {
422 COSTS_N_INSNS (3), /* mulsi */
423 COSTS_N_INSNS (2), /* mulsi_const */
424 COSTS_N_INSNS (2), /* mulsi_const9 */
425 COSTS_N_INSNS (3), /* muldi */
426 COSTS_N_INSNS (34), /* divsi */
427 COSTS_N_INSNS (34), /* divdi */
428 COSTS_N_INSNS (5), /* fp */
429 COSTS_N_INSNS (5), /* dmul */
430 COSTS_N_INSNS (19), /* sdiv */
431 COSTS_N_INSNS (33), /* ddiv */
434 /* Instruction costs on PPC601 processors. */
436 struct processor_costs ppc601_cost = {
437 COSTS_N_INSNS (5), /* mulsi */
438 COSTS_N_INSNS (5), /* mulsi_const */
439 COSTS_N_INSNS (5), /* mulsi_const9 */
440 COSTS_N_INSNS (5), /* muldi */
441 COSTS_N_INSNS (36), /* divsi */
442 COSTS_N_INSNS (36), /* divdi */
443 COSTS_N_INSNS (4), /* fp */
444 COSTS_N_INSNS (5), /* dmul */
445 COSTS_N_INSNS (17), /* sdiv */
446 COSTS_N_INSNS (31), /* ddiv */
449 /* Instruction costs on PPC603 processors. */
451 struct processor_costs ppc603_cost = {
452 COSTS_N_INSNS (5), /* mulsi */
453 COSTS_N_INSNS (3), /* mulsi_const */
454 COSTS_N_INSNS (2), /* mulsi_const9 */
455 COSTS_N_INSNS (5), /* muldi */
456 COSTS_N_INSNS (37), /* divsi */
457 COSTS_N_INSNS (37), /* divdi */
458 COSTS_N_INSNS (3), /* fp */
459 COSTS_N_INSNS (4), /* dmul */
460 COSTS_N_INSNS (18), /* sdiv */
461 COSTS_N_INSNS (33), /* ddiv */
464 /* Instruction costs on PPC604 processors. */
466 struct processor_costs ppc604_cost = {
467 COSTS_N_INSNS (4), /* mulsi */
468 COSTS_N_INSNS (4), /* mulsi_const */
469 COSTS_N_INSNS (4), /* mulsi_const9 */
470 COSTS_N_INSNS (4), /* muldi */
471 COSTS_N_INSNS (20), /* divsi */
472 COSTS_N_INSNS (20), /* divdi */
473 COSTS_N_INSNS (3), /* fp */
474 COSTS_N_INSNS (3), /* dmul */
475 COSTS_N_INSNS (18), /* sdiv */
476 COSTS_N_INSNS (32), /* ddiv */
479 /* Instruction costs on PPC604e processors. */
481 struct processor_costs ppc604e_cost = {
482 COSTS_N_INSNS (2), /* mulsi */
483 COSTS_N_INSNS (2), /* mulsi_const */
484 COSTS_N_INSNS (2), /* mulsi_const9 */
485 COSTS_N_INSNS (2), /* muldi */
486 COSTS_N_INSNS (20), /* divsi */
487 COSTS_N_INSNS (20), /* divdi */
488 COSTS_N_INSNS (3), /* fp */
489 COSTS_N_INSNS (3), /* dmul */
490 COSTS_N_INSNS (18), /* sdiv */
491 COSTS_N_INSNS (32), /* ddiv */
494 /* Instruction costs on PPC620 processors. */
496 struct processor_costs ppc620_cost = {
497 COSTS_N_INSNS (5), /* mulsi */
498 COSTS_N_INSNS (4), /* mulsi_const */
499 COSTS_N_INSNS (3), /* mulsi_const9 */
500 COSTS_N_INSNS (7), /* muldi */
501 COSTS_N_INSNS (21), /* divsi */
502 COSTS_N_INSNS (37), /* divdi */
503 COSTS_N_INSNS (3), /* fp */
504 COSTS_N_INSNS (3), /* dmul */
505 COSTS_N_INSNS (18), /* sdiv */
506 COSTS_N_INSNS (32), /* ddiv */
509 /* Instruction costs on PPC630 processors. */
511 struct processor_costs ppc630_cost = {
512 COSTS_N_INSNS (5), /* mulsi */
513 COSTS_N_INSNS (4), /* mulsi_const */
514 COSTS_N_INSNS (3), /* mulsi_const9 */
515 COSTS_N_INSNS (7), /* muldi */
516 COSTS_N_INSNS (21), /* divsi */
517 COSTS_N_INSNS (37), /* divdi */
518 COSTS_N_INSNS (3), /* fp */
519 COSTS_N_INSNS (3), /* dmul */
520 COSTS_N_INSNS (17), /* sdiv */
521 COSTS_N_INSNS (21), /* ddiv */
524 /* Instruction costs on Cell processor. */
525 /* COSTS_N_INSNS (1) ~ one add. */
527 struct processor_costs ppccell_cost = {
528 COSTS_N_INSNS (9/2)+2, /* mulsi */
529 COSTS_N_INSNS (6/2), /* mulsi_const */
530 COSTS_N_INSNS (6/2), /* mulsi_const9 */
531 COSTS_N_INSNS (15/2)+2, /* muldi */
532 COSTS_N_INSNS (38/2), /* divsi */
533 COSTS_N_INSNS (70/2), /* divdi */
534 COSTS_N_INSNS (10/2), /* fp */
535 COSTS_N_INSNS (10/2), /* dmul */
536 COSTS_N_INSNS (74/2), /* sdiv */
537 COSTS_N_INSNS (74/2), /* ddiv */
540 /* Instruction costs on PPC750 and PPC7400 processors. */
542 struct processor_costs ppc750_cost = {
543 COSTS_N_INSNS (5), /* mulsi */
544 COSTS_N_INSNS (3), /* mulsi_const */
545 COSTS_N_INSNS (2), /* mulsi_const9 */
546 COSTS_N_INSNS (5), /* muldi */
547 COSTS_N_INSNS (17), /* divsi */
548 COSTS_N_INSNS (17), /* divdi */
549 COSTS_N_INSNS (3), /* fp */
550 COSTS_N_INSNS (3), /* dmul */
551 COSTS_N_INSNS (17), /* sdiv */
552 COSTS_N_INSNS (31), /* ddiv */
555 /* Instruction costs on PPC7450 processors. */
557 struct processor_costs ppc7450_cost = {
558 COSTS_N_INSNS (4), /* mulsi */
559 COSTS_N_INSNS (3), /* mulsi_const */
560 COSTS_N_INSNS (3), /* mulsi_const9 */
561 COSTS_N_INSNS (4), /* muldi */
562 COSTS_N_INSNS (23), /* divsi */
563 COSTS_N_INSNS (23), /* divdi */
564 COSTS_N_INSNS (5), /* fp */
565 COSTS_N_INSNS (5), /* dmul */
566 COSTS_N_INSNS (21), /* sdiv */
567 COSTS_N_INSNS (35), /* ddiv */
570 /* Instruction costs on PPC8540 processors. */
572 struct processor_costs ppc8540_cost = {
573 COSTS_N_INSNS (4), /* mulsi */
574 COSTS_N_INSNS (4), /* mulsi_const */
575 COSTS_N_INSNS (4), /* mulsi_const9 */
576 COSTS_N_INSNS (4), /* muldi */
577 COSTS_N_INSNS (19), /* divsi */
578 COSTS_N_INSNS (19), /* divdi */
579 COSTS_N_INSNS (4), /* fp */
580 COSTS_N_INSNS (4), /* dmul */
581 COSTS_N_INSNS (29), /* sdiv */
582 COSTS_N_INSNS (29), /* ddiv */
585 /* Instruction costs on POWER4 and POWER5 processors. */
587 struct processor_costs power4_cost = {
588 COSTS_N_INSNS (3), /* mulsi */
589 COSTS_N_INSNS (2), /* mulsi_const */
590 COSTS_N_INSNS (2), /* mulsi_const9 */
591 COSTS_N_INSNS (4), /* muldi */
592 COSTS_N_INSNS (18), /* divsi */
593 COSTS_N_INSNS (34), /* divdi */
594 COSTS_N_INSNS (3), /* fp */
595 COSTS_N_INSNS (3), /* dmul */
596 COSTS_N_INSNS (17), /* sdiv */
597 COSTS_N_INSNS (17), /* ddiv */
600 /* Instruction costs on POWER6 processors. */
602 struct processor_costs power6_cost = {
603 COSTS_N_INSNS (8), /* mulsi */
604 COSTS_N_INSNS (8), /* mulsi_const */
605 COSTS_N_INSNS (8), /* mulsi_const9 */
606 COSTS_N_INSNS (8), /* muldi */
607 COSTS_N_INSNS (22), /* divsi */
608 COSTS_N_INSNS (28), /* divdi */
609 COSTS_N_INSNS (3), /* fp */
610 COSTS_N_INSNS (3), /* dmul */
611 COSTS_N_INSNS (13), /* sdiv */
612 COSTS_N_INSNS (16), /* ddiv */
616 static bool rs6000_function_ok_for_sibcall (tree, tree);
617 static const char *rs6000_invalid_within_doloop (rtx);
618 static rtx rs6000_generate_compare (enum rtx_code);
619 static void rs6000_maybe_dead (rtx);
620 static void rs6000_emit_stack_tie (void);
621 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
622 static rtx spe_synthesize_frame_save (rtx);
623 static bool spe_func_has_64bit_regs_p (void);
624 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
626 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
627 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
628 static unsigned rs6000_hash_constant (rtx);
629 static unsigned toc_hash_function (const void *);
630 static int toc_hash_eq (const void *, const void *);
631 static int constant_pool_expr_1 (rtx, int *, int *);
632 static bool constant_pool_expr_p (rtx);
633 static bool legitimate_small_data_p (enum machine_mode, rtx);
634 static bool legitimate_indexed_address_p (rtx, int);
635 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
636 static struct machine_function * rs6000_init_machine_status (void);
637 static bool rs6000_assemble_integer (rtx, unsigned int, int);
638 static bool no_global_regs_above (int);
639 #ifdef HAVE_GAS_HIDDEN
640 static void rs6000_assemble_visibility (tree, int);
642 static int rs6000_ra_ever_killed (void);
643 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
644 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
645 static bool rs6000_ms_bitfield_layout_p (tree);
646 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
647 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
648 static const char *rs6000_mangle_fundamental_type (tree);
649 extern const struct attribute_spec rs6000_attribute_table[];
650 static void rs6000_set_default_type_attributes (tree);
651 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
652 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
653 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
655 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
656 static bool rs6000_return_in_memory (tree, tree);
657 static void rs6000_file_start (void);
659 static int rs6000_elf_reloc_rw_mask (void);
660 static void rs6000_elf_asm_out_constructor (rtx, int);
661 static void rs6000_elf_asm_out_destructor (rtx, int);
662 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
663 static void rs6000_elf_asm_init_sections (void);
664 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
665 unsigned HOST_WIDE_INT);
666 static void rs6000_elf_encode_section_info (tree, rtx, int)
669 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, rtx);
671 static void rs6000_xcoff_asm_output_anchor (rtx);
672 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
673 static void rs6000_xcoff_asm_init_sections (void);
674 static int rs6000_xcoff_reloc_rw_mask (void);
675 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
676 static section *rs6000_xcoff_select_section (tree, int,
677 unsigned HOST_WIDE_INT);
678 static void rs6000_xcoff_unique_section (tree, int);
679 static section *rs6000_xcoff_select_rtx_section
680 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
681 static const char * rs6000_xcoff_strip_name_encoding (const char *);
682 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
683 static void rs6000_xcoff_file_start (void);
684 static void rs6000_xcoff_file_end (void);
686 static int rs6000_variable_issue (FILE *, int, rtx, int);
687 static bool rs6000_rtx_costs (rtx, int, int, int *);
688 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
689 static void rs6000_sched_init (FILE *, int, int);
690 static bool is_microcoded_insn (rtx);
691 static bool is_nonpipeline_insn (rtx);
692 static bool is_cracked_insn (rtx);
693 static bool is_branch_slot_insn (rtx);
694 static bool is_load_insn (rtx);
695 static rtx get_store_dest (rtx pat);
696 static bool is_store_insn (rtx);
697 static bool set_to_load_agen (rtx,rtx);
698 static bool adjacent_mem_locations (rtx,rtx);
699 static int rs6000_adjust_priority (rtx, int);
700 static int rs6000_issue_rate (void);
701 static bool rs6000_is_costly_dependence (dep_t, int, int);
702 static rtx get_next_active_insn (rtx, rtx);
703 static bool insn_terminates_group_p (rtx , enum group_termination);
704 static bool insn_must_be_first_in_group (rtx);
705 static bool insn_must_be_last_in_group (rtx);
706 static bool is_costly_group (rtx *, rtx);
707 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
708 static int redefine_groups (FILE *, int, rtx, rtx);
709 static int pad_groups (FILE *, int, rtx, rtx);
710 static void rs6000_sched_finish (FILE *, int);
711 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
712 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
713 static int rs6000_use_sched_lookahead (void);
714 static int rs6000_use_sched_lookahead_guard (rtx);
715 static tree rs6000_builtin_mask_for_load (void);
716 static tree rs6000_builtin_mul_widen_even (tree);
717 static tree rs6000_builtin_mul_widen_odd (tree);
718 static tree rs6000_builtin_conversion (enum tree_code, tree);
720 static void def_builtin (int, const char *, tree, int);
721 static void rs6000_init_builtins (void);
722 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
723 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
724 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
725 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
726 static void altivec_init_builtins (void);
727 static void rs6000_common_init_builtins (void);
728 static void rs6000_init_libfuncs (void);
730 static void enable_mask_for_builtins (struct builtin_description *, int,
731 enum rs6000_builtins,
732 enum rs6000_builtins);
733 static tree build_opaque_vector_type (tree, int);
734 static void spe_init_builtins (void);
735 static rtx spe_expand_builtin (tree, rtx, bool *);
736 static rtx spe_expand_stv_builtin (enum insn_code, tree);
737 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
738 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
739 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
740 static rs6000_stack_t *rs6000_stack_info (void);
741 static void debug_stack_info (rs6000_stack_t *);
743 static rtx altivec_expand_builtin (tree, rtx, bool *);
744 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
745 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
746 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
747 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
748 static rtx altivec_expand_predicate_builtin (enum insn_code,
749 const char *, tree, rtx);
750 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
751 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
752 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
753 static rtx altivec_expand_vec_set_builtin (tree);
754 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
755 static int get_element_number (tree, tree);
756 static bool rs6000_handle_option (size_t, const char *, int);
757 static void rs6000_parse_tls_size_option (void);
758 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
759 static int first_altivec_reg_to_save (void);
760 static unsigned int compute_vrsave_mask (void);
761 static void compute_save_world_info (rs6000_stack_t *info_ptr);
762 static void is_altivec_return_reg (rtx, void *);
763 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
764 int easy_vector_constant (rtx, enum machine_mode);
765 static bool rs6000_is_opaque_type (tree);
766 static rtx rs6000_dwarf_register_span (rtx);
767 static void rs6000_init_dwarf_reg_sizes_extra (tree);
768 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
769 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
770 static rtx rs6000_tls_get_addr (void);
771 static rtx rs6000_got_sym (void);
772 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
773 static const char *rs6000_get_some_local_dynamic_name (void);
774 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
775 static rtx rs6000_complex_function_value (enum machine_mode);
776 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
777 enum machine_mode, tree);
778 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
780 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
781 tree, HOST_WIDE_INT);
782 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
785 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
788 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
789 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
790 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
791 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
792 enum machine_mode, tree,
794 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
796 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
798 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
800 static void macho_branch_islands (void);
801 static int no_previous_def (tree function_name);
802 static tree get_prev_label (tree function_name);
803 static void rs6000_darwin_file_start (void);
806 static tree rs6000_build_builtin_va_list (void);
807 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
808 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
809 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
810 static bool rs6000_vector_mode_supported_p (enum machine_mode);
811 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
813 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
815 static int get_vsel_insn (enum machine_mode);
816 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
817 static tree rs6000_stack_protect_fail (void);
819 const int INSN_NOT_AVAILABLE = -1;
820 static enum machine_mode rs6000_eh_return_filter_mode (void);
822 /* Hash table stuff for keeping track of TOC entries. */
824 struct toc_hash_struct GTY(())
826 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
827 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
829 enum machine_mode key_mode;
833 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
835 /* Default register names. */
836 char rs6000_reg_names[][8] =
838 "0", "1", "2", "3", "4", "5", "6", "7",
839 "8", "9", "10", "11", "12", "13", "14", "15",
840 "16", "17", "18", "19", "20", "21", "22", "23",
841 "24", "25", "26", "27", "28", "29", "30", "31",
842 "0", "1", "2", "3", "4", "5", "6", "7",
843 "8", "9", "10", "11", "12", "13", "14", "15",
844 "16", "17", "18", "19", "20", "21", "22", "23",
845 "24", "25", "26", "27", "28", "29", "30", "31",
846 "mq", "lr", "ctr","ap",
847 "0", "1", "2", "3", "4", "5", "6", "7",
849 /* AltiVec registers. */
850 "0", "1", "2", "3", "4", "5", "6", "7",
851 "8", "9", "10", "11", "12", "13", "14", "15",
852 "16", "17", "18", "19", "20", "21", "22", "23",
853 "24", "25", "26", "27", "28", "29", "30", "31",
856 "spe_acc", "spefscr",
857 /* Soft frame pointer. */
861 #ifdef TARGET_REGNAMES
862 static const char alt_reg_names[][8] =
864 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
865 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
866 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
867 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
868 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
869 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
870 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
871 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
872 "mq", "lr", "ctr", "ap",
873 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
875 /* AltiVec registers. */
876 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
877 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
878 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
879 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
882 "spe_acc", "spefscr",
883 /* Soft frame pointer. */
888 #ifndef MASK_STRICT_ALIGN
889 #define MASK_STRICT_ALIGN 0
891 #ifndef TARGET_PROFILE_KERNEL
892 #define TARGET_PROFILE_KERNEL 0
895 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
896 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
898 /* Initialize the GCC target structure. */
899 #undef TARGET_ATTRIBUTE_TABLE
900 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
901 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
902 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
904 #undef TARGET_ASM_ALIGNED_DI_OP
905 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
907 /* Default unaligned ops are only provided for ELF. Find the ops needed
908 for non-ELF systems. */
909 #ifndef OBJECT_FORMAT_ELF
911 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
913 #undef TARGET_ASM_UNALIGNED_HI_OP
914 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
915 #undef TARGET_ASM_UNALIGNED_SI_OP
916 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
917 #undef TARGET_ASM_UNALIGNED_DI_OP
918 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
921 #undef TARGET_ASM_UNALIGNED_HI_OP
922 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
923 #undef TARGET_ASM_UNALIGNED_SI_OP
924 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
925 #undef TARGET_ASM_UNALIGNED_DI_OP
926 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
927 #undef TARGET_ASM_ALIGNED_DI_OP
928 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
932 /* This hook deals with fixups for relocatable code and DI-mode objects
934 #undef TARGET_ASM_INTEGER
935 #define TARGET_ASM_INTEGER rs6000_assemble_integer
937 #ifdef HAVE_GAS_HIDDEN
938 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
939 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
942 #undef TARGET_HAVE_TLS
943 #define TARGET_HAVE_TLS HAVE_AS_TLS
945 #undef TARGET_CANNOT_FORCE_CONST_MEM
946 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
948 #undef TARGET_ASM_FUNCTION_PROLOGUE
949 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
950 #undef TARGET_ASM_FUNCTION_EPILOGUE
951 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
953 #undef TARGET_SCHED_VARIABLE_ISSUE
954 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
956 #undef TARGET_SCHED_ISSUE_RATE
957 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
958 #undef TARGET_SCHED_ADJUST_COST
959 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
960 #undef TARGET_SCHED_ADJUST_PRIORITY
961 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
962 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
963 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
964 #undef TARGET_SCHED_INIT
965 #define TARGET_SCHED_INIT rs6000_sched_init
966 #undef TARGET_SCHED_FINISH
967 #define TARGET_SCHED_FINISH rs6000_sched_finish
968 #undef TARGET_SCHED_REORDER
969 #define TARGET_SCHED_REORDER rs6000_sched_reorder
970 #undef TARGET_SCHED_REORDER2
971 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
973 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
974 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
976 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
977 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
979 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
980 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
981 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
982 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
983 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
984 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
985 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
986 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
988 #undef TARGET_INIT_BUILTINS
989 #define TARGET_INIT_BUILTINS rs6000_init_builtins
991 #undef TARGET_EXPAND_BUILTIN
992 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
994 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
995 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
997 #undef TARGET_INIT_LIBFUNCS
998 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1001 #undef TARGET_BINDS_LOCAL_P
1002 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1005 #undef TARGET_MS_BITFIELD_LAYOUT_P
1006 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1008 #undef TARGET_ASM_OUTPUT_MI_THUNK
1009 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1011 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1012 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1014 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1015 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1017 #undef TARGET_INVALID_WITHIN_DOLOOP
1018 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1020 #undef TARGET_RTX_COSTS
1021 #define TARGET_RTX_COSTS rs6000_rtx_costs
1022 #undef TARGET_ADDRESS_COST
1023 #define TARGET_ADDRESS_COST hook_int_rtx_0
1025 #undef TARGET_VECTOR_OPAQUE_P
1026 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1028 #undef TARGET_DWARF_REGISTER_SPAN
1029 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1031 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1032 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1034 /* On rs6000, function arguments are promoted, as are function return
1036 #undef TARGET_PROMOTE_FUNCTION_ARGS
1037 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1038 #undef TARGET_PROMOTE_FUNCTION_RETURN
1039 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1041 #undef TARGET_RETURN_IN_MEMORY
1042 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1044 #undef TARGET_SETUP_INCOMING_VARARGS
1045 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1047 /* Always strict argument naming on rs6000. */
1048 #undef TARGET_STRICT_ARGUMENT_NAMING
1049 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1050 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1051 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1052 #undef TARGET_SPLIT_COMPLEX_ARG
1053 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
1054 #undef TARGET_MUST_PASS_IN_STACK
1055 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1056 #undef TARGET_PASS_BY_REFERENCE
1057 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1058 #undef TARGET_ARG_PARTIAL_BYTES
1059 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1061 #undef TARGET_BUILD_BUILTIN_VA_LIST
1062 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1064 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1065 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1067 #undef TARGET_EH_RETURN_FILTER_MODE
1068 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1070 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1071 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1073 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1074 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1076 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1077 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1079 #undef TARGET_HANDLE_OPTION
1080 #define TARGET_HANDLE_OPTION rs6000_handle_option
1082 #undef TARGET_DEFAULT_TARGET_FLAGS
1083 #define TARGET_DEFAULT_TARGET_FLAGS \
1086 #undef TARGET_STACK_PROTECT_FAIL
1087 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1089 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1090 The PowerPC architecture requires only weak consistency among
1091 processors--that is, memory accesses between processors need not be
1092 sequentially consistent and memory accesses among processors can occur
1093 in any order. The ability to order memory accesses weakly provides
1094 opportunities for more efficient use of the system bus. Unless a
1095 dependency exists, the 604e allows read operations to precede store
1097 #undef TARGET_RELAXED_ORDERING
1098 #define TARGET_RELAXED_ORDERING true
1101 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1102 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1105 /* Use a 32-bit anchor range. This leads to sequences like:
1107 addis tmp,anchor,high
1110 where tmp itself acts as an anchor, and can be shared between
1111 accesses to the same 64k page. */
1112 #undef TARGET_MIN_ANCHOR_OFFSET
1113 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1114 #undef TARGET_MAX_ANCHOR_OFFSET
1115 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1116 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1117 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1119 struct gcc_target targetm = TARGET_INITIALIZER;
1122 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1125 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1127 /* The GPRs can hold any mode, but values bigger than one register
1128 cannot go past R31. */
1129 if (INT_REGNO_P (regno))
1130 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1132 /* The float registers can only hold floating modes and DImode.
1133 This excludes the 32-bit decimal float mode for now. */
1134 if (FP_REGNO_P (regno))
1136 (SCALAR_FLOAT_MODE_P (mode)
1137 && (mode != TDmode || (regno % 2) == 0)
1139 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1140 || (GET_MODE_CLASS (mode) == MODE_INT
1141 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1143 /* The CR register can only hold CC modes. */
1144 if (CR_REGNO_P (regno))
1145 return GET_MODE_CLASS (mode) == MODE_CC;
1147 if (XER_REGNO_P (regno))
1148 return mode == PSImode;
1150 /* AltiVec only in AldyVec registers. */
1151 if (ALTIVEC_REGNO_P (regno))
1152 return ALTIVEC_VECTOR_MODE (mode);
1154 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1155 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1158 /* We cannot put TImode anywhere except general register and it must be
1159 able to fit within the register set. */
1161 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1164 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1166 rs6000_init_hard_regno_mode_ok (void)
1170 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1171 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1172 if (rs6000_hard_regno_mode_ok (r, m))
1173 rs6000_hard_regno_mode_ok_p[m][r] = true;
1177 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1180 darwin_rs6000_override_options (void)
1182 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1184 rs6000_altivec_abi = 1;
1185 TARGET_ALTIVEC_VRSAVE = 1;
1186 if (DEFAULT_ABI == ABI_DARWIN)
1188 if (MACHO_DYNAMIC_NO_PIC_P)
1191 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1194 else if (flag_pic == 1)
1199 if (TARGET_64BIT && ! TARGET_POWERPC64)
1201 target_flags |= MASK_POWERPC64;
1202 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1206 rs6000_default_long_calls = 1;
1207 target_flags |= MASK_SOFT_FLOAT;
1210 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1212 if (!flag_mkernel && !flag_apple_kext
1214 && ! (target_flags_explicit & MASK_ALTIVEC))
1215 target_flags |= MASK_ALTIVEC;
1217 /* Unless the user (not the configurer) has explicitly overridden
1218 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1219 G4 unless targetting the kernel. */
1222 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
1223 && ! (target_flags_explicit & MASK_ALTIVEC)
1224 && ! rs6000_select[1].string)
1226 target_flags |= MASK_ALTIVEC;
1231 /* If not otherwise specified by a target, make 'long double' equivalent to
1234 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1235 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1238 /* Override command line options. Mostly we process the processor
1239 type and sometimes adjust other TARGET_ options. */
1242 rs6000_override_options (const char *default_cpu)
1245 struct rs6000_cpu_select *ptr;
1248 /* Simplifications for entries below. */
1251 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1252 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1255 /* This table occasionally claims that a processor does not support
1256 a particular feature even though it does, but the feature is slower
1257 than the alternative. Thus, it shouldn't be relied on as a
1258 complete description of the processor's support.
1260 Please keep this list in order, and don't forget to update the
1261 documentation in invoke.texi when adding a new processor or
1265 const char *const name; /* Canonical processor name. */
1266 const enum processor_type processor; /* Processor type enum value. */
1267 const int target_enable; /* Target flags to enable. */
1268 } const processor_target_table[]
1269 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1270 {"403", PROCESSOR_PPC403,
1271 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1272 {"405", PROCESSOR_PPC405,
1273 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1274 {"405fp", PROCESSOR_PPC405,
1275 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1276 {"440", PROCESSOR_PPC440,
1277 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1278 {"440fp", PROCESSOR_PPC440,
1279 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1280 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1281 {"601", PROCESSOR_PPC601,
1282 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1283 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1284 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1285 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1286 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1287 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1288 {"620", PROCESSOR_PPC620,
1289 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1290 {"630", PROCESSOR_PPC630,
1291 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1292 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1293 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1294 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1295 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1296 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1297 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1298 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1299 {"8540", PROCESSOR_PPC8540,
1300 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_STRICT_ALIGN},
1301 /* 8548 has a dummy entry for now. */
1302 {"8548", PROCESSOR_PPC8540,
1303 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_STRICT_ALIGN},
1304 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1305 {"970", PROCESSOR_POWER4,
1306 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1307 {"cell", PROCESSOR_CELL,
1308 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1309 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1310 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1311 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1312 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1313 {"G5", PROCESSOR_POWER4,
1314 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1315 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1316 {"power2", PROCESSOR_POWER,
1317 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1318 {"power3", PROCESSOR_PPC630,
1319 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1320 {"power4", PROCESSOR_POWER4,
1321 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1322 {"power5", PROCESSOR_POWER5,
1323 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1324 | MASK_MFCRF | MASK_POPCNTB},
1325 {"power5+", PROCESSOR_POWER5,
1326 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1327 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1328 {"power6", PROCESSOR_POWER6,
1329 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1330 | MASK_FPRND | MASK_CMPB | MASK_DFP },
1331 {"power6x", PROCESSOR_POWER6,
1332 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1333 | MASK_FPRND | MASK_CMPB | MASK_MFPGPR | MASK_DFP },
1334 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1335 {"powerpc64", PROCESSOR_POWERPC64,
1336 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1337 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1338 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1339 {"rios2", PROCESSOR_RIOS2,
1340 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1341 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1342 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1343 {"rs64", PROCESSOR_RS64A,
1344 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1347 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1349 /* Some OSs don't support saving the high part of 64-bit registers on
1350 context switch. Other OSs don't support saving Altivec registers.
1351 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1352 settings; if the user wants either, the user must explicitly specify
1353 them and we won't interfere with the user's specification. */
1356 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1357 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1358 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1359 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1360 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP)
1363 rs6000_init_hard_regno_mode_ok ();
1365 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1366 #ifdef OS_MISSING_POWERPC64
1367 if (OS_MISSING_POWERPC64)
1368 set_masks &= ~MASK_POWERPC64;
1370 #ifdef OS_MISSING_ALTIVEC
1371 if (OS_MISSING_ALTIVEC)
1372 set_masks &= ~MASK_ALTIVEC;
1375 /* Don't override by the processor default if given explicitly. */
1376 set_masks &= ~target_flags_explicit;
1378 /* Identify the processor type. */
1379 rs6000_select[0].string = default_cpu;
1380 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1382 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1384 ptr = &rs6000_select[i];
1385 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1387 for (j = 0; j < ptt_size; j++)
1388 if (! strcmp (ptr->string, processor_target_table[j].name))
1390 if (ptr->set_tune_p)
1391 rs6000_cpu = processor_target_table[j].processor;
1393 if (ptr->set_arch_p)
1395 target_flags &= ~set_masks;
1396 target_flags |= (processor_target_table[j].target_enable
1403 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1410 /* If we are optimizing big endian systems for space, use the load/store
1411 multiple and string instructions. */
1412 if (BYTES_BIG_ENDIAN && optimize_size)
1413 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1415 /* Don't allow -mmultiple or -mstring on little endian systems
1416 unless the cpu is a 750, because the hardware doesn't support the
1417 instructions used in little endian mode, and causes an alignment
1418 trap. The 750 does not cause an alignment trap (except when the
1419 target is unaligned). */
1421 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1423 if (TARGET_MULTIPLE)
1425 target_flags &= ~MASK_MULTIPLE;
1426 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1427 warning (0, "-mmultiple is not supported on little endian systems");
1432 target_flags &= ~MASK_STRING;
1433 if ((target_flags_explicit & MASK_STRING) != 0)
1434 warning (0, "-mstring is not supported on little endian systems");
1438 /* Set debug flags */
1439 if (rs6000_debug_name)
1441 if (! strcmp (rs6000_debug_name, "all"))
1442 rs6000_debug_stack = rs6000_debug_arg = 1;
1443 else if (! strcmp (rs6000_debug_name, "stack"))
1444 rs6000_debug_stack = 1;
1445 else if (! strcmp (rs6000_debug_name, "arg"))
1446 rs6000_debug_arg = 1;
1448 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1451 if (rs6000_traceback_name)
1453 if (! strncmp (rs6000_traceback_name, "full", 4))
1454 rs6000_traceback = traceback_full;
1455 else if (! strncmp (rs6000_traceback_name, "part", 4))
1456 rs6000_traceback = traceback_part;
1457 else if (! strncmp (rs6000_traceback_name, "no", 2))
1458 rs6000_traceback = traceback_none;
1460 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1461 rs6000_traceback_name);
1464 if (!rs6000_explicit_options.long_double)
1465 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1467 #ifndef POWERPC_LINUX
1468 if (!rs6000_explicit_options.ieee)
1469 rs6000_ieeequad = 1;
1472 /* Set Altivec ABI as default for powerpc64 linux. */
1473 if (TARGET_ELF && TARGET_64BIT)
1475 rs6000_altivec_abi = 1;
1476 TARGET_ALTIVEC_VRSAVE = 1;
1479 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1480 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1482 rs6000_darwin64_abi = 1;
1484 darwin_one_byte_bool = 1;
1486 /* Default to natural alignment, for better performance. */
1487 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1490 /* Place FP constants in the constant pool instead of TOC
1491 if section anchors enabled. */
1492 if (flag_section_anchors)
1493 TARGET_NO_FP_IN_TOC = 1;
1495 /* Handle -mtls-size option. */
1496 rs6000_parse_tls_size_option ();
1498 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1499 SUBTARGET_OVERRIDE_OPTIONS;
1501 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1502 SUBSUBTARGET_OVERRIDE_OPTIONS;
1504 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1505 SUB3TARGET_OVERRIDE_OPTIONS;
1510 /* The e500 does not have string instructions, and we set
1511 MASK_STRING above when optimizing for size. */
1512 if ((target_flags & MASK_STRING) != 0)
1513 target_flags = target_flags & ~MASK_STRING;
1515 else if (rs6000_select[1].string != NULL)
1517 /* For the powerpc-eabispe configuration, we set all these by
1518 default, so let's unset them if we manually set another
1519 CPU that is not the E500. */
1520 if (!rs6000_explicit_options.abi)
1522 if (!rs6000_explicit_options.spe)
1524 if (!rs6000_explicit_options.float_gprs)
1525 rs6000_float_gprs = 0;
1526 if (!rs6000_explicit_options.isel)
1530 /* Detect invalid option combinations with E500. */
1533 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1534 && rs6000_cpu != PROCESSOR_POWER5
1535 && rs6000_cpu != PROCESSOR_POWER6
1536 && rs6000_cpu != PROCESSOR_CELL);
1537 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1538 || rs6000_cpu == PROCESSOR_POWER5);
1539 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
1540 || rs6000_cpu == PROCESSOR_POWER5
1541 || rs6000_cpu == PROCESSOR_POWER6);
1543 rs6000_sched_restricted_insns_priority
1544 = (rs6000_sched_groups ? 1 : 0);
1546 /* Handle -msched-costly-dep option. */
1547 rs6000_sched_costly_dep
1548 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1550 if (rs6000_sched_costly_dep_str)
1552 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1553 rs6000_sched_costly_dep = no_dep_costly;
1554 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1555 rs6000_sched_costly_dep = all_deps_costly;
1556 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1557 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1558 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1559 rs6000_sched_costly_dep = store_to_load_dep_costly;
1561 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1564 /* Handle -minsert-sched-nops option. */
1565 rs6000_sched_insert_nops
1566 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1568 if (rs6000_sched_insert_nops_str)
1570 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1571 rs6000_sched_insert_nops = sched_finish_none;
1572 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1573 rs6000_sched_insert_nops = sched_finish_pad_groups;
1574 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1575 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1577 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1580 #ifdef TARGET_REGNAMES
1581 /* If the user desires alternate register names, copy in the
1582 alternate names now. */
1583 if (TARGET_REGNAMES)
1584 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1587 /* Set aix_struct_return last, after the ABI is determined.
1588 If -maix-struct-return or -msvr4-struct-return was explicitly
1589 used, don't override with the ABI default. */
1590 if (!rs6000_explicit_options.aix_struct_ret)
1591 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1593 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1594 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1597 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1599 /* We can only guarantee the availability of DI pseudo-ops when
1600 assembling for 64-bit targets. */
1603 targetm.asm_out.aligned_op.di = NULL;
1604 targetm.asm_out.unaligned_op.di = NULL;
1607 /* Set branch target alignment, if not optimizing for size. */
1610 /* Cell wants to be aligned 8byte for dual issue. */
1611 if (rs6000_cpu == PROCESSOR_CELL)
1613 if (align_functions <= 0)
1614 align_functions = 8;
1615 if (align_jumps <= 0)
1617 if (align_loops <= 0)
1620 if (rs6000_align_branch_targets)
1622 if (align_functions <= 0)
1623 align_functions = 16;
1624 if (align_jumps <= 0)
1626 if (align_loops <= 0)
1629 if (align_jumps_max_skip <= 0)
1630 align_jumps_max_skip = 15;
1631 if (align_loops_max_skip <= 0)
1632 align_loops_max_skip = 15;
1635 /* Arrange to save and restore machine status around nested functions. */
1636 init_machine_status = rs6000_init_machine_status;
1638 /* We should always be splitting complex arguments, but we can't break
1639 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1640 if (DEFAULT_ABI != ABI_AIX)
1641 targetm.calls.split_complex_arg = NULL;
1643 /* Initialize rs6000_cost with the appropriate target costs. */
1645 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1649 case PROCESSOR_RIOS1:
1650 rs6000_cost = &rios1_cost;
1653 case PROCESSOR_RIOS2:
1654 rs6000_cost = &rios2_cost;
1657 case PROCESSOR_RS64A:
1658 rs6000_cost = &rs64a_cost;
1661 case PROCESSOR_MPCCORE:
1662 rs6000_cost = &mpccore_cost;
1665 case PROCESSOR_PPC403:
1666 rs6000_cost = &ppc403_cost;
1669 case PROCESSOR_PPC405:
1670 rs6000_cost = &ppc405_cost;
1673 case PROCESSOR_PPC440:
1674 rs6000_cost = &ppc440_cost;
1677 case PROCESSOR_PPC601:
1678 rs6000_cost = &ppc601_cost;
1681 case PROCESSOR_PPC603:
1682 rs6000_cost = &ppc603_cost;
1685 case PROCESSOR_PPC604:
1686 rs6000_cost = &ppc604_cost;
1689 case PROCESSOR_PPC604e:
1690 rs6000_cost = &ppc604e_cost;
1693 case PROCESSOR_PPC620:
1694 rs6000_cost = &ppc620_cost;
1697 case PROCESSOR_PPC630:
1698 rs6000_cost = &ppc630_cost;
1701 case PROCESSOR_CELL:
1702 rs6000_cost = &ppccell_cost;
1705 case PROCESSOR_PPC750:
1706 case PROCESSOR_PPC7400:
1707 rs6000_cost = &ppc750_cost;
1710 case PROCESSOR_PPC7450:
1711 rs6000_cost = &ppc7450_cost;
1714 case PROCESSOR_PPC8540:
1715 rs6000_cost = &ppc8540_cost;
1718 case PROCESSOR_POWER4:
1719 case PROCESSOR_POWER5:
1720 rs6000_cost = &power4_cost;
1723 case PROCESSOR_POWER6:
1724 rs6000_cost = &power6_cost;
1732 /* Implement targetm.vectorize.builtin_mask_for_load. */
1734 rs6000_builtin_mask_for_load (void)
1737 return altivec_builtin_mask_for_load;
1742 /* Implement targetm.vectorize.builtin_conversion. */
1744 rs6000_builtin_conversion (enum tree_code code, tree type)
1746 if (!TARGET_ALTIVEC)
1752 switch (TYPE_MODE (type))
1755 return TYPE_UNSIGNED (type) ?
1756 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFUX] :
1757 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFSX];
1766 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1768 rs6000_builtin_mul_widen_even (tree type)
1770 if (!TARGET_ALTIVEC)
1773 switch (TYPE_MODE (type))
1776 return TYPE_UNSIGNED (type) ?
1777 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH] :
1778 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
1781 return TYPE_UNSIGNED (type) ?
1782 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB] :
1783 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
1789 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
1791 rs6000_builtin_mul_widen_odd (tree type)
1793 if (!TARGET_ALTIVEC)
1796 switch (TYPE_MODE (type))
1799 return TYPE_UNSIGNED (type) ?
1800 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH] :
1801 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
1804 return TYPE_UNSIGNED (type) ?
1805 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB] :
1806 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
1812 /* Handle generic options of the form -mfoo=yes/no.
1813 NAME is the option name.
1814 VALUE is the option value.
1815 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1816 whether the option value is 'yes' or 'no' respectively. */
1818 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1822 else if (!strcmp (value, "yes"))
1824 else if (!strcmp (value, "no"))
1827 error ("unknown -m%s= option specified: '%s'", name, value);
1830 /* Validate and record the size specified with the -mtls-size option. */
1833 rs6000_parse_tls_size_option (void)
1835 if (rs6000_tls_size_string == 0)
1837 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1838 rs6000_tls_size = 16;
1839 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1840 rs6000_tls_size = 32;
1841 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1842 rs6000_tls_size = 64;
1844 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1848 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1850 if (DEFAULT_ABI == ABI_DARWIN)
1851 /* The Darwin libraries never set errno, so we might as well
1852 avoid calling them when that's the only reason we would. */
1853 flag_errno_math = 0;
1855 /* Double growth factor to counter reduced min jump length. */
1856 set_param_value ("max-grow-copy-bb-insns", 16);
1858 /* Enable section anchors by default.
1859 Skip section anchors for Objective C and Objective C++
1860 until front-ends fixed. */
1861 if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
1862 flag_section_anchors = 1;
1865 /* Implement TARGET_HANDLE_OPTION. */
1868 rs6000_handle_option (size_t code, const char *arg, int value)
1873 target_flags &= ~(MASK_POWER | MASK_POWER2
1874 | MASK_MULTIPLE | MASK_STRING);
1875 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1876 | MASK_MULTIPLE | MASK_STRING);
1878 case OPT_mno_powerpc:
1879 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1880 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1881 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1882 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1885 target_flags &= ~MASK_MINIMAL_TOC;
1886 TARGET_NO_FP_IN_TOC = 0;
1887 TARGET_NO_SUM_IN_TOC = 0;
1888 target_flags_explicit |= MASK_MINIMAL_TOC;
1889 #ifdef TARGET_USES_SYSV4_OPT
1890 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1891 just the same as -mminimal-toc. */
1892 target_flags |= MASK_MINIMAL_TOC;
1893 target_flags_explicit |= MASK_MINIMAL_TOC;
1897 #ifdef TARGET_USES_SYSV4_OPT
1899 /* Make -mtoc behave like -mminimal-toc. */
1900 target_flags |= MASK_MINIMAL_TOC;
1901 target_flags_explicit |= MASK_MINIMAL_TOC;
1905 #ifdef TARGET_USES_AIX64_OPT
1910 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
1911 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
1912 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
1915 #ifdef TARGET_USES_AIX64_OPT
1920 target_flags &= ~MASK_POWERPC64;
1921 target_flags_explicit |= MASK_POWERPC64;
1924 case OPT_minsert_sched_nops_:
1925 rs6000_sched_insert_nops_str = arg;
1928 case OPT_mminimal_toc:
1931 TARGET_NO_FP_IN_TOC = 0;
1932 TARGET_NO_SUM_IN_TOC = 0;
1939 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1940 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1947 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1948 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1952 case OPT_mpowerpc_gpopt:
1953 case OPT_mpowerpc_gfxopt:
1956 target_flags |= MASK_POWERPC;
1957 target_flags_explicit |= MASK_POWERPC;
1961 case OPT_maix_struct_return:
1962 case OPT_msvr4_struct_return:
1963 rs6000_explicit_options.aix_struct_ret = true;
1967 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1971 rs6000_explicit_options.isel = true;
1972 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1976 rs6000_explicit_options.spe = true;
1977 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1981 rs6000_debug_name = arg;
1984 #ifdef TARGET_USES_SYSV4_OPT
1986 rs6000_abi_name = arg;
1990 rs6000_sdata_name = arg;
1993 case OPT_mtls_size_:
1994 rs6000_tls_size_string = arg;
1997 case OPT_mrelocatable:
2000 target_flags |= MASK_MINIMAL_TOC;
2001 target_flags_explicit |= MASK_MINIMAL_TOC;
2002 TARGET_NO_FP_IN_TOC = 1;
2006 case OPT_mrelocatable_lib:
2009 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2010 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2011 TARGET_NO_FP_IN_TOC = 1;
2015 target_flags &= ~MASK_RELOCATABLE;
2016 target_flags_explicit |= MASK_RELOCATABLE;
2022 if (!strcmp (arg, "altivec"))
2024 rs6000_explicit_options.abi = true;
2025 rs6000_altivec_abi = 1;
2028 else if (! strcmp (arg, "no-altivec"))
2030 /* ??? Don't set rs6000_explicit_options.abi here, to allow
2031 the default for rs6000_spe_abi to be chosen later. */
2032 rs6000_altivec_abi = 0;
2034 else if (! strcmp (arg, "spe"))
2036 rs6000_explicit_options.abi = true;
2038 rs6000_altivec_abi = 0;
2039 if (!TARGET_SPE_ABI)
2040 error ("not configured for ABI: '%s'", arg);
2042 else if (! strcmp (arg, "no-spe"))
2044 rs6000_explicit_options.abi = true;
2048 /* These are here for testing during development only, do not
2049 document in the manual please. */
2050 else if (! strcmp (arg, "d64"))
2052 rs6000_darwin64_abi = 1;
2053 warning (0, "Using darwin64 ABI");
2055 else if (! strcmp (arg, "d32"))
2057 rs6000_darwin64_abi = 0;
2058 warning (0, "Using old darwin ABI");
2061 else if (! strcmp (arg, "ibmlongdouble"))
2063 rs6000_explicit_options.ieee = true;
2064 rs6000_ieeequad = 0;
2065 warning (0, "Using IBM extended precision long double");
2067 else if (! strcmp (arg, "ieeelongdouble"))
2069 rs6000_explicit_options.ieee = true;
2070 rs6000_ieeequad = 1;
2071 warning (0, "Using IEEE extended precision long double");
2076 error ("unknown ABI specified: '%s'", arg);
2082 rs6000_select[1].string = arg;
2086 rs6000_select[2].string = arg;
2089 case OPT_mtraceback_:
2090 rs6000_traceback_name = arg;
2093 case OPT_mfloat_gprs_:
2094 rs6000_explicit_options.float_gprs = true;
2095 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
2096 rs6000_float_gprs = 1;
2097 else if (! strcmp (arg, "double"))
2098 rs6000_float_gprs = 2;
2099 else if (! strcmp (arg, "no"))
2100 rs6000_float_gprs = 0;
2103 error ("invalid option for -mfloat-gprs: '%s'", arg);
2108 case OPT_mlong_double_:
2109 rs6000_explicit_options.long_double = true;
2110 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2111 if (value != 64 && value != 128)
2113 error ("Unknown switch -mlong-double-%s", arg);
2114 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2118 rs6000_long_double_type_size = value;
2121 case OPT_msched_costly_dep_:
2122 rs6000_sched_costly_dep_str = arg;
2126 rs6000_explicit_options.alignment = true;
2127 if (! strcmp (arg, "power"))
2129 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2130 some C library functions, so warn about it. The flag may be
2131 useful for performance studies from time to time though, so
2132 don't disable it entirely. */
2133 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
2134 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2135 " it is incompatible with the installed C and C++ libraries");
2136 rs6000_alignment_flags = MASK_ALIGN_POWER;
2138 else if (! strcmp (arg, "natural"))
2139 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2142 error ("unknown -malign-XXXXX option specified: '%s'", arg);
2150 /* Do anything needed at the start of the asm file. */
2153 rs6000_file_start (void)
2157 const char *start = buffer;
2158 struct rs6000_cpu_select *ptr;
2159 const char *default_cpu = TARGET_CPU_DEFAULT;
2160 FILE *file = asm_out_file;
2162 default_file_start ();
2164 #ifdef TARGET_BI_ARCH
2165 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
2169 if (flag_verbose_asm)
2171 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
2172 rs6000_select[0].string = default_cpu;
2174 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
2176 ptr = &rs6000_select[i];
2177 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
2179 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
2184 if (PPC405_ERRATUM77)
2186 fprintf (file, "%s PPC405CR_ERRATUM77", start);
2190 #ifdef USING_ELFOS_H
2191 switch (rs6000_sdata)
2193 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
2194 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
2195 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
2196 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
2199 if (rs6000_sdata && g_switch_value)
2201 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
2211 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
2213 switch_to_section (toc_section);
2214 switch_to_section (text_section);
2219 /* Return nonzero if this function is known to have a null epilogue. */
2222 direct_return (void)
2224 if (reload_completed)
2226 rs6000_stack_t *info = rs6000_stack_info ();
2228 if (info->first_gp_reg_save == 32
2229 && info->first_fp_reg_save == 64
2230 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
2231 && ! info->lr_save_p
2232 && ! info->cr_save_p
2233 && info->vrsave_mask == 0
2241 /* Return the number of instructions it takes to form a constant in an
2242 integer register. */
2245 num_insns_constant_wide (HOST_WIDE_INT value)
2247 /* signed constant loadable with {cal|addi} */
2248 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2251 /* constant loadable with {cau|addis} */
2252 else if ((value & 0xffff) == 0
2253 && (value >> 31 == -1 || value >> 31 == 0))
2256 #if HOST_BITS_PER_WIDE_INT == 64
2257 else if (TARGET_POWERPC64)
2259 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2260 HOST_WIDE_INT high = value >> 31;
2262 if (high == 0 || high == -1)
2268 return num_insns_constant_wide (high) + 1;
2270 return (num_insns_constant_wide (high)
2271 + num_insns_constant_wide (low) + 1);
2280 num_insns_constant (rtx op, enum machine_mode mode)
2282 HOST_WIDE_INT low, high;
2284 switch (GET_CODE (op))
2287 #if HOST_BITS_PER_WIDE_INT == 64
2288 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2289 && mask64_operand (op, mode))
2293 return num_insns_constant_wide (INTVAL (op));
2301 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2302 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2303 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2306 if (mode == VOIDmode || mode == DImode)
2308 high = CONST_DOUBLE_HIGH (op);
2309 low = CONST_DOUBLE_LOW (op);
2316 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2317 if (DECIMAL_FLOAT_MODE_P (mode))
2318 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
2320 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2321 high = l[WORDS_BIG_ENDIAN == 0];
2322 low = l[WORDS_BIG_ENDIAN != 0];
2326 return (num_insns_constant_wide (low)
2327 + num_insns_constant_wide (high));
2330 if ((high == 0 && low >= 0)
2331 || (high == -1 && low < 0))
2332 return num_insns_constant_wide (low);
2334 else if (mask64_operand (op, mode))
2338 return num_insns_constant_wide (high) + 1;
2341 return (num_insns_constant_wide (high)
2342 + num_insns_constant_wide (low) + 1);
2350 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2351 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2352 corresponding element of the vector, but for V4SFmode and V2SFmode,
2353 the corresponding "float" is interpreted as an SImode integer. */
2355 static HOST_WIDE_INT
2356 const_vector_elt_as_int (rtx op, unsigned int elt)
2358 rtx tmp = CONST_VECTOR_ELT (op, elt);
2359 if (GET_MODE (op) == V4SFmode
2360 || GET_MODE (op) == V2SFmode)
2361 tmp = gen_lowpart (SImode, tmp);
2362 return INTVAL (tmp);
2365 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2366 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2367 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2368 all items are set to the same value and contain COPIES replicas of the
2369 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2370 operand and the others are set to the value of the operand's msb. */
2373 vspltis_constant (rtx op, unsigned step, unsigned copies)
2375 enum machine_mode mode = GET_MODE (op);
2376 enum machine_mode inner = GET_MODE_INNER (mode);
2379 unsigned nunits = GET_MODE_NUNITS (mode);
2380 unsigned bitsize = GET_MODE_BITSIZE (inner);
2381 unsigned mask = GET_MODE_MASK (inner);
2383 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
2384 HOST_WIDE_INT splat_val = val;
2385 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2387 /* Construct the value to be splatted, if possible. If not, return 0. */
2388 for (i = 2; i <= copies; i *= 2)
2390 HOST_WIDE_INT small_val;
2392 small_val = splat_val >> bitsize;
2394 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2396 splat_val = small_val;
2399 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2400 if (EASY_VECTOR_15 (splat_val))
2403 /* Also check if we can splat, and then add the result to itself. Do so if
2404 the value is positive, of if the splat instruction is using OP's mode;
2405 for splat_val < 0, the splat and the add should use the same mode. */
2406 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2407 && (splat_val >= 0 || (step == 1 && copies == 1)))
2413 /* Check if VAL is present in every STEP-th element, and the
2414 other elements are filled with its most significant bit. */
2415 for (i = 0; i < nunits - 1; ++i)
2417 HOST_WIDE_INT desired_val;
2418 if (((i + 1) & (step - 1)) == 0)
2421 desired_val = msb_val;
2423 if (desired_val != const_vector_elt_as_int (op, i))
2431 /* Return true if OP is of the given MODE and can be synthesized
2432 with a vspltisb, vspltish or vspltisw. */
2435 easy_altivec_constant (rtx op, enum machine_mode mode)
2437 unsigned step, copies;
2439 if (mode == VOIDmode)
2440 mode = GET_MODE (op);
2441 else if (mode != GET_MODE (op))
2444 /* Start with a vspltisw. */
2445 step = GET_MODE_NUNITS (mode) / 4;
2448 if (vspltis_constant (op, step, copies))
2451 /* Then try with a vspltish. */
2457 if (vspltis_constant (op, step, copies))
2460 /* And finally a vspltisb. */
2466 if (vspltis_constant (op, step, copies))
2472 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2473 result is OP. Abort if it is not possible. */
2476 gen_easy_altivec_constant (rtx op)
2478 enum machine_mode mode = GET_MODE (op);
2479 int nunits = GET_MODE_NUNITS (mode);
2480 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2481 unsigned step = nunits / 4;
2482 unsigned copies = 1;
2484 /* Start with a vspltisw. */
2485 if (vspltis_constant (op, step, copies))
2486 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2488 /* Then try with a vspltish. */
2494 if (vspltis_constant (op, step, copies))
2495 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2497 /* And finally a vspltisb. */
2503 if (vspltis_constant (op, step, copies))
2504 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2510 output_vec_const_move (rtx *operands)
2513 enum machine_mode mode;
2518 mode = GET_MODE (dest);
2523 if (zero_constant (vec, mode))
2524 return "vxor %0,%0,%0";
2526 splat_vec = gen_easy_altivec_constant (vec);
2527 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2528 operands[1] = XEXP (splat_vec, 0);
2529 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2532 switch (GET_MODE (splat_vec))
2535 return "vspltisw %0,%1";
2538 return "vspltish %0,%1";
2541 return "vspltisb %0,%1";
2548 gcc_assert (TARGET_SPE);
2550 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2551 pattern of V1DI, V4HI, and V2SF.
2553 FIXME: We should probably return # and add post reload
2554 splitters for these, but this way is so easy ;-). */
2555 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2556 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2557 operands[1] = CONST_VECTOR_ELT (vec, 0);
2558 operands[2] = CONST_VECTOR_ELT (vec, 1);
2560 return "li %0,%1\n\tevmergelo %0,%0,%0";
2562 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2565 /* Initialize vector TARGET to VALS. */
2568 rs6000_expand_vector_init (rtx target, rtx vals)
2570 enum machine_mode mode = GET_MODE (target);
2571 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2572 int n_elts = GET_MODE_NUNITS (mode);
2573 int n_var = 0, one_var = -1;
2574 bool all_same = true, all_const_zero = true;
2578 for (i = 0; i < n_elts; ++i)
2580 x = XVECEXP (vals, 0, i);
2581 if (!CONSTANT_P (x))
2582 ++n_var, one_var = i;
2583 else if (x != CONST0_RTX (inner_mode))
2584 all_const_zero = false;
2586 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2592 if (mode != V4SFmode && all_const_zero)
2594 /* Zero register. */
2595 emit_insn (gen_rtx_SET (VOIDmode, target,
2596 gen_rtx_XOR (mode, target, target)));
2599 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2601 /* Splat immediate. */
2602 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2606 ; /* Splat vector element. */
2609 /* Load from constant pool. */
2610 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2615 /* Store value to stack temp. Load vector element. Splat. */
2618 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2619 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2620 XVECEXP (vals, 0, 0));
2621 x = gen_rtx_UNSPEC (VOIDmode,
2622 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2623 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2625 gen_rtx_SET (VOIDmode,
2628 x = gen_rtx_VEC_SELECT (inner_mode, target,
2629 gen_rtx_PARALLEL (VOIDmode,
2630 gen_rtvec (1, const0_rtx)));
2631 emit_insn (gen_rtx_SET (VOIDmode, target,
2632 gen_rtx_VEC_DUPLICATE (mode, x)));
2636 /* One field is non-constant. Load constant then overwrite
2640 rtx copy = copy_rtx (vals);
2642 /* Load constant part of vector, substitute neighboring value for
2644 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2645 rs6000_expand_vector_init (target, copy);
2647 /* Insert variable. */
2648 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2652 /* Construct the vector in memory one field at a time
2653 and load the whole vector. */
2654 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2655 for (i = 0; i < n_elts; i++)
2656 emit_move_insn (adjust_address_nv (mem, inner_mode,
2657 i * GET_MODE_SIZE (inner_mode)),
2658 XVECEXP (vals, 0, i));
2659 emit_move_insn (target, mem);
2662 /* Set field ELT of TARGET to VAL. */
2665 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2667 enum machine_mode mode = GET_MODE (target);
2668 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2669 rtx reg = gen_reg_rtx (mode);
2671 int width = GET_MODE_SIZE (inner_mode);
2674 /* Load single variable value. */
2675 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2676 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2677 x = gen_rtx_UNSPEC (VOIDmode,
2678 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2679 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2681 gen_rtx_SET (VOIDmode,
2685 /* Linear sequence. */
2686 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2687 for (i = 0; i < 16; ++i)
2688 XVECEXP (mask, 0, i) = GEN_INT (i);
2690 /* Set permute mask to insert element into target. */
2691 for (i = 0; i < width; ++i)
2692 XVECEXP (mask, 0, elt*width + i)
2693 = GEN_INT (i + 0x10);
2694 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2695 x = gen_rtx_UNSPEC (mode,
2696 gen_rtvec (3, target, reg,
2697 force_reg (V16QImode, x)),
2699 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2702 /* Extract field ELT from VEC into TARGET. */
2705 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2707 enum machine_mode mode = GET_MODE (vec);
2708 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2711 /* Allocate mode-sized buffer. */
2712 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2714 /* Add offset to field within buffer matching vector element. */
2715 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2717 /* Store single field into mode-sized buffer. */
2718 x = gen_rtx_UNSPEC (VOIDmode,
2719 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2720 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2722 gen_rtx_SET (VOIDmode,
2725 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2728 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2729 implement ANDing by the mask IN. */
2731 build_mask64_2_operands (rtx in, rtx *out)
2733 #if HOST_BITS_PER_WIDE_INT >= 64
2734 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2737 gcc_assert (GET_CODE (in) == CONST_INT);
2742 /* Assume c initially something like 0x00fff000000fffff. The idea
2743 is to rotate the word so that the middle ^^^^^^ group of zeros
2744 is at the MS end and can be cleared with an rldicl mask. We then
2745 rotate back and clear off the MS ^^ group of zeros with a
2747 c = ~c; /* c == 0xff000ffffff00000 */
2748 lsb = c & -c; /* lsb == 0x0000000000100000 */
2749 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2750 c = ~c; /* c == 0x00fff000000fffff */
2751 c &= -lsb; /* c == 0x00fff00000000000 */
2752 lsb = c & -c; /* lsb == 0x0000100000000000 */
2753 c = ~c; /* c == 0xff000fffffffffff */
2754 c &= -lsb; /* c == 0xff00000000000000 */
2756 while ((lsb >>= 1) != 0)
2757 shift++; /* shift == 44 on exit from loop */
2758 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2759 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2760 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2764 /* Assume c initially something like 0xff000f0000000000. The idea
2765 is to rotate the word so that the ^^^ middle group of zeros
2766 is at the LS end and can be cleared with an rldicr mask. We then
2767 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2769 lsb = c & -c; /* lsb == 0x0000010000000000 */
2770 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2771 c = ~c; /* c == 0x00fff0ffffffffff */
2772 c &= -lsb; /* c == 0x00fff00000000000 */
2773 lsb = c & -c; /* lsb == 0x0000100000000000 */
2774 c = ~c; /* c == 0xff000fffffffffff */
2775 c &= -lsb; /* c == 0xff00000000000000 */
2777 while ((lsb >>= 1) != 0)
2778 shift++; /* shift == 44 on exit from loop */
2779 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2780 m1 >>= shift; /* m1 == 0x0000000000000fff */
2781 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2784 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2785 masks will be all 1's. We are guaranteed more than one transition. */
2786 out[0] = GEN_INT (64 - shift);
2787 out[1] = GEN_INT (m1);
2788 out[2] = GEN_INT (shift);
2789 out[3] = GEN_INT (m2);
2797 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2800 invalid_e500_subreg (rtx op, enum machine_mode mode)
2802 if (TARGET_E500_DOUBLE)
2804 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
2805 subreg:TI and reg:TF. */
2806 if (GET_CODE (op) == SUBREG
2807 && (mode == SImode || mode == DImode || mode == TImode)
2808 && REG_P (SUBREG_REG (op))
2809 && (GET_MODE (SUBREG_REG (op)) == DFmode
2810 || GET_MODE (SUBREG_REG (op)) == TFmode))
2813 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
2815 if (GET_CODE (op) == SUBREG
2816 && (mode == DFmode || mode == TFmode)
2817 && REG_P (SUBREG_REG (op))
2818 && (GET_MODE (SUBREG_REG (op)) == DImode
2819 || GET_MODE (SUBREG_REG (op)) == TImode))
2824 && GET_CODE (op) == SUBREG
2826 && REG_P (SUBREG_REG (op))
2827 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
2833 /* AIX increases natural record alignment to doubleword if the first
2834 field is an FP double while the FP fields remain word aligned. */
2837 rs6000_special_round_type_align (tree type, unsigned int computed,
2838 unsigned int specified)
2840 unsigned int align = MAX (computed, specified);
2841 tree field = TYPE_FIELDS (type);
2843 /* Skip all non field decls */
2844 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2845 field = TREE_CHAIN (field);
2847 if (field != NULL && field != type)
2849 type = TREE_TYPE (field);
2850 while (TREE_CODE (type) == ARRAY_TYPE)
2851 type = TREE_TYPE (type);
2853 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2854 align = MAX (align, 64);
2860 /* Darwin increases record alignment to the natural alignment of
2864 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
2865 unsigned int specified)
2867 unsigned int align = MAX (computed, specified);
2869 if (TYPE_PACKED (type))
2872 /* Find the first field, looking down into aggregates. */
2874 tree field = TYPE_FIELDS (type);
2875 /* Skip all non field decls */
2876 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2877 field = TREE_CHAIN (field);
2880 type = TREE_TYPE (field);
2881 while (TREE_CODE (type) == ARRAY_TYPE)
2882 type = TREE_TYPE (type);
2883 } while (AGGREGATE_TYPE_P (type));
2885 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
2886 align = MAX (align, TYPE_ALIGN (type));
2891 /* Return 1 for an operand in small memory on V.4/eabi. */
2894 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2895 enum machine_mode mode ATTRIBUTE_UNUSED)
2900 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2903 if (DEFAULT_ABI != ABI_V4)
2906 if (GET_CODE (op) == SYMBOL_REF)
2909 else if (GET_CODE (op) != CONST
2910 || GET_CODE (XEXP (op, 0)) != PLUS
2911 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2912 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2917 rtx sum = XEXP (op, 0);
2918 HOST_WIDE_INT summand;
2920 /* We have to be careful here, because it is the referenced address
2921 that must be 32k from _SDA_BASE_, not just the symbol. */
2922 summand = INTVAL (XEXP (sum, 1));
2923 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2926 sym_ref = XEXP (sum, 0);
2929 return SYMBOL_REF_SMALL_P (sym_ref);
2935 /* Return true if either operand is a general purpose register. */
2938 gpr_or_gpr_p (rtx op0, rtx op1)
2940 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2941 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2945 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2948 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2950 switch (GET_CODE (op))
2953 if (RS6000_SYMBOL_REF_TLS_P (op))
2955 else if (CONSTANT_POOL_ADDRESS_P (op))
2957 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2965 else if (! strcmp (XSTR (op, 0), toc_label_name))
2974 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2975 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2977 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2986 constant_pool_expr_p (rtx op)
2990 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2994 toc_relative_expr_p (rtx op)
2998 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3002 legitimate_constant_pool_address_p (rtx x)
3005 && GET_CODE (x) == PLUS
3006 && GET_CODE (XEXP (x, 0)) == REG
3007 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3008 && constant_pool_expr_p (XEXP (x, 1)));
3012 legitimate_small_data_p (enum machine_mode mode, rtx x)
3014 return (DEFAULT_ABI == ABI_V4
3015 && !flag_pic && !TARGET_TOC
3016 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3017 && small_data_operand (x, mode));
3020 /* SPE offset addressing is limited to 5-bits worth of double words. */
3021 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3024 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3026 unsigned HOST_WIDE_INT offset, extra;
3028 if (GET_CODE (x) != PLUS)
3030 if (GET_CODE (XEXP (x, 0)) != REG)
3032 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3034 if (legitimate_constant_pool_address_p (x))
3036 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3039 offset = INTVAL (XEXP (x, 1));
3047 /* AltiVec vector modes. Only reg+reg addressing is valid and
3048 constant offset zero should not occur due to canonicalization.
3049 Allow any offset when not strict before reload. */
3056 /* SPE vector modes. */
3057 return SPE_CONST_OFFSET_OK (offset);
3061 if (TARGET_E500_DOUBLE)
3062 return SPE_CONST_OFFSET_OK (offset);
3065 /* On e500v2, we may have:
3067 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3069 Which gets addressed with evldd instructions. */
3070 if (TARGET_E500_DOUBLE)
3071 return SPE_CONST_OFFSET_OK (offset);
3073 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
3075 else if (offset & 3)
3080 if (TARGET_E500_DOUBLE)
3081 return (SPE_CONST_OFFSET_OK (offset)
3082 && SPE_CONST_OFFSET_OK (offset + 8));
3086 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
3088 else if (offset & 3)
3099 return (offset < 0x10000) && (offset + extra < 0x10000);
3103 legitimate_indexed_address_p (rtx x, int strict)
3107 if (GET_CODE (x) != PLUS)
3113 /* Recognize the rtl generated by reload which we know will later be
3114 replaced with proper base and index regs. */
3116 && reload_in_progress
3117 && (REG_P (op0) || GET_CODE (op0) == PLUS)
3121 return (REG_P (op0) && REG_P (op1)
3122 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
3123 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3124 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3125 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
3129 legitimate_indirect_address_p (rtx x, int strict)
3131 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3135 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3137 if (!TARGET_MACHO || !flag_pic
3138 || mode != SImode || GET_CODE (x) != MEM)
3142 if (GET_CODE (x) != LO_SUM)
3144 if (GET_CODE (XEXP (x, 0)) != REG)
3146 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3150 return CONSTANT_P (x);
3154 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3156 if (GET_CODE (x) != LO_SUM)
3158 if (GET_CODE (XEXP (x, 0)) != REG)
3160 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3162 /* Restrict addressing for DI because of our SUBREG hackery. */
3163 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3168 if (TARGET_ELF || TARGET_MACHO)
3170 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3174 if (GET_MODE_NUNITS (mode) != 1)
3176 if (GET_MODE_BITSIZE (mode) > 64
3177 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
3178 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
3181 return CONSTANT_P (x);
3188 /* Try machine-dependent ways of modifying an illegitimate address
3189 to be legitimate. If we find one, return the new, valid address.
3190 This is used from only one place: `memory_address' in explow.c.
3192 OLDX is the address as it was before break_out_memory_refs was
3193 called. In some cases it is useful to look at this to decide what
3196 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3198 It is always safe for this function to do nothing. It exists to
3199 recognize opportunities to optimize the output.
3201 On RS/6000, first check for the sum of a register with a constant
3202 integer that is out of range. If so, generate code to add the
3203 constant with the low-order 16 bits masked to the register and force
3204 this result into another register (this can be done with `cau').
3205 Then generate an address of REG+(CONST&0xffff), allowing for the
3206 possibility of bit 16 being a one.
3208 Then check for the sum of a register and something not constant, try to
3209 load the other things into a register and return the sum. */
3212 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3213 enum machine_mode mode)
3215 if (GET_CODE (x) == SYMBOL_REF)
3217 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3219 return rs6000_legitimize_tls_address (x, model);
3222 if (GET_CODE (x) == PLUS
3223 && GET_CODE (XEXP (x, 0)) == REG
3224 && GET_CODE (XEXP (x, 1)) == CONST_INT
3225 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
3227 HOST_WIDE_INT high_int, low_int;
3229 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3230 high_int = INTVAL (XEXP (x, 1)) - low_int;
3231 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3232 GEN_INT (high_int)), 0);
3233 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3235 else if (GET_CODE (x) == PLUS
3236 && GET_CODE (XEXP (x, 0)) == REG
3237 && GET_CODE (XEXP (x, 1)) != CONST_INT
3238 && GET_MODE_NUNITS (mode) == 1
3239 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3241 || (((mode != DImode && mode != DFmode && mode != DDmode)
3242 || TARGET_E500_DOUBLE)
3243 && mode != TFmode && mode != TDmode))
3244 && (TARGET_POWERPC64 || mode != DImode)
3247 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3248 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3250 else if (ALTIVEC_VECTOR_MODE (mode))
3254 /* Make sure both operands are registers. */
3255 if (GET_CODE (x) == PLUS)
3256 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3257 force_reg (Pmode, XEXP (x, 1)));
3259 reg = force_reg (Pmode, x);
3262 else if (SPE_VECTOR_MODE (mode)
3263 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3264 || mode == DDmode || mode == TDmode
3265 || mode == DImode)))
3269 /* We accept [reg + reg] and [reg + OFFSET]. */
3271 if (GET_CODE (x) == PLUS)
3273 rtx op1 = XEXP (x, 0);
3274 rtx op2 = XEXP (x, 1);
3276 op1 = force_reg (Pmode, op1);
3278 if (GET_CODE (op2) != REG
3279 && (GET_CODE (op2) != CONST_INT
3280 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3281 op2 = force_reg (Pmode, op2);
3283 return gen_rtx_PLUS (Pmode, op1, op2);
3286 return force_reg (Pmode, x);
3292 && GET_CODE (x) != CONST_INT
3293 && GET_CODE (x) != CONST_DOUBLE
3295 && GET_MODE_NUNITS (mode) == 1
3296 && (GET_MODE_BITSIZE (mode) <= 32
3297 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3299 rtx reg = gen_reg_rtx (Pmode);
3300 emit_insn (gen_elf_high (reg, x));
3301 return gen_rtx_LO_SUM (Pmode, reg, x);
3303 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3306 && ! MACHO_DYNAMIC_NO_PIC_P
3308 && GET_CODE (x) != CONST_INT
3309 && GET_CODE (x) != CONST_DOUBLE
3311 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3315 rtx reg = gen_reg_rtx (Pmode);
3316 emit_insn (gen_macho_high (reg, x));
3317 return gen_rtx_LO_SUM (Pmode, reg, x);
3320 && constant_pool_expr_p (x)
3321 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3323 return create_TOC_reference (x);
3329 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3330 We need to emit DTP-relative relocations. */
3333 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3338 fputs ("\t.long\t", file);
3341 fputs (DOUBLE_INT_ASM_OP, file);
3346 output_addr_const (file, x);
3347 fputs ("@dtprel+0x8000", file);
3350 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3352 static GTY(()) rtx rs6000_tls_symbol;
3354 rs6000_tls_get_addr (void)
3356 if (!rs6000_tls_symbol)
3357 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3359 return rs6000_tls_symbol;
3362 /* Construct the SYMBOL_REF for TLS GOT references. */
3364 static GTY(()) rtx rs6000_got_symbol;
3366 rs6000_got_sym (void)
3368 if (!rs6000_got_symbol)
3370 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3371 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3372 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3375 return rs6000_got_symbol;
3378 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3379 this (thread-local) address. */
3382 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3386 dest = gen_reg_rtx (Pmode);
3387 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3393 tlsreg = gen_rtx_REG (Pmode, 13);
3394 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3398 tlsreg = gen_rtx_REG (Pmode, 2);
3399 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3403 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3407 tmp = gen_reg_rtx (Pmode);
3410 tlsreg = gen_rtx_REG (Pmode, 13);
3411 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3415 tlsreg = gen_rtx_REG (Pmode, 2);
3416 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3420 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3422 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3427 rtx r3, got, tga, tmp1, tmp2, eqv;
3429 /* We currently use relocations like @got@tlsgd for tls, which
3430 means the linker will handle allocation of tls entries, placing
3431 them in the .got section. So use a pointer to the .got section,
3432 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3433 or to secondary GOT sections used by 32-bit -fPIC. */
3435 got = gen_rtx_REG (Pmode, 2);
3439 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3442 rtx gsym = rs6000_got_sym ();
3443 got = gen_reg_rtx (Pmode);
3445 rs6000_emit_move (got, gsym, Pmode);
3451 tmp1 = gen_reg_rtx (Pmode);
3452 tmp2 = gen_reg_rtx (Pmode);
3453 tmp3 = gen_reg_rtx (Pmode);
3454 mem = gen_const_mem (Pmode, tmp1);
3456 first = emit_insn (gen_load_toc_v4_PIC_1b (gsym));
3457 emit_move_insn (tmp1,
3458 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
3459 emit_move_insn (tmp2, mem);
3460 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3461 last = emit_move_insn (got, tmp3);
3462 set_unique_reg_note (last, REG_EQUAL, gsym);
3463 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3465 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3471 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3473 r3 = gen_rtx_REG (Pmode, 3);
3475 insn = gen_tls_gd_64 (r3, got, addr);
3477 insn = gen_tls_gd_32 (r3, got, addr);
3480 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3481 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3482 insn = emit_call_insn (insn);
3483 CONST_OR_PURE_CALL_P (insn) = 1;
3484 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3485 insn = get_insns ();
3487 emit_libcall_block (insn, dest, r3, addr);
3489 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3491 r3 = gen_rtx_REG (Pmode, 3);
3493 insn = gen_tls_ld_64 (r3, got);
3495 insn = gen_tls_ld_32 (r3, got);
3498 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3499 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3500 insn = emit_call_insn (insn);
3501 CONST_OR_PURE_CALL_P (insn) = 1;
3502 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3503 insn = get_insns ();
3505 tmp1 = gen_reg_rtx (Pmode);
3506 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3508 emit_libcall_block (insn, tmp1, r3, eqv);
3509 if (rs6000_tls_size == 16)
3512 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3514 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3516 else if (rs6000_tls_size == 32)
3518 tmp2 = gen_reg_rtx (Pmode);
3520 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3522 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3525 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3527 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3531 tmp2 = gen_reg_rtx (Pmode);
3533 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3535 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3537 insn = gen_rtx_SET (Pmode, dest,
3538 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3544 /* IE, or 64-bit offset LE. */
3545 tmp2 = gen_reg_rtx (Pmode);
3547 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3549 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3552 insn = gen_tls_tls_64 (dest, tmp2, addr);
3554 insn = gen_tls_tls_32 (dest, tmp2, addr);
3562 /* Return 1 if X contains a thread-local symbol. */
3565 rs6000_tls_referenced_p (rtx x)
3567 if (! TARGET_HAVE_TLS)
3570 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3573 /* Return 1 if *X is a thread-local symbol. This is the same as
3574 rs6000_tls_symbol_ref except for the type of the unused argument. */
3577 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3579 return RS6000_SYMBOL_REF_TLS_P (*x);
3582 /* The convention appears to be to define this wherever it is used.
3583 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3584 is now used here. */
3585 #ifndef REG_MODE_OK_FOR_BASE_P
3586 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3589 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3590 replace the input X, or the original X if no replacement is called for.
3591 The output parameter *WIN is 1 if the calling macro should goto WIN,
3594 For RS/6000, we wish to handle large displacements off a base
3595 register by splitting the addend across an addiu/addis and the mem insn.
3596 This cuts number of extra insns needed from 3 to 1.
3598 On Darwin, we use this to generate code for floating point constants.
3599 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3600 The Darwin code is inside #if TARGET_MACHO because only then is
3601 machopic_function_base_name() defined. */
3603 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3604 int opnum, int type,
3605 int ind_levels ATTRIBUTE_UNUSED, int *win)
3607 /* We must recognize output that we have already generated ourselves. */
3608 if (GET_CODE (x) == PLUS
3609 && GET_CODE (XEXP (x, 0)) == PLUS
3610 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3611 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3612 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3614 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3615 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3616 opnum, (enum reload_type)type);
3622 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3623 && GET_CODE (x) == LO_SUM
3624 && GET_CODE (XEXP (x, 0)) == PLUS
3625 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3626 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3627 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3628 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3629 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3630 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3631 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3633 /* Result of previous invocation of this function on Darwin
3634 floating point constant. */
3635 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3636 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3637 opnum, (enum reload_type)type);
3643 /* Force ld/std non-word aligned offset into base register by wrapping
3645 if (GET_CODE (x) == PLUS
3646 && GET_CODE (XEXP (x, 0)) == REG
3647 && REGNO (XEXP (x, 0)) < 32
3648 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3649 && GET_CODE (XEXP (x, 1)) == CONST_INT
3650 && (INTVAL (XEXP (x, 1)) & 3) != 0
3651 && !ALTIVEC_VECTOR_MODE (mode)
3652 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3653 && TARGET_POWERPC64)
3655 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3656 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3657 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3658 opnum, (enum reload_type) type);
3663 if (GET_CODE (x) == PLUS
3664 && GET_CODE (XEXP (x, 0)) == REG
3665 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3666 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3667 && GET_CODE (XEXP (x, 1)) == CONST_INT
3668 && !SPE_VECTOR_MODE (mode)
3669 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3671 && !ALTIVEC_VECTOR_MODE (mode))
3673 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3674 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3676 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3678 /* Check for 32-bit overflow. */
3679 if (high + low != val)
3685 /* Reload the high part into a base reg; leave the low part
3686 in the mem directly. */
3688 x = gen_rtx_PLUS (GET_MODE (x),
3689 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3693 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3694 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3695 opnum, (enum reload_type)type);
3700 if (GET_CODE (x) == SYMBOL_REF
3701 && !ALTIVEC_VECTOR_MODE (mode)
3702 && !SPE_VECTOR_MODE (mode)
3704 && DEFAULT_ABI == ABI_DARWIN
3705 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3707 && DEFAULT_ABI == ABI_V4
3710 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
3711 The same goes for DImode without 64-bit gprs and DFmode
3715 && (mode != DImode || TARGET_POWERPC64)
3716 && (mode != DFmode || TARGET_POWERPC64
3717 || (TARGET_FPRS && TARGET_HARD_FLOAT)))
3722 rtx offset = gen_rtx_CONST (Pmode,
3723 gen_rtx_MINUS (Pmode, x,
3724 machopic_function_base_sym ()));
3725 x = gen_rtx_LO_SUM (GET_MODE (x),
3726 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3727 gen_rtx_HIGH (Pmode, offset)), offset);
3731 x = gen_rtx_LO_SUM (GET_MODE (x),
3732 gen_rtx_HIGH (Pmode, x), x);
3734 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3735 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3736 opnum, (enum reload_type)type);
3741 /* Reload an offset address wrapped by an AND that represents the
3742 masking of the lower bits. Strip the outer AND and let reload
3743 convert the offset address into an indirect address. */
3745 && ALTIVEC_VECTOR_MODE (mode)
3746 && GET_CODE (x) == AND
3747 && GET_CODE (XEXP (x, 0)) == PLUS
3748 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3749 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3750 && GET_CODE (XEXP (x, 1)) == CONST_INT
3751 && INTVAL (XEXP (x, 1)) == -16)
3759 && constant_pool_expr_p (x)
3760 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3762 x = create_TOC_reference (x);
3770 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3771 that is a valid memory address for an instruction.
3772 The MODE argument is the machine mode for the MEM expression
3773 that wants to use this address.
3775 On the RS/6000, there are four valid address: a SYMBOL_REF that
3776 refers to a constant pool entry of an address (or the sum of it
3777 plus a constant), a short (16-bit signed) constant plus a register,
3778 the sum of two registers, or a register indirect, possibly with an
3779 auto-increment. For DFmode and DImode with a constant plus register,
3780 we must ensure that both words are addressable or PowerPC64 with offset
3783 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3784 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
3785 because adjacent memory cells are accessed by adding word-sized offsets
3786 during assembly output. */
3788 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3790 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3792 && ALTIVEC_VECTOR_MODE (mode)
3793 && GET_CODE (x) == AND
3794 && GET_CODE (XEXP (x, 1)) == CONST_INT
3795 && INTVAL (XEXP (x, 1)) == -16)
3798 if (RS6000_SYMBOL_REF_TLS_P (x))
3800 if (legitimate_indirect_address_p (x, reg_ok_strict))
3802 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3803 && !ALTIVEC_VECTOR_MODE (mode)
3804 && !SPE_VECTOR_MODE (mode)
3807 /* Restrict addressing for DI because of our SUBREG hackery. */
3808 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3811 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3813 if (legitimate_small_data_p (mode, x))
3815 if (legitimate_constant_pool_address_p (x))
3817 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3819 && GET_CODE (x) == PLUS
3820 && GET_CODE (XEXP (x, 0)) == REG
3821 && (XEXP (x, 0) == virtual_stack_vars_rtx
3822 || XEXP (x, 0) == arg_pointer_rtx)
3823 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3825 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3830 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3832 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3833 && (TARGET_POWERPC64 || mode != DImode)
3834 && legitimate_indexed_address_p (x, reg_ok_strict))
3836 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3841 /* Go to LABEL if ADDR (a legitimate address expression)
3842 has an effect that depends on the machine mode it is used for.
3844 On the RS/6000 this is true of all integral offsets (since AltiVec
3845 modes don't allow them) or is a pre-increment or decrement.
3847 ??? Except that due to conceptual problems in offsettable_address_p
3848 we can't really report the problems of integral offsets. So leave
3849 this assuming that the adjustable offset must be valid for the
3850 sub-words of a TFmode operand, which is what we had before. */
3853 rs6000_mode_dependent_address (rtx addr)
3855 switch (GET_CODE (addr))
3858 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3860 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3861 return val + 12 + 0x8000 >= 0x10000;
3868 /* Auto-increment cases are now treated generically in recog.c. */
3877 /* More elaborate version of recog's offsettable_memref_p predicate
3878 that works around the ??? note of rs6000_mode_dependent_address.
3879 In particular it accepts
3881 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
3883 in 32-bit mode, that the recog predicate rejects. */
3886 rs6000_offsettable_memref_p (rtx op)
3891 /* First mimic offsettable_memref_p. */
3892 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
3895 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
3896 the latter predicate knows nothing about the mode of the memory
3897 reference and, therefore, assumes that it is the largest supported
3898 mode (TFmode). As a consequence, legitimate offsettable memory
3899 references are rejected. rs6000_legitimate_offset_address_p contains
3900 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
3901 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
3904 /* Return number of consecutive hard regs needed starting at reg REGNO
3905 to hold something of mode MODE.
3906 This is ordinarily the length in words of a value of mode MODE
3907 but can be less for certain modes in special long registers.
3909 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3910 scalar instructions. The upper 32 bits are only available to the
3913 POWER and PowerPC GPRs hold 32 bits worth;
3914 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3917 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3919 if (FP_REGNO_P (regno))
3920 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3922 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3923 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3925 if (ALTIVEC_REGNO_P (regno))
3927 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3929 /* The value returned for SCmode in the E500 double case is 2 for
3930 ABI compatibility; storing an SCmode value in a single register
3931 would require function_arg and rs6000_spe_function_arg to handle
3932 SCmode so as to pass the value correctly in a pair of
3934 if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode)
3935 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3937 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3940 /* Change register usage conditional on target flags. */
3942 rs6000_conditional_register_usage (void)
3946 /* Set MQ register fixed (already call_used) if not POWER
3947 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3952 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3954 fixed_regs[13] = call_used_regs[13]
3955 = call_really_used_regs[13] = 1;
3957 /* Conditionally disable FPRs. */
3958 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3959 for (i = 32; i < 64; i++)
3960 fixed_regs[i] = call_used_regs[i]
3961 = call_really_used_regs[i] = 1;
3963 /* The TOC register is not killed across calls in a way that is
3964 visible to the compiler. */
3965 if (DEFAULT_ABI == ABI_AIX)
3966 call_really_used_regs[2] = 0;
3968 if (DEFAULT_ABI == ABI_V4
3969 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3971 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3973 if (DEFAULT_ABI == ABI_V4
3974 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3976 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3977 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3978 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3980 if (DEFAULT_ABI == ABI_DARWIN
3981 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3982 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3983 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3984 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3986 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3987 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3988 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3991 global_regs[VSCR_REGNO] = 1;
3995 global_regs[SPEFSCR_REGNO] = 1;
3996 fixed_regs[FIXED_SCRATCH]
3997 = call_used_regs[FIXED_SCRATCH]
3998 = call_really_used_regs[FIXED_SCRATCH] = 1;
4001 if (! TARGET_ALTIVEC)
4003 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4004 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4005 call_really_used_regs[VRSAVE_REGNO] = 1;
4008 if (TARGET_ALTIVEC_ABI)
4009 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4010 call_used_regs[i] = call_really_used_regs[i] = 1;
4013 /* Try to output insns to set TARGET equal to the constant C if it can
4014 be done in less than N insns. Do all computations in MODE.
4015 Returns the place where the output has been placed if it can be
4016 done and the insns have been emitted. If it would take more than N
4017 insns, zero is returned and no insns and emitted. */
4020 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4021 rtx source, int n ATTRIBUTE_UNUSED)
4023 rtx result, insn, set;
4024 HOST_WIDE_INT c0, c1;
4031 dest = gen_reg_rtx (mode);
4032 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4036 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
4038 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
4039 GEN_INT (INTVAL (source)
4040 & (~ (HOST_WIDE_INT) 0xffff))));
4041 emit_insn (gen_rtx_SET (VOIDmode, dest,
4042 gen_rtx_IOR (SImode, copy_rtx (result),
4043 GEN_INT (INTVAL (source) & 0xffff))));
4048 switch (GET_CODE (source))
4051 c0 = INTVAL (source);
4056 #if HOST_BITS_PER_WIDE_INT >= 64
4057 c0 = CONST_DOUBLE_LOW (source);
4060 c0 = CONST_DOUBLE_LOW (source);
4061 c1 = CONST_DOUBLE_HIGH (source);
4069 result = rs6000_emit_set_long_const (dest, c0, c1);
4076 insn = get_last_insn ();
4077 set = single_set (insn);
4078 if (! CONSTANT_P (SET_SRC (set)))
4079 set_unique_reg_note (insn, REG_EQUAL, source);
4084 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4085 fall back to a straight forward decomposition. We do this to avoid
4086 exponential run times encountered when looking for longer sequences
4087 with rs6000_emit_set_const. */
4089 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4091 if (!TARGET_POWERPC64)
4093 rtx operand1, operand2;
4095 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4097 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
4099 emit_move_insn (operand1, GEN_INT (c1));
4100 emit_move_insn (operand2, GEN_INT (c2));
4104 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4107 ud2 = (c1 & 0xffff0000) >> 16;
4108 #if HOST_BITS_PER_WIDE_INT >= 64
4112 ud4 = (c2 & 0xffff0000) >> 16;
4114 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4115 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4118 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4120 emit_move_insn (dest, GEN_INT (ud1));
4123 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4124 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4127 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4130 emit_move_insn (dest, GEN_INT (ud2 << 16));
4132 emit_move_insn (copy_rtx (dest),
4133 gen_rtx_IOR (DImode, copy_rtx (dest),
4136 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4137 || (ud4 == 0 && ! (ud3 & 0x8000)))
4140 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4143 emit_move_insn (dest, GEN_INT (ud3 << 16));
4146 emit_move_insn (copy_rtx (dest),
4147 gen_rtx_IOR (DImode, copy_rtx (dest),
4149 emit_move_insn (copy_rtx (dest),
4150 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4153 emit_move_insn (copy_rtx (dest),
4154 gen_rtx_IOR (DImode, copy_rtx (dest),
4160 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4163 emit_move_insn (dest, GEN_INT (ud4 << 16));
4166 emit_move_insn (copy_rtx (dest),
4167 gen_rtx_IOR (DImode, copy_rtx (dest),
4170 emit_move_insn (copy_rtx (dest),
4171 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4174 emit_move_insn (copy_rtx (dest),
4175 gen_rtx_IOR (DImode, copy_rtx (dest),
4176 GEN_INT (ud2 << 16)));
4178 emit_move_insn (copy_rtx (dest),
4179 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
4185 /* Helper for the following. Get rid of [r+r] memory refs
4186 in cases where it won't work (TImode, TFmode, TDmode). */
4189 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4191 if (GET_CODE (operands[0]) == MEM
4192 && GET_CODE (XEXP (operands[0], 0)) != REG
4193 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
4194 && ! reload_in_progress)
4196 = replace_equiv_address (operands[0],
4197 copy_addr_to_reg (XEXP (operands[0], 0)));
4199 if (GET_CODE (operands[1]) == MEM
4200 && GET_CODE (XEXP (operands[1], 0)) != REG
4201 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
4202 && ! reload_in_progress)
4204 = replace_equiv_address (operands[1],
4205 copy_addr_to_reg (XEXP (operands[1], 0)));
4208 /* Emit a move from SOURCE to DEST in mode MODE. */
4210 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4214 operands[1] = source;
4216 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4217 if (GET_CODE (operands[1]) == CONST_DOUBLE
4218 && ! FLOAT_MODE_P (mode)
4219 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4221 /* FIXME. This should never happen. */
4222 /* Since it seems that it does, do the safe thing and convert
4224 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4226 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
4227 || FLOAT_MODE_P (mode)
4228 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
4229 || CONST_DOUBLE_LOW (operands[1]) < 0)
4230 && (CONST_DOUBLE_HIGH (operands[1]) != -1
4231 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
4233 /* Check if GCC is setting up a block move that will end up using FP
4234 registers as temporaries. We must make sure this is acceptable. */
4235 if (GET_CODE (operands[0]) == MEM
4236 && GET_CODE (operands[1]) == MEM
4238 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4239 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4240 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4241 ? 32 : MEM_ALIGN (operands[0])))
4242 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4244 : MEM_ALIGN (operands[1]))))
4245 && ! MEM_VOLATILE_P (operands [0])
4246 && ! MEM_VOLATILE_P (operands [1]))
4248 emit_move_insn (adjust_address (operands[0], SImode, 0),
4249 adjust_address (operands[1], SImode, 0));
4250 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
4251 adjust_address (copy_rtx (operands[1]), SImode, 4));
4255 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
4256 && !gpc_reg_operand (operands[1], mode))
4257 operands[1] = force_reg (mode, operands[1]);
4259 if (mode == SFmode && ! TARGET_POWERPC
4260 && TARGET_HARD_FLOAT && TARGET_FPRS
4261 && GET_CODE (operands[0]) == MEM)
4265 if (reload_in_progress || reload_completed)
4266 regnum = true_regnum (operands[1]);
4267 else if (GET_CODE (operands[1]) == REG)
4268 regnum = REGNO (operands[1]);
4272 /* If operands[1] is a register, on POWER it may have
4273 double-precision data in it, so truncate it to single
4275 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4278 newreg = (no_new_pseudos ? copy_rtx (operands[1])
4279 : gen_reg_rtx (mode));
4280 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4281 operands[1] = newreg;
4285 /* Recognize the case where operand[1] is a reference to thread-local
4286 data and load its address to a register. */
4287 if (rs6000_tls_referenced_p (operands[1]))
4289 enum tls_model model;
4290 rtx tmp = operands[1];
4293 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
4295 addend = XEXP (XEXP (tmp, 0), 1);
4296 tmp = XEXP (XEXP (tmp, 0), 0);
4299 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
4300 model = SYMBOL_REF_TLS_MODEL (tmp);
4301 gcc_assert (model != 0);
4303 tmp = rs6000_legitimize_tls_address (tmp, model);
4306 tmp = gen_rtx_PLUS (mode, tmp, addend);
4307 tmp = force_operand (tmp, operands[0]);
4312 /* Handle the case where reload calls us with an invalid address. */
4313 if (reload_in_progress && mode == Pmode
4314 && (! general_operand (operands[1], mode)
4315 || ! nonimmediate_operand (operands[0], mode)))
4318 /* 128-bit constant floating-point values on Darwin should really be
4319 loaded as two parts. */
4320 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
4321 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4323 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4324 know how to get a DFmode SUBREG of a TFmode. */
4325 enum machine_mode imode = (TARGET_E500_DOUBLE ? DFmode : DImode);
4326 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, 0),
4327 simplify_gen_subreg (imode, operands[1], mode, 0),
4329 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode,
4330 GET_MODE_SIZE (imode)),
4331 simplify_gen_subreg (imode, operands[1], mode,
4332 GET_MODE_SIZE (imode)),
4337 /* FIXME: In the long term, this switch statement should go away
4338 and be replaced by a sequence of tests based on things like
4344 if (CONSTANT_P (operands[1])
4345 && GET_CODE (operands[1]) != CONST_INT)
4346 operands[1] = force_const_mem (mode, operands[1]);
4351 rs6000_eliminate_indexed_memrefs (operands);
4357 if (CONSTANT_P (operands[1])
4358 && ! easy_fp_constant (operands[1], mode))
4359 operands[1] = force_const_mem (mode, operands[1]);
4370 if (CONSTANT_P (operands[1])
4371 && !easy_vector_constant (operands[1], mode))
4372 operands[1] = force_const_mem (mode, operands[1]);
4377 /* Use default pattern for address of ELF small data */
4380 && DEFAULT_ABI == ABI_V4
4381 && (GET_CODE (operands[1]) == SYMBOL_REF
4382 || GET_CODE (operands[1]) == CONST)
4383 && small_data_operand (operands[1], mode))
4385 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4389 if (DEFAULT_ABI == ABI_V4
4390 && mode == Pmode && mode == SImode
4391 && flag_pic == 1 && got_operand (operands[1], mode))
4393 emit_insn (gen_movsi_got (operands[0], operands[1]));
4397 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4401 && CONSTANT_P (operands[1])
4402 && GET_CODE (operands[1]) != HIGH
4403 && GET_CODE (operands[1]) != CONST_INT)
4405 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
4407 /* If this is a function address on -mcall-aixdesc,
4408 convert it to the address of the descriptor. */
4409 if (DEFAULT_ABI == ABI_AIX
4410 && GET_CODE (operands[1]) == SYMBOL_REF
4411 && XSTR (operands[1], 0)[0] == '.')
4413 const char *name = XSTR (operands[1], 0);
4415 while (*name == '.')
4417 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4418 CONSTANT_POOL_ADDRESS_P (new_ref)
4419 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4420 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4421 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4422 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4423 operands[1] = new_ref;
4426 if (DEFAULT_ABI == ABI_DARWIN)
4429 if (MACHO_DYNAMIC_NO_PIC_P)
4431 /* Take care of any required data indirection. */
4432 operands[1] = rs6000_machopic_legitimize_pic_address (
4433 operands[1], mode, operands[0]);
4434 if (operands[0] != operands[1])
4435 emit_insn (gen_rtx_SET (VOIDmode,
4436 operands[0], operands[1]));
4440 emit_insn (gen_macho_high (target, operands[1]));
4441 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4445 emit_insn (gen_elf_high (target, operands[1]));
4446 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4450 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4451 and we have put it in the TOC, we just need to make a TOC-relative
4454 && GET_CODE (operands[1]) == SYMBOL_REF
4455 && constant_pool_expr_p (operands[1])
4456 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4457 get_pool_mode (operands[1])))
4459 operands[1] = create_TOC_reference (operands[1]);
4461 else if (mode == Pmode
4462 && CONSTANT_P (operands[1])
4463 && ((GET_CODE (operands[1]) != CONST_INT
4464 && ! easy_fp_constant (operands[1], mode))
4465 || (GET_CODE (operands[1]) == CONST_INT
4466 && num_insns_constant (operands[1], mode) > 2)
4467 || (GET_CODE (operands[0]) == REG
4468 && FP_REGNO_P (REGNO (operands[0]))))
4469 && GET_CODE (operands[1]) != HIGH
4470 && ! legitimate_constant_pool_address_p (operands[1])
4471 && ! toc_relative_expr_p (operands[1]))
4473 /* Emit a USE operation so that the constant isn't deleted if
4474 expensive optimizations are turned on because nobody
4475 references it. This should only be done for operands that
4476 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4477 This should not be done for operands that contain LABEL_REFs.
4478 For now, we just handle the obvious case. */
4479 if (GET_CODE (operands[1]) != LABEL_REF)
4480 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4483 /* Darwin uses a special PIC legitimizer. */
4484 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4487 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4489 if (operands[0] != operands[1])
4490 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4495 /* If we are to limit the number of things we put in the TOC and
4496 this is a symbol plus a constant we can add in one insn,
4497 just put the symbol in the TOC and add the constant. Don't do
4498 this if reload is in progress. */
4499 if (GET_CODE (operands[1]) == CONST
4500 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4501 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4502 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4503 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4504 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4505 && ! side_effects_p (operands[0]))
4508 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4509 rtx other = XEXP (XEXP (operands[1], 0), 1);
4511 sym = force_reg (mode, sym);
4513 emit_insn (gen_addsi3 (operands[0], sym, other));
4515 emit_insn (gen_adddi3 (operands[0], sym, other));
4519 operands[1] = force_const_mem (mode, operands[1]);
4522 && constant_pool_expr_p (XEXP (operands[1], 0))
4523 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4524 get_pool_constant (XEXP (operands[1], 0)),
4525 get_pool_mode (XEXP (operands[1], 0))))
4528 = gen_const_mem (mode,
4529 create_TOC_reference (XEXP (operands[1], 0)));
4530 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4536 rs6000_eliminate_indexed_memrefs (operands);
4540 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4542 gen_rtx_SET (VOIDmode,
4543 operands[0], operands[1]),
4544 gen_rtx_CLOBBER (VOIDmode,
4545 gen_rtx_SCRATCH (SImode)))));
4554 /* Above, we may have called force_const_mem which may have returned
4555 an invalid address. If we can, fix this up; otherwise, reload will
4556 have to deal with it. */
4557 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4558 operands[1] = validize_mem (operands[1]);
4561 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4564 /* Nonzero if we can use a floating-point register to pass this arg. */
4565 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4566 (SCALAR_FLOAT_MODE_P (MODE) \
4567 && (MODE) != SDmode \
4568 && (CUM)->fregno <= FP_ARG_MAX_REG \
4569 && TARGET_HARD_FLOAT && TARGET_FPRS)
4571 /* Nonzero if we can use an AltiVec register to pass this arg. */
4572 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4573 (ALTIVEC_VECTOR_MODE (MODE) \
4574 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4575 && TARGET_ALTIVEC_ABI \
4578 /* Return a nonzero value to say to return the function value in
4579 memory, just as large structures are always returned. TYPE will be
4580 the data type of the value, and FNTYPE will be the type of the
4581 function doing the returning, or @code{NULL} for libcalls.
4583 The AIX ABI for the RS/6000 specifies that all structures are
4584 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4585 specifies that structures <= 8 bytes are returned in r3/r4, but a
4586 draft put them in memory, and GCC used to implement the draft
4587 instead of the final standard. Therefore, aix_struct_return
4588 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4589 compatibility can change DRAFT_V4_STRUCT_RET to override the
4590 default, and -m switches get the final word. See
4591 rs6000_override_options for more details.
4593 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4594 long double support is enabled. These values are returned in memory.
4596 int_size_in_bytes returns -1 for variable size objects, which go in
4597 memory always. The cast to unsigned makes -1 > 8. */
4600 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4602 /* In the darwin64 abi, try to use registers for larger structs
4604 if (rs6000_darwin64_abi
4605 && TREE_CODE (type) == RECORD_TYPE
4606 && int_size_in_bytes (type) > 0)
4608 CUMULATIVE_ARGS valcum;
4612 valcum.fregno = FP_ARG_MIN_REG;
4613 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4614 /* Do a trial code generation as if this were going to be passed
4615 as an argument; if any part goes in memory, we return NULL. */
4616 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4619 /* Otherwise fall through to more conventional ABI rules. */
4622 if (AGGREGATE_TYPE_P (type)
4623 && (aix_struct_return
4624 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4627 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4628 modes only exist for GCC vector types if -maltivec. */
4629 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4630 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4633 /* Return synthetic vectors in memory. */
4634 if (TREE_CODE (type) == VECTOR_TYPE
4635 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4637 static bool warned_for_return_big_vectors = false;
4638 if (!warned_for_return_big_vectors)
4640 warning (0, "GCC vector returned by reference: "
4641 "non-standard ABI extension with no compatibility guarantee");
4642 warned_for_return_big_vectors = true;
4647 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4653 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4654 for a call to a function whose data type is FNTYPE.
4655 For a library call, FNTYPE is 0.
4657 For incoming args we set the number of arguments in the prototype large
4658 so we never return a PARALLEL. */
4661 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4662 rtx libname ATTRIBUTE_UNUSED, int incoming,
4663 int libcall, int n_named_args)
4665 static CUMULATIVE_ARGS zero_cumulative;
4667 *cum = zero_cumulative;
4669 cum->fregno = FP_ARG_MIN_REG;
4670 cum->vregno = ALTIVEC_ARG_MIN_REG;
4671 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4672 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4673 ? CALL_LIBCALL : CALL_NORMAL);
4674 cum->sysv_gregno = GP_ARG_MIN_REG;
4675 cum->stdarg = fntype
4676 && (TYPE_ARG_TYPES (fntype) != 0
4677 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4678 != void_type_node));
4680 cum->nargs_prototype = 0;
4681 if (incoming || cum->prototype)
4682 cum->nargs_prototype = n_named_args;
4684 /* Check for a longcall attribute. */
4685 if ((!fntype && rs6000_default_long_calls)
4687 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4688 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4689 cum->call_cookie |= CALL_LONG;
4691 if (TARGET_DEBUG_ARG)
4693 fprintf (stderr, "\ninit_cumulative_args:");
4696 tree ret_type = TREE_TYPE (fntype);
4697 fprintf (stderr, " ret code = %s,",
4698 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4701 if (cum->call_cookie & CALL_LONG)
4702 fprintf (stderr, " longcall,");
4704 fprintf (stderr, " proto = %d, nargs = %d\n",
4705 cum->prototype, cum->nargs_prototype);
4710 && TARGET_ALTIVEC_ABI
4711 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4713 error ("cannot return value in vector register because"
4714 " altivec instructions are disabled, use -maltivec"
4719 /* Return true if TYPE must be passed on the stack and not in registers. */
4722 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4724 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4725 return must_pass_in_stack_var_size (mode, type);
4727 return must_pass_in_stack_var_size_or_pad (mode, type);
4730 /* If defined, a C expression which determines whether, and in which
4731 direction, to pad out an argument with extra space. The value
4732 should be of type `enum direction': either `upward' to pad above
4733 the argument, `downward' to pad below, or `none' to inhibit
4736 For the AIX ABI structs are always stored left shifted in their
4740 function_arg_padding (enum machine_mode mode, tree type)
4742 #ifndef AGGREGATE_PADDING_FIXED
4743 #define AGGREGATE_PADDING_FIXED 0
4745 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4746 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4749 if (!AGGREGATE_PADDING_FIXED)
4751 /* GCC used to pass structures of the same size as integer types as
4752 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4753 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4754 passed padded downward, except that -mstrict-align further
4755 muddied the water in that multi-component structures of 2 and 4
4756 bytes in size were passed padded upward.
4758 The following arranges for best compatibility with previous
4759 versions of gcc, but removes the -mstrict-align dependency. */
4760 if (BYTES_BIG_ENDIAN)
4762 HOST_WIDE_INT size = 0;
4764 if (mode == BLKmode)
4766 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4767 size = int_size_in_bytes (type);
4770 size = GET_MODE_SIZE (mode);
4772 if (size == 1 || size == 2 || size == 4)
4778 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4780 if (type != 0 && AGGREGATE_TYPE_P (type))
4784 /* Fall back to the default. */
4785 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4788 /* If defined, a C expression that gives the alignment boundary, in bits,
4789 of an argument with the specified mode and type. If it is not defined,
4790 PARM_BOUNDARY is used for all arguments.
4792 V.4 wants long longs and doubles to be double word aligned. Just
4793 testing the mode size is a boneheaded way to do this as it means
4794 that other types such as complex int are also double word aligned.
4795 However, we're stuck with this because changing the ABI might break
4796 existing library interfaces.
4798 Doubleword align SPE vectors.
4799 Quadword align Altivec vectors.
4800 Quadword align large synthetic vector types. */
4803 function_arg_boundary (enum machine_mode mode, tree type)
4805 if (DEFAULT_ABI == ABI_V4
4806 && (GET_MODE_SIZE (mode) == 8
4807 || (TARGET_HARD_FLOAT
4809 && (mode == TFmode || mode == TDmode))))
4811 else if (SPE_VECTOR_MODE (mode)
4812 || (type && TREE_CODE (type) == VECTOR_TYPE
4813 && int_size_in_bytes (type) >= 8
4814 && int_size_in_bytes (type) < 16))
4816 else if (ALTIVEC_VECTOR_MODE (mode)
4817 || (type && TREE_CODE (type) == VECTOR_TYPE
4818 && int_size_in_bytes (type) >= 16))
4820 else if (rs6000_darwin64_abi && mode == BLKmode
4821 && type && TYPE_ALIGN (type) > 64)
4824 return PARM_BOUNDARY;
4827 /* For a function parm of MODE and TYPE, return the starting word in
4828 the parameter area. NWORDS of the parameter area are already used. */
4831 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4834 unsigned int parm_offset;
4836 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4837 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4838 return nwords + (-(parm_offset + nwords) & align);
4841 /* Compute the size (in words) of a function argument. */
4843 static unsigned long
4844 rs6000_arg_size (enum machine_mode mode, tree type)
4848 if (mode != BLKmode)
4849 size = GET_MODE_SIZE (mode);
4851 size = int_size_in_bytes (type);
4854 return (size + 3) >> 2;
4856 return (size + 7) >> 3;
4859 /* Use this to flush pending int fields. */
4862 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4863 HOST_WIDE_INT bitpos)
4865 unsigned int startbit, endbit;
4866 int intregs, intoffset;
4867 enum machine_mode mode;
4869 if (cum->intoffset == -1)
4872 intoffset = cum->intoffset;
4873 cum->intoffset = -1;
4875 if (intoffset % BITS_PER_WORD != 0)
4877 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4879 if (mode == BLKmode)
4881 /* We couldn't find an appropriate mode, which happens,
4882 e.g., in packed structs when there are 3 bytes to load.
4883 Back intoffset back to the beginning of the word in this
4885 intoffset = intoffset & -BITS_PER_WORD;
4889 startbit = intoffset & -BITS_PER_WORD;
4890 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4891 intregs = (endbit - startbit) / BITS_PER_WORD;
4892 cum->words += intregs;
4895 /* The darwin64 ABI calls for us to recurse down through structs,
4896 looking for elements passed in registers. Unfortunately, we have
4897 to track int register count here also because of misalignments
4898 in powerpc alignment mode. */
4901 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4903 HOST_WIDE_INT startbitpos)
4907 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4908 if (TREE_CODE (f) == FIELD_DECL)
4910 HOST_WIDE_INT bitpos = startbitpos;
4911 tree ftype = TREE_TYPE (f);
4912 enum machine_mode mode;
4913 if (ftype == error_mark_node)
4915 mode = TYPE_MODE (ftype);
4917 if (DECL_SIZE (f) != 0
4918 && host_integerp (bit_position (f), 1))
4919 bitpos += int_bit_position (f);
4921 /* ??? FIXME: else assume zero offset. */
4923 if (TREE_CODE (ftype) == RECORD_TYPE)
4924 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4925 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4927 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4928 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4929 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4931 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4933 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4937 else if (cum->intoffset == -1)
4938 cum->intoffset = bitpos;
4942 /* Update the data in CUM to advance over an argument
4943 of mode MODE and data type TYPE.
4944 (TYPE is null for libcalls where that information may not be available.)
4946 Note that for args passed by reference, function_arg will be called
4947 with MODE and TYPE set to that of the pointer to the arg, not the arg
4951 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4952 tree type, int named, int depth)
4956 /* Only tick off an argument if we're not recursing. */
4958 cum->nargs_prototype--;
4960 if (TARGET_ALTIVEC_ABI
4961 && (ALTIVEC_VECTOR_MODE (mode)
4962 || (type && TREE_CODE (type) == VECTOR_TYPE
4963 && int_size_in_bytes (type) == 16)))
4967 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4970 if (!TARGET_ALTIVEC)
4971 error ("cannot pass argument in vector register because"
4972 " altivec instructions are disabled, use -maltivec"
4975 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4976 even if it is going to be passed in a vector register.
4977 Darwin does the same for variable-argument functions. */
4978 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4979 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4989 /* Vector parameters must be 16-byte aligned. This places
4990 them at 2 mod 4 in terms of words in 32-bit mode, since
4991 the parameter save area starts at offset 24 from the
4992 stack. In 64-bit mode, they just have to start on an
4993 even word, since the parameter save area is 16-byte
4994 aligned. Space for GPRs is reserved even if the argument
4995 will be passed in memory. */
4997 align = (2 - cum->words) & 3;
4999 align = cum->words & 1;
5000 cum->words += align + rs6000_arg_size (mode, type);
5002 if (TARGET_DEBUG_ARG)
5004 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
5006 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
5007 cum->nargs_prototype, cum->prototype,
5008 GET_MODE_NAME (mode));
5012 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
5014 && cum->sysv_gregno <= GP_ARG_MAX_REG)
5017 else if (rs6000_darwin64_abi
5019 && TREE_CODE (type) == RECORD_TYPE
5020 && (size = int_size_in_bytes (type)) > 0)
5022 /* Variable sized types have size == -1 and are
5023 treated as if consisting entirely of ints.
5024 Pad to 16 byte boundary if needed. */
5025 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5026 && (cum->words % 2) != 0)
5028 /* For varargs, we can just go up by the size of the struct. */
5030 cum->words += (size + 7) / 8;
5033 /* It is tempting to say int register count just goes up by
5034 sizeof(type)/8, but this is wrong in a case such as
5035 { int; double; int; } [powerpc alignment]. We have to
5036 grovel through the fields for these too. */
5038 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
5039 rs6000_darwin64_record_arg_advance_flush (cum,
5040 size * BITS_PER_UNIT);
5043 else if (DEFAULT_ABI == ABI_V4)
5045 if (TARGET_HARD_FLOAT && TARGET_FPRS
5046 && (mode == SFmode || mode == DFmode
5047 || mode == DDmode || mode == TDmode
5048 || (mode == TFmode && !TARGET_IEEEQUAD)))
5050 /* _Decimal128 must use an even/odd register pair. This assumes
5051 that the register number is odd when fregno is odd. */
5052 if (mode == TDmode && (cum->fregno % 2) == 1)
5055 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5056 <= FP_ARG_V4_MAX_REG)
5057 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5060 cum->fregno = FP_ARG_V4_MAX_REG + 1;
5061 if (mode == DFmode || mode == TFmode || mode == DDmode || mode == TDmode)
5062 cum->words += cum->words & 1;
5063 cum->words += rs6000_arg_size (mode, type);
5068 int n_words = rs6000_arg_size (mode, type);
5069 int gregno = cum->sysv_gregno;
5071 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5072 (r7,r8) or (r9,r10). As does any other 2 word item such
5073 as complex int due to a historical mistake. */
5075 gregno += (1 - gregno) & 1;
5077 /* Multi-reg args are not split between registers and stack. */
5078 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5080 /* Long long and SPE vectors are aligned on the stack.
5081 So are other 2 word items such as complex int due to
5082 a historical mistake. */
5084 cum->words += cum->words & 1;
5085 cum->words += n_words;
5088 /* Note: continuing to accumulate gregno past when we've started
5089 spilling to the stack indicates the fact that we've started
5090 spilling to the stack to expand_builtin_saveregs. */
5091 cum->sysv_gregno = gregno + n_words;
5094 if (TARGET_DEBUG_ARG)
5096 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5097 cum->words, cum->fregno);
5098 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5099 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5100 fprintf (stderr, "mode = %4s, named = %d\n",
5101 GET_MODE_NAME (mode), named);
5106 int n_words = rs6000_arg_size (mode, type);
5107 int start_words = cum->words;
5108 int align_words = rs6000_parm_start (mode, type, start_words);
5110 cum->words = align_words + n_words;
5112 if (SCALAR_FLOAT_MODE_P (mode)
5114 && TARGET_HARD_FLOAT && TARGET_FPRS)
5116 /* _Decimal128 must be passed in an even/odd float register pair.
5117 This assumes that the register number is odd when fregno is
5119 if (mode == TDmode && (cum->fregno % 2) == 1)
5121 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5124 if (TARGET_DEBUG_ARG)
5126 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5127 cum->words, cum->fregno);
5128 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5129 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5130 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5131 named, align_words - start_words, depth);
5137 spe_build_register_parallel (enum machine_mode mode, int gregno)
5144 r1 = gen_rtx_REG (DImode, gregno);
5145 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5146 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
5150 r1 = gen_rtx_REG (DImode, gregno);
5151 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5152 r3 = gen_rtx_REG (DImode, gregno + 2);
5153 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5154 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
5157 r1 = gen_rtx_REG (DImode, gregno);
5158 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5159 r3 = gen_rtx_REG (DImode, gregno + 2);
5160 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5161 r5 = gen_rtx_REG (DImode, gregno + 4);
5162 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
5163 r7 = gen_rtx_REG (DImode, gregno + 6);
5164 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
5165 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
5172 /* Determine where to put a SIMD argument on the SPE. */
5174 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5177 int gregno = cum->sysv_gregno;
5179 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5180 are passed and returned in a pair of GPRs for ABI compatibility. */
5181 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode
5182 || mode == TFmode || mode == TCmode))
5184 int n_words = rs6000_arg_size (mode, type);
5186 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5188 gregno += (1 - gregno) & 1;
5190 /* Multi-reg args are not split between registers and stack. */
5191 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5194 return spe_build_register_parallel (mode, gregno);
5198 int n_words = rs6000_arg_size (mode, type);
5200 /* SPE vectors are put in odd registers. */
5201 if (n_words == 2 && (gregno & 1) == 0)
5204 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5207 enum machine_mode m = SImode;
5209 r1 = gen_rtx_REG (m, gregno);
5210 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5211 r2 = gen_rtx_REG (m, gregno + 1);
5212 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5213 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5220 if (gregno <= GP_ARG_MAX_REG)
5221 return gen_rtx_REG (mode, gregno);
5227 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5228 structure between cum->intoffset and bitpos to integer registers. */
5231 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
5232 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
5234 enum machine_mode mode;
5236 unsigned int startbit, endbit;
5237 int this_regno, intregs, intoffset;
5240 if (cum->intoffset == -1)
5243 intoffset = cum->intoffset;
5244 cum->intoffset = -1;
5246 /* If this is the trailing part of a word, try to only load that
5247 much into the register. Otherwise load the whole register. Note
5248 that in the latter case we may pick up unwanted bits. It's not a
5249 problem at the moment but may wish to revisit. */
5251 if (intoffset % BITS_PER_WORD != 0)
5253 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5255 if (mode == BLKmode)
5257 /* We couldn't find an appropriate mode, which happens,
5258 e.g., in packed structs when there are 3 bytes to load.
5259 Back intoffset back to the beginning of the word in this
5261 intoffset = intoffset & -BITS_PER_WORD;
5268 startbit = intoffset & -BITS_PER_WORD;
5269 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5270 intregs = (endbit - startbit) / BITS_PER_WORD;
5271 this_regno = cum->words + intoffset / BITS_PER_WORD;
5273 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
5276 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
5280 intoffset /= BITS_PER_UNIT;
5283 regno = GP_ARG_MIN_REG + this_regno;
5284 reg = gen_rtx_REG (mode, regno);
5286 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5289 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5293 while (intregs > 0);
5296 /* Recursive workhorse for the following. */
5299 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
5300 HOST_WIDE_INT startbitpos, rtx rvec[],
5305 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5306 if (TREE_CODE (f) == FIELD_DECL)
5308 HOST_WIDE_INT bitpos = startbitpos;
5309 tree ftype = TREE_TYPE (f);
5310 enum machine_mode mode;
5311 if (ftype == error_mark_node)
5313 mode = TYPE_MODE (ftype);
5315 if (DECL_SIZE (f) != 0
5316 && host_integerp (bit_position (f), 1))
5317 bitpos += int_bit_position (f);
5319 /* ??? FIXME: else assume zero offset. */
5321 if (TREE_CODE (ftype) == RECORD_TYPE)
5322 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
5323 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
5328 case SCmode: mode = SFmode; break;
5329 case DCmode: mode = DFmode; break;
5330 case TCmode: mode = TFmode; break;
5334 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5336 = gen_rtx_EXPR_LIST (VOIDmode,
5337 gen_rtx_REG (mode, cum->fregno++),
5338 GEN_INT (bitpos / BITS_PER_UNIT));
5339 if (mode == TFmode || mode == TDmode)
5342 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
5344 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5346 = gen_rtx_EXPR_LIST (VOIDmode,
5347 gen_rtx_REG (mode, cum->vregno++),
5348 GEN_INT (bitpos / BITS_PER_UNIT));
5350 else if (cum->intoffset == -1)
5351 cum->intoffset = bitpos;
5355 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5356 the register(s) to be used for each field and subfield of a struct
5357 being passed by value, along with the offset of where the
5358 register's value may be found in the block. FP fields go in FP
5359 register, vector fields go in vector registers, and everything
5360 else goes in int registers, packed as in memory.
5362 This code is also used for function return values. RETVAL indicates
5363 whether this is the case.
5365 Much of this is taken from the SPARC V9 port, which has a similar
5366 calling convention. */
5369 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
5370 int named, bool retval)
5372 rtx rvec[FIRST_PSEUDO_REGISTER];
5373 int k = 1, kbase = 1;
5374 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5375 /* This is a copy; modifications are not visible to our caller. */
5376 CUMULATIVE_ARGS copy_cum = *orig_cum;
5377 CUMULATIVE_ARGS *cum = ©_cum;
5379 /* Pad to 16 byte boundary if needed. */
5380 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5381 && (cum->words % 2) != 0)
5388 /* Put entries into rvec[] for individual FP and vector fields, and
5389 for the chunks of memory that go in int regs. Note we start at
5390 element 1; 0 is reserved for an indication of using memory, and
5391 may or may not be filled in below. */
5392 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5393 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5395 /* If any part of the struct went on the stack put all of it there.
5396 This hack is because the generic code for
5397 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5398 parts of the struct are not at the beginning. */
5402 return NULL_RTX; /* doesn't go in registers at all */
5404 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5406 if (k > 1 || cum->use_stack)
5407 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5412 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5415 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5419 rtx rvec[GP_ARG_NUM_REG + 1];
5421 if (align_words >= GP_ARG_NUM_REG)
5424 n_units = rs6000_arg_size (mode, type);
5426 /* Optimize the simple case where the arg fits in one gpr, except in
5427 the case of BLKmode due to assign_parms assuming that registers are
5428 BITS_PER_WORD wide. */
5430 || (n_units == 1 && mode != BLKmode))
5431 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5434 if (align_words + n_units > GP_ARG_NUM_REG)
5435 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5436 using a magic NULL_RTX component.
5437 This is not strictly correct. Only some of the arg belongs in
5438 memory, not all of it. However, the normal scheme using
5439 function_arg_partial_nregs can result in unusual subregs, eg.
5440 (subreg:SI (reg:DF) 4), which are not handled well. The code to
5441 store the whole arg to memory is often more efficient than code
5442 to store pieces, and we know that space is available in the right
5443 place for the whole arg. */
5444 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5449 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5450 rtx off = GEN_INT (i++ * 4);
5451 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5453 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5455 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5458 /* Determine where to put an argument to a function.
5459 Value is zero to push the argument on the stack,
5460 or a hard register in which to store the argument.
5462 MODE is the argument's machine mode.
5463 TYPE is the data type of the argument (as a tree).
5464 This is null for libcalls where that information may
5466 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5467 the preceding args and about the function being called. It is
5468 not modified in this routine.
5469 NAMED is nonzero if this argument is a named parameter
5470 (otherwise it is an extra parameter matching an ellipsis).
5472 On RS/6000 the first eight words of non-FP are normally in registers
5473 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5474 Under V.4, the first 8 FP args are in registers.
5476 If this is floating-point and no prototype is specified, we use
5477 both an FP and integer register (or possibly FP reg and stack). Library
5478 functions (when CALL_LIBCALL is set) always have the proper types for args,
5479 so we can pass the FP value just in one register. emit_library_function
5480 doesn't support PARALLEL anyway.
5482 Note that for args passed by reference, function_arg will be called
5483 with MODE and TYPE set to that of the pointer to the arg, not the arg
5487 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5488 tree type, int named)
5490 enum rs6000_abi abi = DEFAULT_ABI;
5492 /* Return a marker to indicate whether CR1 needs to set or clear the
5493 bit that V.4 uses to say fp args were passed in registers.
5494 Assume that we don't need the marker for software floating point,
5495 or compiler generated library calls. */
5496 if (mode == VOIDmode)
5499 && (cum->call_cookie & CALL_LIBCALL) == 0
5501 || (cum->nargs_prototype < 0
5502 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5504 /* For the SPE, we need to crxor CR6 always. */
5506 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5507 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5508 return GEN_INT (cum->call_cookie
5509 | ((cum->fregno == FP_ARG_MIN_REG)
5510 ? CALL_V4_SET_FP_ARGS
5511 : CALL_V4_CLEAR_FP_ARGS));
5514 return GEN_INT (cum->call_cookie);
5517 if (rs6000_darwin64_abi && mode == BLKmode
5518 && TREE_CODE (type) == RECORD_TYPE)
5520 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5521 if (rslt != NULL_RTX)
5523 /* Else fall through to usual handling. */
5526 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5527 if (TARGET_64BIT && ! cum->prototype)
5529 /* Vector parameters get passed in vector register
5530 and also in GPRs or memory, in absence of prototype. */
5533 align_words = (cum->words + 1) & ~1;
5535 if (align_words >= GP_ARG_NUM_REG)
5541 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5543 return gen_rtx_PARALLEL (mode,
5545 gen_rtx_EXPR_LIST (VOIDmode,
5547 gen_rtx_EXPR_LIST (VOIDmode,
5548 gen_rtx_REG (mode, cum->vregno),
5552 return gen_rtx_REG (mode, cum->vregno);
5553 else if (TARGET_ALTIVEC_ABI
5554 && (ALTIVEC_VECTOR_MODE (mode)
5555 || (type && TREE_CODE (type) == VECTOR_TYPE
5556 && int_size_in_bytes (type) == 16)))
5558 if (named || abi == ABI_V4)
5562 /* Vector parameters to varargs functions under AIX or Darwin
5563 get passed in memory and possibly also in GPRs. */
5564 int align, align_words, n_words;
5565 enum machine_mode part_mode;
5567 /* Vector parameters must be 16-byte aligned. This places them at
5568 2 mod 4 in terms of words in 32-bit mode, since the parameter
5569 save area starts at offset 24 from the stack. In 64-bit mode,
5570 they just have to start on an even word, since the parameter
5571 save area is 16-byte aligned. */
5573 align = (2 - cum->words) & 3;
5575 align = cum->words & 1;
5576 align_words = cum->words + align;
5578 /* Out of registers? Memory, then. */
5579 if (align_words >= GP_ARG_NUM_REG)
5582 if (TARGET_32BIT && TARGET_POWERPC64)
5583 return rs6000_mixed_function_arg (mode, type, align_words);
5585 /* The vector value goes in GPRs. Only the part of the
5586 value in GPRs is reported here. */
5588 n_words = rs6000_arg_size (mode, type);
5589 if (align_words + n_words > GP_ARG_NUM_REG)
5590 /* Fortunately, there are only two possibilities, the value
5591 is either wholly in GPRs or half in GPRs and half not. */
5594 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5597 else if (TARGET_SPE_ABI && TARGET_SPE
5598 && (SPE_VECTOR_MODE (mode)
5599 || (TARGET_E500_DOUBLE && (mode == DFmode
5604 || mode == TCmode))))
5605 return rs6000_spe_function_arg (cum, mode, type);
5607 else if (abi == ABI_V4)
5609 if (TARGET_HARD_FLOAT && TARGET_FPRS
5610 && (mode == SFmode || mode == DFmode
5611 || (mode == TFmode && !TARGET_IEEEQUAD)
5612 || mode == DDmode || mode == TDmode))
5614 /* _Decimal128 must use an even/odd register pair. This assumes
5615 that the register number is odd when fregno is odd. */
5616 if (mode == TDmode && (cum->fregno % 2) == 1)
5619 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5620 <= FP_ARG_V4_MAX_REG)
5621 return gen_rtx_REG (mode, cum->fregno);
5627 int n_words = rs6000_arg_size (mode, type);
5628 int gregno = cum->sysv_gregno;
5630 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5631 (r7,r8) or (r9,r10). As does any other 2 word item such
5632 as complex int due to a historical mistake. */
5634 gregno += (1 - gregno) & 1;
5636 /* Multi-reg args are not split between registers and stack. */
5637 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5640 if (TARGET_32BIT && TARGET_POWERPC64)
5641 return rs6000_mixed_function_arg (mode, type,
5642 gregno - GP_ARG_MIN_REG);
5643 return gen_rtx_REG (mode, gregno);
5648 int align_words = rs6000_parm_start (mode, type, cum->words);
5650 /* _Decimal128 must be passed in an even/odd float register pair.
5651 This assumes that the register number is odd when fregno is odd. */
5652 if (mode == TDmode && (cum->fregno % 2) == 1)
5655 if (USE_FP_FOR_ARG_P (cum, mode, type))
5657 rtx rvec[GP_ARG_NUM_REG + 1];
5661 enum machine_mode fmode = mode;
5662 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5664 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5666 /* Currently, we only ever need one reg here because complex
5667 doubles are split. */
5668 gcc_assert (cum->fregno == FP_ARG_MAX_REG
5669 && (fmode == TFmode || fmode == TDmode));
5671 /* Long double or _Decimal128 split over regs and memory. */
5672 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
5675 /* Do we also need to pass this arg in the parameter save
5678 && (cum->nargs_prototype <= 0
5679 || (DEFAULT_ABI == ABI_AIX
5681 && align_words >= GP_ARG_NUM_REG)));
5683 if (!needs_psave && mode == fmode)
5684 return gen_rtx_REG (fmode, cum->fregno);
5689 /* Describe the part that goes in gprs or the stack.
5690 This piece must come first, before the fprs. */
5691 if (align_words < GP_ARG_NUM_REG)
5693 unsigned long n_words = rs6000_arg_size (mode, type);
5695 if (align_words + n_words > GP_ARG_NUM_REG
5696 || (TARGET_32BIT && TARGET_POWERPC64))
5698 /* If this is partially on the stack, then we only
5699 include the portion actually in registers here. */
5700 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5703 if (align_words + n_words > GP_ARG_NUM_REG)
5704 /* Not all of the arg fits in gprs. Say that it
5705 goes in memory too, using a magic NULL_RTX
5706 component. Also see comment in
5707 rs6000_mixed_function_arg for why the normal
5708 function_arg_partial_nregs scheme doesn't work
5710 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5714 r = gen_rtx_REG (rmode,
5715 GP_ARG_MIN_REG + align_words);
5716 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5717 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5719 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5723 /* The whole arg fits in gprs. */
5724 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5725 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5729 /* It's entirely in memory. */
5730 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5733 /* Describe where this piece goes in the fprs. */
5734 r = gen_rtx_REG (fmode, cum->fregno);
5735 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5737 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5739 else if (align_words < GP_ARG_NUM_REG)
5741 if (TARGET_32BIT && TARGET_POWERPC64)
5742 return rs6000_mixed_function_arg (mode, type, align_words);
5744 if (mode == BLKmode)
5747 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5754 /* For an arg passed partly in registers and partly in memory, this is
5755 the number of bytes passed in registers. For args passed entirely in
5756 registers or entirely in memory, zero. When an arg is described by a
5757 PARALLEL, perhaps using more than one register type, this function
5758 returns the number of bytes used by the first element of the PARALLEL. */
5761 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5762 tree type, bool named)
5767 if (DEFAULT_ABI == ABI_V4)
5770 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5771 && cum->nargs_prototype >= 0)
5774 /* In this complicated case we just disable the partial_nregs code. */
5775 if (rs6000_darwin64_abi && mode == BLKmode
5776 && TREE_CODE (type) == RECORD_TYPE
5777 && int_size_in_bytes (type) > 0)
5780 align_words = rs6000_parm_start (mode, type, cum->words);
5782 if (USE_FP_FOR_ARG_P (cum, mode, type))
5784 /* If we are passing this arg in the fixed parameter save area
5785 (gprs or memory) as well as fprs, then this function should
5786 return the number of partial bytes passed in the parameter
5787 save area rather than partial bytes passed in fprs. */
5789 && (cum->nargs_prototype <= 0
5790 || (DEFAULT_ABI == ABI_AIX
5792 && align_words >= GP_ARG_NUM_REG)))
5794 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
5795 > FP_ARG_MAX_REG + 1)
5796 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5797 else if (cum->nargs_prototype >= 0)
5801 if (align_words < GP_ARG_NUM_REG
5802 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5803 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5805 if (ret != 0 && TARGET_DEBUG_ARG)
5806 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5811 /* A C expression that indicates when an argument must be passed by
5812 reference. If nonzero for an argument, a copy of that argument is
5813 made in memory and a pointer to the argument is passed instead of
5814 the argument itself. The pointer is passed in whatever way is
5815 appropriate for passing a pointer to that type.
5817 Under V.4, aggregates and long double are passed by reference.
5819 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5820 reference unless the AltiVec vector extension ABI is in force.
5822 As an extension to all ABIs, variable sized types are passed by
5826 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5827 enum machine_mode mode, tree type,
5828 bool named ATTRIBUTE_UNUSED)
5830 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
5832 if (TARGET_DEBUG_ARG)
5833 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5840 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5842 if (TARGET_DEBUG_ARG)
5843 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5847 if (int_size_in_bytes (type) < 0)
5849 if (TARGET_DEBUG_ARG)
5850 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5854 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5855 modes only exist for GCC vector types if -maltivec. */
5856 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5858 if (TARGET_DEBUG_ARG)
5859 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5863 /* Pass synthetic vectors in memory. */
5864 if (TREE_CODE (type) == VECTOR_TYPE
5865 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5867 static bool warned_for_pass_big_vectors = false;
5868 if (TARGET_DEBUG_ARG)
5869 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5870 if (!warned_for_pass_big_vectors)
5872 warning (0, "GCC vector passed by reference: "
5873 "non-standard ABI extension with no compatibility guarantee");
5874 warned_for_pass_big_vectors = true;
5883 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5886 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5891 for (i = 0; i < nregs; i++)
5893 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5894 if (reload_completed)
5896 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5899 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5900 i * GET_MODE_SIZE (reg_mode));
5903 tem = replace_equiv_address (tem, XEXP (tem, 0));
5907 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5911 /* Perform any needed actions needed for a function that is receiving a
5912 variable number of arguments.
5916 MODE and TYPE are the mode and type of the current parameter.
5918 PRETEND_SIZE is a variable that should be set to the amount of stack
5919 that must be pushed by the prolog to pretend that our caller pushed
5922 Normally, this macro will push all remaining incoming registers on the
5923 stack and set PRETEND_SIZE to the length of the registers pushed. */
5926 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5927 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5930 CUMULATIVE_ARGS next_cum;
5931 int reg_size = TARGET_32BIT ? 4 : 8;
5932 rtx save_area = NULL_RTX, mem;
5933 int first_reg_offset, set;
5935 /* Skip the last named argument. */
5937 function_arg_advance (&next_cum, mode, type, 1, 0);
5939 if (DEFAULT_ABI == ABI_V4)
5941 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5945 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
5946 HOST_WIDE_INT offset = 0;
5948 /* Try to optimize the size of the varargs save area.
5949 The ABI requires that ap.reg_save_area is doubleword
5950 aligned, but we don't need to allocate space for all
5951 the bytes, only those to which we actually will save
5953 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
5954 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
5955 if (TARGET_HARD_FLOAT && TARGET_FPRS
5956 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5957 && cfun->va_list_fpr_size)
5960 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
5961 * UNITS_PER_FP_WORD;
5962 if (cfun->va_list_fpr_size
5963 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5964 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
5966 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5967 * UNITS_PER_FP_WORD;
5971 offset = -((first_reg_offset * reg_size) & ~7);
5972 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
5974 gpr_reg_num = cfun->va_list_gpr_size;
5975 if (reg_size == 4 && (first_reg_offset & 1))
5978 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
5981 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
5983 - (int) (GP_ARG_NUM_REG * reg_size);
5985 if (gpr_size + fpr_size)
5988 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
5989 gcc_assert (GET_CODE (reg_save_area) == MEM);
5990 reg_save_area = XEXP (reg_save_area, 0);
5991 if (GET_CODE (reg_save_area) == PLUS)
5993 gcc_assert (XEXP (reg_save_area, 0)
5994 == virtual_stack_vars_rtx);
5995 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
5996 offset += INTVAL (XEXP (reg_save_area, 1));
5999 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
6002 cfun->machine->varargs_save_offset = offset;
6003 save_area = plus_constant (virtual_stack_vars_rtx, offset);
6008 first_reg_offset = next_cum.words;
6009 save_area = virtual_incoming_args_rtx;
6011 if (targetm.calls.must_pass_in_stack (mode, type))
6012 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
6015 set = get_varargs_alias_set ();
6016 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
6017 && cfun->va_list_gpr_size)
6019 int nregs = GP_ARG_NUM_REG - first_reg_offset;
6021 if (va_list_gpr_counter_field)
6023 /* V4 va_list_gpr_size counts number of registers needed. */
6024 if (nregs > cfun->va_list_gpr_size)
6025 nregs = cfun->va_list_gpr_size;
6029 /* char * va_list instead counts number of bytes needed. */
6030 if (nregs > cfun->va_list_gpr_size / reg_size)
6031 nregs = cfun->va_list_gpr_size / reg_size;
6034 mem = gen_rtx_MEM (BLKmode,
6035 plus_constant (save_area,
6036 first_reg_offset * reg_size));
6037 MEM_NOTRAP_P (mem) = 1;
6038 set_mem_alias_set (mem, set);
6039 set_mem_align (mem, BITS_PER_WORD);
6041 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
6045 /* Save FP registers if needed. */
6046 if (DEFAULT_ABI == ABI_V4
6047 && TARGET_HARD_FLOAT && TARGET_FPRS
6049 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6050 && cfun->va_list_fpr_size)
6052 int fregno = next_cum.fregno, nregs;
6053 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
6054 rtx lab = gen_label_rtx ();
6055 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
6056 * UNITS_PER_FP_WORD);
6059 (gen_rtx_SET (VOIDmode,
6061 gen_rtx_IF_THEN_ELSE (VOIDmode,
6062 gen_rtx_NE (VOIDmode, cr1,
6064 gen_rtx_LABEL_REF (VOIDmode, lab),
6068 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
6069 fregno++, off += UNITS_PER_FP_WORD, nregs++)
6071 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
6072 MEM_NOTRAP_P (mem) = 1;
6073 set_mem_alias_set (mem, set);
6074 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
6075 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
6082 /* Create the va_list data type. */
6085 rs6000_build_builtin_va_list (void)
6087 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
6089 /* For AIX, prefer 'char *' because that's what the system
6090 header files like. */
6091 if (DEFAULT_ABI != ABI_V4)
6092 return build_pointer_type (char_type_node);
6094 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6095 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6097 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
6098 unsigned_char_type_node);
6099 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
6100 unsigned_char_type_node);
6101 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6103 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
6104 short_unsigned_type_node);
6105 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6107 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6110 va_list_gpr_counter_field = f_gpr;
6111 va_list_fpr_counter_field = f_fpr;
6113 DECL_FIELD_CONTEXT (f_gpr) = record;
6114 DECL_FIELD_CONTEXT (f_fpr) = record;
6115 DECL_FIELD_CONTEXT (f_res) = record;
6116 DECL_FIELD_CONTEXT (f_ovf) = record;
6117 DECL_FIELD_CONTEXT (f_sav) = record;
6119 TREE_CHAIN (record) = type_decl;
6120 TYPE_NAME (record) = type_decl;
6121 TYPE_FIELDS (record) = f_gpr;
6122 TREE_CHAIN (f_gpr) = f_fpr;
6123 TREE_CHAIN (f_fpr) = f_res;
6124 TREE_CHAIN (f_res) = f_ovf;
6125 TREE_CHAIN (f_ovf) = f_sav;
6127 layout_type (record);
6129 /* The correct type is an array type of one element. */
6130 return build_array_type (record, build_index_type (size_zero_node));
6133 /* Implement va_start. */
6136 rs6000_va_start (tree valist, rtx nextarg)
6138 HOST_WIDE_INT words, n_gpr, n_fpr;
6139 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6140 tree gpr, fpr, ovf, sav, t;
6142 /* Only SVR4 needs something special. */
6143 if (DEFAULT_ABI != ABI_V4)
6145 std_expand_builtin_va_start (valist, nextarg);
6149 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6150 f_fpr = TREE_CHAIN (f_gpr);
6151 f_res = TREE_CHAIN (f_fpr);
6152 f_ovf = TREE_CHAIN (f_res);
6153 f_sav = TREE_CHAIN (f_ovf);
6155 valist = build_va_arg_indirect_ref (valist);
6156 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6157 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6158 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6159 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6161 /* Count number of gp and fp argument registers used. */
6162 words = current_function_args_info.words;
6163 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
6165 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
6168 if (TARGET_DEBUG_ARG)
6169 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
6170 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
6171 words, n_gpr, n_fpr);
6173 if (cfun->va_list_gpr_size)
6175 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr,
6176 build_int_cst (NULL_TREE, n_gpr));
6177 TREE_SIDE_EFFECTS (t) = 1;
6178 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6181 if (cfun->va_list_fpr_size)
6183 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr,
6184 build_int_cst (NULL_TREE, n_fpr));
6185 TREE_SIDE_EFFECTS (t) = 1;
6186 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6189 /* Find the overflow area. */
6190 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
6192 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t,
6193 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
6194 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6195 TREE_SIDE_EFFECTS (t) = 1;
6196 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6198 /* If there were no va_arg invocations, don't set up the register
6200 if (!cfun->va_list_gpr_size
6201 && !cfun->va_list_fpr_size
6202 && n_gpr < GP_ARG_NUM_REG
6203 && n_fpr < FP_ARG_V4_MAX_REG)
6206 /* Find the register save area. */
6207 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
6208 if (cfun->machine->varargs_save_offset)
6209 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
6210 build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset));
6211 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (sav), sav, t);
6212 TREE_SIDE_EFFECTS (t) = 1;
6213 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6216 /* Implement va_arg. */
6219 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6221 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6222 tree gpr, fpr, ovf, sav, reg, t, u;
6223 int size, rsize, n_reg, sav_ofs, sav_scale;
6224 tree lab_false, lab_over, addr;
6226 tree ptrtype = build_pointer_type (type);
6229 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6231 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
6232 return build_va_arg_indirect_ref (t);
6235 if (DEFAULT_ABI != ABI_V4)
6237 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
6239 tree elem_type = TREE_TYPE (type);
6240 enum machine_mode elem_mode = TYPE_MODE (elem_type);
6241 int elem_size = GET_MODE_SIZE (elem_mode);
6243 if (elem_size < UNITS_PER_WORD)
6245 tree real_part, imag_part;
6246 tree post = NULL_TREE;
6248 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6250 /* Copy the value into a temporary, lest the formal temporary
6251 be reused out from under us. */
6252 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
6253 append_to_statement_list (post, pre_p);
6255 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6258 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
6262 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6265 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6266 f_fpr = TREE_CHAIN (f_gpr);
6267 f_res = TREE_CHAIN (f_fpr);
6268 f_ovf = TREE_CHAIN (f_res);
6269 f_sav = TREE_CHAIN (f_ovf);
6271 valist = build_va_arg_indirect_ref (valist);
6272 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6273 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6274 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6275 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6277 size = int_size_in_bytes (type);
6278 rsize = (size + 3) / 4;
6281 if (TARGET_HARD_FLOAT && TARGET_FPRS
6282 && (TYPE_MODE (type) == SFmode
6283 || TYPE_MODE (type) == DFmode
6284 || TYPE_MODE (type) == TFmode
6285 || TYPE_MODE (type) == DDmode
6286 || TYPE_MODE (type) == TDmode))
6288 /* FP args go in FP registers, if present. */
6290 n_reg = (size + 7) / 8;
6293 if (TYPE_MODE (type) != SFmode)
6298 /* Otherwise into GP registers. */
6307 /* Pull the value out of the saved registers.... */
6310 addr = create_tmp_var (ptr_type_node, "addr");
6311 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6313 /* AltiVec vectors never go in registers when -mabi=altivec. */
6314 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6318 lab_false = create_artificial_label ();
6319 lab_over = create_artificial_label ();
6321 /* Long long and SPE vectors are aligned in the registers.
6322 As are any other 2 gpr item such as complex int due to a
6323 historical mistake. */
6325 if (n_reg == 2 && reg == gpr)
6328 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
6329 size_int (n_reg - 1));
6330 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
6332 /* _Decimal128 is passed in even/odd fpr pairs; the stored
6333 reg number is 0 for f1, so we want to make it odd. */
6334 else if (reg == fpr && TYPE_MODE (type) == TDmode)
6337 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), reg, size_int (1));
6338 u = build2 (MODIFY_EXPR, void_type_node, reg, t);
6341 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6342 t = build2 (GE_EXPR, boolean_type_node, u, t);
6343 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6344 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6345 gimplify_and_add (t, pre_p);
6349 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6351 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
6352 u = build1 (CONVERT_EXPR, integer_type_node, u);
6353 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
6354 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
6356 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6357 gimplify_and_add (t, pre_p);
6359 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6360 gimplify_and_add (t, pre_p);
6362 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6363 append_to_statement_list (t, pre_p);
6365 if ((n_reg == 2 && !regalign) || n_reg > 2)
6367 /* Ensure that we don't find any more args in regs.
6368 Alignment has taken care of for special cases. */
6369 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (reg), reg, size_int (8));
6370 gimplify_and_add (t, pre_p);
6374 /* ... otherwise out of the overflow area. */
6376 /* Care for on-stack alignment if needed. */
6380 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6381 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6382 build_int_cst (NULL_TREE, -align));
6384 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6386 u = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6387 gimplify_and_add (u, pre_p);
6389 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6390 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6391 gimplify_and_add (t, pre_p);
6395 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6396 append_to_statement_list (t, pre_p);
6399 if (STRICT_ALIGNMENT
6400 && (TYPE_ALIGN (type)
6401 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
6403 /* The value (of type complex double, for example) may not be
6404 aligned in memory in the saved registers, so copy via a
6405 temporary. (This is the same code as used for SPARC.) */
6406 tree tmp = create_tmp_var (type, "va_arg_tmp");
6407 tree dest_addr = build_fold_addr_expr (tmp);
6409 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
6410 3, dest_addr, addr, size_int (rsize * 4));
6412 gimplify_and_add (copy, pre_p);
6416 addr = fold_convert (ptrtype, addr);
6417 return build_va_arg_indirect_ref (addr);
6423 def_builtin (int mask, const char *name, tree type, int code)
6425 if (mask & target_flags)
6427 if (rs6000_builtin_decls[code])
6430 rs6000_builtin_decls[code] =
6431 add_builtin_function (name, type, code, BUILT_IN_MD,
6436 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6438 static const struct builtin_description bdesc_3arg[] =
6440 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6441 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6442 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6443 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6444 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6445 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6446 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6447 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6448 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6449 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6450 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6451 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6452 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6453 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6454 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6455 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6456 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6457 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6458 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6459 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6460 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6461 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6462 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6464 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6465 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6466 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6467 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6468 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6469 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6470 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6471 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6472 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6473 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6474 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6475 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6476 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6477 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6478 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6481 /* DST operations: void foo (void *, const int, const char). */
6483 static const struct builtin_description bdesc_dst[] =
6485 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6486 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6487 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6488 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6490 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6491 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6492 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6493 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6496 /* Simple binary operations: VECc = foo (VECa, VECb). */
6498 static struct builtin_description bdesc_2arg[] =
6500 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6501 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6502 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6503 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6504 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6505 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6506 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6507 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6508 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6509 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6510 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6511 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6512 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6513 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6514 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6515 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6516 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6517 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6518 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6519 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6520 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6521 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6522 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6523 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6524 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6525 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6526 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6527 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6528 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6529 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6530 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6531 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6532 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6533 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6534 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6535 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6536 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6537 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6538 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6539 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6540 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6541 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6542 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6543 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6544 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6545 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6546 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6547 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6548 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6549 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6550 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6551 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6552 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6553 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6554 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6555 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6556 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6557 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6558 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6559 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6560 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6561 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6562 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6563 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6564 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6565 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6566 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6567 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6568 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6569 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6570 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6571 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6572 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6573 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6574 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6575 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6576 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6577 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6578 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6579 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6580 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6581 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6582 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6583 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6584 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6585 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6586 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6587 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6588 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6589 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6590 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6591 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6592 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6593 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6594 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6595 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6596 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6597 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6598 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6599 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6600 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6601 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6602 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6603 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6604 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6605 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6606 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6607 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6608 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6609 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6610 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6612 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6613 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6614 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6615 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6616 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6617 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6618 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6619 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6620 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6621 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6622 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6623 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6624 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6625 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6626 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6627 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6628 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6629 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6630 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6631 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6632 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6633 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6634 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6635 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6636 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6637 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6638 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6639 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6640 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6641 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6642 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6643 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6644 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6645 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6646 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6647 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6648 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6649 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6650 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6651 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6652 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6653 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6654 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6655 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6656 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6657 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6658 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6659 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6660 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6661 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6662 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6663 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6664 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6665 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6666 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6667 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6668 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6669 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6670 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6671 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6672 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6673 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6674 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6675 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6676 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6677 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6678 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6679 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6680 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6681 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6682 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6683 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6684 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6685 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6686 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6687 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6688 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6689 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6690 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6691 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6692 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6693 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6694 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6695 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6696 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6697 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6698 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6699 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6700 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6701 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6702 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6703 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6704 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6705 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6706 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6707 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6708 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6709 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6710 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6711 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6712 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6713 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6714 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6715 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6716 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6717 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6718 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6719 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6720 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6721 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6722 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6723 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6724 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6725 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6726 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6727 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6728 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6729 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6730 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6731 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6732 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6733 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6734 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6735 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6736 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6737 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6738 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6740 /* Place holder, leave as first spe builtin. */
6741 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6742 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6743 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6744 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6745 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6746 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6747 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6748 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6749 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6750 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6751 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6752 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6753 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6754 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6755 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6756 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6757 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6758 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6759 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6760 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6761 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6762 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6763 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6764 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6765 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6766 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6767 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6768 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6769 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6770 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6771 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6772 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6773 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6774 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6775 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6776 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6777 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6778 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6779 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6780 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6781 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6782 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6783 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6784 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6785 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6786 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6787 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6788 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6789 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6790 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6791 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6792 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6793 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6794 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6795 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6796 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6797 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6798 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6799 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6800 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6801 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6802 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6803 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6804 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6805 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6806 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6807 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6808 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6809 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6810 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6811 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6812 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6813 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6814 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6815 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6816 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6817 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6818 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6819 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6820 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6821 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6822 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6823 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6824 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6825 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6826 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6827 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6828 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6829 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6830 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6831 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6832 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6833 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6834 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6835 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6836 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6837 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6838 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6839 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6840 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6841 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6842 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6843 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6844 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6845 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6846 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6847 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6848 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6849 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6851 /* SPE binary operations expecting a 5-bit unsigned literal. */
6852 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6854 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6855 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6856 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6857 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6858 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6859 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6860 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6861 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6862 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6863 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6864 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6865 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6866 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6867 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6868 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6869 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6870 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6871 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6872 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6873 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6874 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6875 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6876 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6877 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6878 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6879 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6881 /* Place-holder. Leave as last binary SPE builtin. */
6882 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6885 /* AltiVec predicates. */
6887 struct builtin_description_predicates
6889 const unsigned int mask;
6890 const enum insn_code icode;
6892 const char *const name;
6893 const enum rs6000_builtins code;
6896 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6898 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6899 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6900 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6901 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6902 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6903 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6904 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6905 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6906 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6907 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6908 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6909 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6910 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6912 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6913 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6914 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6917 /* SPE predicates. */
6918 static struct builtin_description bdesc_spe_predicates[] =
6920 /* Place-holder. Leave as first. */
6921 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6922 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6923 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6924 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6925 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6926 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6927 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6928 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6929 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6930 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6931 /* Place-holder. Leave as last. */
6932 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6935 /* SPE evsel predicates. */
6936 static struct builtin_description bdesc_spe_evsel[] =
6938 /* Place-holder. Leave as first. */
6939 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6940 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6941 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6942 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6943 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6944 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6945 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6946 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6947 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6948 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6949 /* Place-holder. Leave as last. */
6950 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6953 /* ABS* operations. */
6955 static const struct builtin_description bdesc_abs[] =
6957 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6958 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6959 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6960 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6961 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6962 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6963 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6966 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6969 static struct builtin_description bdesc_1arg[] =
6971 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6972 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6973 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6974 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6975 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6976 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6977 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6978 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6979 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6980 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6981 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6982 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6983 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6984 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6985 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6986 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6987 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6989 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6990 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6991 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6992 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6993 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6994 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6995 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6996 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6997 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6998 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6999 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
7000 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
7001 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
7002 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
7003 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
7004 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
7005 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
7006 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
7007 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
7009 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7010 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7011 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
7012 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
7013 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
7014 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
7015 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
7016 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
7017 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
7018 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
7019 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
7020 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
7021 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
7022 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
7023 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
7024 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
7025 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
7026 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
7027 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
7028 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
7029 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
7030 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
7031 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
7032 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
7033 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
7034 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
7035 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
7036 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
7037 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
7038 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
7040 /* Place-holder. Leave as last unary SPE builtin. */
7041 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
7045 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
7048 tree arg0 = CALL_EXPR_ARG (exp, 0);
7049 rtx op0 = expand_normal (arg0);
7050 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7051 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7053 if (icode == CODE_FOR_nothing)
7054 /* Builtin not supported on this processor. */
7057 /* If we got invalid arguments bail out before generating bad rtl. */
7058 if (arg0 == error_mark_node)
7061 if (icode == CODE_FOR_altivec_vspltisb
7062 || icode == CODE_FOR_altivec_vspltish
7063 || icode == CODE_FOR_altivec_vspltisw
7064 || icode == CODE_FOR_spe_evsplatfi
7065 || icode == CODE_FOR_spe_evsplati)
7067 /* Only allow 5-bit *signed* literals. */
7068 if (GET_CODE (op0) != CONST_INT
7069 || INTVAL (op0) > 15
7070 || INTVAL (op0) < -16)
7072 error ("argument 1 must be a 5-bit signed literal");
7078 || GET_MODE (target) != tmode
7079 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7080 target = gen_reg_rtx (tmode);
7082 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7083 op0 = copy_to_mode_reg (mode0, op0);
7085 pat = GEN_FCN (icode) (target, op0);
7094 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
7096 rtx pat, scratch1, scratch2;
7097 tree arg0 = CALL_EXPR_ARG (exp, 0);
7098 rtx op0 = expand_normal (arg0);
7099 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7100 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7102 /* If we have invalid arguments, bail out before generating bad rtl. */
7103 if (arg0 == error_mark_node)
7107 || GET_MODE (target) != tmode
7108 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7109 target = gen_reg_rtx (tmode);
7111 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7112 op0 = copy_to_mode_reg (mode0, op0);
7114 scratch1 = gen_reg_rtx (mode0);
7115 scratch2 = gen_reg_rtx (mode0);
7117 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
7126 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
7129 tree arg0 = CALL_EXPR_ARG (exp, 0);
7130 tree arg1 = CALL_EXPR_ARG (exp, 1);
7131 rtx op0 = expand_normal (arg0);
7132 rtx op1 = expand_normal (arg1);
7133 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7134 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7135 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7137 if (icode == CODE_FOR_nothing)
7138 /* Builtin not supported on this processor. */
7141 /* If we got invalid arguments bail out before generating bad rtl. */
7142 if (arg0 == error_mark_node || arg1 == error_mark_node)
7145 if (icode == CODE_FOR_altivec_vcfux
7146 || icode == CODE_FOR_altivec_vcfsx
7147 || icode == CODE_FOR_altivec_vctsxs
7148 || icode == CODE_FOR_altivec_vctuxs
7149 || icode == CODE_FOR_altivec_vspltb
7150 || icode == CODE_FOR_altivec_vsplth
7151 || icode == CODE_FOR_altivec_vspltw
7152 || icode == CODE_FOR_spe_evaddiw
7153 || icode == CODE_FOR_spe_evldd
7154 || icode == CODE_FOR_spe_evldh
7155 || icode == CODE_FOR_spe_evldw
7156 || icode == CODE_FOR_spe_evlhhesplat
7157 || icode == CODE_FOR_spe_evlhhossplat
7158 || icode == CODE_FOR_spe_evlhhousplat
7159 || icode == CODE_FOR_spe_evlwhe
7160 || icode == CODE_FOR_spe_evlwhos
7161 || icode == CODE_FOR_spe_evlwhou
7162 || icode == CODE_FOR_spe_evlwhsplat
7163 || icode == CODE_FOR_spe_evlwwsplat
7164 || icode == CODE_FOR_spe_evrlwi
7165 || icode == CODE_FOR_spe_evslwi
7166 || icode == CODE_FOR_spe_evsrwis
7167 || icode == CODE_FOR_spe_evsubifw
7168 || icode == CODE_FOR_spe_evsrwiu)
7170 /* Only allow 5-bit unsigned literals. */
7172 if (TREE_CODE (arg1) != INTEGER_CST
7173 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7175 error ("argument 2 must be a 5-bit unsigned literal");
7181 || GET_MODE (target) != tmode
7182 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7183 target = gen_reg_rtx (tmode);
7185 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7186 op0 = copy_to_mode_reg (mode0, op0);
7187 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7188 op1 = copy_to_mode_reg (mode1, op1);
7190 pat = GEN_FCN (icode) (target, op0, op1);
7199 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
7200 tree exp, rtx target)
7203 tree cr6_form = CALL_EXPR_ARG (exp, 0);
7204 tree arg0 = CALL_EXPR_ARG (exp, 1);
7205 tree arg1 = CALL_EXPR_ARG (exp, 2);
7206 rtx op0 = expand_normal (arg0);
7207 rtx op1 = expand_normal (arg1);
7208 enum machine_mode tmode = SImode;
7209 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7210 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7213 if (TREE_CODE (cr6_form) != INTEGER_CST)
7215 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7219 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
7221 gcc_assert (mode0 == mode1);
7223 /* If we have invalid arguments, bail out before generating bad rtl. */
7224 if (arg0 == error_mark_node || arg1 == error_mark_node)
7228 || GET_MODE (target) != tmode
7229 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7230 target = gen_reg_rtx (tmode);
7232 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7233 op0 = copy_to_mode_reg (mode0, op0);
7234 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7235 op1 = copy_to_mode_reg (mode1, op1);
7237 scratch = gen_reg_rtx (mode0);
7239 pat = GEN_FCN (icode) (scratch, op0, op1,
7240 gen_rtx_SYMBOL_REF (Pmode, opcode));
7245 /* The vec_any* and vec_all* predicates use the same opcodes for two
7246 different operations, but the bits in CR6 will be different
7247 depending on what information we want. So we have to play tricks
7248 with CR6 to get the right bits out.
7250 If you think this is disgusting, look at the specs for the
7251 AltiVec predicates. */
7253 switch (cr6_form_int)
7256 emit_insn (gen_cr6_test_for_zero (target));
7259 emit_insn (gen_cr6_test_for_zero_reverse (target));
7262 emit_insn (gen_cr6_test_for_lt (target));
7265 emit_insn (gen_cr6_test_for_lt_reverse (target));
7268 error ("argument 1 of __builtin_altivec_predicate is out of range");
7276 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7279 tree arg0 = CALL_EXPR_ARG (exp, 0);
7280 tree arg1 = CALL_EXPR_ARG (exp, 1);
7281 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7282 enum machine_mode mode0 = Pmode;
7283 enum machine_mode mode1 = Pmode;
7284 rtx op0 = expand_normal (arg0);
7285 rtx op1 = expand_normal (arg1);
7287 if (icode == CODE_FOR_nothing)
7288 /* Builtin not supported on this processor. */
7291 /* If we got invalid arguments bail out before generating bad rtl. */
7292 if (arg0 == error_mark_node || arg1 == error_mark_node)
7296 || GET_MODE (target) != tmode
7297 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7298 target = gen_reg_rtx (tmode);
7300 op1 = copy_to_mode_reg (mode1, op1);
7302 if (op0 == const0_rtx)
7304 addr = gen_rtx_MEM (tmode, op1);
7308 op0 = copy_to_mode_reg (mode0, op0);
7309 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7312 pat = GEN_FCN (icode) (target, addr);
7322 spe_expand_stv_builtin (enum insn_code icode, tree exp)
7324 tree arg0 = CALL_EXPR_ARG (exp, 0);
7325 tree arg1 = CALL_EXPR_ARG (exp, 1);
7326 tree arg2 = CALL_EXPR_ARG (exp, 2);
7327 rtx op0 = expand_normal (arg0);
7328 rtx op1 = expand_normal (arg1);
7329 rtx op2 = expand_normal (arg2);
7331 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
7332 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
7333 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
7335 /* Invalid arguments. Bail before doing anything stoopid! */
7336 if (arg0 == error_mark_node
7337 || arg1 == error_mark_node
7338 || arg2 == error_mark_node)
7341 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
7342 op0 = copy_to_mode_reg (mode2, op0);
7343 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
7344 op1 = copy_to_mode_reg (mode0, op1);
7345 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7346 op2 = copy_to_mode_reg (mode1, op2);
7348 pat = GEN_FCN (icode) (op1, op2, op0);
7355 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
7357 tree arg0 = CALL_EXPR_ARG (exp, 0);
7358 tree arg1 = CALL_EXPR_ARG (exp, 1);
7359 tree arg2 = CALL_EXPR_ARG (exp, 2);
7360 rtx op0 = expand_normal (arg0);
7361 rtx op1 = expand_normal (arg1);
7362 rtx op2 = expand_normal (arg2);
7364 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7365 enum machine_mode mode1 = Pmode;
7366 enum machine_mode mode2 = Pmode;
7368 /* Invalid arguments. Bail before doing anything stoopid! */
7369 if (arg0 == error_mark_node
7370 || arg1 == error_mark_node
7371 || arg2 == error_mark_node)
7374 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
7375 op0 = copy_to_mode_reg (tmode, op0);
7377 op2 = copy_to_mode_reg (mode2, op2);
7379 if (op1 == const0_rtx)
7381 addr = gen_rtx_MEM (tmode, op2);
7385 op1 = copy_to_mode_reg (mode1, op1);
7386 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
7389 pat = GEN_FCN (icode) (addr, op0);
7396 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
7399 tree arg0 = CALL_EXPR_ARG (exp, 0);
7400 tree arg1 = CALL_EXPR_ARG (exp, 1);
7401 tree arg2 = CALL_EXPR_ARG (exp, 2);
7402 rtx op0 = expand_normal (arg0);
7403 rtx op1 = expand_normal (arg1);
7404 rtx op2 = expand_normal (arg2);
7405 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7406 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7407 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7408 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
7410 if (icode == CODE_FOR_nothing)
7411 /* Builtin not supported on this processor. */
7414 /* If we got invalid arguments bail out before generating bad rtl. */
7415 if (arg0 == error_mark_node
7416 || arg1 == error_mark_node
7417 || arg2 == error_mark_node)
7420 if (icode == CODE_FOR_altivec_vsldoi_v4sf
7421 || icode == CODE_FOR_altivec_vsldoi_v4si
7422 || icode == CODE_FOR_altivec_vsldoi_v8hi
7423 || icode == CODE_FOR_altivec_vsldoi_v16qi)
7425 /* Only allow 4-bit unsigned literals. */
7427 if (TREE_CODE (arg2) != INTEGER_CST
7428 || TREE_INT_CST_LOW (arg2) & ~0xf)
7430 error ("argument 3 must be a 4-bit unsigned literal");
7436 || GET_MODE (target) != tmode
7437 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7438 target = gen_reg_rtx (tmode);
7440 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7441 op0 = copy_to_mode_reg (mode0, op0);
7442 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7443 op1 = copy_to_mode_reg (mode1, op1);
7444 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7445 op2 = copy_to_mode_reg (mode2, op2);
7447 pat = GEN_FCN (icode) (target, op0, op1, op2);
7455 /* Expand the lvx builtins. */
7457 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7459 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7460 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7462 enum machine_mode tmode, mode0;
7464 enum insn_code icode;
7468 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7469 icode = CODE_FOR_altivec_lvx_v16qi;
7471 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7472 icode = CODE_FOR_altivec_lvx_v8hi;
7474 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7475 icode = CODE_FOR_altivec_lvx_v4si;
7477 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7478 icode = CODE_FOR_altivec_lvx_v4sf;
7487 arg0 = CALL_EXPR_ARG (exp, 0);
7488 op0 = expand_normal (arg0);
7489 tmode = insn_data[icode].operand[0].mode;
7490 mode0 = insn_data[icode].operand[1].mode;
7493 || GET_MODE (target) != tmode
7494 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7495 target = gen_reg_rtx (tmode);
7497 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7498 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7500 pat = GEN_FCN (icode) (target, op0);
7507 /* Expand the stvx builtins. */
7509 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7512 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7513 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7515 enum machine_mode mode0, mode1;
7517 enum insn_code icode;
7521 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7522 icode = CODE_FOR_altivec_stvx_v16qi;
7524 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7525 icode = CODE_FOR_altivec_stvx_v8hi;
7527 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7528 icode = CODE_FOR_altivec_stvx_v4si;
7530 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7531 icode = CODE_FOR_altivec_stvx_v4sf;
7538 arg0 = CALL_EXPR_ARG (exp, 0);
7539 arg1 = CALL_EXPR_ARG (exp, 1);
7540 op0 = expand_normal (arg0);
7541 op1 = expand_normal (arg1);
7542 mode0 = insn_data[icode].operand[0].mode;
7543 mode1 = insn_data[icode].operand[1].mode;
7545 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7546 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7547 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7548 op1 = copy_to_mode_reg (mode1, op1);
7550 pat = GEN_FCN (icode) (op0, op1);
7558 /* Expand the dst builtins. */
7560 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7563 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7564 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7565 tree arg0, arg1, arg2;
7566 enum machine_mode mode0, mode1, mode2;
7567 rtx pat, op0, op1, op2;
7568 struct builtin_description *d;
7573 /* Handle DST variants. */
7574 d = (struct builtin_description *) bdesc_dst;
7575 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7576 if (d->code == fcode)
7578 arg0 = CALL_EXPR_ARG (exp, 0);
7579 arg1 = CALL_EXPR_ARG (exp, 1);
7580 arg2 = CALL_EXPR_ARG (exp, 2);
7581 op0 = expand_normal (arg0);
7582 op1 = expand_normal (arg1);
7583 op2 = expand_normal (arg2);
7584 mode0 = insn_data[d->icode].operand[0].mode;
7585 mode1 = insn_data[d->icode].operand[1].mode;
7586 mode2 = insn_data[d->icode].operand[2].mode;
7588 /* Invalid arguments, bail out before generating bad rtl. */
7589 if (arg0 == error_mark_node
7590 || arg1 == error_mark_node
7591 || arg2 == error_mark_node)
7596 if (TREE_CODE (arg2) != INTEGER_CST
7597 || TREE_INT_CST_LOW (arg2) & ~0x3)
7599 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7603 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7604 op0 = copy_to_mode_reg (Pmode, op0);
7605 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7606 op1 = copy_to_mode_reg (mode1, op1);
7608 pat = GEN_FCN (d->icode) (op0, op1, op2);
7618 /* Expand vec_init builtin. */
7620 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
7622 enum machine_mode tmode = TYPE_MODE (type);
7623 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7624 int i, n_elt = GET_MODE_NUNITS (tmode);
7625 rtvec v = rtvec_alloc (n_elt);
7627 gcc_assert (VECTOR_MODE_P (tmode));
7628 gcc_assert (n_elt == call_expr_nargs (exp));
7630 for (i = 0; i < n_elt; ++i)
7632 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
7633 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7636 if (!target || !register_operand (target, tmode))
7637 target = gen_reg_rtx (tmode);
7639 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7643 /* Return the integer constant in ARG. Constrain it to be in the range
7644 of the subparts of VEC_TYPE; issue an error if not. */
7647 get_element_number (tree vec_type, tree arg)
7649 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7651 if (!host_integerp (arg, 1)
7652 || (elt = tree_low_cst (arg, 1), elt > max))
7654 error ("selector must be an integer constant in the range 0..%wi", max);
7661 /* Expand vec_set builtin. */
7663 altivec_expand_vec_set_builtin (tree exp)
7665 enum machine_mode tmode, mode1;
7666 tree arg0, arg1, arg2;
7670 arg0 = CALL_EXPR_ARG (exp, 0);
7671 arg1 = CALL_EXPR_ARG (exp, 1);
7672 arg2 = CALL_EXPR_ARG (exp, 2);
7674 tmode = TYPE_MODE (TREE_TYPE (arg0));
7675 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7676 gcc_assert (VECTOR_MODE_P (tmode));
7678 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7679 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7680 elt = get_element_number (TREE_TYPE (arg0), arg2);
7682 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7683 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7685 op0 = force_reg (tmode, op0);
7686 op1 = force_reg (mode1, op1);
7688 rs6000_expand_vector_set (op0, op1, elt);
7693 /* Expand vec_ext builtin. */
7695 altivec_expand_vec_ext_builtin (tree exp, rtx target)
7697 enum machine_mode tmode, mode0;
7702 arg0 = CALL_EXPR_ARG (exp, 0);
7703 arg1 = CALL_EXPR_ARG (exp, 1);
7705 op0 = expand_normal (arg0);
7706 elt = get_element_number (TREE_TYPE (arg0), arg1);
7708 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7709 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7710 gcc_assert (VECTOR_MODE_P (mode0));
7712 op0 = force_reg (mode0, op0);
7714 if (optimize || !target || !register_operand (target, tmode))
7715 target = gen_reg_rtx (tmode);
7717 rs6000_expand_vector_extract (target, op0, elt);
7722 /* Expand the builtin in EXP and store the result in TARGET. Store
7723 true in *EXPANDEDP if we found a builtin to expand. */
7725 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7727 struct builtin_description *d;
7728 struct builtin_description_predicates *dp;
7730 enum insn_code icode;
7731 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7734 enum machine_mode tmode, mode0;
7735 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7737 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7738 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7741 error ("unresolved overload for Altivec builtin %qF", fndecl);
7745 target = altivec_expand_ld_builtin (exp, target, expandedp);
7749 target = altivec_expand_st_builtin (exp, target, expandedp);
7753 target = altivec_expand_dst_builtin (exp, target, expandedp);
7761 case ALTIVEC_BUILTIN_STVX:
7762 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp);
7763 case ALTIVEC_BUILTIN_STVEBX:
7764 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
7765 case ALTIVEC_BUILTIN_STVEHX:
7766 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
7767 case ALTIVEC_BUILTIN_STVEWX:
7768 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
7769 case ALTIVEC_BUILTIN_STVXL:
7770 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
7772 case ALTIVEC_BUILTIN_MFVSCR:
7773 icode = CODE_FOR_altivec_mfvscr;
7774 tmode = insn_data[icode].operand[0].mode;
7777 || GET_MODE (target) != tmode
7778 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7779 target = gen_reg_rtx (tmode);
7781 pat = GEN_FCN (icode) (target);
7787 case ALTIVEC_BUILTIN_MTVSCR:
7788 icode = CODE_FOR_altivec_mtvscr;
7789 arg0 = CALL_EXPR_ARG (exp, 0);
7790 op0 = expand_normal (arg0);
7791 mode0 = insn_data[icode].operand[0].mode;
7793 /* If we got invalid arguments bail out before generating bad rtl. */
7794 if (arg0 == error_mark_node)
7797 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7798 op0 = copy_to_mode_reg (mode0, op0);
7800 pat = GEN_FCN (icode) (op0);
7805 case ALTIVEC_BUILTIN_DSSALL:
7806 emit_insn (gen_altivec_dssall ());
7809 case ALTIVEC_BUILTIN_DSS:
7810 icode = CODE_FOR_altivec_dss;
7811 arg0 = CALL_EXPR_ARG (exp, 0);
7813 op0 = expand_normal (arg0);
7814 mode0 = insn_data[icode].operand[0].mode;
7816 /* If we got invalid arguments bail out before generating bad rtl. */
7817 if (arg0 == error_mark_node)
7820 if (TREE_CODE (arg0) != INTEGER_CST
7821 || TREE_INT_CST_LOW (arg0) & ~0x3)
7823 error ("argument to dss must be a 2-bit unsigned literal");
7827 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7828 op0 = copy_to_mode_reg (mode0, op0);
7830 emit_insn (gen_altivec_dss (op0));
7833 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7834 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7835 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7836 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7837 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
7839 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7840 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7841 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7842 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7843 return altivec_expand_vec_set_builtin (exp);
7845 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7846 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7847 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7848 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7849 return altivec_expand_vec_ext_builtin (exp, target);
7856 /* Expand abs* operations. */
7857 d = (struct builtin_description *) bdesc_abs;
7858 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7859 if (d->code == fcode)
7860 return altivec_expand_abs_builtin (d->icode, exp, target);
7862 /* Expand the AltiVec predicates. */
7863 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7864 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7865 if (dp->code == fcode)
7866 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7869 /* LV* are funky. We initialized them differently. */
7872 case ALTIVEC_BUILTIN_LVSL:
7873 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7875 case ALTIVEC_BUILTIN_LVSR:
7876 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7878 case ALTIVEC_BUILTIN_LVEBX:
7879 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7881 case ALTIVEC_BUILTIN_LVEHX:
7882 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7884 case ALTIVEC_BUILTIN_LVEWX:
7885 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7887 case ALTIVEC_BUILTIN_LVXL:
7888 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7890 case ALTIVEC_BUILTIN_LVX:
7891 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7902 /* Binops that need to be initialized manually, but can be expanded
7903 automagically by rs6000_expand_binop_builtin. */
7904 static struct builtin_description bdesc_2arg_spe[] =
7906 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7907 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7908 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7909 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7910 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7911 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7912 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7913 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7914 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7915 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7916 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7917 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7918 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7919 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7920 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7921 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7922 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7923 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7924 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7925 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7926 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7927 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7930 /* Expand the builtin in EXP and store the result in TARGET. Store
7931 true in *EXPANDEDP if we found a builtin to expand.
7933 This expands the SPE builtins that are not simple unary and binary
7936 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7938 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7940 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7941 enum insn_code icode;
7942 enum machine_mode tmode, mode0;
7944 struct builtin_description *d;
7949 /* Syntax check for a 5-bit unsigned immediate. */
7952 case SPE_BUILTIN_EVSTDD:
7953 case SPE_BUILTIN_EVSTDH:
7954 case SPE_BUILTIN_EVSTDW:
7955 case SPE_BUILTIN_EVSTWHE:
7956 case SPE_BUILTIN_EVSTWHO:
7957 case SPE_BUILTIN_EVSTWWE:
7958 case SPE_BUILTIN_EVSTWWO:
7959 arg1 = CALL_EXPR_ARG (exp, 2);
7960 if (TREE_CODE (arg1) != INTEGER_CST
7961 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7963 error ("argument 2 must be a 5-bit unsigned literal");
7971 /* The evsplat*i instructions are not quite generic. */
7974 case SPE_BUILTIN_EVSPLATFI:
7975 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7977 case SPE_BUILTIN_EVSPLATI:
7978 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7984 d = (struct builtin_description *) bdesc_2arg_spe;
7985 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7986 if (d->code == fcode)
7987 return rs6000_expand_binop_builtin (d->icode, exp, target);
7989 d = (struct builtin_description *) bdesc_spe_predicates;
7990 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7991 if (d->code == fcode)
7992 return spe_expand_predicate_builtin (d->icode, exp, target);
7994 d = (struct builtin_description *) bdesc_spe_evsel;
7995 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7996 if (d->code == fcode)
7997 return spe_expand_evsel_builtin (d->icode, exp, target);
8001 case SPE_BUILTIN_EVSTDDX:
8002 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
8003 case SPE_BUILTIN_EVSTDHX:
8004 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
8005 case SPE_BUILTIN_EVSTDWX:
8006 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
8007 case SPE_BUILTIN_EVSTWHEX:
8008 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
8009 case SPE_BUILTIN_EVSTWHOX:
8010 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
8011 case SPE_BUILTIN_EVSTWWEX:
8012 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
8013 case SPE_BUILTIN_EVSTWWOX:
8014 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
8015 case SPE_BUILTIN_EVSTDD:
8016 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
8017 case SPE_BUILTIN_EVSTDH:
8018 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
8019 case SPE_BUILTIN_EVSTDW:
8020 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
8021 case SPE_BUILTIN_EVSTWHE:
8022 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
8023 case SPE_BUILTIN_EVSTWHO:
8024 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
8025 case SPE_BUILTIN_EVSTWWE:
8026 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
8027 case SPE_BUILTIN_EVSTWWO:
8028 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
8029 case SPE_BUILTIN_MFSPEFSCR:
8030 icode = CODE_FOR_spe_mfspefscr;
8031 tmode = insn_data[icode].operand[0].mode;
8034 || GET_MODE (target) != tmode
8035 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8036 target = gen_reg_rtx (tmode);
8038 pat = GEN_FCN (icode) (target);
8043 case SPE_BUILTIN_MTSPEFSCR:
8044 icode = CODE_FOR_spe_mtspefscr;
8045 arg0 = CALL_EXPR_ARG (exp, 0);
8046 op0 = expand_normal (arg0);
8047 mode0 = insn_data[icode].operand[0].mode;
8049 if (arg0 == error_mark_node)
8052 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8053 op0 = copy_to_mode_reg (mode0, op0);
8055 pat = GEN_FCN (icode) (op0);
8068 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8070 rtx pat, scratch, tmp;
8071 tree form = CALL_EXPR_ARG (exp, 0);
8072 tree arg0 = CALL_EXPR_ARG (exp, 1);
8073 tree arg1 = CALL_EXPR_ARG (exp, 2);
8074 rtx op0 = expand_normal (arg0);
8075 rtx op1 = expand_normal (arg1);
8076 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8077 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8081 if (TREE_CODE (form) != INTEGER_CST)
8083 error ("argument 1 of __builtin_spe_predicate must be a constant");
8087 form_int = TREE_INT_CST_LOW (form);
8089 gcc_assert (mode0 == mode1);
8091 if (arg0 == error_mark_node || arg1 == error_mark_node)
8095 || GET_MODE (target) != SImode
8096 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
8097 target = gen_reg_rtx (SImode);
8099 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8100 op0 = copy_to_mode_reg (mode0, op0);
8101 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8102 op1 = copy_to_mode_reg (mode1, op1);
8104 scratch = gen_reg_rtx (CCmode);
8106 pat = GEN_FCN (icode) (scratch, op0, op1);
8111 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
8112 _lower_. We use one compare, but look in different bits of the
8113 CR for each variant.
8115 There are 2 elements in each SPE simd type (upper/lower). The CR
8116 bits are set as follows:
8118 BIT0 | BIT 1 | BIT 2 | BIT 3
8119 U | L | (U | L) | (U & L)
8121 So, for an "all" relationship, BIT 3 would be set.
8122 For an "any" relationship, BIT 2 would be set. Etc.
8124 Following traditional nomenclature, these bits map to:
8126 BIT0 | BIT 1 | BIT 2 | BIT 3
8129 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
8134 /* All variant. OV bit. */
8136 /* We need to get to the OV bit, which is the ORDERED bit. We
8137 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
8138 that's ugly and will make validate_condition_mode die.
8139 So let's just use another pattern. */
8140 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8142 /* Any variant. EQ bit. */
8146 /* Upper variant. LT bit. */
8150 /* Lower variant. GT bit. */
8155 error ("argument 1 of __builtin_spe_predicate is out of range");
8159 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8160 emit_move_insn (target, tmp);
8165 /* The evsel builtins look like this:
8167 e = __builtin_spe_evsel_OP (a, b, c, d);
8171 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
8172 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
8176 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
8179 tree arg0 = CALL_EXPR_ARG (exp, 0);
8180 tree arg1 = CALL_EXPR_ARG (exp, 1);
8181 tree arg2 = CALL_EXPR_ARG (exp, 2);
8182 tree arg3 = CALL_EXPR_ARG (exp, 3);
8183 rtx op0 = expand_normal (arg0);
8184 rtx op1 = expand_normal (arg1);
8185 rtx op2 = expand_normal (arg2);
8186 rtx op3 = expand_normal (arg3);
8187 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8188 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8190 gcc_assert (mode0 == mode1);
8192 if (arg0 == error_mark_node || arg1 == error_mark_node
8193 || arg2 == error_mark_node || arg3 == error_mark_node)
8197 || GET_MODE (target) != mode0
8198 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
8199 target = gen_reg_rtx (mode0);
8201 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8202 op0 = copy_to_mode_reg (mode0, op0);
8203 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8204 op1 = copy_to_mode_reg (mode0, op1);
8205 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
8206 op2 = copy_to_mode_reg (mode0, op2);
8207 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
8208 op3 = copy_to_mode_reg (mode0, op3);
8210 /* Generate the compare. */
8211 scratch = gen_reg_rtx (CCmode);
8212 pat = GEN_FCN (icode) (scratch, op0, op1);
8217 if (mode0 == V2SImode)
8218 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
8220 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
8225 /* Expand an expression EXP that calls a built-in function,
8226 with result going to TARGET if that's convenient
8227 (and in mode MODE if that's convenient).
8228 SUBTARGET may be used as the target for computing one of EXP's operands.
8229 IGNORE is nonzero if the value is to be ignored. */
8232 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8233 enum machine_mode mode ATTRIBUTE_UNUSED,
8234 int ignore ATTRIBUTE_UNUSED)
8236 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8237 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8238 struct builtin_description *d;
8243 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
8244 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8246 int icode = (int) CODE_FOR_altivec_lvsr;
8247 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8248 enum machine_mode mode = insn_data[icode].operand[1].mode;
8252 gcc_assert (TARGET_ALTIVEC);
8254 arg = CALL_EXPR_ARG (exp, 0);
8255 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
8256 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
8257 addr = memory_address (mode, op);
8258 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8262 /* For the load case need to negate the address. */
8263 op = gen_reg_rtx (GET_MODE (addr));
8264 emit_insn (gen_rtx_SET (VOIDmode, op,
8265 gen_rtx_NEG (GET_MODE (addr), addr)));
8267 op = gen_rtx_MEM (mode, op);
8270 || GET_MODE (target) != tmode
8271 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8272 target = gen_reg_rtx (tmode);
8274 /*pat = gen_altivec_lvsr (target, op);*/
8275 pat = GEN_FCN (icode) (target, op);
8283 /* FIXME: There's got to be a nicer way to handle this case than
8284 constructing a new CALL_EXPR. */
8285 if (fcode == ALTIVEC_BUILTIN_VCFUX
8286 || fcode == ALTIVEC_BUILTIN_VCFSX)
8288 if (call_expr_nargs (exp) == 1)
8289 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
8290 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
8295 ret = altivec_expand_builtin (exp, target, &success);
8302 ret = spe_expand_builtin (exp, target, &success);
8308 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
8310 /* Handle simple unary operations. */
8311 d = (struct builtin_description *) bdesc_1arg;
8312 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8313 if (d->code == fcode)
8314 return rs6000_expand_unop_builtin (d->icode, exp, target);
8316 /* Handle simple binary operations. */
8317 d = (struct builtin_description *) bdesc_2arg;
8318 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8319 if (d->code == fcode)
8320 return rs6000_expand_binop_builtin (d->icode, exp, target);
8322 /* Handle simple ternary operations. */
8323 d = (struct builtin_description *) bdesc_3arg;
8324 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8325 if (d->code == fcode)
8326 return rs6000_expand_ternop_builtin (d->icode, exp, target);
8332 build_opaque_vector_type (tree node, int nunits)
8334 node = copy_node (node);
8335 TYPE_MAIN_VARIANT (node) = node;
8336 return build_vector_type (node, nunits);
8340 rs6000_init_builtins (void)
8342 V2SI_type_node = build_vector_type (intSI_type_node, 2);
8343 V2SF_type_node = build_vector_type (float_type_node, 2);
8344 V4HI_type_node = build_vector_type (intHI_type_node, 4);
8345 V4SI_type_node = build_vector_type (intSI_type_node, 4);
8346 V4SF_type_node = build_vector_type (float_type_node, 4);
8347 V8HI_type_node = build_vector_type (intHI_type_node, 8);
8348 V16QI_type_node = build_vector_type (intQI_type_node, 16);
8350 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
8351 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
8352 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
8354 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
8355 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
8356 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
8357 opaque_V4SI_type_node = copy_node (V4SI_type_node);
8359 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
8360 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
8361 'vector unsigned short'. */
8363 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
8364 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8365 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
8366 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8368 long_integer_type_internal_node = long_integer_type_node;
8369 long_unsigned_type_internal_node = long_unsigned_type_node;
8370 intQI_type_internal_node = intQI_type_node;
8371 uintQI_type_internal_node = unsigned_intQI_type_node;
8372 intHI_type_internal_node = intHI_type_node;
8373 uintHI_type_internal_node = unsigned_intHI_type_node;
8374 intSI_type_internal_node = intSI_type_node;
8375 uintSI_type_internal_node = unsigned_intSI_type_node;
8376 float_type_internal_node = float_type_node;
8377 void_type_internal_node = void_type_node;
8379 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8380 get_identifier ("__bool char"),
8381 bool_char_type_node));
8382 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8383 get_identifier ("__bool short"),
8384 bool_short_type_node));
8385 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8386 get_identifier ("__bool int"),
8387 bool_int_type_node));
8388 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8389 get_identifier ("__pixel"),
8392 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
8393 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
8394 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
8395 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8397 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8398 get_identifier ("__vector unsigned char"),
8399 unsigned_V16QI_type_node));
8400 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8401 get_identifier ("__vector signed char"),
8403 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8404 get_identifier ("__vector __bool char"),
8405 bool_V16QI_type_node));
8407 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8408 get_identifier ("__vector unsigned short"),
8409 unsigned_V8HI_type_node));
8410 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8411 get_identifier ("__vector signed short"),
8413 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8414 get_identifier ("__vector __bool short"),
8415 bool_V8HI_type_node));
8417 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8418 get_identifier ("__vector unsigned int"),
8419 unsigned_V4SI_type_node));
8420 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8421 get_identifier ("__vector signed int"),
8423 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8424 get_identifier ("__vector __bool int"),
8425 bool_V4SI_type_node));
8427 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8428 get_identifier ("__vector float"),
8430 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8431 get_identifier ("__vector __pixel"),
8432 pixel_V8HI_type_node));
8435 spe_init_builtins ();
8437 altivec_init_builtins ();
8438 if (TARGET_ALTIVEC || TARGET_SPE)
8439 rs6000_common_init_builtins ();
8442 /* AIX libm provides clog as __clog. */
8443 if (built_in_decls [BUILT_IN_CLOG])
8444 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
8448 /* Search through a set of builtins and enable the mask bits.
8449 DESC is an array of builtins.
8450 SIZE is the total number of builtins.
8451 START is the builtin enum at which to start.
8452 END is the builtin enum at which to end. */
8454 enable_mask_for_builtins (struct builtin_description *desc, int size,
8455 enum rs6000_builtins start,
8456 enum rs6000_builtins end)
8460 for (i = 0; i < size; ++i)
8461 if (desc[i].code == start)
8467 for (; i < size; ++i)
8469 /* Flip all the bits on. */
8470 desc[i].mask = target_flags;
8471 if (desc[i].code == end)
8477 spe_init_builtins (void)
8479 tree endlink = void_list_node;
8480 tree puint_type_node = build_pointer_type (unsigned_type_node);
8481 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
8482 struct builtin_description *d;
8485 tree v2si_ftype_4_v2si
8486 = build_function_type
8487 (opaque_V2SI_type_node,
8488 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8489 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8490 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8491 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8494 tree v2sf_ftype_4_v2sf
8495 = build_function_type
8496 (opaque_V2SF_type_node,
8497 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8498 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8499 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8500 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8503 tree int_ftype_int_v2si_v2si
8504 = build_function_type
8506 tree_cons (NULL_TREE, integer_type_node,
8507 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8508 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8511 tree int_ftype_int_v2sf_v2sf
8512 = build_function_type
8514 tree_cons (NULL_TREE, integer_type_node,
8515 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8516 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8519 tree void_ftype_v2si_puint_int
8520 = build_function_type (void_type_node,
8521 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8522 tree_cons (NULL_TREE, puint_type_node,
8523 tree_cons (NULL_TREE,
8527 tree void_ftype_v2si_puint_char
8528 = build_function_type (void_type_node,
8529 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8530 tree_cons (NULL_TREE, puint_type_node,
8531 tree_cons (NULL_TREE,
8535 tree void_ftype_v2si_pv2si_int
8536 = build_function_type (void_type_node,
8537 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8538 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8539 tree_cons (NULL_TREE,
8543 tree void_ftype_v2si_pv2si_char
8544 = build_function_type (void_type_node,
8545 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8546 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8547 tree_cons (NULL_TREE,
8552 = build_function_type (void_type_node,
8553 tree_cons (NULL_TREE, integer_type_node, endlink));
8556 = build_function_type (integer_type_node, endlink);
8558 tree v2si_ftype_pv2si_int
8559 = build_function_type (opaque_V2SI_type_node,
8560 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8561 tree_cons (NULL_TREE, integer_type_node,
8564 tree v2si_ftype_puint_int
8565 = build_function_type (opaque_V2SI_type_node,
8566 tree_cons (NULL_TREE, puint_type_node,
8567 tree_cons (NULL_TREE, integer_type_node,
8570 tree v2si_ftype_pushort_int
8571 = build_function_type (opaque_V2SI_type_node,
8572 tree_cons (NULL_TREE, pushort_type_node,
8573 tree_cons (NULL_TREE, integer_type_node,
8576 tree v2si_ftype_signed_char
8577 = build_function_type (opaque_V2SI_type_node,
8578 tree_cons (NULL_TREE, signed_char_type_node,
8581 /* The initialization of the simple binary and unary builtins is
8582 done in rs6000_common_init_builtins, but we have to enable the
8583 mask bits here manually because we have run out of `target_flags'
8584 bits. We really need to redesign this mask business. */
8586 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8587 ARRAY_SIZE (bdesc_2arg),
8590 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8591 ARRAY_SIZE (bdesc_1arg),
8593 SPE_BUILTIN_EVSUBFUSIAAW);
8594 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8595 ARRAY_SIZE (bdesc_spe_predicates),
8596 SPE_BUILTIN_EVCMPEQ,
8597 SPE_BUILTIN_EVFSTSTLT);
8598 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8599 ARRAY_SIZE (bdesc_spe_evsel),
8600 SPE_BUILTIN_EVSEL_CMPGTS,
8601 SPE_BUILTIN_EVSEL_FSTSTEQ);
8603 (*lang_hooks.decls.pushdecl)
8604 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8605 opaque_V2SI_type_node));
8607 /* Initialize irregular SPE builtins. */
8609 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8610 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8611 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8612 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8613 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8614 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8615 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8616 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8617 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8618 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8619 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8620 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8621 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8622 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8623 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8624 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8625 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8626 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8629 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8630 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8631 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8632 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8633 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8634 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8635 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8636 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8637 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8638 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8639 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8640 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8641 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8642 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8643 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8644 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8645 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8646 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8647 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8648 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8649 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8650 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8653 d = (struct builtin_description *) bdesc_spe_predicates;
8654 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8658 switch (insn_data[d->icode].operand[1].mode)
8661 type = int_ftype_int_v2si_v2si;
8664 type = int_ftype_int_v2sf_v2sf;
8670 def_builtin (d->mask, d->name, type, d->code);
8673 /* Evsel predicates. */
8674 d = (struct builtin_description *) bdesc_spe_evsel;
8675 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8679 switch (insn_data[d->icode].operand[1].mode)
8682 type = v2si_ftype_4_v2si;
8685 type = v2sf_ftype_4_v2sf;
8691 def_builtin (d->mask, d->name, type, d->code);
8696 altivec_init_builtins (void)
8698 struct builtin_description *d;
8699 struct builtin_description_predicates *dp;
8703 tree pfloat_type_node = build_pointer_type (float_type_node);
8704 tree pint_type_node = build_pointer_type (integer_type_node);
8705 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8706 tree pchar_type_node = build_pointer_type (char_type_node);
8708 tree pvoid_type_node = build_pointer_type (void_type_node);
8710 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8711 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8712 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8713 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8715 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8717 tree int_ftype_opaque
8718 = build_function_type_list (integer_type_node,
8719 opaque_V4SI_type_node, NULL_TREE);
8721 tree opaque_ftype_opaque_int
8722 = build_function_type_list (opaque_V4SI_type_node,
8723 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8724 tree opaque_ftype_opaque_opaque_int
8725 = build_function_type_list (opaque_V4SI_type_node,
8726 opaque_V4SI_type_node, opaque_V4SI_type_node,
8727 integer_type_node, NULL_TREE);
8728 tree int_ftype_int_opaque_opaque
8729 = build_function_type_list (integer_type_node,
8730 integer_type_node, opaque_V4SI_type_node,
8731 opaque_V4SI_type_node, NULL_TREE);
8732 tree int_ftype_int_v4si_v4si
8733 = build_function_type_list (integer_type_node,
8734 integer_type_node, V4SI_type_node,
8735 V4SI_type_node, NULL_TREE);
8736 tree v4sf_ftype_pcfloat
8737 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8738 tree void_ftype_pfloat_v4sf
8739 = build_function_type_list (void_type_node,
8740 pfloat_type_node, V4SF_type_node, NULL_TREE);
8741 tree v4si_ftype_pcint
8742 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8743 tree void_ftype_pint_v4si
8744 = build_function_type_list (void_type_node,
8745 pint_type_node, V4SI_type_node, NULL_TREE);
8746 tree v8hi_ftype_pcshort
8747 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8748 tree void_ftype_pshort_v8hi
8749 = build_function_type_list (void_type_node,
8750 pshort_type_node, V8HI_type_node, NULL_TREE);
8751 tree v16qi_ftype_pcchar
8752 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8753 tree void_ftype_pchar_v16qi
8754 = build_function_type_list (void_type_node,
8755 pchar_type_node, V16QI_type_node, NULL_TREE);
8756 tree void_ftype_v4si
8757 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8758 tree v8hi_ftype_void
8759 = build_function_type (V8HI_type_node, void_list_node);
8760 tree void_ftype_void
8761 = build_function_type (void_type_node, void_list_node);
8763 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8765 tree opaque_ftype_long_pcvoid
8766 = build_function_type_list (opaque_V4SI_type_node,
8767 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8768 tree v16qi_ftype_long_pcvoid
8769 = build_function_type_list (V16QI_type_node,
8770 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8771 tree v8hi_ftype_long_pcvoid
8772 = build_function_type_list (V8HI_type_node,
8773 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8774 tree v4si_ftype_long_pcvoid
8775 = build_function_type_list (V4SI_type_node,
8776 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8778 tree void_ftype_opaque_long_pvoid
8779 = build_function_type_list (void_type_node,
8780 opaque_V4SI_type_node, long_integer_type_node,
8781 pvoid_type_node, NULL_TREE);
8782 tree void_ftype_v4si_long_pvoid
8783 = build_function_type_list (void_type_node,
8784 V4SI_type_node, long_integer_type_node,
8785 pvoid_type_node, NULL_TREE);
8786 tree void_ftype_v16qi_long_pvoid
8787 = build_function_type_list (void_type_node,
8788 V16QI_type_node, long_integer_type_node,
8789 pvoid_type_node, NULL_TREE);
8790 tree void_ftype_v8hi_long_pvoid
8791 = build_function_type_list (void_type_node,
8792 V8HI_type_node, long_integer_type_node,
8793 pvoid_type_node, NULL_TREE);
8794 tree int_ftype_int_v8hi_v8hi
8795 = build_function_type_list (integer_type_node,
8796 integer_type_node, V8HI_type_node,
8797 V8HI_type_node, NULL_TREE);
8798 tree int_ftype_int_v16qi_v16qi
8799 = build_function_type_list (integer_type_node,
8800 integer_type_node, V16QI_type_node,
8801 V16QI_type_node, NULL_TREE);
8802 tree int_ftype_int_v4sf_v4sf
8803 = build_function_type_list (integer_type_node,
8804 integer_type_node, V4SF_type_node,
8805 V4SF_type_node, NULL_TREE);
8806 tree v4si_ftype_v4si
8807 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8808 tree v8hi_ftype_v8hi
8809 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8810 tree v16qi_ftype_v16qi
8811 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8812 tree v4sf_ftype_v4sf
8813 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8814 tree void_ftype_pcvoid_int_int
8815 = build_function_type_list (void_type_node,
8816 pcvoid_type_node, integer_type_node,
8817 integer_type_node, NULL_TREE);
8819 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8820 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8821 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8822 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8823 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8824 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8825 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8826 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8827 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8828 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8829 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8830 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8831 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8832 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8833 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8834 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8835 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8836 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8837 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8838 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8839 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8840 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8841 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8842 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8843 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8844 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8845 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8846 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8847 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8848 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8849 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8850 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8851 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8852 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8853 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8854 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8855 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8856 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8857 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8858 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
8859 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
8860 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
8861 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
8862 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
8863 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
8864 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
8866 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
8868 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
8869 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
8870 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
8871 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
8872 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
8873 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
8874 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
8875 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
8876 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
8877 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8879 /* Add the DST variants. */
8880 d = (struct builtin_description *) bdesc_dst;
8881 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8882 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8884 /* Initialize the predicates. */
8885 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8886 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8888 enum machine_mode mode1;
8890 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8891 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8896 mode1 = insn_data[dp->icode].operand[1].mode;
8901 type = int_ftype_int_opaque_opaque;
8904 type = int_ftype_int_v4si_v4si;
8907 type = int_ftype_int_v8hi_v8hi;
8910 type = int_ftype_int_v16qi_v16qi;
8913 type = int_ftype_int_v4sf_v4sf;
8919 def_builtin (dp->mask, dp->name, type, dp->code);
8922 /* Initialize the abs* operators. */
8923 d = (struct builtin_description *) bdesc_abs;
8924 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8926 enum machine_mode mode0;
8929 mode0 = insn_data[d->icode].operand[0].mode;
8934 type = v4si_ftype_v4si;
8937 type = v8hi_ftype_v8hi;
8940 type = v16qi_ftype_v16qi;
8943 type = v4sf_ftype_v4sf;
8949 def_builtin (d->mask, d->name, type, d->code);
8956 /* Initialize target builtin that implements
8957 targetm.vectorize.builtin_mask_for_load. */
8959 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
8960 v16qi_ftype_long_pcvoid,
8961 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8962 BUILT_IN_MD, NULL, NULL_TREE);
8963 TREE_READONLY (decl) = 1;
8964 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8965 altivec_builtin_mask_for_load = decl;
8968 /* Access to the vec_init patterns. */
8969 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
8970 integer_type_node, integer_type_node,
8971 integer_type_node, NULL_TREE);
8972 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
8973 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
8975 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
8976 short_integer_type_node,
8977 short_integer_type_node,
8978 short_integer_type_node,
8979 short_integer_type_node,
8980 short_integer_type_node,
8981 short_integer_type_node,
8982 short_integer_type_node, NULL_TREE);
8983 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
8984 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
8986 ftype = build_function_type_list (V16QI_type_node, char_type_node,
8987 char_type_node, char_type_node,
8988 char_type_node, char_type_node,
8989 char_type_node, char_type_node,
8990 char_type_node, char_type_node,
8991 char_type_node, char_type_node,
8992 char_type_node, char_type_node,
8993 char_type_node, char_type_node,
8994 char_type_node, NULL_TREE);
8995 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
8996 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
8998 ftype = build_function_type_list (V4SF_type_node, float_type_node,
8999 float_type_node, float_type_node,
9000 float_type_node, NULL_TREE);
9001 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
9002 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
9004 /* Access to the vec_set patterns. */
9005 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
9007 integer_type_node, NULL_TREE);
9008 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
9009 ALTIVEC_BUILTIN_VEC_SET_V4SI);
9011 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
9013 integer_type_node, NULL_TREE);
9014 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
9015 ALTIVEC_BUILTIN_VEC_SET_V8HI);
9017 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
9019 integer_type_node, NULL_TREE);
9020 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
9021 ALTIVEC_BUILTIN_VEC_SET_V16QI);
9023 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
9025 integer_type_node, NULL_TREE);
9026 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
9027 ALTIVEC_BUILTIN_VEC_SET_V4SF);
9029 /* Access to the vec_extract patterns. */
9030 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
9031 integer_type_node, NULL_TREE);
9032 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
9033 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
9035 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
9036 integer_type_node, NULL_TREE);
9037 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
9038 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
9040 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
9041 integer_type_node, NULL_TREE);
9042 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
9043 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
9045 ftype = build_function_type_list (float_type_node, V4SF_type_node,
9046 integer_type_node, NULL_TREE);
9047 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
9048 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
9052 rs6000_common_init_builtins (void)
9054 struct builtin_description *d;
9057 tree v4sf_ftype_v4sf_v4sf_v16qi
9058 = build_function_type_list (V4SF_type_node,
9059 V4SF_type_node, V4SF_type_node,
9060 V16QI_type_node, NULL_TREE);
9061 tree v4si_ftype_v4si_v4si_v16qi
9062 = build_function_type_list (V4SI_type_node,
9063 V4SI_type_node, V4SI_type_node,
9064 V16QI_type_node, NULL_TREE);
9065 tree v8hi_ftype_v8hi_v8hi_v16qi
9066 = build_function_type_list (V8HI_type_node,
9067 V8HI_type_node, V8HI_type_node,
9068 V16QI_type_node, NULL_TREE);
9069 tree v16qi_ftype_v16qi_v16qi_v16qi
9070 = build_function_type_list (V16QI_type_node,
9071 V16QI_type_node, V16QI_type_node,
9072 V16QI_type_node, NULL_TREE);
9074 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
9076 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
9077 tree v16qi_ftype_int
9078 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
9079 tree v8hi_ftype_v16qi
9080 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
9081 tree v4sf_ftype_v4sf
9082 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9084 tree v2si_ftype_v2si_v2si
9085 = build_function_type_list (opaque_V2SI_type_node,
9086 opaque_V2SI_type_node,
9087 opaque_V2SI_type_node, NULL_TREE);
9089 tree v2sf_ftype_v2sf_v2sf
9090 = build_function_type_list (opaque_V2SF_type_node,
9091 opaque_V2SF_type_node,
9092 opaque_V2SF_type_node, NULL_TREE);
9094 tree v2si_ftype_int_int
9095 = build_function_type_list (opaque_V2SI_type_node,
9096 integer_type_node, integer_type_node,
9099 tree opaque_ftype_opaque
9100 = build_function_type_list (opaque_V4SI_type_node,
9101 opaque_V4SI_type_node, NULL_TREE);
9103 tree v2si_ftype_v2si
9104 = build_function_type_list (opaque_V2SI_type_node,
9105 opaque_V2SI_type_node, NULL_TREE);
9107 tree v2sf_ftype_v2sf
9108 = build_function_type_list (opaque_V2SF_type_node,
9109 opaque_V2SF_type_node, NULL_TREE);
9111 tree v2sf_ftype_v2si
9112 = build_function_type_list (opaque_V2SF_type_node,
9113 opaque_V2SI_type_node, NULL_TREE);
9115 tree v2si_ftype_v2sf
9116 = build_function_type_list (opaque_V2SI_type_node,
9117 opaque_V2SF_type_node, NULL_TREE);
9119 tree v2si_ftype_v2si_char
9120 = build_function_type_list (opaque_V2SI_type_node,
9121 opaque_V2SI_type_node,
9122 char_type_node, NULL_TREE);
9124 tree v2si_ftype_int_char
9125 = build_function_type_list (opaque_V2SI_type_node,
9126 integer_type_node, char_type_node, NULL_TREE);
9128 tree v2si_ftype_char
9129 = build_function_type_list (opaque_V2SI_type_node,
9130 char_type_node, NULL_TREE);
9132 tree int_ftype_int_int
9133 = build_function_type_list (integer_type_node,
9134 integer_type_node, integer_type_node,
9137 tree opaque_ftype_opaque_opaque
9138 = build_function_type_list (opaque_V4SI_type_node,
9139 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
9140 tree v4si_ftype_v4si_v4si
9141 = build_function_type_list (V4SI_type_node,
9142 V4SI_type_node, V4SI_type_node, NULL_TREE);
9143 tree v4sf_ftype_v4si_int
9144 = build_function_type_list (V4SF_type_node,
9145 V4SI_type_node, integer_type_node, NULL_TREE);
9146 tree v4si_ftype_v4sf_int
9147 = build_function_type_list (V4SI_type_node,
9148 V4SF_type_node, integer_type_node, NULL_TREE);
9149 tree v4si_ftype_v4si_int
9150 = build_function_type_list (V4SI_type_node,
9151 V4SI_type_node, integer_type_node, NULL_TREE);
9152 tree v8hi_ftype_v8hi_int
9153 = build_function_type_list (V8HI_type_node,
9154 V8HI_type_node, integer_type_node, NULL_TREE);
9155 tree v16qi_ftype_v16qi_int
9156 = build_function_type_list (V16QI_type_node,
9157 V16QI_type_node, integer_type_node, NULL_TREE);
9158 tree v16qi_ftype_v16qi_v16qi_int
9159 = build_function_type_list (V16QI_type_node,
9160 V16QI_type_node, V16QI_type_node,
9161 integer_type_node, NULL_TREE);
9162 tree v8hi_ftype_v8hi_v8hi_int
9163 = build_function_type_list (V8HI_type_node,
9164 V8HI_type_node, V8HI_type_node,
9165 integer_type_node, NULL_TREE);
9166 tree v4si_ftype_v4si_v4si_int
9167 = build_function_type_list (V4SI_type_node,
9168 V4SI_type_node, V4SI_type_node,
9169 integer_type_node, NULL_TREE);
9170 tree v4sf_ftype_v4sf_v4sf_int
9171 = build_function_type_list (V4SF_type_node,
9172 V4SF_type_node, V4SF_type_node,
9173 integer_type_node, NULL_TREE);
9174 tree v4sf_ftype_v4sf_v4sf
9175 = build_function_type_list (V4SF_type_node,
9176 V4SF_type_node, V4SF_type_node, NULL_TREE);
9177 tree opaque_ftype_opaque_opaque_opaque
9178 = build_function_type_list (opaque_V4SI_type_node,
9179 opaque_V4SI_type_node, opaque_V4SI_type_node,
9180 opaque_V4SI_type_node, NULL_TREE);
9181 tree v4sf_ftype_v4sf_v4sf_v4si
9182 = build_function_type_list (V4SF_type_node,
9183 V4SF_type_node, V4SF_type_node,
9184 V4SI_type_node, NULL_TREE);
9185 tree v4sf_ftype_v4sf_v4sf_v4sf
9186 = build_function_type_list (V4SF_type_node,
9187 V4SF_type_node, V4SF_type_node,
9188 V4SF_type_node, NULL_TREE);
9189 tree v4si_ftype_v4si_v4si_v4si
9190 = build_function_type_list (V4SI_type_node,
9191 V4SI_type_node, V4SI_type_node,
9192 V4SI_type_node, NULL_TREE);
9193 tree v8hi_ftype_v8hi_v8hi
9194 = build_function_type_list (V8HI_type_node,
9195 V8HI_type_node, V8HI_type_node, NULL_TREE);
9196 tree v8hi_ftype_v8hi_v8hi_v8hi
9197 = build_function_type_list (V8HI_type_node,
9198 V8HI_type_node, V8HI_type_node,
9199 V8HI_type_node, NULL_TREE);
9200 tree v4si_ftype_v8hi_v8hi_v4si
9201 = build_function_type_list (V4SI_type_node,
9202 V8HI_type_node, V8HI_type_node,
9203 V4SI_type_node, NULL_TREE);
9204 tree v4si_ftype_v16qi_v16qi_v4si
9205 = build_function_type_list (V4SI_type_node,
9206 V16QI_type_node, V16QI_type_node,
9207 V4SI_type_node, NULL_TREE);
9208 tree v16qi_ftype_v16qi_v16qi
9209 = build_function_type_list (V16QI_type_node,
9210 V16QI_type_node, V16QI_type_node, NULL_TREE);
9211 tree v4si_ftype_v4sf_v4sf
9212 = build_function_type_list (V4SI_type_node,
9213 V4SF_type_node, V4SF_type_node, NULL_TREE);
9214 tree v8hi_ftype_v16qi_v16qi
9215 = build_function_type_list (V8HI_type_node,
9216 V16QI_type_node, V16QI_type_node, NULL_TREE);
9217 tree v4si_ftype_v8hi_v8hi
9218 = build_function_type_list (V4SI_type_node,
9219 V8HI_type_node, V8HI_type_node, NULL_TREE);
9220 tree v8hi_ftype_v4si_v4si
9221 = build_function_type_list (V8HI_type_node,
9222 V4SI_type_node, V4SI_type_node, NULL_TREE);
9223 tree v16qi_ftype_v8hi_v8hi
9224 = build_function_type_list (V16QI_type_node,
9225 V8HI_type_node, V8HI_type_node, NULL_TREE);
9226 tree v4si_ftype_v16qi_v4si
9227 = build_function_type_list (V4SI_type_node,
9228 V16QI_type_node, V4SI_type_node, NULL_TREE);
9229 tree v4si_ftype_v16qi_v16qi
9230 = build_function_type_list (V4SI_type_node,
9231 V16QI_type_node, V16QI_type_node, NULL_TREE);
9232 tree v4si_ftype_v8hi_v4si
9233 = build_function_type_list (V4SI_type_node,
9234 V8HI_type_node, V4SI_type_node, NULL_TREE);
9235 tree v4si_ftype_v8hi
9236 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
9237 tree int_ftype_v4si_v4si
9238 = build_function_type_list (integer_type_node,
9239 V4SI_type_node, V4SI_type_node, NULL_TREE);
9240 tree int_ftype_v4sf_v4sf
9241 = build_function_type_list (integer_type_node,
9242 V4SF_type_node, V4SF_type_node, NULL_TREE);
9243 tree int_ftype_v16qi_v16qi
9244 = build_function_type_list (integer_type_node,
9245 V16QI_type_node, V16QI_type_node, NULL_TREE);
9246 tree int_ftype_v8hi_v8hi
9247 = build_function_type_list (integer_type_node,
9248 V8HI_type_node, V8HI_type_node, NULL_TREE);
9250 /* Add the simple ternary operators. */
9251 d = (struct builtin_description *) bdesc_3arg;
9252 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
9254 enum machine_mode mode0, mode1, mode2, mode3;
9256 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9257 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9268 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9271 mode0 = insn_data[d->icode].operand[0].mode;
9272 mode1 = insn_data[d->icode].operand[1].mode;
9273 mode2 = insn_data[d->icode].operand[2].mode;
9274 mode3 = insn_data[d->icode].operand[3].mode;
9277 /* When all four are of the same mode. */
9278 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
9283 type = opaque_ftype_opaque_opaque_opaque;
9286 type = v4si_ftype_v4si_v4si_v4si;
9289 type = v4sf_ftype_v4sf_v4sf_v4sf;
9292 type = v8hi_ftype_v8hi_v8hi_v8hi;
9295 type = v16qi_ftype_v16qi_v16qi_v16qi;
9301 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
9306 type = v4si_ftype_v4si_v4si_v16qi;
9309 type = v4sf_ftype_v4sf_v4sf_v16qi;
9312 type = v8hi_ftype_v8hi_v8hi_v16qi;
9315 type = v16qi_ftype_v16qi_v16qi_v16qi;
9321 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
9322 && mode3 == V4SImode)
9323 type = v4si_ftype_v16qi_v16qi_v4si;
9324 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
9325 && mode3 == V4SImode)
9326 type = v4si_ftype_v8hi_v8hi_v4si;
9327 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
9328 && mode3 == V4SImode)
9329 type = v4sf_ftype_v4sf_v4sf_v4si;
9331 /* vchar, vchar, vchar, 4-bit literal. */
9332 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
9334 type = v16qi_ftype_v16qi_v16qi_int;
9336 /* vshort, vshort, vshort, 4-bit literal. */
9337 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
9339 type = v8hi_ftype_v8hi_v8hi_int;
9341 /* vint, vint, vint, 4-bit literal. */
9342 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
9344 type = v4si_ftype_v4si_v4si_int;
9346 /* vfloat, vfloat, vfloat, 4-bit literal. */
9347 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
9349 type = v4sf_ftype_v4sf_v4sf_int;
9354 def_builtin (d->mask, d->name, type, d->code);
9357 /* Add the simple binary operators. */
9358 d = (struct builtin_description *) bdesc_2arg;
9359 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9361 enum machine_mode mode0, mode1, mode2;
9363 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9364 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9374 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9377 mode0 = insn_data[d->icode].operand[0].mode;
9378 mode1 = insn_data[d->icode].operand[1].mode;
9379 mode2 = insn_data[d->icode].operand[2].mode;
9382 /* When all three operands are of the same mode. */
9383 if (mode0 == mode1 && mode1 == mode2)
9388 type = opaque_ftype_opaque_opaque;
9391 type = v4sf_ftype_v4sf_v4sf;
9394 type = v4si_ftype_v4si_v4si;
9397 type = v16qi_ftype_v16qi_v16qi;
9400 type = v8hi_ftype_v8hi_v8hi;
9403 type = v2si_ftype_v2si_v2si;
9406 type = v2sf_ftype_v2sf_v2sf;
9409 type = int_ftype_int_int;
9416 /* A few other combos we really don't want to do manually. */
9418 /* vint, vfloat, vfloat. */
9419 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
9420 type = v4si_ftype_v4sf_v4sf;
9422 /* vshort, vchar, vchar. */
9423 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
9424 type = v8hi_ftype_v16qi_v16qi;
9426 /* vint, vshort, vshort. */
9427 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
9428 type = v4si_ftype_v8hi_v8hi;
9430 /* vshort, vint, vint. */
9431 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
9432 type = v8hi_ftype_v4si_v4si;
9434 /* vchar, vshort, vshort. */
9435 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
9436 type = v16qi_ftype_v8hi_v8hi;
9438 /* vint, vchar, vint. */
9439 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
9440 type = v4si_ftype_v16qi_v4si;
9442 /* vint, vchar, vchar. */
9443 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
9444 type = v4si_ftype_v16qi_v16qi;
9446 /* vint, vshort, vint. */
9447 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
9448 type = v4si_ftype_v8hi_v4si;
9450 /* vint, vint, 5-bit literal. */
9451 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
9452 type = v4si_ftype_v4si_int;
9454 /* vshort, vshort, 5-bit literal. */
9455 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
9456 type = v8hi_ftype_v8hi_int;
9458 /* vchar, vchar, 5-bit literal. */
9459 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
9460 type = v16qi_ftype_v16qi_int;
9462 /* vfloat, vint, 5-bit literal. */
9463 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
9464 type = v4sf_ftype_v4si_int;
9466 /* vint, vfloat, 5-bit literal. */
9467 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
9468 type = v4si_ftype_v4sf_int;
9470 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
9471 type = v2si_ftype_int_int;
9473 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
9474 type = v2si_ftype_v2si_char;
9476 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
9477 type = v2si_ftype_int_char;
9482 gcc_assert (mode0 == SImode);
9486 type = int_ftype_v4si_v4si;
9489 type = int_ftype_v4sf_v4sf;
9492 type = int_ftype_v16qi_v16qi;
9495 type = int_ftype_v8hi_v8hi;
9502 def_builtin (d->mask, d->name, type, d->code);
9505 /* Add the simple unary operators. */
9506 d = (struct builtin_description *) bdesc_1arg;
9507 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9509 enum machine_mode mode0, mode1;
9511 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9512 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9521 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9524 mode0 = insn_data[d->icode].operand[0].mode;
9525 mode1 = insn_data[d->icode].operand[1].mode;
9528 if (mode0 == V4SImode && mode1 == QImode)
9529 type = v4si_ftype_int;
9530 else if (mode0 == V8HImode && mode1 == QImode)
9531 type = v8hi_ftype_int;
9532 else if (mode0 == V16QImode && mode1 == QImode)
9533 type = v16qi_ftype_int;
9534 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9535 type = opaque_ftype_opaque;
9536 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9537 type = v4sf_ftype_v4sf;
9538 else if (mode0 == V8HImode && mode1 == V16QImode)
9539 type = v8hi_ftype_v16qi;
9540 else if (mode0 == V4SImode && mode1 == V8HImode)
9541 type = v4si_ftype_v8hi;
9542 else if (mode0 == V2SImode && mode1 == V2SImode)
9543 type = v2si_ftype_v2si;
9544 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9545 type = v2sf_ftype_v2sf;
9546 else if (mode0 == V2SFmode && mode1 == V2SImode)
9547 type = v2sf_ftype_v2si;
9548 else if (mode0 == V2SImode && mode1 == V2SFmode)
9549 type = v2si_ftype_v2sf;
9550 else if (mode0 == V2SImode && mode1 == QImode)
9551 type = v2si_ftype_char;
9555 def_builtin (d->mask, d->name, type, d->code);
9560 rs6000_init_libfuncs (void)
9562 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
9563 && !TARGET_POWER2 && !TARGET_POWERPC)
9565 /* AIX library routines for float->int conversion. */
9566 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9567 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9568 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9569 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9572 if (!TARGET_IEEEQUAD)
9573 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9574 if (!TARGET_XL_COMPAT)
9576 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9577 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9578 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9579 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9581 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
9583 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
9584 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
9585 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
9586 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
9587 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
9588 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
9589 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
9590 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
9592 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
9593 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
9594 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
9595 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
9596 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
9597 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
9598 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
9599 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
9604 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9605 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9606 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9607 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9611 /* 32-bit SVR4 quad floating point routines. */
9613 set_optab_libfunc (add_optab, TFmode, "_q_add");
9614 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9615 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9616 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9617 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9618 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9619 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9621 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9622 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9623 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9624 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9625 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9626 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9628 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9629 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9630 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9631 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9632 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9633 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9634 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9635 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9640 /* Expand a block clear operation, and return 1 if successful. Return 0
9641 if we should let the compiler generate normal code.
9643 operands[0] is the destination
9644 operands[1] is the length
9645 operands[3] is the alignment */
9648 expand_block_clear (rtx operands[])
9650 rtx orig_dest = operands[0];
9651 rtx bytes_rtx = operands[1];
9652 rtx align_rtx = operands[3];
9653 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9654 HOST_WIDE_INT align;
9655 HOST_WIDE_INT bytes;
9660 /* If this is not a fixed size move, just call memcpy */
9664 /* This must be a fixed size alignment */
9665 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9666 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9668 /* Anything to clear? */
9669 bytes = INTVAL (bytes_rtx);
9673 /* Use the builtin memset after a point, to avoid huge code bloat.
9674 When optimize_size, avoid any significant code bloat; calling
9675 memset is about 4 instructions, so allow for one instruction to
9676 load zero and three to do clearing. */
9677 if (TARGET_ALTIVEC && align >= 128)
9679 else if (TARGET_POWERPC64 && align >= 32)
9684 if (optimize_size && bytes > 3 * clear_step)
9686 if (! optimize_size && bytes > 8 * clear_step)
9689 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9691 enum machine_mode mode = BLKmode;
9694 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9699 else if (bytes >= 8 && TARGET_POWERPC64
9700 /* 64-bit loads and stores require word-aligned
9702 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9707 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9708 { /* move 4 bytes */
9712 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9713 { /* move 2 bytes */
9717 else /* move 1 byte at a time */
9723 dest = adjust_address (orig_dest, mode, offset);
9725 emit_move_insn (dest, CONST0_RTX (mode));
9732 /* Expand a block move operation, and return 1 if successful. Return 0
9733 if we should let the compiler generate normal code.
9735 operands[0] is the destination
9736 operands[1] is the source
9737 operands[2] is the length
9738 operands[3] is the alignment */
9740 #define MAX_MOVE_REG 4
9743 expand_block_move (rtx operands[])
9745 rtx orig_dest = operands[0];
9746 rtx orig_src = operands[1];
9747 rtx bytes_rtx = operands[2];
9748 rtx align_rtx = operands[3];
9749 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9754 rtx stores[MAX_MOVE_REG];
9757 /* If this is not a fixed size move, just call memcpy */
9761 /* This must be a fixed size alignment */
9762 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9763 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9765 /* Anything to move? */
9766 bytes = INTVAL (bytes_rtx);
9770 /* store_one_arg depends on expand_block_move to handle at least the size of
9771 reg_parm_stack_space. */
9772 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9775 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9778 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9779 rtx (*mov) (rtx, rtx);
9781 enum machine_mode mode = BLKmode;
9784 /* Altivec first, since it will be faster than a string move
9785 when it applies, and usually not significantly larger. */
9786 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9790 gen_func.mov = gen_movv4si;
9792 else if (TARGET_STRING
9793 && bytes > 24 /* move up to 32 bytes at a time */
9801 && ! fixed_regs[12])
9803 move_bytes = (bytes > 32) ? 32 : bytes;
9804 gen_func.movmemsi = gen_movmemsi_8reg;
9806 else if (TARGET_STRING
9807 && bytes > 16 /* move up to 24 bytes at a time */
9813 && ! fixed_regs[10])
9815 move_bytes = (bytes > 24) ? 24 : bytes;
9816 gen_func.movmemsi = gen_movmemsi_6reg;
9818 else if (TARGET_STRING
9819 && bytes > 8 /* move up to 16 bytes at a time */
9825 move_bytes = (bytes > 16) ? 16 : bytes;
9826 gen_func.movmemsi = gen_movmemsi_4reg;
9828 else if (bytes >= 8 && TARGET_POWERPC64
9829 /* 64-bit loads and stores require word-aligned
9831 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9835 gen_func.mov = gen_movdi;
9837 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9838 { /* move up to 8 bytes at a time */
9839 move_bytes = (bytes > 8) ? 8 : bytes;
9840 gen_func.movmemsi = gen_movmemsi_2reg;
9842 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9843 { /* move 4 bytes */
9846 gen_func.mov = gen_movsi;
9848 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9849 { /* move 2 bytes */
9852 gen_func.mov = gen_movhi;
9854 else if (TARGET_STRING && bytes > 1)
9855 { /* move up to 4 bytes at a time */
9856 move_bytes = (bytes > 4) ? 4 : bytes;
9857 gen_func.movmemsi = gen_movmemsi_1reg;
9859 else /* move 1 byte at a time */
9863 gen_func.mov = gen_movqi;
9866 src = adjust_address (orig_src, mode, offset);
9867 dest = adjust_address (orig_dest, mode, offset);
9869 if (mode != BLKmode)
9871 rtx tmp_reg = gen_reg_rtx (mode);
9873 emit_insn ((*gen_func.mov) (tmp_reg, src));
9874 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9877 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9880 for (i = 0; i < num_reg; i++)
9881 emit_insn (stores[i]);
9885 if (mode == BLKmode)
9887 /* Move the address into scratch registers. The movmemsi
9888 patterns require zero offset. */
9889 if (!REG_P (XEXP (src, 0)))
9891 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9892 src = replace_equiv_address (src, src_reg);
9894 set_mem_size (src, GEN_INT (move_bytes));
9896 if (!REG_P (XEXP (dest, 0)))
9898 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9899 dest = replace_equiv_address (dest, dest_reg);
9901 set_mem_size (dest, GEN_INT (move_bytes));
9903 emit_insn ((*gen_func.movmemsi) (dest, src,
9904 GEN_INT (move_bytes & 31),
9913 /* Return a string to perform a load_multiple operation.
9914 operands[0] is the vector.
9915 operands[1] is the source address.
9916 operands[2] is the first destination register. */
9919 rs6000_output_load_multiple (rtx operands[3])
9921 /* We have to handle the case where the pseudo used to contain the address
9922 is assigned to one of the output registers. */
9924 int words = XVECLEN (operands[0], 0);
9927 if (XVECLEN (operands[0], 0) == 1)
9928 return "{l|lwz} %2,0(%1)";
9930 for (i = 0; i < words; i++)
9931 if (refers_to_regno_p (REGNO (operands[2]) + i,
9932 REGNO (operands[2]) + i + 1, operands[1], 0))
9936 xop[0] = GEN_INT (4 * (words-1));
9937 xop[1] = operands[1];
9938 xop[2] = operands[2];
9939 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9944 xop[0] = GEN_INT (4 * (words-1));
9945 xop[1] = operands[1];
9946 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9947 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9952 for (j = 0; j < words; j++)
9955 xop[0] = GEN_INT (j * 4);
9956 xop[1] = operands[1];
9957 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9958 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9960 xop[0] = GEN_INT (i * 4);
9961 xop[1] = operands[1];
9962 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9967 return "{lsi|lswi} %2,%1,%N0";
9971 /* A validation routine: say whether CODE, a condition code, and MODE
9972 match. The other alternatives either don't make sense or should
9973 never be generated. */
9976 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9978 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
9979 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9980 && GET_MODE_CLASS (mode) == MODE_CC);
9982 /* These don't make sense. */
9983 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
9984 || mode != CCUNSmode);
9986 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
9987 || mode == CCUNSmode);
9989 gcc_assert (mode == CCFPmode
9990 || (code != ORDERED && code != UNORDERED
9991 && code != UNEQ && code != LTGT
9992 && code != UNGT && code != UNLT
9993 && code != UNGE && code != UNLE));
9995 /* These should never be generated except for
9996 flag_finite_math_only. */
9997 gcc_assert (mode != CCFPmode
9998 || flag_finite_math_only
9999 || (code != LE && code != GE
10000 && code != UNEQ && code != LTGT
10001 && code != UNGT && code != UNLT));
10003 /* These are invalid; the information is not there. */
10004 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
10008 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
10009 mask required to convert the result of a rotate insn into a shift
10010 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
10013 includes_lshift_p (rtx shiftop, rtx andop)
10015 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10017 shift_mask <<= INTVAL (shiftop);
10019 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10022 /* Similar, but for right shift. */
10025 includes_rshift_p (rtx shiftop, rtx andop)
10027 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10029 shift_mask >>= INTVAL (shiftop);
10031 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10034 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
10035 to perform a left shift. It must have exactly SHIFTOP least
10036 significant 0's, then one or more 1's, then zero or more 0's. */
10039 includes_rldic_lshift_p (rtx shiftop, rtx andop)
10041 if (GET_CODE (andop) == CONST_INT)
10043 HOST_WIDE_INT c, lsb, shift_mask;
10045 c = INTVAL (andop);
10046 if (c == 0 || c == ~0)
10050 shift_mask <<= INTVAL (shiftop);
10052 /* Find the least significant one bit. */
10055 /* It must coincide with the LSB of the shift mask. */
10056 if (-lsb != shift_mask)
10059 /* Invert to look for the next transition (if any). */
10062 /* Remove the low group of ones (originally low group of zeros). */
10065 /* Again find the lsb, and check we have all 1's above. */
10069 else if (GET_CODE (andop) == CONST_DOUBLE
10070 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10072 HOST_WIDE_INT low, high, lsb;
10073 HOST_WIDE_INT shift_mask_low, shift_mask_high;
10075 low = CONST_DOUBLE_LOW (andop);
10076 if (HOST_BITS_PER_WIDE_INT < 64)
10077 high = CONST_DOUBLE_HIGH (andop);
10079 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
10080 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
10083 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10085 shift_mask_high = ~0;
10086 if (INTVAL (shiftop) > 32)
10087 shift_mask_high <<= INTVAL (shiftop) - 32;
10089 lsb = high & -high;
10091 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
10097 lsb = high & -high;
10098 return high == -lsb;
10101 shift_mask_low = ~0;
10102 shift_mask_low <<= INTVAL (shiftop);
10106 if (-lsb != shift_mask_low)
10109 if (HOST_BITS_PER_WIDE_INT < 64)
10114 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10116 lsb = high & -high;
10117 return high == -lsb;
10121 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
10127 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
10128 to perform a left shift. It must have SHIFTOP or more least
10129 significant 0's, with the remainder of the word 1's. */
10132 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
10134 if (GET_CODE (andop) == CONST_INT)
10136 HOST_WIDE_INT c, lsb, shift_mask;
10139 shift_mask <<= INTVAL (shiftop);
10140 c = INTVAL (andop);
10142 /* Find the least significant one bit. */
10145 /* It must be covered by the shift mask.
10146 This test also rejects c == 0. */
10147 if ((lsb & shift_mask) == 0)
10150 /* Check we have all 1's above the transition, and reject all 1's. */
10151 return c == -lsb && lsb != 1;
10153 else if (GET_CODE (andop) == CONST_DOUBLE
10154 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10156 HOST_WIDE_INT low, lsb, shift_mask_low;
10158 low = CONST_DOUBLE_LOW (andop);
10160 if (HOST_BITS_PER_WIDE_INT < 64)
10162 HOST_WIDE_INT high, shift_mask_high;
10164 high = CONST_DOUBLE_HIGH (andop);
10168 shift_mask_high = ~0;
10169 if (INTVAL (shiftop) > 32)
10170 shift_mask_high <<= INTVAL (shiftop) - 32;
10172 lsb = high & -high;
10174 if ((lsb & shift_mask_high) == 0)
10177 return high == -lsb;
10183 shift_mask_low = ~0;
10184 shift_mask_low <<= INTVAL (shiftop);
10188 if ((lsb & shift_mask_low) == 0)
10191 return low == -lsb && lsb != 1;
10197 /* Return 1 if operands will generate a valid arguments to rlwimi
10198 instruction for insert with right shift in 64-bit mode. The mask may
10199 not start on the first bit or stop on the last bit because wrap-around
10200 effects of instruction do not correspond to semantics of RTL insn. */
10203 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
10205 if (INTVAL (startop) > 32
10206 && INTVAL (startop) < 64
10207 && INTVAL (sizeop) > 1
10208 && INTVAL (sizeop) + INTVAL (startop) < 64
10209 && INTVAL (shiftop) > 0
10210 && INTVAL (sizeop) + INTVAL (shiftop) < 32
10211 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
10217 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
10218 for lfq and stfq insns iff the registers are hard registers. */
10221 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
10223 /* We might have been passed a SUBREG. */
10224 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
10227 /* We might have been passed non floating point registers. */
10228 if (!FP_REGNO_P (REGNO (reg1))
10229 || !FP_REGNO_P (REGNO (reg2)))
10232 return (REGNO (reg1) == REGNO (reg2) - 1);
10235 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
10236 addr1 and addr2 must be in consecutive memory locations
10237 (addr2 == addr1 + 8). */
10240 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
10243 unsigned int reg1, reg2;
10244 int offset1, offset2;
10246 /* The mems cannot be volatile. */
10247 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
10250 addr1 = XEXP (mem1, 0);
10251 addr2 = XEXP (mem2, 0);
10253 /* Extract an offset (if used) from the first addr. */
10254 if (GET_CODE (addr1) == PLUS)
10256 /* If not a REG, return zero. */
10257 if (GET_CODE (XEXP (addr1, 0)) != REG)
10261 reg1 = REGNO (XEXP (addr1, 0));
10262 /* The offset must be constant! */
10263 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
10265 offset1 = INTVAL (XEXP (addr1, 1));
10268 else if (GET_CODE (addr1) != REG)
10272 reg1 = REGNO (addr1);
10273 /* This was a simple (mem (reg)) expression. Offset is 0. */
10277 /* And now for the second addr. */
10278 if (GET_CODE (addr2) == PLUS)
10280 /* If not a REG, return zero. */
10281 if (GET_CODE (XEXP (addr2, 0)) != REG)
10285 reg2 = REGNO (XEXP (addr2, 0));
10286 /* The offset must be constant. */
10287 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
10289 offset2 = INTVAL (XEXP (addr2, 1));
10292 else if (GET_CODE (addr2) != REG)
10296 reg2 = REGNO (addr2);
10297 /* This was a simple (mem (reg)) expression. Offset is 0. */
10301 /* Both of these must have the same base register. */
10305 /* The offset for the second addr must be 8 more than the first addr. */
10306 if (offset2 != offset1 + 8)
10309 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10314 /* Return the register class of a scratch register needed to copy IN into
10315 or out of a register in CLASS in MODE. If it can be done directly,
10316 NO_REGS is returned. */
10319 rs6000_secondary_reload_class (enum reg_class class,
10320 enum machine_mode mode ATTRIBUTE_UNUSED,
10325 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
10327 && MACHOPIC_INDIRECT
10331 /* We cannot copy a symbolic operand directly into anything
10332 other than BASE_REGS for TARGET_ELF. So indicate that a
10333 register from BASE_REGS is needed as an intermediate
10336 On Darwin, pic addresses require a load from memory, which
10337 needs a base register. */
10338 if (class != BASE_REGS
10339 && (GET_CODE (in) == SYMBOL_REF
10340 || GET_CODE (in) == HIGH
10341 || GET_CODE (in) == LABEL_REF
10342 || GET_CODE (in) == CONST))
10346 if (GET_CODE (in) == REG)
10348 regno = REGNO (in);
10349 if (regno >= FIRST_PSEUDO_REGISTER)
10351 regno = true_regnum (in);
10352 if (regno >= FIRST_PSEUDO_REGISTER)
10356 else if (GET_CODE (in) == SUBREG)
10358 regno = true_regnum (in);
10359 if (regno >= FIRST_PSEUDO_REGISTER)
10365 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10367 if (class == GENERAL_REGS || class == BASE_REGS
10368 || (regno >= 0 && INT_REGNO_P (regno)))
10371 /* Constants, memory, and FP registers can go into FP registers. */
10372 if ((regno == -1 || FP_REGNO_P (regno))
10373 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
10376 /* Memory, and AltiVec registers can go into AltiVec registers. */
10377 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
10378 && class == ALTIVEC_REGS)
10381 /* We can copy among the CR registers. */
10382 if ((class == CR_REGS || class == CR0_REGS)
10383 && regno >= 0 && CR_REGNO_P (regno))
10386 /* Otherwise, we need GENERAL_REGS. */
10387 return GENERAL_REGS;
10390 /* Given a comparison operation, return the bit number in CCR to test. We
10391 know this is a valid comparison.
10393 SCC_P is 1 if this is for an scc. That means that %D will have been
10394 used instead of %C, so the bits will be in different places.
10396 Return -1 if OP isn't a valid comparison for some reason. */
10399 ccr_bit (rtx op, int scc_p)
10401 enum rtx_code code = GET_CODE (op);
10402 enum machine_mode cc_mode;
10407 if (!COMPARISON_P (op))
10410 reg = XEXP (op, 0);
10412 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
10414 cc_mode = GET_MODE (reg);
10415 cc_regnum = REGNO (reg);
10416 base_bit = 4 * (cc_regnum - CR0_REGNO);
10418 validate_condition_mode (code, cc_mode);
10420 /* When generating a sCOND operation, only positive conditions are
10423 || code == EQ || code == GT || code == LT || code == UNORDERED
10424 || code == GTU || code == LTU);
10429 return scc_p ? base_bit + 3 : base_bit + 2;
10431 return base_bit + 2;
10432 case GT: case GTU: case UNLE:
10433 return base_bit + 1;
10434 case LT: case LTU: case UNGE:
10436 case ORDERED: case UNORDERED:
10437 return base_bit + 3;
10440 /* If scc, we will have done a cror to put the bit in the
10441 unordered position. So test that bit. For integer, this is ! LT
10442 unless this is an scc insn. */
10443 return scc_p ? base_bit + 3 : base_bit;
10446 return scc_p ? base_bit + 3 : base_bit + 1;
10449 gcc_unreachable ();
10453 /* Return the GOT register. */
10456 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10458 /* The second flow pass currently (June 1999) can't update
10459 regs_ever_live without disturbing other parts of the compiler, so
10460 update it here to make the prolog/epilogue code happy. */
10461 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
10462 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10464 current_function_uses_pic_offset_table = 1;
10466 return pic_offset_table_rtx;
10469 /* Function to init struct machine_function.
10470 This will be called, via a pointer variable,
10471 from push_function_context. */
10473 static struct machine_function *
10474 rs6000_init_machine_status (void)
10476 return ggc_alloc_cleared (sizeof (machine_function));
10479 /* These macros test for integers and extract the low-order bits. */
10481 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10482 && GET_MODE (X) == VOIDmode)
10484 #define INT_LOWPART(X) \
10485 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10488 extract_MB (rtx op)
10491 unsigned long val = INT_LOWPART (op);
10493 /* If the high bit is zero, the value is the first 1 bit we find
10495 if ((val & 0x80000000) == 0)
10497 gcc_assert (val & 0xffffffff);
10500 while (((val <<= 1) & 0x80000000) == 0)
10505 /* If the high bit is set and the low bit is not, or the mask is all
10506 1's, the value is zero. */
10507 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10510 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10513 while (((val >>= 1) & 1) != 0)
10520 extract_ME (rtx op)
10523 unsigned long val = INT_LOWPART (op);
10525 /* If the low bit is zero, the value is the first 1 bit we find from
10527 if ((val & 1) == 0)
10529 gcc_assert (val & 0xffffffff);
10532 while (((val >>= 1) & 1) == 0)
10538 /* If the low bit is set and the high bit is not, or the mask is all
10539 1's, the value is 31. */
10540 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10543 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10546 while (((val <<= 1) & 0x80000000) != 0)
10552 /* Locate some local-dynamic symbol still in use by this function
10553 so that we can print its name in some tls_ld pattern. */
10555 static const char *
10556 rs6000_get_some_local_dynamic_name (void)
10560 if (cfun->machine->some_ld_name)
10561 return cfun->machine->some_ld_name;
10563 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10565 && for_each_rtx (&PATTERN (insn),
10566 rs6000_get_some_local_dynamic_name_1, 0))
10567 return cfun->machine->some_ld_name;
10569 gcc_unreachable ();
10572 /* Helper function for rs6000_get_some_local_dynamic_name. */
10575 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10579 if (GET_CODE (x) == SYMBOL_REF)
10581 const char *str = XSTR (x, 0);
10582 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10584 cfun->machine->some_ld_name = str;
10592 /* Write out a function code label. */
10595 rs6000_output_function_entry (FILE *file, const char *fname)
10597 if (fname[0] != '.')
10599 switch (DEFAULT_ABI)
10602 gcc_unreachable ();
10608 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10617 RS6000_OUTPUT_BASENAME (file, fname);
10619 assemble_name (file, fname);
10622 /* Print an operand. Recognize special options, documented below. */
10625 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10626 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10628 #define SMALL_DATA_RELOC "sda21"
10629 #define SMALL_DATA_REG 0
10633 print_operand (FILE *file, rtx x, int code)
10637 unsigned HOST_WIDE_INT uval;
10642 /* Write out an instruction after the call which may be replaced
10643 with glue code by the loader. This depends on the AIX version. */
10644 asm_fprintf (file, RS6000_CALL_GLUE);
10647 /* %a is output_address. */
10650 /* If X is a constant integer whose low-order 5 bits are zero,
10651 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10652 in the AIX assembler where "sri" with a zero shift count
10653 writes a trash instruction. */
10654 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10661 /* If constant, low-order 16 bits of constant, unsigned.
10662 Otherwise, write normally. */
10664 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10666 print_operand (file, x, 0);
10670 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10671 for 64-bit mask direction. */
10672 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10675 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10679 /* X is a CR register. Print the number of the GT bit of the CR. */
10680 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10681 output_operand_lossage ("invalid %%E value");
10683 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10687 /* Like 'J' but get to the GT bit only. */
10688 gcc_assert (GET_CODE (x) == REG);
10690 /* Bit 1 is GT bit. */
10691 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
10693 /* Add one for shift count in rlinm for scc. */
10694 fprintf (file, "%d", i + 1);
10698 /* X is a CR register. Print the number of the EQ bit of the CR */
10699 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10700 output_operand_lossage ("invalid %%E value");
10702 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10706 /* X is a CR register. Print the shift count needed to move it
10707 to the high-order four bits. */
10708 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10709 output_operand_lossage ("invalid %%f value");
10711 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10715 /* Similar, but print the count for the rotate in the opposite
10717 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10718 output_operand_lossage ("invalid %%F value");
10720 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10724 /* X is a constant integer. If it is negative, print "m",
10725 otherwise print "z". This is to make an aze or ame insn. */
10726 if (GET_CODE (x) != CONST_INT)
10727 output_operand_lossage ("invalid %%G value");
10728 else if (INTVAL (x) >= 0)
10735 /* If constant, output low-order five bits. Otherwise, write
10738 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10740 print_operand (file, x, 0);
10744 /* If constant, output low-order six bits. Otherwise, write
10747 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10749 print_operand (file, x, 0);
10753 /* Print `i' if this is a constant, else nothing. */
10759 /* Write the bit number in CCR for jump. */
10760 i = ccr_bit (x, 0);
10762 output_operand_lossage ("invalid %%j code");
10764 fprintf (file, "%d", i);
10768 /* Similar, but add one for shift count in rlinm for scc and pass
10769 scc flag to `ccr_bit'. */
10770 i = ccr_bit (x, 1);
10772 output_operand_lossage ("invalid %%J code");
10774 /* If we want bit 31, write a shift count of zero, not 32. */
10775 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10779 /* X must be a constant. Write the 1's complement of the
10782 output_operand_lossage ("invalid %%k value");
10784 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10788 /* X must be a symbolic constant on ELF. Write an
10789 expression suitable for an 'addi' that adds in the low 16
10790 bits of the MEM. */
10791 if (GET_CODE (x) != CONST)
10793 print_operand_address (file, x);
10794 fputs ("@l", file);
10798 if (GET_CODE (XEXP (x, 0)) != PLUS
10799 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10800 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10801 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10802 output_operand_lossage ("invalid %%K value");
10803 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10804 fputs ("@l", file);
10805 /* For GNU as, there must be a non-alphanumeric character
10806 between 'l' and the number. The '-' is added by
10807 print_operand() already. */
10808 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10810 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10814 /* %l is output_asm_label. */
10817 /* Write second word of DImode or DFmode reference. Works on register
10818 or non-indexed memory only. */
10819 if (GET_CODE (x) == REG)
10820 fputs (reg_names[REGNO (x) + 1], file);
10821 else if (GET_CODE (x) == MEM)
10823 /* Handle possible auto-increment. Since it is pre-increment and
10824 we have already done it, we can just use an offset of word. */
10825 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10826 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10827 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10830 output_address (XEXP (adjust_address_nv (x, SImode,
10834 if (small_data_operand (x, GET_MODE (x)))
10835 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10836 reg_names[SMALL_DATA_REG]);
10841 /* MB value for a mask operand. */
10842 if (! mask_operand (x, SImode))
10843 output_operand_lossage ("invalid %%m value");
10845 fprintf (file, "%d", extract_MB (x));
10849 /* ME value for a mask operand. */
10850 if (! mask_operand (x, SImode))
10851 output_operand_lossage ("invalid %%M value");
10853 fprintf (file, "%d", extract_ME (x));
10856 /* %n outputs the negative of its operand. */
10859 /* Write the number of elements in the vector times 4. */
10860 if (GET_CODE (x) != PARALLEL)
10861 output_operand_lossage ("invalid %%N value");
10863 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10867 /* Similar, but subtract 1 first. */
10868 if (GET_CODE (x) != PARALLEL)
10869 output_operand_lossage ("invalid %%O value");
10871 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10875 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10877 || INT_LOWPART (x) < 0
10878 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10879 output_operand_lossage ("invalid %%p value");
10881 fprintf (file, "%d", i);
10885 /* The operand must be an indirect memory reference. The result
10886 is the register name. */
10887 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10888 || REGNO (XEXP (x, 0)) >= 32)
10889 output_operand_lossage ("invalid %%P value");
10891 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10895 /* This outputs the logical code corresponding to a boolean
10896 expression. The expression may have one or both operands
10897 negated (if one, only the first one). For condition register
10898 logical operations, it will also treat the negated
10899 CR codes as NOTs, but not handle NOTs of them. */
10901 const char *const *t = 0;
10903 enum rtx_code code = GET_CODE (x);
10904 static const char * const tbl[3][3] = {
10905 { "and", "andc", "nor" },
10906 { "or", "orc", "nand" },
10907 { "xor", "eqv", "xor" } };
10911 else if (code == IOR)
10913 else if (code == XOR)
10916 output_operand_lossage ("invalid %%q value");
10918 if (GET_CODE (XEXP (x, 0)) != NOT)
10922 if (GET_CODE (XEXP (x, 1)) == NOT)
10940 /* X is a CR register. Print the mask for `mtcrf'. */
10941 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10942 output_operand_lossage ("invalid %%R value");
10944 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10948 /* Low 5 bits of 32 - value */
10950 output_operand_lossage ("invalid %%s value");
10952 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10956 /* PowerPC64 mask position. All 0's is excluded.
10957 CONST_INT 32-bit mask is considered sign-extended so any
10958 transition must occur within the CONST_INT, not on the boundary. */
10959 if (! mask64_operand (x, DImode))
10960 output_operand_lossage ("invalid %%S value");
10962 uval = INT_LOWPART (x);
10964 if (uval & 1) /* Clear Left */
10966 #if HOST_BITS_PER_WIDE_INT > 64
10967 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10971 else /* Clear Right */
10974 #if HOST_BITS_PER_WIDE_INT > 64
10975 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10981 gcc_assert (i >= 0);
10982 fprintf (file, "%d", i);
10986 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10987 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
10989 /* Bit 3 is OV bit. */
10990 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10992 /* If we want bit 31, write a shift count of zero, not 32. */
10993 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10997 /* Print the symbolic name of a branch target register. */
10998 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10999 && REGNO (x) != COUNT_REGISTER_REGNUM))
11000 output_operand_lossage ("invalid %%T value");
11001 else if (REGNO (x) == LINK_REGISTER_REGNUM)
11002 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
11004 fputs ("ctr", file);
11008 /* High-order 16 bits of constant for use in unsigned operand. */
11010 output_operand_lossage ("invalid %%u value");
11012 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11013 (INT_LOWPART (x) >> 16) & 0xffff);
11017 /* High-order 16 bits of constant for use in signed operand. */
11019 output_operand_lossage ("invalid %%v value");
11021 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11022 (INT_LOWPART (x) >> 16) & 0xffff);
11026 /* Print `u' if this has an auto-increment or auto-decrement. */
11027 if (GET_CODE (x) == MEM
11028 && (GET_CODE (XEXP (x, 0)) == PRE_INC
11029 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
11034 /* Print the trap code for this operand. */
11035 switch (GET_CODE (x))
11038 fputs ("eq", file); /* 4 */
11041 fputs ("ne", file); /* 24 */
11044 fputs ("lt", file); /* 16 */
11047 fputs ("le", file); /* 20 */
11050 fputs ("gt", file); /* 8 */
11053 fputs ("ge", file); /* 12 */
11056 fputs ("llt", file); /* 2 */
11059 fputs ("lle", file); /* 6 */
11062 fputs ("lgt", file); /* 1 */
11065 fputs ("lge", file); /* 5 */
11068 gcc_unreachable ();
11073 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
11076 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
11077 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
11079 print_operand (file, x, 0);
11083 /* MB value for a PowerPC64 rldic operand. */
11084 val = (GET_CODE (x) == CONST_INT
11085 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
11090 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
11091 if ((val <<= 1) < 0)
11094 #if HOST_BITS_PER_WIDE_INT == 32
11095 if (GET_CODE (x) == CONST_INT && i >= 0)
11096 i += 32; /* zero-extend high-part was all 0's */
11097 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
11099 val = CONST_DOUBLE_LOW (x);
11105 for ( ; i < 64; i++)
11106 if ((val <<= 1) < 0)
11111 fprintf (file, "%d", i + 1);
11115 if (GET_CODE (x) == MEM
11116 && legitimate_indexed_address_p (XEXP (x, 0), 0))
11121 /* Like 'L', for third word of TImode */
11122 if (GET_CODE (x) == REG)
11123 fputs (reg_names[REGNO (x) + 2], file);
11124 else if (GET_CODE (x) == MEM)
11126 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11127 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11128 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11130 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
11131 if (small_data_operand (x, GET_MODE (x)))
11132 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11133 reg_names[SMALL_DATA_REG]);
11138 /* X is a SYMBOL_REF. Write out the name preceded by a
11139 period and without any trailing data in brackets. Used for function
11140 names. If we are configured for System V (or the embedded ABI) on
11141 the PowerPC, do not emit the period, since those systems do not use
11142 TOCs and the like. */
11143 gcc_assert (GET_CODE (x) == SYMBOL_REF);
11145 /* Mark the decl as referenced so that cgraph will output the
11147 if (SYMBOL_REF_DECL (x))
11148 mark_decl_referenced (SYMBOL_REF_DECL (x));
11150 /* For macho, check to see if we need a stub. */
11153 const char *name = XSTR (x, 0);
11155 if (MACHOPIC_INDIRECT
11156 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
11157 name = machopic_indirection_name (x, /*stub_p=*/true);
11159 assemble_name (file, name);
11161 else if (!DOT_SYMBOLS)
11162 assemble_name (file, XSTR (x, 0));
11164 rs6000_output_function_entry (file, XSTR (x, 0));
11168 /* Like 'L', for last word of TImode. */
11169 if (GET_CODE (x) == REG)
11170 fputs (reg_names[REGNO (x) + 3], file);
11171 else if (GET_CODE (x) == MEM)
11173 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11174 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11175 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11177 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
11178 if (small_data_operand (x, GET_MODE (x)))
11179 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11180 reg_names[SMALL_DATA_REG]);
11184 /* Print AltiVec or SPE memory operand. */
11189 gcc_assert (GET_CODE (x) == MEM);
11193 /* Ugly hack because %y is overloaded. */
11194 if ((TARGET_SPE || TARGET_E500_DOUBLE)
11195 && (GET_MODE_SIZE (GET_MODE (x)) == 8
11196 || GET_MODE (x) == TFmode
11197 || GET_MODE (x) == TImode))
11199 /* Handle [reg]. */
11200 if (GET_CODE (tmp) == REG)
11202 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
11205 /* Handle [reg+UIMM]. */
11206 else if (GET_CODE (tmp) == PLUS &&
11207 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
11211 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
11213 x = INTVAL (XEXP (tmp, 1));
11214 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
11218 /* Fall through. Must be [reg+reg]. */
11221 && GET_CODE (tmp) == AND
11222 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
11223 && INTVAL (XEXP (tmp, 1)) == -16)
11224 tmp = XEXP (tmp, 0);
11225 if (GET_CODE (tmp) == REG)
11226 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
11229 gcc_assert (GET_CODE (tmp) == PLUS
11230 && REG_P (XEXP (tmp, 0))
11231 && REG_P (XEXP (tmp, 1)));
11233 if (REGNO (XEXP (tmp, 0)) == 0)
11234 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
11235 reg_names[ REGNO (XEXP (tmp, 0)) ]);
11237 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
11238 reg_names[ REGNO (XEXP (tmp, 1)) ]);
11244 if (GET_CODE (x) == REG)
11245 fprintf (file, "%s", reg_names[REGNO (x)]);
11246 else if (GET_CODE (x) == MEM)
11248 /* We need to handle PRE_INC and PRE_DEC here, since we need to
11249 know the width from the mode. */
11250 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
11251 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
11252 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11253 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
11254 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
11255 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11257 output_address (XEXP (x, 0));
11260 output_addr_const (file, x);
11264 assemble_name (file, rs6000_get_some_local_dynamic_name ());
11268 output_operand_lossage ("invalid %%xn code");
11272 /* Print the address of an operand. */
11275 print_operand_address (FILE *file, rtx x)
11277 if (GET_CODE (x) == REG)
11278 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
11279 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
11280 || GET_CODE (x) == LABEL_REF)
11282 output_addr_const (file, x);
11283 if (small_data_operand (x, GET_MODE (x)))
11284 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11285 reg_names[SMALL_DATA_REG]);
11287 gcc_assert (!TARGET_TOC);
11289 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
11291 gcc_assert (REG_P (XEXP (x, 0)));
11292 if (REGNO (XEXP (x, 0)) == 0)
11293 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
11294 reg_names[ REGNO (XEXP (x, 0)) ]);
11296 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
11297 reg_names[ REGNO (XEXP (x, 1)) ]);
11299 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
11300 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
11301 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
11303 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11304 && CONSTANT_P (XEXP (x, 1)))
11306 output_addr_const (file, XEXP (x, 1));
11307 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11311 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11312 && CONSTANT_P (XEXP (x, 1)))
11314 fprintf (file, "lo16(");
11315 output_addr_const (file, XEXP (x, 1));
11316 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11319 else if (legitimate_constant_pool_address_p (x))
11321 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
11323 rtx contains_minus = XEXP (x, 1);
11327 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11328 turn it into (sym) for output_addr_const. */
11329 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
11330 contains_minus = XEXP (contains_minus, 0);
11332 minus = XEXP (contains_minus, 0);
11333 symref = XEXP (minus, 0);
11334 XEXP (contains_minus, 0) = symref;
11339 name = XSTR (symref, 0);
11340 newname = alloca (strlen (name) + sizeof ("@toc"));
11341 strcpy (newname, name);
11342 strcat (newname, "@toc");
11343 XSTR (symref, 0) = newname;
11345 output_addr_const (file, XEXP (x, 1));
11347 XSTR (symref, 0) = name;
11348 XEXP (contains_minus, 0) = minus;
11351 output_addr_const (file, XEXP (x, 1));
11353 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
11356 gcc_unreachable ();
11359 /* Target hook for assembling integer objects. The PowerPC version has
11360 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11361 is defined. It also needs to handle DI-mode objects on 64-bit
11365 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
11367 #ifdef RELOCATABLE_NEEDS_FIXUP
11368 /* Special handling for SI values. */
11369 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
11371 static int recurse = 0;
11373 /* For -mrelocatable, we mark all addresses that need to be fixed up
11374 in the .fixup section. */
11375 if (TARGET_RELOCATABLE
11376 && in_section != toc_section
11377 && in_section != text_section
11378 && !unlikely_text_section_p (in_section)
11380 && GET_CODE (x) != CONST_INT
11381 && GET_CODE (x) != CONST_DOUBLE
11387 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
11389 ASM_OUTPUT_LABEL (asm_out_file, buf);
11390 fprintf (asm_out_file, "\t.long\t(");
11391 output_addr_const (asm_out_file, x);
11392 fprintf (asm_out_file, ")@fixup\n");
11393 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
11394 ASM_OUTPUT_ALIGN (asm_out_file, 2);
11395 fprintf (asm_out_file, "\t.long\t");
11396 assemble_name (asm_out_file, buf);
11397 fprintf (asm_out_file, "\n\t.previous\n");
11401 /* Remove initial .'s to turn a -mcall-aixdesc function
11402 address into the address of the descriptor, not the function
11404 else if (GET_CODE (x) == SYMBOL_REF
11405 && XSTR (x, 0)[0] == '.'
11406 && DEFAULT_ABI == ABI_AIX)
11408 const char *name = XSTR (x, 0);
11409 while (*name == '.')
11412 fprintf (asm_out_file, "\t.long\t%s\n", name);
11416 #endif /* RELOCATABLE_NEEDS_FIXUP */
11417 return default_assemble_integer (x, size, aligned_p);
11420 #ifdef HAVE_GAS_HIDDEN
11421 /* Emit an assembler directive to set symbol visibility for DECL to
11422 VISIBILITY_TYPE. */
11425 rs6000_assemble_visibility (tree decl, int vis)
11427 /* Functions need to have their entry point symbol visibility set as
11428 well as their descriptor symbol visibility. */
11429 if (DEFAULT_ABI == ABI_AIX
11431 && TREE_CODE (decl) == FUNCTION_DECL)
11433 static const char * const visibility_types[] = {
11434 NULL, "internal", "hidden", "protected"
11437 const char *name, *type;
11439 name = ((* targetm.strip_name_encoding)
11440 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
11441 type = visibility_types[vis];
11443 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
11444 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
11447 default_assemble_visibility (decl, vis);
11452 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11454 /* Reversal of FP compares takes care -- an ordered compare
11455 becomes an unordered compare and vice versa. */
11456 if (mode == CCFPmode
11457 && (!flag_finite_math_only
11458 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11459 || code == UNEQ || code == LTGT))
11460 return reverse_condition_maybe_unordered (code);
11462 return reverse_condition (code);
11465 /* Generate a compare for CODE. Return a brand-new rtx that
11466 represents the result of the compare. */
11469 rs6000_generate_compare (enum rtx_code code)
11471 enum machine_mode comp_mode;
11472 rtx compare_result;
11474 if (rs6000_compare_fp_p)
11475 comp_mode = CCFPmode;
11476 else if (code == GTU || code == LTU
11477 || code == GEU || code == LEU)
11478 comp_mode = CCUNSmode;
11479 else if ((code == EQ || code == NE)
11480 && GET_CODE (rs6000_compare_op0) == SUBREG
11481 && GET_CODE (rs6000_compare_op1) == SUBREG
11482 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11483 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11484 /* These are unsigned values, perhaps there will be a later
11485 ordering compare that can be shared with this one.
11486 Unfortunately we cannot detect the signedness of the operands
11487 for non-subregs. */
11488 comp_mode = CCUNSmode;
11490 comp_mode = CCmode;
11492 /* First, the compare. */
11493 compare_result = gen_reg_rtx (comp_mode);
11495 /* E500 FP compare instructions on the GPRs. Yuck! */
11496 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
11497 && rs6000_compare_fp_p)
11499 rtx cmp, or_result, compare_result2;
11500 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11502 if (op_mode == VOIDmode)
11503 op_mode = GET_MODE (rs6000_compare_op1);
11505 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
11506 This explains the following mess. */
11510 case EQ: case UNEQ: case NE: case LTGT:
11514 cmp = flag_unsafe_math_optimizations
11515 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11516 rs6000_compare_op1)
11517 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11518 rs6000_compare_op1);
11522 cmp = flag_unsafe_math_optimizations
11523 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11524 rs6000_compare_op1)
11525 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11526 rs6000_compare_op1);
11530 cmp = flag_unsafe_math_optimizations
11531 ? gen_tsttfeq_gpr (compare_result, rs6000_compare_op0,
11532 rs6000_compare_op1)
11533 : gen_cmptfeq_gpr (compare_result, rs6000_compare_op0,
11534 rs6000_compare_op1);
11538 gcc_unreachable ();
11542 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11546 cmp = flag_unsafe_math_optimizations
11547 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11548 rs6000_compare_op1)
11549 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11550 rs6000_compare_op1);
11554 cmp = flag_unsafe_math_optimizations
11555 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11556 rs6000_compare_op1)
11557 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11558 rs6000_compare_op1);
11562 cmp = flag_unsafe_math_optimizations
11563 ? gen_tsttfgt_gpr (compare_result, rs6000_compare_op0,
11564 rs6000_compare_op1)
11565 : gen_cmptfgt_gpr (compare_result, rs6000_compare_op0,
11566 rs6000_compare_op1);
11570 gcc_unreachable ();
11574 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11578 cmp = flag_unsafe_math_optimizations
11579 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11580 rs6000_compare_op1)
11581 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11582 rs6000_compare_op1);
11586 cmp = flag_unsafe_math_optimizations
11587 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11588 rs6000_compare_op1)
11589 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11590 rs6000_compare_op1);
11594 cmp = flag_unsafe_math_optimizations
11595 ? gen_tsttflt_gpr (compare_result, rs6000_compare_op0,
11596 rs6000_compare_op1)
11597 : gen_cmptflt_gpr (compare_result, rs6000_compare_op0,
11598 rs6000_compare_op1);
11602 gcc_unreachable ();
11606 gcc_unreachable ();
11609 /* Synthesize LE and GE from LT/GT || EQ. */
11610 if (code == LE || code == GE || code == LEU || code == GEU)
11616 case LE: code = LT; break;
11617 case GE: code = GT; break;
11618 case LEU: code = LT; break;
11619 case GEU: code = GT; break;
11620 default: gcc_unreachable ();
11623 compare_result2 = gen_reg_rtx (CCFPmode);
11629 cmp = flag_unsafe_math_optimizations
11630 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11631 rs6000_compare_op1)
11632 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11633 rs6000_compare_op1);
11637 cmp = flag_unsafe_math_optimizations
11638 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11639 rs6000_compare_op1)
11640 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11641 rs6000_compare_op1);
11645 cmp = flag_unsafe_math_optimizations
11646 ? gen_tsttfeq_gpr (compare_result2, rs6000_compare_op0,
11647 rs6000_compare_op1)
11648 : gen_cmptfeq_gpr (compare_result2, rs6000_compare_op0,
11649 rs6000_compare_op1);
11653 gcc_unreachable ();
11657 /* OR them together. */
11658 or_result = gen_reg_rtx (CCFPmode);
11659 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11661 compare_result = or_result;
11666 if (code == NE || code == LTGT)
11676 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11677 CLOBBERs to match cmptf_internal2 pattern. */
11678 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11679 && GET_MODE (rs6000_compare_op0) == TFmode
11680 && !TARGET_IEEEQUAD
11681 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11682 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11684 gen_rtx_SET (VOIDmode,
11686 gen_rtx_COMPARE (comp_mode,
11687 rs6000_compare_op0,
11688 rs6000_compare_op1)),
11689 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11690 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11691 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11692 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11693 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11694 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11695 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11696 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11697 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11698 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11700 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11701 comp_mode = CCEQmode;
11702 compare_result = gen_reg_rtx (CCEQmode);
11704 emit_insn (gen_stack_protect_testdi (compare_result,
11705 rs6000_compare_op0, op1));
11707 emit_insn (gen_stack_protect_testsi (compare_result,
11708 rs6000_compare_op0, op1));
11711 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11712 gen_rtx_COMPARE (comp_mode,
11713 rs6000_compare_op0,
11714 rs6000_compare_op1)));
11717 /* Some kinds of FP comparisons need an OR operation;
11718 under flag_finite_math_only we don't bother. */
11719 if (rs6000_compare_fp_p
11720 && !flag_finite_math_only
11721 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
11722 && (code == LE || code == GE
11723 || code == UNEQ || code == LTGT
11724 || code == UNGT || code == UNLT))
11726 enum rtx_code or1, or2;
11727 rtx or1_rtx, or2_rtx, compare2_rtx;
11728 rtx or_result = gen_reg_rtx (CCEQmode);
11732 case LE: or1 = LT; or2 = EQ; break;
11733 case GE: or1 = GT; or2 = EQ; break;
11734 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11735 case LTGT: or1 = LT; or2 = GT; break;
11736 case UNGT: or1 = UNORDERED; or2 = GT; break;
11737 case UNLT: or1 = UNORDERED; or2 = LT; break;
11738 default: gcc_unreachable ();
11740 validate_condition_mode (or1, comp_mode);
11741 validate_condition_mode (or2, comp_mode);
11742 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11743 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11744 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11745 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11747 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11749 compare_result = or_result;
11753 validate_condition_mode (code, GET_MODE (compare_result));
11755 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11759 /* Emit the RTL for an sCOND pattern. */
11762 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11765 enum machine_mode op_mode;
11766 enum rtx_code cond_code;
11768 condition_rtx = rs6000_generate_compare (code);
11769 cond_code = GET_CODE (condition_rtx);
11771 if (rs6000_compare_fp_p
11772 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11776 PUT_MODE (condition_rtx, SImode);
11777 t = XEXP (condition_rtx, 0);
11779 gcc_assert (cond_code == NE || cond_code == EQ);
11781 if (cond_code == NE)
11782 emit_insn (gen_e500_flip_gt_bit (t, t));
11784 emit_insn (gen_move_from_CR_gt_bit (result, t));
11788 if (cond_code == NE
11789 || cond_code == GE || cond_code == LE
11790 || cond_code == GEU || cond_code == LEU
11791 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11793 rtx not_result = gen_reg_rtx (CCEQmode);
11794 rtx not_op, rev_cond_rtx;
11795 enum machine_mode cc_mode;
11797 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11799 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11800 SImode, XEXP (condition_rtx, 0), const0_rtx);
11801 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11802 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11803 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11806 op_mode = GET_MODE (rs6000_compare_op0);
11807 if (op_mode == VOIDmode)
11808 op_mode = GET_MODE (rs6000_compare_op1);
11810 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11812 PUT_MODE (condition_rtx, DImode);
11813 convert_move (result, condition_rtx, 0);
11817 PUT_MODE (condition_rtx, SImode);
11818 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11822 /* Emit a branch of kind CODE to location LOC. */
11825 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11827 rtx condition_rtx, loc_ref;
11829 condition_rtx = rs6000_generate_compare (code);
11830 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11831 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11832 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11833 loc_ref, pc_rtx)));
11836 /* Return the string to output a conditional branch to LABEL, which is
11837 the operand number of the label, or -1 if the branch is really a
11838 conditional return.
11840 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11841 condition code register and its mode specifies what kind of
11842 comparison we made.
11844 REVERSED is nonzero if we should reverse the sense of the comparison.
11846 INSN is the insn. */
11849 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11851 static char string[64];
11852 enum rtx_code code = GET_CODE (op);
11853 rtx cc_reg = XEXP (op, 0);
11854 enum machine_mode mode = GET_MODE (cc_reg);
11855 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11856 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11857 int really_reversed = reversed ^ need_longbranch;
11863 validate_condition_mode (code, mode);
11865 /* Work out which way this really branches. We could use
11866 reverse_condition_maybe_unordered here always but this
11867 makes the resulting assembler clearer. */
11868 if (really_reversed)
11870 /* Reversal of FP compares takes care -- an ordered compare
11871 becomes an unordered compare and vice versa. */
11872 if (mode == CCFPmode)
11873 code = reverse_condition_maybe_unordered (code);
11875 code = reverse_condition (code);
11878 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11880 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11885 /* Opposite of GT. */
11894 gcc_unreachable ();
11900 /* Not all of these are actually distinct opcodes, but
11901 we distinguish them for clarity of the resulting assembler. */
11902 case NE: case LTGT:
11903 ccode = "ne"; break;
11904 case EQ: case UNEQ:
11905 ccode = "eq"; break;
11907 ccode = "ge"; break;
11908 case GT: case GTU: case UNGT:
11909 ccode = "gt"; break;
11911 ccode = "le"; break;
11912 case LT: case LTU: case UNLT:
11913 ccode = "lt"; break;
11914 case UNORDERED: ccode = "un"; break;
11915 case ORDERED: ccode = "nu"; break;
11916 case UNGE: ccode = "nl"; break;
11917 case UNLE: ccode = "ng"; break;
11919 gcc_unreachable ();
11922 /* Maybe we have a guess as to how likely the branch is.
11923 The old mnemonics don't have a way to specify this information. */
11925 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11926 if (note != NULL_RTX)
11928 /* PROB is the difference from 50%. */
11929 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11931 /* Only hint for highly probable/improbable branches on newer
11932 cpus as static prediction overrides processor dynamic
11933 prediction. For older cpus we may as well always hint, but
11934 assume not taken for branches that are very close to 50% as a
11935 mispredicted taken branch is more expensive than a
11936 mispredicted not-taken branch. */
11937 if (rs6000_always_hint
11938 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
11939 && br_prob_note_reliable_p (note)))
11941 if (abs (prob) > REG_BR_PROB_BASE / 20
11942 && ((prob > 0) ^ need_longbranch))
11950 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11952 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11954 /* We need to escape any '%' characters in the reg_names string.
11955 Assume they'd only be the first character.... */
11956 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11958 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11962 /* If the branch distance was too far, we may have to use an
11963 unconditional branch to go the distance. */
11964 if (need_longbranch)
11965 s += sprintf (s, ",$+8\n\tb %s", label);
11967 s += sprintf (s, ",%s", label);
11973 /* Return the string to flip the GT bit on a CR. */
11975 output_e500_flip_gt_bit (rtx dst, rtx src)
11977 static char string[64];
11980 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
11981 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
11984 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
11985 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
11987 sprintf (string, "crnot %d,%d", a, b);
11991 /* Return insn index for the vector compare instruction for given CODE,
11992 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11996 get_vec_cmp_insn (enum rtx_code code,
11997 enum machine_mode dest_mode,
11998 enum machine_mode op_mode)
12000 if (!TARGET_ALTIVEC)
12001 return INSN_NOT_AVAILABLE;
12006 if (dest_mode == V16QImode && op_mode == V16QImode)
12007 return UNSPEC_VCMPEQUB;
12008 if (dest_mode == V8HImode && op_mode == V8HImode)
12009 return UNSPEC_VCMPEQUH;
12010 if (dest_mode == V4SImode && op_mode == V4SImode)
12011 return UNSPEC_VCMPEQUW;
12012 if (dest_mode == V4SImode && op_mode == V4SFmode)
12013 return UNSPEC_VCMPEQFP;
12016 if (dest_mode == V4SImode && op_mode == V4SFmode)
12017 return UNSPEC_VCMPGEFP;
12019 if (dest_mode == V16QImode && op_mode == V16QImode)
12020 return UNSPEC_VCMPGTSB;
12021 if (dest_mode == V8HImode && op_mode == V8HImode)
12022 return UNSPEC_VCMPGTSH;
12023 if (dest_mode == V4SImode && op_mode == V4SImode)
12024 return UNSPEC_VCMPGTSW;
12025 if (dest_mode == V4SImode && op_mode == V4SFmode)
12026 return UNSPEC_VCMPGTFP;
12029 if (dest_mode == V16QImode && op_mode == V16QImode)
12030 return UNSPEC_VCMPGTUB;
12031 if (dest_mode == V8HImode && op_mode == V8HImode)
12032 return UNSPEC_VCMPGTUH;
12033 if (dest_mode == V4SImode && op_mode == V4SImode)
12034 return UNSPEC_VCMPGTUW;
12039 return INSN_NOT_AVAILABLE;
12042 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
12043 DMODE is expected destination mode. This is a recursive function. */
12046 rs6000_emit_vector_compare (enum rtx_code rcode,
12048 enum machine_mode dmode)
12052 enum machine_mode dest_mode;
12053 enum machine_mode op_mode = GET_MODE (op1);
12055 gcc_assert (TARGET_ALTIVEC);
12056 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
12058 /* Floating point vector compare instructions uses destination V4SImode.
12059 Move destination to appropriate mode later. */
12060 if (dmode == V4SFmode)
12061 dest_mode = V4SImode;
12065 mask = gen_reg_rtx (dest_mode);
12066 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12068 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
12070 bool swap_operands = false;
12071 bool try_again = false;
12076 swap_operands = true;
12081 swap_operands = true;
12089 /* Invert condition and try again.
12090 e.g., A != B becomes ~(A==B). */
12092 enum rtx_code rev_code;
12093 enum insn_code nor_code;
12096 rev_code = reverse_condition_maybe_unordered (rcode);
12097 eq_rtx = rs6000_emit_vector_compare (rev_code, op0, op1,
12100 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
12101 gcc_assert (nor_code != CODE_FOR_nothing);
12102 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
12104 if (dmode != dest_mode)
12106 rtx temp = gen_reg_rtx (dest_mode);
12107 convert_move (temp, mask, 0);
12117 /* Try GT/GTU/LT/LTU OR EQ */
12120 enum insn_code ior_code;
12121 enum rtx_code new_code;
12142 gcc_unreachable ();
12145 c_rtx = rs6000_emit_vector_compare (new_code,
12146 op0, op1, dest_mode);
12147 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
12150 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
12151 gcc_assert (ior_code != CODE_FOR_nothing);
12152 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
12153 if (dmode != dest_mode)
12155 rtx temp = gen_reg_rtx (dest_mode);
12156 convert_move (temp, mask, 0);
12163 gcc_unreachable ();
12168 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12169 /* You only get two chances. */
12170 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
12182 emit_insn (gen_rtx_SET (VOIDmode, mask,
12183 gen_rtx_UNSPEC (dest_mode,
12184 gen_rtvec (2, op0, op1),
12186 if (dmode != dest_mode)
12188 rtx temp = gen_reg_rtx (dest_mode);
12189 convert_move (temp, mask, 0);
12195 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
12196 valid insn doesn exist for given mode. */
12199 get_vsel_insn (enum machine_mode mode)
12204 return UNSPEC_VSEL4SI;
12207 return UNSPEC_VSEL4SF;
12210 return UNSPEC_VSEL8HI;
12213 return UNSPEC_VSEL16QI;
12216 return INSN_NOT_AVAILABLE;
12219 return INSN_NOT_AVAILABLE;
12222 /* Emit vector select insn where DEST is destination using
12223 operands OP1, OP2 and MASK. */
12226 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
12229 enum machine_mode dest_mode = GET_MODE (dest);
12230 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
12232 temp = gen_reg_rtx (dest_mode);
12234 /* For each vector element, select op1 when mask is 1 otherwise
12236 t = gen_rtx_SET (VOIDmode, temp,
12237 gen_rtx_UNSPEC (dest_mode,
12238 gen_rtvec (3, op2, op1, mask),
12241 emit_move_insn (dest, temp);
12245 /* Emit vector conditional expression.
12246 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
12247 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
12250 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
12251 rtx cond, rtx cc_op0, rtx cc_op1)
12253 enum machine_mode dest_mode = GET_MODE (dest);
12254 enum rtx_code rcode = GET_CODE (cond);
12257 if (!TARGET_ALTIVEC)
12260 /* Get the vector mask for the given relational operations. */
12261 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
12263 rs6000_emit_vector_select (dest, op1, op2, mask);
12268 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
12269 operands of the last comparison is nonzero/true, FALSE_COND if it
12270 is zero/false. Return 0 if the hardware has no such operation. */
12273 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12275 enum rtx_code code = GET_CODE (op);
12276 rtx op0 = rs6000_compare_op0;
12277 rtx op1 = rs6000_compare_op1;
12278 REAL_VALUE_TYPE c1;
12279 enum machine_mode compare_mode = GET_MODE (op0);
12280 enum machine_mode result_mode = GET_MODE (dest);
12282 bool is_against_zero;
12284 /* These modes should always match. */
12285 if (GET_MODE (op1) != compare_mode
12286 /* In the isel case however, we can use a compare immediate, so
12287 op1 may be a small constant. */
12288 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
12290 if (GET_MODE (true_cond) != result_mode)
12292 if (GET_MODE (false_cond) != result_mode)
12295 /* First, work out if the hardware can do this at all, or
12296 if it's too slow.... */
12297 if (! rs6000_compare_fp_p)
12300 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
12303 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
12304 && SCALAR_FLOAT_MODE_P (compare_mode))
12307 is_against_zero = op1 == CONST0_RTX (compare_mode);
12309 /* A floating-point subtract might overflow, underflow, or produce
12310 an inexact result, thus changing the floating-point flags, so it
12311 can't be generated if we care about that. It's safe if one side
12312 of the construct is zero, since then no subtract will be
12314 if (SCALAR_FLOAT_MODE_P (compare_mode)
12315 && flag_trapping_math && ! is_against_zero)
12318 /* Eliminate half of the comparisons by switching operands, this
12319 makes the remaining code simpler. */
12320 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
12321 || code == LTGT || code == LT || code == UNLE)
12323 code = reverse_condition_maybe_unordered (code);
12325 true_cond = false_cond;
12329 /* UNEQ and LTGT take four instructions for a comparison with zero,
12330 it'll probably be faster to use a branch here too. */
12331 if (code == UNEQ && HONOR_NANS (compare_mode))
12334 if (GET_CODE (op1) == CONST_DOUBLE)
12335 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
12337 /* We're going to try to implement comparisons by performing
12338 a subtract, then comparing against zero. Unfortunately,
12339 Inf - Inf is NaN which is not zero, and so if we don't
12340 know that the operand is finite and the comparison
12341 would treat EQ different to UNORDERED, we can't do it. */
12342 if (HONOR_INFINITIES (compare_mode)
12343 && code != GT && code != UNGE
12344 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
12345 /* Constructs of the form (a OP b ? a : b) are safe. */
12346 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
12347 || (! rtx_equal_p (op0, true_cond)
12348 && ! rtx_equal_p (op1, true_cond))))
12351 /* At this point we know we can use fsel. */
12353 /* Reduce the comparison to a comparison against zero. */
12354 if (! is_against_zero)
12356 temp = gen_reg_rtx (compare_mode);
12357 emit_insn (gen_rtx_SET (VOIDmode, temp,
12358 gen_rtx_MINUS (compare_mode, op0, op1)));
12360 op1 = CONST0_RTX (compare_mode);
12363 /* If we don't care about NaNs we can reduce some of the comparisons
12364 down to faster ones. */
12365 if (! HONOR_NANS (compare_mode))
12371 true_cond = false_cond;
12384 /* Now, reduce everything down to a GE. */
12391 temp = gen_reg_rtx (compare_mode);
12392 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12397 temp = gen_reg_rtx (compare_mode);
12398 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
12403 temp = gen_reg_rtx (compare_mode);
12404 emit_insn (gen_rtx_SET (VOIDmode, temp,
12405 gen_rtx_NEG (compare_mode,
12406 gen_rtx_ABS (compare_mode, op0))));
12411 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12412 temp = gen_reg_rtx (result_mode);
12413 emit_insn (gen_rtx_SET (VOIDmode, temp,
12414 gen_rtx_IF_THEN_ELSE (result_mode,
12415 gen_rtx_GE (VOIDmode,
12417 true_cond, false_cond)));
12418 false_cond = true_cond;
12421 temp = gen_reg_rtx (compare_mode);
12422 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12427 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
12428 temp = gen_reg_rtx (result_mode);
12429 emit_insn (gen_rtx_SET (VOIDmode, temp,
12430 gen_rtx_IF_THEN_ELSE (result_mode,
12431 gen_rtx_GE (VOIDmode,
12433 true_cond, false_cond)));
12434 true_cond = false_cond;
12437 temp = gen_reg_rtx (compare_mode);
12438 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12443 gcc_unreachable ();
12446 emit_insn (gen_rtx_SET (VOIDmode, dest,
12447 gen_rtx_IF_THEN_ELSE (result_mode,
12448 gen_rtx_GE (VOIDmode,
12450 true_cond, false_cond)));
12454 /* Same as above, but for ints (isel). */
12457 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12459 rtx condition_rtx, cr;
12461 /* All isel implementations thus far are 32-bits. */
12462 if (GET_MODE (rs6000_compare_op0) != SImode)
12465 /* We still have to do the compare, because isel doesn't do a
12466 compare, it just looks at the CRx bits set by a previous compare
12468 condition_rtx = rs6000_generate_compare (GET_CODE (op));
12469 cr = XEXP (condition_rtx, 0);
12471 if (GET_MODE (cr) == CCmode)
12472 emit_insn (gen_isel_signed (dest, condition_rtx,
12473 true_cond, false_cond, cr));
12475 emit_insn (gen_isel_unsigned (dest, condition_rtx,
12476 true_cond, false_cond, cr));
12482 output_isel (rtx *operands)
12484 enum rtx_code code;
12486 code = GET_CODE (operands[1]);
12487 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
12489 PUT_CODE (operands[1], reverse_condition (code));
12490 return "isel %0,%3,%2,%j1";
12493 return "isel %0,%2,%3,%j1";
12497 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
12499 enum machine_mode mode = GET_MODE (op0);
12503 if (code == SMAX || code == SMIN)
12508 if (code == SMAX || code == UMAX)
12509 target = emit_conditional_move (dest, c, op0, op1, mode,
12510 op0, op1, mode, 0);
12512 target = emit_conditional_move (dest, c, op0, op1, mode,
12513 op1, op0, mode, 0);
12514 gcc_assert (target);
12515 if (target != dest)
12516 emit_move_insn (dest, target);
12519 /* Emit instructions to perform a load-reserved/store-conditional operation.
12520 The operation performed is an atomic
12521 (set M (CODE:MODE M OP))
12522 If not NULL, BEFORE is atomically set to M before the operation, and
12523 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
12524 If SYNC_P then a memory barrier is emitted before the operation.
12525 Either OP or M may be wrapped in a NOT operation. */
12528 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
12529 rtx m, rtx op, rtx before_param, rtx after_param,
12532 enum machine_mode used_mode;
12533 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
12536 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12537 rtx shift = NULL_RTX;
12540 emit_insn (gen_memory_barrier ());
12542 if (GET_CODE (m) == NOT)
12543 used_m = XEXP (m, 0);
12547 /* If this is smaller than SImode, we'll have to use SImode with
12549 if (mode == QImode || mode == HImode)
12553 if (MEM_ALIGN (used_m) >= 32)
12556 if (BYTES_BIG_ENDIAN)
12557 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
12559 shift = GEN_INT (ishift);
12563 rtx addrSI, aligned_addr;
12564 int shift_mask = mode == QImode ? 0x18 : 0x10;
12566 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
12567 XEXP (used_m, 0)));
12568 shift = gen_reg_rtx (SImode);
12570 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12571 GEN_INT (shift_mask)));
12572 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12574 aligned_addr = expand_binop (Pmode, and_optab,
12576 GEN_INT (-4), NULL_RTX,
12577 1, OPTAB_LIB_WIDEN);
12578 used_m = change_address (used_m, SImode, aligned_addr);
12579 set_mem_align (used_m, 32);
12580 /* It's safe to keep the old alias set of USED_M, because
12581 the operation is atomic and only affects the original
12583 if (GET_CODE (m) == NOT)
12584 m = gen_rtx_NOT (SImode, used_m);
12589 if (GET_CODE (op) == NOT)
12591 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12592 oldop = gen_rtx_NOT (SImode, oldop);
12595 oldop = lowpart_subreg (SImode, op, mode);
12601 newop = expand_binop (SImode, and_optab,
12602 oldop, GEN_INT (imask), NULL_RTX,
12603 1, OPTAB_LIB_WIDEN);
12604 emit_insn (gen_ashlsi3 (newop, newop, shift));
12608 newop = expand_binop (SImode, ior_optab,
12609 oldop, GEN_INT (~imask), NULL_RTX,
12610 1, OPTAB_LIB_WIDEN);
12611 emit_insn (gen_rotlsi3 (newop, newop, shift));
12619 newop = expand_binop (SImode, and_optab,
12620 oldop, GEN_INT (imask), NULL_RTX,
12621 1, OPTAB_LIB_WIDEN);
12622 emit_insn (gen_ashlsi3 (newop, newop, shift));
12624 mask = gen_reg_rtx (SImode);
12625 emit_move_insn (mask, GEN_INT (imask));
12626 emit_insn (gen_ashlsi3 (mask, mask, shift));
12629 newop = gen_rtx_PLUS (SImode, m, newop);
12631 newop = gen_rtx_MINUS (SImode, m, newop);
12632 newop = gen_rtx_AND (SImode, newop, mask);
12633 newop = gen_rtx_IOR (SImode, newop,
12634 gen_rtx_AND (SImode,
12635 gen_rtx_NOT (SImode, mask),
12641 gcc_unreachable ();
12644 if (GET_CODE (m) == NOT)
12648 mask = gen_reg_rtx (SImode);
12649 emit_move_insn (mask, GEN_INT (imask));
12650 emit_insn (gen_ashlsi3 (mask, mask, shift));
12652 xorm = gen_rtx_XOR (SImode, used_m, mask);
12653 /* Depending on the value of 'op', the XOR or the operation might
12654 be able to be simplified away. */
12655 newop = simplify_gen_binary (code, SImode, xorm, newop);
12658 used_mode = SImode;
12659 before = gen_reg_rtx (used_mode);
12660 after = gen_reg_rtx (used_mode);
12665 before = before_param;
12666 after = after_param;
12668 if (before == NULL_RTX)
12669 before = gen_reg_rtx (used_mode);
12670 if (after == NULL_RTX)
12671 after = gen_reg_rtx (used_mode);
12674 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12675 && used_mode != mode)
12676 the_op = op; /* Computed above. */
12677 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12678 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12680 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12682 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12683 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12684 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12685 gen_rtx_UNSPEC (used_mode,
12686 gen_rtvec (1, the_op),
12688 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12690 if ((code == PLUS || code == MINUS) && used_mode != mode)
12691 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12692 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12694 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12695 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12697 /* Shift and mask the return values properly. */
12698 if (used_mode != mode && before_param)
12700 emit_insn (gen_lshrsi3 (before, before, shift));
12701 convert_move (before_param, before, 1);
12704 if (used_mode != mode && after_param)
12706 emit_insn (gen_lshrsi3 (after, after, shift));
12707 convert_move (after_param, after, 1);
12710 /* The previous sequence will end with a branch that's dependent on
12711 the conditional store, so placing an isync will ensure that no
12712 other instructions (especially, no load or store instructions)
12713 can start before the atomic operation completes. */
12715 emit_insn (gen_isync ());
12718 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12719 COND is true. Mark the jump as unlikely to be taken. */
12722 emit_unlikely_jump (rtx cond, rtx label)
12724 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12727 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12728 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12729 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12732 /* A subroutine of the atomic operation splitters. Emit a load-locked
12733 instruction in MODE. */
12736 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12738 rtx (*fn) (rtx, rtx) = NULL;
12739 if (mode == SImode)
12740 fn = gen_load_locked_si;
12741 else if (mode == DImode)
12742 fn = gen_load_locked_di;
12743 emit_insn (fn (reg, mem));
12746 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12747 instruction in MODE. */
12750 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12752 rtx (*fn) (rtx, rtx, rtx) = NULL;
12753 if (mode == SImode)
12754 fn = gen_store_conditional_si;
12755 else if (mode == DImode)
12756 fn = gen_store_conditional_di;
12758 /* Emit sync before stwcx. to address PPC405 Erratum. */
12759 if (PPC405_ERRATUM77)
12760 emit_insn (gen_memory_barrier ());
12762 emit_insn (fn (res, mem, val));
12765 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
12766 to perform. MEM is the memory on which to operate. VAL is the second
12767 operand of the binary operator. BEFORE and AFTER are optional locations to
12768 return the value of MEM either before of after the operation. SCRATCH is
12769 a scratch register. */
12772 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12773 rtx before, rtx after, rtx scratch)
12775 enum machine_mode mode = GET_MODE (mem);
12776 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12778 emit_insn (gen_memory_barrier ());
12780 label = gen_label_rtx ();
12781 emit_label (label);
12782 label = gen_rtx_LABEL_REF (VOIDmode, label);
12784 if (before == NULL_RTX)
12786 emit_load_locked (mode, before, mem);
12789 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12790 else if (code == AND)
12791 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12793 x = gen_rtx_fmt_ee (code, mode, before, val);
12795 if (after != NULL_RTX)
12796 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12797 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12799 emit_store_conditional (mode, cond, mem, scratch);
12801 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12802 emit_unlikely_jump (x, label);
12804 emit_insn (gen_isync ());
12807 /* Expand an atomic compare and swap operation. MEM is the memory on which
12808 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12809 value to be stored. SCRATCH is a scratch GPR. */
12812 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12815 enum machine_mode mode = GET_MODE (mem);
12816 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12818 emit_insn (gen_memory_barrier ());
12820 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12821 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12822 emit_label (XEXP (label1, 0));
12824 emit_load_locked (mode, retval, mem);
12826 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12827 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12829 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12830 emit_unlikely_jump (x, label2);
12832 emit_move_insn (scratch, newval);
12833 emit_store_conditional (mode, cond, mem, scratch);
12835 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12836 emit_unlikely_jump (x, label1);
12838 emit_insn (gen_isync ());
12839 emit_label (XEXP (label2, 0));
12842 /* Expand an atomic test and set operation. MEM is the memory on which
12843 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12846 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
12848 enum machine_mode mode = GET_MODE (mem);
12849 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12851 emit_insn (gen_memory_barrier ());
12853 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12854 emit_label (XEXP (label, 0));
12856 emit_load_locked (mode, retval, mem);
12857 emit_move_insn (scratch, val);
12858 emit_store_conditional (mode, cond, mem, scratch);
12860 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12861 emit_unlikely_jump (x, label);
12863 emit_insn (gen_isync ());
12867 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
12869 enum machine_mode mode = GET_MODE (mem);
12870 rtx addrSI, align, wdst, shift, mask;
12871 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
12872 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12874 /* Shift amount for subword relative to aligned word. */
12875 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
12876 shift = gen_reg_rtx (SImode);
12877 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12878 GEN_INT (shift_mask)));
12879 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12881 /* Shift and mask old value into position within word. */
12882 oldval = convert_modes (SImode, mode, oldval, 1);
12883 oldval = expand_binop (SImode, and_optab,
12884 oldval, GEN_INT (imask), NULL_RTX,
12885 1, OPTAB_LIB_WIDEN);
12886 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
12888 /* Shift and mask new value into position within word. */
12889 newval = convert_modes (SImode, mode, newval, 1);
12890 newval = expand_binop (SImode, and_optab,
12891 newval, GEN_INT (imask), NULL_RTX,
12892 1, OPTAB_LIB_WIDEN);
12893 emit_insn (gen_ashlsi3 (newval, newval, shift));
12895 /* Mask for insertion. */
12896 mask = gen_reg_rtx (SImode);
12897 emit_move_insn (mask, GEN_INT (imask));
12898 emit_insn (gen_ashlsi3 (mask, mask, shift));
12900 /* Address of aligned word containing subword. */
12901 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
12902 NULL_RTX, 1, OPTAB_LIB_WIDEN);
12903 mem = change_address (mem, SImode, align);
12904 set_mem_align (mem, 32);
12905 MEM_VOLATILE_P (mem) = 1;
12907 wdst = gen_reg_rtx (SImode);
12908 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
12909 oldval, newval, mem));
12911 emit_move_insn (dst, gen_lowpart (mode, wdst));
12915 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
12916 rtx oldval, rtx newval, rtx mem,
12919 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12921 emit_insn (gen_memory_barrier ());
12922 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12923 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12924 emit_label (XEXP (label1, 0));
12926 emit_load_locked (SImode, scratch, mem);
12928 /* Mask subword within loaded value for comparison with oldval.
12929 Use UNSPEC_AND to avoid clobber.*/
12930 emit_insn (gen_rtx_SET (SImode, dest,
12931 gen_rtx_UNSPEC (SImode,
12932 gen_rtvec (2, scratch, mask),
12935 x = gen_rtx_COMPARE (CCmode, dest, oldval);
12936 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12938 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12939 emit_unlikely_jump (x, label2);
12941 /* Clear subword within loaded value for insertion of new value. */
12942 emit_insn (gen_rtx_SET (SImode, scratch,
12943 gen_rtx_AND (SImode,
12944 gen_rtx_NOT (SImode, mask), scratch)));
12945 emit_insn (gen_iorsi3 (scratch, scratch, newval));
12946 emit_store_conditional (SImode, cond, mem, scratch);
12948 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12949 emit_unlikely_jump (x, label1);
12951 emit_insn (gen_isync ());
12952 emit_label (XEXP (label2, 0));
12956 /* Emit instructions to move SRC to DST. Called by splitters for
12957 multi-register moves. It will emit at most one instruction for
12958 each register that is accessed; that is, it won't emit li/lis pairs
12959 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12963 rs6000_split_multireg_move (rtx dst, rtx src)
12965 /* The register number of the first register being moved. */
12967 /* The mode that is to be moved. */
12968 enum machine_mode mode;
12969 /* The mode that the move is being done in, and its size. */
12970 enum machine_mode reg_mode;
12972 /* The number of registers that will be moved. */
12975 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12976 mode = GET_MODE (dst);
12977 nregs = hard_regno_nregs[reg][mode];
12978 if (FP_REGNO_P (reg))
12979 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
12980 else if (ALTIVEC_REGNO_P (reg))
12981 reg_mode = V16QImode;
12982 else if (TARGET_E500_DOUBLE && mode == TFmode)
12985 reg_mode = word_mode;
12986 reg_mode_size = GET_MODE_SIZE (reg_mode);
12988 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
12990 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12992 /* Move register range backwards, if we might have destructive
12995 for (i = nregs - 1; i >= 0; i--)
12996 emit_insn (gen_rtx_SET (VOIDmode,
12997 simplify_gen_subreg (reg_mode, dst, mode,
12998 i * reg_mode_size),
12999 simplify_gen_subreg (reg_mode, src, mode,
13000 i * reg_mode_size)));
13006 bool used_update = false;
13008 if (MEM_P (src) && INT_REGNO_P (reg))
13012 if (GET_CODE (XEXP (src, 0)) == PRE_INC
13013 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
13016 breg = XEXP (XEXP (src, 0), 0);
13017 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
13018 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
13019 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
13020 emit_insn (TARGET_32BIT
13021 ? gen_addsi3 (breg, breg, delta_rtx)
13022 : gen_adddi3 (breg, breg, delta_rtx));
13023 src = replace_equiv_address (src, breg);
13025 else if (! rs6000_offsettable_memref_p (src))
13028 basereg = gen_rtx_REG (Pmode, reg);
13029 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
13030 src = replace_equiv_address (src, basereg);
13033 breg = XEXP (src, 0);
13034 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
13035 breg = XEXP (breg, 0);
13037 /* If the base register we are using to address memory is
13038 also a destination reg, then change that register last. */
13040 && REGNO (breg) >= REGNO (dst)
13041 && REGNO (breg) < REGNO (dst) + nregs)
13042 j = REGNO (breg) - REGNO (dst);
13045 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
13049 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
13050 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
13053 breg = XEXP (XEXP (dst, 0), 0);
13054 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
13055 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
13056 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
13058 /* We have to update the breg before doing the store.
13059 Use store with update, if available. */
13063 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
13064 emit_insn (TARGET_32BIT
13065 ? (TARGET_POWERPC64
13066 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
13067 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
13068 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
13069 used_update = true;
13072 emit_insn (TARGET_32BIT
13073 ? gen_addsi3 (breg, breg, delta_rtx)
13074 : gen_adddi3 (breg, breg, delta_rtx));
13075 dst = replace_equiv_address (dst, breg);
13078 gcc_assert (rs6000_offsettable_memref_p (dst));
13081 for (i = 0; i < nregs; i++)
13083 /* Calculate index to next subword. */
13088 /* If compiler already emitted move of first word by
13089 store with update, no need to do anything. */
13090 if (j == 0 && used_update)
13093 emit_insn (gen_rtx_SET (VOIDmode,
13094 simplify_gen_subreg (reg_mode, dst, mode,
13095 j * reg_mode_size),
13096 simplify_gen_subreg (reg_mode, src, mode,
13097 j * reg_mode_size)));
13103 /* This page contains routines that are used to determine what the
13104 function prologue and epilogue code will do and write them out. */
13106 /* Return the first fixed-point register that is required to be
13107 saved. 32 if none. */
13110 first_reg_to_save (void)
13114 /* Find lowest numbered live register. */
13115 for (first_reg = 13; first_reg <= 31; first_reg++)
13116 if (regs_ever_live[first_reg]
13117 && (! call_used_regs[first_reg]
13118 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
13119 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13120 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
13121 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
13126 && current_function_uses_pic_offset_table
13127 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
13128 return RS6000_PIC_OFFSET_TABLE_REGNUM;
13134 /* Similar, for FP regs. */
13137 first_fp_reg_to_save (void)
13141 /* Find lowest numbered live register. */
13142 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
13143 if (regs_ever_live[first_reg])
13149 /* Similar, for AltiVec regs. */
13152 first_altivec_reg_to_save (void)
13156 /* Stack frame remains as is unless we are in AltiVec ABI. */
13157 if (! TARGET_ALTIVEC_ABI)
13158 return LAST_ALTIVEC_REGNO + 1;
13160 /* On Darwin, the unwind routines are compiled without
13161 TARGET_ALTIVEC, and use save_world to save/restore the
13162 altivec registers when necessary. */
13163 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13164 && ! TARGET_ALTIVEC)
13165 return FIRST_ALTIVEC_REGNO + 20;
13167 /* Find lowest numbered live register. */
13168 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
13169 if (regs_ever_live[i])
13175 /* Return a 32-bit mask of the AltiVec registers we need to set in
13176 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
13177 the 32-bit word is 0. */
13179 static unsigned int
13180 compute_vrsave_mask (void)
13182 unsigned int i, mask = 0;
13184 /* On Darwin, the unwind routines are compiled without
13185 TARGET_ALTIVEC, and use save_world to save/restore the
13186 call-saved altivec registers when necessary. */
13187 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13188 && ! TARGET_ALTIVEC)
13191 /* First, find out if we use _any_ altivec registers. */
13192 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13193 if (regs_ever_live[i])
13194 mask |= ALTIVEC_REG_BIT (i);
13199 /* Next, remove the argument registers from the set. These must
13200 be in the VRSAVE mask set by the caller, so we don't need to add
13201 them in again. More importantly, the mask we compute here is
13202 used to generate CLOBBERs in the set_vrsave insn, and we do not
13203 wish the argument registers to die. */
13204 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
13205 mask &= ~ALTIVEC_REG_BIT (i);
13207 /* Similarly, remove the return value from the set. */
13210 diddle_return_value (is_altivec_return_reg, &yes);
13212 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
13218 /* For a very restricted set of circumstances, we can cut down the
13219 size of prologues/epilogues by calling our own save/restore-the-world
13223 compute_save_world_info (rs6000_stack_t *info_ptr)
13225 info_ptr->world_save_p = 1;
13226 info_ptr->world_save_p
13227 = (WORLD_SAVE_P (info_ptr)
13228 && DEFAULT_ABI == ABI_DARWIN
13229 && ! (current_function_calls_setjmp && flag_exceptions)
13230 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
13231 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
13232 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
13233 && info_ptr->cr_save_p);
13235 /* This will not work in conjunction with sibcalls. Make sure there
13236 are none. (This check is expensive, but seldom executed.) */
13237 if (WORLD_SAVE_P (info_ptr))
13240 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
13241 if ( GET_CODE (insn) == CALL_INSN
13242 && SIBLING_CALL_P (insn))
13244 info_ptr->world_save_p = 0;
13249 if (WORLD_SAVE_P (info_ptr))
13251 /* Even if we're not touching VRsave, make sure there's room on the
13252 stack for it, if it looks like we're calling SAVE_WORLD, which
13253 will attempt to save it. */
13254 info_ptr->vrsave_size = 4;
13256 /* "Save" the VRsave register too if we're saving the world. */
13257 if (info_ptr->vrsave_mask == 0)
13258 info_ptr->vrsave_mask = compute_vrsave_mask ();
13260 /* Because the Darwin register save/restore routines only handle
13261 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
13263 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
13264 && (info_ptr->first_altivec_reg_save
13265 >= FIRST_SAVED_ALTIVEC_REGNO));
13272 is_altivec_return_reg (rtx reg, void *xyes)
13274 bool *yes = (bool *) xyes;
13275 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
13280 /* Calculate the stack information for the current function. This is
13281 complicated by having two separate calling sequences, the AIX calling
13282 sequence and the V.4 calling sequence.
13284 AIX (and Darwin/Mac OS X) stack frames look like:
13286 SP----> +---------------------------------------+
13287 | back chain to caller | 0 0
13288 +---------------------------------------+
13289 | saved CR | 4 8 (8-11)
13290 +---------------------------------------+
13292 +---------------------------------------+
13293 | reserved for compilers | 12 24
13294 +---------------------------------------+
13295 | reserved for binders | 16 32
13296 +---------------------------------------+
13297 | saved TOC pointer | 20 40
13298 +---------------------------------------+
13299 | Parameter save area (P) | 24 48
13300 +---------------------------------------+
13301 | Alloca space (A) | 24+P etc.
13302 +---------------------------------------+
13303 | Local variable space (L) | 24+P+A
13304 +---------------------------------------+
13305 | Float/int conversion temporary (X) | 24+P+A+L
13306 +---------------------------------------+
13307 | Save area for AltiVec registers (W) | 24+P+A+L+X
13308 +---------------------------------------+
13309 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
13310 +---------------------------------------+
13311 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
13312 +---------------------------------------+
13313 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
13314 +---------------------------------------+
13315 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
13316 +---------------------------------------+
13317 old SP->| back chain to caller's caller |
13318 +---------------------------------------+
13320 The required alignment for AIX configurations is two words (i.e., 8
13324 V.4 stack frames look like:
13326 SP----> +---------------------------------------+
13327 | back chain to caller | 0
13328 +---------------------------------------+
13329 | caller's saved LR | 4
13330 +---------------------------------------+
13331 | Parameter save area (P) | 8
13332 +---------------------------------------+
13333 | Alloca space (A) | 8+P
13334 +---------------------------------------+
13335 | Varargs save area (V) | 8+P+A
13336 +---------------------------------------+
13337 | Local variable space (L) | 8+P+A+V
13338 +---------------------------------------+
13339 | Float/int conversion temporary (X) | 8+P+A+V+L
13340 +---------------------------------------+
13341 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
13342 +---------------------------------------+
13343 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
13344 +---------------------------------------+
13345 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
13346 +---------------------------------------+
13347 | SPE: area for 64-bit GP registers |
13348 +---------------------------------------+
13349 | SPE alignment padding |
13350 +---------------------------------------+
13351 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
13352 +---------------------------------------+
13353 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
13354 +---------------------------------------+
13355 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
13356 +---------------------------------------+
13357 old SP->| back chain to caller's caller |
13358 +---------------------------------------+
13360 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
13361 given. (But note below and in sysv4.h that we require only 8 and
13362 may round up the size of our stack frame anyways. The historical
13363 reason is early versions of powerpc-linux which didn't properly
13364 align the stack at program startup. A happy side-effect is that
13365 -mno-eabi libraries can be used with -meabi programs.)
13367 The EABI configuration defaults to the V.4 layout. However,
13368 the stack alignment requirements may differ. If -mno-eabi is not
13369 given, the required stack alignment is 8 bytes; if -mno-eabi is
13370 given, the required alignment is 16 bytes. (But see V.4 comment
13373 #ifndef ABI_STACK_BOUNDARY
13374 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
13377 static rs6000_stack_t *
13378 rs6000_stack_info (void)
13380 static rs6000_stack_t info;
13381 rs6000_stack_t *info_ptr = &info;
13382 int reg_size = TARGET_32BIT ? 4 : 8;
13385 HOST_WIDE_INT non_fixed_size;
13387 memset (&info, 0, sizeof (info));
13391 /* Cache value so we don't rescan instruction chain over and over. */
13392 if (cfun->machine->insn_chain_scanned_p == 0)
13393 cfun->machine->insn_chain_scanned_p
13394 = spe_func_has_64bit_regs_p () + 1;
13395 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
13398 /* Select which calling sequence. */
13399 info_ptr->abi = DEFAULT_ABI;
13401 /* Calculate which registers need to be saved & save area size. */
13402 info_ptr->first_gp_reg_save = first_reg_to_save ();
13403 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
13404 even if it currently looks like we won't. */
13405 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
13406 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
13407 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
13408 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
13409 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
13411 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
13413 /* For the SPE, we have an additional upper 32-bits on each GPR.
13414 Ideally we should save the entire 64-bits only when the upper
13415 half is used in SIMD instructions. Since we only record
13416 registers live (not the size they are used in), this proves
13417 difficult because we'd have to traverse the instruction chain at
13418 the right time, taking reload into account. This is a real pain,
13419 so we opt to save the GPRs in 64-bits always if but one register
13420 gets used in 64-bits. Otherwise, all the registers in the frame
13421 get saved in 32-bits.
13423 So... since when we save all GPRs (except the SP) in 64-bits, the
13424 traditional GP save area will be empty. */
13425 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13426 info_ptr->gp_size = 0;
13428 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
13429 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
13431 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
13432 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
13433 - info_ptr->first_altivec_reg_save);
13435 /* Does this function call anything? */
13436 info_ptr->calls_p = (! current_function_is_leaf
13437 || cfun->machine->ra_needs_full_frame);
13439 /* Determine if we need to save the link register. */
13440 if ((DEFAULT_ABI == ABI_AIX
13441 && current_function_profile
13442 && !TARGET_PROFILE_KERNEL)
13443 #ifdef TARGET_RELOCATABLE
13444 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
13446 || (info_ptr->first_fp_reg_save != 64
13447 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
13448 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
13449 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
13450 || info_ptr->calls_p
13451 || rs6000_ra_ever_killed ())
13453 info_ptr->lr_save_p = 1;
13454 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
13457 /* Determine if we need to save the condition code registers. */
13458 if (regs_ever_live[CR2_REGNO]
13459 || regs_ever_live[CR3_REGNO]
13460 || regs_ever_live[CR4_REGNO])
13462 info_ptr->cr_save_p = 1;
13463 if (DEFAULT_ABI == ABI_V4)
13464 info_ptr->cr_size = reg_size;
13467 /* If the current function calls __builtin_eh_return, then we need
13468 to allocate stack space for registers that will hold data for
13469 the exception handler. */
13470 if (current_function_calls_eh_return)
13473 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
13476 /* SPE saves EH registers in 64-bits. */
13477 ehrd_size = i * (TARGET_SPE_ABI
13478 && info_ptr->spe_64bit_regs_used != 0
13479 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
13484 /* Determine various sizes. */
13485 info_ptr->reg_size = reg_size;
13486 info_ptr->fixed_size = RS6000_SAVE_AREA;
13487 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
13488 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
13489 TARGET_ALTIVEC ? 16 : 8);
13490 if (FRAME_GROWS_DOWNWARD)
13491 info_ptr->vars_size
13492 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
13493 + info_ptr->parm_size,
13494 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
13495 - (info_ptr->fixed_size + info_ptr->vars_size
13496 + info_ptr->parm_size);
13498 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13499 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
13501 info_ptr->spe_gp_size = 0;
13503 if (TARGET_ALTIVEC_ABI)
13504 info_ptr->vrsave_mask = compute_vrsave_mask ();
13506 info_ptr->vrsave_mask = 0;
13508 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
13509 info_ptr->vrsave_size = 4;
13511 info_ptr->vrsave_size = 0;
13513 compute_save_world_info (info_ptr);
13515 /* Calculate the offsets. */
13516 switch (DEFAULT_ABI)
13520 gcc_unreachable ();
13524 info_ptr->fp_save_offset = - info_ptr->fp_size;
13525 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13527 if (TARGET_ALTIVEC_ABI)
13529 info_ptr->vrsave_save_offset
13530 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
13532 /* Align stack so vector save area is on a quadword boundary.
13533 The padding goes above the vectors. */
13534 if (info_ptr->altivec_size != 0)
13535 info_ptr->altivec_padding_size
13536 = info_ptr->vrsave_save_offset & 0xF;
13538 info_ptr->altivec_padding_size = 0;
13540 info_ptr->altivec_save_offset
13541 = info_ptr->vrsave_save_offset
13542 - info_ptr->altivec_padding_size
13543 - info_ptr->altivec_size;
13544 gcc_assert (info_ptr->altivec_size == 0
13545 || info_ptr->altivec_save_offset % 16 == 0);
13547 /* Adjust for AltiVec case. */
13548 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
13551 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
13552 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
13553 info_ptr->lr_save_offset = 2*reg_size;
13557 info_ptr->fp_save_offset = - info_ptr->fp_size;
13558 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13559 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
13561 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13563 /* Align stack so SPE GPR save area is aligned on a
13564 double-word boundary. */
13565 if (info_ptr->spe_gp_size != 0)
13566 info_ptr->spe_padding_size
13567 = 8 - (-info_ptr->cr_save_offset % 8);
13569 info_ptr->spe_padding_size = 0;
13571 info_ptr->spe_gp_save_offset
13572 = info_ptr->cr_save_offset
13573 - info_ptr->spe_padding_size
13574 - info_ptr->spe_gp_size;
13576 /* Adjust for SPE case. */
13577 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
13579 else if (TARGET_ALTIVEC_ABI)
13581 info_ptr->vrsave_save_offset
13582 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
13584 /* Align stack so vector save area is on a quadword boundary. */
13585 if (info_ptr->altivec_size != 0)
13586 info_ptr->altivec_padding_size
13587 = 16 - (-info_ptr->vrsave_save_offset % 16);
13589 info_ptr->altivec_padding_size = 0;
13591 info_ptr->altivec_save_offset
13592 = info_ptr->vrsave_save_offset
13593 - info_ptr->altivec_padding_size
13594 - info_ptr->altivec_size;
13596 /* Adjust for AltiVec case. */
13597 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
13600 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
13601 info_ptr->ehrd_offset -= ehrd_size;
13602 info_ptr->lr_save_offset = reg_size;
13606 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
13607 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
13608 + info_ptr->gp_size
13609 + info_ptr->altivec_size
13610 + info_ptr->altivec_padding_size
13611 + info_ptr->spe_gp_size
13612 + info_ptr->spe_padding_size
13614 + info_ptr->cr_size
13615 + info_ptr->vrsave_size,
13618 non_fixed_size = (info_ptr->vars_size
13619 + info_ptr->parm_size
13620 + info_ptr->save_size);
13622 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
13623 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
13625 /* Determine if we need to allocate any stack frame:
13627 For AIX we need to push the stack if a frame pointer is needed
13628 (because the stack might be dynamically adjusted), if we are
13629 debugging, if we make calls, or if the sum of fp_save, gp_save,
13630 and local variables are more than the space needed to save all
13631 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
13632 + 18*8 = 288 (GPR13 reserved).
13634 For V.4 we don't have the stack cushion that AIX uses, but assume
13635 that the debugger can handle stackless frames. */
13637 if (info_ptr->calls_p)
13638 info_ptr->push_p = 1;
13640 else if (DEFAULT_ABI == ABI_V4)
13641 info_ptr->push_p = non_fixed_size != 0;
13643 else if (frame_pointer_needed)
13644 info_ptr->push_p = 1;
13646 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
13647 info_ptr->push_p = 1;
13650 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
13652 /* Zero offsets if we're not saving those registers. */
13653 if (info_ptr->fp_size == 0)
13654 info_ptr->fp_save_offset = 0;
13656 if (info_ptr->gp_size == 0)
13657 info_ptr->gp_save_offset = 0;
13659 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
13660 info_ptr->altivec_save_offset = 0;
13662 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
13663 info_ptr->vrsave_save_offset = 0;
13665 if (! TARGET_SPE_ABI
13666 || info_ptr->spe_64bit_regs_used == 0
13667 || info_ptr->spe_gp_size == 0)
13668 info_ptr->spe_gp_save_offset = 0;
13670 if (! info_ptr->lr_save_p)
13671 info_ptr->lr_save_offset = 0;
13673 if (! info_ptr->cr_save_p)
13674 info_ptr->cr_save_offset = 0;
13679 /* Return true if the current function uses any GPRs in 64-bit SIMD
13683 spe_func_has_64bit_regs_p (void)
13687 /* Functions that save and restore all the call-saved registers will
13688 need to save/restore the registers in 64-bits. */
13689 if (current_function_calls_eh_return
13690 || current_function_calls_setjmp
13691 || current_function_has_nonlocal_goto)
13694 insns = get_insns ();
13696 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13702 /* FIXME: This should be implemented with attributes...
13704 (set_attr "spe64" "true")....then,
13705 if (get_spe64(insn)) return true;
13707 It's the only reliable way to do the stuff below. */
13709 i = PATTERN (insn);
13710 if (GET_CODE (i) == SET)
13712 enum machine_mode mode = GET_MODE (SET_SRC (i));
13714 if (SPE_VECTOR_MODE (mode))
13716 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
13726 debug_stack_info (rs6000_stack_t *info)
13728 const char *abi_string;
13731 info = rs6000_stack_info ();
13733 fprintf (stderr, "\nStack information for function %s:\n",
13734 ((current_function_decl && DECL_NAME (current_function_decl))
13735 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13740 default: abi_string = "Unknown"; break;
13741 case ABI_NONE: abi_string = "NONE"; break;
13742 case ABI_AIX: abi_string = "AIX"; break;
13743 case ABI_DARWIN: abi_string = "Darwin"; break;
13744 case ABI_V4: abi_string = "V.4"; break;
13747 fprintf (stderr, "\tABI = %5s\n", abi_string);
13749 if (TARGET_ALTIVEC_ABI)
13750 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13752 if (TARGET_SPE_ABI)
13753 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13755 if (info->first_gp_reg_save != 32)
13756 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13758 if (info->first_fp_reg_save != 64)
13759 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13761 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13762 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13763 info->first_altivec_reg_save);
13765 if (info->lr_save_p)
13766 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13768 if (info->cr_save_p)
13769 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13771 if (info->vrsave_mask)
13772 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13775 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13778 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13780 if (info->gp_save_offset)
13781 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13783 if (info->fp_save_offset)
13784 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13786 if (info->altivec_save_offset)
13787 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13788 info->altivec_save_offset);
13790 if (info->spe_gp_save_offset)
13791 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13792 info->spe_gp_save_offset);
13794 if (info->vrsave_save_offset)
13795 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13796 info->vrsave_save_offset);
13798 if (info->lr_save_offset)
13799 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13801 if (info->cr_save_offset)
13802 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13804 if (info->varargs_save_offset)
13805 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13807 if (info->total_size)
13808 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13811 if (info->vars_size)
13812 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13815 if (info->parm_size)
13816 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13818 if (info->fixed_size)
13819 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13822 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13824 if (info->spe_gp_size)
13825 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13828 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13830 if (info->altivec_size)
13831 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13833 if (info->vrsave_size)
13834 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13836 if (info->altivec_padding_size)
13837 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13838 info->altivec_padding_size);
13840 if (info->spe_padding_size)
13841 fprintf (stderr, "\tspe_padding_size = %5d\n",
13842 info->spe_padding_size);
13845 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13847 if (info->save_size)
13848 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13850 if (info->reg_size != 4)
13851 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13853 fprintf (stderr, "\n");
13857 rs6000_return_addr (int count, rtx frame)
13859 /* Currently we don't optimize very well between prolog and body
13860 code and for PIC code the code can be actually quite bad, so
13861 don't try to be too clever here. */
13862 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13864 cfun->machine->ra_needs_full_frame = 1;
13871 plus_constant (copy_to_reg
13872 (gen_rtx_MEM (Pmode,
13873 memory_address (Pmode, frame))),
13874 RETURN_ADDRESS_OFFSET)));
13877 cfun->machine->ra_need_lr = 1;
13878 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13881 /* Say whether a function is a candidate for sibcall handling or not.
13882 We do not allow indirect calls to be optimized into sibling calls.
13883 Also, we can't do it if there are any vector parameters; there's
13884 nowhere to put the VRsave code so it works; note that functions with
13885 vector parameters are required to have a prototype, so the argument
13886 type info must be available here. (The tail recursion case can work
13887 with vector parameters, but there's no way to distinguish here.) */
13889 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13894 if (TARGET_ALTIVEC_VRSAVE)
13896 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13897 type; type = TREE_CHAIN (type))
13899 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13903 if (DEFAULT_ABI == ABI_DARWIN
13904 || (*targetm.binds_local_p) (decl))
13906 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13908 if (!lookup_attribute ("longcall", attr_list)
13909 || lookup_attribute ("shortcall", attr_list))
13916 /* NULL if INSN insn is valid within a low-overhead loop.
13917 Otherwise return why doloop cannot be applied.
13918 PowerPC uses the COUNT register for branch on table instructions. */
13920 static const char *
13921 rs6000_invalid_within_doloop (rtx insn)
13924 return "Function call in the loop.";
13927 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
13928 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
13929 return "Computed branch in the loop.";
13935 rs6000_ra_ever_killed (void)
13941 if (current_function_is_thunk)
13944 /* regs_ever_live has LR marked as used if any sibcalls are present,
13945 but this should not force saving and restoring in the
13946 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13947 clobbers LR, so that is inappropriate. */
13949 /* Also, the prologue can generate a store into LR that
13950 doesn't really count, like this:
13953 bcl to set PIC register
13957 When we're called from the epilogue, we need to avoid counting
13958 this as a store. */
13960 push_topmost_sequence ();
13961 top = get_insns ();
13962 pop_topmost_sequence ();
13963 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13965 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13971 if (!SIBLING_CALL_P (insn))
13974 else if (find_regno_note (insn, REG_INC, LINK_REGISTER_REGNUM))
13976 else if (set_of (reg, insn) != NULL_RTX
13977 && !prologue_epilogue_contains (insn))
13984 /* Add a REG_MAYBE_DEAD note to the insn. */
13986 rs6000_maybe_dead (rtx insn)
13988 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13993 /* Emit instructions needed to load the TOC register.
13994 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13995 a constant pool; or for SVR4 -fpic. */
13998 rs6000_emit_load_toc_table (int fromprolog)
14001 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
14003 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
14006 rtx lab, tmp1, tmp2, got;
14008 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14009 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14011 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14013 got = rs6000_got_sym ();
14014 tmp1 = tmp2 = dest;
14017 tmp1 = gen_reg_rtx (Pmode);
14018 tmp2 = gen_reg_rtx (Pmode);
14020 insn = emit_insn (gen_load_toc_v4_PIC_1 (lab));
14022 rs6000_maybe_dead (insn);
14023 insn = emit_move_insn (tmp1,
14024 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14026 rs6000_maybe_dead (insn);
14027 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
14029 rs6000_maybe_dead (insn);
14030 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
14032 rs6000_maybe_dead (insn);
14034 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
14036 insn = emit_insn (gen_load_toc_v4_pic_si ());
14038 rs6000_maybe_dead (insn);
14039 insn = emit_move_insn (dest,
14040 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14042 rs6000_maybe_dead (insn);
14044 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
14047 rtx temp0 = (fromprolog
14048 ? gen_rtx_REG (Pmode, 0)
14049 : gen_reg_rtx (Pmode));
14055 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14056 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14058 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
14059 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14061 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (symF)));
14062 rs6000_maybe_dead (emit_move_insn (dest,
14063 gen_rtx_REG (Pmode,
14064 LINK_REGISTER_REGNUM)));
14065 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
14073 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14074 emit_insn (gen_load_toc_v4_PIC_1b (tocsym));
14075 emit_move_insn (dest,
14076 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14077 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
14079 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
14081 rs6000_maybe_dead (insn);
14083 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
14085 /* This is for AIX code running in non-PIC ELF32. */
14088 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
14089 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14091 insn = emit_insn (gen_elf_high (dest, realsym));
14093 rs6000_maybe_dead (insn);
14094 insn = emit_insn (gen_elf_low (dest, dest, realsym));
14096 rs6000_maybe_dead (insn);
14100 gcc_assert (DEFAULT_ABI == ABI_AIX);
14103 insn = emit_insn (gen_load_toc_aix_si (dest));
14105 insn = emit_insn (gen_load_toc_aix_di (dest));
14107 rs6000_maybe_dead (insn);
14111 /* Emit instructions to restore the link register after determining where
14112 its value has been stored. */
14115 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
14117 rs6000_stack_t *info = rs6000_stack_info ();
14120 operands[0] = source;
14121 operands[1] = scratch;
14123 if (info->lr_save_p)
14125 rtx frame_rtx = stack_pointer_rtx;
14126 HOST_WIDE_INT sp_offset = 0;
14129 if (frame_pointer_needed
14130 || current_function_calls_alloca
14131 || info->total_size > 32767)
14133 tmp = gen_frame_mem (Pmode, frame_rtx);
14134 emit_move_insn (operands[1], tmp);
14135 frame_rtx = operands[1];
14137 else if (info->push_p)
14138 sp_offset = info->total_size;
14140 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
14141 tmp = gen_frame_mem (Pmode, tmp);
14142 emit_move_insn (tmp, operands[0]);
14145 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
14148 static GTY(()) int set = -1;
14151 get_TOC_alias_set (void)
14154 set = new_alias_set ();
14158 /* This returns nonzero if the current function uses the TOC. This is
14159 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
14160 is generated by the ABI_V4 load_toc_* patterns. */
14167 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14170 rtx pat = PATTERN (insn);
14173 if (GET_CODE (pat) == PARALLEL)
14174 for (i = 0; i < XVECLEN (pat, 0); i++)
14176 rtx sub = XVECEXP (pat, 0, i);
14177 if (GET_CODE (sub) == USE)
14179 sub = XEXP (sub, 0);
14180 if (GET_CODE (sub) == UNSPEC
14181 && XINT (sub, 1) == UNSPEC_TOC)
14191 create_TOC_reference (rtx symbol)
14193 if (no_new_pseudos)
14194 regs_ever_live[TOC_REGISTER] = 1;
14195 return gen_rtx_PLUS (Pmode,
14196 gen_rtx_REG (Pmode, TOC_REGISTER),
14197 gen_rtx_CONST (Pmode,
14198 gen_rtx_MINUS (Pmode, symbol,
14199 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
14202 /* If _Unwind_* has been called from within the same module,
14203 toc register is not guaranteed to be saved to 40(1) on function
14204 entry. Save it there in that case. */
14207 rs6000_aix_emit_builtin_unwind_init (void)
14210 rtx stack_top = gen_reg_rtx (Pmode);
14211 rtx opcode_addr = gen_reg_rtx (Pmode);
14212 rtx opcode = gen_reg_rtx (SImode);
14213 rtx tocompare = gen_reg_rtx (SImode);
14214 rtx no_toc_save_needed = gen_label_rtx ();
14216 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
14217 emit_move_insn (stack_top, mem);
14219 mem = gen_frame_mem (Pmode,
14220 gen_rtx_PLUS (Pmode, stack_top,
14221 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
14222 emit_move_insn (opcode_addr, mem);
14223 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
14224 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
14225 : 0xE8410028, SImode));
14227 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
14228 SImode, NULL_RTX, NULL_RTX,
14229 no_toc_save_needed);
14231 mem = gen_frame_mem (Pmode,
14232 gen_rtx_PLUS (Pmode, stack_top,
14233 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
14234 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
14235 emit_label (no_toc_save_needed);
14238 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
14239 and the change to the stack pointer. */
14242 rs6000_emit_stack_tie (void)
14244 rtx mem = gen_frame_mem (BLKmode,
14245 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
14247 emit_insn (gen_stack_tie (mem));
14250 /* Emit the correct code for allocating stack space, as insns.
14251 If COPY_R12, make sure a copy of the old frame is left in r12.
14252 The generated code may use hard register 0 as a temporary. */
14255 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
14258 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14259 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
14260 rtx todec = gen_int_mode (-size, Pmode);
14262 if (INTVAL (todec) != -size)
14264 warning (0, "stack frame too large");
14265 emit_insn (gen_trap ());
14269 if (current_function_limit_stack)
14271 if (REG_P (stack_limit_rtx)
14272 && REGNO (stack_limit_rtx) > 1
14273 && REGNO (stack_limit_rtx) <= 31)
14275 emit_insn (TARGET_32BIT
14276 ? gen_addsi3 (tmp_reg,
14279 : gen_adddi3 (tmp_reg,
14283 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14286 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
14288 && DEFAULT_ABI == ABI_V4)
14290 rtx toload = gen_rtx_CONST (VOIDmode,
14291 gen_rtx_PLUS (Pmode,
14295 emit_insn (gen_elf_high (tmp_reg, toload));
14296 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
14297 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14301 warning (0, "stack limit expression is not supported");
14304 if (copy_r12 || ! TARGET_UPDATE)
14305 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
14311 /* Need a note here so that try_split doesn't get confused. */
14312 if (get_last_insn () == NULL_RTX)
14313 emit_note (NOTE_INSN_DELETED);
14314 insn = emit_move_insn (tmp_reg, todec);
14315 try_split (PATTERN (insn), insn, 0);
14319 insn = emit_insn (TARGET_32BIT
14320 ? gen_movsi_update (stack_reg, stack_reg,
14322 : gen_movdi_di_update (stack_reg, stack_reg,
14323 todec, stack_reg));
14327 insn = emit_insn (TARGET_32BIT
14328 ? gen_addsi3 (stack_reg, stack_reg, todec)
14329 : gen_adddi3 (stack_reg, stack_reg, todec));
14330 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
14331 gen_rtx_REG (Pmode, 12));
14334 RTX_FRAME_RELATED_P (insn) = 1;
14336 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14337 gen_rtx_SET (VOIDmode, stack_reg,
14338 gen_rtx_PLUS (Pmode, stack_reg,
14343 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
14344 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
14345 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
14346 deduce these equivalences by itself so it wasn't necessary to hold
14347 its hand so much. */
14350 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
14351 rtx reg2, rtx rreg)
14355 /* copy_rtx will not make unique copies of registers, so we need to
14356 ensure we don't have unwanted sharing here. */
14358 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14361 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14363 real = copy_rtx (PATTERN (insn));
14365 if (reg2 != NULL_RTX)
14366 real = replace_rtx (real, reg2, rreg);
14368 real = replace_rtx (real, reg,
14369 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
14370 STACK_POINTER_REGNUM),
14373 /* We expect that 'real' is either a SET or a PARALLEL containing
14374 SETs (and possibly other stuff). In a PARALLEL, all the SETs
14375 are important so they all have to be marked RTX_FRAME_RELATED_P. */
14377 if (GET_CODE (real) == SET)
14381 temp = simplify_rtx (SET_SRC (set));
14383 SET_SRC (set) = temp;
14384 temp = simplify_rtx (SET_DEST (set));
14386 SET_DEST (set) = temp;
14387 if (GET_CODE (SET_DEST (set)) == MEM)
14389 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14391 XEXP (SET_DEST (set), 0) = temp;
14398 gcc_assert (GET_CODE (real) == PARALLEL);
14399 for (i = 0; i < XVECLEN (real, 0); i++)
14400 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
14402 rtx set = XVECEXP (real, 0, i);
14404 temp = simplify_rtx (SET_SRC (set));
14406 SET_SRC (set) = temp;
14407 temp = simplify_rtx (SET_DEST (set));
14409 SET_DEST (set) = temp;
14410 if (GET_CODE (SET_DEST (set)) == MEM)
14412 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14414 XEXP (SET_DEST (set), 0) = temp;
14416 RTX_FRAME_RELATED_P (set) = 1;
14421 real = spe_synthesize_frame_save (real);
14423 RTX_FRAME_RELATED_P (insn) = 1;
14424 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14429 /* Given an SPE frame note, return a PARALLEL of SETs with the
14430 original note, plus a synthetic register save. */
14433 spe_synthesize_frame_save (rtx real)
14435 rtx synth, offset, reg, real2;
14437 if (GET_CODE (real) != SET
14438 || GET_MODE (SET_SRC (real)) != V2SImode)
14441 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
14442 frame related note. The parallel contains a set of the register
14443 being saved, and another set to a synthetic register (n+1200).
14444 This is so we can differentiate between 64-bit and 32-bit saves.
14445 Words cannot describe this nastiness. */
14447 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
14448 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
14449 && GET_CODE (SET_SRC (real)) == REG);
14452 (set (mem (plus (reg x) (const y)))
14455 (set (mem (plus (reg x) (const y+4)))
14459 real2 = copy_rtx (real);
14460 PUT_MODE (SET_DEST (real2), SImode);
14461 reg = SET_SRC (real2);
14462 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
14463 synth = copy_rtx (real2);
14465 if (BYTES_BIG_ENDIAN)
14467 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
14468 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
14471 reg = SET_SRC (synth);
14473 synth = replace_rtx (synth, reg,
14474 gen_rtx_REG (SImode, REGNO (reg) + 1200));
14476 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
14477 synth = replace_rtx (synth, offset,
14478 GEN_INT (INTVAL (offset)
14479 + (BYTES_BIG_ENDIAN ? 0 : 4)));
14481 RTX_FRAME_RELATED_P (synth) = 1;
14482 RTX_FRAME_RELATED_P (real2) = 1;
14483 if (BYTES_BIG_ENDIAN)
14484 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
14486 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
14491 /* Returns an insn that has a vrsave set operation with the
14492 appropriate CLOBBERs. */
14495 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
14498 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
14499 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14502 = gen_rtx_SET (VOIDmode,
14504 gen_rtx_UNSPEC_VOLATILE (SImode,
14505 gen_rtvec (2, reg, vrsave),
14506 UNSPECV_SET_VRSAVE));
14510 /* We need to clobber the registers in the mask so the scheduler
14511 does not move sets to VRSAVE before sets of AltiVec registers.
14513 However, if the function receives nonlocal gotos, reload will set
14514 all call saved registers live. We will end up with:
14516 (set (reg 999) (mem))
14517 (parallel [ (set (reg vrsave) (unspec blah))
14518 (clobber (reg 999))])
14520 The clobber will cause the store into reg 999 to be dead, and
14521 flow will attempt to delete an epilogue insn. In this case, we
14522 need an unspec use/set of the register. */
14524 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14525 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14527 if (!epiloguep || call_used_regs [i])
14528 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
14529 gen_rtx_REG (V4SImode, i));
14532 rtx reg = gen_rtx_REG (V4SImode, i);
14535 = gen_rtx_SET (VOIDmode,
14537 gen_rtx_UNSPEC (V4SImode,
14538 gen_rtvec (1, reg), 27));
14542 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
14544 for (i = 0; i < nclobs; ++i)
14545 XVECEXP (insn, 0, i) = clobs[i];
14550 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
14551 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
14554 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
14555 unsigned int regno, int offset, HOST_WIDE_INT total_size)
14557 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
14558 rtx replacea, replaceb;
14560 int_rtx = GEN_INT (offset);
14562 /* Some cases that need register indexed addressing. */
14563 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
14564 || (TARGET_E500_DOUBLE && mode == DFmode)
14566 && SPE_VECTOR_MODE (mode)
14567 && !SPE_CONST_OFFSET_OK (offset)))
14569 /* Whomever calls us must make sure r11 is available in the
14570 flow path of instructions in the prologue. */
14571 offset_rtx = gen_rtx_REG (Pmode, 11);
14572 emit_move_insn (offset_rtx, int_rtx);
14574 replacea = offset_rtx;
14575 replaceb = int_rtx;
14579 offset_rtx = int_rtx;
14580 replacea = NULL_RTX;
14581 replaceb = NULL_RTX;
14584 reg = gen_rtx_REG (mode, regno);
14585 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
14586 mem = gen_frame_mem (mode, addr);
14588 insn = emit_move_insn (mem, reg);
14590 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
14593 /* Emit an offset memory reference suitable for a frame store, while
14594 converting to a valid addressing mode. */
14597 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
14599 rtx int_rtx, offset_rtx;
14601 int_rtx = GEN_INT (offset);
14603 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
14604 || (TARGET_E500_DOUBLE && mode == DFmode))
14606 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14607 emit_move_insn (offset_rtx, int_rtx);
14610 offset_rtx = int_rtx;
14612 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
14615 /* Look for user-defined global regs. We should not save and restore these,
14616 and cannot use stmw/lmw if there are any in its range. */
14619 no_global_regs_above (int first_greg)
14622 for (i = 0; i < 32 - first_greg; i++)
14623 if (global_regs[first_greg + i])
14628 #ifndef TARGET_FIX_AND_CONTINUE
14629 #define TARGET_FIX_AND_CONTINUE 0
14632 /* Emit function prologue as insns. */
14635 rs6000_emit_prologue (void)
14637 rs6000_stack_t *info = rs6000_stack_info ();
14638 enum machine_mode reg_mode = Pmode;
14639 int reg_size = TARGET_32BIT ? 4 : 8;
14640 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14641 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
14642 rtx frame_reg_rtx = sp_reg_rtx;
14643 rtx cr_save_rtx = NULL_RTX;
14645 int saving_FPRs_inline;
14646 int using_store_multiple;
14647 HOST_WIDE_INT sp_offset = 0;
14649 if (TARGET_FIX_AND_CONTINUE)
14651 /* gdb on darwin arranges to forward a function from the old
14652 address by modifying the first 5 instructions of the function
14653 to branch to the overriding function. This is necessary to
14654 permit function pointers that point to the old function to
14655 actually forward to the new function. */
14656 emit_insn (gen_nop ());
14657 emit_insn (gen_nop ());
14658 emit_insn (gen_nop ());
14659 emit_insn (gen_nop ());
14660 emit_insn (gen_nop ());
14663 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14665 reg_mode = V2SImode;
14669 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14670 && (!TARGET_SPE_ABI
14671 || info->spe_64bit_regs_used == 0)
14672 && info->first_gp_reg_save < 31
14673 && no_global_regs_above (info->first_gp_reg_save));
14674 saving_FPRs_inline = (info->first_fp_reg_save == 64
14675 || FP_SAVE_INLINE (info->first_fp_reg_save)
14676 || current_function_calls_eh_return
14677 || cfun->machine->ra_need_lr);
14679 /* For V.4, update stack before we do any saving and set back pointer. */
14680 if (! WORLD_SAVE_P (info)
14682 && (DEFAULT_ABI == ABI_V4
14683 || current_function_calls_eh_return))
14685 if (info->total_size < 32767)
14686 sp_offset = info->total_size;
14688 frame_reg_rtx = frame_ptr_rtx;
14689 rs6000_emit_allocate_stack (info->total_size,
14690 (frame_reg_rtx != sp_reg_rtx
14691 && (info->cr_save_p
14693 || info->first_fp_reg_save < 64
14694 || info->first_gp_reg_save < 32
14696 if (frame_reg_rtx != sp_reg_rtx)
14697 rs6000_emit_stack_tie ();
14700 /* Handle world saves specially here. */
14701 if (WORLD_SAVE_P (info))
14708 /* save_world expects lr in r0. */
14709 reg0 = gen_rtx_REG (Pmode, 0);
14710 if (info->lr_save_p)
14712 insn = emit_move_insn (reg0,
14713 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14714 RTX_FRAME_RELATED_P (insn) = 1;
14717 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14718 assumptions about the offsets of various bits of the stack
14720 gcc_assert (info->gp_save_offset == -220
14721 && info->fp_save_offset == -144
14722 && info->lr_save_offset == 8
14723 && info->cr_save_offset == 4
14726 && (!current_function_calls_eh_return
14727 || info->ehrd_offset == -432)
14728 && info->vrsave_save_offset == -224
14729 && info->altivec_save_offset == -416);
14731 treg = gen_rtx_REG (SImode, 11);
14732 emit_move_insn (treg, GEN_INT (-info->total_size));
14734 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14735 in R11. It also clobbers R12, so beware! */
14737 /* Preserve CR2 for save_world prologues */
14739 sz += 32 - info->first_gp_reg_save;
14740 sz += 64 - info->first_fp_reg_save;
14741 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14742 p = rtvec_alloc (sz);
14744 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14745 gen_rtx_REG (SImode,
14746 LINK_REGISTER_REGNUM));
14747 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14748 gen_rtx_SYMBOL_REF (Pmode,
14750 /* We do floats first so that the instruction pattern matches
14752 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14754 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14755 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14756 GEN_INT (info->fp_save_offset
14757 + sp_offset + 8 * i));
14758 rtx mem = gen_frame_mem (DFmode, addr);
14760 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14762 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14764 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14765 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14766 GEN_INT (info->altivec_save_offset
14767 + sp_offset + 16 * i));
14768 rtx mem = gen_frame_mem (V4SImode, addr);
14770 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14772 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14774 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14775 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14776 GEN_INT (info->gp_save_offset
14777 + sp_offset + reg_size * i));
14778 rtx mem = gen_frame_mem (reg_mode, addr);
14780 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14784 /* CR register traditionally saved as CR2. */
14785 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14786 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14787 GEN_INT (info->cr_save_offset
14789 rtx mem = gen_frame_mem (reg_mode, addr);
14791 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14793 /* Explain about use of R0. */
14794 if (info->lr_save_p)
14796 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14797 GEN_INT (info->lr_save_offset
14799 rtx mem = gen_frame_mem (reg_mode, addr);
14801 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
14803 /* Explain what happens to the stack pointer. */
14805 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
14806 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
14809 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14810 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14811 treg, GEN_INT (-info->total_size));
14812 sp_offset = info->total_size;
14815 /* Save AltiVec registers if needed. */
14816 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14820 /* There should be a non inline version of this, for when we
14821 are saving lots of vector registers. */
14822 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14823 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14825 rtx areg, savereg, mem;
14828 offset = info->altivec_save_offset + sp_offset
14829 + 16 * (i - info->first_altivec_reg_save);
14831 savereg = gen_rtx_REG (V4SImode, i);
14833 areg = gen_rtx_REG (Pmode, 0);
14834 emit_move_insn (areg, GEN_INT (offset));
14836 /* AltiVec addressing mode is [reg+reg]. */
14837 mem = gen_frame_mem (V4SImode,
14838 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
14840 insn = emit_move_insn (mem, savereg);
14842 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14843 areg, GEN_INT (offset));
14847 /* VRSAVE is a bit vector representing which AltiVec registers
14848 are used. The OS uses this to determine which vector
14849 registers to save on a context switch. We need to save
14850 VRSAVE on the stack frame, add whatever AltiVec registers we
14851 used in this function, and do the corresponding magic in the
14854 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14855 && info->vrsave_mask != 0)
14857 rtx reg, mem, vrsave;
14860 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14861 as frame_reg_rtx and r11 as the static chain pointer for
14862 nested functions. */
14863 reg = gen_rtx_REG (SImode, 0);
14864 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14866 emit_insn (gen_get_vrsave_internal (reg));
14868 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14870 if (!WORLD_SAVE_P (info))
14873 offset = info->vrsave_save_offset + sp_offset;
14874 mem = gen_frame_mem (SImode,
14875 gen_rtx_PLUS (Pmode, frame_reg_rtx,
14876 GEN_INT (offset)));
14877 insn = emit_move_insn (mem, reg);
14880 /* Include the registers in the mask. */
14881 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14883 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14886 /* If we use the link register, get it into r0. */
14887 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14889 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14890 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14891 RTX_FRAME_RELATED_P (insn) = 1;
14894 /* If we need to save CR, put it into r12. */
14895 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14899 cr_save_rtx = gen_rtx_REG (SImode, 12);
14900 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14901 RTX_FRAME_RELATED_P (insn) = 1;
14902 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14903 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14904 But that's OK. All we have to do is specify that _one_ condition
14905 code register is saved in this stack slot. The thrower's epilogue
14906 will then restore all the call-saved registers.
14907 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14908 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14909 gen_rtx_REG (SImode, CR2_REGNO));
14910 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14915 /* Do any required saving of fpr's. If only one or two to save, do
14916 it ourselves. Otherwise, call function. */
14917 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14920 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14921 if ((regs_ever_live[info->first_fp_reg_save+i]
14922 && ! call_used_regs[info->first_fp_reg_save+i]))
14923 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14924 info->first_fp_reg_save + i,
14925 info->fp_save_offset + sp_offset + 8 * i,
14928 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14932 const char *alloc_rname;
14934 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14936 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14937 gen_rtx_REG (Pmode,
14938 LINK_REGISTER_REGNUM));
14939 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14940 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14941 alloc_rname = ggc_strdup (rname);
14942 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14943 gen_rtx_SYMBOL_REF (Pmode,
14945 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14947 rtx addr, reg, mem;
14948 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14949 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14950 GEN_INT (info->fp_save_offset
14951 + sp_offset + 8*i));
14952 mem = gen_frame_mem (DFmode, addr);
14954 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14956 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14957 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14958 NULL_RTX, NULL_RTX);
14961 /* Save GPRs. This is done as a PARALLEL if we are using
14962 the store-multiple instructions. */
14963 if (!WORLD_SAVE_P (info) && using_store_multiple)
14967 p = rtvec_alloc (32 - info->first_gp_reg_save);
14968 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14970 rtx addr, reg, mem;
14971 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14972 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14973 GEN_INT (info->gp_save_offset
14976 mem = gen_frame_mem (reg_mode, addr);
14978 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14980 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14981 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14982 NULL_RTX, NULL_RTX);
14984 else if (!WORLD_SAVE_P (info))
14987 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14988 if ((regs_ever_live[info->first_gp_reg_save + i]
14989 && (!call_used_regs[info->first_gp_reg_save + i]
14990 || (i + info->first_gp_reg_save
14991 == RS6000_PIC_OFFSET_TABLE_REGNUM
14992 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14993 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14994 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14995 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14997 rtx addr, reg, mem;
14998 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15000 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15002 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
15005 if (!SPE_CONST_OFFSET_OK (offset))
15007 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
15008 emit_move_insn (b, GEN_INT (offset));
15011 b = GEN_INT (offset);
15013 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
15014 mem = gen_frame_mem (V2SImode, addr);
15015 insn = emit_move_insn (mem, reg);
15017 if (GET_CODE (b) == CONST_INT)
15018 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15019 NULL_RTX, NULL_RTX);
15021 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15022 b, GEN_INT (offset));
15026 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15027 GEN_INT (info->gp_save_offset
15030 mem = gen_frame_mem (reg_mode, addr);
15032 insn = emit_move_insn (mem, reg);
15033 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15034 NULL_RTX, NULL_RTX);
15039 /* ??? There's no need to emit actual instructions here, but it's the
15040 easiest way to get the frame unwind information emitted. */
15041 if (current_function_calls_eh_return)
15043 unsigned int i, regno;
15045 /* In AIX ABI we need to pretend we save r2 here. */
15048 rtx addr, reg, mem;
15050 reg = gen_rtx_REG (reg_mode, 2);
15051 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15052 GEN_INT (sp_offset + 5 * reg_size));
15053 mem = gen_frame_mem (reg_mode, addr);
15055 insn = emit_move_insn (mem, reg);
15056 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15057 NULL_RTX, NULL_RTX);
15058 PATTERN (insn) = gen_blockage ();
15063 regno = EH_RETURN_DATA_REGNO (i);
15064 if (regno == INVALID_REGNUM)
15067 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
15068 info->ehrd_offset + sp_offset
15069 + reg_size * (int) i,
15074 /* Save lr if we used it. */
15075 if (!WORLD_SAVE_P (info) && info->lr_save_p)
15077 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15078 GEN_INT (info->lr_save_offset + sp_offset));
15079 rtx reg = gen_rtx_REG (Pmode, 0);
15080 rtx mem = gen_rtx_MEM (Pmode, addr);
15081 /* This should not be of frame_alias_set, because of
15082 __builtin_return_address. */
15084 insn = emit_move_insn (mem, reg);
15085 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15086 NULL_RTX, NULL_RTX);
15089 /* Save CR if we use any that must be preserved. */
15090 if (!WORLD_SAVE_P (info) && info->cr_save_p)
15092 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15093 GEN_INT (info->cr_save_offset + sp_offset));
15094 rtx mem = gen_frame_mem (SImode, addr);
15095 /* See the large comment above about why CR2_REGNO is used. */
15096 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
15098 /* If r12 was used to hold the original sp, copy cr into r0 now
15100 if (REGNO (frame_reg_rtx) == 12)
15104 cr_save_rtx = gen_rtx_REG (SImode, 0);
15105 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
15106 RTX_FRAME_RELATED_P (insn) = 1;
15107 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
15108 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15113 insn = emit_move_insn (mem, cr_save_rtx);
15115 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15116 NULL_RTX, NULL_RTX);
15119 /* Update stack and set back pointer unless this is V.4,
15120 for which it was done previously. */
15121 if (!WORLD_SAVE_P (info) && info->push_p
15122 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
15123 rs6000_emit_allocate_stack (info->total_size, FALSE);
15125 /* Set frame pointer, if needed. */
15126 if (frame_pointer_needed)
15128 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
15130 RTX_FRAME_RELATED_P (insn) = 1;
15133 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
15134 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
15135 || (DEFAULT_ABI == ABI_V4
15136 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
15137 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
15139 /* If emit_load_toc_table will use the link register, we need to save
15140 it. We use R12 for this purpose because emit_load_toc_table
15141 can use register 0. This allows us to use a plain 'blr' to return
15142 from the procedure more often. */
15143 int save_LR_around_toc_setup = (TARGET_ELF
15144 && DEFAULT_ABI != ABI_AIX
15146 && ! info->lr_save_p
15147 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
15148 if (save_LR_around_toc_setup)
15150 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
15152 insn = emit_move_insn (frame_ptr_rtx, lr);
15153 rs6000_maybe_dead (insn);
15154 RTX_FRAME_RELATED_P (insn) = 1;
15156 rs6000_emit_load_toc_table (TRUE);
15158 insn = emit_move_insn (lr, frame_ptr_rtx);
15159 rs6000_maybe_dead (insn);
15160 RTX_FRAME_RELATED_P (insn) = 1;
15163 rs6000_emit_load_toc_table (TRUE);
15167 if (DEFAULT_ABI == ABI_DARWIN
15168 && flag_pic && current_function_uses_pic_offset_table)
15170 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
15171 rtx src = machopic_function_base_sym ();
15173 /* Save and restore LR locally around this call (in R0). */
15174 if (!info->lr_save_p)
15175 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr));
15177 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (src)));
15179 insn = emit_move_insn (gen_rtx_REG (Pmode,
15180 RS6000_PIC_OFFSET_TABLE_REGNUM),
15182 rs6000_maybe_dead (insn);
15184 if (!info->lr_save_p)
15185 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0)));
15190 /* Write function prologue. */
15193 rs6000_output_function_prologue (FILE *file,
15194 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15196 rs6000_stack_t *info = rs6000_stack_info ();
15198 if (TARGET_DEBUG_STACK)
15199 debug_stack_info (info);
15201 /* Write .extern for any function we will call to save and restore
15203 if (info->first_fp_reg_save < 64
15204 && !FP_SAVE_INLINE (info->first_fp_reg_save))
15205 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
15206 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
15207 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
15208 RESTORE_FP_SUFFIX);
15210 /* Write .extern for AIX common mode routines, if needed. */
15211 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
15213 fputs ("\t.extern __mulh\n", file);
15214 fputs ("\t.extern __mull\n", file);
15215 fputs ("\t.extern __divss\n", file);
15216 fputs ("\t.extern __divus\n", file);
15217 fputs ("\t.extern __quoss\n", file);
15218 fputs ("\t.extern __quous\n", file);
15219 common_mode_defined = 1;
15222 if (! HAVE_prologue)
15226 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
15227 the "toplevel" insn chain. */
15228 emit_note (NOTE_INSN_DELETED);
15229 rs6000_emit_prologue ();
15230 emit_note (NOTE_INSN_DELETED);
15232 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15236 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15238 INSN_ADDRESSES_NEW (insn, addr);
15243 if (TARGET_DEBUG_STACK)
15244 debug_rtx_list (get_insns (), 100);
15245 final (get_insns (), file, FALSE);
15249 rs6000_pic_labelno++;
15252 /* Emit function epilogue as insns.
15254 At present, dwarf2out_frame_debug_expr doesn't understand
15255 register restores, so we don't bother setting RTX_FRAME_RELATED_P
15256 anywhere in the epilogue. Most of the insns below would in any case
15257 need special notes to explain where r11 is in relation to the stack. */
15260 rs6000_emit_epilogue (int sibcall)
15262 rs6000_stack_t *info;
15263 int restoring_FPRs_inline;
15264 int using_load_multiple;
15265 int using_mtcr_multiple;
15266 int use_backchain_to_restore_sp;
15268 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
15269 rtx frame_reg_rtx = sp_reg_rtx;
15270 enum machine_mode reg_mode = Pmode;
15271 int reg_size = TARGET_32BIT ? 4 : 8;
15274 info = rs6000_stack_info ();
15276 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15278 reg_mode = V2SImode;
15282 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
15283 && (!TARGET_SPE_ABI
15284 || info->spe_64bit_regs_used == 0)
15285 && info->first_gp_reg_save < 31
15286 && no_global_regs_above (info->first_gp_reg_save));
15287 restoring_FPRs_inline = (sibcall
15288 || current_function_calls_eh_return
15289 || info->first_fp_reg_save == 64
15290 || FP_SAVE_INLINE (info->first_fp_reg_save));
15291 use_backchain_to_restore_sp = (frame_pointer_needed
15292 || current_function_calls_alloca
15293 || info->total_size > 32767);
15294 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
15295 || rs6000_cpu == PROCESSOR_PPC603
15296 || rs6000_cpu == PROCESSOR_PPC750
15299 if (WORLD_SAVE_P (info))
15303 const char *alloc_rname;
15306 /* eh_rest_world_r10 will return to the location saved in the LR
15307 stack slot (which is not likely to be our caller.)
15308 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
15309 rest_world is similar, except any R10 parameter is ignored.
15310 The exception-handling stuff that was here in 2.95 is no
15311 longer necessary. */
15315 + 32 - info->first_gp_reg_save
15316 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
15317 + 63 + 1 - info->first_fp_reg_save);
15319 strcpy (rname, ((current_function_calls_eh_return) ?
15320 "*eh_rest_world_r10" : "*rest_world"));
15321 alloc_rname = ggc_strdup (rname);
15324 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
15325 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
15326 gen_rtx_REG (Pmode,
15327 LINK_REGISTER_REGNUM));
15329 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
15330 /* The instruction pattern requires a clobber here;
15331 it is shared with the restVEC helper. */
15333 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
15336 /* CR register traditionally saved as CR2. */
15337 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
15338 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15339 GEN_INT (info->cr_save_offset));
15340 rtx mem = gen_frame_mem (reg_mode, addr);
15342 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15345 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15347 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15348 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15349 GEN_INT (info->gp_save_offset
15351 rtx mem = gen_frame_mem (reg_mode, addr);
15353 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15355 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
15357 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
15358 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15359 GEN_INT (info->altivec_save_offset
15361 rtx mem = gen_frame_mem (V4SImode, addr);
15363 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15365 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
15367 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15368 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15369 GEN_INT (info->fp_save_offset
15371 rtx mem = gen_frame_mem (DFmode, addr);
15373 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15376 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
15378 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
15380 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
15382 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
15384 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
15385 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15390 /* If we have a frame pointer, a call to alloca, or a large stack
15391 frame, restore the old stack pointer using the backchain. Otherwise,
15392 we know what size to update it with. */
15393 if (use_backchain_to_restore_sp)
15395 /* Under V.4, don't reset the stack pointer until after we're done
15396 loading the saved registers. */
15397 if (DEFAULT_ABI == ABI_V4)
15398 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
15400 emit_move_insn (frame_reg_rtx,
15401 gen_rtx_MEM (Pmode, sp_reg_rtx));
15403 else if (info->push_p)
15405 if (DEFAULT_ABI == ABI_V4
15406 || current_function_calls_eh_return)
15407 sp_offset = info->total_size;
15410 emit_insn (TARGET_32BIT
15411 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15412 GEN_INT (info->total_size))
15413 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15414 GEN_INT (info->total_size)));
15418 /* Restore AltiVec registers if needed. */
15419 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15423 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15424 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15426 rtx addr, areg, mem;
15428 areg = gen_rtx_REG (Pmode, 0);
15430 (areg, GEN_INT (info->altivec_save_offset
15432 + 16 * (i - info->first_altivec_reg_save)));
15434 /* AltiVec addressing mode is [reg+reg]. */
15435 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
15436 mem = gen_frame_mem (V4SImode, addr);
15438 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
15442 /* Restore VRSAVE if needed. */
15443 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15444 && info->vrsave_mask != 0)
15446 rtx addr, mem, reg;
15448 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15449 GEN_INT (info->vrsave_save_offset + sp_offset));
15450 mem = gen_frame_mem (SImode, addr);
15451 reg = gen_rtx_REG (SImode, 12);
15452 emit_move_insn (reg, mem);
15454 emit_insn (generate_set_vrsave (reg, info, 1));
15457 /* Get the old lr if we saved it. */
15458 if (info->lr_save_p)
15460 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
15461 info->lr_save_offset + sp_offset);
15463 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
15466 /* Get the old cr if we saved it. */
15467 if (info->cr_save_p)
15469 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15470 GEN_INT (info->cr_save_offset + sp_offset));
15471 rtx mem = gen_frame_mem (SImode, addr);
15473 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
15476 /* Set LR here to try to overlap restores below. */
15477 if (info->lr_save_p)
15478 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
15479 gen_rtx_REG (Pmode, 0));
15481 /* Load exception handler data registers, if needed. */
15482 if (current_function_calls_eh_return)
15484 unsigned int i, regno;
15488 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15489 GEN_INT (sp_offset + 5 * reg_size));
15490 rtx mem = gen_frame_mem (reg_mode, addr);
15492 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
15499 regno = EH_RETURN_DATA_REGNO (i);
15500 if (regno == INVALID_REGNUM)
15503 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
15504 info->ehrd_offset + sp_offset
15505 + reg_size * (int) i);
15507 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
15511 /* Restore GPRs. This is done as a PARALLEL if we are using
15512 the load-multiple instructions. */
15513 if (using_load_multiple)
15516 p = rtvec_alloc (32 - info->first_gp_reg_save);
15517 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15519 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15520 GEN_INT (info->gp_save_offset
15523 rtx mem = gen_frame_mem (reg_mode, addr);
15526 gen_rtx_SET (VOIDmode,
15527 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15530 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15533 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15534 if ((regs_ever_live[info->first_gp_reg_save + i]
15535 && (!call_used_regs[info->first_gp_reg_save + i]
15536 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
15537 && TARGET_TOC && TARGET_MINIMAL_TOC)))
15538 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
15539 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
15540 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
15542 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15543 GEN_INT (info->gp_save_offset
15546 rtx mem = gen_frame_mem (reg_mode, addr);
15548 /* Restore 64-bit quantities for SPE. */
15549 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15551 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
15554 if (!SPE_CONST_OFFSET_OK (offset))
15556 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
15557 emit_move_insn (b, GEN_INT (offset));
15560 b = GEN_INT (offset);
15562 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
15563 mem = gen_frame_mem (V2SImode, addr);
15566 emit_move_insn (gen_rtx_REG (reg_mode,
15567 info->first_gp_reg_save + i), mem);
15570 /* Restore fpr's if we need to do it without calling a function. */
15571 if (restoring_FPRs_inline)
15572 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15573 if ((regs_ever_live[info->first_fp_reg_save+i]
15574 && ! call_used_regs[info->first_fp_reg_save+i]))
15577 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15578 GEN_INT (info->fp_save_offset
15581 mem = gen_frame_mem (DFmode, addr);
15583 emit_move_insn (gen_rtx_REG (DFmode,
15584 info->first_fp_reg_save + i),
15588 /* If we saved cr, restore it here. Just those that were used. */
15589 if (info->cr_save_p)
15591 rtx r12_rtx = gen_rtx_REG (SImode, 12);
15594 if (using_mtcr_multiple)
15596 for (i = 0; i < 8; i++)
15597 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15599 gcc_assert (count);
15602 if (using_mtcr_multiple && count > 1)
15607 p = rtvec_alloc (count);
15610 for (i = 0; i < 8; i++)
15611 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15613 rtvec r = rtvec_alloc (2);
15614 RTVEC_ELT (r, 0) = r12_rtx;
15615 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
15616 RTVEC_ELT (p, ndx) =
15617 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
15618 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
15621 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15622 gcc_assert (ndx == count);
15625 for (i = 0; i < 8; i++)
15626 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15628 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
15634 /* If this is V.4, unwind the stack pointer after all of the loads
15636 if (frame_reg_rtx != sp_reg_rtx)
15638 /* This blockage is needed so that sched doesn't decide to move
15639 the sp change before the register restores. */
15640 rs6000_emit_stack_tie ();
15641 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15643 else if (sp_offset != 0)
15644 emit_insn (TARGET_32BIT
15645 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15646 GEN_INT (sp_offset))
15647 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15648 GEN_INT (sp_offset)));
15650 if (current_function_calls_eh_return)
15652 rtx sa = EH_RETURN_STACKADJ_RTX;
15653 emit_insn (TARGET_32BIT
15654 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
15655 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
15661 if (! restoring_FPRs_inline)
15662 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
15664 p = rtvec_alloc (2);
15666 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15667 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15668 gen_rtx_REG (Pmode,
15669 LINK_REGISTER_REGNUM));
15671 /* If we have to restore more than two FP registers, branch to the
15672 restore function. It will return to our caller. */
15673 if (! restoring_FPRs_inline)
15677 const char *alloc_rname;
15679 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15680 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15681 alloc_rname = ggc_strdup (rname);
15682 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15683 gen_rtx_SYMBOL_REF (Pmode,
15686 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15689 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15690 GEN_INT (info->fp_save_offset + 8*i));
15691 mem = gen_frame_mem (DFmode, addr);
15693 RTVEC_ELT (p, i+3) =
15694 gen_rtx_SET (VOIDmode,
15695 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15700 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15704 /* Write function epilogue. */
15707 rs6000_output_function_epilogue (FILE *file,
15708 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15710 if (! HAVE_epilogue)
15712 rtx insn = get_last_insn ();
15713 /* If the last insn was a BARRIER, we don't have to write anything except
15714 the trace table. */
15715 if (GET_CODE (insn) == NOTE)
15716 insn = prev_nonnote_insn (insn);
15717 if (insn == 0 || GET_CODE (insn) != BARRIER)
15719 /* This is slightly ugly, but at least we don't have two
15720 copies of the epilogue-emitting code. */
15723 /* A NOTE_INSN_DELETED is supposed to be at the start
15724 and end of the "toplevel" insn chain. */
15725 emit_note (NOTE_INSN_DELETED);
15726 rs6000_emit_epilogue (FALSE);
15727 emit_note (NOTE_INSN_DELETED);
15729 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15733 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15735 INSN_ADDRESSES_NEW (insn, addr);
15740 if (TARGET_DEBUG_STACK)
15741 debug_rtx_list (get_insns (), 100);
15742 final (get_insns (), file, FALSE);
15748 macho_branch_islands ();
15749 /* Mach-O doesn't support labels at the end of objects, so if
15750 it looks like we might want one, insert a NOP. */
15752 rtx insn = get_last_insn ();
15755 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
15756 insn = PREV_INSN (insn);
15760 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
15761 fputs ("\tnop\n", file);
15765 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15768 We don't output a traceback table if -finhibit-size-directive was
15769 used. The documentation for -finhibit-size-directive reads
15770 ``don't output a @code{.size} assembler directive, or anything
15771 else that would cause trouble if the function is split in the
15772 middle, and the two halves are placed at locations far apart in
15773 memory.'' The traceback table has this property, since it
15774 includes the offset from the start of the function to the
15775 traceback table itself.
15777 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15778 different traceback table. */
15779 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15780 && rs6000_traceback != traceback_none && !current_function_is_thunk)
15782 const char *fname = NULL;
15783 const char *language_string = lang_hooks.name;
15784 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15786 int optional_tbtab;
15787 rs6000_stack_t *info = rs6000_stack_info ();
15789 if (rs6000_traceback == traceback_full)
15790 optional_tbtab = 1;
15791 else if (rs6000_traceback == traceback_part)
15792 optional_tbtab = 0;
15794 optional_tbtab = !optimize_size && !TARGET_ELF;
15796 if (optional_tbtab)
15798 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15799 while (*fname == '.') /* V.4 encodes . in the name */
15802 /* Need label immediately before tbtab, so we can compute
15803 its offset from the function start. */
15804 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15805 ASM_OUTPUT_LABEL (file, fname);
15808 /* The .tbtab pseudo-op can only be used for the first eight
15809 expressions, since it can't handle the possibly variable
15810 length fields that follow. However, if you omit the optional
15811 fields, the assembler outputs zeros for all optional fields
15812 anyways, giving each variable length field is minimum length
15813 (as defined in sys/debug.h). Thus we can not use the .tbtab
15814 pseudo-op at all. */
15816 /* An all-zero word flags the start of the tbtab, for debuggers
15817 that have to find it by searching forward from the entry
15818 point or from the current pc. */
15819 fputs ("\t.long 0\n", file);
15821 /* Tbtab format type. Use format type 0. */
15822 fputs ("\t.byte 0,", file);
15824 /* Language type. Unfortunately, there does not seem to be any
15825 official way to discover the language being compiled, so we
15826 use language_string.
15827 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15828 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
15829 a number, so for now use 9. */
15830 if (! strcmp (language_string, "GNU C"))
15832 else if (! strcmp (language_string, "GNU F77")
15833 || ! strcmp (language_string, "GNU F95"))
15835 else if (! strcmp (language_string, "GNU Pascal"))
15837 else if (! strcmp (language_string, "GNU Ada"))
15839 else if (! strcmp (language_string, "GNU C++")
15840 || ! strcmp (language_string, "GNU Objective-C++"))
15842 else if (! strcmp (language_string, "GNU Java"))
15844 else if (! strcmp (language_string, "GNU Objective-C"))
15847 gcc_unreachable ();
15848 fprintf (file, "%d,", i);
15850 /* 8 single bit fields: global linkage (not set for C extern linkage,
15851 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15852 from start of procedure stored in tbtab, internal function, function
15853 has controlled storage, function has no toc, function uses fp,
15854 function logs/aborts fp operations. */
15855 /* Assume that fp operations are used if any fp reg must be saved. */
15856 fprintf (file, "%d,",
15857 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15859 /* 6 bitfields: function is interrupt handler, name present in
15860 proc table, function calls alloca, on condition directives
15861 (controls stack walks, 3 bits), saves condition reg, saves
15863 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15864 set up as a frame pointer, even when there is no alloca call. */
15865 fprintf (file, "%d,",
15866 ((optional_tbtab << 6)
15867 | ((optional_tbtab & frame_pointer_needed) << 5)
15868 | (info->cr_save_p << 1)
15869 | (info->lr_save_p)));
15871 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15873 fprintf (file, "%d,",
15874 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15876 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15877 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15879 if (optional_tbtab)
15881 /* Compute the parameter info from the function decl argument
15884 int next_parm_info_bit = 31;
15886 for (decl = DECL_ARGUMENTS (current_function_decl);
15887 decl; decl = TREE_CHAIN (decl))
15889 rtx parameter = DECL_INCOMING_RTL (decl);
15890 enum machine_mode mode = GET_MODE (parameter);
15892 if (GET_CODE (parameter) == REG)
15894 if (SCALAR_FLOAT_MODE_P (mode))
15914 gcc_unreachable ();
15917 /* If only one bit will fit, don't or in this entry. */
15918 if (next_parm_info_bit > 0)
15919 parm_info |= (bits << (next_parm_info_bit - 1));
15920 next_parm_info_bit -= 2;
15924 fixed_parms += ((GET_MODE_SIZE (mode)
15925 + (UNITS_PER_WORD - 1))
15927 next_parm_info_bit -= 1;
15933 /* Number of fixed point parameters. */
15934 /* This is actually the number of words of fixed point parameters; thus
15935 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15936 fprintf (file, "%d,", fixed_parms);
15938 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15940 /* This is actually the number of fp registers that hold parameters;
15941 and thus the maximum value is 13. */
15942 /* Set parameters on stack bit if parameters are not in their original
15943 registers, regardless of whether they are on the stack? Xlc
15944 seems to set the bit when not optimizing. */
15945 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15947 if (! optional_tbtab)
15950 /* Optional fields follow. Some are variable length. */
15952 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15953 11 double float. */
15954 /* There is an entry for each parameter in a register, in the order that
15955 they occur in the parameter list. Any intervening arguments on the
15956 stack are ignored. If the list overflows a long (max possible length
15957 34 bits) then completely leave off all elements that don't fit. */
15958 /* Only emit this long if there was at least one parameter. */
15959 if (fixed_parms || float_parms)
15960 fprintf (file, "\t.long %d\n", parm_info);
15962 /* Offset from start of code to tb table. */
15963 fputs ("\t.long ", file);
15964 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15966 RS6000_OUTPUT_BASENAME (file, fname);
15968 assemble_name (file, fname);
15970 rs6000_output_function_entry (file, fname);
15973 /* Interrupt handler mask. */
15974 /* Omit this long, since we never set the interrupt handler bit
15977 /* Number of CTL (controlled storage) anchors. */
15978 /* Omit this long, since the has_ctl bit is never set above. */
15980 /* Displacement into stack of each CTL anchor. */
15981 /* Omit this list of longs, because there are no CTL anchors. */
15983 /* Length of function name. */
15986 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15988 /* Function name. */
15989 assemble_string (fname, strlen (fname));
15991 /* Register for alloca automatic storage; this is always reg 31.
15992 Only emit this if the alloca bit was set above. */
15993 if (frame_pointer_needed)
15994 fputs ("\t.byte 31\n", file);
15996 fputs ("\t.align 2\n", file);
16000 /* A C compound statement that outputs the assembler code for a thunk
16001 function, used to implement C++ virtual function calls with
16002 multiple inheritance. The thunk acts as a wrapper around a virtual
16003 function, adjusting the implicit object parameter before handing
16004 control off to the real function.
16006 First, emit code to add the integer DELTA to the location that
16007 contains the incoming first argument. Assume that this argument
16008 contains a pointer, and is the one used to pass the `this' pointer
16009 in C++. This is the incoming argument *before* the function
16010 prologue, e.g. `%o0' on a sparc. The addition must preserve the
16011 values of all other incoming arguments.
16013 After the addition, emit code to jump to FUNCTION, which is a
16014 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
16015 not touch the return address. Hence returning from FUNCTION will
16016 return to whoever called the current `thunk'.
16018 The effect must be as if FUNCTION had been called directly with the
16019 adjusted first argument. This macro is responsible for emitting
16020 all of the code for a thunk function; output_function_prologue()
16021 and output_function_epilogue() are not invoked.
16023 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
16024 been extracted from it.) It might possibly be useful on some
16025 targets, but probably not.
16027 If you do not define this macro, the target-independent code in the
16028 C++ frontend will generate a less efficient heavyweight thunk that
16029 calls FUNCTION instead of jumping to it. The generic approach does
16030 not support varargs. */
16033 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16034 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16037 rtx this, insn, funexp;
16039 reload_completed = 1;
16040 epilogue_completed = 1;
16041 no_new_pseudos = 1;
16042 reset_block_changes ();
16044 /* Mark the end of the (empty) prologue. */
16045 emit_note (NOTE_INSN_PROLOGUE_END);
16047 /* Find the "this" pointer. If the function returns a structure,
16048 the structure return pointer is in r3. */
16049 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16050 this = gen_rtx_REG (Pmode, 4);
16052 this = gen_rtx_REG (Pmode, 3);
16054 /* Apply the constant offset, if required. */
16057 rtx delta_rtx = GEN_INT (delta);
16058 emit_insn (TARGET_32BIT
16059 ? gen_addsi3 (this, this, delta_rtx)
16060 : gen_adddi3 (this, this, delta_rtx));
16063 /* Apply the offset from the vtable, if required. */
16066 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
16067 rtx tmp = gen_rtx_REG (Pmode, 12);
16069 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
16070 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
16072 emit_insn (TARGET_32BIT
16073 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
16074 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
16075 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
16079 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
16081 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
16083 emit_insn (TARGET_32BIT
16084 ? gen_addsi3 (this, this, tmp)
16085 : gen_adddi3 (this, this, tmp));
16088 /* Generate a tail call to the target function. */
16089 if (!TREE_USED (function))
16091 assemble_external (function);
16092 TREE_USED (function) = 1;
16094 funexp = XEXP (DECL_RTL (function), 0);
16095 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
16098 if (MACHOPIC_INDIRECT)
16099 funexp = machopic_indirect_call_target (funexp);
16102 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
16103 generate sibcall RTL explicitly. */
16104 insn = emit_call_insn (
16105 gen_rtx_PARALLEL (VOIDmode,
16107 gen_rtx_CALL (VOIDmode,
16108 funexp, const0_rtx),
16109 gen_rtx_USE (VOIDmode, const0_rtx),
16110 gen_rtx_USE (VOIDmode,
16111 gen_rtx_REG (SImode,
16112 LINK_REGISTER_REGNUM)),
16113 gen_rtx_RETURN (VOIDmode))));
16114 SIBLING_CALL_P (insn) = 1;
16117 /* Run just enough of rest_of_compilation to get the insns emitted.
16118 There's not really enough bulk here to make other passes such as
16119 instruction scheduling worth while. Note that use_thunk calls
16120 assemble_start_function and assemble_end_function. */
16121 insn = get_insns ();
16122 insn_locators_initialize ();
16123 shorten_branches (insn);
16124 final_start_function (insn, file, 1);
16125 final (insn, file, 1);
16126 final_end_function ();
16128 reload_completed = 0;
16129 epilogue_completed = 0;
16130 no_new_pseudos = 0;
16133 /* A quick summary of the various types of 'constant-pool tables'
16136 Target Flags Name One table per
16137 AIX (none) AIX TOC object file
16138 AIX -mfull-toc AIX TOC object file
16139 AIX -mminimal-toc AIX minimal TOC translation unit
16140 SVR4/EABI (none) SVR4 SDATA object file
16141 SVR4/EABI -fpic SVR4 pic object file
16142 SVR4/EABI -fPIC SVR4 PIC translation unit
16143 SVR4/EABI -mrelocatable EABI TOC function
16144 SVR4/EABI -maix AIX TOC object file
16145 SVR4/EABI -maix -mminimal-toc
16146 AIX minimal TOC translation unit
16148 Name Reg. Set by entries contains:
16149 made by addrs? fp? sum?
16151 AIX TOC 2 crt0 as Y option option
16152 AIX minimal TOC 30 prolog gcc Y Y option
16153 SVR4 SDATA 13 crt0 gcc N Y N
16154 SVR4 pic 30 prolog ld Y not yet N
16155 SVR4 PIC 30 prolog gcc Y option option
16156 EABI TOC 30 prolog gcc Y option option
16160 /* Hash functions for the hash table. */
16163 rs6000_hash_constant (rtx k)
16165 enum rtx_code code = GET_CODE (k);
16166 enum machine_mode mode = GET_MODE (k);
16167 unsigned result = (code << 3) ^ mode;
16168 const char *format;
16171 format = GET_RTX_FORMAT (code);
16172 flen = strlen (format);
16178 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
16181 if (mode != VOIDmode)
16182 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
16194 for (; fidx < flen; fidx++)
16195 switch (format[fidx])
16200 const char *str = XSTR (k, fidx);
16201 len = strlen (str);
16202 result = result * 613 + len;
16203 for (i = 0; i < len; i++)
16204 result = result * 613 + (unsigned) str[i];
16209 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
16213 result = result * 613 + (unsigned) XINT (k, fidx);
16216 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
16217 result = result * 613 + (unsigned) XWINT (k, fidx);
16221 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
16222 result = result * 613 + (unsigned) (XWINT (k, fidx)
16229 gcc_unreachable ();
16236 toc_hash_function (const void *hash_entry)
16238 const struct toc_hash_struct *thc =
16239 (const struct toc_hash_struct *) hash_entry;
16240 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
16243 /* Compare H1 and H2 for equivalence. */
16246 toc_hash_eq (const void *h1, const void *h2)
16248 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
16249 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
16251 if (((const struct toc_hash_struct *) h1)->key_mode
16252 != ((const struct toc_hash_struct *) h2)->key_mode)
16255 return rtx_equal_p (r1, r2);
16258 /* These are the names given by the C++ front-end to vtables, and
16259 vtable-like objects. Ideally, this logic should not be here;
16260 instead, there should be some programmatic way of inquiring as
16261 to whether or not an object is a vtable. */
16263 #define VTABLE_NAME_P(NAME) \
16264 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
16265 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
16266 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
16267 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
16268 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
16271 rs6000_output_symbol_ref (FILE *file, rtx x)
16273 /* Currently C++ toc references to vtables can be emitted before it
16274 is decided whether the vtable is public or private. If this is
16275 the case, then the linker will eventually complain that there is
16276 a reference to an unknown section. Thus, for vtables only,
16277 we emit the TOC reference to reference the symbol and not the
16279 const char *name = XSTR (x, 0);
16281 if (VTABLE_NAME_P (name))
16283 RS6000_OUTPUT_BASENAME (file, name);
16286 assemble_name (file, name);
16289 /* Output a TOC entry. We derive the entry name from what is being
16293 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
16296 const char *name = buf;
16297 const char *real_name;
16299 HOST_WIDE_INT offset = 0;
16301 gcc_assert (!TARGET_NO_TOC);
16303 /* When the linker won't eliminate them, don't output duplicate
16304 TOC entries (this happens on AIX if there is any kind of TOC,
16305 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
16307 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
16309 struct toc_hash_struct *h;
16312 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
16313 time because GGC is not initialized at that point. */
16314 if (toc_hash_table == NULL)
16315 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
16316 toc_hash_eq, NULL);
16318 h = ggc_alloc (sizeof (*h));
16320 h->key_mode = mode;
16321 h->labelno = labelno;
16323 found = htab_find_slot (toc_hash_table, h, 1);
16324 if (*found == NULL)
16326 else /* This is indeed a duplicate.
16327 Set this label equal to that label. */
16329 fputs ("\t.set ", file);
16330 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16331 fprintf (file, "%d,", labelno);
16332 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16333 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
16339 /* If we're going to put a double constant in the TOC, make sure it's
16340 aligned properly when strict alignment is on. */
16341 if (GET_CODE (x) == CONST_DOUBLE
16342 && STRICT_ALIGNMENT
16343 && GET_MODE_BITSIZE (mode) >= 64
16344 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
16345 ASM_OUTPUT_ALIGN (file, 3);
16348 (*targetm.asm_out.internal_label) (file, "LC", labelno);
16350 /* Handle FP constants specially. Note that if we have a minimal
16351 TOC, things we put here aren't actually in the TOC, so we can allow
16353 if (GET_CODE (x) == CONST_DOUBLE &&
16354 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
16356 REAL_VALUE_TYPE rv;
16359 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16360 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16361 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
16363 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
16367 if (TARGET_MINIMAL_TOC)
16368 fputs (DOUBLE_INT_ASM_OP, file);
16370 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16371 k[0] & 0xffffffff, k[1] & 0xffffffff,
16372 k[2] & 0xffffffff, k[3] & 0xffffffff);
16373 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
16374 k[0] & 0xffffffff, k[1] & 0xffffffff,
16375 k[2] & 0xffffffff, k[3] & 0xffffffff);
16380 if (TARGET_MINIMAL_TOC)
16381 fputs ("\t.long ", file);
16383 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16384 k[0] & 0xffffffff, k[1] & 0xffffffff,
16385 k[2] & 0xffffffff, k[3] & 0xffffffff);
16386 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
16387 k[0] & 0xffffffff, k[1] & 0xffffffff,
16388 k[2] & 0xffffffff, k[3] & 0xffffffff);
16392 else if (GET_CODE (x) == CONST_DOUBLE &&
16393 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
16395 REAL_VALUE_TYPE rv;
16398 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16400 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16401 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
16403 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
16407 if (TARGET_MINIMAL_TOC)
16408 fputs (DOUBLE_INT_ASM_OP, file);
16410 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16411 k[0] & 0xffffffff, k[1] & 0xffffffff);
16412 fprintf (file, "0x%lx%08lx\n",
16413 k[0] & 0xffffffff, k[1] & 0xffffffff);
16418 if (TARGET_MINIMAL_TOC)
16419 fputs ("\t.long ", file);
16421 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16422 k[0] & 0xffffffff, k[1] & 0xffffffff);
16423 fprintf (file, "0x%lx,0x%lx\n",
16424 k[0] & 0xffffffff, k[1] & 0xffffffff);
16428 else if (GET_CODE (x) == CONST_DOUBLE &&
16429 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
16431 REAL_VALUE_TYPE rv;
16434 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16435 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16436 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
16438 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
16442 if (TARGET_MINIMAL_TOC)
16443 fputs (DOUBLE_INT_ASM_OP, file);
16445 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16446 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
16451 if (TARGET_MINIMAL_TOC)
16452 fputs ("\t.long ", file);
16454 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16455 fprintf (file, "0x%lx\n", l & 0xffffffff);
16459 else if (GET_MODE (x) == VOIDmode
16460 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
16462 unsigned HOST_WIDE_INT low;
16463 HOST_WIDE_INT high;
16465 if (GET_CODE (x) == CONST_DOUBLE)
16467 low = CONST_DOUBLE_LOW (x);
16468 high = CONST_DOUBLE_HIGH (x);
16471 #if HOST_BITS_PER_WIDE_INT == 32
16474 high = (low & 0x80000000) ? ~0 : 0;
16478 low = INTVAL (x) & 0xffffffff;
16479 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
16483 /* TOC entries are always Pmode-sized, but since this
16484 is a bigendian machine then if we're putting smaller
16485 integer constants in the TOC we have to pad them.
16486 (This is still a win over putting the constants in
16487 a separate constant pool, because then we'd have
16488 to have both a TOC entry _and_ the actual constant.)
16490 For a 32-bit target, CONST_INT values are loaded and shifted
16491 entirely within `low' and can be stored in one TOC entry. */
16493 /* It would be easy to make this work, but it doesn't now. */
16494 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
16496 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
16498 #if HOST_BITS_PER_WIDE_INT == 32
16499 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
16500 POINTER_SIZE, &low, &high, 0);
16503 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
16504 high = (HOST_WIDE_INT) low >> 32;
16511 if (TARGET_MINIMAL_TOC)
16512 fputs (DOUBLE_INT_ASM_OP, file);
16514 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16515 (long) high & 0xffffffff, (long) low & 0xffffffff);
16516 fprintf (file, "0x%lx%08lx\n",
16517 (long) high & 0xffffffff, (long) low & 0xffffffff);
16522 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
16524 if (TARGET_MINIMAL_TOC)
16525 fputs ("\t.long ", file);
16527 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16528 (long) high & 0xffffffff, (long) low & 0xffffffff);
16529 fprintf (file, "0x%lx,0x%lx\n",
16530 (long) high & 0xffffffff, (long) low & 0xffffffff);
16534 if (TARGET_MINIMAL_TOC)
16535 fputs ("\t.long ", file);
16537 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
16538 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
16544 if (GET_CODE (x) == CONST)
16546 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
16548 base = XEXP (XEXP (x, 0), 0);
16549 offset = INTVAL (XEXP (XEXP (x, 0), 1));
16552 switch (GET_CODE (base))
16555 name = XSTR (base, 0);
16559 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
16560 CODE_LABEL_NUMBER (XEXP (base, 0)));
16564 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
16568 gcc_unreachable ();
16571 real_name = (*targetm.strip_name_encoding) (name);
16572 if (TARGET_MINIMAL_TOC)
16573 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
16576 fprintf (file, "\t.tc %s", real_name);
16579 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
16581 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
16583 fputs ("[TC],", file);
16586 /* Currently C++ toc references to vtables can be emitted before it
16587 is decided whether the vtable is public or private. If this is
16588 the case, then the linker will eventually complain that there is
16589 a TOC reference to an unknown section. Thus, for vtables only,
16590 we emit the TOC reference to reference the symbol and not the
16592 if (VTABLE_NAME_P (name))
16594 RS6000_OUTPUT_BASENAME (file, name);
16596 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16597 else if (offset > 0)
16598 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
16601 output_addr_const (file, x);
16605 /* Output an assembler pseudo-op to write an ASCII string of N characters
16606 starting at P to FILE.
16608 On the RS/6000, we have to do this using the .byte operation and
16609 write out special characters outside the quoted string.
16610 Also, the assembler is broken; very long strings are truncated,
16611 so we must artificially break them up early. */
16614 output_ascii (FILE *file, const char *p, int n)
16617 int i, count_string;
16618 const char *for_string = "\t.byte \"";
16619 const char *for_decimal = "\t.byte ";
16620 const char *to_close = NULL;
16623 for (i = 0; i < n; i++)
16626 if (c >= ' ' && c < 0177)
16629 fputs (for_string, file);
16632 /* Write two quotes to get one. */
16640 for_decimal = "\"\n\t.byte ";
16644 if (count_string >= 512)
16646 fputs (to_close, file);
16648 for_string = "\t.byte \"";
16649 for_decimal = "\t.byte ";
16657 fputs (for_decimal, file);
16658 fprintf (file, "%d", c);
16660 for_string = "\n\t.byte \"";
16661 for_decimal = ", ";
16667 /* Now close the string if we have written one. Then end the line. */
16669 fputs (to_close, file);
16672 /* Generate a unique section name for FILENAME for a section type
16673 represented by SECTION_DESC. Output goes into BUF.
16675 SECTION_DESC can be any string, as long as it is different for each
16676 possible section type.
16678 We name the section in the same manner as xlc. The name begins with an
16679 underscore followed by the filename (after stripping any leading directory
16680 names) with the last period replaced by the string SECTION_DESC. If
16681 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16685 rs6000_gen_section_name (char **buf, const char *filename,
16686 const char *section_desc)
16688 const char *q, *after_last_slash, *last_period = 0;
16692 after_last_slash = filename;
16693 for (q = filename; *q; q++)
16696 after_last_slash = q + 1;
16697 else if (*q == '.')
16701 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16702 *buf = (char *) xmalloc (len);
16707 for (q = after_last_slash; *q; q++)
16709 if (q == last_period)
16711 strcpy (p, section_desc);
16712 p += strlen (section_desc);
16716 else if (ISALNUM (*q))
16720 if (last_period == 0)
16721 strcpy (p, section_desc);
16726 /* Emit profile function. */
16729 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16731 /* Non-standard profiling for kernels, which just saves LR then calls
16732 _mcount without worrying about arg saves. The idea is to change
16733 the function prologue as little as possible as it isn't easy to
16734 account for arg save/restore code added just for _mcount. */
16735 if (TARGET_PROFILE_KERNEL)
16738 if (DEFAULT_ABI == ABI_AIX)
16740 #ifndef NO_PROFILE_COUNTERS
16741 # define NO_PROFILE_COUNTERS 0
16743 if (NO_PROFILE_COUNTERS)
16744 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16748 const char *label_name;
16751 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16752 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16753 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16755 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16759 else if (DEFAULT_ABI == ABI_DARWIN)
16761 const char *mcount_name = RS6000_MCOUNT;
16762 int caller_addr_regno = LINK_REGISTER_REGNUM;
16764 /* Be conservative and always set this, at least for now. */
16765 current_function_uses_pic_offset_table = 1;
16768 /* For PIC code, set up a stub and collect the caller's address
16769 from r0, which is where the prologue puts it. */
16770 if (MACHOPIC_INDIRECT
16771 && current_function_uses_pic_offset_table)
16772 caller_addr_regno = 0;
16774 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16776 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16780 /* Write function profiler code. */
16783 output_function_profiler (FILE *file, int labelno)
16787 switch (DEFAULT_ABI)
16790 gcc_unreachable ();
16795 warning (0, "no profiling of 64-bit code for this ABI");
16798 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16799 fprintf (file, "\tmflr %s\n", reg_names[0]);
16800 if (NO_PROFILE_COUNTERS)
16802 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16803 reg_names[0], reg_names[1]);
16805 else if (TARGET_SECURE_PLT && flag_pic)
16807 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16808 reg_names[0], reg_names[1]);
16809 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16810 asm_fprintf (file, "\t{cau|addis} %s,%s,",
16811 reg_names[12], reg_names[12]);
16812 assemble_name (file, buf);
16813 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
16814 assemble_name (file, buf);
16815 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
16817 else if (flag_pic == 1)
16819 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16820 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16821 reg_names[0], reg_names[1]);
16822 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16823 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16824 assemble_name (file, buf);
16825 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16827 else if (flag_pic > 1)
16829 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16830 reg_names[0], reg_names[1]);
16831 /* Now, we need to get the address of the label. */
16832 fputs ("\tbcl 20,31,1f\n\t.long ", file);
16833 assemble_name (file, buf);
16834 fputs ("-.\n1:", file);
16835 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16836 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16837 reg_names[0], reg_names[11]);
16838 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16839 reg_names[0], reg_names[0], reg_names[11]);
16843 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16844 assemble_name (file, buf);
16845 fputs ("@ha\n", file);
16846 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16847 reg_names[0], reg_names[1]);
16848 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16849 assemble_name (file, buf);
16850 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16853 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16854 fprintf (file, "\tbl %s%s\n",
16855 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16860 if (!TARGET_PROFILE_KERNEL)
16862 /* Don't do anything, done in output_profile_hook (). */
16866 gcc_assert (!TARGET_32BIT);
16868 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16869 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16871 if (cfun->static_chain_decl != NULL)
16873 asm_fprintf (file, "\tstd %s,24(%s)\n",
16874 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16875 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16876 asm_fprintf (file, "\tld %s,24(%s)\n",
16877 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16880 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16888 /* The following variable value is the last issued insn. */
16890 static rtx last_scheduled_insn;
16892 /* The following variable helps to balance issuing of load and
16893 store instructions */
16895 static int load_store_pendulum;
16897 /* Power4 load update and store update instructions are cracked into a
16898 load or store and an integer insn which are executed in the same cycle.
16899 Branches have their own dispatch slot which does not count against the
16900 GCC issue rate, but it changes the program flow so there are no other
16901 instructions to issue in this cycle. */
16904 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16905 int verbose ATTRIBUTE_UNUSED,
16906 rtx insn, int more)
16908 last_scheduled_insn = insn;
16909 if (GET_CODE (PATTERN (insn)) == USE
16910 || GET_CODE (PATTERN (insn)) == CLOBBER)
16912 cached_can_issue_more = more;
16913 return cached_can_issue_more;
16916 if (insn_terminates_group_p (insn, current_group))
16918 cached_can_issue_more = 0;
16919 return cached_can_issue_more;
16922 /* If no reservation, but reach here */
16923 if (recog_memoized (insn) < 0)
16926 if (rs6000_sched_groups)
16928 if (is_microcoded_insn (insn))
16929 cached_can_issue_more = 0;
16930 else if (is_cracked_insn (insn))
16931 cached_can_issue_more = more > 2 ? more - 2 : 0;
16933 cached_can_issue_more = more - 1;
16935 return cached_can_issue_more;
16938 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
16941 cached_can_issue_more = more - 1;
16942 return cached_can_issue_more;
16945 /* Adjust the cost of a scheduling dependency. Return the new cost of
16946 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16949 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16951 enum attr_type attr_type;
16953 if (! recog_memoized (insn))
16956 switch (REG_NOTE_KIND (link))
16960 /* Data dependency; DEP_INSN writes a register that INSN reads
16961 some cycles later. */
16963 /* Separate a load from a narrower, dependent store. */
16964 if (rs6000_sched_groups
16965 && GET_CODE (PATTERN (insn)) == SET
16966 && GET_CODE (PATTERN (dep_insn)) == SET
16967 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16968 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16969 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16970 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16973 attr_type = get_attr_type (insn);
16978 /* Tell the first scheduling pass about the latency between
16979 a mtctr and bctr (and mtlr and br/blr). The first
16980 scheduling pass will not know about this latency since
16981 the mtctr instruction, which has the latency associated
16982 to it, will be generated by reload. */
16983 return TARGET_POWER ? 5 : 4;
16985 /* Leave some extra cycles between a compare and its
16986 dependent branch, to inhibit expensive mispredicts. */
16987 if ((rs6000_cpu_attr == CPU_PPC603
16988 || rs6000_cpu_attr == CPU_PPC604
16989 || rs6000_cpu_attr == CPU_PPC604E
16990 || rs6000_cpu_attr == CPU_PPC620
16991 || rs6000_cpu_attr == CPU_PPC630
16992 || rs6000_cpu_attr == CPU_PPC750
16993 || rs6000_cpu_attr == CPU_PPC7400
16994 || rs6000_cpu_attr == CPU_PPC7450
16995 || rs6000_cpu_attr == CPU_POWER4
16996 || rs6000_cpu_attr == CPU_POWER5
16997 || rs6000_cpu_attr == CPU_CELL)
16998 && recog_memoized (dep_insn)
16999 && (INSN_CODE (dep_insn) >= 0))
17001 switch (get_attr_type (dep_insn))
17005 case TYPE_DELAYED_COMPARE:
17006 case TYPE_IMUL_COMPARE:
17007 case TYPE_LMUL_COMPARE:
17008 case TYPE_FPCOMPARE:
17009 case TYPE_CR_LOGICAL:
17010 case TYPE_DELAYED_CR:
17019 case TYPE_STORE_UX:
17021 case TYPE_FPSTORE_U:
17022 case TYPE_FPSTORE_UX:
17023 if ((rs6000_cpu == PROCESSOR_POWER6)
17024 && recog_memoized (dep_insn)
17025 && (INSN_CODE (dep_insn) >= 0))
17028 if (GET_CODE (PATTERN (insn)) != SET)
17029 /* If this happens, we have to extend this to schedule
17030 optimally. Return default for now. */
17033 /* Adjust the cost for the case where the value written
17034 by a fixed point operation is used as the address
17035 gen value on a store. */
17036 switch (get_attr_type (dep_insn))
17043 if (! store_data_bypass_p (dep_insn, insn))
17047 case TYPE_LOAD_EXT:
17048 case TYPE_LOAD_EXT_U:
17049 case TYPE_LOAD_EXT_UX:
17050 case TYPE_VAR_SHIFT_ROTATE:
17051 case TYPE_VAR_DELAYED_COMPARE:
17053 if (! store_data_bypass_p (dep_insn, insn))
17059 case TYPE_FAST_COMPARE:
17062 case TYPE_INSERT_WORD:
17063 case TYPE_INSERT_DWORD:
17064 case TYPE_FPLOAD_U:
17065 case TYPE_FPLOAD_UX:
17067 case TYPE_STORE_UX:
17068 case TYPE_FPSTORE_U:
17069 case TYPE_FPSTORE_UX:
17071 if (! store_data_bypass_p (dep_insn, insn))
17079 case TYPE_IMUL_COMPARE:
17080 case TYPE_LMUL_COMPARE:
17082 if (! store_data_bypass_p (dep_insn, insn))
17088 if (! store_data_bypass_p (dep_insn, insn))
17094 if (! store_data_bypass_p (dep_insn, insn))
17107 case TYPE_LOAD_EXT:
17108 case TYPE_LOAD_EXT_U:
17109 case TYPE_LOAD_EXT_UX:
17110 if ((rs6000_cpu == PROCESSOR_POWER6)
17111 && recog_memoized (dep_insn)
17112 && (INSN_CODE (dep_insn) >= 0))
17115 /* Adjust the cost for the case where the value written
17116 by a fixed point instruction is used within the address
17117 gen portion of a subsequent load(u)(x) */
17118 switch (get_attr_type (dep_insn))
17125 if (set_to_load_agen (dep_insn, insn))
17129 case TYPE_LOAD_EXT:
17130 case TYPE_LOAD_EXT_U:
17131 case TYPE_LOAD_EXT_UX:
17132 case TYPE_VAR_SHIFT_ROTATE:
17133 case TYPE_VAR_DELAYED_COMPARE:
17135 if (set_to_load_agen (dep_insn, insn))
17141 case TYPE_FAST_COMPARE:
17144 case TYPE_INSERT_WORD:
17145 case TYPE_INSERT_DWORD:
17146 case TYPE_FPLOAD_U:
17147 case TYPE_FPLOAD_UX:
17149 case TYPE_STORE_UX:
17150 case TYPE_FPSTORE_U:
17151 case TYPE_FPSTORE_UX:
17153 if (set_to_load_agen (dep_insn, insn))
17161 case TYPE_IMUL_COMPARE:
17162 case TYPE_LMUL_COMPARE:
17164 if (set_to_load_agen (dep_insn, insn))
17170 if (set_to_load_agen (dep_insn, insn))
17176 if (set_to_load_agen (dep_insn, insn))
17187 if ((rs6000_cpu == PROCESSOR_POWER6)
17188 && recog_memoized (dep_insn)
17189 && (INSN_CODE (dep_insn) >= 0)
17190 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
17197 /* Fall out to return default cost. */
17201 case REG_DEP_OUTPUT:
17202 /* Output dependency; DEP_INSN writes a register that INSN writes some
17204 if ((rs6000_cpu == PROCESSOR_POWER6)
17205 && recog_memoized (dep_insn)
17206 && (INSN_CODE (dep_insn) >= 0))
17208 attr_type = get_attr_type (insn);
17213 if (get_attr_type (dep_insn) == TYPE_FP)
17217 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
17225 /* Anti dependency; DEP_INSN reads a register that INSN writes some
17230 gcc_unreachable ();
17236 /* The function returns a true if INSN is microcoded.
17237 Return false otherwise. */
17240 is_microcoded_insn (rtx insn)
17242 if (!insn || !INSN_P (insn)
17243 || GET_CODE (PATTERN (insn)) == USE
17244 || GET_CODE (PATTERN (insn)) == CLOBBER)
17247 if (rs6000_cpu_attr == CPU_CELL)
17248 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
17250 if (rs6000_sched_groups)
17252 enum attr_type type = get_attr_type (insn);
17253 if (type == TYPE_LOAD_EXT_U
17254 || type == TYPE_LOAD_EXT_UX
17255 || type == TYPE_LOAD_UX
17256 || type == TYPE_STORE_UX
17257 || type == TYPE_MFCR)
17264 /* The function returns true if INSN is cracked into 2 instructions
17265 by the processor (and therefore occupies 2 issue slots). */
17268 is_cracked_insn (rtx insn)
17270 if (!insn || !INSN_P (insn)
17271 || GET_CODE (PATTERN (insn)) == USE
17272 || GET_CODE (PATTERN (insn)) == CLOBBER)
17275 if (rs6000_sched_groups)
17277 enum attr_type type = get_attr_type (insn);
17278 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
17279 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
17280 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
17281 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
17282 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
17283 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
17284 || type == TYPE_IDIV || type == TYPE_LDIV
17285 || type == TYPE_INSERT_WORD)
17292 /* The function returns true if INSN can be issued only from
17293 the branch slot. */
17296 is_branch_slot_insn (rtx insn)
17298 if (!insn || !INSN_P (insn)
17299 || GET_CODE (PATTERN (insn)) == USE
17300 || GET_CODE (PATTERN (insn)) == CLOBBER)
17303 if (rs6000_sched_groups)
17305 enum attr_type type = get_attr_type (insn);
17306 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
17314 /* The function returns true if out_inst sets a value that is
17315 used in the address generation computation of in_insn */
17317 set_to_load_agen (rtx out_insn, rtx in_insn)
17319 rtx out_set, in_set;
17321 /* For performance reasons, only handle the simple case where
17322 both loads are a single_set. */
17323 out_set = single_set (out_insn);
17326 in_set = single_set (in_insn);
17328 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
17334 /* The function returns true if the target storage location of
17335 out_insn is adjacent to the target storage location of in_insn */
17336 /* Return 1 if memory locations are adjacent. */
17339 adjacent_mem_locations (rtx insn1, rtx insn2)
17342 rtx a = get_store_dest (PATTERN (insn1));
17343 rtx b = get_store_dest (PATTERN (insn2));
17345 if ((GET_CODE (XEXP (a, 0)) == REG
17346 || (GET_CODE (XEXP (a, 0)) == PLUS
17347 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
17348 && (GET_CODE (XEXP (b, 0)) == REG
17349 || (GET_CODE (XEXP (b, 0)) == PLUS
17350 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
17352 HOST_WIDE_INT val0 = 0, val1 = 0;
17356 if (GET_CODE (XEXP (a, 0)) == PLUS)
17358 reg0 = XEXP (XEXP (a, 0), 0);
17359 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
17362 reg0 = XEXP (a, 0);
17364 if (GET_CODE (XEXP (b, 0)) == PLUS)
17366 reg1 = XEXP (XEXP (b, 0), 0);
17367 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
17370 reg1 = XEXP (b, 0);
17372 val_diff = val1 - val0;
17374 return ((REGNO (reg0) == REGNO (reg1))
17375 && (val_diff == INTVAL (MEM_SIZE (a))
17376 || val_diff == -INTVAL (MEM_SIZE (b))));
17382 /* A C statement (sans semicolon) to update the integer scheduling
17383 priority INSN_PRIORITY (INSN). Increase the priority to execute the
17384 INSN earlier, reduce the priority to execute INSN later. Do not
17385 define this macro if you do not need to adjust the scheduling
17386 priorities of insns. */
17389 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
17391 /* On machines (like the 750) which have asymmetric integer units,
17392 where one integer unit can do multiply and divides and the other
17393 can't, reduce the priority of multiply/divide so it is scheduled
17394 before other integer operations. */
17397 if (! INSN_P (insn))
17400 if (GET_CODE (PATTERN (insn)) == USE)
17403 switch (rs6000_cpu_attr) {
17405 switch (get_attr_type (insn))
17412 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
17413 priority, priority);
17414 if (priority >= 0 && priority < 0x01000000)
17421 if (insn_must_be_first_in_group (insn)
17422 && reload_completed
17423 && current_sched_info->sched_max_insns_priority
17424 && rs6000_sched_restricted_insns_priority)
17427 /* Prioritize insns that can be dispatched only in the first
17429 if (rs6000_sched_restricted_insns_priority == 1)
17430 /* Attach highest priority to insn. This means that in
17431 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
17432 precede 'priority' (critical path) considerations. */
17433 return current_sched_info->sched_max_insns_priority;
17434 else if (rs6000_sched_restricted_insns_priority == 2)
17435 /* Increase priority of insn by a minimal amount. This means that in
17436 haifa-sched.c:ready_sort(), only 'priority' (critical path)
17437 considerations precede dispatch-slot restriction considerations. */
17438 return (priority + 1);
17441 if (rs6000_cpu == PROCESSOR_POWER6
17442 && ((load_store_pendulum == -2 && is_load_insn (insn))
17443 || (load_store_pendulum == 2 && is_store_insn (insn))))
17444 /* Attach highest priority to insn if the scheduler has just issued two
17445 stores and this instruction is a load, or two loads and this instruction
17446 is a store. Power6 wants loads and stores scheduled alternately
17448 return current_sched_info->sched_max_insns_priority;
17453 /* Return true if the instruction is nonpipelined on the Cell. */
17455 is_nonpipeline_insn (rtx insn)
17457 enum attr_type type;
17458 if (!insn || !INSN_P (insn)
17459 || GET_CODE (PATTERN (insn)) == USE
17460 || GET_CODE (PATTERN (insn)) == CLOBBER)
17463 type = get_attr_type (insn);
17464 if (type == TYPE_IMUL
17465 || type == TYPE_IMUL2
17466 || type == TYPE_IMUL3
17467 || type == TYPE_LMUL
17468 || type == TYPE_IDIV
17469 || type == TYPE_LDIV
17470 || type == TYPE_SDIV
17471 || type == TYPE_DDIV
17472 || type == TYPE_SSQRT
17473 || type == TYPE_DSQRT
17474 || type == TYPE_MFCR
17475 || type == TYPE_MFCRF
17476 || type == TYPE_MFJMPR)
17484 /* Return how many instructions the machine can issue per cycle. */
17487 rs6000_issue_rate (void)
17489 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
17490 if (!reload_completed)
17493 switch (rs6000_cpu_attr) {
17494 case CPU_RIOS1: /* ? */
17496 case CPU_PPC601: /* ? */
17521 /* Return how many instructions to look ahead for better insn
17525 rs6000_use_sched_lookahead (void)
17527 if (rs6000_cpu_attr == CPU_PPC8540)
17529 if (rs6000_cpu_attr == CPU_CELL)
17530 return (reload_completed ? 8 : 0);
17534 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
17536 rs6000_use_sched_lookahead_guard (rtx insn)
17538 if (rs6000_cpu_attr != CPU_CELL)
17541 if (insn == NULL_RTX || !INSN_P (insn))
17544 if (!reload_completed
17545 || is_nonpipeline_insn (insn)
17546 || is_microcoded_insn (insn))
17552 /* Determine is PAT refers to memory. */
17555 is_mem_ref (rtx pat)
17561 if (GET_CODE (pat) == MEM)
17564 /* Recursively process the pattern. */
17565 fmt = GET_RTX_FORMAT (GET_CODE (pat));
17567 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
17570 ret |= is_mem_ref (XEXP (pat, i));
17571 else if (fmt[i] == 'E')
17572 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
17573 ret |= is_mem_ref (XVECEXP (pat, i, j));
17579 /* Determine if PAT is a PATTERN of a load insn. */
17582 is_load_insn1 (rtx pat)
17584 if (!pat || pat == NULL_RTX)
17587 if (GET_CODE (pat) == SET)
17588 return is_mem_ref (SET_SRC (pat));
17590 if (GET_CODE (pat) == PARALLEL)
17594 for (i = 0; i < XVECLEN (pat, 0); i++)
17595 if (is_load_insn1 (XVECEXP (pat, 0, i)))
17602 /* Determine if INSN loads from memory. */
17605 is_load_insn (rtx insn)
17607 if (!insn || !INSN_P (insn))
17610 if (GET_CODE (insn) == CALL_INSN)
17613 return is_load_insn1 (PATTERN (insn));
17616 /* Determine if PAT is a PATTERN of a store insn. */
17619 is_store_insn1 (rtx pat)
17621 if (!pat || pat == NULL_RTX)
17624 if (GET_CODE (pat) == SET)
17625 return is_mem_ref (SET_DEST (pat));
17627 if (GET_CODE (pat) == PARALLEL)
17631 for (i = 0; i < XVECLEN (pat, 0); i++)
17632 if (is_store_insn1 (XVECEXP (pat, 0, i)))
17639 /* Determine if INSN stores to memory. */
17642 is_store_insn (rtx insn)
17644 if (!insn || !INSN_P (insn))
17647 return is_store_insn1 (PATTERN (insn));
17650 /* Return the dest of a store insn. */
17653 get_store_dest (rtx pat)
17655 gcc_assert (is_store_insn1 (pat));
17657 if (GET_CODE (pat) == SET)
17658 return SET_DEST (pat);
17659 else if (GET_CODE (pat) == PARALLEL)
17663 for (i = 0; i < XVECLEN (pat, 0); i++)
17665 rtx inner_pat = XVECEXP (pat, 0, i);
17666 if (GET_CODE (inner_pat) == SET
17667 && is_mem_ref (SET_DEST (inner_pat)))
17671 /* We shouldn't get here, because we should have either a simple
17672 store insn or a store with update which are covered above. */
17676 /* Returns whether the dependence between INSN and NEXT is considered
17677 costly by the given target. */
17680 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
17685 /* If the flag is not enabled - no dependence is considered costly;
17686 allow all dependent insns in the same group.
17687 This is the most aggressive option. */
17688 if (rs6000_sched_costly_dep == no_dep_costly)
17691 /* If the flag is set to 1 - a dependence is always considered costly;
17692 do not allow dependent instructions in the same group.
17693 This is the most conservative option. */
17694 if (rs6000_sched_costly_dep == all_deps_costly)
17697 insn = DEP_PRO (dep);
17698 next = DEP_CON (dep);
17700 if (rs6000_sched_costly_dep == store_to_load_dep_costly
17701 && is_load_insn (next)
17702 && is_store_insn (insn))
17703 /* Prevent load after store in the same group. */
17706 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
17707 && is_load_insn (next)
17708 && is_store_insn (insn)
17709 && DEP_KIND (dep) == REG_DEP_TRUE)
17710 /* Prevent load after store in the same group if it is a true
17714 /* The flag is set to X; dependences with latency >= X are considered costly,
17715 and will not be scheduled in the same group. */
17716 if (rs6000_sched_costly_dep <= max_dep_latency
17717 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
17723 /* Return the next insn after INSN that is found before TAIL is reached,
17724 skipping any "non-active" insns - insns that will not actually occupy
17725 an issue slot. Return NULL_RTX if such an insn is not found. */
17728 get_next_active_insn (rtx insn, rtx tail)
17730 if (insn == NULL_RTX || insn == tail)
17735 insn = NEXT_INSN (insn);
17736 if (insn == NULL_RTX || insn == tail)
17741 || (NONJUMP_INSN_P (insn)
17742 && GET_CODE (PATTERN (insn)) != USE
17743 && GET_CODE (PATTERN (insn)) != CLOBBER
17744 && INSN_CODE (insn) != CODE_FOR_stack_tie))
17750 /* We are about to begin issuing insns for this clock cycle. */
17753 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
17754 rtx *ready ATTRIBUTE_UNUSED,
17755 int *pn_ready ATTRIBUTE_UNUSED,
17756 int clock_var ATTRIBUTE_UNUSED)
17758 int n_ready = *pn_ready;
17761 fprintf (dump, "// rs6000_sched_reorder :\n");
17763 /* Reorder the ready list, if the second to last ready insn
17764 is a nonepipeline insn. */
17765 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
17767 if (is_nonpipeline_insn (ready[n_ready - 1])
17768 && (recog_memoized (ready[n_ready - 2]) > 0))
17769 /* Simply swap first two insns. */
17771 rtx tmp = ready[n_ready - 1];
17772 ready[n_ready - 1] = ready[n_ready - 2];
17773 ready[n_ready - 2] = tmp;
17777 if (rs6000_cpu == PROCESSOR_POWER6)
17778 load_store_pendulum = 0;
17780 return rs6000_issue_rate ();
17783 /* Like rs6000_sched_reorder, but called after issuing each insn. */
17786 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
17787 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
17790 fprintf (dump, "// rs6000_sched_reorder2 :\n");
17792 /* For Power6, we need to handle some special cases to try and keep the
17793 store queue from overflowing and triggering expensive flushes.
17795 This code monitors how load and store instructions are being issued
17796 and skews the ready list one way or the other to increase the likelihood
17797 that a desired instruction is issued at the proper time.
17799 A couple of things are done. First, we maintain a "load_store_pendulum"
17800 to track the current state of load/store issue.
17802 - If the pendulum is at zero, then no loads or stores have been
17803 issued in the current cycle so we do nothing.
17805 - If the pendulum is 1, then a single load has been issued in this
17806 cycle and we attempt to locate another load in the ready list to
17809 - If the pendulum is -2, then two stores have already been
17810 issued in this cycle, so we increase the priority of the first load
17811 in the ready list to increase it's likelihood of being chosen first
17814 - If the pendulum is -1, then a single store has been issued in this
17815 cycle and we attempt to locate another store in the ready list to
17816 issue with it, preferring a store to an adjacent memory location to
17817 facilitate store pairing in the store queue.
17819 - If the pendulum is 2, then two loads have already been
17820 issued in this cycle, so we increase the priority of the first store
17821 in the ready list to increase it's likelihood of being chosen first
17824 - If the pendulum < -2 or > 2, then do nothing.
17826 Note: This code covers the most common scenarios. There exist non
17827 load/store instructions which make use of the LSU and which
17828 would need to be accounted for to strictly model the behavior
17829 of the machine. Those instructions are currently unaccounted
17830 for to help minimize compile time overhead of this code.
17832 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
17838 if (is_store_insn (last_scheduled_insn))
17839 /* Issuing a store, swing the load_store_pendulum to the left */
17840 load_store_pendulum--;
17841 else if (is_load_insn (last_scheduled_insn))
17842 /* Issuing a load, swing the load_store_pendulum to the right */
17843 load_store_pendulum++;
17845 return cached_can_issue_more;
17847 /* If the pendulum is balanced, or there is only one instruction on
17848 the ready list, then all is well, so return. */
17849 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
17850 return cached_can_issue_more;
17852 if (load_store_pendulum == 1)
17854 /* A load has been issued in this cycle. Scan the ready list
17855 for another load to issue with it */
17860 if (is_load_insn (ready[pos]))
17862 /* Found a load. Move it to the head of the ready list,
17863 and adjust it's priority so that it is more likely to
17866 for (i=pos; i<*pn_ready-1; i++)
17867 ready[i] = ready[i + 1];
17868 ready[*pn_ready-1] = tmp;
17869 if INSN_PRIORITY_KNOWN (tmp)
17870 INSN_PRIORITY (tmp)++;
17876 else if (load_store_pendulum == -2)
17878 /* Two stores have been issued in this cycle. Increase the
17879 priority of the first load in the ready list to favor it for
17880 issuing in the next cycle. */
17885 if (is_load_insn (ready[pos])
17886 && INSN_PRIORITY_KNOWN (ready[pos]))
17888 INSN_PRIORITY (ready[pos])++;
17890 /* Adjust the pendulum to account for the fact that a load
17891 was found and increased in priority. This is to prevent
17892 increasing the priority of multiple loads */
17893 load_store_pendulum--;
17900 else if (load_store_pendulum == -1)
17902 /* A store has been issued in this cycle. Scan the ready list for
17903 another store to issue with it, preferring a store to an adjacent
17905 int first_store_pos = -1;
17911 if (is_store_insn (ready[pos]))
17913 /* Maintain the index of the first store found on the
17915 if (first_store_pos == -1)
17916 first_store_pos = pos;
17918 if (is_store_insn (last_scheduled_insn)
17919 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
17921 /* Found an adjacent store. Move it to the head of the
17922 ready list, and adjust it's priority so that it is
17923 more likely to stay there */
17925 for (i=pos; i<*pn_ready-1; i++)
17926 ready[i] = ready[i + 1];
17927 ready[*pn_ready-1] = tmp;
17928 if INSN_PRIORITY_KNOWN (tmp)
17929 INSN_PRIORITY (tmp)++;
17930 first_store_pos = -1;
17938 if (first_store_pos >= 0)
17940 /* An adjacent store wasn't found, but a non-adjacent store was,
17941 so move the non-adjacent store to the front of the ready
17942 list, and adjust its priority so that it is more likely to
17944 tmp = ready[first_store_pos];
17945 for (i=first_store_pos; i<*pn_ready-1; i++)
17946 ready[i] = ready[i + 1];
17947 ready[*pn_ready-1] = tmp;
17948 if INSN_PRIORITY_KNOWN (tmp)
17949 INSN_PRIORITY (tmp)++;
17952 else if (load_store_pendulum == 2)
17954 /* Two loads have been issued in this cycle. Increase the priority
17955 of the first store in the ready list to favor it for issuing in
17961 if (is_store_insn (ready[pos])
17962 && INSN_PRIORITY_KNOWN (ready[pos]))
17964 INSN_PRIORITY (ready[pos])++;
17966 /* Adjust the pendulum to account for the fact that a store
17967 was found and increased in priority. This is to prevent
17968 increasing the priority of multiple stores */
17969 load_store_pendulum++;
17978 return cached_can_issue_more;
17981 /* Return whether the presence of INSN causes a dispatch group termination
17982 of group WHICH_GROUP.
17984 If WHICH_GROUP == current_group, this function will return true if INSN
17985 causes the termination of the current group (i.e, the dispatch group to
17986 which INSN belongs). This means that INSN will be the last insn in the
17987 group it belongs to.
17989 If WHICH_GROUP == previous_group, this function will return true if INSN
17990 causes the termination of the previous group (i.e, the dispatch group that
17991 precedes the group to which INSN belongs). This means that INSN will be
17992 the first insn in the group it belongs to). */
17995 insn_terminates_group_p (rtx insn, enum group_termination which_group)
18002 first = insn_must_be_first_in_group (insn);
18003 last = insn_must_be_last_in_group (insn);
18008 if (which_group == current_group)
18010 else if (which_group == previous_group)
18018 insn_must_be_first_in_group (rtx insn)
18020 enum attr_type type;
18023 || insn == NULL_RTX
18024 || GET_CODE (insn) == NOTE
18025 || GET_CODE (PATTERN (insn)) == USE
18026 || GET_CODE (PATTERN (insn)) == CLOBBER)
18029 switch (rs6000_cpu)
18031 case PROCESSOR_POWER5:
18032 if (is_cracked_insn (insn))
18034 case PROCESSOR_POWER4:
18035 if (is_microcoded_insn (insn))
18038 if (!rs6000_sched_groups)
18041 type = get_attr_type (insn);
18048 case TYPE_DELAYED_CR:
18049 case TYPE_CR_LOGICAL:
18063 case PROCESSOR_POWER6:
18064 type = get_attr_type (insn);
18068 case TYPE_INSERT_DWORD:
18072 case TYPE_VAR_SHIFT_ROTATE:
18079 case TYPE_INSERT_WORD:
18080 case TYPE_DELAYED_COMPARE:
18081 case TYPE_IMUL_COMPARE:
18082 case TYPE_LMUL_COMPARE:
18083 case TYPE_FPCOMPARE:
18094 case TYPE_LOAD_EXT_UX:
18096 case TYPE_STORE_UX:
18097 case TYPE_FPLOAD_U:
18098 case TYPE_FPLOAD_UX:
18099 case TYPE_FPSTORE_U:
18100 case TYPE_FPSTORE_UX:
18114 insn_must_be_last_in_group (rtx insn)
18116 enum attr_type type;
18119 || insn == NULL_RTX
18120 || GET_CODE (insn) == NOTE
18121 || GET_CODE (PATTERN (insn)) == USE
18122 || GET_CODE (PATTERN (insn)) == CLOBBER)
18125 switch (rs6000_cpu) {
18126 case PROCESSOR_POWER4:
18127 case PROCESSOR_POWER5:
18128 if (is_microcoded_insn (insn))
18131 if (is_branch_slot_insn (insn))
18135 case PROCESSOR_POWER6:
18136 type = get_attr_type (insn);
18143 case TYPE_VAR_SHIFT_ROTATE:
18150 case TYPE_DELAYED_COMPARE:
18151 case TYPE_IMUL_COMPARE:
18152 case TYPE_LMUL_COMPARE:
18153 case TYPE_FPCOMPARE:
18174 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
18175 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
18178 is_costly_group (rtx *group_insns, rtx next_insn)
18181 int issue_rate = rs6000_issue_rate ();
18183 for (i = 0; i < issue_rate; i++)
18186 rtx insn = group_insns[i];
18191 FOR_EACH_DEP_LINK (link, INSN_FORW_DEPS (insn))
18193 dep_t dep = DEP_LINK_DEP (link);
18194 rtx next = DEP_CON (dep);
18196 if (next == next_insn
18197 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
18205 /* Utility of the function redefine_groups.
18206 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
18207 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
18208 to keep it "far" (in a separate group) from GROUP_INSNS, following
18209 one of the following schemes, depending on the value of the flag
18210 -minsert_sched_nops = X:
18211 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
18212 in order to force NEXT_INSN into a separate group.
18213 (2) X < sched_finish_regroup_exact: insert exactly X nops.
18214 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
18215 insertion (has a group just ended, how many vacant issue slots remain in the
18216 last group, and how many dispatch groups were encountered so far). */
18219 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
18220 rtx next_insn, bool *group_end, int can_issue_more,
18225 int issue_rate = rs6000_issue_rate ();
18226 bool end = *group_end;
18229 if (next_insn == NULL_RTX)
18230 return can_issue_more;
18232 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
18233 return can_issue_more;
18235 force = is_costly_group (group_insns, next_insn);
18237 return can_issue_more;
18239 if (sched_verbose > 6)
18240 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
18241 *group_count ,can_issue_more);
18243 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
18246 can_issue_more = 0;
18248 /* Since only a branch can be issued in the last issue_slot, it is
18249 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
18250 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
18251 in this case the last nop will start a new group and the branch
18252 will be forced to the new group. */
18253 if (can_issue_more && !is_branch_slot_insn (next_insn))
18256 while (can_issue_more > 0)
18259 emit_insn_before (nop, next_insn);
18267 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
18269 int n_nops = rs6000_sched_insert_nops;
18271 /* Nops can't be issued from the branch slot, so the effective
18272 issue_rate for nops is 'issue_rate - 1'. */
18273 if (can_issue_more == 0)
18274 can_issue_more = issue_rate;
18276 if (can_issue_more == 0)
18278 can_issue_more = issue_rate - 1;
18281 for (i = 0; i < issue_rate; i++)
18283 group_insns[i] = 0;
18290 emit_insn_before (nop, next_insn);
18291 if (can_issue_more == issue_rate - 1) /* new group begins */
18294 if (can_issue_more == 0)
18296 can_issue_more = issue_rate - 1;
18299 for (i = 0; i < issue_rate; i++)
18301 group_insns[i] = 0;
18307 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
18310 /* Is next_insn going to start a new group? */
18313 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18314 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18315 || (can_issue_more < issue_rate &&
18316 insn_terminates_group_p (next_insn, previous_group)));
18317 if (*group_end && end)
18320 if (sched_verbose > 6)
18321 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
18322 *group_count, can_issue_more);
18323 return can_issue_more;
18326 return can_issue_more;
18329 /* This function tries to synch the dispatch groups that the compiler "sees"
18330 with the dispatch groups that the processor dispatcher is expected to
18331 form in practice. It tries to achieve this synchronization by forcing the
18332 estimated processor grouping on the compiler (as opposed to the function
18333 'pad_goups' which tries to force the scheduler's grouping on the processor).
18335 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
18336 examines the (estimated) dispatch groups that will be formed by the processor
18337 dispatcher. It marks these group boundaries to reflect the estimated
18338 processor grouping, overriding the grouping that the scheduler had marked.
18339 Depending on the value of the flag '-minsert-sched-nops' this function can
18340 force certain insns into separate groups or force a certain distance between
18341 them by inserting nops, for example, if there exists a "costly dependence"
18344 The function estimates the group boundaries that the processor will form as
18345 follows: It keeps track of how many vacant issue slots are available after
18346 each insn. A subsequent insn will start a new group if one of the following
18348 - no more vacant issue slots remain in the current dispatch group.
18349 - only the last issue slot, which is the branch slot, is vacant, but the next
18350 insn is not a branch.
18351 - only the last 2 or less issue slots, including the branch slot, are vacant,
18352 which means that a cracked insn (which occupies two issue slots) can't be
18353 issued in this group.
18354 - less than 'issue_rate' slots are vacant, and the next insn always needs to
18355 start a new group. */
18358 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18360 rtx insn, next_insn;
18362 int can_issue_more;
18365 int group_count = 0;
18369 issue_rate = rs6000_issue_rate ();
18370 group_insns = alloca (issue_rate * sizeof (rtx));
18371 for (i = 0; i < issue_rate; i++)
18373 group_insns[i] = 0;
18375 can_issue_more = issue_rate;
18377 insn = get_next_active_insn (prev_head_insn, tail);
18380 while (insn != NULL_RTX)
18382 slot = (issue_rate - can_issue_more);
18383 group_insns[slot] = insn;
18385 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18386 if (insn_terminates_group_p (insn, current_group))
18387 can_issue_more = 0;
18389 next_insn = get_next_active_insn (insn, tail);
18390 if (next_insn == NULL_RTX)
18391 return group_count + 1;
18393 /* Is next_insn going to start a new group? */
18395 = (can_issue_more == 0
18396 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18397 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18398 || (can_issue_more < issue_rate &&
18399 insn_terminates_group_p (next_insn, previous_group)));
18401 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
18402 next_insn, &group_end, can_issue_more,
18408 can_issue_more = 0;
18409 for (i = 0; i < issue_rate; i++)
18411 group_insns[i] = 0;
18415 if (GET_MODE (next_insn) == TImode && can_issue_more)
18416 PUT_MODE (next_insn, VOIDmode);
18417 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
18418 PUT_MODE (next_insn, TImode);
18421 if (can_issue_more == 0)
18422 can_issue_more = issue_rate;
18425 return group_count;
18428 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
18429 dispatch group boundaries that the scheduler had marked. Pad with nops
18430 any dispatch groups which have vacant issue slots, in order to force the
18431 scheduler's grouping on the processor dispatcher. The function
18432 returns the number of dispatch groups found. */
18435 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18437 rtx insn, next_insn;
18440 int can_issue_more;
18442 int group_count = 0;
18444 /* Initialize issue_rate. */
18445 issue_rate = rs6000_issue_rate ();
18446 can_issue_more = issue_rate;
18448 insn = get_next_active_insn (prev_head_insn, tail);
18449 next_insn = get_next_active_insn (insn, tail);
18451 while (insn != NULL_RTX)
18454 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18456 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
18458 if (next_insn == NULL_RTX)
18463 /* If the scheduler had marked group termination at this location
18464 (between insn and next_indn), and neither insn nor next_insn will
18465 force group termination, pad the group with nops to force group
18468 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
18469 && !insn_terminates_group_p (insn, current_group)
18470 && !insn_terminates_group_p (next_insn, previous_group))
18472 if (!is_branch_slot_insn (next_insn))
18475 while (can_issue_more)
18478 emit_insn_before (nop, next_insn);
18483 can_issue_more = issue_rate;
18488 next_insn = get_next_active_insn (insn, tail);
18491 return group_count;
18494 /* We're beginning a new block. Initialize data structures as necessary. */
18497 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
18498 int sched_verbose ATTRIBUTE_UNUSED,
18499 int max_ready ATTRIBUTE_UNUSED)
18501 last_scheduled_insn = NULL_RTX;
18502 load_store_pendulum = 0;
18505 /* The following function is called at the end of scheduling BB.
18506 After reload, it inserts nops at insn group bundling. */
18509 rs6000_sched_finish (FILE *dump, int sched_verbose)
18514 fprintf (dump, "=== Finishing schedule.\n");
18516 if (reload_completed && rs6000_sched_groups)
18518 if (rs6000_sched_insert_nops == sched_finish_none)
18521 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
18522 n_groups = pad_groups (dump, sched_verbose,
18523 current_sched_info->prev_head,
18524 current_sched_info->next_tail);
18526 n_groups = redefine_groups (dump, sched_verbose,
18527 current_sched_info->prev_head,
18528 current_sched_info->next_tail);
18530 if (sched_verbose >= 6)
18532 fprintf (dump, "ngroups = %d\n", n_groups);
18533 print_rtl (dump, current_sched_info->prev_head);
18534 fprintf (dump, "Done finish_sched\n");
18539 /* Length in units of the trampoline for entering a nested function. */
18542 rs6000_trampoline_size (void)
18546 switch (DEFAULT_ABI)
18549 gcc_unreachable ();
18552 ret = (TARGET_32BIT) ? 12 : 24;
18557 ret = (TARGET_32BIT) ? 40 : 48;
18564 /* Emit RTL insns to initialize the variable parts of a trampoline.
18565 FNADDR is an RTX for the address of the function's pure code.
18566 CXT is an RTX for the static chain value for the function. */
18569 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
18571 int regsize = (TARGET_32BIT) ? 4 : 8;
18572 rtx ctx_reg = force_reg (Pmode, cxt);
18574 switch (DEFAULT_ABI)
18577 gcc_unreachable ();
18579 /* Macros to shorten the code expansions below. */
18580 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
18581 #define MEM_PLUS(addr,offset) \
18582 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
18584 /* Under AIX, just build the 3 word function descriptor */
18587 rtx fn_reg = gen_reg_rtx (Pmode);
18588 rtx toc_reg = gen_reg_rtx (Pmode);
18589 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
18590 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
18591 emit_move_insn (MEM_DEREF (addr), fn_reg);
18592 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
18593 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
18597 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
18600 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
18601 FALSE, VOIDmode, 4,
18603 GEN_INT (rs6000_trampoline_size ()), SImode,
18613 /* Table of valid machine attributes. */
18615 const struct attribute_spec rs6000_attribute_table[] =
18617 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
18618 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
18619 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18620 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18621 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18622 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18623 #ifdef SUBTARGET_ATTRIBUTE_TABLE
18624 SUBTARGET_ATTRIBUTE_TABLE,
18626 { NULL, 0, 0, false, false, false, NULL }
18629 /* Handle the "altivec" attribute. The attribute may have
18630 arguments as follows:
18632 __attribute__((altivec(vector__)))
18633 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
18634 __attribute__((altivec(bool__))) (always followed by 'unsigned')
18636 and may appear more than once (e.g., 'vector bool char') in a
18637 given declaration. */
18640 rs6000_handle_altivec_attribute (tree *node,
18641 tree name ATTRIBUTE_UNUSED,
18643 int flags ATTRIBUTE_UNUSED,
18644 bool *no_add_attrs)
18646 tree type = *node, result = NULL_TREE;
18647 enum machine_mode mode;
18650 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
18651 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
18652 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
18655 while (POINTER_TYPE_P (type)
18656 || TREE_CODE (type) == FUNCTION_TYPE
18657 || TREE_CODE (type) == METHOD_TYPE
18658 || TREE_CODE (type) == ARRAY_TYPE)
18659 type = TREE_TYPE (type);
18661 mode = TYPE_MODE (type);
18663 /* Check for invalid AltiVec type qualifiers. */
18664 if (type == long_unsigned_type_node || type == long_integer_type_node)
18667 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
18668 else if (rs6000_warn_altivec_long)
18669 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
18671 else if (type == long_long_unsigned_type_node
18672 || type == long_long_integer_type_node)
18673 error ("use of %<long long%> in AltiVec types is invalid");
18674 else if (type == double_type_node)
18675 error ("use of %<double%> in AltiVec types is invalid");
18676 else if (type == long_double_type_node)
18677 error ("use of %<long double%> in AltiVec types is invalid");
18678 else if (type == boolean_type_node)
18679 error ("use of boolean types in AltiVec types is invalid");
18680 else if (TREE_CODE (type) == COMPLEX_TYPE)
18681 error ("use of %<complex%> in AltiVec types is invalid");
18682 else if (DECIMAL_FLOAT_MODE_P (mode))
18683 error ("use of decimal floating point types in AltiVec types is invalid");
18685 switch (altivec_type)
18688 unsigned_p = TYPE_UNSIGNED (type);
18692 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
18695 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
18698 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
18700 case SFmode: result = V4SF_type_node; break;
18701 /* If the user says 'vector int bool', we may be handed the 'bool'
18702 attribute _before_ the 'vector' attribute, and so select the
18703 proper type in the 'b' case below. */
18704 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
18712 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
18713 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
18714 case QImode: case V16QImode: result = bool_V16QI_type_node;
18721 case V8HImode: result = pixel_V8HI_type_node;
18727 if (result && result != type && TYPE_READONLY (type))
18728 result = build_qualified_type (result, TYPE_QUAL_CONST);
18730 *no_add_attrs = true; /* No need to hang on to the attribute. */
18733 *node = reconstruct_complex_type (*node, result);
18738 /* AltiVec defines four built-in scalar types that serve as vector
18739 elements; we must teach the compiler how to mangle them. */
18741 static const char *
18742 rs6000_mangle_fundamental_type (tree type)
18744 if (type == bool_char_type_node) return "U6__boolc";
18745 if (type == bool_short_type_node) return "U6__bools";
18746 if (type == pixel_type_node) return "u7__pixel";
18747 if (type == bool_int_type_node) return "U6__booli";
18749 /* Mangle IBM extended float long double as `g' (__float128) on
18750 powerpc*-linux where long-double-64 previously was the default. */
18751 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
18753 && TARGET_LONG_DOUBLE_128
18754 && !TARGET_IEEEQUAD)
18757 /* For all other types, use normal C++ mangling. */
18761 /* Handle a "longcall" or "shortcall" attribute; arguments as in
18762 struct attribute_spec.handler. */
18765 rs6000_handle_longcall_attribute (tree *node, tree name,
18766 tree args ATTRIBUTE_UNUSED,
18767 int flags ATTRIBUTE_UNUSED,
18768 bool *no_add_attrs)
18770 if (TREE_CODE (*node) != FUNCTION_TYPE
18771 && TREE_CODE (*node) != FIELD_DECL
18772 && TREE_CODE (*node) != TYPE_DECL)
18774 warning (OPT_Wattributes, "%qs attribute only applies to functions",
18775 IDENTIFIER_POINTER (name));
18776 *no_add_attrs = true;
18782 /* Set longcall attributes on all functions declared when
18783 rs6000_default_long_calls is true. */
18785 rs6000_set_default_type_attributes (tree type)
18787 if (rs6000_default_long_calls
18788 && (TREE_CODE (type) == FUNCTION_TYPE
18789 || TREE_CODE (type) == METHOD_TYPE))
18790 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
18792 TYPE_ATTRIBUTES (type));
18795 darwin_set_default_type_attributes (type);
18799 /* Return a reference suitable for calling a function with the
18800 longcall attribute. */
18803 rs6000_longcall_ref (rtx call_ref)
18805 const char *call_name;
18808 if (GET_CODE (call_ref) != SYMBOL_REF)
18811 /* System V adds '.' to the internal name, so skip them. */
18812 call_name = XSTR (call_ref, 0);
18813 if (*call_name == '.')
18815 while (*call_name == '.')
18818 node = get_identifier (call_name);
18819 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
18822 return force_reg (Pmode, call_ref);
18825 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
18826 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
18829 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
18830 struct attribute_spec.handler. */
18832 rs6000_handle_struct_attribute (tree *node, tree name,
18833 tree args ATTRIBUTE_UNUSED,
18834 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
18837 if (DECL_P (*node))
18839 if (TREE_CODE (*node) == TYPE_DECL)
18840 type = &TREE_TYPE (*node);
18845 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
18846 || TREE_CODE (*type) == UNION_TYPE)))
18848 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
18849 *no_add_attrs = true;
18852 else if ((is_attribute_p ("ms_struct", name)
18853 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
18854 || ((is_attribute_p ("gcc_struct", name)
18855 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
18857 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
18858 IDENTIFIER_POINTER (name));
18859 *no_add_attrs = true;
18866 rs6000_ms_bitfield_layout_p (tree record_type)
18868 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
18869 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
18870 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
18873 #ifdef USING_ELFOS_H
18875 /* A get_unnamed_section callback, used for switching to toc_section. */
18878 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
18880 if (DEFAULT_ABI == ABI_AIX
18881 && TARGET_MINIMAL_TOC
18882 && !TARGET_RELOCATABLE)
18884 if (!toc_initialized)
18886 toc_initialized = 1;
18887 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
18888 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
18889 fprintf (asm_out_file, "\t.tc ");
18890 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
18891 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
18892 fprintf (asm_out_file, "\n");
18894 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18895 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
18896 fprintf (asm_out_file, " = .+32768\n");
18899 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18901 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
18902 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
18905 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18906 if (!toc_initialized)
18908 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
18909 fprintf (asm_out_file, " = .+32768\n");
18910 toc_initialized = 1;
18915 /* Implement TARGET_ASM_INIT_SECTIONS. */
18918 rs6000_elf_asm_init_sections (void)
18921 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
18924 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
18925 SDATA2_SECTION_ASM_OP);
18928 /* Implement TARGET_SELECT_RTX_SECTION. */
18931 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
18932 unsigned HOST_WIDE_INT align)
18934 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
18935 return toc_section;
18937 return default_elf_select_rtx_section (mode, x, align);
18940 /* For a SYMBOL_REF, set generic flags and then perform some
18941 target-specific processing.
18943 When the AIX ABI is requested on a non-AIX system, replace the
18944 function name with the real name (with a leading .) rather than the
18945 function descriptor name. This saves a lot of overriding code to
18946 read the prefixes. */
18949 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
18951 default_encode_section_info (decl, rtl, first);
18954 && TREE_CODE (decl) == FUNCTION_DECL
18956 && DEFAULT_ABI == ABI_AIX)
18958 rtx sym_ref = XEXP (rtl, 0);
18959 size_t len = strlen (XSTR (sym_ref, 0));
18960 char *str = alloca (len + 2);
18962 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
18963 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
18968 rs6000_elf_in_small_data_p (tree decl)
18970 if (rs6000_sdata == SDATA_NONE)
18973 /* We want to merge strings, so we never consider them small data. */
18974 if (TREE_CODE (decl) == STRING_CST)
18977 /* Functions are never in the small data area. */
18978 if (TREE_CODE (decl) == FUNCTION_DECL)
18981 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
18983 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
18984 if (strcmp (section, ".sdata") == 0
18985 || strcmp (section, ".sdata2") == 0
18986 || strcmp (section, ".sbss") == 0
18987 || strcmp (section, ".sbss2") == 0
18988 || strcmp (section, ".PPC.EMB.sdata0") == 0
18989 || strcmp (section, ".PPC.EMB.sbss0") == 0)
18994 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
18997 && (unsigned HOST_WIDE_INT) size <= g_switch_value
18998 /* If it's not public, and we're not going to reference it there,
18999 there's no need to put it in the small data section. */
19000 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
19007 #endif /* USING_ELFOS_H */
19009 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
19012 rs6000_use_blocks_for_constant_p (enum machine_mode mode, rtx x)
19014 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
19017 /* Return a REG that occurs in ADDR with coefficient 1.
19018 ADDR can be effectively incremented by incrementing REG.
19020 r0 is special and we must not select it as an address
19021 register by this routine since our caller will try to
19022 increment the returned register via an "la" instruction. */
19025 find_addr_reg (rtx addr)
19027 while (GET_CODE (addr) == PLUS)
19029 if (GET_CODE (XEXP (addr, 0)) == REG
19030 && REGNO (XEXP (addr, 0)) != 0)
19031 addr = XEXP (addr, 0);
19032 else if (GET_CODE (XEXP (addr, 1)) == REG
19033 && REGNO (XEXP (addr, 1)) != 0)
19034 addr = XEXP (addr, 1);
19035 else if (CONSTANT_P (XEXP (addr, 0)))
19036 addr = XEXP (addr, 1);
19037 else if (CONSTANT_P (XEXP (addr, 1)))
19038 addr = XEXP (addr, 0);
19040 gcc_unreachable ();
19042 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
19047 rs6000_fatal_bad_address (rtx op)
19049 fatal_insn ("bad address", op);
19054 static tree branch_island_list = 0;
19056 /* Remember to generate a branch island for far calls to the given
19060 add_compiler_branch_island (tree label_name, tree function_name,
19063 tree branch_island = build_tree_list (function_name, label_name);
19064 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
19065 TREE_CHAIN (branch_island) = branch_island_list;
19066 branch_island_list = branch_island;
19069 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
19070 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
19071 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
19072 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
19074 /* Generate far-jump branch islands for everything on the
19075 branch_island_list. Invoked immediately after the last instruction
19076 of the epilogue has been emitted; the branch-islands must be
19077 appended to, and contiguous with, the function body. Mach-O stubs
19078 are generated in machopic_output_stub(). */
19081 macho_branch_islands (void)
19084 tree branch_island;
19086 for (branch_island = branch_island_list;
19088 branch_island = TREE_CHAIN (branch_island))
19090 const char *label =
19091 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
19093 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
19094 char name_buf[512];
19095 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
19096 if (name[0] == '*' || name[0] == '&')
19097 strcpy (name_buf, name+1);
19101 strcpy (name_buf+1, name);
19103 strcpy (tmp_buf, "\n");
19104 strcat (tmp_buf, label);
19105 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19106 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19107 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19108 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19111 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
19112 strcat (tmp_buf, label);
19113 strcat (tmp_buf, "_pic\n");
19114 strcat (tmp_buf, label);
19115 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
19117 strcat (tmp_buf, "\taddis r11,r11,ha16(");
19118 strcat (tmp_buf, name_buf);
19119 strcat (tmp_buf, " - ");
19120 strcat (tmp_buf, label);
19121 strcat (tmp_buf, "_pic)\n");
19123 strcat (tmp_buf, "\tmtlr r0\n");
19125 strcat (tmp_buf, "\taddi r12,r11,lo16(");
19126 strcat (tmp_buf, name_buf);
19127 strcat (tmp_buf, " - ");
19128 strcat (tmp_buf, label);
19129 strcat (tmp_buf, "_pic)\n");
19131 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
19135 strcat (tmp_buf, ":\nlis r12,hi16(");
19136 strcat (tmp_buf, name_buf);
19137 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
19138 strcat (tmp_buf, name_buf);
19139 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
19141 output_asm_insn (tmp_buf, 0);
19142 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19143 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19144 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19145 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19148 branch_island_list = 0;
19151 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
19152 already there or not. */
19155 no_previous_def (tree function_name)
19157 tree branch_island;
19158 for (branch_island = branch_island_list;
19160 branch_island = TREE_CHAIN (branch_island))
19161 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19166 /* GET_PREV_LABEL gets the label name from the previous definition of
19170 get_prev_label (tree function_name)
19172 tree branch_island;
19173 for (branch_island = branch_island_list;
19175 branch_island = TREE_CHAIN (branch_island))
19176 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19177 return BRANCH_ISLAND_LABEL_NAME (branch_island);
19181 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
19182 #define DARWIN_LINKER_GENERATES_ISLANDS 0
19185 /* KEXTs still need branch islands. */
19186 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
19187 || flag_mkernel || flag_apple_kext)
19189 /* INSN is either a function call or a millicode call. It may have an
19190 unconditional jump in its delay slot.
19192 CALL_DEST is the routine we are calling. */
19195 output_call (rtx insn, rtx *operands, int dest_operand_number,
19196 int cookie_operand_number)
19198 static char buf[256];
19199 if (DARWIN_GENERATE_ISLANDS
19200 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
19201 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
19204 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
19206 if (no_previous_def (funname))
19208 int line_number = 0;
19209 rtx label_rtx = gen_label_rtx ();
19210 char *label_buf, temp_buf[256];
19211 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
19212 CODE_LABEL_NUMBER (label_rtx));
19213 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
19214 labelname = get_identifier (label_buf);
19215 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
19217 line_number = NOTE_LINE_NUMBER (insn);
19218 add_compiler_branch_island (labelname, funname, line_number);
19221 labelname = get_prev_label (funname);
19223 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
19224 instruction will reach 'foo', otherwise link as 'bl L42'".
19225 "L42" should be a 'branch island', that will do a far jump to
19226 'foo'. Branch islands are generated in
19227 macho_branch_islands(). */
19228 sprintf (buf, "jbsr %%z%d,%.246s",
19229 dest_operand_number, IDENTIFIER_POINTER (labelname));
19232 sprintf (buf, "bl %%z%d", dest_operand_number);
19236 /* Generate PIC and indirect symbol stubs. */
19239 machopic_output_stub (FILE *file, const char *symb, const char *stub)
19241 unsigned int length;
19242 char *symbol_name, *lazy_ptr_name;
19243 char *local_label_0;
19244 static int label = 0;
19246 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
19247 symb = (*targetm.strip_name_encoding) (symb);
19250 length = strlen (symb);
19251 symbol_name = alloca (length + 32);
19252 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
19254 lazy_ptr_name = alloca (length + 32);
19255 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
19258 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
19260 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
19264 fprintf (file, "\t.align 5\n");
19266 fprintf (file, "%s:\n", stub);
19267 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19270 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
19271 sprintf (local_label_0, "\"L%011d$spb\"", label);
19273 fprintf (file, "\tmflr r0\n");
19274 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
19275 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
19276 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
19277 lazy_ptr_name, local_label_0);
19278 fprintf (file, "\tmtlr r0\n");
19279 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
19280 (TARGET_64BIT ? "ldu" : "lwzu"),
19281 lazy_ptr_name, local_label_0);
19282 fprintf (file, "\tmtctr r12\n");
19283 fprintf (file, "\tbctr\n");
19287 fprintf (file, "\t.align 4\n");
19289 fprintf (file, "%s:\n", stub);
19290 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19292 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
19293 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
19294 (TARGET_64BIT ? "ldu" : "lwzu"),
19296 fprintf (file, "\tmtctr r12\n");
19297 fprintf (file, "\tbctr\n");
19300 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
19301 fprintf (file, "%s:\n", lazy_ptr_name);
19302 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19303 fprintf (file, "%sdyld_stub_binding_helper\n",
19304 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
19307 /* Legitimize PIC addresses. If the address is already
19308 position-independent, we return ORIG. Newly generated
19309 position-independent addresses go into a reg. This is REG if non
19310 zero, otherwise we allocate register(s) as necessary. */
19312 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
19315 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
19320 if (reg == NULL && ! reload_in_progress && ! reload_completed)
19321 reg = gen_reg_rtx (Pmode);
19323 if (GET_CODE (orig) == CONST)
19327 if (GET_CODE (XEXP (orig, 0)) == PLUS
19328 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
19331 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
19333 /* Use a different reg for the intermediate value, as
19334 it will be marked UNCHANGING. */
19335 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
19336 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
19339 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
19342 if (GET_CODE (offset) == CONST_INT)
19344 if (SMALL_INT (offset))
19345 return plus_constant (base, INTVAL (offset));
19346 else if (! reload_in_progress && ! reload_completed)
19347 offset = force_reg (Pmode, offset);
19350 rtx mem = force_const_mem (Pmode, orig);
19351 return machopic_legitimize_pic_address (mem, Pmode, reg);
19354 return gen_rtx_PLUS (Pmode, base, offset);
19357 /* Fall back on generic machopic code. */
19358 return machopic_legitimize_pic_address (orig, mode, reg);
19361 /* Output a .machine directive for the Darwin assembler, and call
19362 the generic start_file routine. */
19365 rs6000_darwin_file_start (void)
19367 static const struct
19373 { "ppc64", "ppc64", MASK_64BIT },
19374 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
19375 { "power4", "ppc970", 0 },
19376 { "G5", "ppc970", 0 },
19377 { "7450", "ppc7450", 0 },
19378 { "7400", "ppc7400", MASK_ALTIVEC },
19379 { "G4", "ppc7400", 0 },
19380 { "750", "ppc750", 0 },
19381 { "740", "ppc750", 0 },
19382 { "G3", "ppc750", 0 },
19383 { "604e", "ppc604e", 0 },
19384 { "604", "ppc604", 0 },
19385 { "603e", "ppc603", 0 },
19386 { "603", "ppc603", 0 },
19387 { "601", "ppc601", 0 },
19388 { NULL, "ppc", 0 } };
19389 const char *cpu_id = "";
19392 rs6000_file_start ();
19393 darwin_file_start ();
19395 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
19396 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
19397 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
19398 && rs6000_select[i].string[0] != '\0')
19399 cpu_id = rs6000_select[i].string;
19401 /* Look through the mapping array. Pick the first name that either
19402 matches the argument, has a bit set in IF_SET that is also set
19403 in the target flags, or has a NULL name. */
19406 while (mapping[i].arg != NULL
19407 && strcmp (mapping[i].arg, cpu_id) != 0
19408 && (mapping[i].if_set & target_flags) == 0)
19411 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
19414 #endif /* TARGET_MACHO */
19418 rs6000_elf_reloc_rw_mask (void)
19422 else if (DEFAULT_ABI == ABI_AIX)
19428 /* Record an element in the table of global constructors. SYMBOL is
19429 a SYMBOL_REF of the function to be called; PRIORITY is a number
19430 between 0 and MAX_INIT_PRIORITY.
19432 This differs from default_named_section_asm_out_constructor in
19433 that we have special handling for -mrelocatable. */
19436 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
19438 const char *section = ".ctors";
19441 if (priority != DEFAULT_INIT_PRIORITY)
19443 sprintf (buf, ".ctors.%.5u",
19444 /* Invert the numbering so the linker puts us in the proper
19445 order; constructors are run from right to left, and the
19446 linker sorts in increasing order. */
19447 MAX_INIT_PRIORITY - priority);
19451 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19452 assemble_align (POINTER_SIZE);
19454 if (TARGET_RELOCATABLE)
19456 fputs ("\t.long (", asm_out_file);
19457 output_addr_const (asm_out_file, symbol);
19458 fputs (")@fixup\n", asm_out_file);
19461 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19465 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
19467 const char *section = ".dtors";
19470 if (priority != DEFAULT_INIT_PRIORITY)
19472 sprintf (buf, ".dtors.%.5u",
19473 /* Invert the numbering so the linker puts us in the proper
19474 order; constructors are run from right to left, and the
19475 linker sorts in increasing order. */
19476 MAX_INIT_PRIORITY - priority);
19480 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19481 assemble_align (POINTER_SIZE);
19483 if (TARGET_RELOCATABLE)
19485 fputs ("\t.long (", asm_out_file);
19486 output_addr_const (asm_out_file, symbol);
19487 fputs (")@fixup\n", asm_out_file);
19490 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19494 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
19498 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
19499 ASM_OUTPUT_LABEL (file, name);
19500 fputs (DOUBLE_INT_ASM_OP, file);
19501 rs6000_output_function_entry (file, name);
19502 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
19505 fputs ("\t.size\t", file);
19506 assemble_name (file, name);
19507 fputs (",24\n\t.type\t.", file);
19508 assemble_name (file, name);
19509 fputs (",@function\n", file);
19510 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
19512 fputs ("\t.globl\t.", file);
19513 assemble_name (file, name);
19518 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19519 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19520 rs6000_output_function_entry (file, name);
19521 fputs (":\n", file);
19525 if (TARGET_RELOCATABLE
19526 && !TARGET_SECURE_PLT
19527 && (get_pool_size () != 0 || current_function_profile)
19532 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
19534 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
19535 fprintf (file, "\t.long ");
19536 assemble_name (file, buf);
19538 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
19539 assemble_name (file, buf);
19543 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19544 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19546 if (DEFAULT_ABI == ABI_AIX)
19548 const char *desc_name, *orig_name;
19550 orig_name = (*targetm.strip_name_encoding) (name);
19551 desc_name = orig_name;
19552 while (*desc_name == '.')
19555 if (TREE_PUBLIC (decl))
19556 fprintf (file, "\t.globl %s\n", desc_name);
19558 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19559 fprintf (file, "%s:\n", desc_name);
19560 fprintf (file, "\t.long %s\n", orig_name);
19561 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
19562 if (DEFAULT_ABI == ABI_AIX)
19563 fputs ("\t.long 0\n", file);
19564 fprintf (file, "\t.previous\n");
19566 ASM_OUTPUT_LABEL (file, name);
19570 rs6000_elf_end_indicate_exec_stack (void)
19573 file_end_indicate_exec_stack ();
19579 rs6000_xcoff_asm_output_anchor (rtx symbol)
19583 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
19584 SYMBOL_REF_BLOCK_OFFSET (symbol));
19585 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
19589 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
19591 fputs (GLOBAL_ASM_OP, stream);
19592 RS6000_OUTPUT_BASENAME (stream, name);
19593 putc ('\n', stream);
19596 /* A get_unnamed_decl callback, used for read-only sections. PTR
19597 points to the section string variable. */
19600 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
19602 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
19603 *(const char *const *) directive);
19606 /* Likewise for read-write sections. */
19609 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
19611 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
19612 *(const char *const *) directive);
19615 /* A get_unnamed_section callback, used for switching to toc_section. */
19618 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
19620 if (TARGET_MINIMAL_TOC)
19622 /* toc_section is always selected at least once from
19623 rs6000_xcoff_file_start, so this is guaranteed to
19624 always be defined once and only once in each file. */
19625 if (!toc_initialized)
19627 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
19628 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
19629 toc_initialized = 1;
19631 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
19632 (TARGET_32BIT ? "" : ",3"));
19635 fputs ("\t.toc\n", asm_out_file);
19638 /* Implement TARGET_ASM_INIT_SECTIONS. */
19641 rs6000_xcoff_asm_init_sections (void)
19643 read_only_data_section
19644 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19645 &xcoff_read_only_section_name);
19647 private_data_section
19648 = get_unnamed_section (SECTION_WRITE,
19649 rs6000_xcoff_output_readwrite_section_asm_op,
19650 &xcoff_private_data_section_name);
19652 read_only_private_data_section
19653 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19654 &xcoff_private_data_section_name);
19657 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
19659 readonly_data_section = read_only_data_section;
19660 exception_section = data_section;
19664 rs6000_xcoff_reloc_rw_mask (void)
19670 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
19671 tree decl ATTRIBUTE_UNUSED)
19674 static const char * const suffix[3] = { "PR", "RO", "RW" };
19676 if (flags & SECTION_CODE)
19678 else if (flags & SECTION_WRITE)
19683 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
19684 (flags & SECTION_CODE) ? "." : "",
19685 name, suffix[smclass], flags & SECTION_ENTSIZE);
19689 rs6000_xcoff_select_section (tree decl, int reloc,
19690 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19692 if (decl_readonly_section (decl, reloc))
19694 if (TREE_PUBLIC (decl))
19695 return read_only_data_section;
19697 return read_only_private_data_section;
19701 if (TREE_PUBLIC (decl))
19702 return data_section;
19704 return private_data_section;
19709 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
19713 /* Use select_section for private and uninitialized data. */
19714 if (!TREE_PUBLIC (decl)
19715 || DECL_COMMON (decl)
19716 || DECL_INITIAL (decl) == NULL_TREE
19717 || DECL_INITIAL (decl) == error_mark_node
19718 || (flag_zero_initialized_in_bss
19719 && initializer_zerop (DECL_INITIAL (decl))))
19722 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
19723 name = (*targetm.strip_name_encoding) (name);
19724 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
19727 /* Select section for constant in constant pool.
19729 On RS/6000, all constants are in the private read-only data area.
19730 However, if this is being placed in the TOC it must be output as a
19734 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
19735 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19737 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
19738 return toc_section;
19740 return read_only_private_data_section;
19743 /* Remove any trailing [DS] or the like from the symbol name. */
19745 static const char *
19746 rs6000_xcoff_strip_name_encoding (const char *name)
19751 len = strlen (name);
19752 if (name[len - 1] == ']')
19753 return ggc_alloc_string (name, len - 4);
19758 /* Section attributes. AIX is always PIC. */
19760 static unsigned int
19761 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
19763 unsigned int align;
19764 unsigned int flags = default_section_type_flags (decl, name, reloc);
19766 /* Align to at least UNIT size. */
19767 if (flags & SECTION_CODE)
19768 align = MIN_UNITS_PER_WORD;
19770 /* Increase alignment of large objects if not already stricter. */
19771 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
19772 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
19773 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
19775 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
19778 /* Output at beginning of assembler file.
19780 Initialize the section names for the RS/6000 at this point.
19782 Specify filename, including full path, to assembler.
19784 We want to go into the TOC section so at least one .toc will be emitted.
19785 Also, in order to output proper .bs/.es pairs, we need at least one static
19786 [RW] section emitted.
19788 Finally, declare mcount when profiling to make the assembler happy. */
19791 rs6000_xcoff_file_start (void)
19793 rs6000_gen_section_name (&xcoff_bss_section_name,
19794 main_input_filename, ".bss_");
19795 rs6000_gen_section_name (&xcoff_private_data_section_name,
19796 main_input_filename, ".rw_");
19797 rs6000_gen_section_name (&xcoff_read_only_section_name,
19798 main_input_filename, ".ro_");
19800 fputs ("\t.file\t", asm_out_file);
19801 output_quoted_string (asm_out_file, main_input_filename);
19802 fputc ('\n', asm_out_file);
19803 if (write_symbols != NO_DEBUG)
19804 switch_to_section (private_data_section);
19805 switch_to_section (text_section);
19807 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
19808 rs6000_file_start ();
19811 /* Output at end of assembler file.
19812 On the RS/6000, referencing data should automatically pull in text. */
19815 rs6000_xcoff_file_end (void)
19817 switch_to_section (text_section);
19818 fputs ("_section_.text:\n", asm_out_file);
19819 switch_to_section (data_section);
19820 fputs (TARGET_32BIT
19821 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
19824 #endif /* TARGET_XCOFF */
19826 /* Compute a (partial) cost for rtx X. Return true if the complete
19827 cost has been computed, and false if subexpressions should be
19828 scanned. In either case, *TOTAL contains the cost result. */
19831 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
19833 enum machine_mode mode = GET_MODE (x);
19837 /* On the RS/6000, if it is valid in the insn, it is free. */
19839 if (((outer_code == SET
19840 || outer_code == PLUS
19841 || outer_code == MINUS)
19842 && (satisfies_constraint_I (x)
19843 || satisfies_constraint_L (x)))
19844 || (outer_code == AND
19845 && (satisfies_constraint_K (x)
19847 ? satisfies_constraint_L (x)
19848 : satisfies_constraint_J (x))
19849 || mask_operand (x, mode)
19851 && mask64_operand (x, DImode))))
19852 || ((outer_code == IOR || outer_code == XOR)
19853 && (satisfies_constraint_K (x)
19855 ? satisfies_constraint_L (x)
19856 : satisfies_constraint_J (x))))
19857 || outer_code == ASHIFT
19858 || outer_code == ASHIFTRT
19859 || outer_code == LSHIFTRT
19860 || outer_code == ROTATE
19861 || outer_code == ROTATERT
19862 || outer_code == ZERO_EXTRACT
19863 || (outer_code == MULT
19864 && satisfies_constraint_I (x))
19865 || ((outer_code == DIV || outer_code == UDIV
19866 || outer_code == MOD || outer_code == UMOD)
19867 && exact_log2 (INTVAL (x)) >= 0)
19868 || (outer_code == COMPARE
19869 && (satisfies_constraint_I (x)
19870 || satisfies_constraint_K (x)))
19871 || (outer_code == EQ
19872 && (satisfies_constraint_I (x)
19873 || satisfies_constraint_K (x)
19875 ? satisfies_constraint_L (x)
19876 : satisfies_constraint_J (x))))
19877 || (outer_code == GTU
19878 && satisfies_constraint_I (x))
19879 || (outer_code == LTU
19880 && satisfies_constraint_P (x)))
19885 else if ((outer_code == PLUS
19886 && reg_or_add_cint_operand (x, VOIDmode))
19887 || (outer_code == MINUS
19888 && reg_or_sub_cint_operand (x, VOIDmode))
19889 || ((outer_code == SET
19890 || outer_code == IOR
19891 || outer_code == XOR)
19893 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
19895 *total = COSTS_N_INSNS (1);
19901 if (mode == DImode && code == CONST_DOUBLE)
19903 if ((outer_code == IOR || outer_code == XOR)
19904 && CONST_DOUBLE_HIGH (x) == 0
19905 && (CONST_DOUBLE_LOW (x)
19906 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
19911 else if ((outer_code == AND && and64_2_operand (x, DImode))
19912 || ((outer_code == SET
19913 || outer_code == IOR
19914 || outer_code == XOR)
19915 && CONST_DOUBLE_HIGH (x) == 0))
19917 *total = COSTS_N_INSNS (1);
19927 /* When optimizing for size, MEM should be slightly more expensive
19928 than generating address, e.g., (plus (reg) (const)).
19929 L1 cache latency is about two instructions. */
19930 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
19938 if (mode == DFmode)
19940 if (GET_CODE (XEXP (x, 0)) == MULT)
19942 /* FNMA accounted in outer NEG. */
19943 if (outer_code == NEG)
19944 *total = rs6000_cost->dmul - rs6000_cost->fp;
19946 *total = rs6000_cost->dmul;
19949 *total = rs6000_cost->fp;
19951 else if (mode == SFmode)
19953 /* FNMA accounted in outer NEG. */
19954 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
19957 *total = rs6000_cost->fp;
19960 *total = COSTS_N_INSNS (1);
19964 if (mode == DFmode)
19966 if (GET_CODE (XEXP (x, 0)) == MULT
19967 || GET_CODE (XEXP (x, 1)) == MULT)
19969 /* FNMA accounted in outer NEG. */
19970 if (outer_code == NEG)
19971 *total = rs6000_cost->dmul - rs6000_cost->fp;
19973 *total = rs6000_cost->dmul;
19976 *total = rs6000_cost->fp;
19978 else if (mode == SFmode)
19980 /* FNMA accounted in outer NEG. */
19981 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
19984 *total = rs6000_cost->fp;
19987 *total = COSTS_N_INSNS (1);
19991 if (GET_CODE (XEXP (x, 1)) == CONST_INT
19992 && satisfies_constraint_I (XEXP (x, 1)))
19994 if (INTVAL (XEXP (x, 1)) >= -256
19995 && INTVAL (XEXP (x, 1)) <= 255)
19996 *total = rs6000_cost->mulsi_const9;
19998 *total = rs6000_cost->mulsi_const;
20000 /* FMA accounted in outer PLUS/MINUS. */
20001 else if ((mode == DFmode || mode == SFmode)
20002 && (outer_code == PLUS || outer_code == MINUS))
20004 else if (mode == DFmode)
20005 *total = rs6000_cost->dmul;
20006 else if (mode == SFmode)
20007 *total = rs6000_cost->fp;
20008 else if (mode == DImode)
20009 *total = rs6000_cost->muldi;
20011 *total = rs6000_cost->mulsi;
20016 if (FLOAT_MODE_P (mode))
20018 *total = mode == DFmode ? rs6000_cost->ddiv
20019 : rs6000_cost->sdiv;
20026 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20027 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
20029 if (code == DIV || code == MOD)
20031 *total = COSTS_N_INSNS (2);
20034 *total = COSTS_N_INSNS (1);
20038 if (GET_MODE (XEXP (x, 1)) == DImode)
20039 *total = rs6000_cost->divdi;
20041 *total = rs6000_cost->divsi;
20043 /* Add in shift and subtract for MOD. */
20044 if (code == MOD || code == UMOD)
20045 *total += COSTS_N_INSNS (2);
20049 *total = COSTS_N_INSNS (4);
20053 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
20064 *total = COSTS_N_INSNS (1);
20072 /* Handle mul_highpart. */
20073 if (outer_code == TRUNCATE
20074 && GET_CODE (XEXP (x, 0)) == MULT)
20076 if (mode == DImode)
20077 *total = rs6000_cost->muldi;
20079 *total = rs6000_cost->mulsi;
20082 else if (outer_code == AND)
20085 *total = COSTS_N_INSNS (1);
20090 if (GET_CODE (XEXP (x, 0)) == MEM)
20093 *total = COSTS_N_INSNS (1);
20099 if (!FLOAT_MODE_P (mode))
20101 *total = COSTS_N_INSNS (1);
20107 case UNSIGNED_FLOAT:
20110 case FLOAT_TRUNCATE:
20111 *total = rs6000_cost->fp;
20115 if (mode == DFmode)
20118 *total = rs6000_cost->fp;
20122 switch (XINT (x, 1))
20125 *total = rs6000_cost->fp;
20137 *total = COSTS_N_INSNS (1);
20140 else if (FLOAT_MODE_P (mode)
20141 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
20143 *total = rs6000_cost->fp;
20151 /* Carry bit requires mode == Pmode.
20152 NEG or PLUS already counted so only add one. */
20154 && (outer_code == NEG || outer_code == PLUS))
20156 *total = COSTS_N_INSNS (1);
20159 if (outer_code == SET)
20161 if (XEXP (x, 1) == const0_rtx)
20163 *total = COSTS_N_INSNS (2);
20166 else if (mode == Pmode)
20168 *total = COSTS_N_INSNS (3);
20177 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
20179 *total = COSTS_N_INSNS (2);
20183 if (outer_code == COMPARE)
20197 /* A C expression returning the cost of moving data from a register of class
20198 CLASS1 to one of CLASS2. */
20201 rs6000_register_move_cost (enum machine_mode mode,
20202 enum reg_class from, enum reg_class to)
20204 /* Moves from/to GENERAL_REGS. */
20205 if (reg_classes_intersect_p (to, GENERAL_REGS)
20206 || reg_classes_intersect_p (from, GENERAL_REGS))
20208 if (! reg_classes_intersect_p (to, GENERAL_REGS))
20211 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
20212 return (rs6000_memory_move_cost (mode, from, 0)
20213 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
20215 /* It's more expensive to move CR_REGS than CR0_REGS because of the
20217 else if (from == CR_REGS)
20221 /* A move will cost one instruction per GPR moved. */
20222 return 2 * hard_regno_nregs[0][mode];
20225 /* Moving between two similar registers is just one instruction. */
20226 else if (reg_classes_intersect_p (to, from))
20227 return (mode == TFmode || mode == TDmode) ? 4 : 2;
20229 /* Everything else has to go through GENERAL_REGS. */
20231 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
20232 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
20235 /* A C expressions returning the cost of moving data of MODE from a register to
20239 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
20240 int in ATTRIBUTE_UNUSED)
20242 if (reg_classes_intersect_p (class, GENERAL_REGS))
20243 return 4 * hard_regno_nregs[0][mode];
20244 else if (reg_classes_intersect_p (class, FLOAT_REGS))
20245 return 4 * hard_regno_nregs[32][mode];
20246 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
20247 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
20249 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
20252 /* Newton-Raphson approximation of single-precision floating point divide n/d.
20253 Assumes no trapping math and finite arguments. */
20256 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
20258 rtx x0, e0, e1, y1, u0, v0, one;
20260 x0 = gen_reg_rtx (SFmode);
20261 e0 = gen_reg_rtx (SFmode);
20262 e1 = gen_reg_rtx (SFmode);
20263 y1 = gen_reg_rtx (SFmode);
20264 u0 = gen_reg_rtx (SFmode);
20265 v0 = gen_reg_rtx (SFmode);
20266 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
20268 /* x0 = 1./d estimate */
20269 emit_insn (gen_rtx_SET (VOIDmode, x0,
20270 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
20272 /* e0 = 1. - d * x0 */
20273 emit_insn (gen_rtx_SET (VOIDmode, e0,
20274 gen_rtx_MINUS (SFmode, one,
20275 gen_rtx_MULT (SFmode, d, x0))));
20276 /* e1 = e0 + e0 * e0 */
20277 emit_insn (gen_rtx_SET (VOIDmode, e1,
20278 gen_rtx_PLUS (SFmode,
20279 gen_rtx_MULT (SFmode, e0, e0), e0)));
20280 /* y1 = x0 + e1 * x0 */
20281 emit_insn (gen_rtx_SET (VOIDmode, y1,
20282 gen_rtx_PLUS (SFmode,
20283 gen_rtx_MULT (SFmode, e1, x0), x0)));
20285 emit_insn (gen_rtx_SET (VOIDmode, u0,
20286 gen_rtx_MULT (SFmode, n, y1)));
20287 /* v0 = n - d * u0 */
20288 emit_insn (gen_rtx_SET (VOIDmode, v0,
20289 gen_rtx_MINUS (SFmode, n,
20290 gen_rtx_MULT (SFmode, d, u0))));
20291 /* res = u0 + v0 * y1 */
20292 emit_insn (gen_rtx_SET (VOIDmode, res,
20293 gen_rtx_PLUS (SFmode,
20294 gen_rtx_MULT (SFmode, v0, y1), u0)));
20297 /* Newton-Raphson approximation of double-precision floating point divide n/d.
20298 Assumes no trapping math and finite arguments. */
20301 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
20303 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
20305 x0 = gen_reg_rtx (DFmode);
20306 e0 = gen_reg_rtx (DFmode);
20307 e1 = gen_reg_rtx (DFmode);
20308 e2 = gen_reg_rtx (DFmode);
20309 y1 = gen_reg_rtx (DFmode);
20310 y2 = gen_reg_rtx (DFmode);
20311 y3 = gen_reg_rtx (DFmode);
20312 u0 = gen_reg_rtx (DFmode);
20313 v0 = gen_reg_rtx (DFmode);
20314 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
20316 /* x0 = 1./d estimate */
20317 emit_insn (gen_rtx_SET (VOIDmode, x0,
20318 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
20320 /* e0 = 1. - d * x0 */
20321 emit_insn (gen_rtx_SET (VOIDmode, e0,
20322 gen_rtx_MINUS (DFmode, one,
20323 gen_rtx_MULT (SFmode, d, x0))));
20324 /* y1 = x0 + e0 * x0 */
20325 emit_insn (gen_rtx_SET (VOIDmode, y1,
20326 gen_rtx_PLUS (DFmode,
20327 gen_rtx_MULT (DFmode, e0, x0), x0)));
20329 emit_insn (gen_rtx_SET (VOIDmode, e1,
20330 gen_rtx_MULT (DFmode, e0, e0)));
20331 /* y2 = y1 + e1 * y1 */
20332 emit_insn (gen_rtx_SET (VOIDmode, y2,
20333 gen_rtx_PLUS (DFmode,
20334 gen_rtx_MULT (DFmode, e1, y1), y1)));
20336 emit_insn (gen_rtx_SET (VOIDmode, e2,
20337 gen_rtx_MULT (DFmode, e1, e1)));
20338 /* y3 = y2 + e2 * y2 */
20339 emit_insn (gen_rtx_SET (VOIDmode, y3,
20340 gen_rtx_PLUS (DFmode,
20341 gen_rtx_MULT (DFmode, e2, y2), y2)));
20343 emit_insn (gen_rtx_SET (VOIDmode, u0,
20344 gen_rtx_MULT (DFmode, n, y3)));
20345 /* v0 = n - d * u0 */
20346 emit_insn (gen_rtx_SET (VOIDmode, v0,
20347 gen_rtx_MINUS (DFmode, n,
20348 gen_rtx_MULT (DFmode, d, u0))));
20349 /* res = u0 + v0 * y3 */
20350 emit_insn (gen_rtx_SET (VOIDmode, res,
20351 gen_rtx_PLUS (DFmode,
20352 gen_rtx_MULT (DFmode, v0, y3), u0)));
20356 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
20357 target, and SRC is the argument operand. */
20360 rs6000_emit_popcount (rtx dst, rtx src)
20362 enum machine_mode mode = GET_MODE (dst);
20365 tmp1 = gen_reg_rtx (mode);
20367 if (mode == SImode)
20369 emit_insn (gen_popcntbsi2 (tmp1, src));
20370 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
20372 tmp2 = force_reg (SImode, tmp2);
20373 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
20377 emit_insn (gen_popcntbdi2 (tmp1, src));
20378 tmp2 = expand_mult (DImode, tmp1,
20379 GEN_INT ((HOST_WIDE_INT)
20380 0x01010101 << 32 | 0x01010101),
20382 tmp2 = force_reg (DImode, tmp2);
20383 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
20388 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
20389 target, and SRC is the argument operand. */
20392 rs6000_emit_parity (rtx dst, rtx src)
20394 enum machine_mode mode = GET_MODE (dst);
20397 tmp = gen_reg_rtx (mode);
20398 if (mode == SImode)
20400 /* Is mult+shift >= shift+xor+shift+xor? */
20401 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
20403 rtx tmp1, tmp2, tmp3, tmp4;
20405 tmp1 = gen_reg_rtx (SImode);
20406 emit_insn (gen_popcntbsi2 (tmp1, src));
20408 tmp2 = gen_reg_rtx (SImode);
20409 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
20410 tmp3 = gen_reg_rtx (SImode);
20411 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
20413 tmp4 = gen_reg_rtx (SImode);
20414 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
20415 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
20418 rs6000_emit_popcount (tmp, src);
20419 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
20423 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
20424 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
20426 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
20428 tmp1 = gen_reg_rtx (DImode);
20429 emit_insn (gen_popcntbdi2 (tmp1, src));
20431 tmp2 = gen_reg_rtx (DImode);
20432 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
20433 tmp3 = gen_reg_rtx (DImode);
20434 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
20436 tmp4 = gen_reg_rtx (DImode);
20437 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
20438 tmp5 = gen_reg_rtx (DImode);
20439 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
20441 tmp6 = gen_reg_rtx (DImode);
20442 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
20443 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
20446 rs6000_emit_popcount (tmp, src);
20447 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
20451 /* Return an RTX representing where to find the function value of a
20452 function returning MODE. */
20454 rs6000_complex_function_value (enum machine_mode mode)
20456 unsigned int regno;
20458 enum machine_mode inner = GET_MODE_INNER (mode);
20459 unsigned int inner_bytes = GET_MODE_SIZE (inner);
20461 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
20462 regno = FP_ARG_RETURN;
20465 regno = GP_ARG_RETURN;
20467 /* 32-bit is OK since it'll go in r3/r4. */
20468 if (TARGET_32BIT && inner_bytes >= 4)
20469 return gen_rtx_REG (mode, regno);
20472 if (inner_bytes >= 8)
20473 return gen_rtx_REG (mode, regno);
20475 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
20477 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
20478 GEN_INT (inner_bytes));
20479 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
20482 /* Define how to find the value returned by a function.
20483 VALTYPE is the data type of the value (as a tree).
20484 If the precise function being called is known, FUNC is its FUNCTION_DECL;
20485 otherwise, FUNC is 0.
20487 On the SPE, both FPs and vectors are returned in r3.
20489 On RS/6000 an integer value is in r3 and a floating-point value is in
20490 fp1, unless -msoft-float. */
20493 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
20495 enum machine_mode mode;
20496 unsigned int regno;
20498 /* Special handling for structs in darwin64. */
20499 if (rs6000_darwin64_abi
20500 && TYPE_MODE (valtype) == BLKmode
20501 && TREE_CODE (valtype) == RECORD_TYPE
20502 && int_size_in_bytes (valtype) > 0)
20504 CUMULATIVE_ARGS valcum;
20508 valcum.fregno = FP_ARG_MIN_REG;
20509 valcum.vregno = ALTIVEC_ARG_MIN_REG;
20510 /* Do a trial code generation as if this were going to be passed as
20511 an argument; if any part goes in memory, we return NULL. */
20512 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
20515 /* Otherwise fall through to standard ABI rules. */
20518 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
20520 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20521 return gen_rtx_PARALLEL (DImode,
20523 gen_rtx_EXPR_LIST (VOIDmode,
20524 gen_rtx_REG (SImode, GP_ARG_RETURN),
20526 gen_rtx_EXPR_LIST (VOIDmode,
20527 gen_rtx_REG (SImode,
20528 GP_ARG_RETURN + 1),
20531 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
20533 return gen_rtx_PARALLEL (DCmode,
20535 gen_rtx_EXPR_LIST (VOIDmode,
20536 gen_rtx_REG (SImode, GP_ARG_RETURN),
20538 gen_rtx_EXPR_LIST (VOIDmode,
20539 gen_rtx_REG (SImode,
20540 GP_ARG_RETURN + 1),
20542 gen_rtx_EXPR_LIST (VOIDmode,
20543 gen_rtx_REG (SImode,
20544 GP_ARG_RETURN + 2),
20546 gen_rtx_EXPR_LIST (VOIDmode,
20547 gen_rtx_REG (SImode,
20548 GP_ARG_RETURN + 3),
20552 mode = TYPE_MODE (valtype);
20553 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
20554 || POINTER_TYPE_P (valtype))
20555 mode = TARGET_32BIT ? SImode : DImode;
20557 if (DECIMAL_FLOAT_MODE_P (mode))
20559 if (TARGET_HARD_FLOAT && TARGET_FPRS)
20564 gcc_unreachable ();
20566 regno = GP_ARG_RETURN;
20569 regno = FP_ARG_RETURN;
20572 /* Use f2:f3 specified by the ABI. */
20573 regno = FP_ARG_RETURN + 1;
20578 regno = GP_ARG_RETURN;
20580 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
20581 regno = FP_ARG_RETURN;
20582 else if (TREE_CODE (valtype) == COMPLEX_TYPE
20583 && targetm.calls.split_complex_arg)
20584 return rs6000_complex_function_value (mode);
20585 else if (TREE_CODE (valtype) == VECTOR_TYPE
20586 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
20587 && ALTIVEC_VECTOR_MODE (mode))
20588 regno = ALTIVEC_ARG_RETURN;
20589 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20590 && (mode == DFmode || mode == DCmode
20591 || mode == TFmode || mode == TCmode))
20592 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20594 regno = GP_ARG_RETURN;
20596 return gen_rtx_REG (mode, regno);
20599 /* Define how to find the value returned by a library function
20600 assuming the value has mode MODE. */
20602 rs6000_libcall_value (enum machine_mode mode)
20604 unsigned int regno;
20606 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
20608 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20609 return gen_rtx_PARALLEL (DImode,
20611 gen_rtx_EXPR_LIST (VOIDmode,
20612 gen_rtx_REG (SImode, GP_ARG_RETURN),
20614 gen_rtx_EXPR_LIST (VOIDmode,
20615 gen_rtx_REG (SImode,
20616 GP_ARG_RETURN + 1),
20620 if (DECIMAL_FLOAT_MODE_P (mode))
20622 if (TARGET_HARD_FLOAT && TARGET_FPRS)
20627 gcc_unreachable ();
20629 regno = GP_ARG_RETURN;
20632 regno = FP_ARG_RETURN;
20635 /* Use f2:f3 specified by the ABI. */
20636 regno = FP_ARG_RETURN + 1;
20641 regno = GP_ARG_RETURN;
20643 else if (SCALAR_FLOAT_MODE_P (mode)
20644 && TARGET_HARD_FLOAT && TARGET_FPRS)
20645 regno = FP_ARG_RETURN;
20646 else if (ALTIVEC_VECTOR_MODE (mode)
20647 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
20648 regno = ALTIVEC_ARG_RETURN;
20649 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
20650 return rs6000_complex_function_value (mode);
20651 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20652 && (mode == DFmode || mode == DCmode
20653 || mode == TFmode || mode == TCmode))
20654 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20656 regno = GP_ARG_RETURN;
20658 return gen_rtx_REG (mode, regno);
20661 /* Define the offset between two registers, FROM to be eliminated and its
20662 replacement TO, at the start of a routine. */
20664 rs6000_initial_elimination_offset (int from, int to)
20666 rs6000_stack_t *info = rs6000_stack_info ();
20667 HOST_WIDE_INT offset;
20669 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20670 offset = info->push_p ? 0 : -info->total_size;
20671 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20673 offset = info->push_p ? 0 : -info->total_size;
20674 if (FRAME_GROWS_DOWNWARD)
20675 offset += info->fixed_size + info->vars_size + info->parm_size;
20677 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20678 offset = FRAME_GROWS_DOWNWARD
20679 ? info->fixed_size + info->vars_size + info->parm_size
20681 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20682 offset = info->total_size;
20683 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20684 offset = info->push_p ? info->total_size : 0;
20685 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
20688 gcc_unreachable ();
20693 /* Return true if TYPE is a SPE or AltiVec opaque type. */
20696 rs6000_is_opaque_type (tree type)
20698 return (type == opaque_V2SI_type_node
20699 || type == opaque_V2SF_type_node
20700 || type == opaque_p_V2SI_type_node
20701 || type == opaque_V4SI_type_node);
20705 rs6000_dwarf_register_span (rtx reg)
20710 && (SPE_VECTOR_MODE (GET_MODE (reg))
20711 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
20716 regno = REGNO (reg);
20718 /* The duality of the SPE register size wreaks all kinds of havoc.
20719 This is a way of distinguishing r0 in 32-bits from r0 in
20722 gen_rtx_PARALLEL (VOIDmode,
20725 gen_rtx_REG (SImode, regno + 1200),
20726 gen_rtx_REG (SImode, regno))
20728 gen_rtx_REG (SImode, regno),
20729 gen_rtx_REG (SImode, regno + 1200)));
20732 /* Fill in sizes for SPE register high parts in table used by unwinder. */
20735 rs6000_init_dwarf_reg_sizes_extra (tree address)
20740 enum machine_mode mode = TYPE_MODE (char_type_node);
20741 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, 0);
20742 rtx mem = gen_rtx_MEM (BLKmode, addr);
20743 rtx value = gen_int_mode (4, mode);
20745 for (i = 1201; i < 1232; i++)
20747 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
20748 HOST_WIDE_INT offset
20749 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
20751 emit_move_insn (adjust_address (mem, mode, offset), value);
20756 /* Map internal gcc register numbers to DWARF2 register numbers. */
20759 rs6000_dbx_register_number (unsigned int regno)
20761 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
20763 if (regno == MQ_REGNO)
20765 if (regno == LINK_REGISTER_REGNUM)
20767 if (regno == COUNT_REGISTER_REGNUM)
20769 if (CR_REGNO_P (regno))
20770 return regno - CR0_REGNO + 86;
20771 if (regno == XER_REGNO)
20773 if (ALTIVEC_REGNO_P (regno))
20774 return regno - FIRST_ALTIVEC_REGNO + 1124;
20775 if (regno == VRSAVE_REGNO)
20777 if (regno == VSCR_REGNO)
20779 if (regno == SPE_ACC_REGNO)
20781 if (regno == SPEFSCR_REGNO)
20783 /* SPE high reg number. We get these values of regno from
20784 rs6000_dwarf_register_span. */
20785 gcc_assert (regno >= 1200 && regno < 1232);
20789 /* target hook eh_return_filter_mode */
20790 static enum machine_mode
20791 rs6000_eh_return_filter_mode (void)
20793 return TARGET_32BIT ? SImode : word_mode;
20796 /* Target hook for scalar_mode_supported_p. */
20798 rs6000_scalar_mode_supported_p (enum machine_mode mode)
20800 if (DECIMAL_FLOAT_MODE_P (mode))
20803 return default_scalar_mode_supported_p (mode);
20806 /* Target hook for vector_mode_supported_p. */
20808 rs6000_vector_mode_supported_p (enum machine_mode mode)
20811 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
20814 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
20821 /* Target hook for invalid_arg_for_unprototyped_fn. */
20822 static const char *
20823 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
20825 return (!rs6000_darwin64_abi
20827 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
20828 && (funcdecl == NULL_TREE
20829 || (TREE_CODE (funcdecl) == FUNCTION_DECL
20830 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
20831 ? N_("AltiVec argument passed to unprototyped function")
20835 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
20836 setup by using __stack_chk_fail_local hidden function instead of
20837 calling __stack_chk_fail directly. Otherwise it is better to call
20838 __stack_chk_fail directly. */
20841 rs6000_stack_protect_fail (void)
20843 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
20844 ? default_hidden_stack_protect_fail ()
20845 : default_external_stack_protect_fail ();
20848 #include "gt-rs6000.h"