1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
45 #include "integrate.h"
51 #include "target-def.h"
52 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
56 #include "tree-gimple.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack {
76 int first_gp_reg_save; /* first callee saved GP register used */
77 int first_fp_reg_save; /* first callee saved FP register used */
78 int first_altivec_reg_save; /* first callee saved AltiVec register used */
79 int lr_save_p; /* true if the link reg needs to be saved */
80 int cr_save_p; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask; /* mask of vec registers to save */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset; /* offset to save the varargs registers */
95 int ehrd_offset; /* offset to EH return data */
96 int reg_size; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
111 int spe_64bit_regs_used;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct machine_function GTY(())
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset;
131 /* Target cpu type */
133 enum processor_type rs6000_cpu;
134 struct rs6000_cpu_select rs6000_select[3] =
136 /* switch name, tune arch */
137 { (const char *)0, "--with-cpu=", 1, 1 },
138 { (const char *)0, "-mcpu=", 1, 1 },
139 { (const char *)0, "-mtune=", 1, 0 },
142 /* Always emit branch hint bits. */
143 static GTY(()) bool rs6000_always_hint;
145 /* Schedule instructions for group formation. */
146 static GTY(()) bool rs6000_sched_groups;
148 /* Support for -msched-costly-dep option. */
149 const char *rs6000_sched_costly_dep_str;
150 enum rs6000_dependence_cost rs6000_sched_costly_dep;
152 /* Support for -minsert-sched-nops option. */
153 const char *rs6000_sched_insert_nops_str;
154 enum rs6000_nop_insertion rs6000_sched_insert_nops;
156 /* Support targetm.vectorize.builtin_mask_for_load. */
157 static GTY(()) tree altivec_builtin_mask_for_load;
159 /* Size of long double. */
160 int rs6000_long_double_type_size;
162 /* IEEE quad extended precision long double. */
165 /* Whether -mabi=altivec has appeared. */
166 int rs6000_altivec_abi;
168 /* Nonzero if we want SPE ABI extensions. */
171 /* Nonzero if floating point operations are done in the GPRs. */
172 int rs6000_float_gprs = 0;
174 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
175 int rs6000_darwin64_abi;
177 /* Set to nonzero once AIX common-mode calls have been defined. */
178 static GTY(()) int common_mode_defined;
180 /* Save information from a "cmpxx" operation until the branch or scc is
182 rtx rs6000_compare_op0, rs6000_compare_op1;
183 int rs6000_compare_fp_p;
185 /* Label number of label created for -mrelocatable, to call to so we can
186 get the address of the GOT section */
187 int rs6000_pic_labelno;
190 /* Which abi to adhere to */
191 const char *rs6000_abi_name;
193 /* Semantics of the small data area */
194 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
196 /* Which small data model to use */
197 const char *rs6000_sdata_name = (char *)0;
199 /* Counter for labels which are to be placed in .fixup. */
200 int fixuplabelno = 0;
203 /* Bit size of immediate TLS offsets and string from which it is decoded. */
204 int rs6000_tls_size = 32;
205 const char *rs6000_tls_size_string;
207 /* ABI enumeration available for subtarget to use. */
208 enum rs6000_abi rs6000_current_abi;
210 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
214 const char *rs6000_debug_name;
215 int rs6000_debug_stack; /* debug stack applications */
216 int rs6000_debug_arg; /* debug argument handling */
218 /* Value is TRUE if register/mode pair is acceptable. */
219 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
221 /* Built in types. */
223 tree rs6000_builtin_types[RS6000_BTI_MAX];
224 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
226 const char *rs6000_traceback_name;
228 traceback_default = 0,
234 /* Flag to say the TOC is initialized */
236 char toc_label_name[10];
238 static GTY(()) section *read_only_data_section;
239 static GTY(()) section *private_data_section;
240 static GTY(()) section *read_only_private_data_section;
241 static GTY(()) section *sdata2_section;
242 static GTY(()) section *toc_section;
244 /* Control alignment for fields within structures. */
245 /* String from -malign-XXXXX. */
246 int rs6000_alignment_flags;
248 /* True for any options that were explicitly set. */
250 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
251 bool alignment; /* True if -malign- was used. */
252 bool abi; /* True if -mabi=spe/nospe was used. */
253 bool spe; /* True if -mspe= was used. */
254 bool float_gprs; /* True if -mfloat-gprs= was used. */
255 bool isel; /* True if -misel was used. */
256 bool long_double; /* True if -mlong-double- was used. */
257 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
258 } rs6000_explicit_options;
260 struct builtin_description
262 /* mask is not const because we're going to alter it below. This
263 nonsense will go away when we rewrite the -march infrastructure
264 to give us more target flag bits. */
266 const enum insn_code icode;
267 const char *const name;
268 const enum rs6000_builtins code;
271 /* Target cpu costs. */
273 struct processor_costs {
274 const int mulsi; /* cost of SImode multiplication. */
275 const int mulsi_const; /* cost of SImode multiplication by constant. */
276 const int mulsi_const9; /* cost of SImode mult by short constant. */
277 const int muldi; /* cost of DImode multiplication. */
278 const int divsi; /* cost of SImode division. */
279 const int divdi; /* cost of DImode division. */
280 const int fp; /* cost of simple SFmode and DFmode insns. */
281 const int dmul; /* cost of DFmode multiplication (and fmadd). */
282 const int sdiv; /* cost of SFmode division (fdivs). */
283 const int ddiv; /* cost of DFmode division (fdiv). */
286 const struct processor_costs *rs6000_cost;
288 /* Processor costs (relative to an add) */
290 /* Instruction size costs on 32bit processors. */
292 struct processor_costs size32_cost = {
293 COSTS_N_INSNS (1), /* mulsi */
294 COSTS_N_INSNS (1), /* mulsi_const */
295 COSTS_N_INSNS (1), /* mulsi_const9 */
296 COSTS_N_INSNS (1), /* muldi */
297 COSTS_N_INSNS (1), /* divsi */
298 COSTS_N_INSNS (1), /* divdi */
299 COSTS_N_INSNS (1), /* fp */
300 COSTS_N_INSNS (1), /* dmul */
301 COSTS_N_INSNS (1), /* sdiv */
302 COSTS_N_INSNS (1), /* ddiv */
305 /* Instruction size costs on 64bit processors. */
307 struct processor_costs size64_cost = {
308 COSTS_N_INSNS (1), /* mulsi */
309 COSTS_N_INSNS (1), /* mulsi_const */
310 COSTS_N_INSNS (1), /* mulsi_const9 */
311 COSTS_N_INSNS (1), /* muldi */
312 COSTS_N_INSNS (1), /* divsi */
313 COSTS_N_INSNS (1), /* divdi */
314 COSTS_N_INSNS (1), /* fp */
315 COSTS_N_INSNS (1), /* dmul */
316 COSTS_N_INSNS (1), /* sdiv */
317 COSTS_N_INSNS (1), /* ddiv */
320 /* Instruction costs on RIOS1 processors. */
322 struct processor_costs rios1_cost = {
323 COSTS_N_INSNS (5), /* mulsi */
324 COSTS_N_INSNS (4), /* mulsi_const */
325 COSTS_N_INSNS (3), /* mulsi_const9 */
326 COSTS_N_INSNS (5), /* muldi */
327 COSTS_N_INSNS (19), /* divsi */
328 COSTS_N_INSNS (19), /* divdi */
329 COSTS_N_INSNS (2), /* fp */
330 COSTS_N_INSNS (2), /* dmul */
331 COSTS_N_INSNS (19), /* sdiv */
332 COSTS_N_INSNS (19), /* ddiv */
335 /* Instruction costs on RIOS2 processors. */
337 struct processor_costs rios2_cost = {
338 COSTS_N_INSNS (2), /* mulsi */
339 COSTS_N_INSNS (2), /* mulsi_const */
340 COSTS_N_INSNS (2), /* mulsi_const9 */
341 COSTS_N_INSNS (2), /* muldi */
342 COSTS_N_INSNS (13), /* divsi */
343 COSTS_N_INSNS (13), /* divdi */
344 COSTS_N_INSNS (2), /* fp */
345 COSTS_N_INSNS (2), /* dmul */
346 COSTS_N_INSNS (17), /* sdiv */
347 COSTS_N_INSNS (17), /* ddiv */
350 /* Instruction costs on RS64A processors. */
352 struct processor_costs rs64a_cost = {
353 COSTS_N_INSNS (20), /* mulsi */
354 COSTS_N_INSNS (12), /* mulsi_const */
355 COSTS_N_INSNS (8), /* mulsi_const9 */
356 COSTS_N_INSNS (34), /* muldi */
357 COSTS_N_INSNS (65), /* divsi */
358 COSTS_N_INSNS (67), /* divdi */
359 COSTS_N_INSNS (4), /* fp */
360 COSTS_N_INSNS (4), /* dmul */
361 COSTS_N_INSNS (31), /* sdiv */
362 COSTS_N_INSNS (31), /* ddiv */
365 /* Instruction costs on MPCCORE processors. */
367 struct processor_costs mpccore_cost = {
368 COSTS_N_INSNS (2), /* mulsi */
369 COSTS_N_INSNS (2), /* mulsi_const */
370 COSTS_N_INSNS (2), /* mulsi_const9 */
371 COSTS_N_INSNS (2), /* muldi */
372 COSTS_N_INSNS (6), /* divsi */
373 COSTS_N_INSNS (6), /* divdi */
374 COSTS_N_INSNS (4), /* fp */
375 COSTS_N_INSNS (5), /* dmul */
376 COSTS_N_INSNS (10), /* sdiv */
377 COSTS_N_INSNS (17), /* ddiv */
380 /* Instruction costs on PPC403 processors. */
382 struct processor_costs ppc403_cost = {
383 COSTS_N_INSNS (4), /* mulsi */
384 COSTS_N_INSNS (4), /* mulsi_const */
385 COSTS_N_INSNS (4), /* mulsi_const9 */
386 COSTS_N_INSNS (4), /* muldi */
387 COSTS_N_INSNS (33), /* divsi */
388 COSTS_N_INSNS (33), /* divdi */
389 COSTS_N_INSNS (11), /* fp */
390 COSTS_N_INSNS (11), /* dmul */
391 COSTS_N_INSNS (11), /* sdiv */
392 COSTS_N_INSNS (11), /* ddiv */
395 /* Instruction costs on PPC405 processors. */
397 struct processor_costs ppc405_cost = {
398 COSTS_N_INSNS (5), /* mulsi */
399 COSTS_N_INSNS (4), /* mulsi_const */
400 COSTS_N_INSNS (3), /* mulsi_const9 */
401 COSTS_N_INSNS (5), /* muldi */
402 COSTS_N_INSNS (35), /* divsi */
403 COSTS_N_INSNS (35), /* divdi */
404 COSTS_N_INSNS (11), /* fp */
405 COSTS_N_INSNS (11), /* dmul */
406 COSTS_N_INSNS (11), /* sdiv */
407 COSTS_N_INSNS (11), /* ddiv */
410 /* Instruction costs on PPC440 processors. */
412 struct processor_costs ppc440_cost = {
413 COSTS_N_INSNS (3), /* mulsi */
414 COSTS_N_INSNS (2), /* mulsi_const */
415 COSTS_N_INSNS (2), /* mulsi_const9 */
416 COSTS_N_INSNS (3), /* muldi */
417 COSTS_N_INSNS (34), /* divsi */
418 COSTS_N_INSNS (34), /* divdi */
419 COSTS_N_INSNS (5), /* fp */
420 COSTS_N_INSNS (5), /* dmul */
421 COSTS_N_INSNS (19), /* sdiv */
422 COSTS_N_INSNS (33), /* ddiv */
425 /* Instruction costs on PPC601 processors. */
427 struct processor_costs ppc601_cost = {
428 COSTS_N_INSNS (5), /* mulsi */
429 COSTS_N_INSNS (5), /* mulsi_const */
430 COSTS_N_INSNS (5), /* mulsi_const9 */
431 COSTS_N_INSNS (5), /* muldi */
432 COSTS_N_INSNS (36), /* divsi */
433 COSTS_N_INSNS (36), /* divdi */
434 COSTS_N_INSNS (4), /* fp */
435 COSTS_N_INSNS (5), /* dmul */
436 COSTS_N_INSNS (17), /* sdiv */
437 COSTS_N_INSNS (31), /* ddiv */
440 /* Instruction costs on PPC603 processors. */
442 struct processor_costs ppc603_cost = {
443 COSTS_N_INSNS (5), /* mulsi */
444 COSTS_N_INSNS (3), /* mulsi_const */
445 COSTS_N_INSNS (2), /* mulsi_const9 */
446 COSTS_N_INSNS (5), /* muldi */
447 COSTS_N_INSNS (37), /* divsi */
448 COSTS_N_INSNS (37), /* divdi */
449 COSTS_N_INSNS (3), /* fp */
450 COSTS_N_INSNS (4), /* dmul */
451 COSTS_N_INSNS (18), /* sdiv */
452 COSTS_N_INSNS (33), /* ddiv */
455 /* Instruction costs on PPC604 processors. */
457 struct processor_costs ppc604_cost = {
458 COSTS_N_INSNS (4), /* mulsi */
459 COSTS_N_INSNS (4), /* mulsi_const */
460 COSTS_N_INSNS (4), /* mulsi_const9 */
461 COSTS_N_INSNS (4), /* muldi */
462 COSTS_N_INSNS (20), /* divsi */
463 COSTS_N_INSNS (20), /* divdi */
464 COSTS_N_INSNS (3), /* fp */
465 COSTS_N_INSNS (3), /* dmul */
466 COSTS_N_INSNS (18), /* sdiv */
467 COSTS_N_INSNS (32), /* ddiv */
470 /* Instruction costs on PPC604e processors. */
472 struct processor_costs ppc604e_cost = {
473 COSTS_N_INSNS (2), /* mulsi */
474 COSTS_N_INSNS (2), /* mulsi_const */
475 COSTS_N_INSNS (2), /* mulsi_const9 */
476 COSTS_N_INSNS (2), /* muldi */
477 COSTS_N_INSNS (20), /* divsi */
478 COSTS_N_INSNS (20), /* divdi */
479 COSTS_N_INSNS (3), /* fp */
480 COSTS_N_INSNS (3), /* dmul */
481 COSTS_N_INSNS (18), /* sdiv */
482 COSTS_N_INSNS (32), /* ddiv */
485 /* Instruction costs on PPC620 processors. */
487 struct processor_costs ppc620_cost = {
488 COSTS_N_INSNS (5), /* mulsi */
489 COSTS_N_INSNS (4), /* mulsi_const */
490 COSTS_N_INSNS (3), /* mulsi_const9 */
491 COSTS_N_INSNS (7), /* muldi */
492 COSTS_N_INSNS (21), /* divsi */
493 COSTS_N_INSNS (37), /* divdi */
494 COSTS_N_INSNS (3), /* fp */
495 COSTS_N_INSNS (3), /* dmul */
496 COSTS_N_INSNS (18), /* sdiv */
497 COSTS_N_INSNS (32), /* ddiv */
500 /* Instruction costs on PPC630 processors. */
502 struct processor_costs ppc630_cost = {
503 COSTS_N_INSNS (5), /* mulsi */
504 COSTS_N_INSNS (4), /* mulsi_const */
505 COSTS_N_INSNS (3), /* mulsi_const9 */
506 COSTS_N_INSNS (7), /* muldi */
507 COSTS_N_INSNS (21), /* divsi */
508 COSTS_N_INSNS (37), /* divdi */
509 COSTS_N_INSNS (3), /* fp */
510 COSTS_N_INSNS (3), /* dmul */
511 COSTS_N_INSNS (17), /* sdiv */
512 COSTS_N_INSNS (21), /* ddiv */
515 /* Instruction costs on PPC750 and PPC7400 processors. */
517 struct processor_costs ppc750_cost = {
518 COSTS_N_INSNS (5), /* mulsi */
519 COSTS_N_INSNS (3), /* mulsi_const */
520 COSTS_N_INSNS (2), /* mulsi_const9 */
521 COSTS_N_INSNS (5), /* muldi */
522 COSTS_N_INSNS (17), /* divsi */
523 COSTS_N_INSNS (17), /* divdi */
524 COSTS_N_INSNS (3), /* fp */
525 COSTS_N_INSNS (3), /* dmul */
526 COSTS_N_INSNS (17), /* sdiv */
527 COSTS_N_INSNS (31), /* ddiv */
530 /* Instruction costs on PPC7450 processors. */
532 struct processor_costs ppc7450_cost = {
533 COSTS_N_INSNS (4), /* mulsi */
534 COSTS_N_INSNS (3), /* mulsi_const */
535 COSTS_N_INSNS (3), /* mulsi_const9 */
536 COSTS_N_INSNS (4), /* muldi */
537 COSTS_N_INSNS (23), /* divsi */
538 COSTS_N_INSNS (23), /* divdi */
539 COSTS_N_INSNS (5), /* fp */
540 COSTS_N_INSNS (5), /* dmul */
541 COSTS_N_INSNS (21), /* sdiv */
542 COSTS_N_INSNS (35), /* ddiv */
545 /* Instruction costs on PPC8540 processors. */
547 struct processor_costs ppc8540_cost = {
548 COSTS_N_INSNS (4), /* mulsi */
549 COSTS_N_INSNS (4), /* mulsi_const */
550 COSTS_N_INSNS (4), /* mulsi_const9 */
551 COSTS_N_INSNS (4), /* muldi */
552 COSTS_N_INSNS (19), /* divsi */
553 COSTS_N_INSNS (19), /* divdi */
554 COSTS_N_INSNS (4), /* fp */
555 COSTS_N_INSNS (4), /* dmul */
556 COSTS_N_INSNS (29), /* sdiv */
557 COSTS_N_INSNS (29), /* ddiv */
560 /* Instruction costs on POWER4 and POWER5 processors. */
562 struct processor_costs power4_cost = {
563 COSTS_N_INSNS (3), /* mulsi */
564 COSTS_N_INSNS (2), /* mulsi_const */
565 COSTS_N_INSNS (2), /* mulsi_const9 */
566 COSTS_N_INSNS (4), /* muldi */
567 COSTS_N_INSNS (18), /* divsi */
568 COSTS_N_INSNS (34), /* divdi */
569 COSTS_N_INSNS (3), /* fp */
570 COSTS_N_INSNS (3), /* dmul */
571 COSTS_N_INSNS (17), /* sdiv */
572 COSTS_N_INSNS (17), /* ddiv */
576 static bool rs6000_function_ok_for_sibcall (tree, tree);
577 static const char *rs6000_invalid_within_doloop (rtx);
578 static rtx rs6000_generate_compare (enum rtx_code);
579 static void rs6000_maybe_dead (rtx);
580 static void rs6000_emit_stack_tie (void);
581 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
582 static rtx spe_synthesize_frame_save (rtx);
583 static bool spe_func_has_64bit_regs_p (void);
584 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
586 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
587 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
588 static unsigned rs6000_hash_constant (rtx);
589 static unsigned toc_hash_function (const void *);
590 static int toc_hash_eq (const void *, const void *);
591 static int constant_pool_expr_1 (rtx, int *, int *);
592 static bool constant_pool_expr_p (rtx);
593 static bool legitimate_small_data_p (enum machine_mode, rtx);
594 static bool legitimate_indexed_address_p (rtx, int);
595 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
596 static struct machine_function * rs6000_init_machine_status (void);
597 static bool rs6000_assemble_integer (rtx, unsigned int, int);
598 static bool no_global_regs_above (int);
599 #ifdef HAVE_GAS_HIDDEN
600 static void rs6000_assemble_visibility (tree, int);
602 static int rs6000_ra_ever_killed (void);
603 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
604 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
605 static bool rs6000_ms_bitfield_layout_p (tree);
606 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
607 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
608 static const char *rs6000_mangle_fundamental_type (tree);
609 extern const struct attribute_spec rs6000_attribute_table[];
610 static void rs6000_set_default_type_attributes (tree);
611 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
612 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
613 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
615 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
616 static bool rs6000_return_in_memory (tree, tree);
617 static void rs6000_file_start (void);
619 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
620 static void rs6000_elf_asm_out_constructor (rtx, int);
621 static void rs6000_elf_asm_out_destructor (rtx, int);
622 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
623 static void rs6000_elf_asm_init_sections (void);
624 static section *rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
625 static void rs6000_elf_unique_section (tree, int);
626 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
627 unsigned HOST_WIDE_INT);
628 static void rs6000_elf_encode_section_info (tree, rtx, int)
631 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, rtx);
633 static void rs6000_xcoff_asm_output_anchor (rtx);
634 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
635 static void rs6000_xcoff_asm_init_sections (void);
636 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
637 static section *rs6000_xcoff_select_section (tree, int,
638 unsigned HOST_WIDE_INT);
639 static void rs6000_xcoff_unique_section (tree, int);
640 static section *rs6000_xcoff_select_rtx_section
641 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
642 static const char * rs6000_xcoff_strip_name_encoding (const char *);
643 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
644 static void rs6000_xcoff_file_start (void);
645 static void rs6000_xcoff_file_end (void);
647 static int rs6000_variable_issue (FILE *, int, rtx, int);
648 static bool rs6000_rtx_costs (rtx, int, int, int *);
649 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
650 static bool is_microcoded_insn (rtx);
651 static int is_dispatch_slot_restricted (rtx);
652 static bool is_cracked_insn (rtx);
653 static bool is_branch_slot_insn (rtx);
654 static int rs6000_adjust_priority (rtx, int);
655 static int rs6000_issue_rate (void);
656 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
657 static rtx get_next_active_insn (rtx, rtx);
658 static bool insn_terminates_group_p (rtx , enum group_termination);
659 static bool is_costly_group (rtx *, rtx);
660 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
661 static int redefine_groups (FILE *, int, rtx, rtx);
662 static int pad_groups (FILE *, int, rtx, rtx);
663 static void rs6000_sched_finish (FILE *, int);
664 static int rs6000_use_sched_lookahead (void);
665 static tree rs6000_builtin_mask_for_load (void);
667 static void def_builtin (int, const char *, tree, int);
668 static void rs6000_init_builtins (void);
669 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
670 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
671 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
672 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
673 static void altivec_init_builtins (void);
674 static void rs6000_common_init_builtins (void);
675 static void rs6000_init_libfuncs (void);
677 static void enable_mask_for_builtins (struct builtin_description *, int,
678 enum rs6000_builtins,
679 enum rs6000_builtins);
680 static tree build_opaque_vector_type (tree, int);
681 static void spe_init_builtins (void);
682 static rtx spe_expand_builtin (tree, rtx, bool *);
683 static rtx spe_expand_stv_builtin (enum insn_code, tree);
684 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
685 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
686 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
687 static rs6000_stack_t *rs6000_stack_info (void);
688 static void debug_stack_info (rs6000_stack_t *);
690 static rtx altivec_expand_builtin (tree, rtx, bool *);
691 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
692 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
693 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
694 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
695 static rtx altivec_expand_predicate_builtin (enum insn_code,
696 const char *, tree, rtx);
697 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
698 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
699 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
700 static rtx altivec_expand_vec_set_builtin (tree);
701 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
702 static int get_element_number (tree, tree);
703 static bool rs6000_handle_option (size_t, const char *, int);
704 static void rs6000_parse_tls_size_option (void);
705 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
706 static int first_altivec_reg_to_save (void);
707 static unsigned int compute_vrsave_mask (void);
708 static void compute_save_world_info (rs6000_stack_t *info_ptr);
709 static void is_altivec_return_reg (rtx, void *);
710 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
711 int easy_vector_constant (rtx, enum machine_mode);
712 static bool rs6000_is_opaque_type (tree);
713 static rtx rs6000_dwarf_register_span (rtx);
714 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
715 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
716 static rtx rs6000_tls_get_addr (void);
717 static rtx rs6000_got_sym (void);
718 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
719 static const char *rs6000_get_some_local_dynamic_name (void);
720 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
721 static rtx rs6000_complex_function_value (enum machine_mode);
722 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
723 enum machine_mode, tree);
724 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
726 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
727 tree, HOST_WIDE_INT);
728 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
731 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
734 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
735 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
736 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
737 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
738 enum machine_mode, tree,
740 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
742 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
744 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
746 static void macho_branch_islands (void);
747 static void add_compiler_branch_island (tree, tree, int);
748 static int no_previous_def (tree function_name);
749 static tree get_prev_label (tree function_name);
750 static void rs6000_darwin_file_start (void);
753 static tree rs6000_build_builtin_va_list (void);
754 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
755 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
756 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
757 static bool rs6000_vector_mode_supported_p (enum machine_mode);
758 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
760 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
762 static int get_vsel_insn (enum machine_mode);
763 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
764 static tree rs6000_stack_protect_fail (void);
766 const int INSN_NOT_AVAILABLE = -1;
767 static enum machine_mode rs6000_eh_return_filter_mode (void);
769 /* Hash table stuff for keeping track of TOC entries. */
771 struct toc_hash_struct GTY(())
773 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
774 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
776 enum machine_mode key_mode;
780 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
782 /* Default register names. */
783 char rs6000_reg_names[][8] =
785 "0", "1", "2", "3", "4", "5", "6", "7",
786 "8", "9", "10", "11", "12", "13", "14", "15",
787 "16", "17", "18", "19", "20", "21", "22", "23",
788 "24", "25", "26", "27", "28", "29", "30", "31",
789 "0", "1", "2", "3", "4", "5", "6", "7",
790 "8", "9", "10", "11", "12", "13", "14", "15",
791 "16", "17", "18", "19", "20", "21", "22", "23",
792 "24", "25", "26", "27", "28", "29", "30", "31",
793 "mq", "lr", "ctr","ap",
794 "0", "1", "2", "3", "4", "5", "6", "7",
796 /* AltiVec registers. */
797 "0", "1", "2", "3", "4", "5", "6", "7",
798 "8", "9", "10", "11", "12", "13", "14", "15",
799 "16", "17", "18", "19", "20", "21", "22", "23",
800 "24", "25", "26", "27", "28", "29", "30", "31",
803 "spe_acc", "spefscr",
804 /* Soft frame pointer. */
808 #ifdef TARGET_REGNAMES
809 static const char alt_reg_names[][8] =
811 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
812 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
813 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
814 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
815 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
816 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
817 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
818 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
819 "mq", "lr", "ctr", "ap",
820 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
822 /* AltiVec registers. */
823 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
824 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
825 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
826 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
829 "spe_acc", "spefscr",
830 /* Soft frame pointer. */
835 #ifndef MASK_STRICT_ALIGN
836 #define MASK_STRICT_ALIGN 0
838 #ifndef TARGET_PROFILE_KERNEL
839 #define TARGET_PROFILE_KERNEL 0
842 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
843 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
845 /* Initialize the GCC target structure. */
846 #undef TARGET_ATTRIBUTE_TABLE
847 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
848 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
849 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
851 #undef TARGET_ASM_ALIGNED_DI_OP
852 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
854 /* Default unaligned ops are only provided for ELF. Find the ops needed
855 for non-ELF systems. */
856 #ifndef OBJECT_FORMAT_ELF
858 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
860 #undef TARGET_ASM_UNALIGNED_HI_OP
861 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
862 #undef TARGET_ASM_UNALIGNED_SI_OP
863 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
864 #undef TARGET_ASM_UNALIGNED_DI_OP
865 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
868 #undef TARGET_ASM_UNALIGNED_HI_OP
869 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
870 #undef TARGET_ASM_UNALIGNED_SI_OP
871 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
872 #undef TARGET_ASM_UNALIGNED_DI_OP
873 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
874 #undef TARGET_ASM_ALIGNED_DI_OP
875 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
879 /* This hook deals with fixups for relocatable code and DI-mode objects
881 #undef TARGET_ASM_INTEGER
882 #define TARGET_ASM_INTEGER rs6000_assemble_integer
884 #ifdef HAVE_GAS_HIDDEN
885 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
886 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
889 #undef TARGET_HAVE_TLS
890 #define TARGET_HAVE_TLS HAVE_AS_TLS
892 #undef TARGET_CANNOT_FORCE_CONST_MEM
893 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
895 #undef TARGET_ASM_FUNCTION_PROLOGUE
896 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
897 #undef TARGET_ASM_FUNCTION_EPILOGUE
898 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
900 #undef TARGET_SCHED_VARIABLE_ISSUE
901 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
903 #undef TARGET_SCHED_ISSUE_RATE
904 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
905 #undef TARGET_SCHED_ADJUST_COST
906 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
907 #undef TARGET_SCHED_ADJUST_PRIORITY
908 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
909 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
910 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
911 #undef TARGET_SCHED_FINISH
912 #define TARGET_SCHED_FINISH rs6000_sched_finish
914 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
915 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
917 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
918 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
920 #undef TARGET_INIT_BUILTINS
921 #define TARGET_INIT_BUILTINS rs6000_init_builtins
923 #undef TARGET_EXPAND_BUILTIN
924 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
926 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
927 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
929 #undef TARGET_INIT_LIBFUNCS
930 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
933 #undef TARGET_BINDS_LOCAL_P
934 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
937 #undef TARGET_MS_BITFIELD_LAYOUT_P
938 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
940 #undef TARGET_ASM_OUTPUT_MI_THUNK
941 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
943 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
944 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
946 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
947 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
949 #undef TARGET_INVALID_WITHIN_DOLOOP
950 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
952 #undef TARGET_RTX_COSTS
953 #define TARGET_RTX_COSTS rs6000_rtx_costs
954 #undef TARGET_ADDRESS_COST
955 #define TARGET_ADDRESS_COST hook_int_rtx_0
957 #undef TARGET_VECTOR_OPAQUE_P
958 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
960 #undef TARGET_DWARF_REGISTER_SPAN
961 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
963 /* On rs6000, function arguments are promoted, as are function return
965 #undef TARGET_PROMOTE_FUNCTION_ARGS
966 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
967 #undef TARGET_PROMOTE_FUNCTION_RETURN
968 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
970 #undef TARGET_RETURN_IN_MEMORY
971 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
973 #undef TARGET_SETUP_INCOMING_VARARGS
974 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
976 /* Always strict argument naming on rs6000. */
977 #undef TARGET_STRICT_ARGUMENT_NAMING
978 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
979 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
980 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
981 #undef TARGET_SPLIT_COMPLEX_ARG
982 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
983 #undef TARGET_MUST_PASS_IN_STACK
984 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
985 #undef TARGET_PASS_BY_REFERENCE
986 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
987 #undef TARGET_ARG_PARTIAL_BYTES
988 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
990 #undef TARGET_BUILD_BUILTIN_VA_LIST
991 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
993 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
994 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
996 #undef TARGET_EH_RETURN_FILTER_MODE
997 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
999 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1000 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1002 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1003 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1005 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1006 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1008 #undef TARGET_HANDLE_OPTION
1009 #define TARGET_HANDLE_OPTION rs6000_handle_option
1011 #undef TARGET_DEFAULT_TARGET_FLAGS
1012 #define TARGET_DEFAULT_TARGET_FLAGS \
1015 #undef TARGET_STACK_PROTECT_FAIL
1016 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1018 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1019 The PowerPC architecture requires only weak consistency among
1020 processors--that is, memory accesses between processors need not be
1021 sequentially consistent and memory accesses among processors can occur
1022 in any order. The ability to order memory accesses weakly provides
1023 opportunities for more efficient use of the system bus. Unless a
1024 dependency exists, the 604e allows read operations to precede store
1026 #undef TARGET_RELAXED_ORDERING
1027 #define TARGET_RELAXED_ORDERING true
1030 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1031 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1034 /* Use a 32-bit anchor range. This leads to sequences like:
1036 addis tmp,anchor,high
1039 where tmp itself acts as an anchor, and can be shared between
1040 accesses to the same 64k page. */
1041 #undef TARGET_MIN_ANCHOR_OFFSET
1042 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1043 #undef TARGET_MAX_ANCHOR_OFFSET
1044 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1045 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1046 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1048 struct gcc_target targetm = TARGET_INITIALIZER;
1051 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1054 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1056 /* The GPRs can hold any mode, but values bigger than one register
1057 cannot go past R31. */
1058 if (INT_REGNO_P (regno))
1059 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1061 /* The float registers can only hold floating modes and DImode.
1062 This also excludes decimal float modes. */
1063 if (FP_REGNO_P (regno))
1065 (SCALAR_FLOAT_MODE_P (mode)
1066 && !DECIMAL_FLOAT_MODE_P (mode)
1067 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1068 || (GET_MODE_CLASS (mode) == MODE_INT
1069 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1071 /* The CR register can only hold CC modes. */
1072 if (CR_REGNO_P (regno))
1073 return GET_MODE_CLASS (mode) == MODE_CC;
1075 if (XER_REGNO_P (regno))
1076 return mode == PSImode;
1078 /* AltiVec only in AldyVec registers. */
1079 if (ALTIVEC_REGNO_P (regno))
1080 return ALTIVEC_VECTOR_MODE (mode);
1082 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1083 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1086 /* We cannot put TImode anywhere except general register and it must be
1087 able to fit within the register set. */
1089 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1092 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1094 rs6000_init_hard_regno_mode_ok (void)
1098 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1099 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1100 if (rs6000_hard_regno_mode_ok (r, m))
1101 rs6000_hard_regno_mode_ok_p[m][r] = true;
1104 /* If not otherwise specified by a target, make 'long double' equivalent to
1107 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1108 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1111 /* Override command line options. Mostly we process the processor
1112 type and sometimes adjust other TARGET_ options. */
1115 rs6000_override_options (const char *default_cpu)
1118 struct rs6000_cpu_select *ptr;
1121 /* Simplifications for entries below. */
1124 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1125 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1128 /* This table occasionally claims that a processor does not support
1129 a particular feature even though it does, but the feature is slower
1130 than the alternative. Thus, it shouldn't be relied on as a
1131 complete description of the processor's support.
1133 Please keep this list in order, and don't forget to update the
1134 documentation in invoke.texi when adding a new processor or
1138 const char *const name; /* Canonical processor name. */
1139 const enum processor_type processor; /* Processor type enum value. */
1140 const int target_enable; /* Target flags to enable. */
1141 } const processor_target_table[]
1142 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1143 {"403", PROCESSOR_PPC403,
1144 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1145 {"405", PROCESSOR_PPC405,
1146 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1147 {"405fp", PROCESSOR_PPC405,
1148 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1149 {"440", PROCESSOR_PPC440,
1150 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1151 {"440fp", PROCESSOR_PPC440,
1152 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1153 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1154 {"601", PROCESSOR_PPC601,
1155 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1156 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1157 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1158 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1159 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1160 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1161 {"620", PROCESSOR_PPC620,
1162 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1163 {"630", PROCESSOR_PPC630,
1164 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1165 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1166 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1167 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1168 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1169 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1170 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1171 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1172 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1173 /* 8548 has a dummy entry for now. */
1174 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1175 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1176 {"970", PROCESSOR_POWER4,
1177 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1178 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1179 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1180 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1181 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1182 {"G5", PROCESSOR_POWER4,
1183 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1184 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1185 {"power2", PROCESSOR_POWER,
1186 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1187 {"power3", PROCESSOR_PPC630,
1188 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1189 {"power4", PROCESSOR_POWER4,
1190 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1191 {"power5", PROCESSOR_POWER5,
1192 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1193 | MASK_MFCRF | MASK_POPCNTB},
1194 {"power5+", PROCESSOR_POWER5,
1195 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1196 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1197 {"power6", PROCESSOR_POWER5,
1198 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1200 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1201 {"powerpc64", PROCESSOR_POWERPC64,
1202 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1203 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1204 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1205 {"rios2", PROCESSOR_RIOS2,
1206 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1207 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1208 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1209 {"rs64", PROCESSOR_RS64A,
1210 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1213 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1215 /* Some OSs don't support saving the high part of 64-bit registers on
1216 context switch. Other OSs don't support saving Altivec registers.
1217 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1218 settings; if the user wants either, the user must explicitly specify
1219 them and we won't interfere with the user's specification. */
1222 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1223 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1224 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1225 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1229 rs6000_init_hard_regno_mode_ok ();
1231 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1232 #ifdef OS_MISSING_POWERPC64
1233 if (OS_MISSING_POWERPC64)
1234 set_masks &= ~MASK_POWERPC64;
1236 #ifdef OS_MISSING_ALTIVEC
1237 if (OS_MISSING_ALTIVEC)
1238 set_masks &= ~MASK_ALTIVEC;
1241 /* Don't override by the processor default if given explicitly. */
1242 set_masks &= ~target_flags_explicit;
1244 /* Identify the processor type. */
1245 rs6000_select[0].string = default_cpu;
1246 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1248 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1250 ptr = &rs6000_select[i];
1251 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1253 for (j = 0; j < ptt_size; j++)
1254 if (! strcmp (ptr->string, processor_target_table[j].name))
1256 if (ptr->set_tune_p)
1257 rs6000_cpu = processor_target_table[j].processor;
1259 if (ptr->set_arch_p)
1261 target_flags &= ~set_masks;
1262 target_flags |= (processor_target_table[j].target_enable
1269 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1276 /* If we are optimizing big endian systems for space, use the load/store
1277 multiple and string instructions. */
1278 if (BYTES_BIG_ENDIAN && optimize_size)
1279 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1281 /* Don't allow -mmultiple or -mstring on little endian systems
1282 unless the cpu is a 750, because the hardware doesn't support the
1283 instructions used in little endian mode, and causes an alignment
1284 trap. The 750 does not cause an alignment trap (except when the
1285 target is unaligned). */
1287 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1289 if (TARGET_MULTIPLE)
1291 target_flags &= ~MASK_MULTIPLE;
1292 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1293 warning (0, "-mmultiple is not supported on little endian systems");
1298 target_flags &= ~MASK_STRING;
1299 if ((target_flags_explicit & MASK_STRING) != 0)
1300 warning (0, "-mstring is not supported on little endian systems");
1304 /* Set debug flags */
1305 if (rs6000_debug_name)
1307 if (! strcmp (rs6000_debug_name, "all"))
1308 rs6000_debug_stack = rs6000_debug_arg = 1;
1309 else if (! strcmp (rs6000_debug_name, "stack"))
1310 rs6000_debug_stack = 1;
1311 else if (! strcmp (rs6000_debug_name, "arg"))
1312 rs6000_debug_arg = 1;
1314 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1317 if (rs6000_traceback_name)
1319 if (! strncmp (rs6000_traceback_name, "full", 4))
1320 rs6000_traceback = traceback_full;
1321 else if (! strncmp (rs6000_traceback_name, "part", 4))
1322 rs6000_traceback = traceback_part;
1323 else if (! strncmp (rs6000_traceback_name, "no", 2))
1324 rs6000_traceback = traceback_none;
1326 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1327 rs6000_traceback_name);
1330 if (!rs6000_explicit_options.long_double)
1331 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1333 #ifndef POWERPC_LINUX
1334 if (!rs6000_explicit_options.ieee)
1335 rs6000_ieeequad = 1;
1338 /* Set Altivec ABI as default for powerpc64 linux. */
1339 if (TARGET_ELF && TARGET_64BIT)
1341 rs6000_altivec_abi = 1;
1342 TARGET_ALTIVEC_VRSAVE = 1;
1345 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1346 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1348 rs6000_darwin64_abi = 1;
1350 darwin_one_byte_bool = 1;
1352 /* Default to natural alignment, for better performance. */
1353 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1356 /* Place FP constants in the constant pool instead of TOC
1357 if section anchors enabled. */
1358 if (flag_section_anchors)
1359 TARGET_NO_FP_IN_TOC = 1;
1361 /* Handle -mtls-size option. */
1362 rs6000_parse_tls_size_option ();
1364 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1365 SUBTARGET_OVERRIDE_OPTIONS;
1367 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1368 SUBSUBTARGET_OVERRIDE_OPTIONS;
1370 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1371 SUB3TARGET_OVERRIDE_OPTIONS;
1377 error ("AltiVec and E500 instructions cannot coexist");
1379 /* The e500 does not have string instructions, and we set
1380 MASK_STRING above when optimizing for size. */
1381 if ((target_flags & MASK_STRING) != 0)
1382 target_flags = target_flags & ~MASK_STRING;
1384 else if (rs6000_select[1].string != NULL)
1386 /* For the powerpc-eabispe configuration, we set all these by
1387 default, so let's unset them if we manually set another
1388 CPU that is not the E500. */
1389 if (!rs6000_explicit_options.abi)
1391 if (!rs6000_explicit_options.spe)
1393 if (!rs6000_explicit_options.float_gprs)
1394 rs6000_float_gprs = 0;
1395 if (!rs6000_explicit_options.isel)
1397 if (!rs6000_explicit_options.long_double)
1398 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1401 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1402 && rs6000_cpu != PROCESSOR_POWER5);
1403 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1404 || rs6000_cpu == PROCESSOR_POWER5);
1406 rs6000_sched_restricted_insns_priority
1407 = (rs6000_sched_groups ? 1 : 0);
1409 /* Handle -msched-costly-dep option. */
1410 rs6000_sched_costly_dep
1411 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1413 if (rs6000_sched_costly_dep_str)
1415 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1416 rs6000_sched_costly_dep = no_dep_costly;
1417 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1418 rs6000_sched_costly_dep = all_deps_costly;
1419 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1420 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1421 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1422 rs6000_sched_costly_dep = store_to_load_dep_costly;
1424 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1427 /* Handle -minsert-sched-nops option. */
1428 rs6000_sched_insert_nops
1429 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1431 if (rs6000_sched_insert_nops_str)
1433 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1434 rs6000_sched_insert_nops = sched_finish_none;
1435 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1436 rs6000_sched_insert_nops = sched_finish_pad_groups;
1437 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1438 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1440 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1443 #ifdef TARGET_REGNAMES
1444 /* If the user desires alternate register names, copy in the
1445 alternate names now. */
1446 if (TARGET_REGNAMES)
1447 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1450 /* Set aix_struct_return last, after the ABI is determined.
1451 If -maix-struct-return or -msvr4-struct-return was explicitly
1452 used, don't override with the ABI default. */
1453 if (!rs6000_explicit_options.aix_struct_ret)
1454 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1456 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1457 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1460 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1462 /* We can only guarantee the availability of DI pseudo-ops when
1463 assembling for 64-bit targets. */
1466 targetm.asm_out.aligned_op.di = NULL;
1467 targetm.asm_out.unaligned_op.di = NULL;
1470 /* Set branch target alignment, if not optimizing for size. */
1473 if (rs6000_sched_groups)
1475 if (align_functions <= 0)
1476 align_functions = 16;
1477 if (align_jumps <= 0)
1479 if (align_loops <= 0)
1482 if (align_jumps_max_skip <= 0)
1483 align_jumps_max_skip = 15;
1484 if (align_loops_max_skip <= 0)
1485 align_loops_max_skip = 15;
1488 /* Arrange to save and restore machine status around nested functions. */
1489 init_machine_status = rs6000_init_machine_status;
1491 /* We should always be splitting complex arguments, but we can't break
1492 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1493 if (DEFAULT_ABI != ABI_AIX)
1494 targetm.calls.split_complex_arg = NULL;
1496 /* Initialize rs6000_cost with the appropriate target costs. */
1498 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1502 case PROCESSOR_RIOS1:
1503 rs6000_cost = &rios1_cost;
1506 case PROCESSOR_RIOS2:
1507 rs6000_cost = &rios2_cost;
1510 case PROCESSOR_RS64A:
1511 rs6000_cost = &rs64a_cost;
1514 case PROCESSOR_MPCCORE:
1515 rs6000_cost = &mpccore_cost;
1518 case PROCESSOR_PPC403:
1519 rs6000_cost = &ppc403_cost;
1522 case PROCESSOR_PPC405:
1523 rs6000_cost = &ppc405_cost;
1526 case PROCESSOR_PPC440:
1527 rs6000_cost = &ppc440_cost;
1530 case PROCESSOR_PPC601:
1531 rs6000_cost = &ppc601_cost;
1534 case PROCESSOR_PPC603:
1535 rs6000_cost = &ppc603_cost;
1538 case PROCESSOR_PPC604:
1539 rs6000_cost = &ppc604_cost;
1542 case PROCESSOR_PPC604e:
1543 rs6000_cost = &ppc604e_cost;
1546 case PROCESSOR_PPC620:
1547 rs6000_cost = &ppc620_cost;
1550 case PROCESSOR_PPC630:
1551 rs6000_cost = &ppc630_cost;
1554 case PROCESSOR_PPC750:
1555 case PROCESSOR_PPC7400:
1556 rs6000_cost = &ppc750_cost;
1559 case PROCESSOR_PPC7450:
1560 rs6000_cost = &ppc7450_cost;
1563 case PROCESSOR_PPC8540:
1564 rs6000_cost = &ppc8540_cost;
1567 case PROCESSOR_POWER4:
1568 case PROCESSOR_POWER5:
1569 rs6000_cost = &power4_cost;
1577 /* Implement targetm.vectorize.builtin_mask_for_load. */
1579 rs6000_builtin_mask_for_load (void)
1582 return altivec_builtin_mask_for_load;
1587 /* Handle generic options of the form -mfoo=yes/no.
1588 NAME is the option name.
1589 VALUE is the option value.
1590 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1591 whether the option value is 'yes' or 'no' respectively. */
1593 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1597 else if (!strcmp (value, "yes"))
1599 else if (!strcmp (value, "no"))
1602 error ("unknown -m%s= option specified: '%s'", name, value);
1605 /* Validate and record the size specified with the -mtls-size option. */
1608 rs6000_parse_tls_size_option (void)
1610 if (rs6000_tls_size_string == 0)
1612 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1613 rs6000_tls_size = 16;
1614 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1615 rs6000_tls_size = 32;
1616 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1617 rs6000_tls_size = 64;
1619 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1623 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1625 if (DEFAULT_ABI == ABI_DARWIN)
1626 /* The Darwin libraries never set errno, so we might as well
1627 avoid calling them when that's the only reason we would. */
1628 flag_errno_math = 0;
1630 /* Double growth factor to counter reduced min jump length. */
1631 set_param_value ("max-grow-copy-bb-insns", 16);
1633 /* Enable section anchors by default.
1634 Skip section anchors for Objective C and Objective C++
1635 until front-ends fixed. */
1636 if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
1637 flag_section_anchors = 1;
1640 /* Implement TARGET_HANDLE_OPTION. */
1643 rs6000_handle_option (size_t code, const char *arg, int value)
1648 target_flags &= ~(MASK_POWER | MASK_POWER2
1649 | MASK_MULTIPLE | MASK_STRING);
1650 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1651 | MASK_MULTIPLE | MASK_STRING);
1653 case OPT_mno_powerpc:
1654 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1655 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1656 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1657 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1660 target_flags &= ~MASK_MINIMAL_TOC;
1661 TARGET_NO_FP_IN_TOC = 0;
1662 TARGET_NO_SUM_IN_TOC = 0;
1663 target_flags_explicit |= MASK_MINIMAL_TOC;
1664 #ifdef TARGET_USES_SYSV4_OPT
1665 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1666 just the same as -mminimal-toc. */
1667 target_flags |= MASK_MINIMAL_TOC;
1668 target_flags_explicit |= MASK_MINIMAL_TOC;
1672 #ifdef TARGET_USES_SYSV4_OPT
1674 /* Make -mtoc behave like -mminimal-toc. */
1675 target_flags |= MASK_MINIMAL_TOC;
1676 target_flags_explicit |= MASK_MINIMAL_TOC;
1680 #ifdef TARGET_USES_AIX64_OPT
1685 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
1686 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
1687 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
1690 #ifdef TARGET_USES_AIX64_OPT
1695 target_flags &= ~MASK_POWERPC64;
1696 target_flags_explicit |= MASK_POWERPC64;
1699 case OPT_minsert_sched_nops_:
1700 rs6000_sched_insert_nops_str = arg;
1703 case OPT_mminimal_toc:
1706 TARGET_NO_FP_IN_TOC = 0;
1707 TARGET_NO_SUM_IN_TOC = 0;
1714 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1715 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1722 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1723 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1727 case OPT_mpowerpc_gpopt:
1728 case OPT_mpowerpc_gfxopt:
1731 target_flags |= MASK_POWERPC;
1732 target_flags_explicit |= MASK_POWERPC;
1736 case OPT_maix_struct_return:
1737 case OPT_msvr4_struct_return:
1738 rs6000_explicit_options.aix_struct_ret = true;
1742 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1746 rs6000_explicit_options.isel = true;
1747 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1751 rs6000_explicit_options.spe = true;
1752 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1753 /* No SPE means 64-bit long doubles, even if an E500. */
1755 rs6000_long_double_type_size = 64;
1759 rs6000_debug_name = arg;
1762 #ifdef TARGET_USES_SYSV4_OPT
1764 rs6000_abi_name = arg;
1768 rs6000_sdata_name = arg;
1771 case OPT_mtls_size_:
1772 rs6000_tls_size_string = arg;
1775 case OPT_mrelocatable:
1778 target_flags |= MASK_MINIMAL_TOC;
1779 target_flags_explicit |= MASK_MINIMAL_TOC;
1780 TARGET_NO_FP_IN_TOC = 1;
1784 case OPT_mrelocatable_lib:
1787 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
1788 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
1789 TARGET_NO_FP_IN_TOC = 1;
1793 target_flags &= ~MASK_RELOCATABLE;
1794 target_flags_explicit |= MASK_RELOCATABLE;
1800 if (!strcmp (arg, "altivec"))
1802 rs6000_explicit_options.abi = true;
1803 rs6000_altivec_abi = 1;
1806 else if (! strcmp (arg, "no-altivec"))
1808 /* ??? Don't set rs6000_explicit_options.abi here, to allow
1809 the default for rs6000_spe_abi to be chosen later. */
1810 rs6000_altivec_abi = 0;
1812 else if (! strcmp (arg, "spe"))
1814 rs6000_explicit_options.abi = true;
1816 rs6000_altivec_abi = 0;
1817 if (!TARGET_SPE_ABI)
1818 error ("not configured for ABI: '%s'", arg);
1820 else if (! strcmp (arg, "no-spe"))
1822 rs6000_explicit_options.abi = true;
1826 /* These are here for testing during development only, do not
1827 document in the manual please. */
1828 else if (! strcmp (arg, "d64"))
1830 rs6000_darwin64_abi = 1;
1831 warning (0, "Using darwin64 ABI");
1833 else if (! strcmp (arg, "d32"))
1835 rs6000_darwin64_abi = 0;
1836 warning (0, "Using old darwin ABI");
1839 else if (! strcmp (arg, "ibmlongdouble"))
1841 rs6000_explicit_options.ieee = true;
1842 rs6000_ieeequad = 0;
1843 warning (0, "Using IBM extended precision long double");
1845 else if (! strcmp (arg, "ieeelongdouble"))
1847 rs6000_explicit_options.ieee = true;
1848 rs6000_ieeequad = 1;
1849 warning (0, "Using IEEE extended precision long double");
1854 error ("unknown ABI specified: '%s'", arg);
1860 rs6000_select[1].string = arg;
1864 rs6000_select[2].string = arg;
1867 case OPT_mtraceback_:
1868 rs6000_traceback_name = arg;
1871 case OPT_mfloat_gprs_:
1872 rs6000_explicit_options.float_gprs = true;
1873 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
1874 rs6000_float_gprs = 1;
1875 else if (! strcmp (arg, "double"))
1876 rs6000_float_gprs = 2;
1877 else if (! strcmp (arg, "no"))
1878 rs6000_float_gprs = 0;
1881 error ("invalid option for -mfloat-gprs: '%s'", arg);
1886 case OPT_mlong_double_:
1887 rs6000_explicit_options.long_double = true;
1888 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1889 if (value != 64 && value != 128)
1891 error ("Unknown switch -mlong-double-%s", arg);
1892 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1896 rs6000_long_double_type_size = value;
1899 case OPT_msched_costly_dep_:
1900 rs6000_sched_costly_dep_str = arg;
1904 rs6000_explicit_options.alignment = true;
1905 if (! strcmp (arg, "power"))
1907 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1908 some C library functions, so warn about it. The flag may be
1909 useful for performance studies from time to time though, so
1910 don't disable it entirely. */
1911 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1912 warning (0, "-malign-power is not supported for 64-bit Darwin;"
1913 " it is incompatible with the installed C and C++ libraries");
1914 rs6000_alignment_flags = MASK_ALIGN_POWER;
1916 else if (! strcmp (arg, "natural"))
1917 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1920 error ("unknown -malign-XXXXX option specified: '%s'", arg);
1928 /* Do anything needed at the start of the asm file. */
1931 rs6000_file_start (void)
1935 const char *start = buffer;
1936 struct rs6000_cpu_select *ptr;
1937 const char *default_cpu = TARGET_CPU_DEFAULT;
1938 FILE *file = asm_out_file;
1940 default_file_start ();
1942 #ifdef TARGET_BI_ARCH
1943 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1947 if (flag_verbose_asm)
1949 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1950 rs6000_select[0].string = default_cpu;
1952 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1954 ptr = &rs6000_select[i];
1955 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1957 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1962 if (PPC405_ERRATUM77)
1964 fprintf (file, "%s PPC405CR_ERRATUM77", start);
1968 #ifdef USING_ELFOS_H
1969 switch (rs6000_sdata)
1971 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1972 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1973 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1974 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1977 if (rs6000_sdata && g_switch_value)
1979 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1989 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1991 switch_to_section (toc_section);
1992 switch_to_section (text_section);
1997 /* Return nonzero if this function is known to have a null epilogue. */
2000 direct_return (void)
2002 if (reload_completed)
2004 rs6000_stack_t *info = rs6000_stack_info ();
2006 if (info->first_gp_reg_save == 32
2007 && info->first_fp_reg_save == 64
2008 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
2009 && ! info->lr_save_p
2010 && ! info->cr_save_p
2011 && info->vrsave_mask == 0
2019 /* Return the number of instructions it takes to form a constant in an
2020 integer register. */
2023 num_insns_constant_wide (HOST_WIDE_INT value)
2025 /* signed constant loadable with {cal|addi} */
2026 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2029 /* constant loadable with {cau|addis} */
2030 else if ((value & 0xffff) == 0
2031 && (value >> 31 == -1 || value >> 31 == 0))
2034 #if HOST_BITS_PER_WIDE_INT == 64
2035 else if (TARGET_POWERPC64)
2037 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2038 HOST_WIDE_INT high = value >> 31;
2040 if (high == 0 || high == -1)
2046 return num_insns_constant_wide (high) + 1;
2048 return (num_insns_constant_wide (high)
2049 + num_insns_constant_wide (low) + 1);
2058 num_insns_constant (rtx op, enum machine_mode mode)
2060 HOST_WIDE_INT low, high;
2062 switch (GET_CODE (op))
2065 #if HOST_BITS_PER_WIDE_INT == 64
2066 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2067 && mask64_operand (op, mode))
2071 return num_insns_constant_wide (INTVAL (op));
2079 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2080 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2081 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2084 if (mode == VOIDmode || mode == DImode)
2086 high = CONST_DOUBLE_HIGH (op);
2087 low = CONST_DOUBLE_LOW (op);
2094 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2095 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2096 high = l[WORDS_BIG_ENDIAN == 0];
2097 low = l[WORDS_BIG_ENDIAN != 0];
2101 return (num_insns_constant_wide (low)
2102 + num_insns_constant_wide (high));
2105 if ((high == 0 && low >= 0)
2106 || (high == -1 && low < 0))
2107 return num_insns_constant_wide (low);
2109 else if (mask64_operand (op, mode))
2113 return num_insns_constant_wide (high) + 1;
2116 return (num_insns_constant_wide (high)
2117 + num_insns_constant_wide (low) + 1);
2125 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2126 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2127 corresponding element of the vector, but for V4SFmode and V2SFmode,
2128 the corresponding "float" is interpreted as an SImode integer. */
2130 static HOST_WIDE_INT
2131 const_vector_elt_as_int (rtx op, unsigned int elt)
2133 rtx tmp = CONST_VECTOR_ELT (op, elt);
2134 if (GET_MODE (op) == V4SFmode
2135 || GET_MODE (op) == V2SFmode)
2136 tmp = gen_lowpart (SImode, tmp);
2137 return INTVAL (tmp);
2140 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2141 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2142 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2143 all items are set to the same value and contain COPIES replicas of the
2144 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2145 operand and the others are set to the value of the operand's msb. */
2148 vspltis_constant (rtx op, unsigned step, unsigned copies)
2150 enum machine_mode mode = GET_MODE (op);
2151 enum machine_mode inner = GET_MODE_INNER (mode);
2154 unsigned nunits = GET_MODE_NUNITS (mode);
2155 unsigned bitsize = GET_MODE_BITSIZE (inner);
2156 unsigned mask = GET_MODE_MASK (inner);
2158 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
2159 HOST_WIDE_INT splat_val = val;
2160 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2162 /* Construct the value to be splatted, if possible. If not, return 0. */
2163 for (i = 2; i <= copies; i *= 2)
2165 HOST_WIDE_INT small_val;
2167 small_val = splat_val >> bitsize;
2169 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2171 splat_val = small_val;
2174 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2175 if (EASY_VECTOR_15 (splat_val))
2178 /* Also check if we can splat, and then add the result to itself. Do so if
2179 the value is positive, of if the splat instruction is using OP's mode;
2180 for splat_val < 0, the splat and the add should use the same mode. */
2181 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2182 && (splat_val >= 0 || (step == 1 && copies == 1)))
2188 /* Check if VAL is present in every STEP-th element, and the
2189 other elements are filled with its most significant bit. */
2190 for (i = 0; i < nunits - 1; ++i)
2192 HOST_WIDE_INT desired_val;
2193 if (((i + 1) & (step - 1)) == 0)
2196 desired_val = msb_val;
2198 if (desired_val != const_vector_elt_as_int (op, i))
2206 /* Return true if OP is of the given MODE and can be synthesized
2207 with a vspltisb, vspltish or vspltisw. */
2210 easy_altivec_constant (rtx op, enum machine_mode mode)
2212 unsigned step, copies;
2214 if (mode == VOIDmode)
2215 mode = GET_MODE (op);
2216 else if (mode != GET_MODE (op))
2219 /* Start with a vspltisw. */
2220 step = GET_MODE_NUNITS (mode) / 4;
2223 if (vspltis_constant (op, step, copies))
2226 /* Then try with a vspltish. */
2232 if (vspltis_constant (op, step, copies))
2235 /* And finally a vspltisb. */
2241 if (vspltis_constant (op, step, copies))
2247 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2248 result is OP. Abort if it is not possible. */
2251 gen_easy_altivec_constant (rtx op)
2253 enum machine_mode mode = GET_MODE (op);
2254 int nunits = GET_MODE_NUNITS (mode);
2255 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2256 unsigned step = nunits / 4;
2257 unsigned copies = 1;
2259 /* Start with a vspltisw. */
2260 if (vspltis_constant (op, step, copies))
2261 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2263 /* Then try with a vspltish. */
2269 if (vspltis_constant (op, step, copies))
2270 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2272 /* And finally a vspltisb. */
2278 if (vspltis_constant (op, step, copies))
2279 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2285 output_vec_const_move (rtx *operands)
2288 enum machine_mode mode;
2293 mode = GET_MODE (dest);
2298 if (zero_constant (vec, mode))
2299 return "vxor %0,%0,%0";
2301 splat_vec = gen_easy_altivec_constant (vec);
2302 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2303 operands[1] = XEXP (splat_vec, 0);
2304 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2307 switch (GET_MODE (splat_vec))
2310 return "vspltisw %0,%1";
2313 return "vspltish %0,%1";
2316 return "vspltisb %0,%1";
2323 gcc_assert (TARGET_SPE);
2325 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2326 pattern of V1DI, V4HI, and V2SF.
2328 FIXME: We should probably return # and add post reload
2329 splitters for these, but this way is so easy ;-). */
2330 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2331 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2332 operands[1] = CONST_VECTOR_ELT (vec, 0);
2333 operands[2] = CONST_VECTOR_ELT (vec, 1);
2335 return "li %0,%1\n\tevmergelo %0,%0,%0";
2337 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2340 /* Initialize vector TARGET to VALS. */
2343 rs6000_expand_vector_init (rtx target, rtx vals)
2345 enum machine_mode mode = GET_MODE (target);
2346 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2347 int n_elts = GET_MODE_NUNITS (mode);
2348 int n_var = 0, one_var = -1;
2349 bool all_same = true, all_const_zero = true;
2353 for (i = 0; i < n_elts; ++i)
2355 x = XVECEXP (vals, 0, i);
2356 if (!CONSTANT_P (x))
2357 ++n_var, one_var = i;
2358 else if (x != CONST0_RTX (inner_mode))
2359 all_const_zero = false;
2361 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2367 if (mode != V4SFmode && all_const_zero)
2369 /* Zero register. */
2370 emit_insn (gen_rtx_SET (VOIDmode, target,
2371 gen_rtx_XOR (mode, target, target)));
2374 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2376 /* Splat immediate. */
2377 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2381 ; /* Splat vector element. */
2384 /* Load from constant pool. */
2385 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2390 /* Store value to stack temp. Load vector element. Splat. */
2393 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2394 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2395 XVECEXP (vals, 0, 0));
2396 x = gen_rtx_UNSPEC (VOIDmode,
2397 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2398 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2400 gen_rtx_SET (VOIDmode,
2403 x = gen_rtx_VEC_SELECT (inner_mode, target,
2404 gen_rtx_PARALLEL (VOIDmode,
2405 gen_rtvec (1, const0_rtx)));
2406 emit_insn (gen_rtx_SET (VOIDmode, target,
2407 gen_rtx_VEC_DUPLICATE (mode, x)));
2411 /* One field is non-constant. Load constant then overwrite
2415 rtx copy = copy_rtx (vals);
2417 /* Load constant part of vector, substitute neighboring value for
2419 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2420 rs6000_expand_vector_init (target, copy);
2422 /* Insert variable. */
2423 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2427 /* Construct the vector in memory one field at a time
2428 and load the whole vector. */
2429 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2430 for (i = 0; i < n_elts; i++)
2431 emit_move_insn (adjust_address_nv (mem, inner_mode,
2432 i * GET_MODE_SIZE (inner_mode)),
2433 XVECEXP (vals, 0, i));
2434 emit_move_insn (target, mem);
2437 /* Set field ELT of TARGET to VAL. */
2440 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2442 enum machine_mode mode = GET_MODE (target);
2443 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2444 rtx reg = gen_reg_rtx (mode);
2446 int width = GET_MODE_SIZE (inner_mode);
2449 /* Load single variable value. */
2450 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2451 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2452 x = gen_rtx_UNSPEC (VOIDmode,
2453 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2454 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2456 gen_rtx_SET (VOIDmode,
2460 /* Linear sequence. */
2461 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2462 for (i = 0; i < 16; ++i)
2463 XVECEXP (mask, 0, i) = GEN_INT (i);
2465 /* Set permute mask to insert element into target. */
2466 for (i = 0; i < width; ++i)
2467 XVECEXP (mask, 0, elt*width + i)
2468 = GEN_INT (i + 0x10);
2469 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2470 x = gen_rtx_UNSPEC (mode,
2471 gen_rtvec (3, target, reg,
2472 force_reg (V16QImode, x)),
2474 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2477 /* Extract field ELT from VEC into TARGET. */
2480 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2482 enum machine_mode mode = GET_MODE (vec);
2483 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2486 /* Allocate mode-sized buffer. */
2487 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2489 /* Add offset to field within buffer matching vector element. */
2490 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2492 /* Store single field into mode-sized buffer. */
2493 x = gen_rtx_UNSPEC (VOIDmode,
2494 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2495 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2497 gen_rtx_SET (VOIDmode,
2500 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2503 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2504 implement ANDing by the mask IN. */
2506 build_mask64_2_operands (rtx in, rtx *out)
2508 #if HOST_BITS_PER_WIDE_INT >= 64
2509 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2512 gcc_assert (GET_CODE (in) == CONST_INT);
2517 /* Assume c initially something like 0x00fff000000fffff. The idea
2518 is to rotate the word so that the middle ^^^^^^ group of zeros
2519 is at the MS end and can be cleared with an rldicl mask. We then
2520 rotate back and clear off the MS ^^ group of zeros with a
2522 c = ~c; /* c == 0xff000ffffff00000 */
2523 lsb = c & -c; /* lsb == 0x0000000000100000 */
2524 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2525 c = ~c; /* c == 0x00fff000000fffff */
2526 c &= -lsb; /* c == 0x00fff00000000000 */
2527 lsb = c & -c; /* lsb == 0x0000100000000000 */
2528 c = ~c; /* c == 0xff000fffffffffff */
2529 c &= -lsb; /* c == 0xff00000000000000 */
2531 while ((lsb >>= 1) != 0)
2532 shift++; /* shift == 44 on exit from loop */
2533 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2534 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2535 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2539 /* Assume c initially something like 0xff000f0000000000. The idea
2540 is to rotate the word so that the ^^^ middle group of zeros
2541 is at the LS end and can be cleared with an rldicr mask. We then
2542 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2544 lsb = c & -c; /* lsb == 0x0000010000000000 */
2545 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2546 c = ~c; /* c == 0x00fff0ffffffffff */
2547 c &= -lsb; /* c == 0x00fff00000000000 */
2548 lsb = c & -c; /* lsb == 0x0000100000000000 */
2549 c = ~c; /* c == 0xff000fffffffffff */
2550 c &= -lsb; /* c == 0xff00000000000000 */
2552 while ((lsb >>= 1) != 0)
2553 shift++; /* shift == 44 on exit from loop */
2554 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2555 m1 >>= shift; /* m1 == 0x0000000000000fff */
2556 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2559 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2560 masks will be all 1's. We are guaranteed more than one transition. */
2561 out[0] = GEN_INT (64 - shift);
2562 out[1] = GEN_INT (m1);
2563 out[2] = GEN_INT (shift);
2564 out[3] = GEN_INT (m2);
2572 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2575 invalid_e500_subreg (rtx op, enum machine_mode mode)
2577 /* Reject (subreg:SI (reg:DF)). */
2578 if (GET_CODE (op) == SUBREG
2580 && REG_P (SUBREG_REG (op))
2581 && GET_MODE (SUBREG_REG (op)) == DFmode)
2584 /* Reject (subreg:DF (reg:DI)). */
2585 if (GET_CODE (op) == SUBREG
2587 && REG_P (SUBREG_REG (op))
2588 && GET_MODE (SUBREG_REG (op)) == DImode)
2594 /* Darwin, AIX increases natural record alignment to doubleword if the first
2595 field is an FP double while the FP fields remain word aligned. */
2598 rs6000_special_round_type_align (tree type, unsigned int computed,
2599 unsigned int specified)
2601 unsigned int align = MAX (computed, specified);
2602 tree field = TYPE_FIELDS (type);
2604 /* Skip all non field decls */
2605 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2606 field = TREE_CHAIN (field);
2608 if (field != NULL && field != type)
2610 type = TREE_TYPE (field);
2611 while (TREE_CODE (type) == ARRAY_TYPE)
2612 type = TREE_TYPE (type);
2614 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2615 align = MAX (align, 64);
2621 /* Return 1 for an operand in small memory on V.4/eabi. */
2624 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2625 enum machine_mode mode ATTRIBUTE_UNUSED)
2630 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2633 if (DEFAULT_ABI != ABI_V4)
2636 if (GET_CODE (op) == SYMBOL_REF)
2639 else if (GET_CODE (op) != CONST
2640 || GET_CODE (XEXP (op, 0)) != PLUS
2641 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2642 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2647 rtx sum = XEXP (op, 0);
2648 HOST_WIDE_INT summand;
2650 /* We have to be careful here, because it is the referenced address
2651 that must be 32k from _SDA_BASE_, not just the symbol. */
2652 summand = INTVAL (XEXP (sum, 1));
2653 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2656 sym_ref = XEXP (sum, 0);
2659 return SYMBOL_REF_SMALL_P (sym_ref);
2665 /* Return true if either operand is a general purpose register. */
2668 gpr_or_gpr_p (rtx op0, rtx op1)
2670 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2671 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2675 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2678 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2680 switch (GET_CODE (op))
2683 if (RS6000_SYMBOL_REF_TLS_P (op))
2685 else if (CONSTANT_POOL_ADDRESS_P (op))
2687 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2695 else if (! strcmp (XSTR (op, 0), toc_label_name))
2704 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2705 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2707 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2716 constant_pool_expr_p (rtx op)
2720 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2724 toc_relative_expr_p (rtx op)
2728 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2732 legitimate_constant_pool_address_p (rtx x)
2735 && GET_CODE (x) == PLUS
2736 && GET_CODE (XEXP (x, 0)) == REG
2737 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2738 && constant_pool_expr_p (XEXP (x, 1)));
2742 legitimate_small_data_p (enum machine_mode mode, rtx x)
2744 return (DEFAULT_ABI == ABI_V4
2745 && !flag_pic && !TARGET_TOC
2746 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2747 && small_data_operand (x, mode));
2750 /* SPE offset addressing is limited to 5-bits worth of double words. */
2751 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2754 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2756 unsigned HOST_WIDE_INT offset, extra;
2758 if (GET_CODE (x) != PLUS)
2760 if (GET_CODE (XEXP (x, 0)) != REG)
2762 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2764 if (legitimate_constant_pool_address_p (x))
2766 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2769 offset = INTVAL (XEXP (x, 1));
2777 /* AltiVec vector modes. Only reg+reg addressing is valid and
2778 constant offset zero should not occur due to canonicalization.
2779 Allow any offset when not strict before reload. */
2786 /* SPE vector modes. */
2787 return SPE_CONST_OFFSET_OK (offset);
2790 if (TARGET_E500_DOUBLE)
2791 return SPE_CONST_OFFSET_OK (offset);
2794 /* On e500v2, we may have:
2796 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2798 Which gets addressed with evldd instructions. */
2799 if (TARGET_E500_DOUBLE)
2800 return SPE_CONST_OFFSET_OK (offset);
2802 if (mode == DFmode || !TARGET_POWERPC64)
2804 else if (offset & 3)
2810 if (mode == TFmode || !TARGET_POWERPC64)
2812 else if (offset & 3)
2823 return (offset < 0x10000) && (offset + extra < 0x10000);
2827 legitimate_indexed_address_p (rtx x, int strict)
2831 if (GET_CODE (x) != PLUS)
2837 /* Recognize the rtl generated by reload which we know will later be
2838 replaced with proper base and index regs. */
2840 && reload_in_progress
2841 && (REG_P (op0) || GET_CODE (op0) == PLUS)
2845 return (REG_P (op0) && REG_P (op1)
2846 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
2847 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2848 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2849 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
2853 legitimate_indirect_address_p (rtx x, int strict)
2855 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2859 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2861 if (!TARGET_MACHO || !flag_pic
2862 || mode != SImode || GET_CODE (x) != MEM)
2866 if (GET_CODE (x) != LO_SUM)
2868 if (GET_CODE (XEXP (x, 0)) != REG)
2870 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2874 return CONSTANT_P (x);
2878 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2880 if (GET_CODE (x) != LO_SUM)
2882 if (GET_CODE (XEXP (x, 0)) != REG)
2884 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2886 /* Restrict addressing for DI because of our SUBREG hackery. */
2887 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
2891 if (TARGET_ELF || TARGET_MACHO)
2893 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2897 if (GET_MODE_NUNITS (mode) != 1)
2899 if (GET_MODE_BITSIZE (mode) > 64
2900 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2901 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
2904 return CONSTANT_P (x);
2911 /* Try machine-dependent ways of modifying an illegitimate address
2912 to be legitimate. If we find one, return the new, valid address.
2913 This is used from only one place: `memory_address' in explow.c.
2915 OLDX is the address as it was before break_out_memory_refs was
2916 called. In some cases it is useful to look at this to decide what
2919 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2921 It is always safe for this function to do nothing. It exists to
2922 recognize opportunities to optimize the output.
2924 On RS/6000, first check for the sum of a register with a constant
2925 integer that is out of range. If so, generate code to add the
2926 constant with the low-order 16 bits masked to the register and force
2927 this result into another register (this can be done with `cau').
2928 Then generate an address of REG+(CONST&0xffff), allowing for the
2929 possibility of bit 16 being a one.
2931 Then check for the sum of a register and something not constant, try to
2932 load the other things into a register and return the sum. */
2935 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2936 enum machine_mode mode)
2938 if (GET_CODE (x) == SYMBOL_REF)
2940 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2942 return rs6000_legitimize_tls_address (x, model);
2945 if (GET_CODE (x) == PLUS
2946 && GET_CODE (XEXP (x, 0)) == REG
2947 && GET_CODE (XEXP (x, 1)) == CONST_INT
2948 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2950 HOST_WIDE_INT high_int, low_int;
2952 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2953 high_int = INTVAL (XEXP (x, 1)) - low_int;
2954 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2955 GEN_INT (high_int)), 0);
2956 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2958 else if (GET_CODE (x) == PLUS
2959 && GET_CODE (XEXP (x, 0)) == REG
2960 && GET_CODE (XEXP (x, 1)) != CONST_INT
2961 && GET_MODE_NUNITS (mode) == 1
2962 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2964 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2966 && (TARGET_POWERPC64 || mode != DImode)
2969 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2970 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2972 else if (ALTIVEC_VECTOR_MODE (mode))
2976 /* Make sure both operands are registers. */
2977 if (GET_CODE (x) == PLUS)
2978 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2979 force_reg (Pmode, XEXP (x, 1)));
2981 reg = force_reg (Pmode, x);
2984 else if (SPE_VECTOR_MODE (mode)
2985 || (TARGET_E500_DOUBLE && (mode == DFmode
2986 || mode == DImode)))
2990 /* We accept [reg + reg] and [reg + OFFSET]. */
2992 if (GET_CODE (x) == PLUS)
2994 rtx op1 = XEXP (x, 0);
2995 rtx op2 = XEXP (x, 1);
2997 op1 = force_reg (Pmode, op1);
2999 if (GET_CODE (op2) != REG
3000 && (GET_CODE (op2) != CONST_INT
3001 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3002 op2 = force_reg (Pmode, op2);
3004 return gen_rtx_PLUS (Pmode, op1, op2);
3007 return force_reg (Pmode, x);
3013 && GET_CODE (x) != CONST_INT
3014 && GET_CODE (x) != CONST_DOUBLE
3016 && GET_MODE_NUNITS (mode) == 1
3017 && (GET_MODE_BITSIZE (mode) <= 32
3018 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3020 rtx reg = gen_reg_rtx (Pmode);
3021 emit_insn (gen_elf_high (reg, x));
3022 return gen_rtx_LO_SUM (Pmode, reg, x);
3024 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3027 && ! MACHO_DYNAMIC_NO_PIC_P
3029 && GET_CODE (x) != CONST_INT
3030 && GET_CODE (x) != CONST_DOUBLE
3032 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3036 rtx reg = gen_reg_rtx (Pmode);
3037 emit_insn (gen_macho_high (reg, x));
3038 return gen_rtx_LO_SUM (Pmode, reg, x);
3041 && constant_pool_expr_p (x)
3042 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3044 return create_TOC_reference (x);
3050 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3051 We need to emit DTP-relative relocations. */
3054 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3059 fputs ("\t.long\t", file);
3062 fputs (DOUBLE_INT_ASM_OP, file);
3067 output_addr_const (file, x);
3068 fputs ("@dtprel+0x8000", file);
3071 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3073 static GTY(()) rtx rs6000_tls_symbol;
3075 rs6000_tls_get_addr (void)
3077 if (!rs6000_tls_symbol)
3078 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3080 return rs6000_tls_symbol;
3083 /* Construct the SYMBOL_REF for TLS GOT references. */
3085 static GTY(()) rtx rs6000_got_symbol;
3087 rs6000_got_sym (void)
3089 if (!rs6000_got_symbol)
3091 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3092 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3093 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3096 return rs6000_got_symbol;
3099 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3100 this (thread-local) address. */
3103 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3107 dest = gen_reg_rtx (Pmode);
3108 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3114 tlsreg = gen_rtx_REG (Pmode, 13);
3115 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3119 tlsreg = gen_rtx_REG (Pmode, 2);
3120 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3124 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3128 tmp = gen_reg_rtx (Pmode);
3131 tlsreg = gen_rtx_REG (Pmode, 13);
3132 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3136 tlsreg = gen_rtx_REG (Pmode, 2);
3137 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3141 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3143 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3148 rtx r3, got, tga, tmp1, tmp2, eqv;
3150 /* We currently use relocations like @got@tlsgd for tls, which
3151 means the linker will handle allocation of tls entries, placing
3152 them in the .got section. So use a pointer to the .got section,
3153 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3154 or to secondary GOT sections used by 32-bit -fPIC. */
3156 got = gen_rtx_REG (Pmode, 2);
3160 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3163 rtx gsym = rs6000_got_sym ();
3164 got = gen_reg_rtx (Pmode);
3166 rs6000_emit_move (got, gsym, Pmode);
3169 rtx tempLR, tmp3, mem;
3172 tempLR = gen_reg_rtx (Pmode);
3173 tmp1 = gen_reg_rtx (Pmode);
3174 tmp2 = gen_reg_rtx (Pmode);
3175 tmp3 = gen_reg_rtx (Pmode);
3176 mem = gen_const_mem (Pmode, tmp1);
3178 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
3179 emit_move_insn (tmp1, tempLR);
3180 emit_move_insn (tmp2, mem);
3181 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3182 last = emit_move_insn (got, tmp3);
3183 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3185 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3187 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3193 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3195 r3 = gen_rtx_REG (Pmode, 3);
3197 insn = gen_tls_gd_64 (r3, got, addr);
3199 insn = gen_tls_gd_32 (r3, got, addr);
3202 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3203 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3204 insn = emit_call_insn (insn);
3205 CONST_OR_PURE_CALL_P (insn) = 1;
3206 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3207 insn = get_insns ();
3209 emit_libcall_block (insn, dest, r3, addr);
3211 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3213 r3 = gen_rtx_REG (Pmode, 3);
3215 insn = gen_tls_ld_64 (r3, got);
3217 insn = gen_tls_ld_32 (r3, got);
3220 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3221 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3222 insn = emit_call_insn (insn);
3223 CONST_OR_PURE_CALL_P (insn) = 1;
3224 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3225 insn = get_insns ();
3227 tmp1 = gen_reg_rtx (Pmode);
3228 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3230 emit_libcall_block (insn, tmp1, r3, eqv);
3231 if (rs6000_tls_size == 16)
3234 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3236 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3238 else if (rs6000_tls_size == 32)
3240 tmp2 = gen_reg_rtx (Pmode);
3242 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3244 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3247 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3249 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3253 tmp2 = gen_reg_rtx (Pmode);
3255 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3257 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3259 insn = gen_rtx_SET (Pmode, dest,
3260 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3266 /* IE, or 64 bit offset LE. */
3267 tmp2 = gen_reg_rtx (Pmode);
3269 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3271 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3274 insn = gen_tls_tls_64 (dest, tmp2, addr);
3276 insn = gen_tls_tls_32 (dest, tmp2, addr);
3284 /* Return 1 if X contains a thread-local symbol. */
3287 rs6000_tls_referenced_p (rtx x)
3289 if (! TARGET_HAVE_TLS)
3292 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3295 /* Return 1 if *X is a thread-local symbol. This is the same as
3296 rs6000_tls_symbol_ref except for the type of the unused argument. */
3299 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3301 return RS6000_SYMBOL_REF_TLS_P (*x);
3304 /* The convention appears to be to define this wherever it is used.
3305 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3306 is now used here. */
3307 #ifndef REG_MODE_OK_FOR_BASE_P
3308 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3311 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3312 replace the input X, or the original X if no replacement is called for.
3313 The output parameter *WIN is 1 if the calling macro should goto WIN,
3316 For RS/6000, we wish to handle large displacements off a base
3317 register by splitting the addend across an addiu/addis and the mem insn.
3318 This cuts number of extra insns needed from 3 to 1.
3320 On Darwin, we use this to generate code for floating point constants.
3321 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3322 The Darwin code is inside #if TARGET_MACHO because only then is
3323 machopic_function_base_name() defined. */
3325 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3326 int opnum, int type,
3327 int ind_levels ATTRIBUTE_UNUSED, int *win)
3329 /* We must recognize output that we have already generated ourselves. */
3330 if (GET_CODE (x) == PLUS
3331 && GET_CODE (XEXP (x, 0)) == PLUS
3332 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3333 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3334 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3336 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3337 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3338 opnum, (enum reload_type)type);
3344 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3345 && GET_CODE (x) == LO_SUM
3346 && GET_CODE (XEXP (x, 0)) == PLUS
3347 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3348 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3349 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3350 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3351 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3352 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3353 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3355 /* Result of previous invocation of this function on Darwin
3356 floating point constant. */
3357 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3358 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3359 opnum, (enum reload_type)type);
3365 /* Force ld/std non-word aligned offset into base register by wrapping
3367 if (GET_CODE (x) == PLUS
3368 && GET_CODE (XEXP (x, 0)) == REG
3369 && REGNO (XEXP (x, 0)) < 32
3370 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3371 && GET_CODE (XEXP (x, 1)) == CONST_INT
3372 && (INTVAL (XEXP (x, 1)) & 3) != 0
3373 && !ALTIVEC_VECTOR_MODE (mode)
3374 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3375 && TARGET_POWERPC64)
3377 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3378 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3379 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3380 opnum, (enum reload_type) type);
3385 if (GET_CODE (x) == PLUS
3386 && GET_CODE (XEXP (x, 0)) == REG
3387 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3388 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3389 && GET_CODE (XEXP (x, 1)) == CONST_INT
3390 && !SPE_VECTOR_MODE (mode)
3391 && !(TARGET_E500_DOUBLE && (mode == DFmode
3393 && !ALTIVEC_VECTOR_MODE (mode))
3395 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3396 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3398 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3400 /* Check for 32-bit overflow. */
3401 if (high + low != val)
3407 /* Reload the high part into a base reg; leave the low part
3408 in the mem directly. */
3410 x = gen_rtx_PLUS (GET_MODE (x),
3411 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3415 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3416 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3417 opnum, (enum reload_type)type);
3422 if (GET_CODE (x) == SYMBOL_REF
3423 && !ALTIVEC_VECTOR_MODE (mode)
3424 && !SPE_VECTOR_MODE (mode)
3426 && DEFAULT_ABI == ABI_DARWIN
3427 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3429 && DEFAULT_ABI == ABI_V4
3432 /* Don't do this for TFmode, since the result isn't offsettable.
3433 The same goes for DImode without 64-bit gprs and DFmode
3436 && (mode != DImode || TARGET_POWERPC64)
3437 && (mode != DFmode || TARGET_POWERPC64
3438 || (TARGET_FPRS && TARGET_HARD_FLOAT)))
3443 rtx offset = gen_rtx_CONST (Pmode,
3444 gen_rtx_MINUS (Pmode, x,
3445 machopic_function_base_sym ()));
3446 x = gen_rtx_LO_SUM (GET_MODE (x),
3447 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3448 gen_rtx_HIGH (Pmode, offset)), offset);
3452 x = gen_rtx_LO_SUM (GET_MODE (x),
3453 gen_rtx_HIGH (Pmode, x), x);
3455 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3456 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3457 opnum, (enum reload_type)type);
3462 /* Reload an offset address wrapped by an AND that represents the
3463 masking of the lower bits. Strip the outer AND and let reload
3464 convert the offset address into an indirect address. */
3466 && ALTIVEC_VECTOR_MODE (mode)
3467 && GET_CODE (x) == AND
3468 && GET_CODE (XEXP (x, 0)) == PLUS
3469 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3470 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3471 && GET_CODE (XEXP (x, 1)) == CONST_INT
3472 && INTVAL (XEXP (x, 1)) == -16)
3480 && constant_pool_expr_p (x)
3481 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3483 x = create_TOC_reference (x);
3491 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3492 that is a valid memory address for an instruction.
3493 The MODE argument is the machine mode for the MEM expression
3494 that wants to use this address.
3496 On the RS/6000, there are four valid address: a SYMBOL_REF that
3497 refers to a constant pool entry of an address (or the sum of it
3498 plus a constant), a short (16-bit signed) constant plus a register,
3499 the sum of two registers, or a register indirect, possibly with an
3500 auto-increment. For DFmode and DImode with a constant plus register,
3501 we must ensure that both words are addressable or PowerPC64 with offset
3504 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3505 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3506 adjacent memory cells are accessed by adding word-sized offsets
3507 during assembly output. */
3509 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3511 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3513 && ALTIVEC_VECTOR_MODE (mode)
3514 && GET_CODE (x) == AND
3515 && GET_CODE (XEXP (x, 1)) == CONST_INT
3516 && INTVAL (XEXP (x, 1)) == -16)
3519 if (RS6000_SYMBOL_REF_TLS_P (x))
3521 if (legitimate_indirect_address_p (x, reg_ok_strict))
3523 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3524 && !ALTIVEC_VECTOR_MODE (mode)
3525 && !SPE_VECTOR_MODE (mode)
3527 /* Restrict addressing for DI because of our SUBREG hackery. */
3528 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3530 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3532 if (legitimate_small_data_p (mode, x))
3534 if (legitimate_constant_pool_address_p (x))
3536 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3538 && GET_CODE (x) == PLUS
3539 && GET_CODE (XEXP (x, 0)) == REG
3540 && (XEXP (x, 0) == virtual_stack_vars_rtx
3541 || XEXP (x, 0) == arg_pointer_rtx)
3542 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3544 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3548 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3550 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3551 && (TARGET_POWERPC64 || mode != DImode)
3552 && legitimate_indexed_address_p (x, reg_ok_strict))
3554 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3559 /* Go to LABEL if ADDR (a legitimate address expression)
3560 has an effect that depends on the machine mode it is used for.
3562 On the RS/6000 this is true of all integral offsets (since AltiVec
3563 modes don't allow them) or is a pre-increment or decrement.
3565 ??? Except that due to conceptual problems in offsettable_address_p
3566 we can't really report the problems of integral offsets. So leave
3567 this assuming that the adjustable offset must be valid for the
3568 sub-words of a TFmode operand, which is what we had before. */
3571 rs6000_mode_dependent_address (rtx addr)
3573 switch (GET_CODE (addr))
3576 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3578 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3579 return val + 12 + 0x8000 >= 0x10000;
3588 return TARGET_UPDATE;
3597 /* More elaborate version of recog's offsettable_memref_p predicate
3598 that works around the ??? note of rs6000_mode_dependent_address.
3599 In particular it accepts
3601 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
3603 in 32-bit mode, that the recog predicate rejects. */
3606 rs6000_offsettable_memref_p (rtx op)
3611 /* First mimic offsettable_memref_p. */
3612 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
3615 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
3616 the latter predicate knows nothing about the mode of the memory
3617 reference and, therefore, assumes that it is the largest supported
3618 mode (TFmode). As a consequence, legitimate offsettable memory
3619 references are rejected. rs6000_legitimate_offset_address_p contains
3620 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
3621 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
3624 /* Return number of consecutive hard regs needed starting at reg REGNO
3625 to hold something of mode MODE.
3626 This is ordinarily the length in words of a value of mode MODE
3627 but can be less for certain modes in special long registers.
3629 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3630 scalar instructions. The upper 32 bits are only available to the
3633 POWER and PowerPC GPRs hold 32 bits worth;
3634 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3637 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3639 if (FP_REGNO_P (regno))
3640 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3642 if (TARGET_E500_DOUBLE && mode == DFmode)
3645 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3646 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3648 if (ALTIVEC_REGNO_P (regno))
3650 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3652 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3655 /* Change register usage conditional on target flags. */
3657 rs6000_conditional_register_usage (void)
3661 /* Set MQ register fixed (already call_used) if not POWER
3662 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3667 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3669 fixed_regs[13] = call_used_regs[13]
3670 = call_really_used_regs[13] = 1;
3672 /* Conditionally disable FPRs. */
3673 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3674 for (i = 32; i < 64; i++)
3675 fixed_regs[i] = call_used_regs[i]
3676 = call_really_used_regs[i] = 1;
3678 /* The TOC register is not killed across calls in a way that is
3679 visible to the compiler. */
3680 if (DEFAULT_ABI == ABI_AIX)
3681 call_really_used_regs[2] = 0;
3683 if (DEFAULT_ABI == ABI_V4
3684 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3686 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3688 if (DEFAULT_ABI == ABI_V4
3689 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3691 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3692 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3693 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3695 if (DEFAULT_ABI == ABI_DARWIN
3696 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3697 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3698 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3699 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3701 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3702 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3703 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3706 global_regs[VSCR_REGNO] = 1;
3710 global_regs[SPEFSCR_REGNO] = 1;
3711 fixed_regs[FIXED_SCRATCH]
3712 = call_used_regs[FIXED_SCRATCH]
3713 = call_really_used_regs[FIXED_SCRATCH] = 1;
3716 if (! TARGET_ALTIVEC)
3718 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3719 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3720 call_really_used_regs[VRSAVE_REGNO] = 1;
3723 if (TARGET_ALTIVEC_ABI)
3724 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3725 call_used_regs[i] = call_really_used_regs[i] = 1;
3728 /* Try to output insns to set TARGET equal to the constant C if it can
3729 be done in less than N insns. Do all computations in MODE.
3730 Returns the place where the output has been placed if it can be
3731 done and the insns have been emitted. If it would take more than N
3732 insns, zero is returned and no insns and emitted. */
3735 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3736 rtx source, int n ATTRIBUTE_UNUSED)
3738 rtx result, insn, set;
3739 HOST_WIDE_INT c0, c1;
3746 dest = gen_reg_rtx (mode);
3747 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3751 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3753 emit_insn (gen_rtx_SET (VOIDmode, result,
3754 GEN_INT (INTVAL (source)
3755 & (~ (HOST_WIDE_INT) 0xffff))));
3756 emit_insn (gen_rtx_SET (VOIDmode, dest,
3757 gen_rtx_IOR (SImode, result,
3758 GEN_INT (INTVAL (source) & 0xffff))));
3763 switch (GET_CODE (source))
3766 c0 = INTVAL (source);
3771 #if HOST_BITS_PER_WIDE_INT >= 64
3772 c0 = CONST_DOUBLE_LOW (source);
3775 c0 = CONST_DOUBLE_LOW (source);
3776 c1 = CONST_DOUBLE_HIGH (source);
3784 result = rs6000_emit_set_long_const (dest, c0, c1);
3791 insn = get_last_insn ();
3792 set = single_set (insn);
3793 if (! CONSTANT_P (SET_SRC (set)))
3794 set_unique_reg_note (insn, REG_EQUAL, source);
3799 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3800 fall back to a straight forward decomposition. We do this to avoid
3801 exponential run times encountered when looking for longer sequences
3802 with rs6000_emit_set_const. */
3804 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3806 if (!TARGET_POWERPC64)
3808 rtx operand1, operand2;
3810 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3812 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3814 emit_move_insn (operand1, GEN_INT (c1));
3815 emit_move_insn (operand2, GEN_INT (c2));
3819 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3822 ud2 = (c1 & 0xffff0000) >> 16;
3823 #if HOST_BITS_PER_WIDE_INT >= 64
3827 ud4 = (c2 & 0xffff0000) >> 16;
3829 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3830 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3833 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3835 emit_move_insn (dest, GEN_INT (ud1));
3838 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3839 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3842 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3845 emit_move_insn (dest, GEN_INT (ud2 << 16));
3847 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3849 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3850 || (ud4 == 0 && ! (ud3 & 0x8000)))
3853 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3856 emit_move_insn (dest, GEN_INT (ud3 << 16));
3859 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3860 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3862 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3867 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3870 emit_move_insn (dest, GEN_INT (ud4 << 16));
3873 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3875 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3877 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3878 GEN_INT (ud2 << 16)));
3880 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3886 /* Helper for the following. Get rid of [r+r] memory refs
3887 in cases where it won't work (TImode, TFmode). */
3890 rs6000_eliminate_indexed_memrefs (rtx operands[2])
3892 if (GET_CODE (operands[0]) == MEM
3893 && GET_CODE (XEXP (operands[0], 0)) != REG
3894 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
3895 && ! reload_in_progress)
3897 = replace_equiv_address (operands[0],
3898 copy_addr_to_reg (XEXP (operands[0], 0)));
3900 if (GET_CODE (operands[1]) == MEM
3901 && GET_CODE (XEXP (operands[1], 0)) != REG
3902 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
3903 && ! reload_in_progress)
3905 = replace_equiv_address (operands[1],
3906 copy_addr_to_reg (XEXP (operands[1], 0)));
3909 /* Emit a move from SOURCE to DEST in mode MODE. */
3911 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3915 operands[1] = source;
3917 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3918 if (GET_CODE (operands[1]) == CONST_DOUBLE
3919 && ! FLOAT_MODE_P (mode)
3920 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3922 /* FIXME. This should never happen. */
3923 /* Since it seems that it does, do the safe thing and convert
3925 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3927 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
3928 || FLOAT_MODE_P (mode)
3929 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
3930 || CONST_DOUBLE_LOW (operands[1]) < 0)
3931 && (CONST_DOUBLE_HIGH (operands[1]) != -1
3932 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
3934 /* Check if GCC is setting up a block move that will end up using FP
3935 registers as temporaries. We must make sure this is acceptable. */
3936 if (GET_CODE (operands[0]) == MEM
3937 && GET_CODE (operands[1]) == MEM
3939 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3940 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3941 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3942 ? 32 : MEM_ALIGN (operands[0])))
3943 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3945 : MEM_ALIGN (operands[1]))))
3946 && ! MEM_VOLATILE_P (operands [0])
3947 && ! MEM_VOLATILE_P (operands [1]))
3949 emit_move_insn (adjust_address (operands[0], SImode, 0),
3950 adjust_address (operands[1], SImode, 0));
3951 emit_move_insn (adjust_address (operands[0], SImode, 4),
3952 adjust_address (operands[1], SImode, 4));
3956 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
3957 && !gpc_reg_operand (operands[1], mode))
3958 operands[1] = force_reg (mode, operands[1]);
3960 if (mode == SFmode && ! TARGET_POWERPC
3961 && TARGET_HARD_FLOAT && TARGET_FPRS
3962 && GET_CODE (operands[0]) == MEM)
3966 if (reload_in_progress || reload_completed)
3967 regnum = true_regnum (operands[1]);
3968 else if (GET_CODE (operands[1]) == REG)
3969 regnum = REGNO (operands[1]);
3973 /* If operands[1] is a register, on POWER it may have
3974 double-precision data in it, so truncate it to single
3976 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3979 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3980 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3981 operands[1] = newreg;
3985 /* Recognize the case where operand[1] is a reference to thread-local
3986 data and load its address to a register. */
3987 if (rs6000_tls_referenced_p (operands[1]))
3989 enum tls_model model;
3990 rtx tmp = operands[1];
3993 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
3995 addend = XEXP (XEXP (tmp, 0), 1);
3996 tmp = XEXP (XEXP (tmp, 0), 0);
3999 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
4000 model = SYMBOL_REF_TLS_MODEL (tmp);
4001 gcc_assert (model != 0);
4003 tmp = rs6000_legitimize_tls_address (tmp, model);
4006 tmp = gen_rtx_PLUS (mode, tmp, addend);
4007 tmp = force_operand (tmp, operands[0]);
4012 /* Handle the case where reload calls us with an invalid address. */
4013 if (reload_in_progress && mode == Pmode
4014 && (! general_operand (operands[1], mode)
4015 || ! nonimmediate_operand (operands[0], mode)))
4018 /* 128-bit constant floating-point values on Darwin should really be
4019 loaded as two parts. */
4020 if (!TARGET_IEEEQUAD
4021 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
4022 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4024 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4025 know how to get a DFmode SUBREG of a TFmode. */
4026 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
4027 simplify_gen_subreg (DImode, operands[1], mode, 0),
4029 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
4030 GET_MODE_SIZE (DImode)),
4031 simplify_gen_subreg (DImode, operands[1], mode,
4032 GET_MODE_SIZE (DImode)),
4037 /* FIXME: In the long term, this switch statement should go away
4038 and be replaced by a sequence of tests based on things like
4044 if (CONSTANT_P (operands[1])
4045 && GET_CODE (operands[1]) != CONST_INT)
4046 operands[1] = force_const_mem (mode, operands[1]);
4050 rs6000_eliminate_indexed_memrefs (operands);
4055 if (CONSTANT_P (operands[1])
4056 && ! easy_fp_constant (operands[1], mode))
4057 operands[1] = force_const_mem (mode, operands[1]);
4068 if (CONSTANT_P (operands[1])
4069 && !easy_vector_constant (operands[1], mode))
4070 operands[1] = force_const_mem (mode, operands[1]);
4075 /* Use default pattern for address of ELF small data */
4078 && DEFAULT_ABI == ABI_V4
4079 && (GET_CODE (operands[1]) == SYMBOL_REF
4080 || GET_CODE (operands[1]) == CONST)
4081 && small_data_operand (operands[1], mode))
4083 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4087 if (DEFAULT_ABI == ABI_V4
4088 && mode == Pmode && mode == SImode
4089 && flag_pic == 1 && got_operand (operands[1], mode))
4091 emit_insn (gen_movsi_got (operands[0], operands[1]));
4095 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4099 && CONSTANT_P (operands[1])
4100 && GET_CODE (operands[1]) != HIGH
4101 && GET_CODE (operands[1]) != CONST_INT)
4103 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
4105 /* If this is a function address on -mcall-aixdesc,
4106 convert it to the address of the descriptor. */
4107 if (DEFAULT_ABI == ABI_AIX
4108 && GET_CODE (operands[1]) == SYMBOL_REF
4109 && XSTR (operands[1], 0)[0] == '.')
4111 const char *name = XSTR (operands[1], 0);
4113 while (*name == '.')
4115 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4116 CONSTANT_POOL_ADDRESS_P (new_ref)
4117 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4118 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4119 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4120 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4121 operands[1] = new_ref;
4124 if (DEFAULT_ABI == ABI_DARWIN)
4127 if (MACHO_DYNAMIC_NO_PIC_P)
4129 /* Take care of any required data indirection. */
4130 operands[1] = rs6000_machopic_legitimize_pic_address (
4131 operands[1], mode, operands[0]);
4132 if (operands[0] != operands[1])
4133 emit_insn (gen_rtx_SET (VOIDmode,
4134 operands[0], operands[1]));
4138 emit_insn (gen_macho_high (target, operands[1]));
4139 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4143 emit_insn (gen_elf_high (target, operands[1]));
4144 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4148 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4149 and we have put it in the TOC, we just need to make a TOC-relative
4152 && GET_CODE (operands[1]) == SYMBOL_REF
4153 && constant_pool_expr_p (operands[1])
4154 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4155 get_pool_mode (operands[1])))
4157 operands[1] = create_TOC_reference (operands[1]);
4159 else if (mode == Pmode
4160 && CONSTANT_P (operands[1])
4161 && ((GET_CODE (operands[1]) != CONST_INT
4162 && ! easy_fp_constant (operands[1], mode))
4163 || (GET_CODE (operands[1]) == CONST_INT
4164 && num_insns_constant (operands[1], mode) > 2)
4165 || (GET_CODE (operands[0]) == REG
4166 && FP_REGNO_P (REGNO (operands[0]))))
4167 && GET_CODE (operands[1]) != HIGH
4168 && ! legitimate_constant_pool_address_p (operands[1])
4169 && ! toc_relative_expr_p (operands[1]))
4171 /* Emit a USE operation so that the constant isn't deleted if
4172 expensive optimizations are turned on because nobody
4173 references it. This should only be done for operands that
4174 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4175 This should not be done for operands that contain LABEL_REFs.
4176 For now, we just handle the obvious case. */
4177 if (GET_CODE (operands[1]) != LABEL_REF)
4178 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4181 /* Darwin uses a special PIC legitimizer. */
4182 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4185 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4187 if (operands[0] != operands[1])
4188 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4193 /* If we are to limit the number of things we put in the TOC and
4194 this is a symbol plus a constant we can add in one insn,
4195 just put the symbol in the TOC and add the constant. Don't do
4196 this if reload is in progress. */
4197 if (GET_CODE (operands[1]) == CONST
4198 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4199 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4200 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4201 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4202 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4203 && ! side_effects_p (operands[0]))
4206 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4207 rtx other = XEXP (XEXP (operands[1], 0), 1);
4209 sym = force_reg (mode, sym);
4211 emit_insn (gen_addsi3 (operands[0], sym, other));
4213 emit_insn (gen_adddi3 (operands[0], sym, other));
4217 operands[1] = force_const_mem (mode, operands[1]);
4220 && constant_pool_expr_p (XEXP (operands[1], 0))
4221 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4222 get_pool_constant (XEXP (operands[1], 0)),
4223 get_pool_mode (XEXP (operands[1], 0))))
4226 = gen_const_mem (mode,
4227 create_TOC_reference (XEXP (operands[1], 0)));
4228 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4234 rs6000_eliminate_indexed_memrefs (operands);
4238 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4240 gen_rtx_SET (VOIDmode,
4241 operands[0], operands[1]),
4242 gen_rtx_CLOBBER (VOIDmode,
4243 gen_rtx_SCRATCH (SImode)))));
4252 /* Above, we may have called force_const_mem which may have returned
4253 an invalid address. If we can, fix this up; otherwise, reload will
4254 have to deal with it. */
4255 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4256 operands[1] = validize_mem (operands[1]);
4259 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4262 /* Nonzero if we can use a floating-point register to pass this arg. */
4263 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4264 (SCALAR_FLOAT_MODE_P (MODE) \
4265 && !DECIMAL_FLOAT_MODE_P (MODE) \
4266 && (CUM)->fregno <= FP_ARG_MAX_REG \
4267 && TARGET_HARD_FLOAT && TARGET_FPRS)
4269 /* Nonzero if we can use an AltiVec register to pass this arg. */
4270 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4271 (ALTIVEC_VECTOR_MODE (MODE) \
4272 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4273 && TARGET_ALTIVEC_ABI \
4276 /* Return a nonzero value to say to return the function value in
4277 memory, just as large structures are always returned. TYPE will be
4278 the data type of the value, and FNTYPE will be the type of the
4279 function doing the returning, or @code{NULL} for libcalls.
4281 The AIX ABI for the RS/6000 specifies that all structures are
4282 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4283 specifies that structures <= 8 bytes are returned in r3/r4, but a
4284 draft put them in memory, and GCC used to implement the draft
4285 instead of the final standard. Therefore, aix_struct_return
4286 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4287 compatibility can change DRAFT_V4_STRUCT_RET to override the
4288 default, and -m switches get the final word. See
4289 rs6000_override_options for more details.
4291 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4292 long double support is enabled. These values are returned in memory.
4294 int_size_in_bytes returns -1 for variable size objects, which go in
4295 memory always. The cast to unsigned makes -1 > 8. */
4298 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4300 /* In the darwin64 abi, try to use registers for larger structs
4302 if (rs6000_darwin64_abi
4303 && TREE_CODE (type) == RECORD_TYPE
4304 && int_size_in_bytes (type) > 0)
4306 CUMULATIVE_ARGS valcum;
4310 valcum.fregno = FP_ARG_MIN_REG;
4311 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4312 /* Do a trial code generation as if this were going to be passed
4313 as an argument; if any part goes in memory, we return NULL. */
4314 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4317 /* Otherwise fall through to more conventional ABI rules. */
4320 if (AGGREGATE_TYPE_P (type)
4321 && (aix_struct_return
4322 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4325 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4326 modes only exist for GCC vector types if -maltivec. */
4327 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4328 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4331 /* Return synthetic vectors in memory. */
4332 if (TREE_CODE (type) == VECTOR_TYPE
4333 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4335 static bool warned_for_return_big_vectors = false;
4336 if (!warned_for_return_big_vectors)
4338 warning (0, "GCC vector returned by reference: "
4339 "non-standard ABI extension with no compatibility guarantee");
4340 warned_for_return_big_vectors = true;
4345 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4351 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4352 for a call to a function whose data type is FNTYPE.
4353 For a library call, FNTYPE is 0.
4355 For incoming args we set the number of arguments in the prototype large
4356 so we never return a PARALLEL. */
4359 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4360 rtx libname ATTRIBUTE_UNUSED, int incoming,
4361 int libcall, int n_named_args)
4363 static CUMULATIVE_ARGS zero_cumulative;
4365 *cum = zero_cumulative;
4367 cum->fregno = FP_ARG_MIN_REG;
4368 cum->vregno = ALTIVEC_ARG_MIN_REG;
4369 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4370 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4371 ? CALL_LIBCALL : CALL_NORMAL);
4372 cum->sysv_gregno = GP_ARG_MIN_REG;
4373 cum->stdarg = fntype
4374 && (TYPE_ARG_TYPES (fntype) != 0
4375 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4376 != void_type_node));
4378 cum->nargs_prototype = 0;
4379 if (incoming || cum->prototype)
4380 cum->nargs_prototype = n_named_args;
4382 /* Check for a longcall attribute. */
4383 if ((!fntype && rs6000_default_long_calls)
4385 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4386 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4387 cum->call_cookie |= CALL_LONG;
4389 if (TARGET_DEBUG_ARG)
4391 fprintf (stderr, "\ninit_cumulative_args:");
4394 tree ret_type = TREE_TYPE (fntype);
4395 fprintf (stderr, " ret code = %s,",
4396 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4399 if (cum->call_cookie & CALL_LONG)
4400 fprintf (stderr, " longcall,");
4402 fprintf (stderr, " proto = %d, nargs = %d\n",
4403 cum->prototype, cum->nargs_prototype);
4408 && TARGET_ALTIVEC_ABI
4409 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4411 error ("cannot return value in vector register because"
4412 " altivec instructions are disabled, use -maltivec"
4417 /* Return true if TYPE must be passed on the stack and not in registers. */
4420 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4422 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4423 return must_pass_in_stack_var_size (mode, type);
4425 return must_pass_in_stack_var_size_or_pad (mode, type);
4428 /* If defined, a C expression which determines whether, and in which
4429 direction, to pad out an argument with extra space. The value
4430 should be of type `enum direction': either `upward' to pad above
4431 the argument, `downward' to pad below, or `none' to inhibit
4434 For the AIX ABI structs are always stored left shifted in their
4438 function_arg_padding (enum machine_mode mode, tree type)
4440 #ifndef AGGREGATE_PADDING_FIXED
4441 #define AGGREGATE_PADDING_FIXED 0
4443 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4444 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4447 if (!AGGREGATE_PADDING_FIXED)
4449 /* GCC used to pass structures of the same size as integer types as
4450 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4451 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4452 passed padded downward, except that -mstrict-align further
4453 muddied the water in that multi-component structures of 2 and 4
4454 bytes in size were passed padded upward.
4456 The following arranges for best compatibility with previous
4457 versions of gcc, but removes the -mstrict-align dependency. */
4458 if (BYTES_BIG_ENDIAN)
4460 HOST_WIDE_INT size = 0;
4462 if (mode == BLKmode)
4464 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4465 size = int_size_in_bytes (type);
4468 size = GET_MODE_SIZE (mode);
4470 if (size == 1 || size == 2 || size == 4)
4476 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4478 if (type != 0 && AGGREGATE_TYPE_P (type))
4482 /* Fall back to the default. */
4483 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4486 /* If defined, a C expression that gives the alignment boundary, in bits,
4487 of an argument with the specified mode and type. If it is not defined,
4488 PARM_BOUNDARY is used for all arguments.
4490 V.4 wants long longs and doubles to be double word aligned. Just
4491 testing the mode size is a boneheaded way to do this as it means
4492 that other types such as complex int are also double word aligned.
4493 However, we're stuck with this because changing the ABI might break
4494 existing library interfaces.
4496 Doubleword align SPE vectors.
4497 Quadword align Altivec vectors.
4498 Quadword align large synthetic vector types. */
4501 function_arg_boundary (enum machine_mode mode, tree type)
4503 if (DEFAULT_ABI == ABI_V4
4504 && (GET_MODE_SIZE (mode) == 8
4505 || (TARGET_HARD_FLOAT
4507 && mode == TFmode)))
4509 else if (SPE_VECTOR_MODE (mode)
4510 || (type && TREE_CODE (type) == VECTOR_TYPE
4511 && int_size_in_bytes (type) >= 8
4512 && int_size_in_bytes (type) < 16))
4514 else if (ALTIVEC_VECTOR_MODE (mode)
4515 || (type && TREE_CODE (type) == VECTOR_TYPE
4516 && int_size_in_bytes (type) >= 16))
4518 else if (rs6000_darwin64_abi && mode == BLKmode
4519 && type && TYPE_ALIGN (type) > 64)
4522 return PARM_BOUNDARY;
4525 /* For a function parm of MODE and TYPE, return the starting word in
4526 the parameter area. NWORDS of the parameter area are already used. */
4529 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4532 unsigned int parm_offset;
4534 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4535 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4536 return nwords + (-(parm_offset + nwords) & align);
4539 /* Compute the size (in words) of a function argument. */
4541 static unsigned long
4542 rs6000_arg_size (enum machine_mode mode, tree type)
4546 if (mode != BLKmode)
4547 size = GET_MODE_SIZE (mode);
4549 size = int_size_in_bytes (type);
4552 return (size + 3) >> 2;
4554 return (size + 7) >> 3;
4557 /* Use this to flush pending int fields. */
4560 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4561 HOST_WIDE_INT bitpos)
4563 unsigned int startbit, endbit;
4564 int intregs, intoffset;
4565 enum machine_mode mode;
4567 if (cum->intoffset == -1)
4570 intoffset = cum->intoffset;
4571 cum->intoffset = -1;
4573 if (intoffset % BITS_PER_WORD != 0)
4575 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4577 if (mode == BLKmode)
4579 /* We couldn't find an appropriate mode, which happens,
4580 e.g., in packed structs when there are 3 bytes to load.
4581 Back intoffset back to the beginning of the word in this
4583 intoffset = intoffset & -BITS_PER_WORD;
4587 startbit = intoffset & -BITS_PER_WORD;
4588 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4589 intregs = (endbit - startbit) / BITS_PER_WORD;
4590 cum->words += intregs;
4593 /* The darwin64 ABI calls for us to recurse down through structs,
4594 looking for elements passed in registers. Unfortunately, we have
4595 to track int register count here also because of misalignments
4596 in powerpc alignment mode. */
4599 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4601 HOST_WIDE_INT startbitpos)
4605 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4606 if (TREE_CODE (f) == FIELD_DECL)
4608 HOST_WIDE_INT bitpos = startbitpos;
4609 tree ftype = TREE_TYPE (f);
4610 enum machine_mode mode;
4611 if (ftype == error_mark_node)
4613 mode = TYPE_MODE (ftype);
4615 if (DECL_SIZE (f) != 0
4616 && host_integerp (bit_position (f), 1))
4617 bitpos += int_bit_position (f);
4619 /* ??? FIXME: else assume zero offset. */
4621 if (TREE_CODE (ftype) == RECORD_TYPE)
4622 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4623 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4625 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4626 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4627 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4629 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4631 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4635 else if (cum->intoffset == -1)
4636 cum->intoffset = bitpos;
4640 /* Update the data in CUM to advance over an argument
4641 of mode MODE and data type TYPE.
4642 (TYPE is null for libcalls where that information may not be available.)
4644 Note that for args passed by reference, function_arg will be called
4645 with MODE and TYPE set to that of the pointer to the arg, not the arg
4649 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4650 tree type, int named, int depth)
4654 /* Only tick off an argument if we're not recursing. */
4656 cum->nargs_prototype--;
4658 if (TARGET_ALTIVEC_ABI
4659 && (ALTIVEC_VECTOR_MODE (mode)
4660 || (type && TREE_CODE (type) == VECTOR_TYPE
4661 && int_size_in_bytes (type) == 16)))
4665 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4668 if (!TARGET_ALTIVEC)
4669 error ("cannot pass argument in vector register because"
4670 " altivec instructions are disabled, use -maltivec"
4673 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4674 even if it is going to be passed in a vector register.
4675 Darwin does the same for variable-argument functions. */
4676 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4677 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4687 /* Vector parameters must be 16-byte aligned. This places
4688 them at 2 mod 4 in terms of words in 32-bit mode, since
4689 the parameter save area starts at offset 24 from the
4690 stack. In 64-bit mode, they just have to start on an
4691 even word, since the parameter save area is 16-byte
4692 aligned. Space for GPRs is reserved even if the argument
4693 will be passed in memory. */
4695 align = (2 - cum->words) & 3;
4697 align = cum->words & 1;
4698 cum->words += align + rs6000_arg_size (mode, type);
4700 if (TARGET_DEBUG_ARG)
4702 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4704 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4705 cum->nargs_prototype, cum->prototype,
4706 GET_MODE_NAME (mode));
4710 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4712 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4715 else if (rs6000_darwin64_abi
4717 && TREE_CODE (type) == RECORD_TYPE
4718 && (size = int_size_in_bytes (type)) > 0)
4720 /* Variable sized types have size == -1 and are
4721 treated as if consisting entirely of ints.
4722 Pad to 16 byte boundary if needed. */
4723 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4724 && (cum->words % 2) != 0)
4726 /* For varargs, we can just go up by the size of the struct. */
4728 cum->words += (size + 7) / 8;
4731 /* It is tempting to say int register count just goes up by
4732 sizeof(type)/8, but this is wrong in a case such as
4733 { int; double; int; } [powerpc alignment]. We have to
4734 grovel through the fields for these too. */
4736 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4737 rs6000_darwin64_record_arg_advance_flush (cum,
4738 size * BITS_PER_UNIT);
4741 else if (DEFAULT_ABI == ABI_V4)
4743 if (TARGET_HARD_FLOAT && TARGET_FPRS
4744 && (mode == SFmode || mode == DFmode
4745 || (mode == TFmode && !TARGET_IEEEQUAD)))
4747 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
4748 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4751 cum->fregno = FP_ARG_V4_MAX_REG + 1;
4752 if (mode == DFmode || mode == TFmode)
4753 cum->words += cum->words & 1;
4754 cum->words += rs6000_arg_size (mode, type);
4759 int n_words = rs6000_arg_size (mode, type);
4760 int gregno = cum->sysv_gregno;
4762 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4763 (r7,r8) or (r9,r10). As does any other 2 word item such
4764 as complex int due to a historical mistake. */
4766 gregno += (1 - gregno) & 1;
4768 /* Multi-reg args are not split between registers and stack. */
4769 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4771 /* Long long and SPE vectors are aligned on the stack.
4772 So are other 2 word items such as complex int due to
4773 a historical mistake. */
4775 cum->words += cum->words & 1;
4776 cum->words += n_words;
4779 /* Note: continuing to accumulate gregno past when we've started
4780 spilling to the stack indicates the fact that we've started
4781 spilling to the stack to expand_builtin_saveregs. */
4782 cum->sysv_gregno = gregno + n_words;
4785 if (TARGET_DEBUG_ARG)
4787 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4788 cum->words, cum->fregno);
4789 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4790 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4791 fprintf (stderr, "mode = %4s, named = %d\n",
4792 GET_MODE_NAME (mode), named);
4797 int n_words = rs6000_arg_size (mode, type);
4798 int start_words = cum->words;
4799 int align_words = rs6000_parm_start (mode, type, start_words);
4801 cum->words = align_words + n_words;
4803 if (SCALAR_FLOAT_MODE_P (mode)
4804 && !DECIMAL_FLOAT_MODE_P (mode)
4805 && TARGET_HARD_FLOAT && TARGET_FPRS)
4806 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4808 if (TARGET_DEBUG_ARG)
4810 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4811 cum->words, cum->fregno);
4812 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4813 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4814 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
4815 named, align_words - start_words, depth);
4821 spe_build_register_parallel (enum machine_mode mode, int gregno)
4828 r1 = gen_rtx_REG (DImode, gregno);
4829 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4830 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
4833 r1 = gen_rtx_REG (DImode, gregno);
4834 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4835 r3 = gen_rtx_REG (DImode, gregno + 2);
4836 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4837 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
4844 /* Determine where to put a SIMD argument on the SPE. */
4846 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4849 int gregno = cum->sysv_gregno;
4851 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4852 are passed and returned in a pair of GPRs for ABI compatibility. */
4853 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
4855 int n_words = rs6000_arg_size (mode, type);
4857 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4859 gregno += (1 - gregno) & 1;
4861 /* Multi-reg args are not split between registers and stack. */
4862 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4865 return spe_build_register_parallel (mode, gregno);
4869 int n_words = rs6000_arg_size (mode, type);
4871 /* SPE vectors are put in odd registers. */
4872 if (n_words == 2 && (gregno & 1) == 0)
4875 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4878 enum machine_mode m = SImode;
4880 r1 = gen_rtx_REG (m, gregno);
4881 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4882 r2 = gen_rtx_REG (m, gregno + 1);
4883 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4884 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4891 if (gregno <= GP_ARG_MAX_REG)
4892 return gen_rtx_REG (mode, gregno);
4898 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4899 structure between cum->intoffset and bitpos to integer registers. */
4902 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4903 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
4905 enum machine_mode mode;
4907 unsigned int startbit, endbit;
4908 int this_regno, intregs, intoffset;
4911 if (cum->intoffset == -1)
4914 intoffset = cum->intoffset;
4915 cum->intoffset = -1;
4917 /* If this is the trailing part of a word, try to only load that
4918 much into the register. Otherwise load the whole register. Note
4919 that in the latter case we may pick up unwanted bits. It's not a
4920 problem at the moment but may wish to revisit. */
4922 if (intoffset % BITS_PER_WORD != 0)
4924 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4926 if (mode == BLKmode)
4928 /* We couldn't find an appropriate mode, which happens,
4929 e.g., in packed structs when there are 3 bytes to load.
4930 Back intoffset back to the beginning of the word in this
4932 intoffset = intoffset & -BITS_PER_WORD;
4939 startbit = intoffset & -BITS_PER_WORD;
4940 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4941 intregs = (endbit - startbit) / BITS_PER_WORD;
4942 this_regno = cum->words + intoffset / BITS_PER_WORD;
4944 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4947 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4951 intoffset /= BITS_PER_UNIT;
4954 regno = GP_ARG_MIN_REG + this_regno;
4955 reg = gen_rtx_REG (mode, regno);
4957 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4960 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4964 while (intregs > 0);
4967 /* Recursive workhorse for the following. */
4970 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4971 HOST_WIDE_INT startbitpos, rtx rvec[],
4976 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4977 if (TREE_CODE (f) == FIELD_DECL)
4979 HOST_WIDE_INT bitpos = startbitpos;
4980 tree ftype = TREE_TYPE (f);
4981 enum machine_mode mode;
4982 if (ftype == error_mark_node)
4984 mode = TYPE_MODE (ftype);
4986 if (DECL_SIZE (f) != 0
4987 && host_integerp (bit_position (f), 1))
4988 bitpos += int_bit_position (f);
4990 /* ??? FIXME: else assume zero offset. */
4992 if (TREE_CODE (ftype) == RECORD_TYPE)
4993 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4994 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
4999 case SCmode: mode = SFmode; break;
5000 case DCmode: mode = DFmode; break;
5001 case TCmode: mode = TFmode; break;
5005 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5007 = gen_rtx_EXPR_LIST (VOIDmode,
5008 gen_rtx_REG (mode, cum->fregno++),
5009 GEN_INT (bitpos / BITS_PER_UNIT));
5013 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
5015 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5017 = gen_rtx_EXPR_LIST (VOIDmode,
5018 gen_rtx_REG (mode, cum->vregno++),
5019 GEN_INT (bitpos / BITS_PER_UNIT));
5021 else if (cum->intoffset == -1)
5022 cum->intoffset = bitpos;
5026 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5027 the register(s) to be used for each field and subfield of a struct
5028 being passed by value, along with the offset of where the
5029 register's value may be found in the block. FP fields go in FP
5030 register, vector fields go in vector registers, and everything
5031 else goes in int registers, packed as in memory.
5033 This code is also used for function return values. RETVAL indicates
5034 whether this is the case.
5036 Much of this is taken from the SPARC V9 port, which has a similar
5037 calling convention. */
5040 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
5041 int named, bool retval)
5043 rtx rvec[FIRST_PSEUDO_REGISTER];
5044 int k = 1, kbase = 1;
5045 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5046 /* This is a copy; modifications are not visible to our caller. */
5047 CUMULATIVE_ARGS copy_cum = *orig_cum;
5048 CUMULATIVE_ARGS *cum = ©_cum;
5050 /* Pad to 16 byte boundary if needed. */
5051 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5052 && (cum->words % 2) != 0)
5059 /* Put entries into rvec[] for individual FP and vector fields, and
5060 for the chunks of memory that go in int regs. Note we start at
5061 element 1; 0 is reserved for an indication of using memory, and
5062 may or may not be filled in below. */
5063 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5064 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5066 /* If any part of the struct went on the stack put all of it there.
5067 This hack is because the generic code for
5068 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5069 parts of the struct are not at the beginning. */
5073 return NULL_RTX; /* doesn't go in registers at all */
5075 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5077 if (k > 1 || cum->use_stack)
5078 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5083 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5086 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5090 rtx rvec[GP_ARG_NUM_REG + 1];
5092 if (align_words >= GP_ARG_NUM_REG)
5095 n_units = rs6000_arg_size (mode, type);
5097 /* Optimize the simple case where the arg fits in one gpr, except in
5098 the case of BLKmode due to assign_parms assuming that registers are
5099 BITS_PER_WORD wide. */
5101 || (n_units == 1 && mode != BLKmode))
5102 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5105 if (align_words + n_units > GP_ARG_NUM_REG)
5106 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5107 using a magic NULL_RTX component.
5108 This is not strictly correct. Only some of the arg belongs in
5109 memory, not all of it. However, the normal scheme using
5110 function_arg_partial_nregs can result in unusual subregs, eg.
5111 (subreg:SI (reg:DF) 4), which are not handled well. The code to
5112 store the whole arg to memory is often more efficient than code
5113 to store pieces, and we know that space is available in the right
5114 place for the whole arg. */
5115 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5120 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5121 rtx off = GEN_INT (i++ * 4);
5122 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5124 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5126 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5129 /* Determine where to put an argument to a function.
5130 Value is zero to push the argument on the stack,
5131 or a hard register in which to store the argument.
5133 MODE is the argument's machine mode.
5134 TYPE is the data type of the argument (as a tree).
5135 This is null for libcalls where that information may
5137 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5138 the preceding args and about the function being called. It is
5139 not modified in this routine.
5140 NAMED is nonzero if this argument is a named parameter
5141 (otherwise it is an extra parameter matching an ellipsis).
5143 On RS/6000 the first eight words of non-FP are normally in registers
5144 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5145 Under V.4, the first 8 FP args are in registers.
5147 If this is floating-point and no prototype is specified, we use
5148 both an FP and integer register (or possibly FP reg and stack). Library
5149 functions (when CALL_LIBCALL is set) always have the proper types for args,
5150 so we can pass the FP value just in one register. emit_library_function
5151 doesn't support PARALLEL anyway.
5153 Note that for args passed by reference, function_arg will be called
5154 with MODE and TYPE set to that of the pointer to the arg, not the arg
5158 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5159 tree type, int named)
5161 enum rs6000_abi abi = DEFAULT_ABI;
5163 /* Return a marker to indicate whether CR1 needs to set or clear the
5164 bit that V.4 uses to say fp args were passed in registers.
5165 Assume that we don't need the marker for software floating point,
5166 or compiler generated library calls. */
5167 if (mode == VOIDmode)
5170 && (cum->call_cookie & CALL_LIBCALL) == 0
5172 || (cum->nargs_prototype < 0
5173 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5175 /* For the SPE, we need to crxor CR6 always. */
5177 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5178 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5179 return GEN_INT (cum->call_cookie
5180 | ((cum->fregno == FP_ARG_MIN_REG)
5181 ? CALL_V4_SET_FP_ARGS
5182 : CALL_V4_CLEAR_FP_ARGS));
5185 return GEN_INT (cum->call_cookie);
5188 if (rs6000_darwin64_abi && mode == BLKmode
5189 && TREE_CODE (type) == RECORD_TYPE)
5191 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5192 if (rslt != NULL_RTX)
5194 /* Else fall through to usual handling. */
5197 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5198 if (TARGET_64BIT && ! cum->prototype)
5200 /* Vector parameters get passed in vector register
5201 and also in GPRs or memory, in absence of prototype. */
5204 align_words = (cum->words + 1) & ~1;
5206 if (align_words >= GP_ARG_NUM_REG)
5212 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5214 return gen_rtx_PARALLEL (mode,
5216 gen_rtx_EXPR_LIST (VOIDmode,
5218 gen_rtx_EXPR_LIST (VOIDmode,
5219 gen_rtx_REG (mode, cum->vregno),
5223 return gen_rtx_REG (mode, cum->vregno);
5224 else if (TARGET_ALTIVEC_ABI
5225 && (ALTIVEC_VECTOR_MODE (mode)
5226 || (type && TREE_CODE (type) == VECTOR_TYPE
5227 && int_size_in_bytes (type) == 16)))
5229 if (named || abi == ABI_V4)
5233 /* Vector parameters to varargs functions under AIX or Darwin
5234 get passed in memory and possibly also in GPRs. */
5235 int align, align_words, n_words;
5236 enum machine_mode part_mode;
5238 /* Vector parameters must be 16-byte aligned. This places them at
5239 2 mod 4 in terms of words in 32-bit mode, since the parameter
5240 save area starts at offset 24 from the stack. In 64-bit mode,
5241 they just have to start on an even word, since the parameter
5242 save area is 16-byte aligned. */
5244 align = (2 - cum->words) & 3;
5246 align = cum->words & 1;
5247 align_words = cum->words + align;
5249 /* Out of registers? Memory, then. */
5250 if (align_words >= GP_ARG_NUM_REG)
5253 if (TARGET_32BIT && TARGET_POWERPC64)
5254 return rs6000_mixed_function_arg (mode, type, align_words);
5256 /* The vector value goes in GPRs. Only the part of the
5257 value in GPRs is reported here. */
5259 n_words = rs6000_arg_size (mode, type);
5260 if (align_words + n_words > GP_ARG_NUM_REG)
5261 /* Fortunately, there are only two possibilities, the value
5262 is either wholly in GPRs or half in GPRs and half not. */
5265 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5268 else if (TARGET_SPE_ABI && TARGET_SPE
5269 && (SPE_VECTOR_MODE (mode)
5270 || (TARGET_E500_DOUBLE && (mode == DFmode
5271 || mode == DCmode))))
5272 return rs6000_spe_function_arg (cum, mode, type);
5274 else if (abi == ABI_V4)
5276 if (TARGET_HARD_FLOAT && TARGET_FPRS
5277 && (mode == SFmode || mode == DFmode
5278 || (mode == TFmode && !TARGET_IEEEQUAD)))
5280 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
5281 return gen_rtx_REG (mode, cum->fregno);
5287 int n_words = rs6000_arg_size (mode, type);
5288 int gregno = cum->sysv_gregno;
5290 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5291 (r7,r8) or (r9,r10). As does any other 2 word item such
5292 as complex int due to a historical mistake. */
5294 gregno += (1 - gregno) & 1;
5296 /* Multi-reg args are not split between registers and stack. */
5297 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5300 if (TARGET_32BIT && TARGET_POWERPC64)
5301 return rs6000_mixed_function_arg (mode, type,
5302 gregno - GP_ARG_MIN_REG);
5303 return gen_rtx_REG (mode, gregno);
5308 int align_words = rs6000_parm_start (mode, type, cum->words);
5310 if (USE_FP_FOR_ARG_P (cum, mode, type))
5312 rtx rvec[GP_ARG_NUM_REG + 1];
5316 enum machine_mode fmode = mode;
5317 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5319 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5321 /* Currently, we only ever need one reg here because complex
5322 doubles are split. */
5323 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);
5325 /* Long double split over regs and memory. */
5329 /* Do we also need to pass this arg in the parameter save
5332 && (cum->nargs_prototype <= 0
5333 || (DEFAULT_ABI == ABI_AIX
5335 && align_words >= GP_ARG_NUM_REG)));
5337 if (!needs_psave && mode == fmode)
5338 return gen_rtx_REG (fmode, cum->fregno);
5343 /* Describe the part that goes in gprs or the stack.
5344 This piece must come first, before the fprs. */
5345 if (align_words < GP_ARG_NUM_REG)
5347 unsigned long n_words = rs6000_arg_size (mode, type);
5349 if (align_words + n_words > GP_ARG_NUM_REG
5350 || (TARGET_32BIT && TARGET_POWERPC64))
5352 /* If this is partially on the stack, then we only
5353 include the portion actually in registers here. */
5354 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5357 if (align_words + n_words > GP_ARG_NUM_REG)
5358 /* Not all of the arg fits in gprs. Say that it
5359 goes in memory too, using a magic NULL_RTX
5360 component. Also see comment in
5361 rs6000_mixed_function_arg for why the normal
5362 function_arg_partial_nregs scheme doesn't work
5364 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5368 r = gen_rtx_REG (rmode,
5369 GP_ARG_MIN_REG + align_words);
5370 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5371 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5373 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5377 /* The whole arg fits in gprs. */
5378 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5379 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5383 /* It's entirely in memory. */
5384 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5387 /* Describe where this piece goes in the fprs. */
5388 r = gen_rtx_REG (fmode, cum->fregno);
5389 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5391 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5393 else if (align_words < GP_ARG_NUM_REG)
5395 if (TARGET_32BIT && TARGET_POWERPC64)
5396 return rs6000_mixed_function_arg (mode, type, align_words);
5398 if (mode == BLKmode)
5401 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5408 /* For an arg passed partly in registers and partly in memory, this is
5409 the number of bytes passed in registers. For args passed entirely in
5410 registers or entirely in memory, zero. When an arg is described by a
5411 PARALLEL, perhaps using more than one register type, this function
5412 returns the number of bytes used by the first element of the PARALLEL. */
5415 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5416 tree type, bool named)
5421 if (DEFAULT_ABI == ABI_V4)
5424 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5425 && cum->nargs_prototype >= 0)
5428 /* In this complicated case we just disable the partial_nregs code. */
5429 if (rs6000_darwin64_abi && mode == BLKmode
5430 && TREE_CODE (type) == RECORD_TYPE
5431 && int_size_in_bytes (type) > 0)
5434 align_words = rs6000_parm_start (mode, type, cum->words);
5436 if (USE_FP_FOR_ARG_P (cum, mode, type))
5438 /* If we are passing this arg in the fixed parameter save area
5439 (gprs or memory) as well as fprs, then this function should
5440 return the number of partial bytes passed in the parameter
5441 save area rather than partial bytes passed in fprs. */
5443 && (cum->nargs_prototype <= 0
5444 || (DEFAULT_ABI == ABI_AIX
5446 && align_words >= GP_ARG_NUM_REG)))
5448 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
5449 > FP_ARG_MAX_REG + 1)
5450 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5451 else if (cum->nargs_prototype >= 0)
5455 if (align_words < GP_ARG_NUM_REG
5456 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5457 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5459 if (ret != 0 && TARGET_DEBUG_ARG)
5460 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5465 /* A C expression that indicates when an argument must be passed by
5466 reference. If nonzero for an argument, a copy of that argument is
5467 made in memory and a pointer to the argument is passed instead of
5468 the argument itself. The pointer is passed in whatever way is
5469 appropriate for passing a pointer to that type.
5471 Under V.4, aggregates and long double are passed by reference.
5473 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5474 reference unless the AltiVec vector extension ABI is in force.
5476 As an extension to all ABIs, variable sized types are passed by
5480 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5481 enum machine_mode mode, tree type,
5482 bool named ATTRIBUTE_UNUSED)
5484 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
5486 if (TARGET_DEBUG_ARG)
5487 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5494 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5496 if (TARGET_DEBUG_ARG)
5497 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5501 if (int_size_in_bytes (type) < 0)
5503 if (TARGET_DEBUG_ARG)
5504 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5508 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5509 modes only exist for GCC vector types if -maltivec. */
5510 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5512 if (TARGET_DEBUG_ARG)
5513 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5517 /* Pass synthetic vectors in memory. */
5518 if (TREE_CODE (type) == VECTOR_TYPE
5519 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5521 static bool warned_for_pass_big_vectors = false;
5522 if (TARGET_DEBUG_ARG)
5523 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5524 if (!warned_for_pass_big_vectors)
5526 warning (0, "GCC vector passed by reference: "
5527 "non-standard ABI extension with no compatibility guarantee");
5528 warned_for_pass_big_vectors = true;
5537 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5540 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5545 for (i = 0; i < nregs; i++)
5547 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5548 if (reload_completed)
5550 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5553 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5554 i * GET_MODE_SIZE (reg_mode));
5557 tem = replace_equiv_address (tem, XEXP (tem, 0));
5561 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5565 /* Perform any needed actions needed for a function that is receiving a
5566 variable number of arguments.
5570 MODE and TYPE are the mode and type of the current parameter.
5572 PRETEND_SIZE is a variable that should be set to the amount of stack
5573 that must be pushed by the prolog to pretend that our caller pushed
5576 Normally, this macro will push all remaining incoming registers on the
5577 stack and set PRETEND_SIZE to the length of the registers pushed. */
5580 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5581 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5584 CUMULATIVE_ARGS next_cum;
5585 int reg_size = TARGET_32BIT ? 4 : 8;
5586 rtx save_area = NULL_RTX, mem;
5587 int first_reg_offset, set;
5589 /* Skip the last named argument. */
5591 function_arg_advance (&next_cum, mode, type, 1, 0);
5593 if (DEFAULT_ABI == ABI_V4)
5595 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5599 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
5600 HOST_WIDE_INT offset = 0;
5602 /* Try to optimize the size of the varargs save area.
5603 The ABI requires that ap.reg_save_area is doubleword
5604 aligned, but we don't need to allocate space for all
5605 the bytes, only those to which we actually will save
5607 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
5608 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
5609 if (TARGET_HARD_FLOAT && TARGET_FPRS
5610 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5611 && cfun->va_list_fpr_size)
5614 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
5615 * UNITS_PER_FP_WORD;
5616 if (cfun->va_list_fpr_size
5617 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5618 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
5620 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5621 * UNITS_PER_FP_WORD;
5625 offset = -((first_reg_offset * reg_size) & ~7);
5626 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
5628 gpr_reg_num = cfun->va_list_gpr_size;
5629 if (reg_size == 4 && (first_reg_offset & 1))
5632 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
5635 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
5637 - (int) (GP_ARG_NUM_REG * reg_size);
5639 if (gpr_size + fpr_size)
5642 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
5643 gcc_assert (GET_CODE (reg_save_area) == MEM);
5644 reg_save_area = XEXP (reg_save_area, 0);
5645 if (GET_CODE (reg_save_area) == PLUS)
5647 gcc_assert (XEXP (reg_save_area, 0)
5648 == virtual_stack_vars_rtx);
5649 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
5650 offset += INTVAL (XEXP (reg_save_area, 1));
5653 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
5656 cfun->machine->varargs_save_offset = offset;
5657 save_area = plus_constant (virtual_stack_vars_rtx, offset);
5662 first_reg_offset = next_cum.words;
5663 save_area = virtual_incoming_args_rtx;
5665 if (targetm.calls.must_pass_in_stack (mode, type))
5666 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5669 set = get_varargs_alias_set ();
5670 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5671 && cfun->va_list_gpr_size)
5673 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5675 if (va_list_gpr_counter_field)
5677 /* V4 va_list_gpr_size counts number of registers needed. */
5678 if (nregs > cfun->va_list_gpr_size)
5679 nregs = cfun->va_list_gpr_size;
5683 /* char * va_list instead counts number of bytes needed. */
5684 if (nregs > cfun->va_list_gpr_size / reg_size)
5685 nregs = cfun->va_list_gpr_size / reg_size;
5688 mem = gen_rtx_MEM (BLKmode,
5689 plus_constant (save_area,
5690 first_reg_offset * reg_size));
5691 MEM_NOTRAP_P (mem) = 1;
5692 set_mem_alias_set (mem, set);
5693 set_mem_align (mem, BITS_PER_WORD);
5695 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5699 /* Save FP registers if needed. */
5700 if (DEFAULT_ABI == ABI_V4
5701 && TARGET_HARD_FLOAT && TARGET_FPRS
5703 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5704 && cfun->va_list_fpr_size)
5706 int fregno = next_cum.fregno, nregs;
5707 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5708 rtx lab = gen_label_rtx ();
5709 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
5710 * UNITS_PER_FP_WORD);
5713 (gen_rtx_SET (VOIDmode,
5715 gen_rtx_IF_THEN_ELSE (VOIDmode,
5716 gen_rtx_NE (VOIDmode, cr1,
5718 gen_rtx_LABEL_REF (VOIDmode, lab),
5722 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
5723 fregno++, off += UNITS_PER_FP_WORD, nregs++)
5725 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5726 MEM_NOTRAP_P (mem) = 1;
5727 set_mem_alias_set (mem, set);
5728 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5729 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5736 /* Create the va_list data type. */
5739 rs6000_build_builtin_va_list (void)
5741 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5743 /* For AIX, prefer 'char *' because that's what the system
5744 header files like. */
5745 if (DEFAULT_ABI != ABI_V4)
5746 return build_pointer_type (char_type_node);
5748 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5749 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5751 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5752 unsigned_char_type_node);
5753 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5754 unsigned_char_type_node);
5755 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5757 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5758 short_unsigned_type_node);
5759 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5761 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5764 va_list_gpr_counter_field = f_gpr;
5765 va_list_fpr_counter_field = f_fpr;
5767 DECL_FIELD_CONTEXT (f_gpr) = record;
5768 DECL_FIELD_CONTEXT (f_fpr) = record;
5769 DECL_FIELD_CONTEXT (f_res) = record;
5770 DECL_FIELD_CONTEXT (f_ovf) = record;
5771 DECL_FIELD_CONTEXT (f_sav) = record;
5773 TREE_CHAIN (record) = type_decl;
5774 TYPE_NAME (record) = type_decl;
5775 TYPE_FIELDS (record) = f_gpr;
5776 TREE_CHAIN (f_gpr) = f_fpr;
5777 TREE_CHAIN (f_fpr) = f_res;
5778 TREE_CHAIN (f_res) = f_ovf;
5779 TREE_CHAIN (f_ovf) = f_sav;
5781 layout_type (record);
5783 /* The correct type is an array type of one element. */
5784 return build_array_type (record, build_index_type (size_zero_node));
5787 /* Implement va_start. */
5790 rs6000_va_start (tree valist, rtx nextarg)
5792 HOST_WIDE_INT words, n_gpr, n_fpr;
5793 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5794 tree gpr, fpr, ovf, sav, t;
5796 /* Only SVR4 needs something special. */
5797 if (DEFAULT_ABI != ABI_V4)
5799 std_expand_builtin_va_start (valist, nextarg);
5803 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5804 f_fpr = TREE_CHAIN (f_gpr);
5805 f_res = TREE_CHAIN (f_fpr);
5806 f_ovf = TREE_CHAIN (f_res);
5807 f_sav = TREE_CHAIN (f_ovf);
5809 valist = build_va_arg_indirect_ref (valist);
5810 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5811 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5812 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5813 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5815 /* Count number of gp and fp argument registers used. */
5816 words = current_function_args_info.words;
5817 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5819 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5822 if (TARGET_DEBUG_ARG)
5823 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5824 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5825 words, n_gpr, n_fpr);
5827 if (cfun->va_list_gpr_size)
5829 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5830 build_int_cst (NULL_TREE, n_gpr));
5831 TREE_SIDE_EFFECTS (t) = 1;
5832 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5835 if (cfun->va_list_fpr_size)
5837 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5838 build_int_cst (NULL_TREE, n_fpr));
5839 TREE_SIDE_EFFECTS (t) = 1;
5840 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5843 /* Find the overflow area. */
5844 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5846 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t,
5847 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5848 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5849 TREE_SIDE_EFFECTS (t) = 1;
5850 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5852 /* If there were no va_arg invocations, don't set up the register
5854 if (!cfun->va_list_gpr_size
5855 && !cfun->va_list_fpr_size
5856 && n_gpr < GP_ARG_NUM_REG
5857 && n_fpr < FP_ARG_V4_MAX_REG)
5860 /* Find the register save area. */
5861 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5862 if (cfun->machine->varargs_save_offset)
5863 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
5864 build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset));
5865 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5866 TREE_SIDE_EFFECTS (t) = 1;
5867 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5870 /* Implement va_arg. */
5873 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5875 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5876 tree gpr, fpr, ovf, sav, reg, t, u;
5877 int size, rsize, n_reg, sav_ofs, sav_scale;
5878 tree lab_false, lab_over, addr;
5880 tree ptrtype = build_pointer_type (type);
5882 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5884 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5885 return build_va_arg_indirect_ref (t);
5888 if (DEFAULT_ABI != ABI_V4)
5890 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5892 tree elem_type = TREE_TYPE (type);
5893 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5894 int elem_size = GET_MODE_SIZE (elem_mode);
5896 if (elem_size < UNITS_PER_WORD)
5898 tree real_part, imag_part;
5899 tree post = NULL_TREE;
5901 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5903 /* Copy the value into a temporary, lest the formal temporary
5904 be reused out from under us. */
5905 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5906 append_to_statement_list (post, pre_p);
5908 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5911 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
5915 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5918 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5919 f_fpr = TREE_CHAIN (f_gpr);
5920 f_res = TREE_CHAIN (f_fpr);
5921 f_ovf = TREE_CHAIN (f_res);
5922 f_sav = TREE_CHAIN (f_ovf);
5924 valist = build_va_arg_indirect_ref (valist);
5925 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5926 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5927 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5928 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5930 size = int_size_in_bytes (type);
5931 rsize = (size + 3) / 4;
5934 if (TARGET_HARD_FLOAT && TARGET_FPRS
5935 && (TYPE_MODE (type) == SFmode
5936 || TYPE_MODE (type) == DFmode
5937 || TYPE_MODE (type) == TFmode))
5939 /* FP args go in FP registers, if present. */
5941 n_reg = (size + 7) / 8;
5944 if (TYPE_MODE (type) != SFmode)
5949 /* Otherwise into GP registers. */
5958 /* Pull the value out of the saved registers.... */
5961 addr = create_tmp_var (ptr_type_node, "addr");
5962 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5964 /* AltiVec vectors never go in registers when -mabi=altivec. */
5965 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5969 lab_false = create_artificial_label ();
5970 lab_over = create_artificial_label ();
5972 /* Long long and SPE vectors are aligned in the registers.
5973 As are any other 2 gpr item such as complex int due to a
5974 historical mistake. */
5976 if (n_reg == 2 && reg == gpr)
5978 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5979 size_int (n_reg - 1));
5980 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5983 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5984 t = build2 (GE_EXPR, boolean_type_node, u, t);
5985 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5986 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5987 gimplify_and_add (t, pre_p);
5991 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5993 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5994 u = build1 (CONVERT_EXPR, integer_type_node, u);
5995 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5996 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5998 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5999 gimplify_and_add (t, pre_p);
6001 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6002 gimplify_and_add (t, pre_p);
6004 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6005 append_to_statement_list (t, pre_p);
6007 if ((n_reg == 2 && reg != gpr) || n_reg > 2)
6009 /* Ensure that we don't find any more args in regs.
6010 Alignment has taken care of the n_reg == 2 gpr case. */
6011 t = build2 (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
6012 gimplify_and_add (t, pre_p);
6016 /* ... otherwise out of the overflow area. */
6018 /* Care for on-stack alignment if needed. */
6022 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6023 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6024 build_int_cst (NULL_TREE, -align));
6026 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6028 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
6029 gimplify_and_add (u, pre_p);
6031 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6032 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
6033 gimplify_and_add (t, pre_p);
6037 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6038 append_to_statement_list (t, pre_p);
6041 addr = fold_convert (ptrtype, addr);
6042 return build_va_arg_indirect_ref (addr);
6048 def_builtin (int mask, const char *name, tree type, int code)
6050 if (mask & target_flags)
6052 if (rs6000_builtin_decls[code])
6055 rs6000_builtin_decls[code] =
6056 lang_hooks.builtin_function (name, type, code, BUILT_IN_MD,
6061 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6063 static const struct builtin_description bdesc_3arg[] =
6065 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6066 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6067 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6068 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6069 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6070 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6071 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6072 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6073 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6074 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6075 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6076 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6077 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6078 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6079 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6080 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6081 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6082 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6083 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6084 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6085 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6086 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6087 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6089 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6090 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6091 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6092 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6093 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6094 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6095 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6096 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6097 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6098 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6099 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6100 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6101 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6102 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6103 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6106 /* DST operations: void foo (void *, const int, const char). */
6108 static const struct builtin_description bdesc_dst[] =
6110 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6111 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6112 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6113 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6115 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6116 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6117 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6118 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6121 /* Simple binary operations: VECc = foo (VECa, VECb). */
6123 static struct builtin_description bdesc_2arg[] =
6125 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6126 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6127 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6128 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6129 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6130 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6131 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6132 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6133 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6134 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6135 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6136 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6137 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6138 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6139 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6140 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6141 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6142 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6143 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6144 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6145 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6146 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6147 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6148 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6149 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6150 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6151 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6152 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6153 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6154 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6155 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6156 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6157 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6158 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6159 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6160 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6161 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6162 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6163 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6164 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6165 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6166 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6167 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6168 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6169 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6170 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6171 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6172 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6173 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6174 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6175 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6176 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6177 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6178 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6179 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6180 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6181 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6182 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6183 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6184 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6185 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6186 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6187 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6188 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6189 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6190 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6191 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6192 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6193 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6194 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6195 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6196 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6197 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6198 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6199 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6200 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6201 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6202 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6203 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6204 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6205 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6206 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6207 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6208 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6209 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6210 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6211 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6212 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6213 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6214 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6215 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6216 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6217 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6218 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6219 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6220 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6221 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6222 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6223 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6224 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6225 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6226 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6227 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6228 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6229 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6230 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6231 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6232 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6233 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6234 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6235 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6237 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6238 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6239 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6240 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6241 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6242 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6243 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6244 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6245 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6246 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6247 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6248 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6249 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6250 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6251 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6252 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6253 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6254 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6255 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6256 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6257 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6258 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6259 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6260 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6261 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6262 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6263 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6264 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6265 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6266 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6267 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6268 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6269 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6270 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6271 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6272 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6273 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6274 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6275 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6276 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6277 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6278 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6279 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6280 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6281 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6282 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6283 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6284 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6285 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6286 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6287 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6288 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6289 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6290 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6291 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6292 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6293 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6294 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6295 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6296 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6297 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6298 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6299 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6300 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6301 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6302 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6303 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6304 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6305 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6306 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6307 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6308 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6309 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6310 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6311 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6312 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6313 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6314 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6315 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6316 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6317 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6318 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6319 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6320 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6321 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6322 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6323 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6324 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6325 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6326 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6327 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6328 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6329 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6330 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6331 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6332 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6333 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6334 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6335 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6336 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6337 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6338 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6339 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6340 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6341 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6342 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6343 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6344 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6345 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6346 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6347 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6348 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6349 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6350 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6351 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6352 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6353 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6354 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6355 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6356 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6357 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6358 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6359 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6360 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6361 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6362 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6363 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6365 /* Place holder, leave as first spe builtin. */
6366 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6367 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6368 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6369 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6370 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6371 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6372 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6373 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6374 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6375 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6376 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6377 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6378 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6379 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6380 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6381 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6382 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6383 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6384 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6385 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6386 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6387 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6388 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6389 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6390 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6391 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6392 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6393 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6394 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6395 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6396 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6397 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6398 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6399 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6400 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6401 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6402 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6403 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6404 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6405 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6406 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6407 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6408 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6409 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6410 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6411 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6412 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6413 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6414 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6415 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6416 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6417 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6418 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6419 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6420 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6421 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6422 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6423 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6424 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6425 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6426 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6427 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6428 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6429 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6430 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6431 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6432 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6433 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6434 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6435 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6436 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6437 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6438 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6439 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6440 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6441 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6442 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6443 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6444 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6445 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6446 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6447 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6448 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6449 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6450 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6451 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6452 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6453 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6454 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6455 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6456 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6457 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6458 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6459 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6460 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6461 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6462 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6463 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6464 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6465 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6466 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6467 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6468 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6469 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6470 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6471 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6472 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6473 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6474 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6476 /* SPE binary operations expecting a 5-bit unsigned literal. */
6477 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6479 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6480 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6481 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6482 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6483 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6484 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6485 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6486 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6487 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6488 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6489 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6490 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6491 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6492 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6493 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6494 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6495 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6496 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6497 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6498 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6499 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6500 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6501 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6502 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6503 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6504 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6506 /* Place-holder. Leave as last binary SPE builtin. */
6507 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6510 /* AltiVec predicates. */
6512 struct builtin_description_predicates
6514 const unsigned int mask;
6515 const enum insn_code icode;
6517 const char *const name;
6518 const enum rs6000_builtins code;
6521 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6523 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6524 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6525 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6526 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6527 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6528 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6529 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6530 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6531 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6532 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6533 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6534 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6535 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6537 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6538 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6539 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6542 /* SPE predicates. */
6543 static struct builtin_description bdesc_spe_predicates[] =
6545 /* Place-holder. Leave as first. */
6546 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6547 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6548 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6549 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6550 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6551 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6552 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6553 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6554 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6555 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6556 /* Place-holder. Leave as last. */
6557 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6560 /* SPE evsel predicates. */
6561 static struct builtin_description bdesc_spe_evsel[] =
6563 /* Place-holder. Leave as first. */
6564 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6565 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6566 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6567 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6568 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6569 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6570 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6571 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6572 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6573 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6574 /* Place-holder. Leave as last. */
6575 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6578 /* ABS* operations. */
6580 static const struct builtin_description bdesc_abs[] =
6582 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6583 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6584 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6585 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6586 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6587 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6588 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6591 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6594 static struct builtin_description bdesc_1arg[] =
6596 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6597 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6598 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6599 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6600 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6601 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6602 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6603 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6604 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6605 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6606 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6607 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6608 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6609 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6610 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6611 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6612 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6614 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6615 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6616 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6617 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6618 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6619 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6620 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6621 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6622 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6623 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6624 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
6625 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
6626 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
6627 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
6628 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
6629 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
6630 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
6631 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
6632 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
6634 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6635 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6636 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6637 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6638 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6639 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6640 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6641 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6642 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6643 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6644 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6645 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6646 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6647 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6648 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6649 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6650 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6651 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6652 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6653 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6654 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6655 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6656 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6657 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6658 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6659 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6660 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6661 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6662 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6663 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6665 /* Place-holder. Leave as last unary SPE builtin. */
6666 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
6670 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6673 tree arg0 = TREE_VALUE (arglist);
6674 rtx op0 = expand_normal (arg0);
6675 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6676 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6678 if (icode == CODE_FOR_nothing)
6679 /* Builtin not supported on this processor. */
6682 /* If we got invalid arguments bail out before generating bad rtl. */
6683 if (arg0 == error_mark_node)
6686 if (icode == CODE_FOR_altivec_vspltisb
6687 || icode == CODE_FOR_altivec_vspltish
6688 || icode == CODE_FOR_altivec_vspltisw
6689 || icode == CODE_FOR_spe_evsplatfi
6690 || icode == CODE_FOR_spe_evsplati)
6692 /* Only allow 5-bit *signed* literals. */
6693 if (GET_CODE (op0) != CONST_INT
6694 || INTVAL (op0) > 15
6695 || INTVAL (op0) < -16)
6697 error ("argument 1 must be a 5-bit signed literal");
6703 || GET_MODE (target) != tmode
6704 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6705 target = gen_reg_rtx (tmode);
6707 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6708 op0 = copy_to_mode_reg (mode0, op0);
6710 pat = GEN_FCN (icode) (target, op0);
6719 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6721 rtx pat, scratch1, scratch2;
6722 tree arg0 = TREE_VALUE (arglist);
6723 rtx op0 = expand_normal (arg0);
6724 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6725 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6727 /* If we have invalid arguments, bail out before generating bad rtl. */
6728 if (arg0 == error_mark_node)
6732 || GET_MODE (target) != tmode
6733 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6734 target = gen_reg_rtx (tmode);
6736 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6737 op0 = copy_to_mode_reg (mode0, op0);
6739 scratch1 = gen_reg_rtx (mode0);
6740 scratch2 = gen_reg_rtx (mode0);
6742 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6751 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6754 tree arg0 = TREE_VALUE (arglist);
6755 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6756 rtx op0 = expand_normal (arg0);
6757 rtx op1 = expand_normal (arg1);
6758 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6759 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6760 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6762 if (icode == CODE_FOR_nothing)
6763 /* Builtin not supported on this processor. */
6766 /* If we got invalid arguments bail out before generating bad rtl. */
6767 if (arg0 == error_mark_node || arg1 == error_mark_node)
6770 if (icode == CODE_FOR_altivec_vcfux
6771 || icode == CODE_FOR_altivec_vcfsx
6772 || icode == CODE_FOR_altivec_vctsxs
6773 || icode == CODE_FOR_altivec_vctuxs
6774 || icode == CODE_FOR_altivec_vspltb
6775 || icode == CODE_FOR_altivec_vsplth
6776 || icode == CODE_FOR_altivec_vspltw
6777 || icode == CODE_FOR_spe_evaddiw
6778 || icode == CODE_FOR_spe_evldd
6779 || icode == CODE_FOR_spe_evldh
6780 || icode == CODE_FOR_spe_evldw
6781 || icode == CODE_FOR_spe_evlhhesplat
6782 || icode == CODE_FOR_spe_evlhhossplat
6783 || icode == CODE_FOR_spe_evlhhousplat
6784 || icode == CODE_FOR_spe_evlwhe
6785 || icode == CODE_FOR_spe_evlwhos
6786 || icode == CODE_FOR_spe_evlwhou
6787 || icode == CODE_FOR_spe_evlwhsplat
6788 || icode == CODE_FOR_spe_evlwwsplat
6789 || icode == CODE_FOR_spe_evrlwi
6790 || icode == CODE_FOR_spe_evslwi
6791 || icode == CODE_FOR_spe_evsrwis
6792 || icode == CODE_FOR_spe_evsubifw
6793 || icode == CODE_FOR_spe_evsrwiu)
6795 /* Only allow 5-bit unsigned literals. */
6797 if (TREE_CODE (arg1) != INTEGER_CST
6798 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6800 error ("argument 2 must be a 5-bit unsigned literal");
6806 || GET_MODE (target) != tmode
6807 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6808 target = gen_reg_rtx (tmode);
6810 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6811 op0 = copy_to_mode_reg (mode0, op0);
6812 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6813 op1 = copy_to_mode_reg (mode1, op1);
6815 pat = GEN_FCN (icode) (target, op0, op1);
6824 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6825 tree arglist, rtx target)
6828 tree cr6_form = TREE_VALUE (arglist);
6829 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6830 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6831 rtx op0 = expand_normal (arg0);
6832 rtx op1 = expand_normal (arg1);
6833 enum machine_mode tmode = SImode;
6834 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6835 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6838 if (TREE_CODE (cr6_form) != INTEGER_CST)
6840 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6844 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6846 gcc_assert (mode0 == mode1);
6848 /* If we have invalid arguments, bail out before generating bad rtl. */
6849 if (arg0 == error_mark_node || arg1 == error_mark_node)
6853 || GET_MODE (target) != tmode
6854 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6855 target = gen_reg_rtx (tmode);
6857 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6858 op0 = copy_to_mode_reg (mode0, op0);
6859 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6860 op1 = copy_to_mode_reg (mode1, op1);
6862 scratch = gen_reg_rtx (mode0);
6864 pat = GEN_FCN (icode) (scratch, op0, op1,
6865 gen_rtx_SYMBOL_REF (Pmode, opcode));
6870 /* The vec_any* and vec_all* predicates use the same opcodes for two
6871 different operations, but the bits in CR6 will be different
6872 depending on what information we want. So we have to play tricks
6873 with CR6 to get the right bits out.
6875 If you think this is disgusting, look at the specs for the
6876 AltiVec predicates. */
6878 switch (cr6_form_int)
6881 emit_insn (gen_cr6_test_for_zero (target));
6884 emit_insn (gen_cr6_test_for_zero_reverse (target));
6887 emit_insn (gen_cr6_test_for_lt (target));
6890 emit_insn (gen_cr6_test_for_lt_reverse (target));
6893 error ("argument 1 of __builtin_altivec_predicate is out of range");
6901 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6904 tree arg0 = TREE_VALUE (arglist);
6905 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6906 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6907 enum machine_mode mode0 = Pmode;
6908 enum machine_mode mode1 = Pmode;
6909 rtx op0 = expand_normal (arg0);
6910 rtx op1 = expand_normal (arg1);
6912 if (icode == CODE_FOR_nothing)
6913 /* Builtin not supported on this processor. */
6916 /* If we got invalid arguments bail out before generating bad rtl. */
6917 if (arg0 == error_mark_node || arg1 == error_mark_node)
6921 || GET_MODE (target) != tmode
6922 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6923 target = gen_reg_rtx (tmode);
6925 op1 = copy_to_mode_reg (mode1, op1);
6927 if (op0 == const0_rtx)
6929 addr = gen_rtx_MEM (tmode, op1);
6933 op0 = copy_to_mode_reg (mode0, op0);
6934 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6937 pat = GEN_FCN (icode) (target, addr);
6947 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6949 tree arg0 = TREE_VALUE (arglist);
6950 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6951 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6952 rtx op0 = expand_normal (arg0);
6953 rtx op1 = expand_normal (arg1);
6954 rtx op2 = expand_normal (arg2);
6956 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6957 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6958 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6960 /* Invalid arguments. Bail before doing anything stoopid! */
6961 if (arg0 == error_mark_node
6962 || arg1 == error_mark_node
6963 || arg2 == error_mark_node)
6966 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6967 op0 = copy_to_mode_reg (mode2, op0);
6968 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6969 op1 = copy_to_mode_reg (mode0, op1);
6970 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6971 op2 = copy_to_mode_reg (mode1, op2);
6973 pat = GEN_FCN (icode) (op1, op2, op0);
6980 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6982 tree arg0 = TREE_VALUE (arglist);
6983 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6984 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6985 rtx op0 = expand_normal (arg0);
6986 rtx op1 = expand_normal (arg1);
6987 rtx op2 = expand_normal (arg2);
6989 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6990 enum machine_mode mode1 = Pmode;
6991 enum machine_mode mode2 = Pmode;
6993 /* Invalid arguments. Bail before doing anything stoopid! */
6994 if (arg0 == error_mark_node
6995 || arg1 == error_mark_node
6996 || arg2 == error_mark_node)
6999 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
7000 op0 = copy_to_mode_reg (tmode, op0);
7002 op2 = copy_to_mode_reg (mode2, op2);
7004 if (op1 == const0_rtx)
7006 addr = gen_rtx_MEM (tmode, op2);
7010 op1 = copy_to_mode_reg (mode1, op1);
7011 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
7014 pat = GEN_FCN (icode) (addr, op0);
7021 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
7024 tree arg0 = TREE_VALUE (arglist);
7025 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7026 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7027 rtx op0 = expand_normal (arg0);
7028 rtx op1 = expand_normal (arg1);
7029 rtx op2 = expand_normal (arg2);
7030 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7031 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7032 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7033 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
7035 if (icode == CODE_FOR_nothing)
7036 /* Builtin not supported on this processor. */
7039 /* If we got invalid arguments bail out before generating bad rtl. */
7040 if (arg0 == error_mark_node
7041 || arg1 == error_mark_node
7042 || arg2 == error_mark_node)
7045 if (icode == CODE_FOR_altivec_vsldoi_v4sf
7046 || icode == CODE_FOR_altivec_vsldoi_v4si
7047 || icode == CODE_FOR_altivec_vsldoi_v8hi
7048 || icode == CODE_FOR_altivec_vsldoi_v16qi)
7050 /* Only allow 4-bit unsigned literals. */
7052 if (TREE_CODE (arg2) != INTEGER_CST
7053 || TREE_INT_CST_LOW (arg2) & ~0xf)
7055 error ("argument 3 must be a 4-bit unsigned literal");
7061 || GET_MODE (target) != tmode
7062 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7063 target = gen_reg_rtx (tmode);
7065 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7066 op0 = copy_to_mode_reg (mode0, op0);
7067 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7068 op1 = copy_to_mode_reg (mode1, op1);
7069 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7070 op2 = copy_to_mode_reg (mode2, op2);
7072 pat = GEN_FCN (icode) (target, op0, op1, op2);
7080 /* Expand the lvx builtins. */
7082 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7084 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7085 tree arglist = TREE_OPERAND (exp, 1);
7086 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7088 enum machine_mode tmode, mode0;
7090 enum insn_code icode;
7094 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7095 icode = CODE_FOR_altivec_lvx_v16qi;
7097 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7098 icode = CODE_FOR_altivec_lvx_v8hi;
7100 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7101 icode = CODE_FOR_altivec_lvx_v4si;
7103 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7104 icode = CODE_FOR_altivec_lvx_v4sf;
7113 arg0 = TREE_VALUE (arglist);
7114 op0 = expand_normal (arg0);
7115 tmode = insn_data[icode].operand[0].mode;
7116 mode0 = insn_data[icode].operand[1].mode;
7119 || GET_MODE (target) != tmode
7120 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7121 target = gen_reg_rtx (tmode);
7123 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7124 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7126 pat = GEN_FCN (icode) (target, op0);
7133 /* Expand the stvx builtins. */
7135 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7138 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7139 tree arglist = TREE_OPERAND (exp, 1);
7140 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7142 enum machine_mode mode0, mode1;
7144 enum insn_code icode;
7148 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7149 icode = CODE_FOR_altivec_stvx_v16qi;
7151 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7152 icode = CODE_FOR_altivec_stvx_v8hi;
7154 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7155 icode = CODE_FOR_altivec_stvx_v4si;
7157 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7158 icode = CODE_FOR_altivec_stvx_v4sf;
7165 arg0 = TREE_VALUE (arglist);
7166 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7167 op0 = expand_normal (arg0);
7168 op1 = expand_normal (arg1);
7169 mode0 = insn_data[icode].operand[0].mode;
7170 mode1 = insn_data[icode].operand[1].mode;
7172 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7173 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7174 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7175 op1 = copy_to_mode_reg (mode1, op1);
7177 pat = GEN_FCN (icode) (op0, op1);
7185 /* Expand the dst builtins. */
7187 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7190 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7191 tree arglist = TREE_OPERAND (exp, 1);
7192 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7193 tree arg0, arg1, arg2;
7194 enum machine_mode mode0, mode1, mode2;
7195 rtx pat, op0, op1, op2;
7196 struct builtin_description *d;
7201 /* Handle DST variants. */
7202 d = (struct builtin_description *) bdesc_dst;
7203 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7204 if (d->code == fcode)
7206 arg0 = TREE_VALUE (arglist);
7207 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7208 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7209 op0 = expand_normal (arg0);
7210 op1 = expand_normal (arg1);
7211 op2 = expand_normal (arg2);
7212 mode0 = insn_data[d->icode].operand[0].mode;
7213 mode1 = insn_data[d->icode].operand[1].mode;
7214 mode2 = insn_data[d->icode].operand[2].mode;
7216 /* Invalid arguments, bail out before generating bad rtl. */
7217 if (arg0 == error_mark_node
7218 || arg1 == error_mark_node
7219 || arg2 == error_mark_node)
7224 if (TREE_CODE (arg2) != INTEGER_CST
7225 || TREE_INT_CST_LOW (arg2) & ~0x3)
7227 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7231 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7232 op0 = copy_to_mode_reg (Pmode, op0);
7233 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7234 op1 = copy_to_mode_reg (mode1, op1);
7236 pat = GEN_FCN (d->icode) (op0, op1, op2);
7246 /* Expand vec_init builtin. */
7248 altivec_expand_vec_init_builtin (tree type, tree arglist, rtx target)
7250 enum machine_mode tmode = TYPE_MODE (type);
7251 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7252 int i, n_elt = GET_MODE_NUNITS (tmode);
7253 rtvec v = rtvec_alloc (n_elt);
7255 gcc_assert (VECTOR_MODE_P (tmode));
7257 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
7259 rtx x = expand_normal (TREE_VALUE (arglist));
7260 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7263 gcc_assert (arglist == NULL);
7265 if (!target || !register_operand (target, tmode))
7266 target = gen_reg_rtx (tmode);
7268 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7272 /* Return the integer constant in ARG. Constrain it to be in the range
7273 of the subparts of VEC_TYPE; issue an error if not. */
7276 get_element_number (tree vec_type, tree arg)
7278 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7280 if (!host_integerp (arg, 1)
7281 || (elt = tree_low_cst (arg, 1), elt > max))
7283 error ("selector must be an integer constant in the range 0..%wi", max);
7290 /* Expand vec_set builtin. */
7292 altivec_expand_vec_set_builtin (tree arglist)
7294 enum machine_mode tmode, mode1;
7295 tree arg0, arg1, arg2;
7299 arg0 = TREE_VALUE (arglist);
7300 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7301 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7303 tmode = TYPE_MODE (TREE_TYPE (arg0));
7304 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7305 gcc_assert (VECTOR_MODE_P (tmode));
7307 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7308 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7309 elt = get_element_number (TREE_TYPE (arg0), arg2);
7311 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7312 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7314 op0 = force_reg (tmode, op0);
7315 op1 = force_reg (mode1, op1);
7317 rs6000_expand_vector_set (op0, op1, elt);
7322 /* Expand vec_ext builtin. */
7324 altivec_expand_vec_ext_builtin (tree arglist, rtx target)
7326 enum machine_mode tmode, mode0;
7331 arg0 = TREE_VALUE (arglist);
7332 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7334 op0 = expand_normal (arg0);
7335 elt = get_element_number (TREE_TYPE (arg0), arg1);
7337 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7338 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7339 gcc_assert (VECTOR_MODE_P (mode0));
7341 op0 = force_reg (mode0, op0);
7343 if (optimize || !target || !register_operand (target, tmode))
7344 target = gen_reg_rtx (tmode);
7346 rs6000_expand_vector_extract (target, op0, elt);
7351 /* Expand the builtin in EXP and store the result in TARGET. Store
7352 true in *EXPANDEDP if we found a builtin to expand. */
7354 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7356 struct builtin_description *d;
7357 struct builtin_description_predicates *dp;
7359 enum insn_code icode;
7360 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7361 tree arglist = TREE_OPERAND (exp, 1);
7364 enum machine_mode tmode, mode0;
7365 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7367 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7368 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7371 error ("unresolved overload for Altivec builtin %qF", fndecl);
7375 target = altivec_expand_ld_builtin (exp, target, expandedp);
7379 target = altivec_expand_st_builtin (exp, target, expandedp);
7383 target = altivec_expand_dst_builtin (exp, target, expandedp);
7391 case ALTIVEC_BUILTIN_STVX:
7392 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
7393 case ALTIVEC_BUILTIN_STVEBX:
7394 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
7395 case ALTIVEC_BUILTIN_STVEHX:
7396 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
7397 case ALTIVEC_BUILTIN_STVEWX:
7398 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
7399 case ALTIVEC_BUILTIN_STVXL:
7400 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
7402 case ALTIVEC_BUILTIN_MFVSCR:
7403 icode = CODE_FOR_altivec_mfvscr;
7404 tmode = insn_data[icode].operand[0].mode;
7407 || GET_MODE (target) != tmode
7408 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7409 target = gen_reg_rtx (tmode);
7411 pat = GEN_FCN (icode) (target);
7417 case ALTIVEC_BUILTIN_MTVSCR:
7418 icode = CODE_FOR_altivec_mtvscr;
7419 arg0 = TREE_VALUE (arglist);
7420 op0 = expand_normal (arg0);
7421 mode0 = insn_data[icode].operand[0].mode;
7423 /* If we got invalid arguments bail out before generating bad rtl. */
7424 if (arg0 == error_mark_node)
7427 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7428 op0 = copy_to_mode_reg (mode0, op0);
7430 pat = GEN_FCN (icode) (op0);
7435 case ALTIVEC_BUILTIN_DSSALL:
7436 emit_insn (gen_altivec_dssall ());
7439 case ALTIVEC_BUILTIN_DSS:
7440 icode = CODE_FOR_altivec_dss;
7441 arg0 = TREE_VALUE (arglist);
7443 op0 = expand_normal (arg0);
7444 mode0 = insn_data[icode].operand[0].mode;
7446 /* If we got invalid arguments bail out before generating bad rtl. */
7447 if (arg0 == error_mark_node)
7450 if (TREE_CODE (arg0) != INTEGER_CST
7451 || TREE_INT_CST_LOW (arg0) & ~0x3)
7453 error ("argument to dss must be a 2-bit unsigned literal");
7457 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7458 op0 = copy_to_mode_reg (mode0, op0);
7460 emit_insn (gen_altivec_dss (op0));
7463 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7464 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7465 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7466 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7467 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
7469 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7470 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7471 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7472 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7473 return altivec_expand_vec_set_builtin (arglist);
7475 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7476 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7477 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7478 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7479 return altivec_expand_vec_ext_builtin (arglist, target);
7486 /* Expand abs* operations. */
7487 d = (struct builtin_description *) bdesc_abs;
7488 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7489 if (d->code == fcode)
7490 return altivec_expand_abs_builtin (d->icode, arglist, target);
7492 /* Expand the AltiVec predicates. */
7493 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7494 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7495 if (dp->code == fcode)
7496 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7499 /* LV* are funky. We initialized them differently. */
7502 case ALTIVEC_BUILTIN_LVSL:
7503 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7505 case ALTIVEC_BUILTIN_LVSR:
7506 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7508 case ALTIVEC_BUILTIN_LVEBX:
7509 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7511 case ALTIVEC_BUILTIN_LVEHX:
7512 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7514 case ALTIVEC_BUILTIN_LVEWX:
7515 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7517 case ALTIVEC_BUILTIN_LVXL:
7518 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7520 case ALTIVEC_BUILTIN_LVX:
7521 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7532 /* Binops that need to be initialized manually, but can be expanded
7533 automagically by rs6000_expand_binop_builtin. */
7534 static struct builtin_description bdesc_2arg_spe[] =
7536 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7537 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7538 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7539 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7540 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7541 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7542 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7543 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7544 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7545 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7546 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7547 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7548 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7549 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7550 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7551 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7552 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7553 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7554 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7555 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7556 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7557 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7560 /* Expand the builtin in EXP and store the result in TARGET. Store
7561 true in *EXPANDEDP if we found a builtin to expand.
7563 This expands the SPE builtins that are not simple unary and binary
7566 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7568 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7569 tree arglist = TREE_OPERAND (exp, 1);
7571 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7572 enum insn_code icode;
7573 enum machine_mode tmode, mode0;
7575 struct builtin_description *d;
7580 /* Syntax check for a 5-bit unsigned immediate. */
7583 case SPE_BUILTIN_EVSTDD:
7584 case SPE_BUILTIN_EVSTDH:
7585 case SPE_BUILTIN_EVSTDW:
7586 case SPE_BUILTIN_EVSTWHE:
7587 case SPE_BUILTIN_EVSTWHO:
7588 case SPE_BUILTIN_EVSTWWE:
7589 case SPE_BUILTIN_EVSTWWO:
7590 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7591 if (TREE_CODE (arg1) != INTEGER_CST
7592 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7594 error ("argument 2 must be a 5-bit unsigned literal");
7602 /* The evsplat*i instructions are not quite generic. */
7605 case SPE_BUILTIN_EVSPLATFI:
7606 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7608 case SPE_BUILTIN_EVSPLATI:
7609 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7615 d = (struct builtin_description *) bdesc_2arg_spe;
7616 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7617 if (d->code == fcode)
7618 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7620 d = (struct builtin_description *) bdesc_spe_predicates;
7621 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7622 if (d->code == fcode)
7623 return spe_expand_predicate_builtin (d->icode, arglist, target);
7625 d = (struct builtin_description *) bdesc_spe_evsel;
7626 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7627 if (d->code == fcode)
7628 return spe_expand_evsel_builtin (d->icode, arglist, target);
7632 case SPE_BUILTIN_EVSTDDX:
7633 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7634 case SPE_BUILTIN_EVSTDHX:
7635 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7636 case SPE_BUILTIN_EVSTDWX:
7637 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7638 case SPE_BUILTIN_EVSTWHEX:
7639 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7640 case SPE_BUILTIN_EVSTWHOX:
7641 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7642 case SPE_BUILTIN_EVSTWWEX:
7643 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7644 case SPE_BUILTIN_EVSTWWOX:
7645 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7646 case SPE_BUILTIN_EVSTDD:
7647 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7648 case SPE_BUILTIN_EVSTDH:
7649 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7650 case SPE_BUILTIN_EVSTDW:
7651 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7652 case SPE_BUILTIN_EVSTWHE:
7653 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7654 case SPE_BUILTIN_EVSTWHO:
7655 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7656 case SPE_BUILTIN_EVSTWWE:
7657 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7658 case SPE_BUILTIN_EVSTWWO:
7659 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7660 case SPE_BUILTIN_MFSPEFSCR:
7661 icode = CODE_FOR_spe_mfspefscr;
7662 tmode = insn_data[icode].operand[0].mode;
7665 || GET_MODE (target) != tmode
7666 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7667 target = gen_reg_rtx (tmode);
7669 pat = GEN_FCN (icode) (target);
7674 case SPE_BUILTIN_MTSPEFSCR:
7675 icode = CODE_FOR_spe_mtspefscr;
7676 arg0 = TREE_VALUE (arglist);
7677 op0 = expand_normal (arg0);
7678 mode0 = insn_data[icode].operand[0].mode;
7680 if (arg0 == error_mark_node)
7683 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7684 op0 = copy_to_mode_reg (mode0, op0);
7686 pat = GEN_FCN (icode) (op0);
7699 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7701 rtx pat, scratch, tmp;
7702 tree form = TREE_VALUE (arglist);
7703 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7704 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7705 rtx op0 = expand_normal (arg0);
7706 rtx op1 = expand_normal (arg1);
7707 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7708 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7712 if (TREE_CODE (form) != INTEGER_CST)
7714 error ("argument 1 of __builtin_spe_predicate must be a constant");
7718 form_int = TREE_INT_CST_LOW (form);
7720 gcc_assert (mode0 == mode1);
7722 if (arg0 == error_mark_node || arg1 == error_mark_node)
7726 || GET_MODE (target) != SImode
7727 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7728 target = gen_reg_rtx (SImode);
7730 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7731 op0 = copy_to_mode_reg (mode0, op0);
7732 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7733 op1 = copy_to_mode_reg (mode1, op1);
7735 scratch = gen_reg_rtx (CCmode);
7737 pat = GEN_FCN (icode) (scratch, op0, op1);
7742 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7743 _lower_. We use one compare, but look in different bits of the
7744 CR for each variant.
7746 There are 2 elements in each SPE simd type (upper/lower). The CR
7747 bits are set as follows:
7749 BIT0 | BIT 1 | BIT 2 | BIT 3
7750 U | L | (U | L) | (U & L)
7752 So, for an "all" relationship, BIT 3 would be set.
7753 For an "any" relationship, BIT 2 would be set. Etc.
7755 Following traditional nomenclature, these bits map to:
7757 BIT0 | BIT 1 | BIT 2 | BIT 3
7760 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7765 /* All variant. OV bit. */
7767 /* We need to get to the OV bit, which is the ORDERED bit. We
7768 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7769 that's ugly and will make validate_condition_mode die.
7770 So let's just use another pattern. */
7771 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7773 /* Any variant. EQ bit. */
7777 /* Upper variant. LT bit. */
7781 /* Lower variant. GT bit. */
7786 error ("argument 1 of __builtin_spe_predicate is out of range");
7790 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7791 emit_move_insn (target, tmp);
7796 /* The evsel builtins look like this:
7798 e = __builtin_spe_evsel_OP (a, b, c, d);
7802 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7803 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7807 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7810 tree arg0 = TREE_VALUE (arglist);
7811 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7812 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7813 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7814 rtx op0 = expand_normal (arg0);
7815 rtx op1 = expand_normal (arg1);
7816 rtx op2 = expand_normal (arg2);
7817 rtx op3 = expand_normal (arg3);
7818 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7819 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7821 gcc_assert (mode0 == mode1);
7823 if (arg0 == error_mark_node || arg1 == error_mark_node
7824 || arg2 == error_mark_node || arg3 == error_mark_node)
7828 || GET_MODE (target) != mode0
7829 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7830 target = gen_reg_rtx (mode0);
7832 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7833 op0 = copy_to_mode_reg (mode0, op0);
7834 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7835 op1 = copy_to_mode_reg (mode0, op1);
7836 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7837 op2 = copy_to_mode_reg (mode0, op2);
7838 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7839 op3 = copy_to_mode_reg (mode0, op3);
7841 /* Generate the compare. */
7842 scratch = gen_reg_rtx (CCmode);
7843 pat = GEN_FCN (icode) (scratch, op0, op1);
7848 if (mode0 == V2SImode)
7849 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7851 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7856 /* Expand an expression EXP that calls a built-in function,
7857 with result going to TARGET if that's convenient
7858 (and in mode MODE if that's convenient).
7859 SUBTARGET may be used as the target for computing one of EXP's operands.
7860 IGNORE is nonzero if the value is to be ignored. */
7863 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7864 enum machine_mode mode ATTRIBUTE_UNUSED,
7865 int ignore ATTRIBUTE_UNUSED)
7867 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7868 tree arglist = TREE_OPERAND (exp, 1);
7869 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7870 struct builtin_description *d;
7875 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7876 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7878 int icode = (int) CODE_FOR_altivec_lvsr;
7879 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7880 enum machine_mode mode = insn_data[icode].operand[1].mode;
7884 gcc_assert (TARGET_ALTIVEC);
7886 arg = TREE_VALUE (arglist);
7887 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
7888 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7889 addr = memory_address (mode, op);
7890 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7894 /* For the load case need to negate the address. */
7895 op = gen_reg_rtx (GET_MODE (addr));
7896 emit_insn (gen_rtx_SET (VOIDmode, op,
7897 gen_rtx_NEG (GET_MODE (addr), addr)));
7899 op = gen_rtx_MEM (mode, op);
7902 || GET_MODE (target) != tmode
7903 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7904 target = gen_reg_rtx (tmode);
7906 /*pat = gen_altivec_lvsr (target, op);*/
7907 pat = GEN_FCN (icode) (target, op);
7917 ret = altivec_expand_builtin (exp, target, &success);
7924 ret = spe_expand_builtin (exp, target, &success);
7930 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
7932 /* Handle simple unary operations. */
7933 d = (struct builtin_description *) bdesc_1arg;
7934 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7935 if (d->code == fcode)
7936 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7938 /* Handle simple binary operations. */
7939 d = (struct builtin_description *) bdesc_2arg;
7940 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7941 if (d->code == fcode)
7942 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7944 /* Handle simple ternary operations. */
7945 d = (struct builtin_description *) bdesc_3arg;
7946 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7947 if (d->code == fcode)
7948 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7954 build_opaque_vector_type (tree node, int nunits)
7956 node = copy_node (node);
7957 TYPE_MAIN_VARIANT (node) = node;
7958 return build_vector_type (node, nunits);
7962 rs6000_init_builtins (void)
7964 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7965 V2SF_type_node = build_vector_type (float_type_node, 2);
7966 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7967 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7968 V4SF_type_node = build_vector_type (float_type_node, 4);
7969 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7970 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7972 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7973 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7974 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7976 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7977 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7978 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7979 opaque_V4SI_type_node = copy_node (V4SI_type_node);
7981 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7982 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7983 'vector unsigned short'. */
7985 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7986 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7987 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7988 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7990 long_integer_type_internal_node = long_integer_type_node;
7991 long_unsigned_type_internal_node = long_unsigned_type_node;
7992 intQI_type_internal_node = intQI_type_node;
7993 uintQI_type_internal_node = unsigned_intQI_type_node;
7994 intHI_type_internal_node = intHI_type_node;
7995 uintHI_type_internal_node = unsigned_intHI_type_node;
7996 intSI_type_internal_node = intSI_type_node;
7997 uintSI_type_internal_node = unsigned_intSI_type_node;
7998 float_type_internal_node = float_type_node;
7999 void_type_internal_node = void_type_node;
8001 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8002 get_identifier ("__bool char"),
8003 bool_char_type_node));
8004 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8005 get_identifier ("__bool short"),
8006 bool_short_type_node));
8007 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8008 get_identifier ("__bool int"),
8009 bool_int_type_node));
8010 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8011 get_identifier ("__pixel"),
8014 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
8015 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
8016 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
8017 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8019 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8020 get_identifier ("__vector unsigned char"),
8021 unsigned_V16QI_type_node));
8022 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8023 get_identifier ("__vector signed char"),
8025 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8026 get_identifier ("__vector __bool char"),
8027 bool_V16QI_type_node));
8029 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8030 get_identifier ("__vector unsigned short"),
8031 unsigned_V8HI_type_node));
8032 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8033 get_identifier ("__vector signed short"),
8035 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8036 get_identifier ("__vector __bool short"),
8037 bool_V8HI_type_node));
8039 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8040 get_identifier ("__vector unsigned int"),
8041 unsigned_V4SI_type_node));
8042 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8043 get_identifier ("__vector signed int"),
8045 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8046 get_identifier ("__vector __bool int"),
8047 bool_V4SI_type_node));
8049 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8050 get_identifier ("__vector float"),
8052 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8053 get_identifier ("__vector __pixel"),
8054 pixel_V8HI_type_node));
8057 spe_init_builtins ();
8059 altivec_init_builtins ();
8060 if (TARGET_ALTIVEC || TARGET_SPE)
8061 rs6000_common_init_builtins ();
8064 /* AIX libm provides clog as __clog. */
8065 if (built_in_decls [BUILT_IN_CLOG])
8066 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
8070 /* Search through a set of builtins and enable the mask bits.
8071 DESC is an array of builtins.
8072 SIZE is the total number of builtins.
8073 START is the builtin enum at which to start.
8074 END is the builtin enum at which to end. */
8076 enable_mask_for_builtins (struct builtin_description *desc, int size,
8077 enum rs6000_builtins start,
8078 enum rs6000_builtins end)
8082 for (i = 0; i < size; ++i)
8083 if (desc[i].code == start)
8089 for (; i < size; ++i)
8091 /* Flip all the bits on. */
8092 desc[i].mask = target_flags;
8093 if (desc[i].code == end)
8099 spe_init_builtins (void)
8101 tree endlink = void_list_node;
8102 tree puint_type_node = build_pointer_type (unsigned_type_node);
8103 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
8104 struct builtin_description *d;
8107 tree v2si_ftype_4_v2si
8108 = build_function_type
8109 (opaque_V2SI_type_node,
8110 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8111 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8112 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8113 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8116 tree v2sf_ftype_4_v2sf
8117 = build_function_type
8118 (opaque_V2SF_type_node,
8119 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8120 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8121 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8122 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8125 tree int_ftype_int_v2si_v2si
8126 = build_function_type
8128 tree_cons (NULL_TREE, integer_type_node,
8129 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8130 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8133 tree int_ftype_int_v2sf_v2sf
8134 = build_function_type
8136 tree_cons (NULL_TREE, integer_type_node,
8137 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8138 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8141 tree void_ftype_v2si_puint_int
8142 = build_function_type (void_type_node,
8143 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8144 tree_cons (NULL_TREE, puint_type_node,
8145 tree_cons (NULL_TREE,
8149 tree void_ftype_v2si_puint_char
8150 = build_function_type (void_type_node,
8151 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8152 tree_cons (NULL_TREE, puint_type_node,
8153 tree_cons (NULL_TREE,
8157 tree void_ftype_v2si_pv2si_int
8158 = build_function_type (void_type_node,
8159 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8160 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8161 tree_cons (NULL_TREE,
8165 tree void_ftype_v2si_pv2si_char
8166 = build_function_type (void_type_node,
8167 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8168 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8169 tree_cons (NULL_TREE,
8174 = build_function_type (void_type_node,
8175 tree_cons (NULL_TREE, integer_type_node, endlink));
8178 = build_function_type (integer_type_node, endlink);
8180 tree v2si_ftype_pv2si_int
8181 = build_function_type (opaque_V2SI_type_node,
8182 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8183 tree_cons (NULL_TREE, integer_type_node,
8186 tree v2si_ftype_puint_int
8187 = build_function_type (opaque_V2SI_type_node,
8188 tree_cons (NULL_TREE, puint_type_node,
8189 tree_cons (NULL_TREE, integer_type_node,
8192 tree v2si_ftype_pushort_int
8193 = build_function_type (opaque_V2SI_type_node,
8194 tree_cons (NULL_TREE, pushort_type_node,
8195 tree_cons (NULL_TREE, integer_type_node,
8198 tree v2si_ftype_signed_char
8199 = build_function_type (opaque_V2SI_type_node,
8200 tree_cons (NULL_TREE, signed_char_type_node,
8203 /* The initialization of the simple binary and unary builtins is
8204 done in rs6000_common_init_builtins, but we have to enable the
8205 mask bits here manually because we have run out of `target_flags'
8206 bits. We really need to redesign this mask business. */
8208 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8209 ARRAY_SIZE (bdesc_2arg),
8212 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8213 ARRAY_SIZE (bdesc_1arg),
8215 SPE_BUILTIN_EVSUBFUSIAAW);
8216 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8217 ARRAY_SIZE (bdesc_spe_predicates),
8218 SPE_BUILTIN_EVCMPEQ,
8219 SPE_BUILTIN_EVFSTSTLT);
8220 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8221 ARRAY_SIZE (bdesc_spe_evsel),
8222 SPE_BUILTIN_EVSEL_CMPGTS,
8223 SPE_BUILTIN_EVSEL_FSTSTEQ);
8225 (*lang_hooks.decls.pushdecl)
8226 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8227 opaque_V2SI_type_node));
8229 /* Initialize irregular SPE builtins. */
8231 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8232 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8233 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8234 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8235 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8236 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8237 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8238 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8239 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8240 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8241 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8242 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8243 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8244 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8245 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8246 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8247 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8248 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8251 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8252 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8253 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8254 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8255 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8256 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8257 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8258 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8259 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8260 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8261 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8262 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8263 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8264 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8265 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8266 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8267 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8268 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8269 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8270 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8271 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8272 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8275 d = (struct builtin_description *) bdesc_spe_predicates;
8276 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8280 switch (insn_data[d->icode].operand[1].mode)
8283 type = int_ftype_int_v2si_v2si;
8286 type = int_ftype_int_v2sf_v2sf;
8292 def_builtin (d->mask, d->name, type, d->code);
8295 /* Evsel predicates. */
8296 d = (struct builtin_description *) bdesc_spe_evsel;
8297 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8301 switch (insn_data[d->icode].operand[1].mode)
8304 type = v2si_ftype_4_v2si;
8307 type = v2sf_ftype_4_v2sf;
8313 def_builtin (d->mask, d->name, type, d->code);
8318 altivec_init_builtins (void)
8320 struct builtin_description *d;
8321 struct builtin_description_predicates *dp;
8325 tree pfloat_type_node = build_pointer_type (float_type_node);
8326 tree pint_type_node = build_pointer_type (integer_type_node);
8327 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8328 tree pchar_type_node = build_pointer_type (char_type_node);
8330 tree pvoid_type_node = build_pointer_type (void_type_node);
8332 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8333 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8334 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8335 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8337 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8339 tree int_ftype_opaque
8340 = build_function_type_list (integer_type_node,
8341 opaque_V4SI_type_node, NULL_TREE);
8343 tree opaque_ftype_opaque_int
8344 = build_function_type_list (opaque_V4SI_type_node,
8345 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8346 tree opaque_ftype_opaque_opaque_int
8347 = build_function_type_list (opaque_V4SI_type_node,
8348 opaque_V4SI_type_node, opaque_V4SI_type_node,
8349 integer_type_node, NULL_TREE);
8350 tree int_ftype_int_opaque_opaque
8351 = build_function_type_list (integer_type_node,
8352 integer_type_node, opaque_V4SI_type_node,
8353 opaque_V4SI_type_node, NULL_TREE);
8354 tree int_ftype_int_v4si_v4si
8355 = build_function_type_list (integer_type_node,
8356 integer_type_node, V4SI_type_node,
8357 V4SI_type_node, NULL_TREE);
8358 tree v4sf_ftype_pcfloat
8359 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8360 tree void_ftype_pfloat_v4sf
8361 = build_function_type_list (void_type_node,
8362 pfloat_type_node, V4SF_type_node, NULL_TREE);
8363 tree v4si_ftype_pcint
8364 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8365 tree void_ftype_pint_v4si
8366 = build_function_type_list (void_type_node,
8367 pint_type_node, V4SI_type_node, NULL_TREE);
8368 tree v8hi_ftype_pcshort
8369 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8370 tree void_ftype_pshort_v8hi
8371 = build_function_type_list (void_type_node,
8372 pshort_type_node, V8HI_type_node, NULL_TREE);
8373 tree v16qi_ftype_pcchar
8374 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8375 tree void_ftype_pchar_v16qi
8376 = build_function_type_list (void_type_node,
8377 pchar_type_node, V16QI_type_node, NULL_TREE);
8378 tree void_ftype_v4si
8379 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8380 tree v8hi_ftype_void
8381 = build_function_type (V8HI_type_node, void_list_node);
8382 tree void_ftype_void
8383 = build_function_type (void_type_node, void_list_node);
8385 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8387 tree opaque_ftype_long_pcvoid
8388 = build_function_type_list (opaque_V4SI_type_node,
8389 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8390 tree v16qi_ftype_long_pcvoid
8391 = build_function_type_list (V16QI_type_node,
8392 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8393 tree v8hi_ftype_long_pcvoid
8394 = build_function_type_list (V8HI_type_node,
8395 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8396 tree v4si_ftype_long_pcvoid
8397 = build_function_type_list (V4SI_type_node,
8398 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8400 tree void_ftype_opaque_long_pvoid
8401 = build_function_type_list (void_type_node,
8402 opaque_V4SI_type_node, long_integer_type_node,
8403 pvoid_type_node, NULL_TREE);
8404 tree void_ftype_v4si_long_pvoid
8405 = build_function_type_list (void_type_node,
8406 V4SI_type_node, long_integer_type_node,
8407 pvoid_type_node, NULL_TREE);
8408 tree void_ftype_v16qi_long_pvoid
8409 = build_function_type_list (void_type_node,
8410 V16QI_type_node, long_integer_type_node,
8411 pvoid_type_node, NULL_TREE);
8412 tree void_ftype_v8hi_long_pvoid
8413 = build_function_type_list (void_type_node,
8414 V8HI_type_node, long_integer_type_node,
8415 pvoid_type_node, NULL_TREE);
8416 tree int_ftype_int_v8hi_v8hi
8417 = build_function_type_list (integer_type_node,
8418 integer_type_node, V8HI_type_node,
8419 V8HI_type_node, NULL_TREE);
8420 tree int_ftype_int_v16qi_v16qi
8421 = build_function_type_list (integer_type_node,
8422 integer_type_node, V16QI_type_node,
8423 V16QI_type_node, NULL_TREE);
8424 tree int_ftype_int_v4sf_v4sf
8425 = build_function_type_list (integer_type_node,
8426 integer_type_node, V4SF_type_node,
8427 V4SF_type_node, NULL_TREE);
8428 tree v4si_ftype_v4si
8429 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8430 tree v8hi_ftype_v8hi
8431 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8432 tree v16qi_ftype_v16qi
8433 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8434 tree v4sf_ftype_v4sf
8435 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8436 tree void_ftype_pcvoid_int_int
8437 = build_function_type_list (void_type_node,
8438 pcvoid_type_node, integer_type_node,
8439 integer_type_node, NULL_TREE);
8441 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8442 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8443 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8444 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8445 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8446 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8447 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8448 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8449 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8450 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8451 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8452 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8453 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8454 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8455 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8456 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8457 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8458 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8459 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8460 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8461 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8462 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8463 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8464 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8465 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8466 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8467 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8468 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8469 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8470 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8471 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8472 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8473 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8474 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8475 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8476 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8477 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8478 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8479 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8480 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
8481 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
8482 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
8483 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
8484 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
8485 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
8486 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
8488 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
8490 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
8491 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
8492 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
8493 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
8494 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
8495 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
8496 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
8497 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
8498 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
8499 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8501 /* Add the DST variants. */
8502 d = (struct builtin_description *) bdesc_dst;
8503 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8504 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8506 /* Initialize the predicates. */
8507 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8508 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8510 enum machine_mode mode1;
8512 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8513 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8518 mode1 = insn_data[dp->icode].operand[1].mode;
8523 type = int_ftype_int_opaque_opaque;
8526 type = int_ftype_int_v4si_v4si;
8529 type = int_ftype_int_v8hi_v8hi;
8532 type = int_ftype_int_v16qi_v16qi;
8535 type = int_ftype_int_v4sf_v4sf;
8541 def_builtin (dp->mask, dp->name, type, dp->code);
8544 /* Initialize the abs* operators. */
8545 d = (struct builtin_description *) bdesc_abs;
8546 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8548 enum machine_mode mode0;
8551 mode0 = insn_data[d->icode].operand[0].mode;
8556 type = v4si_ftype_v4si;
8559 type = v8hi_ftype_v8hi;
8562 type = v16qi_ftype_v16qi;
8565 type = v4sf_ftype_v4sf;
8571 def_builtin (d->mask, d->name, type, d->code);
8578 /* Initialize target builtin that implements
8579 targetm.vectorize.builtin_mask_for_load. */
8581 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8582 v16qi_ftype_long_pcvoid,
8583 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8585 tree_cons (get_identifier ("const"),
8586 NULL_TREE, NULL_TREE));
8587 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8588 altivec_builtin_mask_for_load = decl;
8591 /* Access to the vec_init patterns. */
8592 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
8593 integer_type_node, integer_type_node,
8594 integer_type_node, NULL_TREE);
8595 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
8596 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
8598 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
8599 short_integer_type_node,
8600 short_integer_type_node,
8601 short_integer_type_node,
8602 short_integer_type_node,
8603 short_integer_type_node,
8604 short_integer_type_node,
8605 short_integer_type_node, NULL_TREE);
8606 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
8607 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
8609 ftype = build_function_type_list (V16QI_type_node, char_type_node,
8610 char_type_node, char_type_node,
8611 char_type_node, char_type_node,
8612 char_type_node, char_type_node,
8613 char_type_node, char_type_node,
8614 char_type_node, char_type_node,
8615 char_type_node, char_type_node,
8616 char_type_node, char_type_node,
8617 char_type_node, NULL_TREE);
8618 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
8619 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
8621 ftype = build_function_type_list (V4SF_type_node, float_type_node,
8622 float_type_node, float_type_node,
8623 float_type_node, NULL_TREE);
8624 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
8625 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
8627 /* Access to the vec_set patterns. */
8628 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
8630 integer_type_node, NULL_TREE);
8631 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
8632 ALTIVEC_BUILTIN_VEC_SET_V4SI);
8634 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
8636 integer_type_node, NULL_TREE);
8637 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
8638 ALTIVEC_BUILTIN_VEC_SET_V8HI);
8640 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
8642 integer_type_node, NULL_TREE);
8643 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
8644 ALTIVEC_BUILTIN_VEC_SET_V16QI);
8646 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
8648 integer_type_node, NULL_TREE);
8649 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
8650 ALTIVEC_BUILTIN_VEC_SET_V4SF);
8652 /* Access to the vec_extract patterns. */
8653 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
8654 integer_type_node, NULL_TREE);
8655 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
8656 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
8658 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
8659 integer_type_node, NULL_TREE);
8660 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
8661 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
8663 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
8664 integer_type_node, NULL_TREE);
8665 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
8666 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
8668 ftype = build_function_type_list (float_type_node, V4SF_type_node,
8669 integer_type_node, NULL_TREE);
8670 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
8671 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
8675 rs6000_common_init_builtins (void)
8677 struct builtin_description *d;
8680 tree v4sf_ftype_v4sf_v4sf_v16qi
8681 = build_function_type_list (V4SF_type_node,
8682 V4SF_type_node, V4SF_type_node,
8683 V16QI_type_node, NULL_TREE);
8684 tree v4si_ftype_v4si_v4si_v16qi
8685 = build_function_type_list (V4SI_type_node,
8686 V4SI_type_node, V4SI_type_node,
8687 V16QI_type_node, NULL_TREE);
8688 tree v8hi_ftype_v8hi_v8hi_v16qi
8689 = build_function_type_list (V8HI_type_node,
8690 V8HI_type_node, V8HI_type_node,
8691 V16QI_type_node, NULL_TREE);
8692 tree v16qi_ftype_v16qi_v16qi_v16qi
8693 = build_function_type_list (V16QI_type_node,
8694 V16QI_type_node, V16QI_type_node,
8695 V16QI_type_node, NULL_TREE);
8697 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8699 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8700 tree v16qi_ftype_int
8701 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8702 tree v8hi_ftype_v16qi
8703 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8704 tree v4sf_ftype_v4sf
8705 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8707 tree v2si_ftype_v2si_v2si
8708 = build_function_type_list (opaque_V2SI_type_node,
8709 opaque_V2SI_type_node,
8710 opaque_V2SI_type_node, NULL_TREE);
8712 tree v2sf_ftype_v2sf_v2sf
8713 = build_function_type_list (opaque_V2SF_type_node,
8714 opaque_V2SF_type_node,
8715 opaque_V2SF_type_node, NULL_TREE);
8717 tree v2si_ftype_int_int
8718 = build_function_type_list (opaque_V2SI_type_node,
8719 integer_type_node, integer_type_node,
8722 tree opaque_ftype_opaque
8723 = build_function_type_list (opaque_V4SI_type_node,
8724 opaque_V4SI_type_node, NULL_TREE);
8726 tree v2si_ftype_v2si
8727 = build_function_type_list (opaque_V2SI_type_node,
8728 opaque_V2SI_type_node, NULL_TREE);
8730 tree v2sf_ftype_v2sf
8731 = build_function_type_list (opaque_V2SF_type_node,
8732 opaque_V2SF_type_node, NULL_TREE);
8734 tree v2sf_ftype_v2si
8735 = build_function_type_list (opaque_V2SF_type_node,
8736 opaque_V2SI_type_node, NULL_TREE);
8738 tree v2si_ftype_v2sf
8739 = build_function_type_list (opaque_V2SI_type_node,
8740 opaque_V2SF_type_node, NULL_TREE);
8742 tree v2si_ftype_v2si_char
8743 = build_function_type_list (opaque_V2SI_type_node,
8744 opaque_V2SI_type_node,
8745 char_type_node, NULL_TREE);
8747 tree v2si_ftype_int_char
8748 = build_function_type_list (opaque_V2SI_type_node,
8749 integer_type_node, char_type_node, NULL_TREE);
8751 tree v2si_ftype_char
8752 = build_function_type_list (opaque_V2SI_type_node,
8753 char_type_node, NULL_TREE);
8755 tree int_ftype_int_int
8756 = build_function_type_list (integer_type_node,
8757 integer_type_node, integer_type_node,
8760 tree opaque_ftype_opaque_opaque
8761 = build_function_type_list (opaque_V4SI_type_node,
8762 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
8763 tree v4si_ftype_v4si_v4si
8764 = build_function_type_list (V4SI_type_node,
8765 V4SI_type_node, V4SI_type_node, NULL_TREE);
8766 tree v4sf_ftype_v4si_int
8767 = build_function_type_list (V4SF_type_node,
8768 V4SI_type_node, integer_type_node, NULL_TREE);
8769 tree v4si_ftype_v4sf_int
8770 = build_function_type_list (V4SI_type_node,
8771 V4SF_type_node, integer_type_node, NULL_TREE);
8772 tree v4si_ftype_v4si_int
8773 = build_function_type_list (V4SI_type_node,
8774 V4SI_type_node, integer_type_node, NULL_TREE);
8775 tree v8hi_ftype_v8hi_int
8776 = build_function_type_list (V8HI_type_node,
8777 V8HI_type_node, integer_type_node, NULL_TREE);
8778 tree v16qi_ftype_v16qi_int
8779 = build_function_type_list (V16QI_type_node,
8780 V16QI_type_node, integer_type_node, NULL_TREE);
8781 tree v16qi_ftype_v16qi_v16qi_int
8782 = build_function_type_list (V16QI_type_node,
8783 V16QI_type_node, V16QI_type_node,
8784 integer_type_node, NULL_TREE);
8785 tree v8hi_ftype_v8hi_v8hi_int
8786 = build_function_type_list (V8HI_type_node,
8787 V8HI_type_node, V8HI_type_node,
8788 integer_type_node, NULL_TREE);
8789 tree v4si_ftype_v4si_v4si_int
8790 = build_function_type_list (V4SI_type_node,
8791 V4SI_type_node, V4SI_type_node,
8792 integer_type_node, NULL_TREE);
8793 tree v4sf_ftype_v4sf_v4sf_int
8794 = build_function_type_list (V4SF_type_node,
8795 V4SF_type_node, V4SF_type_node,
8796 integer_type_node, NULL_TREE);
8797 tree v4sf_ftype_v4sf_v4sf
8798 = build_function_type_list (V4SF_type_node,
8799 V4SF_type_node, V4SF_type_node, NULL_TREE);
8800 tree opaque_ftype_opaque_opaque_opaque
8801 = build_function_type_list (opaque_V4SI_type_node,
8802 opaque_V4SI_type_node, opaque_V4SI_type_node,
8803 opaque_V4SI_type_node, NULL_TREE);
8804 tree v4sf_ftype_v4sf_v4sf_v4si
8805 = build_function_type_list (V4SF_type_node,
8806 V4SF_type_node, V4SF_type_node,
8807 V4SI_type_node, NULL_TREE);
8808 tree v4sf_ftype_v4sf_v4sf_v4sf
8809 = build_function_type_list (V4SF_type_node,
8810 V4SF_type_node, V4SF_type_node,
8811 V4SF_type_node, NULL_TREE);
8812 tree v4si_ftype_v4si_v4si_v4si
8813 = build_function_type_list (V4SI_type_node,
8814 V4SI_type_node, V4SI_type_node,
8815 V4SI_type_node, NULL_TREE);
8816 tree v8hi_ftype_v8hi_v8hi
8817 = build_function_type_list (V8HI_type_node,
8818 V8HI_type_node, V8HI_type_node, NULL_TREE);
8819 tree v8hi_ftype_v8hi_v8hi_v8hi
8820 = build_function_type_list (V8HI_type_node,
8821 V8HI_type_node, V8HI_type_node,
8822 V8HI_type_node, NULL_TREE);
8823 tree v4si_ftype_v8hi_v8hi_v4si
8824 = build_function_type_list (V4SI_type_node,
8825 V8HI_type_node, V8HI_type_node,
8826 V4SI_type_node, NULL_TREE);
8827 tree v4si_ftype_v16qi_v16qi_v4si
8828 = build_function_type_list (V4SI_type_node,
8829 V16QI_type_node, V16QI_type_node,
8830 V4SI_type_node, NULL_TREE);
8831 tree v16qi_ftype_v16qi_v16qi
8832 = build_function_type_list (V16QI_type_node,
8833 V16QI_type_node, V16QI_type_node, NULL_TREE);
8834 tree v4si_ftype_v4sf_v4sf
8835 = build_function_type_list (V4SI_type_node,
8836 V4SF_type_node, V4SF_type_node, NULL_TREE);
8837 tree v8hi_ftype_v16qi_v16qi
8838 = build_function_type_list (V8HI_type_node,
8839 V16QI_type_node, V16QI_type_node, NULL_TREE);
8840 tree v4si_ftype_v8hi_v8hi
8841 = build_function_type_list (V4SI_type_node,
8842 V8HI_type_node, V8HI_type_node, NULL_TREE);
8843 tree v8hi_ftype_v4si_v4si
8844 = build_function_type_list (V8HI_type_node,
8845 V4SI_type_node, V4SI_type_node, NULL_TREE);
8846 tree v16qi_ftype_v8hi_v8hi
8847 = build_function_type_list (V16QI_type_node,
8848 V8HI_type_node, V8HI_type_node, NULL_TREE);
8849 tree v4si_ftype_v16qi_v4si
8850 = build_function_type_list (V4SI_type_node,
8851 V16QI_type_node, V4SI_type_node, NULL_TREE);
8852 tree v4si_ftype_v16qi_v16qi
8853 = build_function_type_list (V4SI_type_node,
8854 V16QI_type_node, V16QI_type_node, NULL_TREE);
8855 tree v4si_ftype_v8hi_v4si
8856 = build_function_type_list (V4SI_type_node,
8857 V8HI_type_node, V4SI_type_node, NULL_TREE);
8858 tree v4si_ftype_v8hi
8859 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8860 tree int_ftype_v4si_v4si
8861 = build_function_type_list (integer_type_node,
8862 V4SI_type_node, V4SI_type_node, NULL_TREE);
8863 tree int_ftype_v4sf_v4sf
8864 = build_function_type_list (integer_type_node,
8865 V4SF_type_node, V4SF_type_node, NULL_TREE);
8866 tree int_ftype_v16qi_v16qi
8867 = build_function_type_list (integer_type_node,
8868 V16QI_type_node, V16QI_type_node, NULL_TREE);
8869 tree int_ftype_v8hi_v8hi
8870 = build_function_type_list (integer_type_node,
8871 V8HI_type_node, V8HI_type_node, NULL_TREE);
8873 /* Add the simple ternary operators. */
8874 d = (struct builtin_description *) bdesc_3arg;
8875 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8877 enum machine_mode mode0, mode1, mode2, mode3;
8879 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8880 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8891 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8894 mode0 = insn_data[d->icode].operand[0].mode;
8895 mode1 = insn_data[d->icode].operand[1].mode;
8896 mode2 = insn_data[d->icode].operand[2].mode;
8897 mode3 = insn_data[d->icode].operand[3].mode;
8900 /* When all four are of the same mode. */
8901 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8906 type = opaque_ftype_opaque_opaque_opaque;
8909 type = v4si_ftype_v4si_v4si_v4si;
8912 type = v4sf_ftype_v4sf_v4sf_v4sf;
8915 type = v8hi_ftype_v8hi_v8hi_v8hi;
8918 type = v16qi_ftype_v16qi_v16qi_v16qi;
8924 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8929 type = v4si_ftype_v4si_v4si_v16qi;
8932 type = v4sf_ftype_v4sf_v4sf_v16qi;
8935 type = v8hi_ftype_v8hi_v8hi_v16qi;
8938 type = v16qi_ftype_v16qi_v16qi_v16qi;
8944 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8945 && mode3 == V4SImode)
8946 type = v4si_ftype_v16qi_v16qi_v4si;
8947 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8948 && mode3 == V4SImode)
8949 type = v4si_ftype_v8hi_v8hi_v4si;
8950 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8951 && mode3 == V4SImode)
8952 type = v4sf_ftype_v4sf_v4sf_v4si;
8954 /* vchar, vchar, vchar, 4 bit literal. */
8955 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8957 type = v16qi_ftype_v16qi_v16qi_int;
8959 /* vshort, vshort, vshort, 4 bit literal. */
8960 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8962 type = v8hi_ftype_v8hi_v8hi_int;
8964 /* vint, vint, vint, 4 bit literal. */
8965 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8967 type = v4si_ftype_v4si_v4si_int;
8969 /* vfloat, vfloat, vfloat, 4 bit literal. */
8970 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8972 type = v4sf_ftype_v4sf_v4sf_int;
8977 def_builtin (d->mask, d->name, type, d->code);
8980 /* Add the simple binary operators. */
8981 d = (struct builtin_description *) bdesc_2arg;
8982 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8984 enum machine_mode mode0, mode1, mode2;
8986 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8987 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8997 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9000 mode0 = insn_data[d->icode].operand[0].mode;
9001 mode1 = insn_data[d->icode].operand[1].mode;
9002 mode2 = insn_data[d->icode].operand[2].mode;
9005 /* When all three operands are of the same mode. */
9006 if (mode0 == mode1 && mode1 == mode2)
9011 type = opaque_ftype_opaque_opaque;
9014 type = v4sf_ftype_v4sf_v4sf;
9017 type = v4si_ftype_v4si_v4si;
9020 type = v16qi_ftype_v16qi_v16qi;
9023 type = v8hi_ftype_v8hi_v8hi;
9026 type = v2si_ftype_v2si_v2si;
9029 type = v2sf_ftype_v2sf_v2sf;
9032 type = int_ftype_int_int;
9039 /* A few other combos we really don't want to do manually. */
9041 /* vint, vfloat, vfloat. */
9042 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
9043 type = v4si_ftype_v4sf_v4sf;
9045 /* vshort, vchar, vchar. */
9046 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
9047 type = v8hi_ftype_v16qi_v16qi;
9049 /* vint, vshort, vshort. */
9050 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
9051 type = v4si_ftype_v8hi_v8hi;
9053 /* vshort, vint, vint. */
9054 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
9055 type = v8hi_ftype_v4si_v4si;
9057 /* vchar, vshort, vshort. */
9058 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
9059 type = v16qi_ftype_v8hi_v8hi;
9061 /* vint, vchar, vint. */
9062 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
9063 type = v4si_ftype_v16qi_v4si;
9065 /* vint, vchar, vchar. */
9066 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
9067 type = v4si_ftype_v16qi_v16qi;
9069 /* vint, vshort, vint. */
9070 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
9071 type = v4si_ftype_v8hi_v4si;
9073 /* vint, vint, 5 bit literal. */
9074 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
9075 type = v4si_ftype_v4si_int;
9077 /* vshort, vshort, 5 bit literal. */
9078 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
9079 type = v8hi_ftype_v8hi_int;
9081 /* vchar, vchar, 5 bit literal. */
9082 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
9083 type = v16qi_ftype_v16qi_int;
9085 /* vfloat, vint, 5 bit literal. */
9086 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
9087 type = v4sf_ftype_v4si_int;
9089 /* vint, vfloat, 5 bit literal. */
9090 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
9091 type = v4si_ftype_v4sf_int;
9093 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
9094 type = v2si_ftype_int_int;
9096 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
9097 type = v2si_ftype_v2si_char;
9099 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
9100 type = v2si_ftype_int_char;
9105 gcc_assert (mode0 == SImode);
9109 type = int_ftype_v4si_v4si;
9112 type = int_ftype_v4sf_v4sf;
9115 type = int_ftype_v16qi_v16qi;
9118 type = int_ftype_v8hi_v8hi;
9125 def_builtin (d->mask, d->name, type, d->code);
9128 /* Add the simple unary operators. */
9129 d = (struct builtin_description *) bdesc_1arg;
9130 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9132 enum machine_mode mode0, mode1;
9134 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9135 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9144 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9147 mode0 = insn_data[d->icode].operand[0].mode;
9148 mode1 = insn_data[d->icode].operand[1].mode;
9151 if (mode0 == V4SImode && mode1 == QImode)
9152 type = v4si_ftype_int;
9153 else if (mode0 == V8HImode && mode1 == QImode)
9154 type = v8hi_ftype_int;
9155 else if (mode0 == V16QImode && mode1 == QImode)
9156 type = v16qi_ftype_int;
9157 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9158 type = opaque_ftype_opaque;
9159 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9160 type = v4sf_ftype_v4sf;
9161 else if (mode0 == V8HImode && mode1 == V16QImode)
9162 type = v8hi_ftype_v16qi;
9163 else if (mode0 == V4SImode && mode1 == V8HImode)
9164 type = v4si_ftype_v8hi;
9165 else if (mode0 == V2SImode && mode1 == V2SImode)
9166 type = v2si_ftype_v2si;
9167 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9168 type = v2sf_ftype_v2sf;
9169 else if (mode0 == V2SFmode && mode1 == V2SImode)
9170 type = v2sf_ftype_v2si;
9171 else if (mode0 == V2SImode && mode1 == V2SFmode)
9172 type = v2si_ftype_v2sf;
9173 else if (mode0 == V2SImode && mode1 == QImode)
9174 type = v2si_ftype_char;
9178 def_builtin (d->mask, d->name, type, d->code);
9183 rs6000_init_libfuncs (void)
9185 if (!TARGET_HARD_FLOAT)
9188 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
9189 && !TARGET_POWER2 && !TARGET_POWERPC)
9191 /* AIX library routines for float->int conversion. */
9192 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9193 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9194 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9195 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9198 if (!TARGET_IEEEQUAD)
9199 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9200 if (!TARGET_XL_COMPAT)
9202 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9203 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9204 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9205 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9209 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9210 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9211 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9212 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9216 /* 32-bit SVR4 quad floating point routines. */
9218 set_optab_libfunc (add_optab, TFmode, "_q_add");
9219 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9220 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9221 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9222 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9223 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9224 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9226 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9227 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9228 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9229 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9230 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9231 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9233 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9234 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9235 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9236 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9237 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9238 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9239 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9240 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9245 /* Expand a block clear operation, and return 1 if successful. Return 0
9246 if we should let the compiler generate normal code.
9248 operands[0] is the destination
9249 operands[1] is the length
9250 operands[3] is the alignment */
9253 expand_block_clear (rtx operands[])
9255 rtx orig_dest = operands[0];
9256 rtx bytes_rtx = operands[1];
9257 rtx align_rtx = operands[3];
9258 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9259 HOST_WIDE_INT align;
9260 HOST_WIDE_INT bytes;
9265 /* If this is not a fixed size move, just call memcpy */
9269 /* This must be a fixed size alignment */
9270 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9271 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9273 /* Anything to clear? */
9274 bytes = INTVAL (bytes_rtx);
9278 /* Use the builtin memset after a point, to avoid huge code bloat.
9279 When optimize_size, avoid any significant code bloat; calling
9280 memset is about 4 instructions, so allow for one instruction to
9281 load zero and three to do clearing. */
9282 if (TARGET_ALTIVEC && align >= 128)
9284 else if (TARGET_POWERPC64 && align >= 32)
9289 if (optimize_size && bytes > 3 * clear_step)
9291 if (! optimize_size && bytes > 8 * clear_step)
9294 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9296 enum machine_mode mode = BLKmode;
9299 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9304 else if (bytes >= 8 && TARGET_POWERPC64
9305 /* 64-bit loads and stores require word-aligned
9307 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9312 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9313 { /* move 4 bytes */
9317 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9318 { /* move 2 bytes */
9322 else /* move 1 byte at a time */
9328 dest = adjust_address (orig_dest, mode, offset);
9330 emit_move_insn (dest, CONST0_RTX (mode));
9337 /* Expand a block move operation, and return 1 if successful. Return 0
9338 if we should let the compiler generate normal code.
9340 operands[0] is the destination
9341 operands[1] is the source
9342 operands[2] is the length
9343 operands[3] is the alignment */
9345 #define MAX_MOVE_REG 4
9348 expand_block_move (rtx operands[])
9350 rtx orig_dest = operands[0];
9351 rtx orig_src = operands[1];
9352 rtx bytes_rtx = operands[2];
9353 rtx align_rtx = operands[3];
9354 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9359 rtx stores[MAX_MOVE_REG];
9362 /* If this is not a fixed size move, just call memcpy */
9366 /* This must be a fixed size alignment */
9367 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9368 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9370 /* Anything to move? */
9371 bytes = INTVAL (bytes_rtx);
9375 /* store_one_arg depends on expand_block_move to handle at least the size of
9376 reg_parm_stack_space. */
9377 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9380 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9383 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9384 rtx (*mov) (rtx, rtx);
9386 enum machine_mode mode = BLKmode;
9389 /* Altivec first, since it will be faster than a string move
9390 when it applies, and usually not significantly larger. */
9391 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9395 gen_func.mov = gen_movv4si;
9397 else if (TARGET_STRING
9398 && bytes > 24 /* move up to 32 bytes at a time */
9406 && ! fixed_regs[12])
9408 move_bytes = (bytes > 32) ? 32 : bytes;
9409 gen_func.movmemsi = gen_movmemsi_8reg;
9411 else if (TARGET_STRING
9412 && bytes > 16 /* move up to 24 bytes at a time */
9418 && ! fixed_regs[10])
9420 move_bytes = (bytes > 24) ? 24 : bytes;
9421 gen_func.movmemsi = gen_movmemsi_6reg;
9423 else if (TARGET_STRING
9424 && bytes > 8 /* move up to 16 bytes at a time */
9430 move_bytes = (bytes > 16) ? 16 : bytes;
9431 gen_func.movmemsi = gen_movmemsi_4reg;
9433 else if (bytes >= 8 && TARGET_POWERPC64
9434 /* 64-bit loads and stores require word-aligned
9436 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9440 gen_func.mov = gen_movdi;
9442 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9443 { /* move up to 8 bytes at a time */
9444 move_bytes = (bytes > 8) ? 8 : bytes;
9445 gen_func.movmemsi = gen_movmemsi_2reg;
9447 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9448 { /* move 4 bytes */
9451 gen_func.mov = gen_movsi;
9453 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9454 { /* move 2 bytes */
9457 gen_func.mov = gen_movhi;
9459 else if (TARGET_STRING && bytes > 1)
9460 { /* move up to 4 bytes at a time */
9461 move_bytes = (bytes > 4) ? 4 : bytes;
9462 gen_func.movmemsi = gen_movmemsi_1reg;
9464 else /* move 1 byte at a time */
9468 gen_func.mov = gen_movqi;
9471 src = adjust_address (orig_src, mode, offset);
9472 dest = adjust_address (orig_dest, mode, offset);
9474 if (mode != BLKmode)
9476 rtx tmp_reg = gen_reg_rtx (mode);
9478 emit_insn ((*gen_func.mov) (tmp_reg, src));
9479 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9482 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9485 for (i = 0; i < num_reg; i++)
9486 emit_insn (stores[i]);
9490 if (mode == BLKmode)
9492 /* Move the address into scratch registers. The movmemsi
9493 patterns require zero offset. */
9494 if (!REG_P (XEXP (src, 0)))
9496 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9497 src = replace_equiv_address (src, src_reg);
9499 set_mem_size (src, GEN_INT (move_bytes));
9501 if (!REG_P (XEXP (dest, 0)))
9503 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9504 dest = replace_equiv_address (dest, dest_reg);
9506 set_mem_size (dest, GEN_INT (move_bytes));
9508 emit_insn ((*gen_func.movmemsi) (dest, src,
9509 GEN_INT (move_bytes & 31),
9518 /* Return a string to perform a load_multiple operation.
9519 operands[0] is the vector.
9520 operands[1] is the source address.
9521 operands[2] is the first destination register. */
9524 rs6000_output_load_multiple (rtx operands[3])
9526 /* We have to handle the case where the pseudo used to contain the address
9527 is assigned to one of the output registers. */
9529 int words = XVECLEN (operands[0], 0);
9532 if (XVECLEN (operands[0], 0) == 1)
9533 return "{l|lwz} %2,0(%1)";
9535 for (i = 0; i < words; i++)
9536 if (refers_to_regno_p (REGNO (operands[2]) + i,
9537 REGNO (operands[2]) + i + 1, operands[1], 0))
9541 xop[0] = GEN_INT (4 * (words-1));
9542 xop[1] = operands[1];
9543 xop[2] = operands[2];
9544 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9549 xop[0] = GEN_INT (4 * (words-1));
9550 xop[1] = operands[1];
9551 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9552 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9557 for (j = 0; j < words; j++)
9560 xop[0] = GEN_INT (j * 4);
9561 xop[1] = operands[1];
9562 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9563 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9565 xop[0] = GEN_INT (i * 4);
9566 xop[1] = operands[1];
9567 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9572 return "{lsi|lswi} %2,%1,%N0";
9576 /* A validation routine: say whether CODE, a condition code, and MODE
9577 match. The other alternatives either don't make sense or should
9578 never be generated. */
9581 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9583 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
9584 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9585 && GET_MODE_CLASS (mode) == MODE_CC);
9587 /* These don't make sense. */
9588 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
9589 || mode != CCUNSmode);
9591 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
9592 || mode == CCUNSmode);
9594 gcc_assert (mode == CCFPmode
9595 || (code != ORDERED && code != UNORDERED
9596 && code != UNEQ && code != LTGT
9597 && code != UNGT && code != UNLT
9598 && code != UNGE && code != UNLE));
9600 /* These should never be generated except for
9601 flag_finite_math_only. */
9602 gcc_assert (mode != CCFPmode
9603 || flag_finite_math_only
9604 || (code != LE && code != GE
9605 && code != UNEQ && code != LTGT
9606 && code != UNGT && code != UNLT));
9608 /* These are invalid; the information is not there. */
9609 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
9613 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9614 mask required to convert the result of a rotate insn into a shift
9615 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9618 includes_lshift_p (rtx shiftop, rtx andop)
9620 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9622 shift_mask <<= INTVAL (shiftop);
9624 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9627 /* Similar, but for right shift. */
9630 includes_rshift_p (rtx shiftop, rtx andop)
9632 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9634 shift_mask >>= INTVAL (shiftop);
9636 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9639 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9640 to perform a left shift. It must have exactly SHIFTOP least
9641 significant 0's, then one or more 1's, then zero or more 0's. */
9644 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9646 if (GET_CODE (andop) == CONST_INT)
9648 HOST_WIDE_INT c, lsb, shift_mask;
9651 if (c == 0 || c == ~0)
9655 shift_mask <<= INTVAL (shiftop);
9657 /* Find the least significant one bit. */
9660 /* It must coincide with the LSB of the shift mask. */
9661 if (-lsb != shift_mask)
9664 /* Invert to look for the next transition (if any). */
9667 /* Remove the low group of ones (originally low group of zeros). */
9670 /* Again find the lsb, and check we have all 1's above. */
9674 else if (GET_CODE (andop) == CONST_DOUBLE
9675 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9677 HOST_WIDE_INT low, high, lsb;
9678 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9680 low = CONST_DOUBLE_LOW (andop);
9681 if (HOST_BITS_PER_WIDE_INT < 64)
9682 high = CONST_DOUBLE_HIGH (andop);
9684 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9685 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9688 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9690 shift_mask_high = ~0;
9691 if (INTVAL (shiftop) > 32)
9692 shift_mask_high <<= INTVAL (shiftop) - 32;
9696 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9703 return high == -lsb;
9706 shift_mask_low = ~0;
9707 shift_mask_low <<= INTVAL (shiftop);
9711 if (-lsb != shift_mask_low)
9714 if (HOST_BITS_PER_WIDE_INT < 64)
9719 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9722 return high == -lsb;
9726 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9732 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9733 to perform a left shift. It must have SHIFTOP or more least
9734 significant 0's, with the remainder of the word 1's. */
9737 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9739 if (GET_CODE (andop) == CONST_INT)
9741 HOST_WIDE_INT c, lsb, shift_mask;
9744 shift_mask <<= INTVAL (shiftop);
9747 /* Find the least significant one bit. */
9750 /* It must be covered by the shift mask.
9751 This test also rejects c == 0. */
9752 if ((lsb & shift_mask) == 0)
9755 /* Check we have all 1's above the transition, and reject all 1's. */
9756 return c == -lsb && lsb != 1;
9758 else if (GET_CODE (andop) == CONST_DOUBLE
9759 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9761 HOST_WIDE_INT low, lsb, shift_mask_low;
9763 low = CONST_DOUBLE_LOW (andop);
9765 if (HOST_BITS_PER_WIDE_INT < 64)
9767 HOST_WIDE_INT high, shift_mask_high;
9769 high = CONST_DOUBLE_HIGH (andop);
9773 shift_mask_high = ~0;
9774 if (INTVAL (shiftop) > 32)
9775 shift_mask_high <<= INTVAL (shiftop) - 32;
9779 if ((lsb & shift_mask_high) == 0)
9782 return high == -lsb;
9788 shift_mask_low = ~0;
9789 shift_mask_low <<= INTVAL (shiftop);
9793 if ((lsb & shift_mask_low) == 0)
9796 return low == -lsb && lsb != 1;
9802 /* Return 1 if operands will generate a valid arguments to rlwimi
9803 instruction for insert with right shift in 64-bit mode. The mask may
9804 not start on the first bit or stop on the last bit because wrap-around
9805 effects of instruction do not correspond to semantics of RTL insn. */
9808 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9810 if (INTVAL (startop) > 32
9811 && INTVAL (startop) < 64
9812 && INTVAL (sizeop) > 1
9813 && INTVAL (sizeop) + INTVAL (startop) < 64
9814 && INTVAL (shiftop) > 0
9815 && INTVAL (sizeop) + INTVAL (shiftop) < 32
9816 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9822 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9823 for lfq and stfq insns iff the registers are hard registers. */
9826 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
9828 /* We might have been passed a SUBREG. */
9829 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
9832 /* We might have been passed non floating point registers. */
9833 if (!FP_REGNO_P (REGNO (reg1))
9834 || !FP_REGNO_P (REGNO (reg2)))
9837 return (REGNO (reg1) == REGNO (reg2) - 1);
9840 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9841 addr1 and addr2 must be in consecutive memory locations
9842 (addr2 == addr1 + 8). */
9845 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
9848 unsigned int reg1, reg2;
9849 int offset1, offset2;
9851 /* The mems cannot be volatile. */
9852 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9855 addr1 = XEXP (mem1, 0);
9856 addr2 = XEXP (mem2, 0);
9858 /* Extract an offset (if used) from the first addr. */
9859 if (GET_CODE (addr1) == PLUS)
9861 /* If not a REG, return zero. */
9862 if (GET_CODE (XEXP (addr1, 0)) != REG)
9866 reg1 = REGNO (XEXP (addr1, 0));
9867 /* The offset must be constant! */
9868 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
9870 offset1 = INTVAL (XEXP (addr1, 1));
9873 else if (GET_CODE (addr1) != REG)
9877 reg1 = REGNO (addr1);
9878 /* This was a simple (mem (reg)) expression. Offset is 0. */
9882 /* And now for the second addr. */
9883 if (GET_CODE (addr2) == PLUS)
9885 /* If not a REG, return zero. */
9886 if (GET_CODE (XEXP (addr2, 0)) != REG)
9890 reg2 = REGNO (XEXP (addr2, 0));
9891 /* The offset must be constant. */
9892 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9894 offset2 = INTVAL (XEXP (addr2, 1));
9897 else if (GET_CODE (addr2) != REG)
9901 reg2 = REGNO (addr2);
9902 /* This was a simple (mem (reg)) expression. Offset is 0. */
9906 /* Both of these must have the same base register. */
9910 /* The offset for the second addr must be 8 more than the first addr. */
9911 if (offset2 != offset1 + 8)
9914 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9919 /* Return the register class of a scratch register needed to copy IN into
9920 or out of a register in CLASS in MODE. If it can be done directly,
9921 NO_REGS is returned. */
9924 rs6000_secondary_reload_class (enum reg_class class,
9925 enum machine_mode mode ATTRIBUTE_UNUSED,
9930 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9932 && MACHOPIC_INDIRECT
9936 /* We cannot copy a symbolic operand directly into anything
9937 other than BASE_REGS for TARGET_ELF. So indicate that a
9938 register from BASE_REGS is needed as an intermediate
9941 On Darwin, pic addresses require a load from memory, which
9942 needs a base register. */
9943 if (class != BASE_REGS
9944 && (GET_CODE (in) == SYMBOL_REF
9945 || GET_CODE (in) == HIGH
9946 || GET_CODE (in) == LABEL_REF
9947 || GET_CODE (in) == CONST))
9951 if (GET_CODE (in) == REG)
9954 if (regno >= FIRST_PSEUDO_REGISTER)
9956 regno = true_regnum (in);
9957 if (regno >= FIRST_PSEUDO_REGISTER)
9961 else if (GET_CODE (in) == SUBREG)
9963 regno = true_regnum (in);
9964 if (regno >= FIRST_PSEUDO_REGISTER)
9970 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9972 if (class == GENERAL_REGS || class == BASE_REGS
9973 || (regno >= 0 && INT_REGNO_P (regno)))
9976 /* Constants, memory, and FP registers can go into FP registers. */
9977 if ((regno == -1 || FP_REGNO_P (regno))
9978 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
9981 /* Memory, and AltiVec registers can go into AltiVec registers. */
9982 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
9983 && class == ALTIVEC_REGS)
9986 /* We can copy among the CR registers. */
9987 if ((class == CR_REGS || class == CR0_REGS)
9988 && regno >= 0 && CR_REGNO_P (regno))
9991 /* Otherwise, we need GENERAL_REGS. */
9992 return GENERAL_REGS;
9995 /* Given a comparison operation, return the bit number in CCR to test. We
9996 know this is a valid comparison.
9998 SCC_P is 1 if this is for an scc. That means that %D will have been
9999 used instead of %C, so the bits will be in different places.
10001 Return -1 if OP isn't a valid comparison for some reason. */
10004 ccr_bit (rtx op, int scc_p)
10006 enum rtx_code code = GET_CODE (op);
10007 enum machine_mode cc_mode;
10012 if (!COMPARISON_P (op))
10015 reg = XEXP (op, 0);
10017 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
10019 cc_mode = GET_MODE (reg);
10020 cc_regnum = REGNO (reg);
10021 base_bit = 4 * (cc_regnum - CR0_REGNO);
10023 validate_condition_mode (code, cc_mode);
10025 /* When generating a sCOND operation, only positive conditions are
10028 || code == EQ || code == GT || code == LT || code == UNORDERED
10029 || code == GTU || code == LTU);
10034 return scc_p ? base_bit + 3 : base_bit + 2;
10036 return base_bit + 2;
10037 case GT: case GTU: case UNLE:
10038 return base_bit + 1;
10039 case LT: case LTU: case UNGE:
10041 case ORDERED: case UNORDERED:
10042 return base_bit + 3;
10045 /* If scc, we will have done a cror to put the bit in the
10046 unordered position. So test that bit. For integer, this is ! LT
10047 unless this is an scc insn. */
10048 return scc_p ? base_bit + 3 : base_bit;
10051 return scc_p ? base_bit + 3 : base_bit + 1;
10054 gcc_unreachable ();
10058 /* Return the GOT register. */
10061 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10063 /* The second flow pass currently (June 1999) can't update
10064 regs_ever_live without disturbing other parts of the compiler, so
10065 update it here to make the prolog/epilogue code happy. */
10066 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
10067 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10069 current_function_uses_pic_offset_table = 1;
10071 return pic_offset_table_rtx;
10074 /* Function to init struct machine_function.
10075 This will be called, via a pointer variable,
10076 from push_function_context. */
10078 static struct machine_function *
10079 rs6000_init_machine_status (void)
10081 return ggc_alloc_cleared (sizeof (machine_function));
10084 /* These macros test for integers and extract the low-order bits. */
10086 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10087 && GET_MODE (X) == VOIDmode)
10089 #define INT_LOWPART(X) \
10090 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10093 extract_MB (rtx op)
10096 unsigned long val = INT_LOWPART (op);
10098 /* If the high bit is zero, the value is the first 1 bit we find
10100 if ((val & 0x80000000) == 0)
10102 gcc_assert (val & 0xffffffff);
10105 while (((val <<= 1) & 0x80000000) == 0)
10110 /* If the high bit is set and the low bit is not, or the mask is all
10111 1's, the value is zero. */
10112 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10115 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10118 while (((val >>= 1) & 1) != 0)
10125 extract_ME (rtx op)
10128 unsigned long val = INT_LOWPART (op);
10130 /* If the low bit is zero, the value is the first 1 bit we find from
10132 if ((val & 1) == 0)
10134 gcc_assert (val & 0xffffffff);
10137 while (((val >>= 1) & 1) == 0)
10143 /* If the low bit is set and the high bit is not, or the mask is all
10144 1's, the value is 31. */
10145 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10148 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10151 while (((val <<= 1) & 0x80000000) != 0)
10157 /* Locate some local-dynamic symbol still in use by this function
10158 so that we can print its name in some tls_ld pattern. */
10160 static const char *
10161 rs6000_get_some_local_dynamic_name (void)
10165 if (cfun->machine->some_ld_name)
10166 return cfun->machine->some_ld_name;
10168 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10170 && for_each_rtx (&PATTERN (insn),
10171 rs6000_get_some_local_dynamic_name_1, 0))
10172 return cfun->machine->some_ld_name;
10174 gcc_unreachable ();
10177 /* Helper function for rs6000_get_some_local_dynamic_name. */
10180 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10184 if (GET_CODE (x) == SYMBOL_REF)
10186 const char *str = XSTR (x, 0);
10187 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10189 cfun->machine->some_ld_name = str;
10197 /* Write out a function code label. */
10200 rs6000_output_function_entry (FILE *file, const char *fname)
10202 if (fname[0] != '.')
10204 switch (DEFAULT_ABI)
10207 gcc_unreachable ();
10213 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10222 RS6000_OUTPUT_BASENAME (file, fname);
10224 assemble_name (file, fname);
10227 /* Print an operand. Recognize special options, documented below. */
10230 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10231 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10233 #define SMALL_DATA_RELOC "sda21"
10234 #define SMALL_DATA_REG 0
10238 print_operand (FILE *file, rtx x, int code)
10242 unsigned HOST_WIDE_INT uval;
10247 /* Write out an instruction after the call which may be replaced
10248 with glue code by the loader. This depends on the AIX version. */
10249 asm_fprintf (file, RS6000_CALL_GLUE);
10252 /* %a is output_address. */
10255 /* If X is a constant integer whose low-order 5 bits are zero,
10256 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10257 in the AIX assembler where "sri" with a zero shift count
10258 writes a trash instruction. */
10259 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10266 /* If constant, low-order 16 bits of constant, unsigned.
10267 Otherwise, write normally. */
10269 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10271 print_operand (file, x, 0);
10275 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10276 for 64-bit mask direction. */
10277 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10280 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10284 /* X is a CR register. Print the number of the GT bit of the CR. */
10285 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10286 output_operand_lossage ("invalid %%E value");
10288 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10292 /* Like 'J' but get to the GT bit only. */
10293 gcc_assert (GET_CODE (x) == REG);
10295 /* Bit 1 is GT bit. */
10296 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
10298 /* Add one for shift count in rlinm for scc. */
10299 fprintf (file, "%d", i + 1);
10303 /* X is a CR register. Print the number of the EQ bit of the CR */
10304 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10305 output_operand_lossage ("invalid %%E value");
10307 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10311 /* X is a CR register. Print the shift count needed to move it
10312 to the high-order four bits. */
10313 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10314 output_operand_lossage ("invalid %%f value");
10316 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10320 /* Similar, but print the count for the rotate in the opposite
10322 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10323 output_operand_lossage ("invalid %%F value");
10325 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10329 /* X is a constant integer. If it is negative, print "m",
10330 otherwise print "z". This is to make an aze or ame insn. */
10331 if (GET_CODE (x) != CONST_INT)
10332 output_operand_lossage ("invalid %%G value");
10333 else if (INTVAL (x) >= 0)
10340 /* If constant, output low-order five bits. Otherwise, write
10343 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10345 print_operand (file, x, 0);
10349 /* If constant, output low-order six bits. Otherwise, write
10352 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10354 print_operand (file, x, 0);
10358 /* Print `i' if this is a constant, else nothing. */
10364 /* Write the bit number in CCR for jump. */
10365 i = ccr_bit (x, 0);
10367 output_operand_lossage ("invalid %%j code");
10369 fprintf (file, "%d", i);
10373 /* Similar, but add one for shift count in rlinm for scc and pass
10374 scc flag to `ccr_bit'. */
10375 i = ccr_bit (x, 1);
10377 output_operand_lossage ("invalid %%J code");
10379 /* If we want bit 31, write a shift count of zero, not 32. */
10380 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10384 /* X must be a constant. Write the 1's complement of the
10387 output_operand_lossage ("invalid %%k value");
10389 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10393 /* X must be a symbolic constant on ELF. Write an
10394 expression suitable for an 'addi' that adds in the low 16
10395 bits of the MEM. */
10396 if (GET_CODE (x) != CONST)
10398 print_operand_address (file, x);
10399 fputs ("@l", file);
10403 if (GET_CODE (XEXP (x, 0)) != PLUS
10404 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10405 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10406 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10407 output_operand_lossage ("invalid %%K value");
10408 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10409 fputs ("@l", file);
10410 /* For GNU as, there must be a non-alphanumeric character
10411 between 'l' and the number. The '-' is added by
10412 print_operand() already. */
10413 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10415 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10419 /* %l is output_asm_label. */
10422 /* Write second word of DImode or DFmode reference. Works on register
10423 or non-indexed memory only. */
10424 if (GET_CODE (x) == REG)
10425 fputs (reg_names[REGNO (x) + 1], file);
10426 else if (GET_CODE (x) == MEM)
10428 /* Handle possible auto-increment. Since it is pre-increment and
10429 we have already done it, we can just use an offset of word. */
10430 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10431 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10432 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10435 output_address (XEXP (adjust_address_nv (x, SImode,
10439 if (small_data_operand (x, GET_MODE (x)))
10440 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10441 reg_names[SMALL_DATA_REG]);
10446 /* MB value for a mask operand. */
10447 if (! mask_operand (x, SImode))
10448 output_operand_lossage ("invalid %%m value");
10450 fprintf (file, "%d", extract_MB (x));
10454 /* ME value for a mask operand. */
10455 if (! mask_operand (x, SImode))
10456 output_operand_lossage ("invalid %%M value");
10458 fprintf (file, "%d", extract_ME (x));
10461 /* %n outputs the negative of its operand. */
10464 /* Write the number of elements in the vector times 4. */
10465 if (GET_CODE (x) != PARALLEL)
10466 output_operand_lossage ("invalid %%N value");
10468 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10472 /* Similar, but subtract 1 first. */
10473 if (GET_CODE (x) != PARALLEL)
10474 output_operand_lossage ("invalid %%O value");
10476 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10480 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10482 || INT_LOWPART (x) < 0
10483 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10484 output_operand_lossage ("invalid %%p value");
10486 fprintf (file, "%d", i);
10490 /* The operand must be an indirect memory reference. The result
10491 is the register name. */
10492 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10493 || REGNO (XEXP (x, 0)) >= 32)
10494 output_operand_lossage ("invalid %%P value");
10496 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10500 /* This outputs the logical code corresponding to a boolean
10501 expression. The expression may have one or both operands
10502 negated (if one, only the first one). For condition register
10503 logical operations, it will also treat the negated
10504 CR codes as NOTs, but not handle NOTs of them. */
10506 const char *const *t = 0;
10508 enum rtx_code code = GET_CODE (x);
10509 static const char * const tbl[3][3] = {
10510 { "and", "andc", "nor" },
10511 { "or", "orc", "nand" },
10512 { "xor", "eqv", "xor" } };
10516 else if (code == IOR)
10518 else if (code == XOR)
10521 output_operand_lossage ("invalid %%q value");
10523 if (GET_CODE (XEXP (x, 0)) != NOT)
10527 if (GET_CODE (XEXP (x, 1)) == NOT)
10545 /* X is a CR register. Print the mask for `mtcrf'. */
10546 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10547 output_operand_lossage ("invalid %%R value");
10549 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10553 /* Low 5 bits of 32 - value */
10555 output_operand_lossage ("invalid %%s value");
10557 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10561 /* PowerPC64 mask position. All 0's is excluded.
10562 CONST_INT 32-bit mask is considered sign-extended so any
10563 transition must occur within the CONST_INT, not on the boundary. */
10564 if (! mask64_operand (x, DImode))
10565 output_operand_lossage ("invalid %%S value");
10567 uval = INT_LOWPART (x);
10569 if (uval & 1) /* Clear Left */
10571 #if HOST_BITS_PER_WIDE_INT > 64
10572 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10576 else /* Clear Right */
10579 #if HOST_BITS_PER_WIDE_INT > 64
10580 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10586 gcc_assert (i >= 0);
10587 fprintf (file, "%d", i);
10591 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10592 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
10594 /* Bit 3 is OV bit. */
10595 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10597 /* If we want bit 31, write a shift count of zero, not 32. */
10598 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10602 /* Print the symbolic name of a branch target register. */
10603 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10604 && REGNO (x) != COUNT_REGISTER_REGNUM))
10605 output_operand_lossage ("invalid %%T value");
10606 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10607 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10609 fputs ("ctr", file);
10613 /* High-order 16 bits of constant for use in unsigned operand. */
10615 output_operand_lossage ("invalid %%u value");
10617 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10618 (INT_LOWPART (x) >> 16) & 0xffff);
10622 /* High-order 16 bits of constant for use in signed operand. */
10624 output_operand_lossage ("invalid %%v value");
10626 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10627 (INT_LOWPART (x) >> 16) & 0xffff);
10631 /* Print `u' if this has an auto-increment or auto-decrement. */
10632 if (GET_CODE (x) == MEM
10633 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10634 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10639 /* Print the trap code for this operand. */
10640 switch (GET_CODE (x))
10643 fputs ("eq", file); /* 4 */
10646 fputs ("ne", file); /* 24 */
10649 fputs ("lt", file); /* 16 */
10652 fputs ("le", file); /* 20 */
10655 fputs ("gt", file); /* 8 */
10658 fputs ("ge", file); /* 12 */
10661 fputs ("llt", file); /* 2 */
10664 fputs ("lle", file); /* 6 */
10667 fputs ("lgt", file); /* 1 */
10670 fputs ("lge", file); /* 5 */
10673 gcc_unreachable ();
10678 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10681 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10682 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10684 print_operand (file, x, 0);
10688 /* MB value for a PowerPC64 rldic operand. */
10689 val = (GET_CODE (x) == CONST_INT
10690 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10695 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10696 if ((val <<= 1) < 0)
10699 #if HOST_BITS_PER_WIDE_INT == 32
10700 if (GET_CODE (x) == CONST_INT && i >= 0)
10701 i += 32; /* zero-extend high-part was all 0's */
10702 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10704 val = CONST_DOUBLE_LOW (x);
10710 for ( ; i < 64; i++)
10711 if ((val <<= 1) < 0)
10716 fprintf (file, "%d", i + 1);
10720 if (GET_CODE (x) == MEM
10721 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10726 /* Like 'L', for third word of TImode */
10727 if (GET_CODE (x) == REG)
10728 fputs (reg_names[REGNO (x) + 2], file);
10729 else if (GET_CODE (x) == MEM)
10731 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10732 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10733 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10735 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10736 if (small_data_operand (x, GET_MODE (x)))
10737 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10738 reg_names[SMALL_DATA_REG]);
10743 /* X is a SYMBOL_REF. Write out the name preceded by a
10744 period and without any trailing data in brackets. Used for function
10745 names. If we are configured for System V (or the embedded ABI) on
10746 the PowerPC, do not emit the period, since those systems do not use
10747 TOCs and the like. */
10748 gcc_assert (GET_CODE (x) == SYMBOL_REF);
10750 /* Mark the decl as referenced so that cgraph will output the
10752 if (SYMBOL_REF_DECL (x))
10753 mark_decl_referenced (SYMBOL_REF_DECL (x));
10755 /* For macho, check to see if we need a stub. */
10758 const char *name = XSTR (x, 0);
10760 if (MACHOPIC_INDIRECT
10761 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10762 name = machopic_indirection_name (x, /*stub_p=*/true);
10764 assemble_name (file, name);
10766 else if (!DOT_SYMBOLS)
10767 assemble_name (file, XSTR (x, 0));
10769 rs6000_output_function_entry (file, XSTR (x, 0));
10773 /* Like 'L', for last word of TImode. */
10774 if (GET_CODE (x) == REG)
10775 fputs (reg_names[REGNO (x) + 3], file);
10776 else if (GET_CODE (x) == MEM)
10778 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10779 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10780 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10782 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10783 if (small_data_operand (x, GET_MODE (x)))
10784 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10785 reg_names[SMALL_DATA_REG]);
10789 /* Print AltiVec or SPE memory operand. */
10794 gcc_assert (GET_CODE (x) == MEM);
10798 /* Ugly hack because %y is overloaded. */
10799 if (TARGET_E500 && GET_MODE_SIZE (GET_MODE (x)) == 8)
10801 /* Handle [reg]. */
10802 if (GET_CODE (tmp) == REG)
10804 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10807 /* Handle [reg+UIMM]. */
10808 else if (GET_CODE (tmp) == PLUS &&
10809 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10813 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
10815 x = INTVAL (XEXP (tmp, 1));
10816 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10820 /* Fall through. Must be [reg+reg]. */
10823 && GET_CODE (tmp) == AND
10824 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10825 && INTVAL (XEXP (tmp, 1)) == -16)
10826 tmp = XEXP (tmp, 0);
10827 if (GET_CODE (tmp) == REG)
10828 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
10831 gcc_assert (GET_CODE (tmp) == PLUS
10832 && REG_P (XEXP (tmp, 0))
10833 && REG_P (XEXP (tmp, 1)));
10835 if (REGNO (XEXP (tmp, 0)) == 0)
10836 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10837 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10839 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10840 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10846 if (GET_CODE (x) == REG)
10847 fprintf (file, "%s", reg_names[REGNO (x)]);
10848 else if (GET_CODE (x) == MEM)
10850 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10851 know the width from the mode. */
10852 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
10853 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10854 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10855 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
10856 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10857 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10859 output_address (XEXP (x, 0));
10862 output_addr_const (file, x);
10866 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10870 output_operand_lossage ("invalid %%xn code");
10874 /* Print the address of an operand. */
10877 print_operand_address (FILE *file, rtx x)
10879 if (GET_CODE (x) == REG)
10880 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
10881 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10882 || GET_CODE (x) == LABEL_REF)
10884 output_addr_const (file, x);
10885 if (small_data_operand (x, GET_MODE (x)))
10886 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10887 reg_names[SMALL_DATA_REG]);
10889 gcc_assert (!TARGET_TOC);
10891 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10893 gcc_assert (REG_P (XEXP (x, 0)));
10894 if (REGNO (XEXP (x, 0)) == 0)
10895 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10896 reg_names[ REGNO (XEXP (x, 0)) ]);
10898 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10899 reg_names[ REGNO (XEXP (x, 1)) ]);
10901 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
10902 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10903 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
10905 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10906 && CONSTANT_P (XEXP (x, 1)))
10908 output_addr_const (file, XEXP (x, 1));
10909 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10913 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10914 && CONSTANT_P (XEXP (x, 1)))
10916 fprintf (file, "lo16(");
10917 output_addr_const (file, XEXP (x, 1));
10918 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10921 else if (legitimate_constant_pool_address_p (x))
10923 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
10925 rtx contains_minus = XEXP (x, 1);
10929 /* Find the (minus (sym) (toc)) buried in X, and temporarily
10930 turn it into (sym) for output_addr_const. */
10931 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10932 contains_minus = XEXP (contains_minus, 0);
10934 minus = XEXP (contains_minus, 0);
10935 symref = XEXP (minus, 0);
10936 XEXP (contains_minus, 0) = symref;
10941 name = XSTR (symref, 0);
10942 newname = alloca (strlen (name) + sizeof ("@toc"));
10943 strcpy (newname, name);
10944 strcat (newname, "@toc");
10945 XSTR (symref, 0) = newname;
10947 output_addr_const (file, XEXP (x, 1));
10949 XSTR (symref, 0) = name;
10950 XEXP (contains_minus, 0) = minus;
10953 output_addr_const (file, XEXP (x, 1));
10955 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
10958 gcc_unreachable ();
10961 /* Target hook for assembling integer objects. The PowerPC version has
10962 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10963 is defined. It also needs to handle DI-mode objects on 64-bit
10967 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
10969 #ifdef RELOCATABLE_NEEDS_FIXUP
10970 /* Special handling for SI values. */
10971 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
10973 static int recurse = 0;
10975 /* For -mrelocatable, we mark all addresses that need to be fixed up
10976 in the .fixup section. */
10977 if (TARGET_RELOCATABLE
10978 && in_section != toc_section
10979 && in_section != text_section
10980 && !unlikely_text_section_p (in_section)
10982 && GET_CODE (x) != CONST_INT
10983 && GET_CODE (x) != CONST_DOUBLE
10989 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
10991 ASM_OUTPUT_LABEL (asm_out_file, buf);
10992 fprintf (asm_out_file, "\t.long\t(");
10993 output_addr_const (asm_out_file, x);
10994 fprintf (asm_out_file, ")@fixup\n");
10995 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
10996 ASM_OUTPUT_ALIGN (asm_out_file, 2);
10997 fprintf (asm_out_file, "\t.long\t");
10998 assemble_name (asm_out_file, buf);
10999 fprintf (asm_out_file, "\n\t.previous\n");
11003 /* Remove initial .'s to turn a -mcall-aixdesc function
11004 address into the address of the descriptor, not the function
11006 else if (GET_CODE (x) == SYMBOL_REF
11007 && XSTR (x, 0)[0] == '.'
11008 && DEFAULT_ABI == ABI_AIX)
11010 const char *name = XSTR (x, 0);
11011 while (*name == '.')
11014 fprintf (asm_out_file, "\t.long\t%s\n", name);
11018 #endif /* RELOCATABLE_NEEDS_FIXUP */
11019 return default_assemble_integer (x, size, aligned_p);
11022 #ifdef HAVE_GAS_HIDDEN
11023 /* Emit an assembler directive to set symbol visibility for DECL to
11024 VISIBILITY_TYPE. */
11027 rs6000_assemble_visibility (tree decl, int vis)
11029 /* Functions need to have their entry point symbol visibility set as
11030 well as their descriptor symbol visibility. */
11031 if (DEFAULT_ABI == ABI_AIX
11033 && TREE_CODE (decl) == FUNCTION_DECL)
11035 static const char * const visibility_types[] = {
11036 NULL, "internal", "hidden", "protected"
11039 const char *name, *type;
11041 name = ((* targetm.strip_name_encoding)
11042 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
11043 type = visibility_types[vis];
11045 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
11046 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
11049 default_assemble_visibility (decl, vis);
11054 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11056 /* Reversal of FP compares takes care -- an ordered compare
11057 becomes an unordered compare and vice versa. */
11058 if (mode == CCFPmode
11059 && (!flag_finite_math_only
11060 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11061 || code == UNEQ || code == LTGT))
11062 return reverse_condition_maybe_unordered (code);
11064 return reverse_condition (code);
11067 /* Generate a compare for CODE. Return a brand-new rtx that
11068 represents the result of the compare. */
11071 rs6000_generate_compare (enum rtx_code code)
11073 enum machine_mode comp_mode;
11074 rtx compare_result;
11076 if (rs6000_compare_fp_p)
11077 comp_mode = CCFPmode;
11078 else if (code == GTU || code == LTU
11079 || code == GEU || code == LEU)
11080 comp_mode = CCUNSmode;
11081 else if ((code == EQ || code == NE)
11082 && GET_CODE (rs6000_compare_op0) == SUBREG
11083 && GET_CODE (rs6000_compare_op1) == SUBREG
11084 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11085 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11086 /* These are unsigned values, perhaps there will be a later
11087 ordering compare that can be shared with this one.
11088 Unfortunately we cannot detect the signedness of the operands
11089 for non-subregs. */
11090 comp_mode = CCUNSmode;
11092 comp_mode = CCmode;
11094 /* First, the compare. */
11095 compare_result = gen_reg_rtx (comp_mode);
11097 /* E500 FP compare instructions on the GPRs. Yuck! */
11098 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11099 && rs6000_compare_fp_p)
11101 rtx cmp, or_result, compare_result2;
11102 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11104 if (op_mode == VOIDmode)
11105 op_mode = GET_MODE (rs6000_compare_op1);
11107 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
11108 This explains the following mess. */
11112 case EQ: case UNEQ: case NE: case LTGT:
11116 cmp = flag_unsafe_math_optimizations
11117 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11118 rs6000_compare_op1)
11119 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11120 rs6000_compare_op1);
11124 cmp = flag_unsafe_math_optimizations
11125 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11126 rs6000_compare_op1)
11127 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11128 rs6000_compare_op1);
11132 gcc_unreachable ();
11136 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11140 cmp = flag_unsafe_math_optimizations
11141 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11142 rs6000_compare_op1)
11143 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11144 rs6000_compare_op1);
11148 cmp = flag_unsafe_math_optimizations
11149 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11150 rs6000_compare_op1)
11151 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11152 rs6000_compare_op1);
11156 gcc_unreachable ();
11160 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11164 cmp = flag_unsafe_math_optimizations
11165 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11166 rs6000_compare_op1)
11167 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11168 rs6000_compare_op1);
11172 cmp = flag_unsafe_math_optimizations
11173 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11174 rs6000_compare_op1)
11175 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11176 rs6000_compare_op1);
11180 gcc_unreachable ();
11184 gcc_unreachable ();
11187 /* Synthesize LE and GE from LT/GT || EQ. */
11188 if (code == LE || code == GE || code == LEU || code == GEU)
11194 case LE: code = LT; break;
11195 case GE: code = GT; break;
11196 case LEU: code = LT; break;
11197 case GEU: code = GT; break;
11198 default: gcc_unreachable ();
11201 compare_result2 = gen_reg_rtx (CCFPmode);
11207 cmp = flag_unsafe_math_optimizations
11208 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11209 rs6000_compare_op1)
11210 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11211 rs6000_compare_op1);
11215 cmp = flag_unsafe_math_optimizations
11216 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11217 rs6000_compare_op1)
11218 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11219 rs6000_compare_op1);
11223 gcc_unreachable ();
11227 /* OR them together. */
11228 or_result = gen_reg_rtx (CCFPmode);
11229 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11231 compare_result = or_result;
11236 if (code == NE || code == LTGT)
11246 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11247 CLOBBERs to match cmptf_internal2 pattern. */
11248 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11249 && GET_MODE (rs6000_compare_op0) == TFmode
11250 && !TARGET_IEEEQUAD
11251 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11252 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11254 gen_rtx_SET (VOIDmode,
11256 gen_rtx_COMPARE (comp_mode,
11257 rs6000_compare_op0,
11258 rs6000_compare_op1)),
11259 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11260 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11261 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11262 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11263 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11264 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11265 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11266 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11267 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11268 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11270 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11271 comp_mode = CCEQmode;
11272 compare_result = gen_reg_rtx (CCEQmode);
11274 emit_insn (gen_stack_protect_testdi (compare_result,
11275 rs6000_compare_op0, op1));
11277 emit_insn (gen_stack_protect_testsi (compare_result,
11278 rs6000_compare_op0, op1));
11281 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11282 gen_rtx_COMPARE (comp_mode,
11283 rs6000_compare_op0,
11284 rs6000_compare_op1)));
11287 /* Some kinds of FP comparisons need an OR operation;
11288 under flag_finite_math_only we don't bother. */
11289 if (rs6000_compare_fp_p
11290 && !flag_finite_math_only
11291 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11292 && (code == LE || code == GE
11293 || code == UNEQ || code == LTGT
11294 || code == UNGT || code == UNLT))
11296 enum rtx_code or1, or2;
11297 rtx or1_rtx, or2_rtx, compare2_rtx;
11298 rtx or_result = gen_reg_rtx (CCEQmode);
11302 case LE: or1 = LT; or2 = EQ; break;
11303 case GE: or1 = GT; or2 = EQ; break;
11304 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11305 case LTGT: or1 = LT; or2 = GT; break;
11306 case UNGT: or1 = UNORDERED; or2 = GT; break;
11307 case UNLT: or1 = UNORDERED; or2 = LT; break;
11308 default: gcc_unreachable ();
11310 validate_condition_mode (or1, comp_mode);
11311 validate_condition_mode (or2, comp_mode);
11312 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11313 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11314 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11315 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11317 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11319 compare_result = or_result;
11323 validate_condition_mode (code, GET_MODE (compare_result));
11325 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11329 /* Emit the RTL for an sCOND pattern. */
11332 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11335 enum machine_mode op_mode;
11336 enum rtx_code cond_code;
11338 condition_rtx = rs6000_generate_compare (code);
11339 cond_code = GET_CODE (condition_rtx);
11341 if (TARGET_E500 && rs6000_compare_fp_p
11342 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11346 PUT_MODE (condition_rtx, SImode);
11347 t = XEXP (condition_rtx, 0);
11349 gcc_assert (cond_code == NE || cond_code == EQ);
11351 if (cond_code == NE)
11352 emit_insn (gen_e500_flip_gt_bit (t, t));
11354 emit_insn (gen_move_from_CR_gt_bit (result, t));
11358 if (cond_code == NE
11359 || cond_code == GE || cond_code == LE
11360 || cond_code == GEU || cond_code == LEU
11361 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11363 rtx not_result = gen_reg_rtx (CCEQmode);
11364 rtx not_op, rev_cond_rtx;
11365 enum machine_mode cc_mode;
11367 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11369 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11370 SImode, XEXP (condition_rtx, 0), const0_rtx);
11371 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11372 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11373 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11376 op_mode = GET_MODE (rs6000_compare_op0);
11377 if (op_mode == VOIDmode)
11378 op_mode = GET_MODE (rs6000_compare_op1);
11380 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11382 PUT_MODE (condition_rtx, DImode);
11383 convert_move (result, condition_rtx, 0);
11387 PUT_MODE (condition_rtx, SImode);
11388 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11392 /* Emit a branch of kind CODE to location LOC. */
11395 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11397 rtx condition_rtx, loc_ref;
11399 condition_rtx = rs6000_generate_compare (code);
11400 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11401 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11402 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11403 loc_ref, pc_rtx)));
11406 /* Return the string to output a conditional branch to LABEL, which is
11407 the operand number of the label, or -1 if the branch is really a
11408 conditional return.
11410 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11411 condition code register and its mode specifies what kind of
11412 comparison we made.
11414 REVERSED is nonzero if we should reverse the sense of the comparison.
11416 INSN is the insn. */
11419 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11421 static char string[64];
11422 enum rtx_code code = GET_CODE (op);
11423 rtx cc_reg = XEXP (op, 0);
11424 enum machine_mode mode = GET_MODE (cc_reg);
11425 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11426 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11427 int really_reversed = reversed ^ need_longbranch;
11433 validate_condition_mode (code, mode);
11435 /* Work out which way this really branches. We could use
11436 reverse_condition_maybe_unordered here always but this
11437 makes the resulting assembler clearer. */
11438 if (really_reversed)
11440 /* Reversal of FP compares takes care -- an ordered compare
11441 becomes an unordered compare and vice versa. */
11442 if (mode == CCFPmode)
11443 code = reverse_condition_maybe_unordered (code);
11445 code = reverse_condition (code);
11448 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11450 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11455 /* Opposite of GT. */
11464 gcc_unreachable ();
11470 /* Not all of these are actually distinct opcodes, but
11471 we distinguish them for clarity of the resulting assembler. */
11472 case NE: case LTGT:
11473 ccode = "ne"; break;
11474 case EQ: case UNEQ:
11475 ccode = "eq"; break;
11477 ccode = "ge"; break;
11478 case GT: case GTU: case UNGT:
11479 ccode = "gt"; break;
11481 ccode = "le"; break;
11482 case LT: case LTU: case UNLT:
11483 ccode = "lt"; break;
11484 case UNORDERED: ccode = "un"; break;
11485 case ORDERED: ccode = "nu"; break;
11486 case UNGE: ccode = "nl"; break;
11487 case UNLE: ccode = "ng"; break;
11489 gcc_unreachable ();
11492 /* Maybe we have a guess as to how likely the branch is.
11493 The old mnemonics don't have a way to specify this information. */
11495 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11496 if (note != NULL_RTX)
11498 /* PROB is the difference from 50%. */
11499 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11501 /* Only hint for highly probable/improbable branches on newer
11502 cpus as static prediction overrides processor dynamic
11503 prediction. For older cpus we may as well always hint, but
11504 assume not taken for branches that are very close to 50% as a
11505 mispredicted taken branch is more expensive than a
11506 mispredicted not-taken branch. */
11507 if (rs6000_always_hint
11508 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
11509 && br_prob_note_reliable_p (note)))
11511 if (abs (prob) > REG_BR_PROB_BASE / 20
11512 && ((prob > 0) ^ need_longbranch))
11520 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11522 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11524 /* We need to escape any '%' characters in the reg_names string.
11525 Assume they'd only be the first character.... */
11526 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11528 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11532 /* If the branch distance was too far, we may have to use an
11533 unconditional branch to go the distance. */
11534 if (need_longbranch)
11535 s += sprintf (s, ",$+8\n\tb %s", label);
11537 s += sprintf (s, ",%s", label);
11543 /* Return the string to flip the GT bit on a CR. */
11545 output_e500_flip_gt_bit (rtx dst, rtx src)
11547 static char string[64];
11550 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
11551 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
11554 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
11555 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
11557 sprintf (string, "crnot %d,%d", a, b);
11561 /* Return insn index for the vector compare instruction for given CODE,
11562 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11566 get_vec_cmp_insn (enum rtx_code code,
11567 enum machine_mode dest_mode,
11568 enum machine_mode op_mode)
11570 if (!TARGET_ALTIVEC)
11571 return INSN_NOT_AVAILABLE;
11576 if (dest_mode == V16QImode && op_mode == V16QImode)
11577 return UNSPEC_VCMPEQUB;
11578 if (dest_mode == V8HImode && op_mode == V8HImode)
11579 return UNSPEC_VCMPEQUH;
11580 if (dest_mode == V4SImode && op_mode == V4SImode)
11581 return UNSPEC_VCMPEQUW;
11582 if (dest_mode == V4SImode && op_mode == V4SFmode)
11583 return UNSPEC_VCMPEQFP;
11586 if (dest_mode == V4SImode && op_mode == V4SFmode)
11587 return UNSPEC_VCMPGEFP;
11589 if (dest_mode == V16QImode && op_mode == V16QImode)
11590 return UNSPEC_VCMPGTSB;
11591 if (dest_mode == V8HImode && op_mode == V8HImode)
11592 return UNSPEC_VCMPGTSH;
11593 if (dest_mode == V4SImode && op_mode == V4SImode)
11594 return UNSPEC_VCMPGTSW;
11595 if (dest_mode == V4SImode && op_mode == V4SFmode)
11596 return UNSPEC_VCMPGTFP;
11599 if (dest_mode == V16QImode && op_mode == V16QImode)
11600 return UNSPEC_VCMPGTUB;
11601 if (dest_mode == V8HImode && op_mode == V8HImode)
11602 return UNSPEC_VCMPGTUH;
11603 if (dest_mode == V4SImode && op_mode == V4SImode)
11604 return UNSPEC_VCMPGTUW;
11609 return INSN_NOT_AVAILABLE;
11612 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11613 DMODE is expected destination mode. This is a recursive function. */
11616 rs6000_emit_vector_compare (enum rtx_code rcode,
11618 enum machine_mode dmode)
11622 enum machine_mode dest_mode;
11623 enum machine_mode op_mode = GET_MODE (op1);
11625 gcc_assert (TARGET_ALTIVEC);
11626 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
11628 /* Floating point vector compare instructions uses destination V4SImode.
11629 Move destination to appropriate mode later. */
11630 if (dmode == V4SFmode)
11631 dest_mode = V4SImode;
11635 mask = gen_reg_rtx (dest_mode);
11636 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11638 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11640 bool swap_operands = false;
11641 bool try_again = false;
11646 swap_operands = true;
11651 swap_operands = true;
11655 /* Treat A != B as ~(A==B). */
11657 enum insn_code nor_code;
11658 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11661 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11662 gcc_assert (nor_code != CODE_FOR_nothing);
11663 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11665 if (dmode != dest_mode)
11667 rtx temp = gen_reg_rtx (dest_mode);
11668 convert_move (temp, mask, 0);
11678 /* Try GT/GTU/LT/LTU OR EQ */
11681 enum insn_code ior_code;
11682 enum rtx_code new_code;
11703 gcc_unreachable ();
11706 c_rtx = rs6000_emit_vector_compare (new_code,
11707 op0, op1, dest_mode);
11708 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11711 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11712 gcc_assert (ior_code != CODE_FOR_nothing);
11713 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11714 if (dmode != dest_mode)
11716 rtx temp = gen_reg_rtx (dest_mode);
11717 convert_move (temp, mask, 0);
11724 gcc_unreachable ();
11729 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11730 /* You only get two chances. */
11731 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
11743 emit_insn (gen_rtx_SET (VOIDmode, mask,
11744 gen_rtx_UNSPEC (dest_mode,
11745 gen_rtvec (2, op0, op1),
11747 if (dmode != dest_mode)
11749 rtx temp = gen_reg_rtx (dest_mode);
11750 convert_move (temp, mask, 0);
11756 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11757 valid insn doesn exist for given mode. */
11760 get_vsel_insn (enum machine_mode mode)
11765 return UNSPEC_VSEL4SI;
11768 return UNSPEC_VSEL4SF;
11771 return UNSPEC_VSEL8HI;
11774 return UNSPEC_VSEL16QI;
11777 return INSN_NOT_AVAILABLE;
11780 return INSN_NOT_AVAILABLE;
11783 /* Emit vector select insn where DEST is destination using
11784 operands OP1, OP2 and MASK. */
11787 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11790 enum machine_mode dest_mode = GET_MODE (dest);
11791 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11793 temp = gen_reg_rtx (dest_mode);
11795 /* For each vector element, select op1 when mask is 1 otherwise
11797 t = gen_rtx_SET (VOIDmode, temp,
11798 gen_rtx_UNSPEC (dest_mode,
11799 gen_rtvec (3, op2, op1, mask),
11802 emit_move_insn (dest, temp);
11806 /* Emit vector conditional expression.
11807 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11808 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11811 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11812 rtx cond, rtx cc_op0, rtx cc_op1)
11814 enum machine_mode dest_mode = GET_MODE (dest);
11815 enum rtx_code rcode = GET_CODE (cond);
11818 if (!TARGET_ALTIVEC)
11821 /* Get the vector mask for the given relational operations. */
11822 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11824 rs6000_emit_vector_select (dest, op1, op2, mask);
11829 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11830 operands of the last comparison is nonzero/true, FALSE_COND if it
11831 is zero/false. Return 0 if the hardware has no such operation. */
11834 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11836 enum rtx_code code = GET_CODE (op);
11837 rtx op0 = rs6000_compare_op0;
11838 rtx op1 = rs6000_compare_op1;
11839 REAL_VALUE_TYPE c1;
11840 enum machine_mode compare_mode = GET_MODE (op0);
11841 enum machine_mode result_mode = GET_MODE (dest);
11843 bool is_against_zero;
11845 /* These modes should always match. */
11846 if (GET_MODE (op1) != compare_mode
11847 /* In the isel case however, we can use a compare immediate, so
11848 op1 may be a small constant. */
11849 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11851 if (GET_MODE (true_cond) != result_mode)
11853 if (GET_MODE (false_cond) != result_mode)
11856 /* First, work out if the hardware can do this at all, or
11857 if it's too slow.... */
11858 if (! rs6000_compare_fp_p)
11861 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11864 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11865 && SCALAR_FLOAT_MODE_P (compare_mode))
11868 is_against_zero = op1 == CONST0_RTX (compare_mode);
11870 /* A floating-point subtract might overflow, underflow, or produce
11871 an inexact result, thus changing the floating-point flags, so it
11872 can't be generated if we care about that. It's safe if one side
11873 of the construct is zero, since then no subtract will be
11875 if (SCALAR_FLOAT_MODE_P (compare_mode)
11876 && flag_trapping_math && ! is_against_zero)
11879 /* Eliminate half of the comparisons by switching operands, this
11880 makes the remaining code simpler. */
11881 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
11882 || code == LTGT || code == LT || code == UNLE)
11884 code = reverse_condition_maybe_unordered (code);
11886 true_cond = false_cond;
11890 /* UNEQ and LTGT take four instructions for a comparison with zero,
11891 it'll probably be faster to use a branch here too. */
11892 if (code == UNEQ && HONOR_NANS (compare_mode))
11895 if (GET_CODE (op1) == CONST_DOUBLE)
11896 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
11898 /* We're going to try to implement comparisons by performing
11899 a subtract, then comparing against zero. Unfortunately,
11900 Inf - Inf is NaN which is not zero, and so if we don't
11901 know that the operand is finite and the comparison
11902 would treat EQ different to UNORDERED, we can't do it. */
11903 if (HONOR_INFINITIES (compare_mode)
11904 && code != GT && code != UNGE
11905 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
11906 /* Constructs of the form (a OP b ? a : b) are safe. */
11907 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
11908 || (! rtx_equal_p (op0, true_cond)
11909 && ! rtx_equal_p (op1, true_cond))))
11912 /* At this point we know we can use fsel. */
11914 /* Reduce the comparison to a comparison against zero. */
11915 if (! is_against_zero)
11917 temp = gen_reg_rtx (compare_mode);
11918 emit_insn (gen_rtx_SET (VOIDmode, temp,
11919 gen_rtx_MINUS (compare_mode, op0, op1)));
11921 op1 = CONST0_RTX (compare_mode);
11924 /* If we don't care about NaNs we can reduce some of the comparisons
11925 down to faster ones. */
11926 if (! HONOR_NANS (compare_mode))
11932 true_cond = false_cond;
11945 /* Now, reduce everything down to a GE. */
11952 temp = gen_reg_rtx (compare_mode);
11953 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11958 temp = gen_reg_rtx (compare_mode);
11959 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
11964 temp = gen_reg_rtx (compare_mode);
11965 emit_insn (gen_rtx_SET (VOIDmode, temp,
11966 gen_rtx_NEG (compare_mode,
11967 gen_rtx_ABS (compare_mode, op0))));
11972 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
11973 temp = gen_reg_rtx (result_mode);
11974 emit_insn (gen_rtx_SET (VOIDmode, temp,
11975 gen_rtx_IF_THEN_ELSE (result_mode,
11976 gen_rtx_GE (VOIDmode,
11978 true_cond, false_cond)));
11979 false_cond = true_cond;
11982 temp = gen_reg_rtx (compare_mode);
11983 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11988 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
11989 temp = gen_reg_rtx (result_mode);
11990 emit_insn (gen_rtx_SET (VOIDmode, temp,
11991 gen_rtx_IF_THEN_ELSE (result_mode,
11992 gen_rtx_GE (VOIDmode,
11994 true_cond, false_cond)));
11995 true_cond = false_cond;
11998 temp = gen_reg_rtx (compare_mode);
11999 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12004 gcc_unreachable ();
12007 emit_insn (gen_rtx_SET (VOIDmode, dest,
12008 gen_rtx_IF_THEN_ELSE (result_mode,
12009 gen_rtx_GE (VOIDmode,
12011 true_cond, false_cond)));
12015 /* Same as above, but for ints (isel). */
12018 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12020 rtx condition_rtx, cr;
12022 /* All isel implementations thus far are 32-bits. */
12023 if (GET_MODE (rs6000_compare_op0) != SImode)
12026 /* We still have to do the compare, because isel doesn't do a
12027 compare, it just looks at the CRx bits set by a previous compare
12029 condition_rtx = rs6000_generate_compare (GET_CODE (op));
12030 cr = XEXP (condition_rtx, 0);
12032 if (GET_MODE (cr) == CCmode)
12033 emit_insn (gen_isel_signed (dest, condition_rtx,
12034 true_cond, false_cond, cr));
12036 emit_insn (gen_isel_unsigned (dest, condition_rtx,
12037 true_cond, false_cond, cr));
12043 output_isel (rtx *operands)
12045 enum rtx_code code;
12047 code = GET_CODE (operands[1]);
12048 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
12050 PUT_CODE (operands[1], reverse_condition (code));
12051 return "isel %0,%3,%2,%j1";
12054 return "isel %0,%2,%3,%j1";
12058 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
12060 enum machine_mode mode = GET_MODE (op0);
12064 if (code == SMAX || code == SMIN)
12069 if (code == SMAX || code == UMAX)
12070 target = emit_conditional_move (dest, c, op0, op1, mode,
12071 op0, op1, mode, 0);
12073 target = emit_conditional_move (dest, c, op0, op1, mode,
12074 op1, op0, mode, 0);
12075 gcc_assert (target);
12076 if (target != dest)
12077 emit_move_insn (dest, target);
12080 /* Emit instructions to perform a load-reserved/store-conditional operation.
12081 The operation performed is an atomic
12082 (set M (CODE:MODE M OP))
12083 If not NULL, BEFORE is atomically set to M before the operation, and
12084 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
12085 If SYNC_P then a memory barrier is emitted before the operation.
12086 Either OP or M may be wrapped in a NOT operation. */
12089 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
12090 rtx m, rtx op, rtx before_param, rtx after_param,
12093 enum machine_mode used_mode;
12094 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
12097 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12098 rtx shift = NULL_RTX;
12101 emit_insn (gen_memory_barrier ());
12103 if (GET_CODE (m) == NOT)
12104 used_m = XEXP (m, 0);
12108 /* If this is smaller than SImode, we'll have to use SImode with
12110 if (mode == QImode || mode == HImode)
12114 if (MEM_ALIGN (used_m) >= 32)
12117 if (BYTES_BIG_ENDIAN)
12118 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
12120 shift = GEN_INT (ishift);
12124 rtx addrSI, aligned_addr;
12125 int shift_mask = mode == QImode ? 0x18 : 0x10;
12127 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
12128 XEXP (used_m, 0)));
12129 shift = gen_reg_rtx (SImode);
12131 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12132 GEN_INT (shift_mask)));
12133 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12135 aligned_addr = expand_binop (Pmode, and_optab,
12137 GEN_INT (-4), NULL_RTX,
12138 1, OPTAB_LIB_WIDEN);
12139 used_m = change_address (used_m, SImode, aligned_addr);
12140 set_mem_align (used_m, 32);
12141 /* It's safe to keep the old alias set of USED_M, because
12142 the operation is atomic and only affects the original
12144 if (GET_CODE (m) == NOT)
12145 m = gen_rtx_NOT (SImode, used_m);
12150 if (GET_CODE (op) == NOT)
12152 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12153 oldop = gen_rtx_NOT (SImode, oldop);
12156 oldop = lowpart_subreg (SImode, op, mode);
12162 newop = expand_binop (SImode, and_optab,
12163 oldop, GEN_INT (imask), NULL_RTX,
12164 1, OPTAB_LIB_WIDEN);
12165 emit_insn (gen_ashlsi3 (newop, newop, shift));
12169 newop = expand_binop (SImode, ior_optab,
12170 oldop, GEN_INT (~imask), NULL_RTX,
12171 1, OPTAB_LIB_WIDEN);
12172 emit_insn (gen_rotlsi3 (newop, newop, shift));
12180 newop = expand_binop (SImode, and_optab,
12181 oldop, GEN_INT (imask), NULL_RTX,
12182 1, OPTAB_LIB_WIDEN);
12183 emit_insn (gen_ashlsi3 (newop, newop, shift));
12185 mask = gen_reg_rtx (SImode);
12186 emit_move_insn (mask, GEN_INT (imask));
12187 emit_insn (gen_ashlsi3 (mask, mask, shift));
12190 newop = gen_rtx_PLUS (SImode, m, newop);
12192 newop = gen_rtx_MINUS (SImode, m, newop);
12193 newop = gen_rtx_AND (SImode, newop, mask);
12194 newop = gen_rtx_IOR (SImode, newop,
12195 gen_rtx_AND (SImode,
12196 gen_rtx_NOT (SImode, mask),
12202 gcc_unreachable ();
12205 if (GET_CODE (m) == NOT)
12209 mask = gen_reg_rtx (SImode);
12210 emit_move_insn (mask, GEN_INT (imask));
12211 emit_insn (gen_ashlsi3 (mask, mask, shift));
12213 xorm = gen_rtx_XOR (SImode, used_m, mask);
12214 /* Depending on the value of 'op', the XOR or the operation might
12215 be able to be simplified away. */
12216 newop = simplify_gen_binary (code, SImode, xorm, newop);
12219 used_mode = SImode;
12220 before = gen_reg_rtx (used_mode);
12221 after = gen_reg_rtx (used_mode);
12226 before = before_param;
12227 after = after_param;
12229 if (before == NULL_RTX)
12230 before = gen_reg_rtx (used_mode);
12231 if (after == NULL_RTX)
12232 after = gen_reg_rtx (used_mode);
12235 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12236 && used_mode != mode)
12237 the_op = op; /* Computed above. */
12238 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12239 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12241 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12243 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12244 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12245 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12246 gen_rtx_UNSPEC (used_mode,
12247 gen_rtvec (1, the_op),
12249 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12251 if ((code == PLUS || code == MINUS) && used_mode != mode)
12252 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12253 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12255 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12256 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12258 /* Shift and mask the return values properly. */
12259 if (used_mode != mode && before_param)
12261 emit_insn (gen_lshrsi3 (before, before, shift));
12262 convert_move (before_param, before, 1);
12265 if (used_mode != mode && after_param)
12267 emit_insn (gen_lshrsi3 (after, after, shift));
12268 convert_move (after_param, after, 1);
12271 /* The previous sequence will end with a branch that's dependent on
12272 the conditional store, so placing an isync will ensure that no
12273 other instructions (especially, no load or store instructions)
12274 can start before the atomic operation completes. */
12276 emit_insn (gen_isync ());
12279 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12280 COND is true. Mark the jump as unlikely to be taken. */
12283 emit_unlikely_jump (rtx cond, rtx label)
12285 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12288 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12289 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12290 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12293 /* A subroutine of the atomic operation splitters. Emit a load-locked
12294 instruction in MODE. */
12297 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12299 rtx (*fn) (rtx, rtx) = NULL;
12300 if (mode == SImode)
12301 fn = gen_load_locked_si;
12302 else if (mode == DImode)
12303 fn = gen_load_locked_di;
12304 emit_insn (fn (reg, mem));
12307 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12308 instruction in MODE. */
12311 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12313 rtx (*fn) (rtx, rtx, rtx) = NULL;
12314 if (mode == SImode)
12315 fn = gen_store_conditional_si;
12316 else if (mode == DImode)
12317 fn = gen_store_conditional_di;
12319 /* Emit sync before stwcx. to address PPC405 Erratum. */
12320 if (PPC405_ERRATUM77)
12321 emit_insn (gen_memory_barrier ());
12323 emit_insn (fn (res, mem, val));
12326 /* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation
12327 to perform. MEM is the memory on which to operate. VAL is the second
12328 operand of the binary operator. BEFORE and AFTER are optional locations to
12329 return the value of MEM either before of after the operation. SCRATCH is
12330 a scratch register. */
12333 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12334 rtx before, rtx after, rtx scratch)
12336 enum machine_mode mode = GET_MODE (mem);
12337 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12339 emit_insn (gen_memory_barrier ());
12341 label = gen_label_rtx ();
12342 emit_label (label);
12343 label = gen_rtx_LABEL_REF (VOIDmode, label);
12345 if (before == NULL_RTX)
12347 emit_load_locked (mode, before, mem);
12350 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12351 else if (code == AND)
12352 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12354 x = gen_rtx_fmt_ee (code, mode, before, val);
12356 if (after != NULL_RTX)
12357 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12358 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12360 emit_store_conditional (mode, cond, mem, scratch);
12362 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12363 emit_unlikely_jump (x, label);
12365 emit_insn (gen_isync ());
12368 /* Expand an atomic compare and swap operation. MEM is the memory on which
12369 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12370 value to be stored. SCRATCH is a scratch GPR. */
12373 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12376 enum machine_mode mode = GET_MODE (mem);
12377 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12379 emit_insn (gen_memory_barrier ());
12381 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12382 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12383 emit_label (XEXP (label1, 0));
12385 emit_load_locked (mode, retval, mem);
12387 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12388 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12390 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12391 emit_unlikely_jump (x, label2);
12393 emit_move_insn (scratch, newval);
12394 emit_store_conditional (mode, cond, mem, scratch);
12396 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12397 emit_unlikely_jump (x, label1);
12399 emit_insn (gen_isync ());
12400 emit_label (XEXP (label2, 0));
12403 /* Expand an atomic test and set operation. MEM is the memory on which
12404 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12407 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
12409 enum machine_mode mode = GET_MODE (mem);
12410 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12412 emit_insn (gen_memory_barrier ());
12414 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12415 emit_label (XEXP (label, 0));
12417 emit_load_locked (mode, retval, mem);
12418 emit_move_insn (scratch, val);
12419 emit_store_conditional (mode, cond, mem, scratch);
12421 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12422 emit_unlikely_jump (x, label);
12424 emit_insn (gen_isync ());
12428 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
12430 enum machine_mode mode = GET_MODE (mem);
12431 rtx addrSI, align, wdst, shift, mask;
12432 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
12433 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12435 /* Shift amount for subword relative to aligned word. */
12436 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
12437 shift = gen_reg_rtx (SImode);
12438 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12439 GEN_INT (shift_mask)));
12440 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12442 /* Shift and mask old value into position within word. */
12443 oldval = convert_modes (SImode, mode, oldval, 1);
12444 oldval = expand_binop (SImode, and_optab,
12445 oldval, GEN_INT (imask), NULL_RTX,
12446 1, OPTAB_LIB_WIDEN);
12447 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
12449 /* Shift and mask new value into position within word. */
12450 newval = convert_modes (SImode, mode, newval, 1);
12451 newval = expand_binop (SImode, and_optab,
12452 newval, GEN_INT (imask), NULL_RTX,
12453 1, OPTAB_LIB_WIDEN);
12454 emit_insn (gen_ashlsi3 (newval, newval, shift));
12456 /* Mask for insertion. */
12457 mask = gen_reg_rtx (SImode);
12458 emit_move_insn (mask, GEN_INT (imask));
12459 emit_insn (gen_ashlsi3 (mask, mask, shift));
12461 /* Address of aligned word containing subword. */
12462 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
12463 NULL_RTX, 1, OPTAB_LIB_WIDEN);
12464 mem = change_address (mem, SImode, align);
12465 set_mem_align (mem, 32);
12466 MEM_VOLATILE_P (mem) = 1;
12468 wdst = gen_reg_rtx (SImode);
12469 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
12470 oldval, newval, mem));
12472 emit_move_insn (dst, gen_lowpart (mode, wdst));
12476 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
12477 rtx oldval, rtx newval, rtx mem,
12480 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12482 emit_insn (gen_memory_barrier ());
12483 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12484 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12485 emit_label (XEXP (label1, 0));
12487 emit_load_locked (SImode, scratch, mem);
12489 /* Mask subword within loaded value for comparison with oldval.
12490 Use UNSPEC_AND to avoid clobber.*/
12491 emit_insn (gen_rtx_SET (SImode, dest,
12492 gen_rtx_UNSPEC (SImode,
12493 gen_rtvec (2, scratch, mask),
12496 x = gen_rtx_COMPARE (CCmode, dest, oldval);
12497 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12499 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12500 emit_unlikely_jump (x, label2);
12502 /* Clear subword within loaded value for insertion of new value. */
12503 emit_insn (gen_rtx_SET (SImode, scratch,
12504 gen_rtx_AND (SImode,
12505 gen_rtx_NOT (SImode, mask), scratch)));
12506 emit_insn (gen_iorsi3 (scratch, scratch, newval));
12507 emit_store_conditional (SImode, cond, mem, scratch);
12509 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12510 emit_unlikely_jump (x, label1);
12512 emit_insn (gen_isync ());
12513 emit_label (XEXP (label2, 0));
12517 /* Emit instructions to move SRC to DST. Called by splitters for
12518 multi-register moves. It will emit at most one instruction for
12519 each register that is accessed; that is, it won't emit li/lis pairs
12520 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12524 rs6000_split_multireg_move (rtx dst, rtx src)
12526 /* The register number of the first register being moved. */
12528 /* The mode that is to be moved. */
12529 enum machine_mode mode;
12530 /* The mode that the move is being done in, and its size. */
12531 enum machine_mode reg_mode;
12533 /* The number of registers that will be moved. */
12536 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12537 mode = GET_MODE (dst);
12538 nregs = hard_regno_nregs[reg][mode];
12539 if (FP_REGNO_P (reg))
12541 else if (ALTIVEC_REGNO_P (reg))
12542 reg_mode = V16QImode;
12544 reg_mode = word_mode;
12545 reg_mode_size = GET_MODE_SIZE (reg_mode);
12547 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
12549 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12551 /* Move register range backwards, if we might have destructive
12554 for (i = nregs - 1; i >= 0; i--)
12555 emit_insn (gen_rtx_SET (VOIDmode,
12556 simplify_gen_subreg (reg_mode, dst, mode,
12557 i * reg_mode_size),
12558 simplify_gen_subreg (reg_mode, src, mode,
12559 i * reg_mode_size)));
12565 bool used_update = false;
12567 if (MEM_P (src) && INT_REGNO_P (reg))
12571 if (GET_CODE (XEXP (src, 0)) == PRE_INC
12572 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
12575 breg = XEXP (XEXP (src, 0), 0);
12576 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
12577 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
12578 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
12579 emit_insn (TARGET_32BIT
12580 ? gen_addsi3 (breg, breg, delta_rtx)
12581 : gen_adddi3 (breg, breg, delta_rtx));
12582 src = replace_equiv_address (src, breg);
12584 else if (! rs6000_offsettable_memref_p (src))
12587 basereg = gen_rtx_REG (Pmode, reg);
12588 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
12589 src = replace_equiv_address (src, basereg);
12592 breg = XEXP (src, 0);
12593 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
12594 breg = XEXP (breg, 0);
12596 /* If the base register we are using to address memory is
12597 also a destination reg, then change that register last. */
12599 && REGNO (breg) >= REGNO (dst)
12600 && REGNO (breg) < REGNO (dst) + nregs)
12601 j = REGNO (breg) - REGNO (dst);
12604 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
12608 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
12609 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
12612 breg = XEXP (XEXP (dst, 0), 0);
12613 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
12614 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
12615 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
12617 /* We have to update the breg before doing the store.
12618 Use store with update, if available. */
12622 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
12623 emit_insn (TARGET_32BIT
12624 ? (TARGET_POWERPC64
12625 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
12626 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
12627 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
12628 used_update = true;
12631 emit_insn (TARGET_32BIT
12632 ? gen_addsi3 (breg, breg, delta_rtx)
12633 : gen_adddi3 (breg, breg, delta_rtx));
12634 dst = replace_equiv_address (dst, breg);
12637 gcc_assert (rs6000_offsettable_memref_p (dst));
12640 for (i = 0; i < nregs; i++)
12642 /* Calculate index to next subword. */
12647 /* If compiler already emitted move of first word by
12648 store with update, no need to do anything. */
12649 if (j == 0 && used_update)
12652 emit_insn (gen_rtx_SET (VOIDmode,
12653 simplify_gen_subreg (reg_mode, dst, mode,
12654 j * reg_mode_size),
12655 simplify_gen_subreg (reg_mode, src, mode,
12656 j * reg_mode_size)));
12662 /* This page contains routines that are used to determine what the
12663 function prologue and epilogue code will do and write them out. */
12665 /* Return the first fixed-point register that is required to be
12666 saved. 32 if none. */
12669 first_reg_to_save (void)
12673 /* Find lowest numbered live register. */
12674 for (first_reg = 13; first_reg <= 31; first_reg++)
12675 if (regs_ever_live[first_reg]
12676 && (! call_used_regs[first_reg]
12677 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12678 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12679 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12680 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12685 && current_function_uses_pic_offset_table
12686 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12687 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12693 /* Similar, for FP regs. */
12696 first_fp_reg_to_save (void)
12700 /* Find lowest numbered live register. */
12701 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12702 if (regs_ever_live[first_reg])
12708 /* Similar, for AltiVec regs. */
12711 first_altivec_reg_to_save (void)
12715 /* Stack frame remains as is unless we are in AltiVec ABI. */
12716 if (! TARGET_ALTIVEC_ABI)
12717 return LAST_ALTIVEC_REGNO + 1;
12719 /* Find lowest numbered live register. */
12720 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12721 if (regs_ever_live[i])
12727 /* Return a 32-bit mask of the AltiVec registers we need to set in
12728 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12729 the 32-bit word is 0. */
12731 static unsigned int
12732 compute_vrsave_mask (void)
12734 unsigned int i, mask = 0;
12736 /* First, find out if we use _any_ altivec registers. */
12737 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12738 if (regs_ever_live[i])
12739 mask |= ALTIVEC_REG_BIT (i);
12744 /* Next, remove the argument registers from the set. These must
12745 be in the VRSAVE mask set by the caller, so we don't need to add
12746 them in again. More importantly, the mask we compute here is
12747 used to generate CLOBBERs in the set_vrsave insn, and we do not
12748 wish the argument registers to die. */
12749 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12750 mask &= ~ALTIVEC_REG_BIT (i);
12752 /* Similarly, remove the return value from the set. */
12755 diddle_return_value (is_altivec_return_reg, &yes);
12757 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12763 /* For a very restricted set of circumstances, we can cut down the
12764 size of prologues/epilogues by calling our own save/restore-the-world
12768 compute_save_world_info (rs6000_stack_t *info_ptr)
12770 info_ptr->world_save_p = 1;
12771 info_ptr->world_save_p
12772 = (WORLD_SAVE_P (info_ptr)
12773 && DEFAULT_ABI == ABI_DARWIN
12774 && ! (current_function_calls_setjmp && flag_exceptions)
12775 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12776 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12777 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12778 && info_ptr->cr_save_p);
12780 /* This will not work in conjunction with sibcalls. Make sure there
12781 are none. (This check is expensive, but seldom executed.) */
12782 if (WORLD_SAVE_P (info_ptr))
12785 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12786 if ( GET_CODE (insn) == CALL_INSN
12787 && SIBLING_CALL_P (insn))
12789 info_ptr->world_save_p = 0;
12794 if (WORLD_SAVE_P (info_ptr))
12796 /* Even if we're not touching VRsave, make sure there's room on the
12797 stack for it, if it looks like we're calling SAVE_WORLD, which
12798 will attempt to save it. */
12799 info_ptr->vrsave_size = 4;
12801 /* "Save" the VRsave register too if we're saving the world. */
12802 if (info_ptr->vrsave_mask == 0)
12803 info_ptr->vrsave_mask = compute_vrsave_mask ();
12805 /* Because the Darwin register save/restore routines only handle
12806 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12808 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
12809 && (info_ptr->first_altivec_reg_save
12810 >= FIRST_SAVED_ALTIVEC_REGNO));
12817 is_altivec_return_reg (rtx reg, void *xyes)
12819 bool *yes = (bool *) xyes;
12820 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
12825 /* Calculate the stack information for the current function. This is
12826 complicated by having two separate calling sequences, the AIX calling
12827 sequence and the V.4 calling sequence.
12829 AIX (and Darwin/Mac OS X) stack frames look like:
12831 SP----> +---------------------------------------+
12832 | back chain to caller | 0 0
12833 +---------------------------------------+
12834 | saved CR | 4 8 (8-11)
12835 +---------------------------------------+
12837 +---------------------------------------+
12838 | reserved for compilers | 12 24
12839 +---------------------------------------+
12840 | reserved for binders | 16 32
12841 +---------------------------------------+
12842 | saved TOC pointer | 20 40
12843 +---------------------------------------+
12844 | Parameter save area (P) | 24 48
12845 +---------------------------------------+
12846 | Alloca space (A) | 24+P etc.
12847 +---------------------------------------+
12848 | Local variable space (L) | 24+P+A
12849 +---------------------------------------+
12850 | Float/int conversion temporary (X) | 24+P+A+L
12851 +---------------------------------------+
12852 | Save area for AltiVec registers (W) | 24+P+A+L+X
12853 +---------------------------------------+
12854 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12855 +---------------------------------------+
12856 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12857 +---------------------------------------+
12858 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12859 +---------------------------------------+
12860 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12861 +---------------------------------------+
12862 old SP->| back chain to caller's caller |
12863 +---------------------------------------+
12865 The required alignment for AIX configurations is two words (i.e., 8
12869 V.4 stack frames look like:
12871 SP----> +---------------------------------------+
12872 | back chain to caller | 0
12873 +---------------------------------------+
12874 | caller's saved LR | 4
12875 +---------------------------------------+
12876 | Parameter save area (P) | 8
12877 +---------------------------------------+
12878 | Alloca space (A) | 8+P
12879 +---------------------------------------+
12880 | Varargs save area (V) | 8+P+A
12881 +---------------------------------------+
12882 | Local variable space (L) | 8+P+A+V
12883 +---------------------------------------+
12884 | Float/int conversion temporary (X) | 8+P+A+V+L
12885 +---------------------------------------+
12886 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12887 +---------------------------------------+
12888 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12889 +---------------------------------------+
12890 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12891 +---------------------------------------+
12892 | SPE: area for 64-bit GP registers |
12893 +---------------------------------------+
12894 | SPE alignment padding |
12895 +---------------------------------------+
12896 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12897 +---------------------------------------+
12898 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12899 +---------------------------------------+
12900 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12901 +---------------------------------------+
12902 old SP->| back chain to caller's caller |
12903 +---------------------------------------+
12905 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12906 given. (But note below and in sysv4.h that we require only 8 and
12907 may round up the size of our stack frame anyways. The historical
12908 reason is early versions of powerpc-linux which didn't properly
12909 align the stack at program startup. A happy side-effect is that
12910 -mno-eabi libraries can be used with -meabi programs.)
12912 The EABI configuration defaults to the V.4 layout. However,
12913 the stack alignment requirements may differ. If -mno-eabi is not
12914 given, the required stack alignment is 8 bytes; if -mno-eabi is
12915 given, the required alignment is 16 bytes. (But see V.4 comment
12918 #ifndef ABI_STACK_BOUNDARY
12919 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12922 static rs6000_stack_t *
12923 rs6000_stack_info (void)
12925 static rs6000_stack_t info;
12926 rs6000_stack_t *info_ptr = &info;
12927 int reg_size = TARGET_32BIT ? 4 : 8;
12930 HOST_WIDE_INT non_fixed_size;
12932 memset (&info, 0, sizeof (info));
12936 /* Cache value so we don't rescan instruction chain over and over. */
12937 if (cfun->machine->insn_chain_scanned_p == 0)
12938 cfun->machine->insn_chain_scanned_p
12939 = spe_func_has_64bit_regs_p () + 1;
12940 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
12943 /* Select which calling sequence. */
12944 info_ptr->abi = DEFAULT_ABI;
12946 /* Calculate which registers need to be saved & save area size. */
12947 info_ptr->first_gp_reg_save = first_reg_to_save ();
12948 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12949 even if it currently looks like we won't. */
12950 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
12951 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12952 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
12953 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12954 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
12956 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
12958 /* For the SPE, we have an additional upper 32-bits on each GPR.
12959 Ideally we should save the entire 64-bits only when the upper
12960 half is used in SIMD instructions. Since we only record
12961 registers live (not the size they are used in), this proves
12962 difficult because we'd have to traverse the instruction chain at
12963 the right time, taking reload into account. This is a real pain,
12964 so we opt to save the GPRs in 64-bits always if but one register
12965 gets used in 64-bits. Otherwise, all the registers in the frame
12966 get saved in 32-bits.
12968 So... since when we save all GPRs (except the SP) in 64-bits, the
12969 traditional GP save area will be empty. */
12970 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12971 info_ptr->gp_size = 0;
12973 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12974 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12976 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12977 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12978 - info_ptr->first_altivec_reg_save);
12980 /* Does this function call anything? */
12981 info_ptr->calls_p = (! current_function_is_leaf
12982 || cfun->machine->ra_needs_full_frame);
12984 /* Determine if we need to save the link register. */
12985 if ((DEFAULT_ABI == ABI_AIX
12986 && current_function_profile
12987 && !TARGET_PROFILE_KERNEL)
12988 #ifdef TARGET_RELOCATABLE
12989 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12991 || (info_ptr->first_fp_reg_save != 64
12992 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
12993 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
12994 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
12995 || info_ptr->calls_p
12996 || rs6000_ra_ever_killed ())
12998 info_ptr->lr_save_p = 1;
12999 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
13002 /* Determine if we need to save the condition code registers. */
13003 if (regs_ever_live[CR2_REGNO]
13004 || regs_ever_live[CR3_REGNO]
13005 || regs_ever_live[CR4_REGNO])
13007 info_ptr->cr_save_p = 1;
13008 if (DEFAULT_ABI == ABI_V4)
13009 info_ptr->cr_size = reg_size;
13012 /* If the current function calls __builtin_eh_return, then we need
13013 to allocate stack space for registers that will hold data for
13014 the exception handler. */
13015 if (current_function_calls_eh_return)
13018 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
13021 /* SPE saves EH registers in 64-bits. */
13022 ehrd_size = i * (TARGET_SPE_ABI
13023 && info_ptr->spe_64bit_regs_used != 0
13024 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
13029 /* Determine various sizes. */
13030 info_ptr->reg_size = reg_size;
13031 info_ptr->fixed_size = RS6000_SAVE_AREA;
13032 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
13033 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
13034 TARGET_ALTIVEC ? 16 : 8);
13035 if (FRAME_GROWS_DOWNWARD)
13036 info_ptr->vars_size
13037 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
13038 + info_ptr->parm_size,
13039 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
13040 - (info_ptr->fixed_size + info_ptr->vars_size
13041 + info_ptr->parm_size);
13043 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13044 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
13046 info_ptr->spe_gp_size = 0;
13048 if (TARGET_ALTIVEC_ABI)
13049 info_ptr->vrsave_mask = compute_vrsave_mask ();
13051 info_ptr->vrsave_mask = 0;
13053 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
13054 info_ptr->vrsave_size = 4;
13056 info_ptr->vrsave_size = 0;
13058 compute_save_world_info (info_ptr);
13060 /* Calculate the offsets. */
13061 switch (DEFAULT_ABI)
13065 gcc_unreachable ();
13069 info_ptr->fp_save_offset = - info_ptr->fp_size;
13070 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13072 if (TARGET_ALTIVEC_ABI)
13074 info_ptr->vrsave_save_offset
13075 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
13077 /* Align stack so vector save area is on a quadword boundary. */
13078 if (info_ptr->altivec_size != 0)
13079 info_ptr->altivec_padding_size
13080 = 16 - (-info_ptr->vrsave_save_offset % 16);
13082 info_ptr->altivec_padding_size = 0;
13084 info_ptr->altivec_save_offset
13085 = info_ptr->vrsave_save_offset
13086 - info_ptr->altivec_padding_size
13087 - info_ptr->altivec_size;
13089 /* Adjust for AltiVec case. */
13090 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
13093 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
13094 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
13095 info_ptr->lr_save_offset = 2*reg_size;
13099 info_ptr->fp_save_offset = - info_ptr->fp_size;
13100 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13101 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
13103 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13105 /* Align stack so SPE GPR save area is aligned on a
13106 double-word boundary. */
13107 if (info_ptr->spe_gp_size != 0)
13108 info_ptr->spe_padding_size
13109 = 8 - (-info_ptr->cr_save_offset % 8);
13111 info_ptr->spe_padding_size = 0;
13113 info_ptr->spe_gp_save_offset
13114 = info_ptr->cr_save_offset
13115 - info_ptr->spe_padding_size
13116 - info_ptr->spe_gp_size;
13118 /* Adjust for SPE case. */
13119 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
13121 else if (TARGET_ALTIVEC_ABI)
13123 info_ptr->vrsave_save_offset
13124 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
13126 /* Align stack so vector save area is on a quadword boundary. */
13127 if (info_ptr->altivec_size != 0)
13128 info_ptr->altivec_padding_size
13129 = 16 - (-info_ptr->vrsave_save_offset % 16);
13131 info_ptr->altivec_padding_size = 0;
13133 info_ptr->altivec_save_offset
13134 = info_ptr->vrsave_save_offset
13135 - info_ptr->altivec_padding_size
13136 - info_ptr->altivec_size;
13138 /* Adjust for AltiVec case. */
13139 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
13142 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
13143 info_ptr->ehrd_offset -= ehrd_size;
13144 info_ptr->lr_save_offset = reg_size;
13148 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
13149 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
13150 + info_ptr->gp_size
13151 + info_ptr->altivec_size
13152 + info_ptr->altivec_padding_size
13153 + info_ptr->spe_gp_size
13154 + info_ptr->spe_padding_size
13156 + info_ptr->cr_size
13157 + info_ptr->vrsave_size,
13160 non_fixed_size = (info_ptr->vars_size
13161 + info_ptr->parm_size
13162 + info_ptr->save_size);
13164 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
13165 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
13167 /* Determine if we need to allocate any stack frame:
13169 For AIX we need to push the stack if a frame pointer is needed
13170 (because the stack might be dynamically adjusted), if we are
13171 debugging, if we make calls, or if the sum of fp_save, gp_save,
13172 and local variables are more than the space needed to save all
13173 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
13174 + 18*8 = 288 (GPR13 reserved).
13176 For V.4 we don't have the stack cushion that AIX uses, but assume
13177 that the debugger can handle stackless frames. */
13179 if (info_ptr->calls_p)
13180 info_ptr->push_p = 1;
13182 else if (DEFAULT_ABI == ABI_V4)
13183 info_ptr->push_p = non_fixed_size != 0;
13185 else if (frame_pointer_needed)
13186 info_ptr->push_p = 1;
13188 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
13189 info_ptr->push_p = 1;
13192 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
13194 /* Zero offsets if we're not saving those registers. */
13195 if (info_ptr->fp_size == 0)
13196 info_ptr->fp_save_offset = 0;
13198 if (info_ptr->gp_size == 0)
13199 info_ptr->gp_save_offset = 0;
13201 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
13202 info_ptr->altivec_save_offset = 0;
13204 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
13205 info_ptr->vrsave_save_offset = 0;
13207 if (! TARGET_SPE_ABI
13208 || info_ptr->spe_64bit_regs_used == 0
13209 || info_ptr->spe_gp_size == 0)
13210 info_ptr->spe_gp_save_offset = 0;
13212 if (! info_ptr->lr_save_p)
13213 info_ptr->lr_save_offset = 0;
13215 if (! info_ptr->cr_save_p)
13216 info_ptr->cr_save_offset = 0;
13221 /* Return true if the current function uses any GPRs in 64-bit SIMD
13225 spe_func_has_64bit_regs_p (void)
13229 /* Functions that save and restore all the call-saved registers will
13230 need to save/restore the registers in 64-bits. */
13231 if (current_function_calls_eh_return
13232 || current_function_calls_setjmp
13233 || current_function_has_nonlocal_goto)
13236 insns = get_insns ();
13238 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13244 /* FIXME: This should be implemented with attributes...
13246 (set_attr "spe64" "true")....then,
13247 if (get_spe64(insn)) return true;
13249 It's the only reliable way to do the stuff below. */
13251 i = PATTERN (insn);
13252 if (GET_CODE (i) == SET)
13254 enum machine_mode mode = GET_MODE (SET_SRC (i));
13256 if (SPE_VECTOR_MODE (mode))
13258 if (TARGET_E500_DOUBLE && mode == DFmode)
13268 debug_stack_info (rs6000_stack_t *info)
13270 const char *abi_string;
13273 info = rs6000_stack_info ();
13275 fprintf (stderr, "\nStack information for function %s:\n",
13276 ((current_function_decl && DECL_NAME (current_function_decl))
13277 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13282 default: abi_string = "Unknown"; break;
13283 case ABI_NONE: abi_string = "NONE"; break;
13284 case ABI_AIX: abi_string = "AIX"; break;
13285 case ABI_DARWIN: abi_string = "Darwin"; break;
13286 case ABI_V4: abi_string = "V.4"; break;
13289 fprintf (stderr, "\tABI = %5s\n", abi_string);
13291 if (TARGET_ALTIVEC_ABI)
13292 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13294 if (TARGET_SPE_ABI)
13295 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13297 if (info->first_gp_reg_save != 32)
13298 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13300 if (info->first_fp_reg_save != 64)
13301 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13303 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13304 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13305 info->first_altivec_reg_save);
13307 if (info->lr_save_p)
13308 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13310 if (info->cr_save_p)
13311 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13313 if (info->vrsave_mask)
13314 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13317 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13320 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13322 if (info->gp_save_offset)
13323 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13325 if (info->fp_save_offset)
13326 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13328 if (info->altivec_save_offset)
13329 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13330 info->altivec_save_offset);
13332 if (info->spe_gp_save_offset)
13333 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13334 info->spe_gp_save_offset);
13336 if (info->vrsave_save_offset)
13337 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13338 info->vrsave_save_offset);
13340 if (info->lr_save_offset)
13341 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13343 if (info->cr_save_offset)
13344 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13346 if (info->varargs_save_offset)
13347 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13349 if (info->total_size)
13350 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13353 if (info->vars_size)
13354 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13357 if (info->parm_size)
13358 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13360 if (info->fixed_size)
13361 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13364 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13366 if (info->spe_gp_size)
13367 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13370 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13372 if (info->altivec_size)
13373 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13375 if (info->vrsave_size)
13376 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13378 if (info->altivec_padding_size)
13379 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13380 info->altivec_padding_size);
13382 if (info->spe_padding_size)
13383 fprintf (stderr, "\tspe_padding_size = %5d\n",
13384 info->spe_padding_size);
13387 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13389 if (info->save_size)
13390 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13392 if (info->reg_size != 4)
13393 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13395 fprintf (stderr, "\n");
13399 rs6000_return_addr (int count, rtx frame)
13401 /* Currently we don't optimize very well between prolog and body
13402 code and for PIC code the code can be actually quite bad, so
13403 don't try to be too clever here. */
13404 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13406 cfun->machine->ra_needs_full_frame = 1;
13413 plus_constant (copy_to_reg
13414 (gen_rtx_MEM (Pmode,
13415 memory_address (Pmode, frame))),
13416 RETURN_ADDRESS_OFFSET)));
13419 cfun->machine->ra_need_lr = 1;
13420 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13423 /* Say whether a function is a candidate for sibcall handling or not.
13424 We do not allow indirect calls to be optimized into sibling calls.
13425 Also, we can't do it if there are any vector parameters; there's
13426 nowhere to put the VRsave code so it works; note that functions with
13427 vector parameters are required to have a prototype, so the argument
13428 type info must be available here. (The tail recursion case can work
13429 with vector parameters, but there's no way to distinguish here.) */
13431 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13436 if (TARGET_ALTIVEC_VRSAVE)
13438 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13439 type; type = TREE_CHAIN (type))
13441 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13445 if (DEFAULT_ABI == ABI_DARWIN
13446 || (*targetm.binds_local_p) (decl))
13448 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13450 if (!lookup_attribute ("longcall", attr_list)
13451 || lookup_attribute ("shortcall", attr_list))
13458 /* NULL if INSN insn is valid within a low-overhead loop.
13459 Otherwise return why doloop cannot be applied.
13460 PowerPC uses the COUNT register for branch on table instructions. */
13462 static const char *
13463 rs6000_invalid_within_doloop (rtx insn)
13466 return "Function call in the loop.";
13469 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
13470 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
13471 return "Computed branch in the loop.";
13477 rs6000_ra_ever_killed (void)
13483 if (current_function_is_thunk)
13486 /* regs_ever_live has LR marked as used if any sibcalls are present,
13487 but this should not force saving and restoring in the
13488 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13489 clobbers LR, so that is inappropriate. */
13491 /* Also, the prologue can generate a store into LR that
13492 doesn't really count, like this:
13495 bcl to set PIC register
13499 When we're called from the epilogue, we need to avoid counting
13500 this as a store. */
13502 push_topmost_sequence ();
13503 top = get_insns ();
13504 pop_topmost_sequence ();
13505 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13507 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13513 if (!SIBLING_CALL_P (insn))
13516 else if (find_regno_note (insn, REG_INC, LINK_REGISTER_REGNUM))
13518 else if (set_of (reg, insn) != NULL_RTX
13519 && !prologue_epilogue_contains (insn))
13526 /* Add a REG_MAYBE_DEAD note to the insn. */
13528 rs6000_maybe_dead (rtx insn)
13530 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13535 /* Emit instructions needed to load the TOC register.
13536 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13537 a constant pool; or for SVR4 -fpic. */
13540 rs6000_emit_load_toc_table (int fromprolog)
13543 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13545 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
13548 rtx lab, tmp1, tmp2, got, tempLR;
13550 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13551 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13553 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13555 got = rs6000_got_sym ();
13556 tmp1 = tmp2 = dest;
13559 tmp1 = gen_reg_rtx (Pmode);
13560 tmp2 = gen_reg_rtx (Pmode);
13562 tempLR = (fromprolog
13563 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13564 : gen_reg_rtx (Pmode));
13565 insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab));
13567 rs6000_maybe_dead (insn);
13568 insn = emit_move_insn (tmp1, tempLR);
13570 rs6000_maybe_dead (insn);
13571 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
13573 rs6000_maybe_dead (insn);
13574 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
13576 rs6000_maybe_dead (insn);
13578 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
13580 rtx tempLR = (fromprolog
13581 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13582 : gen_reg_rtx (Pmode));
13584 insn = emit_insn (gen_load_toc_v4_pic_si (tempLR));
13586 rs6000_maybe_dead (insn);
13587 insn = emit_move_insn (dest, tempLR);
13589 rs6000_maybe_dead (insn);
13591 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
13594 rtx tempLR = (fromprolog
13595 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13596 : gen_reg_rtx (Pmode));
13597 rtx temp0 = (fromprolog
13598 ? gen_rtx_REG (Pmode, 0)
13599 : gen_reg_rtx (Pmode));
13605 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13606 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13608 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
13609 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13611 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
13613 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
13614 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
13622 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13623 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
13624 emit_move_insn (dest, tempLR);
13625 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
13627 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
13629 rs6000_maybe_dead (insn);
13631 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
13633 /* This is for AIX code running in non-PIC ELF32. */
13636 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
13637 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13639 insn = emit_insn (gen_elf_high (dest, realsym));
13641 rs6000_maybe_dead (insn);
13642 insn = emit_insn (gen_elf_low (dest, dest, realsym));
13644 rs6000_maybe_dead (insn);
13648 gcc_assert (DEFAULT_ABI == ABI_AIX);
13651 insn = emit_insn (gen_load_toc_aix_si (dest));
13653 insn = emit_insn (gen_load_toc_aix_di (dest));
13655 rs6000_maybe_dead (insn);
13659 /* Emit instructions to restore the link register after determining where
13660 its value has been stored. */
13663 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
13665 rs6000_stack_t *info = rs6000_stack_info ();
13668 operands[0] = source;
13669 operands[1] = scratch;
13671 if (info->lr_save_p)
13673 rtx frame_rtx = stack_pointer_rtx;
13674 HOST_WIDE_INT sp_offset = 0;
13677 if (frame_pointer_needed
13678 || current_function_calls_alloca
13679 || info->total_size > 32767)
13681 tmp = gen_frame_mem (Pmode, frame_rtx);
13682 emit_move_insn (operands[1], tmp);
13683 frame_rtx = operands[1];
13685 else if (info->push_p)
13686 sp_offset = info->total_size;
13688 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13689 tmp = gen_frame_mem (Pmode, tmp);
13690 emit_move_insn (tmp, operands[0]);
13693 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13696 static GTY(()) int set = -1;
13699 get_TOC_alias_set (void)
13702 set = new_alias_set ();
13706 /* This returns nonzero if the current function uses the TOC. This is
13707 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13708 is generated by the ABI_V4 load_toc_* patterns. */
13715 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13718 rtx pat = PATTERN (insn);
13721 if (GET_CODE (pat) == PARALLEL)
13722 for (i = 0; i < XVECLEN (pat, 0); i++)
13724 rtx sub = XVECEXP (pat, 0, i);
13725 if (GET_CODE (sub) == USE)
13727 sub = XEXP (sub, 0);
13728 if (GET_CODE (sub) == UNSPEC
13729 && XINT (sub, 1) == UNSPEC_TOC)
13739 create_TOC_reference (rtx symbol)
13741 if (no_new_pseudos)
13742 regs_ever_live[TOC_REGISTER] = 1;
13743 return gen_rtx_PLUS (Pmode,
13744 gen_rtx_REG (Pmode, TOC_REGISTER),
13745 gen_rtx_CONST (Pmode,
13746 gen_rtx_MINUS (Pmode, symbol,
13747 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13750 /* If _Unwind_* has been called from within the same module,
13751 toc register is not guaranteed to be saved to 40(1) on function
13752 entry. Save it there in that case. */
13755 rs6000_aix_emit_builtin_unwind_init (void)
13758 rtx stack_top = gen_reg_rtx (Pmode);
13759 rtx opcode_addr = gen_reg_rtx (Pmode);
13760 rtx opcode = gen_reg_rtx (SImode);
13761 rtx tocompare = gen_reg_rtx (SImode);
13762 rtx no_toc_save_needed = gen_label_rtx ();
13764 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
13765 emit_move_insn (stack_top, mem);
13767 mem = gen_frame_mem (Pmode,
13768 gen_rtx_PLUS (Pmode, stack_top,
13769 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13770 emit_move_insn (opcode_addr, mem);
13771 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13772 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13773 : 0xE8410028, SImode));
13775 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13776 SImode, NULL_RTX, NULL_RTX,
13777 no_toc_save_needed);
13779 mem = gen_frame_mem (Pmode,
13780 gen_rtx_PLUS (Pmode, stack_top,
13781 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13782 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13783 emit_label (no_toc_save_needed);
13786 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
13787 and the change to the stack pointer. */
13790 rs6000_emit_stack_tie (void)
13792 rtx mem = gen_frame_mem (BLKmode,
13793 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
13795 emit_insn (gen_stack_tie (mem));
13798 /* Emit the correct code for allocating stack space, as insns.
13799 If COPY_R12, make sure a copy of the old frame is left in r12.
13800 The generated code may use hard register 0 as a temporary. */
13803 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
13806 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13807 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
13808 rtx todec = gen_int_mode (-size, Pmode);
13810 if (INTVAL (todec) != -size)
13812 warning (0, "stack frame too large");
13813 emit_insn (gen_trap ());
13817 if (current_function_limit_stack)
13819 if (REG_P (stack_limit_rtx)
13820 && REGNO (stack_limit_rtx) > 1
13821 && REGNO (stack_limit_rtx) <= 31)
13823 emit_insn (TARGET_32BIT
13824 ? gen_addsi3 (tmp_reg,
13827 : gen_adddi3 (tmp_reg,
13831 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13834 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
13836 && DEFAULT_ABI == ABI_V4)
13838 rtx toload = gen_rtx_CONST (VOIDmode,
13839 gen_rtx_PLUS (Pmode,
13843 emit_insn (gen_elf_high (tmp_reg, toload));
13844 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
13845 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13849 warning (0, "stack limit expression is not supported");
13852 if (copy_r12 || ! TARGET_UPDATE)
13853 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
13859 /* Need a note here so that try_split doesn't get confused. */
13860 if (get_last_insn () == NULL_RTX)
13861 emit_note (NOTE_INSN_DELETED);
13862 insn = emit_move_insn (tmp_reg, todec);
13863 try_split (PATTERN (insn), insn, 0);
13867 insn = emit_insn (TARGET_32BIT
13868 ? gen_movsi_update (stack_reg, stack_reg,
13870 : gen_movdi_di_update (stack_reg, stack_reg,
13871 todec, stack_reg));
13875 insn = emit_insn (TARGET_32BIT
13876 ? gen_addsi3 (stack_reg, stack_reg, todec)
13877 : gen_adddi3 (stack_reg, stack_reg, todec));
13878 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
13879 gen_rtx_REG (Pmode, 12));
13882 RTX_FRAME_RELATED_P (insn) = 1;
13884 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13885 gen_rtx_SET (VOIDmode, stack_reg,
13886 gen_rtx_PLUS (Pmode, stack_reg,
13891 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13892 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13893 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13894 deduce these equivalences by itself so it wasn't necessary to hold
13895 its hand so much. */
13898 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13899 rtx reg2, rtx rreg)
13903 /* copy_rtx will not make unique copies of registers, so we need to
13904 ensure we don't have unwanted sharing here. */
13906 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13909 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13911 real = copy_rtx (PATTERN (insn));
13913 if (reg2 != NULL_RTX)
13914 real = replace_rtx (real, reg2, rreg);
13916 real = replace_rtx (real, reg,
13917 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13918 STACK_POINTER_REGNUM),
13921 /* We expect that 'real' is either a SET or a PARALLEL containing
13922 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13923 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13925 if (GET_CODE (real) == SET)
13929 temp = simplify_rtx (SET_SRC (set));
13931 SET_SRC (set) = temp;
13932 temp = simplify_rtx (SET_DEST (set));
13934 SET_DEST (set) = temp;
13935 if (GET_CODE (SET_DEST (set)) == MEM)
13937 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13939 XEXP (SET_DEST (set), 0) = temp;
13946 gcc_assert (GET_CODE (real) == PARALLEL);
13947 for (i = 0; i < XVECLEN (real, 0); i++)
13948 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13950 rtx set = XVECEXP (real, 0, i);
13952 temp = simplify_rtx (SET_SRC (set));
13954 SET_SRC (set) = temp;
13955 temp = simplify_rtx (SET_DEST (set));
13957 SET_DEST (set) = temp;
13958 if (GET_CODE (SET_DEST (set)) == MEM)
13960 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13962 XEXP (SET_DEST (set), 0) = temp;
13964 RTX_FRAME_RELATED_P (set) = 1;
13969 real = spe_synthesize_frame_save (real);
13971 RTX_FRAME_RELATED_P (insn) = 1;
13972 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13977 /* Given an SPE frame note, return a PARALLEL of SETs with the
13978 original note, plus a synthetic register save. */
13981 spe_synthesize_frame_save (rtx real)
13983 rtx synth, offset, reg, real2;
13985 if (GET_CODE (real) != SET
13986 || GET_MODE (SET_SRC (real)) != V2SImode)
13989 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13990 frame related note. The parallel contains a set of the register
13991 being saved, and another set to a synthetic register (n+1200).
13992 This is so we can differentiate between 64-bit and 32-bit saves.
13993 Words cannot describe this nastiness. */
13995 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
13996 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
13997 && GET_CODE (SET_SRC (real)) == REG);
14000 (set (mem (plus (reg x) (const y)))
14003 (set (mem (plus (reg x) (const y+4)))
14007 real2 = copy_rtx (real);
14008 PUT_MODE (SET_DEST (real2), SImode);
14009 reg = SET_SRC (real2);
14010 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
14011 synth = copy_rtx (real2);
14013 if (BYTES_BIG_ENDIAN)
14015 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
14016 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
14019 reg = SET_SRC (synth);
14021 synth = replace_rtx (synth, reg,
14022 gen_rtx_REG (SImode, REGNO (reg) + 1200));
14024 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
14025 synth = replace_rtx (synth, offset,
14026 GEN_INT (INTVAL (offset)
14027 + (BYTES_BIG_ENDIAN ? 0 : 4)));
14029 RTX_FRAME_RELATED_P (synth) = 1;
14030 RTX_FRAME_RELATED_P (real2) = 1;
14031 if (BYTES_BIG_ENDIAN)
14032 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
14034 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
14039 /* Returns an insn that has a vrsave set operation with the
14040 appropriate CLOBBERs. */
14043 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
14046 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
14047 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14050 = gen_rtx_SET (VOIDmode,
14052 gen_rtx_UNSPEC_VOLATILE (SImode,
14053 gen_rtvec (2, reg, vrsave),
14054 UNSPECV_SET_VRSAVE));
14058 /* We need to clobber the registers in the mask so the scheduler
14059 does not move sets to VRSAVE before sets of AltiVec registers.
14061 However, if the function receives nonlocal gotos, reload will set
14062 all call saved registers live. We will end up with:
14064 (set (reg 999) (mem))
14065 (parallel [ (set (reg vrsave) (unspec blah))
14066 (clobber (reg 999))])
14068 The clobber will cause the store into reg 999 to be dead, and
14069 flow will attempt to delete an epilogue insn. In this case, we
14070 need an unspec use/set of the register. */
14072 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14073 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14075 if (!epiloguep || call_used_regs [i])
14076 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
14077 gen_rtx_REG (V4SImode, i));
14080 rtx reg = gen_rtx_REG (V4SImode, i);
14083 = gen_rtx_SET (VOIDmode,
14085 gen_rtx_UNSPEC (V4SImode,
14086 gen_rtvec (1, reg), 27));
14090 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
14092 for (i = 0; i < nclobs; ++i)
14093 XVECEXP (insn, 0, i) = clobs[i];
14098 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
14099 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
14102 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
14103 unsigned int regno, int offset, HOST_WIDE_INT total_size)
14105 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
14106 rtx replacea, replaceb;
14108 int_rtx = GEN_INT (offset);
14110 /* Some cases that need register indexed addressing. */
14111 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
14112 || (TARGET_E500_DOUBLE && mode == DFmode)
14114 && SPE_VECTOR_MODE (mode)
14115 && !SPE_CONST_OFFSET_OK (offset)))
14117 /* Whomever calls us must make sure r11 is available in the
14118 flow path of instructions in the prologue. */
14119 offset_rtx = gen_rtx_REG (Pmode, 11);
14120 emit_move_insn (offset_rtx, int_rtx);
14122 replacea = offset_rtx;
14123 replaceb = int_rtx;
14127 offset_rtx = int_rtx;
14128 replacea = NULL_RTX;
14129 replaceb = NULL_RTX;
14132 reg = gen_rtx_REG (mode, regno);
14133 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
14134 mem = gen_frame_mem (mode, addr);
14136 insn = emit_move_insn (mem, reg);
14138 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
14141 /* Emit an offset memory reference suitable for a frame store, while
14142 converting to a valid addressing mode. */
14145 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
14147 rtx int_rtx, offset_rtx;
14149 int_rtx = GEN_INT (offset);
14151 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
14152 || (TARGET_E500_DOUBLE && mode == DFmode))
14154 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14155 emit_move_insn (offset_rtx, int_rtx);
14158 offset_rtx = int_rtx;
14160 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
14163 /* Look for user-defined global regs. We should not save and restore these,
14164 and cannot use stmw/lmw if there are any in its range. */
14167 no_global_regs_above (int first_greg)
14170 for (i = 0; i < 32 - first_greg; i++)
14171 if (global_regs[first_greg + i])
14176 #ifndef TARGET_FIX_AND_CONTINUE
14177 #define TARGET_FIX_AND_CONTINUE 0
14180 /* Emit function prologue as insns. */
14183 rs6000_emit_prologue (void)
14185 rs6000_stack_t *info = rs6000_stack_info ();
14186 enum machine_mode reg_mode = Pmode;
14187 int reg_size = TARGET_32BIT ? 4 : 8;
14188 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14189 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
14190 rtx frame_reg_rtx = sp_reg_rtx;
14191 rtx cr_save_rtx = NULL_RTX;
14193 int saving_FPRs_inline;
14194 int using_store_multiple;
14195 HOST_WIDE_INT sp_offset = 0;
14197 if (TARGET_FIX_AND_CONTINUE)
14199 /* gdb on darwin arranges to forward a function from the old
14200 address by modifying the first 5 instructions of the function
14201 to branch to the overriding function. This is necessary to
14202 permit function pointers that point to the old function to
14203 actually forward to the new function. */
14204 emit_insn (gen_nop ());
14205 emit_insn (gen_nop ());
14206 emit_insn (gen_nop ());
14207 emit_insn (gen_nop ());
14208 emit_insn (gen_nop ());
14211 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14213 reg_mode = V2SImode;
14217 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14218 && (!TARGET_SPE_ABI
14219 || info->spe_64bit_regs_used == 0)
14220 && info->first_gp_reg_save < 31
14221 && no_global_regs_above (info->first_gp_reg_save));
14222 saving_FPRs_inline = (info->first_fp_reg_save == 64
14223 || FP_SAVE_INLINE (info->first_fp_reg_save)
14224 || current_function_calls_eh_return
14225 || cfun->machine->ra_need_lr);
14227 /* For V.4, update stack before we do any saving and set back pointer. */
14229 && (DEFAULT_ABI == ABI_V4
14230 || current_function_calls_eh_return))
14232 if (info->total_size < 32767)
14233 sp_offset = info->total_size;
14235 frame_reg_rtx = frame_ptr_rtx;
14236 rs6000_emit_allocate_stack (info->total_size,
14237 (frame_reg_rtx != sp_reg_rtx
14238 && (info->cr_save_p
14240 || info->first_fp_reg_save < 64
14241 || info->first_gp_reg_save < 32
14243 if (frame_reg_rtx != sp_reg_rtx)
14244 rs6000_emit_stack_tie ();
14247 /* Handle world saves specially here. */
14248 if (WORLD_SAVE_P (info))
14254 /* save_world expects lr in r0. */
14255 if (info->lr_save_p)
14257 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14258 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14259 RTX_FRAME_RELATED_P (insn) = 1;
14262 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14263 assumptions about the offsets of various bits of the stack
14265 gcc_assert (info->gp_save_offset == -220
14266 && info->fp_save_offset == -144
14267 && info->lr_save_offset == 8
14268 && info->cr_save_offset == 4
14271 && (!current_function_calls_eh_return
14272 || info->ehrd_offset == -432)
14273 && info->vrsave_save_offset == -224
14274 && info->altivec_save_offset == (-224 -16 -192));
14276 treg = gen_rtx_REG (SImode, 11);
14277 emit_move_insn (treg, GEN_INT (-info->total_size));
14279 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14280 in R11. It also clobbers R12, so beware! */
14282 /* Preserve CR2 for save_world prologues */
14284 sz += 32 - info->first_gp_reg_save;
14285 sz += 64 - info->first_fp_reg_save;
14286 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14287 p = rtvec_alloc (sz);
14289 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14290 gen_rtx_REG (Pmode,
14291 LINK_REGISTER_REGNUM));
14292 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14293 gen_rtx_SYMBOL_REF (Pmode,
14295 /* We do floats first so that the instruction pattern matches
14297 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14299 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14300 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14301 GEN_INT (info->fp_save_offset
14302 + sp_offset + 8 * i));
14303 rtx mem = gen_frame_mem (DFmode, addr);
14305 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14307 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14309 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14310 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14311 GEN_INT (info->altivec_save_offset
14312 + sp_offset + 16 * i));
14313 rtx mem = gen_frame_mem (V4SImode, addr);
14315 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14317 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14319 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14320 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14321 GEN_INT (info->gp_save_offset
14322 + sp_offset + reg_size * i));
14323 rtx mem = gen_frame_mem (reg_mode, addr);
14325 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14329 /* CR register traditionally saved as CR2. */
14330 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14331 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14332 GEN_INT (info->cr_save_offset
14334 rtx mem = gen_frame_mem (reg_mode, addr);
14336 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14338 /* Prevent any attempt to delete the setting of r0 and treg! */
14339 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
14340 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
14341 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
14343 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14344 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14345 NULL_RTX, NULL_RTX);
14347 if (current_function_calls_eh_return)
14352 unsigned int regno = EH_RETURN_DATA_REGNO (i);
14353 if (regno == INVALID_REGNUM)
14355 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14356 info->ehrd_offset + sp_offset
14357 + reg_size * (int) i,
14363 /* Save AltiVec registers if needed. */
14364 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14368 /* There should be a non inline version of this, for when we
14369 are saving lots of vector registers. */
14370 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14371 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14373 rtx areg, savereg, mem;
14376 offset = info->altivec_save_offset + sp_offset
14377 + 16 * (i - info->first_altivec_reg_save);
14379 savereg = gen_rtx_REG (V4SImode, i);
14381 areg = gen_rtx_REG (Pmode, 0);
14382 emit_move_insn (areg, GEN_INT (offset));
14384 /* AltiVec addressing mode is [reg+reg]. */
14385 mem = gen_frame_mem (V4SImode,
14386 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
14388 insn = emit_move_insn (mem, savereg);
14390 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14391 areg, GEN_INT (offset));
14395 /* VRSAVE is a bit vector representing which AltiVec registers
14396 are used. The OS uses this to determine which vector
14397 registers to save on a context switch. We need to save
14398 VRSAVE on the stack frame, add whatever AltiVec registers we
14399 used in this function, and do the corresponding magic in the
14402 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14403 && info->vrsave_mask != 0)
14405 rtx reg, mem, vrsave;
14408 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14409 as frame_reg_rtx and r11 as the static chain pointer for
14410 nested functions. */
14411 reg = gen_rtx_REG (SImode, 0);
14412 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14414 emit_insn (gen_get_vrsave_internal (reg));
14416 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14418 if (!WORLD_SAVE_P (info))
14421 offset = info->vrsave_save_offset + sp_offset;
14422 mem = gen_frame_mem (SImode,
14423 gen_rtx_PLUS (Pmode, frame_reg_rtx,
14424 GEN_INT (offset)));
14425 insn = emit_move_insn (mem, reg);
14428 /* Include the registers in the mask. */
14429 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14431 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14434 /* If we use the link register, get it into r0. */
14435 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14437 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14438 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14439 RTX_FRAME_RELATED_P (insn) = 1;
14442 /* If we need to save CR, put it into r12. */
14443 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14447 cr_save_rtx = gen_rtx_REG (SImode, 12);
14448 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14449 RTX_FRAME_RELATED_P (insn) = 1;
14450 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14451 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14452 But that's OK. All we have to do is specify that _one_ condition
14453 code register is saved in this stack slot. The thrower's epilogue
14454 will then restore all the call-saved registers.
14455 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14456 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14457 gen_rtx_REG (SImode, CR2_REGNO));
14458 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14463 /* Do any required saving of fpr's. If only one or two to save, do
14464 it ourselves. Otherwise, call function. */
14465 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14468 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14469 if ((regs_ever_live[info->first_fp_reg_save+i]
14470 && ! call_used_regs[info->first_fp_reg_save+i]))
14471 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14472 info->first_fp_reg_save + i,
14473 info->fp_save_offset + sp_offset + 8 * i,
14476 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14480 const char *alloc_rname;
14482 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14484 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14485 gen_rtx_REG (Pmode,
14486 LINK_REGISTER_REGNUM));
14487 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14488 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14489 alloc_rname = ggc_strdup (rname);
14490 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14491 gen_rtx_SYMBOL_REF (Pmode,
14493 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14495 rtx addr, reg, mem;
14496 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14497 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14498 GEN_INT (info->fp_save_offset
14499 + sp_offset + 8*i));
14500 mem = gen_frame_mem (DFmode, addr);
14502 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14504 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14505 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14506 NULL_RTX, NULL_RTX);
14509 /* Save GPRs. This is done as a PARALLEL if we are using
14510 the store-multiple instructions. */
14511 if (!WORLD_SAVE_P (info) && using_store_multiple)
14515 p = rtvec_alloc (32 - info->first_gp_reg_save);
14516 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14518 rtx addr, reg, mem;
14519 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14520 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14521 GEN_INT (info->gp_save_offset
14524 mem = gen_frame_mem (reg_mode, addr);
14526 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14528 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14529 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14530 NULL_RTX, NULL_RTX);
14532 else if (!WORLD_SAVE_P (info))
14535 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14536 if ((regs_ever_live[info->first_gp_reg_save + i]
14537 && (!call_used_regs[info->first_gp_reg_save + i]
14538 || (i + info->first_gp_reg_save
14539 == RS6000_PIC_OFFSET_TABLE_REGNUM
14540 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14541 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14542 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14543 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14545 rtx addr, reg, mem;
14546 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14548 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14550 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14553 if (!SPE_CONST_OFFSET_OK (offset))
14555 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14556 emit_move_insn (b, GEN_INT (offset));
14559 b = GEN_INT (offset);
14561 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14562 mem = gen_frame_mem (V2SImode, addr);
14563 insn = emit_move_insn (mem, reg);
14565 if (GET_CODE (b) == CONST_INT)
14566 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14567 NULL_RTX, NULL_RTX);
14569 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14570 b, GEN_INT (offset));
14574 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14575 GEN_INT (info->gp_save_offset
14578 mem = gen_frame_mem (reg_mode, addr);
14580 insn = emit_move_insn (mem, reg);
14581 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14582 NULL_RTX, NULL_RTX);
14587 /* ??? There's no need to emit actual instructions here, but it's the
14588 easiest way to get the frame unwind information emitted. */
14589 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
14591 unsigned int i, regno;
14593 /* In AIX ABI we need to pretend we save r2 here. */
14596 rtx addr, reg, mem;
14598 reg = gen_rtx_REG (reg_mode, 2);
14599 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14600 GEN_INT (sp_offset + 5 * reg_size));
14601 mem = gen_frame_mem (reg_mode, addr);
14603 insn = emit_move_insn (mem, reg);
14604 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14605 NULL_RTX, NULL_RTX);
14606 PATTERN (insn) = gen_blockage ();
14611 regno = EH_RETURN_DATA_REGNO (i);
14612 if (regno == INVALID_REGNUM)
14615 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14616 info->ehrd_offset + sp_offset
14617 + reg_size * (int) i,
14622 /* Save lr if we used it. */
14623 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14625 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14626 GEN_INT (info->lr_save_offset + sp_offset));
14627 rtx reg = gen_rtx_REG (Pmode, 0);
14628 rtx mem = gen_rtx_MEM (Pmode, addr);
14629 /* This should not be of frame_alias_set, because of
14630 __builtin_return_address. */
14632 insn = emit_move_insn (mem, reg);
14633 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14634 NULL_RTX, NULL_RTX);
14637 /* Save CR if we use any that must be preserved. */
14638 if (!WORLD_SAVE_P (info) && info->cr_save_p)
14640 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14641 GEN_INT (info->cr_save_offset + sp_offset));
14642 rtx mem = gen_frame_mem (SImode, addr);
14643 /* See the large comment above about why CR2_REGNO is used. */
14644 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
14646 /* If r12 was used to hold the original sp, copy cr into r0 now
14648 if (REGNO (frame_reg_rtx) == 12)
14652 cr_save_rtx = gen_rtx_REG (SImode, 0);
14653 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14654 RTX_FRAME_RELATED_P (insn) = 1;
14655 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
14656 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14661 insn = emit_move_insn (mem, cr_save_rtx);
14663 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14664 NULL_RTX, NULL_RTX);
14667 /* Update stack and set back pointer unless this is V.4,
14668 for which it was done previously. */
14669 if (!WORLD_SAVE_P (info) && info->push_p
14670 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
14671 rs6000_emit_allocate_stack (info->total_size, FALSE);
14673 /* Set frame pointer, if needed. */
14674 if (frame_pointer_needed)
14676 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
14678 RTX_FRAME_RELATED_P (insn) = 1;
14681 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14682 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
14683 || (DEFAULT_ABI == ABI_V4
14684 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
14685 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
14687 /* If emit_load_toc_table will use the link register, we need to save
14688 it. We use R12 for this purpose because emit_load_toc_table
14689 can use register 0. This allows us to use a plain 'blr' to return
14690 from the procedure more often. */
14691 int save_LR_around_toc_setup = (TARGET_ELF
14692 && DEFAULT_ABI != ABI_AIX
14694 && ! info->lr_save_p
14695 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
14696 if (save_LR_around_toc_setup)
14698 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14700 insn = emit_move_insn (frame_ptr_rtx, lr);
14701 rs6000_maybe_dead (insn);
14702 RTX_FRAME_RELATED_P (insn) = 1;
14704 rs6000_emit_load_toc_table (TRUE);
14706 insn = emit_move_insn (lr, frame_ptr_rtx);
14707 rs6000_maybe_dead (insn);
14708 RTX_FRAME_RELATED_P (insn) = 1;
14711 rs6000_emit_load_toc_table (TRUE);
14715 if (DEFAULT_ABI == ABI_DARWIN
14716 && flag_pic && current_function_uses_pic_offset_table)
14718 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14719 rtx src = machopic_function_base_sym ();
14721 /* Save and restore LR locally around this call (in R0). */
14722 if (!info->lr_save_p)
14723 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr));
14725 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14727 insn = emit_move_insn (gen_rtx_REG (Pmode,
14728 RS6000_PIC_OFFSET_TABLE_REGNUM),
14730 rs6000_maybe_dead (insn);
14732 if (!info->lr_save_p)
14733 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0)));
14738 /* Write function prologue. */
14741 rs6000_output_function_prologue (FILE *file,
14742 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14744 rs6000_stack_t *info = rs6000_stack_info ();
14746 if (TARGET_DEBUG_STACK)
14747 debug_stack_info (info);
14749 /* Write .extern for any function we will call to save and restore
14751 if (info->first_fp_reg_save < 64
14752 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14753 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14754 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14755 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14756 RESTORE_FP_SUFFIX);
14758 /* Write .extern for AIX common mode routines, if needed. */
14759 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14761 fputs ("\t.extern __mulh\n", file);
14762 fputs ("\t.extern __mull\n", file);
14763 fputs ("\t.extern __divss\n", file);
14764 fputs ("\t.extern __divus\n", file);
14765 fputs ("\t.extern __quoss\n", file);
14766 fputs ("\t.extern __quous\n", file);
14767 common_mode_defined = 1;
14770 if (! HAVE_prologue)
14774 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14775 the "toplevel" insn chain. */
14776 emit_note (NOTE_INSN_DELETED);
14777 rs6000_emit_prologue ();
14778 emit_note (NOTE_INSN_DELETED);
14780 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14784 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14786 INSN_ADDRESSES_NEW (insn, addr);
14791 if (TARGET_DEBUG_STACK)
14792 debug_rtx_list (get_insns (), 100);
14793 final (get_insns (), file, FALSE);
14797 rs6000_pic_labelno++;
14800 /* Emit function epilogue as insns.
14802 At present, dwarf2out_frame_debug_expr doesn't understand
14803 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14804 anywhere in the epilogue. Most of the insns below would in any case
14805 need special notes to explain where r11 is in relation to the stack. */
14808 rs6000_emit_epilogue (int sibcall)
14810 rs6000_stack_t *info;
14811 int restoring_FPRs_inline;
14812 int using_load_multiple;
14813 int using_mfcr_multiple;
14814 int use_backchain_to_restore_sp;
14816 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
14817 rtx frame_reg_rtx = sp_reg_rtx;
14818 enum machine_mode reg_mode = Pmode;
14819 int reg_size = TARGET_32BIT ? 4 : 8;
14822 info = rs6000_stack_info ();
14824 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14826 reg_mode = V2SImode;
14830 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14831 && (!TARGET_SPE_ABI
14832 || info->spe_64bit_regs_used == 0)
14833 && info->first_gp_reg_save < 31
14834 && no_global_regs_above (info->first_gp_reg_save));
14835 restoring_FPRs_inline = (sibcall
14836 || current_function_calls_eh_return
14837 || info->first_fp_reg_save == 64
14838 || FP_SAVE_INLINE (info->first_fp_reg_save));
14839 use_backchain_to_restore_sp = (frame_pointer_needed
14840 || current_function_calls_alloca
14841 || info->total_size > 32767);
14842 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
14843 || rs6000_cpu == PROCESSOR_PPC603
14844 || rs6000_cpu == PROCESSOR_PPC750
14847 if (WORLD_SAVE_P (info))
14851 const char *alloc_rname;
14854 /* eh_rest_world_r10 will return to the location saved in the LR
14855 stack slot (which is not likely to be our caller.)
14856 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14857 rest_world is similar, except any R10 parameter is ignored.
14858 The exception-handling stuff that was here in 2.95 is no
14859 longer necessary. */
14863 + 32 - info->first_gp_reg_save
14864 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
14865 + 63 + 1 - info->first_fp_reg_save);
14867 strcpy (rname, ((current_function_calls_eh_return) ?
14868 "*eh_rest_world_r10" : "*rest_world"));
14869 alloc_rname = ggc_strdup (rname);
14872 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
14873 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14874 gen_rtx_REG (Pmode,
14875 LINK_REGISTER_REGNUM));
14877 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
14878 /* The instruction pattern requires a clobber here;
14879 it is shared with the restVEC helper. */
14881 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14884 /* CR register traditionally saved as CR2. */
14885 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14886 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14887 GEN_INT (info->cr_save_offset));
14888 rtx mem = gen_frame_mem (reg_mode, addr);
14890 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14893 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14895 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14896 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14897 GEN_INT (info->gp_save_offset
14899 rtx mem = gen_frame_mem (reg_mode, addr);
14901 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14903 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14905 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14906 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14907 GEN_INT (info->altivec_save_offset
14909 rtx mem = gen_frame_mem (V4SImode, addr);
14911 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14913 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14915 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14916 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14917 GEN_INT (info->fp_save_offset
14919 rtx mem = gen_frame_mem (DFmode, addr);
14921 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14924 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
14926 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
14928 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
14930 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
14932 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
14933 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14938 /* If we have a frame pointer, a call to alloca, or a large stack
14939 frame, restore the old stack pointer using the backchain. Otherwise,
14940 we know what size to update it with. */
14941 if (use_backchain_to_restore_sp)
14943 /* Under V.4, don't reset the stack pointer until after we're done
14944 loading the saved registers. */
14945 if (DEFAULT_ABI == ABI_V4)
14946 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
14948 emit_move_insn (frame_reg_rtx,
14949 gen_rtx_MEM (Pmode, sp_reg_rtx));
14951 else if (info->push_p)
14953 if (DEFAULT_ABI == ABI_V4
14954 || current_function_calls_eh_return)
14955 sp_offset = info->total_size;
14958 emit_insn (TARGET_32BIT
14959 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14960 GEN_INT (info->total_size))
14961 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14962 GEN_INT (info->total_size)));
14966 /* Restore AltiVec registers if needed. */
14967 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14971 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14972 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14974 rtx addr, areg, mem;
14976 areg = gen_rtx_REG (Pmode, 0);
14978 (areg, GEN_INT (info->altivec_save_offset
14980 + 16 * (i - info->first_altivec_reg_save)));
14982 /* AltiVec addressing mode is [reg+reg]. */
14983 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14984 mem = gen_frame_mem (V4SImode, addr);
14986 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14990 /* Restore VRSAVE if needed. */
14991 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14992 && info->vrsave_mask != 0)
14994 rtx addr, mem, reg;
14996 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14997 GEN_INT (info->vrsave_save_offset + sp_offset));
14998 mem = gen_frame_mem (SImode, addr);
14999 reg = gen_rtx_REG (SImode, 12);
15000 emit_move_insn (reg, mem);
15002 emit_insn (generate_set_vrsave (reg, info, 1));
15005 /* Get the old lr if we saved it. */
15006 if (info->lr_save_p)
15008 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
15009 info->lr_save_offset + sp_offset);
15011 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
15014 /* Get the old cr if we saved it. */
15015 if (info->cr_save_p)
15017 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15018 GEN_INT (info->cr_save_offset + sp_offset));
15019 rtx mem = gen_frame_mem (SImode, addr);
15021 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
15024 /* Set LR here to try to overlap restores below. */
15025 if (info->lr_save_p)
15026 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
15027 gen_rtx_REG (Pmode, 0));
15029 /* Load exception handler data registers, if needed. */
15030 if (current_function_calls_eh_return)
15032 unsigned int i, regno;
15036 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15037 GEN_INT (sp_offset + 5 * reg_size));
15038 rtx mem = gen_frame_mem (reg_mode, addr);
15040 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
15047 regno = EH_RETURN_DATA_REGNO (i);
15048 if (regno == INVALID_REGNUM)
15051 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
15052 info->ehrd_offset + sp_offset
15053 + reg_size * (int) i);
15055 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
15059 /* Restore GPRs. This is done as a PARALLEL if we are using
15060 the load-multiple instructions. */
15061 if (using_load_multiple)
15064 p = rtvec_alloc (32 - info->first_gp_reg_save);
15065 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15067 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15068 GEN_INT (info->gp_save_offset
15071 rtx mem = gen_frame_mem (reg_mode, addr);
15074 gen_rtx_SET (VOIDmode,
15075 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15078 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15081 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15082 if ((regs_ever_live[info->first_gp_reg_save + i]
15083 && (!call_used_regs[info->first_gp_reg_save + i]
15084 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
15085 && TARGET_TOC && TARGET_MINIMAL_TOC)))
15086 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
15087 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
15088 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
15090 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15091 GEN_INT (info->gp_save_offset
15094 rtx mem = gen_frame_mem (reg_mode, addr);
15096 /* Restore 64-bit quantities for SPE. */
15097 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15099 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
15102 if (!SPE_CONST_OFFSET_OK (offset))
15104 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
15105 emit_move_insn (b, GEN_INT (offset));
15108 b = GEN_INT (offset);
15110 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
15111 mem = gen_frame_mem (V2SImode, addr);
15114 emit_move_insn (gen_rtx_REG (reg_mode,
15115 info->first_gp_reg_save + i), mem);
15118 /* Restore fpr's if we need to do it without calling a function. */
15119 if (restoring_FPRs_inline)
15120 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15121 if ((regs_ever_live[info->first_fp_reg_save+i]
15122 && ! call_used_regs[info->first_fp_reg_save+i]))
15125 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15126 GEN_INT (info->fp_save_offset
15129 mem = gen_frame_mem (DFmode, addr);
15131 emit_move_insn (gen_rtx_REG (DFmode,
15132 info->first_fp_reg_save + i),
15136 /* If we saved cr, restore it here. Just those that were used. */
15137 if (info->cr_save_p)
15139 rtx r12_rtx = gen_rtx_REG (SImode, 12);
15142 if (using_mfcr_multiple)
15144 for (i = 0; i < 8; i++)
15145 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15147 gcc_assert (count);
15150 if (using_mfcr_multiple && count > 1)
15155 p = rtvec_alloc (count);
15158 for (i = 0; i < 8; i++)
15159 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15161 rtvec r = rtvec_alloc (2);
15162 RTVEC_ELT (r, 0) = r12_rtx;
15163 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
15164 RTVEC_ELT (p, ndx) =
15165 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
15166 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
15169 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15170 gcc_assert (ndx == count);
15173 for (i = 0; i < 8; i++)
15174 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15176 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
15182 /* If this is V.4, unwind the stack pointer after all of the loads
15184 if (frame_reg_rtx != sp_reg_rtx)
15186 /* This blockage is needed so that sched doesn't decide to move
15187 the sp change before the register restores. */
15188 rs6000_emit_stack_tie ();
15189 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15191 else if (sp_offset != 0)
15192 emit_insn (TARGET_32BIT
15193 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15194 GEN_INT (sp_offset))
15195 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15196 GEN_INT (sp_offset)));
15198 if (current_function_calls_eh_return)
15200 rtx sa = EH_RETURN_STACKADJ_RTX;
15201 emit_insn (TARGET_32BIT
15202 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
15203 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
15209 if (! restoring_FPRs_inline)
15210 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
15212 p = rtvec_alloc (2);
15214 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15215 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15216 gen_rtx_REG (Pmode,
15217 LINK_REGISTER_REGNUM));
15219 /* If we have to restore more than two FP registers, branch to the
15220 restore function. It will return to our caller. */
15221 if (! restoring_FPRs_inline)
15225 const char *alloc_rname;
15227 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15228 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15229 alloc_rname = ggc_strdup (rname);
15230 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15231 gen_rtx_SYMBOL_REF (Pmode,
15234 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15237 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15238 GEN_INT (info->fp_save_offset + 8*i));
15239 mem = gen_frame_mem (DFmode, addr);
15241 RTVEC_ELT (p, i+3) =
15242 gen_rtx_SET (VOIDmode,
15243 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15248 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15252 /* Write function epilogue. */
15255 rs6000_output_function_epilogue (FILE *file,
15256 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15258 if (! HAVE_epilogue)
15260 rtx insn = get_last_insn ();
15261 /* If the last insn was a BARRIER, we don't have to write anything except
15262 the trace table. */
15263 if (GET_CODE (insn) == NOTE)
15264 insn = prev_nonnote_insn (insn);
15265 if (insn == 0 || GET_CODE (insn) != BARRIER)
15267 /* This is slightly ugly, but at least we don't have two
15268 copies of the epilogue-emitting code. */
15271 /* A NOTE_INSN_DELETED is supposed to be at the start
15272 and end of the "toplevel" insn chain. */
15273 emit_note (NOTE_INSN_DELETED);
15274 rs6000_emit_epilogue (FALSE);
15275 emit_note (NOTE_INSN_DELETED);
15277 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15281 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15283 INSN_ADDRESSES_NEW (insn, addr);
15288 if (TARGET_DEBUG_STACK)
15289 debug_rtx_list (get_insns (), 100);
15290 final (get_insns (), file, FALSE);
15296 macho_branch_islands ();
15297 /* Mach-O doesn't support labels at the end of objects, so if
15298 it looks like we might want one, insert a NOP. */
15300 rtx insn = get_last_insn ();
15303 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
15304 insn = PREV_INSN (insn);
15308 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
15309 fputs ("\tnop\n", file);
15313 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15316 We don't output a traceback table if -finhibit-size-directive was
15317 used. The documentation for -finhibit-size-directive reads
15318 ``don't output a @code{.size} assembler directive, or anything
15319 else that would cause trouble if the function is split in the
15320 middle, and the two halves are placed at locations far apart in
15321 memory.'' The traceback table has this property, since it
15322 includes the offset from the start of the function to the
15323 traceback table itself.
15325 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15326 different traceback table. */
15327 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15328 && rs6000_traceback != traceback_none && !current_function_is_thunk)
15330 const char *fname = NULL;
15331 const char *language_string = lang_hooks.name;
15332 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15334 int optional_tbtab;
15335 rs6000_stack_t *info = rs6000_stack_info ();
15337 if (rs6000_traceback == traceback_full)
15338 optional_tbtab = 1;
15339 else if (rs6000_traceback == traceback_part)
15340 optional_tbtab = 0;
15342 optional_tbtab = !optimize_size && !TARGET_ELF;
15344 if (optional_tbtab)
15346 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15347 while (*fname == '.') /* V.4 encodes . in the name */
15350 /* Need label immediately before tbtab, so we can compute
15351 its offset from the function start. */
15352 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15353 ASM_OUTPUT_LABEL (file, fname);
15356 /* The .tbtab pseudo-op can only be used for the first eight
15357 expressions, since it can't handle the possibly variable
15358 length fields that follow. However, if you omit the optional
15359 fields, the assembler outputs zeros for all optional fields
15360 anyways, giving each variable length field is minimum length
15361 (as defined in sys/debug.h). Thus we can not use the .tbtab
15362 pseudo-op at all. */
15364 /* An all-zero word flags the start of the tbtab, for debuggers
15365 that have to find it by searching forward from the entry
15366 point or from the current pc. */
15367 fputs ("\t.long 0\n", file);
15369 /* Tbtab format type. Use format type 0. */
15370 fputs ("\t.byte 0,", file);
15372 /* Language type. Unfortunately, there does not seem to be any
15373 official way to discover the language being compiled, so we
15374 use language_string.
15375 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15376 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
15377 a number, so for now use 9. */
15378 if (! strcmp (language_string, "GNU C"))
15380 else if (! strcmp (language_string, "GNU F77")
15381 || ! strcmp (language_string, "GNU F95"))
15383 else if (! strcmp (language_string, "GNU Pascal"))
15385 else if (! strcmp (language_string, "GNU Ada"))
15387 else if (! strcmp (language_string, "GNU C++")
15388 || ! strcmp (language_string, "GNU Objective-C++"))
15390 else if (! strcmp (language_string, "GNU Java"))
15392 else if (! strcmp (language_string, "GNU Objective-C"))
15395 gcc_unreachable ();
15396 fprintf (file, "%d,", i);
15398 /* 8 single bit fields: global linkage (not set for C extern linkage,
15399 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15400 from start of procedure stored in tbtab, internal function, function
15401 has controlled storage, function has no toc, function uses fp,
15402 function logs/aborts fp operations. */
15403 /* Assume that fp operations are used if any fp reg must be saved. */
15404 fprintf (file, "%d,",
15405 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15407 /* 6 bitfields: function is interrupt handler, name present in
15408 proc table, function calls alloca, on condition directives
15409 (controls stack walks, 3 bits), saves condition reg, saves
15411 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15412 set up as a frame pointer, even when there is no alloca call. */
15413 fprintf (file, "%d,",
15414 ((optional_tbtab << 6)
15415 | ((optional_tbtab & frame_pointer_needed) << 5)
15416 | (info->cr_save_p << 1)
15417 | (info->lr_save_p)));
15419 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15421 fprintf (file, "%d,",
15422 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15424 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15425 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15427 if (optional_tbtab)
15429 /* Compute the parameter info from the function decl argument
15432 int next_parm_info_bit = 31;
15434 for (decl = DECL_ARGUMENTS (current_function_decl);
15435 decl; decl = TREE_CHAIN (decl))
15437 rtx parameter = DECL_INCOMING_RTL (decl);
15438 enum machine_mode mode = GET_MODE (parameter);
15440 if (GET_CODE (parameter) == REG)
15442 if (SCALAR_FLOAT_MODE_P (mode))
15460 gcc_unreachable ();
15463 /* If only one bit will fit, don't or in this entry. */
15464 if (next_parm_info_bit > 0)
15465 parm_info |= (bits << (next_parm_info_bit - 1));
15466 next_parm_info_bit -= 2;
15470 fixed_parms += ((GET_MODE_SIZE (mode)
15471 + (UNITS_PER_WORD - 1))
15473 next_parm_info_bit -= 1;
15479 /* Number of fixed point parameters. */
15480 /* This is actually the number of words of fixed point parameters; thus
15481 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15482 fprintf (file, "%d,", fixed_parms);
15484 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15486 /* This is actually the number of fp registers that hold parameters;
15487 and thus the maximum value is 13. */
15488 /* Set parameters on stack bit if parameters are not in their original
15489 registers, regardless of whether they are on the stack? Xlc
15490 seems to set the bit when not optimizing. */
15491 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15493 if (! optional_tbtab)
15496 /* Optional fields follow. Some are variable length. */
15498 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15499 11 double float. */
15500 /* There is an entry for each parameter in a register, in the order that
15501 they occur in the parameter list. Any intervening arguments on the
15502 stack are ignored. If the list overflows a long (max possible length
15503 34 bits) then completely leave off all elements that don't fit. */
15504 /* Only emit this long if there was at least one parameter. */
15505 if (fixed_parms || float_parms)
15506 fprintf (file, "\t.long %d\n", parm_info);
15508 /* Offset from start of code to tb table. */
15509 fputs ("\t.long ", file);
15510 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15512 RS6000_OUTPUT_BASENAME (file, fname);
15514 assemble_name (file, fname);
15516 rs6000_output_function_entry (file, fname);
15519 /* Interrupt handler mask. */
15520 /* Omit this long, since we never set the interrupt handler bit
15523 /* Number of CTL (controlled storage) anchors. */
15524 /* Omit this long, since the has_ctl bit is never set above. */
15526 /* Displacement into stack of each CTL anchor. */
15527 /* Omit this list of longs, because there are no CTL anchors. */
15529 /* Length of function name. */
15532 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15534 /* Function name. */
15535 assemble_string (fname, strlen (fname));
15537 /* Register for alloca automatic storage; this is always reg 31.
15538 Only emit this if the alloca bit was set above. */
15539 if (frame_pointer_needed)
15540 fputs ("\t.byte 31\n", file);
15542 fputs ("\t.align 2\n", file);
15546 /* A C compound statement that outputs the assembler code for a thunk
15547 function, used to implement C++ virtual function calls with
15548 multiple inheritance. The thunk acts as a wrapper around a virtual
15549 function, adjusting the implicit object parameter before handing
15550 control off to the real function.
15552 First, emit code to add the integer DELTA to the location that
15553 contains the incoming first argument. Assume that this argument
15554 contains a pointer, and is the one used to pass the `this' pointer
15555 in C++. This is the incoming argument *before* the function
15556 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15557 values of all other incoming arguments.
15559 After the addition, emit code to jump to FUNCTION, which is a
15560 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15561 not touch the return address. Hence returning from FUNCTION will
15562 return to whoever called the current `thunk'.
15564 The effect must be as if FUNCTION had been called directly with the
15565 adjusted first argument. This macro is responsible for emitting
15566 all of the code for a thunk function; output_function_prologue()
15567 and output_function_epilogue() are not invoked.
15569 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15570 been extracted from it.) It might possibly be useful on some
15571 targets, but probably not.
15573 If you do not define this macro, the target-independent code in the
15574 C++ frontend will generate a less efficient heavyweight thunk that
15575 calls FUNCTION instead of jumping to it. The generic approach does
15576 not support varargs. */
15579 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15580 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15583 rtx this, insn, funexp;
15585 reload_completed = 1;
15586 epilogue_completed = 1;
15587 no_new_pseudos = 1;
15588 reset_block_changes ();
15590 /* Mark the end of the (empty) prologue. */
15591 emit_note (NOTE_INSN_PROLOGUE_END);
15593 /* Find the "this" pointer. If the function returns a structure,
15594 the structure return pointer is in r3. */
15595 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15596 this = gen_rtx_REG (Pmode, 4);
15598 this = gen_rtx_REG (Pmode, 3);
15600 /* Apply the constant offset, if required. */
15603 rtx delta_rtx = GEN_INT (delta);
15604 emit_insn (TARGET_32BIT
15605 ? gen_addsi3 (this, this, delta_rtx)
15606 : gen_adddi3 (this, this, delta_rtx));
15609 /* Apply the offset from the vtable, if required. */
15612 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15613 rtx tmp = gen_rtx_REG (Pmode, 12);
15615 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
15616 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15618 emit_insn (TARGET_32BIT
15619 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
15620 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
15621 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15625 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15627 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15629 emit_insn (TARGET_32BIT
15630 ? gen_addsi3 (this, this, tmp)
15631 : gen_adddi3 (this, this, tmp));
15634 /* Generate a tail call to the target function. */
15635 if (!TREE_USED (function))
15637 assemble_external (function);
15638 TREE_USED (function) = 1;
15640 funexp = XEXP (DECL_RTL (function), 0);
15641 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15644 if (MACHOPIC_INDIRECT)
15645 funexp = machopic_indirect_call_target (funexp);
15648 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15649 generate sibcall RTL explicitly. */
15650 insn = emit_call_insn (
15651 gen_rtx_PARALLEL (VOIDmode,
15653 gen_rtx_CALL (VOIDmode,
15654 funexp, const0_rtx),
15655 gen_rtx_USE (VOIDmode, const0_rtx),
15656 gen_rtx_USE (VOIDmode,
15657 gen_rtx_REG (SImode,
15658 LINK_REGISTER_REGNUM)),
15659 gen_rtx_RETURN (VOIDmode))));
15660 SIBLING_CALL_P (insn) = 1;
15663 /* Run just enough of rest_of_compilation to get the insns emitted.
15664 There's not really enough bulk here to make other passes such as
15665 instruction scheduling worth while. Note that use_thunk calls
15666 assemble_start_function and assemble_end_function. */
15667 insn = get_insns ();
15668 insn_locators_initialize ();
15669 shorten_branches (insn);
15670 final_start_function (insn, file, 1);
15671 final (insn, file, 1);
15672 final_end_function ();
15674 reload_completed = 0;
15675 epilogue_completed = 0;
15676 no_new_pseudos = 0;
15679 /* A quick summary of the various types of 'constant-pool tables'
15682 Target Flags Name One table per
15683 AIX (none) AIX TOC object file
15684 AIX -mfull-toc AIX TOC object file
15685 AIX -mminimal-toc AIX minimal TOC translation unit
15686 SVR4/EABI (none) SVR4 SDATA object file
15687 SVR4/EABI -fpic SVR4 pic object file
15688 SVR4/EABI -fPIC SVR4 PIC translation unit
15689 SVR4/EABI -mrelocatable EABI TOC function
15690 SVR4/EABI -maix AIX TOC object file
15691 SVR4/EABI -maix -mminimal-toc
15692 AIX minimal TOC translation unit
15694 Name Reg. Set by entries contains:
15695 made by addrs? fp? sum?
15697 AIX TOC 2 crt0 as Y option option
15698 AIX minimal TOC 30 prolog gcc Y Y option
15699 SVR4 SDATA 13 crt0 gcc N Y N
15700 SVR4 pic 30 prolog ld Y not yet N
15701 SVR4 PIC 30 prolog gcc Y option option
15702 EABI TOC 30 prolog gcc Y option option
15706 /* Hash functions for the hash table. */
15709 rs6000_hash_constant (rtx k)
15711 enum rtx_code code = GET_CODE (k);
15712 enum machine_mode mode = GET_MODE (k);
15713 unsigned result = (code << 3) ^ mode;
15714 const char *format;
15717 format = GET_RTX_FORMAT (code);
15718 flen = strlen (format);
15724 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15727 if (mode != VOIDmode)
15728 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15740 for (; fidx < flen; fidx++)
15741 switch (format[fidx])
15746 const char *str = XSTR (k, fidx);
15747 len = strlen (str);
15748 result = result * 613 + len;
15749 for (i = 0; i < len; i++)
15750 result = result * 613 + (unsigned) str[i];
15755 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15759 result = result * 613 + (unsigned) XINT (k, fidx);
15762 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15763 result = result * 613 + (unsigned) XWINT (k, fidx);
15767 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
15768 result = result * 613 + (unsigned) (XWINT (k, fidx)
15775 gcc_unreachable ();
15782 toc_hash_function (const void *hash_entry)
15784 const struct toc_hash_struct *thc =
15785 (const struct toc_hash_struct *) hash_entry;
15786 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15789 /* Compare H1 and H2 for equivalence. */
15792 toc_hash_eq (const void *h1, const void *h2)
15794 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
15795 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
15797 if (((const struct toc_hash_struct *) h1)->key_mode
15798 != ((const struct toc_hash_struct *) h2)->key_mode)
15801 return rtx_equal_p (r1, r2);
15804 /* These are the names given by the C++ front-end to vtables, and
15805 vtable-like objects. Ideally, this logic should not be here;
15806 instead, there should be some programmatic way of inquiring as
15807 to whether or not an object is a vtable. */
15809 #define VTABLE_NAME_P(NAME) \
15810 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
15811 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15812 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15813 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15814 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15817 rs6000_output_symbol_ref (FILE *file, rtx x)
15819 /* Currently C++ toc references to vtables can be emitted before it
15820 is decided whether the vtable is public or private. If this is
15821 the case, then the linker will eventually complain that there is
15822 a reference to an unknown section. Thus, for vtables only,
15823 we emit the TOC reference to reference the symbol and not the
15825 const char *name = XSTR (x, 0);
15827 if (VTABLE_NAME_P (name))
15829 RS6000_OUTPUT_BASENAME (file, name);
15832 assemble_name (file, name);
15835 /* Output a TOC entry. We derive the entry name from what is being
15839 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
15842 const char *name = buf;
15843 const char *real_name;
15845 HOST_WIDE_INT offset = 0;
15847 gcc_assert (!TARGET_NO_TOC);
15849 /* When the linker won't eliminate them, don't output duplicate
15850 TOC entries (this happens on AIX if there is any kind of TOC,
15851 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15853 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15855 struct toc_hash_struct *h;
15858 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15859 time because GGC is not initialized at that point. */
15860 if (toc_hash_table == NULL)
15861 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15862 toc_hash_eq, NULL);
15864 h = ggc_alloc (sizeof (*h));
15866 h->key_mode = mode;
15867 h->labelno = labelno;
15869 found = htab_find_slot (toc_hash_table, h, 1);
15870 if (*found == NULL)
15872 else /* This is indeed a duplicate.
15873 Set this label equal to that label. */
15875 fputs ("\t.set ", file);
15876 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15877 fprintf (file, "%d,", labelno);
15878 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15879 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15885 /* If we're going to put a double constant in the TOC, make sure it's
15886 aligned properly when strict alignment is on. */
15887 if (GET_CODE (x) == CONST_DOUBLE
15888 && STRICT_ALIGNMENT
15889 && GET_MODE_BITSIZE (mode) >= 64
15890 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15891 ASM_OUTPUT_ALIGN (file, 3);
15894 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15896 /* Handle FP constants specially. Note that if we have a minimal
15897 TOC, things we put here aren't actually in the TOC, so we can allow
15899 if (GET_CODE (x) == CONST_DOUBLE &&
15900 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
15902 REAL_VALUE_TYPE rv;
15905 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15906 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15907 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
15909 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15913 if (TARGET_MINIMAL_TOC)
15914 fputs (DOUBLE_INT_ASM_OP, file);
15916 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15917 k[0] & 0xffffffff, k[1] & 0xffffffff,
15918 k[2] & 0xffffffff, k[3] & 0xffffffff);
15919 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15920 k[0] & 0xffffffff, k[1] & 0xffffffff,
15921 k[2] & 0xffffffff, k[3] & 0xffffffff);
15926 if (TARGET_MINIMAL_TOC)
15927 fputs ("\t.long ", file);
15929 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15930 k[0] & 0xffffffff, k[1] & 0xffffffff,
15931 k[2] & 0xffffffff, k[3] & 0xffffffff);
15932 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15933 k[0] & 0xffffffff, k[1] & 0xffffffff,
15934 k[2] & 0xffffffff, k[3] & 0xffffffff);
15938 else if (GET_CODE (x) == CONST_DOUBLE &&
15939 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
15941 REAL_VALUE_TYPE rv;
15944 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15946 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15947 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
15949 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
15953 if (TARGET_MINIMAL_TOC)
15954 fputs (DOUBLE_INT_ASM_OP, file);
15956 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15957 k[0] & 0xffffffff, k[1] & 0xffffffff);
15958 fprintf (file, "0x%lx%08lx\n",
15959 k[0] & 0xffffffff, k[1] & 0xffffffff);
15964 if (TARGET_MINIMAL_TOC)
15965 fputs ("\t.long ", file);
15967 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15968 k[0] & 0xffffffff, k[1] & 0xffffffff);
15969 fprintf (file, "0x%lx,0x%lx\n",
15970 k[0] & 0xffffffff, k[1] & 0xffffffff);
15974 else if (GET_CODE (x) == CONST_DOUBLE &&
15975 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
15977 REAL_VALUE_TYPE rv;
15980 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15981 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15982 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
15984 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15988 if (TARGET_MINIMAL_TOC)
15989 fputs (DOUBLE_INT_ASM_OP, file);
15991 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15992 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
15997 if (TARGET_MINIMAL_TOC)
15998 fputs ("\t.long ", file);
16000 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16001 fprintf (file, "0x%lx\n", l & 0xffffffff);
16005 else if (GET_MODE (x) == VOIDmode
16006 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
16008 unsigned HOST_WIDE_INT low;
16009 HOST_WIDE_INT high;
16011 if (GET_CODE (x) == CONST_DOUBLE)
16013 low = CONST_DOUBLE_LOW (x);
16014 high = CONST_DOUBLE_HIGH (x);
16017 #if HOST_BITS_PER_WIDE_INT == 32
16020 high = (low & 0x80000000) ? ~0 : 0;
16024 low = INTVAL (x) & 0xffffffff;
16025 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
16029 /* TOC entries are always Pmode-sized, but since this
16030 is a bigendian machine then if we're putting smaller
16031 integer constants in the TOC we have to pad them.
16032 (This is still a win over putting the constants in
16033 a separate constant pool, because then we'd have
16034 to have both a TOC entry _and_ the actual constant.)
16036 For a 32-bit target, CONST_INT values are loaded and shifted
16037 entirely within `low' and can be stored in one TOC entry. */
16039 /* It would be easy to make this work, but it doesn't now. */
16040 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
16042 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
16044 #if HOST_BITS_PER_WIDE_INT == 32
16045 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
16046 POINTER_SIZE, &low, &high, 0);
16049 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
16050 high = (HOST_WIDE_INT) low >> 32;
16057 if (TARGET_MINIMAL_TOC)
16058 fputs (DOUBLE_INT_ASM_OP, file);
16060 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16061 (long) high & 0xffffffff, (long) low & 0xffffffff);
16062 fprintf (file, "0x%lx%08lx\n",
16063 (long) high & 0xffffffff, (long) low & 0xffffffff);
16068 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
16070 if (TARGET_MINIMAL_TOC)
16071 fputs ("\t.long ", file);
16073 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16074 (long) high & 0xffffffff, (long) low & 0xffffffff);
16075 fprintf (file, "0x%lx,0x%lx\n",
16076 (long) high & 0xffffffff, (long) low & 0xffffffff);
16080 if (TARGET_MINIMAL_TOC)
16081 fputs ("\t.long ", file);
16083 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
16084 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
16090 if (GET_CODE (x) == CONST)
16092 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
16094 base = XEXP (XEXP (x, 0), 0);
16095 offset = INTVAL (XEXP (XEXP (x, 0), 1));
16098 switch (GET_CODE (base))
16101 name = XSTR (base, 0);
16105 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
16106 CODE_LABEL_NUMBER (XEXP (base, 0)));
16110 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
16114 gcc_unreachable ();
16117 real_name = (*targetm.strip_name_encoding) (name);
16118 if (TARGET_MINIMAL_TOC)
16119 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
16122 fprintf (file, "\t.tc %s", real_name);
16125 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
16127 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
16129 fputs ("[TC],", file);
16132 /* Currently C++ toc references to vtables can be emitted before it
16133 is decided whether the vtable is public or private. If this is
16134 the case, then the linker will eventually complain that there is
16135 a TOC reference to an unknown section. Thus, for vtables only,
16136 we emit the TOC reference to reference the symbol and not the
16138 if (VTABLE_NAME_P (name))
16140 RS6000_OUTPUT_BASENAME (file, name);
16142 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16143 else if (offset > 0)
16144 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
16147 output_addr_const (file, x);
16151 /* Output an assembler pseudo-op to write an ASCII string of N characters
16152 starting at P to FILE.
16154 On the RS/6000, we have to do this using the .byte operation and
16155 write out special characters outside the quoted string.
16156 Also, the assembler is broken; very long strings are truncated,
16157 so we must artificially break them up early. */
16160 output_ascii (FILE *file, const char *p, int n)
16163 int i, count_string;
16164 const char *for_string = "\t.byte \"";
16165 const char *for_decimal = "\t.byte ";
16166 const char *to_close = NULL;
16169 for (i = 0; i < n; i++)
16172 if (c >= ' ' && c < 0177)
16175 fputs (for_string, file);
16178 /* Write two quotes to get one. */
16186 for_decimal = "\"\n\t.byte ";
16190 if (count_string >= 512)
16192 fputs (to_close, file);
16194 for_string = "\t.byte \"";
16195 for_decimal = "\t.byte ";
16203 fputs (for_decimal, file);
16204 fprintf (file, "%d", c);
16206 for_string = "\n\t.byte \"";
16207 for_decimal = ", ";
16213 /* Now close the string if we have written one. Then end the line. */
16215 fputs (to_close, file);
16218 /* Generate a unique section name for FILENAME for a section type
16219 represented by SECTION_DESC. Output goes into BUF.
16221 SECTION_DESC can be any string, as long as it is different for each
16222 possible section type.
16224 We name the section in the same manner as xlc. The name begins with an
16225 underscore followed by the filename (after stripping any leading directory
16226 names) with the last period replaced by the string SECTION_DESC. If
16227 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16231 rs6000_gen_section_name (char **buf, const char *filename,
16232 const char *section_desc)
16234 const char *q, *after_last_slash, *last_period = 0;
16238 after_last_slash = filename;
16239 for (q = filename; *q; q++)
16242 after_last_slash = q + 1;
16243 else if (*q == '.')
16247 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16248 *buf = (char *) xmalloc (len);
16253 for (q = after_last_slash; *q; q++)
16255 if (q == last_period)
16257 strcpy (p, section_desc);
16258 p += strlen (section_desc);
16262 else if (ISALNUM (*q))
16266 if (last_period == 0)
16267 strcpy (p, section_desc);
16272 /* Emit profile function. */
16275 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16277 /* Non-standard profiling for kernels, which just saves LR then calls
16278 _mcount without worrying about arg saves. The idea is to change
16279 the function prologue as little as possible as it isn't easy to
16280 account for arg save/restore code added just for _mcount. */
16281 if (TARGET_PROFILE_KERNEL)
16284 if (DEFAULT_ABI == ABI_AIX)
16286 #ifndef NO_PROFILE_COUNTERS
16287 # define NO_PROFILE_COUNTERS 0
16289 if (NO_PROFILE_COUNTERS)
16290 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16294 const char *label_name;
16297 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16298 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16299 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16301 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16305 else if (DEFAULT_ABI == ABI_DARWIN)
16307 const char *mcount_name = RS6000_MCOUNT;
16308 int caller_addr_regno = LINK_REGISTER_REGNUM;
16310 /* Be conservative and always set this, at least for now. */
16311 current_function_uses_pic_offset_table = 1;
16314 /* For PIC code, set up a stub and collect the caller's address
16315 from r0, which is where the prologue puts it. */
16316 if (MACHOPIC_INDIRECT
16317 && current_function_uses_pic_offset_table)
16318 caller_addr_regno = 0;
16320 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16322 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16326 /* Write function profiler code. */
16329 output_function_profiler (FILE *file, int labelno)
16333 switch (DEFAULT_ABI)
16336 gcc_unreachable ();
16341 warning (0, "no profiling of 64-bit code for this ABI");
16344 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16345 fprintf (file, "\tmflr %s\n", reg_names[0]);
16346 if (NO_PROFILE_COUNTERS)
16348 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16349 reg_names[0], reg_names[1]);
16351 else if (TARGET_SECURE_PLT && flag_pic)
16353 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16354 reg_names[0], reg_names[1]);
16355 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16356 asm_fprintf (file, "\t{cau|addis} %s,%s,",
16357 reg_names[12], reg_names[12]);
16358 assemble_name (file, buf);
16359 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
16360 assemble_name (file, buf);
16361 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
16363 else if (flag_pic == 1)
16365 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16366 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16367 reg_names[0], reg_names[1]);
16368 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16369 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16370 assemble_name (file, buf);
16371 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16373 else if (flag_pic > 1)
16375 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16376 reg_names[0], reg_names[1]);
16377 /* Now, we need to get the address of the label. */
16378 fputs ("\tbcl 20,31,1f\n\t.long ", file);
16379 assemble_name (file, buf);
16380 fputs ("-.\n1:", file);
16381 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16382 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16383 reg_names[0], reg_names[11]);
16384 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16385 reg_names[0], reg_names[0], reg_names[11]);
16389 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16390 assemble_name (file, buf);
16391 fputs ("@ha\n", file);
16392 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16393 reg_names[0], reg_names[1]);
16394 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16395 assemble_name (file, buf);
16396 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16399 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16400 fprintf (file, "\tbl %s%s\n",
16401 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16406 if (!TARGET_PROFILE_KERNEL)
16408 /* Don't do anything, done in output_profile_hook (). */
16412 gcc_assert (!TARGET_32BIT);
16414 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16415 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16417 if (cfun->static_chain_decl != NULL)
16419 asm_fprintf (file, "\tstd %s,24(%s)\n",
16420 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16421 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16422 asm_fprintf (file, "\tld %s,24(%s)\n",
16423 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16426 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16433 /* Power4 load update and store update instructions are cracked into a
16434 load or store and an integer insn which are executed in the same cycle.
16435 Branches have their own dispatch slot which does not count against the
16436 GCC issue rate, but it changes the program flow so there are no other
16437 instructions to issue in this cycle. */
16440 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16441 int verbose ATTRIBUTE_UNUSED,
16442 rtx insn, int more)
16444 if (GET_CODE (PATTERN (insn)) == USE
16445 || GET_CODE (PATTERN (insn)) == CLOBBER)
16448 if (rs6000_sched_groups)
16450 if (is_microcoded_insn (insn))
16452 else if (is_cracked_insn (insn))
16453 return more > 2 ? more - 2 : 0;
16459 /* Adjust the cost of a scheduling dependency. Return the new cost of
16460 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16463 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16465 if (! recog_memoized (insn))
16468 if (REG_NOTE_KIND (link) != 0)
16471 if (REG_NOTE_KIND (link) == 0)
16473 /* Data dependency; DEP_INSN writes a register that INSN reads
16474 some cycles later. */
16476 /* Separate a load from a narrower, dependent store. */
16477 if (rs6000_sched_groups
16478 && GET_CODE (PATTERN (insn)) == SET
16479 && GET_CODE (PATTERN (dep_insn)) == SET
16480 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16481 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16482 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16483 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16486 switch (get_attr_type (insn))
16489 /* Tell the first scheduling pass about the latency between
16490 a mtctr and bctr (and mtlr and br/blr). The first
16491 scheduling pass will not know about this latency since
16492 the mtctr instruction, which has the latency associated
16493 to it, will be generated by reload. */
16494 return TARGET_POWER ? 5 : 4;
16496 /* Leave some extra cycles between a compare and its
16497 dependent branch, to inhibit expensive mispredicts. */
16498 if ((rs6000_cpu_attr == CPU_PPC603
16499 || rs6000_cpu_attr == CPU_PPC604
16500 || rs6000_cpu_attr == CPU_PPC604E
16501 || rs6000_cpu_attr == CPU_PPC620
16502 || rs6000_cpu_attr == CPU_PPC630
16503 || rs6000_cpu_attr == CPU_PPC750
16504 || rs6000_cpu_attr == CPU_PPC7400
16505 || rs6000_cpu_attr == CPU_PPC7450
16506 || rs6000_cpu_attr == CPU_POWER4
16507 || rs6000_cpu_attr == CPU_POWER5)
16508 && recog_memoized (dep_insn)
16509 && (INSN_CODE (dep_insn) >= 0)
16510 && (get_attr_type (dep_insn) == TYPE_CMP
16511 || get_attr_type (dep_insn) == TYPE_COMPARE
16512 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
16513 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
16514 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
16515 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
16516 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
16517 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
16522 /* Fall out to return default cost. */
16528 /* The function returns a true if INSN is microcoded.
16529 Return false otherwise. */
16532 is_microcoded_insn (rtx insn)
16534 if (!insn || !INSN_P (insn)
16535 || GET_CODE (PATTERN (insn)) == USE
16536 || GET_CODE (PATTERN (insn)) == CLOBBER)
16539 if (rs6000_sched_groups)
16541 enum attr_type type = get_attr_type (insn);
16542 if (type == TYPE_LOAD_EXT_U
16543 || type == TYPE_LOAD_EXT_UX
16544 || type == TYPE_LOAD_UX
16545 || type == TYPE_STORE_UX
16546 || type == TYPE_MFCR)
16553 /* The function returns a nonzero value if INSN can be scheduled only
16554 as the first insn in a dispatch group ("dispatch-slot restricted").
16555 In this case, the returned value indicates how many dispatch slots
16556 the insn occupies (at the beginning of the group).
16557 Return 0 otherwise. */
16560 is_dispatch_slot_restricted (rtx insn)
16562 enum attr_type type;
16564 if (!rs6000_sched_groups)
16568 || insn == NULL_RTX
16569 || GET_CODE (insn) == NOTE
16570 || GET_CODE (PATTERN (insn)) == USE
16571 || GET_CODE (PATTERN (insn)) == CLOBBER)
16574 type = get_attr_type (insn);
16581 case TYPE_DELAYED_CR:
16582 case TYPE_CR_LOGICAL:
16595 if (rs6000_cpu == PROCESSOR_POWER5
16596 && is_cracked_insn (insn))
16602 /* The function returns true if INSN is cracked into 2 instructions
16603 by the processor (and therefore occupies 2 issue slots). */
16606 is_cracked_insn (rtx insn)
16608 if (!insn || !INSN_P (insn)
16609 || GET_CODE (PATTERN (insn)) == USE
16610 || GET_CODE (PATTERN (insn)) == CLOBBER)
16613 if (rs6000_sched_groups)
16615 enum attr_type type = get_attr_type (insn);
16616 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
16617 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
16618 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
16619 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
16620 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
16621 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
16622 || type == TYPE_IDIV || type == TYPE_LDIV
16623 || type == TYPE_INSERT_WORD)
16630 /* The function returns true if INSN can be issued only from
16631 the branch slot. */
16634 is_branch_slot_insn (rtx insn)
16636 if (!insn || !INSN_P (insn)
16637 || GET_CODE (PATTERN (insn)) == USE
16638 || GET_CODE (PATTERN (insn)) == CLOBBER)
16641 if (rs6000_sched_groups)
16643 enum attr_type type = get_attr_type (insn);
16644 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
16652 /* A C statement (sans semicolon) to update the integer scheduling
16653 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16654 INSN earlier, reduce the priority to execute INSN later. Do not
16655 define this macro if you do not need to adjust the scheduling
16656 priorities of insns. */
16659 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
16661 /* On machines (like the 750) which have asymmetric integer units,
16662 where one integer unit can do multiply and divides and the other
16663 can't, reduce the priority of multiply/divide so it is scheduled
16664 before other integer operations. */
16667 if (! INSN_P (insn))
16670 if (GET_CODE (PATTERN (insn)) == USE)
16673 switch (rs6000_cpu_attr) {
16675 switch (get_attr_type (insn))
16682 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
16683 priority, priority);
16684 if (priority >= 0 && priority < 0x01000000)
16691 if (is_dispatch_slot_restricted (insn)
16692 && reload_completed
16693 && current_sched_info->sched_max_insns_priority
16694 && rs6000_sched_restricted_insns_priority)
16697 /* Prioritize insns that can be dispatched only in the first
16699 if (rs6000_sched_restricted_insns_priority == 1)
16700 /* Attach highest priority to insn. This means that in
16701 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16702 precede 'priority' (critical path) considerations. */
16703 return current_sched_info->sched_max_insns_priority;
16704 else if (rs6000_sched_restricted_insns_priority == 2)
16705 /* Increase priority of insn by a minimal amount. This means that in
16706 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16707 considerations precede dispatch-slot restriction considerations. */
16708 return (priority + 1);
16714 /* Return how many instructions the machine can issue per cycle. */
16717 rs6000_issue_rate (void)
16719 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16720 if (!reload_completed)
16723 switch (rs6000_cpu_attr) {
16724 case CPU_RIOS1: /* ? */
16726 case CPU_PPC601: /* ? */
16749 /* Return how many instructions to look ahead for better insn
16753 rs6000_use_sched_lookahead (void)
16755 if (rs6000_cpu_attr == CPU_PPC8540)
16760 /* Determine is PAT refers to memory. */
16763 is_mem_ref (rtx pat)
16769 if (GET_CODE (pat) == MEM)
16772 /* Recursively process the pattern. */
16773 fmt = GET_RTX_FORMAT (GET_CODE (pat));
16775 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
16778 ret |= is_mem_ref (XEXP (pat, i));
16779 else if (fmt[i] == 'E')
16780 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
16781 ret |= is_mem_ref (XVECEXP (pat, i, j));
16787 /* Determine if PAT is a PATTERN of a load insn. */
16790 is_load_insn1 (rtx pat)
16792 if (!pat || pat == NULL_RTX)
16795 if (GET_CODE (pat) == SET)
16796 return is_mem_ref (SET_SRC (pat));
16798 if (GET_CODE (pat) == PARALLEL)
16802 for (i = 0; i < XVECLEN (pat, 0); i++)
16803 if (is_load_insn1 (XVECEXP (pat, 0, i)))
16810 /* Determine if INSN loads from memory. */
16813 is_load_insn (rtx insn)
16815 if (!insn || !INSN_P (insn))
16818 if (GET_CODE (insn) == CALL_INSN)
16821 return is_load_insn1 (PATTERN (insn));
16824 /* Determine if PAT is a PATTERN of a store insn. */
16827 is_store_insn1 (rtx pat)
16829 if (!pat || pat == NULL_RTX)
16832 if (GET_CODE (pat) == SET)
16833 return is_mem_ref (SET_DEST (pat));
16835 if (GET_CODE (pat) == PARALLEL)
16839 for (i = 0; i < XVECLEN (pat, 0); i++)
16840 if (is_store_insn1 (XVECEXP (pat, 0, i)))
16847 /* Determine if INSN stores to memory. */
16850 is_store_insn (rtx insn)
16852 if (!insn || !INSN_P (insn))
16855 return is_store_insn1 (PATTERN (insn));
16858 /* Returns whether the dependence between INSN and NEXT is considered
16859 costly by the given target. */
16862 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
16865 /* If the flag is not enabled - no dependence is considered costly;
16866 allow all dependent insns in the same group.
16867 This is the most aggressive option. */
16868 if (rs6000_sched_costly_dep == no_dep_costly)
16871 /* If the flag is set to 1 - a dependence is always considered costly;
16872 do not allow dependent instructions in the same group.
16873 This is the most conservative option. */
16874 if (rs6000_sched_costly_dep == all_deps_costly)
16877 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16878 && is_load_insn (next)
16879 && is_store_insn (insn))
16880 /* Prevent load after store in the same group. */
16883 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16884 && is_load_insn (next)
16885 && is_store_insn (insn)
16886 && (!link || (int) REG_NOTE_KIND (link) == 0))
16887 /* Prevent load after store in the same group if it is a true
16891 /* The flag is set to X; dependences with latency >= X are considered costly,
16892 and will not be scheduled in the same group. */
16893 if (rs6000_sched_costly_dep <= max_dep_latency
16894 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16900 /* Return the next insn after INSN that is found before TAIL is reached,
16901 skipping any "non-active" insns - insns that will not actually occupy
16902 an issue slot. Return NULL_RTX if such an insn is not found. */
16905 get_next_active_insn (rtx insn, rtx tail)
16907 if (insn == NULL_RTX || insn == tail)
16912 insn = NEXT_INSN (insn);
16913 if (insn == NULL_RTX || insn == tail)
16918 || (NONJUMP_INSN_P (insn)
16919 && GET_CODE (PATTERN (insn)) != USE
16920 && GET_CODE (PATTERN (insn)) != CLOBBER
16921 && INSN_CODE (insn) != CODE_FOR_stack_tie))
16927 /* Return whether the presence of INSN causes a dispatch group termination
16928 of group WHICH_GROUP.
16930 If WHICH_GROUP == current_group, this function will return true if INSN
16931 causes the termination of the current group (i.e, the dispatch group to
16932 which INSN belongs). This means that INSN will be the last insn in the
16933 group it belongs to.
16935 If WHICH_GROUP == previous_group, this function will return true if INSN
16936 causes the termination of the previous group (i.e, the dispatch group that
16937 precedes the group to which INSN belongs). This means that INSN will be
16938 the first insn in the group it belongs to). */
16941 insn_terminates_group_p (rtx insn, enum group_termination which_group)
16943 enum attr_type type;
16948 type = get_attr_type (insn);
16950 if (is_microcoded_insn (insn))
16953 if (which_group == current_group)
16955 if (is_branch_slot_insn (insn))
16959 else if (which_group == previous_group)
16961 if (is_dispatch_slot_restricted (insn))
16969 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16970 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16973 is_costly_group (rtx *group_insns, rtx next_insn)
16978 int issue_rate = rs6000_issue_rate ();
16980 for (i = 0; i < issue_rate; i++)
16982 rtx insn = group_insns[i];
16985 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
16987 rtx next = XEXP (link, 0);
16988 if (next == next_insn)
16990 cost = insn_cost (insn, link, next_insn);
16991 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
17000 /* Utility of the function redefine_groups.
17001 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
17002 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
17003 to keep it "far" (in a separate group) from GROUP_INSNS, following
17004 one of the following schemes, depending on the value of the flag
17005 -minsert_sched_nops = X:
17006 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
17007 in order to force NEXT_INSN into a separate group.
17008 (2) X < sched_finish_regroup_exact: insert exactly X nops.
17009 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
17010 insertion (has a group just ended, how many vacant issue slots remain in the
17011 last group, and how many dispatch groups were encountered so far). */
17014 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
17015 rtx next_insn, bool *group_end, int can_issue_more,
17020 int issue_rate = rs6000_issue_rate ();
17021 bool end = *group_end;
17024 if (next_insn == NULL_RTX)
17025 return can_issue_more;
17027 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
17028 return can_issue_more;
17030 force = is_costly_group (group_insns, next_insn);
17032 return can_issue_more;
17034 if (sched_verbose > 6)
17035 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
17036 *group_count ,can_issue_more);
17038 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
17041 can_issue_more = 0;
17043 /* Since only a branch can be issued in the last issue_slot, it is
17044 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
17045 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
17046 in this case the last nop will start a new group and the branch
17047 will be forced to the new group. */
17048 if (can_issue_more && !is_branch_slot_insn (next_insn))
17051 while (can_issue_more > 0)
17054 emit_insn_before (nop, next_insn);
17062 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
17064 int n_nops = rs6000_sched_insert_nops;
17066 /* Nops can't be issued from the branch slot, so the effective
17067 issue_rate for nops is 'issue_rate - 1'. */
17068 if (can_issue_more == 0)
17069 can_issue_more = issue_rate;
17071 if (can_issue_more == 0)
17073 can_issue_more = issue_rate - 1;
17076 for (i = 0; i < issue_rate; i++)
17078 group_insns[i] = 0;
17085 emit_insn_before (nop, next_insn);
17086 if (can_issue_more == issue_rate - 1) /* new group begins */
17089 if (can_issue_more == 0)
17091 can_issue_more = issue_rate - 1;
17094 for (i = 0; i < issue_rate; i++)
17096 group_insns[i] = 0;
17102 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
17105 /* Is next_insn going to start a new group? */
17108 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
17109 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
17110 || (can_issue_more < issue_rate &&
17111 insn_terminates_group_p (next_insn, previous_group)));
17112 if (*group_end && end)
17115 if (sched_verbose > 6)
17116 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
17117 *group_count, can_issue_more);
17118 return can_issue_more;
17121 return can_issue_more;
17124 /* This function tries to synch the dispatch groups that the compiler "sees"
17125 with the dispatch groups that the processor dispatcher is expected to
17126 form in practice. It tries to achieve this synchronization by forcing the
17127 estimated processor grouping on the compiler (as opposed to the function
17128 'pad_goups' which tries to force the scheduler's grouping on the processor).
17130 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
17131 examines the (estimated) dispatch groups that will be formed by the processor
17132 dispatcher. It marks these group boundaries to reflect the estimated
17133 processor grouping, overriding the grouping that the scheduler had marked.
17134 Depending on the value of the flag '-minsert-sched-nops' this function can
17135 force certain insns into separate groups or force a certain distance between
17136 them by inserting nops, for example, if there exists a "costly dependence"
17139 The function estimates the group boundaries that the processor will form as
17140 follows: It keeps track of how many vacant issue slots are available after
17141 each insn. A subsequent insn will start a new group if one of the following
17143 - no more vacant issue slots remain in the current dispatch group.
17144 - only the last issue slot, which is the branch slot, is vacant, but the next
17145 insn is not a branch.
17146 - only the last 2 or less issue slots, including the branch slot, are vacant,
17147 which means that a cracked insn (which occupies two issue slots) can't be
17148 issued in this group.
17149 - less than 'issue_rate' slots are vacant, and the next insn always needs to
17150 start a new group. */
17153 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
17155 rtx insn, next_insn;
17157 int can_issue_more;
17160 int group_count = 0;
17164 issue_rate = rs6000_issue_rate ();
17165 group_insns = alloca (issue_rate * sizeof (rtx));
17166 for (i = 0; i < issue_rate; i++)
17168 group_insns[i] = 0;
17170 can_issue_more = issue_rate;
17172 insn = get_next_active_insn (prev_head_insn, tail);
17175 while (insn != NULL_RTX)
17177 slot = (issue_rate - can_issue_more);
17178 group_insns[slot] = insn;
17180 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
17181 if (insn_terminates_group_p (insn, current_group))
17182 can_issue_more = 0;
17184 next_insn = get_next_active_insn (insn, tail);
17185 if (next_insn == NULL_RTX)
17186 return group_count + 1;
17188 /* Is next_insn going to start a new group? */
17190 = (can_issue_more == 0
17191 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
17192 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
17193 || (can_issue_more < issue_rate &&
17194 insn_terminates_group_p (next_insn, previous_group)));
17196 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
17197 next_insn, &group_end, can_issue_more,
17203 can_issue_more = 0;
17204 for (i = 0; i < issue_rate; i++)
17206 group_insns[i] = 0;
17210 if (GET_MODE (next_insn) == TImode && can_issue_more)
17211 PUT_MODE (next_insn, VOIDmode);
17212 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
17213 PUT_MODE (next_insn, TImode);
17216 if (can_issue_more == 0)
17217 can_issue_more = issue_rate;
17220 return group_count;
17223 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
17224 dispatch group boundaries that the scheduler had marked. Pad with nops
17225 any dispatch groups which have vacant issue slots, in order to force the
17226 scheduler's grouping on the processor dispatcher. The function
17227 returns the number of dispatch groups found. */
17230 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
17232 rtx insn, next_insn;
17235 int can_issue_more;
17237 int group_count = 0;
17239 /* Initialize issue_rate. */
17240 issue_rate = rs6000_issue_rate ();
17241 can_issue_more = issue_rate;
17243 insn = get_next_active_insn (prev_head_insn, tail);
17244 next_insn = get_next_active_insn (insn, tail);
17246 while (insn != NULL_RTX)
17249 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
17251 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
17253 if (next_insn == NULL_RTX)
17258 /* If the scheduler had marked group termination at this location
17259 (between insn and next_indn), and neither insn nor next_insn will
17260 force group termination, pad the group with nops to force group
17263 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
17264 && !insn_terminates_group_p (insn, current_group)
17265 && !insn_terminates_group_p (next_insn, previous_group))
17267 if (!is_branch_slot_insn (next_insn))
17270 while (can_issue_more)
17273 emit_insn_before (nop, next_insn);
17278 can_issue_more = issue_rate;
17283 next_insn = get_next_active_insn (insn, tail);
17286 return group_count;
17289 /* The following function is called at the end of scheduling BB.
17290 After reload, it inserts nops at insn group bundling. */
17293 rs6000_sched_finish (FILE *dump, int sched_verbose)
17298 fprintf (dump, "=== Finishing schedule.\n");
17300 if (reload_completed && rs6000_sched_groups)
17302 if (rs6000_sched_insert_nops == sched_finish_none)
17305 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
17306 n_groups = pad_groups (dump, sched_verbose,
17307 current_sched_info->prev_head,
17308 current_sched_info->next_tail);
17310 n_groups = redefine_groups (dump, sched_verbose,
17311 current_sched_info->prev_head,
17312 current_sched_info->next_tail);
17314 if (sched_verbose >= 6)
17316 fprintf (dump, "ngroups = %d\n", n_groups);
17317 print_rtl (dump, current_sched_info->prev_head);
17318 fprintf (dump, "Done finish_sched\n");
17323 /* Length in units of the trampoline for entering a nested function. */
17326 rs6000_trampoline_size (void)
17330 switch (DEFAULT_ABI)
17333 gcc_unreachable ();
17336 ret = (TARGET_32BIT) ? 12 : 24;
17341 ret = (TARGET_32BIT) ? 40 : 48;
17348 /* Emit RTL insns to initialize the variable parts of a trampoline.
17349 FNADDR is an RTX for the address of the function's pure code.
17350 CXT is an RTX for the static chain value for the function. */
17353 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
17355 int regsize = (TARGET_32BIT) ? 4 : 8;
17356 rtx ctx_reg = force_reg (Pmode, cxt);
17358 switch (DEFAULT_ABI)
17361 gcc_unreachable ();
17363 /* Macros to shorten the code expansions below. */
17364 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
17365 #define MEM_PLUS(addr,offset) \
17366 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
17368 /* Under AIX, just build the 3 word function descriptor */
17371 rtx fn_reg = gen_reg_rtx (Pmode);
17372 rtx toc_reg = gen_reg_rtx (Pmode);
17373 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
17374 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
17375 emit_move_insn (MEM_DEREF (addr), fn_reg);
17376 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
17377 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
17381 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
17384 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
17385 FALSE, VOIDmode, 4,
17387 GEN_INT (rs6000_trampoline_size ()), SImode,
17397 /* Table of valid machine attributes. */
17399 const struct attribute_spec rs6000_attribute_table[] =
17401 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
17402 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
17403 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17404 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17405 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
17406 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
17407 #ifdef SUBTARGET_ATTRIBUTE_TABLE
17408 SUBTARGET_ATTRIBUTE_TABLE,
17410 { NULL, 0, 0, false, false, false, NULL }
17413 /* Handle the "altivec" attribute. The attribute may have
17414 arguments as follows:
17416 __attribute__((altivec(vector__)))
17417 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
17418 __attribute__((altivec(bool__))) (always followed by 'unsigned')
17420 and may appear more than once (e.g., 'vector bool char') in a
17421 given declaration. */
17424 rs6000_handle_altivec_attribute (tree *node,
17425 tree name ATTRIBUTE_UNUSED,
17427 int flags ATTRIBUTE_UNUSED,
17428 bool *no_add_attrs)
17430 tree type = *node, result = NULL_TREE;
17431 enum machine_mode mode;
17434 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
17435 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
17436 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
17439 while (POINTER_TYPE_P (type)
17440 || TREE_CODE (type) == FUNCTION_TYPE
17441 || TREE_CODE (type) == METHOD_TYPE
17442 || TREE_CODE (type) == ARRAY_TYPE)
17443 type = TREE_TYPE (type);
17445 mode = TYPE_MODE (type);
17447 /* Check for invalid AltiVec type qualifiers. */
17448 if (type == long_unsigned_type_node || type == long_integer_type_node)
17451 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
17452 else if (rs6000_warn_altivec_long)
17453 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
17455 else if (type == long_long_unsigned_type_node
17456 || type == long_long_integer_type_node)
17457 error ("use of %<long long%> in AltiVec types is invalid");
17458 else if (type == double_type_node)
17459 error ("use of %<double%> in AltiVec types is invalid");
17460 else if (type == long_double_type_node)
17461 error ("use of %<long double%> in AltiVec types is invalid");
17462 else if (type == boolean_type_node)
17463 error ("use of boolean types in AltiVec types is invalid");
17464 else if (TREE_CODE (type) == COMPLEX_TYPE)
17465 error ("use of %<complex%> in AltiVec types is invalid");
17466 else if (DECIMAL_FLOAT_MODE_P (mode))
17467 error ("use of decimal floating point types in AltiVec types is invalid");
17469 switch (altivec_type)
17472 unsigned_p = TYPE_UNSIGNED (type);
17476 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
17479 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
17482 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
17484 case SFmode: result = V4SF_type_node; break;
17485 /* If the user says 'vector int bool', we may be handed the 'bool'
17486 attribute _before_ the 'vector' attribute, and so select the
17487 proper type in the 'b' case below. */
17488 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
17496 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
17497 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
17498 case QImode: case V16QImode: result = bool_V16QI_type_node;
17505 case V8HImode: result = pixel_V8HI_type_node;
17511 if (result && result != type && TYPE_READONLY (type))
17512 result = build_qualified_type (result, TYPE_QUAL_CONST);
17514 *no_add_attrs = true; /* No need to hang on to the attribute. */
17517 *node = reconstruct_complex_type (*node, result);
17522 /* AltiVec defines four built-in scalar types that serve as vector
17523 elements; we must teach the compiler how to mangle them. */
17525 static const char *
17526 rs6000_mangle_fundamental_type (tree type)
17528 if (type == bool_char_type_node) return "U6__boolc";
17529 if (type == bool_short_type_node) return "U6__bools";
17530 if (type == pixel_type_node) return "u7__pixel";
17531 if (type == bool_int_type_node) return "U6__booli";
17533 /* Mangle IBM extended float long double as `g' (__float128) on
17534 powerpc*-linux where long-double-64 previously was the default. */
17535 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
17537 && TARGET_LONG_DOUBLE_128
17538 && !TARGET_IEEEQUAD)
17541 /* For all other types, use normal C++ mangling. */
17545 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17546 struct attribute_spec.handler. */
17549 rs6000_handle_longcall_attribute (tree *node, tree name,
17550 tree args ATTRIBUTE_UNUSED,
17551 int flags ATTRIBUTE_UNUSED,
17552 bool *no_add_attrs)
17554 if (TREE_CODE (*node) != FUNCTION_TYPE
17555 && TREE_CODE (*node) != FIELD_DECL
17556 && TREE_CODE (*node) != TYPE_DECL)
17558 warning (OPT_Wattributes, "%qs attribute only applies to functions",
17559 IDENTIFIER_POINTER (name));
17560 *no_add_attrs = true;
17566 /* Set longcall attributes on all functions declared when
17567 rs6000_default_long_calls is true. */
17569 rs6000_set_default_type_attributes (tree type)
17571 if (rs6000_default_long_calls
17572 && (TREE_CODE (type) == FUNCTION_TYPE
17573 || TREE_CODE (type) == METHOD_TYPE))
17574 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
17576 TYPE_ATTRIBUTES (type));
17579 darwin_set_default_type_attributes (type);
17583 /* Return a reference suitable for calling a function with the
17584 longcall attribute. */
17587 rs6000_longcall_ref (rtx call_ref)
17589 const char *call_name;
17592 if (GET_CODE (call_ref) != SYMBOL_REF)
17595 /* System V adds '.' to the internal name, so skip them. */
17596 call_name = XSTR (call_ref, 0);
17597 if (*call_name == '.')
17599 while (*call_name == '.')
17602 node = get_identifier (call_name);
17603 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
17606 return force_reg (Pmode, call_ref);
17609 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
17610 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
17613 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
17614 struct attribute_spec.handler. */
17616 rs6000_handle_struct_attribute (tree *node, tree name,
17617 tree args ATTRIBUTE_UNUSED,
17618 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
17621 if (DECL_P (*node))
17623 if (TREE_CODE (*node) == TYPE_DECL)
17624 type = &TREE_TYPE (*node);
17629 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
17630 || TREE_CODE (*type) == UNION_TYPE)))
17632 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
17633 *no_add_attrs = true;
17636 else if ((is_attribute_p ("ms_struct", name)
17637 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
17638 || ((is_attribute_p ("gcc_struct", name)
17639 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
17641 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
17642 IDENTIFIER_POINTER (name));
17643 *no_add_attrs = true;
17650 rs6000_ms_bitfield_layout_p (tree record_type)
17652 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
17653 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
17654 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
17657 #ifdef USING_ELFOS_H
17659 /* A get_unnamed_section callback, used for switching to toc_section. */
17662 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
17664 if (DEFAULT_ABI == ABI_AIX
17665 && TARGET_MINIMAL_TOC
17666 && !TARGET_RELOCATABLE)
17668 if (!toc_initialized)
17670 toc_initialized = 1;
17671 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17672 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
17673 fprintf (asm_out_file, "\t.tc ");
17674 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
17675 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17676 fprintf (asm_out_file, "\n");
17678 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17679 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17680 fprintf (asm_out_file, " = .+32768\n");
17683 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17685 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
17686 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17689 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17690 if (!toc_initialized)
17692 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17693 fprintf (asm_out_file, " = .+32768\n");
17694 toc_initialized = 1;
17699 /* Implement TARGET_ASM_INIT_SECTIONS. */
17702 rs6000_elf_asm_init_sections (void)
17705 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
17708 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
17709 SDATA2_SECTION_ASM_OP);
17712 /* Implement TARGET_SELECT_RTX_SECTION. */
17715 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
17716 unsigned HOST_WIDE_INT align)
17718 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17719 return toc_section;
17721 return default_elf_select_rtx_section (mode, x, align);
17724 /* Implement TARGET_ASM_SELECT_SECTION for ELF targets. */
17727 rs6000_elf_select_section (tree decl, int reloc,
17728 unsigned HOST_WIDE_INT align)
17730 /* Pretend that we're always building for a shared library when
17731 ABI_AIX, because otherwise we end up with dynamic relocations
17732 in read-only sections. This happens for function pointers,
17733 references to vtables in typeinfo, and probably other cases. */
17734 return default_elf_select_section_1 (decl, reloc, align,
17735 flag_pic || DEFAULT_ABI == ABI_AIX);
17738 /* A C statement to build up a unique section name, expressed as a
17739 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17740 RELOC indicates whether the initial value of EXP requires
17741 link-time relocations. If you do not define this macro, GCC will use
17742 the symbol name prefixed by `.' as the section name. Note - this
17743 macro can now be called for uninitialized data items as well as
17744 initialized data and functions. */
17747 rs6000_elf_unique_section (tree decl, int reloc)
17749 /* As above, pretend that we're always building for a shared library
17750 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
17751 default_unique_section_1 (decl, reloc,
17752 flag_pic || DEFAULT_ABI == ABI_AIX);
17755 /* For a SYMBOL_REF, set generic flags and then perform some
17756 target-specific processing.
17758 When the AIX ABI is requested on a non-AIX system, replace the
17759 function name with the real name (with a leading .) rather than the
17760 function descriptor name. This saves a lot of overriding code to
17761 read the prefixes. */
17764 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
17766 default_encode_section_info (decl, rtl, first);
17769 && TREE_CODE (decl) == FUNCTION_DECL
17771 && DEFAULT_ABI == ABI_AIX)
17773 rtx sym_ref = XEXP (rtl, 0);
17774 size_t len = strlen (XSTR (sym_ref, 0));
17775 char *str = alloca (len + 2);
17777 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
17778 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
17783 rs6000_elf_in_small_data_p (tree decl)
17785 if (rs6000_sdata == SDATA_NONE)
17788 /* We want to merge strings, so we never consider them small data. */
17789 if (TREE_CODE (decl) == STRING_CST)
17792 /* Functions are never in the small data area. */
17793 if (TREE_CODE (decl) == FUNCTION_DECL)
17796 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
17798 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
17799 if (strcmp (section, ".sdata") == 0
17800 || strcmp (section, ".sdata2") == 0
17801 || strcmp (section, ".sbss") == 0
17802 || strcmp (section, ".sbss2") == 0
17803 || strcmp (section, ".PPC.EMB.sdata0") == 0
17804 || strcmp (section, ".PPC.EMB.sbss0") == 0)
17809 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
17812 && (unsigned HOST_WIDE_INT) size <= g_switch_value
17813 /* If it's not public, and we're not going to reference it there,
17814 there's no need to put it in the small data section. */
17815 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
17822 #endif /* USING_ELFOS_H */
17824 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
17827 rs6000_use_blocks_for_constant_p (enum machine_mode mode, rtx x)
17829 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
17832 /* Return a REG that occurs in ADDR with coefficient 1.
17833 ADDR can be effectively incremented by incrementing REG.
17835 r0 is special and we must not select it as an address
17836 register by this routine since our caller will try to
17837 increment the returned register via an "la" instruction. */
17840 find_addr_reg (rtx addr)
17842 while (GET_CODE (addr) == PLUS)
17844 if (GET_CODE (XEXP (addr, 0)) == REG
17845 && REGNO (XEXP (addr, 0)) != 0)
17846 addr = XEXP (addr, 0);
17847 else if (GET_CODE (XEXP (addr, 1)) == REG
17848 && REGNO (XEXP (addr, 1)) != 0)
17849 addr = XEXP (addr, 1);
17850 else if (CONSTANT_P (XEXP (addr, 0)))
17851 addr = XEXP (addr, 1);
17852 else if (CONSTANT_P (XEXP (addr, 1)))
17853 addr = XEXP (addr, 0);
17855 gcc_unreachable ();
17857 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
17862 rs6000_fatal_bad_address (rtx op)
17864 fatal_insn ("bad address", op);
17869 static tree branch_island_list = 0;
17871 /* Remember to generate a branch island for far calls to the given
17875 add_compiler_branch_island (tree label_name, tree function_name,
17878 tree branch_island = build_tree_list (function_name, label_name);
17879 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
17880 TREE_CHAIN (branch_island) = branch_island_list;
17881 branch_island_list = branch_island;
17884 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17885 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17886 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17887 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17889 /* Generate far-jump branch islands for everything on the
17890 branch_island_list. Invoked immediately after the last instruction
17891 of the epilogue has been emitted; the branch-islands must be
17892 appended to, and contiguous with, the function body. Mach-O stubs
17893 are generated in machopic_output_stub(). */
17896 macho_branch_islands (void)
17899 tree branch_island;
17901 for (branch_island = branch_island_list;
17903 branch_island = TREE_CHAIN (branch_island))
17905 const char *label =
17906 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
17908 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
17909 char name_buf[512];
17910 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17911 if (name[0] == '*' || name[0] == '&')
17912 strcpy (name_buf, name+1);
17916 strcpy (name_buf+1, name);
17918 strcpy (tmp_buf, "\n");
17919 strcat (tmp_buf, label);
17920 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17921 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17922 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17923 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17926 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
17927 strcat (tmp_buf, label);
17928 strcat (tmp_buf, "_pic\n");
17929 strcat (tmp_buf, label);
17930 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
17932 strcat (tmp_buf, "\taddis r11,r11,ha16(");
17933 strcat (tmp_buf, name_buf);
17934 strcat (tmp_buf, " - ");
17935 strcat (tmp_buf, label);
17936 strcat (tmp_buf, "_pic)\n");
17938 strcat (tmp_buf, "\tmtlr r0\n");
17940 strcat (tmp_buf, "\taddi r12,r11,lo16(");
17941 strcat (tmp_buf, name_buf);
17942 strcat (tmp_buf, " - ");
17943 strcat (tmp_buf, label);
17944 strcat (tmp_buf, "_pic)\n");
17946 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
17950 strcat (tmp_buf, ":\nlis r12,hi16(");
17951 strcat (tmp_buf, name_buf);
17952 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
17953 strcat (tmp_buf, name_buf);
17954 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
17956 output_asm_insn (tmp_buf, 0);
17957 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17958 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17959 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17960 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17963 branch_island_list = 0;
17966 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17967 already there or not. */
17970 no_previous_def (tree function_name)
17972 tree branch_island;
17973 for (branch_island = branch_island_list;
17975 branch_island = TREE_CHAIN (branch_island))
17976 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17981 /* GET_PREV_LABEL gets the label name from the previous definition of
17985 get_prev_label (tree function_name)
17987 tree branch_island;
17988 for (branch_island = branch_island_list;
17990 branch_island = TREE_CHAIN (branch_island))
17991 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17992 return BRANCH_ISLAND_LABEL_NAME (branch_island);
17996 /* INSN is either a function call or a millicode call. It may have an
17997 unconditional jump in its delay slot.
17999 CALL_DEST is the routine we are calling. */
18002 output_call (rtx insn, rtx *operands, int dest_operand_number,
18003 int cookie_operand_number)
18005 static char buf[256];
18006 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
18007 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
18010 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
18012 if (no_previous_def (funname))
18014 int line_number = 0;
18015 rtx label_rtx = gen_label_rtx ();
18016 char *label_buf, temp_buf[256];
18017 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
18018 CODE_LABEL_NUMBER (label_rtx));
18019 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
18020 labelname = get_identifier (label_buf);
18021 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
18023 line_number = NOTE_LINE_NUMBER (insn);
18024 add_compiler_branch_island (labelname, funname, line_number);
18027 labelname = get_prev_label (funname);
18029 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
18030 instruction will reach 'foo', otherwise link as 'bl L42'".
18031 "L42" should be a 'branch island', that will do a far jump to
18032 'foo'. Branch islands are generated in
18033 macho_branch_islands(). */
18034 sprintf (buf, "jbsr %%z%d,%.246s",
18035 dest_operand_number, IDENTIFIER_POINTER (labelname));
18038 sprintf (buf, "bl %%z%d", dest_operand_number);
18042 /* Generate PIC and indirect symbol stubs. */
18045 machopic_output_stub (FILE *file, const char *symb, const char *stub)
18047 unsigned int length;
18048 char *symbol_name, *lazy_ptr_name;
18049 char *local_label_0;
18050 static int label = 0;
18052 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
18053 symb = (*targetm.strip_name_encoding) (symb);
18056 length = strlen (symb);
18057 symbol_name = alloca (length + 32);
18058 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
18060 lazy_ptr_name = alloca (length + 32);
18061 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
18064 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
18066 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
18070 fprintf (file, "\t.align 5\n");
18072 fprintf (file, "%s:\n", stub);
18073 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
18076 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
18077 sprintf (local_label_0, "\"L%011d$spb\"", label);
18079 fprintf (file, "\tmflr r0\n");
18080 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
18081 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
18082 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
18083 lazy_ptr_name, local_label_0);
18084 fprintf (file, "\tmtlr r0\n");
18085 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
18086 (TARGET_64BIT ? "ldu" : "lwzu"),
18087 lazy_ptr_name, local_label_0);
18088 fprintf (file, "\tmtctr r12\n");
18089 fprintf (file, "\tbctr\n");
18093 fprintf (file, "\t.align 4\n");
18095 fprintf (file, "%s:\n", stub);
18096 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
18098 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
18099 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
18100 (TARGET_64BIT ? "ldu" : "lwzu"),
18102 fprintf (file, "\tmtctr r12\n");
18103 fprintf (file, "\tbctr\n");
18106 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
18107 fprintf (file, "%s:\n", lazy_ptr_name);
18108 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
18109 fprintf (file, "%sdyld_stub_binding_helper\n",
18110 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
18113 /* Legitimize PIC addresses. If the address is already
18114 position-independent, we return ORIG. Newly generated
18115 position-independent addresses go into a reg. This is REG if non
18116 zero, otherwise we allocate register(s) as necessary. */
18118 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
18121 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
18126 if (reg == NULL && ! reload_in_progress && ! reload_completed)
18127 reg = gen_reg_rtx (Pmode);
18129 if (GET_CODE (orig) == CONST)
18133 if (GET_CODE (XEXP (orig, 0)) == PLUS
18134 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
18137 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
18139 /* Use a different reg for the intermediate value, as
18140 it will be marked UNCHANGING. */
18141 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
18142 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
18145 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
18148 if (GET_CODE (offset) == CONST_INT)
18150 if (SMALL_INT (offset))
18151 return plus_constant (base, INTVAL (offset));
18152 else if (! reload_in_progress && ! reload_completed)
18153 offset = force_reg (Pmode, offset);
18156 rtx mem = force_const_mem (Pmode, orig);
18157 return machopic_legitimize_pic_address (mem, Pmode, reg);
18160 return gen_rtx_PLUS (Pmode, base, offset);
18163 /* Fall back on generic machopic code. */
18164 return machopic_legitimize_pic_address (orig, mode, reg);
18167 /* Output a .machine directive for the Darwin assembler, and call
18168 the generic start_file routine. */
18171 rs6000_darwin_file_start (void)
18173 static const struct
18179 { "ppc64", "ppc64", MASK_64BIT },
18180 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
18181 { "power4", "ppc970", 0 },
18182 { "G5", "ppc970", 0 },
18183 { "7450", "ppc7450", 0 },
18184 { "7400", "ppc7400", MASK_ALTIVEC },
18185 { "G4", "ppc7400", 0 },
18186 { "750", "ppc750", 0 },
18187 { "740", "ppc750", 0 },
18188 { "G3", "ppc750", 0 },
18189 { "604e", "ppc604e", 0 },
18190 { "604", "ppc604", 0 },
18191 { "603e", "ppc603", 0 },
18192 { "603", "ppc603", 0 },
18193 { "601", "ppc601", 0 },
18194 { NULL, "ppc", 0 } };
18195 const char *cpu_id = "";
18198 rs6000_file_start ();
18199 darwin_file_start ();
18201 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
18202 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
18203 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
18204 && rs6000_select[i].string[0] != '\0')
18205 cpu_id = rs6000_select[i].string;
18207 /* Look through the mapping array. Pick the first name that either
18208 matches the argument, has a bit set in IF_SET that is also set
18209 in the target flags, or has a NULL name. */
18212 while (mapping[i].arg != NULL
18213 && strcmp (mapping[i].arg, cpu_id) != 0
18214 && (mapping[i].if_set & target_flags) == 0)
18217 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
18220 #endif /* TARGET_MACHO */
18223 static unsigned int
18224 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
18226 return default_section_type_flags_1 (decl, name, reloc,
18227 flag_pic || DEFAULT_ABI == ABI_AIX);
18230 /* Record an element in the table of global constructors. SYMBOL is
18231 a SYMBOL_REF of the function to be called; PRIORITY is a number
18232 between 0 and MAX_INIT_PRIORITY.
18234 This differs from default_named_section_asm_out_constructor in
18235 that we have special handling for -mrelocatable. */
18238 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
18240 const char *section = ".ctors";
18243 if (priority != DEFAULT_INIT_PRIORITY)
18245 sprintf (buf, ".ctors.%.5u",
18246 /* Invert the numbering so the linker puts us in the proper
18247 order; constructors are run from right to left, and the
18248 linker sorts in increasing order. */
18249 MAX_INIT_PRIORITY - priority);
18253 switch_to_section (get_section (section, SECTION_WRITE, NULL));
18254 assemble_align (POINTER_SIZE);
18256 if (TARGET_RELOCATABLE)
18258 fputs ("\t.long (", asm_out_file);
18259 output_addr_const (asm_out_file, symbol);
18260 fputs (")@fixup\n", asm_out_file);
18263 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
18267 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
18269 const char *section = ".dtors";
18272 if (priority != DEFAULT_INIT_PRIORITY)
18274 sprintf (buf, ".dtors.%.5u",
18275 /* Invert the numbering so the linker puts us in the proper
18276 order; constructors are run from right to left, and the
18277 linker sorts in increasing order. */
18278 MAX_INIT_PRIORITY - priority);
18282 switch_to_section (get_section (section, SECTION_WRITE, NULL));
18283 assemble_align (POINTER_SIZE);
18285 if (TARGET_RELOCATABLE)
18287 fputs ("\t.long (", asm_out_file);
18288 output_addr_const (asm_out_file, symbol);
18289 fputs (")@fixup\n", asm_out_file);
18292 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
18296 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
18300 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
18301 ASM_OUTPUT_LABEL (file, name);
18302 fputs (DOUBLE_INT_ASM_OP, file);
18303 rs6000_output_function_entry (file, name);
18304 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
18307 fputs ("\t.size\t", file);
18308 assemble_name (file, name);
18309 fputs (",24\n\t.type\t.", file);
18310 assemble_name (file, name);
18311 fputs (",@function\n", file);
18312 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
18314 fputs ("\t.globl\t.", file);
18315 assemble_name (file, name);
18320 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18321 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18322 rs6000_output_function_entry (file, name);
18323 fputs (":\n", file);
18327 if (TARGET_RELOCATABLE
18328 && !TARGET_SECURE_PLT
18329 && (get_pool_size () != 0 || current_function_profile)
18334 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
18336 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
18337 fprintf (file, "\t.long ");
18338 assemble_name (file, buf);
18340 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
18341 assemble_name (file, buf);
18345 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18346 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18348 if (DEFAULT_ABI == ABI_AIX)
18350 const char *desc_name, *orig_name;
18352 orig_name = (*targetm.strip_name_encoding) (name);
18353 desc_name = orig_name;
18354 while (*desc_name == '.')
18357 if (TREE_PUBLIC (decl))
18358 fprintf (file, "\t.globl %s\n", desc_name);
18360 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18361 fprintf (file, "%s:\n", desc_name);
18362 fprintf (file, "\t.long %s\n", orig_name);
18363 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
18364 if (DEFAULT_ABI == ABI_AIX)
18365 fputs ("\t.long 0\n", file);
18366 fprintf (file, "\t.previous\n");
18368 ASM_OUTPUT_LABEL (file, name);
18372 rs6000_elf_end_indicate_exec_stack (void)
18375 file_end_indicate_exec_stack ();
18381 rs6000_xcoff_asm_output_anchor (rtx symbol)
18385 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
18386 SYMBOL_REF_BLOCK_OFFSET (symbol));
18387 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
18391 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
18393 fputs (GLOBAL_ASM_OP, stream);
18394 RS6000_OUTPUT_BASENAME (stream, name);
18395 putc ('\n', stream);
18398 /* A get_unnamed_decl callback, used for read-only sections. PTR
18399 points to the section string variable. */
18402 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
18404 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
18405 *(const char *const *) directive);
18408 /* Likewise for read-write sections. */
18411 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
18413 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
18414 *(const char *const *) directive);
18417 /* A get_unnamed_section callback, used for switching to toc_section. */
18420 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
18422 if (TARGET_MINIMAL_TOC)
18424 /* toc_section is always selected at least once from
18425 rs6000_xcoff_file_start, so this is guaranteed to
18426 always be defined once and only once in each file. */
18427 if (!toc_initialized)
18429 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
18430 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
18431 toc_initialized = 1;
18433 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
18434 (TARGET_32BIT ? "" : ",3"));
18437 fputs ("\t.toc\n", asm_out_file);
18440 /* Implement TARGET_ASM_INIT_SECTIONS. */
18443 rs6000_xcoff_asm_init_sections (void)
18445 read_only_data_section
18446 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18447 &xcoff_read_only_section_name);
18449 private_data_section
18450 = get_unnamed_section (SECTION_WRITE,
18451 rs6000_xcoff_output_readwrite_section_asm_op,
18452 &xcoff_private_data_section_name);
18454 read_only_private_data_section
18455 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18456 &xcoff_private_data_section_name);
18459 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
18461 readonly_data_section = read_only_data_section;
18462 exception_section = data_section;
18466 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
18467 tree decl ATTRIBUTE_UNUSED)
18470 static const char * const suffix[3] = { "PR", "RO", "RW" };
18472 if (flags & SECTION_CODE)
18474 else if (flags & SECTION_WRITE)
18479 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
18480 (flags & SECTION_CODE) ? "." : "",
18481 name, suffix[smclass], flags & SECTION_ENTSIZE);
18485 rs6000_xcoff_select_section (tree decl, int reloc,
18486 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18488 if (decl_readonly_section_1 (decl, reloc, 1))
18490 if (TREE_PUBLIC (decl))
18491 return read_only_data_section;
18493 return read_only_private_data_section;
18497 if (TREE_PUBLIC (decl))
18498 return data_section;
18500 return private_data_section;
18505 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
18509 /* Use select_section for private and uninitialized data. */
18510 if (!TREE_PUBLIC (decl)
18511 || DECL_COMMON (decl)
18512 || DECL_INITIAL (decl) == NULL_TREE
18513 || DECL_INITIAL (decl) == error_mark_node
18514 || (flag_zero_initialized_in_bss
18515 && initializer_zerop (DECL_INITIAL (decl))))
18518 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
18519 name = (*targetm.strip_name_encoding) (name);
18520 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
18523 /* Select section for constant in constant pool.
18525 On RS/6000, all constants are in the private read-only data area.
18526 However, if this is being placed in the TOC it must be output as a
18530 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
18531 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18533 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
18534 return toc_section;
18536 return read_only_private_data_section;
18539 /* Remove any trailing [DS] or the like from the symbol name. */
18541 static const char *
18542 rs6000_xcoff_strip_name_encoding (const char *name)
18547 len = strlen (name);
18548 if (name[len - 1] == ']')
18549 return ggc_alloc_string (name, len - 4);
18554 /* Section attributes. AIX is always PIC. */
18556 static unsigned int
18557 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
18559 unsigned int align;
18560 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
18562 /* Align to at least UNIT size. */
18563 if (flags & SECTION_CODE)
18564 align = MIN_UNITS_PER_WORD;
18566 /* Increase alignment of large objects if not already stricter. */
18567 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
18568 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
18569 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
18571 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
18574 /* Output at beginning of assembler file.
18576 Initialize the section names for the RS/6000 at this point.
18578 Specify filename, including full path, to assembler.
18580 We want to go into the TOC section so at least one .toc will be emitted.
18581 Also, in order to output proper .bs/.es pairs, we need at least one static
18582 [RW] section emitted.
18584 Finally, declare mcount when profiling to make the assembler happy. */
18587 rs6000_xcoff_file_start (void)
18589 rs6000_gen_section_name (&xcoff_bss_section_name,
18590 main_input_filename, ".bss_");
18591 rs6000_gen_section_name (&xcoff_private_data_section_name,
18592 main_input_filename, ".rw_");
18593 rs6000_gen_section_name (&xcoff_read_only_section_name,
18594 main_input_filename, ".ro_");
18596 fputs ("\t.file\t", asm_out_file);
18597 output_quoted_string (asm_out_file, main_input_filename);
18598 fputc ('\n', asm_out_file);
18599 if (write_symbols != NO_DEBUG)
18600 switch_to_section (private_data_section);
18601 switch_to_section (text_section);
18603 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
18604 rs6000_file_start ();
18607 /* Output at end of assembler file.
18608 On the RS/6000, referencing data should automatically pull in text. */
18611 rs6000_xcoff_file_end (void)
18613 switch_to_section (text_section);
18614 fputs ("_section_.text:\n", asm_out_file);
18615 switch_to_section (data_section);
18616 fputs (TARGET_32BIT
18617 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
18620 #endif /* TARGET_XCOFF */
18622 /* Compute a (partial) cost for rtx X. Return true if the complete
18623 cost has been computed, and false if subexpressions should be
18624 scanned. In either case, *TOTAL contains the cost result. */
18627 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
18629 enum machine_mode mode = GET_MODE (x);
18633 /* On the RS/6000, if it is valid in the insn, it is free. */
18635 if (((outer_code == SET
18636 || outer_code == PLUS
18637 || outer_code == MINUS)
18638 && (satisfies_constraint_I (x)
18639 || satisfies_constraint_L (x)))
18640 || (outer_code == AND
18641 && (satisfies_constraint_K (x)
18643 ? satisfies_constraint_L (x)
18644 : satisfies_constraint_J (x))
18645 || mask_operand (x, mode)
18647 && mask64_operand (x, DImode))))
18648 || ((outer_code == IOR || outer_code == XOR)
18649 && (satisfies_constraint_K (x)
18651 ? satisfies_constraint_L (x)
18652 : satisfies_constraint_J (x))))
18653 || outer_code == ASHIFT
18654 || outer_code == ASHIFTRT
18655 || outer_code == LSHIFTRT
18656 || outer_code == ROTATE
18657 || outer_code == ROTATERT
18658 || outer_code == ZERO_EXTRACT
18659 || (outer_code == MULT
18660 && satisfies_constraint_I (x))
18661 || ((outer_code == DIV || outer_code == UDIV
18662 || outer_code == MOD || outer_code == UMOD)
18663 && exact_log2 (INTVAL (x)) >= 0)
18664 || (outer_code == COMPARE
18665 && (satisfies_constraint_I (x)
18666 || satisfies_constraint_K (x)))
18667 || (outer_code == EQ
18668 && (satisfies_constraint_I (x)
18669 || satisfies_constraint_K (x)
18671 ? satisfies_constraint_L (x)
18672 : satisfies_constraint_J (x))))
18673 || (outer_code == GTU
18674 && satisfies_constraint_I (x))
18675 || (outer_code == LTU
18676 && satisfies_constraint_P (x)))
18681 else if ((outer_code == PLUS
18682 && reg_or_add_cint_operand (x, VOIDmode))
18683 || (outer_code == MINUS
18684 && reg_or_sub_cint_operand (x, VOIDmode))
18685 || ((outer_code == SET
18686 || outer_code == IOR
18687 || outer_code == XOR)
18689 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
18691 *total = COSTS_N_INSNS (1);
18697 if (mode == DImode && code == CONST_DOUBLE)
18699 if ((outer_code == IOR || outer_code == XOR)
18700 && CONST_DOUBLE_HIGH (x) == 0
18701 && (CONST_DOUBLE_LOW (x)
18702 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
18707 else if ((outer_code == AND && and64_2_operand (x, DImode))
18708 || ((outer_code == SET
18709 || outer_code == IOR
18710 || outer_code == XOR)
18711 && CONST_DOUBLE_HIGH (x) == 0))
18713 *total = COSTS_N_INSNS (1);
18723 /* When optimizing for size, MEM should be slightly more expensive
18724 than generating address, e.g., (plus (reg) (const)).
18725 L1 cache latency is about two instructions. */
18726 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18734 if (mode == DFmode)
18736 if (GET_CODE (XEXP (x, 0)) == MULT)
18738 /* FNMA accounted in outer NEG. */
18739 if (outer_code == NEG)
18740 *total = rs6000_cost->dmul - rs6000_cost->fp;
18742 *total = rs6000_cost->dmul;
18745 *total = rs6000_cost->fp;
18747 else if (mode == SFmode)
18749 /* FNMA accounted in outer NEG. */
18750 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18753 *total = rs6000_cost->fp;
18756 *total = COSTS_N_INSNS (1);
18760 if (mode == DFmode)
18762 if (GET_CODE (XEXP (x, 0)) == MULT)
18764 /* FNMA accounted in outer NEG. */
18765 if (outer_code == NEG)
18768 *total = rs6000_cost->dmul;
18771 *total = rs6000_cost->fp;
18773 else if (mode == SFmode)
18775 /* FNMA accounted in outer NEG. */
18776 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18779 *total = rs6000_cost->fp;
18782 *total = COSTS_N_INSNS (1);
18786 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18787 && satisfies_constraint_I (XEXP (x, 1)))
18789 if (INTVAL (XEXP (x, 1)) >= -256
18790 && INTVAL (XEXP (x, 1)) <= 255)
18791 *total = rs6000_cost->mulsi_const9;
18793 *total = rs6000_cost->mulsi_const;
18795 /* FMA accounted in outer PLUS/MINUS. */
18796 else if ((mode == DFmode || mode == SFmode)
18797 && (outer_code == PLUS || outer_code == MINUS))
18799 else if (mode == DFmode)
18800 *total = rs6000_cost->dmul;
18801 else if (mode == SFmode)
18802 *total = rs6000_cost->fp;
18803 else if (mode == DImode)
18804 *total = rs6000_cost->muldi;
18806 *total = rs6000_cost->mulsi;
18811 if (FLOAT_MODE_P (mode))
18813 *total = mode == DFmode ? rs6000_cost->ddiv
18814 : rs6000_cost->sdiv;
18821 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18822 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
18824 if (code == DIV || code == MOD)
18826 *total = COSTS_N_INSNS (2);
18829 *total = COSTS_N_INSNS (1);
18833 if (GET_MODE (XEXP (x, 1)) == DImode)
18834 *total = rs6000_cost->divdi;
18836 *total = rs6000_cost->divsi;
18838 /* Add in shift and subtract for MOD. */
18839 if (code == MOD || code == UMOD)
18840 *total += COSTS_N_INSNS (2);
18844 *total = COSTS_N_INSNS (4);
18848 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
18859 *total = COSTS_N_INSNS (1);
18867 /* Handle mul_highpart. */
18868 if (outer_code == TRUNCATE
18869 && GET_CODE (XEXP (x, 0)) == MULT)
18871 if (mode == DImode)
18872 *total = rs6000_cost->muldi;
18874 *total = rs6000_cost->mulsi;
18877 else if (outer_code == AND)
18880 *total = COSTS_N_INSNS (1);
18885 if (GET_CODE (XEXP (x, 0)) == MEM)
18888 *total = COSTS_N_INSNS (1);
18894 if (!FLOAT_MODE_P (mode))
18896 *total = COSTS_N_INSNS (1);
18902 case UNSIGNED_FLOAT:
18905 case FLOAT_TRUNCATE:
18906 *total = rs6000_cost->fp;
18910 if (mode == DFmode)
18913 *total = rs6000_cost->fp;
18917 switch (XINT (x, 1))
18920 *total = rs6000_cost->fp;
18932 *total = COSTS_N_INSNS (1);
18935 else if (FLOAT_MODE_P (mode)
18936 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
18938 *total = rs6000_cost->fp;
18946 /* Carry bit requires mode == Pmode.
18947 NEG or PLUS already counted so only add one. */
18949 && (outer_code == NEG || outer_code == PLUS))
18951 *total = COSTS_N_INSNS (1);
18954 if (outer_code == SET)
18956 if (XEXP (x, 1) == const0_rtx)
18958 *total = COSTS_N_INSNS (2);
18961 else if (mode == Pmode)
18963 *total = COSTS_N_INSNS (3);
18972 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
18974 *total = COSTS_N_INSNS (2);
18978 if (outer_code == COMPARE)
18992 /* A C expression returning the cost of moving data from a register of class
18993 CLASS1 to one of CLASS2. */
18996 rs6000_register_move_cost (enum machine_mode mode,
18997 enum reg_class from, enum reg_class to)
18999 /* Moves from/to GENERAL_REGS. */
19000 if (reg_classes_intersect_p (to, GENERAL_REGS)
19001 || reg_classes_intersect_p (from, GENERAL_REGS))
19003 if (! reg_classes_intersect_p (to, GENERAL_REGS))
19006 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
19007 return (rs6000_memory_move_cost (mode, from, 0)
19008 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
19010 /* It's more expensive to move CR_REGS than CR0_REGS because of the
19012 else if (from == CR_REGS)
19016 /* A move will cost one instruction per GPR moved. */
19017 return 2 * hard_regno_nregs[0][mode];
19020 /* Moving between two similar registers is just one instruction. */
19021 else if (reg_classes_intersect_p (to, from))
19022 return mode == TFmode ? 4 : 2;
19024 /* Everything else has to go through GENERAL_REGS. */
19026 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
19027 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
19030 /* A C expressions returning the cost of moving data of MODE from a register to
19034 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
19035 int in ATTRIBUTE_UNUSED)
19037 if (reg_classes_intersect_p (class, GENERAL_REGS))
19038 return 4 * hard_regno_nregs[0][mode];
19039 else if (reg_classes_intersect_p (class, FLOAT_REGS))
19040 return 4 * hard_regno_nregs[32][mode];
19041 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
19042 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
19044 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
19047 /* Newton-Raphson approximation of single-precision floating point divide n/d.
19048 Assumes no trapping math and finite arguments. */
19051 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
19053 rtx x0, e0, e1, y1, u0, v0, one;
19055 x0 = gen_reg_rtx (SFmode);
19056 e0 = gen_reg_rtx (SFmode);
19057 e1 = gen_reg_rtx (SFmode);
19058 y1 = gen_reg_rtx (SFmode);
19059 u0 = gen_reg_rtx (SFmode);
19060 v0 = gen_reg_rtx (SFmode);
19061 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
19063 /* x0 = 1./d estimate */
19064 emit_insn (gen_rtx_SET (VOIDmode, x0,
19065 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
19067 /* e0 = 1. - d * x0 */
19068 emit_insn (gen_rtx_SET (VOIDmode, e0,
19069 gen_rtx_MINUS (SFmode, one,
19070 gen_rtx_MULT (SFmode, d, x0))));
19071 /* e1 = e0 + e0 * e0 */
19072 emit_insn (gen_rtx_SET (VOIDmode, e1,
19073 gen_rtx_PLUS (SFmode,
19074 gen_rtx_MULT (SFmode, e0, e0), e0)));
19075 /* y1 = x0 + e1 * x0 */
19076 emit_insn (gen_rtx_SET (VOIDmode, y1,
19077 gen_rtx_PLUS (SFmode,
19078 gen_rtx_MULT (SFmode, e1, x0), x0)));
19080 emit_insn (gen_rtx_SET (VOIDmode, u0,
19081 gen_rtx_MULT (SFmode, n, y1)));
19082 /* v0 = n - d * u0 */
19083 emit_insn (gen_rtx_SET (VOIDmode, v0,
19084 gen_rtx_MINUS (SFmode, n,
19085 gen_rtx_MULT (SFmode, d, u0))));
19086 /* res = u0 + v0 * y1 */
19087 emit_insn (gen_rtx_SET (VOIDmode, res,
19088 gen_rtx_PLUS (SFmode,
19089 gen_rtx_MULT (SFmode, v0, y1), u0)));
19092 /* Newton-Raphson approximation of double-precision floating point divide n/d.
19093 Assumes no trapping math and finite arguments. */
19096 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
19098 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
19100 x0 = gen_reg_rtx (DFmode);
19101 e0 = gen_reg_rtx (DFmode);
19102 e1 = gen_reg_rtx (DFmode);
19103 e2 = gen_reg_rtx (DFmode);
19104 y1 = gen_reg_rtx (DFmode);
19105 y2 = gen_reg_rtx (DFmode);
19106 y3 = gen_reg_rtx (DFmode);
19107 u0 = gen_reg_rtx (DFmode);
19108 v0 = gen_reg_rtx (DFmode);
19109 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
19111 /* x0 = 1./d estimate */
19112 emit_insn (gen_rtx_SET (VOIDmode, x0,
19113 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
19115 /* e0 = 1. - d * x0 */
19116 emit_insn (gen_rtx_SET (VOIDmode, e0,
19117 gen_rtx_MINUS (DFmode, one,
19118 gen_rtx_MULT (SFmode, d, x0))));
19119 /* y1 = x0 + e0 * x0 */
19120 emit_insn (gen_rtx_SET (VOIDmode, y1,
19121 gen_rtx_PLUS (DFmode,
19122 gen_rtx_MULT (DFmode, e0, x0), x0)));
19124 emit_insn (gen_rtx_SET (VOIDmode, e1,
19125 gen_rtx_MULT (DFmode, e0, e0)));
19126 /* y2 = y1 + e1 * y1 */
19127 emit_insn (gen_rtx_SET (VOIDmode, y2,
19128 gen_rtx_PLUS (DFmode,
19129 gen_rtx_MULT (DFmode, e1, y1), y1)));
19131 emit_insn (gen_rtx_SET (VOIDmode, e2,
19132 gen_rtx_MULT (DFmode, e1, e1)));
19133 /* y3 = y2 + e2 * y2 */
19134 emit_insn (gen_rtx_SET (VOIDmode, y3,
19135 gen_rtx_PLUS (DFmode,
19136 gen_rtx_MULT (DFmode, e2, y2), y2)));
19138 emit_insn (gen_rtx_SET (VOIDmode, u0,
19139 gen_rtx_MULT (DFmode, n, y3)));
19140 /* v0 = n - d * u0 */
19141 emit_insn (gen_rtx_SET (VOIDmode, v0,
19142 gen_rtx_MINUS (DFmode, n,
19143 gen_rtx_MULT (DFmode, d, u0))));
19144 /* res = u0 + v0 * y3 */
19145 emit_insn (gen_rtx_SET (VOIDmode, res,
19146 gen_rtx_PLUS (DFmode,
19147 gen_rtx_MULT (DFmode, v0, y3), u0)));
19150 /* Return an RTX representing where to find the function value of a
19151 function returning MODE. */
19153 rs6000_complex_function_value (enum machine_mode mode)
19155 unsigned int regno;
19157 enum machine_mode inner = GET_MODE_INNER (mode);
19158 unsigned int inner_bytes = GET_MODE_SIZE (inner);
19160 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
19161 regno = FP_ARG_RETURN;
19164 regno = GP_ARG_RETURN;
19166 /* 32-bit is OK since it'll go in r3/r4. */
19167 if (TARGET_32BIT && inner_bytes >= 4)
19168 return gen_rtx_REG (mode, regno);
19171 if (inner_bytes >= 8)
19172 return gen_rtx_REG (mode, regno);
19174 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
19176 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
19177 GEN_INT (inner_bytes));
19178 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
19181 /* Define how to find the value returned by a function.
19182 VALTYPE is the data type of the value (as a tree).
19183 If the precise function being called is known, FUNC is its FUNCTION_DECL;
19184 otherwise, FUNC is 0.
19186 On the SPE, both FPs and vectors are returned in r3.
19188 On RS/6000 an integer value is in r3 and a floating-point value is in
19189 fp1, unless -msoft-float. */
19192 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
19194 enum machine_mode mode;
19195 unsigned int regno;
19197 /* Special handling for structs in darwin64. */
19198 if (rs6000_darwin64_abi
19199 && TYPE_MODE (valtype) == BLKmode
19200 && TREE_CODE (valtype) == RECORD_TYPE
19201 && int_size_in_bytes (valtype) > 0)
19203 CUMULATIVE_ARGS valcum;
19207 valcum.fregno = FP_ARG_MIN_REG;
19208 valcum.vregno = ALTIVEC_ARG_MIN_REG;
19209 /* Do a trial code generation as if this were going to be passed as
19210 an argument; if any part goes in memory, we return NULL. */
19211 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
19214 /* Otherwise fall through to standard ABI rules. */
19217 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
19219 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
19220 return gen_rtx_PARALLEL (DImode,
19222 gen_rtx_EXPR_LIST (VOIDmode,
19223 gen_rtx_REG (SImode, GP_ARG_RETURN),
19225 gen_rtx_EXPR_LIST (VOIDmode,
19226 gen_rtx_REG (SImode,
19227 GP_ARG_RETURN + 1),
19230 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
19232 return gen_rtx_PARALLEL (DCmode,
19234 gen_rtx_EXPR_LIST (VOIDmode,
19235 gen_rtx_REG (SImode, GP_ARG_RETURN),
19237 gen_rtx_EXPR_LIST (VOIDmode,
19238 gen_rtx_REG (SImode,
19239 GP_ARG_RETURN + 1),
19241 gen_rtx_EXPR_LIST (VOIDmode,
19242 gen_rtx_REG (SImode,
19243 GP_ARG_RETURN + 2),
19245 gen_rtx_EXPR_LIST (VOIDmode,
19246 gen_rtx_REG (SImode,
19247 GP_ARG_RETURN + 3),
19251 if ((INTEGRAL_TYPE_P (valtype)
19252 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
19253 || POINTER_TYPE_P (valtype))
19254 mode = TARGET_32BIT ? SImode : DImode;
19256 mode = TYPE_MODE (valtype);
19258 if (DECIMAL_FLOAT_MODE_P (mode))
19259 regno = GP_ARG_RETURN;
19260 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
19261 regno = FP_ARG_RETURN;
19262 else if (TREE_CODE (valtype) == COMPLEX_TYPE
19263 && targetm.calls.split_complex_arg)
19264 return rs6000_complex_function_value (mode);
19265 else if (TREE_CODE (valtype) == VECTOR_TYPE
19266 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
19267 && ALTIVEC_VECTOR_MODE (mode))
19268 regno = ALTIVEC_ARG_RETURN;
19269 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
19270 && (mode == DFmode || mode == DCmode))
19271 return spe_build_register_parallel (mode, GP_ARG_RETURN);
19273 regno = GP_ARG_RETURN;
19275 return gen_rtx_REG (mode, regno);
19278 /* Define how to find the value returned by a library function
19279 assuming the value has mode MODE. */
19281 rs6000_libcall_value (enum machine_mode mode)
19283 unsigned int regno;
19285 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
19287 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
19288 return gen_rtx_PARALLEL (DImode,
19290 gen_rtx_EXPR_LIST (VOIDmode,
19291 gen_rtx_REG (SImode, GP_ARG_RETURN),
19293 gen_rtx_EXPR_LIST (VOIDmode,
19294 gen_rtx_REG (SImode,
19295 GP_ARG_RETURN + 1),
19299 if (DECIMAL_FLOAT_MODE_P (mode))
19300 regno = GP_ARG_RETURN;
19301 else if (SCALAR_FLOAT_MODE_P (mode)
19302 && TARGET_HARD_FLOAT && TARGET_FPRS)
19303 regno = FP_ARG_RETURN;
19304 else if (ALTIVEC_VECTOR_MODE (mode)
19305 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
19306 regno = ALTIVEC_ARG_RETURN;
19307 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
19308 return rs6000_complex_function_value (mode);
19309 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
19310 && (mode == DFmode || mode == DCmode))
19311 return spe_build_register_parallel (mode, GP_ARG_RETURN);
19313 regno = GP_ARG_RETURN;
19315 return gen_rtx_REG (mode, regno);
19318 /* Define the offset between two registers, FROM to be eliminated and its
19319 replacement TO, at the start of a routine. */
19321 rs6000_initial_elimination_offset (int from, int to)
19323 rs6000_stack_t *info = rs6000_stack_info ();
19324 HOST_WIDE_INT offset;
19326 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19327 offset = info->push_p ? 0 : -info->total_size;
19328 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19330 offset = info->push_p ? 0 : -info->total_size;
19331 if (FRAME_GROWS_DOWNWARD)
19332 offset += info->fixed_size + info->vars_size + info->parm_size;
19334 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
19335 offset = FRAME_GROWS_DOWNWARD
19336 ? info->fixed_size + info->vars_size + info->parm_size
19338 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
19339 offset = info->total_size;
19340 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19341 offset = info->push_p ? info->total_size : 0;
19342 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
19345 gcc_unreachable ();
19350 /* Return true if TYPE is a SPE or AltiVec opaque type. */
19353 rs6000_is_opaque_type (tree type)
19355 return (type == opaque_V2SI_type_node
19356 || type == opaque_V2SF_type_node
19357 || type == opaque_p_V2SI_type_node
19358 || type == opaque_V4SI_type_node);
19362 rs6000_dwarf_register_span (rtx reg)
19367 && (SPE_VECTOR_MODE (GET_MODE (reg))
19368 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
19373 regno = REGNO (reg);
19375 /* The duality of the SPE register size wreaks all kinds of havoc.
19376 This is a way of distinguishing r0 in 32-bits from r0 in
19379 gen_rtx_PARALLEL (VOIDmode,
19382 gen_rtx_REG (SImode, regno + 1200),
19383 gen_rtx_REG (SImode, regno))
19385 gen_rtx_REG (SImode, regno),
19386 gen_rtx_REG (SImode, regno + 1200)));
19389 /* Map internal gcc register numbers to DWARF2 register numbers. */
19392 rs6000_dbx_register_number (unsigned int regno)
19394 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
19396 if (regno == MQ_REGNO)
19398 if (regno == LINK_REGISTER_REGNUM)
19400 if (regno == COUNT_REGISTER_REGNUM)
19402 if (CR_REGNO_P (regno))
19403 return regno - CR0_REGNO + 86;
19404 if (regno == XER_REGNO)
19406 if (ALTIVEC_REGNO_P (regno))
19407 return regno - FIRST_ALTIVEC_REGNO + 1124;
19408 if (regno == VRSAVE_REGNO)
19410 if (regno == VSCR_REGNO)
19412 if (regno == SPE_ACC_REGNO)
19414 if (regno == SPEFSCR_REGNO)
19416 /* SPE high reg number. We get these values of regno from
19417 rs6000_dwarf_register_span. */
19418 gcc_assert (regno >= 1200 && regno < 1232);
19422 /* target hook eh_return_filter_mode */
19423 static enum machine_mode
19424 rs6000_eh_return_filter_mode (void)
19426 return TARGET_32BIT ? SImode : word_mode;
19429 /* Target hook for scalar_mode_supported_p. */
19431 rs6000_scalar_mode_supported_p (enum machine_mode mode)
19433 if (DECIMAL_FLOAT_MODE_P (mode))
19436 return default_scalar_mode_supported_p (mode);
19439 /* Target hook for vector_mode_supported_p. */
19441 rs6000_vector_mode_supported_p (enum machine_mode mode)
19444 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
19447 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
19454 /* Target hook for invalid_arg_for_unprototyped_fn. */
19455 static const char *
19456 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
19458 return (!rs6000_darwin64_abi
19460 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
19461 && (funcdecl == NULL_TREE
19462 || (TREE_CODE (funcdecl) == FUNCTION_DECL
19463 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
19464 ? N_("AltiVec argument passed to unprototyped function")
19468 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
19469 setup by using __stack_chk_fail_local hidden function instead of
19470 calling __stack_chk_fail directly. Otherwise it is better to call
19471 __stack_chk_fail directly. */
19474 rs6000_stack_protect_fail (void)
19476 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
19477 ? default_hidden_stack_protect_fail ()
19478 : default_external_stack_protect_fail ();
19481 #include "gt-rs6000.h"