1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
45 #include "integrate.h"
51 #include "target-def.h"
52 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
56 #include "tree-gimple.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack {
76 int first_gp_reg_save; /* first callee saved GP register used */
77 int first_fp_reg_save; /* first callee saved FP register used */
78 int first_altivec_reg_save; /* first callee saved AltiVec register used */
79 int lr_save_p; /* true if the link reg needs to be saved */
80 int cr_save_p; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask; /* mask of vec registers to save */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset; /* offset to save the varargs registers */
95 int ehrd_offset; /* offset to EH return data */
96 int reg_size; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
111 int spe_64bit_regs_used;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct machine_function GTY(())
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset;
131 /* Target cpu type */
133 enum processor_type rs6000_cpu;
134 struct rs6000_cpu_select rs6000_select[3] =
136 /* switch name, tune arch */
137 { (const char *)0, "--with-cpu=", 1, 1 },
138 { (const char *)0, "-mcpu=", 1, 1 },
139 { (const char *)0, "-mtune=", 1, 0 },
142 /* Always emit branch hint bits. */
143 static GTY(()) bool rs6000_always_hint;
145 /* Schedule instructions for group formation. */
146 static GTY(()) bool rs6000_sched_groups;
148 /* Support for -msched-costly-dep option. */
149 const char *rs6000_sched_costly_dep_str;
150 enum rs6000_dependence_cost rs6000_sched_costly_dep;
152 /* Support for -minsert-sched-nops option. */
153 const char *rs6000_sched_insert_nops_str;
154 enum rs6000_nop_insertion rs6000_sched_insert_nops;
156 /* Support targetm.vectorize.builtin_mask_for_load. */
157 static GTY(()) tree altivec_builtin_mask_for_load;
159 /* Size of long double. */
160 int rs6000_long_double_type_size;
162 /* IEEE quad extended precision long double. */
165 /* Whether -mabi=altivec has appeared. */
166 int rs6000_altivec_abi;
168 /* Nonzero if we want SPE ABI extensions. */
171 /* Nonzero if floating point operations are done in the GPRs. */
172 int rs6000_float_gprs = 0;
174 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
175 int rs6000_darwin64_abi;
177 /* Set to nonzero once AIX common-mode calls have been defined. */
178 static GTY(()) int common_mode_defined;
180 /* Save information from a "cmpxx" operation until the branch or scc is
182 rtx rs6000_compare_op0, rs6000_compare_op1;
183 int rs6000_compare_fp_p;
185 /* Label number of label created for -mrelocatable, to call to so we can
186 get the address of the GOT section */
187 int rs6000_pic_labelno;
190 /* Which abi to adhere to */
191 const char *rs6000_abi_name;
193 /* Semantics of the small data area */
194 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
196 /* Which small data model to use */
197 const char *rs6000_sdata_name = (char *)0;
199 /* Counter for labels which are to be placed in .fixup. */
200 int fixuplabelno = 0;
203 /* Bit size of immediate TLS offsets and string from which it is decoded. */
204 int rs6000_tls_size = 32;
205 const char *rs6000_tls_size_string;
207 /* ABI enumeration available for subtarget to use. */
208 enum rs6000_abi rs6000_current_abi;
210 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
214 const char *rs6000_debug_name;
215 int rs6000_debug_stack; /* debug stack applications */
216 int rs6000_debug_arg; /* debug argument handling */
218 /* Value is TRUE if register/mode pair is acceptable. */
219 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
221 /* Built in types. */
223 tree rs6000_builtin_types[RS6000_BTI_MAX];
224 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
226 const char *rs6000_traceback_name;
228 traceback_default = 0,
234 /* Flag to say the TOC is initialized */
236 char toc_label_name[10];
238 static GTY(()) section *read_only_data_section;
239 static GTY(()) section *private_data_section;
240 static GTY(()) section *read_only_private_data_section;
241 static GTY(()) section *sdata2_section;
242 static GTY(()) section *toc_section;
244 /* Control alignment for fields within structures. */
245 /* String from -malign-XXXXX. */
246 int rs6000_alignment_flags;
248 /* True for any options that were explicitly set. */
250 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
251 bool alignment; /* True if -malign- was used. */
252 bool abi; /* True if -mabi= was used. */
253 bool spe; /* True if -mspe= was used. */
254 bool float_gprs; /* True if -mfloat-gprs= was used. */
255 bool isel; /* True if -misel was used. */
256 bool long_double; /* True if -mlong-double- was used. */
257 } rs6000_explicit_options;
259 struct builtin_description
261 /* mask is not const because we're going to alter it below. This
262 nonsense will go away when we rewrite the -march infrastructure
263 to give us more target flag bits. */
265 const enum insn_code icode;
266 const char *const name;
267 const enum rs6000_builtins code;
270 /* Target cpu costs. */
272 struct processor_costs {
273 const int mulsi; /* cost of SImode multiplication. */
274 const int mulsi_const; /* cost of SImode multiplication by constant. */
275 const int mulsi_const9; /* cost of SImode mult by short constant. */
276 const int muldi; /* cost of DImode multiplication. */
277 const int divsi; /* cost of SImode division. */
278 const int divdi; /* cost of DImode division. */
279 const int fp; /* cost of simple SFmode and DFmode insns. */
280 const int dmul; /* cost of DFmode multiplication (and fmadd). */
281 const int sdiv; /* cost of SFmode division (fdivs). */
282 const int ddiv; /* cost of DFmode division (fdiv). */
285 const struct processor_costs *rs6000_cost;
287 /* Processor costs (relative to an add) */
289 /* Instruction size costs on 32bit processors. */
291 struct processor_costs size32_cost = {
292 COSTS_N_INSNS (1), /* mulsi */
293 COSTS_N_INSNS (1), /* mulsi_const */
294 COSTS_N_INSNS (1), /* mulsi_const9 */
295 COSTS_N_INSNS (1), /* muldi */
296 COSTS_N_INSNS (1), /* divsi */
297 COSTS_N_INSNS (1), /* divdi */
298 COSTS_N_INSNS (1), /* fp */
299 COSTS_N_INSNS (1), /* dmul */
300 COSTS_N_INSNS (1), /* sdiv */
301 COSTS_N_INSNS (1), /* ddiv */
304 /* Instruction size costs on 64bit processors. */
306 struct processor_costs size64_cost = {
307 COSTS_N_INSNS (1), /* mulsi */
308 COSTS_N_INSNS (1), /* mulsi_const */
309 COSTS_N_INSNS (1), /* mulsi_const9 */
310 COSTS_N_INSNS (1), /* muldi */
311 COSTS_N_INSNS (1), /* divsi */
312 COSTS_N_INSNS (1), /* divdi */
313 COSTS_N_INSNS (1), /* fp */
314 COSTS_N_INSNS (1), /* dmul */
315 COSTS_N_INSNS (1), /* sdiv */
316 COSTS_N_INSNS (1), /* ddiv */
319 /* Instruction costs on RIOS1 processors. */
321 struct processor_costs rios1_cost = {
322 COSTS_N_INSNS (5), /* mulsi */
323 COSTS_N_INSNS (4), /* mulsi_const */
324 COSTS_N_INSNS (3), /* mulsi_const9 */
325 COSTS_N_INSNS (5), /* muldi */
326 COSTS_N_INSNS (19), /* divsi */
327 COSTS_N_INSNS (19), /* divdi */
328 COSTS_N_INSNS (2), /* fp */
329 COSTS_N_INSNS (2), /* dmul */
330 COSTS_N_INSNS (19), /* sdiv */
331 COSTS_N_INSNS (19), /* ddiv */
334 /* Instruction costs on RIOS2 processors. */
336 struct processor_costs rios2_cost = {
337 COSTS_N_INSNS (2), /* mulsi */
338 COSTS_N_INSNS (2), /* mulsi_const */
339 COSTS_N_INSNS (2), /* mulsi_const9 */
340 COSTS_N_INSNS (2), /* muldi */
341 COSTS_N_INSNS (13), /* divsi */
342 COSTS_N_INSNS (13), /* divdi */
343 COSTS_N_INSNS (2), /* fp */
344 COSTS_N_INSNS (2), /* dmul */
345 COSTS_N_INSNS (17), /* sdiv */
346 COSTS_N_INSNS (17), /* ddiv */
349 /* Instruction costs on RS64A processors. */
351 struct processor_costs rs64a_cost = {
352 COSTS_N_INSNS (20), /* mulsi */
353 COSTS_N_INSNS (12), /* mulsi_const */
354 COSTS_N_INSNS (8), /* mulsi_const9 */
355 COSTS_N_INSNS (34), /* muldi */
356 COSTS_N_INSNS (65), /* divsi */
357 COSTS_N_INSNS (67), /* divdi */
358 COSTS_N_INSNS (4), /* fp */
359 COSTS_N_INSNS (4), /* dmul */
360 COSTS_N_INSNS (31), /* sdiv */
361 COSTS_N_INSNS (31), /* ddiv */
364 /* Instruction costs on MPCCORE processors. */
366 struct processor_costs mpccore_cost = {
367 COSTS_N_INSNS (2), /* mulsi */
368 COSTS_N_INSNS (2), /* mulsi_const */
369 COSTS_N_INSNS (2), /* mulsi_const9 */
370 COSTS_N_INSNS (2), /* muldi */
371 COSTS_N_INSNS (6), /* divsi */
372 COSTS_N_INSNS (6), /* divdi */
373 COSTS_N_INSNS (4), /* fp */
374 COSTS_N_INSNS (5), /* dmul */
375 COSTS_N_INSNS (10), /* sdiv */
376 COSTS_N_INSNS (17), /* ddiv */
379 /* Instruction costs on PPC403 processors. */
381 struct processor_costs ppc403_cost = {
382 COSTS_N_INSNS (4), /* mulsi */
383 COSTS_N_INSNS (4), /* mulsi_const */
384 COSTS_N_INSNS (4), /* mulsi_const9 */
385 COSTS_N_INSNS (4), /* muldi */
386 COSTS_N_INSNS (33), /* divsi */
387 COSTS_N_INSNS (33), /* divdi */
388 COSTS_N_INSNS (11), /* fp */
389 COSTS_N_INSNS (11), /* dmul */
390 COSTS_N_INSNS (11), /* sdiv */
391 COSTS_N_INSNS (11), /* ddiv */
394 /* Instruction costs on PPC405 processors. */
396 struct processor_costs ppc405_cost = {
397 COSTS_N_INSNS (5), /* mulsi */
398 COSTS_N_INSNS (4), /* mulsi_const */
399 COSTS_N_INSNS (3), /* mulsi_const9 */
400 COSTS_N_INSNS (5), /* muldi */
401 COSTS_N_INSNS (35), /* divsi */
402 COSTS_N_INSNS (35), /* divdi */
403 COSTS_N_INSNS (11), /* fp */
404 COSTS_N_INSNS (11), /* dmul */
405 COSTS_N_INSNS (11), /* sdiv */
406 COSTS_N_INSNS (11), /* ddiv */
409 /* Instruction costs on PPC440 processors. */
411 struct processor_costs ppc440_cost = {
412 COSTS_N_INSNS (3), /* mulsi */
413 COSTS_N_INSNS (2), /* mulsi_const */
414 COSTS_N_INSNS (2), /* mulsi_const9 */
415 COSTS_N_INSNS (3), /* muldi */
416 COSTS_N_INSNS (34), /* divsi */
417 COSTS_N_INSNS (34), /* divdi */
418 COSTS_N_INSNS (5), /* fp */
419 COSTS_N_INSNS (5), /* dmul */
420 COSTS_N_INSNS (19), /* sdiv */
421 COSTS_N_INSNS (33), /* ddiv */
424 /* Instruction costs on PPC601 processors. */
426 struct processor_costs ppc601_cost = {
427 COSTS_N_INSNS (5), /* mulsi */
428 COSTS_N_INSNS (5), /* mulsi_const */
429 COSTS_N_INSNS (5), /* mulsi_const9 */
430 COSTS_N_INSNS (5), /* muldi */
431 COSTS_N_INSNS (36), /* divsi */
432 COSTS_N_INSNS (36), /* divdi */
433 COSTS_N_INSNS (4), /* fp */
434 COSTS_N_INSNS (5), /* dmul */
435 COSTS_N_INSNS (17), /* sdiv */
436 COSTS_N_INSNS (31), /* ddiv */
439 /* Instruction costs on PPC603 processors. */
441 struct processor_costs ppc603_cost = {
442 COSTS_N_INSNS (5), /* mulsi */
443 COSTS_N_INSNS (3), /* mulsi_const */
444 COSTS_N_INSNS (2), /* mulsi_const9 */
445 COSTS_N_INSNS (5), /* muldi */
446 COSTS_N_INSNS (37), /* divsi */
447 COSTS_N_INSNS (37), /* divdi */
448 COSTS_N_INSNS (3), /* fp */
449 COSTS_N_INSNS (4), /* dmul */
450 COSTS_N_INSNS (18), /* sdiv */
451 COSTS_N_INSNS (33), /* ddiv */
454 /* Instruction costs on PPC604 processors. */
456 struct processor_costs ppc604_cost = {
457 COSTS_N_INSNS (4), /* mulsi */
458 COSTS_N_INSNS (4), /* mulsi_const */
459 COSTS_N_INSNS (4), /* mulsi_const9 */
460 COSTS_N_INSNS (4), /* muldi */
461 COSTS_N_INSNS (20), /* divsi */
462 COSTS_N_INSNS (20), /* divdi */
463 COSTS_N_INSNS (3), /* fp */
464 COSTS_N_INSNS (3), /* dmul */
465 COSTS_N_INSNS (18), /* sdiv */
466 COSTS_N_INSNS (32), /* ddiv */
469 /* Instruction costs on PPC604e processors. */
471 struct processor_costs ppc604e_cost = {
472 COSTS_N_INSNS (2), /* mulsi */
473 COSTS_N_INSNS (2), /* mulsi_const */
474 COSTS_N_INSNS (2), /* mulsi_const9 */
475 COSTS_N_INSNS (2), /* muldi */
476 COSTS_N_INSNS (20), /* divsi */
477 COSTS_N_INSNS (20), /* divdi */
478 COSTS_N_INSNS (3), /* fp */
479 COSTS_N_INSNS (3), /* dmul */
480 COSTS_N_INSNS (18), /* sdiv */
481 COSTS_N_INSNS (32), /* ddiv */
484 /* Instruction costs on PPC620 processors. */
486 struct processor_costs ppc620_cost = {
487 COSTS_N_INSNS (5), /* mulsi */
488 COSTS_N_INSNS (4), /* mulsi_const */
489 COSTS_N_INSNS (3), /* mulsi_const9 */
490 COSTS_N_INSNS (7), /* muldi */
491 COSTS_N_INSNS (21), /* divsi */
492 COSTS_N_INSNS (37), /* divdi */
493 COSTS_N_INSNS (3), /* fp */
494 COSTS_N_INSNS (3), /* dmul */
495 COSTS_N_INSNS (18), /* sdiv */
496 COSTS_N_INSNS (32), /* ddiv */
499 /* Instruction costs on PPC630 processors. */
501 struct processor_costs ppc630_cost = {
502 COSTS_N_INSNS (5), /* mulsi */
503 COSTS_N_INSNS (4), /* mulsi_const */
504 COSTS_N_INSNS (3), /* mulsi_const9 */
505 COSTS_N_INSNS (7), /* muldi */
506 COSTS_N_INSNS (21), /* divsi */
507 COSTS_N_INSNS (37), /* divdi */
508 COSTS_N_INSNS (3), /* fp */
509 COSTS_N_INSNS (3), /* dmul */
510 COSTS_N_INSNS (17), /* sdiv */
511 COSTS_N_INSNS (21), /* ddiv */
514 /* Instruction costs on PPC750 and PPC7400 processors. */
516 struct processor_costs ppc750_cost = {
517 COSTS_N_INSNS (5), /* mulsi */
518 COSTS_N_INSNS (3), /* mulsi_const */
519 COSTS_N_INSNS (2), /* mulsi_const9 */
520 COSTS_N_INSNS (5), /* muldi */
521 COSTS_N_INSNS (17), /* divsi */
522 COSTS_N_INSNS (17), /* divdi */
523 COSTS_N_INSNS (3), /* fp */
524 COSTS_N_INSNS (3), /* dmul */
525 COSTS_N_INSNS (17), /* sdiv */
526 COSTS_N_INSNS (31), /* ddiv */
529 /* Instruction costs on PPC7450 processors. */
531 struct processor_costs ppc7450_cost = {
532 COSTS_N_INSNS (4), /* mulsi */
533 COSTS_N_INSNS (3), /* mulsi_const */
534 COSTS_N_INSNS (3), /* mulsi_const9 */
535 COSTS_N_INSNS (4), /* muldi */
536 COSTS_N_INSNS (23), /* divsi */
537 COSTS_N_INSNS (23), /* divdi */
538 COSTS_N_INSNS (5), /* fp */
539 COSTS_N_INSNS (5), /* dmul */
540 COSTS_N_INSNS (21), /* sdiv */
541 COSTS_N_INSNS (35), /* ddiv */
544 /* Instruction costs on PPC8540 processors. */
546 struct processor_costs ppc8540_cost = {
547 COSTS_N_INSNS (4), /* mulsi */
548 COSTS_N_INSNS (4), /* mulsi_const */
549 COSTS_N_INSNS (4), /* mulsi_const9 */
550 COSTS_N_INSNS (4), /* muldi */
551 COSTS_N_INSNS (19), /* divsi */
552 COSTS_N_INSNS (19), /* divdi */
553 COSTS_N_INSNS (4), /* fp */
554 COSTS_N_INSNS (4), /* dmul */
555 COSTS_N_INSNS (29), /* sdiv */
556 COSTS_N_INSNS (29), /* ddiv */
559 /* Instruction costs on POWER4 and POWER5 processors. */
561 struct processor_costs power4_cost = {
562 COSTS_N_INSNS (3), /* mulsi */
563 COSTS_N_INSNS (2), /* mulsi_const */
564 COSTS_N_INSNS (2), /* mulsi_const9 */
565 COSTS_N_INSNS (4), /* muldi */
566 COSTS_N_INSNS (18), /* divsi */
567 COSTS_N_INSNS (34), /* divdi */
568 COSTS_N_INSNS (3), /* fp */
569 COSTS_N_INSNS (3), /* dmul */
570 COSTS_N_INSNS (17), /* sdiv */
571 COSTS_N_INSNS (17), /* ddiv */
575 static bool rs6000_function_ok_for_sibcall (tree, tree);
576 static const char *rs6000_invalid_within_doloop (rtx);
577 static rtx rs6000_generate_compare (enum rtx_code);
578 static void rs6000_maybe_dead (rtx);
579 static void rs6000_emit_stack_tie (void);
580 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
581 static rtx spe_synthesize_frame_save (rtx);
582 static bool spe_func_has_64bit_regs_p (void);
583 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
585 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
586 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
587 static unsigned rs6000_hash_constant (rtx);
588 static unsigned toc_hash_function (const void *);
589 static int toc_hash_eq (const void *, const void *);
590 static int constant_pool_expr_1 (rtx, int *, int *);
591 static bool constant_pool_expr_p (rtx);
592 static bool legitimate_small_data_p (enum machine_mode, rtx);
593 static bool legitimate_indexed_address_p (rtx, int);
594 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
595 static struct machine_function * rs6000_init_machine_status (void);
596 static bool rs6000_assemble_integer (rtx, unsigned int, int);
597 static bool no_global_regs_above (int);
598 #ifdef HAVE_GAS_HIDDEN
599 static void rs6000_assemble_visibility (tree, int);
601 static int rs6000_ra_ever_killed (void);
602 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
603 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
604 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
605 static const char *rs6000_mangle_fundamental_type (tree);
606 extern const struct attribute_spec rs6000_attribute_table[];
607 static void rs6000_set_default_type_attributes (tree);
608 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
609 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
610 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
612 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
613 static bool rs6000_return_in_memory (tree, tree);
614 static void rs6000_file_start (void);
616 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
617 static void rs6000_elf_asm_out_constructor (rtx, int);
618 static void rs6000_elf_asm_out_destructor (rtx, int);
619 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
620 static void rs6000_elf_asm_init_sections (void);
621 static section *rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
622 static void rs6000_elf_unique_section (tree, int);
623 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
624 unsigned HOST_WIDE_INT);
625 static void rs6000_elf_encode_section_info (tree, rtx, int)
628 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, rtx);
630 static void rs6000_xcoff_asm_output_anchor (rtx);
631 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
632 static void rs6000_xcoff_asm_init_sections (void);
633 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
634 static section *rs6000_xcoff_select_section (tree, int,
635 unsigned HOST_WIDE_INT);
636 static void rs6000_xcoff_unique_section (tree, int);
637 static section *rs6000_xcoff_select_rtx_section
638 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
639 static const char * rs6000_xcoff_strip_name_encoding (const char *);
640 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
641 static void rs6000_xcoff_file_start (void);
642 static void rs6000_xcoff_file_end (void);
644 static int rs6000_variable_issue (FILE *, int, rtx, int);
645 static bool rs6000_rtx_costs (rtx, int, int, int *);
646 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
647 static bool is_microcoded_insn (rtx);
648 static int is_dispatch_slot_restricted (rtx);
649 static bool is_cracked_insn (rtx);
650 static bool is_branch_slot_insn (rtx);
651 static int rs6000_adjust_priority (rtx, int);
652 static int rs6000_issue_rate (void);
653 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
654 static rtx get_next_active_insn (rtx, rtx);
655 static bool insn_terminates_group_p (rtx , enum group_termination);
656 static bool is_costly_group (rtx *, rtx);
657 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
658 static int redefine_groups (FILE *, int, rtx, rtx);
659 static int pad_groups (FILE *, int, rtx, rtx);
660 static void rs6000_sched_finish (FILE *, int);
661 static int rs6000_use_sched_lookahead (void);
662 static tree rs6000_builtin_mask_for_load (void);
664 static void def_builtin (int, const char *, tree, int);
665 static void rs6000_init_builtins (void);
666 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
667 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
668 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
669 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
670 static void altivec_init_builtins (void);
671 static void rs6000_common_init_builtins (void);
672 static void rs6000_init_libfuncs (void);
674 static void enable_mask_for_builtins (struct builtin_description *, int,
675 enum rs6000_builtins,
676 enum rs6000_builtins);
677 static tree build_opaque_vector_type (tree, int);
678 static void spe_init_builtins (void);
679 static rtx spe_expand_builtin (tree, rtx, bool *);
680 static rtx spe_expand_stv_builtin (enum insn_code, tree);
681 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
682 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
683 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
684 static rs6000_stack_t *rs6000_stack_info (void);
685 static void debug_stack_info (rs6000_stack_t *);
687 static rtx altivec_expand_builtin (tree, rtx, bool *);
688 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
689 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
690 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
691 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
692 static rtx altivec_expand_predicate_builtin (enum insn_code,
693 const char *, tree, rtx);
694 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
695 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
696 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
697 static rtx altivec_expand_vec_set_builtin (tree);
698 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
699 static int get_element_number (tree, tree);
700 static bool rs6000_handle_option (size_t, const char *, int);
701 static void rs6000_parse_tls_size_option (void);
702 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
703 static int first_altivec_reg_to_save (void);
704 static unsigned int compute_vrsave_mask (void);
705 static void compute_save_world_info (rs6000_stack_t *info_ptr);
706 static void is_altivec_return_reg (rtx, void *);
707 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
708 int easy_vector_constant (rtx, enum machine_mode);
709 static bool rs6000_is_opaque_type (tree);
710 static rtx rs6000_dwarf_register_span (rtx);
711 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
712 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
713 static rtx rs6000_tls_get_addr (void);
714 static rtx rs6000_got_sym (void);
715 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
716 static const char *rs6000_get_some_local_dynamic_name (void);
717 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
718 static rtx rs6000_complex_function_value (enum machine_mode);
719 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
720 enum machine_mode, tree);
721 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
723 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
724 tree, HOST_WIDE_INT);
725 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
728 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
731 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
732 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
733 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
734 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
735 enum machine_mode, tree,
737 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
739 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
741 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
743 static void macho_branch_islands (void);
744 static void add_compiler_branch_island (tree, tree, int);
745 static int no_previous_def (tree function_name);
746 static tree get_prev_label (tree function_name);
747 static void rs6000_darwin_file_start (void);
750 static tree rs6000_build_builtin_va_list (void);
751 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
752 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
753 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
754 static bool rs6000_vector_mode_supported_p (enum machine_mode);
755 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
757 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
759 static int get_vsel_insn (enum machine_mode);
760 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
761 static tree rs6000_stack_protect_fail (void);
763 const int INSN_NOT_AVAILABLE = -1;
764 static enum machine_mode rs6000_eh_return_filter_mode (void);
766 /* Hash table stuff for keeping track of TOC entries. */
768 struct toc_hash_struct GTY(())
770 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
771 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
773 enum machine_mode key_mode;
777 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
779 /* Default register names. */
780 char rs6000_reg_names[][8] =
782 "0", "1", "2", "3", "4", "5", "6", "7",
783 "8", "9", "10", "11", "12", "13", "14", "15",
784 "16", "17", "18", "19", "20", "21", "22", "23",
785 "24", "25", "26", "27", "28", "29", "30", "31",
786 "0", "1", "2", "3", "4", "5", "6", "7",
787 "8", "9", "10", "11", "12", "13", "14", "15",
788 "16", "17", "18", "19", "20", "21", "22", "23",
789 "24", "25", "26", "27", "28", "29", "30", "31",
790 "mq", "lr", "ctr","ap",
791 "0", "1", "2", "3", "4", "5", "6", "7",
793 /* AltiVec registers. */
794 "0", "1", "2", "3", "4", "5", "6", "7",
795 "8", "9", "10", "11", "12", "13", "14", "15",
796 "16", "17", "18", "19", "20", "21", "22", "23",
797 "24", "25", "26", "27", "28", "29", "30", "31",
800 "spe_acc", "spefscr",
801 /* Soft frame pointer. */
805 #ifdef TARGET_REGNAMES
806 static const char alt_reg_names[][8] =
808 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
809 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
810 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
811 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
812 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
813 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
814 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
815 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
816 "mq", "lr", "ctr", "ap",
817 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
819 /* AltiVec registers. */
820 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
821 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
822 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
823 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
826 "spe_acc", "spefscr",
827 /* Soft frame pointer. */
832 #ifndef MASK_STRICT_ALIGN
833 #define MASK_STRICT_ALIGN 0
835 #ifndef TARGET_PROFILE_KERNEL
836 #define TARGET_PROFILE_KERNEL 0
839 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
840 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
842 /* Initialize the GCC target structure. */
843 #undef TARGET_ATTRIBUTE_TABLE
844 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
845 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
846 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
848 #undef TARGET_ASM_ALIGNED_DI_OP
849 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
851 /* Default unaligned ops are only provided for ELF. Find the ops needed
852 for non-ELF systems. */
853 #ifndef OBJECT_FORMAT_ELF
855 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
857 #undef TARGET_ASM_UNALIGNED_HI_OP
858 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
859 #undef TARGET_ASM_UNALIGNED_SI_OP
860 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
861 #undef TARGET_ASM_UNALIGNED_DI_OP
862 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
865 #undef TARGET_ASM_UNALIGNED_HI_OP
866 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
867 #undef TARGET_ASM_UNALIGNED_SI_OP
868 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
869 #undef TARGET_ASM_UNALIGNED_DI_OP
870 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
871 #undef TARGET_ASM_ALIGNED_DI_OP
872 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
876 /* This hook deals with fixups for relocatable code and DI-mode objects
878 #undef TARGET_ASM_INTEGER
879 #define TARGET_ASM_INTEGER rs6000_assemble_integer
881 #ifdef HAVE_GAS_HIDDEN
882 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
883 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
886 #undef TARGET_HAVE_TLS
887 #define TARGET_HAVE_TLS HAVE_AS_TLS
889 #undef TARGET_CANNOT_FORCE_CONST_MEM
890 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
892 #undef TARGET_ASM_FUNCTION_PROLOGUE
893 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
894 #undef TARGET_ASM_FUNCTION_EPILOGUE
895 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
897 #undef TARGET_SCHED_VARIABLE_ISSUE
898 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
900 #undef TARGET_SCHED_ISSUE_RATE
901 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
902 #undef TARGET_SCHED_ADJUST_COST
903 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
904 #undef TARGET_SCHED_ADJUST_PRIORITY
905 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
906 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
907 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
908 #undef TARGET_SCHED_FINISH
909 #define TARGET_SCHED_FINISH rs6000_sched_finish
911 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
912 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
914 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
915 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
917 #undef TARGET_INIT_BUILTINS
918 #define TARGET_INIT_BUILTINS rs6000_init_builtins
920 #undef TARGET_EXPAND_BUILTIN
921 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
923 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
924 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
926 #undef TARGET_INIT_LIBFUNCS
927 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
930 #undef TARGET_BINDS_LOCAL_P
931 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
934 #undef TARGET_ASM_OUTPUT_MI_THUNK
935 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
937 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
938 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
940 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
941 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
943 #undef TARGET_INVALID_WITHIN_DOLOOP
944 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
946 #undef TARGET_RTX_COSTS
947 #define TARGET_RTX_COSTS rs6000_rtx_costs
948 #undef TARGET_ADDRESS_COST
949 #define TARGET_ADDRESS_COST hook_int_rtx_0
951 #undef TARGET_VECTOR_OPAQUE_P
952 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
954 #undef TARGET_DWARF_REGISTER_SPAN
955 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
957 /* On rs6000, function arguments are promoted, as are function return
959 #undef TARGET_PROMOTE_FUNCTION_ARGS
960 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
961 #undef TARGET_PROMOTE_FUNCTION_RETURN
962 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
964 #undef TARGET_RETURN_IN_MEMORY
965 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
967 #undef TARGET_SETUP_INCOMING_VARARGS
968 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
970 /* Always strict argument naming on rs6000. */
971 #undef TARGET_STRICT_ARGUMENT_NAMING
972 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
973 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
974 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
975 #undef TARGET_SPLIT_COMPLEX_ARG
976 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
977 #undef TARGET_MUST_PASS_IN_STACK
978 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
979 #undef TARGET_PASS_BY_REFERENCE
980 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
981 #undef TARGET_ARG_PARTIAL_BYTES
982 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
984 #undef TARGET_BUILD_BUILTIN_VA_LIST
985 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
987 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
988 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
990 #undef TARGET_EH_RETURN_FILTER_MODE
991 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
993 #undef TARGET_SCALAR_MODE_SUPPORTED_P
994 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
996 #undef TARGET_VECTOR_MODE_SUPPORTED_P
997 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
999 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1000 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1002 #undef TARGET_HANDLE_OPTION
1003 #define TARGET_HANDLE_OPTION rs6000_handle_option
1005 #undef TARGET_DEFAULT_TARGET_FLAGS
1006 #define TARGET_DEFAULT_TARGET_FLAGS \
1009 #undef TARGET_STACK_PROTECT_FAIL
1010 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1012 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1013 The PowerPC architecture requires only weak consistency among
1014 processors--that is, memory accesses between processors need not be
1015 sequentially consistent and memory accesses among processors can occur
1016 in any order. The ability to order memory accesses weakly provides
1017 opportunities for more efficient use of the system bus. Unless a
1018 dependency exists, the 604e allows read operations to precede store
1020 #undef TARGET_RELAXED_ORDERING
1021 #define TARGET_RELAXED_ORDERING true
1024 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1025 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1028 /* Use a 32-bit anchor range. This leads to sequences like:
1030 addis tmp,anchor,high
1033 where tmp itself acts as an anchor, and can be shared between
1034 accesses to the same 64k page. */
1035 #undef TARGET_MIN_ANCHOR_OFFSET
1036 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1037 #undef TARGET_MAX_ANCHOR_OFFSET
1038 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1039 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1040 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1042 struct gcc_target targetm = TARGET_INITIALIZER;
1045 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1048 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1050 /* The GPRs can hold any mode, but values bigger than one register
1051 cannot go past R31. */
1052 if (INT_REGNO_P (regno))
1053 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1055 /* The float registers can only hold floating modes and DImode.
1056 This also excludes decimal float modes. */
1057 if (FP_REGNO_P (regno))
1059 (SCALAR_FLOAT_MODE_P (mode)
1060 && !DECIMAL_FLOAT_MODE_P (mode)
1061 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1062 || (GET_MODE_CLASS (mode) == MODE_INT
1063 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1065 /* The CR register can only hold CC modes. */
1066 if (CR_REGNO_P (regno))
1067 return GET_MODE_CLASS (mode) == MODE_CC;
1069 if (XER_REGNO_P (regno))
1070 return mode == PSImode;
1072 /* AltiVec only in AldyVec registers. */
1073 if (ALTIVEC_REGNO_P (regno))
1074 return ALTIVEC_VECTOR_MODE (mode);
1076 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1077 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1080 /* We cannot put TImode anywhere except general register and it must be
1081 able to fit within the register set. */
1083 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1086 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1088 rs6000_init_hard_regno_mode_ok (void)
1092 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1093 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1094 if (rs6000_hard_regno_mode_ok (r, m))
1095 rs6000_hard_regno_mode_ok_p[m][r] = true;
1098 /* If not otherwise specified by a target, make 'long double' equivalent to
1101 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1102 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1105 /* Override command line options. Mostly we process the processor
1106 type and sometimes adjust other TARGET_ options. */
1109 rs6000_override_options (const char *default_cpu)
1112 struct rs6000_cpu_select *ptr;
1115 /* Simplifications for entries below. */
1118 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1119 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1122 /* This table occasionally claims that a processor does not support
1123 a particular feature even though it does, but the feature is slower
1124 than the alternative. Thus, it shouldn't be relied on as a
1125 complete description of the processor's support.
1127 Please keep this list in order, and don't forget to update the
1128 documentation in invoke.texi when adding a new processor or
1132 const char *const name; /* Canonical processor name. */
1133 const enum processor_type processor; /* Processor type enum value. */
1134 const int target_enable; /* Target flags to enable. */
1135 } const processor_target_table[]
1136 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1137 {"403", PROCESSOR_PPC403,
1138 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1139 {"405", PROCESSOR_PPC405,
1140 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1141 {"405fp", PROCESSOR_PPC405,
1142 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1143 {"440", PROCESSOR_PPC440,
1144 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1145 {"440fp", PROCESSOR_PPC440,
1146 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1147 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1148 {"601", PROCESSOR_PPC601,
1149 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1150 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1151 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1152 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1153 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1154 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1155 {"620", PROCESSOR_PPC620,
1156 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1157 {"630", PROCESSOR_PPC630,
1158 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1159 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1160 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1161 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1162 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1163 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1164 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1165 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1166 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1167 /* 8548 has a dummy entry for now. */
1168 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1169 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1170 {"970", PROCESSOR_POWER4,
1171 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1172 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1173 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1174 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1175 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1176 {"G5", PROCESSOR_POWER4,
1177 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1178 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1179 {"power2", PROCESSOR_POWER,
1180 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1181 {"power3", PROCESSOR_PPC630,
1182 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1183 {"power4", PROCESSOR_POWER4,
1184 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1185 {"power5", PROCESSOR_POWER5,
1186 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1187 | MASK_MFCRF | MASK_POPCNTB},
1188 {"power5+", PROCESSOR_POWER5,
1189 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1190 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1191 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1192 {"powerpc64", PROCESSOR_POWERPC64,
1193 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1194 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1195 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1196 {"rios2", PROCESSOR_RIOS2,
1197 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1198 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1199 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1200 {"rs64", PROCESSOR_RS64A,
1201 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1204 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1206 /* Some OSs don't support saving the high part of 64-bit registers on
1207 context switch. Other OSs don't support saving Altivec registers.
1208 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1209 settings; if the user wants either, the user must explicitly specify
1210 them and we won't interfere with the user's specification. */
1213 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1214 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1215 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1216 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1220 rs6000_init_hard_regno_mode_ok ();
1222 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1223 #ifdef OS_MISSING_POWERPC64
1224 if (OS_MISSING_POWERPC64)
1225 set_masks &= ~MASK_POWERPC64;
1227 #ifdef OS_MISSING_ALTIVEC
1228 if (OS_MISSING_ALTIVEC)
1229 set_masks &= ~MASK_ALTIVEC;
1232 /* Don't override by the processor default if given explicitly. */
1233 set_masks &= ~target_flags_explicit;
1235 /* Identify the processor type. */
1236 rs6000_select[0].string = default_cpu;
1237 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1239 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1241 ptr = &rs6000_select[i];
1242 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1244 for (j = 0; j < ptt_size; j++)
1245 if (! strcmp (ptr->string, processor_target_table[j].name))
1247 if (ptr->set_tune_p)
1248 rs6000_cpu = processor_target_table[j].processor;
1250 if (ptr->set_arch_p)
1252 target_flags &= ~set_masks;
1253 target_flags |= (processor_target_table[j].target_enable
1260 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1267 /* If we are optimizing big endian systems for space, use the load/store
1268 multiple and string instructions. */
1269 if (BYTES_BIG_ENDIAN && optimize_size)
1270 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1272 /* Don't allow -mmultiple or -mstring on little endian systems
1273 unless the cpu is a 750, because the hardware doesn't support the
1274 instructions used in little endian mode, and causes an alignment
1275 trap. The 750 does not cause an alignment trap (except when the
1276 target is unaligned). */
1278 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1280 if (TARGET_MULTIPLE)
1282 target_flags &= ~MASK_MULTIPLE;
1283 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1284 warning (0, "-mmultiple is not supported on little endian systems");
1289 target_flags &= ~MASK_STRING;
1290 if ((target_flags_explicit & MASK_STRING) != 0)
1291 warning (0, "-mstring is not supported on little endian systems");
1295 /* Set debug flags */
1296 if (rs6000_debug_name)
1298 if (! strcmp (rs6000_debug_name, "all"))
1299 rs6000_debug_stack = rs6000_debug_arg = 1;
1300 else if (! strcmp (rs6000_debug_name, "stack"))
1301 rs6000_debug_stack = 1;
1302 else if (! strcmp (rs6000_debug_name, "arg"))
1303 rs6000_debug_arg = 1;
1305 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1308 if (rs6000_traceback_name)
1310 if (! strncmp (rs6000_traceback_name, "full", 4))
1311 rs6000_traceback = traceback_full;
1312 else if (! strncmp (rs6000_traceback_name, "part", 4))
1313 rs6000_traceback = traceback_part;
1314 else if (! strncmp (rs6000_traceback_name, "no", 2))
1315 rs6000_traceback = traceback_none;
1317 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1318 rs6000_traceback_name);
1321 if (!rs6000_explicit_options.long_double)
1322 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1324 #ifndef POWERPC_LINUX
1325 if (!rs6000_explicit_options.abi)
1326 rs6000_ieeequad = 1;
1329 /* Set Altivec ABI as default for powerpc64 linux. */
1330 if (TARGET_ELF && TARGET_64BIT)
1332 rs6000_altivec_abi = 1;
1333 TARGET_ALTIVEC_VRSAVE = 1;
1336 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1337 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1339 rs6000_darwin64_abi = 1;
1341 darwin_one_byte_bool = 1;
1343 /* Default to natural alignment, for better performance. */
1344 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1347 /* Handle -mtls-size option. */
1348 rs6000_parse_tls_size_option ();
1350 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1351 SUBTARGET_OVERRIDE_OPTIONS;
1353 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1354 SUBSUBTARGET_OVERRIDE_OPTIONS;
1356 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1357 SUB3TARGET_OVERRIDE_OPTIONS;
1363 error ("AltiVec and E500 instructions cannot coexist");
1365 /* The e500 does not have string instructions, and we set
1366 MASK_STRING above when optimizing for size. */
1367 if ((target_flags & MASK_STRING) != 0)
1368 target_flags = target_flags & ~MASK_STRING;
1370 else if (rs6000_select[1].string != NULL)
1372 /* For the powerpc-eabispe configuration, we set all these by
1373 default, so let's unset them if we manually set another
1374 CPU that is not the E500. */
1375 if (!rs6000_explicit_options.abi)
1377 if (!rs6000_explicit_options.spe)
1379 if (!rs6000_explicit_options.float_gprs)
1380 rs6000_float_gprs = 0;
1381 if (!rs6000_explicit_options.isel)
1383 if (!rs6000_explicit_options.long_double)
1384 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1387 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1388 && rs6000_cpu != PROCESSOR_POWER5);
1389 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1390 || rs6000_cpu == PROCESSOR_POWER5);
1392 rs6000_sched_restricted_insns_priority
1393 = (rs6000_sched_groups ? 1 : 0);
1395 /* Handle -msched-costly-dep option. */
1396 rs6000_sched_costly_dep
1397 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1399 if (rs6000_sched_costly_dep_str)
1401 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1402 rs6000_sched_costly_dep = no_dep_costly;
1403 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1404 rs6000_sched_costly_dep = all_deps_costly;
1405 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1406 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1407 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1408 rs6000_sched_costly_dep = store_to_load_dep_costly;
1410 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1413 /* Handle -minsert-sched-nops option. */
1414 rs6000_sched_insert_nops
1415 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1417 if (rs6000_sched_insert_nops_str)
1419 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1420 rs6000_sched_insert_nops = sched_finish_none;
1421 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1422 rs6000_sched_insert_nops = sched_finish_pad_groups;
1423 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1424 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1426 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1429 #ifdef TARGET_REGNAMES
1430 /* If the user desires alternate register names, copy in the
1431 alternate names now. */
1432 if (TARGET_REGNAMES)
1433 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1436 /* Set aix_struct_return last, after the ABI is determined.
1437 If -maix-struct-return or -msvr4-struct-return was explicitly
1438 used, don't override with the ABI default. */
1439 if (!rs6000_explicit_options.aix_struct_ret)
1440 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1442 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1443 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1446 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1448 /* We can only guarantee the availability of DI pseudo-ops when
1449 assembling for 64-bit targets. */
1452 targetm.asm_out.aligned_op.di = NULL;
1453 targetm.asm_out.unaligned_op.di = NULL;
1456 /* Set branch target alignment, if not optimizing for size. */
1459 if (rs6000_sched_groups)
1461 if (align_functions <= 0)
1462 align_functions = 16;
1463 if (align_jumps <= 0)
1465 if (align_loops <= 0)
1468 if (align_jumps_max_skip <= 0)
1469 align_jumps_max_skip = 15;
1470 if (align_loops_max_skip <= 0)
1471 align_loops_max_skip = 15;
1474 /* Arrange to save and restore machine status around nested functions. */
1475 init_machine_status = rs6000_init_machine_status;
1477 /* We should always be splitting complex arguments, but we can't break
1478 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1479 if (DEFAULT_ABI != ABI_AIX)
1480 targetm.calls.split_complex_arg = NULL;
1482 /* Initialize rs6000_cost with the appropriate target costs. */
1484 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1488 case PROCESSOR_RIOS1:
1489 rs6000_cost = &rios1_cost;
1492 case PROCESSOR_RIOS2:
1493 rs6000_cost = &rios2_cost;
1496 case PROCESSOR_RS64A:
1497 rs6000_cost = &rs64a_cost;
1500 case PROCESSOR_MPCCORE:
1501 rs6000_cost = &mpccore_cost;
1504 case PROCESSOR_PPC403:
1505 rs6000_cost = &ppc403_cost;
1508 case PROCESSOR_PPC405:
1509 rs6000_cost = &ppc405_cost;
1512 case PROCESSOR_PPC440:
1513 rs6000_cost = &ppc440_cost;
1516 case PROCESSOR_PPC601:
1517 rs6000_cost = &ppc601_cost;
1520 case PROCESSOR_PPC603:
1521 rs6000_cost = &ppc603_cost;
1524 case PROCESSOR_PPC604:
1525 rs6000_cost = &ppc604_cost;
1528 case PROCESSOR_PPC604e:
1529 rs6000_cost = &ppc604e_cost;
1532 case PROCESSOR_PPC620:
1533 rs6000_cost = &ppc620_cost;
1536 case PROCESSOR_PPC630:
1537 rs6000_cost = &ppc630_cost;
1540 case PROCESSOR_PPC750:
1541 case PROCESSOR_PPC7400:
1542 rs6000_cost = &ppc750_cost;
1545 case PROCESSOR_PPC7450:
1546 rs6000_cost = &ppc7450_cost;
1549 case PROCESSOR_PPC8540:
1550 rs6000_cost = &ppc8540_cost;
1553 case PROCESSOR_POWER4:
1554 case PROCESSOR_POWER5:
1555 rs6000_cost = &power4_cost;
1563 /* Implement targetm.vectorize.builtin_mask_for_load. */
1565 rs6000_builtin_mask_for_load (void)
1568 return altivec_builtin_mask_for_load;
1573 /* Handle generic options of the form -mfoo=yes/no.
1574 NAME is the option name.
1575 VALUE is the option value.
1576 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1577 whether the option value is 'yes' or 'no' respectively. */
1579 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1583 else if (!strcmp (value, "yes"))
1585 else if (!strcmp (value, "no"))
1588 error ("unknown -m%s= option specified: '%s'", name, value);
1591 /* Validate and record the size specified with the -mtls-size option. */
1594 rs6000_parse_tls_size_option (void)
1596 if (rs6000_tls_size_string == 0)
1598 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1599 rs6000_tls_size = 16;
1600 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1601 rs6000_tls_size = 32;
1602 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1603 rs6000_tls_size = 64;
1605 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1609 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1611 if (DEFAULT_ABI == ABI_DARWIN)
1612 /* The Darwin libraries never set errno, so we might as well
1613 avoid calling them when that's the only reason we would. */
1614 flag_errno_math = 0;
1616 /* Double growth factor to counter reduced min jump length. */
1617 set_param_value ("max-grow-copy-bb-insns", 16);
1620 /* Implement TARGET_HANDLE_OPTION. */
1623 rs6000_handle_option (size_t code, const char *arg, int value)
1628 target_flags &= ~(MASK_POWER | MASK_POWER2
1629 | MASK_MULTIPLE | MASK_STRING);
1630 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1631 | MASK_MULTIPLE | MASK_STRING);
1633 case OPT_mno_powerpc:
1634 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1635 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1636 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1637 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1640 target_flags &= ~MASK_MINIMAL_TOC;
1641 TARGET_NO_FP_IN_TOC = 0;
1642 TARGET_NO_SUM_IN_TOC = 0;
1643 target_flags_explicit |= MASK_MINIMAL_TOC;
1644 #ifdef TARGET_USES_SYSV4_OPT
1645 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1646 just the same as -mminimal-toc. */
1647 target_flags |= MASK_MINIMAL_TOC;
1648 target_flags_explicit |= MASK_MINIMAL_TOC;
1652 #ifdef TARGET_USES_SYSV4_OPT
1654 /* Make -mtoc behave like -mminimal-toc. */
1655 target_flags |= MASK_MINIMAL_TOC;
1656 target_flags_explicit |= MASK_MINIMAL_TOC;
1660 #ifdef TARGET_USES_AIX64_OPT
1665 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
1666 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
1667 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
1670 #ifdef TARGET_USES_AIX64_OPT
1675 target_flags &= ~MASK_POWERPC64;
1676 target_flags_explicit |= MASK_POWERPC64;
1679 case OPT_minsert_sched_nops_:
1680 rs6000_sched_insert_nops_str = arg;
1683 case OPT_mminimal_toc:
1686 TARGET_NO_FP_IN_TOC = 0;
1687 TARGET_NO_SUM_IN_TOC = 0;
1694 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1695 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1702 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1703 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1707 case OPT_mpowerpc_gpopt:
1708 case OPT_mpowerpc_gfxopt:
1711 target_flags |= MASK_POWERPC;
1712 target_flags_explicit |= MASK_POWERPC;
1716 case OPT_maix_struct_return:
1717 case OPT_msvr4_struct_return:
1718 rs6000_explicit_options.aix_struct_ret = true;
1722 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1726 rs6000_explicit_options.isel = true;
1727 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1731 rs6000_explicit_options.spe = true;
1732 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1733 /* No SPE means 64-bit long doubles, even if an E500. */
1735 rs6000_long_double_type_size = 64;
1739 rs6000_debug_name = arg;
1742 #ifdef TARGET_USES_SYSV4_OPT
1744 rs6000_abi_name = arg;
1748 rs6000_sdata_name = arg;
1751 case OPT_mtls_size_:
1752 rs6000_tls_size_string = arg;
1755 case OPT_mrelocatable:
1758 target_flags |= MASK_MINIMAL_TOC;
1759 target_flags_explicit |= MASK_MINIMAL_TOC;
1760 TARGET_NO_FP_IN_TOC = 1;
1764 case OPT_mrelocatable_lib:
1767 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
1768 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
1769 TARGET_NO_FP_IN_TOC = 1;
1773 target_flags &= ~MASK_RELOCATABLE;
1774 target_flags_explicit |= MASK_RELOCATABLE;
1780 rs6000_explicit_options.abi = true;
1781 if (!strcmp (arg, "altivec"))
1783 rs6000_altivec_abi = 1;
1786 else if (! strcmp (arg, "no-altivec"))
1787 rs6000_altivec_abi = 0;
1788 else if (! strcmp (arg, "spe"))
1791 rs6000_altivec_abi = 0;
1792 if (!TARGET_SPE_ABI)
1793 error ("not configured for ABI: '%s'", arg);
1795 else if (! strcmp (arg, "no-spe"))
1798 /* These are here for testing during development only, do not
1799 document in the manual please. */
1800 else if (! strcmp (arg, "d64"))
1802 rs6000_darwin64_abi = 1;
1803 warning (0, "Using darwin64 ABI");
1805 else if (! strcmp (arg, "d32"))
1807 rs6000_darwin64_abi = 0;
1808 warning (0, "Using old darwin ABI");
1811 else if (! strcmp (arg, "ibmlongdouble"))
1813 rs6000_ieeequad = 0;
1814 warning (0, "Using IBM extended precision long double");
1816 else if (! strcmp (arg, "ieeelongdouble"))
1818 rs6000_ieeequad = 1;
1819 warning (0, "Using IEEE extended precision long double");
1824 error ("unknown ABI specified: '%s'", arg);
1830 rs6000_select[1].string = arg;
1834 rs6000_select[2].string = arg;
1837 case OPT_mtraceback_:
1838 rs6000_traceback_name = arg;
1841 case OPT_mfloat_gprs_:
1842 rs6000_explicit_options.float_gprs = true;
1843 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
1844 rs6000_float_gprs = 1;
1845 else if (! strcmp (arg, "double"))
1846 rs6000_float_gprs = 2;
1847 else if (! strcmp (arg, "no"))
1848 rs6000_float_gprs = 0;
1851 error ("invalid option for -mfloat-gprs: '%s'", arg);
1856 case OPT_mlong_double_:
1857 rs6000_explicit_options.long_double = true;
1858 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1859 if (value != 64 && value != 128)
1861 error ("Unknown switch -mlong-double-%s", arg);
1862 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1866 rs6000_long_double_type_size = value;
1869 case OPT_msched_costly_dep_:
1870 rs6000_sched_costly_dep_str = arg;
1874 rs6000_explicit_options.alignment = true;
1875 if (! strcmp (arg, "power"))
1877 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1878 some C library functions, so warn about it. The flag may be
1879 useful for performance studies from time to time though, so
1880 don't disable it entirely. */
1881 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1882 warning (0, "-malign-power is not supported for 64-bit Darwin;"
1883 " it is incompatible with the installed C and C++ libraries");
1884 rs6000_alignment_flags = MASK_ALIGN_POWER;
1886 else if (! strcmp (arg, "natural"))
1887 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1890 error ("unknown -malign-XXXXX option specified: '%s'", arg);
1898 /* Do anything needed at the start of the asm file. */
1901 rs6000_file_start (void)
1905 const char *start = buffer;
1906 struct rs6000_cpu_select *ptr;
1907 const char *default_cpu = TARGET_CPU_DEFAULT;
1908 FILE *file = asm_out_file;
1910 default_file_start ();
1912 #ifdef TARGET_BI_ARCH
1913 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1917 if (flag_verbose_asm)
1919 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1920 rs6000_select[0].string = default_cpu;
1922 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1924 ptr = &rs6000_select[i];
1925 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1927 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1932 if (PPC405_ERRATUM77)
1934 fprintf (file, "%s PPC405CR_ERRATUM77", start);
1938 #ifdef USING_ELFOS_H
1939 switch (rs6000_sdata)
1941 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1942 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1943 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1944 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1947 if (rs6000_sdata && g_switch_value)
1949 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1959 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1961 switch_to_section (toc_section);
1962 switch_to_section (text_section);
1967 /* Return nonzero if this function is known to have a null epilogue. */
1970 direct_return (void)
1972 if (reload_completed)
1974 rs6000_stack_t *info = rs6000_stack_info ();
1976 if (info->first_gp_reg_save == 32
1977 && info->first_fp_reg_save == 64
1978 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1979 && ! info->lr_save_p
1980 && ! info->cr_save_p
1981 && info->vrsave_mask == 0
1989 /* Return the number of instructions it takes to form a constant in an
1990 integer register. */
1993 num_insns_constant_wide (HOST_WIDE_INT value)
1995 /* signed constant loadable with {cal|addi} */
1996 if (satisfies_constraint_I (GEN_INT (value)))
1999 /* constant loadable with {cau|addis} */
2000 else if (satisfies_constraint_L (GEN_INT (value)))
2003 #if HOST_BITS_PER_WIDE_INT == 64
2004 else if (TARGET_POWERPC64)
2006 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2007 HOST_WIDE_INT high = value >> 31;
2009 if (high == 0 || high == -1)
2015 return num_insns_constant_wide (high) + 1;
2017 return (num_insns_constant_wide (high)
2018 + num_insns_constant_wide (low) + 1);
2027 num_insns_constant (rtx op, enum machine_mode mode)
2029 HOST_WIDE_INT low, high;
2031 switch (GET_CODE (op))
2034 #if HOST_BITS_PER_WIDE_INT == 64
2035 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2036 && mask64_operand (op, mode))
2040 return num_insns_constant_wide (INTVAL (op));
2048 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2049 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2050 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2053 if (mode == VOIDmode || mode == DImode)
2055 high = CONST_DOUBLE_HIGH (op);
2056 low = CONST_DOUBLE_LOW (op);
2063 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2064 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2065 high = l[WORDS_BIG_ENDIAN == 0];
2066 low = l[WORDS_BIG_ENDIAN != 0];
2070 return (num_insns_constant_wide (low)
2071 + num_insns_constant_wide (high));
2074 if ((high == 0 && low >= 0)
2075 || (high == -1 && low < 0))
2076 return num_insns_constant_wide (low);
2078 else if (mask64_operand (op, mode))
2082 return num_insns_constant_wide (high) + 1;
2085 return (num_insns_constant_wide (high)
2086 + num_insns_constant_wide (low) + 1);
2095 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2096 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2097 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2098 all items are set to the same value and contain COPIES replicas of the
2099 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2100 operand and the others are set to the value of the operand's msb. */
2103 vspltis_constant (rtx op, unsigned step, unsigned copies)
2105 enum machine_mode mode = GET_MODE (op);
2106 enum machine_mode inner = GET_MODE_INNER (mode);
2109 unsigned nunits = GET_MODE_NUNITS (mode);
2110 unsigned bitsize = GET_MODE_BITSIZE (inner);
2111 unsigned mask = GET_MODE_MASK (inner);
2113 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2114 HOST_WIDE_INT val = INTVAL (last);
2115 HOST_WIDE_INT splat_val = val;
2116 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2118 /* Construct the value to be splatted, if possible. If not, return 0. */
2119 for (i = 2; i <= copies; i *= 2)
2121 HOST_WIDE_INT small_val;
2123 small_val = splat_val >> bitsize;
2125 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2127 splat_val = small_val;
2130 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2131 if (EASY_VECTOR_15 (splat_val))
2134 /* Also check if we can splat, and then add the result to itself. Do so if
2135 the value is positive, of if the splat instruction is using OP's mode;
2136 for splat_val < 0, the splat and the add should use the same mode. */
2137 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2138 && (splat_val >= 0 || (step == 1 && copies == 1)))
2144 /* Check if VAL is present in every STEP-th element, and the
2145 other elements are filled with its most significant bit. */
2146 for (i = 0; i < nunits - 1; ++i)
2148 HOST_WIDE_INT desired_val;
2149 if (((i + 1) & (step - 1)) == 0)
2152 desired_val = msb_val;
2154 if (desired_val != INTVAL (CONST_VECTOR_ELT (op, i)))
2162 /* Return true if OP is of the given MODE and can be synthesized
2163 with a vspltisb, vspltish or vspltisw. */
2166 easy_altivec_constant (rtx op, enum machine_mode mode)
2168 unsigned step, copies;
2170 if (mode == VOIDmode)
2171 mode = GET_MODE (op);
2172 else if (mode != GET_MODE (op))
2175 /* Start with a vspltisw. */
2176 step = GET_MODE_NUNITS (mode) / 4;
2179 if (vspltis_constant (op, step, copies))
2182 /* Then try with a vspltish. */
2188 if (vspltis_constant (op, step, copies))
2191 /* And finally a vspltisb. */
2197 if (vspltis_constant (op, step, copies))
2203 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2204 result is OP. Abort if it is not possible. */
2207 gen_easy_altivec_constant (rtx op)
2209 enum machine_mode mode = GET_MODE (op);
2210 int nunits = GET_MODE_NUNITS (mode);
2211 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2212 unsigned step = nunits / 4;
2213 unsigned copies = 1;
2215 /* Start with a vspltisw. */
2216 if (vspltis_constant (op, step, copies))
2217 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2219 /* Then try with a vspltish. */
2225 if (vspltis_constant (op, step, copies))
2226 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2228 /* And finally a vspltisb. */
2234 if (vspltis_constant (op, step, copies))
2235 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2241 output_vec_const_move (rtx *operands)
2244 enum machine_mode mode;
2249 mode = GET_MODE (dest);
2254 if (zero_constant (vec, mode))
2255 return "vxor %0,%0,%0";
2257 splat_vec = gen_easy_altivec_constant (vec);
2258 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2259 operands[1] = XEXP (splat_vec, 0);
2260 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2263 switch (GET_MODE (splat_vec))
2266 return "vspltisw %0,%1";
2269 return "vspltish %0,%1";
2272 return "vspltisb %0,%1";
2279 gcc_assert (TARGET_SPE);
2281 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2282 pattern of V1DI, V4HI, and V2SF.
2284 FIXME: We should probably return # and add post reload
2285 splitters for these, but this way is so easy ;-). */
2286 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2287 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2288 operands[1] = CONST_VECTOR_ELT (vec, 0);
2289 operands[2] = CONST_VECTOR_ELT (vec, 1);
2291 return "li %0,%1\n\tevmergelo %0,%0,%0";
2293 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2296 /* Initialize vector TARGET to VALS. */
2299 rs6000_expand_vector_init (rtx target, rtx vals)
2301 enum machine_mode mode = GET_MODE (target);
2302 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2303 int n_elts = GET_MODE_NUNITS (mode);
2304 int n_var = 0, one_var = -1;
2305 bool all_same = true, all_const_zero = true;
2309 for (i = 0; i < n_elts; ++i)
2311 x = XVECEXP (vals, 0, i);
2312 if (!CONSTANT_P (x))
2313 ++n_var, one_var = i;
2314 else if (x != CONST0_RTX (inner_mode))
2315 all_const_zero = false;
2317 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2323 if (mode != V4SFmode && all_const_zero)
2325 /* Zero register. */
2326 emit_insn (gen_rtx_SET (VOIDmode, target,
2327 gen_rtx_XOR (mode, target, target)));
2330 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2332 /* Splat immediate. */
2333 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2337 ; /* Splat vector element. */
2340 /* Load from constant pool. */
2341 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2346 /* Store value to stack temp. Load vector element. Splat. */
2349 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2350 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2351 XVECEXP (vals, 0, 0));
2352 x = gen_rtx_UNSPEC (VOIDmode,
2353 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2354 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2356 gen_rtx_SET (VOIDmode,
2359 x = gen_rtx_VEC_SELECT (inner_mode, target,
2360 gen_rtx_PARALLEL (VOIDmode,
2361 gen_rtvec (1, const0_rtx)));
2362 emit_insn (gen_rtx_SET (VOIDmode, target,
2363 gen_rtx_VEC_DUPLICATE (mode, x)));
2367 /* One field is non-constant. Load constant then overwrite
2371 rtx copy = copy_rtx (vals);
2373 /* Load constant part of vector, substitute neighboring value for
2375 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2376 rs6000_expand_vector_init (target, copy);
2378 /* Insert variable. */
2379 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2383 /* Construct the vector in memory one field at a time
2384 and load the whole vector. */
2385 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2386 for (i = 0; i < n_elts; i++)
2387 emit_move_insn (adjust_address_nv (mem, inner_mode,
2388 i * GET_MODE_SIZE (inner_mode)),
2389 XVECEXP (vals, 0, i));
2390 emit_move_insn (target, mem);
2393 /* Set field ELT of TARGET to VAL. */
2396 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2398 enum machine_mode mode = GET_MODE (target);
2399 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2400 rtx reg = gen_reg_rtx (mode);
2402 int width = GET_MODE_SIZE (inner_mode);
2405 /* Load single variable value. */
2406 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2407 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2408 x = gen_rtx_UNSPEC (VOIDmode,
2409 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2410 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2412 gen_rtx_SET (VOIDmode,
2416 /* Linear sequence. */
2417 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2418 for (i = 0; i < 16; ++i)
2419 XVECEXP (mask, 0, i) = GEN_INT (i);
2421 /* Set permute mask to insert element into target. */
2422 for (i = 0; i < width; ++i)
2423 XVECEXP (mask, 0, elt*width + i)
2424 = GEN_INT (i + 0x10);
2425 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2426 x = gen_rtx_UNSPEC (mode,
2427 gen_rtvec (3, target, reg,
2428 force_reg (V16QImode, x)),
2430 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2433 /* Extract field ELT from VEC into TARGET. */
2436 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2438 enum machine_mode mode = GET_MODE (vec);
2439 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2442 /* Allocate mode-sized buffer. */
2443 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2445 /* Add offset to field within buffer matching vector element. */
2446 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2448 /* Store single field into mode-sized buffer. */
2449 x = gen_rtx_UNSPEC (VOIDmode,
2450 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2451 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2453 gen_rtx_SET (VOIDmode,
2456 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2459 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2460 implement ANDing by the mask IN. */
2462 build_mask64_2_operands (rtx in, rtx *out)
2464 #if HOST_BITS_PER_WIDE_INT >= 64
2465 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2468 gcc_assert (GET_CODE (in) == CONST_INT);
2473 /* Assume c initially something like 0x00fff000000fffff. The idea
2474 is to rotate the word so that the middle ^^^^^^ group of zeros
2475 is at the MS end and can be cleared with an rldicl mask. We then
2476 rotate back and clear off the MS ^^ group of zeros with a
2478 c = ~c; /* c == 0xff000ffffff00000 */
2479 lsb = c & -c; /* lsb == 0x0000000000100000 */
2480 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2481 c = ~c; /* c == 0x00fff000000fffff */
2482 c &= -lsb; /* c == 0x00fff00000000000 */
2483 lsb = c & -c; /* lsb == 0x0000100000000000 */
2484 c = ~c; /* c == 0xff000fffffffffff */
2485 c &= -lsb; /* c == 0xff00000000000000 */
2487 while ((lsb >>= 1) != 0)
2488 shift++; /* shift == 44 on exit from loop */
2489 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2490 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2491 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2495 /* Assume c initially something like 0xff000f0000000000. The idea
2496 is to rotate the word so that the ^^^ middle group of zeros
2497 is at the LS end and can be cleared with an rldicr mask. We then
2498 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2500 lsb = c & -c; /* lsb == 0x0000010000000000 */
2501 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2502 c = ~c; /* c == 0x00fff0ffffffffff */
2503 c &= -lsb; /* c == 0x00fff00000000000 */
2504 lsb = c & -c; /* lsb == 0x0000100000000000 */
2505 c = ~c; /* c == 0xff000fffffffffff */
2506 c &= -lsb; /* c == 0xff00000000000000 */
2508 while ((lsb >>= 1) != 0)
2509 shift++; /* shift == 44 on exit from loop */
2510 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2511 m1 >>= shift; /* m1 == 0x0000000000000fff */
2512 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2515 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2516 masks will be all 1's. We are guaranteed more than one transition. */
2517 out[0] = GEN_INT (64 - shift);
2518 out[1] = GEN_INT (m1);
2519 out[2] = GEN_INT (shift);
2520 out[3] = GEN_INT (m2);
2528 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2531 invalid_e500_subreg (rtx op, enum machine_mode mode)
2533 /* Reject (subreg:SI (reg:DF)). */
2534 if (GET_CODE (op) == SUBREG
2536 && REG_P (SUBREG_REG (op))
2537 && GET_MODE (SUBREG_REG (op)) == DFmode)
2540 /* Reject (subreg:DF (reg:DI)). */
2541 if (GET_CODE (op) == SUBREG
2543 && REG_P (SUBREG_REG (op))
2544 && GET_MODE (SUBREG_REG (op)) == DImode)
2550 /* Darwin, AIX increases natural record alignment to doubleword if the first
2551 field is an FP double while the FP fields remain word aligned. */
2554 rs6000_special_round_type_align (tree type, unsigned int computed,
2555 unsigned int specified)
2557 unsigned int align = MAX (computed, specified);
2558 tree field = TYPE_FIELDS (type);
2560 /* Skip all non field decls */
2561 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2562 field = TREE_CHAIN (field);
2564 if (field != NULL && field != type)
2566 type = TREE_TYPE (field);
2567 while (TREE_CODE (type) == ARRAY_TYPE)
2568 type = TREE_TYPE (type);
2570 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2571 align = MAX (align, 64);
2577 /* Return 1 for an operand in small memory on V.4/eabi. */
2580 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2581 enum machine_mode mode ATTRIBUTE_UNUSED)
2586 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2589 if (DEFAULT_ABI != ABI_V4)
2592 if (GET_CODE (op) == SYMBOL_REF)
2595 else if (GET_CODE (op) != CONST
2596 || GET_CODE (XEXP (op, 0)) != PLUS
2597 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2598 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2603 rtx sum = XEXP (op, 0);
2604 HOST_WIDE_INT summand;
2606 /* We have to be careful here, because it is the referenced address
2607 that must be 32k from _SDA_BASE_, not just the symbol. */
2608 summand = INTVAL (XEXP (sum, 1));
2609 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2612 sym_ref = XEXP (sum, 0);
2615 return SYMBOL_REF_SMALL_P (sym_ref);
2621 /* Return true if either operand is a general purpose register. */
2624 gpr_or_gpr_p (rtx op0, rtx op1)
2626 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2627 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2631 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2634 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2636 switch (GET_CODE (op))
2639 if (RS6000_SYMBOL_REF_TLS_P (op))
2641 else if (CONSTANT_POOL_ADDRESS_P (op))
2643 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2651 else if (! strcmp (XSTR (op, 0), toc_label_name))
2660 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2661 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2663 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2672 constant_pool_expr_p (rtx op)
2676 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2680 toc_relative_expr_p (rtx op)
2684 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2688 legitimate_constant_pool_address_p (rtx x)
2691 && GET_CODE (x) == PLUS
2692 && GET_CODE (XEXP (x, 0)) == REG
2693 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2694 && constant_pool_expr_p (XEXP (x, 1)));
2698 legitimate_small_data_p (enum machine_mode mode, rtx x)
2700 return (DEFAULT_ABI == ABI_V4
2701 && !flag_pic && !TARGET_TOC
2702 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2703 && small_data_operand (x, mode));
2706 /* SPE offset addressing is limited to 5-bits worth of double words. */
2707 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2710 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2712 unsigned HOST_WIDE_INT offset, extra;
2714 if (GET_CODE (x) != PLUS)
2716 if (GET_CODE (XEXP (x, 0)) != REG)
2718 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2720 if (legitimate_constant_pool_address_p (x))
2722 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2725 offset = INTVAL (XEXP (x, 1));
2733 /* AltiVec vector modes. Only reg+reg addressing is valid and
2734 constant offset zero should not occur due to canonicalization.
2735 Allow any offset when not strict before reload. */
2742 /* SPE vector modes. */
2743 return SPE_CONST_OFFSET_OK (offset);
2746 if (TARGET_E500_DOUBLE)
2747 return SPE_CONST_OFFSET_OK (offset);
2750 /* On e500v2, we may have:
2752 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2754 Which gets addressed with evldd instructions. */
2755 if (TARGET_E500_DOUBLE)
2756 return SPE_CONST_OFFSET_OK (offset);
2758 if (mode == DFmode || !TARGET_POWERPC64)
2760 else if (offset & 3)
2766 if (mode == TFmode || !TARGET_POWERPC64)
2768 else if (offset & 3)
2779 return (offset < 0x10000) && (offset + extra < 0x10000);
2783 legitimate_indexed_address_p (rtx x, int strict)
2787 if (GET_CODE (x) != PLUS)
2793 /* Recognize the rtl generated by reload which we know will later be
2794 replaced with proper base and index regs. */
2796 && reload_in_progress
2797 && (REG_P (op0) || GET_CODE (op0) == PLUS)
2801 return (REG_P (op0) && REG_P (op1)
2802 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
2803 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2804 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2805 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
2809 legitimate_indirect_address_p (rtx x, int strict)
2811 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2815 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2817 if (!TARGET_MACHO || !flag_pic
2818 || mode != SImode || GET_CODE (x) != MEM)
2822 if (GET_CODE (x) != LO_SUM)
2824 if (GET_CODE (XEXP (x, 0)) != REG)
2826 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2830 return CONSTANT_P (x);
2834 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2836 if (GET_CODE (x) != LO_SUM)
2838 if (GET_CODE (XEXP (x, 0)) != REG)
2840 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2842 /* Restrict addressing for DI because of our SUBREG hackery. */
2843 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
2847 if (TARGET_ELF || TARGET_MACHO)
2849 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2853 if (GET_MODE_NUNITS (mode) != 1)
2855 if (GET_MODE_BITSIZE (mode) > 64
2856 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2857 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
2860 return CONSTANT_P (x);
2867 /* Try machine-dependent ways of modifying an illegitimate address
2868 to be legitimate. If we find one, return the new, valid address.
2869 This is used from only one place: `memory_address' in explow.c.
2871 OLDX is the address as it was before break_out_memory_refs was
2872 called. In some cases it is useful to look at this to decide what
2875 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2877 It is always safe for this function to do nothing. It exists to
2878 recognize opportunities to optimize the output.
2880 On RS/6000, first check for the sum of a register with a constant
2881 integer that is out of range. If so, generate code to add the
2882 constant with the low-order 16 bits masked to the register and force
2883 this result into another register (this can be done with `cau').
2884 Then generate an address of REG+(CONST&0xffff), allowing for the
2885 possibility of bit 16 being a one.
2887 Then check for the sum of a register and something not constant, try to
2888 load the other things into a register and return the sum. */
2891 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2892 enum machine_mode mode)
2894 if (GET_CODE (x) == SYMBOL_REF)
2896 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2898 return rs6000_legitimize_tls_address (x, model);
2901 if (GET_CODE (x) == PLUS
2902 && GET_CODE (XEXP (x, 0)) == REG
2903 && GET_CODE (XEXP (x, 1)) == CONST_INT
2904 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2906 HOST_WIDE_INT high_int, low_int;
2908 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2909 high_int = INTVAL (XEXP (x, 1)) - low_int;
2910 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2911 GEN_INT (high_int)), 0);
2912 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2914 else if (GET_CODE (x) == PLUS
2915 && GET_CODE (XEXP (x, 0)) == REG
2916 && GET_CODE (XEXP (x, 1)) != CONST_INT
2917 && GET_MODE_NUNITS (mode) == 1
2918 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2920 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2922 && (TARGET_POWERPC64 || mode != DImode)
2925 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2926 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2928 else if (ALTIVEC_VECTOR_MODE (mode))
2932 /* Make sure both operands are registers. */
2933 if (GET_CODE (x) == PLUS)
2934 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2935 force_reg (Pmode, XEXP (x, 1)));
2937 reg = force_reg (Pmode, x);
2940 else if (SPE_VECTOR_MODE (mode)
2941 || (TARGET_E500_DOUBLE && (mode == DFmode
2942 || mode == DImode)))
2946 /* We accept [reg + reg] and [reg + OFFSET]. */
2948 if (GET_CODE (x) == PLUS)
2950 rtx op1 = XEXP (x, 0);
2951 rtx op2 = XEXP (x, 1);
2953 op1 = force_reg (Pmode, op1);
2955 if (GET_CODE (op2) != REG
2956 && (GET_CODE (op2) != CONST_INT
2957 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2958 op2 = force_reg (Pmode, op2);
2960 return gen_rtx_PLUS (Pmode, op1, op2);
2963 return force_reg (Pmode, x);
2969 && GET_CODE (x) != CONST_INT
2970 && GET_CODE (x) != CONST_DOUBLE
2972 && GET_MODE_NUNITS (mode) == 1
2973 && (GET_MODE_BITSIZE (mode) <= 32
2974 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2976 rtx reg = gen_reg_rtx (Pmode);
2977 emit_insn (gen_elf_high (reg, x));
2978 return gen_rtx_LO_SUM (Pmode, reg, x);
2980 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2983 && ! MACHO_DYNAMIC_NO_PIC_P
2985 && GET_CODE (x) != CONST_INT
2986 && GET_CODE (x) != CONST_DOUBLE
2988 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2992 rtx reg = gen_reg_rtx (Pmode);
2993 emit_insn (gen_macho_high (reg, x));
2994 return gen_rtx_LO_SUM (Pmode, reg, x);
2997 && constant_pool_expr_p (x)
2998 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3000 return create_TOC_reference (x);
3006 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3007 We need to emit DTP-relative relocations. */
3010 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3015 fputs ("\t.long\t", file);
3018 fputs (DOUBLE_INT_ASM_OP, file);
3023 output_addr_const (file, x);
3024 fputs ("@dtprel+0x8000", file);
3027 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3029 static GTY(()) rtx rs6000_tls_symbol;
3031 rs6000_tls_get_addr (void)
3033 if (!rs6000_tls_symbol)
3034 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3036 return rs6000_tls_symbol;
3039 /* Construct the SYMBOL_REF for TLS GOT references. */
3041 static GTY(()) rtx rs6000_got_symbol;
3043 rs6000_got_sym (void)
3045 if (!rs6000_got_symbol)
3047 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3048 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3049 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3052 return rs6000_got_symbol;
3055 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3056 this (thread-local) address. */
3059 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3063 dest = gen_reg_rtx (Pmode);
3064 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3070 tlsreg = gen_rtx_REG (Pmode, 13);
3071 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3075 tlsreg = gen_rtx_REG (Pmode, 2);
3076 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3080 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3084 tmp = gen_reg_rtx (Pmode);
3087 tlsreg = gen_rtx_REG (Pmode, 13);
3088 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3092 tlsreg = gen_rtx_REG (Pmode, 2);
3093 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3097 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3099 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3104 rtx r3, got, tga, tmp1, tmp2, eqv;
3106 /* We currently use relocations like @got@tlsgd for tls, which
3107 means the linker will handle allocation of tls entries, placing
3108 them in the .got section. So use a pointer to the .got section,
3109 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3110 or to secondary GOT sections used by 32-bit -fPIC. */
3112 got = gen_rtx_REG (Pmode, 2);
3116 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3119 rtx gsym = rs6000_got_sym ();
3120 got = gen_reg_rtx (Pmode);
3122 rs6000_emit_move (got, gsym, Pmode);
3125 rtx tempLR, tmp3, mem;
3128 tempLR = gen_reg_rtx (Pmode);
3129 tmp1 = gen_reg_rtx (Pmode);
3130 tmp2 = gen_reg_rtx (Pmode);
3131 tmp3 = gen_reg_rtx (Pmode);
3132 mem = gen_const_mem (Pmode, tmp1);
3134 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
3135 emit_move_insn (tmp1, tempLR);
3136 emit_move_insn (tmp2, mem);
3137 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3138 last = emit_move_insn (got, tmp3);
3139 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3141 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3143 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3149 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3151 r3 = gen_rtx_REG (Pmode, 3);
3153 insn = gen_tls_gd_64 (r3, got, addr);
3155 insn = gen_tls_gd_32 (r3, got, addr);
3158 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3159 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3160 insn = emit_call_insn (insn);
3161 CONST_OR_PURE_CALL_P (insn) = 1;
3162 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3163 insn = get_insns ();
3165 emit_libcall_block (insn, dest, r3, addr);
3167 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3169 r3 = gen_rtx_REG (Pmode, 3);
3171 insn = gen_tls_ld_64 (r3, got);
3173 insn = gen_tls_ld_32 (r3, got);
3176 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3177 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3178 insn = emit_call_insn (insn);
3179 CONST_OR_PURE_CALL_P (insn) = 1;
3180 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3181 insn = get_insns ();
3183 tmp1 = gen_reg_rtx (Pmode);
3184 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3186 emit_libcall_block (insn, tmp1, r3, eqv);
3187 if (rs6000_tls_size == 16)
3190 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3192 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3194 else if (rs6000_tls_size == 32)
3196 tmp2 = gen_reg_rtx (Pmode);
3198 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3200 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3203 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3205 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3209 tmp2 = gen_reg_rtx (Pmode);
3211 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3213 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3215 insn = gen_rtx_SET (Pmode, dest,
3216 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3222 /* IE, or 64 bit offset LE. */
3223 tmp2 = gen_reg_rtx (Pmode);
3225 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3227 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3230 insn = gen_tls_tls_64 (dest, tmp2, addr);
3232 insn = gen_tls_tls_32 (dest, tmp2, addr);
3240 /* Return 1 if X contains a thread-local symbol. */
3243 rs6000_tls_referenced_p (rtx x)
3245 if (! TARGET_HAVE_TLS)
3248 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3251 /* Return 1 if *X is a thread-local symbol. This is the same as
3252 rs6000_tls_symbol_ref except for the type of the unused argument. */
3255 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3257 return RS6000_SYMBOL_REF_TLS_P (*x);
3260 /* The convention appears to be to define this wherever it is used.
3261 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3262 is now used here. */
3263 #ifndef REG_MODE_OK_FOR_BASE_P
3264 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3267 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3268 replace the input X, or the original X if no replacement is called for.
3269 The output parameter *WIN is 1 if the calling macro should goto WIN,
3272 For RS/6000, we wish to handle large displacements off a base
3273 register by splitting the addend across an addiu/addis and the mem insn.
3274 This cuts number of extra insns needed from 3 to 1.
3276 On Darwin, we use this to generate code for floating point constants.
3277 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3278 The Darwin code is inside #if TARGET_MACHO because only then is
3279 machopic_function_base_name() defined. */
3281 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3282 int opnum, int type,
3283 int ind_levels ATTRIBUTE_UNUSED, int *win)
3285 /* We must recognize output that we have already generated ourselves. */
3286 if (GET_CODE (x) == PLUS
3287 && GET_CODE (XEXP (x, 0)) == PLUS
3288 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3289 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3290 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3292 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3293 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3294 opnum, (enum reload_type)type);
3300 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3301 && GET_CODE (x) == LO_SUM
3302 && GET_CODE (XEXP (x, 0)) == PLUS
3303 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3304 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3305 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3306 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3307 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3308 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3309 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3311 /* Result of previous invocation of this function on Darwin
3312 floating point constant. */
3313 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3314 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3315 opnum, (enum reload_type)type);
3321 /* Force ld/std non-word aligned offset into base register by wrapping
3323 if (GET_CODE (x) == PLUS
3324 && GET_CODE (XEXP (x, 0)) == REG
3325 && REGNO (XEXP (x, 0)) < 32
3326 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3327 && GET_CODE (XEXP (x, 1)) == CONST_INT
3328 && (INTVAL (XEXP (x, 1)) & 3) != 0
3329 && !ALTIVEC_VECTOR_MODE (mode)
3330 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3331 && TARGET_POWERPC64)
3333 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3334 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3335 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3336 opnum, (enum reload_type) type);
3341 if (GET_CODE (x) == PLUS
3342 && GET_CODE (XEXP (x, 0)) == REG
3343 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3344 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3345 && GET_CODE (XEXP (x, 1)) == CONST_INT
3346 && !SPE_VECTOR_MODE (mode)
3347 && !(TARGET_E500_DOUBLE && (mode == DFmode
3349 && !ALTIVEC_VECTOR_MODE (mode))
3351 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3352 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3354 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3356 /* Check for 32-bit overflow. */
3357 if (high + low != val)
3363 /* Reload the high part into a base reg; leave the low part
3364 in the mem directly. */
3366 x = gen_rtx_PLUS (GET_MODE (x),
3367 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3371 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3372 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3373 opnum, (enum reload_type)type);
3378 if (GET_CODE (x) == SYMBOL_REF
3379 && !ALTIVEC_VECTOR_MODE (mode)
3381 && DEFAULT_ABI == ABI_DARWIN
3382 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3384 && DEFAULT_ABI == ABI_V4
3387 /* Don't do this for TFmode, since the result isn't offsettable.
3388 The same goes for DImode without 64-bit gprs. */
3390 && (mode != DImode || TARGET_POWERPC64))
3395 rtx offset = gen_rtx_CONST (Pmode,
3396 gen_rtx_MINUS (Pmode, x,
3397 machopic_function_base_sym ()));
3398 x = gen_rtx_LO_SUM (GET_MODE (x),
3399 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3400 gen_rtx_HIGH (Pmode, offset)), offset);
3404 x = gen_rtx_LO_SUM (GET_MODE (x),
3405 gen_rtx_HIGH (Pmode, x), x);
3407 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3408 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3409 opnum, (enum reload_type)type);
3414 /* Reload an offset address wrapped by an AND that represents the
3415 masking of the lower bits. Strip the outer AND and let reload
3416 convert the offset address into an indirect address. */
3418 && ALTIVEC_VECTOR_MODE (mode)
3419 && GET_CODE (x) == AND
3420 && GET_CODE (XEXP (x, 0)) == PLUS
3421 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3422 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3423 && GET_CODE (XEXP (x, 1)) == CONST_INT
3424 && INTVAL (XEXP (x, 1)) == -16)
3432 && constant_pool_expr_p (x)
3433 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3435 (x) = create_TOC_reference (x);
3443 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3444 that is a valid memory address for an instruction.
3445 The MODE argument is the machine mode for the MEM expression
3446 that wants to use this address.
3448 On the RS/6000, there are four valid address: a SYMBOL_REF that
3449 refers to a constant pool entry of an address (or the sum of it
3450 plus a constant), a short (16-bit signed) constant plus a register,
3451 the sum of two registers, or a register indirect, possibly with an
3452 auto-increment. For DFmode and DImode with a constant plus register,
3453 we must ensure that both words are addressable or PowerPC64 with offset
3456 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3457 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3458 adjacent memory cells are accessed by adding word-sized offsets
3459 during assembly output. */
3461 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3463 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3465 && ALTIVEC_VECTOR_MODE (mode)
3466 && GET_CODE (x) == AND
3467 && GET_CODE (XEXP (x, 1)) == CONST_INT
3468 && INTVAL (XEXP (x, 1)) == -16)
3471 if (RS6000_SYMBOL_REF_TLS_P (x))
3473 if (legitimate_indirect_address_p (x, reg_ok_strict))
3475 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3476 && !ALTIVEC_VECTOR_MODE (mode)
3477 && !SPE_VECTOR_MODE (mode)
3478 /* Restrict addressing for DI because of our SUBREG hackery. */
3479 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3481 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3483 if (legitimate_small_data_p (mode, x))
3485 if (legitimate_constant_pool_address_p (x))
3487 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3489 && GET_CODE (x) == PLUS
3490 && GET_CODE (XEXP (x, 0)) == REG
3491 && (XEXP (x, 0) == virtual_stack_vars_rtx
3492 || XEXP (x, 0) == arg_pointer_rtx)
3493 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3495 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3499 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3501 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3502 && (TARGET_POWERPC64 || mode != DImode)
3503 && legitimate_indexed_address_p (x, reg_ok_strict))
3505 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3510 /* Go to LABEL if ADDR (a legitimate address expression)
3511 has an effect that depends on the machine mode it is used for.
3513 On the RS/6000 this is true of all integral offsets (since AltiVec
3514 modes don't allow them) or is a pre-increment or decrement.
3516 ??? Except that due to conceptual problems in offsettable_address_p
3517 we can't really report the problems of integral offsets. So leave
3518 this assuming that the adjustable offset must be valid for the
3519 sub-words of a TFmode operand, which is what we had before. */
3522 rs6000_mode_dependent_address (rtx addr)
3524 switch (GET_CODE (addr))
3527 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3529 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3530 return val + 12 + 0x8000 >= 0x10000;
3539 return TARGET_UPDATE;
3548 /* More elaborate version of recog's offsettable_memref_p predicate
3549 that works around the ??? note of rs6000_mode_dependent_address.
3550 In particular it accepts
3552 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
3554 in 32-bit mode, that the recog predicate rejects. */
3557 rs6000_offsettable_memref_p (rtx op)
3562 /* First mimic offsettable_memref_p. */
3563 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
3566 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
3567 the latter predicate knows nothing about the mode of the memory
3568 reference and, therefore, assumes that it is the largest supported
3569 mode (TFmode). As a consequence, legitimate offsettable memory
3570 references are rejected. rs6000_legitimate_offset_address_p contains
3571 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
3572 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
3575 /* Return number of consecutive hard regs needed starting at reg REGNO
3576 to hold something of mode MODE.
3577 This is ordinarily the length in words of a value of mode MODE
3578 but can be less for certain modes in special long registers.
3580 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3581 scalar instructions. The upper 32 bits are only available to the
3584 POWER and PowerPC GPRs hold 32 bits worth;
3585 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3588 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3590 if (FP_REGNO_P (regno))
3591 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3593 if (TARGET_E500_DOUBLE && mode == DFmode)
3596 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3597 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3599 if (ALTIVEC_REGNO_P (regno))
3601 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3603 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3606 /* Change register usage conditional on target flags. */
3608 rs6000_conditional_register_usage (void)
3612 /* Set MQ register fixed (already call_used) if not POWER
3613 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3618 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3620 fixed_regs[13] = call_used_regs[13]
3621 = call_really_used_regs[13] = 1;
3623 /* Conditionally disable FPRs. */
3624 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3625 for (i = 32; i < 64; i++)
3626 fixed_regs[i] = call_used_regs[i]
3627 = call_really_used_regs[i] = 1;
3629 /* The TOC register is not killed across calls in a way that is
3630 visible to the compiler. */
3631 if (DEFAULT_ABI == ABI_AIX)
3632 call_really_used_regs[2] = 0;
3634 if (DEFAULT_ABI == ABI_V4
3635 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3637 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3639 if (DEFAULT_ABI == ABI_V4
3640 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3642 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3643 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3644 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3646 if (DEFAULT_ABI == ABI_DARWIN
3647 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3648 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3649 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3650 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3652 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3653 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3654 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3657 global_regs[VSCR_REGNO] = 1;
3661 global_regs[SPEFSCR_REGNO] = 1;
3662 fixed_regs[FIXED_SCRATCH]
3663 = call_used_regs[FIXED_SCRATCH]
3664 = call_really_used_regs[FIXED_SCRATCH] = 1;
3667 if (! TARGET_ALTIVEC)
3669 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3670 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3671 call_really_used_regs[VRSAVE_REGNO] = 1;
3674 if (TARGET_ALTIVEC_ABI)
3675 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3676 call_used_regs[i] = call_really_used_regs[i] = 1;
3679 /* Try to output insns to set TARGET equal to the constant C if it can
3680 be done in less than N insns. Do all computations in MODE.
3681 Returns the place where the output has been placed if it can be
3682 done and the insns have been emitted. If it would take more than N
3683 insns, zero is returned and no insns and emitted. */
3686 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3687 rtx source, int n ATTRIBUTE_UNUSED)
3689 rtx result, insn, set;
3690 HOST_WIDE_INT c0, c1;
3697 dest = gen_reg_rtx (mode);
3698 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3702 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3704 emit_insn (gen_rtx_SET (VOIDmode, result,
3705 GEN_INT (INTVAL (source)
3706 & (~ (HOST_WIDE_INT) 0xffff))));
3707 emit_insn (gen_rtx_SET (VOIDmode, dest,
3708 gen_rtx_IOR (SImode, result,
3709 GEN_INT (INTVAL (source) & 0xffff))));
3714 switch (GET_CODE (source))
3717 c0 = INTVAL (source);
3722 #if HOST_BITS_PER_WIDE_INT >= 64
3723 c0 = CONST_DOUBLE_LOW (source);
3726 c0 = CONST_DOUBLE_LOW (source);
3727 c1 = CONST_DOUBLE_HIGH (source);
3735 result = rs6000_emit_set_long_const (dest, c0, c1);
3742 insn = get_last_insn ();
3743 set = single_set (insn);
3744 if (! CONSTANT_P (SET_SRC (set)))
3745 set_unique_reg_note (insn, REG_EQUAL, source);
3750 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3751 fall back to a straight forward decomposition. We do this to avoid
3752 exponential run times encountered when looking for longer sequences
3753 with rs6000_emit_set_const. */
3755 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3757 if (!TARGET_POWERPC64)
3759 rtx operand1, operand2;
3761 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3763 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3765 emit_move_insn (operand1, GEN_INT (c1));
3766 emit_move_insn (operand2, GEN_INT (c2));
3770 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3773 ud2 = (c1 & 0xffff0000) >> 16;
3774 #if HOST_BITS_PER_WIDE_INT >= 64
3778 ud4 = (c2 & 0xffff0000) >> 16;
3780 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3781 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3784 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3786 emit_move_insn (dest, GEN_INT (ud1));
3789 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3790 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3793 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3796 emit_move_insn (dest, GEN_INT (ud2 << 16));
3798 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3800 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3801 || (ud4 == 0 && ! (ud3 & 0x8000)))
3804 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3807 emit_move_insn (dest, GEN_INT (ud3 << 16));
3810 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3811 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3813 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3818 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3821 emit_move_insn (dest, GEN_INT (ud4 << 16));
3824 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3826 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3828 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3829 GEN_INT (ud2 << 16)));
3831 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3837 /* Helper for the following. Get rid of [r+r] memory refs
3838 in cases where it won't work (TImode, TFmode). */
3841 rs6000_eliminate_indexed_memrefs (rtx operands[2])
3843 if (GET_CODE (operands[0]) == MEM
3844 && GET_CODE (XEXP (operands[0], 0)) != REG
3845 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
3846 && ! reload_in_progress)
3848 = replace_equiv_address (operands[0],
3849 copy_addr_to_reg (XEXP (operands[0], 0)));
3851 if (GET_CODE (operands[1]) == MEM
3852 && GET_CODE (XEXP (operands[1], 0)) != REG
3853 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
3854 && ! reload_in_progress)
3856 = replace_equiv_address (operands[1],
3857 copy_addr_to_reg (XEXP (operands[1], 0)));
3860 /* Emit a move from SOURCE to DEST in mode MODE. */
3862 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3866 operands[1] = source;
3868 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3869 if (GET_CODE (operands[1]) == CONST_DOUBLE
3870 && ! FLOAT_MODE_P (mode)
3871 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3873 /* FIXME. This should never happen. */
3874 /* Since it seems that it does, do the safe thing and convert
3876 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3878 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
3879 || FLOAT_MODE_P (mode)
3880 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
3881 || CONST_DOUBLE_LOW (operands[1]) < 0)
3882 && (CONST_DOUBLE_HIGH (operands[1]) != -1
3883 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
3885 /* Check if GCC is setting up a block move that will end up using FP
3886 registers as temporaries. We must make sure this is acceptable. */
3887 if (GET_CODE (operands[0]) == MEM
3888 && GET_CODE (operands[1]) == MEM
3890 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3891 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3892 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3893 ? 32 : MEM_ALIGN (operands[0])))
3894 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3896 : MEM_ALIGN (operands[1]))))
3897 && ! MEM_VOLATILE_P (operands [0])
3898 && ! MEM_VOLATILE_P (operands [1]))
3900 emit_move_insn (adjust_address (operands[0], SImode, 0),
3901 adjust_address (operands[1], SImode, 0));
3902 emit_move_insn (adjust_address (operands[0], SImode, 4),
3903 adjust_address (operands[1], SImode, 4));
3907 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
3908 && !gpc_reg_operand (operands[1], mode))
3909 operands[1] = force_reg (mode, operands[1]);
3911 if (mode == SFmode && ! TARGET_POWERPC
3912 && TARGET_HARD_FLOAT && TARGET_FPRS
3913 && GET_CODE (operands[0]) == MEM)
3917 if (reload_in_progress || reload_completed)
3918 regnum = true_regnum (operands[1]);
3919 else if (GET_CODE (operands[1]) == REG)
3920 regnum = REGNO (operands[1]);
3924 /* If operands[1] is a register, on POWER it may have
3925 double-precision data in it, so truncate it to single
3927 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3930 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3931 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3932 operands[1] = newreg;
3936 /* Recognize the case where operand[1] is a reference to thread-local
3937 data and load its address to a register. */
3938 if (rs6000_tls_referenced_p (operands[1]))
3940 enum tls_model model;
3941 rtx tmp = operands[1];
3944 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
3946 addend = XEXP (XEXP (tmp, 0), 1);
3947 tmp = XEXP (XEXP (tmp, 0), 0);
3950 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
3951 model = SYMBOL_REF_TLS_MODEL (tmp);
3952 gcc_assert (model != 0);
3954 tmp = rs6000_legitimize_tls_address (tmp, model);
3957 tmp = gen_rtx_PLUS (mode, tmp, addend);
3958 tmp = force_operand (tmp, operands[0]);
3963 /* Handle the case where reload calls us with an invalid address. */
3964 if (reload_in_progress && mode == Pmode
3965 && (! general_operand (operands[1], mode)
3966 || ! nonimmediate_operand (operands[0], mode)))
3969 /* 128-bit constant floating-point values on Darwin should really be
3970 loaded as two parts. */
3971 if (!TARGET_IEEEQUAD
3972 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3973 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3975 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3976 know how to get a DFmode SUBREG of a TFmode. */
3977 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3978 simplify_gen_subreg (DImode, operands[1], mode, 0),
3980 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3981 GET_MODE_SIZE (DImode)),
3982 simplify_gen_subreg (DImode, operands[1], mode,
3983 GET_MODE_SIZE (DImode)),
3988 /* FIXME: In the long term, this switch statement should go away
3989 and be replaced by a sequence of tests based on things like
3995 if (CONSTANT_P (operands[1])
3996 && GET_CODE (operands[1]) != CONST_INT)
3997 operands[1] = force_const_mem (mode, operands[1]);
4001 rs6000_eliminate_indexed_memrefs (operands);
4006 if (CONSTANT_P (operands[1])
4007 && ! easy_fp_constant (operands[1], mode))
4008 operands[1] = force_const_mem (mode, operands[1]);
4019 if (CONSTANT_P (operands[1])
4020 && !easy_vector_constant (operands[1], mode))
4021 operands[1] = force_const_mem (mode, operands[1]);
4026 /* Use default pattern for address of ELF small data */
4029 && DEFAULT_ABI == ABI_V4
4030 && (GET_CODE (operands[1]) == SYMBOL_REF
4031 || GET_CODE (operands[1]) == CONST)
4032 && small_data_operand (operands[1], mode))
4034 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4038 if (DEFAULT_ABI == ABI_V4
4039 && mode == Pmode && mode == SImode
4040 && flag_pic == 1 && got_operand (operands[1], mode))
4042 emit_insn (gen_movsi_got (operands[0], operands[1]));
4046 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4050 && CONSTANT_P (operands[1])
4051 && GET_CODE (operands[1]) != HIGH
4052 && GET_CODE (operands[1]) != CONST_INT)
4054 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
4056 /* If this is a function address on -mcall-aixdesc,
4057 convert it to the address of the descriptor. */
4058 if (DEFAULT_ABI == ABI_AIX
4059 && GET_CODE (operands[1]) == SYMBOL_REF
4060 && XSTR (operands[1], 0)[0] == '.')
4062 const char *name = XSTR (operands[1], 0);
4064 while (*name == '.')
4066 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4067 CONSTANT_POOL_ADDRESS_P (new_ref)
4068 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4069 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4070 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4071 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4072 operands[1] = new_ref;
4075 if (DEFAULT_ABI == ABI_DARWIN)
4078 if (MACHO_DYNAMIC_NO_PIC_P)
4080 /* Take care of any required data indirection. */
4081 operands[1] = rs6000_machopic_legitimize_pic_address (
4082 operands[1], mode, operands[0]);
4083 if (operands[0] != operands[1])
4084 emit_insn (gen_rtx_SET (VOIDmode,
4085 operands[0], operands[1]));
4089 emit_insn (gen_macho_high (target, operands[1]));
4090 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4094 emit_insn (gen_elf_high (target, operands[1]));
4095 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4099 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4100 and we have put it in the TOC, we just need to make a TOC-relative
4103 && GET_CODE (operands[1]) == SYMBOL_REF
4104 && constant_pool_expr_p (operands[1])
4105 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4106 get_pool_mode (operands[1])))
4108 operands[1] = create_TOC_reference (operands[1]);
4110 else if (mode == Pmode
4111 && CONSTANT_P (operands[1])
4112 && ((GET_CODE (operands[1]) != CONST_INT
4113 && ! easy_fp_constant (operands[1], mode))
4114 || (GET_CODE (operands[1]) == CONST_INT
4115 && num_insns_constant (operands[1], mode) > 2)
4116 || (GET_CODE (operands[0]) == REG
4117 && FP_REGNO_P (REGNO (operands[0]))))
4118 && GET_CODE (operands[1]) != HIGH
4119 && ! legitimate_constant_pool_address_p (operands[1])
4120 && ! toc_relative_expr_p (operands[1]))
4122 /* Emit a USE operation so that the constant isn't deleted if
4123 expensive optimizations are turned on because nobody
4124 references it. This should only be done for operands that
4125 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4126 This should not be done for operands that contain LABEL_REFs.
4127 For now, we just handle the obvious case. */
4128 if (GET_CODE (operands[1]) != LABEL_REF)
4129 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4132 /* Darwin uses a special PIC legitimizer. */
4133 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4136 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4138 if (operands[0] != operands[1])
4139 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4144 /* If we are to limit the number of things we put in the TOC and
4145 this is a symbol plus a constant we can add in one insn,
4146 just put the symbol in the TOC and add the constant. Don't do
4147 this if reload is in progress. */
4148 if (GET_CODE (operands[1]) == CONST
4149 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4150 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4151 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4152 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4153 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4154 && ! side_effects_p (operands[0]))
4157 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4158 rtx other = XEXP (XEXP (operands[1], 0), 1);
4160 sym = force_reg (mode, sym);
4162 emit_insn (gen_addsi3 (operands[0], sym, other));
4164 emit_insn (gen_adddi3 (operands[0], sym, other));
4168 operands[1] = force_const_mem (mode, operands[1]);
4171 && constant_pool_expr_p (XEXP (operands[1], 0))
4172 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4173 get_pool_constant (XEXP (operands[1], 0)),
4174 get_pool_mode (XEXP (operands[1], 0))))
4177 = gen_const_mem (mode,
4178 create_TOC_reference (XEXP (operands[1], 0)));
4179 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4185 rs6000_eliminate_indexed_memrefs (operands);
4189 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4191 gen_rtx_SET (VOIDmode,
4192 operands[0], operands[1]),
4193 gen_rtx_CLOBBER (VOIDmode,
4194 gen_rtx_SCRATCH (SImode)))));
4203 /* Above, we may have called force_const_mem which may have returned
4204 an invalid address. If we can, fix this up; otherwise, reload will
4205 have to deal with it. */
4206 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4207 operands[1] = validize_mem (operands[1]);
4210 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4213 /* Nonzero if we can use a floating-point register to pass this arg. */
4214 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4215 (SCALAR_FLOAT_MODE_P (MODE) \
4216 && !DECIMAL_FLOAT_MODE_P (MODE) \
4217 && (CUM)->fregno <= FP_ARG_MAX_REG \
4218 && TARGET_HARD_FLOAT && TARGET_FPRS)
4220 /* Nonzero if we can use an AltiVec register to pass this arg. */
4221 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4222 (ALTIVEC_VECTOR_MODE (MODE) \
4223 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4224 && TARGET_ALTIVEC_ABI \
4227 /* Return a nonzero value to say to return the function value in
4228 memory, just as large structures are always returned. TYPE will be
4229 the data type of the value, and FNTYPE will be the type of the
4230 function doing the returning, or @code{NULL} for libcalls.
4232 The AIX ABI for the RS/6000 specifies that all structures are
4233 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4234 specifies that structures <= 8 bytes are returned in r3/r4, but a
4235 draft put them in memory, and GCC used to implement the draft
4236 instead of the final standard. Therefore, aix_struct_return
4237 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4238 compatibility can change DRAFT_V4_STRUCT_RET to override the
4239 default, and -m switches get the final word. See
4240 rs6000_override_options for more details.
4242 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4243 long double support is enabled. These values are returned in memory.
4245 int_size_in_bytes returns -1 for variable size objects, which go in
4246 memory always. The cast to unsigned makes -1 > 8. */
4249 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4251 /* In the darwin64 abi, try to use registers for larger structs
4253 if (rs6000_darwin64_abi
4254 && TREE_CODE (type) == RECORD_TYPE
4255 && int_size_in_bytes (type) > 0)
4257 CUMULATIVE_ARGS valcum;
4261 valcum.fregno = FP_ARG_MIN_REG;
4262 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4263 /* Do a trial code generation as if this were going to be passed
4264 as an argument; if any part goes in memory, we return NULL. */
4265 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4268 /* Otherwise fall through to more conventional ABI rules. */
4271 if (AGGREGATE_TYPE_P (type)
4272 && (aix_struct_return
4273 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4276 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4277 modes only exist for GCC vector types if -maltivec. */
4278 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4279 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4282 /* Return synthetic vectors in memory. */
4283 if (TREE_CODE (type) == VECTOR_TYPE
4284 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4286 static bool warned_for_return_big_vectors = false;
4287 if (!warned_for_return_big_vectors)
4289 warning (0, "GCC vector returned by reference: "
4290 "non-standard ABI extension with no compatibility guarantee");
4291 warned_for_return_big_vectors = true;
4296 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4302 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4303 for a call to a function whose data type is FNTYPE.
4304 For a library call, FNTYPE is 0.
4306 For incoming args we set the number of arguments in the prototype large
4307 so we never return a PARALLEL. */
4310 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4311 rtx libname ATTRIBUTE_UNUSED, int incoming,
4312 int libcall, int n_named_args)
4314 static CUMULATIVE_ARGS zero_cumulative;
4316 *cum = zero_cumulative;
4318 cum->fregno = FP_ARG_MIN_REG;
4319 cum->vregno = ALTIVEC_ARG_MIN_REG;
4320 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4321 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4322 ? CALL_LIBCALL : CALL_NORMAL);
4323 cum->sysv_gregno = GP_ARG_MIN_REG;
4324 cum->stdarg = fntype
4325 && (TYPE_ARG_TYPES (fntype) != 0
4326 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4327 != void_type_node));
4329 cum->nargs_prototype = 0;
4330 if (incoming || cum->prototype)
4331 cum->nargs_prototype = n_named_args;
4333 /* Check for a longcall attribute. */
4334 if ((!fntype && rs6000_default_long_calls)
4336 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4337 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4338 cum->call_cookie |= CALL_LONG;
4340 if (TARGET_DEBUG_ARG)
4342 fprintf (stderr, "\ninit_cumulative_args:");
4345 tree ret_type = TREE_TYPE (fntype);
4346 fprintf (stderr, " ret code = %s,",
4347 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4350 if (cum->call_cookie & CALL_LONG)
4351 fprintf (stderr, " longcall,");
4353 fprintf (stderr, " proto = %d, nargs = %d\n",
4354 cum->prototype, cum->nargs_prototype);
4359 && TARGET_ALTIVEC_ABI
4360 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4362 error ("cannot return value in vector register because"
4363 " altivec instructions are disabled, use -maltivec"
4368 /* Return true if TYPE must be passed on the stack and not in registers. */
4371 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4373 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4374 return must_pass_in_stack_var_size (mode, type);
4376 return must_pass_in_stack_var_size_or_pad (mode, type);
4379 /* If defined, a C expression which determines whether, and in which
4380 direction, to pad out an argument with extra space. The value
4381 should be of type `enum direction': either `upward' to pad above
4382 the argument, `downward' to pad below, or `none' to inhibit
4385 For the AIX ABI structs are always stored left shifted in their
4389 function_arg_padding (enum machine_mode mode, tree type)
4391 #ifndef AGGREGATE_PADDING_FIXED
4392 #define AGGREGATE_PADDING_FIXED 0
4394 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4395 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4398 if (!AGGREGATE_PADDING_FIXED)
4400 /* GCC used to pass structures of the same size as integer types as
4401 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4402 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4403 passed padded downward, except that -mstrict-align further
4404 muddied the water in that multi-component structures of 2 and 4
4405 bytes in size were passed padded upward.
4407 The following arranges for best compatibility with previous
4408 versions of gcc, but removes the -mstrict-align dependency. */
4409 if (BYTES_BIG_ENDIAN)
4411 HOST_WIDE_INT size = 0;
4413 if (mode == BLKmode)
4415 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4416 size = int_size_in_bytes (type);
4419 size = GET_MODE_SIZE (mode);
4421 if (size == 1 || size == 2 || size == 4)
4427 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4429 if (type != 0 && AGGREGATE_TYPE_P (type))
4433 /* Fall back to the default. */
4434 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4437 /* If defined, a C expression that gives the alignment boundary, in bits,
4438 of an argument with the specified mode and type. If it is not defined,
4439 PARM_BOUNDARY is used for all arguments.
4441 V.4 wants long longs to be double word aligned.
4442 Doubleword align SPE vectors.
4443 Quadword align Altivec vectors.
4444 Quadword align large synthetic vector types. */
4447 function_arg_boundary (enum machine_mode mode, tree type)
4449 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4451 else if (SPE_VECTOR_MODE (mode)
4452 || (type && TREE_CODE (type) == VECTOR_TYPE
4453 && int_size_in_bytes (type) >= 8
4454 && int_size_in_bytes (type) < 16))
4456 else if (ALTIVEC_VECTOR_MODE (mode)
4457 || (type && TREE_CODE (type) == VECTOR_TYPE
4458 && int_size_in_bytes (type) >= 16))
4460 else if (rs6000_darwin64_abi && mode == BLKmode
4461 && type && TYPE_ALIGN (type) > 64)
4464 return PARM_BOUNDARY;
4467 /* For a function parm of MODE and TYPE, return the starting word in
4468 the parameter area. NWORDS of the parameter area are already used. */
4471 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4474 unsigned int parm_offset;
4476 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4477 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4478 return nwords + (-(parm_offset + nwords) & align);
4481 /* Compute the size (in words) of a function argument. */
4483 static unsigned long
4484 rs6000_arg_size (enum machine_mode mode, tree type)
4488 if (mode != BLKmode)
4489 size = GET_MODE_SIZE (mode);
4491 size = int_size_in_bytes (type);
4494 return (size + 3) >> 2;
4496 return (size + 7) >> 3;
4499 /* Use this to flush pending int fields. */
4502 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4503 HOST_WIDE_INT bitpos)
4505 unsigned int startbit, endbit;
4506 int intregs, intoffset;
4507 enum machine_mode mode;
4509 if (cum->intoffset == -1)
4512 intoffset = cum->intoffset;
4513 cum->intoffset = -1;
4515 if (intoffset % BITS_PER_WORD != 0)
4517 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4519 if (mode == BLKmode)
4521 /* We couldn't find an appropriate mode, which happens,
4522 e.g., in packed structs when there are 3 bytes to load.
4523 Back intoffset back to the beginning of the word in this
4525 intoffset = intoffset & -BITS_PER_WORD;
4529 startbit = intoffset & -BITS_PER_WORD;
4530 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4531 intregs = (endbit - startbit) / BITS_PER_WORD;
4532 cum->words += intregs;
4535 /* The darwin64 ABI calls for us to recurse down through structs,
4536 looking for elements passed in registers. Unfortunately, we have
4537 to track int register count here also because of misalignments
4538 in powerpc alignment mode. */
4541 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4543 HOST_WIDE_INT startbitpos)
4547 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4548 if (TREE_CODE (f) == FIELD_DECL)
4550 HOST_WIDE_INT bitpos = startbitpos;
4551 tree ftype = TREE_TYPE (f);
4552 enum machine_mode mode = TYPE_MODE (ftype);
4554 if (DECL_SIZE (f) != 0
4555 && host_integerp (bit_position (f), 1))
4556 bitpos += int_bit_position (f);
4558 /* ??? FIXME: else assume zero offset. */
4560 if (TREE_CODE (ftype) == RECORD_TYPE)
4561 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4562 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4564 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4565 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4566 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4568 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4570 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4574 else if (cum->intoffset == -1)
4575 cum->intoffset = bitpos;
4579 /* Update the data in CUM to advance over an argument
4580 of mode MODE and data type TYPE.
4581 (TYPE is null for libcalls where that information may not be available.)
4583 Note that for args passed by reference, function_arg will be called
4584 with MODE and TYPE set to that of the pointer to the arg, not the arg
4588 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4589 tree type, int named, int depth)
4593 /* Only tick off an argument if we're not recursing. */
4595 cum->nargs_prototype--;
4597 if (TARGET_ALTIVEC_ABI
4598 && (ALTIVEC_VECTOR_MODE (mode)
4599 || (type && TREE_CODE (type) == VECTOR_TYPE
4600 && int_size_in_bytes (type) == 16)))
4604 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4607 if (!TARGET_ALTIVEC)
4608 error ("cannot pass argument in vector register because"
4609 " altivec instructions are disabled, use -maltivec"
4612 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4613 even if it is going to be passed in a vector register.
4614 Darwin does the same for variable-argument functions. */
4615 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4616 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4626 /* Vector parameters must be 16-byte aligned. This places
4627 them at 2 mod 4 in terms of words in 32-bit mode, since
4628 the parameter save area starts at offset 24 from the
4629 stack. In 64-bit mode, they just have to start on an
4630 even word, since the parameter save area is 16-byte
4631 aligned. Space for GPRs is reserved even if the argument
4632 will be passed in memory. */
4634 align = (2 - cum->words) & 3;
4636 align = cum->words & 1;
4637 cum->words += align + rs6000_arg_size (mode, type);
4639 if (TARGET_DEBUG_ARG)
4641 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4643 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4644 cum->nargs_prototype, cum->prototype,
4645 GET_MODE_NAME (mode));
4649 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4651 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4654 else if (rs6000_darwin64_abi
4656 && TREE_CODE (type) == RECORD_TYPE
4657 && (size = int_size_in_bytes (type)) > 0)
4659 /* Variable sized types have size == -1 and are
4660 treated as if consisting entirely of ints.
4661 Pad to 16 byte boundary if needed. */
4662 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4663 && (cum->words % 2) != 0)
4665 /* For varargs, we can just go up by the size of the struct. */
4667 cum->words += (size + 7) / 8;
4670 /* It is tempting to say int register count just goes up by
4671 sizeof(type)/8, but this is wrong in a case such as
4672 { int; double; int; } [powerpc alignment]. We have to
4673 grovel through the fields for these too. */
4675 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4676 rs6000_darwin64_record_arg_advance_flush (cum,
4677 size * BITS_PER_UNIT);
4680 else if (DEFAULT_ABI == ABI_V4)
4682 if (TARGET_HARD_FLOAT && TARGET_FPRS
4683 && (mode == SFmode || mode == DFmode
4684 || (mode == TFmode && !TARGET_IEEEQUAD)))
4686 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
4687 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4690 cum->fregno = FP_ARG_V4_MAX_REG + 1;
4691 if (mode == DFmode || mode == TFmode)
4692 cum->words += cum->words & 1;
4693 cum->words += rs6000_arg_size (mode, type);
4698 int n_words = rs6000_arg_size (mode, type);
4699 int gregno = cum->sysv_gregno;
4701 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4702 (r7,r8) or (r9,r10). As does any other 2 word item such
4703 as complex int due to a historical mistake. */
4705 gregno += (1 - gregno) & 1;
4707 /* Multi-reg args are not split between registers and stack. */
4708 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4710 /* Long long and SPE vectors are aligned on the stack.
4711 So are other 2 word items such as complex int due to
4712 a historical mistake. */
4714 cum->words += cum->words & 1;
4715 cum->words += n_words;
4718 /* Note: continuing to accumulate gregno past when we've started
4719 spilling to the stack indicates the fact that we've started
4720 spilling to the stack to expand_builtin_saveregs. */
4721 cum->sysv_gregno = gregno + n_words;
4724 if (TARGET_DEBUG_ARG)
4726 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4727 cum->words, cum->fregno);
4728 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4729 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4730 fprintf (stderr, "mode = %4s, named = %d\n",
4731 GET_MODE_NAME (mode), named);
4736 int n_words = rs6000_arg_size (mode, type);
4737 int start_words = cum->words;
4738 int align_words = rs6000_parm_start (mode, type, start_words);
4740 cum->words = align_words + n_words;
4742 if (SCALAR_FLOAT_MODE_P (mode)
4743 && !DECIMAL_FLOAT_MODE_P (mode)
4744 && TARGET_HARD_FLOAT && TARGET_FPRS)
4745 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4747 if (TARGET_DEBUG_ARG)
4749 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4750 cum->words, cum->fregno);
4751 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4752 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4753 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
4754 named, align_words - start_words, depth);
4760 spe_build_register_parallel (enum machine_mode mode, int gregno)
4767 r1 = gen_rtx_REG (DImode, gregno);
4768 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4769 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
4772 r1 = gen_rtx_REG (DImode, gregno);
4773 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4774 r3 = gen_rtx_REG (DImode, gregno + 2);
4775 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4776 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
4783 /* Determine where to put a SIMD argument on the SPE. */
4785 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4788 int gregno = cum->sysv_gregno;
4790 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4791 are passed and returned in a pair of GPRs for ABI compatibility. */
4792 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
4794 int n_words = rs6000_arg_size (mode, type);
4796 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4798 gregno += (1 - gregno) & 1;
4800 /* Multi-reg args are not split between registers and stack. */
4801 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4804 return spe_build_register_parallel (mode, gregno);
4808 int n_words = rs6000_arg_size (mode, type);
4810 /* SPE vectors are put in odd registers. */
4811 if (n_words == 2 && (gregno & 1) == 0)
4814 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4817 enum machine_mode m = SImode;
4819 r1 = gen_rtx_REG (m, gregno);
4820 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4821 r2 = gen_rtx_REG (m, gregno + 1);
4822 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4823 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4830 if (gregno <= GP_ARG_MAX_REG)
4831 return gen_rtx_REG (mode, gregno);
4837 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4838 structure between cum->intoffset and bitpos to integer registers. */
4841 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4842 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
4844 enum machine_mode mode;
4846 unsigned int startbit, endbit;
4847 int this_regno, intregs, intoffset;
4850 if (cum->intoffset == -1)
4853 intoffset = cum->intoffset;
4854 cum->intoffset = -1;
4856 /* If this is the trailing part of a word, try to only load that
4857 much into the register. Otherwise load the whole register. Note
4858 that in the latter case we may pick up unwanted bits. It's not a
4859 problem at the moment but may wish to revisit. */
4861 if (intoffset % BITS_PER_WORD != 0)
4863 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4865 if (mode == BLKmode)
4867 /* We couldn't find an appropriate mode, which happens,
4868 e.g., in packed structs when there are 3 bytes to load.
4869 Back intoffset back to the beginning of the word in this
4871 intoffset = intoffset & -BITS_PER_WORD;
4878 startbit = intoffset & -BITS_PER_WORD;
4879 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4880 intregs = (endbit - startbit) / BITS_PER_WORD;
4881 this_regno = cum->words + intoffset / BITS_PER_WORD;
4883 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4886 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4890 intoffset /= BITS_PER_UNIT;
4893 regno = GP_ARG_MIN_REG + this_regno;
4894 reg = gen_rtx_REG (mode, regno);
4896 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4899 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4903 while (intregs > 0);
4906 /* Recursive workhorse for the following. */
4909 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4910 HOST_WIDE_INT startbitpos, rtx rvec[],
4915 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4916 if (TREE_CODE (f) == FIELD_DECL)
4918 HOST_WIDE_INT bitpos = startbitpos;
4919 tree ftype = TREE_TYPE (f);
4920 enum machine_mode mode = TYPE_MODE (ftype);
4922 if (DECL_SIZE (f) != 0
4923 && host_integerp (bit_position (f), 1))
4924 bitpos += int_bit_position (f);
4926 /* ??? FIXME: else assume zero offset. */
4928 if (TREE_CODE (ftype) == RECORD_TYPE)
4929 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4930 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
4935 case SCmode: mode = SFmode; break;
4936 case DCmode: mode = DFmode; break;
4937 case TCmode: mode = TFmode; break;
4941 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4943 = gen_rtx_EXPR_LIST (VOIDmode,
4944 gen_rtx_REG (mode, cum->fregno++),
4945 GEN_INT (bitpos / BITS_PER_UNIT));
4949 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4951 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4953 = gen_rtx_EXPR_LIST (VOIDmode,
4954 gen_rtx_REG (mode, cum->vregno++),
4955 GEN_INT (bitpos / BITS_PER_UNIT));
4957 else if (cum->intoffset == -1)
4958 cum->intoffset = bitpos;
4962 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4963 the register(s) to be used for each field and subfield of a struct
4964 being passed by value, along with the offset of where the
4965 register's value may be found in the block. FP fields go in FP
4966 register, vector fields go in vector registers, and everything
4967 else goes in int registers, packed as in memory.
4969 This code is also used for function return values. RETVAL indicates
4970 whether this is the case.
4972 Much of this is taken from the SPARC V9 port, which has a similar
4973 calling convention. */
4976 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4977 int named, bool retval)
4979 rtx rvec[FIRST_PSEUDO_REGISTER];
4980 int k = 1, kbase = 1;
4981 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4982 /* This is a copy; modifications are not visible to our caller. */
4983 CUMULATIVE_ARGS copy_cum = *orig_cum;
4984 CUMULATIVE_ARGS *cum = ©_cum;
4986 /* Pad to 16 byte boundary if needed. */
4987 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4988 && (cum->words % 2) != 0)
4995 /* Put entries into rvec[] for individual FP and vector fields, and
4996 for the chunks of memory that go in int regs. Note we start at
4997 element 1; 0 is reserved for an indication of using memory, and
4998 may or may not be filled in below. */
4999 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5000 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5002 /* If any part of the struct went on the stack put all of it there.
5003 This hack is because the generic code for
5004 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5005 parts of the struct are not at the beginning. */
5009 return NULL_RTX; /* doesn't go in registers at all */
5011 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5013 if (k > 1 || cum->use_stack)
5014 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5019 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5022 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5026 rtx rvec[GP_ARG_NUM_REG + 1];
5028 if (align_words >= GP_ARG_NUM_REG)
5031 n_units = rs6000_arg_size (mode, type);
5033 /* Optimize the simple case where the arg fits in one gpr, except in
5034 the case of BLKmode due to assign_parms assuming that registers are
5035 BITS_PER_WORD wide. */
5037 || (n_units == 1 && mode != BLKmode))
5038 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5041 if (align_words + n_units > GP_ARG_NUM_REG)
5042 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5043 using a magic NULL_RTX component.
5044 FIXME: This is not strictly correct. Only some of the arg
5045 belongs in memory, not all of it. However, there isn't any way
5046 to do this currently, apart from building rtx descriptions for
5047 the pieces of memory we want stored. Due to bugs in the generic
5048 code we can't use the normal function_arg_partial_nregs scheme
5049 with the PARALLEL arg description we emit here.
5050 In any case, the code to store the whole arg to memory is often
5051 more efficient than code to store pieces, and we know that space
5052 is available in the right place for the whole arg. */
5053 /* FIXME: This should be fixed since the conversion to
5054 TARGET_ARG_PARTIAL_BYTES. */
5055 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5060 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5061 rtx off = GEN_INT (i++ * 4);
5062 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5064 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5066 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5069 /* Determine where to put an argument to a function.
5070 Value is zero to push the argument on the stack,
5071 or a hard register in which to store the argument.
5073 MODE is the argument's machine mode.
5074 TYPE is the data type of the argument (as a tree).
5075 This is null for libcalls where that information may
5077 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5078 the preceding args and about the function being called. It is
5079 not modified in this routine.
5080 NAMED is nonzero if this argument is a named parameter
5081 (otherwise it is an extra parameter matching an ellipsis).
5083 On RS/6000 the first eight words of non-FP are normally in registers
5084 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5085 Under V.4, the first 8 FP args are in registers.
5087 If this is floating-point and no prototype is specified, we use
5088 both an FP and integer register (or possibly FP reg and stack). Library
5089 functions (when CALL_LIBCALL is set) always have the proper types for args,
5090 so we can pass the FP value just in one register. emit_library_function
5091 doesn't support PARALLEL anyway.
5093 Note that for args passed by reference, function_arg will be called
5094 with MODE and TYPE set to that of the pointer to the arg, not the arg
5098 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5099 tree type, int named)
5101 enum rs6000_abi abi = DEFAULT_ABI;
5103 /* Return a marker to indicate whether CR1 needs to set or clear the
5104 bit that V.4 uses to say fp args were passed in registers.
5105 Assume that we don't need the marker for software floating point,
5106 or compiler generated library calls. */
5107 if (mode == VOIDmode)
5110 && (cum->call_cookie & CALL_LIBCALL) == 0
5112 || (cum->nargs_prototype < 0
5113 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5115 /* For the SPE, we need to crxor CR6 always. */
5117 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5118 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5119 return GEN_INT (cum->call_cookie
5120 | ((cum->fregno == FP_ARG_MIN_REG)
5121 ? CALL_V4_SET_FP_ARGS
5122 : CALL_V4_CLEAR_FP_ARGS));
5125 return GEN_INT (cum->call_cookie);
5128 if (rs6000_darwin64_abi && mode == BLKmode
5129 && TREE_CODE (type) == RECORD_TYPE)
5131 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5132 if (rslt != NULL_RTX)
5134 /* Else fall through to usual handling. */
5137 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5138 if (TARGET_64BIT && ! cum->prototype)
5140 /* Vector parameters get passed in vector register
5141 and also in GPRs or memory, in absence of prototype. */
5144 align_words = (cum->words + 1) & ~1;
5146 if (align_words >= GP_ARG_NUM_REG)
5152 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5154 return gen_rtx_PARALLEL (mode,
5156 gen_rtx_EXPR_LIST (VOIDmode,
5158 gen_rtx_EXPR_LIST (VOIDmode,
5159 gen_rtx_REG (mode, cum->vregno),
5163 return gen_rtx_REG (mode, cum->vregno);
5164 else if (TARGET_ALTIVEC_ABI
5165 && (ALTIVEC_VECTOR_MODE (mode)
5166 || (type && TREE_CODE (type) == VECTOR_TYPE
5167 && int_size_in_bytes (type) == 16)))
5169 if (named || abi == ABI_V4)
5173 /* Vector parameters to varargs functions under AIX or Darwin
5174 get passed in memory and possibly also in GPRs. */
5175 int align, align_words, n_words;
5176 enum machine_mode part_mode;
5178 /* Vector parameters must be 16-byte aligned. This places them at
5179 2 mod 4 in terms of words in 32-bit mode, since the parameter
5180 save area starts at offset 24 from the stack. In 64-bit mode,
5181 they just have to start on an even word, since the parameter
5182 save area is 16-byte aligned. */
5184 align = (2 - cum->words) & 3;
5186 align = cum->words & 1;
5187 align_words = cum->words + align;
5189 /* Out of registers? Memory, then. */
5190 if (align_words >= GP_ARG_NUM_REG)
5193 if (TARGET_32BIT && TARGET_POWERPC64)
5194 return rs6000_mixed_function_arg (mode, type, align_words);
5196 /* The vector value goes in GPRs. Only the part of the
5197 value in GPRs is reported here. */
5199 n_words = rs6000_arg_size (mode, type);
5200 if (align_words + n_words > GP_ARG_NUM_REG)
5201 /* Fortunately, there are only two possibilities, the value
5202 is either wholly in GPRs or half in GPRs and half not. */
5205 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5208 else if (TARGET_SPE_ABI && TARGET_SPE
5209 && (SPE_VECTOR_MODE (mode)
5210 || (TARGET_E500_DOUBLE && (mode == DFmode
5211 || mode == DCmode))))
5212 return rs6000_spe_function_arg (cum, mode, type);
5214 else if (abi == ABI_V4)
5216 if (TARGET_HARD_FLOAT && TARGET_FPRS
5217 && (mode == SFmode || mode == DFmode
5218 || (mode == TFmode && !TARGET_IEEEQUAD)))
5220 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
5221 return gen_rtx_REG (mode, cum->fregno);
5227 int n_words = rs6000_arg_size (mode, type);
5228 int gregno = cum->sysv_gregno;
5230 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5231 (r7,r8) or (r9,r10). As does any other 2 word item such
5232 as complex int due to a historical mistake. */
5234 gregno += (1 - gregno) & 1;
5236 /* Multi-reg args are not split between registers and stack. */
5237 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5240 if (TARGET_32BIT && TARGET_POWERPC64)
5241 return rs6000_mixed_function_arg (mode, type,
5242 gregno - GP_ARG_MIN_REG);
5243 return gen_rtx_REG (mode, gregno);
5248 int align_words = rs6000_parm_start (mode, type, cum->words);
5250 if (USE_FP_FOR_ARG_P (cum, mode, type))
5252 rtx rvec[GP_ARG_NUM_REG + 1];
5256 enum machine_mode fmode = mode;
5257 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5259 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5261 /* Currently, we only ever need one reg here because complex
5262 doubles are split. */
5263 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);
5265 /* Long double split over regs and memory. */
5269 /* Do we also need to pass this arg in the parameter save
5272 && (cum->nargs_prototype <= 0
5273 || (DEFAULT_ABI == ABI_AIX
5275 && align_words >= GP_ARG_NUM_REG)));
5277 if (!needs_psave && mode == fmode)
5278 return gen_rtx_REG (fmode, cum->fregno);
5283 /* Describe the part that goes in gprs or the stack.
5284 This piece must come first, before the fprs. */
5285 if (align_words < GP_ARG_NUM_REG)
5287 unsigned long n_words = rs6000_arg_size (mode, type);
5289 if (align_words + n_words > GP_ARG_NUM_REG
5290 || (TARGET_32BIT && TARGET_POWERPC64))
5292 /* If this is partially on the stack, then we only
5293 include the portion actually in registers here. */
5294 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5297 if (align_words + n_words > GP_ARG_NUM_REG
5298 && (TARGET_32BIT && TARGET_POWERPC64))
5299 /* Not all of the arg fits in gprs. Say that it
5300 goes in memory too, using a magic NULL_RTX
5301 component. Also see comment in
5302 rs6000_mixed_function_arg for why the normal
5303 function_arg_partial_nregs scheme doesn't work
5305 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5309 r = gen_rtx_REG (rmode,
5310 GP_ARG_MIN_REG + align_words);
5311 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5312 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5314 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5318 /* The whole arg fits in gprs. */
5319 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5320 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5324 /* It's entirely in memory. */
5325 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5328 /* Describe where this piece goes in the fprs. */
5329 r = gen_rtx_REG (fmode, cum->fregno);
5330 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5332 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5334 else if (align_words < GP_ARG_NUM_REG)
5336 if (TARGET_32BIT && TARGET_POWERPC64)
5337 return rs6000_mixed_function_arg (mode, type, align_words);
5339 if (mode == BLKmode)
5342 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5349 /* For an arg passed partly in registers and partly in memory, this is
5350 the number of bytes passed in registers. For args passed entirely in
5351 registers or entirely in memory, zero. When an arg is described by a
5352 PARALLEL, perhaps using more than one register type, this function
5353 returns the number of bytes used by the first element of the PARALLEL. */
5356 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5357 tree type, bool named)
5362 if (DEFAULT_ABI == ABI_V4)
5365 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5366 && cum->nargs_prototype >= 0)
5369 /* In this complicated case we just disable the partial_nregs code. */
5370 if (rs6000_darwin64_abi && mode == BLKmode
5371 && TREE_CODE (type) == RECORD_TYPE
5372 && int_size_in_bytes (type) > 0)
5375 align_words = rs6000_parm_start (mode, type, cum->words);
5377 if (USE_FP_FOR_ARG_P (cum, mode, type)
5378 /* If we are passing this arg in the fixed parameter save area
5379 (gprs or memory) as well as fprs, then this function should
5380 return the number of bytes passed in the parameter save area
5381 rather than bytes passed in fprs. */
5383 && (cum->nargs_prototype <= 0
5384 || (DEFAULT_ABI == ABI_AIX
5386 && align_words >= GP_ARG_NUM_REG))))
5388 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
5389 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5390 else if (cum->nargs_prototype >= 0)
5394 if (align_words < GP_ARG_NUM_REG
5395 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5396 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5398 if (ret != 0 && TARGET_DEBUG_ARG)
5399 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5404 /* A C expression that indicates when an argument must be passed by
5405 reference. If nonzero for an argument, a copy of that argument is
5406 made in memory and a pointer to the argument is passed instead of
5407 the argument itself. The pointer is passed in whatever way is
5408 appropriate for passing a pointer to that type.
5410 Under V.4, aggregates and long double are passed by reference.
5412 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5413 reference unless the AltiVec vector extension ABI is in force.
5415 As an extension to all ABIs, variable sized types are passed by
5419 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5420 enum machine_mode mode, tree type,
5421 bool named ATTRIBUTE_UNUSED)
5423 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
5425 if (TARGET_DEBUG_ARG)
5426 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5433 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5435 if (TARGET_DEBUG_ARG)
5436 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5440 if (int_size_in_bytes (type) < 0)
5442 if (TARGET_DEBUG_ARG)
5443 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5447 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5448 modes only exist for GCC vector types if -maltivec. */
5449 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5451 if (TARGET_DEBUG_ARG)
5452 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5456 /* Pass synthetic vectors in memory. */
5457 if (TREE_CODE (type) == VECTOR_TYPE
5458 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5460 static bool warned_for_pass_big_vectors = false;
5461 if (TARGET_DEBUG_ARG)
5462 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5463 if (!warned_for_pass_big_vectors)
5465 warning (0, "GCC vector passed by reference: "
5466 "non-standard ABI extension with no compatibility guarantee");
5467 warned_for_pass_big_vectors = true;
5476 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5479 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5484 for (i = 0; i < nregs; i++)
5486 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5487 if (reload_completed)
5489 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5492 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5493 i * GET_MODE_SIZE (reg_mode));
5496 tem = replace_equiv_address (tem, XEXP (tem, 0));
5500 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5504 /* Perform any needed actions needed for a function that is receiving a
5505 variable number of arguments.
5509 MODE and TYPE are the mode and type of the current parameter.
5511 PRETEND_SIZE is a variable that should be set to the amount of stack
5512 that must be pushed by the prolog to pretend that our caller pushed
5515 Normally, this macro will push all remaining incoming registers on the
5516 stack and set PRETEND_SIZE to the length of the registers pushed. */
5519 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5520 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5523 CUMULATIVE_ARGS next_cum;
5524 int reg_size = TARGET_32BIT ? 4 : 8;
5525 rtx save_area = NULL_RTX, mem;
5526 int first_reg_offset, set;
5528 /* Skip the last named argument. */
5530 function_arg_advance (&next_cum, mode, type, 1, 0);
5532 if (DEFAULT_ABI == ABI_V4)
5534 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5538 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
5539 HOST_WIDE_INT offset = 0;
5541 /* Try to optimize the size of the varargs save area.
5542 The ABI requires that ap.reg_save_area is doubleword
5543 aligned, but we don't need to allocate space for all
5544 the bytes, only those to which we actually will save
5546 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
5547 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
5548 if (TARGET_HARD_FLOAT && TARGET_FPRS
5549 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5550 && cfun->va_list_fpr_size)
5553 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
5554 * UNITS_PER_FP_WORD;
5555 if (cfun->va_list_fpr_size
5556 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5557 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
5559 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5560 * UNITS_PER_FP_WORD;
5564 offset = -((first_reg_offset * reg_size) & ~7);
5565 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
5567 gpr_reg_num = cfun->va_list_gpr_size;
5568 if (reg_size == 4 && (first_reg_offset & 1))
5571 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
5574 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
5576 - (int) (GP_ARG_NUM_REG * reg_size);
5578 if (gpr_size + fpr_size)
5581 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
5582 gcc_assert (GET_CODE (reg_save_area) == MEM);
5583 reg_save_area = XEXP (reg_save_area, 0);
5584 if (GET_CODE (reg_save_area) == PLUS)
5586 gcc_assert (XEXP (reg_save_area, 0)
5587 == virtual_stack_vars_rtx);
5588 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
5589 offset += INTVAL (XEXP (reg_save_area, 1));
5592 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
5595 cfun->machine->varargs_save_offset = offset;
5596 save_area = plus_constant (virtual_stack_vars_rtx, offset);
5601 first_reg_offset = next_cum.words;
5602 save_area = virtual_incoming_args_rtx;
5604 if (targetm.calls.must_pass_in_stack (mode, type))
5605 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5608 set = get_varargs_alias_set ();
5609 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5610 && cfun->va_list_gpr_size)
5612 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5614 if (va_list_gpr_counter_field)
5616 /* V4 va_list_gpr_size counts number of registers needed. */
5617 if (nregs > cfun->va_list_gpr_size)
5618 nregs = cfun->va_list_gpr_size;
5622 /* char * va_list instead counts number of bytes needed. */
5623 if (nregs > cfun->va_list_gpr_size / reg_size)
5624 nregs = cfun->va_list_gpr_size / reg_size;
5627 mem = gen_rtx_MEM (BLKmode,
5628 plus_constant (save_area,
5629 first_reg_offset * reg_size));
5630 MEM_NOTRAP_P (mem) = 1;
5631 set_mem_alias_set (mem, set);
5632 set_mem_align (mem, BITS_PER_WORD);
5634 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5638 /* Save FP registers if needed. */
5639 if (DEFAULT_ABI == ABI_V4
5640 && TARGET_HARD_FLOAT && TARGET_FPRS
5642 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5643 && cfun->va_list_fpr_size)
5645 int fregno = next_cum.fregno, nregs;
5646 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5647 rtx lab = gen_label_rtx ();
5648 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
5649 * UNITS_PER_FP_WORD);
5652 (gen_rtx_SET (VOIDmode,
5654 gen_rtx_IF_THEN_ELSE (VOIDmode,
5655 gen_rtx_NE (VOIDmode, cr1,
5657 gen_rtx_LABEL_REF (VOIDmode, lab),
5661 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
5662 fregno++, off += UNITS_PER_FP_WORD, nregs++)
5664 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5665 MEM_NOTRAP_P (mem) = 1;
5666 set_mem_alias_set (mem, set);
5667 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5668 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5675 /* Create the va_list data type. */
5678 rs6000_build_builtin_va_list (void)
5680 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5682 /* For AIX, prefer 'char *' because that's what the system
5683 header files like. */
5684 if (DEFAULT_ABI != ABI_V4)
5685 return build_pointer_type (char_type_node);
5687 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5688 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5690 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5691 unsigned_char_type_node);
5692 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5693 unsigned_char_type_node);
5694 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5696 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5697 short_unsigned_type_node);
5698 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5700 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5703 va_list_gpr_counter_field = f_gpr;
5704 va_list_fpr_counter_field = f_fpr;
5706 DECL_FIELD_CONTEXT (f_gpr) = record;
5707 DECL_FIELD_CONTEXT (f_fpr) = record;
5708 DECL_FIELD_CONTEXT (f_res) = record;
5709 DECL_FIELD_CONTEXT (f_ovf) = record;
5710 DECL_FIELD_CONTEXT (f_sav) = record;
5712 TREE_CHAIN (record) = type_decl;
5713 TYPE_NAME (record) = type_decl;
5714 TYPE_FIELDS (record) = f_gpr;
5715 TREE_CHAIN (f_gpr) = f_fpr;
5716 TREE_CHAIN (f_fpr) = f_res;
5717 TREE_CHAIN (f_res) = f_ovf;
5718 TREE_CHAIN (f_ovf) = f_sav;
5720 layout_type (record);
5722 /* The correct type is an array type of one element. */
5723 return build_array_type (record, build_index_type (size_zero_node));
5726 /* Implement va_start. */
5729 rs6000_va_start (tree valist, rtx nextarg)
5731 HOST_WIDE_INT words, n_gpr, n_fpr;
5732 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5733 tree gpr, fpr, ovf, sav, t;
5735 /* Only SVR4 needs something special. */
5736 if (DEFAULT_ABI != ABI_V4)
5738 std_expand_builtin_va_start (valist, nextarg);
5742 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5743 f_fpr = TREE_CHAIN (f_gpr);
5744 f_res = TREE_CHAIN (f_fpr);
5745 f_ovf = TREE_CHAIN (f_res);
5746 f_sav = TREE_CHAIN (f_ovf);
5748 valist = build_va_arg_indirect_ref (valist);
5749 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5750 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5751 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5752 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5754 /* Count number of gp and fp argument registers used. */
5755 words = current_function_args_info.words;
5756 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5758 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5761 if (TARGET_DEBUG_ARG)
5762 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5763 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5764 words, n_gpr, n_fpr);
5766 if (cfun->va_list_gpr_size)
5768 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5769 build_int_cst (NULL_TREE, n_gpr));
5770 TREE_SIDE_EFFECTS (t) = 1;
5771 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5774 if (cfun->va_list_fpr_size)
5776 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5777 build_int_cst (NULL_TREE, n_fpr));
5778 TREE_SIDE_EFFECTS (t) = 1;
5779 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5782 /* Find the overflow area. */
5783 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5785 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t,
5786 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5787 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5788 TREE_SIDE_EFFECTS (t) = 1;
5789 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5791 /* If there were no va_arg invocations, don't set up the register
5793 if (!cfun->va_list_gpr_size
5794 && !cfun->va_list_fpr_size
5795 && n_gpr < GP_ARG_NUM_REG
5796 && n_fpr < FP_ARG_V4_MAX_REG)
5799 /* Find the register save area. */
5800 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5801 if (cfun->machine->varargs_save_offset)
5802 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
5803 build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset));
5804 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5805 TREE_SIDE_EFFECTS (t) = 1;
5806 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5809 /* Implement va_arg. */
5812 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5814 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5815 tree gpr, fpr, ovf, sav, reg, t, u;
5816 int size, rsize, n_reg, sav_ofs, sav_scale;
5817 tree lab_false, lab_over, addr;
5819 tree ptrtype = build_pointer_type (type);
5821 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5823 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5824 return build_va_arg_indirect_ref (t);
5827 if (DEFAULT_ABI != ABI_V4)
5829 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5831 tree elem_type = TREE_TYPE (type);
5832 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5833 int elem_size = GET_MODE_SIZE (elem_mode);
5835 if (elem_size < UNITS_PER_WORD)
5837 tree real_part, imag_part;
5838 tree post = NULL_TREE;
5840 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5842 /* Copy the value into a temporary, lest the formal temporary
5843 be reused out from under us. */
5844 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5845 append_to_statement_list (post, pre_p);
5847 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5850 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
5854 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5857 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5858 f_fpr = TREE_CHAIN (f_gpr);
5859 f_res = TREE_CHAIN (f_fpr);
5860 f_ovf = TREE_CHAIN (f_res);
5861 f_sav = TREE_CHAIN (f_ovf);
5863 valist = build_va_arg_indirect_ref (valist);
5864 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5865 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5866 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5867 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5869 size = int_size_in_bytes (type);
5870 rsize = (size + 3) / 4;
5873 if (TARGET_HARD_FLOAT && TARGET_FPRS
5874 && (TYPE_MODE (type) == SFmode
5875 || TYPE_MODE (type) == DFmode
5876 || TYPE_MODE (type) == TFmode))
5878 /* FP args go in FP registers, if present. */
5880 n_reg = (size + 7) / 8;
5883 if (TYPE_MODE (type) != SFmode)
5888 /* Otherwise into GP registers. */
5897 /* Pull the value out of the saved registers.... */
5900 addr = create_tmp_var (ptr_type_node, "addr");
5901 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5903 /* AltiVec vectors never go in registers when -mabi=altivec. */
5904 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5908 lab_false = create_artificial_label ();
5909 lab_over = create_artificial_label ();
5911 /* Long long and SPE vectors are aligned in the registers.
5912 As are any other 2 gpr item such as complex int due to a
5913 historical mistake. */
5915 if (n_reg == 2 && reg == gpr)
5917 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5918 size_int (n_reg - 1));
5919 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5922 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5923 t = build2 (GE_EXPR, boolean_type_node, u, t);
5924 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5925 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5926 gimplify_and_add (t, pre_p);
5930 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5932 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5933 u = build1 (CONVERT_EXPR, integer_type_node, u);
5934 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5935 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5937 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5938 gimplify_and_add (t, pre_p);
5940 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5941 gimplify_and_add (t, pre_p);
5943 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5944 append_to_statement_list (t, pre_p);
5948 /* Ensure that we don't find any more args in regs.
5949 Alignment has taken care of the n_reg == 2 case. */
5950 t = build2 (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
5951 gimplify_and_add (t, pre_p);
5955 /* ... otherwise out of the overflow area. */
5957 /* Care for on-stack alignment if needed. */
5961 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
5962 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5963 build_int_cst (NULL_TREE, -align));
5965 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5967 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5968 gimplify_and_add (u, pre_p);
5970 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
5971 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5972 gimplify_and_add (t, pre_p);
5976 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5977 append_to_statement_list (t, pre_p);
5980 addr = fold_convert (ptrtype, addr);
5981 return build_va_arg_indirect_ref (addr);
5987 def_builtin (int mask, const char *name, tree type, int code)
5989 if (mask & target_flags)
5991 if (rs6000_builtin_decls[code])
5994 rs6000_builtin_decls[code] =
5995 lang_hooks.builtin_function (name, type, code, BUILT_IN_MD,
6000 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6002 static const struct builtin_description bdesc_3arg[] =
6004 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6005 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6006 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6007 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6008 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6009 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6010 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6011 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6012 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6013 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6014 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6015 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6016 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6017 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6018 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6019 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6020 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6021 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6022 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6023 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6024 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6025 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6026 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6028 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6029 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6030 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6031 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6032 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6033 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6034 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6035 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6036 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6037 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6038 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6039 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6040 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6041 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6042 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6045 /* DST operations: void foo (void *, const int, const char). */
6047 static const struct builtin_description bdesc_dst[] =
6049 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6050 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6051 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6052 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6054 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6055 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6056 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6057 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6060 /* Simple binary operations: VECc = foo (VECa, VECb). */
6062 static struct builtin_description bdesc_2arg[] =
6064 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6065 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6066 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6067 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6068 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6069 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6070 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6071 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6072 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6073 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6074 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6075 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6076 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6077 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6078 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6079 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6080 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6081 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6082 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6083 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6084 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6085 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6086 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6087 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6088 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6089 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6090 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6091 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6092 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6093 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6094 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6095 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6096 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6097 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6098 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6099 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6100 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6101 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6102 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6103 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6104 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6105 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6106 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6107 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6108 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6109 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6110 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6111 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6112 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6113 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6114 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6115 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6116 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6117 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6118 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6119 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6120 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6121 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6122 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6123 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6124 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6125 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6126 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6127 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6128 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6129 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6130 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6131 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6132 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6133 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6134 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6135 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6136 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6137 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6138 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6139 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6140 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6141 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6142 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6143 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6144 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6145 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6146 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6147 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6148 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6149 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6150 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6151 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6152 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6153 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6154 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6155 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6156 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6157 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6158 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6159 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6160 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6161 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6162 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6163 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6164 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6165 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6166 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6167 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6168 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6169 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6170 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6171 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6172 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6173 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6174 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6176 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6177 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6178 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6179 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6180 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6181 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6182 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6183 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6184 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6185 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6186 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6187 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6188 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6189 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6190 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6191 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6192 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6193 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6194 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6195 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6196 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6197 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6198 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6199 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6200 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6201 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6202 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6203 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6204 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6205 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6206 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6207 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6208 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6209 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6210 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6211 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6212 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6213 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6214 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6215 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6216 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6217 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6218 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6219 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6220 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6221 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6222 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6223 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6224 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6225 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6226 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6227 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6228 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6229 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6230 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6231 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6232 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6233 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6234 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6235 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6236 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6237 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6238 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6239 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6240 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6241 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6242 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6243 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6244 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6245 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6246 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6247 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6248 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6249 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6250 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6251 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6252 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6253 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6254 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6255 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6256 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6257 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6258 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6259 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6260 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6261 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6262 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6263 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6264 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6265 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6266 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6267 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6268 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6269 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6270 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6271 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6272 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6273 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6274 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6275 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6276 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6277 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6278 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6279 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6280 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6281 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6282 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6283 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6284 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6285 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6286 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6287 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6288 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6289 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6290 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6291 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6292 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6293 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6294 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6295 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6296 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6297 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6298 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6299 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6300 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6301 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6302 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6304 /* Place holder, leave as first spe builtin. */
6305 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6306 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6307 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6308 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6309 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6310 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6311 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6312 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6313 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6314 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6315 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6316 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6317 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6318 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6319 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6320 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6321 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6322 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6323 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6324 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6325 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6326 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6327 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6328 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6329 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6330 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6331 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6332 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6333 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6334 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6335 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6336 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6337 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6338 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6339 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6340 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6341 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6342 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6343 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6344 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6345 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6346 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6347 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6348 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6349 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6350 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6351 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6352 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6353 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6354 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6355 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6356 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6357 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6358 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6359 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6360 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6361 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6362 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6363 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6364 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6365 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6366 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6367 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6368 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6369 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6370 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6371 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6372 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6373 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6374 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6375 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6376 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6377 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6378 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6379 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6380 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6381 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6382 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6383 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6384 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6385 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6386 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6387 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6388 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6389 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6390 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6391 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6392 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6393 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6394 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6395 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6396 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6397 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6398 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6399 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6400 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6401 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6402 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6403 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6404 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6405 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6406 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6407 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6408 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6409 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6410 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6411 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6412 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6413 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6415 /* SPE binary operations expecting a 5-bit unsigned literal. */
6416 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6418 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6419 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6420 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6421 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6422 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6423 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6424 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6425 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6426 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6427 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6428 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6429 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6430 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6431 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6432 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6433 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6434 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6435 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6436 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6437 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6438 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6439 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6440 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6441 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6442 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6443 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6445 /* Place-holder. Leave as last binary SPE builtin. */
6446 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6449 /* AltiVec predicates. */
6451 struct builtin_description_predicates
6453 const unsigned int mask;
6454 const enum insn_code icode;
6456 const char *const name;
6457 const enum rs6000_builtins code;
6460 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6462 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6463 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6464 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6465 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6466 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6467 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6468 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6469 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6470 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6471 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6472 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6473 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6474 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6476 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6477 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6478 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6481 /* SPE predicates. */
6482 static struct builtin_description bdesc_spe_predicates[] =
6484 /* Place-holder. Leave as first. */
6485 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6486 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6487 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6488 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6489 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6490 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6491 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6492 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6493 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6494 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6495 /* Place-holder. Leave as last. */
6496 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6499 /* SPE evsel predicates. */
6500 static struct builtin_description bdesc_spe_evsel[] =
6502 /* Place-holder. Leave as first. */
6503 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6504 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6505 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6506 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6507 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6508 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6509 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6510 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6511 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6512 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6513 /* Place-holder. Leave as last. */
6514 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6517 /* ABS* operations. */
6519 static const struct builtin_description bdesc_abs[] =
6521 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6522 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6523 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6524 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6525 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6526 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6527 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6530 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6533 static struct builtin_description bdesc_1arg[] =
6535 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6536 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6537 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6538 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6539 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6540 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6541 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6542 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6543 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6544 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6545 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6546 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6547 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6548 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6549 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6550 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6551 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6553 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6554 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6555 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6556 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6557 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6558 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6559 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6560 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6561 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6562 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6563 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
6564 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
6565 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
6566 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
6567 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
6568 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
6569 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
6570 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
6571 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
6573 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6574 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6575 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6576 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6577 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6578 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6579 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6580 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6581 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6582 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6583 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6584 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6585 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6586 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6587 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6588 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6589 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6590 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6591 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6592 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6593 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6594 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6595 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6596 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6597 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6598 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6599 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6600 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6601 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6602 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6604 /* Place-holder. Leave as last unary SPE builtin. */
6605 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
6609 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6612 tree arg0 = TREE_VALUE (arglist);
6613 rtx op0 = expand_normal (arg0);
6614 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6615 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6617 if (icode == CODE_FOR_nothing)
6618 /* Builtin not supported on this processor. */
6621 /* If we got invalid arguments bail out before generating bad rtl. */
6622 if (arg0 == error_mark_node)
6625 if (icode == CODE_FOR_altivec_vspltisb
6626 || icode == CODE_FOR_altivec_vspltish
6627 || icode == CODE_FOR_altivec_vspltisw
6628 || icode == CODE_FOR_spe_evsplatfi
6629 || icode == CODE_FOR_spe_evsplati)
6631 /* Only allow 5-bit *signed* literals. */
6632 if (GET_CODE (op0) != CONST_INT
6633 || INTVAL (op0) > 15
6634 || INTVAL (op0) < -16)
6636 error ("argument 1 must be a 5-bit signed literal");
6642 || GET_MODE (target) != tmode
6643 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6644 target = gen_reg_rtx (tmode);
6646 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6647 op0 = copy_to_mode_reg (mode0, op0);
6649 pat = GEN_FCN (icode) (target, op0);
6658 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6660 rtx pat, scratch1, scratch2;
6661 tree arg0 = TREE_VALUE (arglist);
6662 rtx op0 = expand_normal (arg0);
6663 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6664 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6666 /* If we have invalid arguments, bail out before generating bad rtl. */
6667 if (arg0 == error_mark_node)
6671 || GET_MODE (target) != tmode
6672 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6673 target = gen_reg_rtx (tmode);
6675 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6676 op0 = copy_to_mode_reg (mode0, op0);
6678 scratch1 = gen_reg_rtx (mode0);
6679 scratch2 = gen_reg_rtx (mode0);
6681 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6690 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6693 tree arg0 = TREE_VALUE (arglist);
6694 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6695 rtx op0 = expand_normal (arg0);
6696 rtx op1 = expand_normal (arg1);
6697 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6698 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6699 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6701 if (icode == CODE_FOR_nothing)
6702 /* Builtin not supported on this processor. */
6705 /* If we got invalid arguments bail out before generating bad rtl. */
6706 if (arg0 == error_mark_node || arg1 == error_mark_node)
6709 if (icode == CODE_FOR_altivec_vcfux
6710 || icode == CODE_FOR_altivec_vcfsx
6711 || icode == CODE_FOR_altivec_vctsxs
6712 || icode == CODE_FOR_altivec_vctuxs
6713 || icode == CODE_FOR_altivec_vspltb
6714 || icode == CODE_FOR_altivec_vsplth
6715 || icode == CODE_FOR_altivec_vspltw
6716 || icode == CODE_FOR_spe_evaddiw
6717 || icode == CODE_FOR_spe_evldd
6718 || icode == CODE_FOR_spe_evldh
6719 || icode == CODE_FOR_spe_evldw
6720 || icode == CODE_FOR_spe_evlhhesplat
6721 || icode == CODE_FOR_spe_evlhhossplat
6722 || icode == CODE_FOR_spe_evlhhousplat
6723 || icode == CODE_FOR_spe_evlwhe
6724 || icode == CODE_FOR_spe_evlwhos
6725 || icode == CODE_FOR_spe_evlwhou
6726 || icode == CODE_FOR_spe_evlwhsplat
6727 || icode == CODE_FOR_spe_evlwwsplat
6728 || icode == CODE_FOR_spe_evrlwi
6729 || icode == CODE_FOR_spe_evslwi
6730 || icode == CODE_FOR_spe_evsrwis
6731 || icode == CODE_FOR_spe_evsubifw
6732 || icode == CODE_FOR_spe_evsrwiu)
6734 /* Only allow 5-bit unsigned literals. */
6736 if (TREE_CODE (arg1) != INTEGER_CST
6737 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6739 error ("argument 2 must be a 5-bit unsigned literal");
6745 || GET_MODE (target) != tmode
6746 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6747 target = gen_reg_rtx (tmode);
6749 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6750 op0 = copy_to_mode_reg (mode0, op0);
6751 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6752 op1 = copy_to_mode_reg (mode1, op1);
6754 pat = GEN_FCN (icode) (target, op0, op1);
6763 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6764 tree arglist, rtx target)
6767 tree cr6_form = TREE_VALUE (arglist);
6768 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6769 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6770 rtx op0 = expand_normal (arg0);
6771 rtx op1 = expand_normal (arg1);
6772 enum machine_mode tmode = SImode;
6773 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6774 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6777 if (TREE_CODE (cr6_form) != INTEGER_CST)
6779 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6783 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6785 gcc_assert (mode0 == mode1);
6787 /* If we have invalid arguments, bail out before generating bad rtl. */
6788 if (arg0 == error_mark_node || arg1 == error_mark_node)
6792 || GET_MODE (target) != tmode
6793 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6794 target = gen_reg_rtx (tmode);
6796 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6797 op0 = copy_to_mode_reg (mode0, op0);
6798 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6799 op1 = copy_to_mode_reg (mode1, op1);
6801 scratch = gen_reg_rtx (mode0);
6803 pat = GEN_FCN (icode) (scratch, op0, op1,
6804 gen_rtx_SYMBOL_REF (Pmode, opcode));
6809 /* The vec_any* and vec_all* predicates use the same opcodes for two
6810 different operations, but the bits in CR6 will be different
6811 depending on what information we want. So we have to play tricks
6812 with CR6 to get the right bits out.
6814 If you think this is disgusting, look at the specs for the
6815 AltiVec predicates. */
6817 switch (cr6_form_int)
6820 emit_insn (gen_cr6_test_for_zero (target));
6823 emit_insn (gen_cr6_test_for_zero_reverse (target));
6826 emit_insn (gen_cr6_test_for_lt (target));
6829 emit_insn (gen_cr6_test_for_lt_reverse (target));
6832 error ("argument 1 of __builtin_altivec_predicate is out of range");
6840 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6843 tree arg0 = TREE_VALUE (arglist);
6844 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6845 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6846 enum machine_mode mode0 = Pmode;
6847 enum machine_mode mode1 = Pmode;
6848 rtx op0 = expand_normal (arg0);
6849 rtx op1 = expand_normal (arg1);
6851 if (icode == CODE_FOR_nothing)
6852 /* Builtin not supported on this processor. */
6855 /* If we got invalid arguments bail out before generating bad rtl. */
6856 if (arg0 == error_mark_node || arg1 == error_mark_node)
6860 || GET_MODE (target) != tmode
6861 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6862 target = gen_reg_rtx (tmode);
6864 op1 = copy_to_mode_reg (mode1, op1);
6866 if (op0 == const0_rtx)
6868 addr = gen_rtx_MEM (tmode, op1);
6872 op0 = copy_to_mode_reg (mode0, op0);
6873 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6876 pat = GEN_FCN (icode) (target, addr);
6886 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6888 tree arg0 = TREE_VALUE (arglist);
6889 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6890 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6891 rtx op0 = expand_normal (arg0);
6892 rtx op1 = expand_normal (arg1);
6893 rtx op2 = expand_normal (arg2);
6895 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6896 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6897 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6899 /* Invalid arguments. Bail before doing anything stoopid! */
6900 if (arg0 == error_mark_node
6901 || arg1 == error_mark_node
6902 || arg2 == error_mark_node)
6905 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6906 op0 = copy_to_mode_reg (mode2, op0);
6907 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6908 op1 = copy_to_mode_reg (mode0, op1);
6909 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6910 op2 = copy_to_mode_reg (mode1, op2);
6912 pat = GEN_FCN (icode) (op1, op2, op0);
6919 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6921 tree arg0 = TREE_VALUE (arglist);
6922 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6923 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6924 rtx op0 = expand_normal (arg0);
6925 rtx op1 = expand_normal (arg1);
6926 rtx op2 = expand_normal (arg2);
6928 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6929 enum machine_mode mode1 = Pmode;
6930 enum machine_mode mode2 = Pmode;
6932 /* Invalid arguments. Bail before doing anything stoopid! */
6933 if (arg0 == error_mark_node
6934 || arg1 == error_mark_node
6935 || arg2 == error_mark_node)
6938 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6939 op0 = copy_to_mode_reg (tmode, op0);
6941 op2 = copy_to_mode_reg (mode2, op2);
6943 if (op1 == const0_rtx)
6945 addr = gen_rtx_MEM (tmode, op2);
6949 op1 = copy_to_mode_reg (mode1, op1);
6950 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6953 pat = GEN_FCN (icode) (addr, op0);
6960 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6963 tree arg0 = TREE_VALUE (arglist);
6964 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6965 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6966 rtx op0 = expand_normal (arg0);
6967 rtx op1 = expand_normal (arg1);
6968 rtx op2 = expand_normal (arg2);
6969 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6970 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6971 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6972 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6974 if (icode == CODE_FOR_nothing)
6975 /* Builtin not supported on this processor. */
6978 /* If we got invalid arguments bail out before generating bad rtl. */
6979 if (arg0 == error_mark_node
6980 || arg1 == error_mark_node
6981 || arg2 == error_mark_node)
6984 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6985 || icode == CODE_FOR_altivec_vsldoi_v4si
6986 || icode == CODE_FOR_altivec_vsldoi_v8hi
6987 || icode == CODE_FOR_altivec_vsldoi_v16qi)
6989 /* Only allow 4-bit unsigned literals. */
6991 if (TREE_CODE (arg2) != INTEGER_CST
6992 || TREE_INT_CST_LOW (arg2) & ~0xf)
6994 error ("argument 3 must be a 4-bit unsigned literal");
7000 || GET_MODE (target) != tmode
7001 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7002 target = gen_reg_rtx (tmode);
7004 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7005 op0 = copy_to_mode_reg (mode0, op0);
7006 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7007 op1 = copy_to_mode_reg (mode1, op1);
7008 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7009 op2 = copy_to_mode_reg (mode2, op2);
7011 pat = GEN_FCN (icode) (target, op0, op1, op2);
7019 /* Expand the lvx builtins. */
7021 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7023 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7024 tree arglist = TREE_OPERAND (exp, 1);
7025 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7027 enum machine_mode tmode, mode0;
7029 enum insn_code icode;
7033 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7034 icode = CODE_FOR_altivec_lvx_v16qi;
7036 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7037 icode = CODE_FOR_altivec_lvx_v8hi;
7039 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7040 icode = CODE_FOR_altivec_lvx_v4si;
7042 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7043 icode = CODE_FOR_altivec_lvx_v4sf;
7052 arg0 = TREE_VALUE (arglist);
7053 op0 = expand_normal (arg0);
7054 tmode = insn_data[icode].operand[0].mode;
7055 mode0 = insn_data[icode].operand[1].mode;
7058 || GET_MODE (target) != tmode
7059 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7060 target = gen_reg_rtx (tmode);
7062 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7063 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7065 pat = GEN_FCN (icode) (target, op0);
7072 /* Expand the stvx builtins. */
7074 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7077 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7078 tree arglist = TREE_OPERAND (exp, 1);
7079 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7081 enum machine_mode mode0, mode1;
7083 enum insn_code icode;
7087 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7088 icode = CODE_FOR_altivec_stvx_v16qi;
7090 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7091 icode = CODE_FOR_altivec_stvx_v8hi;
7093 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7094 icode = CODE_FOR_altivec_stvx_v4si;
7096 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7097 icode = CODE_FOR_altivec_stvx_v4sf;
7104 arg0 = TREE_VALUE (arglist);
7105 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7106 op0 = expand_normal (arg0);
7107 op1 = expand_normal (arg1);
7108 mode0 = insn_data[icode].operand[0].mode;
7109 mode1 = insn_data[icode].operand[1].mode;
7111 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7112 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7113 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7114 op1 = copy_to_mode_reg (mode1, op1);
7116 pat = GEN_FCN (icode) (op0, op1);
7124 /* Expand the dst builtins. */
7126 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7129 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7130 tree arglist = TREE_OPERAND (exp, 1);
7131 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7132 tree arg0, arg1, arg2;
7133 enum machine_mode mode0, mode1, mode2;
7134 rtx pat, op0, op1, op2;
7135 struct builtin_description *d;
7140 /* Handle DST variants. */
7141 d = (struct builtin_description *) bdesc_dst;
7142 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7143 if (d->code == fcode)
7145 arg0 = TREE_VALUE (arglist);
7146 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7147 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7148 op0 = expand_normal (arg0);
7149 op1 = expand_normal (arg1);
7150 op2 = expand_normal (arg2);
7151 mode0 = insn_data[d->icode].operand[0].mode;
7152 mode1 = insn_data[d->icode].operand[1].mode;
7153 mode2 = insn_data[d->icode].operand[2].mode;
7155 /* Invalid arguments, bail out before generating bad rtl. */
7156 if (arg0 == error_mark_node
7157 || arg1 == error_mark_node
7158 || arg2 == error_mark_node)
7163 if (TREE_CODE (arg2) != INTEGER_CST
7164 || TREE_INT_CST_LOW (arg2) & ~0x3)
7166 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7170 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7171 op0 = copy_to_mode_reg (Pmode, op0);
7172 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7173 op1 = copy_to_mode_reg (mode1, op1);
7175 pat = GEN_FCN (d->icode) (op0, op1, op2);
7185 /* Expand vec_init builtin. */
7187 altivec_expand_vec_init_builtin (tree type, tree arglist, rtx target)
7189 enum machine_mode tmode = TYPE_MODE (type);
7190 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7191 int i, n_elt = GET_MODE_NUNITS (tmode);
7192 rtvec v = rtvec_alloc (n_elt);
7194 gcc_assert (VECTOR_MODE_P (tmode));
7196 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
7198 rtx x = expand_normal (TREE_VALUE (arglist));
7199 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7202 gcc_assert (arglist == NULL);
7204 if (!target || !register_operand (target, tmode))
7205 target = gen_reg_rtx (tmode);
7207 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7211 /* Return the integer constant in ARG. Constrain it to be in the range
7212 of the subparts of VEC_TYPE; issue an error if not. */
7215 get_element_number (tree vec_type, tree arg)
7217 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7219 if (!host_integerp (arg, 1)
7220 || (elt = tree_low_cst (arg, 1), elt > max))
7222 error ("selector must be an integer constant in the range 0..%wi", max);
7229 /* Expand vec_set builtin. */
7231 altivec_expand_vec_set_builtin (tree arglist)
7233 enum machine_mode tmode, mode1;
7234 tree arg0, arg1, arg2;
7238 arg0 = TREE_VALUE (arglist);
7239 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7240 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7242 tmode = TYPE_MODE (TREE_TYPE (arg0));
7243 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7244 gcc_assert (VECTOR_MODE_P (tmode));
7246 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7247 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7248 elt = get_element_number (TREE_TYPE (arg0), arg2);
7250 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7251 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7253 op0 = force_reg (tmode, op0);
7254 op1 = force_reg (mode1, op1);
7256 rs6000_expand_vector_set (op0, op1, elt);
7261 /* Expand vec_ext builtin. */
7263 altivec_expand_vec_ext_builtin (tree arglist, rtx target)
7265 enum machine_mode tmode, mode0;
7270 arg0 = TREE_VALUE (arglist);
7271 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7273 op0 = expand_normal (arg0);
7274 elt = get_element_number (TREE_TYPE (arg0), arg1);
7276 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7277 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7278 gcc_assert (VECTOR_MODE_P (mode0));
7280 op0 = force_reg (mode0, op0);
7282 if (optimize || !target || !register_operand (target, tmode))
7283 target = gen_reg_rtx (tmode);
7285 rs6000_expand_vector_extract (target, op0, elt);
7290 /* Expand the builtin in EXP and store the result in TARGET. Store
7291 true in *EXPANDEDP if we found a builtin to expand. */
7293 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7295 struct builtin_description *d;
7296 struct builtin_description_predicates *dp;
7298 enum insn_code icode;
7299 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7300 tree arglist = TREE_OPERAND (exp, 1);
7303 enum machine_mode tmode, mode0;
7304 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7306 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7307 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7310 error ("unresolved overload for Altivec builtin %qF", fndecl);
7314 target = altivec_expand_ld_builtin (exp, target, expandedp);
7318 target = altivec_expand_st_builtin (exp, target, expandedp);
7322 target = altivec_expand_dst_builtin (exp, target, expandedp);
7330 case ALTIVEC_BUILTIN_STVX:
7331 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
7332 case ALTIVEC_BUILTIN_STVEBX:
7333 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
7334 case ALTIVEC_BUILTIN_STVEHX:
7335 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
7336 case ALTIVEC_BUILTIN_STVEWX:
7337 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
7338 case ALTIVEC_BUILTIN_STVXL:
7339 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
7341 case ALTIVEC_BUILTIN_MFVSCR:
7342 icode = CODE_FOR_altivec_mfvscr;
7343 tmode = insn_data[icode].operand[0].mode;
7346 || GET_MODE (target) != tmode
7347 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7348 target = gen_reg_rtx (tmode);
7350 pat = GEN_FCN (icode) (target);
7356 case ALTIVEC_BUILTIN_MTVSCR:
7357 icode = CODE_FOR_altivec_mtvscr;
7358 arg0 = TREE_VALUE (arglist);
7359 op0 = expand_normal (arg0);
7360 mode0 = insn_data[icode].operand[0].mode;
7362 /* If we got invalid arguments bail out before generating bad rtl. */
7363 if (arg0 == error_mark_node)
7366 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7367 op0 = copy_to_mode_reg (mode0, op0);
7369 pat = GEN_FCN (icode) (op0);
7374 case ALTIVEC_BUILTIN_DSSALL:
7375 emit_insn (gen_altivec_dssall ());
7378 case ALTIVEC_BUILTIN_DSS:
7379 icode = CODE_FOR_altivec_dss;
7380 arg0 = TREE_VALUE (arglist);
7382 op0 = expand_normal (arg0);
7383 mode0 = insn_data[icode].operand[0].mode;
7385 /* If we got invalid arguments bail out before generating bad rtl. */
7386 if (arg0 == error_mark_node)
7389 if (TREE_CODE (arg0) != INTEGER_CST
7390 || TREE_INT_CST_LOW (arg0) & ~0x3)
7392 error ("argument to dss must be a 2-bit unsigned literal");
7396 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7397 op0 = copy_to_mode_reg (mode0, op0);
7399 emit_insn (gen_altivec_dss (op0));
7402 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7403 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7404 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7405 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7406 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
7408 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7409 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7410 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7411 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7412 return altivec_expand_vec_set_builtin (arglist);
7414 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7415 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7416 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7417 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7418 return altivec_expand_vec_ext_builtin (arglist, target);
7425 /* Expand abs* operations. */
7426 d = (struct builtin_description *) bdesc_abs;
7427 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7428 if (d->code == fcode)
7429 return altivec_expand_abs_builtin (d->icode, arglist, target);
7431 /* Expand the AltiVec predicates. */
7432 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7433 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7434 if (dp->code == fcode)
7435 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7438 /* LV* are funky. We initialized them differently. */
7441 case ALTIVEC_BUILTIN_LVSL:
7442 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7444 case ALTIVEC_BUILTIN_LVSR:
7445 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7447 case ALTIVEC_BUILTIN_LVEBX:
7448 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7450 case ALTIVEC_BUILTIN_LVEHX:
7451 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7453 case ALTIVEC_BUILTIN_LVEWX:
7454 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7456 case ALTIVEC_BUILTIN_LVXL:
7457 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7459 case ALTIVEC_BUILTIN_LVX:
7460 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7471 /* Binops that need to be initialized manually, but can be expanded
7472 automagically by rs6000_expand_binop_builtin. */
7473 static struct builtin_description bdesc_2arg_spe[] =
7475 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7476 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7477 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7478 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7479 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7480 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7481 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7482 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7483 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7484 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7485 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7486 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7487 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7488 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7489 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7490 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7491 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7492 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7493 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7494 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7495 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7496 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7499 /* Expand the builtin in EXP and store the result in TARGET. Store
7500 true in *EXPANDEDP if we found a builtin to expand.
7502 This expands the SPE builtins that are not simple unary and binary
7505 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7507 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7508 tree arglist = TREE_OPERAND (exp, 1);
7510 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7511 enum insn_code icode;
7512 enum machine_mode tmode, mode0;
7514 struct builtin_description *d;
7519 /* Syntax check for a 5-bit unsigned immediate. */
7522 case SPE_BUILTIN_EVSTDD:
7523 case SPE_BUILTIN_EVSTDH:
7524 case SPE_BUILTIN_EVSTDW:
7525 case SPE_BUILTIN_EVSTWHE:
7526 case SPE_BUILTIN_EVSTWHO:
7527 case SPE_BUILTIN_EVSTWWE:
7528 case SPE_BUILTIN_EVSTWWO:
7529 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7530 if (TREE_CODE (arg1) != INTEGER_CST
7531 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7533 error ("argument 2 must be a 5-bit unsigned literal");
7541 /* The evsplat*i instructions are not quite generic. */
7544 case SPE_BUILTIN_EVSPLATFI:
7545 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7547 case SPE_BUILTIN_EVSPLATI:
7548 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7554 d = (struct builtin_description *) bdesc_2arg_spe;
7555 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7556 if (d->code == fcode)
7557 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7559 d = (struct builtin_description *) bdesc_spe_predicates;
7560 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7561 if (d->code == fcode)
7562 return spe_expand_predicate_builtin (d->icode, arglist, target);
7564 d = (struct builtin_description *) bdesc_spe_evsel;
7565 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7566 if (d->code == fcode)
7567 return spe_expand_evsel_builtin (d->icode, arglist, target);
7571 case SPE_BUILTIN_EVSTDDX:
7572 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7573 case SPE_BUILTIN_EVSTDHX:
7574 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7575 case SPE_BUILTIN_EVSTDWX:
7576 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7577 case SPE_BUILTIN_EVSTWHEX:
7578 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7579 case SPE_BUILTIN_EVSTWHOX:
7580 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7581 case SPE_BUILTIN_EVSTWWEX:
7582 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7583 case SPE_BUILTIN_EVSTWWOX:
7584 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7585 case SPE_BUILTIN_EVSTDD:
7586 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7587 case SPE_BUILTIN_EVSTDH:
7588 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7589 case SPE_BUILTIN_EVSTDW:
7590 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7591 case SPE_BUILTIN_EVSTWHE:
7592 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7593 case SPE_BUILTIN_EVSTWHO:
7594 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7595 case SPE_BUILTIN_EVSTWWE:
7596 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7597 case SPE_BUILTIN_EVSTWWO:
7598 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7599 case SPE_BUILTIN_MFSPEFSCR:
7600 icode = CODE_FOR_spe_mfspefscr;
7601 tmode = insn_data[icode].operand[0].mode;
7604 || GET_MODE (target) != tmode
7605 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7606 target = gen_reg_rtx (tmode);
7608 pat = GEN_FCN (icode) (target);
7613 case SPE_BUILTIN_MTSPEFSCR:
7614 icode = CODE_FOR_spe_mtspefscr;
7615 arg0 = TREE_VALUE (arglist);
7616 op0 = expand_normal (arg0);
7617 mode0 = insn_data[icode].operand[0].mode;
7619 if (arg0 == error_mark_node)
7622 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7623 op0 = copy_to_mode_reg (mode0, op0);
7625 pat = GEN_FCN (icode) (op0);
7638 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7640 rtx pat, scratch, tmp;
7641 tree form = TREE_VALUE (arglist);
7642 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7643 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7644 rtx op0 = expand_normal (arg0);
7645 rtx op1 = expand_normal (arg1);
7646 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7647 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7651 if (TREE_CODE (form) != INTEGER_CST)
7653 error ("argument 1 of __builtin_spe_predicate must be a constant");
7657 form_int = TREE_INT_CST_LOW (form);
7659 gcc_assert (mode0 == mode1);
7661 if (arg0 == error_mark_node || arg1 == error_mark_node)
7665 || GET_MODE (target) != SImode
7666 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7667 target = gen_reg_rtx (SImode);
7669 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7670 op0 = copy_to_mode_reg (mode0, op0);
7671 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7672 op1 = copy_to_mode_reg (mode1, op1);
7674 scratch = gen_reg_rtx (CCmode);
7676 pat = GEN_FCN (icode) (scratch, op0, op1);
7681 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7682 _lower_. We use one compare, but look in different bits of the
7683 CR for each variant.
7685 There are 2 elements in each SPE simd type (upper/lower). The CR
7686 bits are set as follows:
7688 BIT0 | BIT 1 | BIT 2 | BIT 3
7689 U | L | (U | L) | (U & L)
7691 So, for an "all" relationship, BIT 3 would be set.
7692 For an "any" relationship, BIT 2 would be set. Etc.
7694 Following traditional nomenclature, these bits map to:
7696 BIT0 | BIT 1 | BIT 2 | BIT 3
7699 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7704 /* All variant. OV bit. */
7706 /* We need to get to the OV bit, which is the ORDERED bit. We
7707 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7708 that's ugly and will make validate_condition_mode die.
7709 So let's just use another pattern. */
7710 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7712 /* Any variant. EQ bit. */
7716 /* Upper variant. LT bit. */
7720 /* Lower variant. GT bit. */
7725 error ("argument 1 of __builtin_spe_predicate is out of range");
7729 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7730 emit_move_insn (target, tmp);
7735 /* The evsel builtins look like this:
7737 e = __builtin_spe_evsel_OP (a, b, c, d);
7741 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7742 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7746 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7749 tree arg0 = TREE_VALUE (arglist);
7750 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7751 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7752 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7753 rtx op0 = expand_normal (arg0);
7754 rtx op1 = expand_normal (arg1);
7755 rtx op2 = expand_normal (arg2);
7756 rtx op3 = expand_normal (arg3);
7757 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7758 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7760 gcc_assert (mode0 == mode1);
7762 if (arg0 == error_mark_node || arg1 == error_mark_node
7763 || arg2 == error_mark_node || arg3 == error_mark_node)
7767 || GET_MODE (target) != mode0
7768 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7769 target = gen_reg_rtx (mode0);
7771 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7772 op0 = copy_to_mode_reg (mode0, op0);
7773 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7774 op1 = copy_to_mode_reg (mode0, op1);
7775 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7776 op2 = copy_to_mode_reg (mode0, op2);
7777 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7778 op3 = copy_to_mode_reg (mode0, op3);
7780 /* Generate the compare. */
7781 scratch = gen_reg_rtx (CCmode);
7782 pat = GEN_FCN (icode) (scratch, op0, op1);
7787 if (mode0 == V2SImode)
7788 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7790 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7795 /* Expand an expression EXP that calls a built-in function,
7796 with result going to TARGET if that's convenient
7797 (and in mode MODE if that's convenient).
7798 SUBTARGET may be used as the target for computing one of EXP's operands.
7799 IGNORE is nonzero if the value is to be ignored. */
7802 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7803 enum machine_mode mode ATTRIBUTE_UNUSED,
7804 int ignore ATTRIBUTE_UNUSED)
7806 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7807 tree arglist = TREE_OPERAND (exp, 1);
7808 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7809 struct builtin_description *d;
7814 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7815 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7817 int icode = (int) CODE_FOR_altivec_lvsr;
7818 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7819 enum machine_mode mode = insn_data[icode].operand[1].mode;
7823 gcc_assert (TARGET_ALTIVEC);
7825 arg = TREE_VALUE (arglist);
7826 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
7827 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7828 addr = memory_address (mode, op);
7829 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7833 /* For the load case need to negate the address. */
7834 op = gen_reg_rtx (GET_MODE (addr));
7835 emit_insn (gen_rtx_SET (VOIDmode, op,
7836 gen_rtx_NEG (GET_MODE (addr), addr)));
7838 op = gen_rtx_MEM (mode, op);
7841 || GET_MODE (target) != tmode
7842 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7843 target = gen_reg_rtx (tmode);
7845 /*pat = gen_altivec_lvsr (target, op);*/
7846 pat = GEN_FCN (icode) (target, op);
7856 ret = altivec_expand_builtin (exp, target, &success);
7863 ret = spe_expand_builtin (exp, target, &success);
7869 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
7871 /* Handle simple unary operations. */
7872 d = (struct builtin_description *) bdesc_1arg;
7873 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7874 if (d->code == fcode)
7875 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7877 /* Handle simple binary operations. */
7878 d = (struct builtin_description *) bdesc_2arg;
7879 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7880 if (d->code == fcode)
7881 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7883 /* Handle simple ternary operations. */
7884 d = (struct builtin_description *) bdesc_3arg;
7885 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7886 if (d->code == fcode)
7887 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7893 build_opaque_vector_type (tree node, int nunits)
7895 node = copy_node (node);
7896 TYPE_MAIN_VARIANT (node) = node;
7897 return build_vector_type (node, nunits);
7901 rs6000_init_builtins (void)
7903 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7904 V2SF_type_node = build_vector_type (float_type_node, 2);
7905 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7906 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7907 V4SF_type_node = build_vector_type (float_type_node, 4);
7908 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7909 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7911 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7912 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7913 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7915 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7916 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7917 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7918 opaque_V4SI_type_node = copy_node (V4SI_type_node);
7920 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7921 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7922 'vector unsigned short'. */
7924 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7925 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7926 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7927 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7929 long_integer_type_internal_node = long_integer_type_node;
7930 long_unsigned_type_internal_node = long_unsigned_type_node;
7931 intQI_type_internal_node = intQI_type_node;
7932 uintQI_type_internal_node = unsigned_intQI_type_node;
7933 intHI_type_internal_node = intHI_type_node;
7934 uintHI_type_internal_node = unsigned_intHI_type_node;
7935 intSI_type_internal_node = intSI_type_node;
7936 uintSI_type_internal_node = unsigned_intSI_type_node;
7937 float_type_internal_node = float_type_node;
7938 void_type_internal_node = void_type_node;
7940 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7941 get_identifier ("__bool char"),
7942 bool_char_type_node));
7943 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7944 get_identifier ("__bool short"),
7945 bool_short_type_node));
7946 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7947 get_identifier ("__bool int"),
7948 bool_int_type_node));
7949 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7950 get_identifier ("__pixel"),
7953 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7954 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7955 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7956 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7958 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7959 get_identifier ("__vector unsigned char"),
7960 unsigned_V16QI_type_node));
7961 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7962 get_identifier ("__vector signed char"),
7964 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7965 get_identifier ("__vector __bool char"),
7966 bool_V16QI_type_node));
7968 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7969 get_identifier ("__vector unsigned short"),
7970 unsigned_V8HI_type_node));
7971 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7972 get_identifier ("__vector signed short"),
7974 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7975 get_identifier ("__vector __bool short"),
7976 bool_V8HI_type_node));
7978 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7979 get_identifier ("__vector unsigned int"),
7980 unsigned_V4SI_type_node));
7981 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7982 get_identifier ("__vector signed int"),
7984 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7985 get_identifier ("__vector __bool int"),
7986 bool_V4SI_type_node));
7988 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7989 get_identifier ("__vector float"),
7991 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7992 get_identifier ("__vector __pixel"),
7993 pixel_V8HI_type_node));
7996 spe_init_builtins ();
7998 altivec_init_builtins ();
7999 if (TARGET_ALTIVEC || TARGET_SPE)
8000 rs6000_common_init_builtins ();
8003 /* AIX libm provides clog as __clog. */
8004 if (built_in_decls [BUILT_IN_CLOG])
8005 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
8009 /* Search through a set of builtins and enable the mask bits.
8010 DESC is an array of builtins.
8011 SIZE is the total number of builtins.
8012 START is the builtin enum at which to start.
8013 END is the builtin enum at which to end. */
8015 enable_mask_for_builtins (struct builtin_description *desc, int size,
8016 enum rs6000_builtins start,
8017 enum rs6000_builtins end)
8021 for (i = 0; i < size; ++i)
8022 if (desc[i].code == start)
8028 for (; i < size; ++i)
8030 /* Flip all the bits on. */
8031 desc[i].mask = target_flags;
8032 if (desc[i].code == end)
8038 spe_init_builtins (void)
8040 tree endlink = void_list_node;
8041 tree puint_type_node = build_pointer_type (unsigned_type_node);
8042 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
8043 struct builtin_description *d;
8046 tree v2si_ftype_4_v2si
8047 = build_function_type
8048 (opaque_V2SI_type_node,
8049 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8050 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8051 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8052 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8055 tree v2sf_ftype_4_v2sf
8056 = build_function_type
8057 (opaque_V2SF_type_node,
8058 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8059 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8060 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8061 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8064 tree int_ftype_int_v2si_v2si
8065 = build_function_type
8067 tree_cons (NULL_TREE, integer_type_node,
8068 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8069 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8072 tree int_ftype_int_v2sf_v2sf
8073 = build_function_type
8075 tree_cons (NULL_TREE, integer_type_node,
8076 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8077 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8080 tree void_ftype_v2si_puint_int
8081 = build_function_type (void_type_node,
8082 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8083 tree_cons (NULL_TREE, puint_type_node,
8084 tree_cons (NULL_TREE,
8088 tree void_ftype_v2si_puint_char
8089 = build_function_type (void_type_node,
8090 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8091 tree_cons (NULL_TREE, puint_type_node,
8092 tree_cons (NULL_TREE,
8096 tree void_ftype_v2si_pv2si_int
8097 = build_function_type (void_type_node,
8098 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8099 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8100 tree_cons (NULL_TREE,
8104 tree void_ftype_v2si_pv2si_char
8105 = build_function_type (void_type_node,
8106 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8107 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8108 tree_cons (NULL_TREE,
8113 = build_function_type (void_type_node,
8114 tree_cons (NULL_TREE, integer_type_node, endlink));
8117 = build_function_type (integer_type_node, endlink);
8119 tree v2si_ftype_pv2si_int
8120 = build_function_type (opaque_V2SI_type_node,
8121 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8122 tree_cons (NULL_TREE, integer_type_node,
8125 tree v2si_ftype_puint_int
8126 = build_function_type (opaque_V2SI_type_node,
8127 tree_cons (NULL_TREE, puint_type_node,
8128 tree_cons (NULL_TREE, integer_type_node,
8131 tree v2si_ftype_pushort_int
8132 = build_function_type (opaque_V2SI_type_node,
8133 tree_cons (NULL_TREE, pushort_type_node,
8134 tree_cons (NULL_TREE, integer_type_node,
8137 tree v2si_ftype_signed_char
8138 = build_function_type (opaque_V2SI_type_node,
8139 tree_cons (NULL_TREE, signed_char_type_node,
8142 /* The initialization of the simple binary and unary builtins is
8143 done in rs6000_common_init_builtins, but we have to enable the
8144 mask bits here manually because we have run out of `target_flags'
8145 bits. We really need to redesign this mask business. */
8147 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8148 ARRAY_SIZE (bdesc_2arg),
8151 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8152 ARRAY_SIZE (bdesc_1arg),
8154 SPE_BUILTIN_EVSUBFUSIAAW);
8155 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8156 ARRAY_SIZE (bdesc_spe_predicates),
8157 SPE_BUILTIN_EVCMPEQ,
8158 SPE_BUILTIN_EVFSTSTLT);
8159 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8160 ARRAY_SIZE (bdesc_spe_evsel),
8161 SPE_BUILTIN_EVSEL_CMPGTS,
8162 SPE_BUILTIN_EVSEL_FSTSTEQ);
8164 (*lang_hooks.decls.pushdecl)
8165 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8166 opaque_V2SI_type_node));
8168 /* Initialize irregular SPE builtins. */
8170 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8171 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8172 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8173 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8174 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8175 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8176 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8177 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8178 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8179 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8180 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8181 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8182 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8183 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8184 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8185 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8186 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8187 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8190 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8191 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8192 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8193 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8194 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8195 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8196 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8197 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8198 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8199 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8200 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8201 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8202 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8203 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8204 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8205 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8206 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8207 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8208 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8209 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8210 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8211 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8214 d = (struct builtin_description *) bdesc_spe_predicates;
8215 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8219 switch (insn_data[d->icode].operand[1].mode)
8222 type = int_ftype_int_v2si_v2si;
8225 type = int_ftype_int_v2sf_v2sf;
8231 def_builtin (d->mask, d->name, type, d->code);
8234 /* Evsel predicates. */
8235 d = (struct builtin_description *) bdesc_spe_evsel;
8236 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8240 switch (insn_data[d->icode].operand[1].mode)
8243 type = v2si_ftype_4_v2si;
8246 type = v2sf_ftype_4_v2sf;
8252 def_builtin (d->mask, d->name, type, d->code);
8257 altivec_init_builtins (void)
8259 struct builtin_description *d;
8260 struct builtin_description_predicates *dp;
8264 tree pfloat_type_node = build_pointer_type (float_type_node);
8265 tree pint_type_node = build_pointer_type (integer_type_node);
8266 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8267 tree pchar_type_node = build_pointer_type (char_type_node);
8269 tree pvoid_type_node = build_pointer_type (void_type_node);
8271 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8272 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8273 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8274 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8276 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8278 tree int_ftype_opaque
8279 = build_function_type_list (integer_type_node,
8280 opaque_V4SI_type_node, NULL_TREE);
8282 tree opaque_ftype_opaque_int
8283 = build_function_type_list (opaque_V4SI_type_node,
8284 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8285 tree opaque_ftype_opaque_opaque_int
8286 = build_function_type_list (opaque_V4SI_type_node,
8287 opaque_V4SI_type_node, opaque_V4SI_type_node,
8288 integer_type_node, NULL_TREE);
8289 tree int_ftype_int_opaque_opaque
8290 = build_function_type_list (integer_type_node,
8291 integer_type_node, opaque_V4SI_type_node,
8292 opaque_V4SI_type_node, NULL_TREE);
8293 tree int_ftype_int_v4si_v4si
8294 = build_function_type_list (integer_type_node,
8295 integer_type_node, V4SI_type_node,
8296 V4SI_type_node, NULL_TREE);
8297 tree v4sf_ftype_pcfloat
8298 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8299 tree void_ftype_pfloat_v4sf
8300 = build_function_type_list (void_type_node,
8301 pfloat_type_node, V4SF_type_node, NULL_TREE);
8302 tree v4si_ftype_pcint
8303 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8304 tree void_ftype_pint_v4si
8305 = build_function_type_list (void_type_node,
8306 pint_type_node, V4SI_type_node, NULL_TREE);
8307 tree v8hi_ftype_pcshort
8308 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8309 tree void_ftype_pshort_v8hi
8310 = build_function_type_list (void_type_node,
8311 pshort_type_node, V8HI_type_node, NULL_TREE);
8312 tree v16qi_ftype_pcchar
8313 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8314 tree void_ftype_pchar_v16qi
8315 = build_function_type_list (void_type_node,
8316 pchar_type_node, V16QI_type_node, NULL_TREE);
8317 tree void_ftype_v4si
8318 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8319 tree v8hi_ftype_void
8320 = build_function_type (V8HI_type_node, void_list_node);
8321 tree void_ftype_void
8322 = build_function_type (void_type_node, void_list_node);
8324 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8326 tree opaque_ftype_long_pcvoid
8327 = build_function_type_list (opaque_V4SI_type_node,
8328 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8329 tree v16qi_ftype_long_pcvoid
8330 = build_function_type_list (V16QI_type_node,
8331 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8332 tree v8hi_ftype_long_pcvoid
8333 = build_function_type_list (V8HI_type_node,
8334 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8335 tree v4si_ftype_long_pcvoid
8336 = build_function_type_list (V4SI_type_node,
8337 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8339 tree void_ftype_opaque_long_pvoid
8340 = build_function_type_list (void_type_node,
8341 opaque_V4SI_type_node, long_integer_type_node,
8342 pvoid_type_node, NULL_TREE);
8343 tree void_ftype_v4si_long_pvoid
8344 = build_function_type_list (void_type_node,
8345 V4SI_type_node, long_integer_type_node,
8346 pvoid_type_node, NULL_TREE);
8347 tree void_ftype_v16qi_long_pvoid
8348 = build_function_type_list (void_type_node,
8349 V16QI_type_node, long_integer_type_node,
8350 pvoid_type_node, NULL_TREE);
8351 tree void_ftype_v8hi_long_pvoid
8352 = build_function_type_list (void_type_node,
8353 V8HI_type_node, long_integer_type_node,
8354 pvoid_type_node, NULL_TREE);
8355 tree int_ftype_int_v8hi_v8hi
8356 = build_function_type_list (integer_type_node,
8357 integer_type_node, V8HI_type_node,
8358 V8HI_type_node, NULL_TREE);
8359 tree int_ftype_int_v16qi_v16qi
8360 = build_function_type_list (integer_type_node,
8361 integer_type_node, V16QI_type_node,
8362 V16QI_type_node, NULL_TREE);
8363 tree int_ftype_int_v4sf_v4sf
8364 = build_function_type_list (integer_type_node,
8365 integer_type_node, V4SF_type_node,
8366 V4SF_type_node, NULL_TREE);
8367 tree v4si_ftype_v4si
8368 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8369 tree v8hi_ftype_v8hi
8370 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8371 tree v16qi_ftype_v16qi
8372 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8373 tree v4sf_ftype_v4sf
8374 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8375 tree void_ftype_pcvoid_int_int
8376 = build_function_type_list (void_type_node,
8377 pcvoid_type_node, integer_type_node,
8378 integer_type_node, NULL_TREE);
8380 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8381 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8382 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8383 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8384 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8385 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8386 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8387 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8388 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8389 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8390 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8391 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8392 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8393 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8394 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8395 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8396 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8397 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8398 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8399 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8400 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8401 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8402 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8403 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8404 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8405 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8406 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8407 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8408 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8409 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8410 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8411 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8412 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8413 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8414 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8415 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8416 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8417 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8418 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8419 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
8420 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
8421 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
8422 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
8423 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
8424 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
8425 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
8427 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
8429 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
8430 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
8431 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
8432 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
8433 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
8434 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
8435 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
8436 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
8437 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
8438 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8440 /* Add the DST variants. */
8441 d = (struct builtin_description *) bdesc_dst;
8442 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8443 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8445 /* Initialize the predicates. */
8446 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8447 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8449 enum machine_mode mode1;
8451 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8452 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8457 mode1 = insn_data[dp->icode].operand[1].mode;
8462 type = int_ftype_int_opaque_opaque;
8465 type = int_ftype_int_v4si_v4si;
8468 type = int_ftype_int_v8hi_v8hi;
8471 type = int_ftype_int_v16qi_v16qi;
8474 type = int_ftype_int_v4sf_v4sf;
8480 def_builtin (dp->mask, dp->name, type, dp->code);
8483 /* Initialize the abs* operators. */
8484 d = (struct builtin_description *) bdesc_abs;
8485 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8487 enum machine_mode mode0;
8490 mode0 = insn_data[d->icode].operand[0].mode;
8495 type = v4si_ftype_v4si;
8498 type = v8hi_ftype_v8hi;
8501 type = v16qi_ftype_v16qi;
8504 type = v4sf_ftype_v4sf;
8510 def_builtin (d->mask, d->name, type, d->code);
8517 /* Initialize target builtin that implements
8518 targetm.vectorize.builtin_mask_for_load. */
8520 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8521 v16qi_ftype_long_pcvoid,
8522 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8524 tree_cons (get_identifier ("const"),
8525 NULL_TREE, NULL_TREE));
8526 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8527 altivec_builtin_mask_for_load = decl;
8530 /* Access to the vec_init patterns. */
8531 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
8532 integer_type_node, integer_type_node,
8533 integer_type_node, NULL_TREE);
8534 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
8535 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
8537 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
8538 short_integer_type_node,
8539 short_integer_type_node,
8540 short_integer_type_node,
8541 short_integer_type_node,
8542 short_integer_type_node,
8543 short_integer_type_node,
8544 short_integer_type_node, NULL_TREE);
8545 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
8546 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
8548 ftype = build_function_type_list (V16QI_type_node, char_type_node,
8549 char_type_node, char_type_node,
8550 char_type_node, char_type_node,
8551 char_type_node, char_type_node,
8552 char_type_node, char_type_node,
8553 char_type_node, char_type_node,
8554 char_type_node, char_type_node,
8555 char_type_node, char_type_node,
8556 char_type_node, NULL_TREE);
8557 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
8558 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
8560 ftype = build_function_type_list (V4SF_type_node, float_type_node,
8561 float_type_node, float_type_node,
8562 float_type_node, NULL_TREE);
8563 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
8564 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
8566 /* Access to the vec_set patterns. */
8567 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
8569 integer_type_node, NULL_TREE);
8570 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
8571 ALTIVEC_BUILTIN_VEC_SET_V4SI);
8573 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
8575 integer_type_node, NULL_TREE);
8576 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
8577 ALTIVEC_BUILTIN_VEC_SET_V8HI);
8579 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
8581 integer_type_node, NULL_TREE);
8582 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
8583 ALTIVEC_BUILTIN_VEC_SET_V16QI);
8585 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
8587 integer_type_node, NULL_TREE);
8588 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
8589 ALTIVEC_BUILTIN_VEC_SET_V4SF);
8591 /* Access to the vec_extract patterns. */
8592 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
8593 integer_type_node, NULL_TREE);
8594 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
8595 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
8597 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
8598 integer_type_node, NULL_TREE);
8599 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
8600 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
8602 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
8603 integer_type_node, NULL_TREE);
8604 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
8605 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
8607 ftype = build_function_type_list (float_type_node, V4SF_type_node,
8608 integer_type_node, NULL_TREE);
8609 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
8610 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
8614 rs6000_common_init_builtins (void)
8616 struct builtin_description *d;
8619 tree v4sf_ftype_v4sf_v4sf_v16qi
8620 = build_function_type_list (V4SF_type_node,
8621 V4SF_type_node, V4SF_type_node,
8622 V16QI_type_node, NULL_TREE);
8623 tree v4si_ftype_v4si_v4si_v16qi
8624 = build_function_type_list (V4SI_type_node,
8625 V4SI_type_node, V4SI_type_node,
8626 V16QI_type_node, NULL_TREE);
8627 tree v8hi_ftype_v8hi_v8hi_v16qi
8628 = build_function_type_list (V8HI_type_node,
8629 V8HI_type_node, V8HI_type_node,
8630 V16QI_type_node, NULL_TREE);
8631 tree v16qi_ftype_v16qi_v16qi_v16qi
8632 = build_function_type_list (V16QI_type_node,
8633 V16QI_type_node, V16QI_type_node,
8634 V16QI_type_node, NULL_TREE);
8636 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8638 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8639 tree v16qi_ftype_int
8640 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8641 tree v8hi_ftype_v16qi
8642 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8643 tree v4sf_ftype_v4sf
8644 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8646 tree v2si_ftype_v2si_v2si
8647 = build_function_type_list (opaque_V2SI_type_node,
8648 opaque_V2SI_type_node,
8649 opaque_V2SI_type_node, NULL_TREE);
8651 tree v2sf_ftype_v2sf_v2sf
8652 = build_function_type_list (opaque_V2SF_type_node,
8653 opaque_V2SF_type_node,
8654 opaque_V2SF_type_node, NULL_TREE);
8656 tree v2si_ftype_int_int
8657 = build_function_type_list (opaque_V2SI_type_node,
8658 integer_type_node, integer_type_node,
8661 tree opaque_ftype_opaque
8662 = build_function_type_list (opaque_V4SI_type_node,
8663 opaque_V4SI_type_node, NULL_TREE);
8665 tree v2si_ftype_v2si
8666 = build_function_type_list (opaque_V2SI_type_node,
8667 opaque_V2SI_type_node, NULL_TREE);
8669 tree v2sf_ftype_v2sf
8670 = build_function_type_list (opaque_V2SF_type_node,
8671 opaque_V2SF_type_node, NULL_TREE);
8673 tree v2sf_ftype_v2si
8674 = build_function_type_list (opaque_V2SF_type_node,
8675 opaque_V2SI_type_node, NULL_TREE);
8677 tree v2si_ftype_v2sf
8678 = build_function_type_list (opaque_V2SI_type_node,
8679 opaque_V2SF_type_node, NULL_TREE);
8681 tree v2si_ftype_v2si_char
8682 = build_function_type_list (opaque_V2SI_type_node,
8683 opaque_V2SI_type_node,
8684 char_type_node, NULL_TREE);
8686 tree v2si_ftype_int_char
8687 = build_function_type_list (opaque_V2SI_type_node,
8688 integer_type_node, char_type_node, NULL_TREE);
8690 tree v2si_ftype_char
8691 = build_function_type_list (opaque_V2SI_type_node,
8692 char_type_node, NULL_TREE);
8694 tree int_ftype_int_int
8695 = build_function_type_list (integer_type_node,
8696 integer_type_node, integer_type_node,
8699 tree opaque_ftype_opaque_opaque
8700 = build_function_type_list (opaque_V4SI_type_node,
8701 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
8702 tree v4si_ftype_v4si_v4si
8703 = build_function_type_list (V4SI_type_node,
8704 V4SI_type_node, V4SI_type_node, NULL_TREE);
8705 tree v4sf_ftype_v4si_int
8706 = build_function_type_list (V4SF_type_node,
8707 V4SI_type_node, integer_type_node, NULL_TREE);
8708 tree v4si_ftype_v4sf_int
8709 = build_function_type_list (V4SI_type_node,
8710 V4SF_type_node, integer_type_node, NULL_TREE);
8711 tree v4si_ftype_v4si_int
8712 = build_function_type_list (V4SI_type_node,
8713 V4SI_type_node, integer_type_node, NULL_TREE);
8714 tree v8hi_ftype_v8hi_int
8715 = build_function_type_list (V8HI_type_node,
8716 V8HI_type_node, integer_type_node, NULL_TREE);
8717 tree v16qi_ftype_v16qi_int
8718 = build_function_type_list (V16QI_type_node,
8719 V16QI_type_node, integer_type_node, NULL_TREE);
8720 tree v16qi_ftype_v16qi_v16qi_int
8721 = build_function_type_list (V16QI_type_node,
8722 V16QI_type_node, V16QI_type_node,
8723 integer_type_node, NULL_TREE);
8724 tree v8hi_ftype_v8hi_v8hi_int
8725 = build_function_type_list (V8HI_type_node,
8726 V8HI_type_node, V8HI_type_node,
8727 integer_type_node, NULL_TREE);
8728 tree v4si_ftype_v4si_v4si_int
8729 = build_function_type_list (V4SI_type_node,
8730 V4SI_type_node, V4SI_type_node,
8731 integer_type_node, NULL_TREE);
8732 tree v4sf_ftype_v4sf_v4sf_int
8733 = build_function_type_list (V4SF_type_node,
8734 V4SF_type_node, V4SF_type_node,
8735 integer_type_node, NULL_TREE);
8736 tree v4sf_ftype_v4sf_v4sf
8737 = build_function_type_list (V4SF_type_node,
8738 V4SF_type_node, V4SF_type_node, NULL_TREE);
8739 tree opaque_ftype_opaque_opaque_opaque
8740 = build_function_type_list (opaque_V4SI_type_node,
8741 opaque_V4SI_type_node, opaque_V4SI_type_node,
8742 opaque_V4SI_type_node, NULL_TREE);
8743 tree v4sf_ftype_v4sf_v4sf_v4si
8744 = build_function_type_list (V4SF_type_node,
8745 V4SF_type_node, V4SF_type_node,
8746 V4SI_type_node, NULL_TREE);
8747 tree v4sf_ftype_v4sf_v4sf_v4sf
8748 = build_function_type_list (V4SF_type_node,
8749 V4SF_type_node, V4SF_type_node,
8750 V4SF_type_node, NULL_TREE);
8751 tree v4si_ftype_v4si_v4si_v4si
8752 = build_function_type_list (V4SI_type_node,
8753 V4SI_type_node, V4SI_type_node,
8754 V4SI_type_node, NULL_TREE);
8755 tree v8hi_ftype_v8hi_v8hi
8756 = build_function_type_list (V8HI_type_node,
8757 V8HI_type_node, V8HI_type_node, NULL_TREE);
8758 tree v8hi_ftype_v8hi_v8hi_v8hi
8759 = build_function_type_list (V8HI_type_node,
8760 V8HI_type_node, V8HI_type_node,
8761 V8HI_type_node, NULL_TREE);
8762 tree v4si_ftype_v8hi_v8hi_v4si
8763 = build_function_type_list (V4SI_type_node,
8764 V8HI_type_node, V8HI_type_node,
8765 V4SI_type_node, NULL_TREE);
8766 tree v4si_ftype_v16qi_v16qi_v4si
8767 = build_function_type_list (V4SI_type_node,
8768 V16QI_type_node, V16QI_type_node,
8769 V4SI_type_node, NULL_TREE);
8770 tree v16qi_ftype_v16qi_v16qi
8771 = build_function_type_list (V16QI_type_node,
8772 V16QI_type_node, V16QI_type_node, NULL_TREE);
8773 tree v4si_ftype_v4sf_v4sf
8774 = build_function_type_list (V4SI_type_node,
8775 V4SF_type_node, V4SF_type_node, NULL_TREE);
8776 tree v8hi_ftype_v16qi_v16qi
8777 = build_function_type_list (V8HI_type_node,
8778 V16QI_type_node, V16QI_type_node, NULL_TREE);
8779 tree v4si_ftype_v8hi_v8hi
8780 = build_function_type_list (V4SI_type_node,
8781 V8HI_type_node, V8HI_type_node, NULL_TREE);
8782 tree v8hi_ftype_v4si_v4si
8783 = build_function_type_list (V8HI_type_node,
8784 V4SI_type_node, V4SI_type_node, NULL_TREE);
8785 tree v16qi_ftype_v8hi_v8hi
8786 = build_function_type_list (V16QI_type_node,
8787 V8HI_type_node, V8HI_type_node, NULL_TREE);
8788 tree v4si_ftype_v16qi_v4si
8789 = build_function_type_list (V4SI_type_node,
8790 V16QI_type_node, V4SI_type_node, NULL_TREE);
8791 tree v4si_ftype_v16qi_v16qi
8792 = build_function_type_list (V4SI_type_node,
8793 V16QI_type_node, V16QI_type_node, NULL_TREE);
8794 tree v4si_ftype_v8hi_v4si
8795 = build_function_type_list (V4SI_type_node,
8796 V8HI_type_node, V4SI_type_node, NULL_TREE);
8797 tree v4si_ftype_v8hi
8798 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8799 tree int_ftype_v4si_v4si
8800 = build_function_type_list (integer_type_node,
8801 V4SI_type_node, V4SI_type_node, NULL_TREE);
8802 tree int_ftype_v4sf_v4sf
8803 = build_function_type_list (integer_type_node,
8804 V4SF_type_node, V4SF_type_node, NULL_TREE);
8805 tree int_ftype_v16qi_v16qi
8806 = build_function_type_list (integer_type_node,
8807 V16QI_type_node, V16QI_type_node, NULL_TREE);
8808 tree int_ftype_v8hi_v8hi
8809 = build_function_type_list (integer_type_node,
8810 V8HI_type_node, V8HI_type_node, NULL_TREE);
8812 /* Add the simple ternary operators. */
8813 d = (struct builtin_description *) bdesc_3arg;
8814 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8816 enum machine_mode mode0, mode1, mode2, mode3;
8818 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8819 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8830 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8833 mode0 = insn_data[d->icode].operand[0].mode;
8834 mode1 = insn_data[d->icode].operand[1].mode;
8835 mode2 = insn_data[d->icode].operand[2].mode;
8836 mode3 = insn_data[d->icode].operand[3].mode;
8839 /* When all four are of the same mode. */
8840 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8845 type = opaque_ftype_opaque_opaque_opaque;
8848 type = v4si_ftype_v4si_v4si_v4si;
8851 type = v4sf_ftype_v4sf_v4sf_v4sf;
8854 type = v8hi_ftype_v8hi_v8hi_v8hi;
8857 type = v16qi_ftype_v16qi_v16qi_v16qi;
8863 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8868 type = v4si_ftype_v4si_v4si_v16qi;
8871 type = v4sf_ftype_v4sf_v4sf_v16qi;
8874 type = v8hi_ftype_v8hi_v8hi_v16qi;
8877 type = v16qi_ftype_v16qi_v16qi_v16qi;
8883 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8884 && mode3 == V4SImode)
8885 type = v4si_ftype_v16qi_v16qi_v4si;
8886 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8887 && mode3 == V4SImode)
8888 type = v4si_ftype_v8hi_v8hi_v4si;
8889 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8890 && mode3 == V4SImode)
8891 type = v4sf_ftype_v4sf_v4sf_v4si;
8893 /* vchar, vchar, vchar, 4 bit literal. */
8894 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8896 type = v16qi_ftype_v16qi_v16qi_int;
8898 /* vshort, vshort, vshort, 4 bit literal. */
8899 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8901 type = v8hi_ftype_v8hi_v8hi_int;
8903 /* vint, vint, vint, 4 bit literal. */
8904 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8906 type = v4si_ftype_v4si_v4si_int;
8908 /* vfloat, vfloat, vfloat, 4 bit literal. */
8909 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8911 type = v4sf_ftype_v4sf_v4sf_int;
8916 def_builtin (d->mask, d->name, type, d->code);
8919 /* Add the simple binary operators. */
8920 d = (struct builtin_description *) bdesc_2arg;
8921 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8923 enum machine_mode mode0, mode1, mode2;
8925 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8926 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8936 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8939 mode0 = insn_data[d->icode].operand[0].mode;
8940 mode1 = insn_data[d->icode].operand[1].mode;
8941 mode2 = insn_data[d->icode].operand[2].mode;
8944 /* When all three operands are of the same mode. */
8945 if (mode0 == mode1 && mode1 == mode2)
8950 type = opaque_ftype_opaque_opaque;
8953 type = v4sf_ftype_v4sf_v4sf;
8956 type = v4si_ftype_v4si_v4si;
8959 type = v16qi_ftype_v16qi_v16qi;
8962 type = v8hi_ftype_v8hi_v8hi;
8965 type = v2si_ftype_v2si_v2si;
8968 type = v2sf_ftype_v2sf_v2sf;
8971 type = int_ftype_int_int;
8978 /* A few other combos we really don't want to do manually. */
8980 /* vint, vfloat, vfloat. */
8981 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8982 type = v4si_ftype_v4sf_v4sf;
8984 /* vshort, vchar, vchar. */
8985 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8986 type = v8hi_ftype_v16qi_v16qi;
8988 /* vint, vshort, vshort. */
8989 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8990 type = v4si_ftype_v8hi_v8hi;
8992 /* vshort, vint, vint. */
8993 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8994 type = v8hi_ftype_v4si_v4si;
8996 /* vchar, vshort, vshort. */
8997 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8998 type = v16qi_ftype_v8hi_v8hi;
9000 /* vint, vchar, vint. */
9001 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
9002 type = v4si_ftype_v16qi_v4si;
9004 /* vint, vchar, vchar. */
9005 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
9006 type = v4si_ftype_v16qi_v16qi;
9008 /* vint, vshort, vint. */
9009 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
9010 type = v4si_ftype_v8hi_v4si;
9012 /* vint, vint, 5 bit literal. */
9013 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
9014 type = v4si_ftype_v4si_int;
9016 /* vshort, vshort, 5 bit literal. */
9017 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
9018 type = v8hi_ftype_v8hi_int;
9020 /* vchar, vchar, 5 bit literal. */
9021 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
9022 type = v16qi_ftype_v16qi_int;
9024 /* vfloat, vint, 5 bit literal. */
9025 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
9026 type = v4sf_ftype_v4si_int;
9028 /* vint, vfloat, 5 bit literal. */
9029 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
9030 type = v4si_ftype_v4sf_int;
9032 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
9033 type = v2si_ftype_int_int;
9035 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
9036 type = v2si_ftype_v2si_char;
9038 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
9039 type = v2si_ftype_int_char;
9044 gcc_assert (mode0 == SImode);
9048 type = int_ftype_v4si_v4si;
9051 type = int_ftype_v4sf_v4sf;
9054 type = int_ftype_v16qi_v16qi;
9057 type = int_ftype_v8hi_v8hi;
9064 def_builtin (d->mask, d->name, type, d->code);
9067 /* Add the simple unary operators. */
9068 d = (struct builtin_description *) bdesc_1arg;
9069 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9071 enum machine_mode mode0, mode1;
9073 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9074 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9083 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9086 mode0 = insn_data[d->icode].operand[0].mode;
9087 mode1 = insn_data[d->icode].operand[1].mode;
9090 if (mode0 == V4SImode && mode1 == QImode)
9091 type = v4si_ftype_int;
9092 else if (mode0 == V8HImode && mode1 == QImode)
9093 type = v8hi_ftype_int;
9094 else if (mode0 == V16QImode && mode1 == QImode)
9095 type = v16qi_ftype_int;
9096 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9097 type = opaque_ftype_opaque;
9098 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9099 type = v4sf_ftype_v4sf;
9100 else if (mode0 == V8HImode && mode1 == V16QImode)
9101 type = v8hi_ftype_v16qi;
9102 else if (mode0 == V4SImode && mode1 == V8HImode)
9103 type = v4si_ftype_v8hi;
9104 else if (mode0 == V2SImode && mode1 == V2SImode)
9105 type = v2si_ftype_v2si;
9106 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9107 type = v2sf_ftype_v2sf;
9108 else if (mode0 == V2SFmode && mode1 == V2SImode)
9109 type = v2sf_ftype_v2si;
9110 else if (mode0 == V2SImode && mode1 == V2SFmode)
9111 type = v2si_ftype_v2sf;
9112 else if (mode0 == V2SImode && mode1 == QImode)
9113 type = v2si_ftype_char;
9117 def_builtin (d->mask, d->name, type, d->code);
9122 rs6000_init_libfuncs (void)
9124 if (!TARGET_HARD_FLOAT)
9127 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
9128 && !TARGET_POWER2 && !TARGET_POWERPC)
9130 /* AIX library routines for float->int conversion. */
9131 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9132 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9133 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9134 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9137 if (!TARGET_IEEEQUAD)
9138 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9139 if (!TARGET_XL_COMPAT)
9141 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9142 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9143 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9144 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9148 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9149 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9150 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9151 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9155 /* 32-bit SVR4 quad floating point routines. */
9157 set_optab_libfunc (add_optab, TFmode, "_q_add");
9158 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9159 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9160 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9161 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9162 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9163 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9165 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9166 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9167 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9168 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9169 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9170 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9172 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9173 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9174 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9175 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9176 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9177 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9178 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9179 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9184 /* Expand a block clear operation, and return 1 if successful. Return 0
9185 if we should let the compiler generate normal code.
9187 operands[0] is the destination
9188 operands[1] is the length
9189 operands[3] is the alignment */
9192 expand_block_clear (rtx operands[])
9194 rtx orig_dest = operands[0];
9195 rtx bytes_rtx = operands[1];
9196 rtx align_rtx = operands[3];
9197 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9198 HOST_WIDE_INT align;
9199 HOST_WIDE_INT bytes;
9204 /* If this is not a fixed size move, just call memcpy */
9208 /* This must be a fixed size alignment */
9209 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9210 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9212 /* Anything to clear? */
9213 bytes = INTVAL (bytes_rtx);
9217 /* Use the builtin memset after a point, to avoid huge code bloat.
9218 When optimize_size, avoid any significant code bloat; calling
9219 memset is about 4 instructions, so allow for one instruction to
9220 load zero and three to do clearing. */
9221 if (TARGET_ALTIVEC && align >= 128)
9223 else if (TARGET_POWERPC64 && align >= 32)
9228 if (optimize_size && bytes > 3 * clear_step)
9230 if (! optimize_size && bytes > 8 * clear_step)
9233 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9235 enum machine_mode mode = BLKmode;
9238 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9243 else if (bytes >= 8 && TARGET_POWERPC64
9244 /* 64-bit loads and stores require word-aligned
9246 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9251 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9252 { /* move 4 bytes */
9256 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9257 { /* move 2 bytes */
9261 else /* move 1 byte at a time */
9267 dest = adjust_address (orig_dest, mode, offset);
9269 emit_move_insn (dest, CONST0_RTX (mode));
9276 /* Expand a block move operation, and return 1 if successful. Return 0
9277 if we should let the compiler generate normal code.
9279 operands[0] is the destination
9280 operands[1] is the source
9281 operands[2] is the length
9282 operands[3] is the alignment */
9284 #define MAX_MOVE_REG 4
9287 expand_block_move (rtx operands[])
9289 rtx orig_dest = operands[0];
9290 rtx orig_src = operands[1];
9291 rtx bytes_rtx = operands[2];
9292 rtx align_rtx = operands[3];
9293 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9298 rtx stores[MAX_MOVE_REG];
9301 /* If this is not a fixed size move, just call memcpy */
9305 /* This must be a fixed size alignment */
9306 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9307 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9309 /* Anything to move? */
9310 bytes = INTVAL (bytes_rtx);
9314 /* store_one_arg depends on expand_block_move to handle at least the size of
9315 reg_parm_stack_space. */
9316 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9319 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9322 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9323 rtx (*mov) (rtx, rtx);
9325 enum machine_mode mode = BLKmode;
9328 /* Altivec first, since it will be faster than a string move
9329 when it applies, and usually not significantly larger. */
9330 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9334 gen_func.mov = gen_movv4si;
9336 else if (TARGET_STRING
9337 && bytes > 24 /* move up to 32 bytes at a time */
9345 && ! fixed_regs[12])
9347 move_bytes = (bytes > 32) ? 32 : bytes;
9348 gen_func.movmemsi = gen_movmemsi_8reg;
9350 else if (TARGET_STRING
9351 && bytes > 16 /* move up to 24 bytes at a time */
9357 && ! fixed_regs[10])
9359 move_bytes = (bytes > 24) ? 24 : bytes;
9360 gen_func.movmemsi = gen_movmemsi_6reg;
9362 else if (TARGET_STRING
9363 && bytes > 8 /* move up to 16 bytes at a time */
9369 move_bytes = (bytes > 16) ? 16 : bytes;
9370 gen_func.movmemsi = gen_movmemsi_4reg;
9372 else if (bytes >= 8 && TARGET_POWERPC64
9373 /* 64-bit loads and stores require word-aligned
9375 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9379 gen_func.mov = gen_movdi;
9381 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9382 { /* move up to 8 bytes at a time */
9383 move_bytes = (bytes > 8) ? 8 : bytes;
9384 gen_func.movmemsi = gen_movmemsi_2reg;
9386 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9387 { /* move 4 bytes */
9390 gen_func.mov = gen_movsi;
9392 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9393 { /* move 2 bytes */
9396 gen_func.mov = gen_movhi;
9398 else if (TARGET_STRING && bytes > 1)
9399 { /* move up to 4 bytes at a time */
9400 move_bytes = (bytes > 4) ? 4 : bytes;
9401 gen_func.movmemsi = gen_movmemsi_1reg;
9403 else /* move 1 byte at a time */
9407 gen_func.mov = gen_movqi;
9410 src = adjust_address (orig_src, mode, offset);
9411 dest = adjust_address (orig_dest, mode, offset);
9413 if (mode != BLKmode)
9415 rtx tmp_reg = gen_reg_rtx (mode);
9417 emit_insn ((*gen_func.mov) (tmp_reg, src));
9418 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9421 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9424 for (i = 0; i < num_reg; i++)
9425 emit_insn (stores[i]);
9429 if (mode == BLKmode)
9431 /* Move the address into scratch registers. The movmemsi
9432 patterns require zero offset. */
9433 if (!REG_P (XEXP (src, 0)))
9435 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9436 src = replace_equiv_address (src, src_reg);
9438 set_mem_size (src, GEN_INT (move_bytes));
9440 if (!REG_P (XEXP (dest, 0)))
9442 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9443 dest = replace_equiv_address (dest, dest_reg);
9445 set_mem_size (dest, GEN_INT (move_bytes));
9447 emit_insn ((*gen_func.movmemsi) (dest, src,
9448 GEN_INT (move_bytes & 31),
9457 /* Return a string to perform a load_multiple operation.
9458 operands[0] is the vector.
9459 operands[1] is the source address.
9460 operands[2] is the first destination register. */
9463 rs6000_output_load_multiple (rtx operands[3])
9465 /* We have to handle the case where the pseudo used to contain the address
9466 is assigned to one of the output registers. */
9468 int words = XVECLEN (operands[0], 0);
9471 if (XVECLEN (operands[0], 0) == 1)
9472 return "{l|lwz} %2,0(%1)";
9474 for (i = 0; i < words; i++)
9475 if (refers_to_regno_p (REGNO (operands[2]) + i,
9476 REGNO (operands[2]) + i + 1, operands[1], 0))
9480 xop[0] = GEN_INT (4 * (words-1));
9481 xop[1] = operands[1];
9482 xop[2] = operands[2];
9483 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9488 xop[0] = GEN_INT (4 * (words-1));
9489 xop[1] = operands[1];
9490 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9491 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9496 for (j = 0; j < words; j++)
9499 xop[0] = GEN_INT (j * 4);
9500 xop[1] = operands[1];
9501 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9502 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9504 xop[0] = GEN_INT (i * 4);
9505 xop[1] = operands[1];
9506 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9511 return "{lsi|lswi} %2,%1,%N0";
9515 /* A validation routine: say whether CODE, a condition code, and MODE
9516 match. The other alternatives either don't make sense or should
9517 never be generated. */
9520 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9522 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
9523 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9524 && GET_MODE_CLASS (mode) == MODE_CC);
9526 /* These don't make sense. */
9527 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
9528 || mode != CCUNSmode);
9530 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
9531 || mode == CCUNSmode);
9533 gcc_assert (mode == CCFPmode
9534 || (code != ORDERED && code != UNORDERED
9535 && code != UNEQ && code != LTGT
9536 && code != UNGT && code != UNLT
9537 && code != UNGE && code != UNLE));
9539 /* These should never be generated except for
9540 flag_finite_math_only. */
9541 gcc_assert (mode != CCFPmode
9542 || flag_finite_math_only
9543 || (code != LE && code != GE
9544 && code != UNEQ && code != LTGT
9545 && code != UNGT && code != UNLT));
9547 /* These are invalid; the information is not there. */
9548 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
9552 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9553 mask required to convert the result of a rotate insn into a shift
9554 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9557 includes_lshift_p (rtx shiftop, rtx andop)
9559 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9561 shift_mask <<= INTVAL (shiftop);
9563 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9566 /* Similar, but for right shift. */
9569 includes_rshift_p (rtx shiftop, rtx andop)
9571 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9573 shift_mask >>= INTVAL (shiftop);
9575 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9578 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9579 to perform a left shift. It must have exactly SHIFTOP least
9580 significant 0's, then one or more 1's, then zero or more 0's. */
9583 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9585 if (GET_CODE (andop) == CONST_INT)
9587 HOST_WIDE_INT c, lsb, shift_mask;
9590 if (c == 0 || c == ~0)
9594 shift_mask <<= INTVAL (shiftop);
9596 /* Find the least significant one bit. */
9599 /* It must coincide with the LSB of the shift mask. */
9600 if (-lsb != shift_mask)
9603 /* Invert to look for the next transition (if any). */
9606 /* Remove the low group of ones (originally low group of zeros). */
9609 /* Again find the lsb, and check we have all 1's above. */
9613 else if (GET_CODE (andop) == CONST_DOUBLE
9614 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9616 HOST_WIDE_INT low, high, lsb;
9617 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9619 low = CONST_DOUBLE_LOW (andop);
9620 if (HOST_BITS_PER_WIDE_INT < 64)
9621 high = CONST_DOUBLE_HIGH (andop);
9623 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9624 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9627 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9629 shift_mask_high = ~0;
9630 if (INTVAL (shiftop) > 32)
9631 shift_mask_high <<= INTVAL (shiftop) - 32;
9635 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9642 return high == -lsb;
9645 shift_mask_low = ~0;
9646 shift_mask_low <<= INTVAL (shiftop);
9650 if (-lsb != shift_mask_low)
9653 if (HOST_BITS_PER_WIDE_INT < 64)
9658 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9661 return high == -lsb;
9665 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9671 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9672 to perform a left shift. It must have SHIFTOP or more least
9673 significant 0's, with the remainder of the word 1's. */
9676 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9678 if (GET_CODE (andop) == CONST_INT)
9680 HOST_WIDE_INT c, lsb, shift_mask;
9683 shift_mask <<= INTVAL (shiftop);
9686 /* Find the least significant one bit. */
9689 /* It must be covered by the shift mask.
9690 This test also rejects c == 0. */
9691 if ((lsb & shift_mask) == 0)
9694 /* Check we have all 1's above the transition, and reject all 1's. */
9695 return c == -lsb && lsb != 1;
9697 else if (GET_CODE (andop) == CONST_DOUBLE
9698 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9700 HOST_WIDE_INT low, lsb, shift_mask_low;
9702 low = CONST_DOUBLE_LOW (andop);
9704 if (HOST_BITS_PER_WIDE_INT < 64)
9706 HOST_WIDE_INT high, shift_mask_high;
9708 high = CONST_DOUBLE_HIGH (andop);
9712 shift_mask_high = ~0;
9713 if (INTVAL (shiftop) > 32)
9714 shift_mask_high <<= INTVAL (shiftop) - 32;
9718 if ((lsb & shift_mask_high) == 0)
9721 return high == -lsb;
9727 shift_mask_low = ~0;
9728 shift_mask_low <<= INTVAL (shiftop);
9732 if ((lsb & shift_mask_low) == 0)
9735 return low == -lsb && lsb != 1;
9741 /* Return 1 if operands will generate a valid arguments to rlwimi
9742 instruction for insert with right shift in 64-bit mode. The mask may
9743 not start on the first bit or stop on the last bit because wrap-around
9744 effects of instruction do not correspond to semantics of RTL insn. */
9747 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9749 if (INTVAL (startop) < 64
9750 && INTVAL (startop) > 32
9751 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9752 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9753 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9754 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9755 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9761 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9762 for lfq and stfq insns iff the registers are hard registers. */
9765 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
9767 /* We might have been passed a SUBREG. */
9768 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
9771 /* We might have been passed non floating point registers. */
9772 if (!FP_REGNO_P (REGNO (reg1))
9773 || !FP_REGNO_P (REGNO (reg2)))
9776 return (REGNO (reg1) == REGNO (reg2) - 1);
9779 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9780 addr1 and addr2 must be in consecutive memory locations
9781 (addr2 == addr1 + 8). */
9784 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
9787 unsigned int reg1, reg2;
9788 int offset1, offset2;
9790 /* The mems cannot be volatile. */
9791 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9794 addr1 = XEXP (mem1, 0);
9795 addr2 = XEXP (mem2, 0);
9797 /* Extract an offset (if used) from the first addr. */
9798 if (GET_CODE (addr1) == PLUS)
9800 /* If not a REG, return zero. */
9801 if (GET_CODE (XEXP (addr1, 0)) != REG)
9805 reg1 = REGNO (XEXP (addr1, 0));
9806 /* The offset must be constant! */
9807 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
9809 offset1 = INTVAL (XEXP (addr1, 1));
9812 else if (GET_CODE (addr1) != REG)
9816 reg1 = REGNO (addr1);
9817 /* This was a simple (mem (reg)) expression. Offset is 0. */
9821 /* And now for the second addr. */
9822 if (GET_CODE (addr2) == PLUS)
9824 /* If not a REG, return zero. */
9825 if (GET_CODE (XEXP (addr2, 0)) != REG)
9829 reg2 = REGNO (XEXP (addr2, 0));
9830 /* The offset must be constant. */
9831 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9833 offset2 = INTVAL (XEXP (addr2, 1));
9836 else if (GET_CODE (addr2) != REG)
9840 reg2 = REGNO (addr2);
9841 /* This was a simple (mem (reg)) expression. Offset is 0. */
9845 /* Both of these must have the same base register. */
9849 /* The offset for the second addr must be 8 more than the first addr. */
9850 if (offset2 != offset1 + 8)
9853 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9858 /* Return the register class of a scratch register needed to copy IN into
9859 or out of a register in CLASS in MODE. If it can be done directly,
9860 NO_REGS is returned. */
9863 rs6000_secondary_reload_class (enum reg_class class,
9864 enum machine_mode mode ATTRIBUTE_UNUSED,
9869 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9871 && MACHOPIC_INDIRECT
9875 /* We cannot copy a symbolic operand directly into anything
9876 other than BASE_REGS for TARGET_ELF. So indicate that a
9877 register from BASE_REGS is needed as an intermediate
9880 On Darwin, pic addresses require a load from memory, which
9881 needs a base register. */
9882 if (class != BASE_REGS
9883 && (GET_CODE (in) == SYMBOL_REF
9884 || GET_CODE (in) == HIGH
9885 || GET_CODE (in) == LABEL_REF
9886 || GET_CODE (in) == CONST))
9890 if (GET_CODE (in) == REG)
9893 if (regno >= FIRST_PSEUDO_REGISTER)
9895 regno = true_regnum (in);
9896 if (regno >= FIRST_PSEUDO_REGISTER)
9900 else if (GET_CODE (in) == SUBREG)
9902 regno = true_regnum (in);
9903 if (regno >= FIRST_PSEUDO_REGISTER)
9909 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9911 if (class == GENERAL_REGS || class == BASE_REGS
9912 || (regno >= 0 && INT_REGNO_P (regno)))
9915 /* Constants, memory, and FP registers can go into FP registers. */
9916 if ((regno == -1 || FP_REGNO_P (regno))
9917 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
9920 /* Memory, and AltiVec registers can go into AltiVec registers. */
9921 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
9922 && class == ALTIVEC_REGS)
9925 /* We can copy among the CR registers. */
9926 if ((class == CR_REGS || class == CR0_REGS)
9927 && regno >= 0 && CR_REGNO_P (regno))
9930 /* Otherwise, we need GENERAL_REGS. */
9931 return GENERAL_REGS;
9934 /* Given a comparison operation, return the bit number in CCR to test. We
9935 know this is a valid comparison.
9937 SCC_P is 1 if this is for an scc. That means that %D will have been
9938 used instead of %C, so the bits will be in different places.
9940 Return -1 if OP isn't a valid comparison for some reason. */
9943 ccr_bit (rtx op, int scc_p)
9945 enum rtx_code code = GET_CODE (op);
9946 enum machine_mode cc_mode;
9951 if (!COMPARISON_P (op))
9956 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
9958 cc_mode = GET_MODE (reg);
9959 cc_regnum = REGNO (reg);
9960 base_bit = 4 * (cc_regnum - CR0_REGNO);
9962 validate_condition_mode (code, cc_mode);
9964 /* When generating a sCOND operation, only positive conditions are
9967 || code == EQ || code == GT || code == LT || code == UNORDERED
9968 || code == GTU || code == LTU);
9973 return scc_p ? base_bit + 3 : base_bit + 2;
9975 return base_bit + 2;
9976 case GT: case GTU: case UNLE:
9977 return base_bit + 1;
9978 case LT: case LTU: case UNGE:
9980 case ORDERED: case UNORDERED:
9981 return base_bit + 3;
9984 /* If scc, we will have done a cror to put the bit in the
9985 unordered position. So test that bit. For integer, this is ! LT
9986 unless this is an scc insn. */
9987 return scc_p ? base_bit + 3 : base_bit;
9990 return scc_p ? base_bit + 3 : base_bit + 1;
9997 /* Return the GOT register. */
10000 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10002 /* The second flow pass currently (June 1999) can't update
10003 regs_ever_live without disturbing other parts of the compiler, so
10004 update it here to make the prolog/epilogue code happy. */
10005 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
10006 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10008 current_function_uses_pic_offset_table = 1;
10010 return pic_offset_table_rtx;
10013 /* Function to init struct machine_function.
10014 This will be called, via a pointer variable,
10015 from push_function_context. */
10017 static struct machine_function *
10018 rs6000_init_machine_status (void)
10020 return ggc_alloc_cleared (sizeof (machine_function));
10023 /* These macros test for integers and extract the low-order bits. */
10025 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10026 && GET_MODE (X) == VOIDmode)
10028 #define INT_LOWPART(X) \
10029 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10032 extract_MB (rtx op)
10035 unsigned long val = INT_LOWPART (op);
10037 /* If the high bit is zero, the value is the first 1 bit we find
10039 if ((val & 0x80000000) == 0)
10041 gcc_assert (val & 0xffffffff);
10044 while (((val <<= 1) & 0x80000000) == 0)
10049 /* If the high bit is set and the low bit is not, or the mask is all
10050 1's, the value is zero. */
10051 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10054 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10057 while (((val >>= 1) & 1) != 0)
10064 extract_ME (rtx op)
10067 unsigned long val = INT_LOWPART (op);
10069 /* If the low bit is zero, the value is the first 1 bit we find from
10071 if ((val & 1) == 0)
10073 gcc_assert (val & 0xffffffff);
10076 while (((val >>= 1) & 1) == 0)
10082 /* If the low bit is set and the high bit is not, or the mask is all
10083 1's, the value is 31. */
10084 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10087 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10090 while (((val <<= 1) & 0x80000000) != 0)
10096 /* Locate some local-dynamic symbol still in use by this function
10097 so that we can print its name in some tls_ld pattern. */
10099 static const char *
10100 rs6000_get_some_local_dynamic_name (void)
10104 if (cfun->machine->some_ld_name)
10105 return cfun->machine->some_ld_name;
10107 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10109 && for_each_rtx (&PATTERN (insn),
10110 rs6000_get_some_local_dynamic_name_1, 0))
10111 return cfun->machine->some_ld_name;
10113 gcc_unreachable ();
10116 /* Helper function for rs6000_get_some_local_dynamic_name. */
10119 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10123 if (GET_CODE (x) == SYMBOL_REF)
10125 const char *str = XSTR (x, 0);
10126 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10128 cfun->machine->some_ld_name = str;
10136 /* Write out a function code label. */
10139 rs6000_output_function_entry (FILE *file, const char *fname)
10141 if (fname[0] != '.')
10143 switch (DEFAULT_ABI)
10146 gcc_unreachable ();
10152 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10161 RS6000_OUTPUT_BASENAME (file, fname);
10163 assemble_name (file, fname);
10166 /* Print an operand. Recognize special options, documented below. */
10169 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10170 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10172 #define SMALL_DATA_RELOC "sda21"
10173 #define SMALL_DATA_REG 0
10177 print_operand (FILE *file, rtx x, int code)
10181 unsigned HOST_WIDE_INT uval;
10186 /* Write out an instruction after the call which may be replaced
10187 with glue code by the loader. This depends on the AIX version. */
10188 asm_fprintf (file, RS6000_CALL_GLUE);
10191 /* %a is output_address. */
10194 /* If X is a constant integer whose low-order 5 bits are zero,
10195 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10196 in the AIX assembler where "sri" with a zero shift count
10197 writes a trash instruction. */
10198 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10205 /* If constant, low-order 16 bits of constant, unsigned.
10206 Otherwise, write normally. */
10208 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10210 print_operand (file, x, 0);
10214 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10215 for 64-bit mask direction. */
10216 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10219 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10223 /* X is a CR register. Print the number of the GT bit of the CR. */
10224 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10225 output_operand_lossage ("invalid %%E value");
10227 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10231 /* Like 'J' but get to the EQ bit. */
10232 gcc_assert (GET_CODE (x) == REG);
10234 /* Bit 1 is EQ bit. */
10235 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
10237 fprintf (file, "%d", i);
10241 /* X is a CR register. Print the number of the EQ bit of the CR */
10242 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10243 output_operand_lossage ("invalid %%E value");
10245 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10249 /* X is a CR register. Print the shift count needed to move it
10250 to the high-order four bits. */
10251 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10252 output_operand_lossage ("invalid %%f value");
10254 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10258 /* Similar, but print the count for the rotate in the opposite
10260 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10261 output_operand_lossage ("invalid %%F value");
10263 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10267 /* X is a constant integer. If it is negative, print "m",
10268 otherwise print "z". This is to make an aze or ame insn. */
10269 if (GET_CODE (x) != CONST_INT)
10270 output_operand_lossage ("invalid %%G value");
10271 else if (INTVAL (x) >= 0)
10278 /* If constant, output low-order five bits. Otherwise, write
10281 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10283 print_operand (file, x, 0);
10287 /* If constant, output low-order six bits. Otherwise, write
10290 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10292 print_operand (file, x, 0);
10296 /* Print `i' if this is a constant, else nothing. */
10302 /* Write the bit number in CCR for jump. */
10303 i = ccr_bit (x, 0);
10305 output_operand_lossage ("invalid %%j code");
10307 fprintf (file, "%d", i);
10311 /* Similar, but add one for shift count in rlinm for scc and pass
10312 scc flag to `ccr_bit'. */
10313 i = ccr_bit (x, 1);
10315 output_operand_lossage ("invalid %%J code");
10317 /* If we want bit 31, write a shift count of zero, not 32. */
10318 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10322 /* X must be a constant. Write the 1's complement of the
10325 output_operand_lossage ("invalid %%k value");
10327 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10331 /* X must be a symbolic constant on ELF. Write an
10332 expression suitable for an 'addi' that adds in the low 16
10333 bits of the MEM. */
10334 if (GET_CODE (x) != CONST)
10336 print_operand_address (file, x);
10337 fputs ("@l", file);
10341 if (GET_CODE (XEXP (x, 0)) != PLUS
10342 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10343 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10344 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10345 output_operand_lossage ("invalid %%K value");
10346 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10347 fputs ("@l", file);
10348 /* For GNU as, there must be a non-alphanumeric character
10349 between 'l' and the number. The '-' is added by
10350 print_operand() already. */
10351 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10353 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10357 /* %l is output_asm_label. */
10360 /* Write second word of DImode or DFmode reference. Works on register
10361 or non-indexed memory only. */
10362 if (GET_CODE (x) == REG)
10363 fputs (reg_names[REGNO (x) + 1], file);
10364 else if (GET_CODE (x) == MEM)
10366 /* Handle possible auto-increment. Since it is pre-increment and
10367 we have already done it, we can just use an offset of word. */
10368 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10369 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10370 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10373 output_address (XEXP (adjust_address_nv (x, SImode,
10377 if (small_data_operand (x, GET_MODE (x)))
10378 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10379 reg_names[SMALL_DATA_REG]);
10384 /* MB value for a mask operand. */
10385 if (! mask_operand (x, SImode))
10386 output_operand_lossage ("invalid %%m value");
10388 fprintf (file, "%d", extract_MB (x));
10392 /* ME value for a mask operand. */
10393 if (! mask_operand (x, SImode))
10394 output_operand_lossage ("invalid %%M value");
10396 fprintf (file, "%d", extract_ME (x));
10399 /* %n outputs the negative of its operand. */
10402 /* Write the number of elements in the vector times 4. */
10403 if (GET_CODE (x) != PARALLEL)
10404 output_operand_lossage ("invalid %%N value");
10406 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10410 /* Similar, but subtract 1 first. */
10411 if (GET_CODE (x) != PARALLEL)
10412 output_operand_lossage ("invalid %%O value");
10414 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10418 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10420 || INT_LOWPART (x) < 0
10421 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10422 output_operand_lossage ("invalid %%p value");
10424 fprintf (file, "%d", i);
10428 /* The operand must be an indirect memory reference. The result
10429 is the register name. */
10430 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10431 || REGNO (XEXP (x, 0)) >= 32)
10432 output_operand_lossage ("invalid %%P value");
10434 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10438 /* This outputs the logical code corresponding to a boolean
10439 expression. The expression may have one or both operands
10440 negated (if one, only the first one). For condition register
10441 logical operations, it will also treat the negated
10442 CR codes as NOTs, but not handle NOTs of them. */
10444 const char *const *t = 0;
10446 enum rtx_code code = GET_CODE (x);
10447 static const char * const tbl[3][3] = {
10448 { "and", "andc", "nor" },
10449 { "or", "orc", "nand" },
10450 { "xor", "eqv", "xor" } };
10454 else if (code == IOR)
10456 else if (code == XOR)
10459 output_operand_lossage ("invalid %%q value");
10461 if (GET_CODE (XEXP (x, 0)) != NOT)
10465 if (GET_CODE (XEXP (x, 1)) == NOT)
10483 /* X is a CR register. Print the mask for `mtcrf'. */
10484 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10485 output_operand_lossage ("invalid %%R value");
10487 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10491 /* Low 5 bits of 32 - value */
10493 output_operand_lossage ("invalid %%s value");
10495 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10499 /* PowerPC64 mask position. All 0's is excluded.
10500 CONST_INT 32-bit mask is considered sign-extended so any
10501 transition must occur within the CONST_INT, not on the boundary. */
10502 if (! mask64_operand (x, DImode))
10503 output_operand_lossage ("invalid %%S value");
10505 uval = INT_LOWPART (x);
10507 if (uval & 1) /* Clear Left */
10509 #if HOST_BITS_PER_WIDE_INT > 64
10510 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10514 else /* Clear Right */
10517 #if HOST_BITS_PER_WIDE_INT > 64
10518 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10524 gcc_assert (i >= 0);
10525 fprintf (file, "%d", i);
10529 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10530 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
10532 /* Bit 3 is OV bit. */
10533 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10535 /* If we want bit 31, write a shift count of zero, not 32. */
10536 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10540 /* Print the symbolic name of a branch target register. */
10541 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10542 && REGNO (x) != COUNT_REGISTER_REGNUM))
10543 output_operand_lossage ("invalid %%T value");
10544 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10545 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10547 fputs ("ctr", file);
10551 /* High-order 16 bits of constant for use in unsigned operand. */
10553 output_operand_lossage ("invalid %%u value");
10555 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10556 (INT_LOWPART (x) >> 16) & 0xffff);
10560 /* High-order 16 bits of constant for use in signed operand. */
10562 output_operand_lossage ("invalid %%v value");
10564 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10565 (INT_LOWPART (x) >> 16) & 0xffff);
10569 /* Print `u' if this has an auto-increment or auto-decrement. */
10570 if (GET_CODE (x) == MEM
10571 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10572 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10577 /* Print the trap code for this operand. */
10578 switch (GET_CODE (x))
10581 fputs ("eq", file); /* 4 */
10584 fputs ("ne", file); /* 24 */
10587 fputs ("lt", file); /* 16 */
10590 fputs ("le", file); /* 20 */
10593 fputs ("gt", file); /* 8 */
10596 fputs ("ge", file); /* 12 */
10599 fputs ("llt", file); /* 2 */
10602 fputs ("lle", file); /* 6 */
10605 fputs ("lgt", file); /* 1 */
10608 fputs ("lge", file); /* 5 */
10611 gcc_unreachable ();
10616 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10619 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10620 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10622 print_operand (file, x, 0);
10626 /* MB value for a PowerPC64 rldic operand. */
10627 val = (GET_CODE (x) == CONST_INT
10628 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10633 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10634 if ((val <<= 1) < 0)
10637 #if HOST_BITS_PER_WIDE_INT == 32
10638 if (GET_CODE (x) == CONST_INT && i >= 0)
10639 i += 32; /* zero-extend high-part was all 0's */
10640 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10642 val = CONST_DOUBLE_LOW (x);
10648 for ( ; i < 64; i++)
10649 if ((val <<= 1) < 0)
10654 fprintf (file, "%d", i + 1);
10658 if (GET_CODE (x) == MEM
10659 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10664 /* Like 'L', for third word of TImode */
10665 if (GET_CODE (x) == REG)
10666 fputs (reg_names[REGNO (x) + 2], file);
10667 else if (GET_CODE (x) == MEM)
10669 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10670 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10671 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10673 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10674 if (small_data_operand (x, GET_MODE (x)))
10675 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10676 reg_names[SMALL_DATA_REG]);
10681 /* X is a SYMBOL_REF. Write out the name preceded by a
10682 period and without any trailing data in brackets. Used for function
10683 names. If we are configured for System V (or the embedded ABI) on
10684 the PowerPC, do not emit the period, since those systems do not use
10685 TOCs and the like. */
10686 gcc_assert (GET_CODE (x) == SYMBOL_REF);
10688 /* Mark the decl as referenced so that cgraph will output the
10690 if (SYMBOL_REF_DECL (x))
10691 mark_decl_referenced (SYMBOL_REF_DECL (x));
10693 /* For macho, check to see if we need a stub. */
10696 const char *name = XSTR (x, 0);
10698 if (MACHOPIC_INDIRECT
10699 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10700 name = machopic_indirection_name (x, /*stub_p=*/true);
10702 assemble_name (file, name);
10704 else if (!DOT_SYMBOLS)
10705 assemble_name (file, XSTR (x, 0));
10707 rs6000_output_function_entry (file, XSTR (x, 0));
10711 /* Like 'L', for last word of TImode. */
10712 if (GET_CODE (x) == REG)
10713 fputs (reg_names[REGNO (x) + 3], file);
10714 else if (GET_CODE (x) == MEM)
10716 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10717 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10718 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10720 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10721 if (small_data_operand (x, GET_MODE (x)))
10722 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10723 reg_names[SMALL_DATA_REG]);
10727 /* Print AltiVec or SPE memory operand. */
10732 gcc_assert (GET_CODE (x) == MEM);
10738 /* Handle [reg]. */
10739 if (GET_CODE (tmp) == REG)
10741 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10744 /* Handle [reg+UIMM]. */
10745 else if (GET_CODE (tmp) == PLUS &&
10746 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10750 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
10752 x = INTVAL (XEXP (tmp, 1));
10753 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10757 /* Fall through. Must be [reg+reg]. */
10760 && GET_CODE (tmp) == AND
10761 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10762 && INTVAL (XEXP (tmp, 1)) == -16)
10763 tmp = XEXP (tmp, 0);
10764 if (GET_CODE (tmp) == REG)
10765 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
10768 gcc_assert (GET_CODE (tmp) == PLUS
10769 && REG_P (XEXP (tmp, 0))
10770 && REG_P (XEXP (tmp, 1)));
10772 if (REGNO (XEXP (tmp, 0)) == 0)
10773 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10774 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10776 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10777 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10783 if (GET_CODE (x) == REG)
10784 fprintf (file, "%s", reg_names[REGNO (x)]);
10785 else if (GET_CODE (x) == MEM)
10787 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10788 know the width from the mode. */
10789 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
10790 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10791 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10792 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
10793 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10794 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10796 output_address (XEXP (x, 0));
10799 output_addr_const (file, x);
10803 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10807 output_operand_lossage ("invalid %%xn code");
10811 /* Print the address of an operand. */
10814 print_operand_address (FILE *file, rtx x)
10816 if (GET_CODE (x) == REG)
10817 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
10818 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10819 || GET_CODE (x) == LABEL_REF)
10821 output_addr_const (file, x);
10822 if (small_data_operand (x, GET_MODE (x)))
10823 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10824 reg_names[SMALL_DATA_REG]);
10826 gcc_assert (!TARGET_TOC);
10828 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10830 gcc_assert (REG_P (XEXP (x, 0)));
10831 if (REGNO (XEXP (x, 0)) == 0)
10832 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10833 reg_names[ REGNO (XEXP (x, 0)) ]);
10835 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10836 reg_names[ REGNO (XEXP (x, 1)) ]);
10838 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
10839 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10840 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
10842 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10843 && CONSTANT_P (XEXP (x, 1)))
10845 output_addr_const (file, XEXP (x, 1));
10846 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10850 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10851 && CONSTANT_P (XEXP (x, 1)))
10853 fprintf (file, "lo16(");
10854 output_addr_const (file, XEXP (x, 1));
10855 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10858 else if (legitimate_constant_pool_address_p (x))
10860 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
10862 rtx contains_minus = XEXP (x, 1);
10866 /* Find the (minus (sym) (toc)) buried in X, and temporarily
10867 turn it into (sym) for output_addr_const. */
10868 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10869 contains_minus = XEXP (contains_minus, 0);
10871 minus = XEXP (contains_minus, 0);
10872 symref = XEXP (minus, 0);
10873 XEXP (contains_minus, 0) = symref;
10878 name = XSTR (symref, 0);
10879 newname = alloca (strlen (name) + sizeof ("@toc"));
10880 strcpy (newname, name);
10881 strcat (newname, "@toc");
10882 XSTR (symref, 0) = newname;
10884 output_addr_const (file, XEXP (x, 1));
10886 XSTR (symref, 0) = name;
10887 XEXP (contains_minus, 0) = minus;
10890 output_addr_const (file, XEXP (x, 1));
10892 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
10895 gcc_unreachable ();
10898 /* Target hook for assembling integer objects. The PowerPC version has
10899 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10900 is defined. It also needs to handle DI-mode objects on 64-bit
10904 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
10906 #ifdef RELOCATABLE_NEEDS_FIXUP
10907 /* Special handling for SI values. */
10908 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
10910 static int recurse = 0;
10912 /* For -mrelocatable, we mark all addresses that need to be fixed up
10913 in the .fixup section. */
10914 if (TARGET_RELOCATABLE
10915 && in_section != toc_section
10916 && in_section != text_section
10917 && !unlikely_text_section_p (in_section)
10919 && GET_CODE (x) != CONST_INT
10920 && GET_CODE (x) != CONST_DOUBLE
10926 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
10928 ASM_OUTPUT_LABEL (asm_out_file, buf);
10929 fprintf (asm_out_file, "\t.long\t(");
10930 output_addr_const (asm_out_file, x);
10931 fprintf (asm_out_file, ")@fixup\n");
10932 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
10933 ASM_OUTPUT_ALIGN (asm_out_file, 2);
10934 fprintf (asm_out_file, "\t.long\t");
10935 assemble_name (asm_out_file, buf);
10936 fprintf (asm_out_file, "\n\t.previous\n");
10940 /* Remove initial .'s to turn a -mcall-aixdesc function
10941 address into the address of the descriptor, not the function
10943 else if (GET_CODE (x) == SYMBOL_REF
10944 && XSTR (x, 0)[0] == '.'
10945 && DEFAULT_ABI == ABI_AIX)
10947 const char *name = XSTR (x, 0);
10948 while (*name == '.')
10951 fprintf (asm_out_file, "\t.long\t%s\n", name);
10955 #endif /* RELOCATABLE_NEEDS_FIXUP */
10956 return default_assemble_integer (x, size, aligned_p);
10959 #ifdef HAVE_GAS_HIDDEN
10960 /* Emit an assembler directive to set symbol visibility for DECL to
10961 VISIBILITY_TYPE. */
10964 rs6000_assemble_visibility (tree decl, int vis)
10966 /* Functions need to have their entry point symbol visibility set as
10967 well as their descriptor symbol visibility. */
10968 if (DEFAULT_ABI == ABI_AIX
10970 && TREE_CODE (decl) == FUNCTION_DECL)
10972 static const char * const visibility_types[] = {
10973 NULL, "internal", "hidden", "protected"
10976 const char *name, *type;
10978 name = ((* targetm.strip_name_encoding)
10979 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
10980 type = visibility_types[vis];
10982 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
10983 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
10986 default_assemble_visibility (decl, vis);
10991 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
10993 /* Reversal of FP compares takes care -- an ordered compare
10994 becomes an unordered compare and vice versa. */
10995 if (mode == CCFPmode
10996 && (!flag_finite_math_only
10997 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
10998 || code == UNEQ || code == LTGT))
10999 return reverse_condition_maybe_unordered (code);
11001 return reverse_condition (code);
11004 /* Generate a compare for CODE. Return a brand-new rtx that
11005 represents the result of the compare. */
11008 rs6000_generate_compare (enum rtx_code code)
11010 enum machine_mode comp_mode;
11011 rtx compare_result;
11013 if (rs6000_compare_fp_p)
11014 comp_mode = CCFPmode;
11015 else if (code == GTU || code == LTU
11016 || code == GEU || code == LEU)
11017 comp_mode = CCUNSmode;
11018 else if ((code == EQ || code == NE)
11019 && GET_CODE (rs6000_compare_op0) == SUBREG
11020 && GET_CODE (rs6000_compare_op1) == SUBREG
11021 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11022 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11023 /* These are unsigned values, perhaps there will be a later
11024 ordering compare that can be shared with this one.
11025 Unfortunately we cannot detect the signedness of the operands
11026 for non-subregs. */
11027 comp_mode = CCUNSmode;
11029 comp_mode = CCmode;
11031 /* First, the compare. */
11032 compare_result = gen_reg_rtx (comp_mode);
11034 /* SPE FP compare instructions on the GPRs. Yuck! */
11035 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11036 && rs6000_compare_fp_p)
11038 rtx cmp, or_result, compare_result2;
11039 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11041 if (op_mode == VOIDmode)
11042 op_mode = GET_MODE (rs6000_compare_op1);
11044 /* Note: The E500 comparison instructions set the GT bit (x +
11045 1), on success. This explains the mess. */
11049 case EQ: case UNEQ: case NE: case LTGT:
11053 cmp = flag_unsafe_math_optimizations
11054 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11055 rs6000_compare_op1)
11056 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11057 rs6000_compare_op1);
11061 cmp = flag_unsafe_math_optimizations
11062 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11063 rs6000_compare_op1)
11064 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11065 rs6000_compare_op1);
11069 gcc_unreachable ();
11073 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11077 cmp = flag_unsafe_math_optimizations
11078 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11079 rs6000_compare_op1)
11080 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11081 rs6000_compare_op1);
11085 cmp = flag_unsafe_math_optimizations
11086 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11087 rs6000_compare_op1)
11088 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11089 rs6000_compare_op1);
11093 gcc_unreachable ();
11097 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11101 cmp = flag_unsafe_math_optimizations
11102 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11103 rs6000_compare_op1)
11104 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11105 rs6000_compare_op1);
11109 cmp = flag_unsafe_math_optimizations
11110 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11111 rs6000_compare_op1)
11112 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11113 rs6000_compare_op1);
11117 gcc_unreachable ();
11121 gcc_unreachable ();
11124 /* Synthesize LE and GE from LT/GT || EQ. */
11125 if (code == LE || code == GE || code == LEU || code == GEU)
11131 case LE: code = LT; break;
11132 case GE: code = GT; break;
11133 case LEU: code = LT; break;
11134 case GEU: code = GT; break;
11135 default: gcc_unreachable ();
11138 compare_result2 = gen_reg_rtx (CCFPmode);
11144 cmp = flag_unsafe_math_optimizations
11145 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11146 rs6000_compare_op1)
11147 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11148 rs6000_compare_op1);
11152 cmp = flag_unsafe_math_optimizations
11153 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11154 rs6000_compare_op1)
11155 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11156 rs6000_compare_op1);
11160 gcc_unreachable ();
11164 /* OR them together. */
11165 or_result = gen_reg_rtx (CCFPmode);
11166 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11168 compare_result = or_result;
11173 if (code == NE || code == LTGT)
11183 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11184 CLOBBERs to match cmptf_internal2 pattern. */
11185 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11186 && GET_MODE (rs6000_compare_op0) == TFmode
11187 && !TARGET_IEEEQUAD
11188 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11189 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11191 gen_rtx_SET (VOIDmode,
11193 gen_rtx_COMPARE (comp_mode,
11194 rs6000_compare_op0,
11195 rs6000_compare_op1)),
11196 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11197 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11198 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11199 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11200 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11201 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11202 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11203 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11204 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11205 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11207 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11208 comp_mode = CCEQmode;
11209 compare_result = gen_reg_rtx (CCEQmode);
11211 emit_insn (gen_stack_protect_testdi (compare_result,
11212 rs6000_compare_op0, op1));
11214 emit_insn (gen_stack_protect_testsi (compare_result,
11215 rs6000_compare_op0, op1));
11218 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11219 gen_rtx_COMPARE (comp_mode,
11220 rs6000_compare_op0,
11221 rs6000_compare_op1)));
11224 /* Some kinds of FP comparisons need an OR operation;
11225 under flag_finite_math_only we don't bother. */
11226 if (rs6000_compare_fp_p
11227 && !flag_finite_math_only
11228 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11229 && (code == LE || code == GE
11230 || code == UNEQ || code == LTGT
11231 || code == UNGT || code == UNLT))
11233 enum rtx_code or1, or2;
11234 rtx or1_rtx, or2_rtx, compare2_rtx;
11235 rtx or_result = gen_reg_rtx (CCEQmode);
11239 case LE: or1 = LT; or2 = EQ; break;
11240 case GE: or1 = GT; or2 = EQ; break;
11241 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11242 case LTGT: or1 = LT; or2 = GT; break;
11243 case UNGT: or1 = UNORDERED; or2 = GT; break;
11244 case UNLT: or1 = UNORDERED; or2 = LT; break;
11245 default: gcc_unreachable ();
11247 validate_condition_mode (or1, comp_mode);
11248 validate_condition_mode (or2, comp_mode);
11249 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11250 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11251 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11252 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11254 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11256 compare_result = or_result;
11260 validate_condition_mode (code, GET_MODE (compare_result));
11262 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11266 /* Emit the RTL for an sCOND pattern. */
11269 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11272 enum machine_mode op_mode;
11273 enum rtx_code cond_code;
11275 condition_rtx = rs6000_generate_compare (code);
11276 cond_code = GET_CODE (condition_rtx);
11278 if (TARGET_E500 && rs6000_compare_fp_p
11279 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11283 PUT_MODE (condition_rtx, SImode);
11284 t = XEXP (condition_rtx, 0);
11286 gcc_assert (cond_code == NE || cond_code == EQ);
11288 if (cond_code == NE)
11289 emit_insn (gen_e500_flip_gt_bit (t, t));
11291 emit_insn (gen_move_from_CR_gt_bit (result, t));
11295 if (cond_code == NE
11296 || cond_code == GE || cond_code == LE
11297 || cond_code == GEU || cond_code == LEU
11298 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11300 rtx not_result = gen_reg_rtx (CCEQmode);
11301 rtx not_op, rev_cond_rtx;
11302 enum machine_mode cc_mode;
11304 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11306 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11307 SImode, XEXP (condition_rtx, 0), const0_rtx);
11308 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11309 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11310 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11313 op_mode = GET_MODE (rs6000_compare_op0);
11314 if (op_mode == VOIDmode)
11315 op_mode = GET_MODE (rs6000_compare_op1);
11317 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11319 PUT_MODE (condition_rtx, DImode);
11320 convert_move (result, condition_rtx, 0);
11324 PUT_MODE (condition_rtx, SImode);
11325 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11329 /* Emit a branch of kind CODE to location LOC. */
11332 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11334 rtx condition_rtx, loc_ref;
11336 condition_rtx = rs6000_generate_compare (code);
11337 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11338 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11339 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11340 loc_ref, pc_rtx)));
11343 /* Return the string to output a conditional branch to LABEL, which is
11344 the operand number of the label, or -1 if the branch is really a
11345 conditional return.
11347 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11348 condition code register and its mode specifies what kind of
11349 comparison we made.
11351 REVERSED is nonzero if we should reverse the sense of the comparison.
11353 INSN is the insn. */
11356 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11358 static char string[64];
11359 enum rtx_code code = GET_CODE (op);
11360 rtx cc_reg = XEXP (op, 0);
11361 enum machine_mode mode = GET_MODE (cc_reg);
11362 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11363 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11364 int really_reversed = reversed ^ need_longbranch;
11370 validate_condition_mode (code, mode);
11372 /* Work out which way this really branches. We could use
11373 reverse_condition_maybe_unordered here always but this
11374 makes the resulting assembler clearer. */
11375 if (really_reversed)
11377 /* Reversal of FP compares takes care -- an ordered compare
11378 becomes an unordered compare and vice versa. */
11379 if (mode == CCFPmode)
11380 code = reverse_condition_maybe_unordered (code);
11382 code = reverse_condition (code);
11385 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11387 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11392 /* Opposite of GT. */
11401 gcc_unreachable ();
11407 /* Not all of these are actually distinct opcodes, but
11408 we distinguish them for clarity of the resulting assembler. */
11409 case NE: case LTGT:
11410 ccode = "ne"; break;
11411 case EQ: case UNEQ:
11412 ccode = "eq"; break;
11414 ccode = "ge"; break;
11415 case GT: case GTU: case UNGT:
11416 ccode = "gt"; break;
11418 ccode = "le"; break;
11419 case LT: case LTU: case UNLT:
11420 ccode = "lt"; break;
11421 case UNORDERED: ccode = "un"; break;
11422 case ORDERED: ccode = "nu"; break;
11423 case UNGE: ccode = "nl"; break;
11424 case UNLE: ccode = "ng"; break;
11426 gcc_unreachable ();
11429 /* Maybe we have a guess as to how likely the branch is.
11430 The old mnemonics don't have a way to specify this information. */
11432 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11433 if (note != NULL_RTX)
11435 /* PROB is the difference from 50%. */
11436 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11438 /* Only hint for highly probable/improbable branches on newer
11439 cpus as static prediction overrides processor dynamic
11440 prediction. For older cpus we may as well always hint, but
11441 assume not taken for branches that are very close to 50% as a
11442 mispredicted taken branch is more expensive than a
11443 mispredicted not-taken branch. */
11444 if (rs6000_always_hint
11445 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
11447 if (abs (prob) > REG_BR_PROB_BASE / 20
11448 && ((prob > 0) ^ need_longbranch))
11456 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11458 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11460 /* We need to escape any '%' characters in the reg_names string.
11461 Assume they'd only be the first character.... */
11462 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11464 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11468 /* If the branch distance was too far, we may have to use an
11469 unconditional branch to go the distance. */
11470 if (need_longbranch)
11471 s += sprintf (s, ",$+8\n\tb %s", label);
11473 s += sprintf (s, ",%s", label);
11479 /* Return the string to flip the GT bit on a CR. */
11481 output_e500_flip_gt_bit (rtx dst, rtx src)
11483 static char string[64];
11486 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
11487 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
11490 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
11491 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
11493 sprintf (string, "crnot %d,%d", a, b);
11497 /* Return insn index for the vector compare instruction for given CODE,
11498 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11502 get_vec_cmp_insn (enum rtx_code code,
11503 enum machine_mode dest_mode,
11504 enum machine_mode op_mode)
11506 if (!TARGET_ALTIVEC)
11507 return INSN_NOT_AVAILABLE;
11512 if (dest_mode == V16QImode && op_mode == V16QImode)
11513 return UNSPEC_VCMPEQUB;
11514 if (dest_mode == V8HImode && op_mode == V8HImode)
11515 return UNSPEC_VCMPEQUH;
11516 if (dest_mode == V4SImode && op_mode == V4SImode)
11517 return UNSPEC_VCMPEQUW;
11518 if (dest_mode == V4SImode && op_mode == V4SFmode)
11519 return UNSPEC_VCMPEQFP;
11522 if (dest_mode == V4SImode && op_mode == V4SFmode)
11523 return UNSPEC_VCMPGEFP;
11525 if (dest_mode == V16QImode && op_mode == V16QImode)
11526 return UNSPEC_VCMPGTSB;
11527 if (dest_mode == V8HImode && op_mode == V8HImode)
11528 return UNSPEC_VCMPGTSH;
11529 if (dest_mode == V4SImode && op_mode == V4SImode)
11530 return UNSPEC_VCMPGTSW;
11531 if (dest_mode == V4SImode && op_mode == V4SFmode)
11532 return UNSPEC_VCMPGTFP;
11535 if (dest_mode == V16QImode && op_mode == V16QImode)
11536 return UNSPEC_VCMPGTUB;
11537 if (dest_mode == V8HImode && op_mode == V8HImode)
11538 return UNSPEC_VCMPGTUH;
11539 if (dest_mode == V4SImode && op_mode == V4SImode)
11540 return UNSPEC_VCMPGTUW;
11545 return INSN_NOT_AVAILABLE;
11548 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11549 DMODE is expected destination mode. This is a recursive function. */
11552 rs6000_emit_vector_compare (enum rtx_code rcode,
11554 enum machine_mode dmode)
11558 enum machine_mode dest_mode;
11559 enum machine_mode op_mode = GET_MODE (op1);
11561 gcc_assert (TARGET_ALTIVEC);
11562 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
11564 /* Floating point vector compare instructions uses destination V4SImode.
11565 Move destination to appropriate mode later. */
11566 if (dmode == V4SFmode)
11567 dest_mode = V4SImode;
11571 mask = gen_reg_rtx (dest_mode);
11572 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11574 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11576 bool swap_operands = false;
11577 bool try_again = false;
11582 swap_operands = true;
11587 swap_operands = true;
11591 /* Treat A != B as ~(A==B). */
11593 enum insn_code nor_code;
11594 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11597 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11598 gcc_assert (nor_code != CODE_FOR_nothing);
11599 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11601 if (dmode != dest_mode)
11603 rtx temp = gen_reg_rtx (dest_mode);
11604 convert_move (temp, mask, 0);
11614 /* Try GT/GTU/LT/LTU OR EQ */
11617 enum insn_code ior_code;
11618 enum rtx_code new_code;
11639 gcc_unreachable ();
11642 c_rtx = rs6000_emit_vector_compare (new_code,
11643 op0, op1, dest_mode);
11644 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11647 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11648 gcc_assert (ior_code != CODE_FOR_nothing);
11649 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11650 if (dmode != dest_mode)
11652 rtx temp = gen_reg_rtx (dest_mode);
11653 convert_move (temp, mask, 0);
11660 gcc_unreachable ();
11665 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11666 /* You only get two chances. */
11667 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
11679 emit_insn (gen_rtx_SET (VOIDmode, mask,
11680 gen_rtx_UNSPEC (dest_mode,
11681 gen_rtvec (2, op0, op1),
11683 if (dmode != dest_mode)
11685 rtx temp = gen_reg_rtx (dest_mode);
11686 convert_move (temp, mask, 0);
11692 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11693 valid insn doesn exist for given mode. */
11696 get_vsel_insn (enum machine_mode mode)
11701 return UNSPEC_VSEL4SI;
11704 return UNSPEC_VSEL4SF;
11707 return UNSPEC_VSEL8HI;
11710 return UNSPEC_VSEL16QI;
11713 return INSN_NOT_AVAILABLE;
11716 return INSN_NOT_AVAILABLE;
11719 /* Emit vector select insn where DEST is destination using
11720 operands OP1, OP2 and MASK. */
11723 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11726 enum machine_mode dest_mode = GET_MODE (dest);
11727 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11729 temp = gen_reg_rtx (dest_mode);
11731 /* For each vector element, select op1 when mask is 1 otherwise
11733 t = gen_rtx_SET (VOIDmode, temp,
11734 gen_rtx_UNSPEC (dest_mode,
11735 gen_rtvec (3, op2, op1, mask),
11738 emit_move_insn (dest, temp);
11742 /* Emit vector conditional expression.
11743 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11744 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11747 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11748 rtx cond, rtx cc_op0, rtx cc_op1)
11750 enum machine_mode dest_mode = GET_MODE (dest);
11751 enum rtx_code rcode = GET_CODE (cond);
11754 if (!TARGET_ALTIVEC)
11757 /* Get the vector mask for the given relational operations. */
11758 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11760 rs6000_emit_vector_select (dest, op1, op2, mask);
11765 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11766 operands of the last comparison is nonzero/true, FALSE_COND if it
11767 is zero/false. Return 0 if the hardware has no such operation. */
11770 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11772 enum rtx_code code = GET_CODE (op);
11773 rtx op0 = rs6000_compare_op0;
11774 rtx op1 = rs6000_compare_op1;
11775 REAL_VALUE_TYPE c1;
11776 enum machine_mode compare_mode = GET_MODE (op0);
11777 enum machine_mode result_mode = GET_MODE (dest);
11779 bool is_against_zero;
11781 /* These modes should always match. */
11782 if (GET_MODE (op1) != compare_mode
11783 /* In the isel case however, we can use a compare immediate, so
11784 op1 may be a small constant. */
11785 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11787 if (GET_MODE (true_cond) != result_mode)
11789 if (GET_MODE (false_cond) != result_mode)
11792 /* First, work out if the hardware can do this at all, or
11793 if it's too slow.... */
11794 if (! rs6000_compare_fp_p)
11797 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11800 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11801 && SCALAR_FLOAT_MODE_P (compare_mode))
11804 is_against_zero = op1 == CONST0_RTX (compare_mode);
11806 /* A floating-point subtract might overflow, underflow, or produce
11807 an inexact result, thus changing the floating-point flags, so it
11808 can't be generated if we care about that. It's safe if one side
11809 of the construct is zero, since then no subtract will be
11811 if (SCALAR_FLOAT_MODE_P (compare_mode)
11812 && flag_trapping_math && ! is_against_zero)
11815 /* Eliminate half of the comparisons by switching operands, this
11816 makes the remaining code simpler. */
11817 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
11818 || code == LTGT || code == LT || code == UNLE)
11820 code = reverse_condition_maybe_unordered (code);
11822 true_cond = false_cond;
11826 /* UNEQ and LTGT take four instructions for a comparison with zero,
11827 it'll probably be faster to use a branch here too. */
11828 if (code == UNEQ && HONOR_NANS (compare_mode))
11831 if (GET_CODE (op1) == CONST_DOUBLE)
11832 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
11834 /* We're going to try to implement comparisons by performing
11835 a subtract, then comparing against zero. Unfortunately,
11836 Inf - Inf is NaN which is not zero, and so if we don't
11837 know that the operand is finite and the comparison
11838 would treat EQ different to UNORDERED, we can't do it. */
11839 if (HONOR_INFINITIES (compare_mode)
11840 && code != GT && code != UNGE
11841 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
11842 /* Constructs of the form (a OP b ? a : b) are safe. */
11843 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
11844 || (! rtx_equal_p (op0, true_cond)
11845 && ! rtx_equal_p (op1, true_cond))))
11848 /* At this point we know we can use fsel. */
11850 /* Reduce the comparison to a comparison against zero. */
11851 if (! is_against_zero)
11853 temp = gen_reg_rtx (compare_mode);
11854 emit_insn (gen_rtx_SET (VOIDmode, temp,
11855 gen_rtx_MINUS (compare_mode, op0, op1)));
11857 op1 = CONST0_RTX (compare_mode);
11860 /* If we don't care about NaNs we can reduce some of the comparisons
11861 down to faster ones. */
11862 if (! HONOR_NANS (compare_mode))
11868 true_cond = false_cond;
11881 /* Now, reduce everything down to a GE. */
11888 temp = gen_reg_rtx (compare_mode);
11889 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11894 temp = gen_reg_rtx (compare_mode);
11895 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
11900 temp = gen_reg_rtx (compare_mode);
11901 emit_insn (gen_rtx_SET (VOIDmode, temp,
11902 gen_rtx_NEG (compare_mode,
11903 gen_rtx_ABS (compare_mode, op0))));
11908 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
11909 temp = gen_reg_rtx (result_mode);
11910 emit_insn (gen_rtx_SET (VOIDmode, temp,
11911 gen_rtx_IF_THEN_ELSE (result_mode,
11912 gen_rtx_GE (VOIDmode,
11914 true_cond, false_cond)));
11915 false_cond = true_cond;
11918 temp = gen_reg_rtx (compare_mode);
11919 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11924 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
11925 temp = gen_reg_rtx (result_mode);
11926 emit_insn (gen_rtx_SET (VOIDmode, temp,
11927 gen_rtx_IF_THEN_ELSE (result_mode,
11928 gen_rtx_GE (VOIDmode,
11930 true_cond, false_cond)));
11931 true_cond = false_cond;
11934 temp = gen_reg_rtx (compare_mode);
11935 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11940 gcc_unreachable ();
11943 emit_insn (gen_rtx_SET (VOIDmode, dest,
11944 gen_rtx_IF_THEN_ELSE (result_mode,
11945 gen_rtx_GE (VOIDmode,
11947 true_cond, false_cond)));
11951 /* Same as above, but for ints (isel). */
11954 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11956 rtx condition_rtx, cr;
11958 /* All isel implementations thus far are 32-bits. */
11959 if (GET_MODE (rs6000_compare_op0) != SImode)
11962 /* We still have to do the compare, because isel doesn't do a
11963 compare, it just looks at the CRx bits set by a previous compare
11965 condition_rtx = rs6000_generate_compare (GET_CODE (op));
11966 cr = XEXP (condition_rtx, 0);
11968 if (GET_MODE (cr) == CCmode)
11969 emit_insn (gen_isel_signed (dest, condition_rtx,
11970 true_cond, false_cond, cr));
11972 emit_insn (gen_isel_unsigned (dest, condition_rtx,
11973 true_cond, false_cond, cr));
11979 output_isel (rtx *operands)
11981 enum rtx_code code;
11983 code = GET_CODE (operands[1]);
11984 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
11986 PUT_CODE (operands[1], reverse_condition (code));
11987 return "isel %0,%3,%2,%j1";
11990 return "isel %0,%2,%3,%j1";
11994 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
11996 enum machine_mode mode = GET_MODE (op0);
12000 if (code == SMAX || code == SMIN)
12005 if (code == SMAX || code == UMAX)
12006 target = emit_conditional_move (dest, c, op0, op1, mode,
12007 op0, op1, mode, 0);
12009 target = emit_conditional_move (dest, c, op0, op1, mode,
12010 op1, op0, mode, 0);
12011 gcc_assert (target);
12012 if (target != dest)
12013 emit_move_insn (dest, target);
12016 /* Emit instructions to perform a load-reserved/store-conditional operation.
12017 The operation performed is an atomic
12018 (set M (CODE:MODE M OP))
12019 If not NULL, BEFORE is atomically set to M before the operation, and
12020 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
12021 If SYNC_P then a memory barrier is emitted before the operation.
12022 Either OP or M may be wrapped in a NOT operation. */
12025 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
12026 rtx m, rtx op, rtx before_param, rtx after_param,
12029 enum machine_mode used_mode;
12030 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
12033 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12034 rtx shift = NULL_RTX;
12037 emit_insn (gen_memory_barrier ());
12039 if (GET_CODE (m) == NOT)
12040 used_m = XEXP (m, 0);
12044 /* If this is smaller than SImode, we'll have to use SImode with
12046 if (mode == QImode || mode == HImode)
12050 if (MEM_ALIGN (used_m) >= 32)
12053 if (BYTES_BIG_ENDIAN)
12054 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
12056 shift = GEN_INT (ishift);
12060 rtx addrSI, aligned_addr;
12061 int shift_mask = mode == QImode ? 0x18 : 0x10;
12063 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
12064 XEXP (used_m, 0)));
12065 shift = gen_reg_rtx (SImode);
12067 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12068 GEN_INT (shift_mask)));
12069 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12071 aligned_addr = expand_binop (Pmode, and_optab,
12073 GEN_INT (-4), NULL_RTX,
12074 1, OPTAB_LIB_WIDEN);
12075 used_m = change_address (used_m, SImode, aligned_addr);
12076 set_mem_align (used_m, 32);
12077 /* It's safe to keep the old alias set of USED_M, because
12078 the operation is atomic and only affects the original
12080 if (GET_CODE (m) == NOT)
12081 m = gen_rtx_NOT (SImode, used_m);
12086 if (GET_CODE (op) == NOT)
12088 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12089 oldop = gen_rtx_NOT (SImode, oldop);
12092 oldop = lowpart_subreg (SImode, op, mode);
12098 newop = expand_binop (SImode, and_optab,
12099 oldop, GEN_INT (imask), NULL_RTX,
12100 1, OPTAB_LIB_WIDEN);
12101 emit_insn (gen_ashlsi3 (newop, newop, shift));
12105 newop = expand_binop (SImode, ior_optab,
12106 oldop, GEN_INT (~imask), NULL_RTX,
12107 1, OPTAB_LIB_WIDEN);
12108 emit_insn (gen_rotlsi3 (newop, newop, shift));
12116 newop = expand_binop (SImode, and_optab,
12117 oldop, GEN_INT (imask), NULL_RTX,
12118 1, OPTAB_LIB_WIDEN);
12119 emit_insn (gen_ashlsi3 (newop, newop, shift));
12121 mask = gen_reg_rtx (SImode);
12122 emit_move_insn (mask, GEN_INT (imask));
12123 emit_insn (gen_ashlsi3 (mask, mask, shift));
12126 newop = gen_rtx_PLUS (SImode, m, newop);
12128 newop = gen_rtx_MINUS (SImode, m, newop);
12129 newop = gen_rtx_AND (SImode, newop, mask);
12130 newop = gen_rtx_IOR (SImode, newop,
12131 gen_rtx_AND (SImode,
12132 gen_rtx_NOT (SImode, mask),
12138 gcc_unreachable ();
12141 if (GET_CODE (m) == NOT)
12145 mask = gen_reg_rtx (SImode);
12146 emit_move_insn (mask, GEN_INT (imask));
12147 emit_insn (gen_ashlsi3 (mask, mask, shift));
12149 xorm = gen_rtx_XOR (SImode, used_m, mask);
12150 /* Depending on the value of 'op', the XOR or the operation might
12151 be able to be simplified away. */
12152 newop = simplify_gen_binary (code, SImode, xorm, newop);
12155 used_mode = SImode;
12156 before = gen_reg_rtx (used_mode);
12157 after = gen_reg_rtx (used_mode);
12162 before = before_param;
12163 after = after_param;
12165 if (before == NULL_RTX)
12166 before = gen_reg_rtx (used_mode);
12167 if (after == NULL_RTX)
12168 after = gen_reg_rtx (used_mode);
12171 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12172 && used_mode != mode)
12173 the_op = op; /* Computed above. */
12174 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12175 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12177 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12179 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12180 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12181 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12182 gen_rtx_UNSPEC (used_mode,
12183 gen_rtvec (1, the_op),
12185 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12187 if ((code == PLUS || code == MINUS) && used_mode != mode)
12188 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12189 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12191 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12192 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12194 /* Shift and mask the return values properly. */
12195 if (used_mode != mode && before_param)
12197 emit_insn (gen_lshrsi3 (before, before, shift));
12198 convert_move (before_param, before, 1);
12201 if (used_mode != mode && after_param)
12203 emit_insn (gen_lshrsi3 (after, after, shift));
12204 convert_move (after_param, after, 1);
12207 /* The previous sequence will end with a branch that's dependent on
12208 the conditional store, so placing an isync will ensure that no
12209 other instructions (especially, no load or store instructions)
12210 can start before the atomic operation completes. */
12212 emit_insn (gen_isync ());
12215 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12216 COND is true. Mark the jump as unlikely to be taken. */
12219 emit_unlikely_jump (rtx cond, rtx label)
12221 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12224 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12225 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12226 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12229 /* A subroutine of the atomic operation splitters. Emit a load-locked
12230 instruction in MODE. */
12233 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12235 rtx (*fn) (rtx, rtx) = NULL;
12236 if (mode == SImode)
12237 fn = gen_load_locked_si;
12238 else if (mode == DImode)
12239 fn = gen_load_locked_di;
12240 emit_insn (fn (reg, mem));
12243 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12244 instruction in MODE. */
12247 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12249 rtx (*fn) (rtx, rtx, rtx) = NULL;
12250 if (mode == SImode)
12251 fn = gen_store_conditional_si;
12252 else if (mode == DImode)
12253 fn = gen_store_conditional_di;
12255 /* Emit sync before stwcx. to address PPC405 Erratum. */
12256 if (PPC405_ERRATUM77)
12257 emit_insn (gen_memory_barrier ());
12259 emit_insn (fn (res, mem, val));
12262 /* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation
12263 to perform. MEM is the memory on which to operate. VAL is the second
12264 operand of the binary operator. BEFORE and AFTER are optional locations to
12265 return the value of MEM either before of after the operation. SCRATCH is
12266 a scratch register. */
12269 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12270 rtx before, rtx after, rtx scratch)
12272 enum machine_mode mode = GET_MODE (mem);
12273 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12275 emit_insn (gen_memory_barrier ());
12277 label = gen_label_rtx ();
12278 emit_label (label);
12279 label = gen_rtx_LABEL_REF (VOIDmode, label);
12281 if (before == NULL_RTX)
12283 emit_load_locked (mode, before, mem);
12286 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12287 else if (code == AND)
12288 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12290 x = gen_rtx_fmt_ee (code, mode, before, val);
12292 if (after != NULL_RTX)
12293 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12294 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12296 emit_store_conditional (mode, cond, mem, scratch);
12298 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12299 emit_unlikely_jump (x, label);
12301 emit_insn (gen_isync ());
12304 /* Expand an atomic compare and swap operation. MEM is the memory on which
12305 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12306 value to be stored. SCRATCH is a scratch GPR. */
12309 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12312 enum machine_mode mode = GET_MODE (mem);
12313 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12315 emit_insn (gen_memory_barrier ());
12317 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12318 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12319 emit_label (XEXP (label1, 0));
12321 emit_load_locked (mode, retval, mem);
12323 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12324 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12326 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12327 emit_unlikely_jump (x, label2);
12329 emit_move_insn (scratch, newval);
12330 emit_store_conditional (mode, cond, mem, scratch);
12332 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12333 emit_unlikely_jump (x, label1);
12335 emit_insn (gen_isync ());
12336 emit_label (XEXP (label2, 0));
12339 /* Expand an atomic test and set operation. MEM is the memory on which
12340 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12343 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
12345 enum machine_mode mode = GET_MODE (mem);
12346 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12348 emit_insn (gen_memory_barrier ());
12350 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12351 emit_label (XEXP (label, 0));
12353 emit_load_locked (mode, retval, mem);
12354 emit_move_insn (scratch, val);
12355 emit_store_conditional (mode, cond, mem, scratch);
12357 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12358 emit_unlikely_jump (x, label);
12360 emit_insn (gen_isync ());
12364 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
12366 enum machine_mode mode = GET_MODE (mem);
12367 rtx addrSI, align, wdst, shift, mask;
12368 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
12369 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12371 /* Shift amount for subword relative to aligned word. */
12372 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
12373 shift = gen_reg_rtx (SImode);
12374 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12375 GEN_INT (shift_mask)));
12376 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12378 /* Shift and mask old value into position within word. */
12379 oldval = convert_modes (SImode, mode, oldval, 1);
12380 oldval = expand_binop (SImode, and_optab,
12381 oldval, GEN_INT (imask), NULL_RTX,
12382 1, OPTAB_LIB_WIDEN);
12383 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
12385 /* Shift and mask new value into position within word. */
12386 newval = convert_modes (SImode, mode, newval, 1);
12387 newval = expand_binop (SImode, and_optab,
12388 newval, GEN_INT (imask), NULL_RTX,
12389 1, OPTAB_LIB_WIDEN);
12390 emit_insn (gen_ashlsi3 (newval, newval, shift));
12392 /* Mask for insertion. */
12393 mask = gen_reg_rtx (SImode);
12394 emit_move_insn (mask, GEN_INT (imask));
12395 emit_insn (gen_ashlsi3 (mask, mask, shift));
12397 /* Address of aligned word containing subword. */
12398 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
12399 NULL_RTX, 1, OPTAB_LIB_WIDEN);
12400 mem = change_address (mem, SImode, align);
12401 set_mem_align (mem, 32);
12402 MEM_VOLATILE_P (mem) = 1;
12404 wdst = gen_reg_rtx (SImode);
12405 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
12406 oldval, newval, mem));
12408 emit_move_insn (dst, gen_lowpart (mode, wdst));
12412 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
12413 rtx oldval, rtx newval, rtx mem,
12416 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12418 emit_insn (gen_memory_barrier ());
12419 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12420 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12421 emit_label (XEXP (label1, 0));
12423 emit_load_locked (SImode, scratch, mem);
12425 /* Mask subword within loaded value for comparison with oldval.
12426 Use UNSPEC_AND to avoid clobber.*/
12427 emit_insn (gen_rtx_SET (SImode, dest,
12428 gen_rtx_UNSPEC (SImode,
12429 gen_rtvec (2, scratch, mask),
12432 x = gen_rtx_COMPARE (CCmode, dest, oldval);
12433 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12435 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12436 emit_unlikely_jump (x, label2);
12438 /* Clear subword within loaded value for insertion of new value. */
12439 emit_insn (gen_rtx_SET (SImode, scratch,
12440 gen_rtx_AND (SImode,
12441 gen_rtx_NOT (SImode, mask), scratch)));
12442 emit_insn (gen_iorsi3 (scratch, scratch, newval));
12443 emit_store_conditional (SImode, cond, mem, scratch);
12445 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12446 emit_unlikely_jump (x, label1);
12448 emit_insn (gen_isync ());
12449 emit_label (XEXP (label2, 0));
12453 /* Emit instructions to move SRC to DST. Called by splitters for
12454 multi-register moves. It will emit at most one instruction for
12455 each register that is accessed; that is, it won't emit li/lis pairs
12456 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12460 rs6000_split_multireg_move (rtx dst, rtx src)
12462 /* The register number of the first register being moved. */
12464 /* The mode that is to be moved. */
12465 enum machine_mode mode;
12466 /* The mode that the move is being done in, and its size. */
12467 enum machine_mode reg_mode;
12469 /* The number of registers that will be moved. */
12472 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12473 mode = GET_MODE (dst);
12474 nregs = hard_regno_nregs[reg][mode];
12475 if (FP_REGNO_P (reg))
12477 else if (ALTIVEC_REGNO_P (reg))
12478 reg_mode = V16QImode;
12480 reg_mode = word_mode;
12481 reg_mode_size = GET_MODE_SIZE (reg_mode);
12483 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
12485 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12487 /* Move register range backwards, if we might have destructive
12490 for (i = nregs - 1; i >= 0; i--)
12491 emit_insn (gen_rtx_SET (VOIDmode,
12492 simplify_gen_subreg (reg_mode, dst, mode,
12493 i * reg_mode_size),
12494 simplify_gen_subreg (reg_mode, src, mode,
12495 i * reg_mode_size)));
12501 bool used_update = false;
12503 if (MEM_P (src) && INT_REGNO_P (reg))
12507 if (GET_CODE (XEXP (src, 0)) == PRE_INC
12508 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
12511 breg = XEXP (XEXP (src, 0), 0);
12512 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
12513 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
12514 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
12515 emit_insn (TARGET_32BIT
12516 ? gen_addsi3 (breg, breg, delta_rtx)
12517 : gen_adddi3 (breg, breg, delta_rtx));
12518 src = replace_equiv_address (src, breg);
12520 else if (! rs6000_offsettable_memref_p (src))
12523 basereg = gen_rtx_REG (Pmode, reg);
12524 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
12525 src = replace_equiv_address (src, basereg);
12528 breg = XEXP (src, 0);
12529 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
12530 breg = XEXP (breg, 0);
12532 /* If the base register we are using to address memory is
12533 also a destination reg, then change that register last. */
12535 && REGNO (breg) >= REGNO (dst)
12536 && REGNO (breg) < REGNO (dst) + nregs)
12537 j = REGNO (breg) - REGNO (dst);
12540 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
12544 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
12545 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
12548 breg = XEXP (XEXP (dst, 0), 0);
12549 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
12550 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
12551 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
12553 /* We have to update the breg before doing the store.
12554 Use store with update, if available. */
12558 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
12559 emit_insn (TARGET_32BIT
12560 ? (TARGET_POWERPC64
12561 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
12562 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
12563 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
12564 used_update = true;
12567 emit_insn (TARGET_32BIT
12568 ? gen_addsi3 (breg, breg, delta_rtx)
12569 : gen_adddi3 (breg, breg, delta_rtx));
12570 dst = replace_equiv_address (dst, breg);
12573 gcc_assert (rs6000_offsettable_memref_p (dst));
12576 for (i = 0; i < nregs; i++)
12578 /* Calculate index to next subword. */
12583 /* If compiler already emitted move of first word by
12584 store with update, no need to do anything. */
12585 if (j == 0 && used_update)
12588 emit_insn (gen_rtx_SET (VOIDmode,
12589 simplify_gen_subreg (reg_mode, dst, mode,
12590 j * reg_mode_size),
12591 simplify_gen_subreg (reg_mode, src, mode,
12592 j * reg_mode_size)));
12598 /* This page contains routines that are used to determine what the
12599 function prologue and epilogue code will do and write them out. */
12601 /* Return the first fixed-point register that is required to be
12602 saved. 32 if none. */
12605 first_reg_to_save (void)
12609 /* Find lowest numbered live register. */
12610 for (first_reg = 13; first_reg <= 31; first_reg++)
12611 if (regs_ever_live[first_reg]
12612 && (! call_used_regs[first_reg]
12613 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12614 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12615 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12616 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12621 && current_function_uses_pic_offset_table
12622 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12623 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12629 /* Similar, for FP regs. */
12632 first_fp_reg_to_save (void)
12636 /* Find lowest numbered live register. */
12637 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12638 if (regs_ever_live[first_reg])
12644 /* Similar, for AltiVec regs. */
12647 first_altivec_reg_to_save (void)
12651 /* Stack frame remains as is unless we are in AltiVec ABI. */
12652 if (! TARGET_ALTIVEC_ABI)
12653 return LAST_ALTIVEC_REGNO + 1;
12655 /* Find lowest numbered live register. */
12656 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12657 if (regs_ever_live[i])
12663 /* Return a 32-bit mask of the AltiVec registers we need to set in
12664 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12665 the 32-bit word is 0. */
12667 static unsigned int
12668 compute_vrsave_mask (void)
12670 unsigned int i, mask = 0;
12672 /* First, find out if we use _any_ altivec registers. */
12673 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12674 if (regs_ever_live[i])
12675 mask |= ALTIVEC_REG_BIT (i);
12680 /* Next, remove the argument registers from the set. These must
12681 be in the VRSAVE mask set by the caller, so we don't need to add
12682 them in again. More importantly, the mask we compute here is
12683 used to generate CLOBBERs in the set_vrsave insn, and we do not
12684 wish the argument registers to die. */
12685 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12686 mask &= ~ALTIVEC_REG_BIT (i);
12688 /* Similarly, remove the return value from the set. */
12691 diddle_return_value (is_altivec_return_reg, &yes);
12693 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12699 /* For a very restricted set of circumstances, we can cut down the
12700 size of prologues/epilogues by calling our own save/restore-the-world
12704 compute_save_world_info (rs6000_stack_t *info_ptr)
12706 info_ptr->world_save_p = 1;
12707 info_ptr->world_save_p
12708 = (WORLD_SAVE_P (info_ptr)
12709 && DEFAULT_ABI == ABI_DARWIN
12710 && ! (current_function_calls_setjmp && flag_exceptions)
12711 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12712 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12713 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12714 && info_ptr->cr_save_p);
12716 /* This will not work in conjunction with sibcalls. Make sure there
12717 are none. (This check is expensive, but seldom executed.) */
12718 if (WORLD_SAVE_P (info_ptr))
12721 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12722 if ( GET_CODE (insn) == CALL_INSN
12723 && SIBLING_CALL_P (insn))
12725 info_ptr->world_save_p = 0;
12730 if (WORLD_SAVE_P (info_ptr))
12732 /* Even if we're not touching VRsave, make sure there's room on the
12733 stack for it, if it looks like we're calling SAVE_WORLD, which
12734 will attempt to save it. */
12735 info_ptr->vrsave_size = 4;
12737 /* "Save" the VRsave register too if we're saving the world. */
12738 if (info_ptr->vrsave_mask == 0)
12739 info_ptr->vrsave_mask = compute_vrsave_mask ();
12741 /* Because the Darwin register save/restore routines only handle
12742 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12744 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
12745 && (info_ptr->first_altivec_reg_save
12746 >= FIRST_SAVED_ALTIVEC_REGNO));
12753 is_altivec_return_reg (rtx reg, void *xyes)
12755 bool *yes = (bool *) xyes;
12756 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
12761 /* Calculate the stack information for the current function. This is
12762 complicated by having two separate calling sequences, the AIX calling
12763 sequence and the V.4 calling sequence.
12765 AIX (and Darwin/Mac OS X) stack frames look like:
12767 SP----> +---------------------------------------+
12768 | back chain to caller | 0 0
12769 +---------------------------------------+
12770 | saved CR | 4 8 (8-11)
12771 +---------------------------------------+
12773 +---------------------------------------+
12774 | reserved for compilers | 12 24
12775 +---------------------------------------+
12776 | reserved for binders | 16 32
12777 +---------------------------------------+
12778 | saved TOC pointer | 20 40
12779 +---------------------------------------+
12780 | Parameter save area (P) | 24 48
12781 +---------------------------------------+
12782 | Alloca space (A) | 24+P etc.
12783 +---------------------------------------+
12784 | Local variable space (L) | 24+P+A
12785 +---------------------------------------+
12786 | Float/int conversion temporary (X) | 24+P+A+L
12787 +---------------------------------------+
12788 | Save area for AltiVec registers (W) | 24+P+A+L+X
12789 +---------------------------------------+
12790 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12791 +---------------------------------------+
12792 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12793 +---------------------------------------+
12794 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12795 +---------------------------------------+
12796 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12797 +---------------------------------------+
12798 old SP->| back chain to caller's caller |
12799 +---------------------------------------+
12801 The required alignment for AIX configurations is two words (i.e., 8
12805 V.4 stack frames look like:
12807 SP----> +---------------------------------------+
12808 | back chain to caller | 0
12809 +---------------------------------------+
12810 | caller's saved LR | 4
12811 +---------------------------------------+
12812 | Parameter save area (P) | 8
12813 +---------------------------------------+
12814 | Alloca space (A) | 8+P
12815 +---------------------------------------+
12816 | Varargs save area (V) | 8+P+A
12817 +---------------------------------------+
12818 | Local variable space (L) | 8+P+A+V
12819 +---------------------------------------+
12820 | Float/int conversion temporary (X) | 8+P+A+V+L
12821 +---------------------------------------+
12822 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12823 +---------------------------------------+
12824 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12825 +---------------------------------------+
12826 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12827 +---------------------------------------+
12828 | SPE: area for 64-bit GP registers |
12829 +---------------------------------------+
12830 | SPE alignment padding |
12831 +---------------------------------------+
12832 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12833 +---------------------------------------+
12834 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12835 +---------------------------------------+
12836 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12837 +---------------------------------------+
12838 old SP->| back chain to caller's caller |
12839 +---------------------------------------+
12841 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12842 given. (But note below and in sysv4.h that we require only 8 and
12843 may round up the size of our stack frame anyways. The historical
12844 reason is early versions of powerpc-linux which didn't properly
12845 align the stack at program startup. A happy side-effect is that
12846 -mno-eabi libraries can be used with -meabi programs.)
12848 The EABI configuration defaults to the V.4 layout. However,
12849 the stack alignment requirements may differ. If -mno-eabi is not
12850 given, the required stack alignment is 8 bytes; if -mno-eabi is
12851 given, the required alignment is 16 bytes. (But see V.4 comment
12854 #ifndef ABI_STACK_BOUNDARY
12855 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12858 static rs6000_stack_t *
12859 rs6000_stack_info (void)
12861 static rs6000_stack_t info;
12862 rs6000_stack_t *info_ptr = &info;
12863 int reg_size = TARGET_32BIT ? 4 : 8;
12866 HOST_WIDE_INT non_fixed_size;
12868 memset (&info, 0, sizeof (info));
12872 /* Cache value so we don't rescan instruction chain over and over. */
12873 if (cfun->machine->insn_chain_scanned_p == 0)
12874 cfun->machine->insn_chain_scanned_p
12875 = spe_func_has_64bit_regs_p () + 1;
12876 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
12879 /* Select which calling sequence. */
12880 info_ptr->abi = DEFAULT_ABI;
12882 /* Calculate which registers need to be saved & save area size. */
12883 info_ptr->first_gp_reg_save = first_reg_to_save ();
12884 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12885 even if it currently looks like we won't. */
12886 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
12887 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12888 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
12889 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12890 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
12892 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
12894 /* For the SPE, we have an additional upper 32-bits on each GPR.
12895 Ideally we should save the entire 64-bits only when the upper
12896 half is used in SIMD instructions. Since we only record
12897 registers live (not the size they are used in), this proves
12898 difficult because we'd have to traverse the instruction chain at
12899 the right time, taking reload into account. This is a real pain,
12900 so we opt to save the GPRs in 64-bits always if but one register
12901 gets used in 64-bits. Otherwise, all the registers in the frame
12902 get saved in 32-bits.
12904 So... since when we save all GPRs (except the SP) in 64-bits, the
12905 traditional GP save area will be empty. */
12906 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12907 info_ptr->gp_size = 0;
12909 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12910 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12912 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12913 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12914 - info_ptr->first_altivec_reg_save);
12916 /* Does this function call anything? */
12917 info_ptr->calls_p = (! current_function_is_leaf
12918 || cfun->machine->ra_needs_full_frame);
12920 /* Determine if we need to save the link register. */
12921 if ((DEFAULT_ABI == ABI_AIX
12922 && current_function_profile
12923 && !TARGET_PROFILE_KERNEL)
12924 #ifdef TARGET_RELOCATABLE
12925 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12927 || (info_ptr->first_fp_reg_save != 64
12928 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
12929 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
12930 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
12931 || info_ptr->calls_p
12932 || rs6000_ra_ever_killed ())
12934 info_ptr->lr_save_p = 1;
12935 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
12938 /* Determine if we need to save the condition code registers. */
12939 if (regs_ever_live[CR2_REGNO]
12940 || regs_ever_live[CR3_REGNO]
12941 || regs_ever_live[CR4_REGNO])
12943 info_ptr->cr_save_p = 1;
12944 if (DEFAULT_ABI == ABI_V4)
12945 info_ptr->cr_size = reg_size;
12948 /* If the current function calls __builtin_eh_return, then we need
12949 to allocate stack space for registers that will hold data for
12950 the exception handler. */
12951 if (current_function_calls_eh_return)
12954 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12957 /* SPE saves EH registers in 64-bits. */
12958 ehrd_size = i * (TARGET_SPE_ABI
12959 && info_ptr->spe_64bit_regs_used != 0
12960 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
12965 /* Determine various sizes. */
12966 info_ptr->reg_size = reg_size;
12967 info_ptr->fixed_size = RS6000_SAVE_AREA;
12968 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
12969 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
12970 TARGET_ALTIVEC ? 16 : 8);
12971 if (FRAME_GROWS_DOWNWARD)
12972 info_ptr->vars_size
12973 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
12974 + info_ptr->parm_size,
12975 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
12976 - (info_ptr->fixed_size + info_ptr->vars_size
12977 + info_ptr->parm_size);
12979 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12980 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12982 info_ptr->spe_gp_size = 0;
12984 if (TARGET_ALTIVEC_ABI)
12985 info_ptr->vrsave_mask = compute_vrsave_mask ();
12987 info_ptr->vrsave_mask = 0;
12989 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
12990 info_ptr->vrsave_size = 4;
12992 info_ptr->vrsave_size = 0;
12994 compute_save_world_info (info_ptr);
12996 /* Calculate the offsets. */
12997 switch (DEFAULT_ABI)
13001 gcc_unreachable ();
13005 info_ptr->fp_save_offset = - info_ptr->fp_size;
13006 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13008 if (TARGET_ALTIVEC_ABI)
13010 info_ptr->vrsave_save_offset
13011 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
13013 /* Align stack so vector save area is on a quadword boundary. */
13014 if (info_ptr->altivec_size != 0)
13015 info_ptr->altivec_padding_size
13016 = 16 - (-info_ptr->vrsave_save_offset % 16);
13018 info_ptr->altivec_padding_size = 0;
13020 info_ptr->altivec_save_offset
13021 = info_ptr->vrsave_save_offset
13022 - info_ptr->altivec_padding_size
13023 - info_ptr->altivec_size;
13025 /* Adjust for AltiVec case. */
13026 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
13029 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
13030 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
13031 info_ptr->lr_save_offset = 2*reg_size;
13035 info_ptr->fp_save_offset = - info_ptr->fp_size;
13036 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13037 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
13039 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13041 /* Align stack so SPE GPR save area is aligned on a
13042 double-word boundary. */
13043 if (info_ptr->spe_gp_size != 0)
13044 info_ptr->spe_padding_size
13045 = 8 - (-info_ptr->cr_save_offset % 8);
13047 info_ptr->spe_padding_size = 0;
13049 info_ptr->spe_gp_save_offset
13050 = info_ptr->cr_save_offset
13051 - info_ptr->spe_padding_size
13052 - info_ptr->spe_gp_size;
13054 /* Adjust for SPE case. */
13055 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
13057 else if (TARGET_ALTIVEC_ABI)
13059 info_ptr->vrsave_save_offset
13060 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
13062 /* Align stack so vector save area is on a quadword boundary. */
13063 if (info_ptr->altivec_size != 0)
13064 info_ptr->altivec_padding_size
13065 = 16 - (-info_ptr->vrsave_save_offset % 16);
13067 info_ptr->altivec_padding_size = 0;
13069 info_ptr->altivec_save_offset
13070 = info_ptr->vrsave_save_offset
13071 - info_ptr->altivec_padding_size
13072 - info_ptr->altivec_size;
13074 /* Adjust for AltiVec case. */
13075 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
13078 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
13079 info_ptr->ehrd_offset -= ehrd_size;
13080 info_ptr->lr_save_offset = reg_size;
13084 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
13085 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
13086 + info_ptr->gp_size
13087 + info_ptr->altivec_size
13088 + info_ptr->altivec_padding_size
13089 + info_ptr->spe_gp_size
13090 + info_ptr->spe_padding_size
13092 + info_ptr->cr_size
13093 + info_ptr->vrsave_size,
13096 non_fixed_size = (info_ptr->vars_size
13097 + info_ptr->parm_size
13098 + info_ptr->save_size);
13100 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
13101 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
13103 /* Determine if we need to allocate any stack frame:
13105 For AIX we need to push the stack if a frame pointer is needed
13106 (because the stack might be dynamically adjusted), if we are
13107 debugging, if we make calls, or if the sum of fp_save, gp_save,
13108 and local variables are more than the space needed to save all
13109 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
13110 + 18*8 = 288 (GPR13 reserved).
13112 For V.4 we don't have the stack cushion that AIX uses, but assume
13113 that the debugger can handle stackless frames. */
13115 if (info_ptr->calls_p)
13116 info_ptr->push_p = 1;
13118 else if (DEFAULT_ABI == ABI_V4)
13119 info_ptr->push_p = non_fixed_size != 0;
13121 else if (frame_pointer_needed)
13122 info_ptr->push_p = 1;
13124 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
13125 info_ptr->push_p = 1;
13128 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
13130 /* Zero offsets if we're not saving those registers. */
13131 if (info_ptr->fp_size == 0)
13132 info_ptr->fp_save_offset = 0;
13134 if (info_ptr->gp_size == 0)
13135 info_ptr->gp_save_offset = 0;
13137 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
13138 info_ptr->altivec_save_offset = 0;
13140 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
13141 info_ptr->vrsave_save_offset = 0;
13143 if (! TARGET_SPE_ABI
13144 || info_ptr->spe_64bit_regs_used == 0
13145 || info_ptr->spe_gp_size == 0)
13146 info_ptr->spe_gp_save_offset = 0;
13148 if (! info_ptr->lr_save_p)
13149 info_ptr->lr_save_offset = 0;
13151 if (! info_ptr->cr_save_p)
13152 info_ptr->cr_save_offset = 0;
13157 /* Return true if the current function uses any GPRs in 64-bit SIMD
13161 spe_func_has_64bit_regs_p (void)
13165 /* Functions that save and restore all the call-saved registers will
13166 need to save/restore the registers in 64-bits. */
13167 if (current_function_calls_eh_return
13168 || current_function_calls_setjmp
13169 || current_function_has_nonlocal_goto)
13172 insns = get_insns ();
13174 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13180 /* FIXME: This should be implemented with attributes...
13182 (set_attr "spe64" "true")....then,
13183 if (get_spe64(insn)) return true;
13185 It's the only reliable way to do the stuff below. */
13187 i = PATTERN (insn);
13188 if (GET_CODE (i) == SET)
13190 enum machine_mode mode = GET_MODE (SET_SRC (i));
13192 if (SPE_VECTOR_MODE (mode))
13194 if (TARGET_E500_DOUBLE && mode == DFmode)
13204 debug_stack_info (rs6000_stack_t *info)
13206 const char *abi_string;
13209 info = rs6000_stack_info ();
13211 fprintf (stderr, "\nStack information for function %s:\n",
13212 ((current_function_decl && DECL_NAME (current_function_decl))
13213 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13218 default: abi_string = "Unknown"; break;
13219 case ABI_NONE: abi_string = "NONE"; break;
13220 case ABI_AIX: abi_string = "AIX"; break;
13221 case ABI_DARWIN: abi_string = "Darwin"; break;
13222 case ABI_V4: abi_string = "V.4"; break;
13225 fprintf (stderr, "\tABI = %5s\n", abi_string);
13227 if (TARGET_ALTIVEC_ABI)
13228 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13230 if (TARGET_SPE_ABI)
13231 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13233 if (info->first_gp_reg_save != 32)
13234 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13236 if (info->first_fp_reg_save != 64)
13237 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13239 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13240 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13241 info->first_altivec_reg_save);
13243 if (info->lr_save_p)
13244 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13246 if (info->cr_save_p)
13247 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13249 if (info->vrsave_mask)
13250 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13253 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13256 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13258 if (info->gp_save_offset)
13259 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13261 if (info->fp_save_offset)
13262 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13264 if (info->altivec_save_offset)
13265 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13266 info->altivec_save_offset);
13268 if (info->spe_gp_save_offset)
13269 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13270 info->spe_gp_save_offset);
13272 if (info->vrsave_save_offset)
13273 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13274 info->vrsave_save_offset);
13276 if (info->lr_save_offset)
13277 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13279 if (info->cr_save_offset)
13280 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13282 if (info->varargs_save_offset)
13283 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13285 if (info->total_size)
13286 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13289 if (info->vars_size)
13290 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13293 if (info->parm_size)
13294 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13296 if (info->fixed_size)
13297 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13300 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13302 if (info->spe_gp_size)
13303 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13306 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13308 if (info->altivec_size)
13309 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13311 if (info->vrsave_size)
13312 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13314 if (info->altivec_padding_size)
13315 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13316 info->altivec_padding_size);
13318 if (info->spe_padding_size)
13319 fprintf (stderr, "\tspe_padding_size = %5d\n",
13320 info->spe_padding_size);
13323 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13325 if (info->save_size)
13326 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13328 if (info->reg_size != 4)
13329 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13331 fprintf (stderr, "\n");
13335 rs6000_return_addr (int count, rtx frame)
13337 /* Currently we don't optimize very well between prolog and body
13338 code and for PIC code the code can be actually quite bad, so
13339 don't try to be too clever here. */
13340 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13342 cfun->machine->ra_needs_full_frame = 1;
13349 plus_constant (copy_to_reg
13350 (gen_rtx_MEM (Pmode,
13351 memory_address (Pmode, frame))),
13352 RETURN_ADDRESS_OFFSET)));
13355 cfun->machine->ra_need_lr = 1;
13356 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13359 /* Say whether a function is a candidate for sibcall handling or not.
13360 We do not allow indirect calls to be optimized into sibling calls.
13361 Also, we can't do it if there are any vector parameters; there's
13362 nowhere to put the VRsave code so it works; note that functions with
13363 vector parameters are required to have a prototype, so the argument
13364 type info must be available here. (The tail recursion case can work
13365 with vector parameters, but there's no way to distinguish here.) */
13367 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13372 if (TARGET_ALTIVEC_VRSAVE)
13374 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13375 type; type = TREE_CHAIN (type))
13377 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13381 if (DEFAULT_ABI == ABI_DARWIN
13382 || (*targetm.binds_local_p) (decl))
13384 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13386 if (!lookup_attribute ("longcall", attr_list)
13387 || lookup_attribute ("shortcall", attr_list))
13394 /* NULL if INSN insn is valid within a low-overhead loop.
13395 Otherwise return why doloop cannot be applied.
13396 PowerPC uses the COUNT register for branch on table instructions. */
13398 static const char *
13399 rs6000_invalid_within_doloop (rtx insn)
13402 return "Function call in the loop.";
13405 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
13406 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
13407 return "Computed branch in the loop.";
13413 rs6000_ra_ever_killed (void)
13419 if (current_function_is_thunk)
13422 /* regs_ever_live has LR marked as used if any sibcalls are present,
13423 but this should not force saving and restoring in the
13424 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13425 clobbers LR, so that is inappropriate. */
13427 /* Also, the prologue can generate a store into LR that
13428 doesn't really count, like this:
13431 bcl to set PIC register
13435 When we're called from the epilogue, we need to avoid counting
13436 this as a store. */
13438 push_topmost_sequence ();
13439 top = get_insns ();
13440 pop_topmost_sequence ();
13441 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13443 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13449 if (!SIBLING_CALL_P (insn))
13452 else if (find_regno_note (insn, REG_INC, LINK_REGISTER_REGNUM))
13454 else if (set_of (reg, insn) != NULL_RTX
13455 && !prologue_epilogue_contains (insn))
13462 /* Add a REG_MAYBE_DEAD note to the insn. */
13464 rs6000_maybe_dead (rtx insn)
13466 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13471 /* Emit instructions needed to load the TOC register.
13472 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13473 a constant pool; or for SVR4 -fpic. */
13476 rs6000_emit_load_toc_table (int fromprolog)
13479 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13481 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
13484 rtx lab, tmp1, tmp2, got, tempLR;
13486 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13487 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13489 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13491 got = rs6000_got_sym ();
13492 tmp1 = tmp2 = dest;
13495 tmp1 = gen_reg_rtx (Pmode);
13496 tmp2 = gen_reg_rtx (Pmode);
13498 tempLR = (fromprolog
13499 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13500 : gen_reg_rtx (Pmode));
13501 insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab));
13503 rs6000_maybe_dead (insn);
13504 insn = emit_move_insn (tmp1, tempLR);
13506 rs6000_maybe_dead (insn);
13507 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
13509 rs6000_maybe_dead (insn);
13510 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
13512 rs6000_maybe_dead (insn);
13514 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
13516 rtx tempLR = (fromprolog
13517 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13518 : gen_reg_rtx (Pmode));
13520 insn = emit_insn (gen_load_toc_v4_pic_si (tempLR));
13522 rs6000_maybe_dead (insn);
13523 insn = emit_move_insn (dest, tempLR);
13525 rs6000_maybe_dead (insn);
13527 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
13530 rtx tempLR = (fromprolog
13531 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13532 : gen_reg_rtx (Pmode));
13533 rtx temp0 = (fromprolog
13534 ? gen_rtx_REG (Pmode, 0)
13535 : gen_reg_rtx (Pmode));
13541 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13542 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13544 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
13545 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13547 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
13549 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
13550 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
13558 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13559 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
13560 emit_move_insn (dest, tempLR);
13561 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
13563 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
13565 rs6000_maybe_dead (insn);
13567 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
13569 /* This is for AIX code running in non-PIC ELF32. */
13572 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
13573 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13575 insn = emit_insn (gen_elf_high (dest, realsym));
13577 rs6000_maybe_dead (insn);
13578 insn = emit_insn (gen_elf_low (dest, dest, realsym));
13580 rs6000_maybe_dead (insn);
13584 gcc_assert (DEFAULT_ABI == ABI_AIX);
13587 insn = emit_insn (gen_load_toc_aix_si (dest));
13589 insn = emit_insn (gen_load_toc_aix_di (dest));
13591 rs6000_maybe_dead (insn);
13595 /* Emit instructions to restore the link register after determining where
13596 its value has been stored. */
13599 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
13601 rs6000_stack_t *info = rs6000_stack_info ();
13604 operands[0] = source;
13605 operands[1] = scratch;
13607 if (info->lr_save_p)
13609 rtx frame_rtx = stack_pointer_rtx;
13610 HOST_WIDE_INT sp_offset = 0;
13613 if (frame_pointer_needed
13614 || current_function_calls_alloca
13615 || info->total_size > 32767)
13617 tmp = gen_frame_mem (Pmode, frame_rtx);
13618 emit_move_insn (operands[1], tmp);
13619 frame_rtx = operands[1];
13621 else if (info->push_p)
13622 sp_offset = info->total_size;
13624 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13625 tmp = gen_frame_mem (Pmode, tmp);
13626 emit_move_insn (tmp, operands[0]);
13629 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13632 static GTY(()) int set = -1;
13635 get_TOC_alias_set (void)
13638 set = new_alias_set ();
13642 /* This returns nonzero if the current function uses the TOC. This is
13643 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13644 is generated by the ABI_V4 load_toc_* patterns. */
13651 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13654 rtx pat = PATTERN (insn);
13657 if (GET_CODE (pat) == PARALLEL)
13658 for (i = 0; i < XVECLEN (pat, 0); i++)
13660 rtx sub = XVECEXP (pat, 0, i);
13661 if (GET_CODE (sub) == USE)
13663 sub = XEXP (sub, 0);
13664 if (GET_CODE (sub) == UNSPEC
13665 && XINT (sub, 1) == UNSPEC_TOC)
13675 create_TOC_reference (rtx symbol)
13677 if (no_new_pseudos)
13678 regs_ever_live[TOC_REGISTER] = 1;
13679 return gen_rtx_PLUS (Pmode,
13680 gen_rtx_REG (Pmode, TOC_REGISTER),
13681 gen_rtx_CONST (Pmode,
13682 gen_rtx_MINUS (Pmode, symbol,
13683 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13686 /* If _Unwind_* has been called from within the same module,
13687 toc register is not guaranteed to be saved to 40(1) on function
13688 entry. Save it there in that case. */
13691 rs6000_aix_emit_builtin_unwind_init (void)
13694 rtx stack_top = gen_reg_rtx (Pmode);
13695 rtx opcode_addr = gen_reg_rtx (Pmode);
13696 rtx opcode = gen_reg_rtx (SImode);
13697 rtx tocompare = gen_reg_rtx (SImode);
13698 rtx no_toc_save_needed = gen_label_rtx ();
13700 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
13701 emit_move_insn (stack_top, mem);
13703 mem = gen_frame_mem (Pmode,
13704 gen_rtx_PLUS (Pmode, stack_top,
13705 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13706 emit_move_insn (opcode_addr, mem);
13707 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13708 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13709 : 0xE8410028, SImode));
13711 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13712 SImode, NULL_RTX, NULL_RTX,
13713 no_toc_save_needed);
13715 mem = gen_frame_mem (Pmode,
13716 gen_rtx_PLUS (Pmode, stack_top,
13717 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13718 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13719 emit_label (no_toc_save_needed);
13722 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
13723 and the change to the stack pointer. */
13726 rs6000_emit_stack_tie (void)
13728 rtx mem = gen_frame_mem (BLKmode,
13729 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
13731 emit_insn (gen_stack_tie (mem));
13734 /* Emit the correct code for allocating stack space, as insns.
13735 If COPY_R12, make sure a copy of the old frame is left in r12.
13736 The generated code may use hard register 0 as a temporary. */
13739 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
13742 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13743 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
13744 rtx todec = gen_int_mode (-size, Pmode);
13746 if (INTVAL (todec) != -size)
13748 warning (0, "stack frame too large");
13749 emit_insn (gen_trap ());
13753 if (current_function_limit_stack)
13755 if (REG_P (stack_limit_rtx)
13756 && REGNO (stack_limit_rtx) > 1
13757 && REGNO (stack_limit_rtx) <= 31)
13759 emit_insn (TARGET_32BIT
13760 ? gen_addsi3 (tmp_reg,
13763 : gen_adddi3 (tmp_reg,
13767 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13770 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
13772 && DEFAULT_ABI == ABI_V4)
13774 rtx toload = gen_rtx_CONST (VOIDmode,
13775 gen_rtx_PLUS (Pmode,
13779 emit_insn (gen_elf_high (tmp_reg, toload));
13780 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
13781 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13785 warning (0, "stack limit expression is not supported");
13788 if (copy_r12 || ! TARGET_UPDATE)
13789 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
13795 /* Need a note here so that try_split doesn't get confused. */
13796 if (get_last_insn () == NULL_RTX)
13797 emit_note (NOTE_INSN_DELETED);
13798 insn = emit_move_insn (tmp_reg, todec);
13799 try_split (PATTERN (insn), insn, 0);
13803 insn = emit_insn (TARGET_32BIT
13804 ? gen_movsi_update (stack_reg, stack_reg,
13806 : gen_movdi_di_update (stack_reg, stack_reg,
13807 todec, stack_reg));
13811 insn = emit_insn (TARGET_32BIT
13812 ? gen_addsi3 (stack_reg, stack_reg, todec)
13813 : gen_adddi3 (stack_reg, stack_reg, todec));
13814 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
13815 gen_rtx_REG (Pmode, 12));
13818 RTX_FRAME_RELATED_P (insn) = 1;
13820 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13821 gen_rtx_SET (VOIDmode, stack_reg,
13822 gen_rtx_PLUS (Pmode, stack_reg,
13827 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13828 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13829 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13830 deduce these equivalences by itself so it wasn't necessary to hold
13831 its hand so much. */
13834 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13835 rtx reg2, rtx rreg)
13839 /* copy_rtx will not make unique copies of registers, so we need to
13840 ensure we don't have unwanted sharing here. */
13842 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13845 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13847 real = copy_rtx (PATTERN (insn));
13849 if (reg2 != NULL_RTX)
13850 real = replace_rtx (real, reg2, rreg);
13852 real = replace_rtx (real, reg,
13853 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13854 STACK_POINTER_REGNUM),
13857 /* We expect that 'real' is either a SET or a PARALLEL containing
13858 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13859 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13861 if (GET_CODE (real) == SET)
13865 temp = simplify_rtx (SET_SRC (set));
13867 SET_SRC (set) = temp;
13868 temp = simplify_rtx (SET_DEST (set));
13870 SET_DEST (set) = temp;
13871 if (GET_CODE (SET_DEST (set)) == MEM)
13873 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13875 XEXP (SET_DEST (set), 0) = temp;
13882 gcc_assert (GET_CODE (real) == PARALLEL);
13883 for (i = 0; i < XVECLEN (real, 0); i++)
13884 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13886 rtx set = XVECEXP (real, 0, i);
13888 temp = simplify_rtx (SET_SRC (set));
13890 SET_SRC (set) = temp;
13891 temp = simplify_rtx (SET_DEST (set));
13893 SET_DEST (set) = temp;
13894 if (GET_CODE (SET_DEST (set)) == MEM)
13896 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13898 XEXP (SET_DEST (set), 0) = temp;
13900 RTX_FRAME_RELATED_P (set) = 1;
13905 real = spe_synthesize_frame_save (real);
13907 RTX_FRAME_RELATED_P (insn) = 1;
13908 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13913 /* Given an SPE frame note, return a PARALLEL of SETs with the
13914 original note, plus a synthetic register save. */
13917 spe_synthesize_frame_save (rtx real)
13919 rtx synth, offset, reg, real2;
13921 if (GET_CODE (real) != SET
13922 || GET_MODE (SET_SRC (real)) != V2SImode)
13925 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13926 frame related note. The parallel contains a set of the register
13927 being saved, and another set to a synthetic register (n+1200).
13928 This is so we can differentiate between 64-bit and 32-bit saves.
13929 Words cannot describe this nastiness. */
13931 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
13932 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
13933 && GET_CODE (SET_SRC (real)) == REG);
13936 (set (mem (plus (reg x) (const y)))
13939 (set (mem (plus (reg x) (const y+4)))
13943 real2 = copy_rtx (real);
13944 PUT_MODE (SET_DEST (real2), SImode);
13945 reg = SET_SRC (real2);
13946 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
13947 synth = copy_rtx (real2);
13949 if (BYTES_BIG_ENDIAN)
13951 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
13952 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
13955 reg = SET_SRC (synth);
13957 synth = replace_rtx (synth, reg,
13958 gen_rtx_REG (SImode, REGNO (reg) + 1200));
13960 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
13961 synth = replace_rtx (synth, offset,
13962 GEN_INT (INTVAL (offset)
13963 + (BYTES_BIG_ENDIAN ? 0 : 4)));
13965 RTX_FRAME_RELATED_P (synth) = 1;
13966 RTX_FRAME_RELATED_P (real2) = 1;
13967 if (BYTES_BIG_ENDIAN)
13968 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
13970 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
13975 /* Returns an insn that has a vrsave set operation with the
13976 appropriate CLOBBERs. */
13979 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
13982 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
13983 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13986 = gen_rtx_SET (VOIDmode,
13988 gen_rtx_UNSPEC_VOLATILE (SImode,
13989 gen_rtvec (2, reg, vrsave),
13990 UNSPECV_SET_VRSAVE));
13994 /* We need to clobber the registers in the mask so the scheduler
13995 does not move sets to VRSAVE before sets of AltiVec registers.
13997 However, if the function receives nonlocal gotos, reload will set
13998 all call saved registers live. We will end up with:
14000 (set (reg 999) (mem))
14001 (parallel [ (set (reg vrsave) (unspec blah))
14002 (clobber (reg 999))])
14004 The clobber will cause the store into reg 999 to be dead, and
14005 flow will attempt to delete an epilogue insn. In this case, we
14006 need an unspec use/set of the register. */
14008 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14009 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14011 if (!epiloguep || call_used_regs [i])
14012 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
14013 gen_rtx_REG (V4SImode, i));
14016 rtx reg = gen_rtx_REG (V4SImode, i);
14019 = gen_rtx_SET (VOIDmode,
14021 gen_rtx_UNSPEC (V4SImode,
14022 gen_rtvec (1, reg), 27));
14026 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
14028 for (i = 0; i < nclobs; ++i)
14029 XVECEXP (insn, 0, i) = clobs[i];
14034 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
14035 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
14038 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
14039 unsigned int regno, int offset, HOST_WIDE_INT total_size)
14041 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
14042 rtx replacea, replaceb;
14044 int_rtx = GEN_INT (offset);
14046 /* Some cases that need register indexed addressing. */
14047 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
14048 || (TARGET_E500_DOUBLE && mode == DFmode)
14050 && SPE_VECTOR_MODE (mode)
14051 && !SPE_CONST_OFFSET_OK (offset)))
14053 /* Whomever calls us must make sure r11 is available in the
14054 flow path of instructions in the prologue. */
14055 offset_rtx = gen_rtx_REG (Pmode, 11);
14056 emit_move_insn (offset_rtx, int_rtx);
14058 replacea = offset_rtx;
14059 replaceb = int_rtx;
14063 offset_rtx = int_rtx;
14064 replacea = NULL_RTX;
14065 replaceb = NULL_RTX;
14068 reg = gen_rtx_REG (mode, regno);
14069 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
14070 mem = gen_frame_mem (mode, addr);
14072 insn = emit_move_insn (mem, reg);
14074 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
14077 /* Emit an offset memory reference suitable for a frame store, while
14078 converting to a valid addressing mode. */
14081 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
14083 rtx int_rtx, offset_rtx;
14085 int_rtx = GEN_INT (offset);
14087 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
14088 || (TARGET_E500_DOUBLE && mode == DFmode))
14090 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14091 emit_move_insn (offset_rtx, int_rtx);
14094 offset_rtx = int_rtx;
14096 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
14099 /* Look for user-defined global regs. We should not save and restore these,
14100 and cannot use stmw/lmw if there are any in its range. */
14103 no_global_regs_above (int first_greg)
14106 for (i = 0; i < 32 - first_greg; i++)
14107 if (global_regs[first_greg + i])
14112 #ifndef TARGET_FIX_AND_CONTINUE
14113 #define TARGET_FIX_AND_CONTINUE 0
14116 /* Emit function prologue as insns. */
14119 rs6000_emit_prologue (void)
14121 rs6000_stack_t *info = rs6000_stack_info ();
14122 enum machine_mode reg_mode = Pmode;
14123 int reg_size = TARGET_32BIT ? 4 : 8;
14124 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14125 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
14126 rtx frame_reg_rtx = sp_reg_rtx;
14127 rtx cr_save_rtx = NULL_RTX;
14129 int saving_FPRs_inline;
14130 int using_store_multiple;
14131 HOST_WIDE_INT sp_offset = 0;
14133 if (TARGET_FIX_AND_CONTINUE)
14135 /* gdb on darwin arranges to forward a function from the old
14136 address by modifying the first 5 instructions of the function
14137 to branch to the overriding function. This is necessary to
14138 permit function pointers that point to the old function to
14139 actually forward to the new function. */
14140 emit_insn (gen_nop ());
14141 emit_insn (gen_nop ());
14142 emit_insn (gen_nop ());
14143 emit_insn (gen_nop ());
14144 emit_insn (gen_nop ());
14147 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14149 reg_mode = V2SImode;
14153 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14154 && (!TARGET_SPE_ABI
14155 || info->spe_64bit_regs_used == 0)
14156 && info->first_gp_reg_save < 31
14157 && no_global_regs_above (info->first_gp_reg_save));
14158 saving_FPRs_inline = (info->first_fp_reg_save == 64
14159 || FP_SAVE_INLINE (info->first_fp_reg_save)
14160 || current_function_calls_eh_return
14161 || cfun->machine->ra_need_lr);
14163 /* For V.4, update stack before we do any saving and set back pointer. */
14165 && (DEFAULT_ABI == ABI_V4
14166 || current_function_calls_eh_return))
14168 if (info->total_size < 32767)
14169 sp_offset = info->total_size;
14171 frame_reg_rtx = frame_ptr_rtx;
14172 rs6000_emit_allocate_stack (info->total_size,
14173 (frame_reg_rtx != sp_reg_rtx
14174 && (info->cr_save_p
14176 || info->first_fp_reg_save < 64
14177 || info->first_gp_reg_save < 32
14179 if (frame_reg_rtx != sp_reg_rtx)
14180 rs6000_emit_stack_tie ();
14183 /* Handle world saves specially here. */
14184 if (WORLD_SAVE_P (info))
14190 /* save_world expects lr in r0. */
14191 if (info->lr_save_p)
14193 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14194 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14195 RTX_FRAME_RELATED_P (insn) = 1;
14198 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14199 assumptions about the offsets of various bits of the stack
14201 gcc_assert (info->gp_save_offset == -220
14202 && info->fp_save_offset == -144
14203 && info->lr_save_offset == 8
14204 && info->cr_save_offset == 4
14207 && (!current_function_calls_eh_return
14208 || info->ehrd_offset == -432)
14209 && info->vrsave_save_offset == -224
14210 && info->altivec_save_offset == (-224 -16 -192));
14212 treg = gen_rtx_REG (SImode, 11);
14213 emit_move_insn (treg, GEN_INT (-info->total_size));
14215 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14216 in R11. It also clobbers R12, so beware! */
14218 /* Preserve CR2 for save_world prologues */
14220 sz += 32 - info->first_gp_reg_save;
14221 sz += 64 - info->first_fp_reg_save;
14222 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14223 p = rtvec_alloc (sz);
14225 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14226 gen_rtx_REG (Pmode,
14227 LINK_REGISTER_REGNUM));
14228 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14229 gen_rtx_SYMBOL_REF (Pmode,
14231 /* We do floats first so that the instruction pattern matches
14233 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14235 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14236 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14237 GEN_INT (info->fp_save_offset
14238 + sp_offset + 8 * i));
14239 rtx mem = gen_frame_mem (DFmode, addr);
14241 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14243 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14245 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14246 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14247 GEN_INT (info->altivec_save_offset
14248 + sp_offset + 16 * i));
14249 rtx mem = gen_frame_mem (V4SImode, addr);
14251 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14253 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14255 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14256 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14257 GEN_INT (info->gp_save_offset
14258 + sp_offset + reg_size * i));
14259 rtx mem = gen_frame_mem (reg_mode, addr);
14261 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14265 /* CR register traditionally saved as CR2. */
14266 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14267 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14268 GEN_INT (info->cr_save_offset
14270 rtx mem = gen_frame_mem (reg_mode, addr);
14272 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14274 /* Prevent any attempt to delete the setting of r0 and treg! */
14275 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
14276 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
14277 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
14279 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14280 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14281 NULL_RTX, NULL_RTX);
14283 if (current_function_calls_eh_return)
14288 unsigned int regno = EH_RETURN_DATA_REGNO (i);
14289 if (regno == INVALID_REGNUM)
14291 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14292 info->ehrd_offset + sp_offset
14293 + reg_size * (int) i,
14299 /* Save AltiVec registers if needed. */
14300 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14304 /* There should be a non inline version of this, for when we
14305 are saving lots of vector registers. */
14306 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14307 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14309 rtx areg, savereg, mem;
14312 offset = info->altivec_save_offset + sp_offset
14313 + 16 * (i - info->first_altivec_reg_save);
14315 savereg = gen_rtx_REG (V4SImode, i);
14317 areg = gen_rtx_REG (Pmode, 0);
14318 emit_move_insn (areg, GEN_INT (offset));
14320 /* AltiVec addressing mode is [reg+reg]. */
14321 mem = gen_frame_mem (V4SImode,
14322 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
14324 insn = emit_move_insn (mem, savereg);
14326 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14327 areg, GEN_INT (offset));
14331 /* VRSAVE is a bit vector representing which AltiVec registers
14332 are used. The OS uses this to determine which vector
14333 registers to save on a context switch. We need to save
14334 VRSAVE on the stack frame, add whatever AltiVec registers we
14335 used in this function, and do the corresponding magic in the
14338 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14339 && info->vrsave_mask != 0)
14341 rtx reg, mem, vrsave;
14344 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14345 as frame_reg_rtx and r11 as the static chain pointer for
14346 nested functions. */
14347 reg = gen_rtx_REG (SImode, 0);
14348 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14350 emit_insn (gen_get_vrsave_internal (reg));
14352 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14354 if (!WORLD_SAVE_P (info))
14357 offset = info->vrsave_save_offset + sp_offset;
14358 mem = gen_frame_mem (SImode,
14359 gen_rtx_PLUS (Pmode, frame_reg_rtx,
14360 GEN_INT (offset)));
14361 insn = emit_move_insn (mem, reg);
14364 /* Include the registers in the mask. */
14365 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14367 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14370 /* If we use the link register, get it into r0. */
14371 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14373 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14374 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14375 RTX_FRAME_RELATED_P (insn) = 1;
14378 /* If we need to save CR, put it into r12. */
14379 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14383 cr_save_rtx = gen_rtx_REG (SImode, 12);
14384 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14385 RTX_FRAME_RELATED_P (insn) = 1;
14386 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14387 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14388 But that's OK. All we have to do is specify that _one_ condition
14389 code register is saved in this stack slot. The thrower's epilogue
14390 will then restore all the call-saved registers.
14391 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14392 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14393 gen_rtx_REG (SImode, CR2_REGNO));
14394 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14399 /* Do any required saving of fpr's. If only one or two to save, do
14400 it ourselves. Otherwise, call function. */
14401 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14404 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14405 if ((regs_ever_live[info->first_fp_reg_save+i]
14406 && ! call_used_regs[info->first_fp_reg_save+i]))
14407 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14408 info->first_fp_reg_save + i,
14409 info->fp_save_offset + sp_offset + 8 * i,
14412 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14416 const char *alloc_rname;
14418 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14420 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14421 gen_rtx_REG (Pmode,
14422 LINK_REGISTER_REGNUM));
14423 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14424 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14425 alloc_rname = ggc_strdup (rname);
14426 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14427 gen_rtx_SYMBOL_REF (Pmode,
14429 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14431 rtx addr, reg, mem;
14432 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14433 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14434 GEN_INT (info->fp_save_offset
14435 + sp_offset + 8*i));
14436 mem = gen_frame_mem (DFmode, addr);
14438 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14440 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14441 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14442 NULL_RTX, NULL_RTX);
14445 /* Save GPRs. This is done as a PARALLEL if we are using
14446 the store-multiple instructions. */
14447 if (!WORLD_SAVE_P (info) && using_store_multiple)
14451 p = rtvec_alloc (32 - info->first_gp_reg_save);
14452 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14454 rtx addr, reg, mem;
14455 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14456 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14457 GEN_INT (info->gp_save_offset
14460 mem = gen_frame_mem (reg_mode, addr);
14462 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14464 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14465 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14466 NULL_RTX, NULL_RTX);
14468 else if (!WORLD_SAVE_P (info))
14471 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14472 if ((regs_ever_live[info->first_gp_reg_save + i]
14473 && (!call_used_regs[info->first_gp_reg_save + i]
14474 || (i + info->first_gp_reg_save
14475 == RS6000_PIC_OFFSET_TABLE_REGNUM
14476 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14477 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14478 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14479 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14481 rtx addr, reg, mem;
14482 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14484 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14486 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14489 if (!SPE_CONST_OFFSET_OK (offset))
14491 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14492 emit_move_insn (b, GEN_INT (offset));
14495 b = GEN_INT (offset);
14497 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14498 mem = gen_frame_mem (V2SImode, addr);
14499 insn = emit_move_insn (mem, reg);
14501 if (GET_CODE (b) == CONST_INT)
14502 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14503 NULL_RTX, NULL_RTX);
14505 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14506 b, GEN_INT (offset));
14510 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14511 GEN_INT (info->gp_save_offset
14514 mem = gen_frame_mem (reg_mode, addr);
14516 insn = emit_move_insn (mem, reg);
14517 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14518 NULL_RTX, NULL_RTX);
14523 /* ??? There's no need to emit actual instructions here, but it's the
14524 easiest way to get the frame unwind information emitted. */
14525 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
14527 unsigned int i, regno;
14529 /* In AIX ABI we need to pretend we save r2 here. */
14532 rtx addr, reg, mem;
14534 reg = gen_rtx_REG (reg_mode, 2);
14535 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14536 GEN_INT (sp_offset + 5 * reg_size));
14537 mem = gen_frame_mem (reg_mode, addr);
14539 insn = emit_move_insn (mem, reg);
14540 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14541 NULL_RTX, NULL_RTX);
14542 PATTERN (insn) = gen_blockage ();
14547 regno = EH_RETURN_DATA_REGNO (i);
14548 if (regno == INVALID_REGNUM)
14551 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14552 info->ehrd_offset + sp_offset
14553 + reg_size * (int) i,
14558 /* Save lr if we used it. */
14559 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14561 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14562 GEN_INT (info->lr_save_offset + sp_offset));
14563 rtx reg = gen_rtx_REG (Pmode, 0);
14564 rtx mem = gen_rtx_MEM (Pmode, addr);
14565 /* This should not be of frame_alias_set, because of
14566 __builtin_return_address. */
14568 insn = emit_move_insn (mem, reg);
14569 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14570 NULL_RTX, NULL_RTX);
14573 /* Save CR if we use any that must be preserved. */
14574 if (!WORLD_SAVE_P (info) && info->cr_save_p)
14576 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14577 GEN_INT (info->cr_save_offset + sp_offset));
14578 rtx mem = gen_frame_mem (SImode, addr);
14579 /* See the large comment above about why CR2_REGNO is used. */
14580 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
14582 /* If r12 was used to hold the original sp, copy cr into r0 now
14584 if (REGNO (frame_reg_rtx) == 12)
14588 cr_save_rtx = gen_rtx_REG (SImode, 0);
14589 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14590 RTX_FRAME_RELATED_P (insn) = 1;
14591 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
14592 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14597 insn = emit_move_insn (mem, cr_save_rtx);
14599 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14600 NULL_RTX, NULL_RTX);
14603 /* Update stack and set back pointer unless this is V.4,
14604 for which it was done previously. */
14605 if (!WORLD_SAVE_P (info) && info->push_p
14606 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
14607 rs6000_emit_allocate_stack (info->total_size, FALSE);
14609 /* Set frame pointer, if needed. */
14610 if (frame_pointer_needed)
14612 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
14614 RTX_FRAME_RELATED_P (insn) = 1;
14617 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14618 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
14619 || (DEFAULT_ABI == ABI_V4
14620 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
14621 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
14623 /* If emit_load_toc_table will use the link register, we need to save
14624 it. We use R12 for this purpose because emit_load_toc_table
14625 can use register 0. This allows us to use a plain 'blr' to return
14626 from the procedure more often. */
14627 int save_LR_around_toc_setup = (TARGET_ELF
14628 && DEFAULT_ABI != ABI_AIX
14630 && ! info->lr_save_p
14631 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
14632 if (save_LR_around_toc_setup)
14634 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14636 insn = emit_move_insn (frame_ptr_rtx, lr);
14637 rs6000_maybe_dead (insn);
14638 RTX_FRAME_RELATED_P (insn) = 1;
14640 rs6000_emit_load_toc_table (TRUE);
14642 insn = emit_move_insn (lr, frame_ptr_rtx);
14643 rs6000_maybe_dead (insn);
14644 RTX_FRAME_RELATED_P (insn) = 1;
14647 rs6000_emit_load_toc_table (TRUE);
14651 if (DEFAULT_ABI == ABI_DARWIN
14652 && flag_pic && current_function_uses_pic_offset_table)
14654 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14655 rtx src = machopic_function_base_sym ();
14657 /* Save and restore LR locally around this call (in R0). */
14658 if (!info->lr_save_p)
14659 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr));
14661 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14663 insn = emit_move_insn (gen_rtx_REG (Pmode,
14664 RS6000_PIC_OFFSET_TABLE_REGNUM),
14666 rs6000_maybe_dead (insn);
14668 if (!info->lr_save_p)
14669 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0)));
14674 /* Write function prologue. */
14677 rs6000_output_function_prologue (FILE *file,
14678 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14680 rs6000_stack_t *info = rs6000_stack_info ();
14682 if (TARGET_DEBUG_STACK)
14683 debug_stack_info (info);
14685 /* Write .extern for any function we will call to save and restore
14687 if (info->first_fp_reg_save < 64
14688 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14689 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14690 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14691 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14692 RESTORE_FP_SUFFIX);
14694 /* Write .extern for AIX common mode routines, if needed. */
14695 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14697 fputs ("\t.extern __mulh\n", file);
14698 fputs ("\t.extern __mull\n", file);
14699 fputs ("\t.extern __divss\n", file);
14700 fputs ("\t.extern __divus\n", file);
14701 fputs ("\t.extern __quoss\n", file);
14702 fputs ("\t.extern __quous\n", file);
14703 common_mode_defined = 1;
14706 if (! HAVE_prologue)
14710 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14711 the "toplevel" insn chain. */
14712 emit_note (NOTE_INSN_DELETED);
14713 rs6000_emit_prologue ();
14714 emit_note (NOTE_INSN_DELETED);
14716 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14720 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14722 INSN_ADDRESSES_NEW (insn, addr);
14727 if (TARGET_DEBUG_STACK)
14728 debug_rtx_list (get_insns (), 100);
14729 final (get_insns (), file, FALSE);
14733 rs6000_pic_labelno++;
14736 /* Emit function epilogue as insns.
14738 At present, dwarf2out_frame_debug_expr doesn't understand
14739 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14740 anywhere in the epilogue. Most of the insns below would in any case
14741 need special notes to explain where r11 is in relation to the stack. */
14744 rs6000_emit_epilogue (int sibcall)
14746 rs6000_stack_t *info;
14747 int restoring_FPRs_inline;
14748 int using_load_multiple;
14749 int using_mfcr_multiple;
14750 int use_backchain_to_restore_sp;
14752 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
14753 rtx frame_reg_rtx = sp_reg_rtx;
14754 enum machine_mode reg_mode = Pmode;
14755 int reg_size = TARGET_32BIT ? 4 : 8;
14758 info = rs6000_stack_info ();
14760 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14762 reg_mode = V2SImode;
14766 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14767 && (!TARGET_SPE_ABI
14768 || info->spe_64bit_regs_used == 0)
14769 && info->first_gp_reg_save < 31
14770 && no_global_regs_above (info->first_gp_reg_save));
14771 restoring_FPRs_inline = (sibcall
14772 || current_function_calls_eh_return
14773 || info->first_fp_reg_save == 64
14774 || FP_SAVE_INLINE (info->first_fp_reg_save));
14775 use_backchain_to_restore_sp = (frame_pointer_needed
14776 || current_function_calls_alloca
14777 || info->total_size > 32767);
14778 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
14779 || rs6000_cpu == PROCESSOR_PPC603
14780 || rs6000_cpu == PROCESSOR_PPC750
14783 if (WORLD_SAVE_P (info))
14787 const char *alloc_rname;
14790 /* eh_rest_world_r10 will return to the location saved in the LR
14791 stack slot (which is not likely to be our caller.)
14792 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14793 rest_world is similar, except any R10 parameter is ignored.
14794 The exception-handling stuff that was here in 2.95 is no
14795 longer necessary. */
14799 + 32 - info->first_gp_reg_save
14800 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
14801 + 63 + 1 - info->first_fp_reg_save);
14803 strcpy (rname, ((current_function_calls_eh_return) ?
14804 "*eh_rest_world_r10" : "*rest_world"));
14805 alloc_rname = ggc_strdup (rname);
14808 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
14809 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14810 gen_rtx_REG (Pmode,
14811 LINK_REGISTER_REGNUM));
14813 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
14814 /* The instruction pattern requires a clobber here;
14815 it is shared with the restVEC helper. */
14817 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14820 /* CR register traditionally saved as CR2. */
14821 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14822 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14823 GEN_INT (info->cr_save_offset));
14824 rtx mem = gen_frame_mem (reg_mode, addr);
14826 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14829 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14831 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14832 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14833 GEN_INT (info->gp_save_offset
14835 rtx mem = gen_frame_mem (reg_mode, addr);
14837 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14839 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14841 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14842 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14843 GEN_INT (info->altivec_save_offset
14845 rtx mem = gen_frame_mem (V4SImode, addr);
14847 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14849 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14851 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14852 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14853 GEN_INT (info->fp_save_offset
14855 rtx mem = gen_frame_mem (DFmode, addr);
14857 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14860 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
14862 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
14864 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
14866 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
14868 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
14869 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14874 /* If we have a frame pointer, a call to alloca, or a large stack
14875 frame, restore the old stack pointer using the backchain. Otherwise,
14876 we know what size to update it with. */
14877 if (use_backchain_to_restore_sp)
14879 /* Under V.4, don't reset the stack pointer until after we're done
14880 loading the saved registers. */
14881 if (DEFAULT_ABI == ABI_V4)
14882 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
14884 emit_move_insn (frame_reg_rtx,
14885 gen_rtx_MEM (Pmode, sp_reg_rtx));
14887 else if (info->push_p)
14889 if (DEFAULT_ABI == ABI_V4
14890 || current_function_calls_eh_return)
14891 sp_offset = info->total_size;
14894 emit_insn (TARGET_32BIT
14895 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14896 GEN_INT (info->total_size))
14897 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14898 GEN_INT (info->total_size)));
14902 /* Restore AltiVec registers if needed. */
14903 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14907 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14908 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14910 rtx addr, areg, mem;
14912 areg = gen_rtx_REG (Pmode, 0);
14914 (areg, GEN_INT (info->altivec_save_offset
14916 + 16 * (i - info->first_altivec_reg_save)));
14918 /* AltiVec addressing mode is [reg+reg]. */
14919 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14920 mem = gen_frame_mem (V4SImode, addr);
14922 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14926 /* Restore VRSAVE if needed. */
14927 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14928 && info->vrsave_mask != 0)
14930 rtx addr, mem, reg;
14932 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14933 GEN_INT (info->vrsave_save_offset + sp_offset));
14934 mem = gen_frame_mem (SImode, addr);
14935 reg = gen_rtx_REG (SImode, 12);
14936 emit_move_insn (reg, mem);
14938 emit_insn (generate_set_vrsave (reg, info, 1));
14941 /* Get the old lr if we saved it. */
14942 if (info->lr_save_p)
14944 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
14945 info->lr_save_offset + sp_offset);
14947 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
14950 /* Get the old cr if we saved it. */
14951 if (info->cr_save_p)
14953 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14954 GEN_INT (info->cr_save_offset + sp_offset));
14955 rtx mem = gen_frame_mem (SImode, addr);
14957 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
14960 /* Set LR here to try to overlap restores below. */
14961 if (info->lr_save_p)
14962 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
14963 gen_rtx_REG (Pmode, 0));
14965 /* Load exception handler data registers, if needed. */
14966 if (current_function_calls_eh_return)
14968 unsigned int i, regno;
14972 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14973 GEN_INT (sp_offset + 5 * reg_size));
14974 rtx mem = gen_frame_mem (reg_mode, addr);
14976 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
14983 regno = EH_RETURN_DATA_REGNO (i);
14984 if (regno == INVALID_REGNUM)
14987 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
14988 info->ehrd_offset + sp_offset
14989 + reg_size * (int) i);
14991 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
14995 /* Restore GPRs. This is done as a PARALLEL if we are using
14996 the load-multiple instructions. */
14997 if (using_load_multiple)
15000 p = rtvec_alloc (32 - info->first_gp_reg_save);
15001 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15003 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15004 GEN_INT (info->gp_save_offset
15007 rtx mem = gen_frame_mem (reg_mode, addr);
15010 gen_rtx_SET (VOIDmode,
15011 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15014 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15017 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15018 if ((regs_ever_live[info->first_gp_reg_save + i]
15019 && (!call_used_regs[info->first_gp_reg_save + i]
15020 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
15021 && TARGET_TOC && TARGET_MINIMAL_TOC)))
15022 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
15023 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
15024 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
15026 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15027 GEN_INT (info->gp_save_offset
15030 rtx mem = gen_frame_mem (reg_mode, addr);
15032 /* Restore 64-bit quantities for SPE. */
15033 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15035 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
15038 if (!SPE_CONST_OFFSET_OK (offset))
15040 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
15041 emit_move_insn (b, GEN_INT (offset));
15044 b = GEN_INT (offset);
15046 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
15047 mem = gen_frame_mem (V2SImode, addr);
15050 emit_move_insn (gen_rtx_REG (reg_mode,
15051 info->first_gp_reg_save + i), mem);
15054 /* Restore fpr's if we need to do it without calling a function. */
15055 if (restoring_FPRs_inline)
15056 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15057 if ((regs_ever_live[info->first_fp_reg_save+i]
15058 && ! call_used_regs[info->first_fp_reg_save+i]))
15061 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15062 GEN_INT (info->fp_save_offset
15065 mem = gen_frame_mem (DFmode, addr);
15067 emit_move_insn (gen_rtx_REG (DFmode,
15068 info->first_fp_reg_save + i),
15072 /* If we saved cr, restore it here. Just those that were used. */
15073 if (info->cr_save_p)
15075 rtx r12_rtx = gen_rtx_REG (SImode, 12);
15078 if (using_mfcr_multiple)
15080 for (i = 0; i < 8; i++)
15081 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15083 gcc_assert (count);
15086 if (using_mfcr_multiple && count > 1)
15091 p = rtvec_alloc (count);
15094 for (i = 0; i < 8; i++)
15095 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15097 rtvec r = rtvec_alloc (2);
15098 RTVEC_ELT (r, 0) = r12_rtx;
15099 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
15100 RTVEC_ELT (p, ndx) =
15101 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
15102 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
15105 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15106 gcc_assert (ndx == count);
15109 for (i = 0; i < 8; i++)
15110 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15112 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
15118 /* If this is V.4, unwind the stack pointer after all of the loads
15120 if (frame_reg_rtx != sp_reg_rtx)
15122 /* This blockage is needed so that sched doesn't decide to move
15123 the sp change before the register restores. */
15124 rs6000_emit_stack_tie ();
15125 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15127 else if (sp_offset != 0)
15128 emit_insn (TARGET_32BIT
15129 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15130 GEN_INT (sp_offset))
15131 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15132 GEN_INT (sp_offset)));
15134 if (current_function_calls_eh_return)
15136 rtx sa = EH_RETURN_STACKADJ_RTX;
15137 emit_insn (TARGET_32BIT
15138 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
15139 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
15145 if (! restoring_FPRs_inline)
15146 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
15148 p = rtvec_alloc (2);
15150 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15151 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15152 gen_rtx_REG (Pmode,
15153 LINK_REGISTER_REGNUM));
15155 /* If we have to restore more than two FP registers, branch to the
15156 restore function. It will return to our caller. */
15157 if (! restoring_FPRs_inline)
15161 const char *alloc_rname;
15163 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15164 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15165 alloc_rname = ggc_strdup (rname);
15166 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15167 gen_rtx_SYMBOL_REF (Pmode,
15170 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15173 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15174 GEN_INT (info->fp_save_offset + 8*i));
15175 mem = gen_frame_mem (DFmode, addr);
15177 RTVEC_ELT (p, i+3) =
15178 gen_rtx_SET (VOIDmode,
15179 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15184 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15188 /* Write function epilogue. */
15191 rs6000_output_function_epilogue (FILE *file,
15192 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15194 if (! HAVE_epilogue)
15196 rtx insn = get_last_insn ();
15197 /* If the last insn was a BARRIER, we don't have to write anything except
15198 the trace table. */
15199 if (GET_CODE (insn) == NOTE)
15200 insn = prev_nonnote_insn (insn);
15201 if (insn == 0 || GET_CODE (insn) != BARRIER)
15203 /* This is slightly ugly, but at least we don't have two
15204 copies of the epilogue-emitting code. */
15207 /* A NOTE_INSN_DELETED is supposed to be at the start
15208 and end of the "toplevel" insn chain. */
15209 emit_note (NOTE_INSN_DELETED);
15210 rs6000_emit_epilogue (FALSE);
15211 emit_note (NOTE_INSN_DELETED);
15213 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15217 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15219 INSN_ADDRESSES_NEW (insn, addr);
15224 if (TARGET_DEBUG_STACK)
15225 debug_rtx_list (get_insns (), 100);
15226 final (get_insns (), file, FALSE);
15232 macho_branch_islands ();
15233 /* Mach-O doesn't support labels at the end of objects, so if
15234 it looks like we might want one, insert a NOP. */
15236 rtx insn = get_last_insn ();
15239 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
15240 insn = PREV_INSN (insn);
15244 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
15245 fputs ("\tnop\n", file);
15249 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15252 We don't output a traceback table if -finhibit-size-directive was
15253 used. The documentation for -finhibit-size-directive reads
15254 ``don't output a @code{.size} assembler directive, or anything
15255 else that would cause trouble if the function is split in the
15256 middle, and the two halves are placed at locations far apart in
15257 memory.'' The traceback table has this property, since it
15258 includes the offset from the start of the function to the
15259 traceback table itself.
15261 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15262 different traceback table. */
15263 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15264 && rs6000_traceback != traceback_none && !current_function_is_thunk)
15266 const char *fname = NULL;
15267 const char *language_string = lang_hooks.name;
15268 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15270 int optional_tbtab;
15271 rs6000_stack_t *info = rs6000_stack_info ();
15273 if (rs6000_traceback == traceback_full)
15274 optional_tbtab = 1;
15275 else if (rs6000_traceback == traceback_part)
15276 optional_tbtab = 0;
15278 optional_tbtab = !optimize_size && !TARGET_ELF;
15280 if (optional_tbtab)
15282 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15283 while (*fname == '.') /* V.4 encodes . in the name */
15286 /* Need label immediately before tbtab, so we can compute
15287 its offset from the function start. */
15288 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15289 ASM_OUTPUT_LABEL (file, fname);
15292 /* The .tbtab pseudo-op can only be used for the first eight
15293 expressions, since it can't handle the possibly variable
15294 length fields that follow. However, if you omit the optional
15295 fields, the assembler outputs zeros for all optional fields
15296 anyways, giving each variable length field is minimum length
15297 (as defined in sys/debug.h). Thus we can not use the .tbtab
15298 pseudo-op at all. */
15300 /* An all-zero word flags the start of the tbtab, for debuggers
15301 that have to find it by searching forward from the entry
15302 point or from the current pc. */
15303 fputs ("\t.long 0\n", file);
15305 /* Tbtab format type. Use format type 0. */
15306 fputs ("\t.byte 0,", file);
15308 /* Language type. Unfortunately, there does not seem to be any
15309 official way to discover the language being compiled, so we
15310 use language_string.
15311 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15312 Java is 13. Objective-C is 14. */
15313 if (! strcmp (language_string, "GNU C"))
15315 else if (! strcmp (language_string, "GNU F77")
15316 || ! strcmp (language_string, "GNU F95"))
15318 else if (! strcmp (language_string, "GNU Pascal"))
15320 else if (! strcmp (language_string, "GNU Ada"))
15322 else if (! strcmp (language_string, "GNU C++"))
15324 else if (! strcmp (language_string, "GNU Java"))
15326 else if (! strcmp (language_string, "GNU Objective-C"))
15329 gcc_unreachable ();
15330 fprintf (file, "%d,", i);
15332 /* 8 single bit fields: global linkage (not set for C extern linkage,
15333 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15334 from start of procedure stored in tbtab, internal function, function
15335 has controlled storage, function has no toc, function uses fp,
15336 function logs/aborts fp operations. */
15337 /* Assume that fp operations are used if any fp reg must be saved. */
15338 fprintf (file, "%d,",
15339 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15341 /* 6 bitfields: function is interrupt handler, name present in
15342 proc table, function calls alloca, on condition directives
15343 (controls stack walks, 3 bits), saves condition reg, saves
15345 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15346 set up as a frame pointer, even when there is no alloca call. */
15347 fprintf (file, "%d,",
15348 ((optional_tbtab << 6)
15349 | ((optional_tbtab & frame_pointer_needed) << 5)
15350 | (info->cr_save_p << 1)
15351 | (info->lr_save_p)));
15353 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15355 fprintf (file, "%d,",
15356 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15358 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15359 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15361 if (optional_tbtab)
15363 /* Compute the parameter info from the function decl argument
15366 int next_parm_info_bit = 31;
15368 for (decl = DECL_ARGUMENTS (current_function_decl);
15369 decl; decl = TREE_CHAIN (decl))
15371 rtx parameter = DECL_INCOMING_RTL (decl);
15372 enum machine_mode mode = GET_MODE (parameter);
15374 if (GET_CODE (parameter) == REG)
15376 if (SCALAR_FLOAT_MODE_P (mode))
15394 gcc_unreachable ();
15397 /* If only one bit will fit, don't or in this entry. */
15398 if (next_parm_info_bit > 0)
15399 parm_info |= (bits << (next_parm_info_bit - 1));
15400 next_parm_info_bit -= 2;
15404 fixed_parms += ((GET_MODE_SIZE (mode)
15405 + (UNITS_PER_WORD - 1))
15407 next_parm_info_bit -= 1;
15413 /* Number of fixed point parameters. */
15414 /* This is actually the number of words of fixed point parameters; thus
15415 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15416 fprintf (file, "%d,", fixed_parms);
15418 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15420 /* This is actually the number of fp registers that hold parameters;
15421 and thus the maximum value is 13. */
15422 /* Set parameters on stack bit if parameters are not in their original
15423 registers, regardless of whether they are on the stack? Xlc
15424 seems to set the bit when not optimizing. */
15425 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15427 if (! optional_tbtab)
15430 /* Optional fields follow. Some are variable length. */
15432 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15433 11 double float. */
15434 /* There is an entry for each parameter in a register, in the order that
15435 they occur in the parameter list. Any intervening arguments on the
15436 stack are ignored. If the list overflows a long (max possible length
15437 34 bits) then completely leave off all elements that don't fit. */
15438 /* Only emit this long if there was at least one parameter. */
15439 if (fixed_parms || float_parms)
15440 fprintf (file, "\t.long %d\n", parm_info);
15442 /* Offset from start of code to tb table. */
15443 fputs ("\t.long ", file);
15444 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15446 RS6000_OUTPUT_BASENAME (file, fname);
15448 assemble_name (file, fname);
15450 rs6000_output_function_entry (file, fname);
15453 /* Interrupt handler mask. */
15454 /* Omit this long, since we never set the interrupt handler bit
15457 /* Number of CTL (controlled storage) anchors. */
15458 /* Omit this long, since the has_ctl bit is never set above. */
15460 /* Displacement into stack of each CTL anchor. */
15461 /* Omit this list of longs, because there are no CTL anchors. */
15463 /* Length of function name. */
15466 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15468 /* Function name. */
15469 assemble_string (fname, strlen (fname));
15471 /* Register for alloca automatic storage; this is always reg 31.
15472 Only emit this if the alloca bit was set above. */
15473 if (frame_pointer_needed)
15474 fputs ("\t.byte 31\n", file);
15476 fputs ("\t.align 2\n", file);
15480 /* A C compound statement that outputs the assembler code for a thunk
15481 function, used to implement C++ virtual function calls with
15482 multiple inheritance. The thunk acts as a wrapper around a virtual
15483 function, adjusting the implicit object parameter before handing
15484 control off to the real function.
15486 First, emit code to add the integer DELTA to the location that
15487 contains the incoming first argument. Assume that this argument
15488 contains a pointer, and is the one used to pass the `this' pointer
15489 in C++. This is the incoming argument *before* the function
15490 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15491 values of all other incoming arguments.
15493 After the addition, emit code to jump to FUNCTION, which is a
15494 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15495 not touch the return address. Hence returning from FUNCTION will
15496 return to whoever called the current `thunk'.
15498 The effect must be as if FUNCTION had been called directly with the
15499 adjusted first argument. This macro is responsible for emitting
15500 all of the code for a thunk function; output_function_prologue()
15501 and output_function_epilogue() are not invoked.
15503 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15504 been extracted from it.) It might possibly be useful on some
15505 targets, but probably not.
15507 If you do not define this macro, the target-independent code in the
15508 C++ frontend will generate a less efficient heavyweight thunk that
15509 calls FUNCTION instead of jumping to it. The generic approach does
15510 not support varargs. */
15513 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15514 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15517 rtx this, insn, funexp;
15519 reload_completed = 1;
15520 epilogue_completed = 1;
15521 no_new_pseudos = 1;
15522 reset_block_changes ();
15524 /* Mark the end of the (empty) prologue. */
15525 emit_note (NOTE_INSN_PROLOGUE_END);
15527 /* Find the "this" pointer. If the function returns a structure,
15528 the structure return pointer is in r3. */
15529 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15530 this = gen_rtx_REG (Pmode, 4);
15532 this = gen_rtx_REG (Pmode, 3);
15534 /* Apply the constant offset, if required. */
15537 rtx delta_rtx = GEN_INT (delta);
15538 emit_insn (TARGET_32BIT
15539 ? gen_addsi3 (this, this, delta_rtx)
15540 : gen_adddi3 (this, this, delta_rtx));
15543 /* Apply the offset from the vtable, if required. */
15546 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15547 rtx tmp = gen_rtx_REG (Pmode, 12);
15549 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
15550 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15552 emit_insn (TARGET_32BIT
15553 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
15554 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
15555 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15559 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15561 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15563 emit_insn (TARGET_32BIT
15564 ? gen_addsi3 (this, this, tmp)
15565 : gen_adddi3 (this, this, tmp));
15568 /* Generate a tail call to the target function. */
15569 if (!TREE_USED (function))
15571 assemble_external (function);
15572 TREE_USED (function) = 1;
15574 funexp = XEXP (DECL_RTL (function), 0);
15575 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15578 if (MACHOPIC_INDIRECT)
15579 funexp = machopic_indirect_call_target (funexp);
15582 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15583 generate sibcall RTL explicitly. */
15584 insn = emit_call_insn (
15585 gen_rtx_PARALLEL (VOIDmode,
15587 gen_rtx_CALL (VOIDmode,
15588 funexp, const0_rtx),
15589 gen_rtx_USE (VOIDmode, const0_rtx),
15590 gen_rtx_USE (VOIDmode,
15591 gen_rtx_REG (SImode,
15592 LINK_REGISTER_REGNUM)),
15593 gen_rtx_RETURN (VOIDmode))));
15594 SIBLING_CALL_P (insn) = 1;
15597 /* Run just enough of rest_of_compilation to get the insns emitted.
15598 There's not really enough bulk here to make other passes such as
15599 instruction scheduling worth while. Note that use_thunk calls
15600 assemble_start_function and assemble_end_function. */
15601 insn = get_insns ();
15602 insn_locators_initialize ();
15603 shorten_branches (insn);
15604 final_start_function (insn, file, 1);
15605 final (insn, file, 1);
15606 final_end_function ();
15608 reload_completed = 0;
15609 epilogue_completed = 0;
15610 no_new_pseudos = 0;
15613 /* A quick summary of the various types of 'constant-pool tables'
15616 Target Flags Name One table per
15617 AIX (none) AIX TOC object file
15618 AIX -mfull-toc AIX TOC object file
15619 AIX -mminimal-toc AIX minimal TOC translation unit
15620 SVR4/EABI (none) SVR4 SDATA object file
15621 SVR4/EABI -fpic SVR4 pic object file
15622 SVR4/EABI -fPIC SVR4 PIC translation unit
15623 SVR4/EABI -mrelocatable EABI TOC function
15624 SVR4/EABI -maix AIX TOC object file
15625 SVR4/EABI -maix -mminimal-toc
15626 AIX minimal TOC translation unit
15628 Name Reg. Set by entries contains:
15629 made by addrs? fp? sum?
15631 AIX TOC 2 crt0 as Y option option
15632 AIX minimal TOC 30 prolog gcc Y Y option
15633 SVR4 SDATA 13 crt0 gcc N Y N
15634 SVR4 pic 30 prolog ld Y not yet N
15635 SVR4 PIC 30 prolog gcc Y option option
15636 EABI TOC 30 prolog gcc Y option option
15640 /* Hash functions for the hash table. */
15643 rs6000_hash_constant (rtx k)
15645 enum rtx_code code = GET_CODE (k);
15646 enum machine_mode mode = GET_MODE (k);
15647 unsigned result = (code << 3) ^ mode;
15648 const char *format;
15651 format = GET_RTX_FORMAT (code);
15652 flen = strlen (format);
15658 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15661 if (mode != VOIDmode)
15662 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15674 for (; fidx < flen; fidx++)
15675 switch (format[fidx])
15680 const char *str = XSTR (k, fidx);
15681 len = strlen (str);
15682 result = result * 613 + len;
15683 for (i = 0; i < len; i++)
15684 result = result * 613 + (unsigned) str[i];
15689 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15693 result = result * 613 + (unsigned) XINT (k, fidx);
15696 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15697 result = result * 613 + (unsigned) XWINT (k, fidx);
15701 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
15702 result = result * 613 + (unsigned) (XWINT (k, fidx)
15709 gcc_unreachable ();
15716 toc_hash_function (const void *hash_entry)
15718 const struct toc_hash_struct *thc =
15719 (const struct toc_hash_struct *) hash_entry;
15720 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15723 /* Compare H1 and H2 for equivalence. */
15726 toc_hash_eq (const void *h1, const void *h2)
15728 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
15729 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
15731 if (((const struct toc_hash_struct *) h1)->key_mode
15732 != ((const struct toc_hash_struct *) h2)->key_mode)
15735 return rtx_equal_p (r1, r2);
15738 /* These are the names given by the C++ front-end to vtables, and
15739 vtable-like objects. Ideally, this logic should not be here;
15740 instead, there should be some programmatic way of inquiring as
15741 to whether or not an object is a vtable. */
15743 #define VTABLE_NAME_P(NAME) \
15744 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
15745 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15746 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15747 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15748 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15751 rs6000_output_symbol_ref (FILE *file, rtx x)
15753 /* Currently C++ toc references to vtables can be emitted before it
15754 is decided whether the vtable is public or private. If this is
15755 the case, then the linker will eventually complain that there is
15756 a reference to an unknown section. Thus, for vtables only,
15757 we emit the TOC reference to reference the symbol and not the
15759 const char *name = XSTR (x, 0);
15761 if (VTABLE_NAME_P (name))
15763 RS6000_OUTPUT_BASENAME (file, name);
15766 assemble_name (file, name);
15769 /* Output a TOC entry. We derive the entry name from what is being
15773 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
15776 const char *name = buf;
15777 const char *real_name;
15779 HOST_WIDE_INT offset = 0;
15781 gcc_assert (!TARGET_NO_TOC);
15783 /* When the linker won't eliminate them, don't output duplicate
15784 TOC entries (this happens on AIX if there is any kind of TOC,
15785 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15787 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15789 struct toc_hash_struct *h;
15792 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15793 time because GGC is not initialized at that point. */
15794 if (toc_hash_table == NULL)
15795 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15796 toc_hash_eq, NULL);
15798 h = ggc_alloc (sizeof (*h));
15800 h->key_mode = mode;
15801 h->labelno = labelno;
15803 found = htab_find_slot (toc_hash_table, h, 1);
15804 if (*found == NULL)
15806 else /* This is indeed a duplicate.
15807 Set this label equal to that label. */
15809 fputs ("\t.set ", file);
15810 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15811 fprintf (file, "%d,", labelno);
15812 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15813 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15819 /* If we're going to put a double constant in the TOC, make sure it's
15820 aligned properly when strict alignment is on. */
15821 if (GET_CODE (x) == CONST_DOUBLE
15822 && STRICT_ALIGNMENT
15823 && GET_MODE_BITSIZE (mode) >= 64
15824 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15825 ASM_OUTPUT_ALIGN (file, 3);
15828 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15830 /* Handle FP constants specially. Note that if we have a minimal
15831 TOC, things we put here aren't actually in the TOC, so we can allow
15833 if (GET_CODE (x) == CONST_DOUBLE &&
15834 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
15836 REAL_VALUE_TYPE rv;
15839 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15840 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15841 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
15843 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15847 if (TARGET_MINIMAL_TOC)
15848 fputs (DOUBLE_INT_ASM_OP, file);
15850 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15851 k[0] & 0xffffffff, k[1] & 0xffffffff,
15852 k[2] & 0xffffffff, k[3] & 0xffffffff);
15853 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15854 k[0] & 0xffffffff, k[1] & 0xffffffff,
15855 k[2] & 0xffffffff, k[3] & 0xffffffff);
15860 if (TARGET_MINIMAL_TOC)
15861 fputs ("\t.long ", file);
15863 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15864 k[0] & 0xffffffff, k[1] & 0xffffffff,
15865 k[2] & 0xffffffff, k[3] & 0xffffffff);
15866 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15867 k[0] & 0xffffffff, k[1] & 0xffffffff,
15868 k[2] & 0xffffffff, k[3] & 0xffffffff);
15872 else if (GET_CODE (x) == CONST_DOUBLE &&
15873 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
15875 REAL_VALUE_TYPE rv;
15878 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15880 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15881 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
15883 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
15887 if (TARGET_MINIMAL_TOC)
15888 fputs (DOUBLE_INT_ASM_OP, file);
15890 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15891 k[0] & 0xffffffff, k[1] & 0xffffffff);
15892 fprintf (file, "0x%lx%08lx\n",
15893 k[0] & 0xffffffff, k[1] & 0xffffffff);
15898 if (TARGET_MINIMAL_TOC)
15899 fputs ("\t.long ", file);
15901 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15902 k[0] & 0xffffffff, k[1] & 0xffffffff);
15903 fprintf (file, "0x%lx,0x%lx\n",
15904 k[0] & 0xffffffff, k[1] & 0xffffffff);
15908 else if (GET_CODE (x) == CONST_DOUBLE &&
15909 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
15911 REAL_VALUE_TYPE rv;
15914 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15915 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
15916 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
15918 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15922 if (TARGET_MINIMAL_TOC)
15923 fputs (DOUBLE_INT_ASM_OP, file);
15925 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15926 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
15931 if (TARGET_MINIMAL_TOC)
15932 fputs ("\t.long ", file);
15934 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15935 fprintf (file, "0x%lx\n", l & 0xffffffff);
15939 else if (GET_MODE (x) == VOIDmode
15940 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
15942 unsigned HOST_WIDE_INT low;
15943 HOST_WIDE_INT high;
15945 if (GET_CODE (x) == CONST_DOUBLE)
15947 low = CONST_DOUBLE_LOW (x);
15948 high = CONST_DOUBLE_HIGH (x);
15951 #if HOST_BITS_PER_WIDE_INT == 32
15954 high = (low & 0x80000000) ? ~0 : 0;
15958 low = INTVAL (x) & 0xffffffff;
15959 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
15963 /* TOC entries are always Pmode-sized, but since this
15964 is a bigendian machine then if we're putting smaller
15965 integer constants in the TOC we have to pad them.
15966 (This is still a win over putting the constants in
15967 a separate constant pool, because then we'd have
15968 to have both a TOC entry _and_ the actual constant.)
15970 For a 32-bit target, CONST_INT values are loaded and shifted
15971 entirely within `low' and can be stored in one TOC entry. */
15973 /* It would be easy to make this work, but it doesn't now. */
15974 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
15976 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
15978 #if HOST_BITS_PER_WIDE_INT == 32
15979 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15980 POINTER_SIZE, &low, &high, 0);
15983 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
15984 high = (HOST_WIDE_INT) low >> 32;
15991 if (TARGET_MINIMAL_TOC)
15992 fputs (DOUBLE_INT_ASM_OP, file);
15994 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15995 (long) high & 0xffffffff, (long) low & 0xffffffff);
15996 fprintf (file, "0x%lx%08lx\n",
15997 (long) high & 0xffffffff, (long) low & 0xffffffff);
16002 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
16004 if (TARGET_MINIMAL_TOC)
16005 fputs ("\t.long ", file);
16007 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16008 (long) high & 0xffffffff, (long) low & 0xffffffff);
16009 fprintf (file, "0x%lx,0x%lx\n",
16010 (long) high & 0xffffffff, (long) low & 0xffffffff);
16014 if (TARGET_MINIMAL_TOC)
16015 fputs ("\t.long ", file);
16017 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
16018 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
16024 if (GET_CODE (x) == CONST)
16026 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
16028 base = XEXP (XEXP (x, 0), 0);
16029 offset = INTVAL (XEXP (XEXP (x, 0), 1));
16032 switch (GET_CODE (base))
16035 name = XSTR (base, 0);
16039 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
16040 CODE_LABEL_NUMBER (XEXP (base, 0)));
16044 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
16048 gcc_unreachable ();
16051 real_name = (*targetm.strip_name_encoding) (name);
16052 if (TARGET_MINIMAL_TOC)
16053 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
16056 fprintf (file, "\t.tc %s", real_name);
16059 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
16061 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
16063 fputs ("[TC],", file);
16066 /* Currently C++ toc references to vtables can be emitted before it
16067 is decided whether the vtable is public or private. If this is
16068 the case, then the linker will eventually complain that there is
16069 a TOC reference to an unknown section. Thus, for vtables only,
16070 we emit the TOC reference to reference the symbol and not the
16072 if (VTABLE_NAME_P (name))
16074 RS6000_OUTPUT_BASENAME (file, name);
16076 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16077 else if (offset > 0)
16078 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
16081 output_addr_const (file, x);
16085 /* Output an assembler pseudo-op to write an ASCII string of N characters
16086 starting at P to FILE.
16088 On the RS/6000, we have to do this using the .byte operation and
16089 write out special characters outside the quoted string.
16090 Also, the assembler is broken; very long strings are truncated,
16091 so we must artificially break them up early. */
16094 output_ascii (FILE *file, const char *p, int n)
16097 int i, count_string;
16098 const char *for_string = "\t.byte \"";
16099 const char *for_decimal = "\t.byte ";
16100 const char *to_close = NULL;
16103 for (i = 0; i < n; i++)
16106 if (c >= ' ' && c < 0177)
16109 fputs (for_string, file);
16112 /* Write two quotes to get one. */
16120 for_decimal = "\"\n\t.byte ";
16124 if (count_string >= 512)
16126 fputs (to_close, file);
16128 for_string = "\t.byte \"";
16129 for_decimal = "\t.byte ";
16137 fputs (for_decimal, file);
16138 fprintf (file, "%d", c);
16140 for_string = "\n\t.byte \"";
16141 for_decimal = ", ";
16147 /* Now close the string if we have written one. Then end the line. */
16149 fputs (to_close, file);
16152 /* Generate a unique section name for FILENAME for a section type
16153 represented by SECTION_DESC. Output goes into BUF.
16155 SECTION_DESC can be any string, as long as it is different for each
16156 possible section type.
16158 We name the section in the same manner as xlc. The name begins with an
16159 underscore followed by the filename (after stripping any leading directory
16160 names) with the last period replaced by the string SECTION_DESC. If
16161 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16165 rs6000_gen_section_name (char **buf, const char *filename,
16166 const char *section_desc)
16168 const char *q, *after_last_slash, *last_period = 0;
16172 after_last_slash = filename;
16173 for (q = filename; *q; q++)
16176 after_last_slash = q + 1;
16177 else if (*q == '.')
16181 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16182 *buf = (char *) xmalloc (len);
16187 for (q = after_last_slash; *q; q++)
16189 if (q == last_period)
16191 strcpy (p, section_desc);
16192 p += strlen (section_desc);
16196 else if (ISALNUM (*q))
16200 if (last_period == 0)
16201 strcpy (p, section_desc);
16206 /* Emit profile function. */
16209 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16211 /* Non-standard profiling for kernels, which just saves LR then calls
16212 _mcount without worrying about arg saves. The idea is to change
16213 the function prologue as little as possible as it isn't easy to
16214 account for arg save/restore code added just for _mcount. */
16215 if (TARGET_PROFILE_KERNEL)
16218 if (DEFAULT_ABI == ABI_AIX)
16220 #ifndef NO_PROFILE_COUNTERS
16221 # define NO_PROFILE_COUNTERS 0
16223 if (NO_PROFILE_COUNTERS)
16224 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16228 const char *label_name;
16231 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16232 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16233 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16235 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16239 else if (DEFAULT_ABI == ABI_DARWIN)
16241 const char *mcount_name = RS6000_MCOUNT;
16242 int caller_addr_regno = LINK_REGISTER_REGNUM;
16244 /* Be conservative and always set this, at least for now. */
16245 current_function_uses_pic_offset_table = 1;
16248 /* For PIC code, set up a stub and collect the caller's address
16249 from r0, which is where the prologue puts it. */
16250 if (MACHOPIC_INDIRECT
16251 && current_function_uses_pic_offset_table)
16252 caller_addr_regno = 0;
16254 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16256 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16260 /* Write function profiler code. */
16263 output_function_profiler (FILE *file, int labelno)
16267 switch (DEFAULT_ABI)
16270 gcc_unreachable ();
16275 warning (0, "no profiling of 64-bit code for this ABI");
16278 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16279 fprintf (file, "\tmflr %s\n", reg_names[0]);
16280 if (NO_PROFILE_COUNTERS)
16282 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16283 reg_names[0], reg_names[1]);
16285 else if (TARGET_SECURE_PLT && flag_pic)
16287 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16288 reg_names[0], reg_names[1]);
16289 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16290 asm_fprintf (file, "\t{cau|addis} %s,%s,",
16291 reg_names[12], reg_names[12]);
16292 assemble_name (file, buf);
16293 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
16294 assemble_name (file, buf);
16295 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
16297 else if (flag_pic == 1)
16299 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16300 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16301 reg_names[0], reg_names[1]);
16302 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16303 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16304 assemble_name (file, buf);
16305 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16307 else if (flag_pic > 1)
16309 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16310 reg_names[0], reg_names[1]);
16311 /* Now, we need to get the address of the label. */
16312 fputs ("\tbcl 20,31,1f\n\t.long ", file);
16313 assemble_name (file, buf);
16314 fputs ("-.\n1:", file);
16315 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16316 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16317 reg_names[0], reg_names[11]);
16318 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16319 reg_names[0], reg_names[0], reg_names[11]);
16323 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16324 assemble_name (file, buf);
16325 fputs ("@ha\n", file);
16326 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16327 reg_names[0], reg_names[1]);
16328 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16329 assemble_name (file, buf);
16330 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16333 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16334 fprintf (file, "\tbl %s%s\n",
16335 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16340 if (!TARGET_PROFILE_KERNEL)
16342 /* Don't do anything, done in output_profile_hook (). */
16346 gcc_assert (!TARGET_32BIT);
16348 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16349 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16351 if (cfun->static_chain_decl != NULL)
16353 asm_fprintf (file, "\tstd %s,24(%s)\n",
16354 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16355 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16356 asm_fprintf (file, "\tld %s,24(%s)\n",
16357 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16360 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16367 /* Power4 load update and store update instructions are cracked into a
16368 load or store and an integer insn which are executed in the same cycle.
16369 Branches have their own dispatch slot which does not count against the
16370 GCC issue rate, but it changes the program flow so there are no other
16371 instructions to issue in this cycle. */
16374 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16375 int verbose ATTRIBUTE_UNUSED,
16376 rtx insn, int more)
16378 if (GET_CODE (PATTERN (insn)) == USE
16379 || GET_CODE (PATTERN (insn)) == CLOBBER)
16382 if (rs6000_sched_groups)
16384 if (is_microcoded_insn (insn))
16386 else if (is_cracked_insn (insn))
16387 return more > 2 ? more - 2 : 0;
16393 /* Adjust the cost of a scheduling dependency. Return the new cost of
16394 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16397 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16399 if (! recog_memoized (insn))
16402 if (REG_NOTE_KIND (link) != 0)
16405 if (REG_NOTE_KIND (link) == 0)
16407 /* Data dependency; DEP_INSN writes a register that INSN reads
16408 some cycles later. */
16410 /* Separate a load from a narrower, dependent store. */
16411 if (rs6000_sched_groups
16412 && GET_CODE (PATTERN (insn)) == SET
16413 && GET_CODE (PATTERN (dep_insn)) == SET
16414 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16415 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16416 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16417 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16420 switch (get_attr_type (insn))
16423 /* Tell the first scheduling pass about the latency between
16424 a mtctr and bctr (and mtlr and br/blr). The first
16425 scheduling pass will not know about this latency since
16426 the mtctr instruction, which has the latency associated
16427 to it, will be generated by reload. */
16428 return TARGET_POWER ? 5 : 4;
16430 /* Leave some extra cycles between a compare and its
16431 dependent branch, to inhibit expensive mispredicts. */
16432 if ((rs6000_cpu_attr == CPU_PPC603
16433 || rs6000_cpu_attr == CPU_PPC604
16434 || rs6000_cpu_attr == CPU_PPC604E
16435 || rs6000_cpu_attr == CPU_PPC620
16436 || rs6000_cpu_attr == CPU_PPC630
16437 || rs6000_cpu_attr == CPU_PPC750
16438 || rs6000_cpu_attr == CPU_PPC7400
16439 || rs6000_cpu_attr == CPU_PPC7450
16440 || rs6000_cpu_attr == CPU_POWER4
16441 || rs6000_cpu_attr == CPU_POWER5)
16442 && recog_memoized (dep_insn)
16443 && (INSN_CODE (dep_insn) >= 0)
16444 && (get_attr_type (dep_insn) == TYPE_CMP
16445 || get_attr_type (dep_insn) == TYPE_COMPARE
16446 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
16447 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
16448 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
16449 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
16450 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
16451 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
16456 /* Fall out to return default cost. */
16462 /* The function returns a true if INSN is microcoded.
16463 Return false otherwise. */
16466 is_microcoded_insn (rtx insn)
16468 if (!insn || !INSN_P (insn)
16469 || GET_CODE (PATTERN (insn)) == USE
16470 || GET_CODE (PATTERN (insn)) == CLOBBER)
16473 if (rs6000_sched_groups)
16475 enum attr_type type = get_attr_type (insn);
16476 if (type == TYPE_LOAD_EXT_U
16477 || type == TYPE_LOAD_EXT_UX
16478 || type == TYPE_LOAD_UX
16479 || type == TYPE_STORE_UX
16480 || type == TYPE_MFCR)
16487 /* The function returns a nonzero value if INSN can be scheduled only
16488 as the first insn in a dispatch group ("dispatch-slot restricted").
16489 In this case, the returned value indicates how many dispatch slots
16490 the insn occupies (at the beginning of the group).
16491 Return 0 otherwise. */
16494 is_dispatch_slot_restricted (rtx insn)
16496 enum attr_type type;
16498 if (!rs6000_sched_groups)
16502 || insn == NULL_RTX
16503 || GET_CODE (insn) == NOTE
16504 || GET_CODE (PATTERN (insn)) == USE
16505 || GET_CODE (PATTERN (insn)) == CLOBBER)
16508 type = get_attr_type (insn);
16515 case TYPE_DELAYED_CR:
16516 case TYPE_CR_LOGICAL:
16529 if (rs6000_cpu == PROCESSOR_POWER5
16530 && is_cracked_insn (insn))
16536 /* The function returns true if INSN is cracked into 2 instructions
16537 by the processor (and therefore occupies 2 issue slots). */
16540 is_cracked_insn (rtx insn)
16542 if (!insn || !INSN_P (insn)
16543 || GET_CODE (PATTERN (insn)) == USE
16544 || GET_CODE (PATTERN (insn)) == CLOBBER)
16547 if (rs6000_sched_groups)
16549 enum attr_type type = get_attr_type (insn);
16550 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
16551 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
16552 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
16553 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
16554 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
16555 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
16556 || type == TYPE_IDIV || type == TYPE_LDIV
16557 || type == TYPE_INSERT_WORD)
16564 /* The function returns true if INSN can be issued only from
16565 the branch slot. */
16568 is_branch_slot_insn (rtx insn)
16570 if (!insn || !INSN_P (insn)
16571 || GET_CODE (PATTERN (insn)) == USE
16572 || GET_CODE (PATTERN (insn)) == CLOBBER)
16575 if (rs6000_sched_groups)
16577 enum attr_type type = get_attr_type (insn);
16578 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
16586 /* A C statement (sans semicolon) to update the integer scheduling
16587 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16588 INSN earlier, reduce the priority to execute INSN later. Do not
16589 define this macro if you do not need to adjust the scheduling
16590 priorities of insns. */
16593 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
16595 /* On machines (like the 750) which have asymmetric integer units,
16596 where one integer unit can do multiply and divides and the other
16597 can't, reduce the priority of multiply/divide so it is scheduled
16598 before other integer operations. */
16601 if (! INSN_P (insn))
16604 if (GET_CODE (PATTERN (insn)) == USE)
16607 switch (rs6000_cpu_attr) {
16609 switch (get_attr_type (insn))
16616 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
16617 priority, priority);
16618 if (priority >= 0 && priority < 0x01000000)
16625 if (is_dispatch_slot_restricted (insn)
16626 && reload_completed
16627 && current_sched_info->sched_max_insns_priority
16628 && rs6000_sched_restricted_insns_priority)
16631 /* Prioritize insns that can be dispatched only in the first
16633 if (rs6000_sched_restricted_insns_priority == 1)
16634 /* Attach highest priority to insn. This means that in
16635 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16636 precede 'priority' (critical path) considerations. */
16637 return current_sched_info->sched_max_insns_priority;
16638 else if (rs6000_sched_restricted_insns_priority == 2)
16639 /* Increase priority of insn by a minimal amount. This means that in
16640 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16641 considerations precede dispatch-slot restriction considerations. */
16642 return (priority + 1);
16648 /* Return how many instructions the machine can issue per cycle. */
16651 rs6000_issue_rate (void)
16653 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16654 if (!reload_completed)
16657 switch (rs6000_cpu_attr) {
16658 case CPU_RIOS1: /* ? */
16660 case CPU_PPC601: /* ? */
16683 /* Return how many instructions to look ahead for better insn
16687 rs6000_use_sched_lookahead (void)
16689 if (rs6000_cpu_attr == CPU_PPC8540)
16694 /* Determine is PAT refers to memory. */
16697 is_mem_ref (rtx pat)
16703 if (GET_CODE (pat) == MEM)
16706 /* Recursively process the pattern. */
16707 fmt = GET_RTX_FORMAT (GET_CODE (pat));
16709 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
16712 ret |= is_mem_ref (XEXP (pat, i));
16713 else if (fmt[i] == 'E')
16714 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
16715 ret |= is_mem_ref (XVECEXP (pat, i, j));
16721 /* Determine if PAT is a PATTERN of a load insn. */
16724 is_load_insn1 (rtx pat)
16726 if (!pat || pat == NULL_RTX)
16729 if (GET_CODE (pat) == SET)
16730 return is_mem_ref (SET_SRC (pat));
16732 if (GET_CODE (pat) == PARALLEL)
16736 for (i = 0; i < XVECLEN (pat, 0); i++)
16737 if (is_load_insn1 (XVECEXP (pat, 0, i)))
16744 /* Determine if INSN loads from memory. */
16747 is_load_insn (rtx insn)
16749 if (!insn || !INSN_P (insn))
16752 if (GET_CODE (insn) == CALL_INSN)
16755 return is_load_insn1 (PATTERN (insn));
16758 /* Determine if PAT is a PATTERN of a store insn. */
16761 is_store_insn1 (rtx pat)
16763 if (!pat || pat == NULL_RTX)
16766 if (GET_CODE (pat) == SET)
16767 return is_mem_ref (SET_DEST (pat));
16769 if (GET_CODE (pat) == PARALLEL)
16773 for (i = 0; i < XVECLEN (pat, 0); i++)
16774 if (is_store_insn1 (XVECEXP (pat, 0, i)))
16781 /* Determine if INSN stores to memory. */
16784 is_store_insn (rtx insn)
16786 if (!insn || !INSN_P (insn))
16789 return is_store_insn1 (PATTERN (insn));
16792 /* Returns whether the dependence between INSN and NEXT is considered
16793 costly by the given target. */
16796 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
16799 /* If the flag is not enabled - no dependence is considered costly;
16800 allow all dependent insns in the same group.
16801 This is the most aggressive option. */
16802 if (rs6000_sched_costly_dep == no_dep_costly)
16805 /* If the flag is set to 1 - a dependence is always considered costly;
16806 do not allow dependent instructions in the same group.
16807 This is the most conservative option. */
16808 if (rs6000_sched_costly_dep == all_deps_costly)
16811 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16812 && is_load_insn (next)
16813 && is_store_insn (insn))
16814 /* Prevent load after store in the same group. */
16817 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16818 && is_load_insn (next)
16819 && is_store_insn (insn)
16820 && (!link || (int) REG_NOTE_KIND (link) == 0))
16821 /* Prevent load after store in the same group if it is a true
16825 /* The flag is set to X; dependences with latency >= X are considered costly,
16826 and will not be scheduled in the same group. */
16827 if (rs6000_sched_costly_dep <= max_dep_latency
16828 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16834 /* Return the next insn after INSN that is found before TAIL is reached,
16835 skipping any "non-active" insns - insns that will not actually occupy
16836 an issue slot. Return NULL_RTX if such an insn is not found. */
16839 get_next_active_insn (rtx insn, rtx tail)
16841 if (insn == NULL_RTX || insn == tail)
16846 insn = NEXT_INSN (insn);
16847 if (insn == NULL_RTX || insn == tail)
16852 || (NONJUMP_INSN_P (insn)
16853 && GET_CODE (PATTERN (insn)) != USE
16854 && GET_CODE (PATTERN (insn)) != CLOBBER
16855 && INSN_CODE (insn) != CODE_FOR_stack_tie))
16861 /* Return whether the presence of INSN causes a dispatch group termination
16862 of group WHICH_GROUP.
16864 If WHICH_GROUP == current_group, this function will return true if INSN
16865 causes the termination of the current group (i.e, the dispatch group to
16866 which INSN belongs). This means that INSN will be the last insn in the
16867 group it belongs to.
16869 If WHICH_GROUP == previous_group, this function will return true if INSN
16870 causes the termination of the previous group (i.e, the dispatch group that
16871 precedes the group to which INSN belongs). This means that INSN will be
16872 the first insn in the group it belongs to). */
16875 insn_terminates_group_p (rtx insn, enum group_termination which_group)
16877 enum attr_type type;
16882 type = get_attr_type (insn);
16884 if (is_microcoded_insn (insn))
16887 if (which_group == current_group)
16889 if (is_branch_slot_insn (insn))
16893 else if (which_group == previous_group)
16895 if (is_dispatch_slot_restricted (insn))
16903 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16904 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16907 is_costly_group (rtx *group_insns, rtx next_insn)
16912 int issue_rate = rs6000_issue_rate ();
16914 for (i = 0; i < issue_rate; i++)
16916 rtx insn = group_insns[i];
16919 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
16921 rtx next = XEXP (link, 0);
16922 if (next == next_insn)
16924 cost = insn_cost (insn, link, next_insn);
16925 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
16934 /* Utility of the function redefine_groups.
16935 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16936 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16937 to keep it "far" (in a separate group) from GROUP_INSNS, following
16938 one of the following schemes, depending on the value of the flag
16939 -minsert_sched_nops = X:
16940 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16941 in order to force NEXT_INSN into a separate group.
16942 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16943 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16944 insertion (has a group just ended, how many vacant issue slots remain in the
16945 last group, and how many dispatch groups were encountered so far). */
16948 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
16949 rtx next_insn, bool *group_end, int can_issue_more,
16954 int issue_rate = rs6000_issue_rate ();
16955 bool end = *group_end;
16958 if (next_insn == NULL_RTX)
16959 return can_issue_more;
16961 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
16962 return can_issue_more;
16964 force = is_costly_group (group_insns, next_insn);
16966 return can_issue_more;
16968 if (sched_verbose > 6)
16969 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
16970 *group_count ,can_issue_more);
16972 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
16975 can_issue_more = 0;
16977 /* Since only a branch can be issued in the last issue_slot, it is
16978 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16979 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16980 in this case the last nop will start a new group and the branch
16981 will be forced to the new group. */
16982 if (can_issue_more && !is_branch_slot_insn (next_insn))
16985 while (can_issue_more > 0)
16988 emit_insn_before (nop, next_insn);
16996 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
16998 int n_nops = rs6000_sched_insert_nops;
17000 /* Nops can't be issued from the branch slot, so the effective
17001 issue_rate for nops is 'issue_rate - 1'. */
17002 if (can_issue_more == 0)
17003 can_issue_more = issue_rate;
17005 if (can_issue_more == 0)
17007 can_issue_more = issue_rate - 1;
17010 for (i = 0; i < issue_rate; i++)
17012 group_insns[i] = 0;
17019 emit_insn_before (nop, next_insn);
17020 if (can_issue_more == issue_rate - 1) /* new group begins */
17023 if (can_issue_more == 0)
17025 can_issue_more = issue_rate - 1;
17028 for (i = 0; i < issue_rate; i++)
17030 group_insns[i] = 0;
17036 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
17039 /* Is next_insn going to start a new group? */
17042 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
17043 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
17044 || (can_issue_more < issue_rate &&
17045 insn_terminates_group_p (next_insn, previous_group)));
17046 if (*group_end && end)
17049 if (sched_verbose > 6)
17050 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
17051 *group_count, can_issue_more);
17052 return can_issue_more;
17055 return can_issue_more;
17058 /* This function tries to synch the dispatch groups that the compiler "sees"
17059 with the dispatch groups that the processor dispatcher is expected to
17060 form in practice. It tries to achieve this synchronization by forcing the
17061 estimated processor grouping on the compiler (as opposed to the function
17062 'pad_goups' which tries to force the scheduler's grouping on the processor).
17064 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
17065 examines the (estimated) dispatch groups that will be formed by the processor
17066 dispatcher. It marks these group boundaries to reflect the estimated
17067 processor grouping, overriding the grouping that the scheduler had marked.
17068 Depending on the value of the flag '-minsert-sched-nops' this function can
17069 force certain insns into separate groups or force a certain distance between
17070 them by inserting nops, for example, if there exists a "costly dependence"
17073 The function estimates the group boundaries that the processor will form as
17074 follows: It keeps track of how many vacant issue slots are available after
17075 each insn. A subsequent insn will start a new group if one of the following
17077 - no more vacant issue slots remain in the current dispatch group.
17078 - only the last issue slot, which is the branch slot, is vacant, but the next
17079 insn is not a branch.
17080 - only the last 2 or less issue slots, including the branch slot, are vacant,
17081 which means that a cracked insn (which occupies two issue slots) can't be
17082 issued in this group.
17083 - less than 'issue_rate' slots are vacant, and the next insn always needs to
17084 start a new group. */
17087 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
17089 rtx insn, next_insn;
17091 int can_issue_more;
17094 int group_count = 0;
17098 issue_rate = rs6000_issue_rate ();
17099 group_insns = alloca (issue_rate * sizeof (rtx));
17100 for (i = 0; i < issue_rate; i++)
17102 group_insns[i] = 0;
17104 can_issue_more = issue_rate;
17106 insn = get_next_active_insn (prev_head_insn, tail);
17109 while (insn != NULL_RTX)
17111 slot = (issue_rate - can_issue_more);
17112 group_insns[slot] = insn;
17114 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
17115 if (insn_terminates_group_p (insn, current_group))
17116 can_issue_more = 0;
17118 next_insn = get_next_active_insn (insn, tail);
17119 if (next_insn == NULL_RTX)
17120 return group_count + 1;
17122 /* Is next_insn going to start a new group? */
17124 = (can_issue_more == 0
17125 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
17126 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
17127 || (can_issue_more < issue_rate &&
17128 insn_terminates_group_p (next_insn, previous_group)));
17130 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
17131 next_insn, &group_end, can_issue_more,
17137 can_issue_more = 0;
17138 for (i = 0; i < issue_rate; i++)
17140 group_insns[i] = 0;
17144 if (GET_MODE (next_insn) == TImode && can_issue_more)
17145 PUT_MODE (next_insn, VOIDmode);
17146 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
17147 PUT_MODE (next_insn, TImode);
17150 if (can_issue_more == 0)
17151 can_issue_more = issue_rate;
17154 return group_count;
17157 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
17158 dispatch group boundaries that the scheduler had marked. Pad with nops
17159 any dispatch groups which have vacant issue slots, in order to force the
17160 scheduler's grouping on the processor dispatcher. The function
17161 returns the number of dispatch groups found. */
17164 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
17166 rtx insn, next_insn;
17169 int can_issue_more;
17171 int group_count = 0;
17173 /* Initialize issue_rate. */
17174 issue_rate = rs6000_issue_rate ();
17175 can_issue_more = issue_rate;
17177 insn = get_next_active_insn (prev_head_insn, tail);
17178 next_insn = get_next_active_insn (insn, tail);
17180 while (insn != NULL_RTX)
17183 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
17185 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
17187 if (next_insn == NULL_RTX)
17192 /* If the scheduler had marked group termination at this location
17193 (between insn and next_indn), and neither insn nor next_insn will
17194 force group termination, pad the group with nops to force group
17197 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
17198 && !insn_terminates_group_p (insn, current_group)
17199 && !insn_terminates_group_p (next_insn, previous_group))
17201 if (!is_branch_slot_insn (next_insn))
17204 while (can_issue_more)
17207 emit_insn_before (nop, next_insn);
17212 can_issue_more = issue_rate;
17217 next_insn = get_next_active_insn (insn, tail);
17220 return group_count;
17223 /* The following function is called at the end of scheduling BB.
17224 After reload, it inserts nops at insn group bundling. */
17227 rs6000_sched_finish (FILE *dump, int sched_verbose)
17232 fprintf (dump, "=== Finishing schedule.\n");
17234 if (reload_completed && rs6000_sched_groups)
17236 if (rs6000_sched_insert_nops == sched_finish_none)
17239 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
17240 n_groups = pad_groups (dump, sched_verbose,
17241 current_sched_info->prev_head,
17242 current_sched_info->next_tail);
17244 n_groups = redefine_groups (dump, sched_verbose,
17245 current_sched_info->prev_head,
17246 current_sched_info->next_tail);
17248 if (sched_verbose >= 6)
17250 fprintf (dump, "ngroups = %d\n", n_groups);
17251 print_rtl (dump, current_sched_info->prev_head);
17252 fprintf (dump, "Done finish_sched\n");
17257 /* Length in units of the trampoline for entering a nested function. */
17260 rs6000_trampoline_size (void)
17264 switch (DEFAULT_ABI)
17267 gcc_unreachable ();
17270 ret = (TARGET_32BIT) ? 12 : 24;
17275 ret = (TARGET_32BIT) ? 40 : 48;
17282 /* Emit RTL insns to initialize the variable parts of a trampoline.
17283 FNADDR is an RTX for the address of the function's pure code.
17284 CXT is an RTX for the static chain value for the function. */
17287 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
17289 enum machine_mode pmode = Pmode;
17290 int regsize = (TARGET_32BIT) ? 4 : 8;
17291 rtx ctx_reg = force_reg (pmode, cxt);
17293 switch (DEFAULT_ABI)
17296 gcc_unreachable ();
17298 /* Macros to shorten the code expansions below. */
17299 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
17300 #define MEM_PLUS(addr,offset) \
17301 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
17303 /* Under AIX, just build the 3 word function descriptor */
17306 rtx fn_reg = gen_reg_rtx (pmode);
17307 rtx toc_reg = gen_reg_rtx (pmode);
17308 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
17309 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
17310 emit_move_insn (MEM_DEREF (addr), fn_reg);
17311 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
17312 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
17316 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
17319 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
17320 FALSE, VOIDmode, 4,
17322 GEN_INT (rs6000_trampoline_size ()), SImode,
17332 /* Table of valid machine attributes. */
17334 const struct attribute_spec rs6000_attribute_table[] =
17336 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
17337 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
17338 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17339 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17340 #ifdef SUBTARGET_ATTRIBUTE_TABLE
17341 SUBTARGET_ATTRIBUTE_TABLE,
17343 { NULL, 0, 0, false, false, false, NULL }
17346 /* Handle the "altivec" attribute. The attribute may have
17347 arguments as follows:
17349 __attribute__((altivec(vector__)))
17350 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
17351 __attribute__((altivec(bool__))) (always followed by 'unsigned')
17353 and may appear more than once (e.g., 'vector bool char') in a
17354 given declaration. */
17357 rs6000_handle_altivec_attribute (tree *node,
17358 tree name ATTRIBUTE_UNUSED,
17360 int flags ATTRIBUTE_UNUSED,
17361 bool *no_add_attrs)
17363 tree type = *node, result = NULL_TREE;
17364 enum machine_mode mode;
17367 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
17368 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
17369 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
17372 while (POINTER_TYPE_P (type)
17373 || TREE_CODE (type) == FUNCTION_TYPE
17374 || TREE_CODE (type) == METHOD_TYPE
17375 || TREE_CODE (type) == ARRAY_TYPE)
17376 type = TREE_TYPE (type);
17378 mode = TYPE_MODE (type);
17380 /* Check for invalid AltiVec type qualifiers. */
17381 if (type == long_unsigned_type_node || type == long_integer_type_node)
17384 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
17385 else if (rs6000_warn_altivec_long)
17386 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
17388 else if (type == long_long_unsigned_type_node
17389 || type == long_long_integer_type_node)
17390 error ("use of %<long long%> in AltiVec types is invalid");
17391 else if (type == double_type_node)
17392 error ("use of %<double%> in AltiVec types is invalid");
17393 else if (type == long_double_type_node)
17394 error ("use of %<long double%> in AltiVec types is invalid");
17395 else if (type == boolean_type_node)
17396 error ("use of boolean types in AltiVec types is invalid");
17397 else if (TREE_CODE (type) == COMPLEX_TYPE)
17398 error ("use of %<complex%> in AltiVec types is invalid");
17399 else if (DECIMAL_FLOAT_MODE_P (mode))
17400 error ("use of decimal floating point types in AltiVec types is invalid");
17402 switch (altivec_type)
17405 unsigned_p = TYPE_UNSIGNED (type);
17409 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
17412 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
17415 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
17417 case SFmode: result = V4SF_type_node; break;
17418 /* If the user says 'vector int bool', we may be handed the 'bool'
17419 attribute _before_ the 'vector' attribute, and so select the
17420 proper type in the 'b' case below. */
17421 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
17429 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
17430 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
17431 case QImode: case V16QImode: result = bool_V16QI_type_node;
17438 case V8HImode: result = pixel_V8HI_type_node;
17444 if (result && result != type && TYPE_READONLY (type))
17445 result = build_qualified_type (result, TYPE_QUAL_CONST);
17447 *no_add_attrs = true; /* No need to hang on to the attribute. */
17450 *node = reconstruct_complex_type (*node, result);
17455 /* AltiVec defines four built-in scalar types that serve as vector
17456 elements; we must teach the compiler how to mangle them. */
17458 static const char *
17459 rs6000_mangle_fundamental_type (tree type)
17461 if (type == bool_char_type_node) return "U6__boolc";
17462 if (type == bool_short_type_node) return "U6__bools";
17463 if (type == pixel_type_node) return "u7__pixel";
17464 if (type == bool_int_type_node) return "U6__booli";
17466 /* Mangle IBM extended float long double as `g' (__float128) on
17467 powerpc*-linux where long-double-64 previously was the default. */
17468 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
17470 && TARGET_LONG_DOUBLE_128
17471 && !TARGET_IEEEQUAD)
17474 /* For all other types, use normal C++ mangling. */
17478 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17479 struct attribute_spec.handler. */
17482 rs6000_handle_longcall_attribute (tree *node, tree name,
17483 tree args ATTRIBUTE_UNUSED,
17484 int flags ATTRIBUTE_UNUSED,
17485 bool *no_add_attrs)
17487 if (TREE_CODE (*node) != FUNCTION_TYPE
17488 && TREE_CODE (*node) != FIELD_DECL
17489 && TREE_CODE (*node) != TYPE_DECL)
17491 warning (OPT_Wattributes, "%qs attribute only applies to functions",
17492 IDENTIFIER_POINTER (name));
17493 *no_add_attrs = true;
17499 /* Set longcall attributes on all functions declared when
17500 rs6000_default_long_calls is true. */
17502 rs6000_set_default_type_attributes (tree type)
17504 if (rs6000_default_long_calls
17505 && (TREE_CODE (type) == FUNCTION_TYPE
17506 || TREE_CODE (type) == METHOD_TYPE))
17507 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
17509 TYPE_ATTRIBUTES (type));
17512 /* Return a reference suitable for calling a function with the
17513 longcall attribute. */
17516 rs6000_longcall_ref (rtx call_ref)
17518 const char *call_name;
17521 if (GET_CODE (call_ref) != SYMBOL_REF)
17524 /* System V adds '.' to the internal name, so skip them. */
17525 call_name = XSTR (call_ref, 0);
17526 if (*call_name == '.')
17528 while (*call_name == '.')
17531 node = get_identifier (call_name);
17532 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
17535 return force_reg (Pmode, call_ref);
17538 #ifdef USING_ELFOS_H
17540 /* A get_unnamed_section callback, used for switching to toc_section. */
17543 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
17545 if (DEFAULT_ABI == ABI_AIX
17546 && TARGET_MINIMAL_TOC
17547 && !TARGET_RELOCATABLE)
17549 if (!toc_initialized)
17551 toc_initialized = 1;
17552 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17553 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
17554 fprintf (asm_out_file, "\t.tc ");
17555 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
17556 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17557 fprintf (asm_out_file, "\n");
17559 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17560 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17561 fprintf (asm_out_file, " = .+32768\n");
17564 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17566 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
17567 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
17570 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17571 if (!toc_initialized)
17573 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
17574 fprintf (asm_out_file, " = .+32768\n");
17575 toc_initialized = 1;
17580 /* Implement TARGET_ASM_INIT_SECTIONS. */
17583 rs6000_elf_asm_init_sections (void)
17586 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
17589 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
17590 SDATA2_SECTION_ASM_OP);
17593 /* Implement TARGET_SELECT_RTX_SECTION. */
17596 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
17597 unsigned HOST_WIDE_INT align)
17599 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17600 return toc_section;
17602 return default_elf_select_rtx_section (mode, x, align);
17605 /* Implement TARGET_ASM_SELECT_SECTION for ELF targets. */
17608 rs6000_elf_select_section (tree decl, int reloc,
17609 unsigned HOST_WIDE_INT align)
17611 /* Pretend that we're always building for a shared library when
17612 ABI_AIX, because otherwise we end up with dynamic relocations
17613 in read-only sections. This happens for function pointers,
17614 references to vtables in typeinfo, and probably other cases. */
17615 return default_elf_select_section_1 (decl, reloc, align,
17616 flag_pic || DEFAULT_ABI == ABI_AIX);
17619 /* A C statement to build up a unique section name, expressed as a
17620 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17621 RELOC indicates whether the initial value of EXP requires
17622 link-time relocations. If you do not define this macro, GCC will use
17623 the symbol name prefixed by `.' as the section name. Note - this
17624 macro can now be called for uninitialized data items as well as
17625 initialized data and functions. */
17628 rs6000_elf_unique_section (tree decl, int reloc)
17630 /* As above, pretend that we're always building for a shared library
17631 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
17632 default_unique_section_1 (decl, reloc,
17633 flag_pic || DEFAULT_ABI == ABI_AIX);
17636 /* For a SYMBOL_REF, set generic flags and then perform some
17637 target-specific processing.
17639 When the AIX ABI is requested on a non-AIX system, replace the
17640 function name with the real name (with a leading .) rather than the
17641 function descriptor name. This saves a lot of overriding code to
17642 read the prefixes. */
17645 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
17647 default_encode_section_info (decl, rtl, first);
17650 && TREE_CODE (decl) == FUNCTION_DECL
17652 && DEFAULT_ABI == ABI_AIX)
17654 rtx sym_ref = XEXP (rtl, 0);
17655 size_t len = strlen (XSTR (sym_ref, 0));
17656 char *str = alloca (len + 2);
17658 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
17659 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
17664 rs6000_elf_in_small_data_p (tree decl)
17666 if (rs6000_sdata == SDATA_NONE)
17669 /* We want to merge strings, so we never consider them small data. */
17670 if (TREE_CODE (decl) == STRING_CST)
17673 /* Functions are never in the small data area. */
17674 if (TREE_CODE (decl) == FUNCTION_DECL)
17677 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
17679 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
17680 if (strcmp (section, ".sdata") == 0
17681 || strcmp (section, ".sdata2") == 0
17682 || strcmp (section, ".sbss") == 0
17683 || strcmp (section, ".sbss2") == 0
17684 || strcmp (section, ".PPC.EMB.sdata0") == 0
17685 || strcmp (section, ".PPC.EMB.sbss0") == 0)
17690 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
17693 && (unsigned HOST_WIDE_INT) size <= g_switch_value
17694 /* If it's not public, and we're not going to reference it there,
17695 there's no need to put it in the small data section. */
17696 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
17703 #endif /* USING_ELFOS_H */
17705 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
17708 rs6000_use_blocks_for_constant_p (enum machine_mode mode, rtx x)
17710 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
17713 /* Return a REG that occurs in ADDR with coefficient 1.
17714 ADDR can be effectively incremented by incrementing REG.
17716 r0 is special and we must not select it as an address
17717 register by this routine since our caller will try to
17718 increment the returned register via an "la" instruction. */
17721 find_addr_reg (rtx addr)
17723 while (GET_CODE (addr) == PLUS)
17725 if (GET_CODE (XEXP (addr, 0)) == REG
17726 && REGNO (XEXP (addr, 0)) != 0)
17727 addr = XEXP (addr, 0);
17728 else if (GET_CODE (XEXP (addr, 1)) == REG
17729 && REGNO (XEXP (addr, 1)) != 0)
17730 addr = XEXP (addr, 1);
17731 else if (CONSTANT_P (XEXP (addr, 0)))
17732 addr = XEXP (addr, 1);
17733 else if (CONSTANT_P (XEXP (addr, 1)))
17734 addr = XEXP (addr, 0);
17736 gcc_unreachable ();
17738 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
17743 rs6000_fatal_bad_address (rtx op)
17745 fatal_insn ("bad address", op);
17750 static tree branch_island_list = 0;
17752 /* Remember to generate a branch island for far calls to the given
17756 add_compiler_branch_island (tree label_name, tree function_name,
17759 tree branch_island = build_tree_list (function_name, label_name);
17760 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
17761 TREE_CHAIN (branch_island) = branch_island_list;
17762 branch_island_list = branch_island;
17765 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17766 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17767 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17768 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17770 /* Generate far-jump branch islands for everything on the
17771 branch_island_list. Invoked immediately after the last instruction
17772 of the epilogue has been emitted; the branch-islands must be
17773 appended to, and contiguous with, the function body. Mach-O stubs
17774 are generated in machopic_output_stub(). */
17777 macho_branch_islands (void)
17780 tree branch_island;
17782 for (branch_island = branch_island_list;
17784 branch_island = TREE_CHAIN (branch_island))
17786 const char *label =
17787 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
17789 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
17790 char name_buf[512];
17791 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17792 if (name[0] == '*' || name[0] == '&')
17793 strcpy (name_buf, name+1);
17797 strcpy (name_buf+1, name);
17799 strcpy (tmp_buf, "\n");
17800 strcat (tmp_buf, label);
17801 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17802 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17803 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17804 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17807 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
17808 strcat (tmp_buf, label);
17809 strcat (tmp_buf, "_pic\n");
17810 strcat (tmp_buf, label);
17811 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
17813 strcat (tmp_buf, "\taddis r11,r11,ha16(");
17814 strcat (tmp_buf, name_buf);
17815 strcat (tmp_buf, " - ");
17816 strcat (tmp_buf, label);
17817 strcat (tmp_buf, "_pic)\n");
17819 strcat (tmp_buf, "\tmtlr r0\n");
17821 strcat (tmp_buf, "\taddi r12,r11,lo16(");
17822 strcat (tmp_buf, name_buf);
17823 strcat (tmp_buf, " - ");
17824 strcat (tmp_buf, label);
17825 strcat (tmp_buf, "_pic)\n");
17827 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
17831 strcat (tmp_buf, ":\nlis r12,hi16(");
17832 strcat (tmp_buf, name_buf);
17833 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
17834 strcat (tmp_buf, name_buf);
17835 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
17837 output_asm_insn (tmp_buf, 0);
17838 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17839 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17840 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17841 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17844 branch_island_list = 0;
17847 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17848 already there or not. */
17851 no_previous_def (tree function_name)
17853 tree branch_island;
17854 for (branch_island = branch_island_list;
17856 branch_island = TREE_CHAIN (branch_island))
17857 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17862 /* GET_PREV_LABEL gets the label name from the previous definition of
17866 get_prev_label (tree function_name)
17868 tree branch_island;
17869 for (branch_island = branch_island_list;
17871 branch_island = TREE_CHAIN (branch_island))
17872 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17873 return BRANCH_ISLAND_LABEL_NAME (branch_island);
17877 /* INSN is either a function call or a millicode call. It may have an
17878 unconditional jump in its delay slot.
17880 CALL_DEST is the routine we are calling. */
17883 output_call (rtx insn, rtx *operands, int dest_operand_number,
17884 int cookie_operand_number)
17886 static char buf[256];
17887 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
17888 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
17891 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
17893 if (no_previous_def (funname))
17895 int line_number = 0;
17896 rtx label_rtx = gen_label_rtx ();
17897 char *label_buf, temp_buf[256];
17898 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
17899 CODE_LABEL_NUMBER (label_rtx));
17900 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
17901 labelname = get_identifier (label_buf);
17902 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
17904 line_number = NOTE_LINE_NUMBER (insn);
17905 add_compiler_branch_island (labelname, funname, line_number);
17908 labelname = get_prev_label (funname);
17910 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17911 instruction will reach 'foo', otherwise link as 'bl L42'".
17912 "L42" should be a 'branch island', that will do a far jump to
17913 'foo'. Branch islands are generated in
17914 macho_branch_islands(). */
17915 sprintf (buf, "jbsr %%z%d,%.246s",
17916 dest_operand_number, IDENTIFIER_POINTER (labelname));
17919 sprintf (buf, "bl %%z%d", dest_operand_number);
17923 /* Generate PIC and indirect symbol stubs. */
17926 machopic_output_stub (FILE *file, const char *symb, const char *stub)
17928 unsigned int length;
17929 char *symbol_name, *lazy_ptr_name;
17930 char *local_label_0;
17931 static int label = 0;
17933 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17934 symb = (*targetm.strip_name_encoding) (symb);
17937 length = strlen (symb);
17938 symbol_name = alloca (length + 32);
17939 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17941 lazy_ptr_name = alloca (length + 32);
17942 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
17945 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
17947 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
17951 fprintf (file, "\t.align 5\n");
17953 fprintf (file, "%s:\n", stub);
17954 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17957 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
17958 sprintf (local_label_0, "\"L%011d$spb\"", label);
17960 fprintf (file, "\tmflr r0\n");
17961 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
17962 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
17963 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
17964 lazy_ptr_name, local_label_0);
17965 fprintf (file, "\tmtlr r0\n");
17966 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
17967 (TARGET_64BIT ? "ldu" : "lwzu"),
17968 lazy_ptr_name, local_label_0);
17969 fprintf (file, "\tmtctr r12\n");
17970 fprintf (file, "\tbctr\n");
17974 fprintf (file, "\t.align 4\n");
17976 fprintf (file, "%s:\n", stub);
17977 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17979 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
17980 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
17981 (TARGET_64BIT ? "ldu" : "lwzu"),
17983 fprintf (file, "\tmtctr r12\n");
17984 fprintf (file, "\tbctr\n");
17987 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
17988 fprintf (file, "%s:\n", lazy_ptr_name);
17989 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17990 fprintf (file, "%sdyld_stub_binding_helper\n",
17991 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
17994 /* Legitimize PIC addresses. If the address is already
17995 position-independent, we return ORIG. Newly generated
17996 position-independent addresses go into a reg. This is REG if non
17997 zero, otherwise we allocate register(s) as necessary. */
17999 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
18002 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
18007 if (reg == NULL && ! reload_in_progress && ! reload_completed)
18008 reg = gen_reg_rtx (Pmode);
18010 if (GET_CODE (orig) == CONST)
18014 if (GET_CODE (XEXP (orig, 0)) == PLUS
18015 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
18018 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
18020 /* Use a different reg for the intermediate value, as
18021 it will be marked UNCHANGING. */
18022 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
18023 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
18026 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
18029 if (GET_CODE (offset) == CONST_INT)
18031 if (SMALL_INT (offset))
18032 return plus_constant (base, INTVAL (offset));
18033 else if (! reload_in_progress && ! reload_completed)
18034 offset = force_reg (Pmode, offset);
18037 rtx mem = force_const_mem (Pmode, orig);
18038 return machopic_legitimize_pic_address (mem, Pmode, reg);
18041 return gen_rtx_PLUS (Pmode, base, offset);
18044 /* Fall back on generic machopic code. */
18045 return machopic_legitimize_pic_address (orig, mode, reg);
18048 /* Output a .machine directive for the Darwin assembler, and call
18049 the generic start_file routine. */
18052 rs6000_darwin_file_start (void)
18054 static const struct
18060 { "ppc64", "ppc64", MASK_64BIT },
18061 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
18062 { "power4", "ppc970", 0 },
18063 { "G5", "ppc970", 0 },
18064 { "7450", "ppc7450", 0 },
18065 { "7400", "ppc7400", MASK_ALTIVEC },
18066 { "G4", "ppc7400", 0 },
18067 { "750", "ppc750", 0 },
18068 { "740", "ppc750", 0 },
18069 { "G3", "ppc750", 0 },
18070 { "604e", "ppc604e", 0 },
18071 { "604", "ppc604", 0 },
18072 { "603e", "ppc603", 0 },
18073 { "603", "ppc603", 0 },
18074 { "601", "ppc601", 0 },
18075 { NULL, "ppc", 0 } };
18076 const char *cpu_id = "";
18079 rs6000_file_start ();
18080 darwin_file_start ();
18082 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
18083 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
18084 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
18085 && rs6000_select[i].string[0] != '\0')
18086 cpu_id = rs6000_select[i].string;
18088 /* Look through the mapping array. Pick the first name that either
18089 matches the argument, has a bit set in IF_SET that is also set
18090 in the target flags, or has a NULL name. */
18093 while (mapping[i].arg != NULL
18094 && strcmp (mapping[i].arg, cpu_id) != 0
18095 && (mapping[i].if_set & target_flags) == 0)
18098 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
18101 #endif /* TARGET_MACHO */
18104 static unsigned int
18105 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
18107 return default_section_type_flags_1 (decl, name, reloc,
18108 flag_pic || DEFAULT_ABI == ABI_AIX);
18111 /* Record an element in the table of global constructors. SYMBOL is
18112 a SYMBOL_REF of the function to be called; PRIORITY is a number
18113 between 0 and MAX_INIT_PRIORITY.
18115 This differs from default_named_section_asm_out_constructor in
18116 that we have special handling for -mrelocatable. */
18119 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
18121 const char *section = ".ctors";
18124 if (priority != DEFAULT_INIT_PRIORITY)
18126 sprintf (buf, ".ctors.%.5u",
18127 /* Invert the numbering so the linker puts us in the proper
18128 order; constructors are run from right to left, and the
18129 linker sorts in increasing order. */
18130 MAX_INIT_PRIORITY - priority);
18134 switch_to_section (get_section (section, SECTION_WRITE, NULL));
18135 assemble_align (POINTER_SIZE);
18137 if (TARGET_RELOCATABLE)
18139 fputs ("\t.long (", asm_out_file);
18140 output_addr_const (asm_out_file, symbol);
18141 fputs (")@fixup\n", asm_out_file);
18144 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
18148 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
18150 const char *section = ".dtors";
18153 if (priority != DEFAULT_INIT_PRIORITY)
18155 sprintf (buf, ".dtors.%.5u",
18156 /* Invert the numbering so the linker puts us in the proper
18157 order; constructors are run from right to left, and the
18158 linker sorts in increasing order. */
18159 MAX_INIT_PRIORITY - priority);
18163 switch_to_section (get_section (section, SECTION_WRITE, NULL));
18164 assemble_align (POINTER_SIZE);
18166 if (TARGET_RELOCATABLE)
18168 fputs ("\t.long (", asm_out_file);
18169 output_addr_const (asm_out_file, symbol);
18170 fputs (")@fixup\n", asm_out_file);
18173 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
18177 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
18181 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
18182 ASM_OUTPUT_LABEL (file, name);
18183 fputs (DOUBLE_INT_ASM_OP, file);
18184 rs6000_output_function_entry (file, name);
18185 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
18188 fputs ("\t.size\t", file);
18189 assemble_name (file, name);
18190 fputs (",24\n\t.type\t.", file);
18191 assemble_name (file, name);
18192 fputs (",@function\n", file);
18193 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
18195 fputs ("\t.globl\t.", file);
18196 assemble_name (file, name);
18201 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18202 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18203 rs6000_output_function_entry (file, name);
18204 fputs (":\n", file);
18208 if (TARGET_RELOCATABLE
18209 && !TARGET_SECURE_PLT
18210 && (get_pool_size () != 0 || current_function_profile)
18215 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
18217 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
18218 fprintf (file, "\t.long ");
18219 assemble_name (file, buf);
18221 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
18222 assemble_name (file, buf);
18226 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18227 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18229 if (DEFAULT_ABI == ABI_AIX)
18231 const char *desc_name, *orig_name;
18233 orig_name = (*targetm.strip_name_encoding) (name);
18234 desc_name = orig_name;
18235 while (*desc_name == '.')
18238 if (TREE_PUBLIC (decl))
18239 fprintf (file, "\t.globl %s\n", desc_name);
18241 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18242 fprintf (file, "%s:\n", desc_name);
18243 fprintf (file, "\t.long %s\n", orig_name);
18244 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
18245 if (DEFAULT_ABI == ABI_AIX)
18246 fputs ("\t.long 0\n", file);
18247 fprintf (file, "\t.previous\n");
18249 ASM_OUTPUT_LABEL (file, name);
18253 rs6000_elf_end_indicate_exec_stack (void)
18256 file_end_indicate_exec_stack ();
18262 rs6000_xcoff_asm_output_anchor (rtx symbol)
18266 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
18267 SYMBOL_REF_BLOCK_OFFSET (symbol));
18268 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
18272 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
18274 fputs (GLOBAL_ASM_OP, stream);
18275 RS6000_OUTPUT_BASENAME (stream, name);
18276 putc ('\n', stream);
18279 /* A get_unnamed_decl callback, used for read-only sections. PTR
18280 points to the section string variable. */
18283 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
18285 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
18286 *(const char *const *) directive);
18289 /* Likewise for read-write sections. */
18292 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
18294 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
18295 *(const char *const *) directive);
18298 /* A get_unnamed_section callback, used for switching to toc_section. */
18301 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
18303 if (TARGET_MINIMAL_TOC)
18305 /* toc_section is always selected at least once from
18306 rs6000_xcoff_file_start, so this is guaranteed to
18307 always be defined once and only once in each file. */
18308 if (!toc_initialized)
18310 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
18311 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
18312 toc_initialized = 1;
18314 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
18315 (TARGET_32BIT ? "" : ",3"));
18318 fputs ("\t.toc\n", asm_out_file);
18321 /* Implement TARGET_ASM_INIT_SECTIONS. */
18324 rs6000_xcoff_asm_init_sections (void)
18326 read_only_data_section
18327 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18328 &xcoff_read_only_section_name);
18330 private_data_section
18331 = get_unnamed_section (SECTION_WRITE,
18332 rs6000_xcoff_output_readwrite_section_asm_op,
18333 &xcoff_private_data_section_name);
18335 read_only_private_data_section
18336 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
18337 &xcoff_private_data_section_name);
18340 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
18342 readonly_data_section = read_only_data_section;
18343 exception_section = data_section;
18347 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
18348 tree decl ATTRIBUTE_UNUSED)
18351 static const char * const suffix[3] = { "PR", "RO", "RW" };
18353 if (flags & SECTION_CODE)
18355 else if (flags & SECTION_WRITE)
18360 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
18361 (flags & SECTION_CODE) ? "." : "",
18362 name, suffix[smclass], flags & SECTION_ENTSIZE);
18366 rs6000_xcoff_select_section (tree decl, int reloc,
18367 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18369 if (decl_readonly_section_1 (decl, reloc, 1))
18371 if (TREE_PUBLIC (decl))
18372 return read_only_data_section;
18374 return read_only_private_data_section;
18378 if (TREE_PUBLIC (decl))
18379 return data_section;
18381 return private_data_section;
18386 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
18390 /* Use select_section for private and uninitialized data. */
18391 if (!TREE_PUBLIC (decl)
18392 || DECL_COMMON (decl)
18393 || DECL_INITIAL (decl) == NULL_TREE
18394 || DECL_INITIAL (decl) == error_mark_node
18395 || (flag_zero_initialized_in_bss
18396 && initializer_zerop (DECL_INITIAL (decl))))
18399 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
18400 name = (*targetm.strip_name_encoding) (name);
18401 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
18404 /* Select section for constant in constant pool.
18406 On RS/6000, all constants are in the private read-only data area.
18407 However, if this is being placed in the TOC it must be output as a
18411 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
18412 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18414 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
18415 return toc_section;
18417 return read_only_private_data_section;
18420 /* Remove any trailing [DS] or the like from the symbol name. */
18422 static const char *
18423 rs6000_xcoff_strip_name_encoding (const char *name)
18428 len = strlen (name);
18429 if (name[len - 1] == ']')
18430 return ggc_alloc_string (name, len - 4);
18435 /* Section attributes. AIX is always PIC. */
18437 static unsigned int
18438 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
18440 unsigned int align;
18441 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
18443 /* Align to at least UNIT size. */
18444 if (flags & SECTION_CODE)
18445 align = MIN_UNITS_PER_WORD;
18447 /* Increase alignment of large objects if not already stricter. */
18448 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
18449 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
18450 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
18452 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
18455 /* Output at beginning of assembler file.
18457 Initialize the section names for the RS/6000 at this point.
18459 Specify filename, including full path, to assembler.
18461 We want to go into the TOC section so at least one .toc will be emitted.
18462 Also, in order to output proper .bs/.es pairs, we need at least one static
18463 [RW] section emitted.
18465 Finally, declare mcount when profiling to make the assembler happy. */
18468 rs6000_xcoff_file_start (void)
18470 rs6000_gen_section_name (&xcoff_bss_section_name,
18471 main_input_filename, ".bss_");
18472 rs6000_gen_section_name (&xcoff_private_data_section_name,
18473 main_input_filename, ".rw_");
18474 rs6000_gen_section_name (&xcoff_read_only_section_name,
18475 main_input_filename, ".ro_");
18477 fputs ("\t.file\t", asm_out_file);
18478 output_quoted_string (asm_out_file, main_input_filename);
18479 fputc ('\n', asm_out_file);
18480 if (write_symbols != NO_DEBUG)
18481 switch_to_section (private_data_section);
18482 switch_to_section (text_section);
18484 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
18485 rs6000_file_start ();
18488 /* Output at end of assembler file.
18489 On the RS/6000, referencing data should automatically pull in text. */
18492 rs6000_xcoff_file_end (void)
18494 switch_to_section (text_section);
18495 fputs ("_section_.text:\n", asm_out_file);
18496 switch_to_section (data_section);
18497 fputs (TARGET_32BIT
18498 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
18501 #endif /* TARGET_XCOFF */
18503 /* Compute a (partial) cost for rtx X. Return true if the complete
18504 cost has been computed, and false if subexpressions should be
18505 scanned. In either case, *TOTAL contains the cost result. */
18508 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
18510 enum machine_mode mode = GET_MODE (x);
18514 /* On the RS/6000, if it is valid in the insn, it is free. */
18516 if (((outer_code == SET
18517 || outer_code == PLUS
18518 || outer_code == MINUS)
18519 && (satisfies_constraint_I (x)
18520 || satisfies_constraint_L (x)))
18521 || (outer_code == AND
18522 && (satisfies_constraint_K (x)
18524 ? satisfies_constraint_L (x)
18525 : satisfies_constraint_J (x))
18526 || mask_operand (x, mode)
18528 && mask64_operand (x, DImode))))
18529 || ((outer_code == IOR || outer_code == XOR)
18530 && (satisfies_constraint_K (x)
18532 ? satisfies_constraint_L (x)
18533 : satisfies_constraint_J (x))))
18534 || outer_code == ASHIFT
18535 || outer_code == ASHIFTRT
18536 || outer_code == LSHIFTRT
18537 || outer_code == ROTATE
18538 || outer_code == ROTATERT
18539 || outer_code == ZERO_EXTRACT
18540 || (outer_code == MULT
18541 && satisfies_constraint_I (x))
18542 || ((outer_code == DIV || outer_code == UDIV
18543 || outer_code == MOD || outer_code == UMOD)
18544 && exact_log2 (INTVAL (x)) >= 0)
18545 || (outer_code == COMPARE
18546 && (satisfies_constraint_I (x)
18547 || satisfies_constraint_K (x)))
18548 || (outer_code == EQ
18549 && (satisfies_constraint_I (x)
18550 || satisfies_constraint_K (x)
18552 ? satisfies_constraint_L (x)
18553 : satisfies_constraint_J (x))))
18554 || (outer_code == GTU
18555 && satisfies_constraint_I (x))
18556 || (outer_code == LTU
18557 && satisfies_constraint_P (x)))
18562 else if ((outer_code == PLUS
18563 && reg_or_add_cint_operand (x, VOIDmode))
18564 || (outer_code == MINUS
18565 && reg_or_sub_cint_operand (x, VOIDmode))
18566 || ((outer_code == SET
18567 || outer_code == IOR
18568 || outer_code == XOR)
18570 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
18572 *total = COSTS_N_INSNS (1);
18579 && ((outer_code == AND
18580 && (satisfies_constraint_K (x)
18581 || satisfies_constraint_L (x)
18582 || mask_operand (x, DImode)
18583 || mask64_operand (x, DImode)))
18584 || ((outer_code == IOR || outer_code == XOR)
18585 && CONST_DOUBLE_HIGH (x) == 0
18586 && (CONST_DOUBLE_LOW (x)
18587 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
18592 else if (mode == DImode
18593 && (outer_code == SET
18594 || outer_code == IOR
18595 || outer_code == XOR)
18596 && CONST_DOUBLE_HIGH (x) == 0)
18598 *total = COSTS_N_INSNS (1);
18607 /* When optimizing for size, MEM should be slightly more expensive
18608 than generating address, e.g., (plus (reg) (const)).
18609 L1 cache latency is about two instructions. */
18610 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18618 if (mode == DFmode)
18620 if (GET_CODE (XEXP (x, 0)) == MULT)
18622 /* FNMA accounted in outer NEG. */
18623 if (outer_code == NEG)
18624 *total = rs6000_cost->dmul - rs6000_cost->fp;
18626 *total = rs6000_cost->dmul;
18629 *total = rs6000_cost->fp;
18631 else if (mode == SFmode)
18633 /* FNMA accounted in outer NEG. */
18634 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18637 *total = rs6000_cost->fp;
18640 *total = COSTS_N_INSNS (1);
18644 if (mode == DFmode)
18646 if (GET_CODE (XEXP (x, 0)) == MULT)
18648 /* FNMA accounted in outer NEG. */
18649 if (outer_code == NEG)
18652 *total = rs6000_cost->dmul;
18655 *total = rs6000_cost->fp;
18657 else if (mode == SFmode)
18659 /* FNMA accounted in outer NEG. */
18660 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18663 *total = rs6000_cost->fp;
18666 *total = COSTS_N_INSNS (1);
18670 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18671 && satisfies_constraint_I (XEXP (x, 1)))
18673 if (INTVAL (XEXP (x, 1)) >= -256
18674 && INTVAL (XEXP (x, 1)) <= 255)
18675 *total = rs6000_cost->mulsi_const9;
18677 *total = rs6000_cost->mulsi_const;
18679 /* FMA accounted in outer PLUS/MINUS. */
18680 else if ((mode == DFmode || mode == SFmode)
18681 && (outer_code == PLUS || outer_code == MINUS))
18683 else if (mode == DFmode)
18684 *total = rs6000_cost->dmul;
18685 else if (mode == SFmode)
18686 *total = rs6000_cost->fp;
18687 else if (mode == DImode)
18688 *total = rs6000_cost->muldi;
18690 *total = rs6000_cost->mulsi;
18695 if (FLOAT_MODE_P (mode))
18697 *total = mode == DFmode ? rs6000_cost->ddiv
18698 : rs6000_cost->sdiv;
18705 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18706 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
18708 if (code == DIV || code == MOD)
18710 *total = COSTS_N_INSNS (2);
18713 *total = COSTS_N_INSNS (1);
18717 if (GET_MODE (XEXP (x, 1)) == DImode)
18718 *total = rs6000_cost->divdi;
18720 *total = rs6000_cost->divsi;
18722 /* Add in shift and subtract for MOD. */
18723 if (code == MOD || code == UMOD)
18724 *total += COSTS_N_INSNS (2);
18728 *total = COSTS_N_INSNS (4);
18732 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
18743 *total = COSTS_N_INSNS (1);
18751 /* Handle mul_highpart. */
18752 if (outer_code == TRUNCATE
18753 && GET_CODE (XEXP (x, 0)) == MULT)
18755 if (mode == DImode)
18756 *total = rs6000_cost->muldi;
18758 *total = rs6000_cost->mulsi;
18761 else if (outer_code == AND)
18764 *total = COSTS_N_INSNS (1);
18769 if (GET_CODE (XEXP (x, 0)) == MEM)
18772 *total = COSTS_N_INSNS (1);
18778 if (!FLOAT_MODE_P (mode))
18780 *total = COSTS_N_INSNS (1);
18786 case UNSIGNED_FLOAT:
18789 case FLOAT_TRUNCATE:
18790 *total = rs6000_cost->fp;
18794 if (mode == DFmode)
18797 *total = rs6000_cost->fp;
18801 switch (XINT (x, 1))
18804 *total = rs6000_cost->fp;
18816 *total = COSTS_N_INSNS (1);
18819 else if (FLOAT_MODE_P (mode)
18820 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
18822 *total = rs6000_cost->fp;
18830 /* Carry bit requires mode == Pmode.
18831 NEG or PLUS already counted so only add one. */
18833 && (outer_code == NEG || outer_code == PLUS))
18835 *total = COSTS_N_INSNS (1);
18838 if (outer_code == SET)
18840 if (XEXP (x, 1) == const0_rtx)
18842 *total = COSTS_N_INSNS (2);
18845 else if (mode == Pmode)
18847 *total = COSTS_N_INSNS (3);
18856 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
18858 *total = COSTS_N_INSNS (2);
18862 if (outer_code == COMPARE)
18876 /* A C expression returning the cost of moving data from a register of class
18877 CLASS1 to one of CLASS2. */
18880 rs6000_register_move_cost (enum machine_mode mode,
18881 enum reg_class from, enum reg_class to)
18883 /* Moves from/to GENERAL_REGS. */
18884 if (reg_classes_intersect_p (to, GENERAL_REGS)
18885 || reg_classes_intersect_p (from, GENERAL_REGS))
18887 if (! reg_classes_intersect_p (to, GENERAL_REGS))
18890 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
18891 return (rs6000_memory_move_cost (mode, from, 0)
18892 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
18894 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18896 else if (from == CR_REGS)
18900 /* A move will cost one instruction per GPR moved. */
18901 return 2 * hard_regno_nregs[0][mode];
18904 /* Moving between two similar registers is just one instruction. */
18905 else if (reg_classes_intersect_p (to, from))
18906 return mode == TFmode ? 4 : 2;
18908 /* Everything else has to go through GENERAL_REGS. */
18910 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
18911 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
18914 /* A C expressions returning the cost of moving data of MODE from a register to
18918 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
18919 int in ATTRIBUTE_UNUSED)
18921 if (reg_classes_intersect_p (class, GENERAL_REGS))
18922 return 4 * hard_regno_nregs[0][mode];
18923 else if (reg_classes_intersect_p (class, FLOAT_REGS))
18924 return 4 * hard_regno_nregs[32][mode];
18925 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
18926 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
18928 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
18931 /* Newton-Raphson approximation of single-precision floating point divide n/d.
18932 Assumes no trapping math and finite arguments. */
18935 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
18937 rtx x0, e0, e1, y1, u0, v0, one;
18939 x0 = gen_reg_rtx (SFmode);
18940 e0 = gen_reg_rtx (SFmode);
18941 e1 = gen_reg_rtx (SFmode);
18942 y1 = gen_reg_rtx (SFmode);
18943 u0 = gen_reg_rtx (SFmode);
18944 v0 = gen_reg_rtx (SFmode);
18945 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
18947 /* x0 = 1./d estimate */
18948 emit_insn (gen_rtx_SET (VOIDmode, x0,
18949 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
18951 /* e0 = 1. - d * x0 */
18952 emit_insn (gen_rtx_SET (VOIDmode, e0,
18953 gen_rtx_MINUS (SFmode, one,
18954 gen_rtx_MULT (SFmode, d, x0))));
18955 /* e1 = e0 + e0 * e0 */
18956 emit_insn (gen_rtx_SET (VOIDmode, e1,
18957 gen_rtx_PLUS (SFmode,
18958 gen_rtx_MULT (SFmode, e0, e0), e0)));
18959 /* y1 = x0 + e1 * x0 */
18960 emit_insn (gen_rtx_SET (VOIDmode, y1,
18961 gen_rtx_PLUS (SFmode,
18962 gen_rtx_MULT (SFmode, e1, x0), x0)));
18964 emit_insn (gen_rtx_SET (VOIDmode, u0,
18965 gen_rtx_MULT (SFmode, n, y1)));
18966 /* v0 = n - d * u0 */
18967 emit_insn (gen_rtx_SET (VOIDmode, v0,
18968 gen_rtx_MINUS (SFmode, n,
18969 gen_rtx_MULT (SFmode, d, u0))));
18970 /* res = u0 + v0 * y1 */
18971 emit_insn (gen_rtx_SET (VOIDmode, res,
18972 gen_rtx_PLUS (SFmode,
18973 gen_rtx_MULT (SFmode, v0, y1), u0)));
18976 /* Newton-Raphson approximation of double-precision floating point divide n/d.
18977 Assumes no trapping math and finite arguments. */
18980 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
18982 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
18984 x0 = gen_reg_rtx (DFmode);
18985 e0 = gen_reg_rtx (DFmode);
18986 e1 = gen_reg_rtx (DFmode);
18987 e2 = gen_reg_rtx (DFmode);
18988 y1 = gen_reg_rtx (DFmode);
18989 y2 = gen_reg_rtx (DFmode);
18990 y3 = gen_reg_rtx (DFmode);
18991 u0 = gen_reg_rtx (DFmode);
18992 v0 = gen_reg_rtx (DFmode);
18993 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
18995 /* x0 = 1./d estimate */
18996 emit_insn (gen_rtx_SET (VOIDmode, x0,
18997 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
18999 /* e0 = 1. - d * x0 */
19000 emit_insn (gen_rtx_SET (VOIDmode, e0,
19001 gen_rtx_MINUS (DFmode, one,
19002 gen_rtx_MULT (SFmode, d, x0))));
19003 /* y1 = x0 + e0 * x0 */
19004 emit_insn (gen_rtx_SET (VOIDmode, y1,
19005 gen_rtx_PLUS (DFmode,
19006 gen_rtx_MULT (DFmode, e0, x0), x0)));
19008 emit_insn (gen_rtx_SET (VOIDmode, e1,
19009 gen_rtx_MULT (DFmode, e0, e0)));
19010 /* y2 = y1 + e1 * y1 */
19011 emit_insn (gen_rtx_SET (VOIDmode, y2,
19012 gen_rtx_PLUS (DFmode,
19013 gen_rtx_MULT (DFmode, e1, y1), y1)));
19015 emit_insn (gen_rtx_SET (VOIDmode, e2,
19016 gen_rtx_MULT (DFmode, e1, e1)));
19017 /* y3 = y2 + e2 * y2 */
19018 emit_insn (gen_rtx_SET (VOIDmode, y3,
19019 gen_rtx_PLUS (DFmode,
19020 gen_rtx_MULT (DFmode, e2, y2), y2)));
19022 emit_insn (gen_rtx_SET (VOIDmode, u0,
19023 gen_rtx_MULT (DFmode, n, y3)));
19024 /* v0 = n - d * u0 */
19025 emit_insn (gen_rtx_SET (VOIDmode, v0,
19026 gen_rtx_MINUS (DFmode, n,
19027 gen_rtx_MULT (DFmode, d, u0))));
19028 /* res = u0 + v0 * y3 */
19029 emit_insn (gen_rtx_SET (VOIDmode, res,
19030 gen_rtx_PLUS (DFmode,
19031 gen_rtx_MULT (DFmode, v0, y3), u0)));
19034 /* Return an RTX representing where to find the function value of a
19035 function returning MODE. */
19037 rs6000_complex_function_value (enum machine_mode mode)
19039 unsigned int regno;
19041 enum machine_mode inner = GET_MODE_INNER (mode);
19042 unsigned int inner_bytes = GET_MODE_SIZE (inner);
19044 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
19045 regno = FP_ARG_RETURN;
19048 regno = GP_ARG_RETURN;
19050 /* 32-bit is OK since it'll go in r3/r4. */
19051 if (TARGET_32BIT && inner_bytes >= 4)
19052 return gen_rtx_REG (mode, regno);
19055 if (inner_bytes >= 8)
19056 return gen_rtx_REG (mode, regno);
19058 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
19060 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
19061 GEN_INT (inner_bytes));
19062 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
19065 /* Define how to find the value returned by a function.
19066 VALTYPE is the data type of the value (as a tree).
19067 If the precise function being called is known, FUNC is its FUNCTION_DECL;
19068 otherwise, FUNC is 0.
19070 On the SPE, both FPs and vectors are returned in r3.
19072 On RS/6000 an integer value is in r3 and a floating-point value is in
19073 fp1, unless -msoft-float. */
19076 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
19078 enum machine_mode mode;
19079 unsigned int regno;
19081 /* Special handling for structs in darwin64. */
19082 if (rs6000_darwin64_abi
19083 && TYPE_MODE (valtype) == BLKmode
19084 && TREE_CODE (valtype) == RECORD_TYPE
19085 && int_size_in_bytes (valtype) > 0)
19087 CUMULATIVE_ARGS valcum;
19091 valcum.fregno = FP_ARG_MIN_REG;
19092 valcum.vregno = ALTIVEC_ARG_MIN_REG;
19093 /* Do a trial code generation as if this were going to be passed as
19094 an argument; if any part goes in memory, we return NULL. */
19095 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
19098 /* Otherwise fall through to standard ABI rules. */
19101 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
19103 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
19104 return gen_rtx_PARALLEL (DImode,
19106 gen_rtx_EXPR_LIST (VOIDmode,
19107 gen_rtx_REG (SImode, GP_ARG_RETURN),
19109 gen_rtx_EXPR_LIST (VOIDmode,
19110 gen_rtx_REG (SImode,
19111 GP_ARG_RETURN + 1),
19114 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
19116 return gen_rtx_PARALLEL (DCmode,
19118 gen_rtx_EXPR_LIST (VOIDmode,
19119 gen_rtx_REG (SImode, GP_ARG_RETURN),
19121 gen_rtx_EXPR_LIST (VOIDmode,
19122 gen_rtx_REG (SImode,
19123 GP_ARG_RETURN + 1),
19125 gen_rtx_EXPR_LIST (VOIDmode,
19126 gen_rtx_REG (SImode,
19127 GP_ARG_RETURN + 2),
19129 gen_rtx_EXPR_LIST (VOIDmode,
19130 gen_rtx_REG (SImode,
19131 GP_ARG_RETURN + 3),
19135 if ((INTEGRAL_TYPE_P (valtype)
19136 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
19137 || POINTER_TYPE_P (valtype))
19138 mode = TARGET_32BIT ? SImode : DImode;
19140 mode = TYPE_MODE (valtype);
19142 if (DECIMAL_FLOAT_MODE_P (mode))
19143 regno = GP_ARG_RETURN;
19144 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
19145 regno = FP_ARG_RETURN;
19146 else if (TREE_CODE (valtype) == COMPLEX_TYPE
19147 && targetm.calls.split_complex_arg)
19148 return rs6000_complex_function_value (mode);
19149 else if (TREE_CODE (valtype) == VECTOR_TYPE
19150 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
19151 && ALTIVEC_VECTOR_MODE (mode))
19152 regno = ALTIVEC_ARG_RETURN;
19153 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
19154 && (mode == DFmode || mode == DCmode))
19155 return spe_build_register_parallel (mode, GP_ARG_RETURN);
19157 regno = GP_ARG_RETURN;
19159 return gen_rtx_REG (mode, regno);
19162 /* Define how to find the value returned by a library function
19163 assuming the value has mode MODE. */
19165 rs6000_libcall_value (enum machine_mode mode)
19167 unsigned int regno;
19169 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
19171 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
19172 return gen_rtx_PARALLEL (DImode,
19174 gen_rtx_EXPR_LIST (VOIDmode,
19175 gen_rtx_REG (SImode, GP_ARG_RETURN),
19177 gen_rtx_EXPR_LIST (VOIDmode,
19178 gen_rtx_REG (SImode,
19179 GP_ARG_RETURN + 1),
19183 if (DECIMAL_FLOAT_MODE_P (mode))
19184 regno = GP_ARG_RETURN;
19185 else if (SCALAR_FLOAT_MODE_P (mode)
19186 && TARGET_HARD_FLOAT && TARGET_FPRS)
19187 regno = FP_ARG_RETURN;
19188 else if (ALTIVEC_VECTOR_MODE (mode)
19189 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
19190 regno = ALTIVEC_ARG_RETURN;
19191 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
19192 return rs6000_complex_function_value (mode);
19193 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
19194 && (mode == DFmode || mode == DCmode))
19195 return spe_build_register_parallel (mode, GP_ARG_RETURN);
19197 regno = GP_ARG_RETURN;
19199 return gen_rtx_REG (mode, regno);
19202 /* Define the offset between two registers, FROM to be eliminated and its
19203 replacement TO, at the start of a routine. */
19205 rs6000_initial_elimination_offset (int from, int to)
19207 rs6000_stack_t *info = rs6000_stack_info ();
19208 HOST_WIDE_INT offset;
19210 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19211 offset = info->push_p ? 0 : -info->total_size;
19212 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19214 offset = info->push_p ? 0 : -info->total_size;
19215 if (FRAME_GROWS_DOWNWARD)
19216 offset += info->fixed_size + info->vars_size + info->parm_size;
19218 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
19219 offset = FRAME_GROWS_DOWNWARD
19220 ? info->fixed_size + info->vars_size + info->parm_size
19222 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
19223 offset = info->total_size;
19224 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
19225 offset = info->push_p ? info->total_size : 0;
19226 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
19229 gcc_unreachable ();
19234 /* Return true if TYPE is a SPE or AltiVec opaque type. */
19237 rs6000_is_opaque_type (tree type)
19239 return (type == opaque_V2SI_type_node
19240 || type == opaque_V2SF_type_node
19241 || type == opaque_p_V2SI_type_node
19242 || type == opaque_V4SI_type_node);
19246 rs6000_dwarf_register_span (rtx reg)
19251 && (SPE_VECTOR_MODE (GET_MODE (reg))
19252 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
19257 regno = REGNO (reg);
19259 /* The duality of the SPE register size wreaks all kinds of havoc.
19260 This is a way of distinguishing r0 in 32-bits from r0 in
19263 gen_rtx_PARALLEL (VOIDmode,
19266 gen_rtx_REG (SImode, regno + 1200),
19267 gen_rtx_REG (SImode, regno))
19269 gen_rtx_REG (SImode, regno),
19270 gen_rtx_REG (SImode, regno + 1200)));
19273 /* Map internal gcc register numbers to DWARF2 register numbers. */
19276 rs6000_dbx_register_number (unsigned int regno)
19278 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
19280 if (regno == MQ_REGNO)
19282 if (regno == LINK_REGISTER_REGNUM)
19284 if (regno == COUNT_REGISTER_REGNUM)
19286 if (CR_REGNO_P (regno))
19287 return regno - CR0_REGNO + 86;
19288 if (regno == XER_REGNO)
19290 if (ALTIVEC_REGNO_P (regno))
19291 return regno - FIRST_ALTIVEC_REGNO + 1124;
19292 if (regno == VRSAVE_REGNO)
19294 if (regno == VSCR_REGNO)
19296 if (regno == SPE_ACC_REGNO)
19298 if (regno == SPEFSCR_REGNO)
19300 /* SPE high reg number. We get these values of regno from
19301 rs6000_dwarf_register_span. */
19302 gcc_assert (regno >= 1200 && regno < 1232);
19306 /* target hook eh_return_filter_mode */
19307 static enum machine_mode
19308 rs6000_eh_return_filter_mode (void)
19310 return TARGET_32BIT ? SImode : word_mode;
19313 /* Target hook for scalar_mode_supported_p. */
19315 rs6000_scalar_mode_supported_p (enum machine_mode mode)
19317 if (DECIMAL_FLOAT_MODE_P (mode))
19320 return default_scalar_mode_supported_p (mode);
19323 /* Target hook for vector_mode_supported_p. */
19325 rs6000_vector_mode_supported_p (enum machine_mode mode)
19328 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
19331 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
19338 /* Target hook for invalid_arg_for_unprototyped_fn. */
19339 static const char *
19340 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
19342 return (!rs6000_darwin64_abi
19344 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
19345 && (funcdecl == NULL_TREE
19346 || (TREE_CODE (funcdecl) == FUNCTION_DECL
19347 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
19348 ? N_("AltiVec argument passed to unprototyped function")
19352 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
19353 setup by using __stack_chk_fail_local hidden function instead of
19354 calling __stack_chk_fail directly. Otherwise it is better to call
19355 __stack_chk_fail directly. */
19358 rs6000_stack_protect_fail (void)
19360 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
19361 ? default_hidden_stack_protect_fail ()
19362 : default_external_stack_protect_fail ();
19365 #include "gt-rs6000.h"